From 0f011679c07bf0cba1b78b022c2a2b4db1c943c9 Mon Sep 17 00:00:00 2001 From: NCTU CS ISIP Date: Fri, 6 Mar 2020 17:42:52 +0800 Subject: [PATCH 01/70] NCTU_CS_ISIP Signed-off-by: NCTU CS ISIP --- openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c index d3e851f07b..e11d97edf2 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c @@ -1,4 +1,4 @@ -/* +/* * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. From fb30fc6aa54755ebbe09f76b68e0d3e980b3371e Mon Sep 17 00:00:00 2001 From: NCTU CS ISIP Date: Fri, 6 Mar 2020 18:36:33 +0800 Subject: [PATCH 02/70] GPU branch Signed-off-by: NCTU CS ISIP --- openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c index e11d97edf2..442864bb06 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c @@ -18,7 +18,7 @@ * For more information about the OpenAirInterface (OAI) Software Alliance: * contact@openairinterface.org */ - + /*!\file nrLDPC_decoder.c * \brief Defines the LDPC decoder * \author Sebastian Wagner (TCL Communications) Email: From 1f6dbb20fe18972ca05c34ba541cb9ffbac5e508 Mon Sep 17 00:00:00 2001 From: NCTU CS ISIP Date: Fri, 6 Mar 2020 19:12:31 +0800 Subject: [PATCH 03/70] LDPC implementation on GPU Signed-off-by: NCTU CS ISIP --- .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i3.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i4.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h | 51 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i0.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i5.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h | 47 +++ .../CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h | 47 +++ openair1/PHY/CODING/GPU_LDPC/README.md | 17 + .../CODING/GPU_LDPC/intuitive_ldpc/Makefile | 36 ++ .../CODING/GPU_LDPC/intuitive_ldpc/check.sh | 32 ++ .../CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu | 323 ++++++++++++++++++ .../CODING/GPU_LDPC/intuitive_ldpc/util.cu | 37 ++ .../PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h | 47 +++ .../CODING/GPU_LDPC/optimized_ldpc/Makefile | 29 ++ .../optimized_ldpc/bg1_i1_index_array.h | 9 + .../CODING/GPU_LDPC/optimized_ldpc/check.sh | 10 + .../CODING/GPU_LDPC/optimized_ldpc/gen_idx.c | 198 +++++++++++ .../CODING/GPU_LDPC/optimized_ldpc/ldpc.cu | 297 ++++++++++++++++ .../GPU_LDPC/optimized_ldpc/test/test.cu | 228 +++++++++++++ .../GPU_LDPC/optimized_ldpc/test/test.h | 7 + .../PHY/CODING/GPU_LDPC/test_input/8448/1.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/10.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/100.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/11.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/12.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/13.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/14.txt | 6 + .../CODING/GPU_LDPC/test_input/8448/15.txt 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openair1/PHY/CODING/GPU_LDPC/test_input/8448/76.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/77.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/78.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/79.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/8.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/80.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/81.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/82.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/83.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/84.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/85.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/86.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/87.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/88.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/89.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/9.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/90.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/91.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/92.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/93.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/94.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/95.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/96.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/97.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/98.txt create mode 100644 openair1/PHY/CODING/GPU_LDPC/test_input/8448/99.txt diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h new file mode 100644 index 0000000000..01731910b2 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I0_H_ +#define _ISIP_LDPC_BG1_I0_H_ +static int BG1_I0[46*68] = { + 251, 70, 227, 160, 0, 101, 11, 0, 0, 60, 230, 111, 192, 10, 0, 196, 24, 0, 191, 36, 240, 32, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 0, 240, 118, 125, 72, 0, 223, 105, 174, 0, 221, 103, 0, 110, 133, 143, 156, 0, 256, 0, 29, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 107, 112, 186, 0, 64, 118, 94, 230, 178, 96, 40, 0, 0, 143, 226, 226, 0, 246, 206, 252, 118, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 122, 90, 0, 85, 21, 0, 151, 132, 244, 0, 137, 87, 247, 220, 212, 0, 241, 77, 245, 0, 145, 13, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 158, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 206, 237, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 232, 0, 0, 0, 29, 0, 0, 0, 0, 124, 116, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 184, 0, 0, 0, 0, 0, 23, 0, 0, 0, 29, 68, 0, 245, 0, 0, 0, 12, 158, 0, 212, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 221, 45, 0, 0, 160, 0, 0, 32, 168, 0, 0, 0, 0, 0, 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 113, 5, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 212, 0, 0, 0, 103, 0, 0, 165, 0, 110, 242, 0, 91, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 104, 183, 0, 0, 0, 0, 0, 0, 0, 0, 110, 22, 0, 143, 0, 0, 0, 15, 62, 0, 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 99, 150, 0, 168, 0, 0, 161, 50, 0, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 78, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84, 0, 0, 0, 183, 0, 0, 0, 0, 79, 253, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 161, 43, 0, 0, 0, 0, 0, 0, 0, 0, 22, 33, 0, 235, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 178, 0, 0, 249, 0, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 186, 0, 0, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 207, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 56, 0, 0, 207, 128, 17, 0, 0, 0, 230, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 41, 97, 0, 0, 0, 0, 0, 0, 0, 0, 66, 0, 0, 64, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 65, 0, 50, 0, 0, 0, 0, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 52, 0, 155, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 165, 0, 60, 2, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 234, 9, 0, 0, 0, 0, 156, 148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 61, 74, 0, 0, 0, 0, 0, 73, 128, 0, 225, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 152, 0, 0, 187, 0, 0, 0, 0, 0, 218, 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 161, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 250, 0, 0, 0, 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 110, 0, 0, 0, 132, 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 143, 189, 0, 0, 0, 159, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 157, 148, 0, 0, 0, 0, 0, 0, 0, 171, 0, 0, 0, 0, 0, 0, 0, 153, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 113, 0, 0, 87, 237, 0, 0, 0, 0, 0, 0, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 24, 0, 0, 0, 0, 137, 117, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 196, 0, 244, 0, 216, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 26, 0, 0, 0, 0, 105, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 129, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 237, 0, 0, 0, 85, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 74, 0, 0, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 96, 0, 0, 0, 0, 0, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 173, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 222, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 113, 0, 200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 3, 188, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 212, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 128, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 165, 0, 160, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 162, 0, 0, 0, 0, 198, 0, 0, 0, 0, 0, 208, 0, 0, 0, 0, 0, 0, 0, 0, 0, 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 52, 0, 0, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 199, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 221, 0, 0, 0, 0, 0, 0, 0, 0, 0, 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 168, 0, 0, 0, 0, 0, 0, 0, 0, 152, 158, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 174, 0, 140, 0, 0, 0, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 158, 0, 0, 0, 0, 0, 0, 0, 138, 0, 0, 0, 0, 0, 0, 0, 0, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 168, 0, 174, 0, 0, 0, 0, 0, 140, 0, 0, 0, 0, 0, 0, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 150, 0, 0, 0, 158, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 138, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 164, 0, 174, 0, 0, 0, 0, 0, 0, 140, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 140, 0, 0, 0, 0, 0, 0, 158, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 150, 0, 0, 0, 0, 152, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h new file mode 100644 index 0000000000..e7ff7f339b --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I1_H_ +#define _ISIP_LDPC_BG1_I1_H_ +static int BG1_I1[46*68] = { + 308, 20, 51, 370, 0, 182, 217, 0, 0, 318, 289, 110, 18, 358, 0, 216, 107, 0, 243, 181, 331, 347, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 77, 0, 77, 74, 289, 145, 0, 332, 332, 179, 0, 296, 343, 0, 218, 100, 355, 115, 0, 332, 0, 113, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 206, 251, 329, 0, 333, 257, 162, 268, 161, 64, 130, 0, 0, 201, 89, 54, 0, 132, 241, 206, 14, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 277, 88, 0, 1, 276, 0, 200, 154, 57, 0, 133, 306, 232, 342, 213, 0, 305, 301, 272, 0, 40, 358, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 333, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 196, 15, 0, 116, 0, 0, 0, 0, 0, 0, 0, 0, 167, 0, 0, 0, 242, 0, 0, 0, 0, 52, 158, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 279, 0, 0, 0, 0, 0, 258, 0, 0, 0, 2, 352, 0, 93, 0, 0, 0, 254, 19, 0, 226, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 10, 63, 0, 0, 317, 0, 0, 334, 291, 0, 0, 0, 0, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 308, 180, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 40, 0, 0, 225, 0, 369, 68, 0, 171, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 367, 233, 0, 0, 0, 0, 0, 0, 0, 0, 322, 134, 0, 58, 0, 0, 0, 304, 64, 0, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 102, 340, 0, 275, 0, 0, 112, 384, 0, 0, 0, 0, 0, 355, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 49, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 48, 0, 0, 0, 0, 189, 335, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 78, 187, 0, 0, 0, 0, 0, 0, 0, 0, 175, 233, 0, 51, 0, 0, 0, 0, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 314, 0, 0, 178, 0, 0, 0, 267, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 116, 0, 0, 371, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 143, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 249, 0, 0, 138, 90, 348, 0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 242, 3, 0, 0, 0, 0, 0, 0, 0, 0, 211, 0, 0, 319, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 270, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 14, 0, 339, 0, 0, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 0, 0, 0, 0, 290, 0, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 261, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 304, 0, 82, 359, 0, 0, 0, 376, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 164, 281, 0, 0, 0, 0, 133, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 146, 214, 0, 0, 0, 0, 0, 345, 243, 0, 198, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 188, 0, 0, 207, 0, 0, 0, 0, 0, 265, 0, 342, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 206, 0, 0, 0, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 329, 0, 0, 0, 214, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 234, 0, 0, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 25, 90, 0, 0, 0, 0, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 299, 0, 0, 159, 236, 0, 0, 0, 0, 0, 0, 340, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 235, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 73, 0, 0, 0, 0, 18, 384, 0, 0, 0, 0, 0, 0, 313, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 230, 0, 0, 261, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 101, 0, 0, 0, 0, 0, 216, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 259, 0, 0, 257, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 202, 0, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 288, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 324, 9, 0, 0, 0, 0, 0, 0, 0, 0, 362, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 231, 0, 0, 0, 0, 0, 0, 149, 0, 0, 0, 0, 0, 0, 0, 203, 0, 313, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 321, 0, 0, 0, 0, 336, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 267, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 314, 298, 0, 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 270, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 186, 0, 0, 0, 0, 0, 0, 0, 0, 178, 290, 0, 215, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 259, 0, 94, 0, 0, 0, 347, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 298, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 176, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 313, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 53, 0, 315, 0, 0, 0, 0, 0, 140, 0, 0, 0, 0, 0, 0, 0, 0, 289, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 114, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 219, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 133, 0, 115, 0, 0, 0, 0, 0, 0, 169, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 81, 0, 0, 0, 0, 0, 0, 79, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 275, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 136, 0, 0, 0, 0, 150, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h new file mode 100644 index 0000000000..9b2875f765 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I2_H_ +#define _ISIP_LDPC_BG1_I2_H_ +static int BG1_I2[46*68] = { + 74, 16, 104, 50, 0, 241, 40, 0, 0, 16, 163, 216, 165, 134, 0, 299, 111, 0, 114, 17, 190, 33, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 304, 0, 295, 28, 262, 162, 0, 134, 5, 81, 0, 130, 301, 0, 77, 267, 73, 84, 0, 261, 0, 302, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 69, 8, 81, 0, 281, 39, 228, 203, 201, 72, 107, 0, 0, 296, 284, 302, 0, 185, 247, 231, 277, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 221, 209, 0, 31, 198, 0, 62, 176, 80, 0, 282, 304, 254, 165, 54, 0, 45, 29, 78, 0, 320, 69, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 234, 206, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 84, 293, 0, 51, 0, 0, 0, 0, 0, 0, 0, 0, 319, 0, 0, 0, 202, 0, 0, 0, 0, 268, 280, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 290, 0, 0, 0, 0, 0, 22, 0, 0, 0, 294, 14, 0, 233, 0, 0, 0, 303, 139, 0, 236, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 13, 89, 0, 0, 208, 0, 0, 51, 26, 0, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 296, 134, 0, 131, 0, 0, 0, 0, 0, 0, 0, 0, 232, 0, 0, 0, 297, 0, 0, 111, 0, 270, 246, 0, 155, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 190, 245, 0, 0, 0, 0, 0, 0, 0, 0, 37, 287, 0, 152, 0, 0, 0, 268, 136, 0, 210, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 81, 0, 212, 0, 0, 76, 162, 0, 0, 0, 0, 0, 312, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 17, 148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 291, 0, 0, 0, 290, 0, 0, 0, 0, 178, 44, 281, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 230, 236, 0, 0, 0, 0, 0, 0, 0, 0, 170, 49, 0, 106, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 40, 0, 0, 303, 0, 0, 0, 304, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 161, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 300, 0, 0, 55, 62, 180, 0, 0, 0, 259, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 230, 291, 0, 0, 0, 0, 0, 0, 0, 0, 61, 0, 0, 131, 0, 0, 0, 0, 185, 0, 0, 0, 0, 0, 0, 52, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 70, 0, 141, 0, 0, 0, 0, 0, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 116, 0, 301, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 258, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 148, 0, 129, 52, 0, 0, 0, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 261, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 295, 292, 0, 0, 0, 0, 142, 296, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 65, 182, 0, 0, 0, 0, 0, 102, 271, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 302, 0, 0, 163, 0, 0, 0, 0, 0, 41, 0, 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 80, 0, 0, 0, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 133, 0, 0, 0, 284, 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 56, 0, 0, 0, 317, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 250, 51, 0, 0, 0, 0, 0, 0, 0, 134, 0, 0, 0, 0, 0, 0, 0, 106, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 290, 0, 0, 281, 111, 0, 0, 0, 0, 0, 0, 188, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 282, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 173, 0, 0, 0, 0, 296, 97, 0, 0, 0, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 271, 0, 111, 0, 319, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 211, 0, 0, 0, 0, 30, 0, 305, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 12, 0, 0, 0, 294, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 51, 0, 235, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 309, 0, 0, 0, 118, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, 0, 0, 106, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 223, 0, 0, 0, 0, 0, 309, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 0, 0, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 272, 0, 0, 0, 0, 0, 0, 0, 0, 0, 218, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 171, 21, 0, 0, 0, 0, 0, 0, 0, 0, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 188, 0, 0, 0, 0, 0, 0, 297, 0, 0, 0, 0, 0, 0, 0, 6, 0, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 208, 0, 0, 0, 0, 159, 0, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 286, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 180, 179, 0, 0, 161, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 299, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 152, 0, 0, 0, 0, 0, 0, 0, 0, 180, 65, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 103, 0, 78, 0, 0, 0, 193, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 209, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 33, 0, 0, 0, 0, 0, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 198, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 155, 0, 48, 0, 0, 0, 0, 0, 125, 0, 0, 0, 0, 0, 0, 0, 0, 208, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 227, 0, 0, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 70, 0, 177, 0, 0, 0, 0, 0, 0, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 235, 0, 0, 0, 0, 0, 0, 228, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 261, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 102, 0, 0, 0, 0, 229, 0, 0, 0, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i3.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i3.h new file mode 100644 index 0000000000..0563f61255 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i3.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I3_H_ +#define _ISIP_LDPC_BG1_I3_H_ +static int BG1_I3[46*68] = { + 224, 17, 95, 92, 0, 75, 11, 0, 0, 1, 206, 217, 22, 216, 0, 15, 71, 0, 142, 199, 105, 82, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 142, 0, 46, 152, 47, 120, 0, 158, 134, 88, 0, 207, 94, 0, 80, 10, 119, 195, 0, 32, 0, 188, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 208, 204, 32, 0, 177, 181, 187, 96, 154, 178, 71, 0, 0, 78, 215, 78, 0, 199, 118, 224, 91, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 202, 19, 0, 166, 6, 0, 46, 143, 17, 0, 35, 156, 214, 148, 70, 0, 97, 75, 100, 0, 31, 159, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 171, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 165, 60, 0, 87, 0, 0, 0, 0, 0, 0, 0, 0, 81, 0, 0, 0, 183, 0, 0, 0, 0, 131, 154, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 159, 0, 0, 0, 0, 0, 120, 0, 0, 0, 114, 22, 0, 64, 0, 0, 0, 52, 137, 0, 117, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 18, 77, 0, 0, 105, 0, 0, 101, 151, 0, 0, 0, 0, 0, 159, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 34, 96, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 218, 0, 0, 0, 205, 0, 0, 40, 0, 59, 45, 0, 202, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 10, 38, 0, 0, 0, 0, 0, 0, 0, 0, 214, 106, 0, 90, 0, 0, 0, 186, 110, 0, 219, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 83, 166, 0, 175, 0, 0, 20, 195, 0, 0, 0, 0, 0, 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 53, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 36, 0, 0, 0, 0, 33, 85, 202, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 143, 176, 0, 0, 0, 0, 0, 0, 0, 0, 137, 4, 0, 29, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 82, 0, 0, 57, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 218, 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 176, 0, 0, 212, 192, 52, 0, 0, 0, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 91, 121, 0, 0, 0, 0, 0, 0, 0, 0, 132, 0, 0, 210, 0, 0, 0, 0, 210, 0, 0, 0, 0, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 155, 0, 165, 0, 0, 0, 0, 0, 0, 0, 44, 0, 0, 0, 0, 0, 0, 0, 0, 190, 0, 102, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 111, 0, 201, 64, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 111, 201, 0, 0, 0, 0, 144, 187, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 9, 7, 0, 0, 0, 0, 0, 104, 199, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 106, 0, 0, 211, 0, 0, 0, 0, 0, 122, 0, 215, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 193, 0, 0, 0, 132, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 221, 0, 0, 0, 51, 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 54, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 149, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 89, 204, 0, 0, 0, 0, 0, 0, 0, 169, 0, 0, 0, 0, 0, 0, 0, 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 50, 0, 0, 158, 65, 0, 0, 0, 0, 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 125, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 2, 0, 0, 0, 0, 167, 66, 0, 0, 0, 0, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 108, 0, 177, 0, 213, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 209, 0, 0, 0, 0, 142, 0, 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 147, 0, 0, 0, 154, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 218, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 54, 0, 0, 0, 0, 0, 0, 69, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 131, 0, 0, 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 124, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 176, 0, 0, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 178, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 193, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 210, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 115, 50, 0, 0, 0, 0, 0, 0, 0, 0, 162, 0, 0, 0, 0, 0, 0, 0, 0, 0, 138, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 83, 0, 0, 0, 0, 0, 0, 187, 0, 0, 0, 0, 0, 0, 0, 69, 0, 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 193, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 188, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 158, 1, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 196, 0, 0, 0, 0, 0, 0, 0, 0, 0, 139, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 124, 0, 0, 0, 0, 0, 0, 0, 0, 91, 74, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 13, 0, 78, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 68, 0, 0, 0, 0, 0, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 97, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 24, 0, 216, 0, 0, 0, 0, 0, 61, 0, 0, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 115, 0, 0, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 207, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 135, 0, 0, 0, 0, 0, 0, 162, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 85, 0, 0, 0, 0, 0, 0, 5, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 185, 0, 0, 0, 0, 122, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i4.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i4.h new file mode 100644 index 0000000000..bdc058b982 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i4.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I4_H_ +#define _ISIP_LDPC_BG1_I4_H_ +static int BG1_I4[46*68] = { + 212, 199, 189, 187, 0, 220, 5, 0, 0, 30, 145, 117, 217, 116, 0, 234, 145, 0, 96, 217, 74, 262, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 180, 0, 163, 224, 257, 161, 0, 77, 203, 118, 0, 110, 16, 0, 73, 153, 159, 148, 0, 157, 0, 120, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 259, 168, 221, 0, 134, 244, 203, 219, 64, 1, 4, 0, 0, 75, 230, 1, 0, 217, 270, 201, 235, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 188, 146, 0, 167, 109, 0, 83, 133, 198, 0, 42, 163, 58, 37, 116, 0, 243, 166, 1, 0, 114, 109, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 247, 236, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 262, 182, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 284, 0, 0, 0, 255, 0, 0, 0, 0, 80, 145, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 81, 0, 0, 0, 0, 0, 145, 0, 0, 0, 170, 91, 0, 60, 0, 0, 0, 178, 152, 0, 109, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 170, 190, 0, 0, 155, 0, 0, 185, 105, 0, 0, 0, 0, 0, 165, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 55, 1, 0, 253, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 99, 0, 0, 47, 0, 16, 231, 0, 55, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 163, 160, 0, 0, 0, 0, 0, 0, 0, 0, 94, 135, 0, 46, 0, 0, 0, 133, 77, 0, 210, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 179, 2, 0, 29, 0, 0, 268, 235, 0, 0, 0, 0, 0, 202, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 56, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 275, 0, 0, 0, 182, 0, 0, 0, 0, 274, 40, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 226, 163, 0, 0, 0, 0, 0, 0, 0, 0, 245, 152, 0, 239, 0, 0, 0, 0, 244, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 232, 0, 0, 1, 0, 0, 0, 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 0, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 187, 0, 0, 254, 17, 1, 0, 0, 0, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 171, 1, 0, 0, 0, 0, 0, 0, 0, 0, 184, 0, 0, 109, 0, 0, 0, 0, 69, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 271, 0, 14, 0, 0, 0, 0, 0, 0, 0, 100, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 154, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 138, 0, 1, 1, 0, 0, 0, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 162, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 152, 1, 0, 0, 0, 0, 242, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 0, 0, 0, 119, 145, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 266, 0, 0, 82, 0, 0, 0, 0, 0, 91, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 65, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 267, 0, 0, 0, 10, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 190, 73, 0, 0, 0, 258, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 181, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 237, 0, 0, 200, 1, 0, 0, 0, 0, 0, 0, 267, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 206, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 278, 0, 0, 0, 0, 0, 0, 0, 0, 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145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 167, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 212, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 198, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 109, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 200, 0, 0, 0, 0, 279, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 206, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 191, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 154, 0, 1, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 217, 0, 0, 0, 0, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 28, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 244, 0, 1, 0, 0, 0, 0, 0, 0, 271, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 19, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 169, 0, 0, 0, 0, 1, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h new file mode 100644 index 0000000000..2abfb3a319 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I5_H_ +#define _ISIP_LDPC_BG1_I5_H_ +static int BG1_I5[46*68] = { + 295, 119, 168, 331, 0, 208, 166, 0, 0, 244, 251, 2, 340, 202, 0, 54, 348, 0, 305, 168, 48, 189, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 78, 0, 226, 97, 339, 269, 0, 113, 303, 51, 0, 168, 254, 0, 335, 243, 258, 134, 0, 10, 0, 303, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 227, 36, 214, 0, 303, 112, 266, 129, 238, 295, 128, 0, 0, 111, 287, 126, 0, 132, 164, 211, 8, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 98, 95, 0, 50, 280, 0, 140, 167, 92, 0, 107, 247, 346, 270, 186, 0, 250, 216, 144, 0, 122, 122, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 43, 257, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 220, 131, 0, 252, 0, 0, 0, 0, 0, 0, 0, 0, 323, 0, 0, 0, 296, 0, 0, 0, 0, 259, 284, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 295, 0, 0, 0, 0, 0, 74, 0, 0, 0, 331, 100, 0, 173, 0, 0, 0, 151, 285, 0, 306, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 4, 104, 0, 0, 225, 0, 0, 298, 216, 0, 0, 0, 0, 0, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 349, 76, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 313, 0, 0, 0, 225, 0, 0, 18, 0, 60, 315, 0, 245, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 157, 89, 0, 0, 0, 0, 0, 0, 0, 0, 294, 112, 0, 93, 0, 0, 0, 153, 24, 0, 338, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 176, 254, 0, 28, 0, 0, 232, 50, 0, 0, 0, 0, 0, 268, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 26, 323, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 201, 0, 0, 0, 352, 0, 0, 0, 0, 167, 339, 193, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 124, 218, 0, 0, 0, 0, 0, 0, 0, 0, 143, 111, 0, 177, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 312, 0, 0, 252, 0, 0, 0, 266, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 323, 0, 0, 278, 157, 67, 0, 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 177, 349, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 82, 0, 0, 0, 0, 177, 0, 0, 0, 0, 0, 0, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 191, 0, 294, 0, 0, 0, 0, 0, 0, 0, 333, 0, 0, 0, 0, 0, 0, 0, 0, 332, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 229, 0, 248, 117, 0, 0, 0, 191, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 287, 247, 0, 0, 0, 0, 182, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 88, 111, 0, 0, 0, 0, 0, 148, 259, 0, 205, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 90, 0, 0, 66, 0, 0, 0, 0, 0, 156, 0, 245, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 163, 0, 0, 0, 265, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 347, 0, 0, 0, 144, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 281, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 158, 237, 0, 0, 0, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 19, 7, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 305, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 39, 0, 0, 171, 250, 0, 0, 0, 0, 0, 0, 289, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 280, 0, 0, 0, 0, 256, 112, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 326, 0, 327, 0, 227, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 92, 0, 0, 0, 0, 327, 0, 269, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 103, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 274, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 105, 0, 0, 0, 244, 0, 0, 0, 0, 0, 0, 108, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 213, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 102, 0, 0, 0, 0, 0, 298, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 280, 0, 0, 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 352, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 266, 0, 339, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 57, 305, 0, 0, 0, 0, 0, 0, 0, 0, 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 61, 0, 0, 0, 0, 0, 0, 321, 0, 0, 0, 0, 0, 0, 0, 113, 0, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 101, 0, 0, 0, 0, 211, 0, 0, 0, 0, 0, 196, 0, 0, 0, 0, 0, 0, 0, 0, 0, 269, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 36, 0, 0, 189, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 237, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 165, 0, 0, 0, 0, 0, 0, 0, 0, 197, 210, 0, 247, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 237, 0, 265, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 305, 0, 0, 0, 0, 0, 0, 0, 238, 0, 0, 0, 0, 0, 0, 0, 0, 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 124, 0, 78, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 289, 0, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 54, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 80, 0, 0, 0, 0, 0, 0, 245, 0, 294, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 83, 0, 0, 0, 0, 68, 0, 0, 0, 236, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h new file mode 100644 index 0000000000..91812045b5 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I6_H_ +#define _ISIP_LDPC_BG1_I6_H_ +static int BG1_I6[46*68] = { + 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 23, 0, 12, 125, 1, 11, 0, 1, 1, 3, 0, 17, 61, 0, 1, 7, 31, 1, 0, 169, 0, 32, 106, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 133, 38, 22, 0, 181, 5, 150, 49, 39, 123, 196, 0, 0, 156, 29, 86, 0, 48, 180, 43, 67, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 5, 7, 0, 34, 114, 0, 50, 22, 7, 0, 152, 84, 155, 88, 6, 0, 93, 174, 121, 0, 3, 143, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 25, 205, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 186, 101, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 66, 0, 0, 0, 208, 0, 0, 0, 0, 162, 73, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 5, 0, 0, 0, 0, 0, 0, 7, 0, 143, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 182, 0, 0, 0, 0, 46, 0, 0, 0, 154, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h new file mode 100644 index 0000000000..90563ade57 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h @@ -0,0 +1,51 @@ +#ifndef _ISIP_LDPC_BG1_I7_H_ +#define _ISIP_LDPC_BG1_I7_H_ +static int BG1_I7[46*68] = { + 136, 228, 127, 135, 0, 85, 84, 0, 0, 54, 226, 206, 129, 76, 0, 136, 218, 0, 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0000000000..7590dc1d73 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i0.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I0_H_ +#define _ISIP_LDPC_BG2_I0_H_ +static int BG2_I0[42*52] = { + 10, 118, 205, 27, 0, 0, 190, 0, 0, 206, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 168, 0, 0, 167, 254, 126, 227, 157, 225, 253, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 82, 115, 0, 45, 53, 0, 0, 0, 241, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 9, 59, 0, 159, 105, 210, 55, 19, 129, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 180, 215, 0, 0, 0, 0, 0, 0, 0, 0, 0, 72, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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236, 0, 239, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 47, 140, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 229, 0, 0, 0, 0, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 30, 0, 0, 0, 0, 144, 0, 0, 0, 0, 161, 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 9, 0, 0, 0, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 99, 102, 0, 0, 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 19, 0, 0, 0, 29, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 141, 0, 39, 0, 0, 0, 0, 155, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 220, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 32, 0, 0, 0, 67, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 240, 0, 0, 0, 0, 0, 0, 173, 0, 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 130, 0, 0, 0, 230, 0, 0, 0, 0, 0, 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h new file mode 100644 index 0000000000..0b07f65df2 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I1_H_ +#define _ISIP_LDPC_BG2_I1_H_ +static int BG2_I1[42*52] = { + 175, 98, 167, 67, 0, 0, 72, 0, 0, 173, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 0, 0, 37, 49, 93, 32, 188, 186, 4, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 26, 115, 0, 118, 111, 0, 0, 0, 115, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 137, 176, 0, 114, 73, 124, 119, 29, 187, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 73, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 11, 45, 0, 0, 0, 122, 0, 81, 0, 0, 0, 49, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 130, 0, 0, 0, 0, 93, 0, 101, 0, 50, 0, 185, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 81, 0, 0, 0, 187, 0, 17, 0, 0, 0, 103, 0, 144, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 119, 71, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 153, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 29, 0, 0, 0, 0, 0, 0, 133, 0, 186, 179, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 148, 0, 0, 0, 8, 0, 0, 0, 0, 0, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h new file mode 100644 index 0000000000..95d00f47a7 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I2_H_ +#define _ISIP_LDPC_BG2_I2_H_ +static int BG2_I2[42*52] = { + 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 138, 0, 0, 125, 1, 1, 89, 1, 1, 56, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 21, 95, 0, 100, 10, 0, 0, 0, 109, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 39, 16, 0, 103, 147, 13, 58, 54, 47, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 137, 0, 0, 0, 0, 0, 0, 0, 0, 0, 158, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 132, 0, 0, 0, 143, 0, 142, 0, 0, 0, 65, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 125, 0, 100, 0, 46, 0, 149, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 46, 0, 149, 0, 0, 0, 97, 0, 79, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 88, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 37, 0, 0, 144, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h new file mode 100644 index 0000000000..33675c80b0 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I3_H_ +#define _ISIP_LDPC_BG2_I3_H_ +static int BG2_I3[42*52] = { + 73, 111, 24, 182, 0, 0, 96, 0, 0, 9, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 54, 0, 0, 157, 116, 157, 116, 201, 30, 32, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 153, 132, 0, 47, 192, 0, 0, 0, 92, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 186, 7, 0, 37, 125, 125, 111, 157, 134, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 201, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 186, 139, 0, 0, 0, 171, 0, 220, 0, 0, 0, 194, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 124, 0, 0, 0, 0, 56, 0, 32, 0, 223, 0, 210, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 104, 0, 0, 0, 14, 0, 106, 0, 0, 0, 151, 0, 182, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 148, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 153, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 3, 0, 0, 0, 0, 0, 0, 31, 0, 185, 84, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 175, 151, 0, 0, 0, 0, 9, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 100, 0, 0, 0, 0, 0, 0, 139, 0, 111, 0, 0, 0, 100, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 47, 0, 218, 0, 0, 0, 0, 0, 0, 0, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 38, 114, 0, 0, 0, 0, 0, 0, 144, 0, 0, 0, 0, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 37, 0, 0, 0, 0, 96, 0, 0, 0, 0, 41, 0, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 201, 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 76, 0, 0, 0, 0, 0, 0, 0, 159, 0, 135, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 49, 0, 0, 0, 133, 0, 0, 0, 0, 0, 207, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 69, 0, 0, 0, 0, 0, 17, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 36, 139, 0, 0, 0, 0, 0, 0, 0, 0, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 7, 0, 0, 21, 0, 0, 0, 0, 0, 0, 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 81, 0, 0, 0, 0, 0, 0, 0, 44, 0, 0, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 50, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 157, 0, 0, 55, 0, 135, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 154, 89, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 212, 0, 0, 0, 0, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 91, 0, 0, 0, 0, 7, 0, 0, 0, 0, 222, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 0, 0, 0, 0, 0, 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 217, 213, 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 109, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 107, 0, 0, 45, 0, 186, 0, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 109, 0, 0, 0, 0, 22, 0, 0, 0, 0, 0, 0, 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 72, 0, 0, 0, 0, 13, 0, 0, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 202, 70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 92, 0, 0, 0, 166, 0, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 2, 0, 176, 0, 0, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 38, 0, 0, 0, 98, 0, 0, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 107, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 155, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 0, 0, 99, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 121, 0, 0, 0, 102, 0, 0, 0, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h new file mode 100644 index 0000000000..768869a5b8 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I4_H_ +#define _ISIP_LDPC_BG2_I4_H_ +static int BG2_I4[42*52] = { + 4, 27, 54, 36, 0, 0, 116, 0, 0, 128, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 20, 0, 0, 95, 105, 67, 85, 99, 70, 51, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 96, 107, 0, 93, 111, 0, 0, 0, 112, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 121, 122, 0, 23, 5, 74, 50, 129, 80, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 43, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 52, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 41, 141, 0, 0, 0, 85, 0, 138, 0, 0, 0, 72, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 110, 0, 0, 0, 0, 88, 0, 108, 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b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i5.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I5_H_ +#define _ISIP_LDPC_BG2_I5_H_ +static int BG2_I5[42*52] = { + 157, 144, 15, 4, 0, 0, 41, 0, 0, 124, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 18, 0, 0, 66, 64, 2, 56, 38, 172, 134, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 99, 169, 0, 108, 83, 0, 0, 0, 143, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 54, 175, 0, 175, 128, 18, 90, 18, 106, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 87, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 80, 85, 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0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h new file mode 100644 index 0000000000..a94ff36dab --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I6_H_ +#define _ISIP_LDPC_BG2_I6_H_ +static int BG2_I6[42*52] = { + 144, 20, 177, 166, 0, 0, 197, 0, 0, 14, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 19, 0, 0, 28, 4, 103, 186, 18, 15, 181, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 127, 164, 0, 48, 184, 0, 0, 0, 133, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 37, 49, 0, 19, 112, 204, 4, 192, 161, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 44, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 137, 50, 0, 0, 0, 37, 0, 133, 0, 0, 0, 63, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 35, 0, 199, 0, 169, 0, 13, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 164, 0, 0, 0, 79, 0, 144, 0, 0, 0, 108, 0, 59, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 102, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 187, 0, 0, 0, 0, 0, 0, 28, 0, 206, 82, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 126, 61, 0, 0, 0, 0, 178, 52, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 40, 0, 0, 0, 0, 0, 0, 30, 0, 36, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 19, 0, 156, 0, 0, 0, 0, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 33, 54, 0, 0, 0, 0, 0, 0, 96, 0, 0, 0, 0, 187, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 92, 0, 0, 0, 0, 21, 0, 0, 0, 0, 53, 0, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 126, 0, 0, 0, 0, 0, 0, 0, 32, 0, 55, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 58, 0, 0, 0, 202, 0, 0, 0, 0, 0, 143, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 130, 0, 0, 0, 0, 0, 204, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 111, 125, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 197, 0, 0, 36, 0, 0, 0, 0, 0, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 11, 0, 0, 0, 0, 0, 0, 0, 123, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 203, 127, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 158, 0, 0, 0, 168, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 198, 0, 168, 0, 0, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 158, 0, 0, 0, 174, 0, 0, 0, 0, 0, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 182, 0, 0, 0, 0, 0, 0, 158, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 164, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 192, 0, 0, 0, 198, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h new file mode 100644 index 0000000000..21cbe57a3f --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h @@ -0,0 +1,47 @@ +#ifndef _ISIP_LDPC_BG2_I7_H_ +#define _ISIP_LDPC_BG2_I7_H_ +static int BG2_I7[42*52] = { + 146, 132, 72, 22, 0, 0, 24, 0, 0, 113, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 143, 0, 0, 175, 184, 28, 97, 24, 10, 168, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 75, 32, 0, 4, 54, 0, 0, 0, 156, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 240, 172, 0, 96, 111, 160, 200, 44, 76, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 30, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 181, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 122, 42, 0, 0, 0, 170, 0, 89, 0, 0, 0, 208, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 138, 0, 0, 0, 0, 73, 0, 173, 0, 125, 0, 57, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 87, 0, 0, 0, 187, 0, 88, 0, 0, 0, 173, 0, 155, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 177, 170, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 226, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 168, 0, 0, 0, 0, 0, 0, 239, 0, 49, 69, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 39, 218, 0, 0, 0, 0, 209, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 179, 0, 0, 0, 0, 0, 0, 215, 0, 169, 0, 0, 0, 52, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 125, 0, 123, 0, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 49, 58, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 220, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 83, 0, 0, 0, 0, 233, 0, 0, 0, 0, 205, 0, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 218, 158, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 171, 0, 0, 0, 0, 0, 0, 0, 24, 0, 176, 203, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 197, 0, 0, 0, 174, 0, 0, 0, 0, 0, 196, 219, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 129, 0, 0, 0, 0, 0, 212, 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 40, 85, 0, 0, 0, 0, 0, 0, 0, 0, 89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 118, 0, 0, 228, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 239, 0, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 196, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 6, 0, 0, 95, 0, 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 82, 20, 0, 0, 0, 0, 0, 0, 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 67, 0, 0, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 147, 0, 0, 0, 0, 67, 0, 0, 0, 0, 191, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 65, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 8, 145, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 26, 0, 0, 0, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 38, 0, 0, 140, 0, 222, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 202, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 180, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 47, 0, 0, 0, 0, 3, 0, 0, 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 185, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 136, 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 86, 0, 0, 0, 226, 0, 0, 0, 0, 0, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 179, 0, 113, 0, 0, 0, 0, 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 155, 0, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 43, 0, 0, 0, 42, 0, 0, 0, 0, 0, 106, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 168, 0, 0, 0, 0, 0, 0, 46, 0, 0, 0, 0, 190, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, 68, 0, 0, 181, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 54, 0, 0, 0, 216, 0, 0, 0, 0, 0, 231, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 +}; +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/README.md b/openair1/PHY/CODING/GPU_LDPC/README.md new file mode 100644 index 0000000000..b460d5fa77 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/README.md @@ -0,0 +1,17 @@ +### LDPC DECODER ++ `intuitive_ldpc`: + Intuitive methods of LDPC decoder. This method stores the whole expanded Base Graph, CN, BN buffer as they are. Then, does the cn and bn process according to the equation in `nrLDPC.pdf`. + ++ `optimized_ldpc`: + This version inherits the idea of current oai ldpc_decoder. It stores lots of LUTs and shrinks the cn, bnbuffer size comparing to the former implementation. Right now, it only supports the longest code block 8448. + +### Usage ++ `make ldpc` will compile the program `ldpc`. ++ `make prof [num=<0~100>]` will show the detail of GPU activity. ++ `make test` will build ldpc executable and run `check.sh` to verify the correctness of the implementation. + +### Verification ++ The input (channel output) of the LDPC decoder is produced by the `ldpctest` program from OAI. ++ The verification is done by comparing the data decoded with the input data (channel output), and also the data output(`estimated_output`) produced by oai `ldpctest`. + + diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/Makefile b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/Makefile new file mode 100644 index 0000000000..b6af255a6e --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/Makefile @@ -0,0 +1,36 @@ +NVCC = nvcc +CFLAGS = +PROF = nvprof +exec = ldpc +file = channel_output.txt +OBJS = util.o +code = 8448 +num = 1 +.PHONY: clean debug + + +## Target-specific Variable Values +debug: CFLAGS += -Ddebug -g -G +debug: clean $(exec) + cuda-gdb -q --args $(exec) -l $(code) -f $(file) + +$(exec): $(exec).cu $(OBJS) + $(NVCC) $(CFLAGS) -o $@ $^ + +%.o: %.cu + cp ../test_input/8448/$(num).txt $(file) + $(NVCC) $(CFLAGS) -o $@ -c $< + +run: clean $(exec) + ./$(exec) -l $(code) -f $(file) + +prof: clean $(exec) + cp ../test_input/8448/$(num).txt $(file) + $(PROF) ./$(exec) -l $(code) -f $(file) + +test: clean $(exec) + ./check.sh $(code) + rm $(OBJS) $(file) + +clean: + rm -rf *.o test.* $(exec) CN* BN* log.txt channel_output.txt diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/check.sh b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/check.sh new file mode 100644 index 0000000000..b24a22c97a --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/check.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +exec=ldpc + +help() +{ + echo "Usage: $0 " +} + +main() +{ + if [ -z $@ ]; then + help + exit 1 + fi + + dir=$@ + files=`ls ../test_input/$dir | grep txt` +# files="1.txt 2.txt 3.txt" + + index=1 + for file in $files + do + cp ../test_input/$dir/$file channel_output.txt + echo "==== test $index ====" >> log.txt + ./$exec -l $dir -f channel_output.txt >> log.txt + echo ' ' >> log.txt + index=$((index+1)) + done +} + +main $@ diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu new file mode 100644 index 0000000000..faf0438d76 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu @@ -0,0 +1,323 @@ +#include +#include +#include +#include +#include +#include +#include "../BGs/isip_ldpc_bg1_i0.h" +#include "../BGs/isip_ldpc_bg1_i1.h" +#include "../BGs/isip_ldpc_bg1_i2.h" +#include "../BGs/isip_ldpc_bg1_i3.h" +#include "../BGs/isip_ldpc_bg1_i4.h" +#include "../BGs/isip_ldpc_bg1_i5.h" +#include "../BGs/isip_ldpc_bg1_i6.h" +#include "../BGs/isip_ldpc_bg1_i7.h" +#include "../BGs/isip_ldpc_bg2_i0.h" +#include "../BGs/isip_ldpc_bg2_i1.h" +#include "../BGs/isip_ldpc_bg2_i2.h" +#include "../BGs/isip_ldpc_bg2_i3.h" +#include "../BGs/isip_ldpc_bg2_i4.h" +#include "../BGs/isip_ldpc_bg2_i5.h" +#include "../BGs/isip_ldpc_bg2_i6.h" +#include "../BGs/isip_ldpc_bg2_i7.h" +#include "util.h" + +#define TNPB 35 +#define BNPG 1024 +#define ITER 5 + +__constant__ int BG_GPU[46*68]; + + + +__global__ +void BNProcess(int flag, int *BN, int *CN, int *CNbuf, const int *const_llr, int BG_col, int BG_row, int Zc) +{ + int *CNG = (flag)? CN : CNbuf; + int id = blockIdx.x*blockDim.x + threadIdx.x; + + for(int col = id; col < BG_col*Zc; col += (TNPB*BNPG)) + { + int tmp = const_llr[col]; + for(int row = 0; row < BG_row; row++) + { + int up_shift = (BG_GPU[col/Zc + row*BG_col] - 1)%Zc; + if(up_shift != -1) + { + int row_idx = col%Zc; + row_idx = row_idx - up_shift; + if(row_idx < 0) row_idx = Zc + row_idx; + + row_idx = row*Zc + row_idx; + tmp = tmp + CNG[row_idx*BG_col*Zc + col]; + } + } + BN[col] = tmp; + } + __syncthreads(); +} + + + +__global__ void CNProcess(int flag, int *BN, int *CN, int *CNbuf, int BG_col, int BG_row, int Zc) +{ + int *CNG = (flag)? CN : CNbuf; + int *SCNG = (flag)? CNbuf : CN; + int id = blockIdx.x*blockDim.x + threadIdx.x; + + for(int row = id; row < BG_row*Zc; row += (TNPB*BNPG)) + { + for(int col = 0; col < BG_col; col++) + { + int right_shift = BG_GPU[(row/Zc)*BG_col + col] -1; + if(right_shift != -1) + { + int row_idx = row; +// int col_idx = ((row%384) + right_shift%384) %384 + col*384; + int col_idx = (row + right_shift) %Zc + col*Zc; + int sgn_cnt = 0, min = INT32_MAX; + for(int comp = 0; comp < BG_col; comp++) + { + if(comp == col) continue; + int comp_right_shift = BG_GPU[(row/Zc)*BG_col + comp] -1; + if(comp_right_shift != -1) + { + int comp_row_idx = row; +// int comp_col_idx = ((row%384) + (comp_right_shift%384)) %384 + comp*384; + int comp_col_idx = (row + comp_right_shift) %Zc + comp*Zc; + int tmp = BN[comp_col_idx] - CNG[comp_row_idx*BG_col*Zc + comp_col_idx]; + if(tmp < 0) + { + tmp = -tmp; + sgn_cnt++; + } + if(tmp < min) min = tmp; + } + } + SCNG[row_idx*BG_col*Zc + col_idx] = (sgn_cnt%2 == 0)? min: -min; + } + } + } + __syncthreads(); +} + +__global__ void BitDetermination(int *BN, unsigned int *decode_d) +{ + __shared__ int tmp[256]; + int tid = blockIdx.x*256 + threadIdx.x; + int bid = threadIdx.x; + tmp[bid] = 0; + + + if(BN[tid] < 0) + { + tmp[bid] = 1 << (bid&7); + } + + __syncthreads(); + + if(threadIdx.x < 32) + { + decode_d[blockIdx.x*32 + threadIdx.x] = 0; + for(int i = 0; i < 8; i++) + { + decode_d[blockIdx.x*32 + threadIdx.x] += tmp[threadIdx.x*8+i]; + } + } +} + + +// helper function +void printllr(const char *name, int *src, int *des, int count, int type_size) +{ + cudaCheck( cudaMemcpy((void *)des, (const void *)src, count*type_size, cudaMemcpyDeviceToHost) ); + + FILE *fp = fopen(name, "w"); + if(!fp) printf("[error]: open file %s failed\n", name); + + for(int i = 0; i < count; i++){ + fprintf(fp, "llr[%d]= %d\n", i, des[i]); + } +} + + +int main(int argc, char* argv[]) +{ + int opt = 0, block_length = 0, BG = 0, Kb = 0, Zc = 0, BG_row = 0, BG_col = 0, lift_index = 0; + char file[50] = {}; + short lift_size[51] = {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}; + short lift_set[][9] = { + {2,4,8,16,32,64,128,256}, + {3,6,12,24,48,96,192,384}, + {5,10,20,40,80,160,320}, + {7,14,28,56,112,224}, + {9,18,36,72,144,288}, + {11,22,44,88,176,352}, + {13,26,52,104,208}, + {15,30,60,120,240}, + {0}}; + + while( (opt = getopt(argc, argv, "l:f:")) != -1){ + switch(opt){ + case 'l': + block_length = atoi(optarg); + break; + case 'f': + strncpy(file, optarg, strlen(optarg)); + break; + default: + fprintf(stderr, "Usage: %s [-l code block length] <-f input file>\n", argv[0]); + exit(1); + } + } + + if(block_length == 0 || file[0] == ' '){ + fprintf(stderr, "no input file specified or code block length == 0"); + } + + if(block_length > 3840){ + BG = 1; + Kb = 22; + BG_row = 46; + BG_col = 68; + }else if(block_length <= 3840){ + BG = 2; + BG_row = 42; + BG_col = 52; + if(block_length > 640) + Kb = 10; + else if(block_length > 560) + Kb = 9; + else if(block_length > 192) + Kb = 8; + else + Kb = 6; + } + + for(int i = 0; i < 51; i++){ + if(lift_size[i] >= (double)block_length/Kb){ + Zc = lift_size[i]; + break; + } + } + + for(int i = 0; lift_set[i][0] != 0; i++){ + for(int j = 0; lift_set[i][j] != 0; j++){ + if(Zc == lift_set[i][j]){ + lift_index = i; + break; + } + } + } + + int *BG_CPU = NULL; + switch(lift_index){ + case 0: + BG_CPU = (BG == 1)? BG1_I0:BG2_I0; + break; + case 1: + BG_CPU = (BG == 1)? BG1_I1:BG2_I1; + break; + case 2: + BG_CPU = (BG == 1)? BG1_I2:BG2_I2; + break; + case 3: + BG_CPU = (BG == 1)? BG1_I3:BG2_I3; + break; + case 4: + BG_CPU = (BG == 1)? BG1_I4:BG2_I4; + break; + case 5: + BG_CPU = (BG == 1)? BG1_I5:BG2_I5; + break; + case 6: + BG_CPU = (BG == 1)? BG1_I6:BG2_I6; + break; + case 7: + BG_CPU = (BG == 1)? BG1_I7:BG2_I7; + break; + } + +// printf("BG %d lift_index %d Zc %d BG_row %d BG_col %d\n", BG, lift_index, Zc, BG_row, BG_col); + + // alloc cpu memory + unsigned int *input = (unsigned int*)malloc(sizeof(unsigned int)*8448/8), *decode_output_d, *decode_output_h; + int *BN, *CN, *CNbuf, *channel_output, *const_llr; +// debug +// int *p_BN = (int*)calloc(68*384, sizeof(int)); +// int *p_CN = (int*)calloc(68*384*46*384, sizeof(int)); + int *debug_llr = (int*)calloc(68*384, sizeof(int)); + cudaCheck( cudaHostAlloc((void**)&channel_output, 68*384*sizeof(int), cudaHostAllocDefault) ); + cudaCheck( cudaHostAlloc((void**)&decode_output_h, (8448/8)*sizeof(unsigned int), cudaHostAllocMapped) ); + // | cudaHostAllocPortable | cudaHostAllocMapped | cudaHostAllocWriteCombined); + + // read data from input file + ReadDataFromFile(file, input, channel_output, block_length, BG_col, Zc); + + // alloc gpu memory + // BG + cudaCheck( cudaMemcpyToSymbol(BG_GPU, BG_CPU, BG_col*BG_row*sizeof(int)) ); + // LLR CN BN BUF + size_t p_llr; + cudaCheck( cudaMallocPitch((void**)&const_llr, &p_llr, 68*384*sizeof(int), 1) ); + cudaCheck( cudaMallocPitch((void**)&BN, &p_llr, 68*384*sizeof(int), 1) ); + cudaCheck( cudaMallocPitch((void**)&CN, &p_llr, 68*384*sizeof(int), 46*384) ); + cudaCheck( cudaMallocPitch((void**)&CNbuf, &p_llr, 68*384*sizeof(int), 46*384) ); + + cudaCheck( cudaMemcpyAsync((void*)const_llr, (const void*)channel_output, 68*384*sizeof(int), cudaMemcpyHostToDevice) ); + cudaCheck( cudaMemcpyAsync((void*)BN, (const void*)channel_output, 68*384*sizeof(int), cudaMemcpyHostToDevice) ); + cudaCheck( cudaHostGetDevicePointer((void**)&decode_output_d, (void*)decode_output_h, 0) ); + cudaDeviceSynchronize(); + + cudaEvent_t start, end; + float time; + + cudaEventCreate(&start); + cudaEventCreate(&end); + + cudaEventRecord(start,0); + + dim3 grid(BNPG, 1, 1); + dim3 block(TNPB, 1, 1); + int flag = 0; + char str[20] = {}; + for(int it = 0; it < ITER; it++){ + CNProcess<<>>(flag, BN, CN, CNbuf, BG_col, BG_row, Zc); + flag = (flag+1)&1; + BNProcess<<>>(flag, BN, CN, CNbuf, const_llr, BG_col, BG_row, Zc); +#ifdef debug + snprintf(str, 20, "%s_%d", "llr", it); + printllr(str, BN, debug_llr, 68*384, sizeof(int)); +#endif + } + BitDetermination<<<33, 256>>>(BN, decode_output_d); + + cudaDeviceSynchronize(); + cudaEventRecord(end,0); + cudaEventSynchronize(end); + cudaEventElapsedTime(&time, start, end); + + + int err_num = 0; + for(int i = 0; i < block_length/8; i++){ + if(input[i] != decode_output_h[i]){ + printf("input[%d] = %d, decode_output[%d] = %d\n", i, input[i], i, decode_output_h[i]); + err_num++; + } + } + printf("err_num == %d\n", err_num); + printf("decode time:%f ms\n",time); + + // free resource + free(input); +// free(p_BN); +// free(p_CN); + cudaFreeHost(channel_output); + cudaFreeHost(decode_output_h); + cudaFree(const_llr); + cudaFree(BN); + cudaFree(CN); + cudaFree(CNbuf); + + return 0; +} diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.cu b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.cu new file mode 100644 index 0000000000..ff39c16938 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.cu @@ -0,0 +1,37 @@ +#include +#include +#include "util.h" + + +void ReadDataFromFile(const char *file, unsigned int *input_data_arr, int *channel_data_arr, int block_length, int BG_col, int Zc) +{ +// static const char testin[] = "../test_input/test_case_1.txt"; + file_t inputfile; + strcpy(inputfile.filename, file); + inputfile.fptr = fopen(inputfile.filename, "r"); + if(inputfile.fptr == NULL) + { + puts("cannot open file"); + } + + // data processing + fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of gen test + for(int i = 0; i < block_length/8; i++) + { + fscanf(inputfile.fptr, "%d", &input_data_arr[i]); + } + fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of '\n' + fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of test end + fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of channel + /* + for(int i = 0; i < 2*384; i++) + { + channel_data_arr[i] = 0; + } + */ + for(int i = 0; i < BG_col*Zc; i++) + { + fscanf(inputfile.fptr, "%d", &channel_data_arr[i]); + } + fclose(inputfile.fptr); +} diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h new file mode 100644 index 0000000000..51ce0e9604 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h @@ -0,0 +1,47 @@ +#ifndef __UTIL_H__ +#define __UTIL_H__ + +// cuda check macro +#define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } +inline void cudaAssert(cudaError_t code, const char *file, int line) +{ + if (code != cudaSuccess){ + fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line); + exit(code); + } +} + +// struct +typedef struct +{ + FILE* fptr; + char filename[64]; + char tmp[64]; +}file_t; + +// utility +void ReadDataFromFile(const char*, unsigned int*, int*, int, int, int); +__global__ void BNProcess(int flag, int *BN, int *CN, int *CNbuf, const int *const_llr); +__global__ void CNProcess(int flag, int *BN, int *CN, int *CNbuf); +__global__ void BitDetermination(int *BN, unsigned int *decode_d); + +/* +int32_t nrLDPC_decoder(t_nrLDPC_dec_params* p_decParams, + int8_t* p_llr, int8_t* p_out, + t_nrLDPC_procBuf* p_procBuf, + t_nrLDPC_time_stats* p_profiler){ + + return iter; +} + +static inline uint32_t nrLDPC_decoder_core(int8_t* p_llr, int8_t* p_out, + t_nrLDPC_procBuf* p_procBuf, + uint32_t numLLR, t_nrLDPC_lut* p_lut, + t_nrLDPC_dec_params* p_decParams, + t_nrLDPC_time_stats* p_profiler){ + + return iter; +} + +*/ +#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/Makefile b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/Makefile new file mode 100644 index 0000000000..bf4f3b82d1 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/Makefile @@ -0,0 +1,29 @@ +EXEC = gen_idx +TXT = gen_matrix.txt +DEBUG = debug +FILE = channel_output.txt +num = 1 +CFLAGS= + +gen: clean gen_idx.c + $(CC) $(EXEC).c -o $(EXEC) -g + +ldpc: clean ldpc.cu + cp ../test_input/8448/$(num).txt $(FILE) + nvcc $(CFLAGS) ldpc.cu -o ldpc + mkdir debug + +test: ldpc + ./check.sh + +cgdb: CFLAGS += -g -G +cgdb: clean ldpc + cuda-gdb --silent --args ldpc $(FILE) + +prof: clean ldpc + cp ../test_input/8448/$(num).txt $(FILE) + nvprof ./ldpc $(FILE) + +.PHONY: clean +clean: + $(RM) -rf $(DEBUG) $(EXEC) $(TXT) ldpc log.txt $(FILE) diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/bg1_i1_index_array.h b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/bg1_i1_index_array.h new file mode 100644 index 0000000000..74dd3d9536 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/bg1_i1_index_array.h @@ -0,0 +1,9 @@ +int l2c_idx[121344] = { 307, 403, 818, 1521, 2101, 2520, 3773, 4128, 4333, 4625, 5349, 5975, 6250, 7154, 7476, 8010, 8410, 8449, 8832, 308, 404, 819, 1522, 2102, 2521, 3774, 4129, 4334, 4626, 5350, 5976, 6251, 7155, 7477, 8011, 8411, 8450, 8833, 309, 405, 820, 1523, 2103, 2522, 3775, 4130, 4335, 4627, 5351, 5977, 6252, 7156, 7478, 8012, 8412, 8451, 8834, 310, 406, 821, 1524, 2104, 2523, 3776, 4131, 4336, 4628, 5352, 5978, 6253, 7157, 7479, 8013, 8413, 8452, 8835, 311, 407, 822, 1525, 2105, 2524, 3777, 4132, 4337, 4629, 5353, 5979, 6254, 7158, 7480, 8014, 8414, 8453, 8836, 312, 408, 823, 1526, 2106, 2525, 3778, 4133, 4338, 4630, 5354, 5980, 6255, 7159, 7481, 8015, 8415, 8454, 8837, 313, 409, 824, 1527, 2107, 2526, 3779, 4134, 4339, 4631, 5355, 5981, 6256, 7160, 7482, 8016, 8416, 8455, 8838, 314, 410, 825, 1528, 2108, 2527, 3780, 4135, 4340, 4632, 5356, 5982, 6257, 7161, 7483, 8017, 8417, 8456, 8839, 315, 411, 826, 1529, 2109, 2528, 3781, 4136, 4341, 4633, 5357, 5983, 6258, 7162, 7484, 8018, 8418, 8457, 8840, 316, 412, 827, 1530, 2110, 2529, 3782, 4137, 4342, 4634, 5358, 5984, 6259, 7163, 7485, 8019, 8419, 8458, 8841, 317, 413, 828, 1531, 2111, 2530, 3783, 4138, 4343, 4635, 5359, 5985, 6260, 7164, 7486, 8020, 8420, 8459, 8842, 318, 414, 829, 1532, 2112, 2531, 3784, 4139, 4344, 4636, 5360, 5986, 6261, 7165, 7487, 8021, 8421, 8460, 8843, 319, 415, 830, 1533, 2113, 2532, 3785, 4140, 4345, 4637, 5361, 5987, 6262, 7166, 7488, 8022, 8422, 8461, 8844, 320, 416, 831, 1534, 2114, 2533, 3786, 4141, 4346, 4638, 5362, 5988, 6263, 7167, 7489, 8023, 8423, 8462, 8845, 321, 417, 832, 1535, 2115, 2534, 3787, 4142, 4347, 4639, 5363, 5989, 6264, 7168, 7490, 8024, 8424, 8463, 8846, 322, 418, 833, 1152, 2116, 2535, 3788, 4143, 4348, 4640, 5364, 5990, 6265, 7169, 7491, 8025, 8425, 8464, 8847, 323, 419, 834, 1153, 2117, 2536, 3789, 4144, 4349, 4641, 5365, 5991, 6266, 7170, 7492, 8026, 8426, 8465, 8848, 324, 420, 835, 1154, 2118, 2537, 3790, 4145, 4350, 4642, 5366, 5992, 6267, 7171, 7493, 8027, 8427, 8466, 8849, 325, 421, 836, 1155, 2119, 2538, 3791, 4146, 4351, 4643, 5367, 5993, 6268, 7172, 7494, 8028, 8428, 8467, 8850, 326, 422, 837, 1156, 2120, 2539, 3792, 4147, 4352, 4644, 5368, 5994, 6269, 7173, 7495, 8029, 8429, 8468, 8851, 327, 423, 838, 1157, 2121, 2540, 3793, 4148, 4353, 4645, 5369, 5995, 6270, 7174, 7496, 8030, 8430, 8469, 8852, 328, 424, 839, 1158, 2122, 2541, 3794, 4149, 4354, 4646, 5370, 5996, 6271, 7175, 7497, 8031, 8431, 8470, 8853, 329, 425, 840, 1159, 2123, 2542, 3795, 4150, 4355, 4647, 5371, 5997, 6272, 7176, 7498, 8032, 8432, 8471, 8854, 330, 426, 841, 1160, 2124, 2543, 3796, 4151, 4356, 4648, 5372, 5998, 6273, 7177, 7499, 8033, 8433, 8472, 8855, 331, 427, 842, 1161, 2125, 2544, 3797, 4152, 4357, 4649, 5373, 5999, 6274, 7178, 7500, 8034, 8434, 8473, 8856, 332, 428, 843, 1162, 2126, 2545, 3798, 4153, 4358, 4650, 5374, 6000, 6275, 7179, 7501, 8035, 8435, 8474, 8857, 333, 429, 844, 1163, 2127, 2546, 3799, 4154, 4359, 4651, 5375, 6001, 6276, 7180, 7502, 8036, 8436, 8475, 8858, 334, 430, 845, 1164, 2128, 2547, 3800, 4155, 4360, 4652, 4992, 6002, 6277, 7181, 7503, 8037, 8437, 8476, 8859, 335, 431, 846, 1165, 2129, 2548, 3801, 4156, 4361, 4653, 4993, 6003, 6278, 7182, 7504, 8038, 8438, 8477, 8860, 336, 432, 847, 1166, 2130, 2549, 3802, 4157, 4362, 4654, 4994, 6004, 6279, 7183, 7505, 8039, 8439, 8478, 8861, 337, 433, 848, 1167, 2131, 2550, 3803, 4158, 4363, 4655, 4995, 6005, 6280, 7184, 7506, 8040, 8440, 8479, 8862, 338, 434, 849, 1168, 2132, 2551, 3804, 4159, 4364, 4656, 4996, 6006, 6281, 7185, 7507, 8041, 8441, 8480, 8863, 339, 435, 850, 1169, 2133, 2552, 3805, 4160, 4365, 4657, 4997, 6007, 6282, 7186, 7508, 8042, 8442, 8481, 8864, 340, 436, 851, 1170, 2134, 2553, 3806, 4161, 4366, 4658, 4998, 6008, 6283, 7187, 7509, 8043, 8443, 8482, 8865, 341, 437, 852, 1171, 2135, 2554, 3807, 4162, 4367, 4659, 4999, 6009, 6284, 7188, 7510, 8044, 8444, 8483, 8866, 342, 438, 853, 1172, 2136, 2555, 3808, 4163, 4368, 4660, 5000, 6010, 6285, 7189, 7511, 8045, 8445, 8484, 8867, 343, 439, 854, 1173, 2137, 2556, 3809, 4164, 4369, 4661, 5001, 6011, 6286, 7190, 7512, 8046, 8446, 8485, 8868, 344, 440, 855, 1174, 2138, 2557, 3810, 4165, 4370, 4662, 5002, 6012, 6287, 7191, 7513, 8047, 8447, 8486, 8869, 345, 441, 856, 1175, 2139, 2558, 3811, 4166, 4371, 4663, 5003, 6013, 6288, 7192, 7514, 8048, 8064, 8487, 8870, 346, 442, 857, 1176, 2140, 2559, 3812, 4167, 4372, 4664, 5004, 6014, 6289, 7193, 7515, 8049, 8065, 8488, 8871, 347, 443, 858, 1177, 2141, 2560, 3813, 4168, 4373, 4665, 5005, 6015, 6290, 7194, 7516, 8050, 8066, 8489, 8872, 348, 444, 859, 1178, 2142, 2561, 3814, 4169, 4374, 4666, 5006, 6016, 6291, 7195, 7517, 8051, 8067, 8490, 8873, 349, 445, 860, 1179, 2143, 2562, 3815, 4170, 4375, 4667, 5007, 6017, 6292, 7196, 7518, 8052, 8068, 8491, 8874, 350, 446, 861, 1180, 2144, 2563, 3816, 4171, 4376, 4668, 5008, 6018, 6293, 7197, 7519, 8053, 8069, 8492, 8875, 351, 447, 862, 1181, 2145, 2564, 3817, 4172, 4377, 4669, 5009, 6019, 6294, 7198, 7520, 8054, 8070, 8493, 8876, 352, 448, 863, 1182, 2146, 2565, 3818, 4173, 4378, 4670, 5010, 6020, 6295, 7199, 7521, 8055, 8071, 8494, 8877, 353, 449, 864, 1183, 2147, 2566, 3819, 4174, 4379, 4671, 5011, 6021, 6296, 7200, 7522, 8056, 8072, 8495, 8878, 354, 450, 865, 1184, 2148, 2567, 3820, 4175, 4380, 4672, 5012, 6022, 6297, 7201, 7523, 8057, 8073, 8496, 8879, 355, 451, 866, 1185, 2149, 2568, 3821, 4176, 4381, 4673, 5013, 6023, 6298, 7202, 7524, 8058, 8074, 8497, 8880, 356, 452, 867, 1186, 2150, 2569, 3822, 4177, 4382, 4674, 5014, 6024, 6299, 7203, 7525, 8059, 8075, 8498, 8881, 357, 453, 868, 1187, 2151, 2570, 3823, 4178, 4383, 4675, 5015, 6025, 6300, 7204, 7526, 8060, 8076, 8499, 8882, 358, 454, 869, 1188, 2152, 2571, 3824, 4179, 4384, 4676, 5016, 6026, 6301, 7205, 7527, 8061, 8077, 8500, 8883, 359, 455, 870, 1189, 2153, 2572, 3825, 4180, 4385, 4677, 5017, 6027, 6302, 7206, 7528, 8062, 8078, 8501, 8884, 360, 456, 871, 1190, 2154, 2573, 3826, 4181, 4386, 4678, 5018, 6028, 6303, 7207, 7529, 8063, 8079, 8502, 8885, 361, 457, 872, 1191, 2155, 2574, 3827, 4182, 4387, 4679, 5019, 6029, 6304, 7208, 7530, 7680, 8080, 8503, 8886, 362, 458, 873, 1192, 2156, 2575, 3828, 4183, 4388, 4680, 5020, 6030, 6305, 7209, 7531, 7681, 8081, 8504, 8887, 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3490, 3845, 4434, 4726, 5066, 6076, 6351, 7255, 7577, 7727, 8127, 8550, 8933, 25, 505, 920, 1239, 2203, 2622, 3491, 3846, 4435, 4727, 5067, 6077, 6352, 7256, 7578, 7728, 8128, 8551, 8934, 26, 506, 921, 1240, 2204, 2623, 3492, 3847, 4436, 4728, 5068, 6078, 6353, 7257, 7579, 7729, 8129, 8552, 8935, 27, 507, 922, 1241, 2205, 2624, 3493, 3848, 4437, 4729, 5069, 6079, 6354, 7258, 7580, 7730, 8130, 8553, 8936, 28, 508, 923, 1242, 2206, 2625, 3494, 3849, 4438, 4730, 5070, 6080, 6355, 7259, 7581, 7731, 8131, 8554, 8937, 29, 509, 924, 1243, 2207, 2626, 3495, 3850, 4439, 4731, 5071, 6081, 6356, 7260, 7582, 7732, 8132, 8555, 8938, 30, 510, 925, 1244, 2208, 2627, 3496, 3851, 4440, 4732, 5072, 6082, 6357, 7261, 7583, 7733, 8133, 8556, 8939, 31, 511, 926, 1245, 2209, 2628, 3497, 3852, 4441, 4733, 5073, 6083, 6358, 7262, 7584, 7734, 8134, 8557, 8940, 32, 512, 927, 1246, 2210, 2629, 3498, 3853, 4442, 4734, 5074, 6084, 6359, 7263, 7585, 7735, 8135, 8558, 8941, 33, 513, 928, 1247, 2211, 2630, 3499, 3854, 4443, 4735, 5075, 6085, 6360, 7264, 7586, 7736, 8136, 8559, 8942, 34, 514, 929, 1248, 2212, 2631, 3500, 3855, 4444, 4736, 5076, 6086, 6361, 7265, 7587, 7737, 8137, 8560, 8943, 35, 515, 930, 1249, 2213, 2632, 3501, 3856, 4445, 4737, 5077, 6087, 6362, 7266, 7588, 7738, 8138, 8561, 8944, 36, 516, 931, 1250, 2214, 2633, 3502, 3857, 4446, 4738, 5078, 6088, 6363, 7267, 7589, 7739, 8139, 8562, 8945, 37, 517, 932, 1251, 2215, 2634, 3503, 3858, 4447, 4739, 5079, 6089, 6364, 7268, 7590, 7740, 8140, 8563, 8946, 38, 518, 933, 1252, 2216, 2635, 3504, 3859, 4448, 4740, 5080, 6090, 6365, 7269, 7591, 7741, 8141, 8564, 8947, 39, 519, 934, 1253, 2217, 2636, 3505, 3860, 4449, 4741, 5081, 6091, 6366, 7270, 7592, 7742, 8142, 8565, 8948, 40, 520, 935, 1254, 2218, 2637, 3506, 3861, 4450, 4742, 5082, 6092, 6367, 7271, 7593, 7743, 8143, 8566, 8949, 41, 521, 936, 1255, 2219, 2638, 3507, 3862, 4451, 4743, 5083, 6093, 6368, 7272, 7594, 7744, 8144, 8567, 8950, 42, 522, 937, 1256, 2220, 2639, 3508, 3863, 4452, 4744, 5084, 6094, 6369, 7273, 7595, 7745, 8145, 8568, 8951, 43, 523, 938, 1257, 2221, 2640, 3509, 3864, 4453, 4745, 5085, 6095, 6370, 7274, 7596, 7746, 8146, 8569, 8952, 44, 524, 939, 1258, 2222, 2641, 3510, 3865, 4454, 4746, 5086, 6096, 6371, 7275, 7597, 7747, 8147, 8570, 8953, 45, 525, 940, 1259, 2223, 2642, 3511, 3866, 4455, 4747, 5087, 6097, 6372, 7276, 7598, 7748, 8148, 8571, 8954, 46, 526, 941, 1260, 2224, 2643, 3512, 3867, 4456, 4748, 5088, 6098, 6373, 7277, 7599, 7749, 8149, 8572, 8955, 47, 527, 942, 1261, 2225, 2644, 3513, 3868, 4457, 4749, 5089, 6099, 6374, 7278, 7600, 7750, 8150, 8573, 8956, 48, 528, 943, 1262, 2226, 2645, 3514, 3869, 4458, 4750, 5090, 6100, 6375, 7279, 7601, 7751, 8151, 8574, 8957, 49, 529, 944, 1263, 2227, 2646, 3515, 3870, 4459, 4751, 5091, 6101, 6376, 7280, 7602, 7752, 8152, 8575, 8958, 50, 530, 945, 1264, 2228, 2647, 3516, 3871, 4460, 4752, 5092, 6102, 6377, 7281, 7603, 7753, 8153, 8576, 8959, 51, 531, 946, 1265, 2229, 2648, 3517, 3872, 4461, 4753, 5093, 6103, 6378, 7282, 7604, 7754, 8154, 8577, 8960, 52, 532, 947, 1266, 2230, 2649, 3518, 3873, 4462, 4754, 5094, 6104, 6379, 7283, 7605, 7755, 8155, 8578, 8961, 53, 533, 948, 1267, 2231, 2650, 3519, 3874, 4463, 4755, 5095, 6105, 6380, 7284, 7606, 7756, 8156, 8579, 8962, 54, 534, 949, 1268, 2232, 2651, 3520, 3875, 4464, 4756, 5096, 6106, 6381, 7285, 7607, 7757, 8157, 8580, 8963, 55, 535, 950, 1269, 2233, 2652, 3521, 3876, 4465, 4757, 5097, 6107, 6382, 7286, 7608, 7758, 8158, 8581, 8964, 56, 536, 951, 1270, 2234, 2653, 3522, 3877, 4466, 4758, 5098, 6108, 6383, 7287, 7609, 7759, 8159, 8582, 8965, 57, 537, 952, 1271, 2235, 2654, 3523, 3878, 4467, 4759, 5099, 6109, 6384, 7288, 7610, 7760, 8160, 8583, 8966, 58, 538, 953, 1272, 2236, 2655, 3524, 3879, 4468, 4760, 5100, 6110, 6385, 7289, 7611, 7761, 8161, 8584, 8967, 59, 539, 954, 1273, 2237, 2656, 3525, 3880, 4469, 4761, 5101, 6111, 6386, 7290, 7612, 7762, 8162, 8585, 8968, 60, 540, 955, 1274, 2238, 2657, 3526, 3881, 4470, 4762, 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6121, 6396, 6916, 7622, 7772, 8172, 8595, 8978, 70, 550, 965, 1284, 2248, 2667, 3536, 3891, 4480, 4772, 5112, 6122, 6397, 6917, 7623, 7773, 8173, 8596, 8979, 71, 551, 966, 1285, 2249, 2668, 3537, 3892, 4481, 4773, 5113, 6123, 6398, 6918, 7624, 7774, 8174, 8597, 8980, 72, 552, 967, 1286, 2250, 2669, 3538, 3893, 4482, 4774, 5114, 6124, 6399, 6919, 7625, 7775, 8175, 8598, 8981, 73, 553, 968, 1287, 2251, 2670, 3539, 3894, 4483, 4775, 5115, 6125, 6400, 6920, 7626, 7776, 8176, 8599, 8982, 74, 554, 969, 1288, 2252, 2671, 3540, 3895, 4484, 4776, 5116, 6126, 6401, 6921, 7627, 7777, 8177, 8600, 8983, 75, 555, 970, 1289, 2253, 2672, 3541, 3896, 4485, 4777, 5117, 6127, 6402, 6922, 7628, 7778, 8178, 8601, 8984, 76, 556, 971, 1290, 2254, 2673, 3542, 3897, 4486, 4778, 5118, 6128, 6403, 6923, 7629, 7779, 8179, 8602, 8985, 77, 557, 972, 1291, 2255, 2674, 3543, 3898, 4487, 4779, 5119, 6129, 6404, 6924, 7630, 7780, 8180, 8603, 8986, 78, 558, 973, 1292, 2256, 2675, 3544, 3899, 4488, 4780, 5120, 6130, 6405, 6925, 7631, 7781, 8181, 8604, 8987, 79, 559, 974, 1293, 2257, 2676, 3545, 3900, 4489, 4781, 5121, 6131, 6406, 6926, 7632, 7782, 8182, 8605, 8988, 80, 560, 975, 1294, 2258, 2677, 3546, 3901, 4490, 4782, 5122, 6132, 6407, 6927, 7633, 7783, 8183, 8606, 8989, 81, 561, 976, 1295, 2259, 2678, 3547, 3902, 4491, 4783, 5123, 6133, 6408, 6928, 7634, 7784, 8184, 8607, 8990, 82, 562, 977, 1296, 2260, 2679, 3548, 3903, 4492, 4784, 5124, 6134, 6409, 6929, 7635, 7785, 8185, 8608, 8991, 83, 563, 978, 1297, 2261, 2680, 3549, 3904, 4493, 4785, 5125, 6135, 6410, 6930, 7636, 7786, 8186, 8609, 8992, 84, 564, 979, 1298, 2262, 2681, 3550, 3905, 4494, 4786, 5126, 6136, 6411, 6931, 7637, 7787, 8187, 8610, 8993, 85, 565, 980, 1299, 2263, 2682, 3551, 3906, 4495, 4787, 5127, 6137, 6412, 6932, 7638, 7788, 8188, 8611, 8994, 86, 566, 981, 1300, 2264, 2683, 3552, 3907, 4496, 4788, 5128, 6138, 6413, 6933, 7639, 7789, 8189, 8612, 8995, 87, 567, 982, 1301, 2265, 2684, 3553, 3908, 4497, 4789, 5129, 6139, 6414, 6934, 7640, 7790, 8190, 8613, 8996, 88, 568, 983, 1302, 2266, 2685, 3554, 3909, 4498, 4790, 5130, 6140, 6415, 6935, 7641, 7791, 8191, 8614, 8997, 89, 569, 984, 1303, 2267, 2686, 3555, 3910, 4499, 4791, 5131, 6141, 6416, 6936, 7642, 7792, 8192, 8615, 8998, 90, 570, 985, 1304, 2268, 2687, 3556, 3911, 4500, 4792, 5132, 6142, 6417, 6937, 7643, 7793, 8193, 8616, 8999, 91, 571, 986, 1305, 2269, 2304, 3557, 3912, 4501, 4793, 5133, 6143, 6418, 6938, 7644, 7794, 8194, 8617, 9000, 92, 572, 987, 1306, 2270, 2305, 3558, 3913, 4502, 4794, 5134, 5760, 6419, 6939, 7645, 7795, 8195, 8618, 9001, 93, 573, 988, 1307, 2271, 2306, 3559, 3914, 4503, 4795, 5135, 5761, 6420, 6940, 7646, 7796, 8196, 8619, 9002, 94, 574, 989, 1308, 2272, 2307, 3560, 3915, 4504, 4796, 5136, 5762, 6421, 6941, 7647, 7797, 8197, 8620, 9003, 95, 575, 990, 1309, 2273, 2308, 3561, 3916, 4505, 4797, 5137, 5763, 6422, 6942, 7648, 7798, 8198, 8621, 9004, 96, 576, 991, 1310, 2274, 2309, 3562, 3917, 4506, 4798, 5138, 5764, 6423, 6943, 7649, 7799, 8199, 8622, 9005, 97, 577, 992, 1311, 2275, 2310, 3563, 3918, 4507, 4799, 5139, 5765, 6424, 6944, 7650, 7800, 8200, 8623, 9006, 98, 578, 993, 1312, 2276, 2311, 3564, 3919, 4508, 4800, 5140, 5766, 6425, 6945, 7651, 7801, 8201, 8624, 9007, 99, 579, 994, 1313, 2277, 2312, 3565, 3920, 4509, 4801, 5141, 5767, 6426, 6946, 7652, 7802, 8202, 8625, 9008, 100, 580, 995, 1314, 2278, 2313, 3566, 3921, 4510, 4802, 5142, 5768, 6427, 6947, 7653, 7803, 8203, 8626, 9009, 101, 581, 996, 1315, 2279, 2314, 3567, 3922, 4511, 4803, 5143, 5769, 6428, 6948, 7654, 7804, 8204, 8627, 9010, 102, 582, 997, 1316, 2280, 2315, 3568, 3923, 4512, 4804, 5144, 5770, 6429, 6949, 7655, 7805, 8205, 8628, 9011, 103, 583, 998, 1317, 2281, 2316, 3569, 3924, 4513, 4805, 5145, 5771, 6430, 6950, 7656, 7806, 8206, 8629, 9012, 104, 584, 999, 1318, 2282, 2317, 3570, 3925, 4514, 4806, 5146, 5772, 6431, 6951, 7657, 7807, 8207, 8630, 9013, 105, 585, 1000, 1319, 2283, 2318, 3571, 3926, 4515, 4807, 5147, 5773, 6432, 6952, 7658, 7808, 8208, 8631, 9014, 106, 586, 1001, 1320, 2284, 2319, 3572, 3927, 4516, 4808, 5148, 5774, 6433, 6953, 7659, 7809, 8209, 8632, 9015, 107, 587, 1002, 1321, 2285, 2320, 3573, 3928, 4517, 4809, 5149, 5775, 6434, 6954, 7660, 7810, 8210, 8633, 9016, 108, 588, 1003, 1322, 2286, 2321, 3574, 3929, 4518, 4810, 5150, 5776, 6435, 6955, 7661, 7811, 8211, 8634, 9017, 109, 589, 1004, 1323, 2287, 2322, 3575, 3930, 4519, 4811, 5151, 5777, 6436, 6956, 7662, 7812, 8212, 8635, 9018, 110, 590, 1005, 1324, 2288, 2323, 3576, 3931, 4520, 4812, 5152, 5778, 6437, 6957, 7663, 7813, 8213, 8636, 9019, 111, 591, 1006, 1325, 2289, 2324, 3577, 3932, 4521, 4813, 5153, 5779, 6438, 6958, 7664, 7814, 8214, 8637, 9020, 112, 592, 1007, 1326, 2290, 2325, 3578, 3933, 4522, 4814, 5154, 5780, 6439, 6959, 7665, 7815, 8215, 8638, 9021, 113, 593, 1008, 1327, 2291, 2326, 3579, 3934, 4523, 4815, 5155, 5781, 6440, 6960, 7666, 7816, 8216, 8639, 9022, 114, 594, 1009, 1328, 2292, 2327, 3580, 3935, 4524, 4816, 5156, 5782, 6441, 6961, 7667, 7817, 8217, 8640, 9023, 115, 595, 1010, 1329, 2293, 2328, 3581, 3936, 4525, 4817, 5157, 5783, 6442, 6962, 7668, 7818, 8218, 8641, 9024, 116, 596, 1011, 1330, 2294, 2329, 3582, 3937, 4526, 4818, 5158, 5784, 6443, 6963, 7669, 7819, 8219, 8642, 9025, 117, 597, 1012, 1331, 2295, 2330, 3583, 3938, 4527, 4819, 5159, 5785, 6444, 6964, 7670, 7820, 8220, 8643, 9026, 118, 598, 1013, 1332, 2296, 2331, 3584, 3939, 4528, 4820, 5160, 5786, 6445, 6965, 7671, 7821, 8221, 8644, 9027, 119, 599, 1014, 1333, 2297, 2332, 3585, 3940, 4529, 4821, 5161, 5787, 6446, 6966, 7672, 7822, 8222, 8645, 9028, 120, 600, 1015, 1334, 2298, 2333, 3586, 3941, 4530, 4822, 5162, 5788, 6447, 6967, 7673, 7823, 8223, 8646, 9029, 121, 601, 1016, 1335, 2299, 2334, 3587, 3942, 4531, 4823, 5163, 5789, 6448, 6968, 7674, 7824, 8224, 8647, 9030, 122, 602, 1017, 1336, 2300, 2335, 3588, 3943, 4532, 4824, 5164, 5790, 6449, 6969, 7675, 7825, 8225, 8648, 9031, 123, 603, 1018, 1337, 2301, 2336, 3589, 3944, 4533, 4825, 5165, 5791, 6450, 6970, 7676, 7826, 8226, 8649, 9032, 124, 604, 1019, 1338, 2302, 2337, 3590, 3945, 4534, 4826, 5166, 5792, 6451, 6971, 7677, 7827, 8227, 8650, 9033, 125, 605, 1020, 1339, 2303, 2338, 3591, 3946, 4535, 4827, 5167, 5793, 6452, 6972, 7678, 7828, 8228, 8651, 9034, 126, 606, 1021, 1340, 1920, 2339, 3592, 3947, 4536, 4828, 5168, 5794, 6453, 6973, 7679, 7829, 8229, 8652, 9035, 127, 607, 1022, 1341, 1921, 2340, 3593, 3948, 4537, 4829, 5169, 5795, 6454, 6974, 7296, 7830, 8230, 8653, 9036, 128, 608, 1023, 1342, 1922, 2341, 3594, 3949, 4538, 4830, 5170, 5796, 6455, 6975, 7297, 7831, 8231, 8654, 9037, 129, 609, 1024, 1343, 1923, 2342, 3595, 3950, 4539, 4831, 5171, 5797, 6456, 6976, 7298, 7832, 8232, 8655, 9038, 130, 610, 1025, 1344, 1924, 2343, 3596, 3951, 4540, 4832, 5172, 5798, 6457, 6977, 7299, 7833, 8233, 8656, 9039, 131, 611, 1026, 1345, 1925, 2344, 3597, 3952, 4541, 4833, 5173, 5799, 6458, 6978, 7300, 7834, 8234, 8657, 9040, 132, 612, 1027, 1346, 1926, 2345, 3598, 3953, 4542, 4834, 5174, 5800, 6459, 6979, 7301, 7835, 8235, 8658, 9041, 133, 613, 1028, 1347, 1927, 2346, 3599, 3954, 4543, 4835, 5175, 5801, 6460, 6980, 7302, 7836, 8236, 8659, 9042, 134, 614, 1029, 1348, 1928, 2347, 3600, 3955, 4544, 4836, 5176, 5802, 6461, 6981, 7303, 7837, 8237, 8660, 9043, 135, 615, 1030, 1349, 1929, 2348, 3601, 3956, 4545, 4837, 5177, 5803, 6462, 6982, 7304, 7838, 8238, 8661, 9044, 136, 616, 1031, 1350, 1930, 2349, 3602, 3957, 4546, 4838, 5178, 5804, 6463, 6983, 7305, 7839, 8239, 8662, 9045, 137, 617, 1032, 1351, 1931, 2350, 3603, 3958, 4547, 4839, 5179, 5805, 6464, 6984, 7306, 7840, 8240, 8663, 9046, 138, 618, 1033, 1352, 1932, 2351, 3604, 3959, 4548, 4840, 5180, 5806, 6465, 6985, 7307, 7841, 8241, 8664, 9047, 139, 619, 1034, 1353, 1933, 2352, 3605, 3960, 4549, 4841, 5181, 5807, 6466, 6986, 7308, 7842, 8242, 8665, 9048, 140, 620, 1035, 1354, 1934, 2353, 3606, 3961, 4550, 4842, 5182, 5808, 6467, 6987, 7309, 7843, 8243, 8666, 9049, 141, 621, 1036, 1355, 1935, 2354, 3607, 3962, 4551, 4843, 5183, 5809, 6468, 6988, 7310, 7844, 8244, 8667, 9050, 142, 622, 1037, 1356, 1936, 2355, 3608, 3963, 4552, 4844, 5184, 5810, 6469, 6989, 7311, 7845, 8245, 8668, 9051, 143, 623, 1038, 1357, 1937, 2356, 3609, 3964, 4553, 4845, 5185, 5811, 6470, 6990, 7312, 7846, 8246, 8669, 9052, 144, 624, 1039, 1358, 1938, 2357, 3610, 3965, 4554, 4846, 5186, 5812, 6471, 6991, 7313, 7847, 8247, 8670, 9053, 145, 625, 1040, 1359, 1939, 2358, 3611, 3966, 4555, 4847, 5187, 5813, 6472, 6992, 7314, 7848, 8248, 8671, 9054, 146, 626, 1041, 1360, 1940, 2359, 3612, 3967, 4556, 4848, 5188, 5814, 6473, 6993, 7315, 7849, 8249, 8672, 9055, 147, 627, 1042, 1361, 1941, 2360, 3613, 3968, 4557, 4849, 5189, 5815, 6474, 6994, 7316, 7850, 8250, 8673, 9056, 148, 628, 1043, 1362, 1942, 2361, 3614, 3969, 4558, 4850, 5190, 5816, 6475, 6995, 7317, 7851, 8251, 8674, 9057, 149, 629, 1044, 1363, 1943, 2362, 3615, 3970, 4559, 4851, 5191, 5817, 6476, 6996, 7318, 7852, 8252, 8675, 9058, 150, 630, 1045, 1364, 1944, 2363, 3616, 3971, 4560, 4852, 5192, 5818, 6477, 6997, 7319, 7853, 8253, 8676, 9059, 151, 631, 1046, 1365, 1945, 2364, 3617, 3972, 4561, 4853, 5193, 5819, 6478, 6998, 7320, 7854, 8254, 8677, 9060, 152, 632, 1047, 1366, 1946, 2365, 3618, 3973, 4562, 4854, 5194, 5820, 6479, 6999, 7321, 7855, 8255, 8678, 9061, 153, 633, 1048, 1367, 1947, 2366, 3619, 3974, 4563, 4855, 5195, 5821, 6480, 7000, 7322, 7856, 8256, 8679, 9062, 154, 634, 1049, 1368, 1948, 2367, 3620, 3975, 4564, 4856, 5196, 5822, 6481, 7001, 7323, 7857, 8257, 8680, 9063, 155, 635, 1050, 1369, 1949, 2368, 3621, 3976, 4565, 4857, 5197, 5823, 6482, 7002, 7324, 7858, 8258, 8681, 9064, 156, 636, 1051, 1370, 1950, 2369, 3622, 3977, 4566, 4858, 5198, 5824, 6483, 7003, 7325, 7859, 8259, 8682, 9065, 157, 637, 1052, 1371, 1951, 2370, 3623, 3978, 4567, 4859, 5199, 5825, 6484, 7004, 7326, 7860, 8260, 8683, 9066, 158, 638, 1053, 1372, 1952, 2371, 3624, 3979, 4568, 4860, 5200, 5826, 6485, 7005, 7327, 7861, 8261, 8684, 9067, 159, 639, 1054, 1373, 1953, 2372, 3625, 3980, 4569, 4861, 5201, 5827, 6486, 7006, 7328, 7862, 8262, 8685, 9068, 160, 640, 1055, 1374, 1954, 2373, 3626, 3981, 4570, 4862, 5202, 5828, 6487, 7007, 7329, 7863, 8263, 8686, 9069, 161, 641, 1056, 1375, 1955, 2374, 3627, 3982, 4571, 4863, 5203, 5829, 6488, 7008, 7330, 7864, 8264, 8687, 9070, 162, 642, 1057, 1376, 1956, 2375, 3628, 3983, 4572, 4864, 5204, 5830, 6489, 7009, 7331, 7865, 8265, 8688, 9071, 163, 643, 1058, 1377, 1957, 2376, 3629, 3984, 4573, 4865, 5205, 5831, 6490, 7010, 7332, 7866, 8266, 8689, 9072, 164, 644, 1059, 1378, 1958, 2377, 3630, 3985, 4574, 4866, 5206, 5832, 6491, 7011, 7333, 7867, 8267, 8690, 9073, 165, 645, 1060, 1379, 1959, 2378, 3631, 3986, 4575, 4867, 5207, 5833, 6492, 7012, 7334, 7868, 8268, 8691, 9074, 166, 646, 1061, 1380, 1960, 2379, 3632, 3987, 4576, 4868, 5208, 5834, 6493, 7013, 7335, 7869, 8269, 8692, 9075, 167, 647, 1062, 1381, 1961, 2380, 3633, 3988, 4577, 4869, 5209, 5835, 6494, 7014, 7336, 7870, 8270, 8693, 9076, 168, 648, 1063, 1382, 1962, 2381, 3634, 3989, 4578, 4870, 5210, 5836, 6495, 7015, 7337, 7871, 8271, 8694, 9077, 169, 649, 1064, 1383, 1963, 2382, 3635, 3990, 4579, 4871, 5211, 5837, 6496, 7016, 7338, 7872, 8272, 8695, 9078, 170, 650, 1065, 1384, 1964, 2383, 3636, 3991, 4580, 4872, 5212, 5838, 6497, 7017, 7339, 7873, 8273, 8696, 9079, 171, 651, 1066, 1385, 1965, 2384, 3637, 3992, 4581, 4873, 5213, 5839, 6498, 7018, 7340, 7874, 8274, 8697, 9080, 172, 652, 1067, 1386, 1966, 2385, 3638, 3993, 4582, 4874, 5214, 5840, 6499, 7019, 7341, 7875, 8275, 8698, 9081, 173, 653, 1068, 1387, 1967, 2386, 3639, 3994, 4583, 4875, 5215, 5841, 6500, 7020, 7342, 7876, 8276, 8699, 9082, 174, 654, 1069, 1388, 1968, 2387, 3640, 3995, 4584, 4876, 5216, 5842, 6501, 7021, 7343, 7877, 8277, 8700, 9083, 175, 655, 1070, 1389, 1969, 2388, 3641, 3996, 4585, 4877, 5217, 5843, 6502, 7022, 7344, 7878, 8278, 8701, 9084, 176, 656, 1071, 1390, 1970, 2389, 3642, 3997, 4586, 4878, 5218, 5844, 6503, 7023, 7345, 7879, 8279, 8702, 9085, 177, 657, 1072, 1391, 1971, 2390, 3643, 3998, 4587, 4879, 5219, 5845, 6504, 7024, 7346, 7880, 8280, 8703, 9086, 178, 658, 1073, 1392, 1972, 2391, 3644, 3999, 4588, 4880, 5220, 5846, 6505, 7025, 7347, 7881, 8281, 8704, 9087, 179, 659, 1074, 1393, 1973, 2392, 3645, 4000, 4589, 4881, 5221, 5847, 6506, 7026, 7348, 7882, 8282, 8705, 9088, 180, 660, 1075, 1394, 1974, 2393, 3646, 4001, 4590, 4882, 5222, 5848, 6507, 7027, 7349, 7883, 8283, 8706, 9089, 181, 661, 1076, 1395, 1975, 2394, 3647, 4002, 4591, 4883, 5223, 5849, 6508, 7028, 7350, 7884, 8284, 8707, 9090, 182, 662, 1077, 1396, 1976, 2395, 3648, 4003, 4592, 4884, 5224, 5850, 6509, 7029, 7351, 7885, 8285, 8708, 9091, 183, 663, 1078, 1397, 1977, 2396, 3649, 4004, 4593, 4885, 5225, 5851, 6510, 7030, 7352, 7886, 8286, 8709, 9092, 184, 664, 1079, 1398, 1978, 2397, 3650, 4005, 4594, 4886, 5226, 5852, 6511, 7031, 7353, 7887, 8287, 8710, 9093, 185, 665, 1080, 1399, 1979, 2398, 3651, 4006, 4595, 4887, 5227, 5853, 6512, 7032, 7354, 7888, 8288, 8711, 9094, 186, 666, 1081, 1400, 1980, 2399, 3652, 4007, 4596, 4888, 5228, 5854, 6513, 7033, 7355, 7889, 8289, 8712, 9095, 187, 667, 1082, 1401, 1981, 2400, 3653, 4008, 4597, 4889, 5229, 5855, 6514, 7034, 7356, 7890, 8290, 8713, 9096, 188, 668, 1083, 1402, 1982, 2401, 3654, 4009, 4598, 4890, 5230, 5856, 6515, 7035, 7357, 7891, 8291, 8714, 9097, 189, 669, 1084, 1403, 1983, 2402, 3655, 4010, 4599, 4891, 5231, 5857, 6516, 7036, 7358, 7892, 8292, 8715, 9098, 190, 670, 1085, 1404, 1984, 2403, 3656, 4011, 4600, 4892, 5232, 5858, 6517, 7037, 7359, 7893, 8293, 8716, 9099, 191, 671, 1086, 1405, 1985, 2404, 3657, 4012, 4601, 4893, 5233, 5859, 6518, 7038, 7360, 7894, 8294, 8717, 9100, 192, 672, 1087, 1406, 1986, 2405, 3658, 4013, 4602, 4894, 5234, 5860, 6519, 7039, 7361, 7895, 8295, 8718, 9101, 193, 673, 1088, 1407, 1987, 2406, 3659, 4014, 4603, 4895, 5235, 5861, 6520, 7040, 7362, 7896, 8296, 8719, 9102, 194, 674, 1089, 1408, 1988, 2407, 3660, 4015, 4604, 4896, 5236, 5862, 6521, 7041, 7363, 7897, 8297, 8720, 9103, 195, 675, 1090, 1409, 1989, 2408, 3661, 4016, 4605, 4897, 5237, 5863, 6522, 7042, 7364, 7898, 8298, 8721, 9104, 196, 676, 1091, 1410, 1990, 2409, 3662, 4017, 4606, 4898, 5238, 5864, 6523, 7043, 7365, 7899, 8299, 8722, 9105, 197, 677, 1092, 1411, 1991, 2410, 3663, 4018, 4607, 4899, 5239, 5865, 6524, 7044, 7366, 7900, 8300, 8723, 9106, 198, 678, 1093, 1412, 1992, 2411, 3664, 4019, 4224, 4900, 5240, 5866, 6525, 7045, 7367, 7901, 8301, 8724, 9107, 199, 679, 1094, 1413, 1993, 2412, 3665, 4020, 4225, 4901, 5241, 5867, 6526, 7046, 7368, 7902, 8302, 8725, 9108, 200, 680, 1095, 1414, 1994, 2413, 3666, 4021, 4226, 4902, 5242, 5868, 6527, 7047, 7369, 7903, 8303, 8726, 9109, 201, 681, 1096, 1415, 1995, 2414, 3667, 4022, 4227, 4903, 5243, 5869, 6144, 7048, 7370, 7904, 8304, 8727, 9110, 202, 682, 1097, 1416, 1996, 2415, 3668, 4023, 4228, 4904, 5244, 5870, 6145, 7049, 7371, 7905, 8305, 8728, 9111, 203, 683, 1098, 1417, 1997, 2416, 3669, 4024, 4229, 4905, 5245, 5871, 6146, 7050, 7372, 7906, 8306, 8729, 9112, 204, 684, 1099, 1418, 1998, 2417, 3670, 4025, 4230, 4906, 5246, 5872, 6147, 7051, 7373, 7907, 8307, 8730, 9113, 205, 685, 1100, 1419, 1999, 2418, 3671, 4026, 4231, 4907, 5247, 5873, 6148, 7052, 7374, 7908, 8308, 8731, 9114, 206, 686, 1101, 1420, 2000, 2419, 3672, 4027, 4232, 4908, 5248, 5874, 6149, 7053, 7375, 7909, 8309, 8732, 9115, 207, 687, 1102, 1421, 2001, 2420, 3673, 4028, 4233, 4909, 5249, 5875, 6150, 7054, 7376, 7910, 8310, 8733, 9116, 208, 688, 1103, 1422, 2002, 2421, 3674, 4029, 4234, 4910, 5250, 5876, 6151, 7055, 7377, 7911, 8311, 8734, 9117, 209, 689, 1104, 1423, 2003, 2422, 3675, 4030, 4235, 4911, 5251, 5877, 6152, 7056, 7378, 7912, 8312, 8735, 9118, 210, 690, 1105, 1424, 2004, 2423, 3676, 4031, 4236, 4912, 5252, 5878, 6153, 7057, 7379, 7913, 8313, 8736, 9119, 211, 691, 1106, 1425, 2005, 2424, 3677, 4032, 4237, 4913, 5253, 5879, 6154, 7058, 7380, 7914, 8314, 8737, 9120, 212, 692, 1107, 1426, 2006, 2425, 3678, 4033, 4238, 4914, 5254, 5880, 6155, 7059, 7381, 7915, 8315, 8738, 9121, 213, 693, 1108, 1427, 2007, 2426, 3679, 4034, 4239, 4915, 5255, 5881, 6156, 7060, 7382, 7916, 8316, 8739, 9122, 214, 694, 1109, 1428, 2008, 2427, 3680, 4035, 4240, 4916, 5256, 5882, 6157, 7061, 7383, 7917, 8317, 8740, 9123, 215, 695, 1110, 1429, 2009, 2428, 3681, 4036, 4241, 4917, 5257, 5883, 6158, 7062, 7384, 7918, 8318, 8741, 9124, 216, 696, 1111, 1430, 2010, 2429, 3682, 4037, 4242, 4918, 5258, 5884, 6159, 7063, 7385, 7919, 8319, 8742, 9125, 217, 697, 1112, 1431, 2011, 2430, 3683, 4038, 4243, 4919, 5259, 5885, 6160, 7064, 7386, 7920, 8320, 8743, 9126, 218, 698, 1113, 1432, 2012, 2431, 3684, 4039, 4244, 4920, 5260, 5886, 6161, 7065, 7387, 7921, 8321, 8744, 9127, 219, 699, 1114, 1433, 2013, 2432, 3685, 4040, 4245, 4921, 5261, 5887, 6162, 7066, 7388, 7922, 8322, 8745, 9128, 220, 700, 1115, 1434, 2014, 2433, 3686, 4041, 4246, 4922, 5262, 5888, 6163, 7067, 7389, 7923, 8323, 8746, 9129, 221, 701, 1116, 1435, 2015, 2434, 3687, 4042, 4247, 4923, 5263, 5889, 6164, 7068, 7390, 7924, 8324, 8747, 9130, 222, 702, 1117, 1436, 2016, 2435, 3688, 4043, 4248, 4924, 5264, 5890, 6165, 7069, 7391, 7925, 8325, 8748, 9131, 223, 703, 1118, 1437, 2017, 2436, 3689, 4044, 4249, 4925, 5265, 5891, 6166, 7070, 7392, 7926, 8326, 8749, 9132, 224, 704, 1119, 1438, 2018, 2437, 3690, 4045, 4250, 4926, 5266, 5892, 6167, 7071, 7393, 7927, 8327, 8750, 9133, 225, 705, 1120, 1439, 2019, 2438, 3691, 4046, 4251, 4927, 5267, 5893, 6168, 7072, 7394, 7928, 8328, 8751, 9134, 226, 706, 1121, 1440, 2020, 2439, 3692, 4047, 4252, 4928, 5268, 5894, 6169, 7073, 7395, 7929, 8329, 8752, 9135, 227, 707, 1122, 1441, 2021, 2440, 3693, 4048, 4253, 4929, 5269, 5895, 6170, 7074, 7396, 7930, 8330, 8753, 9136, 228, 708, 1123, 1442, 2022, 2441, 3694, 4049, 4254, 4930, 5270, 5896, 6171, 7075, 7397, 7931, 8331, 8754, 9137, 229, 709, 1124, 1443, 2023, 2442, 3695, 4050, 4255, 4931, 5271, 5897, 6172, 7076, 7398, 7932, 8332, 8755, 9138, 230, 710, 1125, 1444, 2024, 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311, 1079, 1460, 1675, 2299, 2870, 3254, 3485, 4370, 4801, 5444, 6094, 6349, 6877, 7478, 8411, 8683, 9067, 9451, 312, 1080, 1461, 1676, 2300, 2871, 3255, 3486, 4371, 4802, 5445, 6095, 6350, 6878, 7479, 8412, 8684, 9068, 9452, 313, 1081, 1462, 1677, 2301, 2872, 3256, 3487, 4372, 4803, 5446, 6096, 6351, 6879, 7480, 8413, 8685, 9069, 9453, 314, 1082, 1463, 1678, 2302, 2873, 3257, 3488, 4373, 4804, 5447, 6097, 6352, 6880, 7481, 8414, 8686, 9070, 9454, 315, 1083, 1464, 1679, 2303, 2874, 3258, 3489, 4374, 4805, 5448, 6098, 6353, 6881, 7482, 8415, 8687, 9071, 9455, 316, 1084, 1465, 1680, 1920, 2875, 3259, 3490, 4375, 4806, 5449, 6099, 6354, 6882, 7483, 8416, 8688, 9072, 9456, 317, 1085, 1466, 1681, 1921, 2876, 3260, 3491, 4376, 4807, 5450, 6100, 6355, 6883, 7484, 8417, 8689, 9073, 9457, 318, 1086, 1467, 1682, 1922, 2877, 3261, 3492, 4377, 4808, 5451, 6101, 6356, 6884, 7485, 8418, 8690, 9074, 9458, 319, 1087, 1468, 1683, 1923, 2878, 3262, 3493, 4378, 4809, 5452, 6102, 6357, 6885, 7486, 8419, 8691, 9075, 9459, 320, 1088, 1469, 1684, 1924, 2879, 3263, 3494, 4379, 4810, 5453, 6103, 6358, 6886, 7487, 8420, 8692, 9076, 9460, 321, 1089, 1470, 1685, 1925, 2880, 3264, 3495, 4380, 4811, 5454, 6104, 6359, 6887, 7488, 8421, 8693, 9077, 9461, 322, 1090, 1471, 1686, 1926, 2881, 3265, 3496, 4381, 4812, 5455, 6105, 6360, 6888, 7489, 8422, 8694, 9078, 9462, 323, 1091, 1472, 1687, 1927, 2882, 3266, 3497, 4382, 4813, 5456, 6106, 6361, 6889, 7490, 8423, 8695, 9079, 9463, 324, 1092, 1473, 1688, 1928, 2883, 3267, 3498, 4383, 4814, 5457, 6107, 6362, 6890, 7491, 8424, 8696, 9080, 9464, 325, 1093, 1474, 1689, 1929, 2884, 3268, 3499, 4384, 4815, 5458, 6108, 6363, 6891, 7492, 8425, 8697, 9081, 9465, 326, 1094, 1475, 1690, 1930, 2885, 3269, 3500, 4385, 4816, 5459, 6109, 6364, 6892, 7493, 8426, 8698, 9082, 9466, 327, 1095, 1476, 1691, 1931, 2886, 3270, 3501, 4386, 4817, 5460, 6110, 6365, 6893, 7494, 8427, 8699, 9083, 9467, 328, 1096, 1477, 1692, 1932, 2887, 3271, 3502, 4387, 4818, 5461, 6111, 6366, 6894, 7495, 8428, 8700, 9084, 9468, 329, 1097, 1478, 1693, 1933, 2888, 3272, 3503, 4388, 4819, 5462, 6112, 6367, 6895, 7496, 8429, 8701, 9085, 9469, 330, 1098, 1479, 1694, 1934, 2889, 3273, 3504, 4389, 4820, 5463, 6113, 6368, 6896, 7497, 8430, 8702, 9086, 9470, 331, 1099, 1480, 1695, 1935, 2890, 3274, 3505, 4390, 4821, 5464, 6114, 6369, 6897, 7498, 8431, 8703, 9087, 9471, 332, 1100, 1481, 1696, 1936, 2891, 3275, 3506, 4391, 4822, 5465, 6115, 6370, 6898, 7499, 8432, 8704, 9088, 9472, 333, 1101, 1482, 1697, 1937, 2892, 3276, 3507, 4392, 4823, 5466, 6116, 6371, 6899, 7500, 8433, 8705, 9089, 9473, 334, 1102, 1483, 1698, 1938, 2893, 3277, 3508, 4393, 4824, 5467, 6117, 6372, 6900, 7501, 8434, 8706, 9090, 9474, 335, 1103, 1484, 1699, 1939, 2894, 3278, 3509, 4394, 4825, 5468, 6118, 6373, 6901, 7502, 8435, 8707, 9091, 9475, 336, 1104, 1485, 1700, 1940, 2895, 3279, 3510, 4395, 4826, 5469, 6119, 6374, 6902, 7503, 8436, 8708, 9092, 9476, 337, 1105, 1486, 1701, 1941, 2896, 3280, 3511, 4396, 4827, 5470, 6120, 6375, 6903, 7504, 8437, 8709, 9093, 9477, 338, 1106, 1487, 1702, 1942, 2897, 3281, 3512, 4397, 4828, 5471, 6121, 6376, 6904, 7505, 8438, 8710, 9094, 9478, 339, 1107, 1488, 1703, 1943, 2898, 3282, 3513, 4398, 4829, 5472, 6122, 6377, 6905, 7506, 8439, 8711, 9095, 9479, 340, 1108, 1489, 1704, 1944, 2899, 3283, 3514, 4399, 4830, 5473, 6123, 6378, 6906, 7507, 8440, 8712, 9096, 9480, 341, 1109, 1490, 1705, 1945, 2900, 3284, 3515, 4400, 4831, 5474, 6124, 6379, 6907, 7508, 8441, 8713, 9097, 9481, 342, 1110, 1491, 1706, 1946, 2901, 3285, 3516, 4401, 4832, 5475, 6125, 6380, 6908, 7509, 8442, 8714, 9098, 9482, 343, 1111, 1492, 1707, 1947, 2902, 3286, 3517, 4402, 4833, 5476, 6126, 6381, 6909, 7510, 8443, 8715, 9099, 9483, 344, 1112, 1493, 1708, 1948, 2903, 3287, 3518, 4403, 4834, 5477, 6127, 6382, 6910, 7511, 8444, 8716, 9100, 9484, 345, 1113, 1494, 1709, 1949, 2904, 3288, 3519, 4404, 4835, 5478, 6128, 6383, 6911, 7512, 8445, 8717, 9101, 9485, 346, 1114, 1495, 1710, 1950, 2905, 3289, 3520, 4405, 4836, 5479, 6129, 6384, 6528, 7513, 8446, 8718, 9102, 9486, 347, 1115, 1496, 1711, 1951, 2906, 3290, 3521, 4406, 4837, 5480, 6130, 6385, 6529, 7514, 8447, 8719, 9103, 9487, 348, 1116, 1497, 1712, 1952, 2907, 3291, 3522, 4407, 4838, 5481, 6131, 6386, 6530, 7515, 8064, 8720, 9104, 9488, 349, 1117, 1498, 1713, 1953, 2908, 3292, 3523, 4408, 4839, 5482, 6132, 6387, 6531, 7516, 8065, 8721, 9105, 9489, 350, 1118, 1499, 1714, 1954, 2909, 3293, 3524, 4409, 4840, 5483, 6133, 6388, 6532, 7517, 8066, 8722, 9106, 9490, 351, 1119, 1500, 1715, 1955, 2910, 3294, 3525, 4410, 4841, 5484, 6134, 6389, 6533, 7518, 8067, 8723, 9107, 9491, 352, 1120, 1501, 1716, 1956, 2911, 3295, 3526, 4411, 4842, 5485, 6135, 6390, 6534, 7519, 8068, 8724, 9108, 9492, 353, 1121, 1502, 1717, 1957, 2912, 3296, 3527, 4412, 4843, 5486, 6136, 6391, 6535, 7520, 8069, 8725, 9109, 9493, 354, 1122, 1503, 1718, 1958, 2913, 3297, 3528, 4413, 4844, 5487, 6137, 6392, 6536, 7521, 8070, 8726, 9110, 9494, 355, 1123, 1504, 1719, 1959, 2914, 3298, 3529, 4414, 4845, 5488, 6138, 6393, 6537, 7522, 8071, 8727, 9111, 9495, 356, 1124, 1505, 1720, 1960, 2915, 3299, 3530, 4415, 4846, 5489, 6139, 6394, 6538, 7523, 8072, 8728, 9112, 9496, 357, 1125, 1506, 1721, 1961, 2916, 3300, 3531, 4416, 4847, 5490, 6140, 6395, 6539, 7524, 8073, 8729, 9113, 9497, 358, 1126, 1507, 1722, 1962, 2917, 3301, 3532, 4417, 4848, 5491, 6141, 6396, 6540, 7525, 8074, 8730, 9114, 9498, 359, 1127, 1508, 1723, 1963, 2918, 3302, 3533, 4418, 4849, 5492, 6142, 6397, 6541, 7526, 8075, 8731, 9115, 9499, 360, 1128, 1509, 1724, 1964, 2919, 3303, 3534, 4419, 4850, 5493, 6143, 6398, 6542, 7527, 8076, 8732, 9116, 9500, 361, 1129, 1510, 1725, 1965, 2920, 3304, 3535, 4420, 4851, 5494, 5760, 6399, 6543, 7528, 8077, 8733, 9117, 9501, 362, 1130, 1511, 1726, 1966, 2921, 3305, 3536, 4421, 4852, 5495, 5761, 6400, 6544, 7529, 8078, 8734, 9118, 9502, 363, 1131, 1512, 1727, 1967, 2922, 3306, 3537, 4422, 4853, 5496, 5762, 6401, 6545, 7530, 8079, 8735, 9119, 9503, 364, 1132, 1513, 1728, 1968, 2923, 3307, 3538, 4423, 4854, 5497, 5763, 6402, 6546, 7531, 8080, 8736, 9120, 9504, 365, 1133, 1514, 1729, 1969, 2924, 3308, 3539, 4424, 4855, 5498, 5764, 6403, 6547, 7532, 8081, 8737, 9121, 9505, 366, 1134, 1515, 1730, 1970, 2925, 3309, 3540, 4425, 4856, 5499, 5765, 6404, 6548, 7533, 8082, 8738, 9122, 9506, 367, 1135, 1516, 1731, 1971, 2926, 3310, 3541, 4426, 4857, 5500, 5766, 6405, 6549, 7534, 8083, 8739, 9123, 9507, 368, 1136, 1517, 1732, 1972, 2927, 3311, 3542, 4427, 4858, 5501, 5767, 6406, 6550, 7535, 8084, 8740, 9124, 9508, 369, 1137, 1518, 1733, 1973, 2928, 3312, 3543, 4428, 4859, 5502, 5768, 6407, 6551, 7536, 8085, 8741, 9125, 9509, 370, 1138, 1519, 1734, 1974, 2929, 3313, 3544, 4429, 4860, 5503, 5769, 6408, 6552, 7537, 8086, 8742, 9126, 9510, 371, 1139, 1520, 1735, 1975, 2930, 3314, 3545, 4430, 4861, 5504, 5770, 6409, 6553, 7538, 8087, 8743, 9127, 9511, 372, 1140, 1521, 1736, 1976, 2931, 3315, 3546, 4431, 4862, 5505, 5771, 6410, 6554, 7539, 8088, 8744, 9128, 9512, 373, 1141, 1522, 1737, 1977, 2932, 3316, 3547, 4432, 4863, 5506, 5772, 6411, 6555, 7540, 8089, 8745, 9129, 9513, 374, 1142, 1523, 1738, 1978, 2933, 3317, 3548, 4433, 4864, 5507, 5773, 6412, 6556, 7541, 8090, 8746, 9130, 9514, 375, 1143, 1524, 1739, 1979, 2934, 3318, 3549, 4434, 4865, 5508, 5774, 6413, 6557, 7542, 8091, 8747, 9131, 9515, 376, 1144, 1525, 1740, 1980, 2935, 3319, 3550, 4435, 4866, 5509, 5775, 6414, 6558, 7543, 8092, 8748, 9132, 9516, 377, 1145, 1526, 1741, 1981, 2936, 3320, 3551, 4436, 4867, 5510, 5776, 6415, 6559, 7544, 8093, 8749, 9133, 9517, 378, 1146, 1527, 1742, 1982, 2937, 3321, 3552, 4437, 4868, 5511, 5777, 6416, 6560, 7545, 8094, 8750, 9134, 9518, 379, 1147, 1528, 1743, 1983, 2938, 3322, 3553, 4438, 4869, 5512, 5778, 6417, 6561, 7546, 8095, 8751, 9135, 9519, 380, 1148, 1529, 1744, 1984, 2939, 3323, 3554, 4439, 4870, 5513, 5779, 6418, 6562, 7547, 8096, 8752, 9136, 9520, 381, 1149, 1530, 1745, 1985, 2940, 3324, 3555, 4440, 4871, 5514, 5780, 6419, 6563, 7548, 8097, 8753, 9137, 9521, 382, 1150, 1531, 1746, 1986, 2941, 3325, 3556, 4441, 4872, 5515, 5781, 6420, 6564, 7549, 8098, 8754, 9138, 9522, 383, 1151, 1532, 1747, 1987, 2942, 3326, 3557, 4442, 4873, 5516, 5782, 6421, 6565, 7550, 8099, 8755, 9139, 9523, 0, 768, 1533, 1748, 1988, 2943, 3327, 3558, 4443, 4874, 5517, 5783, 6422, 6566, 7551, 8100, 8756, 9140, 9524, 1, 769, 1534, 1749, 1989, 2944, 3328, 3559, 4444, 4875, 5518, 5784, 6423, 6567, 7552, 8101, 8757, 9141, 9525, 2, 770, 1535, 1750, 1990, 2945, 3329, 3560, 4445, 4876, 5519, 5785, 6424, 6568, 7553, 8102, 8758, 9142, 9526, 3, 771, 1152, 1751, 1991, 2946, 3330, 3561, 4446, 4877, 5520, 5786, 6425, 6569, 7554, 8103, 8759, 9143, 9527, 4, 772, 1153, 1752, 1992, 2947, 3331, 3562, 4447, 4878, 5521, 5787, 6426, 6570, 7555, 8104, 8760, 9144, 9528, 5, 773, 1154, 1753, 1993, 2948, 3332, 3563, 4448, 4879, 5522, 5788, 6427, 6571, 7556, 8105, 8761, 9145, 9529, 6, 774, 1155, 1754, 1994, 2949, 3333, 3564, 4449, 4880, 5523, 5789, 6428, 6572, 7557, 8106, 8762, 9146, 9530, 7, 775, 1156, 1755, 1995, 2950, 3334, 3565, 4450, 4881, 5524, 5790, 6429, 6573, 7558, 8107, 8763, 9147, 9531, 8, 776, 1157, 1756, 1996, 2951, 3335, 3566, 4451, 4882, 5525, 5791, 6430, 6574, 7559, 8108, 8764, 9148, 9532, 9, 777, 1158, 1757, 1997, 2952, 3336, 3567, 4452, 4883, 5526, 5792, 6431, 6575, 7560, 8109, 8765, 9149, 9533, 10, 778, 1159, 1758, 1998, 2953, 3337, 3568, 4453, 4884, 5527, 5793, 6432, 6576, 7561, 8110, 8766, 9150, 9534, 11, 779, 1160, 1759, 1999, 2954, 3338, 3569, 4454, 4885, 5528, 5794, 6433, 6577, 7562, 8111, 8767, 9151, 9535, 12, 780, 1161, 1760, 2000, 2955, 3339, 3570, 4455, 4886, 5529, 5795, 6434, 6578, 7563, 8112, 8768, 9152, 9536, 13, 781, 1162, 1761, 2001, 2956, 3340, 3571, 4456, 4887, 5530, 5796, 6435, 6579, 7564, 8113, 8769, 9153, 9537, 14, 782, 1163, 1762, 2002, 2957, 3341, 3572, 4457, 4888, 5531, 5797, 6436, 6580, 7565, 8114, 8770, 9154, 9538, 15, 783, 1164, 1763, 2003, 2958, 3342, 3573, 4458, 4889, 5532, 5798, 6437, 6581, 7566, 8115, 8771, 9155, 9539, 16, 784, 1165, 1764, 2004, 2959, 3343, 3574, 4459, 4890, 5533, 5799, 6438, 6582, 7567, 8116, 8772, 9156, 9540, 17, 785, 1166, 1765, 2005, 2960, 3344, 3575, 4460, 4891, 5534, 5800, 6439, 6583, 7568, 8117, 8773, 9157, 9541, 18, 786, 1167, 1766, 2006, 2961, 3345, 3576, 4461, 4892, 5535, 5801, 6440, 6584, 7569, 8118, 8774, 9158, 9542, 19, 787, 1168, 1767, 2007, 2962, 3346, 3577, 4462, 4893, 5536, 5802, 6441, 6585, 7570, 8119, 8775, 9159, 9543, 20, 788, 1169, 1768, 2008, 2963, 3347, 3578, 4463, 4894, 5537, 5803, 6442, 6586, 7571, 8120, 8776, 9160, 9544, 21, 789, 1170, 1769, 2009, 2964, 3348, 3579, 4464, 4895, 5538, 5804, 6443, 6587, 7572, 8121, 8777, 9161, 9545, 22, 790, 1171, 1770, 2010, 2965, 3349, 3580, 4465, 4896, 5539, 5805, 6444, 6588, 7573, 8122, 8778, 9162, 9546, 23, 791, 1172, 1771, 2011, 2966, 3350, 3581, 4466, 4897, 5540, 5806, 6445, 6589, 7574, 8123, 8779, 9163, 9547, 24, 792, 1173, 1772, 2012, 2967, 3351, 3582, 4467, 4898, 5541, 5807, 6446, 6590, 7575, 8124, 8780, 9164, 9548, 25, 793, 1174, 1773, 2013, 2968, 3352, 3583, 4468, 4899, 5542, 5808, 6447, 6591, 7576, 8125, 8781, 9165, 9549, 26, 794, 1175, 1774, 2014, 2969, 3353, 3584, 4469, 4900, 5543, 5809, 6448, 6592, 7577, 8126, 8782, 9166, 9550, 27, 795, 1176, 1775, 2015, 2970, 3354, 3585, 4470, 4901, 5544, 5810, 6449, 6593, 7578, 8127, 8783, 9167, 9551, 28, 796, 1177, 1776, 2016, 2971, 3355, 3586, 4471, 4902, 5545, 5811, 6450, 6594, 7579, 8128, 8784, 9168, 9552, 29, 797, 1178, 1777, 2017, 2972, 3356, 3587, 4472, 4903, 5546, 5812, 6451, 6595, 7580, 8129, 8785, 9169, 9553, 30, 798, 1179, 1778, 2018, 2973, 3357, 3588, 4473, 4904, 5547, 5813, 6452, 6596, 7581, 8130, 8786, 9170, 9554, 31, 799, 1180, 1779, 2019, 2974, 3358, 3589, 4474, 4905, 5548, 5814, 6453, 6597, 7582, 8131, 8787, 9171, 9555, 32, 800, 1181, 1780, 2020, 2975, 3359, 3590, 4475, 4906, 5549, 5815, 6454, 6598, 7583, 8132, 8788, 9172, 9556, 33, 801, 1182, 1781, 2021, 2976, 3360, 3591, 4476, 4907, 5550, 5816, 6455, 6599, 7584, 8133, 8789, 9173, 9557, 34, 802, 1183, 1782, 2022, 2977, 3361, 3592, 4477, 4908, 5551, 5817, 6456, 6600, 7585, 8134, 8790, 9174, 9558, 35, 803, 1184, 1783, 2023, 2978, 3362, 3593, 4478, 4909, 5552, 5818, 6457, 6601, 7586, 8135, 8791, 9175, 9559, 36, 804, 1185, 1784, 2024, 2979, 3363, 3594, 4479, 4910, 5553, 5819, 6458, 6602, 7587, 8136, 8792, 9176, 9560, 37, 805, 1186, 1785, 2025, 2980, 3364, 3595, 4480, 4911, 5554, 5820, 6459, 6603, 7588, 8137, 8793, 9177, 9561, 38, 806, 1187, 1786, 2026, 2981, 3365, 3596, 4481, 4912, 5555, 5821, 6460, 6604, 7589, 8138, 8794, 9178, 9562, 39, 807, 1188, 1787, 2027, 2982, 3366, 3597, 4482, 4913, 5556, 5822, 6461, 6605, 7590, 8139, 8795, 9179, 9563, 40, 808, 1189, 1788, 2028, 2983, 3367, 3598, 4483, 4914, 5557, 5823, 6462, 6606, 7591, 8140, 8796, 9180, 9564, 41, 809, 1190, 1789, 2029, 2984, 3368, 3599, 4484, 4915, 5558, 5824, 6463, 6607, 7592, 8141, 8797, 9181, 9565, 42, 810, 1191, 1790, 2030, 2985, 3369, 3600, 4485, 4916, 5559, 5825, 6464, 6608, 7593, 8142, 8798, 9182, 9566, 43, 811, 1192, 1791, 2031, 2986, 3370, 3601, 4486, 4917, 5560, 5826, 6465, 6609, 7594, 8143, 8799, 9183, 9567, 44, 812, 1193, 1792, 2032, 2987, 3371, 3602, 4487, 4918, 5561, 5827, 6466, 6610, 7595, 8144, 8800, 9184, 9568, 45, 813, 1194, 1793, 2033, 2988, 3372, 3603, 4488, 4919, 5562, 5828, 6467, 6611, 7596, 8145, 8801, 9185, 9569, 46, 814, 1195, 1794, 2034, 2989, 3373, 3604, 4489, 4920, 5563, 5829, 6468, 6612, 7597, 8146, 8802, 9186, 9570, 47, 815, 1196, 1795, 2035, 2990, 3374, 3605, 4490, 4921, 5564, 5830, 6469, 6613, 7598, 8147, 8803, 9187, 9571, 48, 816, 1197, 1796, 2036, 2991, 3375, 3606, 4491, 4922, 5565, 5831, 6470, 6614, 7599, 8148, 8804, 9188, 9572, 49, 817, 1198, 1797, 2037, 2992, 3376, 3607, 4492, 4923, 5566, 5832, 6471, 6615, 7600, 8149, 8805, 9189, 9573, 50, 818, 1199, 1798, 2038, 2993, 3377, 3608, 4493, 4924, 5567, 5833, 6472, 6616, 7601, 8150, 8806, 9190, 9574, 51, 819, 1200, 1799, 2039, 2994, 3378, 3609, 4494, 4925, 5568, 5834, 6473, 6617, 7602, 8151, 8807, 9191, 9575, 52, 820, 1201, 1800, 2040, 2995, 3379, 3610, 4495, 4926, 5569, 5835, 6474, 6618, 7603, 8152, 8808, 9192, 9576, 53, 821, 1202, 1801, 2041, 2996, 3380, 3611, 4496, 4927, 5570, 5836, 6475, 6619, 7604, 8153, 8809, 9193, 9577, 54, 822, 1203, 1802, 2042, 2997, 3381, 3612, 4497, 4928, 5571, 5837, 6476, 6620, 7605, 8154, 8810, 9194, 9578, 55, 823, 1204, 1803, 2043, 2998, 3382, 3613, 4498, 4929, 5572, 5838, 6477, 6621, 7606, 8155, 8811, 9195, 9579, 56, 824, 1205, 1804, 2044, 2999, 3383, 3614, 4499, 4930, 5573, 5839, 6478, 6622, 7607, 8156, 8812, 9196, 9580, 57, 825, 1206, 1805, 2045, 3000, 3384, 3615, 4500, 4931, 5574, 5840, 6479, 6623, 7608, 8157, 8813, 9197, 9581, 58, 826, 1207, 1806, 2046, 3001, 3385, 3616, 4501, 4932, 5575, 5841, 6480, 6624, 7609, 8158, 8814, 9198, 9582, 59, 827, 1208, 1807, 2047, 3002, 3386, 3617, 4502, 4933, 5576, 5842, 6481, 6625, 7610, 8159, 8815, 9199, 9583, 60, 828, 1209, 1808, 2048, 3003, 3387, 3618, 4503, 4934, 5577, 5843, 6482, 6626, 7611, 8160, 8816, 9200, 9584, 61, 829, 1210, 1809, 2049, 3004, 3388, 3619, 4504, 4935, 5578, 5844, 6483, 6627, 7612, 8161, 8817, 9201, 9585, 62, 830, 1211, 1810, 2050, 3005, 3389, 3620, 4505, 4936, 5579, 5845, 6484, 6628, 7613, 8162, 8818, 9202, 9586, 63, 831, 1212, 1811, 2051, 3006, 3390, 3621, 4506, 4937, 5580, 5846, 6485, 6629, 7614, 8163, 8819, 9203, 9587, 64, 832, 1213, 1812, 2052, 3007, 3391, 3622, 4507, 4938, 5581, 5847, 6486, 6630, 7615, 8164, 8820, 9204, 9588, 65, 833, 1214, 1813, 2053, 3008, 3392, 3623, 4508, 4939, 5582, 5848, 6487, 6631, 7616, 8165, 8821, 9205, 9589, 66, 834, 1215, 1814, 2054, 3009, 3393, 3624, 4509, 4940, 5583, 5849, 6488, 6632, 7617, 8166, 8822, 9206, 9590, 67, 835, 1216, 1815, 2055, 3010, 3394, 3625, 4510, 4941, 5584, 5850, 6489, 6633, 7618, 8167, 8823, 9207, 9591, 68, 836, 1217, 1816, 2056, 3011, 3395, 3626, 4511, 4942, 5585, 5851, 6490, 6634, 7619, 8168, 8824, 9208, 9592, 69, 837, 1218, 1817, 2057, 3012, 3396, 3627, 4512, 4943, 5586, 5852, 6491, 6635, 7620, 8169, 8825, 9209, 9593, 70, 838, 1219, 1818, 2058, 3013, 3397, 3628, 4513, 4944, 5587, 5853, 6492, 6636, 7621, 8170, 8826, 9210, 9594, 71, 839, 1220, 1819, 2059, 3014, 3398, 3629, 4514, 4945, 5588, 5854, 6493, 6637, 7622, 8171, 8827, 9211, 9595, 72, 840, 1221, 1820, 2060, 3015, 3399, 3630, 4515, 4946, 5589, 5855, 6494, 6638, 7623, 8172, 8828, 9212, 9596, 73, 841, 1222, 1821, 2061, 3016, 3400, 3631, 4516, 4947, 5590, 5856, 6495, 6639, 7624, 8173, 8829, 9213, 9597, 74, 842, 1223, 1822, 2062, 3017, 3401, 3632, 4517, 4948, 5591, 5857, 6496, 6640, 7625, 8174, 8830, 9214, 9598, 75, 843, 1224, 1823, 2063, 3018, 3402, 3633, 4518, 4949, 5592, 5858, 6497, 6641, 7626, 8175, 8831, 9215, 9599, 205, 634, 1096, 1868, 2176, 2465, 2955, 3232, 3519, 3969, 5192, 5464, 5813, 6659, 7152, 7501, 7693, 9216, 9600, 206, 635, 1097, 1869, 2177, 2466, 2956, 3233, 3520, 3970, 5193, 5465, 5814, 6660, 7153, 7502, 7694, 9217, 9601, 207, 636, 1098, 1870, 2178, 2467, 2957, 3234, 3521, 3971, 5194, 5466, 5815, 6661, 7154, 7503, 7695, 9218, 9602, 208, 637, 1099, 1871, 2179, 2468, 2958, 3235, 3522, 3972, 5195, 5467, 5816, 6662, 7155, 7504, 7696, 9219, 9603, 209, 638, 1100, 1872, 2180, 2469, 2959, 3236, 3523, 3973, 5196, 5468, 5817, 6663, 7156, 7505, 7697, 9220, 9604, 210, 639, 1101, 1873, 2181, 2470, 2960, 3237, 3524, 3974, 5197, 5469, 5818, 6664, 7157, 7506, 7698, 9221, 9605, 211, 640, 1102, 1874, 2182, 2471, 2961, 3238, 3525, 3975, 5198, 5470, 5819, 6665, 7158, 7507, 7699, 9222, 9606, 212, 641, 1103, 1875, 2183, 2472, 2962, 3239, 3526, 3976, 5199, 5471, 5820, 6666, 7159, 7508, 7700, 9223, 9607, 213, 642, 1104, 1876, 2184, 2473, 2963, 3240, 3527, 3977, 5200, 5472, 5821, 6667, 7160, 7509, 7701, 9224, 9608, 214, 643, 1105, 1877, 2185, 2474, 2964, 3241, 3528, 3978, 5201, 5473, 5822, 6668, 7161, 7510, 7702, 9225, 9609, 215, 644, 1106, 1878, 2186, 2475, 2965, 3242, 3529, 3979, 5202, 5474, 5823, 6669, 7162, 7511, 7703, 9226, 9610, 216, 645, 1107, 1879, 2187, 2476, 2966, 3243, 3530, 3980, 5203, 5475, 5824, 6670, 7163, 7512, 7704, 9227, 9611, 217, 646, 1108, 1880, 2188, 2477, 2967, 3244, 3531, 3981, 5204, 5476, 5825, 6671, 7164, 7513, 7705, 9228, 9612, 218, 647, 1109, 1881, 2189, 2478, 2968, 3245, 3532, 3982, 5205, 5477, 5826, 6672, 7165, 7514, 7706, 9229, 9613, 219, 648, 1110, 1882, 2190, 2479, 2969, 3246, 3533, 3983, 5206, 5478, 5827, 6673, 7166, 7515, 7707, 9230, 9614, 220, 649, 1111, 1883, 2191, 2480, 2970, 3247, 3534, 3984, 5207, 5479, 5828, 6674, 7167, 7516, 7708, 9231, 9615, 221, 650, 1112, 1884, 2192, 2481, 2971, 3248, 3535, 3985, 5208, 5480, 5829, 6675, 7168, 7517, 7709, 9232, 9616, 222, 651, 1113, 1885, 2193, 2482, 2972, 3249, 3536, 3986, 5209, 5481, 5830, 6676, 7169, 7518, 7710, 9233, 9617, 223, 652, 1114, 1886, 2194, 2483, 2973, 3250, 3537, 3987, 5210, 5482, 5831, 6677, 7170, 7519, 7711, 9234, 9618, 224, 653, 1115, 1887, 2195, 2484, 2974, 3251, 3538, 3988, 5211, 5483, 5832, 6678, 7171, 7520, 7712, 9235, 9619, 225, 654, 1116, 1888, 2196, 2485, 2975, 3252, 3539, 3989, 5212, 5484, 5833, 6679, 7172, 7521, 7713, 9236, 9620, 226, 655, 1117, 1889, 2197, 2486, 2976, 3253, 3540, 3990, 5213, 5485, 5834, 6680, 7173, 7522, 7714, 9237, 9621, 227, 656, 1118, 1890, 2198, 2487, 2977, 3254, 3541, 3991, 5214, 5486, 5835, 6681, 7174, 7523, 7715, 9238, 9622, 228, 657, 1119, 1891, 2199, 2488, 2978, 3255, 3542, 3992, 5215, 5487, 5836, 6682, 7175, 7524, 7716, 9239, 9623, 229, 658, 1120, 1892, 2200, 2489, 2979, 3256, 3543, 3993, 5216, 5488, 5837, 6683, 7176, 7525, 7717, 9240, 9624, 230, 659, 1121, 1893, 2201, 2490, 2980, 3257, 3544, 3994, 5217, 5489, 5838, 6684, 7177, 7526, 7718, 9241, 9625, 231, 660, 1122, 1894, 2202, 2491, 2981, 3258, 3545, 3995, 5218, 5490, 5839, 6685, 7178, 7527, 7719, 9242, 9626, 232, 661, 1123, 1895, 2203, 2492, 2982, 3259, 3546, 3996, 5219, 5491, 5840, 6686, 7179, 7528, 7720, 9243, 9627, 233, 662, 1124, 1896, 2204, 2493, 2983, 3260, 3547, 3997, 5220, 5492, 5841, 6687, 7180, 7529, 7721, 9244, 9628, 234, 663, 1125, 1897, 2205, 2494, 2984, 3261, 3548, 3998, 5221, 5493, 5842, 6688, 7181, 7530, 7722, 9245, 9629, 235, 664, 1126, 1898, 2206, 2495, 2985, 3262, 3549, 3999, 5222, 5494, 5843, 6689, 7182, 7531, 7723, 9246, 9630, 236, 665, 1127, 1899, 2207, 2496, 2986, 3263, 3550, 4000, 5223, 5495, 5844, 6690, 7183, 7532, 7724, 9247, 9631, 237, 666, 1128, 1900, 2208, 2497, 2987, 3264, 3551, 4001, 5224, 5496, 5845, 6691, 7184, 7533, 7725, 9248, 9632, 238, 667, 1129, 1901, 2209, 2498, 2988, 3265, 3552, 4002, 5225, 5497, 5846, 6692, 7185, 7534, 7726, 9249, 9633, 239, 668, 1130, 1902, 2210, 2499, 2989, 3266, 3553, 4003, 5226, 5498, 5847, 6693, 7186, 7535, 7727, 9250, 9634, 240, 669, 1131, 1903, 2211, 2500, 2990, 3267, 3554, 4004, 5227, 5499, 5848, 6694, 7187, 7536, 7728, 9251, 9635, 241, 670, 1132, 1904, 2212, 2501, 2991, 3268, 3555, 4005, 5228, 5500, 5849, 6695, 7188, 7537, 7729, 9252, 9636, 242, 671, 1133, 1905, 2213, 2502, 2992, 3269, 3556, 4006, 5229, 5501, 5850, 6696, 7189, 7538, 7730, 9253, 9637, 243, 672, 1134, 1906, 2214, 2503, 2993, 3270, 3557, 4007, 5230, 5502, 5851, 6697, 7190, 7539, 7731, 9254, 9638, 244, 673, 1135, 1907, 2215, 2504, 2994, 3271, 3558, 4008, 5231, 5503, 5852, 6698, 7191, 7540, 7732, 9255, 9639, 245, 674, 1136, 1908, 2216, 2505, 2995, 3272, 3559, 4009, 5232, 5504, 5853, 6699, 7192, 7541, 7733, 9256, 9640, 246, 675, 1137, 1909, 2217, 2506, 2996, 3273, 3560, 4010, 5233, 5505, 5854, 6700, 7193, 7542, 7734, 9257, 9641, 247, 676, 1138, 1910, 2218, 2507, 2997, 3274, 3561, 4011, 5234, 5506, 5855, 6701, 7194, 7543, 7735, 9258, 9642, 248, 677, 1139, 1911, 2219, 2508, 2998, 3275, 3562, 4012, 5235, 5507, 5856, 6702, 7195, 7544, 7736, 9259, 9643, 249, 678, 1140, 1912, 2220, 2509, 2999, 3276, 3563, 4013, 5236, 5508, 5857, 6703, 7196, 7545, 7737, 9260, 9644, 250, 679, 1141, 1913, 2221, 2510, 3000, 3277, 3564, 4014, 5237, 5509, 5858, 6704, 7197, 7546, 7738, 9261, 9645, 251, 680, 1142, 1914, 2222, 2511, 3001, 3278, 3565, 4015, 5238, 5510, 5859, 6705, 7198, 7547, 7739, 9262, 9646, 252, 681, 1143, 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396, 858, 1630, 1938, 2611, 2717, 3378, 3665, 4115, 5338, 5610, 5959, 6805, 6914, 7647, 7839, 9362, 9746, 352, 397, 859, 1631, 1939, 2612, 2718, 3379, 3666, 4116, 5339, 5611, 5960, 6806, 6915, 7648, 7840, 9363, 9747, 353, 398, 860, 1632, 1940, 2613, 2719, 3380, 3667, 4117, 5340, 5612, 5961, 6807, 6916, 7649, 7841, 9364, 9748, 354, 399, 861, 1633, 1941, 2614, 2720, 3381, 3668, 4118, 5341, 5613, 5962, 6808, 6917, 7650, 7842, 9365, 9749, 355, 400, 862, 1634, 1942, 2615, 2721, 3382, 3669, 4119, 5342, 5614, 5963, 6809, 6918, 7651, 7843, 9366, 9750, 356, 401, 863, 1635, 1943, 2616, 2722, 3383, 3670, 4120, 5343, 5615, 5964, 6810, 6919, 7652, 7844, 9367, 9751, 357, 402, 864, 1636, 1944, 2617, 2723, 3384, 3671, 4121, 5344, 5616, 5965, 6811, 6920, 7653, 7845, 9368, 9752, 358, 403, 865, 1637, 1945, 2618, 2724, 3385, 3672, 4122, 5345, 5617, 5966, 6812, 6921, 7654, 7846, 9369, 9753, 359, 404, 866, 1638, 1946, 2619, 2725, 3386, 3673, 4123, 5346, 5618, 5967, 6813, 6922, 7655, 7847, 9370, 9754, 360, 405, 867, 1639, 1947, 2620, 2726, 3387, 3674, 4124, 5347, 5619, 5968, 6814, 6923, 7656, 7848, 9371, 9755, 361, 406, 868, 1640, 1948, 2621, 2727, 3388, 3675, 4125, 5348, 5620, 5969, 6815, 6924, 7657, 7849, 9372, 9756, 362, 407, 869, 1641, 1949, 2622, 2728, 3389, 3676, 4126, 5349, 5621, 5970, 6816, 6925, 7658, 7850, 9373, 9757, 363, 408, 870, 1642, 1950, 2623, 2729, 3390, 3677, 4127, 5350, 5622, 5971, 6817, 6926, 7659, 7851, 9374, 9758, 364, 409, 871, 1643, 1951, 2624, 2730, 3391, 3678, 4128, 5351, 5623, 5972, 6818, 6927, 7660, 7852, 9375, 9759, 365, 410, 872, 1644, 1952, 2625, 2731, 3392, 3679, 4129, 5352, 5624, 5973, 6819, 6928, 7661, 7853, 9376, 9760, 366, 411, 873, 1645, 1953, 2626, 2732, 3393, 3680, 4130, 5353, 5625, 5974, 6820, 6929, 7662, 7854, 9377, 9761, 367, 412, 874, 1646, 1954, 2627, 2733, 3394, 3681, 4131, 5354, 5626, 5975, 6821, 6930, 7663, 7855, 9378, 9762, 368, 413, 875, 1647, 1955, 2628, 2734, 3395, 3682, 4132, 5355, 5627, 5976, 6822, 6931, 7664, 7856, 9379, 9763, 369, 414, 876, 1648, 1956, 2629, 2735, 3396, 3683, 4133, 5356, 5628, 5977, 6823, 6932, 7665, 7857, 9380, 9764, 370, 415, 877, 1649, 1957, 2630, 2736, 3397, 3684, 4134, 5357, 5629, 5978, 6824, 6933, 7666, 7858, 9381, 9765, 371, 416, 878, 1650, 1958, 2631, 2737, 3398, 3685, 4135, 5358, 5630, 5979, 6825, 6934, 7667, 7859, 9382, 9766, 372, 417, 879, 1651, 1959, 2632, 2738, 3399, 3686, 4136, 5359, 5631, 5980, 6826, 6935, 7668, 7860, 9383, 9767, 373, 418, 880, 1652, 1960, 2633, 2739, 3400, 3687, 4137, 5360, 5632, 5981, 6827, 6936, 7669, 7861, 9384, 9768, 374, 419, 881, 1653, 1961, 2634, 2740, 3401, 3688, 4138, 5361, 5633, 5982, 6828, 6937, 7670, 7862, 9385, 9769, 375, 420, 882, 1654, 1962, 2635, 2741, 3402, 3689, 4139, 5362, 5634, 5983, 6829, 6938, 7671, 7863, 9386, 9770, 376, 421, 883, 1655, 1963, 2636, 2742, 3403, 3690, 4140, 5363, 5635, 5984, 6830, 6939, 7672, 7864, 9387, 9771, 377, 422, 884, 1656, 1964, 2637, 2743, 3404, 3691, 4141, 5364, 5636, 5985, 6831, 6940, 7673, 7865, 9388, 9772, 378, 423, 885, 1657, 1965, 2638, 2744, 3405, 3692, 4142, 5365, 5637, 5986, 6832, 6941, 7674, 7866, 9389, 9773, 379, 424, 886, 1658, 1966, 2639, 2745, 3406, 3693, 4143, 5366, 5638, 5987, 6833, 6942, 7675, 7867, 9390, 9774, 380, 425, 887, 1659, 1967, 2640, 2746, 3407, 3694, 4144, 5367, 5639, 5988, 6834, 6943, 7676, 7868, 9391, 9775, 381, 426, 888, 1660, 1968, 2641, 2747, 3408, 3695, 4145, 5368, 5640, 5989, 6835, 6944, 7677, 7869, 9392, 9776, 382, 427, 889, 1661, 1969, 2642, 2748, 3409, 3696, 4146, 5369, 5641, 5990, 6836, 6945, 7678, 7870, 9393, 9777, 383, 428, 890, 1662, 1970, 2643, 2749, 3410, 3697, 4147, 5370, 5642, 5991, 6837, 6946, 7679, 7871, 9394, 9778, 0, 429, 891, 1663, 1971, 2644, 2750, 3411, 3698, 4148, 5371, 5643, 5992, 6838, 6947, 7296, 7872, 9395, 9779, 1, 430, 892, 1664, 1972, 2645, 2751, 3412, 3699, 4149, 5372, 5644, 5993, 6839, 6948, 7297, 7873, 9396, 9780, 2, 431, 893, 1665, 1973, 2646, 2752, 3413, 3700, 4150, 5373, 5645, 5994, 6840, 6949, 7298, 7874, 9397, 9781, 3, 432, 894, 1666, 1974, 2647, 2753, 3414, 3701, 4151, 5374, 5646, 5995, 6841, 6950, 7299, 7875, 9398, 9782, 4, 433, 895, 1667, 1975, 2648, 2754, 3415, 3702, 4152, 5375, 5647, 5996, 6842, 6951, 7300, 7876, 9399, 9783, 5, 434, 896, 1668, 1976, 2649, 2755, 3416, 3703, 4153, 4992, 5648, 5997, 6843, 6952, 7301, 7877, 9400, 9784, 6, 435, 897, 1669, 1977, 2650, 2756, 3417, 3704, 4154, 4993, 5649, 5998, 6844, 6953, 7302, 7878, 9401, 9785, 7, 436, 898, 1670, 1978, 2651, 2757, 3418, 3705, 4155, 4994, 5650, 5999, 6845, 6954, 7303, 7879, 9402, 9786, 8, 437, 899, 1671, 1979, 2652, 2758, 3419, 3706, 4156, 4995, 5651, 6000, 6846, 6955, 7304, 7880, 9403, 9787, 9, 438, 900, 1672, 1980, 2653, 2759, 3420, 3707, 4157, 4996, 5652, 6001, 6847, 6956, 7305, 7881, 9404, 9788, 10, 439, 901, 1673, 1981, 2654, 2760, 3421, 3708, 4158, 4997, 5653, 6002, 6848, 6957, 7306, 7882, 9405, 9789, 11, 440, 902, 1674, 1982, 2655, 2761, 3422, 3709, 4159, 4998, 5654, 6003, 6849, 6958, 7307, 7883, 9406, 9790, 12, 441, 903, 1675, 1983, 2656, 2762, 3423, 3710, 4160, 4999, 5655, 6004, 6850, 6959, 7308, 7884, 9407, 9791, 13, 442, 904, 1676, 1984, 2657, 2763, 3424, 3711, 4161, 5000, 5656, 6005, 6851, 6960, 7309, 7885, 9408, 9792, 14, 443, 905, 1677, 1985, 2658, 2764, 3425, 3712, 4162, 5001, 5657, 6006, 6852, 6961, 7310, 7886, 9409, 9793, 15, 444, 906, 1678, 1986, 2659, 2765, 3426, 3713, 4163, 5002, 5658, 6007, 6853, 6962, 7311, 7887, 9410, 9794, 16, 445, 907, 1679, 1987, 2660, 2766, 3427, 3714, 4164, 5003, 5659, 6008, 6854, 6963, 7312, 7888, 9411, 9795, 17, 446, 908, 1680, 1988, 2661, 2767, 3428, 3715, 4165, 5004, 5660, 6009, 6855, 6964, 7313, 7889, 9412, 9796, 18, 447, 909, 1681, 1989, 2662, 2768, 3429, 3716, 4166, 5005, 5661, 6010, 6856, 6965, 7314, 7890, 9413, 9797, 19, 448, 910, 1682, 1990, 2663, 2769, 3430, 3717, 4167, 5006, 5662, 6011, 6857, 6966, 7315, 7891, 9414, 9798, 20, 449, 911, 1683, 1991, 2664, 2770, 3431, 3718, 4168, 5007, 5663, 6012, 6858, 6967, 7316, 7892, 9415, 9799, 21, 450, 912, 1684, 1992, 2665, 2771, 3432, 3719, 4169, 5008, 5664, 6013, 6859, 6968, 7317, 7893, 9416, 9800, 22, 451, 913, 1685, 1993, 2666, 2772, 3433, 3720, 4170, 5009, 5665, 6014, 6860, 6969, 7318, 7894, 9417, 9801, 23, 452, 914, 1686, 1994, 2667, 2773, 3434, 3721, 4171, 5010, 5666, 6015, 6861, 6970, 7319, 7895, 9418, 9802, 24, 453, 915, 1687, 1995, 2668, 2774, 3435, 3722, 4172, 5011, 5667, 6016, 6862, 6971, 7320, 7896, 9419, 9803, 25, 454, 916, 1688, 1996, 2669, 2775, 3436, 3723, 4173, 5012, 5668, 6017, 6863, 6972, 7321, 7897, 9420, 9804, 26, 455, 917, 1689, 1997, 2670, 2776, 3437, 3724, 4174, 5013, 5669, 6018, 6864, 6973, 7322, 7898, 9421, 9805, 27, 456, 918, 1690, 1998, 2671, 2777, 3438, 3725, 4175, 5014, 5670, 6019, 6865, 6974, 7323, 7899, 9422, 9806, 28, 457, 919, 1691, 1999, 2672, 2778, 3439, 3726, 4176, 5015, 5671, 6020, 6866, 6975, 7324, 7900, 9423, 9807, 29, 458, 920, 1692, 2000, 2673, 2779, 3440, 3727, 4177, 5016, 5672, 6021, 6867, 6976, 7325, 7901, 9424, 9808, 30, 459, 921, 1693, 2001, 2674, 2780, 3441, 3728, 4178, 5017, 5673, 6022, 6868, 6977, 7326, 7902, 9425, 9809, 31, 460, 922, 1694, 2002, 2675, 2781, 3442, 3729, 4179, 5018, 5674, 6023, 6869, 6978, 7327, 7903, 9426, 9810, 32, 461, 923, 1695, 2003, 2676, 2782, 3443, 3730, 4180, 5019, 5675, 6024, 6870, 6979, 7328, 7904, 9427, 9811, 33, 462, 924, 1696, 2004, 2677, 2783, 3444, 3731, 4181, 5020, 5676, 6025, 6871, 6980, 7329, 7905, 9428, 9812, 34, 463, 925, 1697, 2005, 2678, 2784, 3445, 3732, 4182, 5021, 5677, 6026, 6872, 6981, 7330, 7906, 9429, 9813, 35, 464, 926, 1698, 2006, 2679, 2785, 3446, 3733, 4183, 5022, 5678, 6027, 6873, 6982, 7331, 7907, 9430, 9814, 36, 465, 927, 1699, 2007, 2680, 2786, 3447, 3734, 4184, 5023, 5679, 6028, 6874, 6983, 7332, 7908, 9431, 9815, 37, 466, 928, 1700, 2008, 2681, 2787, 3448, 3735, 4185, 5024, 5680, 6029, 6875, 6984, 7333, 7909, 9432, 9816, 38, 467, 929, 1701, 2009, 2682, 2788, 3449, 3736, 4186, 5025, 5681, 6030, 6876, 6985, 7334, 7910, 9433, 9817, 39, 468, 930, 1702, 2010, 2683, 2789, 3450, 3737, 4187, 5026, 5682, 6031, 6877, 6986, 7335, 7911, 9434, 9818, 40, 469, 931, 1703, 2011, 2684, 2790, 3451, 3738, 4188, 5027, 5683, 6032, 6878, 6987, 7336, 7912, 9435, 9819, 41, 470, 932, 1704, 2012, 2685, 2791, 3452, 3739, 4189, 5028, 5684, 6033, 6879, 6988, 7337, 7913, 9436, 9820, 42, 471, 933, 1705, 2013, 2686, 2792, 3453, 3740, 4190, 5029, 5685, 6034, 6880, 6989, 7338, 7914, 9437, 9821, 43, 472, 934, 1706, 2014, 2687, 2793, 3454, 3741, 4191, 5030, 5686, 6035, 6881, 6990, 7339, 7915, 9438, 9822, 44, 473, 935, 1707, 2015, 2304, 2794, 3455, 3742, 4192, 5031, 5687, 6036, 6882, 6991, 7340, 7916, 9439, 9823, 45, 474, 936, 1708, 2016, 2305, 2795, 3072, 3743, 4193, 5032, 5688, 6037, 6883, 6992, 7341, 7917, 9440, 9824, 46, 475, 937, 1709, 2017, 2306, 2796, 3073, 3744, 4194, 5033, 5689, 6038, 6884, 6993, 7342, 7918, 9441, 9825, 47, 476, 938, 1710, 2018, 2307, 2797, 3074, 3745, 4195, 5034, 5690, 6039, 6885, 6994, 7343, 7919, 9442, 9826, 48, 477, 939, 1711, 2019, 2308, 2798, 3075, 3746, 4196, 5035, 5691, 6040, 6886, 6995, 7344, 7920, 9443, 9827, 49, 478, 940, 1712, 2020, 2309, 2799, 3076, 3747, 4197, 5036, 5692, 6041, 6887, 6996, 7345, 7921, 9444, 9828, 50, 479, 941, 1713, 2021, 2310, 2800, 3077, 3748, 4198, 5037, 5693, 6042, 6888, 6997, 7346, 7922, 9445, 9829, 51, 480, 942, 1714, 2022, 2311, 2801, 3078, 3749, 4199, 5038, 5694, 6043, 6889, 6998, 7347, 7923, 9446, 9830, 52, 481, 943, 1715, 2023, 2312, 2802, 3079, 3750, 4200, 5039, 5695, 6044, 6890, 6999, 7348, 7924, 9447, 9831, 53, 482, 944, 1716, 2024, 2313, 2803, 3080, 3751, 4201, 5040, 5696, 6045, 6891, 7000, 7349, 7925, 9448, 9832, 54, 483, 945, 1717, 2025, 2314, 2804, 3081, 3752, 4202, 5041, 5697, 6046, 6892, 7001, 7350, 7926, 9449, 9833, 55, 484, 946, 1718, 2026, 2315, 2805, 3082, 3753, 4203, 5042, 5698, 6047, 6893, 7002, 7351, 7927, 9450, 9834, 56, 485, 947, 1719, 2027, 2316, 2806, 3083, 3754, 4204, 5043, 5699, 6048, 6894, 7003, 7352, 7928, 9451, 9835, 57, 486, 948, 1720, 2028, 2317, 2807, 3084, 3755, 4205, 5044, 5700, 6049, 6895, 7004, 7353, 7929, 9452, 9836, 58, 487, 949, 1721, 2029, 2318, 2808, 3085, 3756, 4206, 5045, 5701, 6050, 6896, 7005, 7354, 7930, 9453, 9837, 59, 488, 950, 1722, 2030, 2319, 2809, 3086, 3757, 4207, 5046, 5702, 6051, 6897, 7006, 7355, 7931, 9454, 9838, 60, 489, 951, 1723, 2031, 2320, 2810, 3087, 3758, 4208, 5047, 5703, 6052, 6898, 7007, 7356, 7932, 9455, 9839, 61, 490, 952, 1724, 2032, 2321, 2811, 3088, 3759, 4209, 5048, 5704, 6053, 6899, 7008, 7357, 7933, 9456, 9840, 62, 491, 953, 1725, 2033, 2322, 2812, 3089, 3760, 4210, 5049, 5705, 6054, 6900, 7009, 7358, 7934, 9457, 9841, 63, 492, 954, 1726, 2034, 2323, 2813, 3090, 3761, 4211, 5050, 5706, 6055, 6901, 7010, 7359, 7935, 9458, 9842, 64, 493, 955, 1727, 2035, 2324, 2814, 3091, 3762, 4212, 5051, 5707, 6056, 6902, 7011, 7360, 7936, 9459, 9843, 65, 494, 956, 1728, 2036, 2325, 2815, 3092, 3763, 4213, 5052, 5708, 6057, 6903, 7012, 7361, 7937, 9460, 9844, 66, 495, 957, 1729, 2037, 2326, 2816, 3093, 3764, 4214, 5053, 5709, 6058, 6904, 7013, 7362, 7938, 9461, 9845, 67, 496, 958, 1730, 2038, 2327, 2817, 3094, 3765, 4215, 5054, 5710, 6059, 6905, 7014, 7363, 7939, 9462, 9846, 68, 497, 959, 1731, 2039, 2328, 2818, 3095, 3766, 4216, 5055, 5711, 6060, 6906, 7015, 7364, 7940, 9463, 9847, 69, 498, 960, 1732, 2040, 2329, 2819, 3096, 3767, 4217, 5056, 5712, 6061, 6907, 7016, 7365, 7941, 9464, 9848, 70, 499, 961, 1733, 2041, 2330, 2820, 3097, 3768, 4218, 5057, 5713, 6062, 6908, 7017, 7366, 7942, 9465, 9849, 71, 500, 962, 1734, 2042, 2331, 2821, 3098, 3769, 4219, 5058, 5714, 6063, 6909, 7018, 7367, 7943, 9466, 9850, 72, 501, 963, 1735, 2043, 2332, 2822, 3099, 3770, 4220, 5059, 5715, 6064, 6910, 7019, 7368, 7944, 9467, 9851, 73, 502, 964, 1736, 2044, 2333, 2823, 3100, 3771, 4221, 5060, 5716, 6065, 6911, 7020, 7369, 7945, 9468, 9852, 74, 503, 965, 1737, 2045, 2334, 2824, 3101, 3772, 4222, 5061, 5717, 6066, 6528, 7021, 7370, 7946, 9469, 9853, 75, 504, 966, 1738, 2046, 2335, 2825, 3102, 3773, 4223, 5062, 5718, 6067, 6529, 7022, 7371, 7947, 9470, 9854, 76, 505, 967, 1739, 2047, 2336, 2826, 3103, 3774, 3840, 5063, 5719, 6068, 6530, 7023, 7372, 7948, 9471, 9855, 77, 506, 968, 1740, 2048, 2337, 2827, 3104, 3775, 3841, 5064, 5720, 6069, 6531, 7024, 7373, 7949, 9472, 9856, 78, 507, 969, 1741, 2049, 2338, 2828, 3105, 3776, 3842, 5065, 5721, 6070, 6532, 7025, 7374, 7950, 9473, 9857, 79, 508, 970, 1742, 2050, 2339, 2829, 3106, 3777, 3843, 5066, 5722, 6071, 6533, 7026, 7375, 7951, 9474, 9858, 80, 509, 971, 1743, 2051, 2340, 2830, 3107, 3778, 3844, 5067, 5723, 6072, 6534, 7027, 7376, 7952, 9475, 9859, 81, 510, 972, 1744, 2052, 2341, 2831, 3108, 3779, 3845, 5068, 5724, 6073, 6535, 7028, 7377, 7953, 9476, 9860, 82, 511, 973, 1745, 2053, 2342, 2832, 3109, 3780, 3846, 5069, 5725, 6074, 6536, 7029, 7378, 7954, 9477, 9861, 83, 512, 974, 1746, 2054, 2343, 2833, 3110, 3781, 3847, 5070, 5726, 6075, 6537, 7030, 7379, 7955, 9478, 9862, 84, 513, 975, 1747, 2055, 2344, 2834, 3111, 3782, 3848, 5071, 5727, 6076, 6538, 7031, 7380, 7956, 9479, 9863, 85, 514, 976, 1748, 2056, 2345, 2835, 3112, 3783, 3849, 5072, 5728, 6077, 6539, 7032, 7381, 7957, 9480, 9864, 86, 515, 977, 1749, 2057, 2346, 2836, 3113, 3784, 3850, 5073, 5729, 6078, 6540, 7033, 7382, 7958, 9481, 9865, 87, 516, 978, 1750, 2058, 2347, 2837, 3114, 3785, 3851, 5074, 5730, 6079, 6541, 7034, 7383, 7959, 9482, 9866, 88, 517, 979, 1751, 2059, 2348, 2838, 3115, 3786, 3852, 5075, 5731, 6080, 6542, 7035, 7384, 7960, 9483, 9867, 89, 518, 980, 1752, 2060, 2349, 2839, 3116, 3787, 3853, 5076, 5732, 6081, 6543, 7036, 7385, 7961, 9484, 9868, 90, 519, 981, 1753, 2061, 2350, 2840, 3117, 3788, 3854, 5077, 5733, 6082, 6544, 7037, 7386, 7962, 9485, 9869, 91, 520, 982, 1754, 2062, 2351, 2841, 3118, 3789, 3855, 5078, 5734, 6083, 6545, 7038, 7387, 7963, 9486, 9870, 92, 521, 983, 1755, 2063, 2352, 2842, 3119, 3790, 3856, 5079, 5735, 6084, 6546, 7039, 7388, 7964, 9487, 9871, 93, 522, 984, 1756, 2064, 2353, 2843, 3120, 3791, 3857, 5080, 5736, 6085, 6547, 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4852, 5346, 5601, 6461, 6841, 7196, 7732, 8434, 8462, 9613, 290, 485, 1166, 1825, 2517, 2855, 3142, 3986, 4543, 4853, 5347, 5602, 6462, 6842, 7197, 7733, 8435, 8463, 9614, 291, 486, 1167, 1826, 2518, 2856, 3143, 3987, 4544, 4854, 5348, 5603, 6463, 6843, 7198, 7734, 8436, 8464, 9615, 292, 487, 1168, 1827, 2519, 2857, 3144, 3988, 4545, 4855, 5349, 5604, 6464, 6844, 7199, 7735, 8437, 8465, 9616, 293, 488, 1169, 1828, 2520, 2858, 3145, 3989, 4546, 4856, 5350, 5605, 6465, 6845, 7200, 7736, 8438, 8466, 9617, 294, 489, 1170, 1829, 2521, 2859, 3146, 3990, 4547, 4857, 5351, 5606, 6466, 6846, 7201, 7737, 8439, 8467, 9618, 295, 490, 1171, 1830, 2522, 2860, 3147, 3991, 4548, 4858, 5352, 5607, 6467, 6847, 7202, 7738, 8440, 8468, 9619, 296, 491, 1172, 1831, 2523, 2861, 3148, 3992, 4549, 4859, 5353, 5608, 6468, 6848, 7203, 7739, 8441, 8469, 9620, 297, 492, 1173, 1832, 2524, 2862, 3149, 3993, 4550, 4860, 5354, 5609, 6469, 6849, 7204, 7740, 8442, 8470, 9621, 298, 493, 1174, 1833, 2525, 2863, 3150, 3994, 4551, 4861, 5355, 5610, 6470, 6850, 7205, 7741, 8443, 8471, 9622, 299, 494, 1175, 1834, 2526, 2864, 3151, 3995, 4552, 4862, 5356, 5611, 6471, 6851, 7206, 7742, 8444, 8472, 9623, 300, 495, 1176, 1835, 2527, 2865, 3152, 3996, 4553, 4863, 5357, 5612, 6472, 6852, 7207, 7743, 8445, 8473, 9624, 301, 496, 1177, 1836, 2528, 2866, 3153, 3997, 4554, 4864, 5358, 5613, 6473, 6853, 7208, 7744, 8446, 8474, 9625, 302, 497, 1178, 1837, 2529, 2867, 3154, 3998, 4555, 4865, 5359, 5614, 6474, 6854, 7209, 7745, 8447, 8475, 9626, 303, 498, 1179, 1838, 2530, 2868, 3155, 3999, 4556, 4866, 5360, 5615, 6475, 6855, 7210, 7746, 8064, 8476, 9627, 304, 499, 1180, 1839, 2531, 2869, 3156, 4000, 4557, 4867, 5361, 5616, 6476, 6856, 7211, 7747, 8065, 8477, 9628, 305, 500, 1181, 1840, 2532, 2870, 3157, 4001, 4558, 4868, 5362, 5617, 6477, 6857, 7212, 7748, 8066, 8478, 9629, 306, 501, 1182, 1841, 2533, 2871, 3158, 4002, 4559, 4869, 5363, 5618, 6478, 6858, 7213, 7749, 8067, 8479, 9630, 307, 502, 1183, 1842, 2534, 2872, 3159, 4003, 4560, 4870, 5364, 5619, 6479, 6859, 7214, 7750, 8068, 8480, 9631, 308, 503, 1184, 1843, 2535, 2873, 3160, 4004, 4561, 4871, 5365, 5620, 6480, 6860, 7215, 7751, 8069, 8481, 9632, 309, 504, 1185, 1844, 2536, 2874, 3161, 4005, 4562, 4872, 5366, 5621, 6481, 6861, 7216, 7752, 8070, 8482, 9633, 310, 505, 1186, 1845, 2537, 2875, 3162, 4006, 4563, 4873, 5367, 5622, 6482, 6862, 7217, 7753, 8071, 8483, 9634, 311, 506, 1187, 1846, 2538, 2876, 3163, 4007, 4564, 4874, 5368, 5623, 6483, 6863, 7218, 7754, 8072, 8484, 9635, 312, 507, 1188, 1847, 2539, 2877, 3164, 4008, 4565, 4875, 5369, 5624, 6484, 6864, 7219, 7755, 8073, 8485, 9636, 313, 508, 1189, 1848, 2540, 2878, 3165, 4009, 4566, 4876, 5370, 5625, 6485, 6865, 7220, 7756, 8074, 8486, 9637, 314, 509, 1190, 1849, 2541, 2879, 3166, 4010, 4567, 4877, 5371, 5626, 6486, 6866, 7221, 7757, 8075, 8487, 9638, 315, 510, 1191, 1850, 2542, 2880, 3167, 4011, 4568, 4878, 5372, 5627, 6487, 6867, 7222, 7758, 8076, 8488, 9639, 316, 511, 1192, 1851, 2543, 2881, 3168, 4012, 4569, 4879, 5373, 5628, 6488, 6868, 7223, 7759, 8077, 8489, 9640, 317, 512, 1193, 1852, 2544, 2882, 3169, 4013, 4570, 4880, 5374, 5629, 6489, 6869, 7224, 7760, 8078, 8490, 9641, 318, 513, 1194, 1853, 2545, 2883, 3170, 4014, 4571, 4881, 5375, 5630, 6490, 6870, 7225, 7761, 8079, 8491, 9642, 319, 514, 1195, 1854, 2546, 2884, 3171, 4015, 4572, 4882, 4992, 5631, 6491, 6871, 7226, 7762, 8080, 8492, 9643, 320, 515, 1196, 1855, 2547, 2885, 3172, 4016, 4573, 4883, 4993, 5632, 6492, 6872, 7227, 7763, 8081, 8493, 9644, 321, 516, 1197, 1856, 2548, 2886, 3173, 4017, 4574, 4884, 4994, 5633, 6493, 6873, 7228, 7764, 8082, 8494, 9645, 322, 517, 1198, 1857, 2549, 2887, 3174, 4018, 4575, 4885, 4995, 5634, 6494, 6874, 7229, 7765, 8083, 8495, 9646, 323, 518, 1199, 1858, 2550, 2888, 3175, 4019, 4576, 4886, 4996, 5635, 6495, 6875, 7230, 7766, 8084, 8496, 9647, 324, 519, 1200, 1859, 2551, 2889, 3176, 4020, 4577, 4887, 4997, 5636, 6496, 6876, 7231, 7767, 8085, 8497, 9648, 325, 520, 1201, 1860, 2552, 2890, 3177, 4021, 4578, 4888, 4998, 5637, 6497, 6877, 7232, 7768, 8086, 8498, 9649, 326, 521, 1202, 1861, 2553, 2891, 3178, 4022, 4579, 4889, 4999, 5638, 6498, 6878, 7233, 7769, 8087, 8499, 9650, 327, 522, 1203, 1862, 2554, 2892, 3179, 4023, 4580, 4890, 5000, 5639, 6499, 6879, 7234, 7770, 8088, 8500, 9651, 328, 523, 1204, 1863, 2555, 2893, 3180, 4024, 4581, 4891, 5001, 5640, 6500, 6880, 7235, 7771, 8089, 8501, 9652, 329, 524, 1205, 1864, 2556, 2894, 3181, 4025, 4582, 4892, 5002, 5641, 6501, 6881, 7236, 7772, 8090, 8502, 9653, 330, 525, 1206, 1865, 2557, 2895, 3182, 4026, 4583, 4893, 5003, 5642, 6502, 6882, 7237, 7773, 8091, 8503, 9654, 331, 526, 1207, 1866, 2558, 2896, 3183, 4027, 4584, 4894, 5004, 5643, 6503, 6883, 7238, 7774, 8092, 8504, 9655, 332, 527, 1208, 1867, 2559, 2897, 3184, 4028, 4585, 4895, 5005, 5644, 6504, 6884, 7239, 7775, 8093, 8505, 9656, 333, 528, 1209, 1868, 2560, 2898, 3185, 4029, 4586, 4896, 5006, 5645, 6505, 6885, 7240, 7776, 8094, 8506, 9657, 334, 529, 1210, 1869, 2561, 2899, 3186, 4030, 4587, 4897, 5007, 5646, 6506, 6886, 7241, 7777, 8095, 8507, 9658, 335, 530, 1211, 1870, 2562, 2900, 3187, 4031, 4588, 4898, 5008, 5647, 6507, 6887, 7242, 7778, 8096, 8508, 9659, 336, 531, 1212, 1871, 2563, 2901, 3188, 4032, 4589, 4899, 5009, 5648, 6508, 6888, 7243, 7779, 8097, 8509, 9660, 337, 532, 1213, 1872, 2564, 2902, 3189, 4033, 4590, 4900, 5010, 5649, 6509, 6889, 7244, 7780, 8098, 8510, 9661, 338, 533, 1214, 1873, 2565, 2903, 3190, 4034, 4591, 4901, 5011, 5650, 6510, 6890, 7245, 7781, 8099, 8511, 9662, 339, 534, 1215, 1874, 2566, 2904, 3191, 4035, 4592, 4902, 5012, 5651, 6511, 6891, 7246, 7782, 8100, 8512, 9663, 340, 535, 1216, 1875, 2567, 2905, 3192, 4036, 4593, 4903, 5013, 5652, 6512, 6892, 7247, 7783, 8101, 8513, 9664, 341, 536, 1217, 1876, 2568, 2906, 3193, 4037, 4594, 4904, 5014, 5653, 6513, 6893, 7248, 7784, 8102, 8514, 9665, 342, 537, 1218, 1877, 2569, 2907, 3194, 4038, 4595, 4905, 5015, 5654, 6514, 6894, 7249, 7785, 8103, 8515, 9666, 343, 538, 1219, 1878, 2570, 2908, 3195, 4039, 4596, 4906, 5016, 5655, 6515, 6895, 7250, 7786, 8104, 8516, 9667, 344, 539, 1220, 1879, 2571, 2909, 3196, 4040, 4597, 4907, 5017, 5656, 6516, 6896, 7251, 7787, 8105, 8517, 9668, 345, 540, 1221, 1880, 2572, 2910, 3197, 4041, 4598, 4908, 5018, 5657, 6517, 6897, 7252, 7788, 8106, 8518, 9669, 346, 541, 1222, 1881, 2573, 2911, 3198, 4042, 4599, 4909, 5019, 5658, 6518, 6898, 7253, 7789, 8107, 8519, 9670, 347, 542, 1223, 1882, 2574, 2912, 3199, 4043, 4600, 4910, 5020, 5659, 6519, 6899, 7254, 7790, 8108, 8520, 9671, 348, 543, 1224, 1883, 2575, 2913, 3200, 4044, 4601, 4911, 5021, 5660, 6520, 6900, 7255, 7791, 8109, 8521, 9672, 349, 544, 1225, 1884, 2576, 2914, 3201, 4045, 4602, 4912, 5022, 5661, 6521, 6901, 7256, 7792, 8110, 8522, 9673, 350, 545, 1226, 1885, 2577, 2915, 3202, 4046, 4603, 4913, 5023, 5662, 6522, 6902, 7257, 7793, 8111, 8523, 9674, 351, 546, 1227, 1886, 2578, 2916, 3203, 4047, 4604, 4914, 5024, 5663, 6523, 6903, 7258, 7794, 8112, 8524, 9675, 352, 547, 1228, 1887, 2579, 2917, 3204, 4048, 4605, 4915, 5025, 5664, 6524, 6904, 7259, 7795, 8113, 8525, 9676, 353, 548, 1229, 1888, 2580, 2918, 3205, 4049, 4606, 4916, 5026, 5665, 6525, 6905, 7260, 7796, 8114, 8526, 9677, 354, 549, 1230, 1889, 2581, 2919, 3206, 4050, 4607, 4917, 5027, 5666, 6526, 6906, 7261, 7797, 8115, 8527, 9678, 355, 550, 1231, 1890, 2582, 2920, 3207, 4051, 4224, 4918, 5028, 5667, 6527, 6907, 7262, 7798, 8116, 8528, 9679, 356, 551, 1232, 1891, 2583, 2921, 3208, 4052, 4225, 4919, 5029, 5668, 6144, 6908, 7263, 7799, 8117, 8529, 9680, 357, 552, 1233, 1892, 2584, 2922, 3209, 4053, 4226, 4920, 5030, 5669, 6145, 6909, 7264, 7800, 8118, 8530, 9681, 358, 553, 1234, 1893, 2585, 2923, 3210, 4054, 4227, 4921, 5031, 5670, 6146, 6910, 7265, 7801, 8119, 8531, 9682, 359, 554, 1235, 1894, 2586, 2924, 3211, 4055, 4228, 4922, 5032, 5671, 6147, 6911, 7266, 7802, 8120, 8532, 9683, 360, 555, 1236, 1895, 2587, 2925, 3212, 4056, 4229, 4923, 5033, 5672, 6148, 6528, 7267, 7803, 8121, 8533, 9684, 361, 556, 1237, 1896, 2588, 2926, 3213, 4057, 4230, 4924, 5034, 5673, 6149, 6529, 7268, 7804, 8122, 8534, 9685, 362, 557, 1238, 1897, 2589, 2927, 3214, 4058, 4231, 4925, 5035, 5674, 6150, 6530, 7269, 7805, 8123, 8535, 9686, 363, 558, 1239, 1898, 2590, 2928, 3215, 4059, 4232, 4926, 5036, 5675, 6151, 6531, 7270, 7806, 8124, 8536, 9687, 364, 559, 1240, 1899, 2591, 2929, 3216, 4060, 4233, 4927, 5037, 5676, 6152, 6532, 7271, 7807, 8125, 8537, 9688, 365, 560, 1241, 1900, 2592, 2930, 3217, 4061, 4234, 4928, 5038, 5677, 6153, 6533, 7272, 7808, 8126, 8538, 9689, 366, 561, 1242, 1901, 2593, 2931, 3218, 4062, 4235, 4929, 5039, 5678, 6154, 6534, 7273, 7809, 8127, 8539, 9690, 367, 562, 1243, 1902, 2594, 2932, 3219, 4063, 4236, 4930, 5040, 5679, 6155, 6535, 7274, 7810, 8128, 8540, 9691, 368, 563, 1244, 1903, 2595, 2933, 3220, 4064, 4237, 4931, 5041, 5680, 6156, 6536, 7275, 7811, 8129, 8541, 9692, 369, 564, 1245, 1904, 2596, 2934, 3221, 4065, 4238, 4932, 5042, 5681, 6157, 6537, 7276, 7812, 8130, 8542, 9693, 370, 565, 1246, 1905, 2597, 2935, 3222, 4066, 4239, 4933, 5043, 5682, 6158, 6538, 7277, 7813, 8131, 8543, 9694, 371, 566, 1247, 1906, 2598, 2936, 3223, 4067, 4240, 4934, 5044, 5683, 6159, 6539, 7278, 7814, 8132, 8544, 9695, 372, 567, 1248, 1907, 2599, 2937, 3224, 4068, 4241, 4935, 5045, 5684, 6160, 6540, 7279, 7815, 8133, 8545, 9696, 373, 568, 1249, 1908, 2600, 2938, 3225, 4069, 4242, 4936, 5046, 5685, 6161, 6541, 7280, 7816, 8134, 8546, 9697, 374, 569, 1250, 1909, 2601, 2939, 3226, 4070, 4243, 4937, 5047, 5686, 6162, 6542, 7281, 7817, 8135, 8547, 9698, 375, 570, 1251, 1910, 2602, 2940, 3227, 4071, 4244, 4938, 5048, 5687, 6163, 6543, 7282, 7818, 8136, 8548, 9699, 376, 571, 1252, 1911, 2603, 2941, 3228, 4072, 4245, 4939, 5049, 5688, 6164, 6544, 7283, 7819, 8137, 8549, 9700, 377, 572, 1253, 1912, 2604, 2942, 3229, 4073, 4246, 4940, 5050, 5689, 6165, 6545, 7284, 7820, 8138, 8550, 9701, 378, 573, 1254, 1913, 2605, 2943, 3230, 4074, 4247, 4941, 5051, 5690, 6166, 6546, 7285, 7821, 8139, 8551, 9702, 379, 574, 1255, 1914, 2606, 2944, 3231, 4075, 4248, 4942, 5052, 5691, 6167, 6547, 7286, 7822, 8140, 8552, 9703, 380, 575, 1256, 1915, 2607, 2945, 3232, 4076, 4249, 4943, 5053, 5692, 6168, 6548, 7287, 7823, 8141, 8553, 9704, 381, 576, 1257, 1916, 2608, 2946, 3233, 4077, 4250, 4944, 5054, 5693, 6169, 6549, 7288, 7824, 8142, 8554, 9705, 382, 577, 1258, 1917, 2609, 2947, 3234, 4078, 4251, 4945, 5055, 5694, 6170, 6550, 7289, 7825, 8143, 8555, 9706, 383, 578, 1259, 1918, 2610, 2948, 3235, 4079, 4252, 4946, 5056, 5695, 6171, 6551, 7290, 7826, 8144, 8556, 9707, 0, 579, 1260, 1919, 2611, 2949, 3236, 4080, 4253, 4947, 5057, 5696, 6172, 6552, 7291, 7827, 8145, 8557, 9708, 1, 580, 1261, 1536, 2612, 2950, 3237, 4081, 4254, 4948, 5058, 5697, 6173, 6553, 7292, 7828, 8146, 8558, 9709, 2, 581, 1262, 1537, 2613, 2951, 3238, 4082, 4255, 4949, 5059, 5698, 6174, 6554, 7293, 7829, 8147, 8559, 9710, 3, 582, 1263, 1538, 2614, 2952, 3239, 4083, 4256, 4950, 5060, 5699, 6175, 6555, 7294, 7830, 8148, 8560, 9711, 4, 583, 1264, 1539, 2615, 2953, 3240, 4084, 4257, 4951, 5061, 5700, 6176, 6556, 7295, 7831, 8149, 8561, 9712, 5, 584, 1265, 1540, 2616, 2954, 3241, 4085, 4258, 4952, 5062, 5701, 6177, 6557, 6912, 7832, 8150, 8562, 9713, 6, 585, 1266, 1541, 2617, 2955, 3242, 4086, 4259, 4953, 5063, 5702, 6178, 6558, 6913, 7833, 8151, 8563, 9714, 7, 586, 1267, 1542, 2618, 2956, 3243, 4087, 4260, 4954, 5064, 5703, 6179, 6559, 6914, 7834, 8152, 8564, 9715, 8, 587, 1268, 1543, 2619, 2957, 3244, 4088, 4261, 4955, 5065, 5704, 6180, 6560, 6915, 7835, 8153, 8565, 9716, 9, 588, 1269, 1544, 2620, 2958, 3245, 4089, 4262, 4956, 5066, 5705, 6181, 6561, 6916, 7836, 8154, 8566, 9717, 10, 589, 1270, 1545, 2621, 2959, 3246, 4090, 4263, 4957, 5067, 5706, 6182, 6562, 6917, 7837, 8155, 8567, 9718, 11, 590, 1271, 1546, 2622, 2960, 3247, 4091, 4264, 4958, 5068, 5707, 6183, 6563, 6918, 7838, 8156, 8568, 9719, 12, 591, 1272, 1547, 2623, 2961, 3248, 4092, 4265, 4959, 5069, 5708, 6184, 6564, 6919, 7839, 8157, 8569, 9720, 13, 592, 1273, 1548, 2624, 2962, 3249, 4093, 4266, 4960, 5070, 5709, 6185, 6565, 6920, 7840, 8158, 8570, 9721, 14, 593, 1274, 1549, 2625, 2963, 3250, 4094, 4267, 4961, 5071, 5710, 6186, 6566, 6921, 7841, 8159, 8571, 9722, 15, 594, 1275, 1550, 2626, 2964, 3251, 4095, 4268, 4962, 5072, 5711, 6187, 6567, 6922, 7842, 8160, 8572, 9723, 16, 595, 1276, 1551, 2627, 2965, 3252, 4096, 4269, 4963, 5073, 5712, 6188, 6568, 6923, 7843, 8161, 8573, 9724, 17, 596, 1277, 1552, 2628, 2966, 3253, 4097, 4270, 4964, 5074, 5713, 6189, 6569, 6924, 7844, 8162, 8574, 9725, 18, 597, 1278, 1553, 2629, 2967, 3254, 4098, 4271, 4965, 5075, 5714, 6190, 6570, 6925, 7845, 8163, 8575, 9726, 19, 598, 1279, 1554, 2630, 2968, 3255, 4099, 4272, 4966, 5076, 5715, 6191, 6571, 6926, 7846, 8164, 8576, 9727, 20, 599, 1280, 1555, 2631, 2969, 3256, 4100, 4273, 4967, 5077, 5716, 6192, 6572, 6927, 7847, 8165, 8577, 9728, 21, 600, 1281, 1556, 2632, 2970, 3257, 4101, 4274, 4968, 5078, 5717, 6193, 6573, 6928, 7848, 8166, 8578, 9729, 22, 601, 1282, 1557, 2633, 2971, 3258, 4102, 4275, 4969, 5079, 5718, 6194, 6574, 6929, 7849, 8167, 8579, 9730, 23, 602, 1283, 1558, 2634, 2972, 3259, 4103, 4276, 4970, 5080, 5719, 6195, 6575, 6930, 7850, 8168, 8580, 9731, 24, 603, 1284, 1559, 2635, 2973, 3260, 4104, 4277, 4971, 5081, 5720, 6196, 6576, 6931, 7851, 8169, 8581, 9732, 25, 604, 1285, 1560, 2636, 2974, 3261, 4105, 4278, 4972, 5082, 5721, 6197, 6577, 6932, 7852, 8170, 8582, 9733, 26, 605, 1286, 1561, 2637, 2975, 3262, 4106, 4279, 4973, 5083, 5722, 6198, 6578, 6933, 7853, 8171, 8583, 9734, 27, 606, 1287, 1562, 2638, 2976, 3263, 4107, 4280, 4974, 5084, 5723, 6199, 6579, 6934, 7854, 8172, 8584, 9735, 28, 607, 1288, 1563, 2639, 2977, 3264, 4108, 4281, 4975, 5085, 5724, 6200, 6580, 6935, 7855, 8173, 8585, 9736, 29, 608, 1289, 1564, 2640, 2978, 3265, 4109, 4282, 4976, 5086, 5725, 6201, 6581, 6936, 7856, 8174, 8586, 9737, 30, 609, 1290, 1565, 2641, 2979, 3266, 4110, 4283, 4977, 5087, 5726, 6202, 6582, 6937, 7857, 8175, 8587, 9738, 31, 610, 1291, 1566, 2642, 2980, 3267, 4111, 4284, 4978, 5088, 5727, 6203, 6583, 6938, 7858, 8176, 8588, 9739, 32, 611, 1292, 1567, 2643, 2981, 3268, 4112, 4285, 4979, 5089, 5728, 6204, 6584, 6939, 7859, 8177, 8589, 9740, 33, 612, 1293, 1568, 2644, 2982, 3269, 4113, 4286, 4980, 5090, 5729, 6205, 6585, 6940, 7860, 8178, 8590, 9741, 34, 613, 1294, 1569, 2645, 2983, 3270, 4114, 4287, 4981, 5091, 5730, 6206, 6586, 6941, 7861, 8179, 8591, 9742, 35, 614, 1295, 1570, 2646, 2984, 3271, 4115, 4288, 4982, 5092, 5731, 6207, 6587, 6942, 7862, 8180, 8592, 9743, 36, 615, 1296, 1571, 2647, 2985, 3272, 4116, 4289, 4983, 5093, 5732, 6208, 6588, 6943, 7863, 8181, 8593, 9744, 37, 616, 1297, 1572, 2648, 2986, 3273, 4117, 4290, 4984, 5094, 5733, 6209, 6589, 6944, 7864, 8182, 8594, 9745, 38, 617, 1298, 1573, 2649, 2987, 3274, 4118, 4291, 4985, 5095, 5734, 6210, 6590, 6945, 7865, 8183, 8595, 9746, 39, 618, 1299, 1574, 2650, 2988, 3275, 4119, 4292, 4986, 5096, 5735, 6211, 6591, 6946, 7866, 8184, 8596, 9747, 40, 619, 1300, 1575, 2651, 2989, 3276, 4120, 4293, 4987, 5097, 5736, 6212, 6592, 6947, 7867, 8185, 8597, 9748, 41, 620, 1301, 1576, 2652, 2990, 3277, 4121, 4294, 4988, 5098, 5737, 6213, 6593, 6948, 7868, 8186, 8598, 9749, 42, 621, 1302, 1577, 2653, 2991, 3278, 4122, 4295, 4989, 5099, 5738, 6214, 6594, 6949, 7869, 8187, 8599, 9750, 43, 622, 1303, 1578, 2654, 2992, 3279, 4123, 4296, 4990, 5100, 5739, 6215, 6595, 6950, 7870, 8188, 8600, 9751, 44, 623, 1304, 1579, 2655, 2993, 3280, 4124, 4297, 4991, 5101, 5740, 6216, 6596, 6951, 7871, 8189, 8601, 9752, 45, 624, 1305, 1580, 2656, 2994, 3281, 4125, 4298, 4608, 5102, 5741, 6217, 6597, 6952, 7872, 8190, 8602, 9753, 46, 625, 1306, 1581, 2657, 2995, 3282, 4126, 4299, 4609, 5103, 5742, 6218, 6598, 6953, 7873, 8191, 8603, 9754, 47, 626, 1307, 1582, 2658, 2996, 3283, 4127, 4300, 4610, 5104, 5743, 6219, 6599, 6954, 7874, 8192, 8604, 9755, 48, 627, 1308, 1583, 2659, 2997, 3284, 4128, 4301, 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8610, 25616, 353, 3039, 3508, 8611, 25617, 354, 3040, 3509, 8612, 25618, 355, 3041, 3510, 8613, 25619, 356, 3042, 3511, 8614, 25620, 357, 3043, 3512, 8615, 25621, 358, 3044, 3513, 8616, 25622, 359, 3045, 3514, 8617, 25623, 360, 3046, 3515, 8618, 25624, 361, 3047, 3516, 8619, 25625, 362, 3048, 3517, 8620, 25626, 363, 3049, 3518, 8621, 25627, 364, 3050, 3519, 8622, 25628, 365, 3051, 3520, 8623, 25629, 366, 3052, 3521, 8624, 25630, 367, 3053, 3522, 8625, 25631, 368, 3054, 3523, 8626, 25632, 369, 3055, 3524, 8627, 25633, 370, 3056, 3525, 8628, 25634, 371, 3057, 3526, 8629, 25635, 372, 3058, 3527, 8630, 25636, 373, 3059, 3528, 8631, 25637, 374, 3060, 3529, 8632, 25638, 375, 3061, 3530, 8633, 25639, 376, 3062, 3531, 8634, 25640, 377, 3063, 3532, 8635, 25641, 378, 3064, 3533, 8636, 25642, 379, 3065, 3534, 8637, 25643, 380, 3066, 3535, 8638, 25644, 381, 3067, 3536, 8639, 25645, 382, 3068, 3537, 8640, 25646, 383, 3069, 3538, 8641, 25647, 0, 3070, 3539, 8642, 25648, 1, 3071, 3540, 8643, 25649, 2, 2688, 3541, 8644, 25650, 3, 2689, 3542, 8645, 25651, 4, 2690, 3543, 8646, 25652, 5, 2691, 3544, 8647, 25653, 6, 2692, 3545, 8648, 25654, 7, 2693, 3546, 8649, 25655, 8, 2694, 3547, 8650, 25656, 9, 2695, 3548, 8651, 25657, 10, 2696, 3549, 8652, 25658, 11, 2697, 3550, 8653, 25659, 12, 2698, 3551, 8654, 25660, 13, 2699, 3552, 8655, 25661, 14, 2700, 3553, 8656, 25662, 15, 2701, 3554, 8657, 25663, 16, 2702, 3555, 8658, 25664, 17, 2703, 3556, 8659, 25665, 18, 2704, 3557, 8660, 25666, 19, 2705, 3558, 8661, 25667, 20, 2706, 3559, 8662, 25668, 21, 2707, 3560, 8663, 25669, 22, 2708, 3561, 8664, 25670, 23, 2709, 3562, 8665, 25671, 24, 2710, 3563, 8666, 25672, 25, 2711, 3564, 8667, 25673, 26, 2712, 3565, 8668, 25674, 27, 2713, 3566, 8669, 25675, 28, 2714, 3567, 8670, 25676, 29, 2715, 3568, 8671, 25677, 30, 2716, 3569, 8672, 25678, 31, 2717, 3570, 8673, 25679, 32, 2718, 3571, 8674, 25680, 33, 2719, 3572, 8675, 25681, 34, 2720, 3573, 8676, 25682, 35, 2721, 3574, 8677, 25683, 36, 2722, 3575, 8678, 25684, 37, 2723, 3576, 8679, 25685, 38, 2724, 3577, 8680, 25686, 39, 2725, 3578, 8681, 25687, 40, 2726, 3579, 8682, 25688, 41, 2727, 3580, 8683, 25689, 42, 2728, 3581, 8684, 25690, 43, 2729, 3582, 8685, 25691, 44, 2730, 3583, 8686, 25692, 45, 2731, 3584, 8687, 25693, 46, 2732, 3585, 8688, 25694, 47, 2733, 3586, 8689, 25695, 48, 2734, 3587, 8690, 25696, 49, 2735, 3588, 8691, 25697, 50, 2736, 3589, 8692, 25698, 51, 2737, 3590, 8693, 25699, 52, 2738, 3591, 8694, 25700, 53, 2739, 3592, 8695, 25701, 54, 2740, 3593, 8696, 25702, 55, 2741, 3594, 8697, 25703, 56, 2742, 3595, 8698, 25704, 57, 2743, 3596, 8699, 25705, 58, 2744, 3597, 8700, 25706, 59, 2745, 3598, 8701, 25707, 60, 2746, 3599, 8702, 25708, 61, 2747, 3600, 8703, 25709, 62, 2748, 3601, 8704, 25710, 63, 2749, 3602, 8705, 25711, 64, 2750, 3603, 8706, 25712, 65, 2751, 3604, 8707, 25713, 66, 2752, 3605, 8708, 25714, 67, 2753, 3606, 8709, 25715, 68, 2754, 3607, 8710, 25716, 69, 2755, 3608, 8711, 25717, 70, 2756, 3609, 8712, 25718, 71, 2757, 3610, 8713, 25719, 72, 2758, 3611, 8714, 25720, 73, 2759, 3612, 8715, 25721, 74, 2760, 3613, 8716, 25722, 75, 2761, 3614, 8717, 25723, 76, 2762, 3615, 8718, 25724, 77, 2763, 3616, 8719, 25725, 78, 2764, 3617, 8720, 25726, 79, 2765, 3618, 8721, 25727, 519, 2453, 3855, 25728, 520, 2454, 3856, 25729, 521, 2455, 3857, 25730, 522, 2456, 3858, 25731, 523, 2457, 3859, 25732, 524, 2458, 3860, 25733, 525, 2459, 3861, 25734, 526, 2460, 3862, 25735, 527, 2461, 3863, 25736, 528, 2462, 3864, 25737, 529, 2463, 3865, 25738, 530, 2464, 3866, 25739, 531, 2465, 3867, 25740, 532, 2466, 3868, 25741, 533, 2467, 3869, 25742, 534, 2468, 3870, 25743, 535, 2469, 3871, 25744, 536, 2470, 3872, 25745, 537, 2471, 3873, 25746, 538, 2472, 3874, 25747, 539, 2473, 3875, 25748, 540, 2474, 3876, 25749, 541, 2475, 3877, 25750, 542, 2476, 3878, 25751, 543, 2477, 3879, 25752, 544, 2478, 3880, 25753, 545, 2479, 3881, 25754, 546, 2480, 3882, 25755, 547, 2481, 3883, 25756, 548, 2482, 3884, 25757, 549, 2483, 3885, 25758, 550, 2484, 3886, 25759, 551, 2485, 3887, 25760, 552, 2486, 3888, 25761, 553, 2487, 3889, 25762, 554, 2488, 3890, 25763, 555, 2489, 3891, 25764, 556, 2490, 3892, 25765, 557, 2491, 3893, 25766, 558, 2492, 3894, 25767, 559, 2493, 3895, 25768, 560, 2494, 3896, 25769, 561, 2495, 3897, 25770, 562, 2496, 3898, 25771, 563, 2497, 3899, 25772, 564, 2498, 3900, 25773, 565, 2499, 3901, 25774, 566, 2500, 3902, 25775, 567, 2501, 3903, 25776, 568, 2502, 3904, 25777, 569, 2503, 3905, 25778, 570, 2504, 3906, 25779, 571, 2505, 3907, 25780, 572, 2506, 3908, 25781, 573, 2507, 3909, 25782, 574, 2508, 3910, 25783, 575, 2509, 3911, 25784, 576, 2510, 3912, 25785, 577, 2511, 3913, 25786, 578, 2512, 3914, 25787, 579, 2513, 3915, 25788, 580, 2514, 3916, 25789, 581, 2515, 3917, 25790, 582, 2516, 3918, 25791, 583, 2517, 3919, 25792, 584, 2518, 3920, 25793, 585, 2519, 3921, 25794, 586, 2520, 3922, 25795, 587, 2521, 3923, 25796, 588, 2522, 3924, 25797, 589, 2523, 3925, 25798, 590, 2524, 3926, 25799, 591, 2525, 3927, 25800, 592, 2526, 3928, 25801, 593, 2527, 3929, 25802, 594, 2528, 3930, 25803, 595, 2529, 3931, 25804, 596, 2530, 3932, 25805, 597, 2531, 3933, 25806, 598, 2532, 3934, 25807, 599, 2533, 3935, 25808, 600, 2534, 3936, 25809, 601, 2535, 3937, 25810, 602, 2536, 3938, 25811, 603, 2537, 3939, 25812, 604, 2538, 3940, 25813, 605, 2539, 3941, 25814, 606, 2540, 3942, 25815, 607, 2541, 3943, 25816, 608, 2542, 3944, 25817, 609, 2543, 3945, 25818, 610, 2544, 3946, 25819, 611, 2545, 3947, 25820, 612, 2546, 3948, 25821, 613, 2547, 3949, 25822, 614, 2548, 3950, 25823, 615, 2549, 3951, 25824, 616, 2550, 3952, 25825, 617, 2551, 3953, 25826, 618, 2552, 3954, 25827, 619, 2553, 3955, 25828, 620, 2554, 3956, 25829, 621, 2555, 3957, 25830, 622, 2556, 3958, 25831, 623, 2557, 3959, 25832, 624, 2558, 3960, 25833, 625, 2559, 3961, 25834, 626, 2560, 3962, 25835, 627, 2561, 3963, 25836, 628, 2562, 3964, 25837, 629, 2563, 3965, 25838, 630, 2564, 3966, 25839, 631, 2565, 3967, 25840, 632, 2566, 3968, 25841, 633, 2567, 3969, 25842, 634, 2568, 3970, 25843, 635, 2569, 3971, 25844, 636, 2570, 3972, 25845, 637, 2571, 3973, 25846, 638, 2572, 3974, 25847, 639, 2573, 3975, 25848, 640, 2574, 3976, 25849, 641, 2575, 3977, 25850, 642, 2576, 3978, 25851, 643, 2577, 3979, 25852, 644, 2578, 3980, 25853, 645, 2579, 3981, 25854, 646, 2580, 3982, 25855, 647, 2581, 3983, 25856, 648, 2582, 3984, 25857, 649, 2583, 3985, 25858, 650, 2584, 3986, 25859, 651, 2585, 3987, 25860, 652, 2586, 3988, 25861, 653, 2587, 3989, 25862, 654, 2588, 3990, 25863, 655, 2589, 3991, 25864, 656, 2590, 3992, 25865, 657, 2591, 3993, 25866, 658, 2592, 3994, 25867, 659, 2593, 3995, 25868, 660, 2594, 3996, 25869, 661, 2595, 3997, 25870, 662, 2596, 3998, 25871, 663, 2597, 3999, 25872, 664, 2598, 4000, 25873, 665, 2599, 4001, 25874, 666, 2600, 4002, 25875, 667, 2601, 4003, 25876, 668, 2602, 4004, 25877, 669, 2603, 4005, 25878, 670, 2604, 4006, 25879, 671, 2605, 4007, 25880, 672, 2606, 4008, 25881, 673, 2607, 4009, 25882, 674, 2608, 4010, 25883, 675, 2609, 4011, 25884, 676, 2610, 4012, 25885, 677, 2611, 4013, 25886, 678, 2612, 4014, 25887, 679, 2613, 4015, 25888, 680, 2614, 4016, 25889, 681, 2615, 4017, 25890, 682, 2616, 4018, 25891, 683, 2617, 4019, 25892, 684, 2618, 4020, 25893, 685, 2619, 4021, 25894, 686, 2620, 4022, 25895, 687, 2621, 4023, 25896, 688, 2622, 4024, 25897, 689, 2623, 4025, 25898, 690, 2624, 4026, 25899, 691, 2625, 4027, 25900, 692, 2626, 4028, 25901, 693, 2627, 4029, 25902, 694, 2628, 4030, 25903, 695, 2629, 4031, 25904, 696, 2630, 4032, 25905, 697, 2631, 4033, 25906, 698, 2632, 4034, 25907, 699, 2633, 4035, 25908, 700, 2634, 4036, 25909, 701, 2635, 4037, 25910, 702, 2636, 4038, 25911, 703, 2637, 4039, 25912, 704, 2638, 4040, 25913, 705, 2639, 4041, 25914, 706, 2640, 4042, 25915, 707, 2641, 4043, 25916, 708, 2642, 4044, 25917, 709, 2643, 4045, 25918, 710, 2644, 4046, 25919, 711, 2645, 4047, 25920, 712, 2646, 4048, 25921, 713, 2647, 4049, 25922, 714, 2648, 4050, 25923, 715, 2649, 4051, 25924, 716, 2650, 4052, 25925, 717, 2651, 4053, 25926, 718, 2652, 4054, 25927, 719, 2653, 4055, 25928, 720, 2654, 4056, 25929, 721, 2655, 4057, 25930, 722, 2656, 4058, 25931, 723, 2657, 4059, 25932, 724, 2658, 4060, 25933, 725, 2659, 4061, 25934, 726, 2660, 4062, 25935, 727, 2661, 4063, 25936, 728, 2662, 4064, 25937, 729, 2663, 4065, 25938, 730, 2664, 4066, 25939, 731, 2665, 4067, 25940, 732, 2666, 4068, 25941, 733, 2667, 4069, 25942, 734, 2668, 4070, 25943, 735, 2669, 4071, 25944, 736, 2670, 4072, 25945, 737, 2671, 4073, 25946, 738, 2672, 4074, 25947, 739, 2673, 4075, 25948, 740, 2674, 4076, 25949, 741, 2675, 4077, 25950, 742, 2676, 4078, 25951, 743, 2677, 4079, 25952, 744, 2678, 4080, 25953, 745, 2679, 4081, 25954, 746, 2680, 4082, 25955, 747, 2681, 4083, 25956, 748, 2682, 4084, 25957, 749, 2683, 4085, 25958, 750, 2684, 4086, 25959, 751, 2685, 4087, 25960, 752, 2686, 4088, 25961, 753, 2687, 4089, 25962, 754, 2304, 4090, 25963, 755, 2305, 4091, 25964, 756, 2306, 4092, 25965, 757, 2307, 4093, 25966, 758, 2308, 4094, 25967, 759, 2309, 4095, 25968, 760, 2310, 4096, 25969, 761, 2311, 4097, 25970, 762, 2312, 4098, 25971, 763, 2313, 4099, 25972, 764, 2314, 4100, 25973, 765, 2315, 4101, 25974, 766, 2316, 4102, 25975, 767, 2317, 4103, 25976, 384, 2318, 4104, 25977, 385, 2319, 4105, 25978, 386, 2320, 4106, 25979, 387, 2321, 4107, 25980, 388, 2322, 4108, 25981, 389, 2323, 4109, 25982, 390, 2324, 4110, 25983, 391, 2325, 4111, 25984, 392, 2326, 4112, 25985, 393, 2327, 4113, 25986, 394, 2328, 4114, 25987, 395, 2329, 4115, 25988, 396, 2330, 4116, 25989, 397, 2331, 4117, 25990, 398, 2332, 4118, 25991, 399, 2333, 4119, 25992, 400, 2334, 4120, 25993, 401, 2335, 4121, 25994, 402, 2336, 4122, 25995, 403, 2337, 4123, 25996, 404, 2338, 4124, 25997, 405, 2339, 4125, 25998, 406, 2340, 4126, 25999, 407, 2341, 4127, 26000, 408, 2342, 4128, 26001, 409, 2343, 4129, 26002, 410, 2344, 4130, 26003, 411, 2345, 4131, 26004, 412, 2346, 4132, 26005, 413, 2347, 4133, 26006, 414, 2348, 4134, 26007, 415, 2349, 4135, 26008, 416, 2350, 4136, 26009, 417, 2351, 4137, 26010, 418, 2352, 4138, 26011, 419, 2353, 4139, 26012, 420, 2354, 4140, 26013, 421, 2355, 4141, 26014, 422, 2356, 4142, 26015, 423, 2357, 4143, 26016, 424, 2358, 4144, 26017, 425, 2359, 4145, 26018, 426, 2360, 4146, 26019, 427, 2361, 4147, 26020, 428, 2362, 4148, 26021, 429, 2363, 4149, 26022, 430, 2364, 4150, 26023, 431, 2365, 4151, 26024, 432, 2366, 4152, 26025, 433, 2367, 4153, 26026, 434, 2368, 4154, 26027, 435, 2369, 4155, 26028, 436, 2370, 4156, 26029, 437, 2371, 4157, 26030, 438, 2372, 4158, 26031, 439, 2373, 4159, 26032, 440, 2374, 4160, 26033, 441, 2375, 4161, 26034, 442, 2376, 4162, 26035, 443, 2377, 4163, 26036, 444, 2378, 4164, 26037, 445, 2379, 4165, 26038, 446, 2380, 4166, 26039, 447, 2381, 4167, 26040, 448, 2382, 4168, 26041, 449, 2383, 4169, 26042, 450, 2384, 4170, 26043, 451, 2385, 4171, 26044, 452, 2386, 4172, 26045, 453, 2387, 4173, 26046, 454, 2388, 4174, 26047, 455, 2389, 4175, 26048, 456, 2390, 4176, 26049, 457, 2391, 4177, 26050, 458, 2392, 4178, 26051, 459, 2393, 4179, 26052, 460, 2394, 4180, 26053, 461, 2395, 4181, 26054, 462, 2396, 4182, 26055, 463, 2397, 4183, 26056, 464, 2398, 4184, 26057, 465, 2399, 4185, 26058, 466, 2400, 4186, 26059, 467, 2401, 4187, 26060, 468, 2402, 4188, 26061, 469, 2403, 4189, 26062, 470, 2404, 4190, 26063, 471, 2405, 4191, 26064, 472, 2406, 4192, 26065, 473, 2407, 4193, 26066, 474, 2408, 4194, 26067, 475, 2409, 4195, 26068, 476, 2410, 4196, 26069, 477, 2411, 4197, 26070, 478, 2412, 4198, 26071, 479, 2413, 4199, 26072, 480, 2414, 4200, 26073, 481, 2415, 4201, 26074, 482, 2416, 4202, 26075, 483, 2417, 4203, 26076, 484, 2418, 4204, 26077, 485, 2419, 4205, 26078, 486, 2420, 4206, 26079, 487, 2421, 4207, 26080, 488, 2422, 4208, 26081, 489, 2423, 4209, 26082, 490, 2424, 4210, 26083, 491, 2425, 4211, 26084, 492, 2426, 4212, 26085, 493, 2427, 4213, 26086, 494, 2428, 4214, 26087, 495, 2429, 4215, 26088, 496, 2430, 4216, 26089, 497, 2431, 4217, 26090, 498, 2432, 4218, 26091, 499, 2433, 4219, 26092, 500, 2434, 4220, 26093, 501, 2435, 4221, 26094, 502, 2436, 4222, 26095, 503, 2437, 4223, 26096, 504, 2438, 3840, 26097, 505, 2439, 3841, 26098, 506, 2440, 3842, 26099, 507, 2441, 3843, 26100, 508, 2442, 3844, 26101, 509, 2443, 3845, 26102, 510, 2444, 3846, 26103, 511, 2445, 3847, 26104, 512, 2446, 3848, 26105, 513, 2447, 3849, 26106, 514, 2448, 3850, 26107, 515, 2449, 3851, 26108, 516, 2450, 3852, 26109, 517, 2451, 3853, 26110, 518, 2452, 3854, 26111}; +int c2b_idx[121344] = { 1463, 13148, 17993, 23940, 29340, 31848, 34362, 39489, 40322, 43554, 52224, 54757, 55722, 59294, 61289, 66024, 71322, 73374, 78570, 81156, 86429, 89130, 93285, 97410, 100610, 104550, 108131, 111812, 115516, 119408, 1482, 13167, 18012, 23959, 29343, 31856, 34371, 39496, 40332, 43563, 52232, 54764, 55728, 59301, 61296, 66030, 71328, 73380, 78575, 81162, 86434, 89135, 93290, 97415, 100615, 104555, 108136, 111816, 115520, 119413, 1501, 13186, 18031, 23978, 29346, 31864, 34380, 39503, 40342, 43572, 52240, 54771, 55734, 59308, 61303, 66036, 71334, 73386, 78580, 81168, 86439, 89140, 93295, 97420, 100620, 104560, 108141, 111820, 115524, 119418, 1520, 13205, 18050, 23997, 29349, 31872, 34389, 39510, 40352, 43581, 52248, 54778, 55740, 59315, 61310, 66042, 71340, 73392, 78585, 81174, 86444, 89145, 93300, 97425, 100625, 104565, 108146, 111824, 115528, 119423, 1539, 13224, 18069, 24016, 29352, 31880, 34398, 39517, 40362, 43590, 52256, 54785, 55746, 59322, 61317, 66048, 71346, 73398, 78590, 81180, 86449, 89150, 93305, 97430, 100630, 104570, 108151, 111828, 115532, 119428, 1558, 13243, 18088, 24035, 29355, 31888, 34407, 39524, 40372, 43599, 52264, 54792, 55752, 59329, 61324, 66054, 71352, 73404, 78595, 81186, 86454, 89155, 93310, 97435, 100635, 104575, 108156, 111832, 115536, 119433, 1577, 13262, 18107, 24054, 29358, 31896, 34416, 39531, 40382, 43608, 52272, 54799, 55758, 59336, 61331, 66060, 71358, 73410, 78600, 81192, 86459, 89160, 93315, 97440, 100640, 104580, 108161, 111836, 115540, 119438, 1596, 13281, 18126, 24073, 29361, 31904, 34425, 39538, 40392, 43617, 52280, 54806, 55764, 59343, 61338, 66066, 71364, 73416, 78605, 81198, 86464, 89165, 93320, 97445, 100645, 104585, 108166, 111840, 115544, 119443, 1615, 13300, 18145, 24092, 29364, 31912, 34434, 39545, 40402, 43626, 52288, 54813, 55770, 59350, 61345, 66072, 71370, 73422, 78610, 81204, 86469, 89170, 93325, 97450, 100650, 104590, 108171, 111844, 115548, 119448, 1634, 13319, 18164, 24111, 29367, 31920, 34443, 36864, 40412, 43635, 52296, 54820, 55776, 59357, 61352, 66078, 71376, 73428, 78615, 81210, 86474, 89175, 93330, 97455, 100655, 104595, 108176, 111848, 115552, 119453, 1653, 13338, 18183, 24130, 29370, 31928, 34452, 36871, 40422, 43644, 52304, 54827, 55782, 59364, 61359, 66084, 71382, 73434, 78620, 81216, 86479, 89180, 93335, 97460, 100660, 104600, 108181, 111852, 115556, 119458, 1672, 13357, 18202, 24149, 29373, 31936, 34461, 36878, 40432, 43653, 52312, 54834, 55788, 59371, 61366, 66090, 71388, 73440, 78625, 81222, 86484, 89185, 93340, 97465, 100665, 104605, 108186, 111856, 115560, 119463, 1691, 13376, 18221, 24168, 29376, 31944, 34470, 36885, 40442, 43662, 52320, 54841, 55794, 59378, 61373, 66096, 71394, 73446, 78630, 81228, 86489, 89190, 93345, 97470, 100670, 104610, 108191, 111860, 115564, 119468, 1710, 13395, 18240, 24187, 29379, 31952, 34479, 36892, 40452, 43671, 52328, 54848, 55800, 59385, 61380, 66102, 71400, 73452, 78635, 81234, 86494, 89195, 93350, 97475, 100675, 104615, 108196, 111864, 115568, 119473, 1729, 13414, 18259, 24206, 29382, 31960, 34488, 36899, 40462, 43680, 52336, 54855, 55806, 59392, 61387, 66108, 71406, 73458, 78640, 81240, 86499, 89200, 93355, 97480, 100680, 104620, 108201, 111868, 115572, 119478, 1748, 13433, 18278, 24225, 29385, 31968, 34497, 36906, 40472, 43689, 52344, 54862, 55812, 59399, 61394, 66114, 71412, 73464, 78645, 81246, 86504, 89205, 93360, 97485, 100685, 104625, 108206, 111872, 115576, 119483, 1767, 13452, 18297, 24244, 29388, 31976, 34506, 36913, 40482, 43698, 52352, 54869, 55818, 59406, 61401, 66120, 71418, 73470, 78650, 81252, 86509, 89210, 93365, 97490, 100690, 104630, 108211, 111876, 115580, 119488, 1786, 13471, 18316, 24263, 29391, 31984, 34515, 36920, 40492, 43707, 52360, 54876, 55824, 59413, 61408, 66126, 71424, 73476, 78655, 81258, 86514, 89215, 93370, 97495, 100695, 104635, 108216, 111880, 115584, 119493, 1805, 13490, 18335, 24282, 29394, 31992, 34524, 36927, 40502, 43716, 52368, 54883, 55830, 59420, 61415, 66132, 71430, 73482, 78660, 81264, 86519, 89220, 93375, 97500, 100700, 104640, 108221, 111884, 115588, 119498, 1824, 13509, 18354, 24301, 29397, 32000, 34533, 36934, 40512, 43725, 52376, 54890, 55836, 59427, 61422, 66138, 71436, 73488, 78665, 81270, 86524, 89225, 93380, 97505, 100705, 104645, 108226, 111888, 115592, 119503, 1843, 13528, 18373, 24320, 29400, 32008, 34542, 36941, 40522, 43734, 52384, 54897, 55842, 59434, 61429, 66144, 71442, 73494, 78670, 81276, 86529, 89230, 93385, 97510, 100710, 104650, 108231, 111892, 115596, 119508, 1862, 13547, 18392, 24339, 29403, 32016, 34551, 36948, 40532, 43743, 52392, 54904, 55848, 59441, 61436, 66150, 71448, 73500, 78675, 81282, 86534, 89235, 93390, 97515, 100715, 104655, 108236, 111896, 115600, 119513, 1881, 13566, 18411, 24358, 29406, 32024, 34560, 36955, 40542, 43752, 52400, 54911, 55854, 59448, 61443, 66156, 71454, 73506, 78680, 81288, 86539, 89240, 93395, 97520, 100720, 104660, 108241, 111900, 115604, 119518, 1900, 13585, 18430, 24377, 29409, 32032, 34569, 36962, 40552, 43761, 52408, 54918, 55860, 59455, 61450, 66162, 71460, 73512, 78685, 81294, 86544, 89245, 93400, 97525, 100725, 104665, 108246, 111904, 115608, 119523, 1919, 13604, 18449, 24396, 29412, 32040, 34578, 36969, 40562, 43770, 52416, 54925, 55866, 59462, 61457, 66168, 71466, 73518, 78690, 81300, 86549, 89250, 93405, 97530, 100730, 104670, 108251, 111908, 115612, 119528, 1938, 13623, 18468, 24415, 29415, 32048, 34587, 36976, 40572, 43779, 52424, 54932, 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111039, 111043, 111047, 111051, 111055, 111059, 111063, 111067, 111071, 111075, 111079, 111083, 111087, 111091, 111095, 111099, 111103, 111107, 111111, 111115, 111119, 111123, 111127, 111131, 111135, 111139, 111143, 111147, 111151, 111155, 111159, 111163, 111167, 111171, 111175, 111179, 111183, 111187, 111191, 111195, 111199, 111203, 111207, 111211, 111215, 111219, 111223, 111227, 111231, 111235, 111239, 111243, 111247, 111251, 111255, 111259, 111263, 111267, 111271, 111275, 111279, 111283, 111287, 111291, 111295, 111299, 111303, 111307, 111311, 111315, 111319, 111323, 111327, 111331, 111335, 111339, 111343, 111347, 111351, 111355, 111359, 111363, 111367, 111371, 111375, 111379, 111383, 111387, 111391, 111395, 111399, 111403, 111407, 111411, 111415, 111419, 111423, 111427, 111431, 111435, 111439, 111443, 111447, 111451, 111455, 111459, 111463, 111467, 111471, 111475, 111479, 111483, 111487, 111491, 111495, 111499, 111503, 111507, 111511, 111515, 111519, 111523, 111527, 111531, 111535, 111539, 111543, 111547, 111551, 111555, 111559, 111563, 111567, 111571, 111575, 111579, 111583, 111587, 111591, 111595, 111599, 111603, 111607, 111611, 111615, 111619, 111623, 111627, 111631, 111635, 111639, 111643, 111647, 111651, 111655, 111659, 111663, 111667, 111671, 111675, 111679, 111683, 111687, 111691, 111695, 111699, 111703, 111707, 111711, 111715, 111719, 111723, 111727, 111731, 111735, 111739, 111743, 111747, 111751, 111755, 111759, 111763, 111767, 111771, 111775, 111779, 111783, 111787, 111791, 111795, 111799, 111803, 111807, 111811, 111815, 111819, 111823, 111827, 111831, 111835, 111839, 111843, 111847, 111851, 111855, 111859, 111863, 111867, 111871, 111875, 111879, 111883, 111887, 111891, 111895, 111899, 111903, 111907, 111911, 111915, 111919, 111923, 111927, 111931, 111935, 111939, 111943, 111947, 111951, 111955, 111959, 111963, 111967, 111971, 111975, 111979, 111983, 111987, 111991, 111995, 111999, 112003, 112007, 112011, 112015, 112019, 112023, 112027, 112031, 112035, 112039, 112043, 112047, 112051, 112055, 112059, 112063, 112067, 112071, 112075, 112079, 112083, 112087, 112091, 112095, 112099, 112103, 112107, 112111, 112115, 112119, 112123, 112127, 112131, 112135, 112139, 112143, 112147, 112151, 112155, 112159, 112163, 112167, 112171, 112175, 112179, 112183, 112187, 112191, 112195, 112199, 112203, 112207, 112211, 112215, 112219, 112223, 112227, 112231, 112235, 112239, 112243, 112247, 112251, 112255, 112259, 112263, 112267, 112271, 112275, 112279, 112283, 112287, 112291, 112295, 112299, 112303, 112307, 112311, 112315, 112319, 112323, 112327, 112331, 112335, 112339, 112343, 112347, 112351, 112355, 112359, 112363, 112367, 112371, 112375, 112379, 112383, 112387, 112391, 112395, 112399, 112403, 112407, 112411, 112415, 112419, 112423, 112427, 112431, 112435, 112439, 112443, 112447, 112451, 112455, 112459, 112463, 112467, 112471, 112475, 112479, 112483, 112487, 112491, 112495, 112499, 112503, 112507, 112511, 112516, 112521, 112526, 112531, 112536, 112541, 112546, 112551, 112556, 112561, 112566, 112571, 112576, 112581, 112586, 112591, 112596, 112601, 112606, 112611, 112616, 112621, 112626, 112631, 112636, 112641, 112646, 112651, 112656, 112661, 112666, 112671, 112676, 112681, 112686, 112691, 112696, 112701, 112706, 112711, 112716, 112721, 112726, 112731, 112736, 112741, 112746, 112751, 112756, 112761, 112766, 112771, 112776, 112781, 112786, 112791, 112796, 112801, 112806, 112811, 112816, 112821, 112826, 112831, 112836, 112841, 112846, 112851, 112856, 112861, 112866, 112871, 112876, 112881, 112886, 112891, 112896, 112901, 112906, 112911, 112916, 112921, 112926, 112931, 112936, 112941, 112946, 112951, 112956, 112961, 112966, 112971, 112976, 112981, 112986, 112991, 112996, 113001, 113006, 113011, 113016, 113021, 113026, 113031, 113036, 113041, 113046, 113051, 113056, 113061, 113066, 113071, 113076, 113081, 113086, 113091, 113096, 113101, 113106, 113111, 113116, 113121, 113126, 113131, 113136, 113141, 113146, 113151, 113156, 113161, 113166, 113171, 113176, 113181, 113186, 113191, 113196, 113201, 113206, 113211, 113216, 113221, 113226, 113231, 113236, 113241, 113246, 113251, 113256, 113261, 113266, 113271, 113276, 113281, 113286, 113291, 113296, 113301, 113306, 113311, 113316, 113321, 113326, 113331, 113336, 113341, 113346, 113351, 113356, 113361, 113366, 113371, 113376, 113381, 113386, 113391, 113396, 113401, 113406, 113411, 113416, 113421, 113426, 113431, 113436, 113441, 113446, 113451, 113456, 113461, 113466, 113471, 113476, 113481, 113486, 113491, 113496, 113501, 113506, 113511, 113516, 113521, 113526, 113531, 113536, 113541, 113546, 113551, 113556, 113561, 113566, 113571, 113576, 113581, 113586, 113591, 113596, 113601, 113606, 113611, 113616, 113621, 113626, 113631, 113636, 113641, 113646, 113651, 113656, 113661, 113666, 113671, 113676, 113681, 113686, 113691, 113696, 113701, 113706, 113711, 113716, 113721, 113726, 113731, 113736, 113741, 113746, 113751, 113756, 113761, 113766, 113771, 113776, 113781, 113786, 113791, 113796, 113801, 113806, 113811, 113816, 113821, 113826, 113831, 113836, 113841, 113846, 113851, 113856, 113861, 113866, 113871, 113876, 113881, 113886, 113891, 113896, 113901, 113906, 113911, 113916, 113921, 113926, 113931, 113936, 113941, 113946, 113951, 113956, 113961, 113966, 113971, 113976, 113981, 113986, 113991, 113996, 114001, 114006, 114011, 114016, 114021, 114026, 114031, 114036, 114041, 114046, 114051, 114056, 114061, 114066, 114071, 114076, 114081, 114086, 114091, 114096, 114101, 114106, 114111, 114116, 114121, 114126, 114131, 114136, 114141, 114146, 114151, 114156, 114161, 114166, 114171, 114176, 114181, 114186, 114191, 114196, 114201, 114206, 114211, 114216, 114221, 114226, 114231, 114236, 114241, 114246, 114251, 114256, 114261, 114266, 114271, 114276, 114281, 114286, 114291, 114296, 114301, 114306, 114311, 114316, 114321, 114326, 114331, 114336, 114341, 114346, 114351, 114356, 114361, 114366, 114371, 114376, 114381, 114386, 114391, 114396, 114401, 114406, 114411, 114416, 114421, 114426, 114431, 114435, 114439, 114443, 114447, 114451, 114455, 114459, 114463, 114467, 114471, 114475, 114479, 114483, 114487, 114491, 114495, 114499, 114503, 114507, 114511, 114515, 114519, 114523, 114527, 114531, 114535, 114539, 114543, 114547, 114551, 114555, 114559, 114563, 114567, 114571, 114575, 114579, 114583, 114587, 114591, 114595, 114599, 114603, 114607, 114611, 114615, 114619, 114623, 114627, 114631, 114635, 114639, 114643, 114647, 114651, 114655, 114659, 114663, 114667, 114671, 114675, 114679, 114683, 114687, 114691, 114695, 114699, 114703, 114707, 114711, 114715, 114719, 114723, 114727, 114731, 114735, 114739, 114743, 114747, 114751, 114755, 114759, 114763, 114767, 114771, 114775, 114779, 114783, 114787, 114791, 114795, 114799, 114803, 114807, 114811, 114815, 114819, 114823, 114827, 114831, 114835, 114839, 114843, 114847, 114851, 114855, 114859, 114863, 114867, 114871, 114875, 114879, 114883, 114887, 114891, 114895, 114899, 114903, 114907, 114911, 114915, 114919, 114923, 114927, 114931, 114935, 114939, 114943, 114947, 114951, 114955, 114959, 114963, 114967, 114971, 114975, 114979, 114983, 114987, 114991, 114995, 114999, 115003, 115007, 115011, 115015, 115019, 115023, 115027, 115031, 115035, 115039, 115043, 115047, 115051, 115055, 115059, 115063, 115067, 115071, 115075, 115079, 115083, 115087, 115091, 115095, 115099, 115103, 115107, 115111, 115115, 115119, 115123, 115127, 115131, 115135, 115139, 115143, 115147, 115151, 115155, 115159, 115163, 115167, 115171, 115175, 115179, 115183, 115187, 115191, 115195, 115199, 115203, 115207, 115211, 115215, 115219, 115223, 115227, 115231, 115235, 115239, 115243, 115247, 115251, 115255, 115259, 115263, 115267, 115271, 115275, 115279, 115283, 115287, 115291, 115295, 115299, 115303, 115307, 115311, 115315, 115319, 115323, 115327, 115331, 115335, 115339, 115343, 115347, 115351, 115355, 115359, 115363, 115367, 115371, 115375, 115379, 115383, 115387, 115391, 115395, 115399, 115403, 115407, 115411, 115415, 115419, 115423, 115427, 115431, 115435, 115439, 115443, 115447, 115451, 115455, 115459, 115463, 115467, 115471, 115475, 115479, 115483, 115487, 115491, 115495, 115499, 115503, 115507, 115511, 115515, 115519, 115523, 115527, 115531, 115535, 115539, 115543, 115547, 115551, 115555, 115559, 115563, 115567, 115571, 115575, 115579, 115583, 115587, 115591, 115595, 115599, 115603, 115607, 115611, 115615, 115619, 115623, 115627, 115631, 115635, 115639, 115643, 115647, 115651, 115655, 115659, 115663, 115667, 115671, 115675, 115679, 115683, 115687, 115691, 115695, 115699, 115703, 115707, 115711, 115715, 115719, 115723, 115727, 115731, 115735, 115739, 115743, 115747, 115751, 115755, 115759, 115763, 115767, 115771, 115775, 115779, 115783, 115787, 115791, 115795, 115799, 115803, 115807, 115811, 115815, 115819, 115823, 115827, 115831, 115835, 115839, 115843, 115847, 115851, 115855, 115859, 115863, 115867, 115871, 115875, 115879, 115883, 115887, 115891, 115895, 115899, 115903, 115907, 115911, 115915, 115919, 115923, 115927, 115931, 115935, 115939, 115943, 115947, 115951, 115955, 115959, 115963, 115967, 115972, 115977, 115982, 115987, 115992, 115997, 116002, 116007, 116012, 116017, 116022, 116027, 116032, 116037, 116042, 116047, 116052, 116057, 116062, 116067, 116072, 116077, 116082, 116087, 116092, 116097, 116102, 116107, 116112, 116117, 116122, 116127, 116132, 116137, 116142, 116147, 116152, 116157, 116162, 116167, 116172, 116177, 116182, 116187, 116192, 116197, 116202, 116207, 116212, 116217, 116222, 116227, 116232, 116237, 116242, 116247, 116252, 116257, 116262, 116267, 116272, 116277, 116282, 116287, 116292, 116297, 116302, 116307, 116312, 116317, 116322, 116327, 116332, 116337, 116342, 116347, 116352, 116357, 116362, 116367, 116372, 116377, 116382, 116387, 116392, 116397, 116402, 116407, 116412, 116417, 116422, 116427, 116432, 116437, 116442, 116447, 116452, 116457, 116462, 116467, 116472, 116477, 116482, 116487, 116492, 116497, 116502, 116507, 116512, 116517, 116522, 116527, 116532, 116537, 116542, 116547, 116552, 116557, 116562, 116567, 116572, 116577, 116582, 116587, 116592, 116597, 116602, 116607, 116612, 116617, 116622, 116627, 116632, 116637, 116642, 116647, 116652, 116657, 116662, 116667, 116672, 116677, 116682, 116687, 116692, 116697, 116702, 116707, 116712, 116717, 116722, 116727, 116732, 116737, 116742, 116747, 116752, 116757, 116762, 116767, 116772, 116777, 116782, 116787, 116792, 116797, 116802, 116807, 116812, 116817, 116822, 116827, 116832, 116837, 116842, 116847, 116852, 116857, 116862, 116867, 116872, 116877, 116882, 116887, 116892, 116897, 116902, 116907, 116912, 116917, 116922, 116927, 116932, 116937, 116942, 116947, 116952, 116957, 116962, 116967, 116972, 116977, 116982, 116987, 116992, 116997, 117002, 117007, 117012, 117017, 117022, 117027, 117032, 117037, 117042, 117047, 117052, 117057, 117062, 117067, 117072, 117077, 117082, 117087, 117092, 117097, 117102, 117107, 117112, 117117, 117122, 117127, 117132, 117137, 117142, 117147, 117152, 117157, 117162, 117167, 117172, 117177, 117182, 117187, 117192, 117197, 117202, 117207, 117212, 117217, 117222, 117227, 117232, 117237, 117242, 117247, 117252, 117257, 117262, 117267, 117272, 117277, 117282, 117287, 117292, 117297, 117302, 117307, 117312, 117317, 117322, 117327, 117332, 117337, 117342, 117347, 117352, 117357, 117362, 117367, 117372, 117377, 117382, 117387, 117392, 117397, 117402, 117407, 117412, 117417, 117422, 117427, 117432, 117437, 117442, 117447, 117452, 117457, 117462, 117467, 117472, 117477, 117482, 117487, 117492, 117497, 117502, 117507, 117512, 117517, 117522, 117527, 117532, 117537, 117542, 117547, 117552, 117557, 117562, 117567, 117572, 117577, 117582, 117587, 117592, 117597, 117602, 117607, 117612, 117617, 117622, 117627, 117632, 117637, 117642, 117647, 117652, 117657, 117662, 117667, 117672, 117677, 117682, 117687, 117692, 117697, 117702, 117707, 117712, 117717, 117722, 117727, 117732, 117737, 117742, 117747, 117752, 117757, 117762, 117767, 117772, 117777, 117782, 117787, 117792, 117797, 117802, 117807, 117812, 117817, 117822, 117827, 117832, 117837, 117842, 117847, 117852, 117857, 117862, 117867, 117872, 117877, 117882, 117887, 117892, 117897, 117902, 117907, 117912, 117917, 117922, 117927, 117932, 117937, 117942, 117947, 117952, 117957, 117962, 117967, 117972, 117977, 117982, 117987, 117992, 117997, 118002, 118007, 118012, 118017, 118022, 118027, 118032, 118037, 118042, 118047, 118052, 118057, 118062, 118067, 118072, 118077, 118082, 118087, 118092, 118097, 118102, 118107, 118112, 118117, 118122, 118127, 118132, 118137, 118142, 118147, 118152, 118157, 118162, 118167, 118172, 118177, 118182, 118187, 118192, 118197, 118202, 118207, 118212, 118217, 118222, 118227, 118232, 118237, 118242, 118247, 118252, 118257, 118262, 118267, 118272, 118277, 118282, 118287, 118292, 118297, 118302, 118307, 118312, 118317, 118322, 118327, 118332, 118337, 118342, 118347, 118352, 118357, 118362, 118367, 118372, 118377, 118382, 118387, 118392, 118397, 118402, 118407, 118412, 118417, 118422, 118427, 118432, 118437, 118442, 118447, 118452, 118457, 118462, 118467, 118472, 118477, 118482, 118487, 118492, 118497, 118502, 118507, 118512, 118517, 118522, 118527, 118532, 118537, 118542, 118547, 118552, 118557, 118562, 118567, 118572, 118577, 118582, 118587, 118592, 118597, 118602, 118607, 118612, 118617, 118622, 118627, 118632, 118637, 118642, 118647, 118652, 118657, 118662, 118667, 118672, 118677, 118682, 118687, 118692, 118697, 118702, 118707, 118712, 118717, 118722, 118727, 118732, 118737, 118742, 118747, 118752, 118757, 118762, 118767, 118772, 118777, 118782, 118787, 118792, 118797, 118802, 118807, 118812, 118817, 118822, 118827, 118832, 118837, 118842, 118847, 118852, 118857, 118862, 118867, 118872, 118877, 118882, 118887, 118892, 118897, 118902, 118907, 118912, 118917, 118922, 118927, 118932, 118937, 118942, 118947, 118952, 118957, 118962, 118967, 118972, 118977, 118982, 118987, 118992, 118997, 119002, 119007, 119012, 119017, 119022, 119027, 119032, 119037, 119042, 119047, 119052, 119057, 119062, 119067, 119072, 119077, 119082, 119087, 119092, 119097, 119102, 119107, 119112, 119117, 119122, 119127, 119132, 119137, 119142, 119147, 119152, 119157, 119162, 119167, 119172, 119177, 119182, 119187, 119192, 119197, 119202, 119207, 119212, 119217, 119222, 119227, 119232, 119237, 119242, 119247, 119252, 119257, 119262, 119267, 119272, 119277, 119282, 119287, 119292, 119297, 119302, 119307, 119312, 119317, 119322, 119327, 119332, 119337, 119342, 119347, 119352, 119357, 119362, 119367, 119372, 119377, 119382, 119387, 119392, 119397, 119402, 119407, 119412, 119417, 119422, 119427, 119432, 119437, 119442, 119447, 119452, 119457, 119462, 119467, 119472, 119477, 119482, 119487, 119492, 119497, 119502, 119507, 119512, 119517, 119522, 119527, 119532, 119537, 119542, 119547, 119552, 119557, 119562, 119567, 119572, 119577, 119582, 119587, 119592, 119597, 119602, 119607, 119612, 119617, 119622, 119627, 119632, 119637, 119642, 119647, 119652, 119657, 119662, 119667, 119672, 119677, 119682, 119687, 119692, 119697, 119702, 119707, 119712, 119717, 119722, 119727, 119732, 119737, 119742, 119747, 119752, 119757, 119762, 119767, 119772, 119777, 119782, 119787, 119792, 119797, 119802, 119807, 119811, 119815, 119819, 119823, 119827, 119831, 119835, 119839, 119843, 119847, 119851, 119855, 119859, 119863, 119867, 119871, 119875, 119879, 119883, 119887, 119891, 119895, 119899, 119903, 119907, 119911, 119915, 119919, 119923, 119927, 119931, 119935, 119939, 119943, 119947, 119951, 119955, 119959, 119963, 119967, 119971, 119975, 119979, 119983, 119987, 119991, 119995, 119999, 120003, 120007, 120011, 120015, 120019, 120023, 120027, 120031, 120035, 120039, 120043, 120047, 120051, 120055, 120059, 120063, 120067, 120071, 120075, 120079, 120083, 120087, 120091, 120095, 120099, 120103, 120107, 120111, 120115, 120119, 120123, 120127, 120131, 120135, 120139, 120143, 120147, 120151, 120155, 120159, 120163, 120167, 120171, 120175, 120179, 120183, 120187, 120191, 120195, 120199, 120203, 120207, 120211, 120215, 120219, 120223, 120227, 120231, 120235, 120239, 120243, 120247, 120251, 120255, 120259, 120263, 120267, 120271, 120275, 120279, 120283, 120287, 120291, 120295, 120299, 120303, 120307, 120311, 120315, 120319, 120323, 120327, 120331, 120335, 120339, 120343, 120347, 120351, 120355, 120359, 120363, 120367, 120371, 120375, 120379, 120383, 120387, 120391, 120395, 120399, 120403, 120407, 120411, 120415, 120419, 120423, 120427, 120431, 120435, 120439, 120443, 120447, 120451, 120455, 120459, 120463, 120467, 120471, 120475, 120479, 120483, 120487, 120491, 120495, 120499, 120503, 120507, 120511, 120515, 120519, 120523, 120527, 120531, 120535, 120539, 120543, 120547, 120551, 120555, 120559, 120563, 120567, 120571, 120575, 120579, 120583, 120587, 120591, 120595, 120599, 120603, 120607, 120611, 120615, 120619, 120623, 120627, 120631, 120635, 120639, 120643, 120647, 120651, 120655, 120659, 120663, 120667, 120671, 120675, 120679, 120683, 120687, 120691, 120695, 120699, 120703, 120707, 120711, 120715, 120719, 120723, 120727, 120731, 120735, 120739, 120743, 120747, 120751, 120755, 120759, 120763, 120767, 120771, 120775, 120779, 120783, 120787, 120791, 120795, 120799, 120803, 120807, 120811, 120815, 120819, 120823, 120827, 120831, 120835, 120839, 120843, 120847, 120851, 120855, 120859, 120863, 120867, 120871, 120875, 120879, 120883, 120887, 120891, 120895, 120899, 120903, 120907, 120911, 120915, 120919, 120923, 120927, 120931, 120935, 120939, 120943, 120947, 120951, 120955, 120959, 120963, 120967, 120971, 120975, 120979, 120983, 120987, 120991, 120995, 120999, 121003, 121007, 121011, 121015, 121019, 121023, 121027, 121031, 121035, 121039, 121043, 121047, 121051, 121055, 121059, 121063, 121067, 121071, 121075, 121079, 121083, 121087, 121091, 121095, 121099, 121103, 121107, 121111, 121115, 121119, 121123, 121127, 121131, 121135, 121139, 121143, 121147, 121151, 121155, 121159, 121163, 121167, 121171, 121175, 121179, 121183, 121187, 121191, 121195, 121199, 121203, 121207, 121211, 121215, 121219, 121223, 121227, 121231, 121235, 121239, 121243, 121247, 121251, 121255, 121259, 121263, 121267, 121271, 121275, 121279, 121283, 121287, 121291, 121295, 121299, 121303, 121307, 121311, 121315, 121319, 121323, 121327, 121331, 121335, 121339, 121343}; +int b2c_idx[121344] = { 9210, 12052, 22622, 29019, 33364, 35904, 47147, 51072, 53314, 56268, 64599, 70241, 72484, 82250, 85356, 89424, 93662, 94092, 98688, 9240, 12080, 22629, 29030, 33368, 35912, 47154, 51084, 53324, 56280, 64610, 70248, 72494, 82263, 85363, 89432, 93673, 94104, 98693, 9270, 12108, 22636, 29041, 33372, 35920, 47161, 51096, 53334, 56292, 64621, 70255, 72504, 82276, 85370, 89440, 93684, 94116, 98698, 9300, 12136, 22643, 29052, 33376, 35928, 47168, 51108, 53344, 56304, 64632, 70262, 72514, 82289, 85377, 89448, 93695, 94128, 98703, 9330, 12164, 22650, 29063, 33380, 35936, 47175, 51120, 53354, 56316, 64643, 70269, 72524, 82302, 85384, 89456, 93706, 94140, 98708, 9360, 12192, 22657, 29074, 33384, 35944, 47182, 51132, 53364, 56328, 64654, 70276, 72534, 82315, 85391, 89464, 93717, 94152, 98713, 9390, 12220, 22664, 29085, 33388, 35952, 47189, 51144, 53374, 56340, 64665, 70283, 72544, 82328, 85398, 89472, 93728, 94164, 98718, 9420, 12248, 22671, 29096, 33392, 35960, 47196, 51156, 53384, 56352, 64676, 70290, 72554, 82341, 85405, 89480, 93739, 94176, 98723, 9450, 12276, 22678, 29107, 33396, 35968, 47203, 51168, 53394, 56364, 64687, 70297, 72564, 82354, 85412, 89488, 93750, 94188, 98728, 9480, 12304, 22685, 29118, 33400, 35976, 47210, 51180, 53404, 56376, 64698, 70304, 72574, 82367, 85419, 89496, 93761, 94200, 98733, 9510, 12332, 22692, 29129, 33404, 35984, 47217, 51192, 53414, 56388, 64709, 70311, 72584, 82380, 85426, 89504, 93772, 94212, 98738, 9540, 12360, 22699, 29140, 33408, 35992, 47224, 51204, 53424, 56400, 64720, 70318, 72594, 82393, 85433, 89512, 93783, 94224, 98743, 9570, 12388, 22706, 29151, 33412, 36000, 47231, 51216, 53434, 56412, 64731, 70325, 72604, 82406, 85440, 89520, 93794, 94236, 98748, 9600, 12416, 22713, 29162, 33416, 36008, 47238, 51228, 53444, 56424, 64742, 70332, 72614, 82419, 85447, 89528, 93805, 94248, 98753, 9630, 12444, 22720, 29173, 33420, 36016, 47245, 51240, 53454, 56436, 64753, 70339, 72624, 82432, 85454, 89536, 93816, 94260, 98758, 9660, 12472, 22727, 24960, 33424, 36024, 47252, 51252, 53464, 56448, 64764, 70346, 72634, 82445, 85461, 89544, 93827, 94272, 98763, 9690, 12500, 22734, 24971, 33428, 36032, 47259, 51264, 53474, 56460, 64775, 70353, 72644, 82458, 85468, 89552, 93838, 94284, 98768, 9720, 12528, 22741, 24982, 33432, 36040, 47266, 51276, 53484, 56472, 64786, 70360, 72654, 82471, 85475, 89560, 93849, 94296, 98773, 9750, 12556, 22748, 24993, 33436, 36048, 47273, 51288, 53494, 56484, 64797, 70367, 72664, 82484, 85482, 89568, 93860, 94308, 98778, 9780, 12584, 22755, 25004, 33440, 36056, 47280, 51300, 53504, 56496, 64808, 70374, 72674, 82497, 85489, 89576, 93871, 94320, 98783, 9810, 12612, 22762, 25015, 33444, 36064, 47287, 51312, 53514, 56508, 64819, 70381, 72684, 82510, 85496, 89584, 93882, 94332, 98788, 9840, 12640, 22769, 25026, 33448, 36072, 47294, 51324, 53524, 56520, 64830, 70388, 72694, 82523, 85503, 89592, 93893, 94344, 98793, 9870, 12668, 22776, 25037, 33452, 36080, 47301, 51336, 53534, 56532, 64841, 70395, 72704, 82536, 85510, 89600, 93904, 94356, 98798, 9900, 12696, 22783, 25048, 33456, 36088, 47308, 51348, 53544, 56544, 64852, 70402, 72714, 82549, 85517, 89608, 93915, 94368, 98803, 9930, 12724, 22790, 25059, 33460, 36096, 47315, 51360, 53554, 56556, 64863, 70409, 72724, 82562, 85524, 89616, 93926, 94380, 98808, 9960, 12752, 22797, 25070, 33464, 36104, 47322, 51372, 53564, 56568, 64874, 70416, 72734, 82575, 85531, 89624, 93937, 94392, 98813, 9990, 12780, 22804, 25081, 33468, 36112, 47329, 51384, 53574, 56580, 64885, 70423, 72744, 82588, 85538, 89632, 93948, 94404, 98818, 10020, 12808, 22811, 25092, 33472, 36120, 47336, 51396, 53584, 56592, 60672, 70430, 72754, 82601, 85545, 89640, 93959, 94416, 98823, 10050, 12836, 22818, 25103, 33476, 36128, 47343, 51408, 53594, 56604, 60683, 70437, 72764, 82614, 85552, 89648, 93970, 94428, 98828, 10080, 12864, 22825, 25114, 33480, 36136, 47350, 51420, 53604, 56616, 60694, 70444, 72774, 82627, 85559, 89656, 93981, 94440, 98833, 10110, 12892, 22832, 25125, 33484, 36144, 47357, 51432, 53614, 56628, 60705, 70451, 72784, 82640, 85566, 89664, 93992, 94452, 98838, 10140, 12920, 22839, 25136, 33488, 36152, 47364, 51444, 53624, 56640, 60716, 70458, 72794, 82653, 85573, 89672, 94003, 94464, 98843, 10170, 12948, 22846, 25147, 33492, 36160, 47371, 51456, 53634, 56652, 60727, 70465, 72804, 82666, 85580, 89680, 94014, 94476, 98848, 10200, 12976, 22853, 25158, 33496, 36168, 47378, 51468, 53644, 56664, 60738, 70472, 72814, 82679, 85587, 89688, 94025, 94488, 98853, 10230, 13004, 22860, 25169, 33500, 36176, 47385, 51480, 53654, 56676, 60749, 70479, 72824, 82692, 85594, 89696, 94036, 94500, 98858, 10260, 13032, 22867, 25180, 33504, 36184, 47392, 51492, 53664, 56688, 60760, 70486, 72834, 82705, 85601, 89704, 94047, 94512, 98863, 10290, 13060, 22874, 25191, 33508, 36192, 47399, 51504, 53674, 56700, 60771, 70493, 72844, 82718, 85608, 89712, 94058, 94524, 98868, 10320, 13088, 22881, 25202, 33512, 36200, 47406, 51516, 53684, 56712, 60782, 70500, 72854, 82731, 85615, 89720, 94069, 94536, 98873, 10350, 13116, 22888, 25213, 33516, 36208, 47413, 51528, 53694, 56724, 60793, 70507, 72864, 82744, 85622, 89728, 89856, 94548, 98878, 10380, 13144, 22895, 25224, 33520, 36216, 47420, 51540, 53704, 56736, 60804, 70514, 72874, 82757, 85629, 89736, 89867, 94560, 98883, 10410, 13172, 22902, 25235, 33524, 36224, 47427, 51552, 53714, 56748, 60815, 70521, 72884, 82770, 85636, 89744, 89878, 94572, 98888, 10440, 13200, 22909, 25246, 33528, 36232, 47434, 51564, 53724, 56760, 60826, 70528, 72894, 82783, 85643, 89752, 89889, 94584, 98893, 10470, 13228, 22916, 25257, 33532, 36240, 47441, 51576, 53734, 56772, 60837, 70535, 72904, 82796, 85650, 89760, 89900, 94596, 98898, 10500, 13256, 22923, 25268, 33536, 36248, 47448, 51588, 53744, 56784, 60848, 70542, 72914, 82809, 85657, 89768, 89911, 94608, 98903, 10530, 13284, 22930, 25279, 33540, 36256, 47455, 51600, 53754, 56796, 60859, 70549, 72924, 82822, 85664, 89776, 89922, 94620, 98908, 10560, 13312, 22937, 25290, 33544, 36264, 47462, 51612, 53764, 56808, 60870, 70556, 72934, 82835, 85671, 89784, 89933, 94632, 98913, 10590, 13340, 22944, 25301, 33548, 36272, 47469, 51624, 53774, 56820, 60881, 70563, 72944, 82848, 85678, 89792, 89944, 94644, 98918, 10620, 13368, 22951, 25312, 33552, 36280, 47476, 51636, 53784, 56832, 60892, 70570, 72954, 82861, 85685, 89800, 89955, 94656, 98923, 10650, 13396, 22958, 25323, 33556, 36288, 47483, 51648, 53794, 56844, 60903, 70577, 72964, 82874, 85692, 89808, 89966, 94668, 98928, 10680, 13424, 22965, 25334, 33560, 36296, 47490, 51660, 53804, 56856, 60914, 70584, 72974, 82887, 85699, 89816, 89977, 94680, 98933, 10710, 13452, 22972, 25345, 33564, 36304, 47497, 51672, 53814, 56868, 60925, 70591, 72984, 82900, 85706, 89824, 89988, 94692, 98938, 10740, 13480, 22979, 25356, 33568, 36312, 47504, 51684, 53824, 56880, 60936, 70598, 72994, 82913, 85713, 89832, 89999, 94704, 98943, 10770, 13508, 22986, 25367, 33572, 36320, 47511, 51696, 53834, 56892, 60947, 70605, 73004, 82926, 85720, 89840, 90010, 94716, 98948, 10800, 13536, 22993, 25378, 33576, 36328, 47518, 51708, 53844, 56904, 60958, 70612, 73014, 82939, 85727, 89848, 90021, 94728, 98953, 10830, 13564, 23000, 25389, 33580, 36336, 47525, 51720, 53854, 56916, 60969, 70619, 73024, 82952, 85734, 86784, 90032, 94740, 98958, 10860, 13592, 23007, 25400, 33584, 36344, 47532, 51732, 53864, 56928, 60980, 70626, 73034, 82965, 85741, 86792, 90043, 94752, 98963, 10890, 13620, 23014, 25411, 33588, 36352, 47539, 51744, 53874, 56940, 60991, 70633, 73044, 82978, 85748, 86800, 90054, 94764, 98968, 10920, 13648, 23021, 25422, 33592, 36360, 47546, 51756, 53884, 56952, 61002, 70640, 73054, 82991, 85755, 86808, 90065, 94776, 98973, 10950, 13676, 23028, 25433, 33596, 36368, 47553, 51768, 53894, 56964, 61013, 70647, 73064, 83004, 85762, 86816, 90076, 94788, 98978, 10980, 13704, 23035, 25444, 33600, 36376, 47560, 51780, 53904, 56976, 61024, 70654, 73074, 83017, 85769, 86824, 90087, 94800, 98983, 11010, 13732, 23042, 25455, 33604, 36384, 47567, 51792, 53914, 56988, 61035, 70661, 73084, 83030, 85776, 86832, 90098, 94812, 98988, 11040, 13760, 23049, 25466, 33608, 36392, 47574, 51804, 53924, 57000, 61046, 70668, 73094, 83043, 85783, 86840, 90109, 94824, 98993, 11070, 13788, 23056, 25477, 33612, 36400, 47581, 51816, 53934, 57012, 61057, 70675, 73104, 83056, 85790, 86848, 90120, 94836, 98998, 11100, 13816, 23063, 25488, 33616, 36408, 47588, 51828, 53944, 57024, 61068, 70682, 73114, 83069, 85797, 86856, 90131, 94848, 99003, 11130, 13844, 23070, 25499, 33620, 36416, 47595, 51840, 53954, 57036, 61079, 70689, 73124, 83082, 85804, 86864, 90142, 94860, 99008, 11160, 13872, 23077, 25510, 33624, 36424, 47602, 51852, 53964, 57048, 61090, 70696, 73134, 83095, 85811, 86872, 90153, 94872, 99013, 11190, 13900, 23084, 25521, 33628, 36432, 47609, 51864, 53974, 57060, 61101, 70703, 73144, 83108, 85818, 86880, 90164, 94884, 99018, 11220, 13928, 23091, 25532, 33632, 36440, 44928, 51876, 53984, 57072, 61112, 70710, 73154, 83121, 85825, 86888, 90175, 94896, 99023, 11250, 13956, 23098, 25543, 33636, 36448, 44935, 51888, 53994, 57084, 61123, 70717, 73164, 83134, 85832, 86896, 90186, 94908, 99028, 11280, 13984, 23105, 25554, 33640, 36456, 44942, 51900, 54004, 57096, 61134, 70724, 73174, 83147, 85839, 86904, 90197, 94920, 99033, 11310, 14012, 23112, 25565, 33644, 36464, 44949, 51912, 54014, 57108, 61145, 70731, 73184, 83160, 85846, 86912, 90208, 94932, 99038, 11340, 14040, 23119, 25576, 33648, 36472, 44956, 51924, 54024, 57120, 61156, 70738, 73194, 83173, 85853, 86920, 90219, 94944, 99043, 11370, 14068, 23126, 25587, 33652, 36480, 44963, 51936, 54034, 57132, 61167, 70745, 73204, 83186, 85860, 86928, 90230, 94956, 99048, 11400, 14096, 23133, 25598, 33656, 36488, 44970, 51948, 54044, 57144, 61178, 70752, 73214, 83199, 85867, 86936, 90241, 94968, 99053, 11430, 14124, 23140, 25609, 33660, 36496, 44977, 51960, 54054, 57156, 61189, 70759, 73224, 83212, 85874, 86944, 90252, 94980, 99058, 11460, 14152, 23147, 25620, 33664, 36504, 44984, 51972, 54064, 57168, 61200, 70766, 73234, 83225, 85881, 86952, 90263, 94992, 99063, 11490, 14180, 23154, 25631, 33668, 36512, 44991, 51984, 54074, 57180, 61211, 70773, 73244, 83238, 85888, 86960, 90274, 95004, 99068, 0, 14208, 23161, 25642, 33672, 36520, 44998, 51996, 54084, 57192, 61222, 70780, 73254, 83251, 85895, 86968, 90285, 95016, 99073, 30, 14236, 23168, 25653, 33676, 36528, 45005, 52008, 54094, 57204, 61233, 70787, 73264, 83264, 85902, 86976, 90296, 95028, 99078, 60, 14264, 23175, 25664, 33680, 36536, 45012, 52020, 54104, 57216, 61244, 70794, 73274, 83277, 85909, 86984, 90307, 95040, 99083, 90, 14292, 23182, 25675, 33684, 36544, 45019, 52032, 54114, 57228, 61255, 70801, 73284, 83290, 85916, 86992, 90318, 95052, 99088, 120, 14320, 23189, 25686, 33688, 36552, 45026, 52044, 54124, 57240, 61266, 70808, 73294, 83303, 85923, 87000, 90329, 95064, 99093, 150, 14348, 23196, 25697, 33692, 36560, 45033, 52056, 54134, 57252, 61277, 70815, 73304, 83316, 85930, 87008, 90340, 95076, 99098, 180, 14376, 23203, 25708, 33696, 36568, 45040, 52068, 54144, 57264, 61288, 70822, 73314, 83329, 85937, 87016, 90351, 95088, 99103, 210, 14404, 23210, 25719, 33700, 36576, 45047, 52080, 54154, 57276, 61299, 70829, 73324, 83342, 85944, 87024, 90362, 95100, 99108, 240, 14432, 23217, 25730, 33704, 36584, 45054, 52092, 54164, 57288, 61310, 70836, 73334, 83355, 85951, 87032, 90373, 95112, 99113, 270, 14460, 23224, 25741, 33708, 36592, 45061, 52104, 54174, 57300, 61321, 70843, 73344, 83368, 85958, 87040, 90384, 95124, 99118, 300, 14488, 23231, 25752, 33712, 36600, 45068, 52116, 54184, 57312, 61332, 70850, 73354, 83381, 85965, 87048, 90395, 95136, 99123, 330, 14516, 23238, 25763, 33716, 36608, 45075, 52128, 54194, 57324, 61343, 70857, 73364, 83394, 85972, 87056, 90406, 95148, 99128, 360, 14544, 23245, 25774, 33720, 36616, 45082, 52140, 54204, 57336, 61354, 70864, 73374, 83407, 85979, 87064, 90417, 95160, 99133, 390, 14572, 23252, 25785, 33724, 36624, 45089, 52152, 54214, 57348, 61365, 70871, 73384, 83420, 85986, 87072, 90428, 95172, 99138, 420, 14600, 23259, 25796, 33728, 36632, 45096, 52164, 54224, 57360, 61376, 70878, 73394, 83433, 85993, 87080, 90439, 95184, 99143, 450, 14628, 23266, 25807, 33732, 36640, 45103, 52176, 54234, 57372, 61387, 70885, 73404, 83446, 86000, 87088, 90450, 95196, 99148, 480, 14656, 23273, 25818, 33736, 36648, 45110, 52188, 54244, 57384, 61398, 70892, 73414, 83459, 86007, 87096, 90461, 95208, 99153, 510, 14684, 23280, 25829, 33740, 36656, 45117, 52200, 54254, 57396, 61409, 70899, 73424, 83472, 86014, 87104, 90472, 95220, 99158, 540, 14712, 23287, 25840, 33744, 36664, 45124, 52212, 54264, 57408, 61420, 70906, 73434, 83485, 86021, 87112, 90483, 95232, 99163, 570, 14740, 23294, 25851, 33748, 36672, 45131, 47616, 54274, 57420, 61431, 70913, 73444, 83498, 86028, 87120, 90494, 95244, 99168, 600, 14768, 23301, 25862, 33752, 36680, 45138, 47628, 54284, 57432, 61442, 70920, 73454, 83511, 86035, 87128, 90505, 95256, 99173, 630, 14796, 23308, 25873, 33756, 36688, 45145, 47640, 54294, 57444, 61453, 70927, 73464, 83524, 86042, 87136, 90516, 95268, 99178, 660, 14824, 23315, 25884, 33760, 36696, 45152, 47652, 54304, 57456, 61464, 70934, 73474, 83537, 86049, 87144, 90527, 95280, 99183, 690, 14852, 23322, 25895, 33764, 36704, 45159, 47664, 54314, 57468, 61475, 70941, 73484, 83550, 86056, 87152, 90538, 95292, 99188, 720, 14880, 23329, 25906, 33768, 36712, 45166, 47676, 54324, 57480, 61486, 70948, 73494, 83563, 86063, 87160, 90549, 95304, 99193, 750, 14908, 23336, 25917, 33772, 36720, 45173, 47688, 54334, 57492, 61497, 70955, 73504, 83576, 86070, 87168, 90560, 95316, 99198, 780, 14936, 23343, 25928, 33776, 36728, 45180, 47700, 54344, 57504, 61508, 70962, 73514, 83589, 86077, 87176, 90571, 95328, 99203, 810, 14964, 23350, 25939, 33780, 36736, 45187, 47712, 54354, 57516, 61519, 70969, 73524, 83602, 86084, 87184, 90582, 95340, 99208, 840, 14992, 23357, 25950, 33784, 36744, 45194, 47724, 54364, 57528, 61530, 70976, 73534, 83615, 86091, 87192, 90593, 95352, 99213, 870, 15020, 23364, 25961, 33788, 36752, 45201, 47736, 54374, 57540, 61541, 70983, 73544, 83628, 86098, 87200, 90604, 95364, 99218, 900, 15048, 23371, 25972, 33792, 36760, 45208, 47748, 54384, 57552, 61552, 70990, 73554, 83641, 86105, 87208, 90615, 95376, 99223, 930, 15076, 23378, 25983, 33796, 36768, 45215, 47760, 54394, 57564, 61563, 70997, 73564, 83654, 86112, 87216, 90626, 95388, 99228, 960, 15104, 23385, 25994, 33800, 36776, 45222, 47772, 54404, 57576, 61574, 71004, 73574, 83667, 86119, 87224, 90637, 95400, 99233, 990, 15132, 23392, 26005, 33804, 36784, 45229, 47784, 54414, 57588, 61585, 71011, 73584, 83680, 86126, 87232, 90648, 95412, 99238, 1020, 15160, 23399, 26016, 33808, 36792, 45236, 47796, 54424, 57600, 61596, 71018, 73594, 83693, 86133, 87240, 90659, 95424, 99243, 1050, 15188, 23406, 26027, 33812, 36800, 45243, 47808, 54434, 57612, 61607, 71025, 73604, 83706, 86140, 87248, 90670, 95436, 99248, 1080, 15216, 23413, 26038, 33816, 36808, 45250, 47820, 54444, 57624, 61618, 71032, 73614, 83719, 86147, 87256, 90681, 95448, 99253, 1110, 15244, 23420, 26049, 33820, 36816, 45257, 47832, 54454, 57636, 61629, 71039, 73624, 83732, 86154, 87264, 90692, 95460, 99258, 1140, 15272, 23427, 26060, 33824, 36824, 45264, 47844, 54464, 57648, 61640, 71046, 73634, 83745, 86161, 87272, 90703, 95472, 99263, 1170, 15300, 23434, 26071, 33828, 36832, 45271, 47856, 54474, 57660, 61651, 71053, 73644, 83758, 86168, 87280, 90714, 95484, 99268, 1200, 15328, 23441, 26082, 33832, 36840, 45278, 47868, 54484, 57672, 61662, 71060, 73654, 83771, 86175, 87288, 90725, 95496, 99273, 1230, 15356, 23448, 26093, 33836, 36848, 45285, 47880, 54494, 57684, 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45704, 96743, 120907, 869, 37571, 45711, 96755, 120908, 899, 37583, 45718, 96767, 120909, 929, 37595, 45725, 96779, 120910, 959, 37607, 45732, 96791, 120911, 989, 37619, 45739, 96803, 120912, 1019, 37631, 45746, 96815, 120913, 1049, 37643, 45753, 96827, 120914, 1079, 37655, 45760, 96839, 120915, 1109, 37667, 45767, 96851, 120916, 1139, 37679, 45774, 96863, 120917, 1169, 37691, 45781, 96875, 120918, 1199, 37703, 45788, 96887, 120919, 1229, 37715, 45795, 96899, 120920, 1259, 37727, 45802, 96911, 120921, 1289, 37739, 45809, 96923, 120922, 1319, 37751, 45816, 96935, 120923, 1349, 37763, 45823, 96947, 120924, 1379, 37775, 45830, 96959, 120925, 1409, 37787, 45837, 96971, 120926, 1439, 37799, 45844, 96983, 120927, 1469, 37811, 45851, 96995, 120928, 1499, 37823, 45858, 97007, 120929, 1529, 37835, 45865, 97019, 120930, 1559, 37847, 45872, 97031, 120931, 1589, 37859, 45879, 97043, 120932, 1619, 37871, 45886, 97055, 120933, 1649, 37883, 45893, 97067, 120934, 1679, 37895, 45900, 97079, 120935, 1709, 37907, 45907, 97091, 120936, 1739, 37919, 45914, 97103, 120937, 1769, 37931, 45921, 97115, 120938, 1799, 37943, 45928, 97127, 120939, 1829, 37955, 45935, 97139, 120940, 1859, 37967, 45942, 97151, 120941, 1889, 37979, 45949, 97163, 120942, 1919, 37991, 45956, 97175, 120943, 1949, 38003, 45963, 97187, 120944, 1979, 38015, 45970, 97199, 120945, 2009, 38027, 45977, 97211, 120946, 2039, 38039, 45984, 97223, 120947, 2069, 38051, 45991, 97235, 120948, 2099, 38063, 45998, 97247, 120949, 2129, 38075, 46005, 97259, 120950, 2159, 38087, 46012, 97271, 120951, 2189, 38099, 46019, 97283, 120952, 2219, 38111, 46026, 97295, 120953, 2249, 38123, 46033, 97307, 120954, 2279, 38135, 46040, 97319, 120955, 2309, 38147, 46047, 97331, 120956, 2339, 38159, 46054, 97343, 120957, 2369, 38171, 46061, 97355, 120958, 2399, 38183, 46068, 97367, 120959, 15327, 35375, 47807, 120960, 15355, 35383, 47819, 120961, 15383, 35391, 47831, 120962, 15411, 35399, 47843, 120963, 15439, 35407, 47855, 120964, 15467, 35415, 47867, 120965, 15495, 35423, 47879, 120966, 15523, 35431, 47891, 120967, 15551, 35439, 47903, 120968, 15579, 35447, 47915, 120969, 15607, 35455, 47927, 120970, 15635, 35463, 47939, 120971, 15663, 35471, 47951, 120972, 15691, 35479, 47963, 120973, 15719, 35487, 47975, 120974, 15747, 35495, 47987, 120975, 15775, 35503, 47999, 120976, 15803, 35511, 48011, 120977, 15831, 35519, 48023, 120978, 15859, 35527, 48035, 120979, 15887, 35535, 48047, 120980, 15915, 35543, 48059, 120981, 15943, 35551, 48071, 120982, 15971, 35559, 48083, 120983, 15999, 35567, 48095, 120984, 16027, 35575, 48107, 120985, 16055, 35583, 48119, 120986, 16083, 35591, 48131, 120987, 16111, 35599, 48143, 120988, 16139, 35607, 48155, 120989, 16167, 35615, 48167, 120990, 16195, 35623, 48179, 120991, 16223, 35631, 48191, 120992, 16251, 35639, 48203, 120993, 16279, 35647, 48215, 120994, 16307, 35655, 48227, 120995, 16335, 35663, 48239, 120996, 16363, 35671, 48251, 120997, 16391, 35679, 48263, 120998, 16419, 35687, 48275, 120999, 16447, 35695, 48287, 121000, 16475, 35703, 48299, 121001, 16503, 35711, 48311, 121002, 16531, 35719, 48323, 121003, 16559, 35727, 48335, 121004, 16587, 35735, 48347, 121005, 16615, 35743, 48359, 121006, 16643, 35751, 48371, 121007, 16671, 35759, 48383, 121008, 16699, 35767, 48395, 121009, 16727, 35775, 48407, 121010, 16755, 35783, 48419, 121011, 16783, 35791, 48431, 121012, 16811, 35799, 48443, 121013, 16839, 35807, 48455, 121014, 16867, 35815, 48467, 121015, 16895, 35823, 48479, 121016, 16923, 35831, 48491, 121017, 16951, 35839, 48503, 121018, 16979, 35847, 48515, 121019, 17007, 35855, 48527, 121020, 17035, 35863, 48539, 121021, 17063, 35871, 48551, 121022, 17091, 35879, 48563, 121023, 17119, 35887, 48575, 121024, 17147, 35895, 48587, 121025, 17175, 35903, 48599, 121026, 17203, 35911, 48611, 121027, 17231, 35919, 48623, 121028, 17259, 35927, 48635, 121029, 17287, 35935, 48647, 121030, 17315, 35943, 48659, 121031, 17343, 35951, 48671, 121032, 17371, 35959, 48683, 121033, 17399, 35967, 48695, 121034, 17427, 35975, 48707, 121035, 17455, 35983, 48719, 121036, 17483, 35991, 48731, 121037, 17511, 35999, 48743, 121038, 17539, 36007, 48755, 121039, 17567, 36015, 48767, 121040, 17595, 36023, 48779, 121041, 17623, 36031, 48791, 121042, 17651, 36039, 48803, 121043, 17679, 36047, 48815, 121044, 17707, 36055, 48827, 121045, 17735, 36063, 48839, 121046, 17763, 36071, 48851, 121047, 17791, 36079, 48863, 121048, 17819, 36087, 48875, 121049, 17847, 36095, 48887, 121050, 17875, 36103, 48899, 121051, 17903, 36111, 48911, 121052, 17931, 36119, 48923, 121053, 17959, 36127, 48935, 121054, 17987, 36135, 48947, 121055, 18015, 36143, 48959, 121056, 18043, 36151, 48971, 121057, 18071, 36159, 48983, 121058, 18099, 36167, 48995, 121059, 18127, 36175, 49007, 121060, 18155, 36183, 49019, 121061, 18183, 36191, 49031, 121062, 18211, 36199, 49043, 121063, 18239, 36207, 49055, 121064, 18267, 36215, 49067, 121065, 18295, 36223, 49079, 121066, 18323, 36231, 49091, 121067, 18351, 36239, 49103, 121068, 18379, 36247, 49115, 121069, 18407, 36255, 49127, 121070, 18435, 36263, 49139, 121071, 18463, 36271, 49151, 121072, 18491, 36279, 49163, 121073, 18519, 36287, 49175, 121074, 18547, 36295, 49187, 121075, 18575, 36303, 49199, 121076, 18603, 36311, 49211, 121077, 18631, 36319, 49223, 121078, 18659, 36327, 49235, 121079, 18687, 36335, 49247, 121080, 18715, 36343, 49259, 121081, 18743, 36351, 49271, 121082, 18771, 36359, 49283, 121083, 18799, 36367, 49295, 121084, 18827, 36375, 49307, 121085, 18855, 36383, 49319, 121086, 18883, 36391, 49331, 121087, 18911, 36399, 49343, 121088, 18939, 36407, 49355, 121089, 18967, 36415, 49367, 121090, 18995, 36423, 49379, 121091, 19023, 36431, 49391, 121092, 19051, 36439, 49403, 121093, 19079, 36447, 49415, 121094, 19107, 36455, 49427, 121095, 19135, 36463, 49439, 121096, 19163, 36471, 49451, 121097, 19191, 36479, 49463, 121098, 19219, 36487, 49475, 121099, 19247, 36495, 49487, 121100, 19275, 36503, 49499, 121101, 19303, 36511, 49511, 121102, 19331, 36519, 49523, 121103, 19359, 36527, 49535, 121104, 19387, 36535, 49547, 121105, 19415, 36543, 49559, 121106, 19443, 36551, 49571, 121107, 19471, 36559, 49583, 121108, 19499, 36567, 49595, 121109, 19527, 36575, 49607, 121110, 19555, 36583, 49619, 121111, 19583, 36591, 49631, 121112, 19611, 36599, 49643, 121113, 19639, 36607, 49655, 121114, 19667, 36615, 49667, 121115, 19695, 36623, 49679, 121116, 19723, 36631, 49691, 121117, 19751, 36639, 49703, 121118, 19779, 36647, 49715, 121119, 19807, 36655, 49727, 121120, 19835, 36663, 49739, 121121, 19863, 36671, 49751, 121122, 19891, 36679, 49763, 121123, 19919, 36687, 49775, 121124, 19947, 36695, 49787, 121125, 19975, 36703, 49799, 121126, 20003, 36711, 49811, 121127, 20031, 36719, 49823, 121128, 20059, 36727, 49835, 121129, 20087, 36735, 49847, 121130, 20115, 36743, 49859, 121131, 20143, 36751, 49871, 121132, 20171, 36759, 49883, 121133, 20199, 36767, 49895, 121134, 20227, 36775, 49907, 121135, 20255, 36783, 49919, 121136, 20283, 36791, 49931, 121137, 20311, 36799, 49943, 121138, 20339, 36807, 49955, 121139, 20367, 36815, 49967, 121140, 20395, 36823, 49979, 121141, 20423, 36831, 49991, 121142, 20451, 36839, 50003, 121143, 20479, 36847, 50015, 121144, 20507, 36855, 50027, 121145, 20535, 36863, 50039, 121146, 20563, 36871, 50051, 121147, 20591, 36879, 50063, 121148, 20619, 36887, 50075, 121149, 20647, 36895, 50087, 121150, 20675, 36903, 50099, 121151, 20703, 36911, 50111, 121152, 20731, 36919, 50123, 121153, 20759, 36927, 50135, 121154, 20787, 36935, 50147, 121155, 20815, 36943, 50159, 121156, 20843, 36951, 50171, 121157, 20871, 36959, 50183, 121158, 20899, 36967, 50195, 121159, 20927, 36975, 50207, 121160, 20955, 36983, 50219, 121161, 20983, 36991, 50231, 121162, 21011, 36999, 50243, 121163, 21039, 37007, 50255, 121164, 21067, 37015, 50267, 121165, 21095, 37023, 50279, 121166, 21123, 37031, 50291, 121167, 21151, 37039, 50303, 121168, 21179, 37047, 50315, 121169, 21207, 37055, 50327, 121170, 21235, 37063, 50339, 121171, 21263, 37071, 50351, 121172, 21291, 37079, 50363, 121173, 21319, 37087, 50375, 121174, 21347, 37095, 50387, 121175, 21375, 37103, 50399, 121176, 21403, 37111, 50411, 121177, 21431, 37119, 50423, 121178, 21459, 37127, 50435, 121179, 21487, 37135, 50447, 121180, 21515, 37143, 50459, 121181, 21543, 37151, 50471, 121182, 21571, 37159, 50483, 121183, 21599, 37167, 50495, 121184, 21627, 37175, 50507, 121185, 21655, 37183, 50519, 121186, 21683, 37191, 50531, 121187, 21711, 37199, 50543, 121188, 21739, 37207, 50555, 121189, 21767, 37215, 50567, 121190, 21795, 37223, 50579, 121191, 21823, 37231, 50591, 121192, 21851, 37239, 50603, 121193, 21879, 37247, 50615, 121194, 21907, 34183, 50627, 121195, 21935, 34191, 50639, 121196, 21963, 34199, 50651, 121197, 21991, 34207, 50663, 121198, 22019, 34215, 50675, 121199, 22047, 34223, 50687, 121200, 22075, 34231, 50699, 121201, 22103, 34239, 50711, 121202, 22131, 34247, 50723, 121203, 22159, 34255, 50735, 121204, 22187, 34263, 50747, 121205, 22215, 34271, 50759, 121206, 22243, 34279, 50771, 121207, 22271, 34287, 50783, 121208, 11547, 34295, 50795, 121209, 11575, 34303, 50807, 121210, 11603, 34311, 50819, 121211, 11631, 34319, 50831, 121212, 11659, 34327, 50843, 121213, 11687, 34335, 50855, 121214, 11715, 34343, 50867, 121215, 11743, 34351, 50879, 121216, 11771, 34359, 50891, 121217, 11799, 34367, 50903, 121218, 11827, 34375, 50915, 121219, 11855, 34383, 50927, 121220, 11883, 34391, 50939, 121221, 11911, 34399, 50951, 121222, 11939, 34407, 50963, 121223, 11967, 34415, 50975, 121224, 11995, 34423, 50987, 121225, 12023, 34431, 50999, 121226, 12051, 34439, 51011, 121227, 12079, 34447, 51023, 121228, 12107, 34455, 51035, 121229, 12135, 34463, 51047, 121230, 12163, 34471, 51059, 121231, 12191, 34479, 51071, 121232, 12219, 34487, 51083, 121233, 12247, 34495, 51095, 121234, 12275, 34503, 51107, 121235, 12303, 34511, 51119, 121236, 12331, 34519, 51131, 121237, 12359, 34527, 51143, 121238, 12387, 34535, 51155, 121239, 12415, 34543, 51167, 121240, 12443, 34551, 51179, 121241, 12471, 34559, 51191, 121242, 12499, 34567, 51203, 121243, 12527, 34575, 51215, 121244, 12555, 34583, 51227, 121245, 12583, 34591, 51239, 121246, 12611, 34599, 51251, 121247, 12639, 34607, 51263, 121248, 12667, 34615, 51275, 121249, 12695, 34623, 51287, 121250, 12723, 34631, 51299, 121251, 12751, 34639, 51311, 121252, 12779, 34647, 51323, 121253, 12807, 34655, 51335, 121254, 12835, 34663, 51347, 121255, 12863, 34671, 51359, 121256, 12891, 34679, 51371, 121257, 12919, 34687, 51383, 121258, 12947, 34695, 51395, 121259, 12975, 34703, 51407, 121260, 13003, 34711, 51419, 121261, 13031, 34719, 51431, 121262, 13059, 34727, 51443, 121263, 13087, 34735, 51455, 121264, 13115, 34743, 51467, 121265, 13143, 34751, 51479, 121266, 13171, 34759, 51491, 121267, 13199, 34767, 51503, 121268, 13227, 34775, 51515, 121269, 13255, 34783, 51527, 121270, 13283, 34791, 51539, 121271, 13311, 34799, 51551, 121272, 13339, 34807, 51563, 121273, 13367, 34815, 51575, 121274, 13395, 34823, 51587, 121275, 13423, 34831, 51599, 121276, 13451, 34839, 51611, 121277, 13479, 34847, 51623, 121278, 13507, 34855, 51635, 121279, 13535, 34863, 51647, 121280, 13563, 34871, 51659, 121281, 13591, 34879, 51671, 121282, 13619, 34887, 51683, 121283, 13647, 34895, 51695, 121284, 13675, 34903, 51707, 121285, 13703, 34911, 51719, 121286, 13731, 34919, 51731, 121287, 13759, 34927, 51743, 121288, 13787, 34935, 51755, 121289, 13815, 34943, 51767, 121290, 13843, 34951, 51779, 121291, 13871, 34959, 51791, 121292, 13899, 34967, 51803, 121293, 13927, 34975, 51815, 121294, 13955, 34983, 51827, 121295, 13983, 34991, 51839, 121296, 14011, 34999, 51851, 121297, 14039, 35007, 51863, 121298, 14067, 35015, 51875, 121299, 14095, 35023, 51887, 121300, 14123, 35031, 51899, 121301, 14151, 35039, 51911, 121302, 14179, 35047, 51923, 121303, 14207, 35055, 51935, 121304, 14235, 35063, 51947, 121305, 14263, 35071, 51959, 121306, 14291, 35079, 51971, 121307, 14319, 35087, 51983, 121308, 14347, 35095, 51995, 121309, 14375, 35103, 52007, 121310, 14403, 35111, 52019, 121311, 14431, 35119, 52031, 121312, 14459, 35127, 52043, 121313, 14487, 35135, 52055, 121314, 14515, 35143, 52067, 121315, 14543, 35151, 52079, 121316, 14571, 35159, 52091, 121317, 14599, 35167, 52103, 121318, 14627, 35175, 52115, 121319, 14655, 35183, 52127, 121320, 14683, 35191, 52139, 121321, 14711, 35199, 52151, 121322, 14739, 35207, 52163, 121323, 14767, 35215, 52175, 121324, 14795, 35223, 52187, 121325, 14823, 35231, 52199, 121326, 14851, 35239, 52211, 121327, 14879, 35247, 52223, 121328, 14907, 35255, 47627, 121329, 14935, 35263, 47639, 121330, 14963, 35271, 47651, 121331, 14991, 35279, 47663, 121332, 15019, 35287, 47675, 121333, 15047, 35295, 47687, 121334, 15075, 35303, 47699, 121335, 15103, 35311, 47711, 121336, 15131, 35319, 47723, 121337, 15159, 35327, 47735, 121338, 15187, 35335, 47747, 121339, 15215, 35343, 47759, 121340, 15243, 35351, 47771, 121341, 15271, 35359, 47783, 121342, 15299, 35367, 47795, 121343}; +int cnproc_start_idx[121344] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 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119563, 119563, 119568, 119568, 119568, 119568, 119568, 119573, 119573, 119573, 119573, 119573, 119578, 119578, 119578, 119578, 119578, 119583, 119583, 119583, 119583, 119583, 119588, 119588, 119588, 119588, 119588, 119593, 119593, 119593, 119593, 119593, 119598, 119598, 119598, 119598, 119598, 119603, 119603, 119603, 119603, 119603, 119608, 119608, 119608, 119608, 119608, 119613, 119613, 119613, 119613, 119613, 119618, 119618, 119618, 119618, 119618, 119623, 119623, 119623, 119623, 119623, 119628, 119628, 119628, 119628, 119628, 119633, 119633, 119633, 119633, 119633, 119638, 119638, 119638, 119638, 119638, 119643, 119643, 119643, 119643, 119643, 119648, 119648, 119648, 119648, 119648, 119653, 119653, 119653, 119653, 119653, 119658, 119658, 119658, 119658, 119658, 119663, 119663, 119663, 119663, 119663, 119668, 119668, 119668, 119668, 119668, 119673, 119673, 119673, 119673, 119673, 119678, 119678, 119678, 119678, 119678, 119683, 119683, 119683, 119683, 119683, 119688, 119688, 119688, 119688, 119688, 119693, 119693, 119693, 119693, 119693, 119698, 119698, 119698, 119698, 119698, 119703, 119703, 119703, 119703, 119703, 119708, 119708, 119708, 119708, 119708, 119713, 119713, 119713, 119713, 119713, 119718, 119718, 119718, 119718, 119718, 119723, 119723, 119723, 119723, 119723, 119728, 119728, 119728, 119728, 119728, 119733, 119733, 119733, 119733, 119733, 119738, 119738, 119738, 119738, 119738, 119743, 119743, 119743, 119743, 119743, 119748, 119748, 119748, 119748, 119748, 119753, 119753, 119753, 119753, 119753, 119758, 119758, 119758, 119758, 119758, 119763, 119763, 119763, 119763, 119763, 119768, 119768, 119768, 119768, 119768, 119773, 119773, 119773, 119773, 119773, 119778, 119778, 119778, 119778, 119778, 119783, 119783, 119783, 119783, 119783, 119788, 119788, 119788, 119788, 119788, 119793, 119793, 119793, 119793, 119793, 119798, 119798, 119798, 119798, 119798, 119803, 119803, 119803, 119803, 119803, 119808, 119808, 119808, 119808, 119812, 119812, 119812, 119812, 119816, 119816, 119816, 119816, 119820, 119820, 119820, 119820, 119824, 119824, 119824, 119824, 119828, 119828, 119828, 119828, 119832, 119832, 119832, 119832, 119836, 119836, 119836, 119836, 119840, 119840, 119840, 119840, 119844, 119844, 119844, 119844, 119848, 119848, 119848, 119848, 119852, 119852, 119852, 119852, 119856, 119856, 119856, 119856, 119860, 119860, 119860, 119860, 119864, 119864, 119864, 119864, 119868, 119868, 119868, 119868, 119872, 119872, 119872, 119872, 119876, 119876, 119876, 119876, 119880, 119880, 119880, 119880, 119884, 119884, 119884, 119884, 119888, 119888, 119888, 119888, 119892, 119892, 119892, 119892, 119896, 119896, 119896, 119896, 119900, 119900, 119900, 119900, 119904, 119904, 119904, 119904, 119908, 119908, 119908, 119908, 119912, 119912, 119912, 119912, 119916, 119916, 119916, 119916, 119920, 119920, 119920, 119920, 119924, 119924, 119924, 119924, 119928, 119928, 119928, 119928, 119932, 119932, 119932, 119932, 119936, 119936, 119936, 119936, 119940, 119940, 119940, 119940, 119944, 119944, 119944, 119944, 119948, 119948, 119948, 119948, 119952, 119952, 119952, 119952, 119956, 119956, 119956, 119956, 119960, 119960, 119960, 119960, 119964, 119964, 119964, 119964, 119968, 119968, 119968, 119968, 119972, 119972, 119972, 119972, 119976, 119976, 119976, 119976, 119980, 119980, 119980, 119980, 119984, 119984, 119984, 119984, 119988, 119988, 119988, 119988, 119992, 119992, 119992, 119992, 119996, 119996, 119996, 119996, 120000, 120000, 120000, 120000, 120004, 120004, 120004, 120004, 120008, 120008, 120008, 120008, 120012, 120012, 120012, 120012, 120016, 120016, 120016, 120016, 120020, 120020, 120020, 120020, 120024, 120024, 120024, 120024, 120028, 120028, 120028, 120028, 120032, 120032, 120032, 120032, 120036, 120036, 120036, 120036, 120040, 120040, 120040, 120040, 120044, 120044, 120044, 120044, 120048, 120048, 120048, 120048, 120052, 120052, 120052, 120052, 120056, 120056, 120056, 120056, 120060, 120060, 120060, 120060, 120064, 120064, 120064, 120064, 120068, 120068, 120068, 120068, 120072, 120072, 120072, 120072, 120076, 120076, 120076, 120076, 120080, 120080, 120080, 120080, 120084, 120084, 120084, 120084, 120088, 120088, 120088, 120088, 120092, 120092, 120092, 120092, 120096, 120096, 120096, 120096, 120100, 120100, 120100, 120100, 120104, 120104, 120104, 120104, 120108, 120108, 120108, 120108, 120112, 120112, 120112, 120112, 120116, 120116, 120116, 120116, 120120, 120120, 120120, 120120, 120124, 120124, 120124, 120124, 120128, 120128, 120128, 120128, 120132, 120132, 120132, 120132, 120136, 120136, 120136, 120136, 120140, 120140, 120140, 120140, 120144, 120144, 120144, 120144, 120148, 120148, 120148, 120148, 120152, 120152, 120152, 120152, 120156, 120156, 120156, 120156, 120160, 120160, 120160, 120160, 120164, 120164, 120164, 120164, 120168, 120168, 120168, 120168, 120172, 120172, 120172, 120172, 120176, 120176, 120176, 120176, 120180, 120180, 120180, 120180, 120184, 120184, 120184, 120184, 120188, 120188, 120188, 120188, 120192, 120192, 120192, 120192, 120196, 120196, 120196, 120196, 120200, 120200, 120200, 120200, 120204, 120204, 120204, 120204, 120208, 120208, 120208, 120208, 120212, 120212, 120212, 120212, 120216, 120216, 120216, 120216, 120220, 120220, 120220, 120220, 120224, 120224, 120224, 120224, 120228, 120228, 120228, 120228, 120232, 120232, 120232, 120232, 120236, 120236, 120236, 120236, 120240, 120240, 120240, 120240, 120244, 120244, 120244, 120244, 120248, 120248, 120248, 120248, 120252, 120252, 120252, 120252, 120256, 120256, 120256, 120256, 120260, 120260, 120260, 120260, 120264, 120264, 120264, 120264, 120268, 120268, 120268, 120268, 120272, 120272, 120272, 120272, 120276, 120276, 120276, 120276, 120280, 120280, 120280, 120280, 120284, 120284, 120284, 120284, 120288, 120288, 120288, 120288, 120292, 120292, 120292, 120292, 120296, 120296, 120296, 120296, 120300, 120300, 120300, 120300, 120304, 120304, 120304, 120304, 120308, 120308, 120308, 120308, 120312, 120312, 120312, 120312, 120316, 120316, 120316, 120316, 120320, 120320, 120320, 120320, 120324, 120324, 120324, 120324, 120328, 120328, 120328, 120328, 120332, 120332, 120332, 120332, 120336, 120336, 120336, 120336, 120340, 120340, 120340, 120340, 120344, 120344, 120344, 120344, 120348, 120348, 120348, 120348, 120352, 120352, 120352, 120352, 120356, 120356, 120356, 120356, 120360, 120360, 120360, 120360, 120364, 120364, 120364, 120364, 120368, 120368, 120368, 120368, 120372, 120372, 120372, 120372, 120376, 120376, 120376, 120376, 120380, 120380, 120380, 120380, 120384, 120384, 120384, 120384, 120388, 120388, 120388, 120388, 120392, 120392, 120392, 120392, 120396, 120396, 120396, 120396, 120400, 120400, 120400, 120400, 120404, 120404, 120404, 120404, 120408, 120408, 120408, 120408, 120412, 120412, 120412, 120412, 120416, 120416, 120416, 120416, 120420, 120420, 120420, 120420, 120424, 120424, 120424, 120424, 120428, 120428, 120428, 120428, 120432, 120432, 120432, 120432, 120436, 120436, 120436, 120436, 120440, 120440, 120440, 120440, 120444, 120444, 120444, 120444, 120448, 120448, 120448, 120448, 120452, 120452, 120452, 120452, 120456, 120456, 120456, 120456, 120460, 120460, 120460, 120460, 120464, 120464, 120464, 120464, 120468, 120468, 120468, 120468, 120472, 120472, 120472, 120472, 120476, 120476, 120476, 120476, 120480, 120480, 120480, 120480, 120484, 120484, 120484, 120484, 120488, 120488, 120488, 120488, 120492, 120492, 120492, 120492, 120496, 120496, 120496, 120496, 120500, 120500, 120500, 120500, 120504, 120504, 120504, 120504, 120508, 120508, 120508, 120508, 120512, 120512, 120512, 120512, 120516, 120516, 120516, 120516, 120520, 120520, 120520, 120520, 120524, 120524, 120524, 120524, 120528, 120528, 120528, 120528, 120532, 120532, 120532, 120532, 120536, 120536, 120536, 120536, 120540, 120540, 120540, 120540, 120544, 120544, 120544, 120544, 120548, 120548, 120548, 120548, 120552, 120552, 120552, 120552, 120556, 120556, 120556, 120556, 120560, 120560, 120560, 120560, 120564, 120564, 120564, 120564, 120568, 120568, 120568, 120568, 120572, 120572, 120572, 120572, 120576, 120576, 120576, 120576, 120580, 120580, 120580, 120580, 120584, 120584, 120584, 120584, 120588, 120588, 120588, 120588, 120592, 120592, 120592, 120592, 120596, 120596, 120596, 120596, 120600, 120600, 120600, 120600, 120604, 120604, 120604, 120604, 120608, 120608, 120608, 120608, 120612, 120612, 120612, 120612, 120616, 120616, 120616, 120616, 120620, 120620, 120620, 120620, 120624, 120624, 120624, 120624, 120628, 120628, 120628, 120628, 120632, 120632, 120632, 120632, 120636, 120636, 120636, 120636, 120640, 120640, 120640, 120640, 120644, 120644, 120644, 120644, 120648, 120648, 120648, 120648, 120652, 120652, 120652, 120652, 120656, 120656, 120656, 120656, 120660, 120660, 120660, 120660, 120664, 120664, 120664, 120664, 120668, 120668, 120668, 120668, 120672, 120672, 120672, 120672, 120676, 120676, 120676, 120676, 120680, 120680, 120680, 120680, 120684, 120684, 120684, 120684, 120688, 120688, 120688, 120688, 120692, 120692, 120692, 120692, 120696, 120696, 120696, 120696, 120700, 120700, 120700, 120700, 120704, 120704, 120704, 120704, 120708, 120708, 120708, 120708, 120712, 120712, 120712, 120712, 120716, 120716, 120716, 120716, 120720, 120720, 120720, 120720, 120724, 120724, 120724, 120724, 120728, 120728, 120728, 120728, 120732, 120732, 120732, 120732, 120736, 120736, 120736, 120736, 120740, 120740, 120740, 120740, 120744, 120744, 120744, 120744, 120748, 120748, 120748, 120748, 120752, 120752, 120752, 120752, 120756, 120756, 120756, 120756, 120760, 120760, 120760, 120760, 120764, 120764, 120764, 120764, 120768, 120768, 120768, 120768, 120772, 120772, 120772, 120772, 120776, 120776, 120776, 120776, 120780, 120780, 120780, 120780, 120784, 120784, 120784, 120784, 120788, 120788, 120788, 120788, 120792, 120792, 120792, 120792, 120796, 120796, 120796, 120796, 120800, 120800, 120800, 120800, 120804, 120804, 120804, 120804, 120808, 120808, 120808, 120808, 120812, 120812, 120812, 120812, 120816, 120816, 120816, 120816, 120820, 120820, 120820, 120820, 120824, 120824, 120824, 120824, 120828, 120828, 120828, 120828, 120832, 120832, 120832, 120832, 120836, 120836, 120836, 120836, 120840, 120840, 120840, 120840, 120844, 120844, 120844, 120844, 120848, 120848, 120848, 120848, 120852, 120852, 120852, 120852, 120856, 120856, 120856, 120856, 120860, 120860, 120860, 120860, 120864, 120864, 120864, 120864, 120868, 120868, 120868, 120868, 120872, 120872, 120872, 120872, 120876, 120876, 120876, 120876, 120880, 120880, 120880, 120880, 120884, 120884, 120884, 120884, 120888, 120888, 120888, 120888, 120892, 120892, 120892, 120892, 120896, 120896, 120896, 120896, 120900, 120900, 120900, 120900, 120904, 120904, 120904, 120904, 120908, 120908, 120908, 120908, 120912, 120912, 120912, 120912, 120916, 120916, 120916, 120916, 120920, 120920, 120920, 120920, 120924, 120924, 120924, 120924, 120928, 120928, 120928, 120928, 120932, 120932, 120932, 120932, 120936, 120936, 120936, 120936, 120940, 120940, 120940, 120940, 120944, 120944, 120944, 120944, 120948, 120948, 120948, 120948, 120952, 120952, 120952, 120952, 120956, 120956, 120956, 120956, 120960, 120960, 120960, 120960, 120964, 120964, 120964, 120964, 120968, 120968, 120968, 120968, 120972, 120972, 120972, 120972, 120976, 120976, 120976, 120976, 120980, 120980, 120980, 120980, 120984, 120984, 120984, 120984, 120988, 120988, 120988, 120988, 120992, 120992, 120992, 120992, 120996, 120996, 120996, 120996, 121000, 121000, 121000, 121000, 121004, 121004, 121004, 121004, 121008, 121008, 121008, 121008, 121012, 121012, 121012, 121012, 121016, 121016, 121016, 121016, 121020, 121020, 121020, 121020, 121024, 121024, 121024, 121024, 121028, 121028, 121028, 121028, 121032, 121032, 121032, 121032, 121036, 121036, 121036, 121036, 121040, 121040, 121040, 121040, 121044, 121044, 121044, 121044, 121048, 121048, 121048, 121048, 121052, 121052, 121052, 121052, 121056, 121056, 121056, 121056, 121060, 121060, 121060, 121060, 121064, 121064, 121064, 121064, 121068, 121068, 121068, 121068, 121072, 121072, 121072, 121072, 121076, 121076, 121076, 121076, 121080, 121080, 121080, 121080, 121084, 121084, 121084, 121084, 121088, 121088, 121088, 121088, 121092, 121092, 121092, 121092, 121096, 121096, 121096, 121096, 121100, 121100, 121100, 121100, 121104, 121104, 121104, 121104, 121108, 121108, 121108, 121108, 121112, 121112, 121112, 121112, 121116, 121116, 121116, 121116, 121120, 121120, 121120, 121120, 121124, 121124, 121124, 121124, 121128, 121128, 121128, 121128, 121132, 121132, 121132, 121132, 121136, 121136, 121136, 121136, 121140, 121140, 121140, 121140, 121144, 121144, 121144, 121144, 121148, 121148, 121148, 121148, 121152, 121152, 121152, 121152, 121156, 121156, 121156, 121156, 121160, 121160, 121160, 121160, 121164, 121164, 121164, 121164, 121168, 121168, 121168, 121168, 121172, 121172, 121172, 121172, 121176, 121176, 121176, 121176, 121180, 121180, 121180, 121180, 121184, 121184, 121184, 121184, 121188, 121188, 121188, 121188, 121192, 121192, 121192, 121192, 121196, 121196, 121196, 121196, 121200, 121200, 121200, 121200, 121204, 121204, 121204, 121204, 121208, 121208, 121208, 121208, 121212, 121212, 121212, 121212, 121216, 121216, 121216, 121216, 121220, 121220, 121220, 121220, 121224, 121224, 121224, 121224, 121228, 121228, 121228, 121228, 121232, 121232, 121232, 121232, 121236, 121236, 121236, 121236, 121240, 121240, 121240, 121240, 121244, 121244, 121244, 121244, 121248, 121248, 121248, 121248, 121252, 121252, 121252, 121252, 121256, 121256, 121256, 121256, 121260, 121260, 121260, 121260, 121264, 121264, 121264, 121264, 121268, 121268, 121268, 121268, 121272, 121272, 121272, 121272, 121276, 121276, 121276, 121276, 121280, 121280, 121280, 121280, 121284, 121284, 121284, 121284, 121288, 121288, 121288, 121288, 121292, 121292, 121292, 121292, 121296, 121296, 121296, 121296, 121300, 121300, 121300, 121300, 121304, 121304, 121304, 121304, 121308, 121308, 121308, 121308, 121312, 121312, 121312, 121312, 121316, 121316, 121316, 121316, 121320, 121320, 121320, 121320, 121324, 121324, 121324, 121324, 121328, 121328, 121328, 121328, 121332, 121332, 121332, 121332, 121336, 121336, 121336, 121336, 121340, 121340, 121340, 121340}; +int cnproc_end_idx[121344] = { 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 779, 779, 779, 779, 779, 779, 779, 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119783, 119783, 119783, 119783, 119783, 119788, 119788, 119788, 119788, 119788, 119793, 119793, 119793, 119793, 119793, 119798, 119798, 119798, 119798, 119798, 119803, 119803, 119803, 119803, 119803, 119808, 119808, 119808, 119808, 119808, 119812, 119812, 119812, 119812, 119816, 119816, 119816, 119816, 119820, 119820, 119820, 119820, 119824, 119824, 119824, 119824, 119828, 119828, 119828, 119828, 119832, 119832, 119832, 119832, 119836, 119836, 119836, 119836, 119840, 119840, 119840, 119840, 119844, 119844, 119844, 119844, 119848, 119848, 119848, 119848, 119852, 119852, 119852, 119852, 119856, 119856, 119856, 119856, 119860, 119860, 119860, 119860, 119864, 119864, 119864, 119864, 119868, 119868, 119868, 119868, 119872, 119872, 119872, 119872, 119876, 119876, 119876, 119876, 119880, 119880, 119880, 119880, 119884, 119884, 119884, 119884, 119888, 119888, 119888, 119888, 119892, 119892, 119892, 119892, 119896, 119896, 119896, 119896, 119900, 119900, 119900, 119900, 119904, 119904, 119904, 119904, 119908, 119908, 119908, 119908, 119912, 119912, 119912, 119912, 119916, 119916, 119916, 119916, 119920, 119920, 119920, 119920, 119924, 119924, 119924, 119924, 119928, 119928, 119928, 119928, 119932, 119932, 119932, 119932, 119936, 119936, 119936, 119936, 119940, 119940, 119940, 119940, 119944, 119944, 119944, 119944, 119948, 119948, 119948, 119948, 119952, 119952, 119952, 119952, 119956, 119956, 119956, 119956, 119960, 119960, 119960, 119960, 119964, 119964, 119964, 119964, 119968, 119968, 119968, 119968, 119972, 119972, 119972, 119972, 119976, 119976, 119976, 119976, 119980, 119980, 119980, 119980, 119984, 119984, 119984, 119984, 119988, 119988, 119988, 119988, 119992, 119992, 119992, 119992, 119996, 119996, 119996, 119996, 120000, 120000, 120000, 120000, 120004, 120004, 120004, 120004, 120008, 120008, 120008, 120008, 120012, 120012, 120012, 120012, 120016, 120016, 120016, 120016, 120020, 120020, 120020, 120020, 120024, 120024, 120024, 120024, 120028, 120028, 120028, 120028, 120032, 120032, 120032, 120032, 120036, 120036, 120036, 120036, 120040, 120040, 120040, 120040, 120044, 120044, 120044, 120044, 120048, 120048, 120048, 120048, 120052, 120052, 120052, 120052, 120056, 120056, 120056, 120056, 120060, 120060, 120060, 120060, 120064, 120064, 120064, 120064, 120068, 120068, 120068, 120068, 120072, 120072, 120072, 120072, 120076, 120076, 120076, 120076, 120080, 120080, 120080, 120080, 120084, 120084, 120084, 120084, 120088, 120088, 120088, 120088, 120092, 120092, 120092, 120092, 120096, 120096, 120096, 120096, 120100, 120100, 120100, 120100, 120104, 120104, 120104, 120104, 120108, 120108, 120108, 120108, 120112, 120112, 120112, 120112, 120116, 120116, 120116, 120116, 120120, 120120, 120120, 120120, 120124, 120124, 120124, 120124, 120128, 120128, 120128, 120128, 120132, 120132, 120132, 120132, 120136, 120136, 120136, 120136, 120140, 120140, 120140, 120140, 120144, 120144, 120144, 120144, 120148, 120148, 120148, 120148, 120152, 120152, 120152, 120152, 120156, 120156, 120156, 120156, 120160, 120160, 120160, 120160, 120164, 120164, 120164, 120164, 120168, 120168, 120168, 120168, 120172, 120172, 120172, 120172, 120176, 120176, 120176, 120176, 120180, 120180, 120180, 120180, 120184, 120184, 120184, 120184, 120188, 120188, 120188, 120188, 120192, 120192, 120192, 120192, 120196, 120196, 120196, 120196, 120200, 120200, 120200, 120200, 120204, 120204, 120204, 120204, 120208, 120208, 120208, 120208, 120212, 120212, 120212, 120212, 120216, 120216, 120216, 120216, 120220, 120220, 120220, 120220, 120224, 120224, 120224, 120224, 120228, 120228, 120228, 120228, 120232, 120232, 120232, 120232, 120236, 120236, 120236, 120236, 120240, 120240, 120240, 120240, 120244, 120244, 120244, 120244, 120248, 120248, 120248, 120248, 120252, 120252, 120252, 120252, 120256, 120256, 120256, 120256, 120260, 120260, 120260, 120260, 120264, 120264, 120264, 120264, 120268, 120268, 120268, 120268, 120272, 120272, 120272, 120272, 120276, 120276, 120276, 120276, 120280, 120280, 120280, 120280, 120284, 120284, 120284, 120284, 120288, 120288, 120288, 120288, 120292, 120292, 120292, 120292, 120296, 120296, 120296, 120296, 120300, 120300, 120300, 120300, 120304, 120304, 120304, 120304, 120308, 120308, 120308, 120308, 120312, 120312, 120312, 120312, 120316, 120316, 120316, 120316, 120320, 120320, 120320, 120320, 120324, 120324, 120324, 120324, 120328, 120328, 120328, 120328, 120332, 120332, 120332, 120332, 120336, 120336, 120336, 120336, 120340, 120340, 120340, 120340, 120344, 120344, 120344, 120344, 120348, 120348, 120348, 120348, 120352, 120352, 120352, 120352, 120356, 120356, 120356, 120356, 120360, 120360, 120360, 120360, 120364, 120364, 120364, 120364, 120368, 120368, 120368, 120368, 120372, 120372, 120372, 120372, 120376, 120376, 120376, 120376, 120380, 120380, 120380, 120380, 120384, 120384, 120384, 120384, 120388, 120388, 120388, 120388, 120392, 120392, 120392, 120392, 120396, 120396, 120396, 120396, 120400, 120400, 120400, 120400, 120404, 120404, 120404, 120404, 120408, 120408, 120408, 120408, 120412, 120412, 120412, 120412, 120416, 120416, 120416, 120416, 120420, 120420, 120420, 120420, 120424, 120424, 120424, 120424, 120428, 120428, 120428, 120428, 120432, 120432, 120432, 120432, 120436, 120436, 120436, 120436, 120440, 120440, 120440, 120440, 120444, 120444, 120444, 120444, 120448, 120448, 120448, 120448, 120452, 120452, 120452, 120452, 120456, 120456, 120456, 120456, 120460, 120460, 120460, 120460, 120464, 120464, 120464, 120464, 120468, 120468, 120468, 120468, 120472, 120472, 120472, 120472, 120476, 120476, 120476, 120476, 120480, 120480, 120480, 120480, 120484, 120484, 120484, 120484, 120488, 120488, 120488, 120488, 120492, 120492, 120492, 120492, 120496, 120496, 120496, 120496, 120500, 120500, 120500, 120500, 120504, 120504, 120504, 120504, 120508, 120508, 120508, 120508, 120512, 120512, 120512, 120512, 120516, 120516, 120516, 120516, 120520, 120520, 120520, 120520, 120524, 120524, 120524, 120524, 120528, 120528, 120528, 120528, 120532, 120532, 120532, 120532, 120536, 120536, 120536, 120536, 120540, 120540, 120540, 120540, 120544, 120544, 120544, 120544, 120548, 120548, 120548, 120548, 120552, 120552, 120552, 120552, 120556, 120556, 120556, 120556, 120560, 120560, 120560, 120560, 120564, 120564, 120564, 120564, 120568, 120568, 120568, 120568, 120572, 120572, 120572, 120572, 120576, 120576, 120576, 120576, 120580, 120580, 120580, 120580, 120584, 120584, 120584, 120584, 120588, 120588, 120588, 120588, 120592, 120592, 120592, 120592, 120596, 120596, 120596, 120596, 120600, 120600, 120600, 120600, 120604, 120604, 120604, 120604, 120608, 120608, 120608, 120608, 120612, 120612, 120612, 120612, 120616, 120616, 120616, 120616, 120620, 120620, 120620, 120620, 120624, 120624, 120624, 120624, 120628, 120628, 120628, 120628, 120632, 120632, 120632, 120632, 120636, 120636, 120636, 120636, 120640, 120640, 120640, 120640, 120644, 120644, 120644, 120644, 120648, 120648, 120648, 120648, 120652, 120652, 120652, 120652, 120656, 120656, 120656, 120656, 120660, 120660, 120660, 120660, 120664, 120664, 120664, 120664, 120668, 120668, 120668, 120668, 120672, 120672, 120672, 120672, 120676, 120676, 120676, 120676, 120680, 120680, 120680, 120680, 120684, 120684, 120684, 120684, 120688, 120688, 120688, 120688, 120692, 120692, 120692, 120692, 120696, 120696, 120696, 120696, 120700, 120700, 120700, 120700, 120704, 120704, 120704, 120704, 120708, 120708, 120708, 120708, 120712, 120712, 120712, 120712, 120716, 120716, 120716, 120716, 120720, 120720, 120720, 120720, 120724, 120724, 120724, 120724, 120728, 120728, 120728, 120728, 120732, 120732, 120732, 120732, 120736, 120736, 120736, 120736, 120740, 120740, 120740, 120740, 120744, 120744, 120744, 120744, 120748, 120748, 120748, 120748, 120752, 120752, 120752, 120752, 120756, 120756, 120756, 120756, 120760, 120760, 120760, 120760, 120764, 120764, 120764, 120764, 120768, 120768, 120768, 120768, 120772, 120772, 120772, 120772, 120776, 120776, 120776, 120776, 120780, 120780, 120780, 120780, 120784, 120784, 120784, 120784, 120788, 120788, 120788, 120788, 120792, 120792, 120792, 120792, 120796, 120796, 120796, 120796, 120800, 120800, 120800, 120800, 120804, 120804, 120804, 120804, 120808, 120808, 120808, 120808, 120812, 120812, 120812, 120812, 120816, 120816, 120816, 120816, 120820, 120820, 120820, 120820, 120824, 120824, 120824, 120824, 120828, 120828, 120828, 120828, 120832, 120832, 120832, 120832, 120836, 120836, 120836, 120836, 120840, 120840, 120840, 120840, 120844, 120844, 120844, 120844, 120848, 120848, 120848, 120848, 120852, 120852, 120852, 120852, 120856, 120856, 120856, 120856, 120860, 120860, 120860, 120860, 120864, 120864, 120864, 120864, 120868, 120868, 120868, 120868, 120872, 120872, 120872, 120872, 120876, 120876, 120876, 120876, 120880, 120880, 120880, 120880, 120884, 120884, 120884, 120884, 120888, 120888, 120888, 120888, 120892, 120892, 120892, 120892, 120896, 120896, 120896, 120896, 120900, 120900, 120900, 120900, 120904, 120904, 120904, 120904, 120908, 120908, 120908, 120908, 120912, 120912, 120912, 120912, 120916, 120916, 120916, 120916, 120920, 120920, 120920, 120920, 120924, 120924, 120924, 120924, 120928, 120928, 120928, 120928, 120932, 120932, 120932, 120932, 120936, 120936, 120936, 120936, 120940, 120940, 120940, 120940, 120944, 120944, 120944, 120944, 120948, 120948, 120948, 120948, 120952, 120952, 120952, 120952, 120956, 120956, 120956, 120956, 120960, 120960, 120960, 120960, 120964, 120964, 120964, 120964, 120968, 120968, 120968, 120968, 120972, 120972, 120972, 120972, 120976, 120976, 120976, 120976, 120980, 120980, 120980, 120980, 120984, 120984, 120984, 120984, 120988, 120988, 120988, 120988, 120992, 120992, 120992, 120992, 120996, 120996, 120996, 120996, 121000, 121000, 121000, 121000, 121004, 121004, 121004, 121004, 121008, 121008, 121008, 121008, 121012, 121012, 121012, 121012, 121016, 121016, 121016, 121016, 121020, 121020, 121020, 121020, 121024, 121024, 121024, 121024, 121028, 121028, 121028, 121028, 121032, 121032, 121032, 121032, 121036, 121036, 121036, 121036, 121040, 121040, 121040, 121040, 121044, 121044, 121044, 121044, 121048, 121048, 121048, 121048, 121052, 121052, 121052, 121052, 121056, 121056, 121056, 121056, 121060, 121060, 121060, 121060, 121064, 121064, 121064, 121064, 121068, 121068, 121068, 121068, 121072, 121072, 121072, 121072, 121076, 121076, 121076, 121076, 121080, 121080, 121080, 121080, 121084, 121084, 121084, 121084, 121088, 121088, 121088, 121088, 121092, 121092, 121092, 121092, 121096, 121096, 121096, 121096, 121100, 121100, 121100, 121100, 121104, 121104, 121104, 121104, 121108, 121108, 121108, 121108, 121112, 121112, 121112, 121112, 121116, 121116, 121116, 121116, 121120, 121120, 121120, 121120, 121124, 121124, 121124, 121124, 121128, 121128, 121128, 121128, 121132, 121132, 121132, 121132, 121136, 121136, 121136, 121136, 121140, 121140, 121140, 121140, 121144, 121144, 121144, 121144, 121148, 121148, 121148, 121148, 121152, 121152, 121152, 121152, 121156, 121156, 121156, 121156, 121160, 121160, 121160, 121160, 121164, 121164, 121164, 121164, 121168, 121168, 121168, 121168, 121172, 121172, 121172, 121172, 121176, 121176, 121176, 121176, 121180, 121180, 121180, 121180, 121184, 121184, 121184, 121184, 121188, 121188, 121188, 121188, 121192, 121192, 121192, 121192, 121196, 121196, 121196, 121196, 121200, 121200, 121200, 121200, 121204, 121204, 121204, 121204, 121208, 121208, 121208, 121208, 121212, 121212, 121212, 121212, 121216, 121216, 121216, 121216, 121220, 121220, 121220, 121220, 121224, 121224, 121224, 121224, 121228, 121228, 121228, 121228, 121232, 121232, 121232, 121232, 121236, 121236, 121236, 121236, 121240, 121240, 121240, 121240, 121244, 121244, 121244, 121244, 121248, 121248, 121248, 121248, 121252, 121252, 121252, 121252, 121256, 121256, 121256, 121256, 121260, 121260, 121260, 121260, 121264, 121264, 121264, 121264, 121268, 121268, 121268, 121268, 121272, 121272, 121272, 121272, 121276, 121276, 121276, 121276, 121280, 121280, 121280, 121280, 121284, 121284, 121284, 121284, 121288, 121288, 121288, 121288, 121292, 121292, 121292, 121292, 121296, 121296, 121296, 121296, 121300, 121300, 121300, 121300, 121304, 121304, 121304, 121304, 121308, 121308, 121308, 121308, 121312, 121312, 121312, 121312, 121316, 121316, 121316, 121316, 121320, 121320, 121320, 121320, 121324, 121324, 121324, 121324, 121328, 121328, 121328, 121328, 121332, 121332, 121332, 121332, 121336, 121336, 121336, 121336, 121340, 121340, 121340, 121340, 121344, 121344, 121344, 121344}; +int bnproc_start_idx[121344] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 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120505, 120506, 120507, 120508, 120509, 120510, 120511, 120512, 120513, 120514, 120515, 120516, 120517, 120518, 120519, 120520, 120521, 120522, 120523, 120524, 120525, 120526, 120527, 120528, 120529, 120530, 120531, 120532, 120533, 120534, 120535, 120536, 120537, 120538, 120539, 120540, 120541, 120542, 120543, 120544, 120545, 120546, 120547, 120548, 120549, 120550, 120551, 120552, 120553, 120554, 120555, 120556, 120557, 120558, 120559, 120560, 120561, 120562, 120563, 120564, 120565, 120566, 120567, 120568, 120569, 120570, 120571, 120572, 120573, 120574, 120575, 120576, 120577, 120578, 120579, 120580, 120581, 120582, 120583, 120584, 120585, 120586, 120587, 120588, 120589, 120590, 120591, 120592, 120593, 120594, 120595, 120596, 120597, 120598, 120599, 120600, 120601, 120602, 120603, 120604, 120605, 120606, 120607, 120608, 120609, 120610, 120611, 120612, 120613, 120614, 120615, 120616, 120617, 120618, 120619, 120620, 120621, 120622, 120623, 120624, 120625, 120626, 120627, 120628, 120629, 120630, 120631, 120632, 120633, 120634, 120635, 120636, 120637, 120638, 120639, 120640, 120641, 120642, 120643, 120644, 120645, 120646, 120647, 120648, 120649, 120650, 120651, 120652, 120653, 120654, 120655, 120656, 120657, 120658, 120659, 120660, 120661, 120662, 120663, 120664, 120665, 120666, 120667, 120668, 120669, 120670, 120671, 120672, 120673, 120674, 120675, 120676, 120677, 120678, 120679, 120680, 120681, 120682, 120683, 120684, 120685, 120686, 120687, 120688, 120689, 120690, 120691, 120692, 120693, 120694, 120695, 120696, 120697, 120698, 120699, 120700, 120701, 120702, 120703, 120704, 120705, 120706, 120707, 120708, 120709, 120710, 120711, 120712, 120713, 120714, 120715, 120716, 120717, 120718, 120719, 120720, 120721, 120722, 120723, 120724, 120725, 120726, 120727, 120728, 120729, 120730, 120731, 120732, 120733, 120734, 120735, 120736, 120737, 120738, 120739, 120740, 120741, 120742, 120743, 120744, 120745, 120746, 120747, 120748, 120749, 120750, 120751, 120752, 120753, 120754, 120755, 120756, 120757, 120758, 120759, 120760, 120761, 120762, 120763, 120764, 120765, 120766, 120767, 120768, 120769, 120770, 120771, 120772, 120773, 120774, 120775, 120776, 120777, 120778, 120779, 120780, 120781, 120782, 120783, 120784, 120785, 120786, 120787, 120788, 120789, 120790, 120791, 120792, 120793, 120794, 120795, 120796, 120797, 120798, 120799, 120800, 120801, 120802, 120803, 120804, 120805, 120806, 120807, 120808, 120809, 120810, 120811, 120812, 120813, 120814, 120815, 120816, 120817, 120818, 120819, 120820, 120821, 120822, 120823, 120824, 120825, 120826, 120827, 120828, 120829, 120830, 120831, 120832, 120833, 120834, 120835, 120836, 120837, 120838, 120839, 120840, 120841, 120842, 120843, 120844, 120845, 120846, 120847, 120848, 120849, 120850, 120851, 120852, 120853, 120854, 120855, 120856, 120857, 120858, 120859, 120860, 120861, 120862, 120863, 120864, 120865, 120866, 120867, 120868, 120869, 120870, 120871, 120872, 120873, 120874, 120875, 120876, 120877, 120878, 120879, 120880, 120881, 120882, 120883, 120884, 120885, 120886, 120887, 120888, 120889, 120890, 120891, 120892, 120893, 120894, 120895, 120896, 120897, 120898, 120899, 120900, 120901, 120902, 120903, 120904, 120905, 120906, 120907, 120908, 120909, 120910, 120911, 120912, 120913, 120914, 120915, 120916, 120917, 120918, 120919, 120920, 120921, 120922, 120923, 120924, 120925, 120926, 120927, 120928, 120929, 120930, 120931, 120932, 120933, 120934, 120935, 120936, 120937, 120938, 120939, 120940, 120941, 120942, 120943, 120944, 120945, 120946, 120947, 120948, 120949, 120950, 120951, 120952, 120953, 120954, 120955, 120956, 120957, 120958, 120959, 120960, 120961, 120962, 120963, 120964, 120965, 120966, 120967, 120968, 120969, 120970, 120971, 120972, 120973, 120974, 120975, 120976, 120977, 120978, 120979, 120980, 120981, 120982, 120983, 120984, 120985, 120986, 120987, 120988, 120989, 120990, 120991, 120992, 120993, 120994, 120995, 120996, 120997, 120998, 120999, 121000, 121001, 121002, 121003, 121004, 121005, 121006, 121007, 121008, 121009, 121010, 121011, 121012, 121013, 121014, 121015, 121016, 121017, 121018, 121019, 121020, 121021, 121022, 121023, 121024, 121025, 121026, 121027, 121028, 121029, 121030, 121031, 121032, 121033, 121034, 121035, 121036, 121037, 121038, 121039, 121040, 121041, 121042, 121043, 121044, 121045, 121046, 121047, 121048, 121049, 121050, 121051, 121052, 121053, 121054, 121055, 121056, 121057, 121058, 121059, 121060, 121061, 121062, 121063, 121064, 121065, 121066, 121067, 121068, 121069, 121070, 121071, 121072, 121073, 121074, 121075, 121076, 121077, 121078, 121079, 121080, 121081, 121082, 121083, 121084, 121085, 121086, 121087, 121088, 121089, 121090, 121091, 121092, 121093, 121094, 121095, 121096, 121097, 121098, 121099, 121100, 121101, 121102, 121103, 121104, 121105, 121106, 121107, 121108, 121109, 121110, 121111, 121112, 121113, 121114, 121115, 121116, 121117, 121118, 121119, 121120, 121121, 121122, 121123, 121124, 121125, 121126, 121127, 121128, 121129, 121130, 121131, 121132, 121133, 121134, 121135, 121136, 121137, 121138, 121139, 121140, 121141, 121142, 121143, 121144, 121145, 121146, 121147, 121148, 121149, 121150, 121151, 121152, 121153, 121154, 121155, 121156, 121157, 121158, 121159, 121160, 121161, 121162, 121163, 121164, 121165, 121166, 121167, 121168, 121169, 121170, 121171, 121172, 121173, 121174, 121175, 121176, 121177, 121178, 121179, 121180, 121181, 121182, 121183, 121184, 121185, 121186, 121187, 121188, 121189, 121190, 121191, 121192, 121193, 121194, 121195, 121196, 121197, 121198, 121199, 121200, 121201, 121202, 121203, 121204, 121205, 121206, 121207, 121208, 121209, 121210, 121211, 121212, 121213, 121214, 121215, 121216, 121217, 121218, 121219, 121220, 121221, 121222, 121223, 121224, 121225, 121226, 121227, 121228, 121229, 121230, 121231, 121232, 121233, 121234, 121235, 121236, 121237, 121238, 121239, 121240, 121241, 121242, 121243, 121244, 121245, 121246, 121247, 121248, 121249, 121250, 121251, 121252, 121253, 121254, 121255, 121256, 121257, 121258, 121259, 121260, 121261, 121262, 121263, 121264, 121265, 121266, 121267, 121268, 121269, 121270, 121271, 121272, 121273, 121274, 121275, 121276, 121277, 121278, 121279, 121280, 121281, 121282, 121283, 121284, 121285, 121286, 121287, 121288, 121289, 121290, 121291, 121292, 121293, 121294, 121295, 121296, 121297, 121298, 121299, 121300, 121301, 121302, 121303, 121304, 121305, 121306, 121307, 121308, 121309, 121310, 121311, 121312, 121313, 121314, 121315, 121316, 121317, 121318, 121319, 121320, 121321, 121322, 121323, 121324, 121325, 121326, 121327, 121328, 121329, 121330, 121331, 121332, 121333, 121334, 121335, 121336, 121337, 121338, 121339, 121340, 121341, 121342, 121343}; +int bnproc_end_idx[121344] = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2070, 2070, 2070, 2070, 2070, 2070, 2070, 2070, 2070, 2070, 2070, 2070, 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119468, 119469, 119470, 119471, 119472, 119473, 119474, 119475, 119476, 119477, 119478, 119479, 119480, 119481, 119482, 119483, 119484, 119485, 119486, 119487, 119488, 119489, 119490, 119491, 119492, 119493, 119494, 119495, 119496, 119497, 119498, 119499, 119500, 119501, 119502, 119503, 119504, 119505, 119506, 119507, 119508, 119509, 119510, 119511, 119512, 119513, 119514, 119515, 119516, 119517, 119518, 119519, 119520, 119521, 119522, 119523, 119524, 119525, 119526, 119527, 119528, 119529, 119530, 119531, 119532, 119533, 119534, 119535, 119536, 119537, 119538, 119539, 119540, 119541, 119542, 119543, 119544, 119545, 119546, 119547, 119548, 119549, 119550, 119551, 119552, 119553, 119554, 119555, 119556, 119557, 119558, 119559, 119560, 119561, 119562, 119563, 119564, 119565, 119566, 119567, 119568, 119569, 119570, 119571, 119572, 119573, 119574, 119575, 119576, 119577, 119578, 119579, 119580, 119581, 119582, 119583, 119584, 119585, 119586, 119587, 119588, 119589, 119590, 119591, 119592, 119593, 119594, 119595, 119596, 119597, 119598, 119599, 119600, 119601, 119602, 119603, 119604, 119605, 119606, 119607, 119608, 119609, 119610, 119611, 119612, 119613, 119614, 119615, 119616, 119617, 119618, 119619, 119620, 119621, 119622, 119623, 119624, 119625, 119626, 119627, 119628, 119629, 119630, 119631, 119632, 119633, 119634, 119635, 119636, 119637, 119638, 119639, 119640, 119641, 119642, 119643, 119644, 119645, 119646, 119647, 119648, 119649, 119650, 119651, 119652, 119653, 119654, 119655, 119656, 119657, 119658, 119659, 119660, 119661, 119662, 119663, 119664, 119665, 119666, 119667, 119668, 119669, 119670, 119671, 119672, 119673, 119674, 119675, 119676, 119677, 119678, 119679, 119680, 119681, 119682, 119683, 119684, 119685, 119686, 119687, 119688, 119689, 119690, 119691, 119692, 119693, 119694, 119695, 119696, 119697, 119698, 119699, 119700, 119701, 119702, 119703, 119704, 119705, 119706, 119707, 119708, 119709, 119710, 119711, 119712, 119713, 119714, 119715, 119716, 119717, 119718, 119719, 119720, 119721, 119722, 119723, 119724, 119725, 119726, 119727, 119728, 119729, 119730, 119731, 119732, 119733, 119734, 119735, 119736, 119737, 119738, 119739, 119740, 119741, 119742, 119743, 119744, 119745, 119746, 119747, 119748, 119749, 119750, 119751, 119752, 119753, 119754, 119755, 119756, 119757, 119758, 119759, 119760, 119761, 119762, 119763, 119764, 119765, 119766, 119767, 119768, 119769, 119770, 119771, 119772, 119773, 119774, 119775, 119776, 119777, 119778, 119779, 119780, 119781, 119782, 119783, 119784, 119785, 119786, 119787, 119788, 119789, 119790, 119791, 119792, 119793, 119794, 119795, 119796, 119797, 119798, 119799, 119800, 119801, 119802, 119803, 119804, 119805, 119806, 119807, 119808, 119809, 119810, 119811, 119812, 119813, 119814, 119815, 119816, 119817, 119818, 119819, 119820, 119821, 119822, 119823, 119824, 119825, 119826, 119827, 119828, 119829, 119830, 119831, 119832, 119833, 119834, 119835, 119836, 119837, 119838, 119839, 119840, 119841, 119842, 119843, 119844, 119845, 119846, 119847, 119848, 119849, 119850, 119851, 119852, 119853, 119854, 119855, 119856, 119857, 119858, 119859, 119860, 119861, 119862, 119863, 119864, 119865, 119866, 119867, 119868, 119869, 119870, 119871, 119872, 119873, 119874, 119875, 119876, 119877, 119878, 119879, 119880, 119881, 119882, 119883, 119884, 119885, 119886, 119887, 119888, 119889, 119890, 119891, 119892, 119893, 119894, 119895, 119896, 119897, 119898, 119899, 119900, 119901, 119902, 119903, 119904, 119905, 119906, 119907, 119908, 119909, 119910, 119911, 119912, 119913, 119914, 119915, 119916, 119917, 119918, 119919, 119920, 119921, 119922, 119923, 119924, 119925, 119926, 119927, 119928, 119929, 119930, 119931, 119932, 119933, 119934, 119935, 119936, 119937, 119938, 119939, 119940, 119941, 119942, 119943, 119944, 119945, 119946, 119947, 119948, 119949, 119950, 119951, 119952, 119953, 119954, 119955, 119956, 119957, 119958, 119959, 119960, 119961, 119962, 119963, 119964, 119965, 119966, 119967, 119968, 119969, 119970, 119971, 119972, 119973, 119974, 119975, 119976, 119977, 119978, 119979, 119980, 119981, 119982, 119983, 119984, 119985, 119986, 119987, 119988, 119989, 119990, 119991, 119992, 119993, 119994, 119995, 119996, 119997, 119998, 119999, 120000, 120001, 120002, 120003, 120004, 120005, 120006, 120007, 120008, 120009, 120010, 120011, 120012, 120013, 120014, 120015, 120016, 120017, 120018, 120019, 120020, 120021, 120022, 120023, 120024, 120025, 120026, 120027, 120028, 120029, 120030, 120031, 120032, 120033, 120034, 120035, 120036, 120037, 120038, 120039, 120040, 120041, 120042, 120043, 120044, 120045, 120046, 120047, 120048, 120049, 120050, 120051, 120052, 120053, 120054, 120055, 120056, 120057, 120058, 120059, 120060, 120061, 120062, 120063, 120064, 120065, 120066, 120067, 120068, 120069, 120070, 120071, 120072, 120073, 120074, 120075, 120076, 120077, 120078, 120079, 120080, 120081, 120082, 120083, 120084, 120085, 120086, 120087, 120088, 120089, 120090, 120091, 120092, 120093, 120094, 120095, 120096, 120097, 120098, 120099, 120100, 120101, 120102, 120103, 120104, 120105, 120106, 120107, 120108, 120109, 120110, 120111, 120112, 120113, 120114, 120115, 120116, 120117, 120118, 120119, 120120, 120121, 120122, 120123, 120124, 120125, 120126, 120127, 120128, 120129, 120130, 120131, 120132, 120133, 120134, 120135, 120136, 120137, 120138, 120139, 120140, 120141, 120142, 120143, 120144, 120145, 120146, 120147, 120148, 120149, 120150, 120151, 120152, 120153, 120154, 120155, 120156, 120157, 120158, 120159, 120160, 120161, 120162, 120163, 120164, 120165, 120166, 120167, 120168, 120169, 120170, 120171, 120172, 120173, 120174, 120175, 120176, 120177, 120178, 120179, 120180, 120181, 120182, 120183, 120184, 120185, 120186, 120187, 120188, 120189, 120190, 120191, 120192, 120193, 120194, 120195, 120196, 120197, 120198, 120199, 120200, 120201, 120202, 120203, 120204, 120205, 120206, 120207, 120208, 120209, 120210, 120211, 120212, 120213, 120214, 120215, 120216, 120217, 120218, 120219, 120220, 120221, 120222, 120223, 120224, 120225, 120226, 120227, 120228, 120229, 120230, 120231, 120232, 120233, 120234, 120235, 120236, 120237, 120238, 120239, 120240, 120241, 120242, 120243, 120244, 120245, 120246, 120247, 120248, 120249, 120250, 120251, 120252, 120253, 120254, 120255, 120256, 120257, 120258, 120259, 120260, 120261, 120262, 120263, 120264, 120265, 120266, 120267, 120268, 120269, 120270, 120271, 120272, 120273, 120274, 120275, 120276, 120277, 120278, 120279, 120280, 120281, 120282, 120283, 120284, 120285, 120286, 120287, 120288, 120289, 120290, 120291, 120292, 120293, 120294, 120295, 120296, 120297, 120298, 120299, 120300, 120301, 120302, 120303, 120304, 120305, 120306, 120307, 120308, 120309, 120310, 120311, 120312, 120313, 120314, 120315, 120316, 120317, 120318, 120319, 120320, 120321, 120322, 120323, 120324, 120325, 120326, 120327, 120328, 120329, 120330, 120331, 120332, 120333, 120334, 120335, 120336, 120337, 120338, 120339, 120340, 120341, 120342, 120343, 120344, 120345, 120346, 120347, 120348, 120349, 120350, 120351, 120352, 120353, 120354, 120355, 120356, 120357, 120358, 120359, 120360, 120361, 120362, 120363, 120364, 120365, 120366, 120367, 120368, 120369, 120370, 120371, 120372, 120373, 120374, 120375, 120376, 120377, 120378, 120379, 120380, 120381, 120382, 120383, 120384, 120385, 120386, 120387, 120388, 120389, 120390, 120391, 120392, 120393, 120394, 120395, 120396, 120397, 120398, 120399, 120400, 120401, 120402, 120403, 120404, 120405, 120406, 120407, 120408, 120409, 120410, 120411, 120412, 120413, 120414, 120415, 120416, 120417, 120418, 120419, 120420, 120421, 120422, 120423, 120424, 120425, 120426, 120427, 120428, 120429, 120430, 120431, 120432, 120433, 120434, 120435, 120436, 120437, 120438, 120439, 120440, 120441, 120442, 120443, 120444, 120445, 120446, 120447, 120448, 120449, 120450, 120451, 120452, 120453, 120454, 120455, 120456, 120457, 120458, 120459, 120460, 120461, 120462, 120463, 120464, 120465, 120466, 120467, 120468, 120469, 120470, 120471, 120472, 120473, 120474, 120475, 120476, 120477, 120478, 120479, 120480, 120481, 120482, 120483, 120484, 120485, 120486, 120487, 120488, 120489, 120490, 120491, 120492, 120493, 120494, 120495, 120496, 120497, 120498, 120499, 120500, 120501, 120502, 120503, 120504, 120505, 120506, 120507, 120508, 120509, 120510, 120511, 120512, 120513, 120514, 120515, 120516, 120517, 120518, 120519, 120520, 120521, 120522, 120523, 120524, 120525, 120526, 120527, 120528, 120529, 120530, 120531, 120532, 120533, 120534, 120535, 120536, 120537, 120538, 120539, 120540, 120541, 120542, 120543, 120544, 120545, 120546, 120547, 120548, 120549, 120550, 120551, 120552, 120553, 120554, 120555, 120556, 120557, 120558, 120559, 120560, 120561, 120562, 120563, 120564, 120565, 120566, 120567, 120568, 120569, 120570, 120571, 120572, 120573, 120574, 120575, 120576, 120577, 120578, 120579, 120580, 120581, 120582, 120583, 120584, 120585, 120586, 120587, 120588, 120589, 120590, 120591, 120592, 120593, 120594, 120595, 120596, 120597, 120598, 120599, 120600, 120601, 120602, 120603, 120604, 120605, 120606, 120607, 120608, 120609, 120610, 120611, 120612, 120613, 120614, 120615, 120616, 120617, 120618, 120619, 120620, 120621, 120622, 120623, 120624, 120625, 120626, 120627, 120628, 120629, 120630, 120631, 120632, 120633, 120634, 120635, 120636, 120637, 120638, 120639, 120640, 120641, 120642, 120643, 120644, 120645, 120646, 120647, 120648, 120649, 120650, 120651, 120652, 120653, 120654, 120655, 120656, 120657, 120658, 120659, 120660, 120661, 120662, 120663, 120664, 120665, 120666, 120667, 120668, 120669, 120670, 120671, 120672, 120673, 120674, 120675, 120676, 120677, 120678, 120679, 120680, 120681, 120682, 120683, 120684, 120685, 120686, 120687, 120688, 120689, 120690, 120691, 120692, 120693, 120694, 120695, 120696, 120697, 120698, 120699, 120700, 120701, 120702, 120703, 120704, 120705, 120706, 120707, 120708, 120709, 120710, 120711, 120712, 120713, 120714, 120715, 120716, 120717, 120718, 120719, 120720, 120721, 120722, 120723, 120724, 120725, 120726, 120727, 120728, 120729, 120730, 120731, 120732, 120733, 120734, 120735, 120736, 120737, 120738, 120739, 120740, 120741, 120742, 120743, 120744, 120745, 120746, 120747, 120748, 120749, 120750, 120751, 120752, 120753, 120754, 120755, 120756, 120757, 120758, 120759, 120760, 120761, 120762, 120763, 120764, 120765, 120766, 120767, 120768, 120769, 120770, 120771, 120772, 120773, 120774, 120775, 120776, 120777, 120778, 120779, 120780, 120781, 120782, 120783, 120784, 120785, 120786, 120787, 120788, 120789, 120790, 120791, 120792, 120793, 120794, 120795, 120796, 120797, 120798, 120799, 120800, 120801, 120802, 120803, 120804, 120805, 120806, 120807, 120808, 120809, 120810, 120811, 120812, 120813, 120814, 120815, 120816, 120817, 120818, 120819, 120820, 120821, 120822, 120823, 120824, 120825, 120826, 120827, 120828, 120829, 120830, 120831, 120832, 120833, 120834, 120835, 120836, 120837, 120838, 120839, 120840, 120841, 120842, 120843, 120844, 120845, 120846, 120847, 120848, 120849, 120850, 120851, 120852, 120853, 120854, 120855, 120856, 120857, 120858, 120859, 120860, 120861, 120862, 120863, 120864, 120865, 120866, 120867, 120868, 120869, 120870, 120871, 120872, 120873, 120874, 120875, 120876, 120877, 120878, 120879, 120880, 120881, 120882, 120883, 120884, 120885, 120886, 120887, 120888, 120889, 120890, 120891, 120892, 120893, 120894, 120895, 120896, 120897, 120898, 120899, 120900, 120901, 120902, 120903, 120904, 120905, 120906, 120907, 120908, 120909, 120910, 120911, 120912, 120913, 120914, 120915, 120916, 120917, 120918, 120919, 120920, 120921, 120922, 120923, 120924, 120925, 120926, 120927, 120928, 120929, 120930, 120931, 120932, 120933, 120934, 120935, 120936, 120937, 120938, 120939, 120940, 120941, 120942, 120943, 120944, 120945, 120946, 120947, 120948, 120949, 120950, 120951, 120952, 120953, 120954, 120955, 120956, 120957, 120958, 120959, 120960, 120961, 120962, 120963, 120964, 120965, 120966, 120967, 120968, 120969, 120970, 120971, 120972, 120973, 120974, 120975, 120976, 120977, 120978, 120979, 120980, 120981, 120982, 120983, 120984, 120985, 120986, 120987, 120988, 120989, 120990, 120991, 120992, 120993, 120994, 120995, 120996, 120997, 120998, 120999, 121000, 121001, 121002, 121003, 121004, 121005, 121006, 121007, 121008, 121009, 121010, 121011, 121012, 121013, 121014, 121015, 121016, 121017, 121018, 121019, 121020, 121021, 121022, 121023, 121024, 121025, 121026, 121027, 121028, 121029, 121030, 121031, 121032, 121033, 121034, 121035, 121036, 121037, 121038, 121039, 121040, 121041, 121042, 121043, 121044, 121045, 121046, 121047, 121048, 121049, 121050, 121051, 121052, 121053, 121054, 121055, 121056, 121057, 121058, 121059, 121060, 121061, 121062, 121063, 121064, 121065, 121066, 121067, 121068, 121069, 121070, 121071, 121072, 121073, 121074, 121075, 121076, 121077, 121078, 121079, 121080, 121081, 121082, 121083, 121084, 121085, 121086, 121087, 121088, 121089, 121090, 121091, 121092, 121093, 121094, 121095, 121096, 121097, 121098, 121099, 121100, 121101, 121102, 121103, 121104, 121105, 121106, 121107, 121108, 121109, 121110, 121111, 121112, 121113, 121114, 121115, 121116, 121117, 121118, 121119, 121120, 121121, 121122, 121123, 121124, 121125, 121126, 121127, 121128, 121129, 121130, 121131, 121132, 121133, 121134, 121135, 121136, 121137, 121138, 121139, 121140, 121141, 121142, 121143, 121144, 121145, 121146, 121147, 121148, 121149, 121150, 121151, 121152, 121153, 121154, 121155, 121156, 121157, 121158, 121159, 121160, 121161, 121162, 121163, 121164, 121165, 121166, 121167, 121168, 121169, 121170, 121171, 121172, 121173, 121174, 121175, 121176, 121177, 121178, 121179, 121180, 121181, 121182, 121183, 121184, 121185, 121186, 121187, 121188, 121189, 121190, 121191, 121192, 121193, 121194, 121195, 121196, 121197, 121198, 121199, 121200, 121201, 121202, 121203, 121204, 121205, 121206, 121207, 121208, 121209, 121210, 121211, 121212, 121213, 121214, 121215, 121216, 121217, 121218, 121219, 121220, 121221, 121222, 121223, 121224, 121225, 121226, 121227, 121228, 121229, 121230, 121231, 121232, 121233, 121234, 121235, 121236, 121237, 121238, 121239, 121240, 121241, 121242, 121243, 121244, 121245, 121246, 121247, 121248, 121249, 121250, 121251, 121252, 121253, 121254, 121255, 121256, 121257, 121258, 121259, 121260, 121261, 121262, 121263, 121264, 121265, 121266, 121267, 121268, 121269, 121270, 121271, 121272, 121273, 121274, 121275, 121276, 121277, 121278, 121279, 121280, 121281, 121282, 121283, 121284, 121285, 121286, 121287, 121288, 121289, 121290, 121291, 121292, 121293, 121294, 121295, 121296, 121297, 121298, 121299, 121300, 121301, 121302, 121303, 121304, 121305, 121306, 121307, 121308, 121309, 121310, 121311, 121312, 121313, 121314, 121315, 121316, 121317, 121318, 121319, 121320, 121321, 121322, 121323, 121324, 121325, 121326, 121327, 121328, 121329, 121330, 121331, 121332, 121333, 121334, 121335, 121336, 121337, 121338, 121339, 121340, 121341, 121342, 121343, 121344}; +int llr_idx[26113] = { 0, 30, 60, 90, 120, 150, 180, 210, 240, 270, 300, 330, 360, 390, 420, 450, 480, 510, 540, 570, 600, 630, 660, 690, 720, 750, 780, 810, 840, 870, 900, 930, 960, 990, 1020, 1050, 1080, 1110, 1140, 1170, 1200, 1230, 1260, 1290, 1320, 1350, 1380, 1410, 1440, 1470, 1500, 1530, 1560, 1590, 1620, 1650, 1680, 1710, 1740, 1770, 1800, 1830, 1860, 1890, 1920, 1950, 1980, 2010, 2040, 2070, 2100, 2130, 2160, 2190, 2220, 2250, 2280, 2310, 2340, 2370, 2400, 2430, 2460, 2490, 2520, 2550, 2580, 2610, 2640, 2670, 2700, 2730, 2760, 2790, 2820, 2850, 2880, 2910, 2940, 2970, 3000, 3030, 3060, 3090, 3120, 3150, 3180, 3210, 3240, 3270, 3300, 3330, 3360, 3390, 3420, 3450, 3480, 3510, 3540, 3570, 3600, 3630, 3660, 3690, 3720, 3750, 3780, 3810, 3840, 3870, 3900, 3930, 3960, 3990, 4020, 4050, 4080, 4110, 4140, 4170, 4200, 4230, 4260, 4290, 4320, 4350, 4380, 4410, 4440, 4470, 4500, 4530, 4560, 4590, 4620, 4650, 4680, 4710, 4740, 4770, 4800, 4830, 4860, 4890, 4920, 4950, 4980, 5010, 5040, 5070, 5100, 5130, 5160, 5190, 5220, 5250, 5280, 5310, 5340, 5370, 5400, 5430, 5460, 5490, 5520, 5550, 5580, 5610, 5640, 5670, 5700, 5730, 5760, 5790, 5820, 5850, 5880, 5910, 5940, 5970, 6000, 6030, 6060, 6090, 6120, 6150, 6180, 6210, 6240, 6270, 6300, 6330, 6360, 6390, 6420, 6450, 6480, 6510, 6540, 6570, 6600, 6630, 6660, 6690, 6720, 6750, 6780, 6810, 6840, 6870, 6900, 6930, 6960, 6990, 7020, 7050, 7080, 7110, 7140, 7170, 7200, 7230, 7260, 7290, 7320, 7350, 7380, 7410, 7440, 7470, 7500, 7530, 7560, 7590, 7620, 7650, 7680, 7710, 7740, 7770, 7800, 7830, 7860, 7890, 7920, 7950, 7980, 8010, 8040, 8070, 8100, 8130, 8160, 8190, 8220, 8250, 8280, 8310, 8340, 8370, 8400, 8430, 8460, 8490, 8520, 8550, 8580, 8610, 8640, 8670, 8700, 8730, 8760, 8790, 8820, 8850, 8880, 8910, 8940, 8970, 9000, 9030, 9060, 9090, 9120, 9150, 9180, 9210, 9240, 9270, 9300, 9330, 9360, 9390, 9420, 9450, 9480, 9510, 9540, 9570, 9600, 9630, 9660, 9690, 9720, 9750, 9780, 9810, 9840, 9870, 9900, 9930, 9960, 9990, 10020, 10050, 10080, 10110, 10140, 10170, 10200, 10230, 10260, 10290, 10320, 10350, 10380, 10410, 10440, 10470, 10500, 10530, 10560, 10590, 10620, 10650, 10680, 10710, 10740, 10770, 10800, 10830, 10860, 10890, 10920, 10950, 10980, 11010, 11040, 11070, 11100, 11130, 11160, 11190, 11220, 11250, 11280, 11310, 11340, 11370, 11400, 11430, 11460, 11490, 11520, 11548, 11576, 11604, 11632, 11660, 11688, 11716, 11744, 11772, 11800, 11828, 11856, 11884, 11912, 11940, 11968, 11996, 12024, 12052, 12080, 12108, 12136, 12164, 12192, 12220, 12248, 12276, 12304, 12332, 12360, 12388, 12416, 12444, 12472, 12500, 12528, 12556, 12584, 12612, 12640, 12668, 12696, 12724, 12752, 12780, 12808, 12836, 12864, 12892, 12920, 12948, 12976, 13004, 13032, 13060, 13088, 13116, 13144, 13172, 13200, 13228, 13256, 13284, 13312, 13340, 13368, 13396, 13424, 13452, 13480, 13508, 13536, 13564, 13592, 13620, 13648, 13676, 13704, 13732, 13760, 13788, 13816, 13844, 13872, 13900, 13928, 13956, 13984, 14012, 14040, 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121167, 121168, 121169, 121170, 121171, 121172, 121173, 121174, 121175, 121176, 121177, 121178, 121179, 121180, 121181, 121182, 121183, 121184, 121185, 121186, 121187, 121188, 121189, 121190, 121191, 121192, 121193, 121194, 121195, 121196, 121197, 121198, 121199, 121200, 121201, 121202, 121203, 121204, 121205, 121206, 121207, 121208, 121209, 121210, 121211, 121212, 121213, 121214, 121215, 121216, 121217, 121218, 121219, 121220, 121221, 121222, 121223, 121224, 121225, 121226, 121227, 121228, 121229, 121230, 121231, 121232, 121233, 121234, 121235, 121236, 121237, 121238, 121239, 121240, 121241, 121242, 121243, 121244, 121245, 121246, 121247, 121248, 121249, 121250, 121251, 121252, 121253, 121254, 121255, 121256, 121257, 121258, 121259, 121260, 121261, 121262, 121263, 121264, 121265, 121266, 121267, 121268, 121269, 121270, 121271, 121272, 121273, 121274, 121275, 121276, 121277, 121278, 121279, 121280, 121281, 121282, 121283, 121284, 121285, 121286, 121287, 121288, 121289, 121290, 121291, 121292, 121293, 121294, 121295, 121296, 121297, 121298, 121299, 121300, 121301, 121302, 121303, 121304, 121305, 121306, 121307, 121308, 121309, 121310, 121311, 121312, 121313, 121314, 121315, 121316, 121317, 121318, 121319, 121320, 121321, 121322, 121323, 121324, 121325, 121326, 121327, 121328, 121329, 121330, 121331, 121332, 121333, 121334, 121335, 121336, 121337, 121338, 121339, 121340, 121341, 121342, 121343, 121344}; +int l2b_idx[121344] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 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25643, 25644, 25645, 25646, 25647, 25648, 25649, 25650, 25651, 25652, 25653, 25654, 25655, 25656, 25657, 25658, 25659, 25660, 25661, 25662, 25663, 25664, 25665, 25666, 25667, 25668, 25669, 25670, 25671, 25672, 25673, 25674, 25675, 25676, 25677, 25678, 25679, 25680, 25681, 25682, 25683, 25684, 25685, 25686, 25687, 25688, 25689, 25690, 25691, 25692, 25693, 25694, 25695, 25696, 25697, 25698, 25699, 25700, 25701, 25702, 25703, 25704, 25705, 25706, 25707, 25708, 25709, 25710, 25711, 25712, 25713, 25714, 25715, 25716, 25717, 25718, 25719, 25720, 25721, 25722, 25723, 25724, 25725, 25726, 25727, 25728, 25729, 25730, 25731, 25732, 25733, 25734, 25735, 25736, 25737, 25738, 25739, 25740, 25741, 25742, 25743, 25744, 25745, 25746, 25747, 25748, 25749, 25750, 25751, 25752, 25753, 25754, 25755, 25756, 25757, 25758, 25759, 25760, 25761, 25762, 25763, 25764, 25765, 25766, 25767, 25768, 25769, 25770, 25771, 25772, 25773, 25774, 25775, 25776, 25777, 25778, 25779, 25780, 25781, 25782, 25783, 25784, 25785, 25786, 25787, 25788, 25789, 25790, 25791, 25792, 25793, 25794, 25795, 25796, 25797, 25798, 25799, 25800, 25801, 25802, 25803, 25804, 25805, 25806, 25807, 25808, 25809, 25810, 25811, 25812, 25813, 25814, 25815, 25816, 25817, 25818, 25819, 25820, 25821, 25822, 25823, 25824, 25825, 25826, 25827, 25828, 25829, 25830, 25831, 25832, 25833, 25834, 25835, 25836, 25837, 25838, 25839, 25840, 25841, 25842, 25843, 25844, 25845, 25846, 25847, 25848, 25849, 25850, 25851, 25852, 25853, 25854, 25855, 25856, 25857, 25858, 25859, 25860, 25861, 25862, 25863, 25864, 25865, 25866, 25867, 25868, 25869, 25870, 25871, 25872, 25873, 25874, 25875, 25876, 25877, 25878, 25879, 25880, 25881, 25882, 25883, 25884, 25885, 25886, 25887, 25888, 25889, 25890, 25891, 25892, 25893, 25894, 25895, 25896, 25897, 25898, 25899, 25900, 25901, 25902, 25903, 25904, 25905, 25906, 25907, 25908, 25909, 25910, 25911, 25912, 25913, 25914, 25915, 25916, 25917, 25918, 25919, 25920, 25921, 25922, 25923, 25924, 25925, 25926, 25927, 25928, 25929, 25930, 25931, 25932, 25933, 25934, 25935, 25936, 25937, 25938, 25939, 25940, 25941, 25942, 25943, 25944, 25945, 25946, 25947, 25948, 25949, 25950, 25951, 25952, 25953, 25954, 25955, 25956, 25957, 25958, 25959, 25960, 25961, 25962, 25963, 25964, 25965, 25966, 25967, 25968, 25969, 25970, 25971, 25972, 25973, 25974, 25975, 25976, 25977, 25978, 25979, 25980, 25981, 25982, 25983, 25984, 25985, 25986, 25987, 25988, 25989, 25990, 25991, 25992, 25993, 25994, 25995, 25996, 25997, 25998, 25999, 26000, 26001, 26002, 26003, 26004, 26005, 26006, 26007, 26008, 26009, 26010, 26011, 26012, 26013, 26014, 26015, 26016, 26017, 26018, 26019, 26020, 26021, 26022, 26023, 26024, 26025, 26026, 26027, 26028, 26029, 26030, 26031, 26032, 26033, 26034, 26035, 26036, 26037, 26038, 26039, 26040, 26041, 26042, 26043, 26044, 26045, 26046, 26047, 26048, 26049, 26050, 26051, 26052, 26053, 26054, 26055, 26056, 26057, 26058, 26059, 26060, 26061, 26062, 26063, 26064, 26065, 26066, 26067, 26068, 26069, 26070, 26071, 26072, 26073, 26074, 26075, 26076, 26077, 26078, 26079, 26080, 26081, 26082, 26083, 26084, 26085, 26086, 26087, 26088, 26089, 26090, 26091, 26092, 26093, 26094, 26095, 26096, 26097, 26098, 26099, 26100, 26101, 26102, 26103, 26104, 26105, 26106, 26107, 26108, 26109, 26110, 26111}; diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/check.sh b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/check.sh new file mode 100644 index 0000000000..98814432df --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/check.sh @@ -0,0 +1,10 @@ +set +x +index=1 +for file in ../test_input/8448/* +do + cp $file channel_output.txt + echo "===== test $index =====" >> log.txt + ./ldpc channel_output.txt >> log.txt + echo ' ' >> log.txt + index=$((index+1)) + done diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/gen_idx.c b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/gen_idx.c new file mode 100644 index 0000000000..795918dec6 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/gen_idx.c @@ -0,0 +1,198 @@ +#include +#include +#include +#ifndef test +#include "../BGs/isip_ldpc_bg1_i1.h" +#endif +int l2c_idx[316*384] = {}; // cnbuf[ tid ] = llr[ l2c_idx[tid] ] +int l2b_idx[316*384] = {}; // bnbuf[ tid ] = llr[ l2b_idx[tid] ] +int llr_idx[26113] = {}; // bnbuf2llr, start = llr_idx[tid], end = llr_idx[tid+1], llrbuf[tid] = sum of (bnbuf[start] to bnbuf[end]) +int c2b_idx[316*384] = {}; // bnbuf[ tid ] = cnbuf[ c2b_idx[tid] ] +int b2c_idx[316*384] = {}; // cnbuf[ tid ] = bnbuf[ b2c_idx[tid] ] +int cnproc_start_idx[316*384] = {}; // index for cnproc, int start = cnproc_start_idx[tid] +int cnproc_end_idx[316*384] = {}; // index for cnproc, int end = cnproc_end_idx[tid] +int bnproc_start_idx[316*384] = {}; // index for bnproc, int start = bnproc_start_idx[tid] +int bnproc_end_idx[316*384] = {}; // index for bnproc, int end = bnproc_end_idx[tid] + +int *matrix_transpose(int *matrix, int row, int col) +{ + +} + +void write_to_file(FILE *fp, const char *arr_name, int *arr, int size) +{ + fprintf(fp, "%s[%d] = { %d", arr_name, size, arr[0]); + for(int i = 1; i < size; i++){ + fprintf(fp, ", %d", arr[i]); + } + fprintf(fp, "};\n"); +} + +void matrix_expansion(const int *BG, int row, int col, int Zc, int *matrix) +{ + for(int i = 0; i < row; i++){ + for(int j = 0; j < col; j++){ + int val = BG[i * col + j]; + if(val != 0){ + val = (val-1)%Zc; + for(int k = i*Zc; k < (i+1)*Zc; k++){ + int idx = k*(col*Zc) + (j*Zc+val); + matrix[idx] = 1; + val = (val+1)%Zc; + } + } + } + } +} + +void print_matrix(const int *M, int row, int col) +{ + printf("Matrix:\n{\n"); + for(int i = 0; i < row; i++){ + printf("\t"); + for(int j = 0; j < col; j++){ + printf(" %d,", M[i*col + j]); + } + printf("\n"); + } + printf("}\n"); +} + + +void build_index(const int *BG, int row, int col, int Zc) +{ + int *matrix = (int*)malloc(row*col*Zc*Zc*sizeof(int)); + int cnidx = 0, bnidx = 0, aidx = 0, pidx = 0, lidx1 = 0, lidx2 = 0; + + matrix_expansion(BG, row, col, Zc, matrix); + + // cn label & l2c_idx + for(int i = 0; i < row*Zc; i++){ + for(int j = 0; j < col*Zc; j++){ + int k = i*col*Zc + j; + if(matrix[k] == 1){ + matrix[k] = cnidx+1; + l2c_idx[cnidx] = j; + cnidx++; + } + } + } + + // build c2b_idx & bnproc_idx + for(int i = 0; i < col*Zc; i++){ + int cnt = 0; + int start = aidx, end = 0; + for(int j = 0; j < row*Zc; j++){ + int val = matrix[i + j*col*Zc]; + if(val != 0){ + c2b_idx[aidx] = val -1; + aidx++, cnt++; + } + } + end = start + cnt; + while(cnt--){ + bnproc_start_idx[pidx] = start; + bnproc_end_idx[pidx] = end; + pidx++; + } + } + + printf("cnidx %d\naidx %d\npidx %d\n", cnidx, aidx, pidx); + + matrix_expansion(BG, row, col, Zc, matrix); + + // bn label & llr_idx + for(int i = 0; i < col*Zc; i++){ + llr_idx[lidx1++] = bnidx; + for(int j = 0; j < row*Zc; j++){ + int k = i + j*col*Zc; + if(matrix[k] == 1){ + matrix[k] = bnidx+1; + l2b_idx[lidx2++] = i; + bnidx++; + } + } + } + llr_idx[lidx1] = bnidx; + + // build b2c_idx & cnproc_idx + aidx = pidx = 0; + for(int i = 0; i < row*Zc; i++){ + int cnt = 0; + int start = aidx, end = 0; + for(int j = 0; j < col*Zc; j++){ + int val = matrix[i*col*Zc + j]; + if(val != 0){ + b2c_idx[aidx] = val - 1; + aidx++, cnt++; + } + } + end = start + cnt; + while(cnt--){ + cnproc_start_idx[pidx] = start; + cnproc_end_idx[pidx] = end; + pidx++; + } + } + + printf("bnidx %d\naidx %d\npidx %d\n", bnidx, aidx, pidx); + printf("lidx1 %d\nlidx2 %d\n", lidx1, lidx2); + + free(matrix); +} + +void generate_header(const char *file, int col, int entry, int Zc) +{ +#ifdef test + FILE *f = fopen("test.h", "w"); +#else + FILE *f = fopen(file, "w"); +#endif + write_to_file(f, "int l2c_idx", l2c_idx, entry*Zc); + write_to_file(f, "int c2b_idx", c2b_idx, entry*Zc); + write_to_file(f, "int b2c_idx", b2c_idx, entry*Zc); + write_to_file(f, "int cnproc_start_idx", cnproc_start_idx, entry*Zc); + write_to_file(f, "int cnproc_end_idx", cnproc_end_idx, entry*Zc); + write_to_file(f, "int bnproc_start_idx", bnproc_start_idx, entry*Zc); + write_to_file(f, "int bnproc_end_idx", bnproc_end_idx, entry*Zc); + write_to_file(f, "int llr_idx", llr_idx, col*Zc+1); + write_to_file(f, "int l2b_idx", l2b_idx, entry*Zc); + + fclose(f); +} + + +int main(int argc, char** argv) +{ + int test_BG[4*5] ={ 2, 0, 1, 2, 0, + 0, 3, 0, 2, 2, + 1, 0, 3, 3, 0, + 0, 3, 0, 0, 1}; + // default + int idx = 0, Zc = 384, BG = 1; + int max_row = 46, max_col = 68; + int entry = 316; + char *header_file = "bg1_i1_index_array.h"; +#ifdef test + if(argc == 1){ + printf("\nusage: %s [BG_row] [BG_col] [Zc] [entry] [output_header]\n\n", argv[0]); + return -1; + } +#endif + if(argc == 6){ + max_row = atoi(argv[1]); + max_col = atoi(argv[2]); + Zc = atoi(argv[3]); + entry = atoi(argv[4]); + header_file = argv[5]; + printf("max_row %d, max_col %d, Zc %d\n", max_row, max_col, Zc); + } +#ifdef test + build_index(test_BG, max_row, max_col, Zc); +#else + build_index(BG1_I1, max_row, max_col, Zc); +#endif + generate_header(header_file, max_col, entry, Zc); + + return 0; +} diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/ldpc.cu b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/ldpc.cu new file mode 100644 index 0000000000..f0f68a50f3 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/ldpc.cu @@ -0,0 +1,297 @@ +#include +#include +#include +#include +#include +#include "bg1_i1_index_array.h" + +void print_arr_cpu(const char *file, int *arr, int size) +{ + FILE *fp = fopen(file, "w"); + for(int i = 0; i < size; i++){ + fprintf(fp, "%s[%d]: %d\n", file, i, arr[i]); + } + fclose(fp); +} + +void print_arr(const char *file, int *arr, int size) +{ + int *tmp = (int*)malloc(sizeof(int)*size); + FILE *fp = fopen(file, "w"); + cudaMemcpy((void*)tmp, (const void*)arr, size*sizeof(int), cudaMemcpyDeviceToHost); + cudaDeviceSynchronize(); + for(int i = 0; i < size; i++){ + fprintf(fp, "%s[%d]: %d\n", file, i, tmp[i]); + } + free(tmp); + fclose(fp); +} + +__global__ void llr2CN(float *llr, float *cnbuf, int *l2c_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + cnbuf[tid] = llr[l2c_idx[tid]]; + __syncthreads(); +} + +__global__ void llr2BN(float *llr, float *const_llr, int *l2b_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + const_llr[tid] = llr[l2b_idx[tid]]; + __syncthreads(); +} + +__global__ void CNProcess(float *cnbuf, float *bnbuf, int *b2c_idx, int *cnproc_start_idx, int *cnproc_end_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + int start = cnproc_start_idx[tid]; + int end = cnproc_end_idx[tid]; + + + int sgn = 1, val = INT32_MAX; + for(int i = start; i < end; i++){ + if(i == tid) continue; + + int tmp = cnbuf[i]; + if(tmp < 0){ + tmp = -tmp; + sgn = -sgn; + } + if(val > tmp){ + val = tmp; + } + } + bnbuf[b2c_idx[tid]] = sgn*val;// + const_llr[tid]; + __syncthreads(); +} + +__global__ void add(int *bnbuf, int start, int pid, int *buf) +{ + __shared__ int sdata[25]; + int tid = threadIdx.x; + int num = blockDim.x; + sdata[tid] = bnbuf[start+tid]; + for(int s = num/2; s > 0; s>>=1){ + if(tid < s){ + sdata[tid] += sdata[tid+s]; + } + } + if(tid == 0){ + buf[pid] = sdata[tid]; + } +} + +__global__ void BNProcess(float *const_llr, float *bnbuf, float *cnbuf, int *c2b_idx, int *bnproc_start_idx, int *bnproc_end_idx, float *resbuf) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + float val = 0.0; + + int start = bnproc_start_idx[tid]; + int end = bnproc_end_idx[tid]; + for(int i = start; i < end; i++){ + if(i == tid) continue; + val += bnbuf[i]; + } + +// cnbuf[c2b_idx[tid]] = resbuf[tid] + const_llr[tid]; + cnbuf[c2b_idx[tid]] = val + const_llr[tid]; + __syncthreads(); +} + + +__global__ void BN2llr(float *const_llr, float *bnbuf, float *llrbuf, int *llr_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + int start = llr_idx[tid]; + int end = llr_idx[tid+1]; + + int res = 0.0; + for(int i = start; i < end; i++){ + res += bnbuf[i]; + } + llrbuf[tid] = res + const_llr[tid]; + __syncthreads(); +} + +__global__ void BitDetermination(float *BN, unsigned int *decode_d) +{ + __shared__ int tmp[256]; + int tid = blockIdx.x*256 + threadIdx.x; + int bid = threadIdx.x; + tmp[bid] = 0; + + + if(BN[tid] < 0) + { + tmp[bid] = 1 << (bid&7); + } + + __syncthreads(); + + if(threadIdx.x < 32) + { + decode_d[blockIdx.x*32 + threadIdx.x] = 0; + for(int i = 0; i < 8; i++) + { + decode_d[blockIdx.x*32 + threadIdx.x] += tmp[threadIdx.x*8+i]; + } + } +} + +void Read_Data(char *filename, int *data_sent, float *data_received) +{ + FILE *fp = fopen(filename, "r"); + fscanf(fp, "%*s"); + for(int i = 0; i < 1056; i++){ + fscanf(fp, "%d", &data_sent[i]); + } + fscanf(fp, "%*s"); + fscanf(fp, "%*s"); + fscanf(fp, "%*s"); + for(int i = 0; i < 26112; i++){ + fscanf(fp, "%f", &data_received[i]); + } + fclose(fp); +} + +int main(int argc, char **argv) +{ + int code_length = 8448, BG = 1; + int *input = (int*)malloc(1056*sizeof(int)); + float *llr = (float*)malloc(26112*sizeof(float)); + + float *llr_d, *llrbuf_d, *const_llr_d, *cnbuf_d, *bnbuf_d, *resbuf_d; + unsigned int *decode_output_h, *decode_output_d; + + int *l2c_idx_d, *cnproc_start_idx_d, *cnproc_end_idx_d, *c2b_idx_d, *bnproc_start_idx_d, *bnproc_end_idx_d, *b2c_idx_d, *llr_idx_d, *l2b_idx_d; + + char *file = argv[1]; + + + int blockNum = 237, threadNum = 512; + //int blockNum = 33, threadNum = 256; + //int blockNum = 17, threadNum = 512; + + int rounds = 5, Zc = 384; + + Read_Data(file, input, llr); + + + + size_t p_llr; + cudaHostAlloc((void**)&decode_output_h, 1056*sizeof(unsigned int), cudaHostAllocMapped); + + cudaMallocPitch((void**)&llr_d, &p_llr, 26112*sizeof(float), 1); + cudaMallocPitch((void**)&llrbuf_d, &p_llr, 26112*sizeof(float), 1); + cudaMallocPitch((void**)&const_llr_d, &p_llr, 316*384*sizeof(float), 1); + cudaMallocPitch((void**)&cnbuf_d, &p_llr, 316*384*sizeof(float), 1); + cudaMallocPitch((void**)&bnbuf_d, &p_llr, 316*384*sizeof(float), 1); + cudaMallocPitch((void**)&l2c_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&l2b_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&cnproc_start_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&cnproc_end_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&c2b_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&bnproc_start_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&bnproc_end_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&b2c_idx_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&resbuf_d, &p_llr, 316*384*sizeof(int), 1); + cudaMallocPitch((void**)&llr_idx_d, &p_llr, 26113*sizeof(int), 1); + + cudaMemcpyAsync((void*)llr_d, (const void*)llr, 68*384*sizeof(float), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)l2c_idx_d, (const void*)l2c_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)l2b_idx_d, (const void*)l2b_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)cnproc_start_idx_d, (const void*)cnproc_start_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)cnproc_end_idx_d, (const void*)cnproc_end_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)c2b_idx_d, (const void*)c2b_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)bnproc_start_idx_d, (const void*)bnproc_start_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)bnproc_end_idx_d, (const void*)bnproc_end_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)b2c_idx_d, (const void*)b2c_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)llr_idx_d, (const void*)llr_idx, 26113*sizeof(int), cudaMemcpyHostToDevice); + + cudaHostGetDevicePointer((void**)&decode_output_d, (void*)decode_output_h, 0); + cudaDeviceSynchronize(); + + + printf("BG %d, Zc %d, code_length %d\n", BG, Zc, code_length); + + + cudaEvent_t start, end; + float time; + + cudaEventCreate(&start); + cudaEventCreate(&end); + cudaEventRecord(start, 0); + + + llr2CN<<>>(llr_d, cnbuf_d, l2c_idx_d); + llr2BN<<>>(llr_d, const_llr_d, l2b_idx_d); + +/* + print_arr("debug/const_llr_d", const_llr_d, 26112); + print_arr("debug/cnbuf_d", cnbuf_d, 316*384); + print_arr("debug/const_llrbuf_d", const_llrbuf_d, 316*384); +*/ + + char dir[] = "debug/", cn[] = "cnbuf", bn[] = "bnbuf", llrstr[] = "llrbuf_d"; + char str[100] = {}; + for(int i = 0; i < rounds; i++){ + CNProcess<<>>(cnbuf_d, bnbuf_d, b2c_idx_d, cnproc_start_idx_d, cnproc_end_idx_d); +#ifdef debug + snprintf(str, 20, "%s%s_%d", dir, bn, i+1); + print_arr(str, bnbuf_d, 316*384); +#endif + BNProcess<<>>(const_llr_d, bnbuf_d, cnbuf_d, c2b_idx_d, bnproc_start_idx_d, bnproc_end_idx_d, resbuf_d); +#ifdef debug + snprintf(str, 20, "%s%s_%d", dir, cn, i+1); + print_arr(str, cnbuf_d, 316*384); +#endif + BN2llr<<<51, 512>>>(llr_d, bnbuf_d, llrbuf_d, llr_idx_d); +#ifdef debug + snprintf(str, 20, "%s%s_%d", dir, llrstr, i+1); + print_arr(str, llrbuf_d, 26112); +#endif + } + + BitDetermination<<<33, 256>>>(llrbuf_d, decode_output_d); + cudaDeviceSynchronize(); + + + cudaEventRecord(end, 0); + cudaEventSynchronize(end); + cudaEventElapsedTime(&time, start, end); + printf("time: %.6f ms\n", time); + + + int err = 0; + for(int i = 0; i < 8448/8; i++){ + if(input[i] != decode_output_h[i]){ +// printf("input[%d] :%d, decode_output[%d]: %d\n", i, input[i], i, decode_output_h[i]); + err++; + } + } + printf("err: %d\n", err); + + free(input); + free(llr); + cudaFree(llr_d); + cudaFree(llrbuf_d); + cudaFree(bnbuf_d); + cudaFree(cnbuf_d); + cudaFree(l2c_idx_d); + cudaFree(cnproc_start_idx_d); + cudaFree(cnproc_end_idx_d); + cudaFree(c2b_idx_d); + cudaFree(bnproc_start_idx_d); + cudaFree(bnproc_end_idx_d); + cudaFree(b2c_idx_d); + cudaFree(const_llr_d); + cudaFree(llr_idx_d); + cudaFree(resbuf_d); + + cudaFreeHost(decode_output_h); + return 0; +} diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.cu b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.cu new file mode 100644 index 0000000000..ad33a94b03 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.cu @@ -0,0 +1,228 @@ +#include +#include +#include +#include +#include +#include "test.h" + +void print_arr_cpu(const char *file, int *arr, int size) +{ + FILE *fp = fopen(file, "w"); + for(int i = 0; i < size; i++){ + fprintf(fp, "%s[%d]: %d\n", file, i, arr[i]); + } + fclose(fp); +} + +void print_arr(const char *file, int *arr, int size) +{ + int *tmp = (int*)malloc(sizeof(int)*size); + FILE *fp = fopen(file, "w"); + cudaMemcpy((void*)tmp, (const void*)arr, size*sizeof(int), cudaMemcpyDeviceToHost); + cudaDeviceSynchronize(); + for(int i = 0; i < size; i++){ + fprintf(fp, "%s[%d]: %d\n", file, i, tmp[i]); + } + free(tmp); + fclose(fp); +} + +__global__ void llr2CN(int *llr, int *cnbuf, int *l2c_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + cnbuf[tid] = llr[l2c_idx[tid]]; + __syncthreads(); +} + +__global__ void llr2BN(int *llr, int *const_llr, int *l2b_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + const_llr[tid] = llr[l2b_idx[tid]]; + __syncthreads(); +} + +__global__ void CNProcess(int *cnbuf, int *bnbuf, int *b2c_idx, int *cnproc_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + int start = cnproc_idx[tid*2]; + int end = cnproc_idx[tid*2+1]; +/* + if (tid == 6){ + printf("start %d, end %d\n", start, end); + } +*/ + int sgn = 1, val = INT32_MAX; + for(int i = start; i < end; i++){ + if(i == tid) continue; + + int tmp = cnbuf[i]; +// if(tid == 6) printf("tmp %d\n", tmp); + if(tmp < 0){ + tmp = -tmp; + sgn = -sgn; + } + if(val > tmp){ + val = tmp; +// if(tid == 6)printf("val = tmp\n"); + } +// if(tid == 6) printf("%d\n", val); + } +/* + if(tid == 6){ + printf("b2c_idx[6] %d\n", b2c_idx[tid]); + printf("sgn*val = %d\n", sgn*val); + printf("\n\n"); + } +*/ + bnbuf[b2c_idx[tid]] = sgn*val;// + const_llr[tid]; + __syncthreads(); +} + +__global__ void BNProcess(int *const_llr, int *bnbuf, int *cnbuf, int *c2b_idx, int *bnproc_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + int start = bnproc_idx[tid*2]; + int end = bnproc_idx[tid*2+1]; + + int val = 0; + for(int i = start; i < end; i++){ + if(i == tid) continue; + val += bnbuf[i]; + } + cnbuf[c2b_idx[tid]] = val + const_llr[tid]; + __syncthreads(); +} + +__global__ void BN2llr(int *bnbuf, int *llrbuf, int *llr_idx) +{ + int tid = blockIdx.x*blockDim.x + threadIdx.x; + + int start = llr_idx[tid]; + int end = llr_idx[tid+1]; + + int res = 0; + for(int i = start; i < end; i++){ + res += bnbuf[i]; + } + llrbuf[tid] = res; + __syncthreads(); +} + +__global__ void BitDetermination(int *BN, unsigned int *decode_d) +{ + __shared__ int tmp[256]; + int tid = blockIdx.x*256 + threadIdx.x; + int bid = threadIdx.x; + tmp[bid] = 0; + + + if(BN[tid] < 0) + { + tmp[bid] = 1 << (bid&7); + } + + __syncthreads(); + + if(threadIdx.x < 32) + { + decode_d[blockIdx.x*32 + threadIdx.x] = 0; + for(int i = 0; i < 8; i++) + { + decode_d[blockIdx.x*32 + threadIdx.x] += tmp[threadIdx.x*8+i]; + } + } +} + + +int main(int argc, char **argv) +{ + int llr[15] = {-48, 27, -47, 13, 34, + -41, 51, 29, -6, -19, + -45, -42, -40, -6, -33}; + + int *llr_d, *llrbuf_d, *const_llr_d, *cnbuf_d, *bnbuf_d; + int *l2c_idx_d, *cnproc_idx_d, *c2b_idx_d, *bnproc_idx_d, *b2c_idx_d, *llr_idx_d, *l2b_idx_d; + + int blockNum = 6, threadNum = 11; + int rounds = 5, Zc = 3; + + size_t p_llr; + + cudaMallocPitch((void**)&llr_d, &p_llr, 15*sizeof(int), 1); + cudaMallocPitch((void**)&llrbuf_d, &p_llr, 15*sizeof(int), 1); + cudaMallocPitch((void**)&const_llr_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&cnbuf_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&bnbuf_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&l2c_idx_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&l2b_idx_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&cnproc_idx_d, &p_llr, 33*2*sizeof(int), 1); + cudaMallocPitch((void**)&c2b_idx_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&bnproc_idx_d, &p_llr, 33*2*sizeof(int), 1); + cudaMallocPitch((void**)&b2c_idx_d, &p_llr, 33*sizeof(int), 1); + cudaMallocPitch((void**)&llr_idx_d, &p_llr, 16*sizeof(int), 1); + + cudaMemcpyAsync((void*)llr_d, (const void*)llr, 15*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)l2c_idx_d, (const void*)l2c_idx, 33*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)l2b_idx_d, (const void*)l2b_idx, 33*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)cnproc_idx_d, (const void*)cnproc_idx, 33*2*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)c2b_idx_d, (const void*)c2b_idx, 33*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)bnproc_idx_d, (const void*)bnproc_idx, 33*2*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)b2c_idx_d, (const void*)b2c_idx, 33*sizeof(int), cudaMemcpyHostToDevice); + cudaMemcpyAsync((void*)llr_idx_d, (const void*)llr_idx, 16*sizeof(int), cudaMemcpyHostToDevice); + + cudaDeviceSynchronize(); + + + + llr2CN<<>>(llr_d, cnbuf_d, l2c_idx_d); + llr2CN<<>>(llr_d, const_llr_d, l2b_idx_d); + +/* + print_arr("debug/const_llr_d", const_llr_d, 26112); + print_arr("debug/cnbuf_d", cnbuf_d, 316*384); + print_arr("debug/const_llrbuf_d", const_llrbuf_d, 316*384); +*/ + + char debug[] = "debug/"; + char cn[] = "cnbuf"; + char bn[] = "bnbuf"; + char llrstr[] = "llrbuf_d"; + char str[100] = {}; + for(int i = 0; i < rounds; i++){ + CNProcess<<>>(cnbuf_d, bnbuf_d, b2c_idx_d, cnproc_idx_d); + snprintf(str, 20, "%s%s_%d", debug, bn, i+1); + cudaDeviceSynchronize(); + print_arr(str, bnbuf_d, 33); + + BNProcess<<>>(const_llr_d, bnbuf_d, cnbuf_d, c2b_idx_d, bnproc_idx_d); + snprintf(str, 20, "%s%s_%d", debug, cn, i+1); + print_arr(str, cnbuf_d, 33); + + BN2llr<<<3,5>>>(bnbuf_d, llrbuf_d, llr_idx_d); + snprintf(str, 20, "%s%s_%d", debug, llrstr, i+1); + print_arr(str, llrbuf_d, 15); + } + +// BitDetermination<<<33, 256>>>(llrbuf_d, decode_output_d); + cudaDeviceSynchronize(); + + + cudaFree(llrbuf_d); + cudaFree(bnbuf_d); + cudaFree(cnbuf_d); + cudaFree(l2c_idx_d); + cudaFree(l2b_idx_d); + cudaFree(cnproc_idx_d); + cudaFree(c2b_idx_d); + cudaFree(bnproc_idx_d); + cudaFree(b2c_idx_d); + cudaFree(llr_d); + cudaFree(const_llr_d); + cudaFree(llr_idx_d); + + return 0; +} diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.h b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.h new file mode 100644 index 0000000000..803386643a --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.h @@ -0,0 +1,7 @@ +int l2c_idx[33] = { 1, 6, 10, 2, 7, 11, 0, 8, 9, 5, 10, 13, 3, 11, 14, 4, 9, 12, 0, 8, 11, 1, 6, 9, 2, 7, 10, 5, 12, 3, 13, 4, 14}; +int c2b_idx[33] = { 6, 18, 0, 21, 3, 24, 12, 29, 15, 31, 9, 27, 1, 22, 4, 25, 7, 19, 8, 16, 23, 2, 10, 26, 5, 13, 20, 17, 28, 11, 30, 14, 32}; +int b2c_idx[33] = { 2, 12, 21, 4, 14, 24, 0, 16, 18, 10, 22, 29, 6, 25, 31, 8, 19, 27, 1, 17, 26, 3, 13, 20, 5, 15, 23, 11, 28, 7, 30, 9, 32}; +int cnproc_idx[66] = { 0, 3, 0, 3, 0, 3, 3, 6, 3, 6, 3, 6, 6, 9, 6, 9, 6, 9, 9, 12, 9, 12, 9, 12, 12, 15, 12, 15, 12, 15, 15, 18, 15, 18, 15, 18, 18, 21, 18, 21, 18, 21, 21, 24, 21, 24, 21, 24, 24, 27, 24, 27, 24, 27, 27, 29, 27, 29, 29, 31, 29, 31, 31, 33, 31, 33}; +int bnproc_idx[66] = { 0, 2, 0, 2, 2, 4, 2, 4, 4, 6, 4, 6, 6, 8, 6, 8, 8, 10, 8, 10, 10, 12, 10, 12, 12, 14, 12, 14, 14, 16, 14, 16, 16, 18, 16, 18, 18, 21, 18, 21, 18, 21, 21, 24, 21, 24, 21, 24, 24, 27, 24, 27, 24, 27, 27, 29, 27, 29, 29, 31, 29, 31, 31, 33, 31, 33}; +int llr_idx[16] = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 21, 24, 27, 29, 31, 33}; +int l2b_idx[33] = { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14}; diff --git a/openair1/PHY/CODING/GPU_LDPC/test_input/8448/1.txt b/openair1/PHY/CODING/GPU_LDPC/test_input/8448/1.txt new file mode 100644 index 0000000000..6602abd079 --- /dev/null +++ b/openair1/PHY/CODING/GPU_LDPC/test_input/8448/1.txt @@ -0,0 +1,6 @@ +input +43 155 187 19 233 100 50 223 9 249 100 81 178 108 105 211 214 28 218 89 21 245 85 134 168 166 37 52 140 170 62 184 69 249 203 46 93 253 14 103 246 114 184 168 222 33 124 181 61 86 14 82 76 100 217 244 10 254 40 151 168 102 79 238 95 26 28 189 23 42 36 13 157 220 182 123 254 50 48 59 136 63 142 212 163 103 200 173 101 240 68 14 86 147 252 182 173 24 115 196 67 151 210 224 115 136 91 113 186 140 173 66 203 59 23 110 162 223 27 7 208 96 21 38 243 17 220 161 42 79 101 109 230 55 77 90 191 168 203 121 52 120 188 255 179 211 109 85 178 137 93 130 233 114 169 220 132 133 125 174 213 227 27 187 26 104 21 218 16 225 83 69 89 15 68 13 226 178 98 149 59 191 23 36 50 192 0 182 70 126 100 27 97 127 214 123 231 236 85 247 205 169 60 38 184 129 51 155 51 150 48 110 85 71 146 135 8 146 61 78 16 161 105 113 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3 -68 14 14 -33 6 32 15 16 23 6 43 20 -42 9 11 22 16 -36 31 37 -7 25 -28 -24 -54 -26 -26 34 -11 39 21 36 0 -5 33 37 -7 26 32 -7 8 -18 -36 19 5 -10 -3 -22 20 -39 7 5 26 17 2 -31 -29 55 -15 32 16 23 32 12 -36 -18 31 0 40 -37 -14 -5 29 10 -36 20 -28 1 -28 -7 22 9 35 -26 11 37 20 37 36 -25 -38 -46 6 36 29 31 2 22 -74 -35 8 7 -2 -4 -33 -12 -12 -24 -1 -33 -15 21 -20 25 37 11 28 -21 -33 24 15 24 -22 50 -25 -18 45 26 -36 -15 -49 13 -30 -39 -19 16 -32 14 11 25 -12 -11 39 -21 29 -35 -5 8 -48 26 8 -11 -33 40 16 25 -21 10 25 45 26 19 -5 -20 -22 8 -31 43 -39 -7 2 -11 -37 -26 -36 23 -43 30 -16 -33 -63 6 -31 49 +end From 689426e8c1500e00584efef5b699ab2730e63cdc Mon Sep 17 00:00:00 2001 From: NCTU CS ISIP Date: Wed, 11 Mar 2020 20:02:20 +0800 Subject: [PATCH 04/70] LDPC implement on Quadro p5000 --- cmake_targets/CMakeLists.txt | 47 ++- cmake_targets/build_oai | 3 +- .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h | 51 --- .../CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h | 51 --- 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+############################################## +# Base CUDA setting +############################################## +find_package(CUDA) +message ("cuda include ${CUDA_INCLUDE_DIRS}") +message ("cuda library ${CUDA_LIBRARY_DIRS}") + +add_definitions("-L/usr/local/cuda/lib64") + +SET(CUDA_NVCC_FLAGS + "${CUDA_NVCC_FLAGS};-arch=sm_60") + +# Disable warnings for CUDA +SET(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS};-lpthread;-w;-O3;--default-stream;per-thread;-I/usr/local/cuda/inc;-L/usr/local/cuda/lib -lcutil;-rdc=true;-lcudadevrt") +SET(CUDA_VERBOSE_BUILD ON) +SET(CUDA_HOST_COMPILER "/usr/bin/g++") + +SET(CUDA_SEPARABLE_COMPILATION ON) + ######################################################### # Base directories, compatible with legacy OAI building # ######################################################### @@ -174,7 +193,7 @@ set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER}" ) set(CMAKE_CXX_FLAGS - "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D${MKVER}" + "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11" #-D${MKVER} ) add_definitions("-DASN_DISABLE_OER_SUPPORT") @@ -1300,6 +1319,7 @@ set(PHY_TURBOIF ) set(PHY_LDPCSRC ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_generate_coefficient.c @@ -2695,15 +2715,34 @@ target_link_libraries(smallblocktest m pthread ${ATLAS_LIBRARIES} dl ) -add_executable(ldpctest +################################################### +# For CUDA library +################################################### +CUDA_ADD_LIBRARY(LDPC_CU + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu + ) + +cuda_add_executable(ldpctest ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) -target_link_libraries(ldpctest - -Wl,--start-group UTIL SIMU PHY_NR CONFIG_LIB -Wl,--end-group + +target_link_libraries(ldpctest -ldl + -Wl,--start-group + LDPC_CU UTIL SIMU PHY_NR CONFIG_LIB + -Wl,--end-group m pthread ${ATLAS_LIBRARIES} dl ) +#add_executable(ldpctest +# ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c +# ${T_SOURCE} +# ${SHLIB_LOADER_SOURCES} +# ) +#target_link_libraries(ldpctest +# -Wl,--start-group UTIL SIMU PHY_NR CONFIG_LIB -Wl,--end-group +# m pthread ${ATLAS_LIBRARIES} dl +# ) add_executable(nr_dlschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 6f4d5608f8..829c4a0f6b 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -697,7 +697,8 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim - simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim" +#simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim" +simlist="ldpctest" for f in $simlist ; do compilations \ phy_simulators $f \ diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h deleted file mode 100644 index 01731910b2..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i0.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I0_H_ -#define _ISIP_LDPC_BG1_I0_H_ -static int BG1_I0[46*68] = { - 251, 70, 227, 160, 0, 101, 11, 0, 0, 60, 230, 111, 192, 10, 0, 196, 24, 0, 191, 36, 240, 32, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 3, 0, 240, 118, 125, 72, 0, 223, 105, 174, 0, 221, 103, 0, 110, 133, 143, 156, 0, 256, 0, 29, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 107, 112, 186, 0, 64, 118, 94, 230, 178, 96, 40, 0, 0, 143, 226, 226, 0, 246, 206, 252, 118, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 122, 90, 0, 85, 21, 0, 151, 132, 244, 0, 137, 87, 247, 220, 212, 0, 241, 77, 245, 0, 145, 13, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 158, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 206, 237, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 232, 0, 0, 0, 29, 0, 0, 0, 0, 124, 116, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 184, 0, 0, 0, 0, 0, 23, 0, 0, 0, 29, 68, 0, 245, 0, 0, 0, 12, 158, 0, 212, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 221, 45, 0, 0, 160, 0, 0, 32, 168, 0, 0, 0, 0, 0, 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 113, 5, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 212, 0, 0, 0, 103, 0, 0, 165, 0, 110, 242, 0, 91, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 104, 183, 0, 0, 0, 0, 0, 0, 0, 0, 110, 22, 0, 143, 0, 0, 0, 15, 62, 0, 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 99, 150, 0, 168, 0, 0, 161, 50, 0, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 78, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84, 0, 0, 0, 183, 0, 0, 0, 0, 79, 253, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 161, 43, 0, 0, 0, 0, 0, 0, 0, 0, 22, 33, 0, 235, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 178, 0, 0, 249, 0, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 186, 0, 0, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 207, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 56, 0, 0, 207, 128, 17, 0, 0, 0, 230, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 41, 97, 0, 0, 0, 0, 0, 0, 0, 0, 66, 0, 0, 64, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 65, 0, 50, 0, 0, 0, 0, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 52, 0, 155, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 165, 0, 60, 2, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 234, 9, 0, 0, 0, 0, 156, 148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 61, 74, 0, 0, 0, 0, 0, 73, 128, 0, 225, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 152, 0, 0, 187, 0, 0, 0, 0, 0, 218, 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 161, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 250, 0, 0, 0, 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 110, 0, 0, 0, 132, 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 143, 189, 0, 0, 0, 159, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 157, 148, 0, 0, 0, 0, 0, 0, 0, 171, 0, 0, 0, 0, 0, 0, 0, 153, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 113, 0, 0, 87, 237, 0, 0, 0, 0, 0, 0, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 24, 0, 0, 0, 0, 137, 117, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 196, 0, 244, 0, 216, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 26, 0, 0, 0, 0, 105, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 129, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 237, 0, 0, 0, 85, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 74, 0, 0, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 96, 0, 0, 0, 0, 0, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 173, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 222, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 113, 0, 200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 3, 188, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 212, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 128, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 165, 0, 160, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 162, 0, 0, 0, 0, 198, 0, 0, 0, 0, 0, 208, 0, 0, 0, 0, 0, 0, 0, 0, 0, 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 52, 0, 0, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 199, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 221, 0, 0, 0, 0, 0, 0, 0, 0, 0, 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 168, 0, 0, 0, 0, 0, 0, 0, 0, 152, 158, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 174, 0, 140, 0, 0, 0, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 158, 0, 0, 0, 0, 0, 0, 0, 138, 0, 0, 0, 0, 0, 0, 0, 0, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 168, 0, 174, 0, 0, 0, 0, 0, 140, 0, 0, 0, 0, 0, 0, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 150, 0, 0, 0, 158, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 138, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 164, 0, 174, 0, 0, 0, 0, 0, 0, 140, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 140, 0, 0, 0, 0, 0, 0, 158, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 150, 0, 0, 0, 0, 152, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h deleted file mode 100644 index e7ff7f339b..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i1.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I1_H_ -#define _ISIP_LDPC_BG1_I1_H_ -static int BG1_I1[46*68] = { - 308, 20, 51, 370, 0, 182, 217, 0, 0, 318, 289, 110, 18, 358, 0, 216, 107, 0, 243, 181, 331, 347, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 77, 0, 77, 74, 289, 145, 0, 332, 332, 179, 0, 296, 343, 0, 218, 100, 355, 115, 0, 332, 0, 113, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 206, 251, 329, 0, 333, 257, 162, 268, 161, 64, 130, 0, 0, 201, 89, 54, 0, 132, 241, 206, 14, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 136, 0, 0, 0, 0, 150, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h deleted file mode 100644 index 9b2875f765..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i2.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I2_H_ -#define _ISIP_LDPC_BG1_I2_H_ -static int BG1_I2[46*68] = { - 74, 16, 104, 50, 0, 241, 40, 0, 0, 16, 163, 216, 165, 134, 0, 299, 111, 0, 114, 17, 190, 33, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 304, 0, 295, 28, 262, 162, 0, 134, 5, 81, 0, 130, 301, 0, 77, 267, 73, 84, 0, 261, 0, 302, 1, 1, 1, 0, 0, 0, 0, 0, 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a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i4.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I4_H_ -#define _ISIP_LDPC_BG1_I4_H_ -static int BG1_I4[46*68] = { - 212, 199, 189, 187, 0, 220, 5, 0, 0, 30, 145, 117, 217, 116, 0, 234, 145, 0, 96, 217, 74, 262, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 180, 0, 163, 224, 257, 161, 0, 77, 203, 118, 0, 110, 16, 0, 73, 153, 159, 148, 0, 157, 0, 120, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 259, 168, 221, 0, 134, 244, 203, 219, 64, 1, 4, 0, 0, 75, 230, 1, 0, 217, 270, 201, 235, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 188, 146, 0, 167, 109, 0, 83, 133, 198, 0, 42, 163, 58, 37, 116, 0, 243, 166, 1, 0, 114, 109, 2, 0, 0, 1, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 99, 0, 0, 47, 0, 16, 231, 0, 55, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 163, 160, 0, 0, 0, 0, 0, 0, 0, 0, 94, 135, 0, 46, 0, 0, 0, 133, 77, 0, 210, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 179, 2, 0, 29, 0, 0, 268, 235, 0, 0, 0, 0, 0, 202, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 56, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 275, 0, 0, 0, 182, 0, 0, 0, 0, 274, 40, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 226, 163, 0, 0, 0, 0, 0, 0, 0, 0, 245, 152, 0, 239, 0, 0, 0, 0, 244, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 162, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 152, 1, 0, 0, 0, 0, 242, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 0, 0, 0, 0, 0, 119, 145, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 266, 0, 0, 82, 0, 0, 0, 0, 0, 91, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 65, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 267, 0, 0, 0, 10, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 190, 73, 0, 0, 0, 258, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 181, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 237, 0, 0, 200, 1, 0, 0, 0, 0, 0, 0, 267, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 206, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 278, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 46, 0, 0, 0, 0, 37, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 276, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 156, 0, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 181, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 0, 0, 253, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 145, 0, 0, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 167, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 212, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 198, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 109, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 200, 0, 0, 0, 0, 279, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 206, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 217, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 191, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 154, 0, 1, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 217, 0, 0, 0, 0, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 28, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 244, 0, 1, 0, 0, 0, 0, 0, 0, 271, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 19, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 169, 0, 0, 0, 0, 1, 0, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h deleted file mode 100644 index 2abfb3a319..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i5.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I5_H_ -#define _ISIP_LDPC_BG1_I5_H_ -static int BG1_I5[46*68] = { - 295, 119, 168, 331, 0, 208, 166, 0, 0, 244, 251, 2, 340, 202, 0, 54, 348, 0, 305, 168, 48, 189, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 78, 0, 226, 97, 339, 269, 0, 113, 303, 51, 0, 168, 254, 0, 335, 243, 258, 134, 0, 10, 0, 303, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 227, 36, 214, 0, 303, 112, 266, 129, 238, 295, 128, 0, 0, 111, 287, 126, 0, 132, 164, 211, 8, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 98, 95, 0, 50, 280, 0, 140, 167, 92, 0, 107, 247, 346, 270, 186, 0, 250, 216, 144, 0, 122, 122, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 43, 257, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 220, 131, 0, 252, 0, 0, 0, 0, 0, 0, 0, 0, 323, 0, 0, 0, 296, 0, 0, 0, 0, 259, 284, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 295, 0, 0, 0, 0, 0, 74, 0, 0, 0, 331, 100, 0, 173, 0, 0, 0, 151, 285, 0, 306, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 4, 104, 0, 0, 225, 0, 0, 298, 216, 0, 0, 0, 0, 0, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 349, 76, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 313, 0, 0, 0, 225, 0, 0, 18, 0, 60, 315, 0, 245, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 157, 89, 0, 0, 0, 0, 0, 0, 0, 0, 294, 112, 0, 93, 0, 0, 0, 153, 24, 0, 338, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 176, 254, 0, 28, 0, 0, 232, 50, 0, 0, 0, 0, 0, 268, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 26, 323, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 201, 0, 0, 0, 352, 0, 0, 0, 0, 167, 339, 193, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 124, 218, 0, 0, 0, 0, 0, 0, 0, 0, 143, 111, 0, 177, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 312, 0, 0, 252, 0, 0, 0, 266, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 323, 0, 0, 278, 157, 67, 0, 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 177, 349, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 82, 0, 0, 0, 0, 177, 0, 0, 0, 0, 0, 0, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 191, 0, 294, 0, 0, 0, 0, 0, 0, 0, 333, 0, 0, 0, 0, 0, 0, 0, 0, 332, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 229, 0, 248, 117, 0, 0, 0, 191, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 287, 247, 0, 0, 0, 0, 182, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 88, 111, 0, 0, 0, 0, 0, 148, 259, 0, 205, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 90, 0, 0, 66, 0, 0, 0, 0, 0, 156, 0, 245, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 163, 0, 0, 0, 265, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 347, 0, 0, 0, 144, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 281, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 158, 237, 0, 0, 0, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 19, 7, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 305, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 39, 0, 0, 171, 250, 0, 0, 0, 0, 0, 0, 289, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 280, 0, 0, 0, 0, 256, 112, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 326, 0, 327, 0, 227, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 92, 0, 0, 0, 0, 327, 0, 269, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 103, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 274, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 105, 0, 0, 0, 244, 0, 0, 0, 0, 0, 0, 108, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 213, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 102, 0, 0, 0, 0, 0, 298, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 280, 0, 0, 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 352, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 266, 0, 339, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 57, 305, 0, 0, 0, 0, 0, 0, 0, 0, 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 61, 0, 0, 0, 0, 0, 0, 321, 0, 0, 0, 0, 0, 0, 0, 113, 0, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 101, 0, 0, 0, 0, 211, 0, 0, 0, 0, 0, 196, 0, 0, 0, 0, 0, 0, 0, 0, 0, 269, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 36, 0, 0, 189, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 237, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 165, 0, 0, 0, 0, 0, 0, 0, 0, 197, 210, 0, 247, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 237, 0, 265, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 305, 0, 0, 0, 0, 0, 0, 0, 238, 0, 0, 0, 0, 0, 0, 0, 0, 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 124, 0, 78, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 289, 0, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 0, 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 54, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 80, 0, 0, 0, 0, 0, 0, 245, 0, 294, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 83, 0, 0, 0, 0, 68, 0, 0, 0, 236, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h deleted file mode 100644 index 91812045b5..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i6.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I6_H_ -#define _ISIP_LDPC_BG1_I6_H_ -static int BG1_I6[46*68] = { - 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 23, 0, 12, 125, 1, 11, 0, 1, 1, 3, 0, 17, 61, 0, 1, 7, 31, 1, 0, 169, 0, 32, 106, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 5, 0, 0, 0, 0, 0, 0, 7, 0, 143, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 182, 0, 0, 0, 0, 46, 0, 0, 0, 154, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h deleted file mode 100644 index 90563ade57..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg1_i7.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ISIP_LDPC_BG1_I7_H_ -#define _ISIP_LDPC_BG1_I7_H_ -static int BG1_I7[46*68] = { - 136, 228, 127, 135, 0, 85, 84, 0, 0, 54, 226, 206, 129, 76, 0, 136, 218, 0, 221, 91, 106, 138, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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+0,0 @@ -#ifndef _ISIP_LDPC_BG2_I0_H_ -#define _ISIP_LDPC_BG2_I0_H_ -static int BG2_I0[42*52] = { - 10, 118, 205, 27, 0, 0, 190, 0, 0, 206, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 168, 0, 0, 167, 254, 126, 227, 157, 225, 253, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 82, 115, 0, 45, 53, 0, 0, 0, 241, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 9, 59, 0, 159, 105, 210, 55, 19, 129, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 180, 215, 0, 0, 0, 0, 0, 0, 0, 0, 0, 72, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 232, 42, 0, 0, 0, 195, 0, 160, 0, 0, 0, 104, 0, 0, 0, 1, 0, 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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 64, 0, 112, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 84, 3, 0, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 116, 0, 0, 0, 0, 146, 0, 0, 0, 0, 4, 0, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 52, 0, 0, 0, 0, 0, 0, 0, 0, 0, 176, 214, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 204, 0, 0, 0, 0, 0, 0, 0, 143, 0, 9, 243, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 255, 0, 0, 0, 125, 0, 0, 0, 0, 0, 115, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 221, 0, 0, 0, 0, 0, 195, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 88, 21, 0, 0, 0, 0, 0, 0, 0, 0, 186, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 27, 0, 0, 106, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 77, 0, 0, 0, 0, 0, 0, 0, 43, 0, 0, 0, 0, 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 223, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 24, 0, 0, 236, 0, 239, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 47, 140, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 229, 0, 0, 0, 0, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 30, 0, 0, 0, 0, 144, 0, 0, 0, 0, 161, 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 9, 0, 0, 0, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 99, 102, 0, 0, 136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 19, 0, 0, 0, 29, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 72, 0, 0, 241, 0, 10, 0, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 243, 0, 0, 0, 0, 45, 0, 0, 0, 0, 0, 0, 167, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 133, 0, 0, 0, 0, 165, 0, 0, 236, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 58, 0, 0, 0, 41, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 141, 0, 39, 0, 0, 0, 0, 155, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 220, 0, 0, 152, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 32, 0, 0, 0, 67, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 240, 0, 0, 0, 0, 0, 0, 173, 0, 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 130, 0, 0, 0, 230, 0, 0, 0, 0, 0, 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h deleted file mode 100644 index 0b07f65df2..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i1.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ISIP_LDPC_BG2_I1_H_ -#define _ISIP_LDPC_BG2_I1_H_ -static int BG2_I1[42*52] = { - 175, 98, 167, 67, 0, 0, 72, 0, 0, 173, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 28, 0, 0, 37, 49, 93, 32, 188, 186, 4, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 26, 115, 0, 118, 111, 0, 0, 0, 115, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 137, 176, 0, 114, 73, 124, 119, 29, 187, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 73, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 11, 45, 0, 0, 0, 122, 0, 81, 0, 0, 0, 49, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 130, 0, 0, 0, 0, 93, 0, 101, 0, 50, 0, 185, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 81, 0, 0, 0, 187, 0, 17, 0, 0, 0, 103, 0, 144, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 119, 71, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 153, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 29, 0, 0, 0, 0, 0, 0, 133, 0, 186, 179, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 60, 105, 0, 0, 0, 0, 23, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 33, 0, 0, 0, 0, 0, 0, 93, 0, 175, 0, 0, 0, 155, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 40, 0, 94, 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 50, 126, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 167, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 20, 0, 0, 0, 0, 119, 0, 0, 0, 0, 22, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 69, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 88, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 148, 0, 0, 0, 8, 0, 0, 0, 0, 0, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h deleted file mode 100644 index 95d00f47a7..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i2.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ISIP_LDPC_BG2_I2_H_ -#define _ISIP_LDPC_BG2_I2_H_ -static int BG2_I2[42*52] = { - 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 138, 0, 0, 125, 1, 1, 89, 1, 1, 56, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 21, 95, 0, 100, 10, 0, 0, 0, 109, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 39, 16, 0, 103, 147, 13, 58, 54, 47, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 137, 0, 0, 0, 0, 0, 0, 0, 0, 0, 158, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 132, 0, 0, 0, 143, 0, 142, 0, 0, 0, 65, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 0, 0, 0, 125, 0, 100, 0, 46, 0, 149, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 0, 0, 0, 46, 0, 149, 0, 0, 0, 97, 0, 79, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 88, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 0, 0, 0, 158, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 0, 64, 0, 0, 0, 0, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 1, 0, 0, 0, 94, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 139, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 37, 0, 0, 144, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h deleted file mode 100644 index 33675c80b0..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i3.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ISIP_LDPC_BG2_I3_H_ -#define _ISIP_LDPC_BG2_I3_H_ -static int BG2_I3[42*52] = { - 73, 111, 24, 182, 0, 0, 96, 0, 0, 9, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 54, 0, 0, 157, 116, 157, 116, 201, 30, 32, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 153, 132, 0, 47, 192, 0, 0, 0, 92, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 186, 7, 0, 37, 125, 125, 111, 157, 134, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 201, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 186, 139, 0, 0, 0, 171, 0, 220, 0, 0, 0, 194, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 124, 0, 0, 0, 0, 56, 0, 32, 0, 223, 0, 210, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 104, 0, 0, 0, 14, 0, 106, 0, 0, 0, 151, 0, 182, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 148, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 153, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 3, 0, 0, 0, 0, 0, 0, 31, 0, 185, 84, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 175, 151, 0, 0, 0, 0, 9, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 100, 0, 0, 0, 0, 0, 0, 139, 0, 111, 0, 0, 0, 100, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 47, 0, 218, 0, 0, 0, 0, 0, 0, 0, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 38, 114, 0, 0, 0, 0, 0, 0, 144, 0, 0, 0, 0, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 37, 0, 0, 0, 0, 96, 0, 0, 0, 0, 41, 0, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 201, 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 76, 0, 0, 0, 0, 0, 0, 0, 159, 0, 135, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 49, 0, 0, 0, 133, 0, 0, 0, 0, 0, 207, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 69, 0, 0, 0, 0, 0, 17, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 36, 139, 0, 0, 0, 0, 0, 0, 0, 0, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 7, 0, 0, 21, 0, 0, 0, 0, 0, 0, 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 81, 0, 0, 0, 0, 0, 0, 0, 44, 0, 0, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 50, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 157, 0, 0, 55, 0, 135, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 154, 89, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 212, 0, 0, 0, 0, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 91, 0, 0, 0, 0, 7, 0, 0, 0, 0, 222, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 28, 0, 0, 0, 0, 0, 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 217, 213, 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 109, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 107, 0, 0, 45, 0, 186, 0, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 109, 0, 0, 0, 0, 22, 0, 0, 0, 0, 0, 0, 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 72, 0, 0, 0, 0, 13, 0, 0, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 202, 70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 92, 0, 0, 0, 166, 0, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 2, 0, 176, 0, 0, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 38, 0, 0, 0, 98, 0, 0, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 107, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 155, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 99, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 121, 0, 0, 0, 102, 0, 0, 0, 0, 0, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h deleted file mode 100644 index 768869a5b8..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i4.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ISIP_LDPC_BG2_I4_H_ -#define _ISIP_LDPC_BG2_I4_H_ -static int BG2_I4[42*52] = { - 4, 27, 54, 36, 0, 0, 116, 0, 0, 128, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 20, 0, 0, 95, 105, 67, 85, 99, 70, 51, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 96, 107, 0, 93, 111, 0, 0, 0, 112, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 121, 122, 0, 23, 5, 74, 50, 129, 80, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 43, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 52, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 41, 141, 0, 0, 0, 85, 0, 138, 0, 0, 0, 72, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 110, 0, 0, 0, 0, 88, 0, 108, 0, 134, 0, 140, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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@@ -#ifndef _ISIP_LDPC_BG2_I5_H_ -#define _ISIP_LDPC_BG2_I5_H_ -static int BG2_I5[42*52] = { - 157, 144, 15, 4, 0, 0, 41, 0, 0, 124, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 18, 0, 0, 66, 64, 2, 56, 38, 172, 134, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 99, 169, 0, 108, 83, 0, 0, 0, 143, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 54, 175, 0, 175, 128, 18, 90, 18, 106, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 87, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 80, 85, 0, 0, 0, 36, 0, 104, 0, 0, 0, 61, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 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130, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 168, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 113, 0, 0, 0, 8, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 110, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 106, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 161, 0, 0, 0, 0, 0, 0, 0, 157, 0, 0, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 133, 0, 0, 0, 7, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h deleted file mode 100644 index a94ff36dab..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i6.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ISIP_LDPC_BG2_I6_H_ -#define _ISIP_LDPC_BG2_I6_H_ -static int BG2_I6[42*52] = { - 144, 20, 177, 166, 0, 0, 197, 0, 0, 14, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 19, 0, 0, 28, 4, 103, 186, 18, 15, 181, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 127, 164, 0, 48, 184, 0, 0, 0, 133, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 37, 49, 0, 19, 112, 204, 4, 192, 161, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 44, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 137, 50, 0, 0, 0, 37, 0, 133, 0, 0, 0, 63, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 8, 0, 0, 0, 0, 35, 0, 199, 0, 169, 0, 13, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 164, 0, 0, 0, 79, 0, 144, 0, 0, 0, 108, 0, 59, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 102, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 187, 0, 0, 0, 0, 0, 0, 28, 0, 206, 82, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 126, 61, 0, 0, 0, 0, 178, 52, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 40, 0, 0, 0, 0, 0, 0, 30, 0, 36, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 19, 0, 156, 0, 0, 0, 0, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 33, 54, 0, 0, 0, 0, 0, 0, 96, 0, 0, 0, 0, 187, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 92, 0, 0, 0, 0, 21, 0, 0, 0, 0, 53, 0, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 126, 0, 0, 0, 0, 0, 0, 0, 32, 0, 55, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 58, 0, 0, 0, 202, 0, 0, 0, 0, 0, 143, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 130, 0, 0, 0, 0, 0, 204, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 111, 125, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 197, 0, 0, 36, 0, 0, 0, 0, 0, 0, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 11, 0, 0, 0, 0, 0, 0, 0, 123, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 203, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 53, 0, 0, 171, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 114, 162, 0, 0, 0, 0, 0, 0, 89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 198, 0, 0, 0, 0, 195, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 165, 0, 0, 0, 0, 173, 0, 0, 0, 0, 50, 162, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 169, 0, 0, 0, 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 187, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 51, 0, 0, 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 71, 0, 0, 18, 0, 51, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 190, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 111, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 164, 0, 0, 0, 0, 174, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 198, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 192, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 158, 0, 0, 0, 168, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 198, 0, 168, 0, 0, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 158, 0, 0, 0, 174, 0, 0, 0, 0, 0, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 182, 0, 0, 0, 0, 0, 0, 158, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 194, 0, 0, 0, 0, 0, 0, 0, 164, 0, 0, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 192, 0, 0, 0, 198, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h b/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h deleted file mode 100644 index 21cbe57a3f..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/BGs/isip_ldpc_bg2_i7.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ISIP_LDPC_BG2_I7_H_ -#define _ISIP_LDPC_BG2_I7_H_ -static int BG2_I7[42*52] = { - 146, 132, 72, 22, 0, 0, 24, 0, 0, 113, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 143, 0, 0, 175, 184, 28, 97, 24, 10, 168, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 75, 32, 0, 4, 54, 0, 0, 0, 156, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 240, 172, 0, 96, 111, 160, 200, 44, 76, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 30, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 181, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 122, 42, 0, 0, 0, 170, 0, 89, 0, 0, 0, 208, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 138, 0, 0, 0, 0, 73, 0, 173, 0, 125, 0, 57, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 87, 0, 0, 0, 187, 0, 88, 0, 0, 0, 173, 0, 155, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 177, 170, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 226, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 168, 0, 0, 0, 0, 0, 0, 239, 0, 49, 69, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 39, 218, 0, 0, 0, 0, 209, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 179, 0, 0, 0, 0, 0, 0, 215, 0, 169, 0, 0, 0, 52, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 125, 0, 123, 0, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 49, 58, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 220, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 83, 0, 0, 0, 0, 233, 0, 0, 0, 0, 205, 0, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 218, 158, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 171, 0, 0, 0, 0, 0, 0, 0, 24, 0, 176, 203, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 197, 0, 0, 0, 174, 0, 0, 0, 0, 0, 196, 219, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 129, 0, 0, 0, 0, 0, 212, 211, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 40, 85, 0, 0, 0, 0, 0, 0, 0, 0, 89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 118, 0, 0, 228, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 239, 0, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 196, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 6, 0, 0, 95, 0, 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 82, 20, 0, 0, 0, 0, 0, 0, 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 67, 0, 0, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 147, 0, 0, 0, 0, 67, 0, 0, 0, 0, 191, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, 68, 0, 0, 181, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 0, 54, 0, 0, 0, 216, 0, 0, 0, 0, 0, 231, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 -}; -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/README.md b/openair1/PHY/CODING/GPU_LDPC/README.md deleted file mode 100644 index b460d5fa77..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/README.md +++ /dev/null @@ -1,17 +0,0 @@ -### LDPC DECODER -+ `intuitive_ldpc`: - Intuitive methods of LDPC decoder. This method stores the whole expanded Base Graph, CN, BN buffer as they are. Then, does the cn and bn process according to the equation in `nrLDPC.pdf`. - -+ `optimized_ldpc`: - This version inherits the idea of current oai ldpc_decoder. It stores lots of LUTs and shrinks the cn, bnbuffer size comparing to the former implementation. Right now, it only supports the longest code block 8448. - -### Usage -+ `make ldpc` will compile the program `ldpc`. -+ `make prof [num=<0~100>]` will show the detail of GPU activity. -+ `make test` will build ldpc executable and run `check.sh` to verify the correctness of the implementation. - -### Verification -+ The input (channel output) of the LDPC decoder is produced by the `ldpctest` program from OAI. -+ The verification is done by comparing the data decoded with the input data (channel output), and also the data output(`estimated_output`) produced by oai `ldpctest`. - - diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/Makefile b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/Makefile deleted file mode 100644 index b6af255a6e..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -NVCC = nvcc -CFLAGS = -PROF = nvprof -exec = ldpc -file = channel_output.txt -OBJS = util.o -code = 8448 -num = 1 -.PHONY: clean debug - - -## Target-specific Variable Values -debug: CFLAGS += -Ddebug -g -G -debug: clean $(exec) - cuda-gdb -q --args $(exec) -l $(code) -f $(file) - -$(exec): $(exec).cu $(OBJS) - $(NVCC) $(CFLAGS) -o $@ $^ - -%.o: %.cu - cp ../test_input/8448/$(num).txt $(file) - $(NVCC) $(CFLAGS) -o $@ -c $< - -run: clean $(exec) - ./$(exec) -l $(code) -f $(file) - -prof: clean $(exec) - cp ../test_input/8448/$(num).txt $(file) - $(PROF) ./$(exec) -l $(code) -f $(file) - -test: clean $(exec) - ./check.sh $(code) - rm $(OBJS) $(file) - -clean: - rm -rf *.o test.* $(exec) CN* BN* log.txt channel_output.txt diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/check.sh b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/check.sh deleted file mode 100644 index b24a22c97a..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/check.sh +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/bash - -exec=ldpc - -help() -{ - echo "Usage: $0 " -} - -main() -{ - if [ -z $@ ]; then - help - exit 1 - fi - - dir=$@ - files=`ls ../test_input/$dir | grep txt` -# files="1.txt 2.txt 3.txt" - - index=1 - for file in $files - do - cp ../test_input/$dir/$file channel_output.txt - echo "==== test $index ====" >> log.txt - ./$exec -l $dir -f channel_output.txt >> log.txt - echo ' ' >> log.txt - index=$((index+1)) - done -} - -main $@ diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu deleted file mode 100644 index faf0438d76..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/ldpc.cu +++ /dev/null @@ -1,323 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "../BGs/isip_ldpc_bg1_i0.h" -#include "../BGs/isip_ldpc_bg1_i1.h" -#include "../BGs/isip_ldpc_bg1_i2.h" -#include "../BGs/isip_ldpc_bg1_i3.h" -#include "../BGs/isip_ldpc_bg1_i4.h" -#include "../BGs/isip_ldpc_bg1_i5.h" -#include "../BGs/isip_ldpc_bg1_i6.h" -#include "../BGs/isip_ldpc_bg1_i7.h" -#include "../BGs/isip_ldpc_bg2_i0.h" -#include "../BGs/isip_ldpc_bg2_i1.h" -#include "../BGs/isip_ldpc_bg2_i2.h" -#include "../BGs/isip_ldpc_bg2_i3.h" -#include "../BGs/isip_ldpc_bg2_i4.h" -#include "../BGs/isip_ldpc_bg2_i5.h" -#include "../BGs/isip_ldpc_bg2_i6.h" -#include "../BGs/isip_ldpc_bg2_i7.h" -#include "util.h" - -#define TNPB 35 -#define BNPG 1024 -#define ITER 5 - -__constant__ int BG_GPU[46*68]; - - - -__global__ -void BNProcess(int flag, int *BN, int *CN, int *CNbuf, const int *const_llr, int BG_col, int BG_row, int Zc) -{ - int *CNG = (flag)? CN : CNbuf; - int id = blockIdx.x*blockDim.x + threadIdx.x; - - for(int col = id; col < BG_col*Zc; col += (TNPB*BNPG)) - { - int tmp = const_llr[col]; - for(int row = 0; row < BG_row; row++) - { - int up_shift = (BG_GPU[col/Zc + row*BG_col] - 1)%Zc; - if(up_shift != -1) - { - int row_idx = col%Zc; - row_idx = row_idx - up_shift; - if(row_idx < 0) row_idx = Zc + row_idx; - - row_idx = row*Zc + row_idx; - tmp = tmp + CNG[row_idx*BG_col*Zc + col]; - } - } - BN[col] = tmp; - } - __syncthreads(); -} - - - -__global__ void CNProcess(int flag, int *BN, int *CN, int *CNbuf, int BG_col, int BG_row, int Zc) -{ - int *CNG = (flag)? CN : CNbuf; - int *SCNG = (flag)? CNbuf : CN; - int id = blockIdx.x*blockDim.x + threadIdx.x; - - for(int row = id; row < BG_row*Zc; row += (TNPB*BNPG)) - { - for(int col = 0; col < BG_col; col++) - { - int right_shift = BG_GPU[(row/Zc)*BG_col + col] -1; - if(right_shift != -1) - { - int row_idx = row; -// int col_idx = ((row%384) + right_shift%384) %384 + col*384; - int col_idx = (row + right_shift) %Zc + col*Zc; - int sgn_cnt = 0, min = INT32_MAX; - for(int comp = 0; comp < BG_col; comp++) - { - if(comp == col) continue; - int comp_right_shift = BG_GPU[(row/Zc)*BG_col + comp] -1; - if(comp_right_shift != -1) - { - int comp_row_idx = row; -// int comp_col_idx = ((row%384) + (comp_right_shift%384)) %384 + comp*384; - int comp_col_idx = (row + comp_right_shift) %Zc + comp*Zc; - int tmp = BN[comp_col_idx] - CNG[comp_row_idx*BG_col*Zc + comp_col_idx]; - if(tmp < 0) - { - tmp = -tmp; - sgn_cnt++; - } - if(tmp < min) min = tmp; - } - } - SCNG[row_idx*BG_col*Zc + col_idx] = (sgn_cnt%2 == 0)? min: -min; - } - } - } - __syncthreads(); -} - -__global__ void BitDetermination(int *BN, unsigned int *decode_d) -{ - __shared__ int tmp[256]; - int tid = blockIdx.x*256 + threadIdx.x; - int bid = threadIdx.x; - tmp[bid] = 0; - - - if(BN[tid] < 0) - { - tmp[bid] = 1 << (bid&7); - } - - __syncthreads(); - - if(threadIdx.x < 32) - { - decode_d[blockIdx.x*32 + threadIdx.x] = 0; - for(int i = 0; i < 8; i++) - { - decode_d[blockIdx.x*32 + threadIdx.x] += tmp[threadIdx.x*8+i]; - } - } -} - - -// helper function -void printllr(const char *name, int *src, int *des, int count, int type_size) -{ - cudaCheck( cudaMemcpy((void *)des, (const void *)src, count*type_size, cudaMemcpyDeviceToHost) ); - - FILE *fp = fopen(name, "w"); - if(!fp) printf("[error]: open file %s failed\n", name); - - for(int i = 0; i < count; i++){ - fprintf(fp, "llr[%d]= %d\n", i, des[i]); - } -} - - -int main(int argc, char* argv[]) -{ - int opt = 0, block_length = 0, BG = 0, Kb = 0, Zc = 0, BG_row = 0, BG_col = 0, lift_index = 0; - char file[50] = {}; - short lift_size[51] = {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}; - short lift_set[][9] = { - {2,4,8,16,32,64,128,256}, - {3,6,12,24,48,96,192,384}, - {5,10,20,40,80,160,320}, - {7,14,28,56,112,224}, - {9,18,36,72,144,288}, - {11,22,44,88,176,352}, - {13,26,52,104,208}, - {15,30,60,120,240}, - {0}}; - - while( (opt = getopt(argc, argv, "l:f:")) != -1){ - switch(opt){ - case 'l': - block_length = atoi(optarg); - break; - case 'f': - strncpy(file, optarg, strlen(optarg)); - break; - default: - fprintf(stderr, "Usage: %s [-l code block length] <-f input file>\n", argv[0]); - exit(1); - } - } - - if(block_length == 0 || file[0] == ' '){ - fprintf(stderr, "no input file specified or code block length == 0"); - } - - if(block_length > 3840){ - BG = 1; - Kb = 22; - BG_row = 46; - BG_col = 68; - }else if(block_length <= 3840){ - BG = 2; - BG_row = 42; - BG_col = 52; - if(block_length > 640) - Kb = 10; - else if(block_length > 560) - Kb = 9; - else if(block_length > 192) - Kb = 8; - else - Kb = 6; - } - - for(int i = 0; i < 51; i++){ - if(lift_size[i] >= (double)block_length/Kb){ - Zc = lift_size[i]; - break; - } - } - - for(int i = 0; lift_set[i][0] != 0; i++){ - for(int j = 0; lift_set[i][j] != 0; j++){ - if(Zc == lift_set[i][j]){ - lift_index = i; - break; - } - } - } - - int *BG_CPU = NULL; - switch(lift_index){ - case 0: - BG_CPU = (BG == 1)? BG1_I0:BG2_I0; - break; - case 1: - BG_CPU = (BG == 1)? BG1_I1:BG2_I1; - break; - case 2: - BG_CPU = (BG == 1)? BG1_I2:BG2_I2; - break; - case 3: - BG_CPU = (BG == 1)? BG1_I3:BG2_I3; - break; - case 4: - BG_CPU = (BG == 1)? BG1_I4:BG2_I4; - break; - case 5: - BG_CPU = (BG == 1)? BG1_I5:BG2_I5; - break; - case 6: - BG_CPU = (BG == 1)? BG1_I6:BG2_I6; - break; - case 7: - BG_CPU = (BG == 1)? BG1_I7:BG2_I7; - break; - } - -// printf("BG %d lift_index %d Zc %d BG_row %d BG_col %d\n", BG, lift_index, Zc, BG_row, BG_col); - - // alloc cpu memory - unsigned int *input = (unsigned int*)malloc(sizeof(unsigned int)*8448/8), *decode_output_d, *decode_output_h; - int *BN, *CN, *CNbuf, *channel_output, *const_llr; -// debug -// int *p_BN = (int*)calloc(68*384, sizeof(int)); -// int *p_CN = (int*)calloc(68*384*46*384, sizeof(int)); - int *debug_llr = (int*)calloc(68*384, sizeof(int)); - cudaCheck( cudaHostAlloc((void**)&channel_output, 68*384*sizeof(int), cudaHostAllocDefault) ); - cudaCheck( cudaHostAlloc((void**)&decode_output_h, (8448/8)*sizeof(unsigned int), cudaHostAllocMapped) ); - // | cudaHostAllocPortable | cudaHostAllocMapped | cudaHostAllocWriteCombined); - - // read data from input file - ReadDataFromFile(file, input, channel_output, block_length, BG_col, Zc); - - // alloc gpu memory - // BG - cudaCheck( cudaMemcpyToSymbol(BG_GPU, BG_CPU, BG_col*BG_row*sizeof(int)) ); - // LLR CN BN BUF - size_t p_llr; - cudaCheck( cudaMallocPitch((void**)&const_llr, &p_llr, 68*384*sizeof(int), 1) ); - cudaCheck( cudaMallocPitch((void**)&BN, &p_llr, 68*384*sizeof(int), 1) ); - cudaCheck( cudaMallocPitch((void**)&CN, &p_llr, 68*384*sizeof(int), 46*384) ); - cudaCheck( cudaMallocPitch((void**)&CNbuf, &p_llr, 68*384*sizeof(int), 46*384) ); - - cudaCheck( cudaMemcpyAsync((void*)const_llr, (const void*)channel_output, 68*384*sizeof(int), cudaMemcpyHostToDevice) ); - cudaCheck( cudaMemcpyAsync((void*)BN, (const void*)channel_output, 68*384*sizeof(int), cudaMemcpyHostToDevice) ); - cudaCheck( cudaHostGetDevicePointer((void**)&decode_output_d, (void*)decode_output_h, 0) ); - cudaDeviceSynchronize(); - - cudaEvent_t start, end; - float time; - - cudaEventCreate(&start); - cudaEventCreate(&end); - - cudaEventRecord(start,0); - - dim3 grid(BNPG, 1, 1); - dim3 block(TNPB, 1, 1); - int flag = 0; - char str[20] = {}; - for(int it = 0; it < ITER; it++){ - CNProcess<<>>(flag, BN, CN, CNbuf, BG_col, BG_row, Zc); - flag = (flag+1)&1; - BNProcess<<>>(flag, BN, CN, CNbuf, const_llr, BG_col, BG_row, Zc); -#ifdef debug - snprintf(str, 20, "%s_%d", "llr", it); - printllr(str, BN, debug_llr, 68*384, sizeof(int)); -#endif - } - BitDetermination<<<33, 256>>>(BN, decode_output_d); - - cudaDeviceSynchronize(); - cudaEventRecord(end,0); - cudaEventSynchronize(end); - cudaEventElapsedTime(&time, start, end); - - - int err_num = 0; - for(int i = 0; i < block_length/8; i++){ - if(input[i] != decode_output_h[i]){ - printf("input[%d] = %d, decode_output[%d] = %d\n", i, input[i], i, decode_output_h[i]); - err_num++; - } - } - printf("err_num == %d\n", err_num); - printf("decode time:%f ms\n",time); - - // free resource - free(input); -// free(p_BN); -// free(p_CN); - cudaFreeHost(channel_output); - cudaFreeHost(decode_output_h); - cudaFree(const_llr); - cudaFree(BN); - cudaFree(CN); - cudaFree(CNbuf); - - return 0; -} diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.cu b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.cu deleted file mode 100644 index ff39c16938..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.cu +++ /dev/null @@ -1,37 +0,0 @@ -#include -#include -#include "util.h" - - -void ReadDataFromFile(const char *file, unsigned int *input_data_arr, int *channel_data_arr, int block_length, int BG_col, int Zc) -{ -// static const char testin[] = "../test_input/test_case_1.txt"; - file_t inputfile; - strcpy(inputfile.filename, file); - inputfile.fptr = fopen(inputfile.filename, "r"); - if(inputfile.fptr == NULL) - { - puts("cannot open file"); - } - - // data processing - fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of gen test - for(int i = 0; i < block_length/8; i++) - { - fscanf(inputfile.fptr, "%d", &input_data_arr[i]); - } - fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of '\n' - fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of test end - fgets(inputfile.tmp, 100, inputfile.fptr); // get rid of channel - /* - for(int i = 0; i < 2*384; i++) - { - channel_data_arr[i] = 0; - } - */ - for(int i = 0; i < BG_col*Zc; i++) - { - fscanf(inputfile.fptr, "%d", &channel_data_arr[i]); - } - fclose(inputfile.fptr); -} diff --git a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h b/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h deleted file mode 100644 index 51ce0e9604..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/intuitive_ldpc/util.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __UTIL_H__ -#define __UTIL_H__ - -// cuda check macro -#define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } -inline void cudaAssert(cudaError_t code, const char *file, int line) -{ - if (code != cudaSuccess){ - fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line); - exit(code); - } -} - -// struct -typedef struct -{ - FILE* fptr; - char filename[64]; - char tmp[64]; -}file_t; - -// utility -void ReadDataFromFile(const char*, unsigned int*, int*, int, int, int); -__global__ void BNProcess(int flag, int *BN, int *CN, int *CNbuf, const int *const_llr); -__global__ void CNProcess(int flag, int *BN, int *CN, int *CNbuf); -__global__ void BitDetermination(int *BN, unsigned int *decode_d); - -/* -int32_t nrLDPC_decoder(t_nrLDPC_dec_params* p_decParams, - int8_t* p_llr, int8_t* p_out, - t_nrLDPC_procBuf* p_procBuf, - t_nrLDPC_time_stats* p_profiler){ - - return iter; -} - -static inline uint32_t nrLDPC_decoder_core(int8_t* p_llr, int8_t* p_out, - t_nrLDPC_procBuf* p_procBuf, - uint32_t numLLR, t_nrLDPC_lut* p_lut, - t_nrLDPC_dec_params* p_decParams, - t_nrLDPC_time_stats* p_profiler){ - - return iter; -} - -*/ -#endif diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/Makefile b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/Makefile deleted file mode 100644 index bf4f3b82d1..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -EXEC = gen_idx -TXT = gen_matrix.txt -DEBUG = debug -FILE = channel_output.txt -num = 1 -CFLAGS= - -gen: clean gen_idx.c - $(CC) $(EXEC).c -o $(EXEC) -g - -ldpc: clean ldpc.cu - cp ../test_input/8448/$(num).txt $(FILE) - nvcc $(CFLAGS) ldpc.cu -o ldpc - mkdir debug - -test: ldpc - ./check.sh - -cgdb: CFLAGS += -g -G -cgdb: clean ldpc - cuda-gdb --silent --args ldpc $(FILE) - -prof: clean ldpc - cp ../test_input/8448/$(num).txt $(FILE) - nvprof ./ldpc $(FILE) - -.PHONY: clean -clean: - $(RM) -rf $(DEBUG) $(EXEC) $(TXT) ldpc log.txt $(FILE) diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/bg1_i1_index_array.h b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/bg1_i1_index_array.h deleted file mode 100644 index 74dd3d9536..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/bg1_i1_index_array.h +++ /dev/null @@ -1,9 +0,0 @@ -int l2c_idx[121344] = { 307, 403, 818, 1521, 2101, 2520, 3773, 4128, 4333, 4625, 5349, 5975, 6250, 7154, 7476, 8010, 8410, 8449, 8832, 308, 404, 819, 1522, 2102, 2521, 3774, 4129, 4334, 4626, 5350, 5976, 6251, 7155, 7477, 8011, 8411, 8450, 8833, 309, 405, 820, 1523, 2103, 2522, 3775, 4130, 4335, 4627, 5351, 5977, 6252, 7156, 7478, 8012, 8412, 8451, 8834, 310, 406, 821, 1524, 2104, 2523, 3776, 4131, 4336, 4628, 5352, 5978, 6253, 7157, 7479, 8013, 8413, 8452, 8835, 311, 407, 822, 1525, 2105, 2524, 3777, 4132, 4337, 4629, 5353, 5979, 6254, 7158, 7480, 8014, 8414, 8453, 8836, 312, 408, 823, 1526, 2106, 2525, 3778, 4133, 4338, 4630, 5354, 5980, 6255, 7159, 7481, 8015, 8415, 8454, 8837, 313, 409, 824, 1527, 2107, 2526, 3779, 4134, 4339, 4631, 5355, 5981, 6256, 7160, 7482, 8016, 8416, 8455, 8838, 314, 410, 825, 1528, 2108, 2527, 3780, 4135, 4340, 4632, 5356, 5982, 6257, 7161, 7483, 8017, 8417, 8456, 8839, 315, 411, 826, 1529, 2109, 2528, 3781, 4136, 4341, 4633, 5357, 5983, 6258, 7162, 7484, 8018, 8418, 8457, 8840, 316, 412, 827, 1530, 2110, 2529, 3782, 4137, 4342, 4634, 5358, 5984, 6259, 7163, 7485, 8019, 8419, 8458, 8841, 317, 413, 828, 1531, 2111, 2530, 3783, 4138, 4343, 4635, 5359, 5985, 6260, 7164, 7486, 8020, 8420, 8459, 8842, 318, 414, 829, 1532, 2112, 2531, 3784, 4139, 4344, 4636, 5360, 5986, 6261, 7165, 7487, 8021, 8421, 8460, 8843, 319, 415, 830, 1533, 2113, 2532, 3785, 4140, 4345, 4637, 5361, 5987, 6262, 7166, 7488, 8022, 8422, 8461, 8844, 320, 416, 831, 1534, 2114, 2533, 3786, 4141, 4346, 4638, 5362, 5988, 6263, 7167, 7489, 8023, 8423, 8462, 8845, 321, 417, 832, 1535, 2115, 2534, 3787, 4142, 4347, 4639, 5363, 5989, 6264, 7168, 7490, 8024, 8424, 8463, 8846, 322, 418, 833, 1152, 2116, 2535, 3788, 4143, 4348, 4640, 5364, 5990, 6265, 7169, 7491, 8025, 8425, 8464, 8847, 323, 419, 834, 1153, 2117, 2536, 3789, 4144, 4349, 4641, 5365, 5991, 6266, 7170, 7492, 8026, 8426, 8465, 8848, 324, 420, 835, 1154, 2118, 2537, 3790, 4145, 4350, 4642, 5366, 5992, 6267, 7171, 7493, 8027, 8427, 8466, 8849, 325, 421, 836, 1155, 2119, 2538, 3791, 4146, 4351, 4643, 5367, 5993, 6268, 7172, 7494, 8028, 8428, 8467, 8850, 326, 422, 837, 1156, 2120, 2539, 3792, 4147, 4352, 4644, 5368, 5994, 6269, 7173, 7495, 8029, 8429, 8468, 8851, 327, 423, 838, 1157, 2121, 2540, 3793, 4148, 4353, 4645, 5369, 5995, 6270, 7174, 7496, 8030, 8430, 8469, 8852, 328, 424, 839, 1158, 2122, 2541, 3794, 4149, 4354, 4646, 5370, 5996, 6271, 7175, 7497, 8031, 8431, 8470, 8853, 329, 425, 840, 1159, 2123, 2542, 3795, 4150, 4355, 4647, 5371, 5997, 6272, 7176, 7498, 8032, 8432, 8471, 8854, 330, 426, 841, 1160, 2124, 2543, 3796, 4151, 4356, 4648, 5372, 5998, 6273, 7177, 7499, 8033, 8433, 8472, 8855, 331, 427, 842, 1161, 2125, 2544, 3797, 4152, 4357, 4649, 5373, 5999, 6274, 7178, 7500, 8034, 8434, 8473, 8856, 332, 428, 843, 1162, 2126, 2545, 3798, 4153, 4358, 4650, 5374, 6000, 6275, 7179, 7501, 8035, 8435, 8474, 8857, 333, 429, 844, 1163, 2127, 2546, 3799, 4154, 4359, 4651, 5375, 6001, 6276, 7180, 7502, 8036, 8436, 8475, 8858, 334, 430, 845, 1164, 2128, 2547, 3800, 4155, 4360, 4652, 4992, 6002, 6277, 7181, 7503, 8037, 8437, 8476, 8859, 335, 431, 846, 1165, 2129, 2548, 3801, 4156, 4361, 4653, 4993, 6003, 6278, 7182, 7504, 8038, 8438, 8477, 8860, 336, 432, 847, 1166, 2130, 2549, 3802, 4157, 4362, 4654, 4994, 6004, 6279, 7183, 7505, 8039, 8439, 8478, 8861, 337, 433, 848, 1167, 2131, 2550, 3803, 4158, 4363, 4655, 4995, 6005, 6280, 7184, 7506, 8040, 8440, 8479, 8862, 338, 434, 849, 1168, 2132, 2551, 3804, 4159, 4364, 4656, 4996, 6006, 6281, 7185, 7507, 8041, 8441, 8480, 8863, 339, 435, 850, 1169, 2133, 2552, 3805, 4160, 4365, 4657, 4997, 6007, 6282, 7186, 7508, 8042, 8442, 8481, 8864, 340, 436, 851, 1170, 2134, 2553, 3806, 4161, 4366, 4658, 4998, 6008, 6283, 7187, 7509, 8043, 8443, 8482, 8865, 341, 437, 852, 1171, 2135, 2554, 3807, 4162, 4367, 4659, 4999, 6009, 6284, 7188, 7510, 8044, 8444, 8483, 8866, 342, 438, 853, 1172, 2136, 2555, 3808, 4163, 4368, 4660, 5000, 6010, 6285, 7189, 7511, 8045, 8445, 8484, 8867, 343, 439, 854, 1173, 2137, 2556, 3809, 4164, 4369, 4661, 5001, 6011, 6286, 7190, 7512, 8046, 8446, 8485, 8868, 344, 440, 855, 1174, 2138, 2557, 3810, 4165, 4370, 4662, 5002, 6012, 6287, 7191, 7513, 8047, 8447, 8486, 8869, 345, 441, 856, 1175, 2139, 2558, 3811, 4166, 4371, 4663, 5003, 6013, 6288, 7192, 7514, 8048, 8064, 8487, 8870, 346, 442, 857, 1176, 2140, 2559, 3812, 4167, 4372, 4664, 5004, 6014, 6289, 7193, 7515, 8049, 8065, 8488, 8871, 347, 443, 858, 1177, 2141, 2560, 3813, 4168, 4373, 4665, 5005, 6015, 6290, 7194, 7516, 8050, 8066, 8489, 8872, 348, 444, 859, 1178, 2142, 2561, 3814, 4169, 4374, 4666, 5006, 6016, 6291, 7195, 7517, 8051, 8067, 8490, 8873, 349, 445, 860, 1179, 2143, 2562, 3815, 4170, 4375, 4667, 5007, 6017, 6292, 7196, 7518, 8052, 8068, 8491, 8874, 350, 446, 861, 1180, 2144, 2563, 3816, 4171, 4376, 4668, 5008, 6018, 6293, 7197, 7519, 8053, 8069, 8492, 8875, 351, 447, 862, 1181, 2145, 2564, 3817, 4172, 4377, 4669, 5009, 6019, 6294, 7198, 7520, 8054, 8070, 8493, 8876, 352, 448, 863, 1182, 2146, 2565, 3818, 4173, 4378, 4670, 5010, 6020, 6295, 7199, 7521, 8055, 8071, 8494, 8877, 353, 449, 864, 1183, 2147, 2566, 3819, 4174, 4379, 4671, 5011, 6021, 6296, 7200, 7522, 8056, 8072, 8495, 8878, 354, 450, 865, 1184, 2148, 2567, 3820, 4175, 4380, 4672, 5012, 6022, 6297, 7201, 7523, 8057, 8073, 8496, 8879, 355, 451, 866, 1185, 2149, 2568, 3821, 4176, 4381, 4673, 5013, 6023, 6298, 7202, 7524, 8058, 8074, 8497, 8880, 356, 452, 867, 1186, 2150, 2569, 3822, 4177, 4382, 4674, 5014, 6024, 6299, 7203, 7525, 8059, 8075, 8498, 8881, 357, 453, 868, 1187, 2151, 2570, 3823, 4178, 4383, 4675, 5015, 6025, 6300, 7204, 7526, 8060, 8076, 8499, 8882, 358, 454, 869, 1188, 2152, 2571, 3824, 4179, 4384, 4676, 5016, 6026, 6301, 7205, 7527, 8061, 8077, 8500, 8883, 359, 455, 870, 1189, 2153, 2572, 3825, 4180, 4385, 4677, 5017, 6027, 6302, 7206, 7528, 8062, 8078, 8501, 8884, 360, 456, 871, 1190, 2154, 2573, 3826, 4181, 4386, 4678, 5018, 6028, 6303, 7207, 7529, 8063, 8079, 8502, 8885, 361, 457, 872, 1191, 2155, 2574, 3827, 4182, 4387, 4679, 5019, 6029, 6304, 7208, 7530, 7680, 8080, 8503, 8886, 362, 458, 873, 1192, 2156, 2575, 3828, 4183, 4388, 4680, 5020, 6030, 6305, 7209, 7531, 7681, 8081, 8504, 8887, 363, 459, 874, 1193, 2157, 2576, 3829, 4184, 4389, 4681, 5021, 6031, 6306, 7210, 7532, 7682, 8082, 8505, 8888, 364, 460, 875, 1194, 2158, 2577, 3830, 4185, 4390, 4682, 5022, 6032, 6307, 7211, 7533, 7683, 8083, 8506, 8889, 365, 461, 876, 1195, 2159, 2578, 3831, 4186, 4391, 4683, 5023, 6033, 6308, 7212, 7534, 7684, 8084, 8507, 8890, 366, 462, 877, 1196, 2160, 2579, 3832, 4187, 4392, 4684, 5024, 6034, 6309, 7213, 7535, 7685, 8085, 8508, 8891, 367, 463, 878, 1197, 2161, 2580, 3833, 4188, 4393, 4685, 5025, 6035, 6310, 7214, 7536, 7686, 8086, 8509, 8892, 368, 464, 879, 1198, 2162, 2581, 3834, 4189, 4394, 4686, 5026, 6036, 6311, 7215, 7537, 7687, 8087, 8510, 8893, 369, 465, 880, 1199, 2163, 2582, 3835, 4190, 4395, 4687, 5027, 6037, 6312, 7216, 7538, 7688, 8088, 8511, 8894, 370, 466, 881, 1200, 2164, 2583, 3836, 4191, 4396, 4688, 5028, 6038, 6313, 7217, 7539, 7689, 8089, 8512, 8895, 371, 467, 882, 1201, 2165, 2584, 3837, 4192, 4397, 4689, 5029, 6039, 6314, 7218, 7540, 7690, 8090, 8513, 8896, 372, 468, 883, 1202, 2166, 2585, 3838, 4193, 4398, 4690, 5030, 6040, 6315, 7219, 7541, 7691, 8091, 8514, 8897, 373, 469, 884, 1203, 2167, 2586, 3839, 4194, 4399, 4691, 5031, 6041, 6316, 7220, 7542, 7692, 8092, 8515, 8898, 374, 470, 885, 1204, 2168, 2587, 3456, 4195, 4400, 4692, 5032, 6042, 6317, 7221, 7543, 7693, 8093, 8516, 8899, 375, 471, 886, 1205, 2169, 2588, 3457, 4196, 4401, 4693, 5033, 6043, 6318, 7222, 7544, 7694, 8094, 8517, 8900, 376, 472, 887, 1206, 2170, 2589, 3458, 4197, 4402, 4694, 5034, 6044, 6319, 7223, 7545, 7695, 8095, 8518, 8901, 377, 473, 888, 1207, 2171, 2590, 3459, 4198, 4403, 4695, 5035, 6045, 6320, 7224, 7546, 7696, 8096, 8519, 8902, 378, 474, 889, 1208, 2172, 2591, 3460, 4199, 4404, 4696, 5036, 6046, 6321, 7225, 7547, 7697, 8097, 8520, 8903, 379, 475, 890, 1209, 2173, 2592, 3461, 4200, 4405, 4697, 5037, 6047, 6322, 7226, 7548, 7698, 8098, 8521, 8904, 380, 476, 891, 1210, 2174, 2593, 3462, 4201, 4406, 4698, 5038, 6048, 6323, 7227, 7549, 7699, 8099, 8522, 8905, 381, 477, 892, 1211, 2175, 2594, 3463, 4202, 4407, 4699, 5039, 6049, 6324, 7228, 7550, 7700, 8100, 8523, 8906, 382, 478, 893, 1212, 2176, 2595, 3464, 4203, 4408, 4700, 5040, 6050, 6325, 7229, 7551, 7701, 8101, 8524, 8907, 383, 479, 894, 1213, 2177, 2596, 3465, 4204, 4409, 4701, 5041, 6051, 6326, 7230, 7552, 7702, 8102, 8525, 8908, 0, 480, 895, 1214, 2178, 2597, 3466, 4205, 4410, 4702, 5042, 6052, 6327, 7231, 7553, 7703, 8103, 8526, 8909, 1, 481, 896, 1215, 2179, 2598, 3467, 4206, 4411, 4703, 5043, 6053, 6328, 7232, 7554, 7704, 8104, 8527, 8910, 2, 482, 897, 1216, 2180, 2599, 3468, 4207, 4412, 4704, 5044, 6054, 6329, 7233, 7555, 7705, 8105, 8528, 8911, 3, 483, 898, 1217, 2181, 2600, 3469, 4208, 4413, 4705, 5045, 6055, 6330, 7234, 7556, 7706, 8106, 8529, 8912, 4, 484, 899, 1218, 2182, 2601, 3470, 4209, 4414, 4706, 5046, 6056, 6331, 7235, 7557, 7707, 8107, 8530, 8913, 5, 485, 900, 1219, 2183, 2602, 3471, 4210, 4415, 4707, 5047, 6057, 6332, 7236, 7558, 7708, 8108, 8531, 8914, 6, 486, 901, 1220, 2184, 2603, 3472, 4211, 4416, 4708, 5048, 6058, 6333, 7237, 7559, 7709, 8109, 8532, 8915, 7, 487, 902, 1221, 2185, 2604, 3473, 4212, 4417, 4709, 5049, 6059, 6334, 7238, 7560, 7710, 8110, 8533, 8916, 8, 488, 903, 1222, 2186, 2605, 3474, 4213, 4418, 4710, 5050, 6060, 6335, 7239, 7561, 7711, 8111, 8534, 8917, 9, 489, 904, 1223, 2187, 2606, 3475, 4214, 4419, 4711, 5051, 6061, 6336, 7240, 7562, 7712, 8112, 8535, 8918, 10, 490, 905, 1224, 2188, 2607, 3476, 4215, 4420, 4712, 5052, 6062, 6337, 7241, 7563, 7713, 8113, 8536, 8919, 11, 491, 906, 1225, 2189, 2608, 3477, 4216, 4421, 4713, 5053, 6063, 6338, 7242, 7564, 7714, 8114, 8537, 8920, 12, 492, 907, 1226, 2190, 2609, 3478, 4217, 4422, 4714, 5054, 6064, 6339, 7243, 7565, 7715, 8115, 8538, 8921, 13, 493, 908, 1227, 2191, 2610, 3479, 4218, 4423, 4715, 5055, 6065, 6340, 7244, 7566, 7716, 8116, 8539, 8922, 14, 494, 909, 1228, 2192, 2611, 3480, 4219, 4424, 4716, 5056, 6066, 6341, 7245, 7567, 7717, 8117, 8540, 8923, 15, 495, 910, 1229, 2193, 2612, 3481, 4220, 4425, 4717, 5057, 6067, 6342, 7246, 7568, 7718, 8118, 8541, 8924, 16, 496, 911, 1230, 2194, 2613, 3482, 4221, 4426, 4718, 5058, 6068, 6343, 7247, 7569, 7719, 8119, 8542, 8925, 17, 497, 912, 1231, 2195, 2614, 3483, 4222, 4427, 4719, 5059, 6069, 6344, 7248, 7570, 7720, 8120, 8543, 8926, 18, 498, 913, 1232, 2196, 2615, 3484, 4223, 4428, 4720, 5060, 6070, 6345, 7249, 7571, 7721, 8121, 8544, 8927, 19, 499, 914, 1233, 2197, 2616, 3485, 3840, 4429, 4721, 5061, 6071, 6346, 7250, 7572, 7722, 8122, 8545, 8928, 20, 500, 915, 1234, 2198, 2617, 3486, 3841, 4430, 4722, 5062, 6072, 6347, 7251, 7573, 7723, 8123, 8546, 8929, 21, 501, 916, 1235, 2199, 2618, 3487, 3842, 4431, 4723, 5063, 6073, 6348, 7252, 7574, 7724, 8124, 8547, 8930, 22, 502, 917, 1236, 2200, 2619, 3488, 3843, 4432, 4724, 5064, 6074, 6349, 7253, 7575, 7725, 8125, 8548, 8931, 23, 503, 918, 1237, 2201, 2620, 3489, 3844, 4433, 4725, 5065, 6075, 6350, 7254, 7576, 7726, 8126, 8549, 8932, 24, 504, 919, 1238, 2202, 2621, 3490, 3845, 4434, 4726, 5066, 6076, 6351, 7255, 7577, 7727, 8127, 8550, 8933, 25, 505, 920, 1239, 2203, 2622, 3491, 3846, 4435, 4727, 5067, 6077, 6352, 7256, 7578, 7728, 8128, 8551, 8934, 26, 506, 921, 1240, 2204, 2623, 3492, 3847, 4436, 4728, 5068, 6078, 6353, 7257, 7579, 7729, 8129, 8552, 8935, 27, 507, 922, 1241, 2205, 2624, 3493, 3848, 4437, 4729, 5069, 6079, 6354, 7258, 7580, 7730, 8130, 8553, 8936, 28, 508, 923, 1242, 2206, 2625, 3494, 3849, 4438, 4730, 5070, 6080, 6355, 7259, 7581, 7731, 8131, 8554, 8937, 29, 509, 924, 1243, 2207, 2626, 3495, 3850, 4439, 4731, 5071, 6081, 6356, 7260, 7582, 7732, 8132, 8555, 8938, 30, 510, 925, 1244, 2208, 2627, 3496, 3851, 4440, 4732, 5072, 6082, 6357, 7261, 7583, 7733, 8133, 8556, 8939, 31, 511, 926, 1245, 2209, 2628, 3497, 3852, 4441, 4733, 5073, 6083, 6358, 7262, 7584, 7734, 8134, 8557, 8940, 32, 512, 927, 1246, 2210, 2629, 3498, 3853, 4442, 4734, 5074, 6084, 6359, 7263, 7585, 7735, 8135, 8558, 8941, 33, 513, 928, 1247, 2211, 2630, 3499, 3854, 4443, 4735, 5075, 6085, 6360, 7264, 7586, 7736, 8136, 8559, 8942, 34, 514, 929, 1248, 2212, 2631, 3500, 3855, 4444, 4736, 5076, 6086, 6361, 7265, 7587, 7737, 8137, 8560, 8943, 35, 515, 930, 1249, 2213, 2632, 3501, 3856, 4445, 4737, 5077, 6087, 6362, 7266, 7588, 7738, 8138, 8561, 8944, 36, 516, 931, 1250, 2214, 2633, 3502, 3857, 4446, 4738, 5078, 6088, 6363, 7267, 7589, 7739, 8139, 8562, 8945, 37, 517, 932, 1251, 2215, 2634, 3503, 3858, 4447, 4739, 5079, 6089, 6364, 7268, 7590, 7740, 8140, 8563, 8946, 38, 518, 933, 1252, 2216, 2635, 3504, 3859, 4448, 4740, 5080, 6090, 6365, 7269, 7591, 7741, 8141, 8564, 8947, 39, 519, 934, 1253, 2217, 2636, 3505, 3860, 4449, 4741, 5081, 6091, 6366, 7270, 7592, 7742, 8142, 8565, 8948, 40, 520, 935, 1254, 2218, 2637, 3506, 3861, 4450, 4742, 5082, 6092, 6367, 7271, 7593, 7743, 8143, 8566, 8949, 41, 521, 936, 1255, 2219, 2638, 3507, 3862, 4451, 4743, 5083, 6093, 6368, 7272, 7594, 7744, 8144, 8567, 8950, 42, 522, 937, 1256, 2220, 2639, 3508, 3863, 4452, 4744, 5084, 6094, 6369, 7273, 7595, 7745, 8145, 8568, 8951, 43, 523, 938, 1257, 2221, 2640, 3509, 3864, 4453, 4745, 5085, 6095, 6370, 7274, 7596, 7746, 8146, 8569, 8952, 44, 524, 939, 1258, 2222, 2641, 3510, 3865, 4454, 4746, 5086, 6096, 6371, 7275, 7597, 7747, 8147, 8570, 8953, 45, 525, 940, 1259, 2223, 2642, 3511, 3866, 4455, 4747, 5087, 6097, 6372, 7276, 7598, 7748, 8148, 8571, 8954, 46, 526, 941, 1260, 2224, 2643, 3512, 3867, 4456, 4748, 5088, 6098, 6373, 7277, 7599, 7749, 8149, 8572, 8955, 47, 527, 942, 1261, 2225, 2644, 3513, 3868, 4457, 4749, 5089, 6099, 6374, 7278, 7600, 7750, 8150, 8573, 8956, 48, 528, 943, 1262, 2226, 2645, 3514, 3869, 4458, 4750, 5090, 6100, 6375, 7279, 7601, 7751, 8151, 8574, 8957, 49, 529, 944, 1263, 2227, 2646, 3515, 3870, 4459, 4751, 5091, 6101, 6376, 7280, 7602, 7752, 8152, 8575, 8958, 50, 530, 945, 1264, 2228, 2647, 3516, 3871, 4460, 4752, 5092, 6102, 6377, 7281, 7603, 7753, 8153, 8576, 8959, 51, 531, 946, 1265, 2229, 2648, 3517, 3872, 4461, 4753, 5093, 6103, 6378, 7282, 7604, 7754, 8154, 8577, 8960, 52, 532, 947, 1266, 2230, 2649, 3518, 3873, 4462, 4754, 5094, 6104, 6379, 7283, 7605, 7755, 8155, 8578, 8961, 53, 533, 948, 1267, 2231, 2650, 3519, 3874, 4463, 4755, 5095, 6105, 6380, 7284, 7606, 7756, 8156, 8579, 8962, 54, 534, 949, 1268, 2232, 2651, 3520, 3875, 4464, 4756, 5096, 6106, 6381, 7285, 7607, 7757, 8157, 8580, 8963, 55, 535, 950, 1269, 2233, 2652, 3521, 3876, 4465, 4757, 5097, 6107, 6382, 7286, 7608, 7758, 8158, 8581, 8964, 56, 536, 951, 1270, 2234, 2653, 3522, 3877, 4466, 4758, 5098, 6108, 6383, 7287, 7609, 7759, 8159, 8582, 8965, 57, 537, 952, 1271, 2235, 2654, 3523, 3878, 4467, 4759, 5099, 6109, 6384, 7288, 7610, 7760, 8160, 8583, 8966, 58, 538, 953, 1272, 2236, 2655, 3524, 3879, 4468, 4760, 5100, 6110, 6385, 7289, 7611, 7761, 8161, 8584, 8967, 59, 539, 954, 1273, 2237, 2656, 3525, 3880, 4469, 4761, 5101, 6111, 6386, 7290, 7612, 7762, 8162, 8585, 8968, 60, 540, 955, 1274, 2238, 2657, 3526, 3881, 4470, 4762, 5102, 6112, 6387, 7291, 7613, 7763, 8163, 8586, 8969, 61, 541, 956, 1275, 2239, 2658, 3527, 3882, 4471, 4763, 5103, 6113, 6388, 7292, 7614, 7764, 8164, 8587, 8970, 62, 542, 957, 1276, 2240, 2659, 3528, 3883, 4472, 4764, 5104, 6114, 6389, 7293, 7615, 7765, 8165, 8588, 8971, 63, 543, 958, 1277, 2241, 2660, 3529, 3884, 4473, 4765, 5105, 6115, 6390, 7294, 7616, 7766, 8166, 8589, 8972, 64, 544, 959, 1278, 2242, 2661, 3530, 3885, 4474, 4766, 5106, 6116, 6391, 7295, 7617, 7767, 8167, 8590, 8973, 65, 545, 960, 1279, 2243, 2662, 3531, 3886, 4475, 4767, 5107, 6117, 6392, 6912, 7618, 7768, 8168, 8591, 8974, 66, 546, 961, 1280, 2244, 2663, 3532, 3887, 4476, 4768, 5108, 6118, 6393, 6913, 7619, 7769, 8169, 8592, 8975, 67, 547, 962, 1281, 2245, 2664, 3533, 3888, 4477, 4769, 5109, 6119, 6394, 6914, 7620, 7770, 8170, 8593, 8976, 68, 548, 963, 1282, 2246, 2665, 3534, 3889, 4478, 4770, 5110, 6120, 6395, 6915, 7621, 7771, 8171, 8594, 8977, 69, 549, 964, 1283, 2247, 2666, 3535, 3890, 4479, 4771, 5111, 6121, 6396, 6916, 7622, 7772, 8172, 8595, 8978, 70, 550, 965, 1284, 2248, 2667, 3536, 3891, 4480, 4772, 5112, 6122, 6397, 6917, 7623, 7773, 8173, 8596, 8979, 71, 551, 966, 1285, 2249, 2668, 3537, 3892, 4481, 4773, 5113, 6123, 6398, 6918, 7624, 7774, 8174, 8597, 8980, 72, 552, 967, 1286, 2250, 2669, 3538, 3893, 4482, 4774, 5114, 6124, 6399, 6919, 7625, 7775, 8175, 8598, 8981, 73, 553, 968, 1287, 2251, 2670, 3539, 3894, 4483, 4775, 5115, 6125, 6400, 6920, 7626, 7776, 8176, 8599, 8982, 74, 554, 969, 1288, 2252, 2671, 3540, 3895, 4484, 4776, 5116, 6126, 6401, 6921, 7627, 7777, 8177, 8600, 8983, 75, 555, 970, 1289, 2253, 2672, 3541, 3896, 4485, 4777, 5117, 6127, 6402, 6922, 7628, 7778, 8178, 8601, 8984, 76, 556, 971, 1290, 2254, 2673, 3542, 3897, 4486, 4778, 5118, 6128, 6403, 6923, 7629, 7779, 8179, 8602, 8985, 77, 557, 972, 1291, 2255, 2674, 3543, 3898, 4487, 4779, 5119, 6129, 6404, 6924, 7630, 7780, 8180, 8603, 8986, 78, 558, 973, 1292, 2256, 2675, 3544, 3899, 4488, 4780, 5120, 6130, 6405, 6925, 7631, 7781, 8181, 8604, 8987, 79, 559, 974, 1293, 2257, 2676, 3545, 3900, 4489, 4781, 5121, 6131, 6406, 6926, 7632, 7782, 8182, 8605, 8988, 80, 560, 975, 1294, 2258, 2677, 3546, 3901, 4490, 4782, 5122, 6132, 6407, 6927, 7633, 7783, 8183, 8606, 8989, 81, 561, 976, 1295, 2259, 2678, 3547, 3902, 4491, 4783, 5123, 6133, 6408, 6928, 7634, 7784, 8184, 8607, 8990, 82, 562, 977, 1296, 2260, 2679, 3548, 3903, 4492, 4784, 5124, 6134, 6409, 6929, 7635, 7785, 8185, 8608, 8991, 83, 563, 978, 1297, 2261, 2680, 3549, 3904, 4493, 4785, 5125, 6135, 6410, 6930, 7636, 7786, 8186, 8609, 8992, 84, 564, 979, 1298, 2262, 2681, 3550, 3905, 4494, 4786, 5126, 6136, 6411, 6931, 7637, 7787, 8187, 8610, 8993, 85, 565, 980, 1299, 2263, 2682, 3551, 3906, 4495, 4787, 5127, 6137, 6412, 6932, 7638, 7788, 8188, 8611, 8994, 86, 566, 981, 1300, 2264, 2683, 3552, 3907, 4496, 4788, 5128, 6138, 6413, 6933, 7639, 7789, 8189, 8612, 8995, 87, 567, 982, 1301, 2265, 2684, 3553, 3908, 4497, 4789, 5129, 6139, 6414, 6934, 7640, 7790, 8190, 8613, 8996, 88, 568, 983, 1302, 2266, 2685, 3554, 3909, 4498, 4790, 5130, 6140, 6415, 6935, 7641, 7791, 8191, 8614, 8997, 89, 569, 984, 1303, 2267, 2686, 3555, 3910, 4499, 4791, 5131, 6141, 6416, 6936, 7642, 7792, 8192, 8615, 8998, 90, 570, 985, 1304, 2268, 2687, 3556, 3911, 4500, 4792, 5132, 6142, 6417, 6937, 7643, 7793, 8193, 8616, 8999, 91, 571, 986, 1305, 2269, 2304, 3557, 3912, 4501, 4793, 5133, 6143, 6418, 6938, 7644, 7794, 8194, 8617, 9000, 92, 572, 987, 1306, 2270, 2305, 3558, 3913, 4502, 4794, 5134, 5760, 6419, 6939, 7645, 7795, 8195, 8618, 9001, 93, 573, 988, 1307, 2271, 2306, 3559, 3914, 4503, 4795, 5135, 5761, 6420, 6940, 7646, 7796, 8196, 8619, 9002, 94, 574, 989, 1308, 2272, 2307, 3560, 3915, 4504, 4796, 5136, 5762, 6421, 6941, 7647, 7797, 8197, 8620, 9003, 95, 575, 990, 1309, 2273, 2308, 3561, 3916, 4505, 4797, 5137, 5763, 6422, 6942, 7648, 7798, 8198, 8621, 9004, 96, 576, 991, 1310, 2274, 2309, 3562, 3917, 4506, 4798, 5138, 5764, 6423, 6943, 7649, 7799, 8199, 8622, 9005, 97, 577, 992, 1311, 2275, 2310, 3563, 3918, 4507, 4799, 5139, 5765, 6424, 6944, 7650, 7800, 8200, 8623, 9006, 98, 578, 993, 1312, 2276, 2311, 3564, 3919, 4508, 4800, 5140, 5766, 6425, 6945, 7651, 7801, 8201, 8624, 9007, 99, 579, 994, 1313, 2277, 2312, 3565, 3920, 4509, 4801, 5141, 5767, 6426, 6946, 7652, 7802, 8202, 8625, 9008, 100, 580, 995, 1314, 2278, 2313, 3566, 3921, 4510, 4802, 5142, 5768, 6427, 6947, 7653, 7803, 8203, 8626, 9009, 101, 581, 996, 1315, 2279, 2314, 3567, 3922, 4511, 4803, 5143, 5769, 6428, 6948, 7654, 7804, 8204, 8627, 9010, 102, 582, 997, 1316, 2280, 2315, 3568, 3923, 4512, 4804, 5144, 5770, 6429, 6949, 7655, 7805, 8205, 8628, 9011, 103, 583, 998, 1317, 2281, 2316, 3569, 3924, 4513, 4805, 5145, 5771, 6430, 6950, 7656, 7806, 8206, 8629, 9012, 104, 584, 999, 1318, 2282, 2317, 3570, 3925, 4514, 4806, 5146, 5772, 6431, 6951, 7657, 7807, 8207, 8630, 9013, 105, 585, 1000, 1319, 2283, 2318, 3571, 3926, 4515, 4807, 5147, 5773, 6432, 6952, 7658, 7808, 8208, 8631, 9014, 106, 586, 1001, 1320, 2284, 2319, 3572, 3927, 4516, 4808, 5148, 5774, 6433, 6953, 7659, 7809, 8209, 8632, 9015, 107, 587, 1002, 1321, 2285, 2320, 3573, 3928, 4517, 4809, 5149, 5775, 6434, 6954, 7660, 7810, 8210, 8633, 9016, 108, 588, 1003, 1322, 2286, 2321, 3574, 3929, 4518, 4810, 5150, 5776, 6435, 6955, 7661, 7811, 8211, 8634, 9017, 109, 589, 1004, 1323, 2287, 2322, 3575, 3930, 4519, 4811, 5151, 5777, 6436, 6956, 7662, 7812, 8212, 8635, 9018, 110, 590, 1005, 1324, 2288, 2323, 3576, 3931, 4520, 4812, 5152, 5778, 6437, 6957, 7663, 7813, 8213, 8636, 9019, 111, 591, 1006, 1325, 2289, 2324, 3577, 3932, 4521, 4813, 5153, 5779, 6438, 6958, 7664, 7814, 8214, 8637, 9020, 112, 592, 1007, 1326, 2290, 2325, 3578, 3933, 4522, 4814, 5154, 5780, 6439, 6959, 7665, 7815, 8215, 8638, 9021, 113, 593, 1008, 1327, 2291, 2326, 3579, 3934, 4523, 4815, 5155, 5781, 6440, 6960, 7666, 7816, 8216, 8639, 9022, 114, 594, 1009, 1328, 2292, 2327, 3580, 3935, 4524, 4816, 5156, 5782, 6441, 6961, 7667, 7817, 8217, 8640, 9023, 115, 595, 1010, 1329, 2293, 2328, 3581, 3936, 4525, 4817, 5157, 5783, 6442, 6962, 7668, 7818, 8218, 8641, 9024, 116, 596, 1011, 1330, 2294, 2329, 3582, 3937, 4526, 4818, 5158, 5784, 6443, 6963, 7669, 7819, 8219, 8642, 9025, 117, 597, 1012, 1331, 2295, 2330, 3583, 3938, 4527, 4819, 5159, 5785, 6444, 6964, 7670, 7820, 8220, 8643, 9026, 118, 598, 1013, 1332, 2296, 2331, 3584, 3939, 4528, 4820, 5160, 5786, 6445, 6965, 7671, 7821, 8221, 8644, 9027, 119, 599, 1014, 1333, 2297, 2332, 3585, 3940, 4529, 4821, 5161, 5787, 6446, 6966, 7672, 7822, 8222, 8645, 9028, 120, 600, 1015, 1334, 2298, 2333, 3586, 3941, 4530, 4822, 5162, 5788, 6447, 6967, 7673, 7823, 8223, 8646, 9029, 121, 601, 1016, 1335, 2299, 2334, 3587, 3942, 4531, 4823, 5163, 5789, 6448, 6968, 7674, 7824, 8224, 8647, 9030, 122, 602, 1017, 1336, 2300, 2335, 3588, 3943, 4532, 4824, 5164, 5790, 6449, 6969, 7675, 7825, 8225, 8648, 9031, 123, 603, 1018, 1337, 2301, 2336, 3589, 3944, 4533, 4825, 5165, 5791, 6450, 6970, 7676, 7826, 8226, 8649, 9032, 124, 604, 1019, 1338, 2302, 2337, 3590, 3945, 4534, 4826, 5166, 5792, 6451, 6971, 7677, 7827, 8227, 8650, 9033, 125, 605, 1020, 1339, 2303, 2338, 3591, 3946, 4535, 4827, 5167, 5793, 6452, 6972, 7678, 7828, 8228, 8651, 9034, 126, 606, 1021, 1340, 1920, 2339, 3592, 3947, 4536, 4828, 5168, 5794, 6453, 6973, 7679, 7829, 8229, 8652, 9035, 127, 607, 1022, 1341, 1921, 2340, 3593, 3948, 4537, 4829, 5169, 5795, 6454, 6974, 7296, 7830, 8230, 8653, 9036, 128, 608, 1023, 1342, 1922, 2341, 3594, 3949, 4538, 4830, 5170, 5796, 6455, 6975, 7297, 7831, 8231, 8654, 9037, 129, 609, 1024, 1343, 1923, 2342, 3595, 3950, 4539, 4831, 5171, 5797, 6456, 6976, 7298, 7832, 8232, 8655, 9038, 130, 610, 1025, 1344, 1924, 2343, 3596, 3951, 4540, 4832, 5172, 5798, 6457, 6977, 7299, 7833, 8233, 8656, 9039, 131, 611, 1026, 1345, 1925, 2344, 3597, 3952, 4541, 4833, 5173, 5799, 6458, 6978, 7300, 7834, 8234, 8657, 9040, 132, 612, 1027, 1346, 1926, 2345, 3598, 3953, 4542, 4834, 5174, 5800, 6459, 6979, 7301, 7835, 8235, 8658, 9041, 133, 613, 1028, 1347, 1927, 2346, 3599, 3954, 4543, 4835, 5175, 5801, 6460, 6980, 7302, 7836, 8236, 8659, 9042, 134, 614, 1029, 1348, 1928, 2347, 3600, 3955, 4544, 4836, 5176, 5802, 6461, 6981, 7303, 7837, 8237, 8660, 9043, 135, 615, 1030, 1349, 1929, 2348, 3601, 3956, 4545, 4837, 5177, 5803, 6462, 6982, 7304, 7838, 8238, 8661, 9044, 136, 616, 1031, 1350, 1930, 2349, 3602, 3957, 4546, 4838, 5178, 5804, 6463, 6983, 7305, 7839, 8239, 8662, 9045, 137, 617, 1032, 1351, 1931, 2350, 3603, 3958, 4547, 4839, 5179, 5805, 6464, 6984, 7306, 7840, 8240, 8663, 9046, 138, 618, 1033, 1352, 1932, 2351, 3604, 3959, 4548, 4840, 5180, 5806, 6465, 6985, 7307, 7841, 8241, 8664, 9047, 139, 619, 1034, 1353, 1933, 2352, 3605, 3960, 4549, 4841, 5181, 5807, 6466, 6986, 7308, 7842, 8242, 8665, 9048, 140, 620, 1035, 1354, 1934, 2353, 3606, 3961, 4550, 4842, 5182, 5808, 6467, 6987, 7309, 7843, 8243, 8666, 9049, 141, 621, 1036, 1355, 1935, 2354, 3607, 3962, 4551, 4843, 5183, 5809, 6468, 6988, 7310, 7844, 8244, 8667, 9050, 142, 622, 1037, 1356, 1936, 2355, 3608, 3963, 4552, 4844, 5184, 5810, 6469, 6989, 7311, 7845, 8245, 8668, 9051, 143, 623, 1038, 1357, 1937, 2356, 3609, 3964, 4553, 4845, 5185, 5811, 6470, 6990, 7312, 7846, 8246, 8669, 9052, 144, 624, 1039, 1358, 1938, 2357, 3610, 3965, 4554, 4846, 5186, 5812, 6471, 6991, 7313, 7847, 8247, 8670, 9053, 145, 625, 1040, 1359, 1939, 2358, 3611, 3966, 4555, 4847, 5187, 5813, 6472, 6992, 7314, 7848, 8248, 8671, 9054, 146, 626, 1041, 1360, 1940, 2359, 3612, 3967, 4556, 4848, 5188, 5814, 6473, 6993, 7315, 7849, 8249, 8672, 9055, 147, 627, 1042, 1361, 1941, 2360, 3613, 3968, 4557, 4849, 5189, 5815, 6474, 6994, 7316, 7850, 8250, 8673, 9056, 148, 628, 1043, 1362, 1942, 2361, 3614, 3969, 4558, 4850, 5190, 5816, 6475, 6995, 7317, 7851, 8251, 8674, 9057, 149, 629, 1044, 1363, 1943, 2362, 3615, 3970, 4559, 4851, 5191, 5817, 6476, 6996, 7318, 7852, 8252, 8675, 9058, 150, 630, 1045, 1364, 1944, 2363, 3616, 3971, 4560, 4852, 5192, 5818, 6477, 6997, 7319, 7853, 8253, 8676, 9059, 151, 631, 1046, 1365, 1945, 2364, 3617, 3972, 4561, 4853, 5193, 5819, 6478, 6998, 7320, 7854, 8254, 8677, 9060, 152, 632, 1047, 1366, 1946, 2365, 3618, 3973, 4562, 4854, 5194, 5820, 6479, 6999, 7321, 7855, 8255, 8678, 9061, 153, 633, 1048, 1367, 1947, 2366, 3619, 3974, 4563, 4855, 5195, 5821, 6480, 7000, 7322, 7856, 8256, 8679, 9062, 154, 634, 1049, 1368, 1948, 2367, 3620, 3975, 4564, 4856, 5196, 5822, 6481, 7001, 7323, 7857, 8257, 8680, 9063, 155, 635, 1050, 1369, 1949, 2368, 3621, 3976, 4565, 4857, 5197, 5823, 6482, 7002, 7324, 7858, 8258, 8681, 9064, 156, 636, 1051, 1370, 1950, 2369, 3622, 3977, 4566, 4858, 5198, 5824, 6483, 7003, 7325, 7859, 8259, 8682, 9065, 157, 637, 1052, 1371, 1951, 2370, 3623, 3978, 4567, 4859, 5199, 5825, 6484, 7004, 7326, 7860, 8260, 8683, 9066, 158, 638, 1053, 1372, 1952, 2371, 3624, 3979, 4568, 4860, 5200, 5826, 6485, 7005, 7327, 7861, 8261, 8684, 9067, 159, 639, 1054, 1373, 1953, 2372, 3625, 3980, 4569, 4861, 5201, 5827, 6486, 7006, 7328, 7862, 8262, 8685, 9068, 160, 640, 1055, 1374, 1954, 2373, 3626, 3981, 4570, 4862, 5202, 5828, 6487, 7007, 7329, 7863, 8263, 8686, 9069, 161, 641, 1056, 1375, 1955, 2374, 3627, 3982, 4571, 4863, 5203, 5829, 6488, 7008, 7330, 7864, 8264, 8687, 9070, 162, 642, 1057, 1376, 1956, 2375, 3628, 3983, 4572, 4864, 5204, 5830, 6489, 7009, 7331, 7865, 8265, 8688, 9071, 163, 643, 1058, 1377, 1957, 2376, 3629, 3984, 4573, 4865, 5205, 5831, 6490, 7010, 7332, 7866, 8266, 8689, 9072, 164, 644, 1059, 1378, 1958, 2377, 3630, 3985, 4574, 4866, 5206, 5832, 6491, 7011, 7333, 7867, 8267, 8690, 9073, 165, 645, 1060, 1379, 1959, 2378, 3631, 3986, 4575, 4867, 5207, 5833, 6492, 7012, 7334, 7868, 8268, 8691, 9074, 166, 646, 1061, 1380, 1960, 2379, 3632, 3987, 4576, 4868, 5208, 5834, 6493, 7013, 7335, 7869, 8269, 8692, 9075, 167, 647, 1062, 1381, 1961, 2380, 3633, 3988, 4577, 4869, 5209, 5835, 6494, 7014, 7336, 7870, 8270, 8693, 9076, 168, 648, 1063, 1382, 1962, 2381, 3634, 3989, 4578, 4870, 5210, 5836, 6495, 7015, 7337, 7871, 8271, 8694, 9077, 169, 649, 1064, 1383, 1963, 2382, 3635, 3990, 4579, 4871, 5211, 5837, 6496, 7016, 7338, 7872, 8272, 8695, 9078, 170, 650, 1065, 1384, 1964, 2383, 3636, 3991, 4580, 4872, 5212, 5838, 6497, 7017, 7339, 7873, 8273, 8696, 9079, 171, 651, 1066, 1385, 1965, 2384, 3637, 3992, 4581, 4873, 5213, 5839, 6498, 7018, 7340, 7874, 8274, 8697, 9080, 172, 652, 1067, 1386, 1966, 2385, 3638, 3993, 4582, 4874, 5214, 5840, 6499, 7019, 7341, 7875, 8275, 8698, 9081, 173, 653, 1068, 1387, 1967, 2386, 3639, 3994, 4583, 4875, 5215, 5841, 6500, 7020, 7342, 7876, 8276, 8699, 9082, 174, 654, 1069, 1388, 1968, 2387, 3640, 3995, 4584, 4876, 5216, 5842, 6501, 7021, 7343, 7877, 8277, 8700, 9083, 175, 655, 1070, 1389, 1969, 2388, 3641, 3996, 4585, 4877, 5217, 5843, 6502, 7022, 7344, 7878, 8278, 8701, 9084, 176, 656, 1071, 1390, 1970, 2389, 3642, 3997, 4586, 4878, 5218, 5844, 6503, 7023, 7345, 7879, 8279, 8702, 9085, 177, 657, 1072, 1391, 1971, 2390, 3643, 3998, 4587, 4879, 5219, 5845, 6504, 7024, 7346, 7880, 8280, 8703, 9086, 178, 658, 1073, 1392, 1972, 2391, 3644, 3999, 4588, 4880, 5220, 5846, 6505, 7025, 7347, 7881, 8281, 8704, 9087, 179, 659, 1074, 1393, 1973, 2392, 3645, 4000, 4589, 4881, 5221, 5847, 6506, 7026, 7348, 7882, 8282, 8705, 9088, 180, 660, 1075, 1394, 1974, 2393, 3646, 4001, 4590, 4882, 5222, 5848, 6507, 7027, 7349, 7883, 8283, 8706, 9089, 181, 661, 1076, 1395, 1975, 2394, 3647, 4002, 4591, 4883, 5223, 5849, 6508, 7028, 7350, 7884, 8284, 8707, 9090, 182, 662, 1077, 1396, 1976, 2395, 3648, 4003, 4592, 4884, 5224, 5850, 6509, 7029, 7351, 7885, 8285, 8708, 9091, 183, 663, 1078, 1397, 1977, 2396, 3649, 4004, 4593, 4885, 5225, 5851, 6510, 7030, 7352, 7886, 8286, 8709, 9092, 184, 664, 1079, 1398, 1978, 2397, 3650, 4005, 4594, 4886, 5226, 5852, 6511, 7031, 7353, 7887, 8287, 8710, 9093, 185, 665, 1080, 1399, 1979, 2398, 3651, 4006, 4595, 4887, 5227, 5853, 6512, 7032, 7354, 7888, 8288, 8711, 9094, 186, 666, 1081, 1400, 1980, 2399, 3652, 4007, 4596, 4888, 5228, 5854, 6513, 7033, 7355, 7889, 8289, 8712, 9095, 187, 667, 1082, 1401, 1981, 2400, 3653, 4008, 4597, 4889, 5229, 5855, 6514, 7034, 7356, 7890, 8290, 8713, 9096, 188, 668, 1083, 1402, 1982, 2401, 3654, 4009, 4598, 4890, 5230, 5856, 6515, 7035, 7357, 7891, 8291, 8714, 9097, 189, 669, 1084, 1403, 1983, 2402, 3655, 4010, 4599, 4891, 5231, 5857, 6516, 7036, 7358, 7892, 8292, 8715, 9098, 190, 670, 1085, 1404, 1984, 2403, 3656, 4011, 4600, 4892, 5232, 5858, 6517, 7037, 7359, 7893, 8293, 8716, 9099, 191, 671, 1086, 1405, 1985, 2404, 3657, 4012, 4601, 4893, 5233, 5859, 6518, 7038, 7360, 7894, 8294, 8717, 9100, 192, 672, 1087, 1406, 1986, 2405, 3658, 4013, 4602, 4894, 5234, 5860, 6519, 7039, 7361, 7895, 8295, 8718, 9101, 193, 673, 1088, 1407, 1987, 2406, 3659, 4014, 4603, 4895, 5235, 5861, 6520, 7040, 7362, 7896, 8296, 8719, 9102, 194, 674, 1089, 1408, 1988, 2407, 3660, 4015, 4604, 4896, 5236, 5862, 6521, 7041, 7363, 7897, 8297, 8720, 9103, 195, 675, 1090, 1409, 1989, 2408, 3661, 4016, 4605, 4897, 5237, 5863, 6522, 7042, 7364, 7898, 8298, 8721, 9104, 196, 676, 1091, 1410, 1990, 2409, 3662, 4017, 4606, 4898, 5238, 5864, 6523, 7043, 7365, 7899, 8299, 8722, 9105, 197, 677, 1092, 1411, 1991, 2410, 3663, 4018, 4607, 4899, 5239, 5865, 6524, 7044, 7366, 7900, 8300, 8723, 9106, 198, 678, 1093, 1412, 1992, 2411, 3664, 4019, 4224, 4900, 5240, 5866, 6525, 7045, 7367, 7901, 8301, 8724, 9107, 199, 679, 1094, 1413, 1993, 2412, 3665, 4020, 4225, 4901, 5241, 5867, 6526, 7046, 7368, 7902, 8302, 8725, 9108, 200, 680, 1095, 1414, 1994, 2413, 3666, 4021, 4226, 4902, 5242, 5868, 6527, 7047, 7369, 7903, 8303, 8726, 9109, 201, 681, 1096, 1415, 1995, 2414, 3667, 4022, 4227, 4903, 5243, 5869, 6144, 7048, 7370, 7904, 8304, 8727, 9110, 202, 682, 1097, 1416, 1996, 2415, 3668, 4023, 4228, 4904, 5244, 5870, 6145, 7049, 7371, 7905, 8305, 8728, 9111, 203, 683, 1098, 1417, 1997, 2416, 3669, 4024, 4229, 4905, 5245, 5871, 6146, 7050, 7372, 7906, 8306, 8729, 9112, 204, 684, 1099, 1418, 1998, 2417, 3670, 4025, 4230, 4906, 5246, 5872, 6147, 7051, 7373, 7907, 8307, 8730, 9113, 205, 685, 1100, 1419, 1999, 2418, 3671, 4026, 4231, 4907, 5247, 5873, 6148, 7052, 7374, 7908, 8308, 8731, 9114, 206, 686, 1101, 1420, 2000, 2419, 3672, 4027, 4232, 4908, 5248, 5874, 6149, 7053, 7375, 7909, 8309, 8732, 9115, 207, 687, 1102, 1421, 2001, 2420, 3673, 4028, 4233, 4909, 5249, 5875, 6150, 7054, 7376, 7910, 8310, 8733, 9116, 208, 688, 1103, 1422, 2002, 2421, 3674, 4029, 4234, 4910, 5250, 5876, 6151, 7055, 7377, 7911, 8311, 8734, 9117, 209, 689, 1104, 1423, 2003, 2422, 3675, 4030, 4235, 4911, 5251, 5877, 6152, 7056, 7378, 7912, 8312, 8735, 9118, 210, 690, 1105, 1424, 2004, 2423, 3676, 4031, 4236, 4912, 5252, 5878, 6153, 7057, 7379, 7913, 8313, 8736, 9119, 211, 691, 1106, 1425, 2005, 2424, 3677, 4032, 4237, 4913, 5253, 5879, 6154, 7058, 7380, 7914, 8314, 8737, 9120, 212, 692, 1107, 1426, 2006, 2425, 3678, 4033, 4238, 4914, 5254, 5880, 6155, 7059, 7381, 7915, 8315, 8738, 9121, 213, 693, 1108, 1427, 2007, 2426, 3679, 4034, 4239, 4915, 5255, 5881, 6156, 7060, 7382, 7916, 8316, 8739, 9122, 214, 694, 1109, 1428, 2008, 2427, 3680, 4035, 4240, 4916, 5256, 5882, 6157, 7061, 7383, 7917, 8317, 8740, 9123, 215, 695, 1110, 1429, 2009, 2428, 3681, 4036, 4241, 4917, 5257, 5883, 6158, 7062, 7384, 7918, 8318, 8741, 9124, 216, 696, 1111, 1430, 2010, 2429, 3682, 4037, 4242, 4918, 5258, 5884, 6159, 7063, 7385, 7919, 8319, 8742, 9125, 217, 697, 1112, 1431, 2011, 2430, 3683, 4038, 4243, 4919, 5259, 5885, 6160, 7064, 7386, 7920, 8320, 8743, 9126, 218, 698, 1113, 1432, 2012, 2431, 3684, 4039, 4244, 4920, 5260, 5886, 6161, 7065, 7387, 7921, 8321, 8744, 9127, 219, 699, 1114, 1433, 2013, 2432, 3685, 4040, 4245, 4921, 5261, 5887, 6162, 7066, 7388, 7922, 8322, 8745, 9128, 220, 700, 1115, 1434, 2014, 2433, 3686, 4041, 4246, 4922, 5262, 5888, 6163, 7067, 7389, 7923, 8323, 8746, 9129, 221, 701, 1116, 1435, 2015, 2434, 3687, 4042, 4247, 4923, 5263, 5889, 6164, 7068, 7390, 7924, 8324, 8747, 9130, 222, 702, 1117, 1436, 2016, 2435, 3688, 4043, 4248, 4924, 5264, 5890, 6165, 7069, 7391, 7925, 8325, 8748, 9131, 223, 703, 1118, 1437, 2017, 2436, 3689, 4044, 4249, 4925, 5265, 5891, 6166, 7070, 7392, 7926, 8326, 8749, 9132, 224, 704, 1119, 1438, 2018, 2437, 3690, 4045, 4250, 4926, 5266, 5892, 6167, 7071, 7393, 7927, 8327, 8750, 9133, 225, 705, 1120, 1439, 2019, 2438, 3691, 4046, 4251, 4927, 5267, 5893, 6168, 7072, 7394, 7928, 8328, 8751, 9134, 226, 706, 1121, 1440, 2020, 2439, 3692, 4047, 4252, 4928, 5268, 5894, 6169, 7073, 7395, 7929, 8329, 8752, 9135, 227, 707, 1122, 1441, 2021, 2440, 3693, 4048, 4253, 4929, 5269, 5895, 6170, 7074, 7396, 7930, 8330, 8753, 9136, 228, 708, 1123, 1442, 2022, 2441, 3694, 4049, 4254, 4930, 5270, 5896, 6171, 7075, 7397, 7931, 8331, 8754, 9137, 229, 709, 1124, 1443, 2023, 2442, 3695, 4050, 4255, 4931, 5271, 5897, 6172, 7076, 7398, 7932, 8332, 8755, 9138, 230, 710, 1125, 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9066, 9450, 311, 1079, 1460, 1675, 2299, 2870, 3254, 3485, 4370, 4801, 5444, 6094, 6349, 6877, 7478, 8411, 8683, 9067, 9451, 312, 1080, 1461, 1676, 2300, 2871, 3255, 3486, 4371, 4802, 5445, 6095, 6350, 6878, 7479, 8412, 8684, 9068, 9452, 313, 1081, 1462, 1677, 2301, 2872, 3256, 3487, 4372, 4803, 5446, 6096, 6351, 6879, 7480, 8413, 8685, 9069, 9453, 314, 1082, 1463, 1678, 2302, 2873, 3257, 3488, 4373, 4804, 5447, 6097, 6352, 6880, 7481, 8414, 8686, 9070, 9454, 315, 1083, 1464, 1679, 2303, 2874, 3258, 3489, 4374, 4805, 5448, 6098, 6353, 6881, 7482, 8415, 8687, 9071, 9455, 316, 1084, 1465, 1680, 1920, 2875, 3259, 3490, 4375, 4806, 5449, 6099, 6354, 6882, 7483, 8416, 8688, 9072, 9456, 317, 1085, 1466, 1681, 1921, 2876, 3260, 3491, 4376, 4807, 5450, 6100, 6355, 6883, 7484, 8417, 8689, 9073, 9457, 318, 1086, 1467, 1682, 1922, 2877, 3261, 3492, 4377, 4808, 5451, 6101, 6356, 6884, 7485, 8418, 8690, 9074, 9458, 319, 1087, 1468, 1683, 1923, 2878, 3262, 3493, 4378, 4809, 5452, 6102, 6357, 6885, 7486, 8419, 8691, 9075, 9459, 320, 1088, 1469, 1684, 1924, 2879, 3263, 3494, 4379, 4810, 5453, 6103, 6358, 6886, 7487, 8420, 8692, 9076, 9460, 321, 1089, 1470, 1685, 1925, 2880, 3264, 3495, 4380, 4811, 5454, 6104, 6359, 6887, 7488, 8421, 8693, 9077, 9461, 322, 1090, 1471, 1686, 1926, 2881, 3265, 3496, 4381, 4812, 5455, 6105, 6360, 6888, 7489, 8422, 8694, 9078, 9462, 323, 1091, 1472, 1687, 1927, 2882, 3266, 3497, 4382, 4813, 5456, 6106, 6361, 6889, 7490, 8423, 8695, 9079, 9463, 324, 1092, 1473, 1688, 1928, 2883, 3267, 3498, 4383, 4814, 5457, 6107, 6362, 6890, 7491, 8424, 8696, 9080, 9464, 325, 1093, 1474, 1689, 1929, 2884, 3268, 3499, 4384, 4815, 5458, 6108, 6363, 6891, 7492, 8425, 8697, 9081, 9465, 326, 1094, 1475, 1690, 1930, 2885, 3269, 3500, 4385, 4816, 5459, 6109, 6364, 6892, 7493, 8426, 8698, 9082, 9466, 327, 1095, 1476, 1691, 1931, 2886, 3270, 3501, 4386, 4817, 5460, 6110, 6365, 6893, 7494, 8427, 8699, 9083, 9467, 328, 1096, 1477, 1692, 1932, 2887, 3271, 3502, 4387, 4818, 5461, 6111, 6366, 6894, 7495, 8428, 8700, 9084, 9468, 329, 1097, 1478, 1693, 1933, 2888, 3272, 3503, 4388, 4819, 5462, 6112, 6367, 6895, 7496, 8429, 8701, 9085, 9469, 330, 1098, 1479, 1694, 1934, 2889, 3273, 3504, 4389, 4820, 5463, 6113, 6368, 6896, 7497, 8430, 8702, 9086, 9470, 331, 1099, 1480, 1695, 1935, 2890, 3274, 3505, 4390, 4821, 5464, 6114, 6369, 6897, 7498, 8431, 8703, 9087, 9471, 332, 1100, 1481, 1696, 1936, 2891, 3275, 3506, 4391, 4822, 5465, 6115, 6370, 6898, 7499, 8432, 8704, 9088, 9472, 333, 1101, 1482, 1697, 1937, 2892, 3276, 3507, 4392, 4823, 5466, 6116, 6371, 6899, 7500, 8433, 8705, 9089, 9473, 334, 1102, 1483, 1698, 1938, 2893, 3277, 3508, 4393, 4824, 5467, 6117, 6372, 6900, 7501, 8434, 8706, 9090, 9474, 335, 1103, 1484, 1699, 1939, 2894, 3278, 3509, 4394, 4825, 5468, 6118, 6373, 6901, 7502, 8435, 8707, 9091, 9475, 336, 1104, 1485, 1700, 1940, 2895, 3279, 3510, 4395, 4826, 5469, 6119, 6374, 6902, 7503, 8436, 8708, 9092, 9476, 337, 1105, 1486, 1701, 1941, 2896, 3280, 3511, 4396, 4827, 5470, 6120, 6375, 6903, 7504, 8437, 8709, 9093, 9477, 338, 1106, 1487, 1702, 1942, 2897, 3281, 3512, 4397, 4828, 5471, 6121, 6376, 6904, 7505, 8438, 8710, 9094, 9478, 339, 1107, 1488, 1703, 1943, 2898, 3282, 3513, 4398, 4829, 5472, 6122, 6377, 6905, 7506, 8439, 8711, 9095, 9479, 340, 1108, 1489, 1704, 1944, 2899, 3283, 3514, 4399, 4830, 5473, 6123, 6378, 6906, 7507, 8440, 8712, 9096, 9480, 341, 1109, 1490, 1705, 1945, 2900, 3284, 3515, 4400, 4831, 5474, 6124, 6379, 6907, 7508, 8441, 8713, 9097, 9481, 342, 1110, 1491, 1706, 1946, 2901, 3285, 3516, 4401, 4832, 5475, 6125, 6380, 6908, 7509, 8442, 8714, 9098, 9482, 343, 1111, 1492, 1707, 1947, 2902, 3286, 3517, 4402, 4833, 5476, 6126, 6381, 6909, 7510, 8443, 8715, 9099, 9483, 344, 1112, 1493, 1708, 1948, 2903, 3287, 3518, 4403, 4834, 5477, 6127, 6382, 6910, 7511, 8444, 8716, 9100, 9484, 345, 1113, 1494, 1709, 1949, 2904, 3288, 3519, 4404, 4835, 5478, 6128, 6383, 6911, 7512, 8445, 8717, 9101, 9485, 346, 1114, 1495, 1710, 1950, 2905, 3289, 3520, 4405, 4836, 5479, 6129, 6384, 6528, 7513, 8446, 8718, 9102, 9486, 347, 1115, 1496, 1711, 1951, 2906, 3290, 3521, 4406, 4837, 5480, 6130, 6385, 6529, 7514, 8447, 8719, 9103, 9487, 348, 1116, 1497, 1712, 1952, 2907, 3291, 3522, 4407, 4838, 5481, 6131, 6386, 6530, 7515, 8064, 8720, 9104, 9488, 349, 1117, 1498, 1713, 1953, 2908, 3292, 3523, 4408, 4839, 5482, 6132, 6387, 6531, 7516, 8065, 8721, 9105, 9489, 350, 1118, 1499, 1714, 1954, 2909, 3293, 3524, 4409, 4840, 5483, 6133, 6388, 6532, 7517, 8066, 8722, 9106, 9490, 351, 1119, 1500, 1715, 1955, 2910, 3294, 3525, 4410, 4841, 5484, 6134, 6389, 6533, 7518, 8067, 8723, 9107, 9491, 352, 1120, 1501, 1716, 1956, 2911, 3295, 3526, 4411, 4842, 5485, 6135, 6390, 6534, 7519, 8068, 8724, 9108, 9492, 353, 1121, 1502, 1717, 1957, 2912, 3296, 3527, 4412, 4843, 5486, 6136, 6391, 6535, 7520, 8069, 8725, 9109, 9493, 354, 1122, 1503, 1718, 1958, 2913, 3297, 3528, 4413, 4844, 5487, 6137, 6392, 6536, 7521, 8070, 8726, 9110, 9494, 355, 1123, 1504, 1719, 1959, 2914, 3298, 3529, 4414, 4845, 5488, 6138, 6393, 6537, 7522, 8071, 8727, 9111, 9495, 356, 1124, 1505, 1720, 1960, 2915, 3299, 3530, 4415, 4846, 5489, 6139, 6394, 6538, 7523, 8072, 8728, 9112, 9496, 357, 1125, 1506, 1721, 1961, 2916, 3300, 3531, 4416, 4847, 5490, 6140, 6395, 6539, 7524, 8073, 8729, 9113, 9497, 358, 1126, 1507, 1722, 1962, 2917, 3301, 3532, 4417, 4848, 5491, 6141, 6396, 6540, 7525, 8074, 8730, 9114, 9498, 359, 1127, 1508, 1723, 1963, 2918, 3302, 3533, 4418, 4849, 5492, 6142, 6397, 6541, 7526, 8075, 8731, 9115, 9499, 360, 1128, 1509, 1724, 1964, 2919, 3303, 3534, 4419, 4850, 5493, 6143, 6398, 6542, 7527, 8076, 8732, 9116, 9500, 361, 1129, 1510, 1725, 1965, 2920, 3304, 3535, 4420, 4851, 5494, 5760, 6399, 6543, 7528, 8077, 8733, 9117, 9501, 362, 1130, 1511, 1726, 1966, 2921, 3305, 3536, 4421, 4852, 5495, 5761, 6400, 6544, 7529, 8078, 8734, 9118, 9502, 363, 1131, 1512, 1727, 1967, 2922, 3306, 3537, 4422, 4853, 5496, 5762, 6401, 6545, 7530, 8079, 8735, 9119, 9503, 364, 1132, 1513, 1728, 1968, 2923, 3307, 3538, 4423, 4854, 5497, 5763, 6402, 6546, 7531, 8080, 8736, 9120, 9504, 365, 1133, 1514, 1729, 1969, 2924, 3308, 3539, 4424, 4855, 5498, 5764, 6403, 6547, 7532, 8081, 8737, 9121, 9505, 366, 1134, 1515, 1730, 1970, 2925, 3309, 3540, 4425, 4856, 5499, 5765, 6404, 6548, 7533, 8082, 8738, 9122, 9506, 367, 1135, 1516, 1731, 1971, 2926, 3310, 3541, 4426, 4857, 5500, 5766, 6405, 6549, 7534, 8083, 8739, 9123, 9507, 368, 1136, 1517, 1732, 1972, 2927, 3311, 3542, 4427, 4858, 5501, 5767, 6406, 6550, 7535, 8084, 8740, 9124, 9508, 369, 1137, 1518, 1733, 1973, 2928, 3312, 3543, 4428, 4859, 5502, 5768, 6407, 6551, 7536, 8085, 8741, 9125, 9509, 370, 1138, 1519, 1734, 1974, 2929, 3313, 3544, 4429, 4860, 5503, 5769, 6408, 6552, 7537, 8086, 8742, 9126, 9510, 371, 1139, 1520, 1735, 1975, 2930, 3314, 3545, 4430, 4861, 5504, 5770, 6409, 6553, 7538, 8087, 8743, 9127, 9511, 372, 1140, 1521, 1736, 1976, 2931, 3315, 3546, 4431, 4862, 5505, 5771, 6410, 6554, 7539, 8088, 8744, 9128, 9512, 373, 1141, 1522, 1737, 1977, 2932, 3316, 3547, 4432, 4863, 5506, 5772, 6411, 6555, 7540, 8089, 8745, 9129, 9513, 374, 1142, 1523, 1738, 1978, 2933, 3317, 3548, 4433, 4864, 5507, 5773, 6412, 6556, 7541, 8090, 8746, 9130, 9514, 375, 1143, 1524, 1739, 1979, 2934, 3318, 3549, 4434, 4865, 5508, 5774, 6413, 6557, 7542, 8091, 8747, 9131, 9515, 376, 1144, 1525, 1740, 1980, 2935, 3319, 3550, 4435, 4866, 5509, 5775, 6414, 6558, 7543, 8092, 8748, 9132, 9516, 377, 1145, 1526, 1741, 1981, 2936, 3320, 3551, 4436, 4867, 5510, 5776, 6415, 6559, 7544, 8093, 8749, 9133, 9517, 378, 1146, 1527, 1742, 1982, 2937, 3321, 3552, 4437, 4868, 5511, 5777, 6416, 6560, 7545, 8094, 8750, 9134, 9518, 379, 1147, 1528, 1743, 1983, 2938, 3322, 3553, 4438, 4869, 5512, 5778, 6417, 6561, 7546, 8095, 8751, 9135, 9519, 380, 1148, 1529, 1744, 1984, 2939, 3323, 3554, 4439, 4870, 5513, 5779, 6418, 6562, 7547, 8096, 8752, 9136, 9520, 381, 1149, 1530, 1745, 1985, 2940, 3324, 3555, 4440, 4871, 5514, 5780, 6419, 6563, 7548, 8097, 8753, 9137, 9521, 382, 1150, 1531, 1746, 1986, 2941, 3325, 3556, 4441, 4872, 5515, 5781, 6420, 6564, 7549, 8098, 8754, 9138, 9522, 383, 1151, 1532, 1747, 1987, 2942, 3326, 3557, 4442, 4873, 5516, 5782, 6421, 6565, 7550, 8099, 8755, 9139, 9523, 0, 768, 1533, 1748, 1988, 2943, 3327, 3558, 4443, 4874, 5517, 5783, 6422, 6566, 7551, 8100, 8756, 9140, 9524, 1, 769, 1534, 1749, 1989, 2944, 3328, 3559, 4444, 4875, 5518, 5784, 6423, 6567, 7552, 8101, 8757, 9141, 9525, 2, 770, 1535, 1750, 1990, 2945, 3329, 3560, 4445, 4876, 5519, 5785, 6424, 6568, 7553, 8102, 8758, 9142, 9526, 3, 771, 1152, 1751, 1991, 2946, 3330, 3561, 4446, 4877, 5520, 5786, 6425, 6569, 7554, 8103, 8759, 9143, 9527, 4, 772, 1153, 1752, 1992, 2947, 3331, 3562, 4447, 4878, 5521, 5787, 6426, 6570, 7555, 8104, 8760, 9144, 9528, 5, 773, 1154, 1753, 1993, 2948, 3332, 3563, 4448, 4879, 5522, 5788, 6427, 6571, 7556, 8105, 8761, 9145, 9529, 6, 774, 1155, 1754, 1994, 2949, 3333, 3564, 4449, 4880, 5523, 5789, 6428, 6572, 7557, 8106, 8762, 9146, 9530, 7, 775, 1156, 1755, 1995, 2950, 3334, 3565, 4450, 4881, 5524, 5790, 6429, 6573, 7558, 8107, 8763, 9147, 9531, 8, 776, 1157, 1756, 1996, 2951, 3335, 3566, 4451, 4882, 5525, 5791, 6430, 6574, 7559, 8108, 8764, 9148, 9532, 9, 777, 1158, 1757, 1997, 2952, 3336, 3567, 4452, 4883, 5526, 5792, 6431, 6575, 7560, 8109, 8765, 9149, 9533, 10, 778, 1159, 1758, 1998, 2953, 3337, 3568, 4453, 4884, 5527, 5793, 6432, 6576, 7561, 8110, 8766, 9150, 9534, 11, 779, 1160, 1759, 1999, 2954, 3338, 3569, 4454, 4885, 5528, 5794, 6433, 6577, 7562, 8111, 8767, 9151, 9535, 12, 780, 1161, 1760, 2000, 2955, 3339, 3570, 4455, 4886, 5529, 5795, 6434, 6578, 7563, 8112, 8768, 9152, 9536, 13, 781, 1162, 1761, 2001, 2956, 3340, 3571, 4456, 4887, 5530, 5796, 6435, 6579, 7564, 8113, 8769, 9153, 9537, 14, 782, 1163, 1762, 2002, 2957, 3341, 3572, 4457, 4888, 5531, 5797, 6436, 6580, 7565, 8114, 8770, 9154, 9538, 15, 783, 1164, 1763, 2003, 2958, 3342, 3573, 4458, 4889, 5532, 5798, 6437, 6581, 7566, 8115, 8771, 9155, 9539, 16, 784, 1165, 1764, 2004, 2959, 3343, 3574, 4459, 4890, 5533, 5799, 6438, 6582, 7567, 8116, 8772, 9156, 9540, 17, 785, 1166, 1765, 2005, 2960, 3344, 3575, 4460, 4891, 5534, 5800, 6439, 6583, 7568, 8117, 8773, 9157, 9541, 18, 786, 1167, 1766, 2006, 2961, 3345, 3576, 4461, 4892, 5535, 5801, 6440, 6584, 7569, 8118, 8774, 9158, 9542, 19, 787, 1168, 1767, 2007, 2962, 3346, 3577, 4462, 4893, 5536, 5802, 6441, 6585, 7570, 8119, 8775, 9159, 9543, 20, 788, 1169, 1768, 2008, 2963, 3347, 3578, 4463, 4894, 5537, 5803, 6442, 6586, 7571, 8120, 8776, 9160, 9544, 21, 789, 1170, 1769, 2009, 2964, 3348, 3579, 4464, 4895, 5538, 5804, 6443, 6587, 7572, 8121, 8777, 9161, 9545, 22, 790, 1171, 1770, 2010, 2965, 3349, 3580, 4465, 4896, 5539, 5805, 6444, 6588, 7573, 8122, 8778, 9162, 9546, 23, 791, 1172, 1771, 2011, 2966, 3350, 3581, 4466, 4897, 5540, 5806, 6445, 6589, 7574, 8123, 8779, 9163, 9547, 24, 792, 1173, 1772, 2012, 2967, 3351, 3582, 4467, 4898, 5541, 5807, 6446, 6590, 7575, 8124, 8780, 9164, 9548, 25, 793, 1174, 1773, 2013, 2968, 3352, 3583, 4468, 4899, 5542, 5808, 6447, 6591, 7576, 8125, 8781, 9165, 9549, 26, 794, 1175, 1774, 2014, 2969, 3353, 3584, 4469, 4900, 5543, 5809, 6448, 6592, 7577, 8126, 8782, 9166, 9550, 27, 795, 1176, 1775, 2015, 2970, 3354, 3585, 4470, 4901, 5544, 5810, 6449, 6593, 7578, 8127, 8783, 9167, 9551, 28, 796, 1177, 1776, 2016, 2971, 3355, 3586, 4471, 4902, 5545, 5811, 6450, 6594, 7579, 8128, 8784, 9168, 9552, 29, 797, 1178, 1777, 2017, 2972, 3356, 3587, 4472, 4903, 5546, 5812, 6451, 6595, 7580, 8129, 8785, 9169, 9553, 30, 798, 1179, 1778, 2018, 2973, 3357, 3588, 4473, 4904, 5547, 5813, 6452, 6596, 7581, 8130, 8786, 9170, 9554, 31, 799, 1180, 1779, 2019, 2974, 3358, 3589, 4474, 4905, 5548, 5814, 6453, 6597, 7582, 8131, 8787, 9171, 9555, 32, 800, 1181, 1780, 2020, 2975, 3359, 3590, 4475, 4906, 5549, 5815, 6454, 6598, 7583, 8132, 8788, 9172, 9556, 33, 801, 1182, 1781, 2021, 2976, 3360, 3591, 4476, 4907, 5550, 5816, 6455, 6599, 7584, 8133, 8789, 9173, 9557, 34, 802, 1183, 1782, 2022, 2977, 3361, 3592, 4477, 4908, 5551, 5817, 6456, 6600, 7585, 8134, 8790, 9174, 9558, 35, 803, 1184, 1783, 2023, 2978, 3362, 3593, 4478, 4909, 5552, 5818, 6457, 6601, 7586, 8135, 8791, 9175, 9559, 36, 804, 1185, 1784, 2024, 2979, 3363, 3594, 4479, 4910, 5553, 5819, 6458, 6602, 7587, 8136, 8792, 9176, 9560, 37, 805, 1186, 1785, 2025, 2980, 3364, 3595, 4480, 4911, 5554, 5820, 6459, 6603, 7588, 8137, 8793, 9177, 9561, 38, 806, 1187, 1786, 2026, 2981, 3365, 3596, 4481, 4912, 5555, 5821, 6460, 6604, 7589, 8138, 8794, 9178, 9562, 39, 807, 1188, 1787, 2027, 2982, 3366, 3597, 4482, 4913, 5556, 5822, 6461, 6605, 7590, 8139, 8795, 9179, 9563, 40, 808, 1189, 1788, 2028, 2983, 3367, 3598, 4483, 4914, 5557, 5823, 6462, 6606, 7591, 8140, 8796, 9180, 9564, 41, 809, 1190, 1789, 2029, 2984, 3368, 3599, 4484, 4915, 5558, 5824, 6463, 6607, 7592, 8141, 8797, 9181, 9565, 42, 810, 1191, 1790, 2030, 2985, 3369, 3600, 4485, 4916, 5559, 5825, 6464, 6608, 7593, 8142, 8798, 9182, 9566, 43, 811, 1192, 1791, 2031, 2986, 3370, 3601, 4486, 4917, 5560, 5826, 6465, 6609, 7594, 8143, 8799, 9183, 9567, 44, 812, 1193, 1792, 2032, 2987, 3371, 3602, 4487, 4918, 5561, 5827, 6466, 6610, 7595, 8144, 8800, 9184, 9568, 45, 813, 1194, 1793, 2033, 2988, 3372, 3603, 4488, 4919, 5562, 5828, 6467, 6611, 7596, 8145, 8801, 9185, 9569, 46, 814, 1195, 1794, 2034, 2989, 3373, 3604, 4489, 4920, 5563, 5829, 6468, 6612, 7597, 8146, 8802, 9186, 9570, 47, 815, 1196, 1795, 2035, 2990, 3374, 3605, 4490, 4921, 5564, 5830, 6469, 6613, 7598, 8147, 8803, 9187, 9571, 48, 816, 1197, 1796, 2036, 2991, 3375, 3606, 4491, 4922, 5565, 5831, 6470, 6614, 7599, 8148, 8804, 9188, 9572, 49, 817, 1198, 1797, 2037, 2992, 3376, 3607, 4492, 4923, 5566, 5832, 6471, 6615, 7600, 8149, 8805, 9189, 9573, 50, 818, 1199, 1798, 2038, 2993, 3377, 3608, 4493, 4924, 5567, 5833, 6472, 6616, 7601, 8150, 8806, 9190, 9574, 51, 819, 1200, 1799, 2039, 2994, 3378, 3609, 4494, 4925, 5568, 5834, 6473, 6617, 7602, 8151, 8807, 9191, 9575, 52, 820, 1201, 1800, 2040, 2995, 3379, 3610, 4495, 4926, 5569, 5835, 6474, 6618, 7603, 8152, 8808, 9192, 9576, 53, 821, 1202, 1801, 2041, 2996, 3380, 3611, 4496, 4927, 5570, 5836, 6475, 6619, 7604, 8153, 8809, 9193, 9577, 54, 822, 1203, 1802, 2042, 2997, 3381, 3612, 4497, 4928, 5571, 5837, 6476, 6620, 7605, 8154, 8810, 9194, 9578, 55, 823, 1204, 1803, 2043, 2998, 3382, 3613, 4498, 4929, 5572, 5838, 6477, 6621, 7606, 8155, 8811, 9195, 9579, 56, 824, 1205, 1804, 2044, 2999, 3383, 3614, 4499, 4930, 5573, 5839, 6478, 6622, 7607, 8156, 8812, 9196, 9580, 57, 825, 1206, 1805, 2045, 3000, 3384, 3615, 4500, 4931, 5574, 5840, 6479, 6623, 7608, 8157, 8813, 9197, 9581, 58, 826, 1207, 1806, 2046, 3001, 3385, 3616, 4501, 4932, 5575, 5841, 6480, 6624, 7609, 8158, 8814, 9198, 9582, 59, 827, 1208, 1807, 2047, 3002, 3386, 3617, 4502, 4933, 5576, 5842, 6481, 6625, 7610, 8159, 8815, 9199, 9583, 60, 828, 1209, 1808, 2048, 3003, 3387, 3618, 4503, 4934, 5577, 5843, 6482, 6626, 7611, 8160, 8816, 9200, 9584, 61, 829, 1210, 1809, 2049, 3004, 3388, 3619, 4504, 4935, 5578, 5844, 6483, 6627, 7612, 8161, 8817, 9201, 9585, 62, 830, 1211, 1810, 2050, 3005, 3389, 3620, 4505, 4936, 5579, 5845, 6484, 6628, 7613, 8162, 8818, 9202, 9586, 63, 831, 1212, 1811, 2051, 3006, 3390, 3621, 4506, 4937, 5580, 5846, 6485, 6629, 7614, 8163, 8819, 9203, 9587, 64, 832, 1213, 1812, 2052, 3007, 3391, 3622, 4507, 4938, 5581, 5847, 6486, 6630, 7615, 8164, 8820, 9204, 9588, 65, 833, 1214, 1813, 2053, 3008, 3392, 3623, 4508, 4939, 5582, 5848, 6487, 6631, 7616, 8165, 8821, 9205, 9589, 66, 834, 1215, 1814, 2054, 3009, 3393, 3624, 4509, 4940, 5583, 5849, 6488, 6632, 7617, 8166, 8822, 9206, 9590, 67, 835, 1216, 1815, 2055, 3010, 3394, 3625, 4510, 4941, 5584, 5850, 6489, 6633, 7618, 8167, 8823, 9207, 9591, 68, 836, 1217, 1816, 2056, 3011, 3395, 3626, 4511, 4942, 5585, 5851, 6490, 6634, 7619, 8168, 8824, 9208, 9592, 69, 837, 1218, 1817, 2057, 3012, 3396, 3627, 4512, 4943, 5586, 5852, 6491, 6635, 7620, 8169, 8825, 9209, 9593, 70, 838, 1219, 1818, 2058, 3013, 3397, 3628, 4513, 4944, 5587, 5853, 6492, 6636, 7621, 8170, 8826, 9210, 9594, 71, 839, 1220, 1819, 2059, 3014, 3398, 3629, 4514, 4945, 5588, 5854, 6493, 6637, 7622, 8171, 8827, 9211, 9595, 72, 840, 1221, 1820, 2060, 3015, 3399, 3630, 4515, 4946, 5589, 5855, 6494, 6638, 7623, 8172, 8828, 9212, 9596, 73, 841, 1222, 1821, 2061, 3016, 3400, 3631, 4516, 4947, 5590, 5856, 6495, 6639, 7624, 8173, 8829, 9213, 9597, 74, 842, 1223, 1822, 2062, 3017, 3401, 3632, 4517, 4948, 5591, 5857, 6496, 6640, 7625, 8174, 8830, 9214, 9598, 75, 843, 1224, 1823, 2063, 3018, 3402, 3633, 4518, 4949, 5592, 5858, 6497, 6641, 7626, 8175, 8831, 9215, 9599, 205, 634, 1096, 1868, 2176, 2465, 2955, 3232, 3519, 3969, 5192, 5464, 5813, 6659, 7152, 7501, 7693, 9216, 9600, 206, 635, 1097, 1869, 2177, 2466, 2956, 3233, 3520, 3970, 5193, 5465, 5814, 6660, 7153, 7502, 7694, 9217, 9601, 207, 636, 1098, 1870, 2178, 2467, 2957, 3234, 3521, 3971, 5194, 5466, 5815, 6661, 7154, 7503, 7695, 9218, 9602, 208, 637, 1099, 1871, 2179, 2468, 2958, 3235, 3522, 3972, 5195, 5467, 5816, 6662, 7155, 7504, 7696, 9219, 9603, 209, 638, 1100, 1872, 2180, 2469, 2959, 3236, 3523, 3973, 5196, 5468, 5817, 6663, 7156, 7505, 7697, 9220, 9604, 210, 639, 1101, 1873, 2181, 2470, 2960, 3237, 3524, 3974, 5197, 5469, 5818, 6664, 7157, 7506, 7698, 9221, 9605, 211, 640, 1102, 1874, 2182, 2471, 2961, 3238, 3525, 3975, 5198, 5470, 5819, 6665, 7158, 7507, 7699, 9222, 9606, 212, 641, 1103, 1875, 2183, 2472, 2962, 3239, 3526, 3976, 5199, 5471, 5820, 6666, 7159, 7508, 7700, 9223, 9607, 213, 642, 1104, 1876, 2184, 2473, 2963, 3240, 3527, 3977, 5200, 5472, 5821, 6667, 7160, 7509, 7701, 9224, 9608, 214, 643, 1105, 1877, 2185, 2474, 2964, 3241, 3528, 3978, 5201, 5473, 5822, 6668, 7161, 7510, 7702, 9225, 9609, 215, 644, 1106, 1878, 2186, 2475, 2965, 3242, 3529, 3979, 5202, 5474, 5823, 6669, 7162, 7511, 7703, 9226, 9610, 216, 645, 1107, 1879, 2187, 2476, 2966, 3243, 3530, 3980, 5203, 5475, 5824, 6670, 7163, 7512, 7704, 9227, 9611, 217, 646, 1108, 1880, 2188, 2477, 2967, 3244, 3531, 3981, 5204, 5476, 5825, 6671, 7164, 7513, 7705, 9228, 9612, 218, 647, 1109, 1881, 2189, 2478, 2968, 3245, 3532, 3982, 5205, 5477, 5826, 6672, 7165, 7514, 7706, 9229, 9613, 219, 648, 1110, 1882, 2190, 2479, 2969, 3246, 3533, 3983, 5206, 5478, 5827, 6673, 7166, 7515, 7707, 9230, 9614, 220, 649, 1111, 1883, 2191, 2480, 2970, 3247, 3534, 3984, 5207, 5479, 5828, 6674, 7167, 7516, 7708, 9231, 9615, 221, 650, 1112, 1884, 2192, 2481, 2971, 3248, 3535, 3985, 5208, 5480, 5829, 6675, 7168, 7517, 7709, 9232, 9616, 222, 651, 1113, 1885, 2193, 2482, 2972, 3249, 3536, 3986, 5209, 5481, 5830, 6676, 7169, 7518, 7710, 9233, 9617, 223, 652, 1114, 1886, 2194, 2483, 2973, 3250, 3537, 3987, 5210, 5482, 5831, 6677, 7170, 7519, 7711, 9234, 9618, 224, 653, 1115, 1887, 2195, 2484, 2974, 3251, 3538, 3988, 5211, 5483, 5832, 6678, 7171, 7520, 7712, 9235, 9619, 225, 654, 1116, 1888, 2196, 2485, 2975, 3252, 3539, 3989, 5212, 5484, 5833, 6679, 7172, 7521, 7713, 9236, 9620, 226, 655, 1117, 1889, 2197, 2486, 2976, 3253, 3540, 3990, 5213, 5485, 5834, 6680, 7173, 7522, 7714, 9237, 9621, 227, 656, 1118, 1890, 2198, 2487, 2977, 3254, 3541, 3991, 5214, 5486, 5835, 6681, 7174, 7523, 7715, 9238, 9622, 228, 657, 1119, 1891, 2199, 2488, 2978, 3255, 3542, 3992, 5215, 5487, 5836, 6682, 7175, 7524, 7716, 9239, 9623, 229, 658, 1120, 1892, 2200, 2489, 2979, 3256, 3543, 3993, 5216, 5488, 5837, 6683, 7176, 7525, 7717, 9240, 9624, 230, 659, 1121, 1893, 2201, 2490, 2980, 3257, 3544, 3994, 5217, 5489, 5838, 6684, 7177, 7526, 7718, 9241, 9625, 231, 660, 1122, 1894, 2202, 2491, 2981, 3258, 3545, 3995, 5218, 5490, 5839, 6685, 7178, 7527, 7719, 9242, 9626, 232, 661, 1123, 1895, 2203, 2492, 2982, 3259, 3546, 3996, 5219, 5491, 5840, 6686, 7179, 7528, 7720, 9243, 9627, 233, 662, 1124, 1896, 2204, 2493, 2983, 3260, 3547, 3997, 5220, 5492, 5841, 6687, 7180, 7529, 7721, 9244, 9628, 234, 663, 1125, 1897, 2205, 2494, 2984, 3261, 3548, 3998, 5221, 5493, 5842, 6688, 7181, 7530, 7722, 9245, 9629, 235, 664, 1126, 1898, 2206, 2495, 2985, 3262, 3549, 3999, 5222, 5494, 5843, 6689, 7182, 7531, 7723, 9246, 9630, 236, 665, 1127, 1899, 2207, 2496, 2986, 3263, 3550, 4000, 5223, 5495, 5844, 6690, 7183, 7532, 7724, 9247, 9631, 237, 666, 1128, 1900, 2208, 2497, 2987, 3264, 3551, 4001, 5224, 5496, 5845, 6691, 7184, 7533, 7725, 9248, 9632, 238, 667, 1129, 1901, 2209, 2498, 2988, 3265, 3552, 4002, 5225, 5497, 5846, 6692, 7185, 7534, 7726, 9249, 9633, 239, 668, 1130, 1902, 2210, 2499, 2989, 3266, 3553, 4003, 5226, 5498, 5847, 6693, 7186, 7535, 7727, 9250, 9634, 240, 669, 1131, 1903, 2211, 2500, 2990, 3267, 3554, 4004, 5227, 5499, 5848, 6694, 7187, 7536, 7728, 9251, 9635, 241, 670, 1132, 1904, 2212, 2501, 2991, 3268, 3555, 4005, 5228, 5500, 5849, 6695, 7188, 7537, 7729, 9252, 9636, 242, 671, 1133, 1905, 2213, 2502, 2992, 3269, 3556, 4006, 5229, 5501, 5850, 6696, 7189, 7538, 7730, 9253, 9637, 243, 672, 1134, 1906, 2214, 2503, 2993, 3270, 3557, 4007, 5230, 5502, 5851, 6697, 7190, 7539, 7731, 9254, 9638, 244, 673, 1135, 1907, 2215, 2504, 2994, 3271, 3558, 4008, 5231, 5503, 5852, 6698, 7191, 7540, 7732, 9255, 9639, 245, 674, 1136, 1908, 2216, 2505, 2995, 3272, 3559, 4009, 5232, 5504, 5853, 6699, 7192, 7541, 7733, 9256, 9640, 246, 675, 1137, 1909, 2217, 2506, 2996, 3273, 3560, 4010, 5233, 5505, 5854, 6700, 7193, 7542, 7734, 9257, 9641, 247, 676, 1138, 1910, 2218, 2507, 2997, 3274, 3561, 4011, 5234, 5506, 5855, 6701, 7194, 7543, 7735, 9258, 9642, 248, 677, 1139, 1911, 2219, 2508, 2998, 3275, 3562, 4012, 5235, 5507, 5856, 6702, 7195, 7544, 7736, 9259, 9643, 249, 678, 1140, 1912, 2220, 2509, 2999, 3276, 3563, 4013, 5236, 5508, 5857, 6703, 7196, 7545, 7737, 9260, 9644, 250, 679, 1141, 1913, 2221, 2510, 3000, 3277, 3564, 4014, 5237, 5509, 5858, 6704, 7197, 7546, 7738, 9261, 9645, 251, 680, 1142, 1914, 2222, 2511, 3001, 3278, 3565, 4015, 5238, 5510, 5859, 6705, 7198, 7547, 7739, 9262, 9646, 252, 681, 1143, 1915, 2223, 2512, 3002, 3279, 3566, 4016, 5239, 5511, 5860, 6706, 7199, 7548, 7740, 9263, 9647, 253, 682, 1144, 1916, 2224, 2513, 3003, 3280, 3567, 4017, 5240, 5512, 5861, 6707, 7200, 7549, 7741, 9264, 9648, 254, 683, 1145, 1917, 2225, 2514, 3004, 3281, 3568, 4018, 5241, 5513, 5862, 6708, 7201, 7550, 7742, 9265, 9649, 255, 684, 1146, 1918, 2226, 2515, 3005, 3282, 3569, 4019, 5242, 5514, 5863, 6709, 7202, 7551, 7743, 9266, 9650, 256, 685, 1147, 1919, 2227, 2516, 3006, 3283, 3570, 4020, 5243, 5515, 5864, 6710, 7203, 7552, 7744, 9267, 9651, 257, 686, 1148, 1536, 2228, 2517, 3007, 3284, 3571, 4021, 5244, 5516, 5865, 6711, 7204, 7553, 7745, 9268, 9652, 258, 687, 1149, 1537, 2229, 2518, 3008, 3285, 3572, 4022, 5245, 5517, 5866, 6712, 7205, 7554, 7746, 9269, 9653, 259, 688, 1150, 1538, 2230, 2519, 3009, 3286, 3573, 4023, 5246, 5518, 5867, 6713, 7206, 7555, 7747, 9270, 9654, 260, 689, 1151, 1539, 2231, 2520, 3010, 3287, 3574, 4024, 5247, 5519, 5868, 6714, 7207, 7556, 7748, 9271, 9655, 261, 690, 768, 1540, 2232, 2521, 3011, 3288, 3575, 4025, 5248, 5520, 5869, 6715, 7208, 7557, 7749, 9272, 9656, 262, 691, 769, 1541, 2233, 2522, 3012, 3289, 3576, 4026, 5249, 5521, 5870, 6716, 7209, 7558, 7750, 9273, 9657, 263, 692, 770, 1542, 2234, 2523, 3013, 3290, 3577, 4027, 5250, 5522, 5871, 6717, 7210, 7559, 7751, 9274, 9658, 264, 693, 771, 1543, 2235, 2524, 3014, 3291, 3578, 4028, 5251, 5523, 5872, 6718, 7211, 7560, 7752, 9275, 9659, 265, 694, 772, 1544, 2236, 2525, 3015, 3292, 3579, 4029, 5252, 5524, 5873, 6719, 7212, 7561, 7753, 9276, 9660, 266, 695, 773, 1545, 2237, 2526, 3016, 3293, 3580, 4030, 5253, 5525, 5874, 6720, 7213, 7562, 7754, 9277, 9661, 267, 696, 774, 1546, 2238, 2527, 3017, 3294, 3581, 4031, 5254, 5526, 5875, 6721, 7214, 7563, 7755, 9278, 9662, 268, 697, 775, 1547, 2239, 2528, 3018, 3295, 3582, 4032, 5255, 5527, 5876, 6722, 7215, 7564, 7756, 9279, 9663, 269, 698, 776, 1548, 2240, 2529, 3019, 3296, 3583, 4033, 5256, 5528, 5877, 6723, 7216, 7565, 7757, 9280, 9664, 270, 699, 777, 1549, 2241, 2530, 3020, 3297, 3584, 4034, 5257, 5529, 5878, 6724, 7217, 7566, 7758, 9281, 9665, 271, 700, 778, 1550, 2242, 2531, 3021, 3298, 3585, 4035, 5258, 5530, 5879, 6725, 7218, 7567, 7759, 9282, 9666, 272, 701, 779, 1551, 2243, 2532, 3022, 3299, 3586, 4036, 5259, 5531, 5880, 6726, 7219, 7568, 7760, 9283, 9667, 273, 702, 780, 1552, 2244, 2533, 3023, 3300, 3587, 4037, 5260, 5532, 5881, 6727, 7220, 7569, 7761, 9284, 9668, 274, 703, 781, 1553, 2245, 2534, 3024, 3301, 3588, 4038, 5261, 5533, 5882, 6728, 7221, 7570, 7762, 9285, 9669, 275, 704, 782, 1554, 2246, 2535, 3025, 3302, 3589, 4039, 5262, 5534, 5883, 6729, 7222, 7571, 7763, 9286, 9670, 276, 705, 783, 1555, 2247, 2536, 3026, 3303, 3590, 4040, 5263, 5535, 5884, 6730, 7223, 7572, 7764, 9287, 9671, 277, 706, 784, 1556, 2248, 2537, 3027, 3304, 3591, 4041, 5264, 5536, 5885, 6731, 7224, 7573, 7765, 9288, 9672, 278, 707, 785, 1557, 2249, 2538, 3028, 3305, 3592, 4042, 5265, 5537, 5886, 6732, 7225, 7574, 7766, 9289, 9673, 279, 708, 786, 1558, 2250, 2539, 3029, 3306, 3593, 4043, 5266, 5538, 5887, 6733, 7226, 7575, 7767, 9290, 9674, 280, 709, 787, 1559, 2251, 2540, 3030, 3307, 3594, 4044, 5267, 5539, 5888, 6734, 7227, 7576, 7768, 9291, 9675, 281, 710, 788, 1560, 2252, 2541, 3031, 3308, 3595, 4045, 5268, 5540, 5889, 6735, 7228, 7577, 7769, 9292, 9676, 282, 711, 789, 1561, 2253, 2542, 3032, 3309, 3596, 4046, 5269, 5541, 5890, 6736, 7229, 7578, 7770, 9293, 9677, 283, 712, 790, 1562, 2254, 2543, 3033, 3310, 3597, 4047, 5270, 5542, 5891, 6737, 7230, 7579, 7771, 9294, 9678, 284, 713, 791, 1563, 2255, 2544, 3034, 3311, 3598, 4048, 5271, 5543, 5892, 6738, 7231, 7580, 7772, 9295, 9679, 285, 714, 792, 1564, 2256, 2545, 3035, 3312, 3599, 4049, 5272, 5544, 5893, 6739, 7232, 7581, 7773, 9296, 9680, 286, 715, 793, 1565, 2257, 2546, 3036, 3313, 3600, 4050, 5273, 5545, 5894, 6740, 7233, 7582, 7774, 9297, 9681, 287, 716, 794, 1566, 2258, 2547, 3037, 3314, 3601, 4051, 5274, 5546, 5895, 6741, 7234, 7583, 7775, 9298, 9682, 288, 717, 795, 1567, 2259, 2548, 3038, 3315, 3602, 4052, 5275, 5547, 5896, 6742, 7235, 7584, 7776, 9299, 9683, 289, 718, 796, 1568, 2260, 2549, 3039, 3316, 3603, 4053, 5276, 5548, 5897, 6743, 7236, 7585, 7777, 9300, 9684, 290, 719, 797, 1569, 2261, 2550, 3040, 3317, 3604, 4054, 5277, 5549, 5898, 6744, 7237, 7586, 7778, 9301, 9685, 291, 720, 798, 1570, 2262, 2551, 3041, 3318, 3605, 4055, 5278, 5550, 5899, 6745, 7238, 7587, 7779, 9302, 9686, 292, 721, 799, 1571, 2263, 2552, 3042, 3319, 3606, 4056, 5279, 5551, 5900, 6746, 7239, 7588, 7780, 9303, 9687, 293, 722, 800, 1572, 2264, 2553, 3043, 3320, 3607, 4057, 5280, 5552, 5901, 6747, 7240, 7589, 7781, 9304, 9688, 294, 723, 801, 1573, 2265, 2554, 3044, 3321, 3608, 4058, 5281, 5553, 5902, 6748, 7241, 7590, 7782, 9305, 9689, 295, 724, 802, 1574, 2266, 2555, 3045, 3322, 3609, 4059, 5282, 5554, 5903, 6749, 7242, 7591, 7783, 9306, 9690, 296, 725, 803, 1575, 2267, 2556, 3046, 3323, 3610, 4060, 5283, 5555, 5904, 6750, 7243, 7592, 7784, 9307, 9691, 297, 726, 804, 1576, 2268, 2557, 3047, 3324, 3611, 4061, 5284, 5556, 5905, 6751, 7244, 7593, 7785, 9308, 9692, 298, 727, 805, 1577, 2269, 2558, 3048, 3325, 3612, 4062, 5285, 5557, 5906, 6752, 7245, 7594, 7786, 9309, 9693, 299, 728, 806, 1578, 2270, 2559, 3049, 3326, 3613, 4063, 5286, 5558, 5907, 6753, 7246, 7595, 7787, 9310, 9694, 300, 729, 807, 1579, 2271, 2560, 3050, 3327, 3614, 4064, 5287, 5559, 5908, 6754, 7247, 7596, 7788, 9311, 9695, 301, 730, 808, 1580, 2272, 2561, 3051, 3328, 3615, 4065, 5288, 5560, 5909, 6755, 7248, 7597, 7789, 9312, 9696, 302, 731, 809, 1581, 2273, 2562, 3052, 3329, 3616, 4066, 5289, 5561, 5910, 6756, 7249, 7598, 7790, 9313, 9697, 303, 732, 810, 1582, 2274, 2563, 3053, 3330, 3617, 4067, 5290, 5562, 5911, 6757, 7250, 7599, 7791, 9314, 9698, 304, 733, 811, 1583, 2275, 2564, 3054, 3331, 3618, 4068, 5291, 5563, 5912, 6758, 7251, 7600, 7792, 9315, 9699, 305, 734, 812, 1584, 2276, 2565, 3055, 3332, 3619, 4069, 5292, 5564, 5913, 6759, 7252, 7601, 7793, 9316, 9700, 306, 735, 813, 1585, 2277, 2566, 3056, 3333, 3620, 4070, 5293, 5565, 5914, 6760, 7253, 7602, 7794, 9317, 9701, 307, 736, 814, 1586, 2278, 2567, 3057, 3334, 3621, 4071, 5294, 5566, 5915, 6761, 7254, 7603, 7795, 9318, 9702, 308, 737, 815, 1587, 2279, 2568, 3058, 3335, 3622, 4072, 5295, 5567, 5916, 6762, 7255, 7604, 7796, 9319, 9703, 309, 738, 816, 1588, 2280, 2569, 3059, 3336, 3623, 4073, 5296, 5568, 5917, 6763, 7256, 7605, 7797, 9320, 9704, 310, 739, 817, 1589, 2281, 2570, 3060, 3337, 3624, 4074, 5297, 5569, 5918, 6764, 7257, 7606, 7798, 9321, 9705, 311, 740, 818, 1590, 2282, 2571, 3061, 3338, 3625, 4075, 5298, 5570, 5919, 6765, 7258, 7607, 7799, 9322, 9706, 312, 741, 819, 1591, 2283, 2572, 3062, 3339, 3626, 4076, 5299, 5571, 5920, 6766, 7259, 7608, 7800, 9323, 9707, 313, 742, 820, 1592, 2284, 2573, 3063, 3340, 3627, 4077, 5300, 5572, 5921, 6767, 7260, 7609, 7801, 9324, 9708, 314, 743, 821, 1593, 2285, 2574, 3064, 3341, 3628, 4078, 5301, 5573, 5922, 6768, 7261, 7610, 7802, 9325, 9709, 315, 744, 822, 1594, 2286, 2575, 3065, 3342, 3629, 4079, 5302, 5574, 5923, 6769, 7262, 7611, 7803, 9326, 9710, 316, 745, 823, 1595, 2287, 2576, 3066, 3343, 3630, 4080, 5303, 5575, 5924, 6770, 7263, 7612, 7804, 9327, 9711, 317, 746, 824, 1596, 2288, 2577, 3067, 3344, 3631, 4081, 5304, 5576, 5925, 6771, 7264, 7613, 7805, 9328, 9712, 318, 747, 825, 1597, 2289, 2578, 3068, 3345, 3632, 4082, 5305, 5577, 5926, 6772, 7265, 7614, 7806, 9329, 9713, 319, 748, 826, 1598, 2290, 2579, 3069, 3346, 3633, 4083, 5306, 5578, 5927, 6773, 7266, 7615, 7807, 9330, 9714, 320, 749, 827, 1599, 2291, 2580, 3070, 3347, 3634, 4084, 5307, 5579, 5928, 6774, 7267, 7616, 7808, 9331, 9715, 321, 750, 828, 1600, 2292, 2581, 3071, 3348, 3635, 4085, 5308, 5580, 5929, 6775, 7268, 7617, 7809, 9332, 9716, 322, 751, 829, 1601, 2293, 2582, 2688, 3349, 3636, 4086, 5309, 5581, 5930, 6776, 7269, 7618, 7810, 9333, 9717, 323, 752, 830, 1602, 2294, 2583, 2689, 3350, 3637, 4087, 5310, 5582, 5931, 6777, 7270, 7619, 7811, 9334, 9718, 324, 753, 831, 1603, 2295, 2584, 2690, 3351, 3638, 4088, 5311, 5583, 5932, 6778, 7271, 7620, 7812, 9335, 9719, 325, 754, 832, 1604, 2296, 2585, 2691, 3352, 3639, 4089, 5312, 5584, 5933, 6779, 7272, 7621, 7813, 9336, 9720, 326, 755, 833, 1605, 2297, 2586, 2692, 3353, 3640, 4090, 5313, 5585, 5934, 6780, 7273, 7622, 7814, 9337, 9721, 327, 756, 834, 1606, 2298, 2587, 2693, 3354, 3641, 4091, 5314, 5586, 5935, 6781, 7274, 7623, 7815, 9338, 9722, 328, 757, 835, 1607, 2299, 2588, 2694, 3355, 3642, 4092, 5315, 5587, 5936, 6782, 7275, 7624, 7816, 9339, 9723, 329, 758, 836, 1608, 2300, 2589, 2695, 3356, 3643, 4093, 5316, 5588, 5937, 6783, 7276, 7625, 7817, 9340, 9724, 330, 759, 837, 1609, 2301, 2590, 2696, 3357, 3644, 4094, 5317, 5589, 5938, 6784, 7277, 7626, 7818, 9341, 9725, 331, 760, 838, 1610, 2302, 2591, 2697, 3358, 3645, 4095, 5318, 5590, 5939, 6785, 7278, 7627, 7819, 9342, 9726, 332, 761, 839, 1611, 2303, 2592, 2698, 3359, 3646, 4096, 5319, 5591, 5940, 6786, 7279, 7628, 7820, 9343, 9727, 333, 762, 840, 1612, 1920, 2593, 2699, 3360, 3647, 4097, 5320, 5592, 5941, 6787, 7280, 7629, 7821, 9344, 9728, 334, 763, 841, 1613, 1921, 2594, 2700, 3361, 3648, 4098, 5321, 5593, 5942, 6788, 7281, 7630, 7822, 9345, 9729, 335, 764, 842, 1614, 1922, 2595, 2701, 3362, 3649, 4099, 5322, 5594, 5943, 6789, 7282, 7631, 7823, 9346, 9730, 336, 765, 843, 1615, 1923, 2596, 2702, 3363, 3650, 4100, 5323, 5595, 5944, 6790, 7283, 7632, 7824, 9347, 9731, 337, 766, 844, 1616, 1924, 2597, 2703, 3364, 3651, 4101, 5324, 5596, 5945, 6791, 7284, 7633, 7825, 9348, 9732, 338, 767, 845, 1617, 1925, 2598, 2704, 3365, 3652, 4102, 5325, 5597, 5946, 6792, 7285, 7634, 7826, 9349, 9733, 339, 384, 846, 1618, 1926, 2599, 2705, 3366, 3653, 4103, 5326, 5598, 5947, 6793, 7286, 7635, 7827, 9350, 9734, 340, 385, 847, 1619, 1927, 2600, 2706, 3367, 3654, 4104, 5327, 5599, 5948, 6794, 7287, 7636, 7828, 9351, 9735, 341, 386, 848, 1620, 1928, 2601, 2707, 3368, 3655, 4105, 5328, 5600, 5949, 6795, 7288, 7637, 7829, 9352, 9736, 342, 387, 849, 1621, 1929, 2602, 2708, 3369, 3656, 4106, 5329, 5601, 5950, 6796, 7289, 7638, 7830, 9353, 9737, 343, 388, 850, 1622, 1930, 2603, 2709, 3370, 3657, 4107, 5330, 5602, 5951, 6797, 7290, 7639, 7831, 9354, 9738, 344, 389, 851, 1623, 1931, 2604, 2710, 3371, 3658, 4108, 5331, 5603, 5952, 6798, 7291, 7640, 7832, 9355, 9739, 345, 390, 852, 1624, 1932, 2605, 2711, 3372, 3659, 4109, 5332, 5604, 5953, 6799, 7292, 7641, 7833, 9356, 9740, 346, 391, 853, 1625, 1933, 2606, 2712, 3373, 3660, 4110, 5333, 5605, 5954, 6800, 7293, 7642, 7834, 9357, 9741, 347, 392, 854, 1626, 1934, 2607, 2713, 3374, 3661, 4111, 5334, 5606, 5955, 6801, 7294, 7643, 7835, 9358, 9742, 348, 393, 855, 1627, 1935, 2608, 2714, 3375, 3662, 4112, 5335, 5607, 5956, 6802, 7295, 7644, 7836, 9359, 9743, 349, 394, 856, 1628, 1936, 2609, 2715, 3376, 3663, 4113, 5336, 5608, 5957, 6803, 6912, 7645, 7837, 9360, 9744, 350, 395, 857, 1629, 1937, 2610, 2716, 3377, 3664, 4114, 5337, 5609, 5958, 6804, 6913, 7646, 7838, 9361, 9745, 351, 396, 858, 1630, 1938, 2611, 2717, 3378, 3665, 4115, 5338, 5610, 5959, 6805, 6914, 7647, 7839, 9362, 9746, 352, 397, 859, 1631, 1939, 2612, 2718, 3379, 3666, 4116, 5339, 5611, 5960, 6806, 6915, 7648, 7840, 9363, 9747, 353, 398, 860, 1632, 1940, 2613, 2719, 3380, 3667, 4117, 5340, 5612, 5961, 6807, 6916, 7649, 7841, 9364, 9748, 354, 399, 861, 1633, 1941, 2614, 2720, 3381, 3668, 4118, 5341, 5613, 5962, 6808, 6917, 7650, 7842, 9365, 9749, 355, 400, 862, 1634, 1942, 2615, 2721, 3382, 3669, 4119, 5342, 5614, 5963, 6809, 6918, 7651, 7843, 9366, 9750, 356, 401, 863, 1635, 1943, 2616, 2722, 3383, 3670, 4120, 5343, 5615, 5964, 6810, 6919, 7652, 7844, 9367, 9751, 357, 402, 864, 1636, 1944, 2617, 2723, 3384, 3671, 4121, 5344, 5616, 5965, 6811, 6920, 7653, 7845, 9368, 9752, 358, 403, 865, 1637, 1945, 2618, 2724, 3385, 3672, 4122, 5345, 5617, 5966, 6812, 6921, 7654, 7846, 9369, 9753, 359, 404, 866, 1638, 1946, 2619, 2725, 3386, 3673, 4123, 5346, 5618, 5967, 6813, 6922, 7655, 7847, 9370, 9754, 360, 405, 867, 1639, 1947, 2620, 2726, 3387, 3674, 4124, 5347, 5619, 5968, 6814, 6923, 7656, 7848, 9371, 9755, 361, 406, 868, 1640, 1948, 2621, 2727, 3388, 3675, 4125, 5348, 5620, 5969, 6815, 6924, 7657, 7849, 9372, 9756, 362, 407, 869, 1641, 1949, 2622, 2728, 3389, 3676, 4126, 5349, 5621, 5970, 6816, 6925, 7658, 7850, 9373, 9757, 363, 408, 870, 1642, 1950, 2623, 2729, 3390, 3677, 4127, 5350, 5622, 5971, 6817, 6926, 7659, 7851, 9374, 9758, 364, 409, 871, 1643, 1951, 2624, 2730, 3391, 3678, 4128, 5351, 5623, 5972, 6818, 6927, 7660, 7852, 9375, 9759, 365, 410, 872, 1644, 1952, 2625, 2731, 3392, 3679, 4129, 5352, 5624, 5973, 6819, 6928, 7661, 7853, 9376, 9760, 366, 411, 873, 1645, 1953, 2626, 2732, 3393, 3680, 4130, 5353, 5625, 5974, 6820, 6929, 7662, 7854, 9377, 9761, 367, 412, 874, 1646, 1954, 2627, 2733, 3394, 3681, 4131, 5354, 5626, 5975, 6821, 6930, 7663, 7855, 9378, 9762, 368, 413, 875, 1647, 1955, 2628, 2734, 3395, 3682, 4132, 5355, 5627, 5976, 6822, 6931, 7664, 7856, 9379, 9763, 369, 414, 876, 1648, 1956, 2629, 2735, 3396, 3683, 4133, 5356, 5628, 5977, 6823, 6932, 7665, 7857, 9380, 9764, 370, 415, 877, 1649, 1957, 2630, 2736, 3397, 3684, 4134, 5357, 5629, 5978, 6824, 6933, 7666, 7858, 9381, 9765, 371, 416, 878, 1650, 1958, 2631, 2737, 3398, 3685, 4135, 5358, 5630, 5979, 6825, 6934, 7667, 7859, 9382, 9766, 372, 417, 879, 1651, 1959, 2632, 2738, 3399, 3686, 4136, 5359, 5631, 5980, 6826, 6935, 7668, 7860, 9383, 9767, 373, 418, 880, 1652, 1960, 2633, 2739, 3400, 3687, 4137, 5360, 5632, 5981, 6827, 6936, 7669, 7861, 9384, 9768, 374, 419, 881, 1653, 1961, 2634, 2740, 3401, 3688, 4138, 5361, 5633, 5982, 6828, 6937, 7670, 7862, 9385, 9769, 375, 420, 882, 1654, 1962, 2635, 2741, 3402, 3689, 4139, 5362, 5634, 5983, 6829, 6938, 7671, 7863, 9386, 9770, 376, 421, 883, 1655, 1963, 2636, 2742, 3403, 3690, 4140, 5363, 5635, 5984, 6830, 6939, 7672, 7864, 9387, 9771, 377, 422, 884, 1656, 1964, 2637, 2743, 3404, 3691, 4141, 5364, 5636, 5985, 6831, 6940, 7673, 7865, 9388, 9772, 378, 423, 885, 1657, 1965, 2638, 2744, 3405, 3692, 4142, 5365, 5637, 5986, 6832, 6941, 7674, 7866, 9389, 9773, 379, 424, 886, 1658, 1966, 2639, 2745, 3406, 3693, 4143, 5366, 5638, 5987, 6833, 6942, 7675, 7867, 9390, 9774, 380, 425, 887, 1659, 1967, 2640, 2746, 3407, 3694, 4144, 5367, 5639, 5988, 6834, 6943, 7676, 7868, 9391, 9775, 381, 426, 888, 1660, 1968, 2641, 2747, 3408, 3695, 4145, 5368, 5640, 5989, 6835, 6944, 7677, 7869, 9392, 9776, 382, 427, 889, 1661, 1969, 2642, 2748, 3409, 3696, 4146, 5369, 5641, 5990, 6836, 6945, 7678, 7870, 9393, 9777, 383, 428, 890, 1662, 1970, 2643, 2749, 3410, 3697, 4147, 5370, 5642, 5991, 6837, 6946, 7679, 7871, 9394, 9778, 0, 429, 891, 1663, 1971, 2644, 2750, 3411, 3698, 4148, 5371, 5643, 5992, 6838, 6947, 7296, 7872, 9395, 9779, 1, 430, 892, 1664, 1972, 2645, 2751, 3412, 3699, 4149, 5372, 5644, 5993, 6839, 6948, 7297, 7873, 9396, 9780, 2, 431, 893, 1665, 1973, 2646, 2752, 3413, 3700, 4150, 5373, 5645, 5994, 6840, 6949, 7298, 7874, 9397, 9781, 3, 432, 894, 1666, 1974, 2647, 2753, 3414, 3701, 4151, 5374, 5646, 5995, 6841, 6950, 7299, 7875, 9398, 9782, 4, 433, 895, 1667, 1975, 2648, 2754, 3415, 3702, 4152, 5375, 5647, 5996, 6842, 6951, 7300, 7876, 9399, 9783, 5, 434, 896, 1668, 1976, 2649, 2755, 3416, 3703, 4153, 4992, 5648, 5997, 6843, 6952, 7301, 7877, 9400, 9784, 6, 435, 897, 1669, 1977, 2650, 2756, 3417, 3704, 4154, 4993, 5649, 5998, 6844, 6953, 7302, 7878, 9401, 9785, 7, 436, 898, 1670, 1978, 2651, 2757, 3418, 3705, 4155, 4994, 5650, 5999, 6845, 6954, 7303, 7879, 9402, 9786, 8, 437, 899, 1671, 1979, 2652, 2758, 3419, 3706, 4156, 4995, 5651, 6000, 6846, 6955, 7304, 7880, 9403, 9787, 9, 438, 900, 1672, 1980, 2653, 2759, 3420, 3707, 4157, 4996, 5652, 6001, 6847, 6956, 7305, 7881, 9404, 9788, 10, 439, 901, 1673, 1981, 2654, 2760, 3421, 3708, 4158, 4997, 5653, 6002, 6848, 6957, 7306, 7882, 9405, 9789, 11, 440, 902, 1674, 1982, 2655, 2761, 3422, 3709, 4159, 4998, 5654, 6003, 6849, 6958, 7307, 7883, 9406, 9790, 12, 441, 903, 1675, 1983, 2656, 2762, 3423, 3710, 4160, 4999, 5655, 6004, 6850, 6959, 7308, 7884, 9407, 9791, 13, 442, 904, 1676, 1984, 2657, 2763, 3424, 3711, 4161, 5000, 5656, 6005, 6851, 6960, 7309, 7885, 9408, 9792, 14, 443, 905, 1677, 1985, 2658, 2764, 3425, 3712, 4162, 5001, 5657, 6006, 6852, 6961, 7310, 7886, 9409, 9793, 15, 444, 906, 1678, 1986, 2659, 2765, 3426, 3713, 4163, 5002, 5658, 6007, 6853, 6962, 7311, 7887, 9410, 9794, 16, 445, 907, 1679, 1987, 2660, 2766, 3427, 3714, 4164, 5003, 5659, 6008, 6854, 6963, 7312, 7888, 9411, 9795, 17, 446, 908, 1680, 1988, 2661, 2767, 3428, 3715, 4165, 5004, 5660, 6009, 6855, 6964, 7313, 7889, 9412, 9796, 18, 447, 909, 1681, 1989, 2662, 2768, 3429, 3716, 4166, 5005, 5661, 6010, 6856, 6965, 7314, 7890, 9413, 9797, 19, 448, 910, 1682, 1990, 2663, 2769, 3430, 3717, 4167, 5006, 5662, 6011, 6857, 6966, 7315, 7891, 9414, 9798, 20, 449, 911, 1683, 1991, 2664, 2770, 3431, 3718, 4168, 5007, 5663, 6012, 6858, 6967, 7316, 7892, 9415, 9799, 21, 450, 912, 1684, 1992, 2665, 2771, 3432, 3719, 4169, 5008, 5664, 6013, 6859, 6968, 7317, 7893, 9416, 9800, 22, 451, 913, 1685, 1993, 2666, 2772, 3433, 3720, 4170, 5009, 5665, 6014, 6860, 6969, 7318, 7894, 9417, 9801, 23, 452, 914, 1686, 1994, 2667, 2773, 3434, 3721, 4171, 5010, 5666, 6015, 6861, 6970, 7319, 7895, 9418, 9802, 24, 453, 915, 1687, 1995, 2668, 2774, 3435, 3722, 4172, 5011, 5667, 6016, 6862, 6971, 7320, 7896, 9419, 9803, 25, 454, 916, 1688, 1996, 2669, 2775, 3436, 3723, 4173, 5012, 5668, 6017, 6863, 6972, 7321, 7897, 9420, 9804, 26, 455, 917, 1689, 1997, 2670, 2776, 3437, 3724, 4174, 5013, 5669, 6018, 6864, 6973, 7322, 7898, 9421, 9805, 27, 456, 918, 1690, 1998, 2671, 2777, 3438, 3725, 4175, 5014, 5670, 6019, 6865, 6974, 7323, 7899, 9422, 9806, 28, 457, 919, 1691, 1999, 2672, 2778, 3439, 3726, 4176, 5015, 5671, 6020, 6866, 6975, 7324, 7900, 9423, 9807, 29, 458, 920, 1692, 2000, 2673, 2779, 3440, 3727, 4177, 5016, 5672, 6021, 6867, 6976, 7325, 7901, 9424, 9808, 30, 459, 921, 1693, 2001, 2674, 2780, 3441, 3728, 4178, 5017, 5673, 6022, 6868, 6977, 7326, 7902, 9425, 9809, 31, 460, 922, 1694, 2002, 2675, 2781, 3442, 3729, 4179, 5018, 5674, 6023, 6869, 6978, 7327, 7903, 9426, 9810, 32, 461, 923, 1695, 2003, 2676, 2782, 3443, 3730, 4180, 5019, 5675, 6024, 6870, 6979, 7328, 7904, 9427, 9811, 33, 462, 924, 1696, 2004, 2677, 2783, 3444, 3731, 4181, 5020, 5676, 6025, 6871, 6980, 7329, 7905, 9428, 9812, 34, 463, 925, 1697, 2005, 2678, 2784, 3445, 3732, 4182, 5021, 5677, 6026, 6872, 6981, 7330, 7906, 9429, 9813, 35, 464, 926, 1698, 2006, 2679, 2785, 3446, 3733, 4183, 5022, 5678, 6027, 6873, 6982, 7331, 7907, 9430, 9814, 36, 465, 927, 1699, 2007, 2680, 2786, 3447, 3734, 4184, 5023, 5679, 6028, 6874, 6983, 7332, 7908, 9431, 9815, 37, 466, 928, 1700, 2008, 2681, 2787, 3448, 3735, 4185, 5024, 5680, 6029, 6875, 6984, 7333, 7909, 9432, 9816, 38, 467, 929, 1701, 2009, 2682, 2788, 3449, 3736, 4186, 5025, 5681, 6030, 6876, 6985, 7334, 7910, 9433, 9817, 39, 468, 930, 1702, 2010, 2683, 2789, 3450, 3737, 4187, 5026, 5682, 6031, 6877, 6986, 7335, 7911, 9434, 9818, 40, 469, 931, 1703, 2011, 2684, 2790, 3451, 3738, 4188, 5027, 5683, 6032, 6878, 6987, 7336, 7912, 9435, 9819, 41, 470, 932, 1704, 2012, 2685, 2791, 3452, 3739, 4189, 5028, 5684, 6033, 6879, 6988, 7337, 7913, 9436, 9820, 42, 471, 933, 1705, 2013, 2686, 2792, 3453, 3740, 4190, 5029, 5685, 6034, 6880, 6989, 7338, 7914, 9437, 9821, 43, 472, 934, 1706, 2014, 2687, 2793, 3454, 3741, 4191, 5030, 5686, 6035, 6881, 6990, 7339, 7915, 9438, 9822, 44, 473, 935, 1707, 2015, 2304, 2794, 3455, 3742, 4192, 5031, 5687, 6036, 6882, 6991, 7340, 7916, 9439, 9823, 45, 474, 936, 1708, 2016, 2305, 2795, 3072, 3743, 4193, 5032, 5688, 6037, 6883, 6992, 7341, 7917, 9440, 9824, 46, 475, 937, 1709, 2017, 2306, 2796, 3073, 3744, 4194, 5033, 5689, 6038, 6884, 6993, 7342, 7918, 9441, 9825, 47, 476, 938, 1710, 2018, 2307, 2797, 3074, 3745, 4195, 5034, 5690, 6039, 6885, 6994, 7343, 7919, 9442, 9826, 48, 477, 939, 1711, 2019, 2308, 2798, 3075, 3746, 4196, 5035, 5691, 6040, 6886, 6995, 7344, 7920, 9443, 9827, 49, 478, 940, 1712, 2020, 2309, 2799, 3076, 3747, 4197, 5036, 5692, 6041, 6887, 6996, 7345, 7921, 9444, 9828, 50, 479, 941, 1713, 2021, 2310, 2800, 3077, 3748, 4198, 5037, 5693, 6042, 6888, 6997, 7346, 7922, 9445, 9829, 51, 480, 942, 1714, 2022, 2311, 2801, 3078, 3749, 4199, 5038, 5694, 6043, 6889, 6998, 7347, 7923, 9446, 9830, 52, 481, 943, 1715, 2023, 2312, 2802, 3079, 3750, 4200, 5039, 5695, 6044, 6890, 6999, 7348, 7924, 9447, 9831, 53, 482, 944, 1716, 2024, 2313, 2803, 3080, 3751, 4201, 5040, 5696, 6045, 6891, 7000, 7349, 7925, 9448, 9832, 54, 483, 945, 1717, 2025, 2314, 2804, 3081, 3752, 4202, 5041, 5697, 6046, 6892, 7001, 7350, 7926, 9449, 9833, 55, 484, 946, 1718, 2026, 2315, 2805, 3082, 3753, 4203, 5042, 5698, 6047, 6893, 7002, 7351, 7927, 9450, 9834, 56, 485, 947, 1719, 2027, 2316, 2806, 3083, 3754, 4204, 5043, 5699, 6048, 6894, 7003, 7352, 7928, 9451, 9835, 57, 486, 948, 1720, 2028, 2317, 2807, 3084, 3755, 4205, 5044, 5700, 6049, 6895, 7004, 7353, 7929, 9452, 9836, 58, 487, 949, 1721, 2029, 2318, 2808, 3085, 3756, 4206, 5045, 5701, 6050, 6896, 7005, 7354, 7930, 9453, 9837, 59, 488, 950, 1722, 2030, 2319, 2809, 3086, 3757, 4207, 5046, 5702, 6051, 6897, 7006, 7355, 7931, 9454, 9838, 60, 489, 951, 1723, 2031, 2320, 2810, 3087, 3758, 4208, 5047, 5703, 6052, 6898, 7007, 7356, 7932, 9455, 9839, 61, 490, 952, 1724, 2032, 2321, 2811, 3088, 3759, 4209, 5048, 5704, 6053, 6899, 7008, 7357, 7933, 9456, 9840, 62, 491, 953, 1725, 2033, 2322, 2812, 3089, 3760, 4210, 5049, 5705, 6054, 6900, 7009, 7358, 7934, 9457, 9841, 63, 492, 954, 1726, 2034, 2323, 2813, 3090, 3761, 4211, 5050, 5706, 6055, 6901, 7010, 7359, 7935, 9458, 9842, 64, 493, 955, 1727, 2035, 2324, 2814, 3091, 3762, 4212, 5051, 5707, 6056, 6902, 7011, 7360, 7936, 9459, 9843, 65, 494, 956, 1728, 2036, 2325, 2815, 3092, 3763, 4213, 5052, 5708, 6057, 6903, 7012, 7361, 7937, 9460, 9844, 66, 495, 957, 1729, 2037, 2326, 2816, 3093, 3764, 4214, 5053, 5709, 6058, 6904, 7013, 7362, 7938, 9461, 9845, 67, 496, 958, 1730, 2038, 2327, 2817, 3094, 3765, 4215, 5054, 5710, 6059, 6905, 7014, 7363, 7939, 9462, 9846, 68, 497, 959, 1731, 2039, 2328, 2818, 3095, 3766, 4216, 5055, 5711, 6060, 6906, 7015, 7364, 7940, 9463, 9847, 69, 498, 960, 1732, 2040, 2329, 2819, 3096, 3767, 4217, 5056, 5712, 6061, 6907, 7016, 7365, 7941, 9464, 9848, 70, 499, 961, 1733, 2041, 2330, 2820, 3097, 3768, 4218, 5057, 5713, 6062, 6908, 7017, 7366, 7942, 9465, 9849, 71, 500, 962, 1734, 2042, 2331, 2821, 3098, 3769, 4219, 5058, 5714, 6063, 6909, 7018, 7367, 7943, 9466, 9850, 72, 501, 963, 1735, 2043, 2332, 2822, 3099, 3770, 4220, 5059, 5715, 6064, 6910, 7019, 7368, 7944, 9467, 9851, 73, 502, 964, 1736, 2044, 2333, 2823, 3100, 3771, 4221, 5060, 5716, 6065, 6911, 7020, 7369, 7945, 9468, 9852, 74, 503, 965, 1737, 2045, 2334, 2824, 3101, 3772, 4222, 5061, 5717, 6066, 6528, 7021, 7370, 7946, 9469, 9853, 75, 504, 966, 1738, 2046, 2335, 2825, 3102, 3773, 4223, 5062, 5718, 6067, 6529, 7022, 7371, 7947, 9470, 9854, 76, 505, 967, 1739, 2047, 2336, 2826, 3103, 3774, 3840, 5063, 5719, 6068, 6530, 7023, 7372, 7948, 9471, 9855, 77, 506, 968, 1740, 2048, 2337, 2827, 3104, 3775, 3841, 5064, 5720, 6069, 6531, 7024, 7373, 7949, 9472, 9856, 78, 507, 969, 1741, 2049, 2338, 2828, 3105, 3776, 3842, 5065, 5721, 6070, 6532, 7025, 7374, 7950, 9473, 9857, 79, 508, 970, 1742, 2050, 2339, 2829, 3106, 3777, 3843, 5066, 5722, 6071, 6533, 7026, 7375, 7951, 9474, 9858, 80, 509, 971, 1743, 2051, 2340, 2830, 3107, 3778, 3844, 5067, 5723, 6072, 6534, 7027, 7376, 7952, 9475, 9859, 81, 510, 972, 1744, 2052, 2341, 2831, 3108, 3779, 3845, 5068, 5724, 6073, 6535, 7028, 7377, 7953, 9476, 9860, 82, 511, 973, 1745, 2053, 2342, 2832, 3109, 3780, 3846, 5069, 5725, 6074, 6536, 7029, 7378, 7954, 9477, 9861, 83, 512, 974, 1746, 2054, 2343, 2833, 3110, 3781, 3847, 5070, 5726, 6075, 6537, 7030, 7379, 7955, 9478, 9862, 84, 513, 975, 1747, 2055, 2344, 2834, 3111, 3782, 3848, 5071, 5727, 6076, 6538, 7031, 7380, 7956, 9479, 9863, 85, 514, 976, 1748, 2056, 2345, 2835, 3112, 3783, 3849, 5072, 5728, 6077, 6539, 7032, 7381, 7957, 9480, 9864, 86, 515, 977, 1749, 2057, 2346, 2836, 3113, 3784, 3850, 5073, 5729, 6078, 6540, 7033, 7382, 7958, 9481, 9865, 87, 516, 978, 1750, 2058, 2347, 2837, 3114, 3785, 3851, 5074, 5730, 6079, 6541, 7034, 7383, 7959, 9482, 9866, 88, 517, 979, 1751, 2059, 2348, 2838, 3115, 3786, 3852, 5075, 5731, 6080, 6542, 7035, 7384, 7960, 9483, 9867, 89, 518, 980, 1752, 2060, 2349, 2839, 3116, 3787, 3853, 5076, 5732, 6081, 6543, 7036, 7385, 7961, 9484, 9868, 90, 519, 981, 1753, 2061, 2350, 2840, 3117, 3788, 3854, 5077, 5733, 6082, 6544, 7037, 7386, 7962, 9485, 9869, 91, 520, 982, 1754, 2062, 2351, 2841, 3118, 3789, 3855, 5078, 5734, 6083, 6545, 7038, 7387, 7963, 9486, 9870, 92, 521, 983, 1755, 2063, 2352, 2842, 3119, 3790, 3856, 5079, 5735, 6084, 6546, 7039, 7388, 7964, 9487, 9871, 93, 522, 984, 1756, 2064, 2353, 2843, 3120, 3791, 3857, 5080, 5736, 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3985, 4542, 4852, 5346, 5601, 6461, 6841, 7196, 7732, 8434, 8462, 9613, 290, 485, 1166, 1825, 2517, 2855, 3142, 3986, 4543, 4853, 5347, 5602, 6462, 6842, 7197, 7733, 8435, 8463, 9614, 291, 486, 1167, 1826, 2518, 2856, 3143, 3987, 4544, 4854, 5348, 5603, 6463, 6843, 7198, 7734, 8436, 8464, 9615, 292, 487, 1168, 1827, 2519, 2857, 3144, 3988, 4545, 4855, 5349, 5604, 6464, 6844, 7199, 7735, 8437, 8465, 9616, 293, 488, 1169, 1828, 2520, 2858, 3145, 3989, 4546, 4856, 5350, 5605, 6465, 6845, 7200, 7736, 8438, 8466, 9617, 294, 489, 1170, 1829, 2521, 2859, 3146, 3990, 4547, 4857, 5351, 5606, 6466, 6846, 7201, 7737, 8439, 8467, 9618, 295, 490, 1171, 1830, 2522, 2860, 3147, 3991, 4548, 4858, 5352, 5607, 6467, 6847, 7202, 7738, 8440, 8468, 9619, 296, 491, 1172, 1831, 2523, 2861, 3148, 3992, 4549, 4859, 5353, 5608, 6468, 6848, 7203, 7739, 8441, 8469, 9620, 297, 492, 1173, 1832, 2524, 2862, 3149, 3993, 4550, 4860, 5354, 5609, 6469, 6849, 7204, 7740, 8442, 8470, 9621, 298, 493, 1174, 1833, 2525, 2863, 3150, 3994, 4551, 4861, 5355, 5610, 6470, 6850, 7205, 7741, 8443, 8471, 9622, 299, 494, 1175, 1834, 2526, 2864, 3151, 3995, 4552, 4862, 5356, 5611, 6471, 6851, 7206, 7742, 8444, 8472, 9623, 300, 495, 1176, 1835, 2527, 2865, 3152, 3996, 4553, 4863, 5357, 5612, 6472, 6852, 7207, 7743, 8445, 8473, 9624, 301, 496, 1177, 1836, 2528, 2866, 3153, 3997, 4554, 4864, 5358, 5613, 6473, 6853, 7208, 7744, 8446, 8474, 9625, 302, 497, 1178, 1837, 2529, 2867, 3154, 3998, 4555, 4865, 5359, 5614, 6474, 6854, 7209, 7745, 8447, 8475, 9626, 303, 498, 1179, 1838, 2530, 2868, 3155, 3999, 4556, 4866, 5360, 5615, 6475, 6855, 7210, 7746, 8064, 8476, 9627, 304, 499, 1180, 1839, 2531, 2869, 3156, 4000, 4557, 4867, 5361, 5616, 6476, 6856, 7211, 7747, 8065, 8477, 9628, 305, 500, 1181, 1840, 2532, 2870, 3157, 4001, 4558, 4868, 5362, 5617, 6477, 6857, 7212, 7748, 8066, 8478, 9629, 306, 501, 1182, 1841, 2533, 2871, 3158, 4002, 4559, 4869, 5363, 5618, 6478, 6858, 7213, 7749, 8067, 8479, 9630, 307, 502, 1183, 1842, 2534, 2872, 3159, 4003, 4560, 4870, 5364, 5619, 6479, 6859, 7214, 7750, 8068, 8480, 9631, 308, 503, 1184, 1843, 2535, 2873, 3160, 4004, 4561, 4871, 5365, 5620, 6480, 6860, 7215, 7751, 8069, 8481, 9632, 309, 504, 1185, 1844, 2536, 2874, 3161, 4005, 4562, 4872, 5366, 5621, 6481, 6861, 7216, 7752, 8070, 8482, 9633, 310, 505, 1186, 1845, 2537, 2875, 3162, 4006, 4563, 4873, 5367, 5622, 6482, 6862, 7217, 7753, 8071, 8483, 9634, 311, 506, 1187, 1846, 2538, 2876, 3163, 4007, 4564, 4874, 5368, 5623, 6483, 6863, 7218, 7754, 8072, 8484, 9635, 312, 507, 1188, 1847, 2539, 2877, 3164, 4008, 4565, 4875, 5369, 5624, 6484, 6864, 7219, 7755, 8073, 8485, 9636, 313, 508, 1189, 1848, 2540, 2878, 3165, 4009, 4566, 4876, 5370, 5625, 6485, 6865, 7220, 7756, 8074, 8486, 9637, 314, 509, 1190, 1849, 2541, 2879, 3166, 4010, 4567, 4877, 5371, 5626, 6486, 6866, 7221, 7757, 8075, 8487, 9638, 315, 510, 1191, 1850, 2542, 2880, 3167, 4011, 4568, 4878, 5372, 5627, 6487, 6867, 7222, 7758, 8076, 8488, 9639, 316, 511, 1192, 1851, 2543, 2881, 3168, 4012, 4569, 4879, 5373, 5628, 6488, 6868, 7223, 7759, 8077, 8489, 9640, 317, 512, 1193, 1852, 2544, 2882, 3169, 4013, 4570, 4880, 5374, 5629, 6489, 6869, 7224, 7760, 8078, 8490, 9641, 318, 513, 1194, 1853, 2545, 2883, 3170, 4014, 4571, 4881, 5375, 5630, 6490, 6870, 7225, 7761, 8079, 8491, 9642, 319, 514, 1195, 1854, 2546, 2884, 3171, 4015, 4572, 4882, 4992, 5631, 6491, 6871, 7226, 7762, 8080, 8492, 9643, 320, 515, 1196, 1855, 2547, 2885, 3172, 4016, 4573, 4883, 4993, 5632, 6492, 6872, 7227, 7763, 8081, 8493, 9644, 321, 516, 1197, 1856, 2548, 2886, 3173, 4017, 4574, 4884, 4994, 5633, 6493, 6873, 7228, 7764, 8082, 8494, 9645, 322, 517, 1198, 1857, 2549, 2887, 3174, 4018, 4575, 4885, 4995, 5634, 6494, 6874, 7229, 7765, 8083, 8495, 9646, 323, 518, 1199, 1858, 2550, 2888, 3175, 4019, 4576, 4886, 4996, 5635, 6495, 6875, 7230, 7766, 8084, 8496, 9647, 324, 519, 1200, 1859, 2551, 2889, 3176, 4020, 4577, 4887, 4997, 5636, 6496, 6876, 7231, 7767, 8085, 8497, 9648, 325, 520, 1201, 1860, 2552, 2890, 3177, 4021, 4578, 4888, 4998, 5637, 6497, 6877, 7232, 7768, 8086, 8498, 9649, 326, 521, 1202, 1861, 2553, 2891, 3178, 4022, 4579, 4889, 4999, 5638, 6498, 6878, 7233, 7769, 8087, 8499, 9650, 327, 522, 1203, 1862, 2554, 2892, 3179, 4023, 4580, 4890, 5000, 5639, 6499, 6879, 7234, 7770, 8088, 8500, 9651, 328, 523, 1204, 1863, 2555, 2893, 3180, 4024, 4581, 4891, 5001, 5640, 6500, 6880, 7235, 7771, 8089, 8501, 9652, 329, 524, 1205, 1864, 2556, 2894, 3181, 4025, 4582, 4892, 5002, 5641, 6501, 6881, 7236, 7772, 8090, 8502, 9653, 330, 525, 1206, 1865, 2557, 2895, 3182, 4026, 4583, 4893, 5003, 5642, 6502, 6882, 7237, 7773, 8091, 8503, 9654, 331, 526, 1207, 1866, 2558, 2896, 3183, 4027, 4584, 4894, 5004, 5643, 6503, 6883, 7238, 7774, 8092, 8504, 9655, 332, 527, 1208, 1867, 2559, 2897, 3184, 4028, 4585, 4895, 5005, 5644, 6504, 6884, 7239, 7775, 8093, 8505, 9656, 333, 528, 1209, 1868, 2560, 2898, 3185, 4029, 4586, 4896, 5006, 5645, 6505, 6885, 7240, 7776, 8094, 8506, 9657, 334, 529, 1210, 1869, 2561, 2899, 3186, 4030, 4587, 4897, 5007, 5646, 6506, 6886, 7241, 7777, 8095, 8507, 9658, 335, 530, 1211, 1870, 2562, 2900, 3187, 4031, 4588, 4898, 5008, 5647, 6507, 6887, 7242, 7778, 8096, 8508, 9659, 336, 531, 1212, 1871, 2563, 2901, 3188, 4032, 4589, 4899, 5009, 5648, 6508, 6888, 7243, 7779, 8097, 8509, 9660, 337, 532, 1213, 1872, 2564, 2902, 3189, 4033, 4590, 4900, 5010, 5649, 6509, 6889, 7244, 7780, 8098, 8510, 9661, 338, 533, 1214, 1873, 2565, 2903, 3190, 4034, 4591, 4901, 5011, 5650, 6510, 6890, 7245, 7781, 8099, 8511, 9662, 339, 534, 1215, 1874, 2566, 2904, 3191, 4035, 4592, 4902, 5012, 5651, 6511, 6891, 7246, 7782, 8100, 8512, 9663, 340, 535, 1216, 1875, 2567, 2905, 3192, 4036, 4593, 4903, 5013, 5652, 6512, 6892, 7247, 7783, 8101, 8513, 9664, 341, 536, 1217, 1876, 2568, 2906, 3193, 4037, 4594, 4904, 5014, 5653, 6513, 6893, 7248, 7784, 8102, 8514, 9665, 342, 537, 1218, 1877, 2569, 2907, 3194, 4038, 4595, 4905, 5015, 5654, 6514, 6894, 7249, 7785, 8103, 8515, 9666, 343, 538, 1219, 1878, 2570, 2908, 3195, 4039, 4596, 4906, 5016, 5655, 6515, 6895, 7250, 7786, 8104, 8516, 9667, 344, 539, 1220, 1879, 2571, 2909, 3196, 4040, 4597, 4907, 5017, 5656, 6516, 6896, 7251, 7787, 8105, 8517, 9668, 345, 540, 1221, 1880, 2572, 2910, 3197, 4041, 4598, 4908, 5018, 5657, 6517, 6897, 7252, 7788, 8106, 8518, 9669, 346, 541, 1222, 1881, 2573, 2911, 3198, 4042, 4599, 4909, 5019, 5658, 6518, 6898, 7253, 7789, 8107, 8519, 9670, 347, 542, 1223, 1882, 2574, 2912, 3199, 4043, 4600, 4910, 5020, 5659, 6519, 6899, 7254, 7790, 8108, 8520, 9671, 348, 543, 1224, 1883, 2575, 2913, 3200, 4044, 4601, 4911, 5021, 5660, 6520, 6900, 7255, 7791, 8109, 8521, 9672, 349, 544, 1225, 1884, 2576, 2914, 3201, 4045, 4602, 4912, 5022, 5661, 6521, 6901, 7256, 7792, 8110, 8522, 9673, 350, 545, 1226, 1885, 2577, 2915, 3202, 4046, 4603, 4913, 5023, 5662, 6522, 6902, 7257, 7793, 8111, 8523, 9674, 351, 546, 1227, 1886, 2578, 2916, 3203, 4047, 4604, 4914, 5024, 5663, 6523, 6903, 7258, 7794, 8112, 8524, 9675, 352, 547, 1228, 1887, 2579, 2917, 3204, 4048, 4605, 4915, 5025, 5664, 6524, 6904, 7259, 7795, 8113, 8525, 9676, 353, 548, 1229, 1888, 2580, 2918, 3205, 4049, 4606, 4916, 5026, 5665, 6525, 6905, 7260, 7796, 8114, 8526, 9677, 354, 549, 1230, 1889, 2581, 2919, 3206, 4050, 4607, 4917, 5027, 5666, 6526, 6906, 7261, 7797, 8115, 8527, 9678, 355, 550, 1231, 1890, 2582, 2920, 3207, 4051, 4224, 4918, 5028, 5667, 6527, 6907, 7262, 7798, 8116, 8528, 9679, 356, 551, 1232, 1891, 2583, 2921, 3208, 4052, 4225, 4919, 5029, 5668, 6144, 6908, 7263, 7799, 8117, 8529, 9680, 357, 552, 1233, 1892, 2584, 2922, 3209, 4053, 4226, 4920, 5030, 5669, 6145, 6909, 7264, 7800, 8118, 8530, 9681, 358, 553, 1234, 1893, 2585, 2923, 3210, 4054, 4227, 4921, 5031, 5670, 6146, 6910, 7265, 7801, 8119, 8531, 9682, 359, 554, 1235, 1894, 2586, 2924, 3211, 4055, 4228, 4922, 5032, 5671, 6147, 6911, 7266, 7802, 8120, 8532, 9683, 360, 555, 1236, 1895, 2587, 2925, 3212, 4056, 4229, 4923, 5033, 5672, 6148, 6528, 7267, 7803, 8121, 8533, 9684, 361, 556, 1237, 1896, 2588, 2926, 3213, 4057, 4230, 4924, 5034, 5673, 6149, 6529, 7268, 7804, 8122, 8534, 9685, 362, 557, 1238, 1897, 2589, 2927, 3214, 4058, 4231, 4925, 5035, 5674, 6150, 6530, 7269, 7805, 8123, 8535, 9686, 363, 558, 1239, 1898, 2590, 2928, 3215, 4059, 4232, 4926, 5036, 5675, 6151, 6531, 7270, 7806, 8124, 8536, 9687, 364, 559, 1240, 1899, 2591, 2929, 3216, 4060, 4233, 4927, 5037, 5676, 6152, 6532, 7271, 7807, 8125, 8537, 9688, 365, 560, 1241, 1900, 2592, 2930, 3217, 4061, 4234, 4928, 5038, 5677, 6153, 6533, 7272, 7808, 8126, 8538, 9689, 366, 561, 1242, 1901, 2593, 2931, 3218, 4062, 4235, 4929, 5039, 5678, 6154, 6534, 7273, 7809, 8127, 8539, 9690, 367, 562, 1243, 1902, 2594, 2932, 3219, 4063, 4236, 4930, 5040, 5679, 6155, 6535, 7274, 7810, 8128, 8540, 9691, 368, 563, 1244, 1903, 2595, 2933, 3220, 4064, 4237, 4931, 5041, 5680, 6156, 6536, 7275, 7811, 8129, 8541, 9692, 369, 564, 1245, 1904, 2596, 2934, 3221, 4065, 4238, 4932, 5042, 5681, 6157, 6537, 7276, 7812, 8130, 8542, 9693, 370, 565, 1246, 1905, 2597, 2935, 3222, 4066, 4239, 4933, 5043, 5682, 6158, 6538, 7277, 7813, 8131, 8543, 9694, 371, 566, 1247, 1906, 2598, 2936, 3223, 4067, 4240, 4934, 5044, 5683, 6159, 6539, 7278, 7814, 8132, 8544, 9695, 372, 567, 1248, 1907, 2599, 2937, 3224, 4068, 4241, 4935, 5045, 5684, 6160, 6540, 7279, 7815, 8133, 8545, 9696, 373, 568, 1249, 1908, 2600, 2938, 3225, 4069, 4242, 4936, 5046, 5685, 6161, 6541, 7280, 7816, 8134, 8546, 9697, 374, 569, 1250, 1909, 2601, 2939, 3226, 4070, 4243, 4937, 5047, 5686, 6162, 6542, 7281, 7817, 8135, 8547, 9698, 375, 570, 1251, 1910, 2602, 2940, 3227, 4071, 4244, 4938, 5048, 5687, 6163, 6543, 7282, 7818, 8136, 8548, 9699, 376, 571, 1252, 1911, 2603, 2941, 3228, 4072, 4245, 4939, 5049, 5688, 6164, 6544, 7283, 7819, 8137, 8549, 9700, 377, 572, 1253, 1912, 2604, 2942, 3229, 4073, 4246, 4940, 5050, 5689, 6165, 6545, 7284, 7820, 8138, 8550, 9701, 378, 573, 1254, 1913, 2605, 2943, 3230, 4074, 4247, 4941, 5051, 5690, 6166, 6546, 7285, 7821, 8139, 8551, 9702, 379, 574, 1255, 1914, 2606, 2944, 3231, 4075, 4248, 4942, 5052, 5691, 6167, 6547, 7286, 7822, 8140, 8552, 9703, 380, 575, 1256, 1915, 2607, 2945, 3232, 4076, 4249, 4943, 5053, 5692, 6168, 6548, 7287, 7823, 8141, 8553, 9704, 381, 576, 1257, 1916, 2608, 2946, 3233, 4077, 4250, 4944, 5054, 5693, 6169, 6549, 7288, 7824, 8142, 8554, 9705, 382, 577, 1258, 1917, 2609, 2947, 3234, 4078, 4251, 4945, 5055, 5694, 6170, 6550, 7289, 7825, 8143, 8555, 9706, 383, 578, 1259, 1918, 2610, 2948, 3235, 4079, 4252, 4946, 5056, 5695, 6171, 6551, 7290, 7826, 8144, 8556, 9707, 0, 579, 1260, 1919, 2611, 2949, 3236, 4080, 4253, 4947, 5057, 5696, 6172, 6552, 7291, 7827, 8145, 8557, 9708, 1, 580, 1261, 1536, 2612, 2950, 3237, 4081, 4254, 4948, 5058, 5697, 6173, 6553, 7292, 7828, 8146, 8558, 9709, 2, 581, 1262, 1537, 2613, 2951, 3238, 4082, 4255, 4949, 5059, 5698, 6174, 6554, 7293, 7829, 8147, 8559, 9710, 3, 582, 1263, 1538, 2614, 2952, 3239, 4083, 4256, 4950, 5060, 5699, 6175, 6555, 7294, 7830, 8148, 8560, 9711, 4, 583, 1264, 1539, 2615, 2953, 3240, 4084, 4257, 4951, 5061, 5700, 6176, 6556, 7295, 7831, 8149, 8561, 9712, 5, 584, 1265, 1540, 2616, 2954, 3241, 4085, 4258, 4952, 5062, 5701, 6177, 6557, 6912, 7832, 8150, 8562, 9713, 6, 585, 1266, 1541, 2617, 2955, 3242, 4086, 4259, 4953, 5063, 5702, 6178, 6558, 6913, 7833, 8151, 8563, 9714, 7, 586, 1267, 1542, 2618, 2956, 3243, 4087, 4260, 4954, 5064, 5703, 6179, 6559, 6914, 7834, 8152, 8564, 9715, 8, 587, 1268, 1543, 2619, 2957, 3244, 4088, 4261, 4955, 5065, 5704, 6180, 6560, 6915, 7835, 8153, 8565, 9716, 9, 588, 1269, 1544, 2620, 2958, 3245, 4089, 4262, 4956, 5066, 5705, 6181, 6561, 6916, 7836, 8154, 8566, 9717, 10, 589, 1270, 1545, 2621, 2959, 3246, 4090, 4263, 4957, 5067, 5706, 6182, 6562, 6917, 7837, 8155, 8567, 9718, 11, 590, 1271, 1546, 2622, 2960, 3247, 4091, 4264, 4958, 5068, 5707, 6183, 6563, 6918, 7838, 8156, 8568, 9719, 12, 591, 1272, 1547, 2623, 2961, 3248, 4092, 4265, 4959, 5069, 5708, 6184, 6564, 6919, 7839, 8157, 8569, 9720, 13, 592, 1273, 1548, 2624, 2962, 3249, 4093, 4266, 4960, 5070, 5709, 6185, 6565, 6920, 7840, 8158, 8570, 9721, 14, 593, 1274, 1549, 2625, 2963, 3250, 4094, 4267, 4961, 5071, 5710, 6186, 6566, 6921, 7841, 8159, 8571, 9722, 15, 594, 1275, 1550, 2626, 2964, 3251, 4095, 4268, 4962, 5072, 5711, 6187, 6567, 6922, 7842, 8160, 8572, 9723, 16, 595, 1276, 1551, 2627, 2965, 3252, 4096, 4269, 4963, 5073, 5712, 6188, 6568, 6923, 7843, 8161, 8573, 9724, 17, 596, 1277, 1552, 2628, 2966, 3253, 4097, 4270, 4964, 5074, 5713, 6189, 6569, 6924, 7844, 8162, 8574, 9725, 18, 597, 1278, 1553, 2629, 2967, 3254, 4098, 4271, 4965, 5075, 5714, 6190, 6570, 6925, 7845, 8163, 8575, 9726, 19, 598, 1279, 1554, 2630, 2968, 3255, 4099, 4272, 4966, 5076, 5715, 6191, 6571, 6926, 7846, 8164, 8576, 9727, 20, 599, 1280, 1555, 2631, 2969, 3256, 4100, 4273, 4967, 5077, 5716, 6192, 6572, 6927, 7847, 8165, 8577, 9728, 21, 600, 1281, 1556, 2632, 2970, 3257, 4101, 4274, 4968, 5078, 5717, 6193, 6573, 6928, 7848, 8166, 8578, 9729, 22, 601, 1282, 1557, 2633, 2971, 3258, 4102, 4275, 4969, 5079, 5718, 6194, 6574, 6929, 7849, 8167, 8579, 9730, 23, 602, 1283, 1558, 2634, 2972, 3259, 4103, 4276, 4970, 5080, 5719, 6195, 6575, 6930, 7850, 8168, 8580, 9731, 24, 603, 1284, 1559, 2635, 2973, 3260, 4104, 4277, 4971, 5081, 5720, 6196, 6576, 6931, 7851, 8169, 8581, 9732, 25, 604, 1285, 1560, 2636, 2974, 3261, 4105, 4278, 4972, 5082, 5721, 6197, 6577, 6932, 7852, 8170, 8582, 9733, 26, 605, 1286, 1561, 2637, 2975, 3262, 4106, 4279, 4973, 5083, 5722, 6198, 6578, 6933, 7853, 8171, 8583, 9734, 27, 606, 1287, 1562, 2638, 2976, 3263, 4107, 4280, 4974, 5084, 5723, 6199, 6579, 6934, 7854, 8172, 8584, 9735, 28, 607, 1288, 1563, 2639, 2977, 3264, 4108, 4281, 4975, 5085, 5724, 6200, 6580, 6935, 7855, 8173, 8585, 9736, 29, 608, 1289, 1564, 2640, 2978, 3265, 4109, 4282, 4976, 5086, 5725, 6201, 6581, 6936, 7856, 8174, 8586, 9737, 30, 609, 1290, 1565, 2641, 2979, 3266, 4110, 4283, 4977, 5087, 5726, 6202, 6582, 6937, 7857, 8175, 8587, 9738, 31, 610, 1291, 1566, 2642, 2980, 3267, 4111, 4284, 4978, 5088, 5727, 6203, 6583, 6938, 7858, 8176, 8588, 9739, 32, 611, 1292, 1567, 2643, 2981, 3268, 4112, 4285, 4979, 5089, 5728, 6204, 6584, 6939, 7859, 8177, 8589, 9740, 33, 612, 1293, 1568, 2644, 2982, 3269, 4113, 4286, 4980, 5090, 5729, 6205, 6585, 6940, 7860, 8178, 8590, 9741, 34, 613, 1294, 1569, 2645, 2983, 3270, 4114, 4287, 4981, 5091, 5730, 6206, 6586, 6941, 7861, 8179, 8591, 9742, 35, 614, 1295, 1570, 2646, 2984, 3271, 4115, 4288, 4982, 5092, 5731, 6207, 6587, 6942, 7862, 8180, 8592, 9743, 36, 615, 1296, 1571, 2647, 2985, 3272, 4116, 4289, 4983, 5093, 5732, 6208, 6588, 6943, 7863, 8181, 8593, 9744, 37, 616, 1297, 1572, 2648, 2986, 3273, 4117, 4290, 4984, 5094, 5733, 6209, 6589, 6944, 7864, 8182, 8594, 9745, 38, 617, 1298, 1573, 2649, 2987, 3274, 4118, 4291, 4985, 5095, 5734, 6210, 6590, 6945, 7865, 8183, 8595, 9746, 39, 618, 1299, 1574, 2650, 2988, 3275, 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25682, 35, 2721, 3574, 8677, 25683, 36, 2722, 3575, 8678, 25684, 37, 2723, 3576, 8679, 25685, 38, 2724, 3577, 8680, 25686, 39, 2725, 3578, 8681, 25687, 40, 2726, 3579, 8682, 25688, 41, 2727, 3580, 8683, 25689, 42, 2728, 3581, 8684, 25690, 43, 2729, 3582, 8685, 25691, 44, 2730, 3583, 8686, 25692, 45, 2731, 3584, 8687, 25693, 46, 2732, 3585, 8688, 25694, 47, 2733, 3586, 8689, 25695, 48, 2734, 3587, 8690, 25696, 49, 2735, 3588, 8691, 25697, 50, 2736, 3589, 8692, 25698, 51, 2737, 3590, 8693, 25699, 52, 2738, 3591, 8694, 25700, 53, 2739, 3592, 8695, 25701, 54, 2740, 3593, 8696, 25702, 55, 2741, 3594, 8697, 25703, 56, 2742, 3595, 8698, 25704, 57, 2743, 3596, 8699, 25705, 58, 2744, 3597, 8700, 25706, 59, 2745, 3598, 8701, 25707, 60, 2746, 3599, 8702, 25708, 61, 2747, 3600, 8703, 25709, 62, 2748, 3601, 8704, 25710, 63, 2749, 3602, 8705, 25711, 64, 2750, 3603, 8706, 25712, 65, 2751, 3604, 8707, 25713, 66, 2752, 3605, 8708, 25714, 67, 2753, 3606, 8709, 25715, 68, 2754, 3607, 8710, 25716, 69, 2755, 3608, 8711, 25717, 70, 2756, 3609, 8712, 25718, 71, 2757, 3610, 8713, 25719, 72, 2758, 3611, 8714, 25720, 73, 2759, 3612, 8715, 25721, 74, 2760, 3613, 8716, 25722, 75, 2761, 3614, 8717, 25723, 76, 2762, 3615, 8718, 25724, 77, 2763, 3616, 8719, 25725, 78, 2764, 3617, 8720, 25726, 79, 2765, 3618, 8721, 25727, 519, 2453, 3855, 25728, 520, 2454, 3856, 25729, 521, 2455, 3857, 25730, 522, 2456, 3858, 25731, 523, 2457, 3859, 25732, 524, 2458, 3860, 25733, 525, 2459, 3861, 25734, 526, 2460, 3862, 25735, 527, 2461, 3863, 25736, 528, 2462, 3864, 25737, 529, 2463, 3865, 25738, 530, 2464, 3866, 25739, 531, 2465, 3867, 25740, 532, 2466, 3868, 25741, 533, 2467, 3869, 25742, 534, 2468, 3870, 25743, 535, 2469, 3871, 25744, 536, 2470, 3872, 25745, 537, 2471, 3873, 25746, 538, 2472, 3874, 25747, 539, 2473, 3875, 25748, 540, 2474, 3876, 25749, 541, 2475, 3877, 25750, 542, 2476, 3878, 25751, 543, 2477, 3879, 25752, 544, 2478, 3880, 25753, 545, 2479, 3881, 25754, 546, 2480, 3882, 25755, 547, 2481, 3883, 25756, 548, 2482, 3884, 25757, 549, 2483, 3885, 25758, 550, 2484, 3886, 25759, 551, 2485, 3887, 25760, 552, 2486, 3888, 25761, 553, 2487, 3889, 25762, 554, 2488, 3890, 25763, 555, 2489, 3891, 25764, 556, 2490, 3892, 25765, 557, 2491, 3893, 25766, 558, 2492, 3894, 25767, 559, 2493, 3895, 25768, 560, 2494, 3896, 25769, 561, 2495, 3897, 25770, 562, 2496, 3898, 25771, 563, 2497, 3899, 25772, 564, 2498, 3900, 25773, 565, 2499, 3901, 25774, 566, 2500, 3902, 25775, 567, 2501, 3903, 25776, 568, 2502, 3904, 25777, 569, 2503, 3905, 25778, 570, 2504, 3906, 25779, 571, 2505, 3907, 25780, 572, 2506, 3908, 25781, 573, 2507, 3909, 25782, 574, 2508, 3910, 25783, 575, 2509, 3911, 25784, 576, 2510, 3912, 25785, 577, 2511, 3913, 25786, 578, 2512, 3914, 25787, 579, 2513, 3915, 25788, 580, 2514, 3916, 25789, 581, 2515, 3917, 25790, 582, 2516, 3918, 25791, 583, 2517, 3919, 25792, 584, 2518, 3920, 25793, 585, 2519, 3921, 25794, 586, 2520, 3922, 25795, 587, 2521, 3923, 25796, 588, 2522, 3924, 25797, 589, 2523, 3925, 25798, 590, 2524, 3926, 25799, 591, 2525, 3927, 25800, 592, 2526, 3928, 25801, 593, 2527, 3929, 25802, 594, 2528, 3930, 25803, 595, 2529, 3931, 25804, 596, 2530, 3932, 25805, 597, 2531, 3933, 25806, 598, 2532, 3934, 25807, 599, 2533, 3935, 25808, 600, 2534, 3936, 25809, 601, 2535, 3937, 25810, 602, 2536, 3938, 25811, 603, 2537, 3939, 25812, 604, 2538, 3940, 25813, 605, 2539, 3941, 25814, 606, 2540, 3942, 25815, 607, 2541, 3943, 25816, 608, 2542, 3944, 25817, 609, 2543, 3945, 25818, 610, 2544, 3946, 25819, 611, 2545, 3947, 25820, 612, 2546, 3948, 25821, 613, 2547, 3949, 25822, 614, 2548, 3950, 25823, 615, 2549, 3951, 25824, 616, 2550, 3952, 25825, 617, 2551, 3953, 25826, 618, 2552, 3954, 25827, 619, 2553, 3955, 25828, 620, 2554, 3956, 25829, 621, 2555, 3957, 25830, 622, 2556, 3958, 25831, 623, 2557, 3959, 25832, 624, 2558, 3960, 25833, 625, 2559, 3961, 25834, 626, 2560, 3962, 25835, 627, 2561, 3963, 25836, 628, 2562, 3964, 25837, 629, 2563, 3965, 25838, 630, 2564, 3966, 25839, 631, 2565, 3967, 25840, 632, 2566, 3968, 25841, 633, 2567, 3969, 25842, 634, 2568, 3970, 25843, 635, 2569, 3971, 25844, 636, 2570, 3972, 25845, 637, 2571, 3973, 25846, 638, 2572, 3974, 25847, 639, 2573, 3975, 25848, 640, 2574, 3976, 25849, 641, 2575, 3977, 25850, 642, 2576, 3978, 25851, 643, 2577, 3979, 25852, 644, 2578, 3980, 25853, 645, 2579, 3981, 25854, 646, 2580, 3982, 25855, 647, 2581, 3983, 25856, 648, 2582, 3984, 25857, 649, 2583, 3985, 25858, 650, 2584, 3986, 25859, 651, 2585, 3987, 25860, 652, 2586, 3988, 25861, 653, 2587, 3989, 25862, 654, 2588, 3990, 25863, 655, 2589, 3991, 25864, 656, 2590, 3992, 25865, 657, 2591, 3993, 25866, 658, 2592, 3994, 25867, 659, 2593, 3995, 25868, 660, 2594, 3996, 25869, 661, 2595, 3997, 25870, 662, 2596, 3998, 25871, 663, 2597, 3999, 25872, 664, 2598, 4000, 25873, 665, 2599, 4001, 25874, 666, 2600, 4002, 25875, 667, 2601, 4003, 25876, 668, 2602, 4004, 25877, 669, 2603, 4005, 25878, 670, 2604, 4006, 25879, 671, 2605, 4007, 25880, 672, 2606, 4008, 25881, 673, 2607, 4009, 25882, 674, 2608, 4010, 25883, 675, 2609, 4011, 25884, 676, 2610, 4012, 25885, 677, 2611, 4013, 25886, 678, 2612, 4014, 25887, 679, 2613, 4015, 25888, 680, 2614, 4016, 25889, 681, 2615, 4017, 25890, 682, 2616, 4018, 25891, 683, 2617, 4019, 25892, 684, 2618, 4020, 25893, 685, 2619, 4021, 25894, 686, 2620, 4022, 25895, 687, 2621, 4023, 25896, 688, 2622, 4024, 25897, 689, 2623, 4025, 25898, 690, 2624, 4026, 25899, 691, 2625, 4027, 25900, 692, 2626, 4028, 25901, 693, 2627, 4029, 25902, 694, 2628, 4030, 25903, 695, 2629, 4031, 25904, 696, 2630, 4032, 25905, 697, 2631, 4033, 25906, 698, 2632, 4034, 25907, 699, 2633, 4035, 25908, 700, 2634, 4036, 25909, 701, 2635, 4037, 25910, 702, 2636, 4038, 25911, 703, 2637, 4039, 25912, 704, 2638, 4040, 25913, 705, 2639, 4041, 25914, 706, 2640, 4042, 25915, 707, 2641, 4043, 25916, 708, 2642, 4044, 25917, 709, 2643, 4045, 25918, 710, 2644, 4046, 25919, 711, 2645, 4047, 25920, 712, 2646, 4048, 25921, 713, 2647, 4049, 25922, 714, 2648, 4050, 25923, 715, 2649, 4051, 25924, 716, 2650, 4052, 25925, 717, 2651, 4053, 25926, 718, 2652, 4054, 25927, 719, 2653, 4055, 25928, 720, 2654, 4056, 25929, 721, 2655, 4057, 25930, 722, 2656, 4058, 25931, 723, 2657, 4059, 25932, 724, 2658, 4060, 25933, 725, 2659, 4061, 25934, 726, 2660, 4062, 25935, 727, 2661, 4063, 25936, 728, 2662, 4064, 25937, 729, 2663, 4065, 25938, 730, 2664, 4066, 25939, 731, 2665, 4067, 25940, 732, 2666, 4068, 25941, 733, 2667, 4069, 25942, 734, 2668, 4070, 25943, 735, 2669, 4071, 25944, 736, 2670, 4072, 25945, 737, 2671, 4073, 25946, 738, 2672, 4074, 25947, 739, 2673, 4075, 25948, 740, 2674, 4076, 25949, 741, 2675, 4077, 25950, 742, 2676, 4078, 25951, 743, 2677, 4079, 25952, 744, 2678, 4080, 25953, 745, 2679, 4081, 25954, 746, 2680, 4082, 25955, 747, 2681, 4083, 25956, 748, 2682, 4084, 25957, 749, 2683, 4085, 25958, 750, 2684, 4086, 25959, 751, 2685, 4087, 25960, 752, 2686, 4088, 25961, 753, 2687, 4089, 25962, 754, 2304, 4090, 25963, 755, 2305, 4091, 25964, 756, 2306, 4092, 25965, 757, 2307, 4093, 25966, 758, 2308, 4094, 25967, 759, 2309, 4095, 25968, 760, 2310, 4096, 25969, 761, 2311, 4097, 25970, 762, 2312, 4098, 25971, 763, 2313, 4099, 25972, 764, 2314, 4100, 25973, 765, 2315, 4101, 25974, 766, 2316, 4102, 25975, 767, 2317, 4103, 25976, 384, 2318, 4104, 25977, 385, 2319, 4105, 25978, 386, 2320, 4106, 25979, 387, 2321, 4107, 25980, 388, 2322, 4108, 25981, 389, 2323, 4109, 25982, 390, 2324, 4110, 25983, 391, 2325, 4111, 25984, 392, 2326, 4112, 25985, 393, 2327, 4113, 25986, 394, 2328, 4114, 25987, 395, 2329, 4115, 25988, 396, 2330, 4116, 25989, 397, 2331, 4117, 25990, 398, 2332, 4118, 25991, 399, 2333, 4119, 25992, 400, 2334, 4120, 25993, 401, 2335, 4121, 25994, 402, 2336, 4122, 25995, 403, 2337, 4123, 25996, 404, 2338, 4124, 25997, 405, 2339, 4125, 25998, 406, 2340, 4126, 25999, 407, 2341, 4127, 26000, 408, 2342, 4128, 26001, 409, 2343, 4129, 26002, 410, 2344, 4130, 26003, 411, 2345, 4131, 26004, 412, 2346, 4132, 26005, 413, 2347, 4133, 26006, 414, 2348, 4134, 26007, 415, 2349, 4135, 26008, 416, 2350, 4136, 26009, 417, 2351, 4137, 26010, 418, 2352, 4138, 26011, 419, 2353, 4139, 26012, 420, 2354, 4140, 26013, 421, 2355, 4141, 26014, 422, 2356, 4142, 26015, 423, 2357, 4143, 26016, 424, 2358, 4144, 26017, 425, 2359, 4145, 26018, 426, 2360, 4146, 26019, 427, 2361, 4147, 26020, 428, 2362, 4148, 26021, 429, 2363, 4149, 26022, 430, 2364, 4150, 26023, 431, 2365, 4151, 26024, 432, 2366, 4152, 26025, 433, 2367, 4153, 26026, 434, 2368, 4154, 26027, 435, 2369, 4155, 26028, 436, 2370, 4156, 26029, 437, 2371, 4157, 26030, 438, 2372, 4158, 26031, 439, 2373, 4159, 26032, 440, 2374, 4160, 26033, 441, 2375, 4161, 26034, 442, 2376, 4162, 26035, 443, 2377, 4163, 26036, 444, 2378, 4164, 26037, 445, 2379, 4165, 26038, 446, 2380, 4166, 26039, 447, 2381, 4167, 26040, 448, 2382, 4168, 26041, 449, 2383, 4169, 26042, 450, 2384, 4170, 26043, 451, 2385, 4171, 26044, 452, 2386, 4172, 26045, 453, 2387, 4173, 26046, 454, 2388, 4174, 26047, 455, 2389, 4175, 26048, 456, 2390, 4176, 26049, 457, 2391, 4177, 26050, 458, 2392, 4178, 26051, 459, 2393, 4179, 26052, 460, 2394, 4180, 26053, 461, 2395, 4181, 26054, 462, 2396, 4182, 26055, 463, 2397, 4183, 26056, 464, 2398, 4184, 26057, 465, 2399, 4185, 26058, 466, 2400, 4186, 26059, 467, 2401, 4187, 26060, 468, 2402, 4188, 26061, 469, 2403, 4189, 26062, 470, 2404, 4190, 26063, 471, 2405, 4191, 26064, 472, 2406, 4192, 26065, 473, 2407, 4193, 26066, 474, 2408, 4194, 26067, 475, 2409, 4195, 26068, 476, 2410, 4196, 26069, 477, 2411, 4197, 26070, 478, 2412, 4198, 26071, 479, 2413, 4199, 26072, 480, 2414, 4200, 26073, 481, 2415, 4201, 26074, 482, 2416, 4202, 26075, 483, 2417, 4203, 26076, 484, 2418, 4204, 26077, 485, 2419, 4205, 26078, 486, 2420, 4206, 26079, 487, 2421, 4207, 26080, 488, 2422, 4208, 26081, 489, 2423, 4209, 26082, 490, 2424, 4210, 26083, 491, 2425, 4211, 26084, 492, 2426, 4212, 26085, 493, 2427, 4213, 26086, 494, 2428, 4214, 26087, 495, 2429, 4215, 26088, 496, 2430, 4216, 26089, 497, 2431, 4217, 26090, 498, 2432, 4218, 26091, 499, 2433, 4219, 26092, 500, 2434, 4220, 26093, 501, 2435, 4221, 26094, 502, 2436, 4222, 26095, 503, 2437, 4223, 26096, 504, 2438, 3840, 26097, 505, 2439, 3841, 26098, 506, 2440, 3842, 26099, 507, 2441, 3843, 26100, 508, 2442, 3844, 26101, 509, 2443, 3845, 26102, 510, 2444, 3846, 26103, 511, 2445, 3847, 26104, 512, 2446, 3848, 26105, 513, 2447, 3849, 26106, 514, 2448, 3850, 26107, 515, 2449, 3851, 26108, 516, 2450, 3852, 26109, 517, 2451, 3853, 26110, 518, 2452, 3854, 26111}; -int c2b_idx[121344] = { 1463, 13148, 17993, 23940, 29340, 31848, 34362, 39489, 40322, 43554, 52224, 54757, 55722, 59294, 61289, 66024, 71322, 73374, 78570, 81156, 86429, 89130, 93285, 97410, 100610, 104550, 108131, 111812, 115516, 119408, 1482, 13167, 18012, 23959, 29343, 31856, 34371, 39496, 40332, 43563, 52232, 54764, 55728, 59301, 61296, 66030, 71328, 73380, 78575, 81162, 86434, 89135, 93290, 97415, 100615, 104555, 108136, 111816, 115520, 119413, 1501, 13186, 18031, 23978, 29346, 31864, 34380, 39503, 40342, 43572, 52240, 54771, 55734, 59308, 61303, 66036, 71334, 73386, 78580, 81168, 86439, 89140, 93295, 97420, 100620, 104560, 108141, 111820, 115524, 119418, 1520, 13205, 18050, 23997, 29349, 31872, 34389, 39510, 40352, 43581, 52248, 54778, 55740, 59315, 61310, 66042, 71340, 73392, 78585, 81174, 86444, 89145, 93300, 97425, 100625, 104565, 108146, 111824, 115528, 119423, 1539, 13224, 18069, 24016, 29352, 31880, 34398, 39517, 40362, 43590, 52256, 54785, 55746, 59322, 61317, 66048, 71346, 73398, 78590, 81180, 86449, 89150, 93305, 97430, 100630, 104570, 108151, 111828, 115532, 119428, 1558, 13243, 18088, 24035, 29355, 31888, 34407, 39524, 40372, 43599, 52264, 54792, 55752, 59329, 61324, 66054, 71352, 73404, 78595, 81186, 86454, 89155, 93310, 97435, 100635, 104575, 108156, 111832, 115536, 119433, 1577, 13262, 18107, 24054, 29358, 31896, 34416, 39531, 40382, 43608, 52272, 54799, 55758, 59336, 61331, 66060, 71358, 73410, 78600, 81192, 86459, 89160, 93315, 97440, 100640, 104580, 108161, 111836, 115540, 119438, 1596, 13281, 18126, 24073, 29361, 31904, 34425, 39538, 40392, 43617, 52280, 54806, 55764, 59343, 61338, 66066, 71364, 73416, 78605, 81198, 86464, 89165, 93320, 97445, 100645, 104585, 108166, 111840, 115544, 119443, 1615, 13300, 18145, 24092, 29364, 31912, 34434, 39545, 40402, 43626, 52288, 54813, 55770, 59350, 61345, 66072, 71370, 73422, 78610, 81204, 86469, 89170, 93325, 97450, 100650, 104590, 108171, 111844, 115548, 119448, 1634, 13319, 18164, 24111, 29367, 31920, 34443, 36864, 40412, 43635, 52296, 54820, 55776, 59357, 61352, 66078, 71376, 73428, 78615, 81210, 86474, 89175, 93330, 97455, 100655, 104595, 108176, 111848, 115552, 119453, 1653, 13338, 18183, 24130, 29370, 31928, 34452, 36871, 40422, 43644, 52304, 54827, 55782, 59364, 61359, 66084, 71382, 73434, 78620, 81216, 86479, 89180, 93335, 97460, 100660, 104600, 108181, 111852, 115556, 119458, 1672, 13357, 18202, 24149, 29373, 31936, 34461, 36878, 40432, 43653, 52312, 54834, 55788, 59371, 61366, 66090, 71388, 73440, 78625, 81222, 86484, 89185, 93340, 97465, 100665, 104605, 108186, 111856, 115560, 119463, 1691, 13376, 18221, 24168, 29376, 31944, 34470, 36885, 40442, 43662, 52320, 54841, 55794, 59378, 61373, 66096, 71394, 73446, 78630, 81228, 86489, 89190, 93345, 97470, 100670, 104610, 108191, 111860, 115564, 119468, 1710, 13395, 18240, 24187, 29379, 31952, 34479, 36892, 40452, 43671, 52328, 54848, 55800, 59385, 61380, 66102, 71400, 73452, 78635, 81234, 86494, 89195, 93350, 97475, 100675, 104615, 108196, 111864, 115568, 119473, 1729, 13414, 18259, 24206, 29382, 31960, 34488, 36899, 40462, 43680, 52336, 54855, 55806, 59392, 61387, 66108, 71406, 73458, 78640, 81240, 86499, 89200, 93355, 97480, 100680, 104620, 108201, 111868, 115572, 119478, 1748, 13433, 18278, 24225, 29385, 31968, 34497, 36906, 40472, 43689, 52344, 54862, 55812, 59399, 61394, 66114, 71412, 73464, 78645, 81246, 86504, 89205, 93360, 97485, 100685, 104625, 108206, 111872, 115576, 119483, 1767, 13452, 18297, 24244, 29388, 31976, 34506, 36913, 40482, 43698, 52352, 54869, 55818, 59406, 61401, 66120, 71418, 73470, 78650, 81252, 86509, 89210, 93365, 97490, 100690, 104630, 108211, 111876, 115580, 119488, 1786, 13471, 18316, 24263, 29391, 31984, 34515, 36920, 40492, 43707, 52360, 54876, 55824, 59413, 61408, 66126, 71424, 73476, 78655, 81258, 86514, 89215, 93370, 97495, 100695, 104635, 108216, 111880, 115584, 119493, 1805, 13490, 18335, 24282, 29394, 31992, 34524, 36927, 40502, 43716, 52368, 54883, 55830, 59420, 61415, 66132, 71430, 73482, 78660, 81264, 86519, 89220, 93375, 97500, 100700, 104640, 108221, 111884, 115588, 119498, 1824, 13509, 18354, 24301, 29397, 32000, 34533, 36934, 40512, 43725, 52376, 54890, 55836, 59427, 61422, 66138, 71436, 73488, 78665, 81270, 86524, 89225, 93380, 97505, 100705, 104645, 108226, 111888, 115592, 119503, 1843, 13528, 18373, 24320, 29400, 32008, 34542, 36941, 40522, 43734, 52384, 54897, 55842, 59434, 61429, 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112019, 112023, 112027, 112031, 112035, 112039, 112043, 112047, 112051, 112055, 112059, 112063, 112067, 112071, 112075, 112079, 112083, 112087, 112091, 112095, 112099, 112103, 112107, 112111, 112115, 112119, 112123, 112127, 112131, 112135, 112139, 112143, 112147, 112151, 112155, 112159, 112163, 112167, 112171, 112175, 112179, 112183, 112187, 112191, 112195, 112199, 112203, 112207, 112211, 112215, 112219, 112223, 112227, 112231, 112235, 112239, 112243, 112247, 112251, 112255, 112259, 112263, 112267, 112271, 112275, 112279, 112283, 112287, 112291, 112295, 112299, 112303, 112307, 112311, 112315, 112319, 112323, 112327, 112331, 112335, 112339, 112343, 112347, 112351, 112355, 112359, 112363, 112367, 112371, 112375, 112379, 112383, 112387, 112391, 112395, 112399, 112403, 112407, 112411, 112415, 112419, 112423, 112427, 112431, 112435, 112439, 112443, 112447, 112451, 112455, 112459, 112463, 112467, 112471, 112475, 112479, 112483, 112487, 112491, 112495, 112499, 112503, 112507, 112511, 112516, 112521, 112526, 112531, 112536, 112541, 112546, 112551, 112556, 112561, 112566, 112571, 112576, 112581, 112586, 112591, 112596, 112601, 112606, 112611, 112616, 112621, 112626, 112631, 112636, 112641, 112646, 112651, 112656, 112661, 112666, 112671, 112676, 112681, 112686, 112691, 112696, 112701, 112706, 112711, 112716, 112721, 112726, 112731, 112736, 112741, 112746, 112751, 112756, 112761, 112766, 112771, 112776, 112781, 112786, 112791, 112796, 112801, 112806, 112811, 112816, 112821, 112826, 112831, 112836, 112841, 112846, 112851, 112856, 112861, 112866, 112871, 112876, 112881, 112886, 112891, 112896, 112901, 112906, 112911, 112916, 112921, 112926, 112931, 112936, 112941, 112946, 112951, 112956, 112961, 112966, 112971, 112976, 112981, 112986, 112991, 112996, 113001, 113006, 113011, 113016, 113021, 113026, 113031, 113036, 113041, 113046, 113051, 113056, 113061, 113066, 113071, 113076, 113081, 113086, 113091, 113096, 113101, 113106, 113111, 113116, 113121, 113126, 113131, 113136, 113141, 113146, 113151, 113156, 113161, 113166, 113171, 113176, 113181, 113186, 113191, 113196, 113201, 113206, 113211, 113216, 113221, 113226, 113231, 113236, 113241, 113246, 113251, 113256, 113261, 113266, 113271, 113276, 113281, 113286, 113291, 113296, 113301, 113306, 113311, 113316, 113321, 113326, 113331, 113336, 113341, 113346, 113351, 113356, 113361, 113366, 113371, 113376, 113381, 113386, 113391, 113396, 113401, 113406, 113411, 113416, 113421, 113426, 113431, 113436, 113441, 113446, 113451, 113456, 113461, 113466, 113471, 113476, 113481, 113486, 113491, 113496, 113501, 113506, 113511, 113516, 113521, 113526, 113531, 113536, 113541, 113546, 113551, 113556, 113561, 113566, 113571, 113576, 113581, 113586, 113591, 113596, 113601, 113606, 113611, 113616, 113621, 113626, 113631, 113636, 113641, 113646, 113651, 113656, 113661, 113666, 113671, 113676, 113681, 113686, 113691, 113696, 113701, 113706, 113711, 113716, 113721, 113726, 113731, 113736, 113741, 113746, 113751, 113756, 113761, 113766, 113771, 113776, 113781, 113786, 113791, 113796, 113801, 113806, 113811, 113816, 113821, 113826, 113831, 113836, 113841, 113846, 113851, 113856, 113861, 113866, 113871, 113876, 113881, 113886, 113891, 113896, 113901, 113906, 113911, 113916, 113921, 113926, 113931, 113936, 113941, 113946, 113951, 113956, 113961, 113966, 113971, 113976, 113981, 113986, 113991, 113996, 114001, 114006, 114011, 114016, 114021, 114026, 114031, 114036, 114041, 114046, 114051, 114056, 114061, 114066, 114071, 114076, 114081, 114086, 114091, 114096, 114101, 114106, 114111, 114116, 114121, 114126, 114131, 114136, 114141, 114146, 114151, 114156, 114161, 114166, 114171, 114176, 114181, 114186, 114191, 114196, 114201, 114206, 114211, 114216, 114221, 114226, 114231, 114236, 114241, 114246, 114251, 114256, 114261, 114266, 114271, 114276, 114281, 114286, 114291, 114296, 114301, 114306, 114311, 114316, 114321, 114326, 114331, 114336, 114341, 114346, 114351, 114356, 114361, 114366, 114371, 114376, 114381, 114386, 114391, 114396, 114401, 114406, 114411, 114416, 114421, 114426, 114431, 114435, 114439, 114443, 114447, 114451, 114455, 114459, 114463, 114467, 114471, 114475, 114479, 114483, 114487, 114491, 114495, 114499, 114503, 114507, 114511, 114515, 114519, 114523, 114527, 114531, 114535, 114539, 114543, 114547, 114551, 114555, 114559, 114563, 114567, 114571, 114575, 114579, 114583, 114587, 114591, 114595, 114599, 114603, 114607, 114611, 114615, 114619, 114623, 114627, 114631, 114635, 114639, 114643, 114647, 114651, 114655, 114659, 114663, 114667, 114671, 114675, 114679, 114683, 114687, 114691, 114695, 114699, 114703, 114707, 114711, 114715, 114719, 114723, 114727, 114731, 114735, 114739, 114743, 114747, 114751, 114755, 114759, 114763, 114767, 114771, 114775, 114779, 114783, 114787, 114791, 114795, 114799, 114803, 114807, 114811, 114815, 114819, 114823, 114827, 114831, 114835, 114839, 114843, 114847, 114851, 114855, 114859, 114863, 114867, 114871, 114875, 114879, 114883, 114887, 114891, 114895, 114899, 114903, 114907, 114911, 114915, 114919, 114923, 114927, 114931, 114935, 114939, 114943, 114947, 114951, 114955, 114959, 114963, 114967, 114971, 114975, 114979, 114983, 114987, 114991, 114995, 114999, 115003, 115007, 115011, 115015, 115019, 115023, 115027, 115031, 115035, 115039, 115043, 115047, 115051, 115055, 115059, 115063, 115067, 115071, 115075, 115079, 115083, 115087, 115091, 115095, 115099, 115103, 115107, 115111, 115115, 115119, 115123, 115127, 115131, 115135, 115139, 115143, 115147, 115151, 115155, 115159, 115163, 115167, 115171, 115175, 115179, 115183, 115187, 115191, 115195, 115199, 115203, 115207, 115211, 115215, 115219, 115223, 115227, 115231, 115235, 115239, 115243, 115247, 115251, 115255, 115259, 115263, 115267, 115271, 115275, 115279, 115283, 115287, 115291, 115295, 115299, 115303, 115307, 115311, 115315, 115319, 115323, 115327, 115331, 115335, 115339, 115343, 115347, 115351, 115355, 115359, 115363, 115367, 115371, 115375, 115379, 115383, 115387, 115391, 115395, 115399, 115403, 115407, 115411, 115415, 115419, 115423, 115427, 115431, 115435, 115439, 115443, 115447, 115451, 115455, 115459, 115463, 115467, 115471, 115475, 115479, 115483, 115487, 115491, 115495, 115499, 115503, 115507, 115511, 115515, 115519, 115523, 115527, 115531, 115535, 115539, 115543, 115547, 115551, 115555, 115559, 115563, 115567, 115571, 115575, 115579, 115583, 115587, 115591, 115595, 115599, 115603, 115607, 115611, 115615, 115619, 115623, 115627, 115631, 115635, 115639, 115643, 115647, 115651, 115655, 115659, 115663, 115667, 115671, 115675, 115679, 115683, 115687, 115691, 115695, 115699, 115703, 115707, 115711, 115715, 115719, 115723, 115727, 115731, 115735, 115739, 115743, 115747, 115751, 115755, 115759, 115763, 115767, 115771, 115775, 115779, 115783, 115787, 115791, 115795, 115799, 115803, 115807, 115811, 115815, 115819, 115823, 115827, 115831, 115835, 115839, 115843, 115847, 115851, 115855, 115859, 115863, 115867, 115871, 115875, 115879, 115883, 115887, 115891, 115895, 115899, 115903, 115907, 115911, 115915, 115919, 115923, 115927, 115931, 115935, 115939, 115943, 115947, 115951, 115955, 115959, 115963, 115967, 115972, 115977, 115982, 115987, 115992, 115997, 116002, 116007, 116012, 116017, 116022, 116027, 116032, 116037, 116042, 116047, 116052, 116057, 116062, 116067, 116072, 116077, 116082, 116087, 116092, 116097, 116102, 116107, 116112, 116117, 116122, 116127, 116132, 116137, 116142, 116147, 116152, 116157, 116162, 116167, 116172, 116177, 116182, 116187, 116192, 116197, 116202, 116207, 116212, 116217, 116222, 116227, 116232, 116237, 116242, 116247, 116252, 116257, 116262, 116267, 116272, 116277, 116282, 116287, 116292, 116297, 116302, 116307, 116312, 116317, 116322, 116327, 116332, 116337, 116342, 116347, 116352, 116357, 116362, 116367, 116372, 116377, 116382, 116387, 116392, 116397, 116402, 116407, 116412, 116417, 116422, 116427, 116432, 116437, 116442, 116447, 116452, 116457, 116462, 116467, 116472, 116477, 116482, 116487, 116492, 116497, 116502, 116507, 116512, 116517, 116522, 116527, 116532, 116537, 116542, 116547, 116552, 116557, 116562, 116567, 116572, 116577, 116582, 116587, 116592, 116597, 116602, 116607, 116612, 116617, 116622, 116627, 116632, 116637, 116642, 116647, 116652, 116657, 116662, 116667, 116672, 116677, 116682, 116687, 116692, 116697, 116702, 116707, 116712, 116717, 116722, 116727, 116732, 116737, 116742, 116747, 116752, 116757, 116762, 116767, 116772, 116777, 116782, 116787, 116792, 116797, 116802, 116807, 116812, 116817, 116822, 116827, 116832, 116837, 116842, 116847, 116852, 116857, 116862, 116867, 116872, 116877, 116882, 116887, 116892, 116897, 116902, 116907, 116912, 116917, 116922, 116927, 116932, 116937, 116942, 116947, 116952, 116957, 116962, 116967, 116972, 116977, 116982, 116987, 116992, 116997, 117002, 117007, 117012, 117017, 117022, 117027, 117032, 117037, 117042, 117047, 117052, 117057, 117062, 117067, 117072, 117077, 117082, 117087, 117092, 117097, 117102, 117107, 117112, 117117, 117122, 117127, 117132, 117137, 117142, 117147, 117152, 117157, 117162, 117167, 117172, 117177, 117182, 117187, 117192, 117197, 117202, 117207, 117212, 117217, 117222, 117227, 117232, 117237, 117242, 117247, 117252, 117257, 117262, 117267, 117272, 117277, 117282, 117287, 117292, 117297, 117302, 117307, 117312, 117317, 117322, 117327, 117332, 117337, 117342, 117347, 117352, 117357, 117362, 117367, 117372, 117377, 117382, 117387, 117392, 117397, 117402, 117407, 117412, 117417, 117422, 117427, 117432, 117437, 117442, 117447, 117452, 117457, 117462, 117467, 117472, 117477, 117482, 117487, 117492, 117497, 117502, 117507, 117512, 117517, 117522, 117527, 117532, 117537, 117542, 117547, 117552, 117557, 117562, 117567, 117572, 117577, 117582, 117587, 117592, 117597, 117602, 117607, 117612, 117617, 117622, 117627, 117632, 117637, 117642, 117647, 117652, 117657, 117662, 117667, 117672, 117677, 117682, 117687, 117692, 117697, 117702, 117707, 117712, 117717, 117722, 117727, 117732, 117737, 117742, 117747, 117752, 117757, 117762, 117767, 117772, 117777, 117782, 117787, 117792, 117797, 117802, 117807, 117812, 117817, 117822, 117827, 117832, 117837, 117842, 117847, 117852, 117857, 117862, 117867, 117872, 117877, 117882, 117887, 117892, 117897, 117902, 117907, 117912, 117917, 117922, 117927, 117932, 117937, 117942, 117947, 117952, 117957, 117962, 117967, 117972, 117977, 117982, 117987, 117992, 117997, 118002, 118007, 118012, 118017, 118022, 118027, 118032, 118037, 118042, 118047, 118052, 118057, 118062, 118067, 118072, 118077, 118082, 118087, 118092, 118097, 118102, 118107, 118112, 118117, 118122, 118127, 118132, 118137, 118142, 118147, 118152, 118157, 118162, 118167, 118172, 118177, 118182, 118187, 118192, 118197, 118202, 118207, 118212, 118217, 118222, 118227, 118232, 118237, 118242, 118247, 118252, 118257, 118262, 118267, 118272, 118277, 118282, 118287, 118292, 118297, 118302, 118307, 118312, 118317, 118322, 118327, 118332, 118337, 118342, 118347, 118352, 118357, 118362, 118367, 118372, 118377, 118382, 118387, 118392, 118397, 118402, 118407, 118412, 118417, 118422, 118427, 118432, 118437, 118442, 118447, 118452, 118457, 118462, 118467, 118472, 118477, 118482, 118487, 118492, 118497, 118502, 118507, 118512, 118517, 118522, 118527, 118532, 118537, 118542, 118547, 118552, 118557, 118562, 118567, 118572, 118577, 118582, 118587, 118592, 118597, 118602, 118607, 118612, 118617, 118622, 118627, 118632, 118637, 118642, 118647, 118652, 118657, 118662, 118667, 118672, 118677, 118682, 118687, 118692, 118697, 118702, 118707, 118712, 118717, 118722, 118727, 118732, 118737, 118742, 118747, 118752, 118757, 118762, 118767, 118772, 118777, 118782, 118787, 118792, 118797, 118802, 118807, 118812, 118817, 118822, 118827, 118832, 118837, 118842, 118847, 118852, 118857, 118862, 118867, 118872, 118877, 118882, 118887, 118892, 118897, 118902, 118907, 118912, 118917, 118922, 118927, 118932, 118937, 118942, 118947, 118952, 118957, 118962, 118967, 118972, 118977, 118982, 118987, 118992, 118997, 119002, 119007, 119012, 119017, 119022, 119027, 119032, 119037, 119042, 119047, 119052, 119057, 119062, 119067, 119072, 119077, 119082, 119087, 119092, 119097, 119102, 119107, 119112, 119117, 119122, 119127, 119132, 119137, 119142, 119147, 119152, 119157, 119162, 119167, 119172, 119177, 119182, 119187, 119192, 119197, 119202, 119207, 119212, 119217, 119222, 119227, 119232, 119237, 119242, 119247, 119252, 119257, 119262, 119267, 119272, 119277, 119282, 119287, 119292, 119297, 119302, 119307, 119312, 119317, 119322, 119327, 119332, 119337, 119342, 119347, 119352, 119357, 119362, 119367, 119372, 119377, 119382, 119387, 119392, 119397, 119402, 119407, 119412, 119417, 119422, 119427, 119432, 119437, 119442, 119447, 119452, 119457, 119462, 119467, 119472, 119477, 119482, 119487, 119492, 119497, 119502, 119507, 119512, 119517, 119522, 119527, 119532, 119537, 119542, 119547, 119552, 119557, 119562, 119567, 119572, 119577, 119582, 119587, 119592, 119597, 119602, 119607, 119612, 119617, 119622, 119627, 119632, 119637, 119642, 119647, 119652, 119657, 119662, 119667, 119672, 119677, 119682, 119687, 119692, 119697, 119702, 119707, 119712, 119717, 119722, 119727, 119732, 119737, 119742, 119747, 119752, 119757, 119762, 119767, 119772, 119777, 119782, 119787, 119792, 119797, 119802, 119807, 119811, 119815, 119819, 119823, 119827, 119831, 119835, 119839, 119843, 119847, 119851, 119855, 119859, 119863, 119867, 119871, 119875, 119879, 119883, 119887, 119891, 119895, 119899, 119903, 119907, 119911, 119915, 119919, 119923, 119927, 119931, 119935, 119939, 119943, 119947, 119951, 119955, 119959, 119963, 119967, 119971, 119975, 119979, 119983, 119987, 119991, 119995, 119999, 120003, 120007, 120011, 120015, 120019, 120023, 120027, 120031, 120035, 120039, 120043, 120047, 120051, 120055, 120059, 120063, 120067, 120071, 120075, 120079, 120083, 120087, 120091, 120095, 120099, 120103, 120107, 120111, 120115, 120119, 120123, 120127, 120131, 120135, 120139, 120143, 120147, 120151, 120155, 120159, 120163, 120167, 120171, 120175, 120179, 120183, 120187, 120191, 120195, 120199, 120203, 120207, 120211, 120215, 120219, 120223, 120227, 120231, 120235, 120239, 120243, 120247, 120251, 120255, 120259, 120263, 120267, 120271, 120275, 120279, 120283, 120287, 120291, 120295, 120299, 120303, 120307, 120311, 120315, 120319, 120323, 120327, 120331, 120335, 120339, 120343, 120347, 120351, 120355, 120359, 120363, 120367, 120371, 120375, 120379, 120383, 120387, 120391, 120395, 120399, 120403, 120407, 120411, 120415, 120419, 120423, 120427, 120431, 120435, 120439, 120443, 120447, 120451, 120455, 120459, 120463, 120467, 120471, 120475, 120479, 120483, 120487, 120491, 120495, 120499, 120503, 120507, 120511, 120515, 120519, 120523, 120527, 120531, 120535, 120539, 120543, 120547, 120551, 120555, 120559, 120563, 120567, 120571, 120575, 120579, 120583, 120587, 120591, 120595, 120599, 120603, 120607, 120611, 120615, 120619, 120623, 120627, 120631, 120635, 120639, 120643, 120647, 120651, 120655, 120659, 120663, 120667, 120671, 120675, 120679, 120683, 120687, 120691, 120695, 120699, 120703, 120707, 120711, 120715, 120719, 120723, 120727, 120731, 120735, 120739, 120743, 120747, 120751, 120755, 120759, 120763, 120767, 120771, 120775, 120779, 120783, 120787, 120791, 120795, 120799, 120803, 120807, 120811, 120815, 120819, 120823, 120827, 120831, 120835, 120839, 120843, 120847, 120851, 120855, 120859, 120863, 120867, 120871, 120875, 120879, 120883, 120887, 120891, 120895, 120899, 120903, 120907, 120911, 120915, 120919, 120923, 120927, 120931, 120935, 120939, 120943, 120947, 120951, 120955, 120959, 120963, 120967, 120971, 120975, 120979, 120983, 120987, 120991, 120995, 120999, 121003, 121007, 121011, 121015, 121019, 121023, 121027, 121031, 121035, 121039, 121043, 121047, 121051, 121055, 121059, 121063, 121067, 121071, 121075, 121079, 121083, 121087, 121091, 121095, 121099, 121103, 121107, 121111, 121115, 121119, 121123, 121127, 121131, 121135, 121139, 121143, 121147, 121151, 121155, 121159, 121163, 121167, 121171, 121175, 121179, 121183, 121187, 121191, 121195, 121199, 121203, 121207, 121211, 121215, 121219, 121223, 121227, 121231, 121235, 121239, 121243, 121247, 121251, 121255, 121259, 121263, 121267, 121271, 121275, 121279, 121283, 121287, 121291, 121295, 121299, 121303, 121307, 121311, 121315, 121319, 121323, 121327, 121331, 121335, 121339, 121343}; -int b2c_idx[121344] = { 9210, 12052, 22622, 29019, 33364, 35904, 47147, 51072, 53314, 56268, 64599, 70241, 72484, 82250, 85356, 89424, 93662, 94092, 98688, 9240, 12080, 22629, 29030, 33368, 35912, 47154, 51084, 53324, 56280, 64610, 70248, 72494, 82263, 85363, 89432, 93673, 94104, 98693, 9270, 12108, 22636, 29041, 33372, 35920, 47161, 51096, 53334, 56292, 64621, 70255, 72504, 82276, 85370, 89440, 93684, 94116, 98698, 9300, 12136, 22643, 29052, 33376, 35928, 47168, 51108, 53344, 56304, 64632, 70262, 72514, 82289, 85377, 89448, 93695, 94128, 98703, 9330, 12164, 22650, 29063, 33380, 35936, 47175, 51120, 53354, 56316, 64643, 70269, 72524, 82302, 85384, 89456, 93706, 94140, 98708, 9360, 12192, 22657, 29074, 33384, 35944, 47182, 51132, 53364, 56328, 64654, 70276, 72534, 82315, 85391, 89464, 93717, 94152, 98713, 9390, 12220, 22664, 29085, 33388, 35952, 47189, 51144, 53374, 56340, 64665, 70283, 72544, 82328, 85398, 89472, 93728, 94164, 98718, 9420, 12248, 22671, 29096, 33392, 35960, 47196, 51156, 53384, 56352, 64676, 70290, 72554, 82341, 85405, 89480, 93739, 94176, 98723, 9450, 12276, 22678, 29107, 33396, 35968, 47203, 51168, 53394, 56364, 64687, 70297, 72564, 82354, 85412, 89488, 93750, 94188, 98728, 9480, 12304, 22685, 29118, 33400, 35976, 47210, 51180, 53404, 56376, 64698, 70304, 72574, 82367, 85419, 89496, 93761, 94200, 98733, 9510, 12332, 22692, 29129, 33404, 35984, 47217, 51192, 53414, 56388, 64709, 70311, 72584, 82380, 85426, 89504, 93772, 94212, 98738, 9540, 12360, 22699, 29140, 33408, 35992, 47224, 51204, 53424, 56400, 64720, 70318, 72594, 82393, 85433, 89512, 93783, 94224, 98743, 9570, 12388, 22706, 29151, 33412, 36000, 47231, 51216, 53434, 56412, 64731, 70325, 72604, 82406, 85440, 89520, 93794, 94236, 98748, 9600, 12416, 22713, 29162, 33416, 36008, 47238, 51228, 53444, 56424, 64742, 70332, 72614, 82419, 85447, 89528, 93805, 94248, 98753, 9630, 12444, 22720, 29173, 33420, 36016, 47245, 51240, 53454, 56436, 64753, 70339, 72624, 82432, 85454, 89536, 93816, 94260, 98758, 9660, 12472, 22727, 24960, 33424, 36024, 47252, 51252, 53464, 56448, 64764, 70346, 72634, 82445, 85461, 89544, 93827, 94272, 98763, 9690, 12500, 22734, 24971, 33428, 36032, 47259, 51264, 53474, 56460, 64775, 70353, 72644, 82458, 85468, 89552, 93838, 94284, 98768, 9720, 12528, 22741, 24982, 33432, 36040, 47266, 51276, 53484, 56472, 64786, 70360, 72654, 82471, 85475, 89560, 93849, 94296, 98773, 9750, 12556, 22748, 24993, 33436, 36048, 47273, 51288, 53494, 56484, 64797, 70367, 72664, 82484, 85482, 89568, 93860, 94308, 98778, 9780, 12584, 22755, 25004, 33440, 36056, 47280, 51300, 53504, 56496, 64808, 70374, 72674, 82497, 85489, 89576, 93871, 94320, 98783, 9810, 12612, 22762, 25015, 33444, 36064, 47287, 51312, 53514, 56508, 64819, 70381, 72684, 82510, 85496, 89584, 93882, 94332, 98788, 9840, 12640, 22769, 25026, 33448, 36072, 47294, 51324, 53524, 56520, 64830, 70388, 72694, 82523, 85503, 89592, 93893, 94344, 98793, 9870, 12668, 22776, 25037, 33452, 36080, 47301, 51336, 53534, 56532, 64841, 70395, 72704, 82536, 85510, 89600, 93904, 94356, 98798, 9900, 12696, 22783, 25048, 33456, 36088, 47308, 51348, 53544, 56544, 64852, 70402, 72714, 82549, 85517, 89608, 93915, 94368, 98803, 9930, 12724, 22790, 25059, 33460, 36096, 47315, 51360, 53554, 56556, 64863, 70409, 72724, 82562, 85524, 89616, 93926, 94380, 98808, 9960, 12752, 22797, 25070, 33464, 36104, 47322, 51372, 53564, 56568, 64874, 70416, 72734, 82575, 85531, 89624, 93937, 94392, 98813, 9990, 12780, 22804, 25081, 33468, 36112, 47329, 51384, 53574, 56580, 64885, 70423, 72744, 82588, 85538, 89632, 93948, 94404, 98818, 10020, 12808, 22811, 25092, 33472, 36120, 47336, 51396, 53584, 56592, 60672, 70430, 72754, 82601, 85545, 89640, 93959, 94416, 98823, 10050, 12836, 22818, 25103, 33476, 36128, 47343, 51408, 53594, 56604, 60683, 70437, 72764, 82614, 85552, 89648, 93970, 94428, 98828, 10080, 12864, 22825, 25114, 33480, 36136, 47350, 51420, 53604, 56616, 60694, 70444, 72774, 82627, 85559, 89656, 93981, 94440, 98833, 10110, 12892, 22832, 25125, 33484, 36144, 47357, 51432, 53614, 56628, 60705, 70451, 72784, 82640, 85566, 89664, 93992, 94452, 98838, 10140, 12920, 22839, 25136, 33488, 36152, 47364, 51444, 53624, 56640, 60716, 70458, 72794, 82653, 85573, 89672, 94003, 94464, 98843, 10170, 12948, 22846, 25147, 33492, 36160, 47371, 51456, 53634, 56652, 60727, 70465, 72804, 82666, 85580, 89680, 94014, 94476, 98848, 10200, 12976, 22853, 25158, 33496, 36168, 47378, 51468, 53644, 56664, 60738, 70472, 72814, 82679, 85587, 89688, 94025, 94488, 98853, 10230, 13004, 22860, 25169, 33500, 36176, 47385, 51480, 53654, 56676, 60749, 70479, 72824, 82692, 85594, 89696, 94036, 94500, 98858, 10260, 13032, 22867, 25180, 33504, 36184, 47392, 51492, 53664, 56688, 60760, 70486, 72834, 82705, 85601, 89704, 94047, 94512, 98863, 10290, 13060, 22874, 25191, 33508, 36192, 47399, 51504, 53674, 56700, 60771, 70493, 72844, 82718, 85608, 89712, 94058, 94524, 98868, 10320, 13088, 22881, 25202, 33512, 36200, 47406, 51516, 53684, 56712, 60782, 70500, 72854, 82731, 85615, 89720, 94069, 94536, 98873, 10350, 13116, 22888, 25213, 33516, 36208, 47413, 51528, 53694, 56724, 60793, 70507, 72864, 82744, 85622, 89728, 89856, 94548, 98878, 10380, 13144, 22895, 25224, 33520, 36216, 47420, 51540, 53704, 56736, 60804, 70514, 72874, 82757, 85629, 89736, 89867, 94560, 98883, 10410, 13172, 22902, 25235, 33524, 36224, 47427, 51552, 53714, 56748, 60815, 70521, 72884, 82770, 85636, 89744, 89878, 94572, 98888, 10440, 13200, 22909, 25246, 33528, 36232, 47434, 51564, 53724, 56760, 60826, 70528, 72894, 82783, 85643, 89752, 89889, 94584, 98893, 10470, 13228, 22916, 25257, 33532, 36240, 47441, 51576, 53734, 56772, 60837, 70535, 72904, 82796, 85650, 89760, 89900, 94596, 98898, 10500, 13256, 22923, 25268, 33536, 36248, 47448, 51588, 53744, 56784, 60848, 70542, 72914, 82809, 85657, 89768, 89911, 94608, 98903, 10530, 13284, 22930, 25279, 33540, 36256, 47455, 51600, 53754, 56796, 60859, 70549, 72924, 82822, 85664, 89776, 89922, 94620, 98908, 10560, 13312, 22937, 25290, 33544, 36264, 47462, 51612, 53764, 56808, 60870, 70556, 72934, 82835, 85671, 89784, 89933, 94632, 98913, 10590, 13340, 22944, 25301, 33548, 36272, 47469, 51624, 53774, 56820, 60881, 70563, 72944, 82848, 85678, 89792, 89944, 94644, 98918, 10620, 13368, 22951, 25312, 33552, 36280, 47476, 51636, 53784, 56832, 60892, 70570, 72954, 82861, 85685, 89800, 89955, 94656, 98923, 10650, 13396, 22958, 25323, 33556, 36288, 47483, 51648, 53794, 56844, 60903, 70577, 72964, 82874, 85692, 89808, 89966, 94668, 98928, 10680, 13424, 22965, 25334, 33560, 36296, 47490, 51660, 53804, 56856, 60914, 70584, 72974, 82887, 85699, 89816, 89977, 94680, 98933, 10710, 13452, 22972, 25345, 33564, 36304, 47497, 51672, 53814, 56868, 60925, 70591, 72984, 82900, 85706, 89824, 89988, 94692, 98938, 10740, 13480, 22979, 25356, 33568, 36312, 47504, 51684, 53824, 56880, 60936, 70598, 72994, 82913, 85713, 89832, 89999, 94704, 98943, 10770, 13508, 22986, 25367, 33572, 36320, 47511, 51696, 53834, 56892, 60947, 70605, 73004, 82926, 85720, 89840, 90010, 94716, 98948, 10800, 13536, 22993, 25378, 33576, 36328, 47518, 51708, 53844, 56904, 60958, 70612, 73014, 82939, 85727, 89848, 90021, 94728, 98953, 10830, 13564, 23000, 25389, 33580, 36336, 47525, 51720, 53854, 56916, 60969, 70619, 73024, 82952, 85734, 86784, 90032, 94740, 98958, 10860, 13592, 23007, 25400, 33584, 36344, 47532, 51732, 53864, 56928, 60980, 70626, 73034, 82965, 85741, 86792, 90043, 94752, 98963, 10890, 13620, 23014, 25411, 33588, 36352, 47539, 51744, 53874, 56940, 60991, 70633, 73044, 82978, 85748, 86800, 90054, 94764, 98968, 10920, 13648, 23021, 25422, 33592, 36360, 47546, 51756, 53884, 56952, 61002, 70640, 73054, 82991, 85755, 86808, 90065, 94776, 98973, 10950, 13676, 23028, 25433, 33596, 36368, 47553, 51768, 53894, 56964, 61013, 70647, 73064, 83004, 85762, 86816, 90076, 94788, 98978, 10980, 13704, 23035, 25444, 33600, 36376, 47560, 51780, 53904, 56976, 61024, 70654, 73074, 83017, 85769, 86824, 90087, 94800, 98983, 11010, 13732, 23042, 25455, 33604, 36384, 47567, 51792, 53914, 56988, 61035, 70661, 73084, 83030, 85776, 86832, 90098, 94812, 98988, 11040, 13760, 23049, 25466, 33608, 36392, 47574, 51804, 53924, 57000, 61046, 70668, 73094, 83043, 85783, 86840, 90109, 94824, 98993, 11070, 13788, 23056, 25477, 33612, 36400, 47581, 51816, 53934, 57012, 61057, 70675, 73104, 83056, 85790, 86848, 90120, 94836, 98998, 11100, 13816, 23063, 25488, 33616, 36408, 47588, 51828, 53944, 57024, 61068, 70682, 73114, 83069, 85797, 86856, 90131, 94848, 99003, 11130, 13844, 23070, 25499, 33620, 36416, 47595, 51840, 53954, 57036, 61079, 70689, 73124, 83082, 85804, 86864, 90142, 94860, 99008, 11160, 13872, 23077, 25510, 33624, 36424, 47602, 51852, 53964, 57048, 61090, 70696, 73134, 83095, 85811, 86872, 90153, 94872, 99013, 11190, 13900, 23084, 25521, 33628, 36432, 47609, 51864, 53974, 57060, 61101, 70703, 73144, 83108, 85818, 86880, 90164, 94884, 99018, 11220, 13928, 23091, 25532, 33632, 36440, 44928, 51876, 53984, 57072, 61112, 70710, 73154, 83121, 85825, 86888, 90175, 94896, 99023, 11250, 13956, 23098, 25543, 33636, 36448, 44935, 51888, 53994, 57084, 61123, 70717, 73164, 83134, 85832, 86896, 90186, 94908, 99028, 11280, 13984, 23105, 25554, 33640, 36456, 44942, 51900, 54004, 57096, 61134, 70724, 73174, 83147, 85839, 86904, 90197, 94920, 99033, 11310, 14012, 23112, 25565, 33644, 36464, 44949, 51912, 54014, 57108, 61145, 70731, 73184, 83160, 85846, 86912, 90208, 94932, 99038, 11340, 14040, 23119, 25576, 33648, 36472, 44956, 51924, 54024, 57120, 61156, 70738, 73194, 83173, 85853, 86920, 90219, 94944, 99043, 11370, 14068, 23126, 25587, 33652, 36480, 44963, 51936, 54034, 57132, 61167, 70745, 73204, 83186, 85860, 86928, 90230, 94956, 99048, 11400, 14096, 23133, 25598, 33656, 36488, 44970, 51948, 54044, 57144, 61178, 70752, 73214, 83199, 85867, 86936, 90241, 94968, 99053, 11430, 14124, 23140, 25609, 33660, 36496, 44977, 51960, 54054, 57156, 61189, 70759, 73224, 83212, 85874, 86944, 90252, 94980, 99058, 11460, 14152, 23147, 25620, 33664, 36504, 44984, 51972, 54064, 57168, 61200, 70766, 73234, 83225, 85881, 86952, 90263, 94992, 99063, 11490, 14180, 23154, 25631, 33668, 36512, 44991, 51984, 54074, 57180, 61211, 70773, 73244, 83238, 85888, 86960, 90274, 95004, 99068, 0, 14208, 23161, 25642, 33672, 36520, 44998, 51996, 54084, 57192, 61222, 70780, 73254, 83251, 85895, 86968, 90285, 95016, 99073, 30, 14236, 23168, 25653, 33676, 36528, 45005, 52008, 54094, 57204, 61233, 70787, 73264, 83264, 85902, 86976, 90296, 95028, 99078, 60, 14264, 23175, 25664, 33680, 36536, 45012, 52020, 54104, 57216, 61244, 70794, 73274, 83277, 85909, 86984, 90307, 95040, 99083, 90, 14292, 23182, 25675, 33684, 36544, 45019, 52032, 54114, 57228, 61255, 70801, 73284, 83290, 85916, 86992, 90318, 95052, 99088, 120, 14320, 23189, 25686, 33688, 36552, 45026, 52044, 54124, 57240, 61266, 70808, 73294, 83303, 85923, 87000, 90329, 95064, 99093, 150, 14348, 23196, 25697, 33692, 36560, 45033, 52056, 54134, 57252, 61277, 70815, 73304, 83316, 85930, 87008, 90340, 95076, 99098, 180, 14376, 23203, 25708, 33696, 36568, 45040, 52068, 54144, 57264, 61288, 70822, 73314, 83329, 85937, 87016, 90351, 95088, 99103, 210, 14404, 23210, 25719, 33700, 36576, 45047, 52080, 54154, 57276, 61299, 70829, 73324, 83342, 85944, 87024, 90362, 95100, 99108, 240, 14432, 23217, 25730, 33704, 36584, 45054, 52092, 54164, 57288, 61310, 70836, 73334, 83355, 85951, 87032, 90373, 95112, 99113, 270, 14460, 23224, 25741, 33708, 36592, 45061, 52104, 54174, 57300, 61321, 70843, 73344, 83368, 85958, 87040, 90384, 95124, 99118, 300, 14488, 23231, 25752, 33712, 36600, 45068, 52116, 54184, 57312, 61332, 70850, 73354, 83381, 85965, 87048, 90395, 95136, 99123, 330, 14516, 23238, 25763, 33716, 36608, 45075, 52128, 54194, 57324, 61343, 70857, 73364, 83394, 85972, 87056, 90406, 95148, 99128, 360, 14544, 23245, 25774, 33720, 36616, 45082, 52140, 54204, 57336, 61354, 70864, 73374, 83407, 85979, 87064, 90417, 95160, 99133, 390, 14572, 23252, 25785, 33724, 36624, 45089, 52152, 54214, 57348, 61365, 70871, 73384, 83420, 85986, 87072, 90428, 95172, 99138, 420, 14600, 23259, 25796, 33728, 36632, 45096, 52164, 54224, 57360, 61376, 70878, 73394, 83433, 85993, 87080, 90439, 95184, 99143, 450, 14628, 23266, 25807, 33732, 36640, 45103, 52176, 54234, 57372, 61387, 70885, 73404, 83446, 86000, 87088, 90450, 95196, 99148, 480, 14656, 23273, 25818, 33736, 36648, 45110, 52188, 54244, 57384, 61398, 70892, 73414, 83459, 86007, 87096, 90461, 95208, 99153, 510, 14684, 23280, 25829, 33740, 36656, 45117, 52200, 54254, 57396, 61409, 70899, 73424, 83472, 86014, 87104, 90472, 95220, 99158, 540, 14712, 23287, 25840, 33744, 36664, 45124, 52212, 54264, 57408, 61420, 70906, 73434, 83485, 86021, 87112, 90483, 95232, 99163, 570, 14740, 23294, 25851, 33748, 36672, 45131, 47616, 54274, 57420, 61431, 70913, 73444, 83498, 86028, 87120, 90494, 95244, 99168, 600, 14768, 23301, 25862, 33752, 36680, 45138, 47628, 54284, 57432, 61442, 70920, 73454, 83511, 86035, 87128, 90505, 95256, 99173, 630, 14796, 23308, 25873, 33756, 36688, 45145, 47640, 54294, 57444, 61453, 70927, 73464, 83524, 86042, 87136, 90516, 95268, 99178, 660, 14824, 23315, 25884, 33760, 36696, 45152, 47652, 54304, 57456, 61464, 70934, 73474, 83537, 86049, 87144, 90527, 95280, 99183, 690, 14852, 23322, 25895, 33764, 36704, 45159, 47664, 54314, 57468, 61475, 70941, 73484, 83550, 86056, 87152, 90538, 95292, 99188, 720, 14880, 23329, 25906, 33768, 36712, 45166, 47676, 54324, 57480, 61486, 70948, 73494, 83563, 86063, 87160, 90549, 95304, 99193, 750, 14908, 23336, 25917, 33772, 36720, 45173, 47688, 54334, 57492, 61497, 70955, 73504, 83576, 86070, 87168, 90560, 95316, 99198, 780, 14936, 23343, 25928, 33776, 36728, 45180, 47700, 54344, 57504, 61508, 70962, 73514, 83589, 86077, 87176, 90571, 95328, 99203, 810, 14964, 23350, 25939, 33780, 36736, 45187, 47712, 54354, 57516, 61519, 70969, 73524, 83602, 86084, 87184, 90582, 95340, 99208, 840, 14992, 23357, 25950, 33784, 36744, 45194, 47724, 54364, 57528, 61530, 70976, 73534, 83615, 86091, 87192, 90593, 95352, 99213, 870, 15020, 23364, 25961, 33788, 36752, 45201, 47736, 54374, 57540, 61541, 70983, 73544, 83628, 86098, 87200, 90604, 95364, 99218, 900, 15048, 23371, 25972, 33792, 36760, 45208, 47748, 54384, 57552, 61552, 70990, 73554, 83641, 86105, 87208, 90615, 95376, 99223, 930, 15076, 23378, 25983, 33796, 36768, 45215, 47760, 54394, 57564, 61563, 70997, 73564, 83654, 86112, 87216, 90626, 95388, 99228, 960, 15104, 23385, 25994, 33800, 36776, 45222, 47772, 54404, 57576, 61574, 71004, 73574, 83667, 86119, 87224, 90637, 95400, 99233, 990, 15132, 23392, 26005, 33804, 36784, 45229, 47784, 54414, 57588, 61585, 71011, 73584, 83680, 86126, 87232, 90648, 95412, 99238, 1020, 15160, 23399, 26016, 33808, 36792, 45236, 47796, 54424, 57600, 61596, 71018, 73594, 83693, 86133, 87240, 90659, 95424, 99243, 1050, 15188, 23406, 26027, 33812, 36800, 45243, 47808, 54434, 57612, 61607, 71025, 73604, 83706, 86140, 87248, 90670, 95436, 99248, 1080, 15216, 23413, 26038, 33816, 36808, 45250, 47820, 54444, 57624, 61618, 71032, 73614, 83719, 86147, 87256, 90681, 95448, 99253, 1110, 15244, 23420, 26049, 33820, 36816, 45257, 47832, 54454, 57636, 61629, 71039, 73624, 83732, 86154, 87264, 90692, 95460, 99258, 1140, 15272, 23427, 26060, 33824, 36824, 45264, 47844, 54464, 57648, 61640, 71046, 73634, 83745, 86161, 87272, 90703, 95472, 99263, 1170, 15300, 23434, 26071, 33828, 36832, 45271, 47856, 54474, 57660, 61651, 71053, 73644, 83758, 86168, 87280, 90714, 95484, 99268, 1200, 15328, 23441, 26082, 33832, 36840, 45278, 47868, 54484, 57672, 61662, 71060, 73654, 83771, 86175, 87288, 90725, 95496, 99273, 1230, 15356, 23448, 26093, 33836, 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45690, 96719, 120905, 809, 37547, 45697, 96731, 120906, 839, 37559, 45704, 96743, 120907, 869, 37571, 45711, 96755, 120908, 899, 37583, 45718, 96767, 120909, 929, 37595, 45725, 96779, 120910, 959, 37607, 45732, 96791, 120911, 989, 37619, 45739, 96803, 120912, 1019, 37631, 45746, 96815, 120913, 1049, 37643, 45753, 96827, 120914, 1079, 37655, 45760, 96839, 120915, 1109, 37667, 45767, 96851, 120916, 1139, 37679, 45774, 96863, 120917, 1169, 37691, 45781, 96875, 120918, 1199, 37703, 45788, 96887, 120919, 1229, 37715, 45795, 96899, 120920, 1259, 37727, 45802, 96911, 120921, 1289, 37739, 45809, 96923, 120922, 1319, 37751, 45816, 96935, 120923, 1349, 37763, 45823, 96947, 120924, 1379, 37775, 45830, 96959, 120925, 1409, 37787, 45837, 96971, 120926, 1439, 37799, 45844, 96983, 120927, 1469, 37811, 45851, 96995, 120928, 1499, 37823, 45858, 97007, 120929, 1529, 37835, 45865, 97019, 120930, 1559, 37847, 45872, 97031, 120931, 1589, 37859, 45879, 97043, 120932, 1619, 37871, 45886, 97055, 120933, 1649, 37883, 45893, 97067, 120934, 1679, 37895, 45900, 97079, 120935, 1709, 37907, 45907, 97091, 120936, 1739, 37919, 45914, 97103, 120937, 1769, 37931, 45921, 97115, 120938, 1799, 37943, 45928, 97127, 120939, 1829, 37955, 45935, 97139, 120940, 1859, 37967, 45942, 97151, 120941, 1889, 37979, 45949, 97163, 120942, 1919, 37991, 45956, 97175, 120943, 1949, 38003, 45963, 97187, 120944, 1979, 38015, 45970, 97199, 120945, 2009, 38027, 45977, 97211, 120946, 2039, 38039, 45984, 97223, 120947, 2069, 38051, 45991, 97235, 120948, 2099, 38063, 45998, 97247, 120949, 2129, 38075, 46005, 97259, 120950, 2159, 38087, 46012, 97271, 120951, 2189, 38099, 46019, 97283, 120952, 2219, 38111, 46026, 97295, 120953, 2249, 38123, 46033, 97307, 120954, 2279, 38135, 46040, 97319, 120955, 2309, 38147, 46047, 97331, 120956, 2339, 38159, 46054, 97343, 120957, 2369, 38171, 46061, 97355, 120958, 2399, 38183, 46068, 97367, 120959, 15327, 35375, 47807, 120960, 15355, 35383, 47819, 120961, 15383, 35391, 47831, 120962, 15411, 35399, 47843, 120963, 15439, 35407, 47855, 120964, 15467, 35415, 47867, 120965, 15495, 35423, 47879, 120966, 15523, 35431, 47891, 120967, 15551, 35439, 47903, 120968, 15579, 35447, 47915, 120969, 15607, 35455, 47927, 120970, 15635, 35463, 47939, 120971, 15663, 35471, 47951, 120972, 15691, 35479, 47963, 120973, 15719, 35487, 47975, 120974, 15747, 35495, 47987, 120975, 15775, 35503, 47999, 120976, 15803, 35511, 48011, 120977, 15831, 35519, 48023, 120978, 15859, 35527, 48035, 120979, 15887, 35535, 48047, 120980, 15915, 35543, 48059, 120981, 15943, 35551, 48071, 120982, 15971, 35559, 48083, 120983, 15999, 35567, 48095, 120984, 16027, 35575, 48107, 120985, 16055, 35583, 48119, 120986, 16083, 35591, 48131, 120987, 16111, 35599, 48143, 120988, 16139, 35607, 48155, 120989, 16167, 35615, 48167, 120990, 16195, 35623, 48179, 120991, 16223, 35631, 48191, 120992, 16251, 35639, 48203, 120993, 16279, 35647, 48215, 120994, 16307, 35655, 48227, 120995, 16335, 35663, 48239, 120996, 16363, 35671, 48251, 120997, 16391, 35679, 48263, 120998, 16419, 35687, 48275, 120999, 16447, 35695, 48287, 121000, 16475, 35703, 48299, 121001, 16503, 35711, 48311, 121002, 16531, 35719, 48323, 121003, 16559, 35727, 48335, 121004, 16587, 35735, 48347, 121005, 16615, 35743, 48359, 121006, 16643, 35751, 48371, 121007, 16671, 35759, 48383, 121008, 16699, 35767, 48395, 121009, 16727, 35775, 48407, 121010, 16755, 35783, 48419, 121011, 16783, 35791, 48431, 121012, 16811, 35799, 48443, 121013, 16839, 35807, 48455, 121014, 16867, 35815, 48467, 121015, 16895, 35823, 48479, 121016, 16923, 35831, 48491, 121017, 16951, 35839, 48503, 121018, 16979, 35847, 48515, 121019, 17007, 35855, 48527, 121020, 17035, 35863, 48539, 121021, 17063, 35871, 48551, 121022, 17091, 35879, 48563, 121023, 17119, 35887, 48575, 121024, 17147, 35895, 48587, 121025, 17175, 35903, 48599, 121026, 17203, 35911, 48611, 121027, 17231, 35919, 48623, 121028, 17259, 35927, 48635, 121029, 17287, 35935, 48647, 121030, 17315, 35943, 48659, 121031, 17343, 35951, 48671, 121032, 17371, 35959, 48683, 121033, 17399, 35967, 48695, 121034, 17427, 35975, 48707, 121035, 17455, 35983, 48719, 121036, 17483, 35991, 48731, 121037, 17511, 35999, 48743, 121038, 17539, 36007, 48755, 121039, 17567, 36015, 48767, 121040, 17595, 36023, 48779, 121041, 17623, 36031, 48791, 121042, 17651, 36039, 48803, 121043, 17679, 36047, 48815, 121044, 17707, 36055, 48827, 121045, 17735, 36063, 48839, 121046, 17763, 36071, 48851, 121047, 17791, 36079, 48863, 121048, 17819, 36087, 48875, 121049, 17847, 36095, 48887, 121050, 17875, 36103, 48899, 121051, 17903, 36111, 48911, 121052, 17931, 36119, 48923, 121053, 17959, 36127, 48935, 121054, 17987, 36135, 48947, 121055, 18015, 36143, 48959, 121056, 18043, 36151, 48971, 121057, 18071, 36159, 48983, 121058, 18099, 36167, 48995, 121059, 18127, 36175, 49007, 121060, 18155, 36183, 49019, 121061, 18183, 36191, 49031, 121062, 18211, 36199, 49043, 121063, 18239, 36207, 49055, 121064, 18267, 36215, 49067, 121065, 18295, 36223, 49079, 121066, 18323, 36231, 49091, 121067, 18351, 36239, 49103, 121068, 18379, 36247, 49115, 121069, 18407, 36255, 49127, 121070, 18435, 36263, 49139, 121071, 18463, 36271, 49151, 121072, 18491, 36279, 49163, 121073, 18519, 36287, 49175, 121074, 18547, 36295, 49187, 121075, 18575, 36303, 49199, 121076, 18603, 36311, 49211, 121077, 18631, 36319, 49223, 121078, 18659, 36327, 49235, 121079, 18687, 36335, 49247, 121080, 18715, 36343, 49259, 121081, 18743, 36351, 49271, 121082, 18771, 36359, 49283, 121083, 18799, 36367, 49295, 121084, 18827, 36375, 49307, 121085, 18855, 36383, 49319, 121086, 18883, 36391, 49331, 121087, 18911, 36399, 49343, 121088, 18939, 36407, 49355, 121089, 18967, 36415, 49367, 121090, 18995, 36423, 49379, 121091, 19023, 36431, 49391, 121092, 19051, 36439, 49403, 121093, 19079, 36447, 49415, 121094, 19107, 36455, 49427, 121095, 19135, 36463, 49439, 121096, 19163, 36471, 49451, 121097, 19191, 36479, 49463, 121098, 19219, 36487, 49475, 121099, 19247, 36495, 49487, 121100, 19275, 36503, 49499, 121101, 19303, 36511, 49511, 121102, 19331, 36519, 49523, 121103, 19359, 36527, 49535, 121104, 19387, 36535, 49547, 121105, 19415, 36543, 49559, 121106, 19443, 36551, 49571, 121107, 19471, 36559, 49583, 121108, 19499, 36567, 49595, 121109, 19527, 36575, 49607, 121110, 19555, 36583, 49619, 121111, 19583, 36591, 49631, 121112, 19611, 36599, 49643, 121113, 19639, 36607, 49655, 121114, 19667, 36615, 49667, 121115, 19695, 36623, 49679, 121116, 19723, 36631, 49691, 121117, 19751, 36639, 49703, 121118, 19779, 36647, 49715, 121119, 19807, 36655, 49727, 121120, 19835, 36663, 49739, 121121, 19863, 36671, 49751, 121122, 19891, 36679, 49763, 121123, 19919, 36687, 49775, 121124, 19947, 36695, 49787, 121125, 19975, 36703, 49799, 121126, 20003, 36711, 49811, 121127, 20031, 36719, 49823, 121128, 20059, 36727, 49835, 121129, 20087, 36735, 49847, 121130, 20115, 36743, 49859, 121131, 20143, 36751, 49871, 121132, 20171, 36759, 49883, 121133, 20199, 36767, 49895, 121134, 20227, 36775, 49907, 121135, 20255, 36783, 49919, 121136, 20283, 36791, 49931, 121137, 20311, 36799, 49943, 121138, 20339, 36807, 49955, 121139, 20367, 36815, 49967, 121140, 20395, 36823, 49979, 121141, 20423, 36831, 49991, 121142, 20451, 36839, 50003, 121143, 20479, 36847, 50015, 121144, 20507, 36855, 50027, 121145, 20535, 36863, 50039, 121146, 20563, 36871, 50051, 121147, 20591, 36879, 50063, 121148, 20619, 36887, 50075, 121149, 20647, 36895, 50087, 121150, 20675, 36903, 50099, 121151, 20703, 36911, 50111, 121152, 20731, 36919, 50123, 121153, 20759, 36927, 50135, 121154, 20787, 36935, 50147, 121155, 20815, 36943, 50159, 121156, 20843, 36951, 50171, 121157, 20871, 36959, 50183, 121158, 20899, 36967, 50195, 121159, 20927, 36975, 50207, 121160, 20955, 36983, 50219, 121161, 20983, 36991, 50231, 121162, 21011, 36999, 50243, 121163, 21039, 37007, 50255, 121164, 21067, 37015, 50267, 121165, 21095, 37023, 50279, 121166, 21123, 37031, 50291, 121167, 21151, 37039, 50303, 121168, 21179, 37047, 50315, 121169, 21207, 37055, 50327, 121170, 21235, 37063, 50339, 121171, 21263, 37071, 50351, 121172, 21291, 37079, 50363, 121173, 21319, 37087, 50375, 121174, 21347, 37095, 50387, 121175, 21375, 37103, 50399, 121176, 21403, 37111, 50411, 121177, 21431, 37119, 50423, 121178, 21459, 37127, 50435, 121179, 21487, 37135, 50447, 121180, 21515, 37143, 50459, 121181, 21543, 37151, 50471, 121182, 21571, 37159, 50483, 121183, 21599, 37167, 50495, 121184, 21627, 37175, 50507, 121185, 21655, 37183, 50519, 121186, 21683, 37191, 50531, 121187, 21711, 37199, 50543, 121188, 21739, 37207, 50555, 121189, 21767, 37215, 50567, 121190, 21795, 37223, 50579, 121191, 21823, 37231, 50591, 121192, 21851, 37239, 50603, 121193, 21879, 37247, 50615, 121194, 21907, 34183, 50627, 121195, 21935, 34191, 50639, 121196, 21963, 34199, 50651, 121197, 21991, 34207, 50663, 121198, 22019, 34215, 50675, 121199, 22047, 34223, 50687, 121200, 22075, 34231, 50699, 121201, 22103, 34239, 50711, 121202, 22131, 34247, 50723, 121203, 22159, 34255, 50735, 121204, 22187, 34263, 50747, 121205, 22215, 34271, 50759, 121206, 22243, 34279, 50771, 121207, 22271, 34287, 50783, 121208, 11547, 34295, 50795, 121209, 11575, 34303, 50807, 121210, 11603, 34311, 50819, 121211, 11631, 34319, 50831, 121212, 11659, 34327, 50843, 121213, 11687, 34335, 50855, 121214, 11715, 34343, 50867, 121215, 11743, 34351, 50879, 121216, 11771, 34359, 50891, 121217, 11799, 34367, 50903, 121218, 11827, 34375, 50915, 121219, 11855, 34383, 50927, 121220, 11883, 34391, 50939, 121221, 11911, 34399, 50951, 121222, 11939, 34407, 50963, 121223, 11967, 34415, 50975, 121224, 11995, 34423, 50987, 121225, 12023, 34431, 50999, 121226, 12051, 34439, 51011, 121227, 12079, 34447, 51023, 121228, 12107, 34455, 51035, 121229, 12135, 34463, 51047, 121230, 12163, 34471, 51059, 121231, 12191, 34479, 51071, 121232, 12219, 34487, 51083, 121233, 12247, 34495, 51095, 121234, 12275, 34503, 51107, 121235, 12303, 34511, 51119, 121236, 12331, 34519, 51131, 121237, 12359, 34527, 51143, 121238, 12387, 34535, 51155, 121239, 12415, 34543, 51167, 121240, 12443, 34551, 51179, 121241, 12471, 34559, 51191, 121242, 12499, 34567, 51203, 121243, 12527, 34575, 51215, 121244, 12555, 34583, 51227, 121245, 12583, 34591, 51239, 121246, 12611, 34599, 51251, 121247, 12639, 34607, 51263, 121248, 12667, 34615, 51275, 121249, 12695, 34623, 51287, 121250, 12723, 34631, 51299, 121251, 12751, 34639, 51311, 121252, 12779, 34647, 51323, 121253, 12807, 34655, 51335, 121254, 12835, 34663, 51347, 121255, 12863, 34671, 51359, 121256, 12891, 34679, 51371, 121257, 12919, 34687, 51383, 121258, 12947, 34695, 51395, 121259, 12975, 34703, 51407, 121260, 13003, 34711, 51419, 121261, 13031, 34719, 51431, 121262, 13059, 34727, 51443, 121263, 13087, 34735, 51455, 121264, 13115, 34743, 51467, 121265, 13143, 34751, 51479, 121266, 13171, 34759, 51491, 121267, 13199, 34767, 51503, 121268, 13227, 34775, 51515, 121269, 13255, 34783, 51527, 121270, 13283, 34791, 51539, 121271, 13311, 34799, 51551, 121272, 13339, 34807, 51563, 121273, 13367, 34815, 51575, 121274, 13395, 34823, 51587, 121275, 13423, 34831, 51599, 121276, 13451, 34839, 51611, 121277, 13479, 34847, 51623, 121278, 13507, 34855, 51635, 121279, 13535, 34863, 51647, 121280, 13563, 34871, 51659, 121281, 13591, 34879, 51671, 121282, 13619, 34887, 51683, 121283, 13647, 34895, 51695, 121284, 13675, 34903, 51707, 121285, 13703, 34911, 51719, 121286, 13731, 34919, 51731, 121287, 13759, 34927, 51743, 121288, 13787, 34935, 51755, 121289, 13815, 34943, 51767, 121290, 13843, 34951, 51779, 121291, 13871, 34959, 51791, 121292, 13899, 34967, 51803, 121293, 13927, 34975, 51815, 121294, 13955, 34983, 51827, 121295, 13983, 34991, 51839, 121296, 14011, 34999, 51851, 121297, 14039, 35007, 51863, 121298, 14067, 35015, 51875, 121299, 14095, 35023, 51887, 121300, 14123, 35031, 51899, 121301, 14151, 35039, 51911, 121302, 14179, 35047, 51923, 121303, 14207, 35055, 51935, 121304, 14235, 35063, 51947, 121305, 14263, 35071, 51959, 121306, 14291, 35079, 51971, 121307, 14319, 35087, 51983, 121308, 14347, 35095, 51995, 121309, 14375, 35103, 52007, 121310, 14403, 35111, 52019, 121311, 14431, 35119, 52031, 121312, 14459, 35127, 52043, 121313, 14487, 35135, 52055, 121314, 14515, 35143, 52067, 121315, 14543, 35151, 52079, 121316, 14571, 35159, 52091, 121317, 14599, 35167, 52103, 121318, 14627, 35175, 52115, 121319, 14655, 35183, 52127, 121320, 14683, 35191, 52139, 121321, 14711, 35199, 52151, 121322, 14739, 35207, 52163, 121323, 14767, 35215, 52175, 121324, 14795, 35223, 52187, 121325, 14823, 35231, 52199, 121326, 14851, 35239, 52211, 121327, 14879, 35247, 52223, 121328, 14907, 35255, 47627, 121329, 14935, 35263, 47639, 121330, 14963, 35271, 47651, 121331, 14991, 35279, 47663, 121332, 15019, 35287, 47675, 121333, 15047, 35295, 47687, 121334, 15075, 35303, 47699, 121335, 15103, 35311, 47711, 121336, 15131, 35319, 47723, 121337, 15159, 35327, 47735, 121338, 15187, 35335, 47747, 121339, 15215, 35343, 47759, 121340, 15243, 35351, 47771, 121341, 15271, 35359, 47783, 121342, 15299, 35367, 47795, 121343}; -int cnproc_start_idx[121344] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 209, 209, 209, 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119558, 119558, 119563, 119563, 119563, 119563, 119563, 119568, 119568, 119568, 119568, 119568, 119573, 119573, 119573, 119573, 119573, 119578, 119578, 119578, 119578, 119578, 119583, 119583, 119583, 119583, 119583, 119588, 119588, 119588, 119588, 119588, 119593, 119593, 119593, 119593, 119593, 119598, 119598, 119598, 119598, 119598, 119603, 119603, 119603, 119603, 119603, 119608, 119608, 119608, 119608, 119608, 119613, 119613, 119613, 119613, 119613, 119618, 119618, 119618, 119618, 119618, 119623, 119623, 119623, 119623, 119623, 119628, 119628, 119628, 119628, 119628, 119633, 119633, 119633, 119633, 119633, 119638, 119638, 119638, 119638, 119638, 119643, 119643, 119643, 119643, 119643, 119648, 119648, 119648, 119648, 119648, 119653, 119653, 119653, 119653, 119653, 119658, 119658, 119658, 119658, 119658, 119663, 119663, 119663, 119663, 119663, 119668, 119668, 119668, 119668, 119668, 119673, 119673, 119673, 119673, 119673, 119678, 119678, 119678, 119678, 119678, 119683, 119683, 119683, 119683, 119683, 119688, 119688, 119688, 119688, 119688, 119693, 119693, 119693, 119693, 119693, 119698, 119698, 119698, 119698, 119698, 119703, 119703, 119703, 119703, 119703, 119708, 119708, 119708, 119708, 119708, 119713, 119713, 119713, 119713, 119713, 119718, 119718, 119718, 119718, 119718, 119723, 119723, 119723, 119723, 119723, 119728, 119728, 119728, 119728, 119728, 119733, 119733, 119733, 119733, 119733, 119738, 119738, 119738, 119738, 119738, 119743, 119743, 119743, 119743, 119743, 119748, 119748, 119748, 119748, 119748, 119753, 119753, 119753, 119753, 119753, 119758, 119758, 119758, 119758, 119758, 119763, 119763, 119763, 119763, 119763, 119768, 119768, 119768, 119768, 119768, 119773, 119773, 119773, 119773, 119773, 119778, 119778, 119778, 119778, 119778, 119783, 119783, 119783, 119783, 119783, 119788, 119788, 119788, 119788, 119788, 119793, 119793, 119793, 119793, 119793, 119798, 119798, 119798, 119798, 119798, 119803, 119803, 119803, 119803, 119803, 119808, 119808, 119808, 119808, 119812, 119812, 119812, 119812, 119816, 119816, 119816, 119816, 119820, 119820, 119820, 119820, 119824, 119824, 119824, 119824, 119828, 119828, 119828, 119828, 119832, 119832, 119832, 119832, 119836, 119836, 119836, 119836, 119840, 119840, 119840, 119840, 119844, 119844, 119844, 119844, 119848, 119848, 119848, 119848, 119852, 119852, 119852, 119852, 119856, 119856, 119856, 119856, 119860, 119860, 119860, 119860, 119864, 119864, 119864, 119864, 119868, 119868, 119868, 119868, 119872, 119872, 119872, 119872, 119876, 119876, 119876, 119876, 119880, 119880, 119880, 119880, 119884, 119884, 119884, 119884, 119888, 119888, 119888, 119888, 119892, 119892, 119892, 119892, 119896, 119896, 119896, 119896, 119900, 119900, 119900, 119900, 119904, 119904, 119904, 119904, 119908, 119908, 119908, 119908, 119912, 119912, 119912, 119912, 119916, 119916, 119916, 119916, 119920, 119920, 119920, 119920, 119924, 119924, 119924, 119924, 119928, 119928, 119928, 119928, 119932, 119932, 119932, 119932, 119936, 119936, 119936, 119936, 119940, 119940, 119940, 119940, 119944, 119944, 119944, 119944, 119948, 119948, 119948, 119948, 119952, 119952, 119952, 119952, 119956, 119956, 119956, 119956, 119960, 119960, 119960, 119960, 119964, 119964, 119964, 119964, 119968, 119968, 119968, 119968, 119972, 119972, 119972, 119972, 119976, 119976, 119976, 119976, 119980, 119980, 119980, 119980, 119984, 119984, 119984, 119984, 119988, 119988, 119988, 119988, 119992, 119992, 119992, 119992, 119996, 119996, 119996, 119996, 120000, 120000, 120000, 120000, 120004, 120004, 120004, 120004, 120008, 120008, 120008, 120008, 120012, 120012, 120012, 120012, 120016, 120016, 120016, 120016, 120020, 120020, 120020, 120020, 120024, 120024, 120024, 120024, 120028, 120028, 120028, 120028, 120032, 120032, 120032, 120032, 120036, 120036, 120036, 120036, 120040, 120040, 120040, 120040, 120044, 120044, 120044, 120044, 120048, 120048, 120048, 120048, 120052, 120052, 120052, 120052, 120056, 120056, 120056, 120056, 120060, 120060, 120060, 120060, 120064, 120064, 120064, 120064, 120068, 120068, 120068, 120068, 120072, 120072, 120072, 120072, 120076, 120076, 120076, 120076, 120080, 120080, 120080, 120080, 120084, 120084, 120084, 120084, 120088, 120088, 120088, 120088, 120092, 120092, 120092, 120092, 120096, 120096, 120096, 120096, 120100, 120100, 120100, 120100, 120104, 120104, 120104, 120104, 120108, 120108, 120108, 120108, 120112, 120112, 120112, 120112, 120116, 120116, 120116, 120116, 120120, 120120, 120120, 120120, 120124, 120124, 120124, 120124, 120128, 120128, 120128, 120128, 120132, 120132, 120132, 120132, 120136, 120136, 120136, 120136, 120140, 120140, 120140, 120140, 120144, 120144, 120144, 120144, 120148, 120148, 120148, 120148, 120152, 120152, 120152, 120152, 120156, 120156, 120156, 120156, 120160, 120160, 120160, 120160, 120164, 120164, 120164, 120164, 120168, 120168, 120168, 120168, 120172, 120172, 120172, 120172, 120176, 120176, 120176, 120176, 120180, 120180, 120180, 120180, 120184, 120184, 120184, 120184, 120188, 120188, 120188, 120188, 120192, 120192, 120192, 120192, 120196, 120196, 120196, 120196, 120200, 120200, 120200, 120200, 120204, 120204, 120204, 120204, 120208, 120208, 120208, 120208, 120212, 120212, 120212, 120212, 120216, 120216, 120216, 120216, 120220, 120220, 120220, 120220, 120224, 120224, 120224, 120224, 120228, 120228, 120228, 120228, 120232, 120232, 120232, 120232, 120236, 120236, 120236, 120236, 120240, 120240, 120240, 120240, 120244, 120244, 120244, 120244, 120248, 120248, 120248, 120248, 120252, 120252, 120252, 120252, 120256, 120256, 120256, 120256, 120260, 120260, 120260, 120260, 120264, 120264, 120264, 120264, 120268, 120268, 120268, 120268, 120272, 120272, 120272, 120272, 120276, 120276, 120276, 120276, 120280, 120280, 120280, 120280, 120284, 120284, 120284, 120284, 120288, 120288, 120288, 120288, 120292, 120292, 120292, 120292, 120296, 120296, 120296, 120296, 120300, 120300, 120300, 120300, 120304, 120304, 120304, 120304, 120308, 120308, 120308, 120308, 120312, 120312, 120312, 120312, 120316, 120316, 120316, 120316, 120320, 120320, 120320, 120320, 120324, 120324, 120324, 120324, 120328, 120328, 120328, 120328, 120332, 120332, 120332, 120332, 120336, 120336, 120336, 120336, 120340, 120340, 120340, 120340, 120344, 120344, 120344, 120344, 120348, 120348, 120348, 120348, 120352, 120352, 120352, 120352, 120356, 120356, 120356, 120356, 120360, 120360, 120360, 120360, 120364, 120364, 120364, 120364, 120368, 120368, 120368, 120368, 120372, 120372, 120372, 120372, 120376, 120376, 120376, 120376, 120380, 120380, 120380, 120380, 120384, 120384, 120384, 120384, 120388, 120388, 120388, 120388, 120392, 120392, 120392, 120392, 120396, 120396, 120396, 120396, 120400, 120400, 120400, 120400, 120404, 120404, 120404, 120404, 120408, 120408, 120408, 120408, 120412, 120412, 120412, 120412, 120416, 120416, 120416, 120416, 120420, 120420, 120420, 120420, 120424, 120424, 120424, 120424, 120428, 120428, 120428, 120428, 120432, 120432, 120432, 120432, 120436, 120436, 120436, 120436, 120440, 120440, 120440, 120440, 120444, 120444, 120444, 120444, 120448, 120448, 120448, 120448, 120452, 120452, 120452, 120452, 120456, 120456, 120456, 120456, 120460, 120460, 120460, 120460, 120464, 120464, 120464, 120464, 120468, 120468, 120468, 120468, 120472, 120472, 120472, 120472, 120476, 120476, 120476, 120476, 120480, 120480, 120480, 120480, 120484, 120484, 120484, 120484, 120488, 120488, 120488, 120488, 120492, 120492, 120492, 120492, 120496, 120496, 120496, 120496, 120500, 120500, 120500, 120500, 120504, 120504, 120504, 120504, 120508, 120508, 120508, 120508, 120512, 120512, 120512, 120512, 120516, 120516, 120516, 120516, 120520, 120520, 120520, 120520, 120524, 120524, 120524, 120524, 120528, 120528, 120528, 120528, 120532, 120532, 120532, 120532, 120536, 120536, 120536, 120536, 120540, 120540, 120540, 120540, 120544, 120544, 120544, 120544, 120548, 120548, 120548, 120548, 120552, 120552, 120552, 120552, 120556, 120556, 120556, 120556, 120560, 120560, 120560, 120560, 120564, 120564, 120564, 120564, 120568, 120568, 120568, 120568, 120572, 120572, 120572, 120572, 120576, 120576, 120576, 120576, 120580, 120580, 120580, 120580, 120584, 120584, 120584, 120584, 120588, 120588, 120588, 120588, 120592, 120592, 120592, 120592, 120596, 120596, 120596, 120596, 120600, 120600, 120600, 120600, 120604, 120604, 120604, 120604, 120608, 120608, 120608, 120608, 120612, 120612, 120612, 120612, 120616, 120616, 120616, 120616, 120620, 120620, 120620, 120620, 120624, 120624, 120624, 120624, 120628, 120628, 120628, 120628, 120632, 120632, 120632, 120632, 120636, 120636, 120636, 120636, 120640, 120640, 120640, 120640, 120644, 120644, 120644, 120644, 120648, 120648, 120648, 120648, 120652, 120652, 120652, 120652, 120656, 120656, 120656, 120656, 120660, 120660, 120660, 120660, 120664, 120664, 120664, 120664, 120668, 120668, 120668, 120668, 120672, 120672, 120672, 120672, 120676, 120676, 120676, 120676, 120680, 120680, 120680, 120680, 120684, 120684, 120684, 120684, 120688, 120688, 120688, 120688, 120692, 120692, 120692, 120692, 120696, 120696, 120696, 120696, 120700, 120700, 120700, 120700, 120704, 120704, 120704, 120704, 120708, 120708, 120708, 120708, 120712, 120712, 120712, 120712, 120716, 120716, 120716, 120716, 120720, 120720, 120720, 120720, 120724, 120724, 120724, 120724, 120728, 120728, 120728, 120728, 120732, 120732, 120732, 120732, 120736, 120736, 120736, 120736, 120740, 120740, 120740, 120740, 120744, 120744, 120744, 120744, 120748, 120748, 120748, 120748, 120752, 120752, 120752, 120752, 120756, 120756, 120756, 120756, 120760, 120760, 120760, 120760, 120764, 120764, 120764, 120764, 120768, 120768, 120768, 120768, 120772, 120772, 120772, 120772, 120776, 120776, 120776, 120776, 120780, 120780, 120780, 120780, 120784, 120784, 120784, 120784, 120788, 120788, 120788, 120788, 120792, 120792, 120792, 120792, 120796, 120796, 120796, 120796, 120800, 120800, 120800, 120800, 120804, 120804, 120804, 120804, 120808, 120808, 120808, 120808, 120812, 120812, 120812, 120812, 120816, 120816, 120816, 120816, 120820, 120820, 120820, 120820, 120824, 120824, 120824, 120824, 120828, 120828, 120828, 120828, 120832, 120832, 120832, 120832, 120836, 120836, 120836, 120836, 120840, 120840, 120840, 120840, 120844, 120844, 120844, 120844, 120848, 120848, 120848, 120848, 120852, 120852, 120852, 120852, 120856, 120856, 120856, 120856, 120860, 120860, 120860, 120860, 120864, 120864, 120864, 120864, 120868, 120868, 120868, 120868, 120872, 120872, 120872, 120872, 120876, 120876, 120876, 120876, 120880, 120880, 120880, 120880, 120884, 120884, 120884, 120884, 120888, 120888, 120888, 120888, 120892, 120892, 120892, 120892, 120896, 120896, 120896, 120896, 120900, 120900, 120900, 120900, 120904, 120904, 120904, 120904, 120908, 120908, 120908, 120908, 120912, 120912, 120912, 120912, 120916, 120916, 120916, 120916, 120920, 120920, 120920, 120920, 120924, 120924, 120924, 120924, 120928, 120928, 120928, 120928, 120932, 120932, 120932, 120932, 120936, 120936, 120936, 120936, 120940, 120940, 120940, 120940, 120944, 120944, 120944, 120944, 120948, 120948, 120948, 120948, 120952, 120952, 120952, 120952, 120956, 120956, 120956, 120956, 120960, 120960, 120960, 120960, 120964, 120964, 120964, 120964, 120968, 120968, 120968, 120968, 120972, 120972, 120972, 120972, 120976, 120976, 120976, 120976, 120980, 120980, 120980, 120980, 120984, 120984, 120984, 120984, 120988, 120988, 120988, 120988, 120992, 120992, 120992, 120992, 120996, 120996, 120996, 120996, 121000, 121000, 121000, 121000, 121004, 121004, 121004, 121004, 121008, 121008, 121008, 121008, 121012, 121012, 121012, 121012, 121016, 121016, 121016, 121016, 121020, 121020, 121020, 121020, 121024, 121024, 121024, 121024, 121028, 121028, 121028, 121028, 121032, 121032, 121032, 121032, 121036, 121036, 121036, 121036, 121040, 121040, 121040, 121040, 121044, 121044, 121044, 121044, 121048, 121048, 121048, 121048, 121052, 121052, 121052, 121052, 121056, 121056, 121056, 121056, 121060, 121060, 121060, 121060, 121064, 121064, 121064, 121064, 121068, 121068, 121068, 121068, 121072, 121072, 121072, 121072, 121076, 121076, 121076, 121076, 121080, 121080, 121080, 121080, 121084, 121084, 121084, 121084, 121088, 121088, 121088, 121088, 121092, 121092, 121092, 121092, 121096, 121096, 121096, 121096, 121100, 121100, 121100, 121100, 121104, 121104, 121104, 121104, 121108, 121108, 121108, 121108, 121112, 121112, 121112, 121112, 121116, 121116, 121116, 121116, 121120, 121120, 121120, 121120, 121124, 121124, 121124, 121124, 121128, 121128, 121128, 121128, 121132, 121132, 121132, 121132, 121136, 121136, 121136, 121136, 121140, 121140, 121140, 121140, 121144, 121144, 121144, 121144, 121148, 121148, 121148, 121148, 121152, 121152, 121152, 121152, 121156, 121156, 121156, 121156, 121160, 121160, 121160, 121160, 121164, 121164, 121164, 121164, 121168, 121168, 121168, 121168, 121172, 121172, 121172, 121172, 121176, 121176, 121176, 121176, 121180, 121180, 121180, 121180, 121184, 121184, 121184, 121184, 121188, 121188, 121188, 121188, 121192, 121192, 121192, 121192, 121196, 121196, 121196, 121196, 121200, 121200, 121200, 121200, 121204, 121204, 121204, 121204, 121208, 121208, 121208, 121208, 121212, 121212, 121212, 121212, 121216, 121216, 121216, 121216, 121220, 121220, 121220, 121220, 121224, 121224, 121224, 121224, 121228, 121228, 121228, 121228, 121232, 121232, 121232, 121232, 121236, 121236, 121236, 121236, 121240, 121240, 121240, 121240, 121244, 121244, 121244, 121244, 121248, 121248, 121248, 121248, 121252, 121252, 121252, 121252, 121256, 121256, 121256, 121256, 121260, 121260, 121260, 121260, 121264, 121264, 121264, 121264, 121268, 121268, 121268, 121268, 121272, 121272, 121272, 121272, 121276, 121276, 121276, 121276, 121280, 121280, 121280, 121280, 121284, 121284, 121284, 121284, 121288, 121288, 121288, 121288, 121292, 121292, 121292, 121292, 121296, 121296, 121296, 121296, 121300, 121300, 121300, 121300, 121304, 121304, 121304, 121304, 121308, 121308, 121308, 121308, 121312, 121312, 121312, 121312, 121316, 121316, 121316, 121316, 121320, 121320, 121320, 121320, 121324, 121324, 121324, 121324, 121328, 121328, 121328, 121328, 121332, 121332, 121332, 121332, 121336, 121336, 121336, 121336, 121340, 121340, 121340, 121340}; -int cnproc_end_idx[121344] = { 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 114, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 152, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 190, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 228, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 266, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 304, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 323, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 361, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 380, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 399, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 418, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 456, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 475, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 494, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 513, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 532, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 551, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 589, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 608, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 627, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 646, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 665, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 684, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 703, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 722, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 741, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 760, 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119778, 119778, 119778, 119778, 119778, 119783, 119783, 119783, 119783, 119783, 119788, 119788, 119788, 119788, 119788, 119793, 119793, 119793, 119793, 119793, 119798, 119798, 119798, 119798, 119798, 119803, 119803, 119803, 119803, 119803, 119808, 119808, 119808, 119808, 119808, 119812, 119812, 119812, 119812, 119816, 119816, 119816, 119816, 119820, 119820, 119820, 119820, 119824, 119824, 119824, 119824, 119828, 119828, 119828, 119828, 119832, 119832, 119832, 119832, 119836, 119836, 119836, 119836, 119840, 119840, 119840, 119840, 119844, 119844, 119844, 119844, 119848, 119848, 119848, 119848, 119852, 119852, 119852, 119852, 119856, 119856, 119856, 119856, 119860, 119860, 119860, 119860, 119864, 119864, 119864, 119864, 119868, 119868, 119868, 119868, 119872, 119872, 119872, 119872, 119876, 119876, 119876, 119876, 119880, 119880, 119880, 119880, 119884, 119884, 119884, 119884, 119888, 119888, 119888, 119888, 119892, 119892, 119892, 119892, 119896, 119896, 119896, 119896, 119900, 119900, 119900, 119900, 119904, 119904, 119904, 119904, 119908, 119908, 119908, 119908, 119912, 119912, 119912, 119912, 119916, 119916, 119916, 119916, 119920, 119920, 119920, 119920, 119924, 119924, 119924, 119924, 119928, 119928, 119928, 119928, 119932, 119932, 119932, 119932, 119936, 119936, 119936, 119936, 119940, 119940, 119940, 119940, 119944, 119944, 119944, 119944, 119948, 119948, 119948, 119948, 119952, 119952, 119952, 119952, 119956, 119956, 119956, 119956, 119960, 119960, 119960, 119960, 119964, 119964, 119964, 119964, 119968, 119968, 119968, 119968, 119972, 119972, 119972, 119972, 119976, 119976, 119976, 119976, 119980, 119980, 119980, 119980, 119984, 119984, 119984, 119984, 119988, 119988, 119988, 119988, 119992, 119992, 119992, 119992, 119996, 119996, 119996, 119996, 120000, 120000, 120000, 120000, 120004, 120004, 120004, 120004, 120008, 120008, 120008, 120008, 120012, 120012, 120012, 120012, 120016, 120016, 120016, 120016, 120020, 120020, 120020, 120020, 120024, 120024, 120024, 120024, 120028, 120028, 120028, 120028, 120032, 120032, 120032, 120032, 120036, 120036, 120036, 120036, 120040, 120040, 120040, 120040, 120044, 120044, 120044, 120044, 120048, 120048, 120048, 120048, 120052, 120052, 120052, 120052, 120056, 120056, 120056, 120056, 120060, 120060, 120060, 120060, 120064, 120064, 120064, 120064, 120068, 120068, 120068, 120068, 120072, 120072, 120072, 120072, 120076, 120076, 120076, 120076, 120080, 120080, 120080, 120080, 120084, 120084, 120084, 120084, 120088, 120088, 120088, 120088, 120092, 120092, 120092, 120092, 120096, 120096, 120096, 120096, 120100, 120100, 120100, 120100, 120104, 120104, 120104, 120104, 120108, 120108, 120108, 120108, 120112, 120112, 120112, 120112, 120116, 120116, 120116, 120116, 120120, 120120, 120120, 120120, 120124, 120124, 120124, 120124, 120128, 120128, 120128, 120128, 120132, 120132, 120132, 120132, 120136, 120136, 120136, 120136, 120140, 120140, 120140, 120140, 120144, 120144, 120144, 120144, 120148, 120148, 120148, 120148, 120152, 120152, 120152, 120152, 120156, 120156, 120156, 120156, 120160, 120160, 120160, 120160, 120164, 120164, 120164, 120164, 120168, 120168, 120168, 120168, 120172, 120172, 120172, 120172, 120176, 120176, 120176, 120176, 120180, 120180, 120180, 120180, 120184, 120184, 120184, 120184, 120188, 120188, 120188, 120188, 120192, 120192, 120192, 120192, 120196, 120196, 120196, 120196, 120200, 120200, 120200, 120200, 120204, 120204, 120204, 120204, 120208, 120208, 120208, 120208, 120212, 120212, 120212, 120212, 120216, 120216, 120216, 120216, 120220, 120220, 120220, 120220, 120224, 120224, 120224, 120224, 120228, 120228, 120228, 120228, 120232, 120232, 120232, 120232, 120236, 120236, 120236, 120236, 120240, 120240, 120240, 120240, 120244, 120244, 120244, 120244, 120248, 120248, 120248, 120248, 120252, 120252, 120252, 120252, 120256, 120256, 120256, 120256, 120260, 120260, 120260, 120260, 120264, 120264, 120264, 120264, 120268, 120268, 120268, 120268, 120272, 120272, 120272, 120272, 120276, 120276, 120276, 120276, 120280, 120280, 120280, 120280, 120284, 120284, 120284, 120284, 120288, 120288, 120288, 120288, 120292, 120292, 120292, 120292, 120296, 120296, 120296, 120296, 120300, 120300, 120300, 120300, 120304, 120304, 120304, 120304, 120308, 120308, 120308, 120308, 120312, 120312, 120312, 120312, 120316, 120316, 120316, 120316, 120320, 120320, 120320, 120320, 120324, 120324, 120324, 120324, 120328, 120328, 120328, 120328, 120332, 120332, 120332, 120332, 120336, 120336, 120336, 120336, 120340, 120340, 120340, 120340, 120344, 120344, 120344, 120344, 120348, 120348, 120348, 120348, 120352, 120352, 120352, 120352, 120356, 120356, 120356, 120356, 120360, 120360, 120360, 120360, 120364, 120364, 120364, 120364, 120368, 120368, 120368, 120368, 120372, 120372, 120372, 120372, 120376, 120376, 120376, 120376, 120380, 120380, 120380, 120380, 120384, 120384, 120384, 120384, 120388, 120388, 120388, 120388, 120392, 120392, 120392, 120392, 120396, 120396, 120396, 120396, 120400, 120400, 120400, 120400, 120404, 120404, 120404, 120404, 120408, 120408, 120408, 120408, 120412, 120412, 120412, 120412, 120416, 120416, 120416, 120416, 120420, 120420, 120420, 120420, 120424, 120424, 120424, 120424, 120428, 120428, 120428, 120428, 120432, 120432, 120432, 120432, 120436, 120436, 120436, 120436, 120440, 120440, 120440, 120440, 120444, 120444, 120444, 120444, 120448, 120448, 120448, 120448, 120452, 120452, 120452, 120452, 120456, 120456, 120456, 120456, 120460, 120460, 120460, 120460, 120464, 120464, 120464, 120464, 120468, 120468, 120468, 120468, 120472, 120472, 120472, 120472, 120476, 120476, 120476, 120476, 120480, 120480, 120480, 120480, 120484, 120484, 120484, 120484, 120488, 120488, 120488, 120488, 120492, 120492, 120492, 120492, 120496, 120496, 120496, 120496, 120500, 120500, 120500, 120500, 120504, 120504, 120504, 120504, 120508, 120508, 120508, 120508, 120512, 120512, 120512, 120512, 120516, 120516, 120516, 120516, 120520, 120520, 120520, 120520, 120524, 120524, 120524, 120524, 120528, 120528, 120528, 120528, 120532, 120532, 120532, 120532, 120536, 120536, 120536, 120536, 120540, 120540, 120540, 120540, 120544, 120544, 120544, 120544, 120548, 120548, 120548, 120548, 120552, 120552, 120552, 120552, 120556, 120556, 120556, 120556, 120560, 120560, 120560, 120560, 120564, 120564, 120564, 120564, 120568, 120568, 120568, 120568, 120572, 120572, 120572, 120572, 120576, 120576, 120576, 120576, 120580, 120580, 120580, 120580, 120584, 120584, 120584, 120584, 120588, 120588, 120588, 120588, 120592, 120592, 120592, 120592, 120596, 120596, 120596, 120596, 120600, 120600, 120600, 120600, 120604, 120604, 120604, 120604, 120608, 120608, 120608, 120608, 120612, 120612, 120612, 120612, 120616, 120616, 120616, 120616, 120620, 120620, 120620, 120620, 120624, 120624, 120624, 120624, 120628, 120628, 120628, 120628, 120632, 120632, 120632, 120632, 120636, 120636, 120636, 120636, 120640, 120640, 120640, 120640, 120644, 120644, 120644, 120644, 120648, 120648, 120648, 120648, 120652, 120652, 120652, 120652, 120656, 120656, 120656, 120656, 120660, 120660, 120660, 120660, 120664, 120664, 120664, 120664, 120668, 120668, 120668, 120668, 120672, 120672, 120672, 120672, 120676, 120676, 120676, 120676, 120680, 120680, 120680, 120680, 120684, 120684, 120684, 120684, 120688, 120688, 120688, 120688, 120692, 120692, 120692, 120692, 120696, 120696, 120696, 120696, 120700, 120700, 120700, 120700, 120704, 120704, 120704, 120704, 120708, 120708, 120708, 120708, 120712, 120712, 120712, 120712, 120716, 120716, 120716, 120716, 120720, 120720, 120720, 120720, 120724, 120724, 120724, 120724, 120728, 120728, 120728, 120728, 120732, 120732, 120732, 120732, 120736, 120736, 120736, 120736, 120740, 120740, 120740, 120740, 120744, 120744, 120744, 120744, 120748, 120748, 120748, 120748, 120752, 120752, 120752, 120752, 120756, 120756, 120756, 120756, 120760, 120760, 120760, 120760, 120764, 120764, 120764, 120764, 120768, 120768, 120768, 120768, 120772, 120772, 120772, 120772, 120776, 120776, 120776, 120776, 120780, 120780, 120780, 120780, 120784, 120784, 120784, 120784, 120788, 120788, 120788, 120788, 120792, 120792, 120792, 120792, 120796, 120796, 120796, 120796, 120800, 120800, 120800, 120800, 120804, 120804, 120804, 120804, 120808, 120808, 120808, 120808, 120812, 120812, 120812, 120812, 120816, 120816, 120816, 120816, 120820, 120820, 120820, 120820, 120824, 120824, 120824, 120824, 120828, 120828, 120828, 120828, 120832, 120832, 120832, 120832, 120836, 120836, 120836, 120836, 120840, 120840, 120840, 120840, 120844, 120844, 120844, 120844, 120848, 120848, 120848, 120848, 120852, 120852, 120852, 120852, 120856, 120856, 120856, 120856, 120860, 120860, 120860, 120860, 120864, 120864, 120864, 120864, 120868, 120868, 120868, 120868, 120872, 120872, 120872, 120872, 120876, 120876, 120876, 120876, 120880, 120880, 120880, 120880, 120884, 120884, 120884, 120884, 120888, 120888, 120888, 120888, 120892, 120892, 120892, 120892, 120896, 120896, 120896, 120896, 120900, 120900, 120900, 120900, 120904, 120904, 120904, 120904, 120908, 120908, 120908, 120908, 120912, 120912, 120912, 120912, 120916, 120916, 120916, 120916, 120920, 120920, 120920, 120920, 120924, 120924, 120924, 120924, 120928, 120928, 120928, 120928, 120932, 120932, 120932, 120932, 120936, 120936, 120936, 120936, 120940, 120940, 120940, 120940, 120944, 120944, 120944, 120944, 120948, 120948, 120948, 120948, 120952, 120952, 120952, 120952, 120956, 120956, 120956, 120956, 120960, 120960, 120960, 120960, 120964, 120964, 120964, 120964, 120968, 120968, 120968, 120968, 120972, 120972, 120972, 120972, 120976, 120976, 120976, 120976, 120980, 120980, 120980, 120980, 120984, 120984, 120984, 120984, 120988, 120988, 120988, 120988, 120992, 120992, 120992, 120992, 120996, 120996, 120996, 120996, 121000, 121000, 121000, 121000, 121004, 121004, 121004, 121004, 121008, 121008, 121008, 121008, 121012, 121012, 121012, 121012, 121016, 121016, 121016, 121016, 121020, 121020, 121020, 121020, 121024, 121024, 121024, 121024, 121028, 121028, 121028, 121028, 121032, 121032, 121032, 121032, 121036, 121036, 121036, 121036, 121040, 121040, 121040, 121040, 121044, 121044, 121044, 121044, 121048, 121048, 121048, 121048, 121052, 121052, 121052, 121052, 121056, 121056, 121056, 121056, 121060, 121060, 121060, 121060, 121064, 121064, 121064, 121064, 121068, 121068, 121068, 121068, 121072, 121072, 121072, 121072, 121076, 121076, 121076, 121076, 121080, 121080, 121080, 121080, 121084, 121084, 121084, 121084, 121088, 121088, 121088, 121088, 121092, 121092, 121092, 121092, 121096, 121096, 121096, 121096, 121100, 121100, 121100, 121100, 121104, 121104, 121104, 121104, 121108, 121108, 121108, 121108, 121112, 121112, 121112, 121112, 121116, 121116, 121116, 121116, 121120, 121120, 121120, 121120, 121124, 121124, 121124, 121124, 121128, 121128, 121128, 121128, 121132, 121132, 121132, 121132, 121136, 121136, 121136, 121136, 121140, 121140, 121140, 121140, 121144, 121144, 121144, 121144, 121148, 121148, 121148, 121148, 121152, 121152, 121152, 121152, 121156, 121156, 121156, 121156, 121160, 121160, 121160, 121160, 121164, 121164, 121164, 121164, 121168, 121168, 121168, 121168, 121172, 121172, 121172, 121172, 121176, 121176, 121176, 121176, 121180, 121180, 121180, 121180, 121184, 121184, 121184, 121184, 121188, 121188, 121188, 121188, 121192, 121192, 121192, 121192, 121196, 121196, 121196, 121196, 121200, 121200, 121200, 121200, 121204, 121204, 121204, 121204, 121208, 121208, 121208, 121208, 121212, 121212, 121212, 121212, 121216, 121216, 121216, 121216, 121220, 121220, 121220, 121220, 121224, 121224, 121224, 121224, 121228, 121228, 121228, 121228, 121232, 121232, 121232, 121232, 121236, 121236, 121236, 121236, 121240, 121240, 121240, 121240, 121244, 121244, 121244, 121244, 121248, 121248, 121248, 121248, 121252, 121252, 121252, 121252, 121256, 121256, 121256, 121256, 121260, 121260, 121260, 121260, 121264, 121264, 121264, 121264, 121268, 121268, 121268, 121268, 121272, 121272, 121272, 121272, 121276, 121276, 121276, 121276, 121280, 121280, 121280, 121280, 121284, 121284, 121284, 121284, 121288, 121288, 121288, 121288, 121292, 121292, 121292, 121292, 121296, 121296, 121296, 121296, 121300, 121300, 121300, 121300, 121304, 121304, 121304, 121304, 121308, 121308, 121308, 121308, 121312, 121312, 121312, 121312, 121316, 121316, 121316, 121316, 121320, 121320, 121320, 121320, 121324, 121324, 121324, 121324, 121328, 121328, 121328, 121328, 121332, 121332, 121332, 121332, 121336, 121336, 121336, 121336, 121340, 121340, 121340, 121340, 121344, 121344, 121344, 121344}; -int bnproc_start_idx[121344] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 900, 900, 900, 900, 900, 900, 900, 900, 900, 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120500, 120501, 120502, 120503, 120504, 120505, 120506, 120507, 120508, 120509, 120510, 120511, 120512, 120513, 120514, 120515, 120516, 120517, 120518, 120519, 120520, 120521, 120522, 120523, 120524, 120525, 120526, 120527, 120528, 120529, 120530, 120531, 120532, 120533, 120534, 120535, 120536, 120537, 120538, 120539, 120540, 120541, 120542, 120543, 120544, 120545, 120546, 120547, 120548, 120549, 120550, 120551, 120552, 120553, 120554, 120555, 120556, 120557, 120558, 120559, 120560, 120561, 120562, 120563, 120564, 120565, 120566, 120567, 120568, 120569, 120570, 120571, 120572, 120573, 120574, 120575, 120576, 120577, 120578, 120579, 120580, 120581, 120582, 120583, 120584, 120585, 120586, 120587, 120588, 120589, 120590, 120591, 120592, 120593, 120594, 120595, 120596, 120597, 120598, 120599, 120600, 120601, 120602, 120603, 120604, 120605, 120606, 120607, 120608, 120609, 120610, 120611, 120612, 120613, 120614, 120615, 120616, 120617, 120618, 120619, 120620, 120621, 120622, 120623, 120624, 120625, 120626, 120627, 120628, 120629, 120630, 120631, 120632, 120633, 120634, 120635, 120636, 120637, 120638, 120639, 120640, 120641, 120642, 120643, 120644, 120645, 120646, 120647, 120648, 120649, 120650, 120651, 120652, 120653, 120654, 120655, 120656, 120657, 120658, 120659, 120660, 120661, 120662, 120663, 120664, 120665, 120666, 120667, 120668, 120669, 120670, 120671, 120672, 120673, 120674, 120675, 120676, 120677, 120678, 120679, 120680, 120681, 120682, 120683, 120684, 120685, 120686, 120687, 120688, 120689, 120690, 120691, 120692, 120693, 120694, 120695, 120696, 120697, 120698, 120699, 120700, 120701, 120702, 120703, 120704, 120705, 120706, 120707, 120708, 120709, 120710, 120711, 120712, 120713, 120714, 120715, 120716, 120717, 120718, 120719, 120720, 120721, 120722, 120723, 120724, 120725, 120726, 120727, 120728, 120729, 120730, 120731, 120732, 120733, 120734, 120735, 120736, 120737, 120738, 120739, 120740, 120741, 120742, 120743, 120744, 120745, 120746, 120747, 120748, 120749, 120750, 120751, 120752, 120753, 120754, 120755, 120756, 120757, 120758, 120759, 120760, 120761, 120762, 120763, 120764, 120765, 120766, 120767, 120768, 120769, 120770, 120771, 120772, 120773, 120774, 120775, 120776, 120777, 120778, 120779, 120780, 120781, 120782, 120783, 120784, 120785, 120786, 120787, 120788, 120789, 120790, 120791, 120792, 120793, 120794, 120795, 120796, 120797, 120798, 120799, 120800, 120801, 120802, 120803, 120804, 120805, 120806, 120807, 120808, 120809, 120810, 120811, 120812, 120813, 120814, 120815, 120816, 120817, 120818, 120819, 120820, 120821, 120822, 120823, 120824, 120825, 120826, 120827, 120828, 120829, 120830, 120831, 120832, 120833, 120834, 120835, 120836, 120837, 120838, 120839, 120840, 120841, 120842, 120843, 120844, 120845, 120846, 120847, 120848, 120849, 120850, 120851, 120852, 120853, 120854, 120855, 120856, 120857, 120858, 120859, 120860, 120861, 120862, 120863, 120864, 120865, 120866, 120867, 120868, 120869, 120870, 120871, 120872, 120873, 120874, 120875, 120876, 120877, 120878, 120879, 120880, 120881, 120882, 120883, 120884, 120885, 120886, 120887, 120888, 120889, 120890, 120891, 120892, 120893, 120894, 120895, 120896, 120897, 120898, 120899, 120900, 120901, 120902, 120903, 120904, 120905, 120906, 120907, 120908, 120909, 120910, 120911, 120912, 120913, 120914, 120915, 120916, 120917, 120918, 120919, 120920, 120921, 120922, 120923, 120924, 120925, 120926, 120927, 120928, 120929, 120930, 120931, 120932, 120933, 120934, 120935, 120936, 120937, 120938, 120939, 120940, 120941, 120942, 120943, 120944, 120945, 120946, 120947, 120948, 120949, 120950, 120951, 120952, 120953, 120954, 120955, 120956, 120957, 120958, 120959, 120960, 120961, 120962, 120963, 120964, 120965, 120966, 120967, 120968, 120969, 120970, 120971, 120972, 120973, 120974, 120975, 120976, 120977, 120978, 120979, 120980, 120981, 120982, 120983, 120984, 120985, 120986, 120987, 120988, 120989, 120990, 120991, 120992, 120993, 120994, 120995, 120996, 120997, 120998, 120999, 121000, 121001, 121002, 121003, 121004, 121005, 121006, 121007, 121008, 121009, 121010, 121011, 121012, 121013, 121014, 121015, 121016, 121017, 121018, 121019, 121020, 121021, 121022, 121023, 121024, 121025, 121026, 121027, 121028, 121029, 121030, 121031, 121032, 121033, 121034, 121035, 121036, 121037, 121038, 121039, 121040, 121041, 121042, 121043, 121044, 121045, 121046, 121047, 121048, 121049, 121050, 121051, 121052, 121053, 121054, 121055, 121056, 121057, 121058, 121059, 121060, 121061, 121062, 121063, 121064, 121065, 121066, 121067, 121068, 121069, 121070, 121071, 121072, 121073, 121074, 121075, 121076, 121077, 121078, 121079, 121080, 121081, 121082, 121083, 121084, 121085, 121086, 121087, 121088, 121089, 121090, 121091, 121092, 121093, 121094, 121095, 121096, 121097, 121098, 121099, 121100, 121101, 121102, 121103, 121104, 121105, 121106, 121107, 121108, 121109, 121110, 121111, 121112, 121113, 121114, 121115, 121116, 121117, 121118, 121119, 121120, 121121, 121122, 121123, 121124, 121125, 121126, 121127, 121128, 121129, 121130, 121131, 121132, 121133, 121134, 121135, 121136, 121137, 121138, 121139, 121140, 121141, 121142, 121143, 121144, 121145, 121146, 121147, 121148, 121149, 121150, 121151, 121152, 121153, 121154, 121155, 121156, 121157, 121158, 121159, 121160, 121161, 121162, 121163, 121164, 121165, 121166, 121167, 121168, 121169, 121170, 121171, 121172, 121173, 121174, 121175, 121176, 121177, 121178, 121179, 121180, 121181, 121182, 121183, 121184, 121185, 121186, 121187, 121188, 121189, 121190, 121191, 121192, 121193, 121194, 121195, 121196, 121197, 121198, 121199, 121200, 121201, 121202, 121203, 121204, 121205, 121206, 121207, 121208, 121209, 121210, 121211, 121212, 121213, 121214, 121215, 121216, 121217, 121218, 121219, 121220, 121221, 121222, 121223, 121224, 121225, 121226, 121227, 121228, 121229, 121230, 121231, 121232, 121233, 121234, 121235, 121236, 121237, 121238, 121239, 121240, 121241, 121242, 121243, 121244, 121245, 121246, 121247, 121248, 121249, 121250, 121251, 121252, 121253, 121254, 121255, 121256, 121257, 121258, 121259, 121260, 121261, 121262, 121263, 121264, 121265, 121266, 121267, 121268, 121269, 121270, 121271, 121272, 121273, 121274, 121275, 121276, 121277, 121278, 121279, 121280, 121281, 121282, 121283, 121284, 121285, 121286, 121287, 121288, 121289, 121290, 121291, 121292, 121293, 121294, 121295, 121296, 121297, 121298, 121299, 121300, 121301, 121302, 121303, 121304, 121305, 121306, 121307, 121308, 121309, 121310, 121311, 121312, 121313, 121314, 121315, 121316, 121317, 121318, 121319, 121320, 121321, 121322, 121323, 121324, 121325, 121326, 121327, 121328, 121329, 121330, 121331, 121332, 121333, 121334, 121335, 121336, 121337, 121338, 121339, 121340, 121341, 121342, 121343}; -int bnproc_end_idx[121344] = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 270, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 300, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 330, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 360, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 390, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 420, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 450, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 480, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 540, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 630, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 660, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 690, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 720, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 750, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 780, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 810, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 840, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 930, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 960, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 990, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1020, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1080, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1110, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1140, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1170, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1200, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1230, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1260, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1290, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1320, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1350, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1380, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1410, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1440, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1470, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1530, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1560, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1590, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1650, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1680, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1710, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1740, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1770, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1800, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1830, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1860, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1890, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1950, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 1980, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2010, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2040, 2070, 2070, 2070, 2070, 2070, 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119338, 119339, 119340, 119341, 119342, 119343, 119344, 119345, 119346, 119347, 119348, 119349, 119350, 119351, 119352, 119353, 119354, 119355, 119356, 119357, 119358, 119359, 119360, 119361, 119362, 119363, 119364, 119365, 119366, 119367, 119368, 119369, 119370, 119371, 119372, 119373, 119374, 119375, 119376, 119377, 119378, 119379, 119380, 119381, 119382, 119383, 119384, 119385, 119386, 119387, 119388, 119389, 119390, 119391, 119392, 119393, 119394, 119395, 119396, 119397, 119398, 119399, 119400, 119401, 119402, 119403, 119404, 119405, 119406, 119407, 119408, 119409, 119410, 119411, 119412, 119413, 119414, 119415, 119416, 119417, 119418, 119419, 119420, 119421, 119422, 119423, 119424, 119425, 119426, 119427, 119428, 119429, 119430, 119431, 119432, 119433, 119434, 119435, 119436, 119437, 119438, 119439, 119440, 119441, 119442, 119443, 119444, 119445, 119446, 119447, 119448, 119449, 119450, 119451, 119452, 119453, 119454, 119455, 119456, 119457, 119458, 119459, 119460, 119461, 119462, 119463, 119464, 119465, 119466, 119467, 119468, 119469, 119470, 119471, 119472, 119473, 119474, 119475, 119476, 119477, 119478, 119479, 119480, 119481, 119482, 119483, 119484, 119485, 119486, 119487, 119488, 119489, 119490, 119491, 119492, 119493, 119494, 119495, 119496, 119497, 119498, 119499, 119500, 119501, 119502, 119503, 119504, 119505, 119506, 119507, 119508, 119509, 119510, 119511, 119512, 119513, 119514, 119515, 119516, 119517, 119518, 119519, 119520, 119521, 119522, 119523, 119524, 119525, 119526, 119527, 119528, 119529, 119530, 119531, 119532, 119533, 119534, 119535, 119536, 119537, 119538, 119539, 119540, 119541, 119542, 119543, 119544, 119545, 119546, 119547, 119548, 119549, 119550, 119551, 119552, 119553, 119554, 119555, 119556, 119557, 119558, 119559, 119560, 119561, 119562, 119563, 119564, 119565, 119566, 119567, 119568, 119569, 119570, 119571, 119572, 119573, 119574, 119575, 119576, 119577, 119578, 119579, 119580, 119581, 119582, 119583, 119584, 119585, 119586, 119587, 119588, 119589, 119590, 119591, 119592, 119593, 119594, 119595, 119596, 119597, 119598, 119599, 119600, 119601, 119602, 119603, 119604, 119605, 119606, 119607, 119608, 119609, 119610, 119611, 119612, 119613, 119614, 119615, 119616, 119617, 119618, 119619, 119620, 119621, 119622, 119623, 119624, 119625, 119626, 119627, 119628, 119629, 119630, 119631, 119632, 119633, 119634, 119635, 119636, 119637, 119638, 119639, 119640, 119641, 119642, 119643, 119644, 119645, 119646, 119647, 119648, 119649, 119650, 119651, 119652, 119653, 119654, 119655, 119656, 119657, 119658, 119659, 119660, 119661, 119662, 119663, 119664, 119665, 119666, 119667, 119668, 119669, 119670, 119671, 119672, 119673, 119674, 119675, 119676, 119677, 119678, 119679, 119680, 119681, 119682, 119683, 119684, 119685, 119686, 119687, 119688, 119689, 119690, 119691, 119692, 119693, 119694, 119695, 119696, 119697, 119698, 119699, 119700, 119701, 119702, 119703, 119704, 119705, 119706, 119707, 119708, 119709, 119710, 119711, 119712, 119713, 119714, 119715, 119716, 119717, 119718, 119719, 119720, 119721, 119722, 119723, 119724, 119725, 119726, 119727, 119728, 119729, 119730, 119731, 119732, 119733, 119734, 119735, 119736, 119737, 119738, 119739, 119740, 119741, 119742, 119743, 119744, 119745, 119746, 119747, 119748, 119749, 119750, 119751, 119752, 119753, 119754, 119755, 119756, 119757, 119758, 119759, 119760, 119761, 119762, 119763, 119764, 119765, 119766, 119767, 119768, 119769, 119770, 119771, 119772, 119773, 119774, 119775, 119776, 119777, 119778, 119779, 119780, 119781, 119782, 119783, 119784, 119785, 119786, 119787, 119788, 119789, 119790, 119791, 119792, 119793, 119794, 119795, 119796, 119797, 119798, 119799, 119800, 119801, 119802, 119803, 119804, 119805, 119806, 119807, 119808, 119809, 119810, 119811, 119812, 119813, 119814, 119815, 119816, 119817, 119818, 119819, 119820, 119821, 119822, 119823, 119824, 119825, 119826, 119827, 119828, 119829, 119830, 119831, 119832, 119833, 119834, 119835, 119836, 119837, 119838, 119839, 119840, 119841, 119842, 119843, 119844, 119845, 119846, 119847, 119848, 119849, 119850, 119851, 119852, 119853, 119854, 119855, 119856, 119857, 119858, 119859, 119860, 119861, 119862, 119863, 119864, 119865, 119866, 119867, 119868, 119869, 119870, 119871, 119872, 119873, 119874, 119875, 119876, 119877, 119878, 119879, 119880, 119881, 119882, 119883, 119884, 119885, 119886, 119887, 119888, 119889, 119890, 119891, 119892, 119893, 119894, 119895, 119896, 119897, 119898, 119899, 119900, 119901, 119902, 119903, 119904, 119905, 119906, 119907, 119908, 119909, 119910, 119911, 119912, 119913, 119914, 119915, 119916, 119917, 119918, 119919, 119920, 119921, 119922, 119923, 119924, 119925, 119926, 119927, 119928, 119929, 119930, 119931, 119932, 119933, 119934, 119935, 119936, 119937, 119938, 119939, 119940, 119941, 119942, 119943, 119944, 119945, 119946, 119947, 119948, 119949, 119950, 119951, 119952, 119953, 119954, 119955, 119956, 119957, 119958, 119959, 119960, 119961, 119962, 119963, 119964, 119965, 119966, 119967, 119968, 119969, 119970, 119971, 119972, 119973, 119974, 119975, 119976, 119977, 119978, 119979, 119980, 119981, 119982, 119983, 119984, 119985, 119986, 119987, 119988, 119989, 119990, 119991, 119992, 119993, 119994, 119995, 119996, 119997, 119998, 119999, 120000, 120001, 120002, 120003, 120004, 120005, 120006, 120007, 120008, 120009, 120010, 120011, 120012, 120013, 120014, 120015, 120016, 120017, 120018, 120019, 120020, 120021, 120022, 120023, 120024, 120025, 120026, 120027, 120028, 120029, 120030, 120031, 120032, 120033, 120034, 120035, 120036, 120037, 120038, 120039, 120040, 120041, 120042, 120043, 120044, 120045, 120046, 120047, 120048, 120049, 120050, 120051, 120052, 120053, 120054, 120055, 120056, 120057, 120058, 120059, 120060, 120061, 120062, 120063, 120064, 120065, 120066, 120067, 120068, 120069, 120070, 120071, 120072, 120073, 120074, 120075, 120076, 120077, 120078, 120079, 120080, 120081, 120082, 120083, 120084, 120085, 120086, 120087, 120088, 120089, 120090, 120091, 120092, 120093, 120094, 120095, 120096, 120097, 120098, 120099, 120100, 120101, 120102, 120103, 120104, 120105, 120106, 120107, 120108, 120109, 120110, 120111, 120112, 120113, 120114, 120115, 120116, 120117, 120118, 120119, 120120, 120121, 120122, 120123, 120124, 120125, 120126, 120127, 120128, 120129, 120130, 120131, 120132, 120133, 120134, 120135, 120136, 120137, 120138, 120139, 120140, 120141, 120142, 120143, 120144, 120145, 120146, 120147, 120148, 120149, 120150, 120151, 120152, 120153, 120154, 120155, 120156, 120157, 120158, 120159, 120160, 120161, 120162, 120163, 120164, 120165, 120166, 120167, 120168, 120169, 120170, 120171, 120172, 120173, 120174, 120175, 120176, 120177, 120178, 120179, 120180, 120181, 120182, 120183, 120184, 120185, 120186, 120187, 120188, 120189, 120190, 120191, 120192, 120193, 120194, 120195, 120196, 120197, 120198, 120199, 120200, 120201, 120202, 120203, 120204, 120205, 120206, 120207, 120208, 120209, 120210, 120211, 120212, 120213, 120214, 120215, 120216, 120217, 120218, 120219, 120220, 120221, 120222, 120223, 120224, 120225, 120226, 120227, 120228, 120229, 120230, 120231, 120232, 120233, 120234, 120235, 120236, 120237, 120238, 120239, 120240, 120241, 120242, 120243, 120244, 120245, 120246, 120247, 120248, 120249, 120250, 120251, 120252, 120253, 120254, 120255, 120256, 120257, 120258, 120259, 120260, 120261, 120262, 120263, 120264, 120265, 120266, 120267, 120268, 120269, 120270, 120271, 120272, 120273, 120274, 120275, 120276, 120277, 120278, 120279, 120280, 120281, 120282, 120283, 120284, 120285, 120286, 120287, 120288, 120289, 120290, 120291, 120292, 120293, 120294, 120295, 120296, 120297, 120298, 120299, 120300, 120301, 120302, 120303, 120304, 120305, 120306, 120307, 120308, 120309, 120310, 120311, 120312, 120313, 120314, 120315, 120316, 120317, 120318, 120319, 120320, 120321, 120322, 120323, 120324, 120325, 120326, 120327, 120328, 120329, 120330, 120331, 120332, 120333, 120334, 120335, 120336, 120337, 120338, 120339, 120340, 120341, 120342, 120343, 120344, 120345, 120346, 120347, 120348, 120349, 120350, 120351, 120352, 120353, 120354, 120355, 120356, 120357, 120358, 120359, 120360, 120361, 120362, 120363, 120364, 120365, 120366, 120367, 120368, 120369, 120370, 120371, 120372, 120373, 120374, 120375, 120376, 120377, 120378, 120379, 120380, 120381, 120382, 120383, 120384, 120385, 120386, 120387, 120388, 120389, 120390, 120391, 120392, 120393, 120394, 120395, 120396, 120397, 120398, 120399, 120400, 120401, 120402, 120403, 120404, 120405, 120406, 120407, 120408, 120409, 120410, 120411, 120412, 120413, 120414, 120415, 120416, 120417, 120418, 120419, 120420, 120421, 120422, 120423, 120424, 120425, 120426, 120427, 120428, 120429, 120430, 120431, 120432, 120433, 120434, 120435, 120436, 120437, 120438, 120439, 120440, 120441, 120442, 120443, 120444, 120445, 120446, 120447, 120448, 120449, 120450, 120451, 120452, 120453, 120454, 120455, 120456, 120457, 120458, 120459, 120460, 120461, 120462, 120463, 120464, 120465, 120466, 120467, 120468, 120469, 120470, 120471, 120472, 120473, 120474, 120475, 120476, 120477, 120478, 120479, 120480, 120481, 120482, 120483, 120484, 120485, 120486, 120487, 120488, 120489, 120490, 120491, 120492, 120493, 120494, 120495, 120496, 120497, 120498, 120499, 120500, 120501, 120502, 120503, 120504, 120505, 120506, 120507, 120508, 120509, 120510, 120511, 120512, 120513, 120514, 120515, 120516, 120517, 120518, 120519, 120520, 120521, 120522, 120523, 120524, 120525, 120526, 120527, 120528, 120529, 120530, 120531, 120532, 120533, 120534, 120535, 120536, 120537, 120538, 120539, 120540, 120541, 120542, 120543, 120544, 120545, 120546, 120547, 120548, 120549, 120550, 120551, 120552, 120553, 120554, 120555, 120556, 120557, 120558, 120559, 120560, 120561, 120562, 120563, 120564, 120565, 120566, 120567, 120568, 120569, 120570, 120571, 120572, 120573, 120574, 120575, 120576, 120577, 120578, 120579, 120580, 120581, 120582, 120583, 120584, 120585, 120586, 120587, 120588, 120589, 120590, 120591, 120592, 120593, 120594, 120595, 120596, 120597, 120598, 120599, 120600, 120601, 120602, 120603, 120604, 120605, 120606, 120607, 120608, 120609, 120610, 120611, 120612, 120613, 120614, 120615, 120616, 120617, 120618, 120619, 120620, 120621, 120622, 120623, 120624, 120625, 120626, 120627, 120628, 120629, 120630, 120631, 120632, 120633, 120634, 120635, 120636, 120637, 120638, 120639, 120640, 120641, 120642, 120643, 120644, 120645, 120646, 120647, 120648, 120649, 120650, 120651, 120652, 120653, 120654, 120655, 120656, 120657, 120658, 120659, 120660, 120661, 120662, 120663, 120664, 120665, 120666, 120667, 120668, 120669, 120670, 120671, 120672, 120673, 120674, 120675, 120676, 120677, 120678, 120679, 120680, 120681, 120682, 120683, 120684, 120685, 120686, 120687, 120688, 120689, 120690, 120691, 120692, 120693, 120694, 120695, 120696, 120697, 120698, 120699, 120700, 120701, 120702, 120703, 120704, 120705, 120706, 120707, 120708, 120709, 120710, 120711, 120712, 120713, 120714, 120715, 120716, 120717, 120718, 120719, 120720, 120721, 120722, 120723, 120724, 120725, 120726, 120727, 120728, 120729, 120730, 120731, 120732, 120733, 120734, 120735, 120736, 120737, 120738, 120739, 120740, 120741, 120742, 120743, 120744, 120745, 120746, 120747, 120748, 120749, 120750, 120751, 120752, 120753, 120754, 120755, 120756, 120757, 120758, 120759, 120760, 120761, 120762, 120763, 120764, 120765, 120766, 120767, 120768, 120769, 120770, 120771, 120772, 120773, 120774, 120775, 120776, 120777, 120778, 120779, 120780, 120781, 120782, 120783, 120784, 120785, 120786, 120787, 120788, 120789, 120790, 120791, 120792, 120793, 120794, 120795, 120796, 120797, 120798, 120799, 120800, 120801, 120802, 120803, 120804, 120805, 120806, 120807, 120808, 120809, 120810, 120811, 120812, 120813, 120814, 120815, 120816, 120817, 120818, 120819, 120820, 120821, 120822, 120823, 120824, 120825, 120826, 120827, 120828, 120829, 120830, 120831, 120832, 120833, 120834, 120835, 120836, 120837, 120838, 120839, 120840, 120841, 120842, 120843, 120844, 120845, 120846, 120847, 120848, 120849, 120850, 120851, 120852, 120853, 120854, 120855, 120856, 120857, 120858, 120859, 120860, 120861, 120862, 120863, 120864, 120865, 120866, 120867, 120868, 120869, 120870, 120871, 120872, 120873, 120874, 120875, 120876, 120877, 120878, 120879, 120880, 120881, 120882, 120883, 120884, 120885, 120886, 120887, 120888, 120889, 120890, 120891, 120892, 120893, 120894, 120895, 120896, 120897, 120898, 120899, 120900, 120901, 120902, 120903, 120904, 120905, 120906, 120907, 120908, 120909, 120910, 120911, 120912, 120913, 120914, 120915, 120916, 120917, 120918, 120919, 120920, 120921, 120922, 120923, 120924, 120925, 120926, 120927, 120928, 120929, 120930, 120931, 120932, 120933, 120934, 120935, 120936, 120937, 120938, 120939, 120940, 120941, 120942, 120943, 120944, 120945, 120946, 120947, 120948, 120949, 120950, 120951, 120952, 120953, 120954, 120955, 120956, 120957, 120958, 120959, 120960, 120961, 120962, 120963, 120964, 120965, 120966, 120967, 120968, 120969, 120970, 120971, 120972, 120973, 120974, 120975, 120976, 120977, 120978, 120979, 120980, 120981, 120982, 120983, 120984, 120985, 120986, 120987, 120988, 120989, 120990, 120991, 120992, 120993, 120994, 120995, 120996, 120997, 120998, 120999, 121000, 121001, 121002, 121003, 121004, 121005, 121006, 121007, 121008, 121009, 121010, 121011, 121012, 121013, 121014, 121015, 121016, 121017, 121018, 121019, 121020, 121021, 121022, 121023, 121024, 121025, 121026, 121027, 121028, 121029, 121030, 121031, 121032, 121033, 121034, 121035, 121036, 121037, 121038, 121039, 121040, 121041, 121042, 121043, 121044, 121045, 121046, 121047, 121048, 121049, 121050, 121051, 121052, 121053, 121054, 121055, 121056, 121057, 121058, 121059, 121060, 121061, 121062, 121063, 121064, 121065, 121066, 121067, 121068, 121069, 121070, 121071, 121072, 121073, 121074, 121075, 121076, 121077, 121078, 121079, 121080, 121081, 121082, 121083, 121084, 121085, 121086, 121087, 121088, 121089, 121090, 121091, 121092, 121093, 121094, 121095, 121096, 121097, 121098, 121099, 121100, 121101, 121102, 121103, 121104, 121105, 121106, 121107, 121108, 121109, 121110, 121111, 121112, 121113, 121114, 121115, 121116, 121117, 121118, 121119, 121120, 121121, 121122, 121123, 121124, 121125, 121126, 121127, 121128, 121129, 121130, 121131, 121132, 121133, 121134, 121135, 121136, 121137, 121138, 121139, 121140, 121141, 121142, 121143, 121144, 121145, 121146, 121147, 121148, 121149, 121150, 121151, 121152, 121153, 121154, 121155, 121156, 121157, 121158, 121159, 121160, 121161, 121162, 121163, 121164, 121165, 121166, 121167, 121168, 121169, 121170, 121171, 121172, 121173, 121174, 121175, 121176, 121177, 121178, 121179, 121180, 121181, 121182, 121183, 121184, 121185, 121186, 121187, 121188, 121189, 121190, 121191, 121192, 121193, 121194, 121195, 121196, 121197, 121198, 121199, 121200, 121201, 121202, 121203, 121204, 121205, 121206, 121207, 121208, 121209, 121210, 121211, 121212, 121213, 121214, 121215, 121216, 121217, 121218, 121219, 121220, 121221, 121222, 121223, 121224, 121225, 121226, 121227, 121228, 121229, 121230, 121231, 121232, 121233, 121234, 121235, 121236, 121237, 121238, 121239, 121240, 121241, 121242, 121243, 121244, 121245, 121246, 121247, 121248, 121249, 121250, 121251, 121252, 121253, 121254, 121255, 121256, 121257, 121258, 121259, 121260, 121261, 121262, 121263, 121264, 121265, 121266, 121267, 121268, 121269, 121270, 121271, 121272, 121273, 121274, 121275, 121276, 121277, 121278, 121279, 121280, 121281, 121282, 121283, 121284, 121285, 121286, 121287, 121288, 121289, 121290, 121291, 121292, 121293, 121294, 121295, 121296, 121297, 121298, 121299, 121300, 121301, 121302, 121303, 121304, 121305, 121306, 121307, 121308, 121309, 121310, 121311, 121312, 121313, 121314, 121315, 121316, 121317, 121318, 121319, 121320, 121321, 121322, 121323, 121324, 121325, 121326, 121327, 121328, 121329, 121330, 121331, 121332, 121333, 121334, 121335, 121336, 121337, 121338, 121339, 121340, 121341, 121342, 121343, 121344}; -int llr_idx[26113] = { 0, 30, 60, 90, 120, 150, 180, 210, 240, 270, 300, 330, 360, 390, 420, 450, 480, 510, 540, 570, 600, 630, 660, 690, 720, 750, 780, 810, 840, 870, 900, 930, 960, 990, 1020, 1050, 1080, 1110, 1140, 1170, 1200, 1230, 1260, 1290, 1320, 1350, 1380, 1410, 1440, 1470, 1500, 1530, 1560, 1590, 1620, 1650, 1680, 1710, 1740, 1770, 1800, 1830, 1860, 1890, 1920, 1950, 1980, 2010, 2040, 2070, 2100, 2130, 2160, 2190, 2220, 2250, 2280, 2310, 2340, 2370, 2400, 2430, 2460, 2490, 2520, 2550, 2580, 2610, 2640, 2670, 2700, 2730, 2760, 2790, 2820, 2850, 2880, 2910, 2940, 2970, 3000, 3030, 3060, 3090, 3120, 3150, 3180, 3210, 3240, 3270, 3300, 3330, 3360, 3390, 3420, 3450, 3480, 3510, 3540, 3570, 3600, 3630, 3660, 3690, 3720, 3750, 3780, 3810, 3840, 3870, 3900, 3930, 3960, 3990, 4020, 4050, 4080, 4110, 4140, 4170, 4200, 4230, 4260, 4290, 4320, 4350, 4380, 4410, 4440, 4470, 4500, 4530, 4560, 4590, 4620, 4650, 4680, 4710, 4740, 4770, 4800, 4830, 4860, 4890, 4920, 4950, 4980, 5010, 5040, 5070, 5100, 5130, 5160, 5190, 5220, 5250, 5280, 5310, 5340, 5370, 5400, 5430, 5460, 5490, 5520, 5550, 5580, 5610, 5640, 5670, 5700, 5730, 5760, 5790, 5820, 5850, 5880, 5910, 5940, 5970, 6000, 6030, 6060, 6090, 6120, 6150, 6180, 6210, 6240, 6270, 6300, 6330, 6360, 6390, 6420, 6450, 6480, 6510, 6540, 6570, 6600, 6630, 6660, 6690, 6720, 6750, 6780, 6810, 6840, 6870, 6900, 6930, 6960, 6990, 7020, 7050, 7080, 7110, 7140, 7170, 7200, 7230, 7260, 7290, 7320, 7350, 7380, 7410, 7440, 7470, 7500, 7530, 7560, 7590, 7620, 7650, 7680, 7710, 7740, 7770, 7800, 7830, 7860, 7890, 7920, 7950, 7980, 8010, 8040, 8070, 8100, 8130, 8160, 8190, 8220, 8250, 8280, 8310, 8340, 8370, 8400, 8430, 8460, 8490, 8520, 8550, 8580, 8610, 8640, 8670, 8700, 8730, 8760, 8790, 8820, 8850, 8880, 8910, 8940, 8970, 9000, 9030, 9060, 9090, 9120, 9150, 9180, 9210, 9240, 9270, 9300, 9330, 9360, 9390, 9420, 9450, 9480, 9510, 9540, 9570, 9600, 9630, 9660, 9690, 9720, 9750, 9780, 9810, 9840, 9870, 9900, 9930, 9960, 9990, 10020, 10050, 10080, 10110, 10140, 10170, 10200, 10230, 10260, 10290, 10320, 10350, 10380, 10410, 10440, 10470, 10500, 10530, 10560, 10590, 10620, 10650, 10680, 10710, 10740, 10770, 10800, 10830, 10860, 10890, 10920, 10950, 10980, 11010, 11040, 11070, 11100, 11130, 11160, 11190, 11220, 11250, 11280, 11310, 11340, 11370, 11400, 11430, 11460, 11490, 11520, 11548, 11576, 11604, 11632, 11660, 11688, 11716, 11744, 11772, 11800, 11828, 11856, 11884, 11912, 11940, 11968, 11996, 12024, 12052, 12080, 12108, 12136, 12164, 12192, 12220, 12248, 12276, 12304, 12332, 12360, 12388, 12416, 12444, 12472, 12500, 12528, 12556, 12584, 12612, 12640, 12668, 12696, 12724, 12752, 12780, 12808, 12836, 12864, 12892, 12920, 12948, 12976, 13004, 13032, 13060, 13088, 13116, 13144, 13172, 13200, 13228, 13256, 13284, 13312, 13340, 13368, 13396, 13424, 13452, 13480, 13508, 13536, 13564, 13592, 13620, 13648, 13676, 13704, 13732, 13760, 13788, 13816, 13844, 13872, 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121036, 121037, 121038, 121039, 121040, 121041, 121042, 121043, 121044, 121045, 121046, 121047, 121048, 121049, 121050, 121051, 121052, 121053, 121054, 121055, 121056, 121057, 121058, 121059, 121060, 121061, 121062, 121063, 121064, 121065, 121066, 121067, 121068, 121069, 121070, 121071, 121072, 121073, 121074, 121075, 121076, 121077, 121078, 121079, 121080, 121081, 121082, 121083, 121084, 121085, 121086, 121087, 121088, 121089, 121090, 121091, 121092, 121093, 121094, 121095, 121096, 121097, 121098, 121099, 121100, 121101, 121102, 121103, 121104, 121105, 121106, 121107, 121108, 121109, 121110, 121111, 121112, 121113, 121114, 121115, 121116, 121117, 121118, 121119, 121120, 121121, 121122, 121123, 121124, 121125, 121126, 121127, 121128, 121129, 121130, 121131, 121132, 121133, 121134, 121135, 121136, 121137, 121138, 121139, 121140, 121141, 121142, 121143, 121144, 121145, 121146, 121147, 121148, 121149, 121150, 121151, 121152, 121153, 121154, 121155, 121156, 121157, 121158, 121159, 121160, 121161, 121162, 121163, 121164, 121165, 121166, 121167, 121168, 121169, 121170, 121171, 121172, 121173, 121174, 121175, 121176, 121177, 121178, 121179, 121180, 121181, 121182, 121183, 121184, 121185, 121186, 121187, 121188, 121189, 121190, 121191, 121192, 121193, 121194, 121195, 121196, 121197, 121198, 121199, 121200, 121201, 121202, 121203, 121204, 121205, 121206, 121207, 121208, 121209, 121210, 121211, 121212, 121213, 121214, 121215, 121216, 121217, 121218, 121219, 121220, 121221, 121222, 121223, 121224, 121225, 121226, 121227, 121228, 121229, 121230, 121231, 121232, 121233, 121234, 121235, 121236, 121237, 121238, 121239, 121240, 121241, 121242, 121243, 121244, 121245, 121246, 121247, 121248, 121249, 121250, 121251, 121252, 121253, 121254, 121255, 121256, 121257, 121258, 121259, 121260, 121261, 121262, 121263, 121264, 121265, 121266, 121267, 121268, 121269, 121270, 121271, 121272, 121273, 121274, 121275, 121276, 121277, 121278, 121279, 121280, 121281, 121282, 121283, 121284, 121285, 121286, 121287, 121288, 121289, 121290, 121291, 121292, 121293, 121294, 121295, 121296, 121297, 121298, 121299, 121300, 121301, 121302, 121303, 121304, 121305, 121306, 121307, 121308, 121309, 121310, 121311, 121312, 121313, 121314, 121315, 121316, 121317, 121318, 121319, 121320, 121321, 121322, 121323, 121324, 121325, 121326, 121327, 121328, 121329, 121330, 121331, 121332, 121333, 121334, 121335, 121336, 121337, 121338, 121339, 121340, 121341, 121342, 121343, 121344}; -int l2b_idx[121344] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 45, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 51, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 55, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 58, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 59, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 61, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 66, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 67, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 69, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 71, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 74, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 79, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 81, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 82, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 93, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 94, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 96, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 97, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 101, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 102, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 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25636, 25637, 25638, 25639, 25640, 25641, 25642, 25643, 25644, 25645, 25646, 25647, 25648, 25649, 25650, 25651, 25652, 25653, 25654, 25655, 25656, 25657, 25658, 25659, 25660, 25661, 25662, 25663, 25664, 25665, 25666, 25667, 25668, 25669, 25670, 25671, 25672, 25673, 25674, 25675, 25676, 25677, 25678, 25679, 25680, 25681, 25682, 25683, 25684, 25685, 25686, 25687, 25688, 25689, 25690, 25691, 25692, 25693, 25694, 25695, 25696, 25697, 25698, 25699, 25700, 25701, 25702, 25703, 25704, 25705, 25706, 25707, 25708, 25709, 25710, 25711, 25712, 25713, 25714, 25715, 25716, 25717, 25718, 25719, 25720, 25721, 25722, 25723, 25724, 25725, 25726, 25727, 25728, 25729, 25730, 25731, 25732, 25733, 25734, 25735, 25736, 25737, 25738, 25739, 25740, 25741, 25742, 25743, 25744, 25745, 25746, 25747, 25748, 25749, 25750, 25751, 25752, 25753, 25754, 25755, 25756, 25757, 25758, 25759, 25760, 25761, 25762, 25763, 25764, 25765, 25766, 25767, 25768, 25769, 25770, 25771, 25772, 25773, 25774, 25775, 25776, 25777, 25778, 25779, 25780, 25781, 25782, 25783, 25784, 25785, 25786, 25787, 25788, 25789, 25790, 25791, 25792, 25793, 25794, 25795, 25796, 25797, 25798, 25799, 25800, 25801, 25802, 25803, 25804, 25805, 25806, 25807, 25808, 25809, 25810, 25811, 25812, 25813, 25814, 25815, 25816, 25817, 25818, 25819, 25820, 25821, 25822, 25823, 25824, 25825, 25826, 25827, 25828, 25829, 25830, 25831, 25832, 25833, 25834, 25835, 25836, 25837, 25838, 25839, 25840, 25841, 25842, 25843, 25844, 25845, 25846, 25847, 25848, 25849, 25850, 25851, 25852, 25853, 25854, 25855, 25856, 25857, 25858, 25859, 25860, 25861, 25862, 25863, 25864, 25865, 25866, 25867, 25868, 25869, 25870, 25871, 25872, 25873, 25874, 25875, 25876, 25877, 25878, 25879, 25880, 25881, 25882, 25883, 25884, 25885, 25886, 25887, 25888, 25889, 25890, 25891, 25892, 25893, 25894, 25895, 25896, 25897, 25898, 25899, 25900, 25901, 25902, 25903, 25904, 25905, 25906, 25907, 25908, 25909, 25910, 25911, 25912, 25913, 25914, 25915, 25916, 25917, 25918, 25919, 25920, 25921, 25922, 25923, 25924, 25925, 25926, 25927, 25928, 25929, 25930, 25931, 25932, 25933, 25934, 25935, 25936, 25937, 25938, 25939, 25940, 25941, 25942, 25943, 25944, 25945, 25946, 25947, 25948, 25949, 25950, 25951, 25952, 25953, 25954, 25955, 25956, 25957, 25958, 25959, 25960, 25961, 25962, 25963, 25964, 25965, 25966, 25967, 25968, 25969, 25970, 25971, 25972, 25973, 25974, 25975, 25976, 25977, 25978, 25979, 25980, 25981, 25982, 25983, 25984, 25985, 25986, 25987, 25988, 25989, 25990, 25991, 25992, 25993, 25994, 25995, 25996, 25997, 25998, 25999, 26000, 26001, 26002, 26003, 26004, 26005, 26006, 26007, 26008, 26009, 26010, 26011, 26012, 26013, 26014, 26015, 26016, 26017, 26018, 26019, 26020, 26021, 26022, 26023, 26024, 26025, 26026, 26027, 26028, 26029, 26030, 26031, 26032, 26033, 26034, 26035, 26036, 26037, 26038, 26039, 26040, 26041, 26042, 26043, 26044, 26045, 26046, 26047, 26048, 26049, 26050, 26051, 26052, 26053, 26054, 26055, 26056, 26057, 26058, 26059, 26060, 26061, 26062, 26063, 26064, 26065, 26066, 26067, 26068, 26069, 26070, 26071, 26072, 26073, 26074, 26075, 26076, 26077, 26078, 26079, 26080, 26081, 26082, 26083, 26084, 26085, 26086, 26087, 26088, 26089, 26090, 26091, 26092, 26093, 26094, 26095, 26096, 26097, 26098, 26099, 26100, 26101, 26102, 26103, 26104, 26105, 26106, 26107, 26108, 26109, 26110, 26111}; diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/check.sh b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/check.sh deleted file mode 100644 index 98814432df..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/check.sh +++ /dev/null @@ -1,10 +0,0 @@ -set +x -index=1 -for file in ../test_input/8448/* -do - cp $file channel_output.txt - echo "===== test $index =====" >> log.txt - ./ldpc channel_output.txt >> log.txt - echo ' ' >> log.txt - index=$((index+1)) - done diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/gen_idx.c b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/gen_idx.c deleted file mode 100644 index 795918dec6..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/gen_idx.c +++ /dev/null @@ -1,198 +0,0 @@ -#include -#include -#include -#ifndef test -#include "../BGs/isip_ldpc_bg1_i1.h" -#endif -int l2c_idx[316*384] = {}; // cnbuf[ tid ] = llr[ l2c_idx[tid] ] -int l2b_idx[316*384] = {}; // bnbuf[ tid ] = llr[ l2b_idx[tid] ] -int llr_idx[26113] = {}; // bnbuf2llr, start = llr_idx[tid], end = llr_idx[tid+1], llrbuf[tid] = sum of (bnbuf[start] to bnbuf[end]) -int c2b_idx[316*384] = {}; // bnbuf[ tid ] = cnbuf[ c2b_idx[tid] ] -int b2c_idx[316*384] = {}; // cnbuf[ tid ] = bnbuf[ b2c_idx[tid] ] -int cnproc_start_idx[316*384] = {}; // index for cnproc, int start = cnproc_start_idx[tid] -int cnproc_end_idx[316*384] = {}; // index for cnproc, int end = cnproc_end_idx[tid] -int bnproc_start_idx[316*384] = {}; // index for bnproc, int start = bnproc_start_idx[tid] -int bnproc_end_idx[316*384] = {}; // index for bnproc, int end = bnproc_end_idx[tid] - -int *matrix_transpose(int *matrix, int row, int col) -{ - -} - -void write_to_file(FILE *fp, const char *arr_name, int *arr, int size) -{ - fprintf(fp, "%s[%d] = { %d", arr_name, size, arr[0]); - for(int i = 1; i < size; i++){ - fprintf(fp, ", %d", arr[i]); - } - fprintf(fp, "};\n"); -} - -void matrix_expansion(const int *BG, int row, int col, int Zc, int *matrix) -{ - for(int i = 0; i < row; i++){ - for(int j = 0; j < col; j++){ - int val = BG[i * col + j]; - if(val != 0){ - val = (val-1)%Zc; - for(int k = i*Zc; k < (i+1)*Zc; k++){ - int idx = k*(col*Zc) + (j*Zc+val); - matrix[idx] = 1; - val = (val+1)%Zc; - } - } - } - } -} - -void print_matrix(const int *M, int row, int col) -{ - printf("Matrix:\n{\n"); - for(int i = 0; i < row; i++){ - printf("\t"); - for(int j = 0; j < col; j++){ - printf(" %d,", M[i*col + j]); - } - printf("\n"); - } - printf("}\n"); -} - - -void build_index(const int *BG, int row, int col, int Zc) -{ - int *matrix = (int*)malloc(row*col*Zc*Zc*sizeof(int)); - int cnidx = 0, bnidx = 0, aidx = 0, pidx = 0, lidx1 = 0, lidx2 = 0; - - matrix_expansion(BG, row, col, Zc, matrix); - - // cn label & l2c_idx - for(int i = 0; i < row*Zc; i++){ - for(int j = 0; j < col*Zc; j++){ - int k = i*col*Zc + j; - if(matrix[k] == 1){ - matrix[k] = cnidx+1; - l2c_idx[cnidx] = j; - cnidx++; - } - } - } - - // build c2b_idx & bnproc_idx - for(int i = 0; i < col*Zc; i++){ - int cnt = 0; - int start = aidx, end = 0; - for(int j = 0; j < row*Zc; j++){ - int val = matrix[i + j*col*Zc]; - if(val != 0){ - c2b_idx[aidx] = val -1; - aidx++, cnt++; - } - } - end = start + cnt; - while(cnt--){ - bnproc_start_idx[pidx] = start; - bnproc_end_idx[pidx] = end; - pidx++; - } - } - - printf("cnidx %d\naidx %d\npidx %d\n", cnidx, aidx, pidx); - - matrix_expansion(BG, row, col, Zc, matrix); - - // bn label & llr_idx - for(int i = 0; i < col*Zc; i++){ - llr_idx[lidx1++] = bnidx; - for(int j = 0; j < row*Zc; j++){ - int k = i + j*col*Zc; - if(matrix[k] == 1){ - matrix[k] = bnidx+1; - l2b_idx[lidx2++] = i; - bnidx++; - } - } - } - llr_idx[lidx1] = bnidx; - - // build b2c_idx & cnproc_idx - aidx = pidx = 0; - for(int i = 0; i < row*Zc; i++){ - int cnt = 0; - int start = aidx, end = 0; - for(int j = 0; j < col*Zc; j++){ - int val = matrix[i*col*Zc + j]; - if(val != 0){ - b2c_idx[aidx] = val - 1; - aidx++, cnt++; - } - } - end = start + cnt; - while(cnt--){ - cnproc_start_idx[pidx] = start; - cnproc_end_idx[pidx] = end; - pidx++; - } - } - - printf("bnidx %d\naidx %d\npidx %d\n", bnidx, aidx, pidx); - printf("lidx1 %d\nlidx2 %d\n", lidx1, lidx2); - - free(matrix); -} - -void generate_header(const char *file, int col, int entry, int Zc) -{ -#ifdef test - FILE *f = fopen("test.h", "w"); -#else - FILE *f = fopen(file, "w"); -#endif - write_to_file(f, "int l2c_idx", l2c_idx, entry*Zc); - write_to_file(f, "int c2b_idx", c2b_idx, entry*Zc); - write_to_file(f, "int b2c_idx", b2c_idx, entry*Zc); - write_to_file(f, "int cnproc_start_idx", cnproc_start_idx, entry*Zc); - write_to_file(f, "int cnproc_end_idx", cnproc_end_idx, entry*Zc); - write_to_file(f, "int bnproc_start_idx", bnproc_start_idx, entry*Zc); - write_to_file(f, "int bnproc_end_idx", bnproc_end_idx, entry*Zc); - write_to_file(f, "int llr_idx", llr_idx, col*Zc+1); - write_to_file(f, "int l2b_idx", l2b_idx, entry*Zc); - - fclose(f); -} - - -int main(int argc, char** argv) -{ - int test_BG[4*5] ={ 2, 0, 1, 2, 0, - 0, 3, 0, 2, 2, - 1, 0, 3, 3, 0, - 0, 3, 0, 0, 1}; - // default - int idx = 0, Zc = 384, BG = 1; - int max_row = 46, max_col = 68; - int entry = 316; - char *header_file = "bg1_i1_index_array.h"; -#ifdef test - if(argc == 1){ - printf("\nusage: %s [BG_row] [BG_col] [Zc] [entry] [output_header]\n\n", argv[0]); - return -1; - } -#endif - if(argc == 6){ - max_row = atoi(argv[1]); - max_col = atoi(argv[2]); - Zc = atoi(argv[3]); - entry = atoi(argv[4]); - header_file = argv[5]; - printf("max_row %d, max_col %d, Zc %d\n", max_row, max_col, Zc); - } -#ifdef test - build_index(test_BG, max_row, max_col, Zc); -#else - build_index(BG1_I1, max_row, max_col, Zc); -#endif - generate_header(header_file, max_col, entry, Zc); - - return 0; -} diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/ldpc.cu b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/ldpc.cu deleted file mode 100644 index f0f68a50f3..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/ldpc.cu +++ /dev/null @@ -1,297 +0,0 @@ -#include -#include -#include -#include -#include -#include "bg1_i1_index_array.h" - -void print_arr_cpu(const char *file, int *arr, int size) -{ - FILE *fp = fopen(file, "w"); - for(int i = 0; i < size; i++){ - fprintf(fp, "%s[%d]: %d\n", file, i, arr[i]); - } - fclose(fp); -} - -void print_arr(const char *file, int *arr, int size) -{ - int *tmp = (int*)malloc(sizeof(int)*size); - FILE *fp = fopen(file, "w"); - cudaMemcpy((void*)tmp, (const void*)arr, size*sizeof(int), cudaMemcpyDeviceToHost); - cudaDeviceSynchronize(); - for(int i = 0; i < size; i++){ - fprintf(fp, "%s[%d]: %d\n", file, i, tmp[i]); - } - free(tmp); - fclose(fp); -} - -__global__ void llr2CN(float *llr, float *cnbuf, int *l2c_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - cnbuf[tid] = llr[l2c_idx[tid]]; - __syncthreads(); -} - -__global__ void llr2BN(float *llr, float *const_llr, int *l2b_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - const_llr[tid] = llr[l2b_idx[tid]]; - __syncthreads(); -} - -__global__ void CNProcess(float *cnbuf, float *bnbuf, int *b2c_idx, int *cnproc_start_idx, int *cnproc_end_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - int start = cnproc_start_idx[tid]; - int end = cnproc_end_idx[tid]; - - - int sgn = 1, val = INT32_MAX; - for(int i = start; i < end; i++){ - if(i == tid) continue; - - int tmp = cnbuf[i]; - if(tmp < 0){ - tmp = -tmp; - sgn = -sgn; - } - if(val > tmp){ - val = tmp; - } - } - bnbuf[b2c_idx[tid]] = sgn*val;// + const_llr[tid]; - __syncthreads(); -} - -__global__ void add(int *bnbuf, int start, int pid, int *buf) -{ - __shared__ int sdata[25]; - int tid = threadIdx.x; - int num = blockDim.x; - sdata[tid] = bnbuf[start+tid]; - for(int s = num/2; s > 0; s>>=1){ - if(tid < s){ - sdata[tid] += sdata[tid+s]; - } - } - if(tid == 0){ - buf[pid] = sdata[tid]; - } -} - -__global__ void BNProcess(float *const_llr, float *bnbuf, float *cnbuf, int *c2b_idx, int *bnproc_start_idx, int *bnproc_end_idx, float *resbuf) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - float val = 0.0; - - int start = bnproc_start_idx[tid]; - int end = bnproc_end_idx[tid]; - for(int i = start; i < end; i++){ - if(i == tid) continue; - val += bnbuf[i]; - } - -// cnbuf[c2b_idx[tid]] = resbuf[tid] + const_llr[tid]; - cnbuf[c2b_idx[tid]] = val + const_llr[tid]; - __syncthreads(); -} - - -__global__ void BN2llr(float *const_llr, float *bnbuf, float *llrbuf, int *llr_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - int start = llr_idx[tid]; - int end = llr_idx[tid+1]; - - int res = 0.0; - for(int i = start; i < end; i++){ - res += bnbuf[i]; - } - llrbuf[tid] = res + const_llr[tid]; - __syncthreads(); -} - -__global__ void BitDetermination(float *BN, unsigned int *decode_d) -{ - __shared__ int tmp[256]; - int tid = blockIdx.x*256 + threadIdx.x; - int bid = threadIdx.x; - tmp[bid] = 0; - - - if(BN[tid] < 0) - { - tmp[bid] = 1 << (bid&7); - } - - __syncthreads(); - - if(threadIdx.x < 32) - { - decode_d[blockIdx.x*32 + threadIdx.x] = 0; - for(int i = 0; i < 8; i++) - { - decode_d[blockIdx.x*32 + threadIdx.x] += tmp[threadIdx.x*8+i]; - } - } -} - -void Read_Data(char *filename, int *data_sent, float *data_received) -{ - FILE *fp = fopen(filename, "r"); - fscanf(fp, "%*s"); - for(int i = 0; i < 1056; i++){ - fscanf(fp, "%d", &data_sent[i]); - } - fscanf(fp, "%*s"); - fscanf(fp, "%*s"); - fscanf(fp, "%*s"); - for(int i = 0; i < 26112; i++){ - fscanf(fp, "%f", &data_received[i]); - } - fclose(fp); -} - -int main(int argc, char **argv) -{ - int code_length = 8448, BG = 1; - int *input = (int*)malloc(1056*sizeof(int)); - float *llr = (float*)malloc(26112*sizeof(float)); - - float *llr_d, *llrbuf_d, *const_llr_d, *cnbuf_d, *bnbuf_d, *resbuf_d; - unsigned int *decode_output_h, *decode_output_d; - - int *l2c_idx_d, *cnproc_start_idx_d, *cnproc_end_idx_d, *c2b_idx_d, *bnproc_start_idx_d, *bnproc_end_idx_d, *b2c_idx_d, *llr_idx_d, *l2b_idx_d; - - char *file = argv[1]; - - - int blockNum = 237, threadNum = 512; - //int blockNum = 33, threadNum = 256; - //int blockNum = 17, threadNum = 512; - - int rounds = 5, Zc = 384; - - Read_Data(file, input, llr); - - - - size_t p_llr; - cudaHostAlloc((void**)&decode_output_h, 1056*sizeof(unsigned int), cudaHostAllocMapped); - - cudaMallocPitch((void**)&llr_d, &p_llr, 26112*sizeof(float), 1); - cudaMallocPitch((void**)&llrbuf_d, &p_llr, 26112*sizeof(float), 1); - cudaMallocPitch((void**)&const_llr_d, &p_llr, 316*384*sizeof(float), 1); - cudaMallocPitch((void**)&cnbuf_d, &p_llr, 316*384*sizeof(float), 1); - cudaMallocPitch((void**)&bnbuf_d, &p_llr, 316*384*sizeof(float), 1); - cudaMallocPitch((void**)&l2c_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&l2b_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&cnproc_start_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&cnproc_end_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&c2b_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&bnproc_start_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&bnproc_end_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&b2c_idx_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&resbuf_d, &p_llr, 316*384*sizeof(int), 1); - cudaMallocPitch((void**)&llr_idx_d, &p_llr, 26113*sizeof(int), 1); - - cudaMemcpyAsync((void*)llr_d, (const void*)llr, 68*384*sizeof(float), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)l2c_idx_d, (const void*)l2c_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)l2b_idx_d, (const void*)l2b_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)cnproc_start_idx_d, (const void*)cnproc_start_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)cnproc_end_idx_d, (const void*)cnproc_end_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)c2b_idx_d, (const void*)c2b_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)bnproc_start_idx_d, (const void*)bnproc_start_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)bnproc_end_idx_d, (const void*)bnproc_end_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)b2c_idx_d, (const void*)b2c_idx, 316*384*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)llr_idx_d, (const void*)llr_idx, 26113*sizeof(int), cudaMemcpyHostToDevice); - - cudaHostGetDevicePointer((void**)&decode_output_d, (void*)decode_output_h, 0); - cudaDeviceSynchronize(); - - - printf("BG %d, Zc %d, code_length %d\n", BG, Zc, code_length); - - - cudaEvent_t start, end; - float time; - - cudaEventCreate(&start); - cudaEventCreate(&end); - cudaEventRecord(start, 0); - - - llr2CN<<>>(llr_d, cnbuf_d, l2c_idx_d); - llr2BN<<>>(llr_d, const_llr_d, l2b_idx_d); - -/* - print_arr("debug/const_llr_d", const_llr_d, 26112); - print_arr("debug/cnbuf_d", cnbuf_d, 316*384); - print_arr("debug/const_llrbuf_d", const_llrbuf_d, 316*384); -*/ - - char dir[] = "debug/", cn[] = "cnbuf", bn[] = "bnbuf", llrstr[] = "llrbuf_d"; - char str[100] = {}; - for(int i = 0; i < rounds; i++){ - CNProcess<<>>(cnbuf_d, bnbuf_d, b2c_idx_d, cnproc_start_idx_d, cnproc_end_idx_d); -#ifdef debug - snprintf(str, 20, "%s%s_%d", dir, bn, i+1); - print_arr(str, bnbuf_d, 316*384); -#endif - BNProcess<<>>(const_llr_d, bnbuf_d, cnbuf_d, c2b_idx_d, bnproc_start_idx_d, bnproc_end_idx_d, resbuf_d); -#ifdef debug - snprintf(str, 20, "%s%s_%d", dir, cn, i+1); - print_arr(str, cnbuf_d, 316*384); -#endif - BN2llr<<<51, 512>>>(llr_d, bnbuf_d, llrbuf_d, llr_idx_d); -#ifdef debug - snprintf(str, 20, "%s%s_%d", dir, llrstr, i+1); - print_arr(str, llrbuf_d, 26112); -#endif - } - - BitDetermination<<<33, 256>>>(llrbuf_d, decode_output_d); - cudaDeviceSynchronize(); - - - cudaEventRecord(end, 0); - cudaEventSynchronize(end); - cudaEventElapsedTime(&time, start, end); - printf("time: %.6f ms\n", time); - - - int err = 0; - for(int i = 0; i < 8448/8; i++){ - if(input[i] != decode_output_h[i]){ -// printf("input[%d] :%d, decode_output[%d]: %d\n", i, input[i], i, decode_output_h[i]); - err++; - } - } - printf("err: %d\n", err); - - free(input); - free(llr); - cudaFree(llr_d); - cudaFree(llrbuf_d); - cudaFree(bnbuf_d); - cudaFree(cnbuf_d); - cudaFree(l2c_idx_d); - cudaFree(cnproc_start_idx_d); - cudaFree(cnproc_end_idx_d); - cudaFree(c2b_idx_d); - cudaFree(bnproc_start_idx_d); - cudaFree(bnproc_end_idx_d); - cudaFree(b2c_idx_d); - cudaFree(const_llr_d); - cudaFree(llr_idx_d); - cudaFree(resbuf_d); - - cudaFreeHost(decode_output_h); - return 0; -} diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.cu b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.cu deleted file mode 100644 index ad33a94b03..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.cu +++ /dev/null @@ -1,228 +0,0 @@ -#include -#include -#include -#include -#include -#include "test.h" - -void print_arr_cpu(const char *file, int *arr, int size) -{ - FILE *fp = fopen(file, "w"); - for(int i = 0; i < size; i++){ - fprintf(fp, "%s[%d]: %d\n", file, i, arr[i]); - } - fclose(fp); -} - -void print_arr(const char *file, int *arr, int size) -{ - int *tmp = (int*)malloc(sizeof(int)*size); - FILE *fp = fopen(file, "w"); - cudaMemcpy((void*)tmp, (const void*)arr, size*sizeof(int), cudaMemcpyDeviceToHost); - cudaDeviceSynchronize(); - for(int i = 0; i < size; i++){ - fprintf(fp, "%s[%d]: %d\n", file, i, tmp[i]); - } - free(tmp); - fclose(fp); -} - -__global__ void llr2CN(int *llr, int *cnbuf, int *l2c_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - cnbuf[tid] = llr[l2c_idx[tid]]; - __syncthreads(); -} - -__global__ void llr2BN(int *llr, int *const_llr, int *l2b_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - const_llr[tid] = llr[l2b_idx[tid]]; - __syncthreads(); -} - -__global__ void CNProcess(int *cnbuf, int *bnbuf, int *b2c_idx, int *cnproc_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - int start = cnproc_idx[tid*2]; - int end = cnproc_idx[tid*2+1]; -/* - if (tid == 6){ - printf("start %d, end %d\n", start, end); - } -*/ - int sgn = 1, val = INT32_MAX; - for(int i = start; i < end; i++){ - if(i == tid) continue; - - int tmp = cnbuf[i]; -// if(tid == 6) printf("tmp %d\n", tmp); - if(tmp < 0){ - tmp = -tmp; - sgn = -sgn; - } - if(val > tmp){ - val = tmp; -// if(tid == 6)printf("val = tmp\n"); - } -// if(tid == 6) printf("%d\n", val); - } -/* - if(tid == 6){ - printf("b2c_idx[6] %d\n", b2c_idx[tid]); - printf("sgn*val = %d\n", sgn*val); - printf("\n\n"); - } -*/ - bnbuf[b2c_idx[tid]] = sgn*val;// + const_llr[tid]; - __syncthreads(); -} - -__global__ void BNProcess(int *const_llr, int *bnbuf, int *cnbuf, int *c2b_idx, int *bnproc_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - int start = bnproc_idx[tid*2]; - int end = bnproc_idx[tid*2+1]; - - int val = 0; - for(int i = start; i < end; i++){ - if(i == tid) continue; - val += bnbuf[i]; - } - cnbuf[c2b_idx[tid]] = val + const_llr[tid]; - __syncthreads(); -} - -__global__ void BN2llr(int *bnbuf, int *llrbuf, int *llr_idx) -{ - int tid = blockIdx.x*blockDim.x + threadIdx.x; - - int start = llr_idx[tid]; - int end = llr_idx[tid+1]; - - int res = 0; - for(int i = start; i < end; i++){ - res += bnbuf[i]; - } - llrbuf[tid] = res; - __syncthreads(); -} - -__global__ void BitDetermination(int *BN, unsigned int *decode_d) -{ - __shared__ int tmp[256]; - int tid = blockIdx.x*256 + threadIdx.x; - int bid = threadIdx.x; - tmp[bid] = 0; - - - if(BN[tid] < 0) - { - tmp[bid] = 1 << (bid&7); - } - - __syncthreads(); - - if(threadIdx.x < 32) - { - decode_d[blockIdx.x*32 + threadIdx.x] = 0; - for(int i = 0; i < 8; i++) - { - decode_d[blockIdx.x*32 + threadIdx.x] += tmp[threadIdx.x*8+i]; - } - } -} - - -int main(int argc, char **argv) -{ - int llr[15] = {-48, 27, -47, 13, 34, - -41, 51, 29, -6, -19, - -45, -42, -40, -6, -33}; - - int *llr_d, *llrbuf_d, *const_llr_d, *cnbuf_d, *bnbuf_d; - int *l2c_idx_d, *cnproc_idx_d, *c2b_idx_d, *bnproc_idx_d, *b2c_idx_d, *llr_idx_d, *l2b_idx_d; - - int blockNum = 6, threadNum = 11; - int rounds = 5, Zc = 3; - - size_t p_llr; - - cudaMallocPitch((void**)&llr_d, &p_llr, 15*sizeof(int), 1); - cudaMallocPitch((void**)&llrbuf_d, &p_llr, 15*sizeof(int), 1); - cudaMallocPitch((void**)&const_llr_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&cnbuf_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&bnbuf_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&l2c_idx_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&l2b_idx_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&cnproc_idx_d, &p_llr, 33*2*sizeof(int), 1); - cudaMallocPitch((void**)&c2b_idx_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&bnproc_idx_d, &p_llr, 33*2*sizeof(int), 1); - cudaMallocPitch((void**)&b2c_idx_d, &p_llr, 33*sizeof(int), 1); - cudaMallocPitch((void**)&llr_idx_d, &p_llr, 16*sizeof(int), 1); - - cudaMemcpyAsync((void*)llr_d, (const void*)llr, 15*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)l2c_idx_d, (const void*)l2c_idx, 33*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)l2b_idx_d, (const void*)l2b_idx, 33*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)cnproc_idx_d, (const void*)cnproc_idx, 33*2*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)c2b_idx_d, (const void*)c2b_idx, 33*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)bnproc_idx_d, (const void*)bnproc_idx, 33*2*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)b2c_idx_d, (const void*)b2c_idx, 33*sizeof(int), cudaMemcpyHostToDevice); - cudaMemcpyAsync((void*)llr_idx_d, (const void*)llr_idx, 16*sizeof(int), cudaMemcpyHostToDevice); - - cudaDeviceSynchronize(); - - - - llr2CN<<>>(llr_d, cnbuf_d, l2c_idx_d); - llr2CN<<>>(llr_d, const_llr_d, l2b_idx_d); - -/* - print_arr("debug/const_llr_d", const_llr_d, 26112); - print_arr("debug/cnbuf_d", cnbuf_d, 316*384); - print_arr("debug/const_llrbuf_d", const_llrbuf_d, 316*384); -*/ - - char debug[] = "debug/"; - char cn[] = "cnbuf"; - char bn[] = "bnbuf"; - char llrstr[] = "llrbuf_d"; - char str[100] = {}; - for(int i = 0; i < rounds; i++){ - CNProcess<<>>(cnbuf_d, bnbuf_d, b2c_idx_d, cnproc_idx_d); - snprintf(str, 20, "%s%s_%d", debug, bn, i+1); - cudaDeviceSynchronize(); - print_arr(str, bnbuf_d, 33); - - BNProcess<<>>(const_llr_d, bnbuf_d, cnbuf_d, c2b_idx_d, bnproc_idx_d); - snprintf(str, 20, "%s%s_%d", debug, cn, i+1); - print_arr(str, cnbuf_d, 33); - - BN2llr<<<3,5>>>(bnbuf_d, llrbuf_d, llr_idx_d); - snprintf(str, 20, "%s%s_%d", debug, llrstr, i+1); - print_arr(str, llrbuf_d, 15); - } - -// BitDetermination<<<33, 256>>>(llrbuf_d, decode_output_d); - cudaDeviceSynchronize(); - - - cudaFree(llrbuf_d); - cudaFree(bnbuf_d); - cudaFree(cnbuf_d); - cudaFree(l2c_idx_d); - cudaFree(l2b_idx_d); - cudaFree(cnproc_idx_d); - cudaFree(c2b_idx_d); - cudaFree(bnproc_idx_d); - cudaFree(b2c_idx_d); - cudaFree(llr_d); - cudaFree(const_llr_d); - cudaFree(llr_idx_d); - - return 0; -} diff --git a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.h b/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.h deleted file mode 100644 index 803386643a..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/optimized_ldpc/test/test.h +++ /dev/null @@ -1,7 +0,0 @@ -int l2c_idx[33] = { 1, 6, 10, 2, 7, 11, 0, 8, 9, 5, 10, 13, 3, 11, 14, 4, 9, 12, 0, 8, 11, 1, 6, 9, 2, 7, 10, 5, 12, 3, 13, 4, 14}; -int c2b_idx[33] = { 6, 18, 0, 21, 3, 24, 12, 29, 15, 31, 9, 27, 1, 22, 4, 25, 7, 19, 8, 16, 23, 2, 10, 26, 5, 13, 20, 17, 28, 11, 30, 14, 32}; -int b2c_idx[33] = { 2, 12, 21, 4, 14, 24, 0, 16, 18, 10, 22, 29, 6, 25, 31, 8, 19, 27, 1, 17, 26, 3, 13, 20, 5, 15, 23, 11, 28, 7, 30, 9, 32}; -int cnproc_idx[66] = { 0, 3, 0, 3, 0, 3, 3, 6, 3, 6, 3, 6, 6, 9, 6, 9, 6, 9, 9, 12, 9, 12, 9, 12, 12, 15, 12, 15, 12, 15, 15, 18, 15, 18, 15, 18, 18, 21, 18, 21, 18, 21, 21, 24, 21, 24, 21, 24, 24, 27, 24, 27, 24, 27, 27, 29, 27, 29, 29, 31, 29, 31, 31, 33, 31, 33}; -int bnproc_idx[66] = { 0, 2, 0, 2, 2, 4, 2, 4, 4, 6, 4, 6, 6, 8, 6, 8, 8, 10, 8, 10, 10, 12, 10, 12, 12, 14, 12, 14, 14, 16, 14, 16, 16, 18, 16, 18, 18, 21, 18, 21, 18, 21, 21, 24, 21, 24, 21, 24, 24, 27, 24, 27, 24, 27, 27, 29, 27, 29, 29, 31, 29, 31, 31, 33, 31, 33}; -int llr_idx[16] = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 21, 24, 27, 29, 31, 33}; -int l2b_idx[33] = { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14}; diff --git a/openair1/PHY/CODING/GPU_LDPC/test_input/8448/1.txt b/openair1/PHY/CODING/GPU_LDPC/test_input/8448/1.txt deleted file mode 100644 index 6602abd079..0000000000 --- a/openair1/PHY/CODING/GPU_LDPC/test_input/8448/1.txt +++ /dev/null @@ -1,6 +0,0 @@ -input -43 155 187 19 233 100 50 223 9 249 100 81 178 108 105 211 214 28 218 89 21 245 85 134 168 166 37 52 140 170 62 184 69 249 203 46 93 253 14 103 246 114 184 168 222 33 124 181 61 86 14 82 76 100 217 244 10 254 40 151 168 102 79 238 95 26 28 189 23 42 36 13 157 220 182 123 254 50 48 59 136 63 142 212 163 103 200 173 101 240 68 14 86 147 252 182 173 24 115 196 67 151 210 224 115 136 91 113 186 140 173 66 203 59 23 110 162 223 27 7 208 96 21 38 243 17 220 161 42 79 101 109 230 55 77 90 191 168 203 121 52 120 188 255 179 211 109 85 178 137 93 130 233 114 169 220 132 133 125 174 213 227 27 187 26 104 21 218 16 225 83 69 89 15 68 13 226 178 98 149 59 191 23 36 50 192 0 182 70 126 100 27 97 127 214 123 231 236 85 247 205 169 60 38 184 129 51 155 51 150 48 110 85 71 146 135 8 146 61 78 16 161 105 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-29 16 -45 -19 30 47 23 25 12 13 31 -28 -23 35 19 18 6 -35 10 38 3 34 -16 13 25 10 -31 36 -26 11 21 18 28 -33 -34 7 -12 -22 6 12 -17 23 -26 1 35 -15 -22 20 -2 19 30 -14 13 -30 16 8 25 -7 24 2 -27 -22 28 52 22 16 1 -42 0 -53 7 29 24 34 -27 48 -6 22 -27 29 12 41 -14 11 12 32 3 33 31 -22 -16 25 -5 -34 3 -2 -12 -25 -28 -13 24 3 -68 14 14 -33 6 32 15 16 23 6 43 20 -42 9 11 22 16 -36 31 37 -7 25 -28 -24 -54 -26 -26 34 -11 39 21 36 0 -5 33 37 -7 26 32 -7 8 -18 -36 19 5 -10 -3 -22 20 -39 7 5 26 17 2 -31 -29 55 -15 32 16 23 32 12 -36 -18 31 0 40 -37 -14 -5 29 10 -36 20 -28 1 -28 -7 22 9 35 -26 11 37 20 37 36 -25 -38 -46 6 36 29 31 2 22 -74 -35 8 7 -2 -4 -33 -12 -12 -24 -1 -33 -15 21 -20 25 37 11 28 -21 -33 24 15 24 -22 50 -25 -18 45 26 -36 -15 -49 13 -30 -39 -19 16 -32 14 11 25 -12 -11 39 -21 29 -35 -5 8 -48 26 8 -11 -33 40 16 25 -21 10 25 45 26 19 -5 -20 -22 8 -31 43 -39 -7 2 -11 -37 -26 -36 23 -43 30 -16 -33 -63 6 -31 49 -end diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index 95ee3fed17..3d3e920216 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -29,6 +29,8 @@ #include "PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" +#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h" + #define MAX_NUM_DLSCH_SEGMENTS 16 #define MAX_BLOCK_LENGTH 8448 @@ -395,14 +397,19 @@ int test_ldpc(short No_iteration, for(j=0;j Date: Wed, 13 May 2020 22:21:49 +0800 Subject: [PATCH 05/70] LDPC implementation on Quadro p5000 by NCTU OpinCommect --- .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I1 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I2 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I3 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I4 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I5 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I6 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I7 | 48 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I0 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I1 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I2 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I5 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I6 | 44 ++ .../PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I7 | 44 ++ .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu | 549 ++++++++++++++++++ .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h | 27 + .../nrLDPC_decoder_LYC_debug.cu | 396 +++++++++++++ .../CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h | 211 +++++++ .../nrLDPC_decoder_LYC/nrLDPC_init_mem.h | 86 +++ .../CODING/nrLDPC_decoder_LYC/nrLDPC_types.h | 106 ++++ 22 files changed, 2111 insertions(+) create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I1 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I2 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I3 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I4 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I5 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I6 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I7 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I0 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I1 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I2 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I5 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I6 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I7 create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0 new file mode 100644 index 0000000000..3223238db8 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0 @@ -0,0 +1,48 @@ +int h_base_0 [46*68] = { + 250, 69, 226, 159, -1, 100, 10, -1, -1, 59, 229, 110, 191, 9, -1, 195, 23, -1, 190, 35, 239, 31, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 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100644 index 0000000000..df209d30ce --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I2 @@ -0,0 +1,44 @@ +int h_base_10 [42*52] = { + 0, 0, 0, 0, -1, -1, 0, -1, -1, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 137, -1, -1, 124, 0, 0, 88, 0, 0, 55, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 20, 94, -1, 99, 9, -1, -1, -1, 108, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, 38, 15, -1, 102, 146, 12, 57, 53, 46, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 0, 136, -1, -1, -1, -1, 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b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3 new file mode 100644 index 0000000000..d9efe76f46 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3 @@ -0,0 +1,44 @@ +int h_base_11 [42*52] = { + 72, 110, 23, 181, -1, -1, 95, -1, -1, 8, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 53, -1, -1, 156, 115, 156, 115, 200, 29, 31, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 152, 131, -1, 46, 191, -1, -1, -1, 91, -1, 0, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, 185, 6, -1, 36, 124, 124, 110, 156, 133, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, +}; \ No newline at end of file diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4 new file mode 100644 index 0000000000..2522b14f2e --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4 @@ -0,0 +1,44 @@ +int h_base_12 [42*52] = { + 3, 26, 53, 35, -1, -1, 115, -1, -1, 127, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 19, -1, -1, 94, 104, 66, 84, 98, 69, 50, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 95, 106, -1, 92, 110, -1, -1, -1, 111, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 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+1,549 @@ + /*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu + * \brief LDPC implementation on Quadro p5000 by NCTU OpinCommect + * \author NCTU OpinConnect Terng-Yin Hsu/Yu-Chi Liang/Kai-Tai Yang/Yan-Bo Lin + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ + +#include +#include +#include +#include +#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h" +#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h" + +#include "bgs/BG1_I0" +#include "bgs/BG1_I1" +#include "bgs/BG1_I2" +#include "bgs/BG1_I3" +#include "bgs/BG1_I4" +#include "bgs/BG1_I5" +#include "bgs/BG1_I6" +#include "bgs/BG1_I7" +#include "bgs/BG2_I0" +#include "bgs/BG2_I1" +#include "bgs/BG2_I2" +#include "bgs/BG2_I3" +#include "bgs/BG2_I4" +#include "bgs/BG2_I5" +#include "bgs/BG2_I6" +#include "bgs/BG2_I7" + +#define MAX_ITERATION 5 +#define MC 1 + +#define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } +inline void cudaAssert(cudaError_t code, const char *file, int line) +{ + if (code != cudaSuccess){ + fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line); + exit(code); + } +} + +typedef struct{ + char x; + char y; + short value; +} h_element; + + +h_element h_compact1 [46*19] = {}; +h_element h_compact2 [68*30] = {}; + +__device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 +__device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 + +// row and col element count +__device__ __constant__ char h_ele_row_bg1_count[46] = { + 19, 19, 19, 19, 3, 8, 9, 7, 10, 9, + 7, 8, 7, 6, 7, 7, 6, 6, 6, 6, + 6, 6, 5, 5, 6, 5, 5, 4, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 4, 5, 5, + 4, 5, 4, 5, 5, 4}; +__device__ __constant__ char h_ele_col_bg1_count[68] = { + 30, 28, 7, 11, 9, 4, 8, 12, 8, 7, + 12, 10, 12, 11, 10, 7, 10, 10, 13, 7, + 8, 11, 12, 5, 6, 6, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1}; +__device__ __constant__ char h_ele_row_bg2_count[42] = { + 8, 10, 8, 10, 4, 6, 6, 6, 4, 5, + 5, 5, 4, 5, 5, 4, 5, 5, 4, 4, + 4, 4, 3, 4, 4, 3, 5, 3, 4, 3, + 5, 3, 4, 4, 4, 4, 4, 3, 4, 4, + 4, 4}; +__device__ __constant__ char h_ele_col_bg2_count[52] = { + 22, 23, 10, 5, 5, 14, 7, 13, 6, 8, + 9, 16, 9, 12, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1}; + + +__global__ void warmup() +{ + // warm up gpu for time measurement +} + + +// Kernel 1 +__global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) +{ +// if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp %d\n", threadIdx.x); + int iMCW = blockIdx.y; // codeword id + int iBlkRow = blockIdx.x; // block row in h_base + int iBlkCol; // block col in h_base + int iSubRow = threadIdx.x; // row index in sub_block of h_base + int iCol; // overall col index in h_base + int offsetR; + int shift_t; + +// For 2-min algorithm. + int Q_sign = 0; + int sq; + int Q, Q_abs; + int R_temp; + + int sign = 1; + int rmin1 = INT32_MAX; + int rmin2 = INT32_MAX; + char idx_min = 0; + + h_element h_element_t; + int s = (BG==1)? h_ele_row_bg1_count[iBlkRow]:h_ele_row_bg2_count[iBlkRow]; + offsetR = (iMCW * row*col*Zc) + iBlkRow * Zc + iSubRow; // row*col*Zc = size of dev_dt +// if(blockIdx.x == 0 && threadIdx.x == 1) printf("s: %d, offset %d\n", s, offsetR); +// The 1st recursion + for(int i = 0; i < s; i++) // loop through all the ZxZ sub-blocks in a row + { + h_element_t = dev_h_compact1[i*row+iBlkRow]; // compact_col == row + + iBlkCol = h_element_t.y; + shift_t = h_element_t.value; + + shift_t = (iSubRow + shift_t) % Zc; + iCol = (iMCW * col*Zc) + iBlkCol * Zc + shift_t; // col*Zc = size of llr + Q = dev_llr[iCol]; + Q_abs = (Q>0)? Q : -Q; + sq = Q < 0; +// if(blockIdx.x == 0 && threadIdx.x == 1) printf("i %d, icol %d, Q: %d\n", i, iCol, Q); + // quick version + sign = sign * (1 - sq * 2); + Q_sign |= sq << i; + + if (Q_abs < rmin1){ + rmin2 = rmin1; + rmin1 = Q_abs; + idx_min = i; + } else if (Q_abs < rmin2){ + rmin2 = Q_abs; + } + } + +// if(blockIdx.x == 0 && threadIdx.x == 1)printf("min1 %d, min2 %d, min1_idx %d\n", rmin1, rmin2, idx_min); + +// The 2nd recursion + for(int i = 0; i < s; i++){ + // v0: Best performance so far. 0.75f is the value of alpha. + sq = 1 - 2 * ((Q_sign >> i) & 0x01); +// R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); + R_temp = sign * sq * (i != idx_min ? rmin1 : rmin2); + // write results to global memory + h_element_t = dev_h_compact1[i*row+iBlkRow]; + int addr_temp = offsetR + h_element_t.y * row * Zc; + dev_dt[addr_temp] = R_temp; +// if(blockIdx.x == 0 && threadIdx.x == 1)printf("R_temp %d, temp_addr %d\n", R_temp, addr_temp); + } +} + +// Kernel_1 +__global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) +{ +// if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp\n"); + int iMCW = blockIdx.y; + int iBlkRow = blockIdx.x; // block row in h_base + int iBlkCol; // block col in h_base + int iSubRow = threadIdx.x; // row index in sub_block of h_base + int iCol; // overall col index in h_base + int offsetR; + int shift_t; + +// For 2-min algorithm. + int Q_sign = 0; + int sq; + int Q, Q_abs; + int R_temp; + + int sign = 1; + int rmin1 = INT32_MAX; + int rmin2 = INT32_MAX; + char idx_min = 0; + + h_element h_element_t; + int s = (BG==1)? h_ele_row_bg1_count[iBlkRow]: h_ele_row_bg2_count[iBlkRow]; + offsetR = (iMCW *row*col*Zc) + iBlkRow * Zc + iSubRow; // row * col * Zc = size of dev_dt +// if(blockIdx.x == 0 && threadIdx.x == 1) printf("s: %d, offset %d\n", s, offsetR); +// The 1st recursion + for(int i = 0; i < s; i++) // loop through all the ZxZ sub-blocks in a row + { + h_element_t = dev_h_compact1[i*row+iBlkRow]; + + iBlkCol = h_element_t.y; + shift_t = h_element_t.value; + shift_t = (iSubRow + shift_t) % Zc; + iCol = iBlkCol * Zc + shift_t; + + R_temp = dev_dt[offsetR + iBlkCol * row * Zc]; + + Q = dev_llr[iMCW * (col*Zc) + iCol] - R_temp; + Q_abs = (Q>0)? Q : -Q; +// if(blockIdx.x == 0 && threadIdx.x == 1) printf("i %d, icol %d, Q: %d\n", i, iCol, Q); + sq = Q < 0; + sign = sign * (1 - sq * 2); + Q_sign |= sq << i; + + if (Q_abs < rmin1){ + rmin2 = rmin1; + rmin1 = Q_abs; + idx_min = i; + } else if (Q_abs < rmin2){ + rmin2 = Q_abs; + } + + } + +// if(blockIdx.x == 0 && threadIdx.x == 1)printf("min1 %d, min2 %d, min1_idx %d\n", rmin1, rmin2, idx_min); + +// The 2nd recursion + for(int i = 0; i < s; i ++){ + sq = 1 - 2 * ((Q_sign >> i) & 0x01); +// R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); + R_temp = sign * sq * (i != idx_min ? rmin1 : rmin2); + + // write results to global memory + h_element_t = dev_h_compact1[i*row+iBlkRow]; + int addr_temp = h_element_t.y * row * Zc + offsetR; + dev_dt[addr_temp] = R_temp; +// if(blockIdx.x == 0 && threadIdx.x == 1)printf("R_temp %d, temp_addr %d\n", R_temp, addr_temp); + } +} + +// Kernel 2: VNP processing +__global__ void +ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int BG, int row, int col, int Zc) +{ + int iMCW = blockIdx.y; + int iBlkCol = blockIdx.x; + int iBlkRow; + int iSubCol = threadIdx.x; + int iRow; + int iCol; + + int shift_t, sf; + int APP; + + h_element h_element_t; + + // update all the llr values + iCol = iBlkCol * Zc + iSubCol; + APP = dev_const_llr[iMCW *col*Zc + iCol]; + int offsetDt = iMCW *row*col*Zc + iBlkCol * row * Zc; + int s = (BG==1)? h_ele_col_bg1_count[iBlkCol]:h_ele_col_bg2_count[iBlkCol]; + + for(int i = 0; i < s; i++) + { + h_element_t = dev_h_compact2[i*col+iBlkCol]; + + shift_t = h_element_t.value; + iBlkRow = h_element_t.x; + + sf = iSubCol - shift_t; + sf = (sf + Zc) % Zc; + + iRow = iBlkRow * Zc + sf; + APP = APP + dev_dt[offsetDt + iRow]; + } + if(APP > SCHAR_MAX) APP = SCHAR_MAX; + if(APP < SCHAR_MIN) APP = SCHAR_MIN; + // write back to device global memory + dev_llr[iMCW *col*Zc + iCol] = APP; +} + + +__global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc) +{ + __shared__ unsigned char tmp[128]; + int iMCW = blockIdx.y; + int tid = iMCW * col*Zc + blockIdx.x*128 + threadIdx.x; + int btid = threadIdx.x; + tmp[btid] = 0; + + if(dev[tid] < 0){ + tmp[btid] = 1 << (7-(btid&7)); + } + __syncthreads(); + + if(threadIdx.x < 16){ + host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; + for(int i = 0; i < 8; i++){ + host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; + } + } +} + +void read_BG(int BG, int *h, int row, int col) +{ + int compact_row = 30, compact_col = 19; + if(BG==2){compact_row = 10, compact_col = 23;} + + h_element h_element_temp; + + // init the compact matrix + for(int i = 0; i < compact_col; i++){ + for(int j = 0; j < row; j++){ + h_element_temp.x = 0; + h_element_temp.y = 0; + h_element_temp.value = -1; + h_compact1[i*row+j] = h_element_temp; // h[i][0-11], the same column + } + } + // scan the h matrix, and gengerate compact mode of h + for(int i = 0; i < row; i++){ + int k = 0; + for(int j = 0; j < col; j++){ + if(h[i*col+j] != -1){ + h_element_temp.x = i; + h_element_temp.y = j; + h_element_temp.value = h[i*col+j]; + h_compact1[k*row+i] = h_element_temp; + k++; + } + } + } + + // h_compact2 + // init the compact matrix + for(int i = 0; i < compact_row; i++){ + for(int j = 0; j < col; j++){ + h_element_temp.x = 0; + h_element_temp.y = 0; + h_element_temp.value = -1; + h_compact2[i*col+j] = h_element_temp; + } + } + + for(int j = 0; j < col; j++){ + int k=0; + for(int i = 0; i < row; i++){ + if(h[i*col+j] != -1){ + // although h is transposed, the (x,y) is still (iBlkRow, iBlkCol) + h_element_temp.x = i; + h_element_temp.y = j; + h_element_temp.value = h[i*col+j]; + h_compact2[k*col+j] = h_element_temp; + k++; + } + } + } + + /* + for(int i = 0; i < compact_col; i++){ + for(int j = 0; j < row; j++){ + printf("%3d, ", h_compact1[i*row+j].value); + } + printf("\n"); + } + + for(int i = 0; i < compact_row; i++){ + for(int j = 0; j < col; j++){ + printf("%3d,", h_compact2[i*col+j].value); + } + printf("\n"); + } + */ +} + + +extern "C" +int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder) +{ + // alloc mem + //unsigned char *decision = (unsigned char*)p_out; + + uint16_t Zc = p_decParams->Z; + uint8_t BG = p_decParams->BG; + uint8_t numMaxIter = p_decParams->numMaxIter; + e_nrLDPC_outMode outMode = p_decParams->outMode; + + uint8_t row,col; + if(BG == 1){ + row = 46; + col = 68; + } + else{ + row = 42; + col = 52; + } + int compact_row = 30, compact_col = 19, lift_index=0;; + if(BG==2){compact_row = 10, compact_col = 23;} + + short lift_set[][9] = { + {2,4,8,16,32,64,128,256}, + {3,6,12,24,48,96,192,384}, + {5,10,20,40,80,160,320}, + {7,14,28,56,112,224}, + {9,18,36,72,144,288}, + {11,22,44,88,176,352}, + {13,26,52,104,208}, + {15,30,60,120,240}, + {0} + }; + + for(int i = 0; lift_set[i][0] != 0; i++){ + for(int j = 0; lift_set[i][j] != 0; j++){ + if(Zc == lift_set[i][j]){ + lift_index = i; + break; + } + } + } + + int *h = NULL; + switch(lift_index){ + case 0: + h = (BG == 1)? h_base_0:h_base_8; + break; + case 1: + h = (BG == 1)? h_base_1:h_base_9; + break; + case 2: + h = (BG == 1)? h_base_2:h_base_10; + break; + case 3: + h = (BG == 1)? h_base_3:h_base_11; + break; + case 4: + h = (BG == 1)? h_base_4:h_base_12; + break; + case 5: + h = (BG == 1)? h_base_5:h_base_13; + break; + case 6: + h = (BG == 1)? h_base_6:h_base_14; + break; + case 7: + h = (BG == 1)? h_base_7:h_base_15; + break; + } + /* pack BG in compact graph */ + read_BG(BG, h, row, col); + + + int memorySize_h_compact1 = row * compact_col * sizeof(h_element); + int memorySize_h_compact2 = compact_row * col * sizeof(h_element); + +// cpu + int memorySize_hard_decision = col * Zc * sizeof(unsigned char) * MC; + + +// alloc memory + unsigned char *hard_decision = (unsigned char*)p_out; + +// gpu + int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; + int memorySize_dt_cuda = row * Zc * col * sizeof(char) * MC; + + +// alloc memory + char *dev_llr; + char *dev_dt; + char *dev_const_llr; + unsigned char *dev_tmp; + + cudaCheck( cudaMalloc((void **)&dev_tmp, memorySize_hard_decision) ); + cudaCheck( cudaMalloc((void **)&dev_llr, memorySize_llr_cuda) ); + cudaCheck( cudaMalloc((void **)&dev_const_llr, memorySize_llr_cuda) ); + cudaCheck( cudaMalloc((void **)&dev_dt, memorySize_dt_cuda) ); + +// memcpy host to device + + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, h_compact1, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, h_compact2, memorySize_h_compact2) ); + cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); +start_meas(time_decoder); + cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); + + +// Define CUDA kernel dimension + int blockSizeX = (Zc + 32 - 1)/ 32 * 32; // round block size to multiples of 32 + dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks + dim3 dimBlockKernel1(blockSizeX, 1, 1); + + dim3 dimGridKernel2(col, MC, 1); + dim3 dimBlockKernel2(blockSizeX, 1, 1); + cudaDeviceSynchronize(); + + cudaEvent_t start, end; + float time; + + warmup<<>>(); + warmup<<>>(); + + + cudaEventCreate(&start); + cudaEventCreate(&end); + cudaEventRecord(start, 0); + +// cudaProfilerStart(); + +// lauch kernel + for(int ii = 0; ii < MAX_ITERATION; ii++){ + // first kernel + if(ii == 0){ + ldpc_cnp_kernel_1st_iter + <<>> + (dev_llr, dev_dt, BG, row, col, Zc); + }else{ + ldpc_cnp_kernel + <<>> + (dev_llr, dev_dt, BG, row, col, Zc); + } + + // second kernel + + ldpc_vnp_kernel_normal + <<>> + (dev_llr, dev_dt, dev_const_llr, BG, row, col, Zc); + + } + int pack = block_length/128; + dim3 pack_block(pack, MC, 1); + pack_decoded_bit<<>>(dev_llr, dev_tmp, col, Zc); + + + cudaEventRecord(end, 0); + cudaEventSynchronize(end); + cudaEventElapsedTime(&time, start, end); + + + //cudaCheck( cudaMemcpy((*)hard_decision, (const void*)dev_tmp, memorySize_hard_decision, cudaMemcpyDeviceToHost) ); + cudaCheck( cudaMemcpy((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char), cudaMemcpyDeviceToHost) ); + cudaDeviceSynchronize(); +stop_meas(time_decoder); + + cudaCheck( cudaFree(dev_llr) ); + cudaCheck( cudaFree(dev_dt) ); + cudaCheck( cudaFree(dev_const_llr) ); + cudaCheck( cudaFree(dev_tmp) ); + + //free(hard_decision); + return MAX_ITERATION; + +} diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h new file mode 100644 index 0000000000..c9eb785595 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h @@ -0,0 +1,27 @@ +#ifndef __NR_LDPC_DECODER_LYC__H__ +#define __NR_LDPC_DECODER_LYC__H__ + +#include "nrLDPC_types.h" +#include "nrLDPC_init_mem.h" + +/*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h + * \brief LDPC implementation on Quadro p5000 by NCTU OpinCommect + * \author NCTU OpinConnect Terng-Yin Hsu/Yu-Chi Liang/Kai-Tai Yang/Yan-Bo Lin + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ + +/** + \brief LDPC decoder + \param p_decParams LDPC decoder parameters + \param p_llr Input LLRs + \param p_llrOut Output vector + \param p_profiler LDPC profiler statistics +*/ + +int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder); + +#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu new file mode 100644 index 0000000000..0d22a312bd --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu @@ -0,0 +1,396 @@ +#include +#include +#include +#include +#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h" +#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h" + +#define MAX_ITERATION 5 +#define CW 1 + +#define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } +inline void cudaAssert(cudaError_t code, const char *file, int line) +{ + if (code != cudaSuccess){ + fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line); + exit(code); + } +} +// row and col element count + + + +typedef struct{ + char x; + char y; + short value; +} h_element; + +__device__ __constant__ char h_element_count1_bg1[46] = { + 19, 19, 19, 19, 3, 8, 9, 7, 10, 9, + 7, 8, 7, 6, 7, 7, 6, 6, 6, 6, + 6, 6, 5, 5, 6, 5, 5, 4, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 4, 5, 5, + 4, 5, 4, 5, 5, 4}; +__device__ __constant__ char h_element_count2_bg1[68] = { + 30, 28, 7, 11, 9, 4, 8, 12, 8, 7, + 12, 10, 12, 11, 10, 7, 10, 10, 13, 7, + 8, 11, 12, 5, 6, 6, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1}; +__device__ __constant__ char h_element_count1_bg2[42] = { + 8, 10, 8, 10, 4, 6, 6, 6, 4, 5, + 5, 5, 4, 5, 5, 4, 5, 5, 4, 4, + 4, 4, 3, 4, 4, 3, 5, 3, 4, 3, + 5, 3, 4, 4, 4, 4, 4, 3, 4, 4, + 4, 4}; +__device__ __constant__ char h_element_count2_bg2[52] = { + 22, 23, 10, 5, 5, 14, 7, 13, 6, 8, + 9, 16, 9, 12, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1}; + +// BG +__device__ __constant__ h_element dev_h_base1_1[316]={ + { .x= 0, .y= 0, .value=307 }, { .x= 0, .y= 1, .value= 19 }, { .x= 0, .y= 2, .value= 50 }, { .x= 0, .y= 3, .value=369 }, { .x= 0, .y= 5, .value=181 }, { .x= 0, .y= 6, .value=216 }, { .x= 0, .y= 9, .value=317 }, { .x= 0, .y=10, .value=288 }, { .x= 0, .y=11, .value=109 }, { .x= 0, .y=12, .value= 17 }, + { .x= 0, .y=13, .value=357 }, { .x= 0, .y=15, .value=215 }, { .x= 0, .y=16, .value=106 }, { .x= 0, .y=18, .value=242 }, { .x= 0, .y=19, .value=180 }, { .x= 0, .y=20, .value=330 }, { .x= 0, .y=21, .value=346 }, { .x= 0, .y=22, .value= 1 }, { .x= 0, .y=23, .value= 0 }, { .x= 1, .y= 0, .value= 76 }, + { .x= 1, .y= 2, .value= 76 }, { .x= 1, .y= 3, .value= 73 }, { .x= 1, .y= 4, .value=288 }, { .x= 1, .y= 5, .value=144 }, { .x= 1, .y= 7, .value=331 }, { .x= 1, .y= 8, .value=331 }, { .x= 1, .y= 9, .value=178 }, { .x= 1, .y=11, .value=295 }, { .x= 1, .y=12, .value=342 }, { .x= 1, .y=14, .value=217 }, + { .x= 1, .y=15, .value= 99 }, { .x= 1, .y=16, .value=354 }, { .x= 1, .y=17, .value=114 }, { .x= 1, .y=19, .value=331 }, { .x= 1, .y=21, .value=112 }, { .x= 1, .y=22, .value= 0 }, { .x= 1, .y=23, .value= 0 }, { .x= 1, .y=24, .value= 0 }, { .x= 2, .y= 0, .value=205 }, { .x= 2, .y= 1, .value=250 }, + { .x= 2, .y= 2, .value=328 }, { .x= 2, .y= 4, .value=332 }, { .x= 2, .y= 5, .value=256 }, { .x= 2, .y= 6, .value=161 }, { .x= 2, .y= 7, .value=267 }, { .x= 2, .y= 8, .value=160 }, { .x= 2, .y= 9, .value= 63 }, { .x= 2, .y=10, .value=129 }, { .x= 2, .y=13, .value=200 }, { .x= 2, .y=14, .value= 88 }, + { .x= 2, .y=15, .value= 53 }, { .x= 2, .y=17, .value=131 }, { .x= 2, .y=18, .value=240 }, { .x= 2, .y=19, .value=205 }, { .x= 2, .y=20, .value= 13 }, { .x= 2, .y=24, .value= 0 }, { .x= 2, .y=25, .value= 0 }, { .x= 3, .y= 0, .value=276 }, { .x= 3, .y= 1, .value= 87 }, { .x= 3, .y= 3, .value= 0 }, + { .x= 3, .y= 4, .value=275 }, { .x= 3, .y= 6, .value=199 }, { .x= 3, .y= 7, .value=153 }, { .x= 3, .y= 8, .value= 56 }, { .x= 3, .y=10, .value=132 }, { .x= 3, .y=11, .value=305 }, { .x= 3, .y=12, .value=231 }, { .x= 3, .y=13, .value=341 }, { .x= 3, .y=14, .value=212 }, { .x= 3, .y=16, .value=304 }, + { .x= 3, .y=17, .value=300 }, { .x= 3, .y=18, .value=271 }, { .x= 3, .y=20, .value= 39 }, { .x= 3, .y=21, .value=357 }, { .x= 3, .y=22, .value= 1 }, { .x= 3, .y=25, .value= 0 }, { .x= 4, .y= 0, .value=332 }, { .x= 4, .y= 1, .value=181 }, { .x= 4, .y=26, .value= 0 }, { .x= 5, .y= 0, .value=195 }, + { .x= 5, .y= 1, .value= 14 }, { .x= 5, .y= 3, .value=115 }, { .x= 5, .y=12, .value=166 }, { .x= 5, .y=16, .value=241 }, { .x= 5, .y=21, .value= 51 }, { .x= 5, .y=22, .value=157 }, { .x= 5, .y=27, .value= 0 }, { .x= 6, .y= 0, .value=278 }, { .x= 6, .y= 6, .value=257 }, { .x= 6, .y=10, .value= 1 }, + { .x= 6, .y=11, .value=351 }, { .x= 6, .y=13, .value= 92 }, { .x= 6, .y=17, .value=253 }, { .x= 6, .y=18, .value= 18 }, { .x= 6, .y=20, .value=225 }, { .x= 6, .y=28, .value= 0 }, { .x= 7, .y= 0, .value= 9 }, { .x= 7, .y= 1, .value= 62 }, { .x= 7, .y= 4, .value=316 }, { .x= 7, .y= 7, .value=333 }, + { .x= 7, .y= 8, .value=290 }, { .x= 7, .y=14, .value=114 }, { .x= 7, .y=29, .value= 0 }, { .x= 8, .y= 0, .value=307 }, { .x= 8, .y= 1, .value=179 }, { .x= 8, .y= 3, .value=165 }, { .x= 8, .y=12, .value= 18 }, { .x= 8, .y=16, .value= 39 }, { .x= 8, .y=19, .value=224 }, { .x= 8, .y=21, .value=368 }, + { .x= 8, .y=22, .value= 67 }, { .x= 8, .y=24, .value=170 }, { .x= 8, .y=30, .value= 0 }, { .x= 9, .y= 0, .value=366 }, { .x= 9, .y= 1, .value=232 }, { .x= 9, .y=10, .value=321 }, { .x= 9, .y=11, .value=133 }, { .x= 9, .y=13, .value= 57 }, { .x= 9, .y=17, .value=303 }, { .x= 9, .y=18, .value= 63 }, + { .x= 9, .y=20, .value= 82 }, { .x= 9, .y=31, .value= 0 }, { .x=10, .y= 1, .value=101 }, { .x=10, .y= 2, .value=339 }, { .x=10, .y= 4, .value=274 }, { .x=10, .y= 7, .value=111 }, { .x=10, .y= 8, .value=383 }, { .x=10, .y=14, .value=354 }, { .x=10, .y=32, .value= 0 }, { .x=11, .y= 0, .value= 48 }, + { .x=11, .y= 1, .value=102 }, { .x=11, .y=12, .value= 8 }, { .x=11, .y=16, .value= 47 }, { .x=11, .y=21, .value=188 }, { .x=11, .y=22, .value=334 }, { .x=11, .y=23, .value=115 }, { .x=11, .y=33, .value= 0 }, { .x=12, .y= 0, .value= 77 }, { .x=12, .y= 1, .value=186 }, { .x=12, .y=10, .value=174 }, + { .x=12, .y=11, .value=232 }, { .x=12, .y=13, .value= 50 }, { .x=12, .y=18, .value= 74 }, { .x=12, .y=34, .value= 0 }, { .x=13, .y= 0, .value=313 }, { .x=13, .y= 3, .value=177 }, { .x=13, .y= 7, .value=266 }, { .x=13, .y=20, .value=115 }, { .x=13, .y=23, .value=370 }, { .x=13, .y=35, .value= 0 }, + { .x=14, .y= 0, .value=142 }, { .x=14, .y=12, .value=248 }, { .x=14, .y=15, .value=137 }, { .x=14, .y=16, .value= 89 }, { .x=14, .y=17, .value=347 }, { .x=14, .y=21, .value= 12 }, { .x=14, .y=36, .value= 0 }, { .x=15, .y= 0, .value=241 }, { .x=15, .y= 1, .value= 2 }, { .x=15, .y=10, .value=210 }, + { .x=15, .y=13, .value=318 }, { .x=15, .y=18, .value= 55 }, { .x=15, .y=25, .value=269 }, { .x=15, .y=37, .value= 0 }, { .x=16, .y= 1, .value= 13 }, { .x=16, .y= 3, .value=338 }, { .x=16, .y=11, .value= 57 }, { .x=16, .y=20, .value=289 }, { .x=16, .y=22, .value= 57 }, { .x=16, .y=38, .value= 0 }, + { .x=17, .y= 0, .value=260 }, { .x=17, .y=14, .value=303 }, { .x=17, .y=16, .value= 81 }, { .x=17, .y=17, .value=358 }, { .x=17, .y=21, .value=375 }, { .x=17, .y=39, .value= 0 }, { .x=18, .y= 1, .value=130 }, { .x=18, .y=12, .value=163 }, { .x=18, .y=13, .value=280 }, { .x=18, .y=18, .value=132 }, + { .x=18, .y=19, .value= 4 }, { .x=18, .y=40, .value= 0 }, { .x=19, .y= 0, .value=145 }, { .x=19, .y= 1, .value=213 }, { .x=19, .y= 7, .value=344 }, { .x=19, .y= 8, .value=242 }, { .x=19, .y=10, .value=197 }, { .x=19, .y=41, .value= 0 }, { .x=20, .y= 0, .value=187 }, { .x=20, .y= 3, .value=206 }, + { .x=20, .y= 9, .value=264 }, { .x=20, .y=11, .value=341 }, { .x=20, .y=22, .value= 59 }, { .x=20, .y=42, .value= 0 }, { .x=21, .y= 1, .value=205 }, { .x=21, .y= 5, .value=102 }, { .x=21, .y=16, .value=328 }, { .x=21, .y=20, .value=213 }, { .x=21, .y=21, .value= 97 }, { .x=21, .y=43, .value= 0 }, + { .x=22, .y= 0, .value= 30 }, { .x=22, .y=12, .value= 11 }, { .x=22, .y=13, .value=233 }, { .x=22, .y=17, .value= 22 }, { .x=22, .y=44, .value= 0 }, { .x=23, .y= 1, .value= 24 }, { .x=23, .y= 2, .value= 89 }, { .x=23, .y=10, .value= 61 }, { .x=23, .y=18, .value= 27 }, { .x=23, .y=45, .value= 0 }, + { .x=24, .y= 0, .value=298 }, { .x=24, .y= 3, .value=158 }, { .x=24, .y= 4, .value=235 }, { .x=24, .y=11, .value=339 }, { .x=24, .y=22, .value=234 }, { .x=24, .y=46, .value= 0 }, { .x=25, .y= 1, .value= 72 }, { .x=25, .y= 6, .value= 17 }, { .x=25, .y= 7, .value=383 }, { .x=25, .y=14, .value=312 }, + { .x=25, .y=47, .value= 0 }, { .x=26, .y= 0, .value= 71 }, { .x=26, .y= 2, .value= 81 }, { .x=26, .y= 4, .value= 76 }, { .x=26, .y=15, .value=136 }, { .x=26, .y=48, .value= 0 }, { .x=27, .y= 1, .value=194 }, { .x=27, .y= 6, .value=194 }, { .x=27, .y= 8, .value=101 }, { .x=27, .y=49, .value= 0 }, + { .x=28, .y= 0, .value=222 }, { .x=28, .y= 4, .value= 19 }, { .x=28, .y=19, .value=244 }, { .x=28, .y=21, .value=274 }, { .x=28, .y=50, .value= 0 }, { .x=29, .y= 1, .value=252 }, { .x=29, .y=14, .value= 5 }, { .x=29, .y=18, .value=147 }, { .x=29, .y=25, .value= 78 }, { .x=29, .y=51, .value= 0 }, + { .x=30, .y= 0, .value=159 }, { .x=30, .y=10, .value=229 }, { .x=30, .y=13, .value=260 }, { .x=30, .y=24, .value= 90 }, { .x=30, .y=52, .value= 0 }, { .x=31, .y= 1, .value=100 }, { .x=31, .y= 7, .value=215 }, { .x=31, .y=22, .value=258 }, { .x=31, .y=25, .value=256 }, { .x=31, .y=53, .value= 0 }, + { .x=32, .y= 0, .value=102 }, { .x=32, .y=12, .value=201 }, { .x=32, .y=14, .value=175 }, { .x=32, .y=24, .value=287 }, { .x=32, .y=54, .value= 0 }, { .x=33, .y= 1, .value=323 }, { .x=33, .y= 2, .value= 8 }, { .x=33, .y=11, .value=361 }, { .x=33, .y=21, .value=105 }, { .x=33, .y=55, .value= 0 }, + { .x=34, .y= 0, .value=230 }, { .x=34, .y= 7, .value=148 }, { .x=34, .y=15, .value=202 }, { .x=34, .y=17, .value=312 }, { .x=34, .y=56, .value= 0 }, { .x=35, .y= 1, .value=320 }, { .x=35, .y= 6, .value=335 }, { .x=35, .y=12, .value= 2 }, { .x=35, .y=22, .value=266 }, { .x=35, .y=57, .value= 0 }, + { .x=36, .y= 0, .value=210 }, { .x=36, .y=14, .value=313 }, { .x=36, .y=15, .value=297 }, { .x=36, .y=18, .value= 21 }, { .x=36, .y=58, .value= 0 }, { .x=37, .y= 1, .value=269 }, { .x=37, .y=13, .value= 82 }, { .x=37, .y=23, .value=115 }, { .x=37, .y=59, .value= 0 }, { .x=38, .y= 0, .value=185 }, + { .x=38, .y= 9, .value=177 }, { .x=38, .y=10, .value=289 }, { .x=38, .y=12, .value=214 }, { .x=38, .y=60, .value= 0 }, { .x=39, .y= 1, .value=258 }, { .x=39, .y= 3, .value= 93 }, { .x=39, .y= 7, .value=346 }, { .x=39, .y=19, .value=297 }, { .x=39, .y=61, .value= 0 }, { .x=40, .y= 0, .value=175 }, + { .x=40, .y= 8, .value= 37 }, { .x=40, .y=17, .value=312 }, { .x=40, .y=62, .value= 0 }, { .x=41, .y= 1, .value= 52 }, { .x=41, .y= 3, .value=314 }, { .x=41, .y= 9, .value=139 }, { .x=41, .y=18, .value=288 }, { .x=41, .y=63, .value= 0 }, { .x=42, .y= 0, .value=113 }, { .x=42, .y= 4, .value= 14 }, + { .x=42, .y=24, .value=218 }, { .x=42, .y=64, .value= 0 }, { .x=43, .y= 1, .value=113 }, { .x=43, .y=16, .value=132 }, { .x=43, .y=18, .value=114 }, { .x=43, .y=25, .value=168 }, { .x=43, .y=65, .value= 0 }, { .x=44, .y= 0, .value= 80 }, { .x=44, .y= 7, .value= 78 }, { .x=44, .y= 9, .value=163 }, + { .x=44, .y=22, .value=274 }, { .x=44, .y=66, .value= 0 }, { .x=45, .y= 1, .value=135 }, { .x=45, .y= 6, .value=149 }, { .x=45, .y=10, .value= 15 }, { .x=45, .y=67, .value= 0 } }; +__device__ __constant__ h_element* dev_h_compact1[46]={ + &(dev_h_base1_1[ 0]), &(dev_h_base1_1[ 19]), &(dev_h_base1_1[ 38]), &(dev_h_base1_1[ 57]), &(dev_h_base1_1[ 76]), &(dev_h_base1_1[ 79]), &(dev_h_base1_1[ 87]), &(dev_h_base1_1[ 96]), &(dev_h_base1_1[103]), &(dev_h_base1_1[113]), + &(dev_h_base1_1[122]), &(dev_h_base1_1[129]), &(dev_h_base1_1[137]), &(dev_h_base1_1[144]), &(dev_h_base1_1[150]), &(dev_h_base1_1[157]), &(dev_h_base1_1[164]), &(dev_h_base1_1[170]), &(dev_h_base1_1[176]), &(dev_h_base1_1[182]), + &(dev_h_base1_1[188]), &(dev_h_base1_1[194]), &(dev_h_base1_1[200]), &(dev_h_base1_1[205]), &(dev_h_base1_1[210]), &(dev_h_base1_1[216]), &(dev_h_base1_1[221]), &(dev_h_base1_1[226]), &(dev_h_base1_1[230]), &(dev_h_base1_1[235]), + &(dev_h_base1_1[240]), &(dev_h_base1_1[245]), &(dev_h_base1_1[250]), &(dev_h_base1_1[255]), &(dev_h_base1_1[260]), &(dev_h_base1_1[265]), &(dev_h_base1_1[270]), &(dev_h_base1_1[275]), &(dev_h_base1_1[279]), &(dev_h_base1_1[284]), + &(dev_h_base1_1[289]), &(dev_h_base1_1[293]), &(dev_h_base1_1[298]), &(dev_h_base1_1[302]), &(dev_h_base1_1[307]), &(dev_h_base1_1[312]) }; +__device__ __constant__ h_element dev_h_base2_1[316]={ + { .x= 0, .y= 0, .value=307 }, { .x= 1, .y= 0, .value= 76 }, { .x= 2, .y= 0, .value=205 }, { .x= 3, .y= 0, .value=276 }, { .x= 4, .y= 0, .value=332 }, { .x= 5, .y= 0, .value=195 }, { .x= 6, .y= 0, .value=278 }, { .x= 7, .y= 0, .value= 9 }, { .x= 8, .y= 0, .value=307 }, { .x= 9, .y= 0, .value=366 }, + { .x=11, .y= 0, .value= 48 }, { .x=12, .y= 0, .value= 77 }, { .x=13, .y= 0, .value=313 }, { .x=14, .y= 0, .value=142 }, { .x=15, .y= 0, .value=241 }, { .x=17, .y= 0, .value=260 }, { .x=19, .y= 0, .value=145 }, { .x=20, .y= 0, .value=187 }, { .x=22, .y= 0, .value= 30 }, { .x=24, .y= 0, .value=298 }, + { .x=26, .y= 0, .value= 71 }, { .x=28, .y= 0, .value=222 }, { .x=30, .y= 0, .value=159 }, { .x=32, .y= 0, .value=102 }, { .x=34, .y= 0, .value=230 }, { .x=36, .y= 0, .value=210 }, { .x=38, .y= 0, .value=185 }, { .x=40, .y= 0, .value=175 }, { .x=42, .y= 0, .value=113 }, { .x=44, .y= 0, .value= 80 }, + { .x= 0, .y= 1, .value= 19 }, { .x= 2, .y= 1, .value=250 }, { .x= 3, .y= 1, .value= 87 }, { .x= 4, .y= 1, .value=181 }, { .x= 5, .y= 1, .value= 14 }, { .x= 7, .y= 1, .value= 62 }, { .x= 8, .y= 1, .value=179 }, { .x= 9, .y= 1, .value=232 }, { .x=10, .y= 1, .value=101 }, { .x=11, .y= 1, .value=102 }, + { .x=12, .y= 1, .value=186 }, { .x=15, .y= 1, .value= 2 }, { .x=16, .y= 1, .value= 13 }, { .x=18, .y= 1, .value=130 }, { .x=19, .y= 1, .value=213 }, { .x=21, .y= 1, .value=205 }, { .x=23, .y= 1, .value= 24 }, { .x=25, .y= 1, .value= 72 }, { .x=27, .y= 1, .value=194 }, { .x=29, .y= 1, .value=252 }, + { .x=31, .y= 1, .value=100 }, { .x=33, .y= 1, .value=323 }, { .x=35, .y= 1, .value=320 }, { .x=37, .y= 1, .value=269 }, { .x=39, .y= 1, .value=258 }, { .x=41, .y= 1, .value= 52 }, { .x=43, .y= 1, .value=113 }, { .x=45, .y= 1, .value=135 }, { .x= 0, .y= 2, .value= 50 }, { .x= 1, .y= 2, .value= 76 }, + { .x= 2, .y= 2, .value=328 }, { .x=10, .y= 2, .value=339 }, { .x=23, .y= 2, .value= 89 }, { .x=26, .y= 2, .value= 81 }, { .x=33, .y= 2, .value= 8 }, { .x= 0, .y= 3, .value=369 }, { .x= 1, .y= 3, .value= 73 }, { .x= 3, .y= 3, .value= 0 }, { .x= 5, .y= 3, .value=115 }, { .x= 8, .y= 3, .value=165 }, + { .x=13, .y= 3, .value=177 }, { .x=16, .y= 3, .value=338 }, { .x=20, .y= 3, .value=206 }, { .x=24, .y= 3, .value=158 }, { .x=39, .y= 3, .value= 93 }, { .x=41, .y= 3, .value=314 }, { .x= 1, .y= 4, .value=288 }, { .x= 2, .y= 4, .value=332 }, { .x= 3, .y= 4, .value=275 }, { .x= 7, .y= 4, .value=316 }, + { .x=10, .y= 4, .value=274 }, { .x=24, .y= 4, .value=235 }, { .x=26, .y= 4, .value= 76 }, { .x=28, .y= 4, .value= 19 }, { .x=42, .y= 4, .value= 14 }, { .x= 0, .y= 5, .value=181 }, { .x= 1, .y= 5, .value=144 }, { .x= 2, .y= 5, .value=256 }, { .x=21, .y= 5, .value=102 }, { .x= 0, .y= 6, .value=216 }, + { .x= 2, .y= 6, .value=161 }, { .x= 3, .y= 6, .value=199 }, { .x= 6, .y= 6, .value=257 }, { .x=25, .y= 6, .value= 17 }, { .x=27, .y= 6, .value=194 }, { .x=35, .y= 6, .value=335 }, { .x=45, .y= 6, .value=149 }, { .x= 1, .y= 7, .value=331 }, { .x= 2, .y= 7, .value=267 }, { .x= 3, .y= 7, .value=153 }, + { .x= 7, .y= 7, .value=333 }, { .x=10, .y= 7, .value=111 }, { .x=13, .y= 7, .value=266 }, { .x=19, .y= 7, .value=344 }, { .x=25, .y= 7, .value=383 }, { .x=31, .y= 7, .value=215 }, { .x=34, .y= 7, .value=148 }, { .x=39, .y= 7, .value=346 }, { .x=44, .y= 7, .value= 78 }, { .x= 1, .y= 8, .value=331 }, + { .x= 2, .y= 8, .value=160 }, { .x= 3, .y= 8, .value= 56 }, { .x= 7, .y= 8, .value=290 }, { .x=10, .y= 8, .value=383 }, { .x=19, .y= 8, .value=242 }, { .x=27, .y= 8, .value=101 }, { .x=40, .y= 8, .value= 37 }, { .x= 0, .y= 9, .value=317 }, { .x= 1, .y= 9, .value=178 }, { .x= 2, .y= 9, .value= 63 }, + { .x=20, .y= 9, .value=264 }, { .x=38, .y= 9, .value=177 }, { .x=41, .y= 9, .value=139 }, { .x=44, .y= 9, .value=163 }, { .x= 0, .y=10, .value=288 }, { .x= 2, .y=10, .value=129 }, { .x= 3, .y=10, .value=132 }, { .x= 6, .y=10, .value= 1 }, { .x= 9, .y=10, .value=321 }, { .x=12, .y=10, .value=174 }, + { .x=15, .y=10, .value=210 }, { .x=19, .y=10, .value=197 }, { .x=23, .y=10, .value= 61 }, { .x=30, .y=10, .value=229 }, { .x=38, .y=10, .value=289 }, { .x=45, .y=10, .value= 15 }, { .x= 0, .y=11, .value=109 }, { .x= 1, .y=11, .value=295 }, { .x= 3, .y=11, .value=305 }, { .x= 6, .y=11, .value=351 }, + { .x= 9, .y=11, .value=133 }, { .x=12, .y=11, .value=232 }, { .x=16, .y=11, .value= 57 }, { .x=20, .y=11, .value=341 }, { .x=24, .y=11, .value=339 }, { .x=33, .y=11, .value=361 }, { .x= 0, .y=12, .value= 17 }, { .x= 1, .y=12, .value=342 }, { .x= 3, .y=12, .value=231 }, { .x= 5, .y=12, .value=166 }, + { .x= 8, .y=12, .value= 18 }, { .x=11, .y=12, .value= 8 }, { .x=14, .y=12, .value=248 }, { .x=18, .y=12, .value=163 }, { .x=22, .y=12, .value= 11 }, { .x=32, .y=12, .value=201 }, { .x=35, .y=12, .value= 2 }, { .x=38, .y=12, .value=214 }, { .x= 0, .y=13, .value=357 }, { .x= 2, .y=13, .value=200 }, + { .x= 3, .y=13, .value=341 }, { .x= 6, .y=13, .value= 92 }, { .x= 9, .y=13, .value= 57 }, { .x=12, .y=13, .value= 50 }, { .x=15, .y=13, .value=318 }, { .x=18, .y=13, .value=280 }, { .x=22, .y=13, .value=233 }, { .x=30, .y=13, .value=260 }, { .x=37, .y=13, .value= 82 }, { .x= 1, .y=14, .value=217 }, + { .x= 2, .y=14, .value= 88 }, { .x= 3, .y=14, .value=212 }, { .x= 7, .y=14, .value=114 }, { .x=10, .y=14, .value=354 }, { .x=17, .y=14, .value=303 }, { .x=25, .y=14, .value=312 }, { .x=29, .y=14, .value= 5 }, { .x=32, .y=14, .value=175 }, { .x=36, .y=14, .value=313 }, { .x= 0, .y=15, .value=215 }, + { .x= 1, .y=15, .value= 99 }, { .x= 2, .y=15, .value= 53 }, { .x=14, .y=15, .value=137 }, { .x=26, .y=15, .value=136 }, { .x=34, .y=15, .value=202 }, { .x=36, .y=15, .value=297 }, { .x= 0, .y=16, .value=106 }, { .x= 1, .y=16, .value=354 }, { .x= 3, .y=16, .value=304 }, { .x= 5, .y=16, .value=241 }, + { .x= 8, .y=16, .value= 39 }, { .x=11, .y=16, .value= 47 }, { .x=14, .y=16, .value= 89 }, { .x=17, .y=16, .value= 81 }, { .x=21, .y=16, .value=328 }, { .x=43, .y=16, .value=132 }, { .x= 1, .y=17, .value=114 }, { .x= 2, .y=17, .value=131 }, { .x= 3, .y=17, .value=300 }, { .x= 6, .y=17, .value=253 }, + { .x= 9, .y=17, .value=303 }, { .x=14, .y=17, .value=347 }, { .x=17, .y=17, .value=358 }, { .x=22, .y=17, .value= 22 }, { .x=34, .y=17, .value=312 }, { .x=40, .y=17, .value=312 }, { .x= 0, .y=18, .value=242 }, { .x= 2, .y=18, .value=240 }, { .x= 3, .y=18, .value=271 }, { .x= 6, .y=18, .value= 18 }, + { .x= 9, .y=18, .value= 63 }, { .x=12, .y=18, .value= 74 }, { .x=15, .y=18, .value= 55 }, { .x=18, .y=18, .value=132 }, { .x=23, .y=18, .value= 27 }, { .x=29, .y=18, .value=147 }, { .x=36, .y=18, .value= 21 }, { .x=41, .y=18, .value=288 }, { .x=43, .y=18, .value=114 }, { .x= 0, .y=19, .value=180 }, + { .x= 1, .y=19, .value=331 }, { .x= 2, .y=19, .value=205 }, { .x= 8, .y=19, .value=224 }, { .x=18, .y=19, .value= 4 }, { .x=28, .y=19, .value=244 }, { .x=39, .y=19, .value=297 }, { .x= 0, .y=20, .value=330 }, { .x= 2, .y=20, .value= 13 }, { .x= 3, .y=20, .value= 39 }, { .x= 6, .y=20, .value=225 }, + { .x= 9, .y=20, .value= 82 }, { .x=13, .y=20, .value=115 }, { .x=16, .y=20, .value=289 }, { .x=21, .y=20, .value=213 }, { .x= 0, .y=21, .value=346 }, { .x= 1, .y=21, .value=112 }, { .x= 3, .y=21, .value=357 }, { .x= 5, .y=21, .value= 51 }, { .x= 8, .y=21, .value=368 }, { .x=11, .y=21, .value=188 }, + { .x=14, .y=21, .value= 12 }, { .x=17, .y=21, .value=375 }, { .x=21, .y=21, .value= 97 }, { .x=28, .y=21, .value=274 }, { .x=33, .y=21, .value=105 }, { .x= 0, .y=22, .value= 1 }, { .x= 1, .y=22, .value= 0 }, { .x= 3, .y=22, .value= 1 }, { .x= 5, .y=22, .value=157 }, { .x= 8, .y=22, .value= 67 }, + { .x=11, .y=22, .value=334 }, { .x=16, .y=22, .value= 57 }, { .x=20, .y=22, .value= 59 }, { .x=24, .y=22, .value=234 }, { .x=31, .y=22, .value=258 }, { .x=35, .y=22, .value=266 }, { .x=44, .y=22, .value=274 }, { .x= 0, .y=23, .value= 0 }, { .x= 1, .y=23, .value= 0 }, { .x=11, .y=23, .value=115 }, + { .x=13, .y=23, .value=370 }, { .x=37, .y=23, .value=115 }, { .x= 1, .y=24, .value= 0 }, { .x= 2, .y=24, .value= 0 }, { .x= 8, .y=24, .value=170 }, { .x=30, .y=24, .value= 90 }, { .x=32, .y=24, .value=287 }, { .x=42, .y=24, .value=218 }, { .x= 2, .y=25, .value= 0 }, { .x= 3, .y=25, .value= 0 }, + { .x=15, .y=25, .value=269 }, { .x=29, .y=25, .value= 78 }, { .x=31, .y=25, .value=256 }, { .x=43, .y=25, .value=168 }, { .x= 4, .y=26, .value= 0 }, { .x= 5, .y=27, .value= 0 }, { .x= 6, .y=28, .value= 0 }, { .x= 7, .y=29, .value= 0 }, { .x= 8, .y=30, .value= 0 }, { .x= 9, .y=31, .value= 0 }, + { .x=10, .y=32, .value= 0 }, { .x=11, .y=33, .value= 0 }, { .x=12, .y=34, .value= 0 }, { .x=13, .y=35, .value= 0 }, { .x=14, .y=36, .value= 0 }, { .x=15, .y=37, .value= 0 }, { .x=16, .y=38, .value= 0 }, { .x=17, .y=39, .value= 0 }, { .x=18, .y=40, .value= 0 }, { .x=19, .y=41, .value= 0 }, + { .x=20, .y=42, .value= 0 }, { .x=21, .y=43, .value= 0 }, { .x=22, .y=44, .value= 0 }, { .x=23, .y=45, .value= 0 }, { .x=24, .y=46, .value= 0 }, { .x=25, .y=47, .value= 0 }, { .x=26, .y=48, .value= 0 }, { .x=27, .y=49, .value= 0 }, { .x=28, .y=50, .value= 0 }, { .x=29, .y=51, .value= 0 }, + { .x=30, .y=52, .value= 0 }, { .x=31, .y=53, .value= 0 }, { .x=32, .y=54, .value= 0 }, { .x=33, .y=55, .value= 0 }, { .x=34, .y=56, .value= 0 }, { .x=35, .y=57, .value= 0 }, { .x=36, .y=58, .value= 0 }, { .x=37, .y=59, .value= 0 }, { .x=38, .y=60, .value= 0 }, { .x=39, .y=61, .value= 0 }, + { .x=40, .y=62, .value= 0 }, { .x=41, .y=63, .value= 0 }, { .x=42, .y=64, .value= 0 }, { .x=43, .y=65, .value= 0 }, { .x=44, .y=66, .value= 0 }, { .x=45, .y=67, .value= 0 } }; +__device__ __constant__ h_element* dev_h_compact2[68]={ + &(dev_h_base2_1[ 0]), &(dev_h_base2_1[ 30]), &(dev_h_base2_1[ 58]), &(dev_h_base2_1[ 65]), &(dev_h_base2_1[ 76]), &(dev_h_base2_1[ 85]), &(dev_h_base2_1[ 89]), &(dev_h_base2_1[ 97]), &(dev_h_base2_1[109]), &(dev_h_base2_1[117]), + &(dev_h_base2_1[124]), &(dev_h_base2_1[136]), &(dev_h_base2_1[146]), &(dev_h_base2_1[158]), &(dev_h_base2_1[169]), &(dev_h_base2_1[179]), &(dev_h_base2_1[186]), &(dev_h_base2_1[196]), &(dev_h_base2_1[206]), &(dev_h_base2_1[219]), + &(dev_h_base2_1[226]), &(dev_h_base2_1[234]), &(dev_h_base2_1[245]), &(dev_h_base2_1[257]), &(dev_h_base2_1[262]), &(dev_h_base2_1[268]), &(dev_h_base2_1[274]), &(dev_h_base2_1[275]), &(dev_h_base2_1[276]), &(dev_h_base2_1[277]), + &(dev_h_base2_1[278]), &(dev_h_base2_1[279]), &(dev_h_base2_1[280]), &(dev_h_base2_1[281]), &(dev_h_base2_1[282]), &(dev_h_base2_1[283]), &(dev_h_base2_1[284]), &(dev_h_base2_1[285]), &(dev_h_base2_1[286]), &(dev_h_base2_1[287]), + &(dev_h_base2_1[288]), &(dev_h_base2_1[289]), &(dev_h_base2_1[290]), &(dev_h_base2_1[291]), &(dev_h_base2_1[292]), &(dev_h_base2_1[293]), &(dev_h_base2_1[294]), &(dev_h_base2_1[295]), &(dev_h_base2_1[296]), &(dev_h_base2_1[297]), + &(dev_h_base2_1[298]), &(dev_h_base2_1[299]), &(dev_h_base2_1[300]), &(dev_h_base2_1[301]), &(dev_h_base2_1[302]), &(dev_h_base2_1[303]), &(dev_h_base2_1[304]), &(dev_h_base2_1[305]), &(dev_h_base2_1[306]), &(dev_h_base2_1[307]), + &(dev_h_base2_1[308]), &(dev_h_base2_1[309]), &(dev_h_base2_1[310]), &(dev_h_base2_1[311]), &(dev_h_base2_1[312]), &(dev_h_base2_1[313]), &(dev_h_base2_1[314]), &(dev_h_base2_1[315]) }; + + + + +__device__ void cnp_1st(int row, char* dev_llr, char* dev_buf, int blk, int thd) +{ + int subrow = threadIdx.x, subcol = threadIdx.x, Zc = blockDim.x; + + for(int i = 0; i < row; i++) + { + int cnt = h_element_count1_bg1[i]; + int min1 = INT32_MAX, min2 = INT32_MAX; + int sign = 0, tsign = 1, idx = 0; + int irow = subrow + Zc*i; + + for(int j = 0; j < cnt; j++) + { + h_element tmp = dev_h_compact1[i][j]; + int icol = tmp.y * Zc + (subcol+tmp.value)%Zc; + + int Q = dev_llr[icol]; + int Q_abs = (Q>0)? Q:-Q; + char sq = (Q<0); + tsign = tsign*(1-sq*2); + sign |= (sq << j); + + if(threadIdx.x == thd && i == blk){ + printf("dev_llr[%d](Q): %d, total_sign: %d, sign: %d\n", icol, dev_llr[icol], tsign, sign); + } + + + if(Q_abs < min1){ + min2 = min1; + min1 = Q_abs; + idx = j; + }else if(Q_abs < min2){ + min2 = Q_abs; + } + } + + if(threadIdx.x == thd && i == blk){ + printf("sign: %d, idx: %d, min1: %d, min2: %d\n", sign, idx, min1, min2); + } + + + for(int j = 0; j < cnt; j++) + { + char sq = 1 - 2 * ((sign >> j) & 0x01); + int temp = tsign * sq * ((j != idx)? min1 : min2); + h_element tmp = dev_h_compact1[i][j]; + int addr = irow + tmp.y * row * Zc; + dev_buf[addr] = temp; + + if(threadIdx.x == thd && i == blk){ + printf("temp: %d, addr: %d\n", temp, addr); + } + } + } + __syncthreads(); +} + +__device__ void bnp(int row, int col, char* dev_llr, char* dev_const_llr, char* dev_buf, int blk, int thd) +{ + int subrow = threadIdx.x, subcol = threadIdx.x, Zc = blockDim.x; + for(int i = 0; i < col; i++) + { + int cnt = h_element_count2_bg1[i]; + int icol = i * Zc + subcol; + int sum = dev_const_llr[icol]; + + for(int j = 0; j < cnt; j++) + { + h_element tmp = dev_h_compact2[i][j]; + int irow = tmp.x * Zc + (subrow + Zc - tmp.value)%Zc; + int addr = i * row * Zc + irow; + sum = sum + dev_buf[addr]; + + if(threadIdx.x == thd && i == blk){ + printf("dev_buf[%d]: %d, sum: %d, x: %d, value: %d, irow: %d\n", addr, dev_buf[addr], sum, tmp.x, tmp.value, irow); + } + + } + if(sum > SCHAR_MAX) sum = SCHAR_MAX; + if(sum < SCHAR_MIN) sum = SCHAR_MIN; + dev_llr[icol] = sum; + } + __syncthreads(); +} + + +__device__ void cnp(int row, char* dev_llr, char* dev_buf, int blk, int thd) +{ + int subrow = threadIdx.x, subcol = threadIdx.x, Zc = blockDim.x; + + for(int i = 0; i < row; i++) + { + int cnt = h_element_count1_bg1[i]; + int min1 = INT32_MAX, min2 = INT32_MAX; + int sign = 0, tsign = 1, idx = 0; + int irow = subrow + Zc*i; + + for(int j = 0; j < cnt; j++) + { + h_element tmp = dev_h_compact1[i][j]; + int icol = tmp.y * Zc + (subcol+tmp.value)%Zc; + + int Q_last = dev_buf[tmp.y * row * Zc + irow]; + + int Q = dev_llr[icol] - Q_last; + int Q_abs = (Q>0)? Q:-Q; + char sq = (Q<0); + tsign = tsign*(1-sq*2); + sign |= (sq << j); + + if(threadIdx.x == thd && i == blk){ + printf("dev_llr[%d](Q): %d, total_sign: %d, sign: %d, last Q: %d, last_pos: %d\n", icol, dev_llr[icol], tsign, sign, Q_last, tmp.y * row * Zc + irow); + } + + + if(Q_abs < min1){ + min2 = min1; + min1 = Q_abs; + idx = j; + }else if(Q_abs < min2){ + min2 = Q_abs; + } + } + + if(threadIdx.x == thd && i == blk){ + printf("sign: %d, idx: %d, min1: %d, min2: %d\n", sign, idx, min1, min2); + } + + + for(int j = 0; j < cnt; j++) + { + char sq = 1 - 2 * ((sign >> j) & 0x01); + int temp = tsign * sq * ((j != idx)? min1 : min2); + h_element tmp = dev_h_compact1[i][j]; + int addr = irow + tmp.y * row * Zc; + dev_buf[addr] = temp; + + + if(threadIdx.x == thd && i == blk){ + printf("temp: %d, addr: %d\n", temp, addr); + } + } + } + __syncthreads(); +} + + + +__global__ void ldpc_decoder_gpu(int BG, char *dev_llr, char *dev_const_llr, char *dev_buf, int blk, int thd) +{ + int iteration = 5; + int row = 46, col = 68; + if(BG == 2){ + row = 42; + col = 52; + } + //extern __shared__ sh_llr[]; + //for() + + for(int i = 0; i < iteration; i++){ + if(i == 0){ + cnp_1st(row, dev_llr, dev_buf, blk, thd); + }else{ + cnp(row, dev_llr, dev_buf, blk, thd); + } + + bnp(row, col, dev_llr, dev_const_llr, dev_buf, blk, thd); + } + +} + + +__global__ void pack_decoded_bit(char *dev, unsigned char *host) +{ + __shared__ unsigned char tmp[256]; + int tid = blockIdx.x*128 + threadIdx.x; + int btid = threadIdx.x; + tmp[btid] = 0; + + if(dev[tid] < 0){ + tmp[btid] = 1 << (7-(btid&7)); + } + __syncthreads(); + + if(threadIdx.x < 16){ + host[blockIdx.x*16+threadIdx.x] = 0; + for(int i = 0; i < 8; i++){ + host[blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; + } + } +} + + +//void nrLDPC_decoder_LYC(int BG, int row, int col, int Zc, int block_length) +extern "C" +int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length) +{ + // alloc mem + unsigned char *decision = (unsigned char*)p_out; + + uint16_t Zc = p_decParams->Z; + uint8_t BG = p_decParams->BG; + uint8_t numMaxIter = p_decParams->numMaxIter; + e_nrLDPC_outMode outMode = p_decParams->outMode; + + uint8_t row,col; + if(BG == 1){ + row = 46; + col = 68; + } + else{ + row = 42; + col = 52; + } + // gpu mem size + int memsize_llr = col * Zc * sizeof(char); + int memsize_buf = col * Zc * row * sizeof(char); + + // gpu + char *dev_llr; + char *dev_const_llr; + char *dev_buf; + unsigned char *dev_tmp; + + // gpu alloc + int p; + cudaCheck( cudaMallocPitch((void**)&dev_llr, (size_t*)&p, memsize_llr, 1) ); + cudaCheck( cudaMallocPitch((void**)&dev_const_llr, (size_t*)&p, memsize_llr, 1) ); + cudaCheck( cudaMallocPitch((void**)&dev_buf, (size_t*)&p, memsize_buf, 1) ); + cudaCheck( cudaMallocPitch((void**)&dev_tmp, (size_t*)&p, memsize_llr, 1) ); + + // gpu memcpy + cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memsize_llr, cudaMemcpyHostToDevice) ); + cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memsize_llr, cudaMemcpyHostToDevice) ); + //cudaCheck( cudaMemcpy((void*)dev_const_llr, (const void*)p_llr, memsize_llr, cudaMemcpyHostToDevice) ); + + // gpu argument + dim3 block(CW, 1, 1); + dim3 thread(Zc, 1, 1); + + // debug info + int blk, thd; + fprintf(stderr, "block thread focus: \n"); + scanf("%d%d", &blk, &thd); + + ldpc_decoder_gpu<<>>(BG, dev_llr, dev_const_llr, dev_buf, blk, thd); + + int pack = block_length/128; + pack_decoded_bit<<>>(dev_llr, dev_tmp); + + cudaCheck( cudaMemcpy((void*)decision, (const void*)dev_tmp, block_length*sizeof(unsigned char), cudaMemcpyDeviceToHost) ); + + return MAX_ITERATION; + +} diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h new file mode 100644 index 0000000000..541ab25ea6 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h @@ -0,0 +1,211 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h + * \brief LDPC implementation on Quadro p5000 by NCTU OpinCommect + * \author NCTU OpinConnect Terng-Yin Hsu/Yu-Chi Liang/Kai-Tai Yang/Yan-Bo Lin + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ + +/*!\file nrLDPC_defs.h + * \brief Defines all constants and buffers for the LDPC decoder + * \author Sebastian Wagner (TCL Communications) Email: + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#ifndef __NR_LDPC_DEFS__H__ +#define __NR_LDPC_DEFS__H__ + +// ============================================================================== +// DEFINES + +/** Maximum lifting size */ +#define NR_LDPC_ZMAX 384 + +/** Number of columns in BG1 */ +#define NR_LDPC_NCOL_BG1 68 +/** Number of rows in BG1 */ +#define NR_LDPC_NROW_BG1 46 +/** Number of edges/entries in BG1 */ +#define NR_LDPC_NUM_EDGE_BG1 316 +/** Number of check node (CN) groups in BG1 + A CN group is defined by its number of connected bit nodes. */ +#define NR_LDPC_NUM_CN_GROUPS_BG1 9 +/** First column in BG1 that is connected to only a single CN */ +#define NR_LDPC_START_COL_PARITY_BG1 26 + +/** Number of columns in BG1 for rate 1/3 = 22/(68-2) */ +#define NR_LDPC_NCOL_BG1_R13 NR_LDPC_NCOL_BG1 +/** Number of columns in BG1 for rate 2/3 = 22/(35-2) */ +#define NR_LDPC_NCOL_BG1_R23 35 +/** Number of columns in BG1 for rate 8/9 ~ 22/(27-2) */ +#define NR_LDPC_NCOL_BG1_R89 27 + +/** Number of bit node (BN) groups in BG1 for rate 1/3 + A BN group is defined by its number of connected CNs. */ +#define NR_LDPC_NUM_BN_GROUPS_BG1_R13 30 +/** Number of bit node (BN) groups in BG1 for rate 2/3 */ +#define NR_LDPC_NUM_BN_GROUPS_BG1_R23 8 +/** Number of bit node (BN) groups in BG1 for rate 8/9 */ +#define NR_LDPC_NUM_BN_GROUPS_BG1_R89 5 + +/** Number of columns in BG2 */ +#define NR_LDPC_NCOL_BG2 52 +/** Number of rows in BG2 */ +#define NR_LDPC_NROW_BG2 42 +/** Number of edges/entries in BG2 */ +#define NR_LDPC_NUM_EDGE_BG2 197 +/** Number of check node (CN) groups in BG2 + A CN group is defined by its number of connected bit nodes. */ +#define NR_LDPC_NUM_CN_GROUPS_BG2 6 +/** First column in BG2 that is connected to only a single CN */ +#define NR_LDPC_START_COL_PARITY_BG2 14 + +/** Number of columns in BG2 for rate 1/5 = 10/(52-2) */ +#define NR_LDPC_NCOL_BG2_R15 NR_LDPC_NCOL_BG2 +/** Number of columns in BG2 for rate 1/3 = 10/(32-2) */ +#define NR_LDPC_NCOL_BG2_R13 32 +/** Number of columns in BG2 for rate 2/3 = 10/(17-2) */ +#define NR_LDPC_NCOL_BG2_R23 17 + +/** Number of bit node (BN) groups in BG2 for rate 1/5 + A BN group is defined by its number of connected CNs. */ +#define NR_LDPC_NUM_BN_GROUPS_BG2_R15 23 +/** Number of bit node (BN) groups in BG2 for rate 1/3 */ +#define NR_LDPC_NUM_BN_GROUPS_BG2_R13 10 +/** Number of bit node (BN) groups in BG2 for rate 2/3 */ +#define NR_LDPC_NUM_BN_GROUPS_BG2_R23 6 + +/** Worst case size of the CN processing buffer */ +#define NR_LDPC_SIZE_CN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX +/** Worst case size of the BN processing buffer */ +#define NR_LDPC_SIZE_BN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX + +/** Maximum number of possible input LLR = NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX */ +#define NR_LDPC_MAX_NUM_LLR 26112 + +// ============================================================================== +// GLOBAL CONSTANT VARIABLES + +/** Start addresses for the cnProcBuf for each CN group in BG1*/ +static const uint32_t lut_startAddrCnGroups_BG1[NR_LDPC_NUM_CN_GROUPS_BG1] = {0, 1152, 8832, 43392, 61824, 75264, 81408, 88320, 92160}; +/** Start addresses for the cnProcBuf for each CN group in BG2*/ +static const uint32_t lut_startAddrCnGroups_BG2[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 6912, 37632, 54912, 61824, 67968}; + +/** Number of BNs of CN group for BG1. + E.g. 10 means that there is a CN group where every CN is connected to 10 BNs */ +static const uint8_t lut_numBnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {3, 4, 5, 6, 7, 8, 9, 10, 19}; +/** Number of rows/CNs in every CN group for rate = 1/3 BG1, e.g. 5 rows of CNs connected to 4 BNs */ +static const uint8_t lut_numCnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 5, 18, 8, 5, 2, 2, 1, 4}; +/** Number of rows/CNs in every CN group for rate = 2/3 BG1, e.g. 3 rows of CNs connected to 7 BNs */ +static const uint8_t lut_numCnInCnGroups_BG1_R23[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 3, 2, 2, 1, 4}; +/** Number of rows/CNs in every CN group for rate = 8/9 BG1, e.g. 4 rows of CNs connected to 19 BNs */ +static const uint8_t lut_numCnInCnGroups_BG1_R89[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 0, 0, 0, 0, 4}; + +/** Number of connected BNs for every column in BG1 rate = 1/3, e.g. in first column all BNs are connected to 30 CNs */ +static const uint8_t lut_numEdgesPerBn_BG1_R13[NR_LDPC_START_COL_PARITY_BG1] = {30, 28, 7, 11, 9, 4, 8, 12, 8, 7, 12, 10, 12, 11, 10, 7, 10, 10, 13, 7, 8, 11, 12, 5, 6, 6}; +/** Number of connected BNs for every column in BG1 rate = 2/3, e.g. in first column all BNs are connected to 12 CNs */ +static const uint8_t lut_numEdgesPerBn_BG1_R23[NR_LDPC_START_COL_PARITY_BG1] = {12, 11, 4, 5, 5, 3, 4, 5, 5, 3, 6, 6, 6, 6, 5, 3, 6, 5, 6, 4, 5, 6, 6, 3, 3, 2}; +/** Number of connected BNs for every column in BG1 rate = 8/9, e.g. in first column all BNs are connected to 5 CNs */ +static const uint8_t lut_numEdgesPerBn_BG1_R89[NR_LDPC_START_COL_PARITY_BG1] = {5, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2}; + +/** Number of BNs of CN group for BG2. + E.g. 3 means that there is a CN group where every CN is connected to 3 BNs */ +static const uint8_t lut_numBnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {3, 4, 5, 6, 8, 10}; +/** Number of rows/CNs in every CN group for rate = 1/5 BG2, e.g. 6 rows of CNs connected to 3 BNs */ +static const uint8_t lut_numCnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {6, 20, 9, 3, 2, 2}; +/** Number of rows/CNs in every CN group for rate = 1/3 BG2, e.g. 8 rows of CNs connected to 4 BNs */ +static const uint8_t lut_numCnInCnGroups_BG2_R13[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 8, 7, 3, 2, 2}; +/** Number of rows/CNs in every CN group for rate = 2/3 BG2, e.g. 1 row of CNs connected to 4 BNs */ +static const uint8_t lut_numCnInCnGroups_BG2_R23[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 1, 0, 2, 2, 2}; + +/** Number of connected BNs for every column in BG2 rate = 1/5, e.g. in first column all BNs are connected to 22 CNs */ +static const uint8_t lut_numEdgesPerBn_BG2_R15[NR_LDPC_START_COL_PARITY_BG2] = {22, 23, 10, 5, 5, 14, 7, 13, 6, 8, 9, 16, 9, 12}; +/** Number of connected BNs for every column in BG2 rate = 1/3, e.g. in first column all BNs are connected to 14 CNs */ +static const uint8_t lut_numEdgesPerBn_BG2_R13[NR_LDPC_START_COL_PARITY_BG2] = {14, 16, 2, 4, 4, 6, 6, 8, 6, 6, 6, 13, 5, 7}; +/** Number of connected BNs for every column in BG2 rate = 2/3, e.g. in first column all BNs are connected to 6 CNs */ +static const uint8_t lut_numEdgesPerBn_BG2_R23[NR_LDPC_START_COL_PARITY_BG2] = { 6, 5, 2, 3, 3, 4, 3, 4, 3, 4, 3, 5, 2, 2}; + +// Number of groups for bit node processing +/** Number of connected CNs for every column/BN in BG1 for rate = 1/3, Worst case is BG1 with up to 30 CNs connected to one BN + E.g. 42 parity BNs connected to single CN */ + // BG1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +static const uint8_t lut_numBnInBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {42, 0, 0, 1, 1, 2, 4, 3, 1, 4, 3, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}; +/** Number of connected CNs for every column/BN in BG1 for rate = 2/3 */ +static const uint8_t lut_numBnInBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 9, 1, 5, 3, 7, 8, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/** Number of connected CNs for every column/BN in BG1 for rate = 8/9 */ +static const uint8_t lut_numBnInBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 1, 3,21, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +/** Number of connected CNs for every column/BN in BG2 for rate = 1/5, Worst case is BG1 with up to 30 CNs connected to one BN + E.g. 38 parity BNs connected to single CN */ + // BG2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +static const uint8_t lut_numBnInBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {38, 0, 0, 0, 2, 1, 1, 1, 2, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0}; +/** Number of connected CNs for every column/BN in BG2 for rate = 1/3 */ +static const uint8_t lut_numBnInBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {18, 1, 0, 2, 1, 5, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/** Number of connected CNs for every column/BN in BG2 for rate = 2/3 */ +static const uint8_t lut_numBnInBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 3, 3, 5, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +// Start addresses for the bnProcBuf for each BN group +// BG1 +/** Start address for every BN group within the BN processing buffer for BG1 rate = 1/3 */ +static const uint32_t lut_startAddrBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 17664, 19584, 24192, 34944, 44160, 47616, 62976, 75648, 94080, 99072, 109824}; +/** Start address for every BN group within the BN processing buffer for BG1 rate = 2/3 */ +static const uint32_t lut_startAddrBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 4224, 9984, 14592, 28032, 46464, 50688}; +/** Start address for every BN group within the BN processing buffer for BG1 rate = 8/9 */ +static const uint32_t lut_startAddrBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 2688, 26880, 28416}; + +/** Start address for every BN group within the LLR processing buffer for BG1 rate = 1/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 16512, 16896, 17664, 19200, 20352, 20736, 22272, 23424, 24960, 25344, 25728}; +/** Start address for every BN group within the LLR processing buffer for BG1 rate = 2/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 3840, 5760, 6912, 9600, 12672, 13056}; +/** Start address for every BN group within the LLR processing buffer for BG1 rate = 8/9 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 1536, 9600, 9984}; + +// BG2 +/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/5 */ +static const uint32_t lut_startAddrBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 18432, 20736, 23424, 26496, 33408, 37248, 41856, 46848, 52224, 58368, 66816}; +/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/3 */ +static const uint32_t lut_startAddrBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7680, 10752, 12672, 24192, 26880, 29952, 34944, 40320}; +/** Start address for every BN group within the BN processing buffer for BG2 rate = 2/3 */ +static const uint32_t lut_startAddrBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 3456, 9216, 13824, 17664}; + +/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/5 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 15360, 15744, 16128, 16512, 17280, 17664, 18048, 18432, 18816, 19200, 19584}; +/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7296, 8064, 8448, 10368, 10752, 11136, 11520, 11904}; +/** Start address for every BN group within the LLR processing buffer for BG2 rate = 2/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 2304, 4224, 5376, 6144}; + +/** Vector of 32 '1' in int8 for application with AVX2 */ +static const int8_t ones256_epi8[32] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +/** Vector of 32 '0' in int8 for application with AVX2 */ +static const int8_t zeros256_epi8[32] __attribute__ ((aligned(32))) = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +/** Vector of 32 '127' in int8 for application with AVX2 */ +static const int8_t maxLLR256_epi8[32] __attribute__ ((aligned(32))) = {127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127}; + +#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h new file mode 100644 index 0000000000..bdaa118e1f --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h @@ -0,0 +1,86 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file nrLDPC_init_mem.h + * \brief Defines the function to initialize the LDPC decoder and sets correct LUTs. + * \author Sebastian Wagner (TCL Communications) Email: + * \date 07-12-2018 + * \version 1.0 + * \note + * \warning + */ + +#ifndef __NR_LDPC_INIT_MEM__H__ +#define __NR_LDPC_INIT_MEM__H__ + +#include +#include "nrLDPC_defs.h" +#include "nrLDPC_types.h" + +#ifndef malloc32_clear +/** + \brief Allocates 32 byte aligned memory and initializes to zero + \param size Input size in bytes + \return Pointer to memory +*/ +static inline void* malloc32_clear(size_t size) +{ + void* ptr = (void*) memalign(32, size+32); + memset(ptr, 0, size); + return ptr; +} +#endif + +/** + \brief Allocates and initializes the internal decoder processing buffers + \param p_decParams Pointer to decoder parameters + \param p_lut Pointer to decoder LUTs + \return Number of LLR values +*/ +static inline t_nrLDPC_procBuf* nrLDPC_init_mem(void) +{ + t_nrLDPC_procBuf* p_procBuf = (t_nrLDPC_procBuf*) malloc32_clear(sizeof(t_nrLDPC_procBuf)); + + if (p_procBuf) + { + p_procBuf->cnProcBuf = (int8_t*) malloc32_clear(NR_LDPC_SIZE_CN_PROC_BUF*sizeof(int8_t)); + p_procBuf->cnProcBufRes = (int8_t*) malloc32_clear(NR_LDPC_SIZE_CN_PROC_BUF*sizeof(int8_t)); + p_procBuf->bnProcBuf = (int8_t*) malloc32_clear(NR_LDPC_SIZE_BN_PROC_BUF*sizeof(int8_t)); + p_procBuf->bnProcBufRes = (int8_t*) malloc32_clear(NR_LDPC_SIZE_BN_PROC_BUF*sizeof(int8_t)); + p_procBuf->llrRes = (int8_t*) malloc32_clear(NR_LDPC_MAX_NUM_LLR *sizeof(int8_t)); + p_procBuf->llrProcBuf = (int8_t*) malloc32_clear(NR_LDPC_MAX_NUM_LLR *sizeof(int8_t)); + } + + return(p_procBuf); +} + +static inline void nrLDPC_free_mem(t_nrLDPC_procBuf* p_procBuf) +{ + free(p_procBuf->cnProcBuf); + free(p_procBuf->cnProcBufRes); + free(p_procBuf->bnProcBuf); + free(p_procBuf->bnProcBufRes); + free(p_procBuf->llrRes); + free(p_procBuf->llrProcBuf); + + free(p_procBuf); +} +#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h new file mode 100644 index 0000000000..34322a7780 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h @@ -0,0 +1,106 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file nrLDPC_types.h + * \brief Defines all types for the LDPC decoder + * \author Sebastian Wagner (TCL Communications) Email: + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#ifndef __NR_LDPC_TYPES__H__ +#define __NR_LDPC_TYPES__H__ + +#include "PHY/TOOLS/time_meas.h" +#include "nrLDPC_defs.h" + +// ============================================================================== +// TYPES + +/** + Structure containing the pointers to the LUTs. + */ +typedef struct nrLDPC_lut { + const uint32_t* startAddrCnGroups; /**< Start addresses for CN groups in CN processing buffer */ + const uint8_t* numCnInCnGroups; /**< Number of CNs in every CN group */ + const uint8_t* numBnInBnGroups; /**< Number of CNs in every BN group */ + const uint32_t* startAddrBnGroups; /**< Start addresses for BN groups in BN processing buffer */ + const uint16_t* startAddrBnGroupsLlr; /**< Start addresses for BN groups in LLR processing buffer */ + const uint16_t** circShift[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT for circular shift values for all CN groups and Zs */ + const uint32_t** startAddrBnProcBuf[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT of start addresses of CN groups in BN proc buffer */ + const uint8_t** bnPosBnProcBuf[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT of BN positions in BG for CN groups */ + const uint16_t* llr2llrProcBufAddr; /**< LUT for transferring input LLRs to LLR processing buffer */ + const uint8_t* llr2llrProcBufBnPos; /**< LUT BN position in BG */ + const uint8_t** posBnInCnProcBuf[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT for llr2cnProcBuf */ +} t_nrLDPC_lut; + +/** + Enum with possible LDPC output formats. + */ +typedef enum nrLDPC_outMode { + nrLDPC_outMode_BIT, /**< 32 bits per uint32_t output */ + nrLDPC_outMode_BITINT8, /**< 1 bit per int8_t output */ + nrLDPC_outMode_LLRINT8 /**< Single LLR value per int8_t output */ +} e_nrLDPC_outMode; + +/** + Structure containing LDPC decoder parameters. + */ +typedef struct nrLDPC_dec_params { + uint8_t BG; /**< Base graph */ + uint16_t Z; /**< Lifting size */ + uint8_t R; /**< Decoding rate: Format 15,13,... for code rates 1/5, 1/3,... */ + uint8_t numMaxIter; /**< Maximum number of iterations */ + e_nrLDPC_outMode outMode; /**< Output format */ +} t_nrLDPC_dec_params; + +/** + Structure containing LDPC decoder processing time statistics. + */ +typedef struct nrLDPC_time_stats { + time_stats_t llr2llrProcBuf; /**< Statistics for function llr2llrProcBuf */ + time_stats_t llr2CnProcBuf; /**< Statistics for function llr2CnProcBuf */ + time_stats_t cnProc; /**< Statistics for function cnProc */ + time_stats_t cnProcPc; /**< Statistics for function cnProcPc */ + time_stats_t bnProcPc; /**< Statistics for function bnProcPc */ + time_stats_t bnProc; /**< Statistics for function bnProc */ + time_stats_t cn2bnProcBuf; /**< Statistics for function cn2bnProcBuf */ + time_stats_t bn2cnProcBuf; /**< Statistics for function bn2cnProcBuf */ + time_stats_t llrRes2llrOut; /**< Statistics for function llrRes2llrOut */ + time_stats_t llr2bit; /**< Statistics for function llr2bit */ + time_stats_t total; /**< Statistics for total processing time */ +} t_nrLDPC_time_stats; + +/** + Structure containing the processing buffers + */ +typedef struct nrLDPC_procBuf { + int8_t* cnProcBuf; /**< CN processing buffer */ + int8_t* cnProcBufRes; /**< Buffer for CN processing results */ + int8_t* bnProcBuf; /**< BN processing buffer */ + int8_t* bnProcBufRes; /**< Buffer for BN processing results */ + int8_t* llrRes; /**< Buffer for LLR results */ + int8_t* llrProcBuf; /**< LLR processing buffer */ +} t_nrLDPC_procBuf; + +#endif From da62b92f6edf07d2b737b6e185d8bae674d284ba Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Wed, 13 May 2020 22:24:40 +0800 Subject: [PATCH 06/70] Merge remote-tracking branch 'origin/develop' into NCTU_OpinConnect_LDPC --- ci-scripts/rrc-files/rbconfig.raw | Bin 0 -> 8 bytes ci-scripts/rrc-files/reconfig.raw | Bin 0 -> 479 bytes common/utils/nr/nr_common.c | 150 ++ common/utils/nr/nr_common.h | 65 + executables/uecap.raw | Bin 0 -> 2056 bytes openair1/PHY/CODING/DOC/LDPCImplementation.md | 26 + .../nrLDPC_decoder/nrLDPCdecoder_defs.h | 201 ++ openair1/PHY/CODING/nrLDPC_defs.h | 59 + .../nrLDPC_encoder/ldpc_encode_parity_check.c | 201 ++ .../nrLDPC_encoder/ldpc_encoder_optim.c | 146 ++ .../nrLDPC_encoder/ldpc_encoder_optim8seg.c | 225 ++ .../ldpc_encoder_optim8segmulti.c | 237 ++ openair1/PHY/CODING/nrLDPC_extern.h | 35 + openair1/PHY/CODING/nrLDPC_load.c | 76 + openair1/PHY/NR_REFSIG/ptrs_nr.c | 423 ++++ openair1/PHY/NR_REFSIG/ptrs_nr.h | 81 + .../PHY/NR_TRANSPORT/nr_dci_tools_common.c | 62 + openair1/PHY/NR_TRANSPORT/nr_prach.c | 650 +++++ openair1/PHY/NR_TRANSPORT/nr_prach.h | 891 +++++++ openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 370 +++ .../NR_TRANSPORT/nr_transport_proto_common.h | 1760 ++++++++++++++ openair1/SCHED_NR/nr_prach_procedures.c | 141 ++ openair1/SCHED_NR/phy_frame_config_nr.c | 435 ++++ openair1/SIMULATION/NR_PHY/prachsim.c | 666 ++++++ openair1/SIMULATION/NR_PHY/reconfig.raw | Bin 0 -> 479 bytes .../NR_MAC_UE/nr_ue_dci_configuration.c | 183 ++ .../LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c | 153 ++ openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h | 70 + openair2/RRC/LTE/rrc_eNB_endc.c | 243 ++ openair2/RRC/NR/rrc_gNB_UE_context.c | 223 ++ openair2/RRC/NR/rrc_gNB_UE_context.h | 80 + openair2/RRC/NR/rrc_gNB_internode.c | 127 + openair2/RRC/NR/rrc_gNB_nsa.c | 159 ++ openair2/RRC/NR/rrc_gNB_reconfig.c | 2085 +++++++++++++++++ .../CONF/enb.band7.master.conf | 298 +++ .../CONF/gnb.band257.tm1.32PRB.usrpx300.conf | 271 +++ .../CONF/gnb.band257.tm1.66PRB.usrpn300.conf | 270 +++ .../CONF/gnb.band261.tm1.32PRB.usrpn300.conf | 271 +++ .../gnb.band78.106PRB.30kHz,usrpb2x0.conf | 283 +++ .../CONF/gnb.band78.slave.conf | 284 +++ 40 files changed, 11900 insertions(+) create mode 100644 ci-scripts/rrc-files/rbconfig.raw create mode 100644 ci-scripts/rrc-files/reconfig.raw create mode 100644 common/utils/nr/nr_common.c create mode 100644 common/utils/nr/nr_common.h create mode 100644 executables/uecap.raw create mode 100644 openair1/PHY/CODING/DOC/LDPCImplementation.md create mode 100644 openair1/PHY/CODING/nrLDPC_decoder/nrLDPCdecoder_defs.h create mode 100644 openair1/PHY/CODING/nrLDPC_defs.h create mode 100644 openair1/PHY/CODING/nrLDPC_encoder/ldpc_encode_parity_check.c create mode 100644 openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim.c create mode 100644 openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8seg.c create mode 100644 openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8segmulti.c create mode 100644 openair1/PHY/CODING/nrLDPC_extern.h create mode 100644 openair1/PHY/CODING/nrLDPC_load.c create mode 100644 openair1/PHY/NR_REFSIG/ptrs_nr.c create mode 100644 openair1/PHY/NR_REFSIG/ptrs_nr.h create mode 100644 openair1/PHY/NR_TRANSPORT/nr_dci_tools_common.c create mode 100644 openair1/PHY/NR_TRANSPORT/nr_prach.c create mode 100644 openair1/PHY/NR_TRANSPORT/nr_prach.h create mode 100644 openair1/PHY/NR_TRANSPORT/nr_prach_common.c create mode 100644 openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h create mode 100644 openair1/SCHED_NR/nr_prach_procedures.c create mode 100644 openair1/SCHED_NR/phy_frame_config_nr.c create mode 100644 openair1/SIMULATION/NR_PHY/prachsim.c create mode 100644 openair1/SIMULATION/NR_PHY/reconfig.raw create mode 100644 openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c create mode 100644 openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c create mode 100644 openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h create mode 100644 openair2/RRC/LTE/rrc_eNB_endc.c create mode 100644 openair2/RRC/NR/rrc_gNB_UE_context.c create mode 100644 openair2/RRC/NR/rrc_gNB_UE_context.h create mode 100644 openair2/RRC/NR/rrc_gNB_internode.c create mode 100644 openair2/RRC/NR/rrc_gNB_nsa.c create mode 100644 openair2/RRC/NR/rrc_gNB_reconfig.c create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.master.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band261.tm1.32PRB.usrpn300.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.30kHz,usrpb2x0.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.slave.conf diff --git a/ci-scripts/rrc-files/rbconfig.raw b/ci-scripts/rrc-files/rbconfig.raw new file mode 100644 index 0000000000000000000000000000000000000000..b03f18d1219201d789d1c70e1dced3e84a932990 GIT binary patch literal 8 PcmWgP)DUkvz{3Cl2C4z8 literal 0 HcmV?d00001 diff --git a/ci-scripts/rrc-files/reconfig.raw b/ci-scripts/rrc-files/reconfig.raw new file mode 100644 index 0000000000000000000000000000000000000000..97b41d9b6b0f0662487ca39848f85e9c1f7f8594 GIT binary patch literal 479 zcmZvXK}Zx)0EYiJZ+7;%j_XKUh%ENXDK?21#KRUHp2H>+lyvMMF*~+WLFgem)aA{% zl66`(S%faD6@&yyL3n&?+qPmv2;D@MEa;eCx>&Z|yM5p7`&hU&j$JjxrW$?heDiE# zrp~RxosN$_z1U>h&8!6U&Bpv>RXxWN$Vq{N}IvEipfZ!CNn4gOq0Wp{R}^Kfa2pe-7*}_6@%Q6AZjd^V@W_3Ne!j2yN1Yorg8CJ&MSq*vtF|z9Rf}kw9 zOx9^wP&>JogICi$s@0-2 zPoAI>dgr#}5FkI0;q=V(#{Xt(%cWbI-oqTJ2GB)JI7a5$XTEsf?jL>hsog_Mw{JWI@5GhC+Q#8h* qJUD$YnWS13stM;DOiNO|EftB=CGW!CtAm++osPf`dKT!uA^!qOo0Vh$ literal 0 HcmV?d00001 diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c new file mode 100644 index 0000000000..8a236c49f9 --- /dev/null +++ b/common/utils/nr/nr_common.c @@ -0,0 +1,150 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/* \file config_ue.c + * \brief common utility functions for NR (gNB and UE) + * \author R. Knopp, + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ + +#include +#include "assertions.h" + +int NRRIV2BW(int locationAndBandwidth,int N_RB) { + int tmp = locationAndBandwidth/N_RB; + int tmp2 = locationAndBandwidth%N_RB; + + + if (tmp <= ((N_RB>>1)+1) && (tmp+tmp2)>1)+1) && (tmp+tmp2)0 && (NPRB + RBstart <= BWPsize),"Illegal NPRB/RBstart Configuration (%d,%d) for BWPsize %d\n",NPRB,RBstart,BWPsize); + + if (NPRB <= 1+(BWPsize>>1)) return(BWPsize*(NPRB-1)+RBstart); + else return(BWPsize*(BWPsize+1-NPRB) + (BWPsize-1-RBstart)); +} + +int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) { + return(PRBalloc_to_locationandbandwidth0(NPRB,RBstart,275)); +} +/// Target code rate tables indexed by Imcs +uint16_t nr_target_code_rate_table1[29] = {120, 157, 193, 251, 308, 379, 449, 526, 602, 679, 340, 378, 434, 490, 553, \ + 616, 658, 438, 466, 517, 567, 616, 666, 719, 772, 822, 873, 910, 948}; + // Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point +uint16_t nr_target_code_rate_table2[28] = {120, 193, 308, 449, 602, 378, 434, 490, 553, 616, 658, 466, 517, 567, \ + 616, 666, 719, 772, 822, 873, 1365, 711, 754, 797, 841, 885, 1833, 948}; +uint16_t nr_target_code_rate_table3[29] = {30, 40, 50, 64, 78, 99, 120, 157, 193, 251, 308, 379, 449, 526, 602, 340, \ + 378, 434, 490, 553, 616, 438, 466, 517, 567, 616, 666, 719, 772}; +uint16_t nr_tbs_table[93] = {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, \ + 336, 352, 368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, 640, 672, 704, 736, 768, 808, 848, 888, 928, 984, 1032, 1064, 1128, 1160, 1192, 1224, 1256, \ + 1288, 1320, 1352, 1416, 1480, 1544, 1608, 1672, 1736, 1800, 1864, 1928, 2024, 2088, 2152, 2216, 2280, 2408, 2472, 2536, 2600, 2664, 2728, 2792, 2856, 2976, \ + 3104, 3240, 3368, 3496, 3624, 3752, 3824}; + +uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx) { + switch(table_idx) { + case 1: + return (((Imcs<10)||(Imcs==29))?2:((Imcs<17)||(Imcs==30))?4:((Imcs<29)||(Imcs==31))?6:-1); + break; + + case 2: + return (((Imcs<5)||(Imcs==28))?2:((Imcs<11)||(Imcs==29))?4:((Imcs<20)||(Imcs==30))?6:((Imcs<28)||(Imcs==31))?8:-1); + break; + + case 3: + return (((Imcs<15)||(Imcs==29))?2:((Imcs<21)||(Imcs==30))?4:((Imcs<29)||(Imcs==31))?6:-1); + break; + + default: + AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx); + return(0); + break; + } +} + +uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx) { + switch(table_idx) { + case 1: + return (nr_target_code_rate_table1[Imcs]); + break; + + case 2: + return (nr_target_code_rate_table2[Imcs]); + break; + + case 3: + return (nr_target_code_rate_table3[Imcs]); + break; + + default: + AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx); + return(0); + break; + } +} + +int get_subband_size(int NPRB,int size) { + // implements table 5.2.1.4-2 from 36.214 + // + //Bandwidth part (PRBs) Subband size (PRBs) + // < 24 N/A + //24 – 72 4, 8 + //73 – 144 8, 16 + //145 – 275 16, 32 + + if (NPRB<24) return(1); + if (NPRB<72) return (size==0 ? 4 : 8); + if (NPRB<144) return (size==0 ? 8 : 16); + if (NPRB<275) return (size==0 ? 16 : 32); + AssertFatal(1==0,"Shouldn't get here, NPRB %d\n",NPRB); + +} + +void SLIV2SL(int SLIV,int *S,int *L) { + + int SLIVdiv14 = SLIV/14; + int SLIVmod14 = SLIV%14; + // Either SLIV = 14*(L-1) + S, or SLIV = 14*(14-L+1) + (14-1-S). Condition is 0 <= L <= 14-S + if ((SLIVdiv14 + 1) >= 0 && (SLIVdiv14 <= 13-SLIVmod14)) { + *L=SLIVdiv14+1; + *S=SLIVmod14; + } else { + *L=15-SLIVdiv14; + *S=13-SLIVmod14; + } + +} diff --git a/common/utils/nr/nr_common.h b/common/utils/nr/nr_common.h new file mode 100644 index 0000000000..979cf86343 --- /dev/null +++ b/common/utils/nr/nr_common.h @@ -0,0 +1,65 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/* \file config_ue.c + * \brief common utility functions for NR (gNB and UE) + * \author R. Knopp, + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ + +#include +#include "assertions.h" + +int NRRIV2BW(int locationAndBandwidth,int N_RB); +int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB); +int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize); +int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart); +extern uint16_t nr_target_code_rate_table1[29]; +extern uint16_t nr_target_code_rate_table2[28]; +extern uint16_t nr_target_code_rate_table3[29]; +extern uint16_t nr_tbs_table[93]; +uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx); +uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx); +int get_subband_size(int NPRB,int size); +void SLIV2SL(int SLIV,int *S,int *L); + + +#define CEILIDIV(a,b) ((a+b-1)/b) +#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1)) + +#define cmax(a,b) ((a>b) ? (a) : (b)) +#define cmax3(a,b,c) ((cmax(a,b)>c) ? (cmax(a,b)) : (c)) +#define cmin(a,b) ((aICy)mTYG*c}u|$m+F;8~WAO87I z?PQqlOCpW+r;%3JRS5Jc6eNf!PGYr1iirA9@S&#Ew;~$_L9Dr+xw{M279XV#9+sJJ z&N<(A&pCJJ&R|N+y#7P*)NEjJTkV|`UA-f#Z@$o3+xhO`;pKDVTI;v<@j49Ot3%k;E>6 z>42e7MVNLe=WCMPPqG~~bk^aeMZf%MOS^KzJd!21$h?hULqp~87NO@ER? z8NMgf2fP6I2}!bq1R|}0cO%S7KPJ+F*s_SUB3&Zg=E5rpbuzLQkqSf#Mc;Z#Kn{Ip zR*G_?OuT5;9u0TG?-)_H^Mb--o+zG-sFWx-4U0cSI**7xzYVIgB>PQWRW83@V{UWx z{Gv%nQ$3}Ybm?i~#2^U*Vl^$0YlUPhlmHWIv4U2}0171y8o{I4#bhcA8`PkqYDvp^ zGpBA926E`prVjNpwQdrUL2aR)yOPml3ThIp0ZfPf76-Y}FbhB9^sZCLfSMUEg`^or z#!(caxe%!F6N#V+ndBtY01Z~!;Up;fR_~(u`c!JSI+~^VSbU*B@O$q~_9D|~@jKkv z2n`T4#%n^N6>5MWlF8%?O44357dP7;4%4>NEIkrFzH%d-4L9I%^?ynK{@GYL031Bs z@m>J_>Sf?#I=<(=xVSMxwr`uU9Y@w0Ai3Uu%iKb}Uf-Dcloading `libldpc_optim8seg.so` instead of `libldpc.so` + +``` +./nr-softmodem -O libconfig:gnb.band78.tm1.106PRB.usrpx300.conf:dbgl5 --loader.ldpc.shlibversion _optim8seg +....................... +[CONFIG] loader.ldpc.shlibversion set to default value "" +[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value) +[CONFIG] shlibversion set to _optim8seg from command line +[CONFIG] loader.ldpc 1 options set from command line +[LOADER] library libldpc_optim8seg.so successfully loaded +........................ +``` + +Today, this mechanism is not available in the `ldpctest` phy simulator which doesn't initialize the [configuration module](file://../../../../common/config/DOC/config.md). loads `libldpc.so` and `libldpc_orig.so` to compare the performance of the two implementations. + +###LDPC libraries +Libraries implementing the LDPC algorithms must be named `libldpc<_version>.so`, they must implement two functions: `nrLDPC_decod` and `nrLDPC_encod`. The prototypes for these functions is defined in [nrLDPC_defs.h](file://nrLDPC_defs.h). + +[oai Wikis home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home) diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPCdecoder_defs.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPCdecoder_defs.h new file mode 100644 index 0000000000..c35f93e0fe --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPCdecoder_defs.h @@ -0,0 +1,201 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file nrLDPCdecoder_defs.h + * \brief Defines all constants and buffers for the LDPC decoder + * \author Sebastian Wagner (TCL Communications) Email: + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#ifndef __NR_LDPC_DEFS__H__ +#define __NR_LDPC_DEFS__H__ + +// ============================================================================== +// DEFINES + +/** Maximum lifting size */ +#define NR_LDPC_ZMAX 384 + +/** Number of columns in BG1 */ +#define NR_LDPC_NCOL_BG1 68 +/** Number of rows in BG1 */ +#define NR_LDPC_NROW_BG1 46 +/** Number of edges/entries in BG1 */ +#define NR_LDPC_NUM_EDGE_BG1 316 +/** Number of check node (CN) groups in BG1 + A CN group is defined by its number of connected bit nodes. */ +#define NR_LDPC_NUM_CN_GROUPS_BG1 9 +/** First column in BG1 that is connected to only a single CN */ +#define NR_LDPC_START_COL_PARITY_BG1 26 + +/** Number of columns in BG1 for rate 1/3 = 22/(68-2) */ +#define NR_LDPC_NCOL_BG1_R13 NR_LDPC_NCOL_BG1 +/** Number of columns in BG1 for rate 2/3 = 22/(35-2) */ +#define NR_LDPC_NCOL_BG1_R23 35 +/** Number of columns in BG1 for rate 8/9 ~ 22/(27-2) */ +#define NR_LDPC_NCOL_BG1_R89 27 + +/** Number of bit node (BN) groups in BG1 for rate 1/3 + A BN group is defined by its number of connected CNs. */ +#define NR_LDPC_NUM_BN_GROUPS_BG1_R13 30 +/** Number of bit node (BN) groups in BG1 for rate 2/3 */ +#define NR_LDPC_NUM_BN_GROUPS_BG1_R23 8 +/** Number of bit node (BN) groups in BG1 for rate 8/9 */ +#define NR_LDPC_NUM_BN_GROUPS_BG1_R89 5 + +/** Number of columns in BG2 */ +#define NR_LDPC_NCOL_BG2 52 +/** Number of rows in BG2 */ +#define NR_LDPC_NROW_BG2 42 +/** Number of edges/entries in BG2 */ +#define NR_LDPC_NUM_EDGE_BG2 197 +/** Number of check node (CN) groups in BG2 + A CN group is defined by its number of connected bit nodes. */ +#define NR_LDPC_NUM_CN_GROUPS_BG2 6 +/** First column in BG2 that is connected to only a single CN */ +#define NR_LDPC_START_COL_PARITY_BG2 14 + +/** Number of columns in BG2 for rate 1/5 = 10/(52-2) */ +#define NR_LDPC_NCOL_BG2_R15 NR_LDPC_NCOL_BG2 +/** Number of columns in BG2 for rate 1/3 = 10/(32-2) */ +#define NR_LDPC_NCOL_BG2_R13 32 +/** Number of columns in BG2 for rate 2/3 = 10/(17-2) */ +#define NR_LDPC_NCOL_BG2_R23 17 + +/** Number of bit node (BN) groups in BG2 for rate 1/5 + A BN group is defined by its number of connected CNs. */ +#define NR_LDPC_NUM_BN_GROUPS_BG2_R15 23 +/** Number of bit node (BN) groups in BG2 for rate 1/3 */ +#define NR_LDPC_NUM_BN_GROUPS_BG2_R13 10 +/** Number of bit node (BN) groups in BG2 for rate 2/3 */ +#define NR_LDPC_NUM_BN_GROUPS_BG2_R23 6 + +/** Worst case size of the CN processing buffer */ +#define NR_LDPC_SIZE_CN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX +/** Worst case size of the BN processing buffer */ +#define NR_LDPC_SIZE_BN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX + +/** Maximum number of possible input LLR = NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX */ +#define NR_LDPC_MAX_NUM_LLR 27000 + +// ============================================================================== +// GLOBAL CONSTANT VARIABLES + +/** Start addresses for the cnProcBuf for each CN group in BG1*/ +static const uint32_t lut_startAddrCnGroups_BG1[NR_LDPC_NUM_CN_GROUPS_BG1] = {0, 1152, 8832, 43392, 61824, 75264, 81408, 88320, 92160}; +/** Start addresses for the cnProcBuf for each CN group in BG2*/ +static const uint32_t lut_startAddrCnGroups_BG2[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 6912, 37632, 54912, 61824, 67968}; + +/** Number of BNs of CN group for BG1. + E.g. 10 means that there is a CN group where every CN is connected to 10 BNs */ +static const uint8_t lut_numBnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {3, 4, 5, 6, 7, 8, 9, 10, 19}; +/** Number of rows/CNs in every CN group for rate = 1/3 BG1, e.g. 5 rows of CNs connected to 4 BNs */ +static const uint8_t lut_numCnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 5, 18, 8, 5, 2, 2, 1, 4}; +/** Number of rows/CNs in every CN group for rate = 2/3 BG1, e.g. 3 rows of CNs connected to 7 BNs */ +static const uint8_t lut_numCnInCnGroups_BG1_R23[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 3, 2, 2, 1, 4}; +/** Number of rows/CNs in every CN group for rate = 8/9 BG1, e.g. 4 rows of CNs connected to 19 BNs */ +static const uint8_t lut_numCnInCnGroups_BG1_R89[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 0, 0, 0, 0, 4}; + +/** Number of connected BNs for every column in BG1 rate = 1/3, e.g. in first column all BNs are connected to 30 CNs */ +static const uint8_t lut_numEdgesPerBn_BG1_R13[NR_LDPC_START_COL_PARITY_BG1] = {30, 28, 7, 11, 9, 4, 8, 12, 8, 7, 12, 10, 12, 11, 10, 7, 10, 10, 13, 7, 8, 11, 12, 5, 6, 6}; +/** Number of connected BNs for every column in BG1 rate = 2/3, e.g. in first column all BNs are connected to 12 CNs */ +static const uint8_t lut_numEdgesPerBn_BG1_R23[NR_LDPC_START_COL_PARITY_BG1] = {12, 11, 4, 5, 5, 3, 4, 5, 5, 3, 6, 6, 6, 6, 5, 3, 6, 5, 6, 4, 5, 6, 6, 3, 3, 2}; +/** Number of connected BNs for every column in BG1 rate = 8/9, e.g. in first column all BNs are connected to 5 CNs */ +static const uint8_t lut_numEdgesPerBn_BG1_R89[NR_LDPC_START_COL_PARITY_BG1] = {5, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2}; + +/** Number of BNs of CN group for BG2. + E.g. 3 means that there is a CN group where every CN is connected to 3 BNs */ +static const uint8_t lut_numBnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {3, 4, 5, 6, 8, 10}; +/** Number of rows/CNs in every CN group for rate = 1/5 BG2, e.g. 6 rows of CNs connected to 3 BNs */ +static const uint8_t lut_numCnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {6, 20, 9, 3, 2, 2}; +/** Number of rows/CNs in every CN group for rate = 1/3 BG2, e.g. 8 rows of CNs connected to 4 BNs */ +static const uint8_t lut_numCnInCnGroups_BG2_R13[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 8, 7, 3, 2, 2}; +/** Number of rows/CNs in every CN group for rate = 2/3 BG2, e.g. 1 row of CNs connected to 4 BNs */ +static const uint8_t lut_numCnInCnGroups_BG2_R23[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 1, 0, 2, 2, 2}; + +/** Number of connected BNs for every column in BG2 rate = 1/5, e.g. in first column all BNs are connected to 22 CNs */ +static const uint8_t lut_numEdgesPerBn_BG2_R15[NR_LDPC_START_COL_PARITY_BG2] = {22, 23, 10, 5, 5, 14, 7, 13, 6, 8, 9, 16, 9, 12}; +/** Number of connected BNs for every column in BG2 rate = 1/3, e.g. in first column all BNs are connected to 14 CNs */ +static const uint8_t lut_numEdgesPerBn_BG2_R13[NR_LDPC_START_COL_PARITY_BG2] = {14, 16, 2, 4, 4, 6, 6, 8, 6, 6, 6, 13, 5, 7}; +/** Number of connected BNs for every column in BG2 rate = 2/3, e.g. in first column all BNs are connected to 6 CNs */ +static const uint8_t lut_numEdgesPerBn_BG2_R23[NR_LDPC_START_COL_PARITY_BG2] = { 6, 5, 2, 3, 3, 4, 3, 4, 3, 4, 3, 5, 2, 2}; + +// Number of groups for bit node processing +/** Number of connected CNs for every column/BN in BG1 for rate = 1/3, Worst case is BG1 with up to 30 CNs connected to one BN + E.g. 42 parity BNs connected to single CN */ + // BG1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +static const uint8_t lut_numBnInBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {42, 0, 0, 1, 1, 2, 4, 3, 1, 4, 3, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}; +/** Number of connected CNs for every column/BN in BG1 for rate = 2/3 */ +static const uint8_t lut_numBnInBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 9, 1, 5, 3, 7, 8, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/** Number of connected CNs for every column/BN in BG1 for rate = 8/9 */ +static const uint8_t lut_numBnInBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 1, 3,21, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +/** Number of connected CNs for every column/BN in BG2 for rate = 1/5, Worst case is BG1 with up to 30 CNs connected to one BN + E.g. 38 parity BNs connected to single CN */ + // BG2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +static const uint8_t lut_numBnInBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {38, 0, 0, 0, 2, 1, 1, 1, 2, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0}; +/** Number of connected CNs for every column/BN in BG2 for rate = 1/3 */ +static const uint8_t lut_numBnInBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {18, 1, 0, 2, 1, 5, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/** Number of connected CNs for every column/BN in BG2 for rate = 2/3 */ +static const uint8_t lut_numBnInBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 3, 3, 5, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +// Start addresses for the bnProcBuf for each BN group +// BG1 +/** Start address for every BN group within the BN processing buffer for BG1 rate = 1/3 */ +static const uint32_t lut_startAddrBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 17664, 19584, 24192, 34944, 44160, 47616, 62976, 75648, 94080, 99072, 109824}; +/** Start address for every BN group within the BN processing buffer for BG1 rate = 2/3 */ +static const uint32_t lut_startAddrBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 4224, 9984, 14592, 28032, 46464, 50688}; +/** Start address for every BN group within the BN processing buffer for BG1 rate = 8/9 */ +static const uint32_t lut_startAddrBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 2688, 26880, 28416}; + +/** Start address for every BN group within the LLR processing buffer for BG1 rate = 1/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 16512, 16896, 17664, 19200, 20352, 20736, 22272, 23424, 24960, 25344, 25728}; +/** Start address for every BN group within the LLR processing buffer for BG1 rate = 2/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 3840, 5760, 6912, 9600, 12672, 13056}; +/** Start address for every BN group within the LLR processing buffer for BG1 rate = 8/9 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 1536, 9600, 9984}; + +// BG2 +/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/5 */ +static const uint32_t lut_startAddrBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 18432, 20736, 23424, 26496, 33408, 37248, 41856, 46848, 52224, 58368, 66816}; +/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/3 */ +static const uint32_t lut_startAddrBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7680, 10752, 12672, 24192, 26880, 29952, 34944, 40320}; +/** Start address for every BN group within the BN processing buffer for BG2 rate = 2/3 */ +static const uint32_t lut_startAddrBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 3456, 9216, 13824, 17664}; + +/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/5 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 15360, 15744, 16128, 16512, 17280, 17664, 18048, 18432, 18816, 19200, 19584}; +/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7296, 8064, 8448, 10368, 10752, 11136, 11520, 11904}; +/** Start address for every BN group within the LLR processing buffer for BG2 rate = 2/3 */ +static const uint16_t lut_startAddrBnGroupsLlr_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 2304, 4224, 5376, 6144}; + +/** Vector of 32 '1' in int8 for application with AVX2 */ +static const int8_t ones256_epi8[32] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +/** Vector of 32 '0' in int8 for application with AVX2 */ +static const int8_t zeros256_epi8[32] __attribute__ ((aligned(32))) = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +/** Vector of 32 '127' in int8 for application with AVX2 */ +static const int8_t maxLLR256_epi8[32] __attribute__ ((aligned(32))) = {127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127}; + +#endif diff --git a/openair1/PHY/CODING/nrLDPC_defs.h b/openair1/PHY/CODING/nrLDPC_defs.h new file mode 100644 index 0000000000..b96067f4b6 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_defs.h @@ -0,0 +1,59 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ +//============================================================================================================================ +// encoder interface +#ifndef __NRLDPC_DEFS__H__ +#define __NRLDPC_DEFS__H__ +#include "openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" +/** + \brief LDPC encoder + \param 1 input + \param 2 channel_input + \param 3 int Zc + \param 4 int Kb + \param 5 short block_length + \param 6 short BG + \param 7 int n_segment + \param 8 unsigned int macro_num + \param 9-12 time_stats_t *tinput,*tprep, *tparity,*toutput +*/ +typedef struct { + int n_segments; // optim8seg + unsigned int macro_num; // optim8segmulti + unsigned char gen_code; //orig + time_stats_t *tinput; + time_stats_t *tprep; + time_stats_t *tparity; + time_stats_t *toutput; +}encoder_implemparams_t; +#define INIT0_LDPCIMPLEMPARAMS {0,0,0,NULL,NULL,NULL,NULL} +typedef int(*nrLDPC_encoderfunc_t)(unsigned char **,unsigned char **,int,int,short, short, encoder_implemparams_t*); +//============================================================================================================================ +// decoder interface +/** + \brief LDPC decoder API type definition + \param p_decParams LDPC decoder parameters + \param p_llr Input LLRs + \param p_llrOut Output vector + \param p_profiler LDPC profiler statistics +*/ +typedef int32_t(*nrLDPC_decoderfunc_t)(t_nrLDPC_dec_params* , int8_t*, int8_t* , t_nrLDPC_procBuf* , t_nrLDPC_time_stats* ); +#endif \ No newline at end of file diff --git a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encode_parity_check.c b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encode_parity_check.c new file mode 100644 index 0000000000..738fd49b7d --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encode_parity_check.c @@ -0,0 +1,201 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file ldpc_encode_parity_check.c + * \brief Parity check function used by ldpc encoders + * \author Florian Kaltenberger, Raymond Knopp, Kien le Trung (Eurecom) + * \email openair_tech@eurecom.fr + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#include +#include +#include +#include +#include +#include "assertions.h" +#include "common/utils/LOG/log.h" + + +//#define DEBUG_LDPC + +#include "ldpc384_byte.c" +#include "ldpc352_byte.c" +#include "ldpc320_byte.c" +#include "ldpc288_byte.c" +#include "ldpc256_byte.c" +#include "ldpc240_byte.c" +#include "ldpc224_byte.c" +#include "ldpc208_byte.c" +#include "ldpc192_byte.c" +#include "ldpc176_byte.c" +#include "ldpc_BG2_Zc384_byte.c" +#include "ldpc_BG2_Zc352_byte.c" +#include "ldpc_BG2_Zc320_byte.c" +#include "ldpc_BG2_Zc288_byte.c" +#include "ldpc_BG2_Zc256_byte.c" +#include "ldpc_BG2_Zc240_byte.c" +#include "ldpc_BG2_Zc224_byte.c" +#include "ldpc_BG2_Zc208_byte.c" +#include "ldpc_BG2_Zc192_byte.c" +#include "ldpc_BG2_Zc176_byte.c" +#include "ldpc_BG2_Zc160_byte.c" +#include "ldpc_BG2_Zc144_byte.c" +#include "ldpc_BG2_Zc128_byte.c" +#include "ldpc_BG2_Zc120_byte.c" +#include "ldpc_BG2_Zc112_byte.c" +#include "ldpc_BG2_Zc104_byte.c" +#include "ldpc_BG2_Zc96_byte.c" +#include "ldpc_BG2_Zc88_byte.c" +#include "ldpc_BG2_Zc80_byte.c" +#include "ldpc_BG2_Zc72_byte.c" + + + +static inline void encode_parity_check_part_optim(uint8_t *c,uint8_t *d, short BG,short Zc,short Kb) +{ + + if (BG==1) + { + switch (Zc) + { + case 2: break; + case 3: break; + case 4: break; + case 5: break; + case 6: break; + case 7: break; + case 8: break; + case 9: break; + case 10: break; + case 11: break; + case 12: break; + case 13: break; + case 14: break; + case 15: break; + case 16: break; + case 18: break; + case 20: break; + case 22: break; + case 24: break; + case 26: break; + case 28: break; + case 30: break; + case 32: break; + case 36: break; + case 40: break; + case 44: break; + case 48: break; + case 52: break; + case 56: break; + case 60: break; + case 64: break; + case 72: break; + case 80: break; + case 88: break; + case 96: break; + case 104: break; + case 112: break; + case 120: break; + case 128: break; + case 144: break; + case 160: break; + case 176: ldpc176_byte(c,d); break; + case 192: ldpc192_byte(c,d); break; + case 208: ldpc208_byte(c,d); break; + case 224: ldpc224_byte(c,d); break; + case 240: ldpc240_byte(c,d); break; + case 256: ldpc256_byte(c,d); break; + case 288: ldpc288_byte(c,d); break; + case 320: ldpc320_byte(c,d); break; + case 352: ldpc352_byte(c,d); break; + case 384: ldpc384_byte(c,d); break; + default: AssertFatal(0,"BG %d Zc %d is not supported yet\n",BG,Zc); break; + } + } + else if (BG==2) { + switch (Zc) + { + case 2: break; + case 3: break; + case 4: break; + case 5: break; + case 6: break; + case 7: break; + case 8: break; + case 9: break; + case 10: break; + case 11: break; + case 12: break; + case 13: break; + case 14: break; + case 15: break; + case 16: break; + case 18: break; + case 20: break; + case 22: break; + case 24: break; + case 26: break; + case 28: break; + case 30: break; + case 32: break; + case 36: break; + case 40: break; + case 44: break; + case 48: break; + case 52: break; + case 56: break; + case 60: break; + case 64: break; + case 72: ldpc_BG2_Zc72_byte(c,d); break; + case 80: ldpc_BG2_Zc80_byte(c,d); break; + case 88: ldpc_BG2_Zc88_byte(c,d); break; + case 96: ldpc_BG2_Zc96_byte(c,d); break; + case 104: ldpc_BG2_Zc104_byte(c,d); break; + case 112: ldpc_BG2_Zc112_byte(c,d); break; + case 120: ldpc_BG2_Zc120_byte(c,d); break; + case 128: ldpc_BG2_Zc128_byte(c,d); break; + case 144: ldpc_BG2_Zc144_byte(c,d); break; + case 160: ldpc_BG2_Zc160_byte(c,d); break; + case 176: ldpc_BG2_Zc176_byte(c,d); break; + case 192: ldpc_BG2_Zc192_byte(c,d); break; + case 208: ldpc_BG2_Zc208_byte(c,d); break; + case 224: ldpc_BG2_Zc224_byte(c,d); break; + case 240: ldpc_BG2_Zc240_byte(c,d); break; + case 256: ldpc_BG2_Zc256_byte(c,d); break; + case 288: ldpc_BG2_Zc288_byte(c,d); break; + case 320: ldpc_BG2_Zc320_byte(c,d); break; + case 352: ldpc_BG2_Zc352_byte(c,d); break; + case 384: ldpc_BG2_Zc384_byte(c,d); break; + default: AssertFatal(0,"BG %d Zc %d is not supported yet\n",BG,Zc); break; + } + } + else { + AssertFatal(0,"BG %d is not supported yet\n",BG); + } + +} + + + diff --git a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim.c b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim.c new file mode 100644 index 0000000000..7da265494a --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim.c @@ -0,0 +1,146 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file ldpc_encoder2.c + * \brief Defines the optimized LDPC encoder + * \author Florian Kaltenberger, Raymond Knopp, Kien le Trung (Eurecom) + * \email openair_tech@eurecom.fr + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#include +#include +#include +#include +#include +#include "assertions.h" +#include "common/utils/LOG/log.h" +#include "PHY/TOOLS/time_meas.h" +#include "openair1/PHY/CODING/nrLDPC_defs.h" +#include "ldpc_encode_parity_check.c" +#include "ldpc_generate_coefficient.c" +//#define DEBUG_LDPC + + + + + +int nrLDPC_encod(unsigned char **test_input,unsigned char **channel_input,int Zc,int Kb,short block_length, short BG, encoder_implemparams_t *impp) +{ + + short nrows=0,ncols=0; + int i,i1,rate=3; + int no_punctured_columns,removed_bit; + + int simd_size; + + //determine number of bits in codeword + //if (block_length>3840) + if (BG==1) + { + //BG=1; + nrows=46; //parity check bits + ncols=22; //info bits + rate=3; + } + //else if (block_length<=3840) + else if (BG==2) + { + //BG=2; + nrows=42; //parity check bits + ncols=10; // info bits + rate=5; + + } + + +#ifdef DEBUG_LDPC + LOG_D(PHY,"ldpc_encoder_optim_8seg: BG %d, Zc %d, Kb %d, block_length %d\n",BG,Zc,Kb,block_length); + LOG_D(PHY,"ldpc_encoder_optim_8seg: PDU %x %x %x %x\n",test_input[0][0],test_input[0][1],test_input[0][2],test_input[0][3]); +#endif + + if ((Zc&31) > 0) simd_size = 16; + else simd_size = 32; + + unsigned char c[22*Zc] __attribute__((aligned(32))); //padded input, unpacked, max size + unsigned char d[46*Zc] __attribute__((aligned(32))); //coded parity part output, unpacked, max size + + unsigned char c_extension[2*22*Zc*simd_size] __attribute__((aligned(32))); //double size matrix of c + + // calculate number of punctured bits + no_punctured_columns=(int)((nrows-2)*Zc+block_length-block_length*rate)/Zc; + removed_bit=(nrows-no_punctured_columns-2) * Zc+block_length-(int)(block_length*rate); + // printf("%d\n",no_punctured_columns); + // printf("%d\n",removed_bit); + // unpack input + memset(c,0,sizeof(unsigned char) * ncols * Zc); + memset(d,0,sizeof(unsigned char) * nrows * Zc); + + if(impp->tinput != NULL) start_meas(impp->tinput); + for (i=0; i>(i&7)))>>(7-(i&7)); + //printf("c(%d,%d)=%d\n",j,i,temp); + } + + if(impp->tinput != NULL) stop_meas(impp->tinput); + + if ((BG==1 && Zc>176) || (BG==2 && Zc>64)) { + // extend matrix + if(impp->tprep != NULL) start_meas(impp->tprep); + for (i1=0; i1 < ncols; i1++) + { + memcpy(&c_extension[2*i1*Zc], &c[i1*Zc], Zc*sizeof(unsigned char)); + memcpy(&c_extension[(2*i1+1)*Zc], &c[i1*Zc], Zc*sizeof(unsigned char)); + } + for (i1=1;i1tprep != NULL) stop_meas(impp->tprep); + //parity check part + if(impp->tparity != NULL) start_meas(impp->tparity); + encode_parity_check_part_optim(c_extension, d, BG, Zc, Kb); + if(impp->tparity != NULL) stop_meas(impp->tparity); + } + else { + if (encode_parity_check_part_orig(c, d, BG, Zc, Kb, block_length)!=0) { + printf("Problem with encoder\n"); + return(-1); + } + } + if(impp->toutput != NULL) start_meas(impp->toutput); + // information part and puncture columns + memcpy(&channel_input[0][0], &c[2*Zc], (block_length-2*Zc)*sizeof(unsigned char)); + memcpy(&channel_input[0][block_length-2*Zc], &d[0], ((nrows-no_punctured_columns) * Zc-removed_bit)*sizeof(unsigned char)); + + if(impp->toutput != NULL) stop_meas(impp->toutput); + return 0; +} + + diff --git a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8seg.c b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8seg.c new file mode 100644 index 0000000000..a974e86e27 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8seg.c @@ -0,0 +1,225 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file ldpc_encoder2.c + * \brief Defines the optimized LDPC encoder + * \author Florian Kaltenberger, Raymond Knopp, Kien le Trung (Eurecom) + * \email openair_tech@eurecom.fr + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#include +#include +#include +#include +#include +#include "assertions.h" +#include "common/utils/LOG/log.h" +#include "PHY/TOOLS/time_meas.h" +#include "openair1/PHY/CODING/nrLDPC_defs.h" +//#define DEBUG_LDPC +#include "ldpc_encode_parity_check.c" +#include "ldpc_generate_coefficient.c" + + + +int nrLDPC_encod(unsigned char **test_input,unsigned char **channel_input,int Zc,int Kb,short block_length, short BG, encoder_implemparams_t *impp) +{ + + short nrows=0,ncols=0; + int i,i1,j,rate=3; + int no_punctured_columns,removed_bit; + char temp; + int simd_size; + +#ifdef __AVX2__ + __m256i shufmask = _mm256_set_epi64x(0x0303030303030303, 0x0202020202020202,0x0101010101010101, 0x0000000000000000); + __m256i andmask = _mm256_set1_epi64x(0x0102040810204080); // every 8 bits -> 8 bytes, pattern repeats. + __m256i zero256 = _mm256_setzero_si256(); + __m256i masks[8]; + register __m256i c256; + masks[0] = _mm256_set1_epi8(0x1); + masks[1] = _mm256_set1_epi8(0x2); + masks[2] = _mm256_set1_epi8(0x4); + masks[3] = _mm256_set1_epi8(0x8); + masks[4] = _mm256_set1_epi8(0x10); + masks[5] = _mm256_set1_epi8(0x20); + masks[6] = _mm256_set1_epi8(0x40); + masks[7] = _mm256_set1_epi8(0x80); +#endif + + AssertFatal((impp->n_segments>0&&impp->n_segments<=8),"0 < n_segments %d <= 8\n",impp->n_segments); + + //determine number of bits in codeword + //if (block_length>3840) + if (BG==1) + { + nrows=46; //parity check bits + ncols=22; //info bits + rate=3; + } + //else if (block_length<=3840) + else if (BG==2) + { + //BG=2; + nrows=42; //parity check bits + ncols=10; // info bits + rate=5; + + } + +#ifdef DEBUG_LDPC + LOG_D(PHY,"ldpc_encoder_optim_8seg: BG %d, Zc %d, Kb %d, block_length %d, segments %d\n",BG,Zc,Kb,block_length,n_segments); + LOG_D(PHY,"ldpc_encoder_optim_8seg: PDU (seg 0) %x %x %x %x\n",test_input[0][0],test_input[0][1],test_input[0][2],test_input[0][3]); +#endif + + AssertFatal(Zc>0,"no valid Zc found for block length %d\n",block_length); + + if ((Zc&31) > 0) simd_size = 16; + else simd_size = 32; + + unsigned char c[22*Zc] __attribute__((aligned(32))); //padded input, unpacked, max size + unsigned char d[46*Zc] __attribute__((aligned(32))); //coded parity part output, unpacked, max size + + unsigned char c_extension[2*22*Zc*simd_size] __attribute__((aligned(32))); //double size matrix of c + + // calculate number of punctured bits + no_punctured_columns=(int)((nrows-2)*Zc+block_length-block_length*rate)/Zc; + removed_bit=(nrows-no_punctured_columns-2) * Zc+block_length-(int)(block_length*rate); + // printf("%d\n",no_punctured_columns); + // printf("%d\n",removed_bit); + // unpack input + memset(c,0,sizeof(unsigned char) * ncols * Zc); + memset(d,0,sizeof(unsigned char) * nrows * Zc); + + if(impp->tinput != NULL) start_meas(impp->tinput); +#if 0 + for (i=0; i>(i&7)))>>(7-(i&7)); + //printf("c(%d,%d)=%d\n",j,i,temp); + c[i] |= (temp << j); + } + } +#else +#ifdef __AVX2__ + for (i=0; i>5; i++) { + c256 = _mm256_and_si256(_mm256_cmpeq_epi8(_mm256_andnot_si256(_mm256_shuffle_epi8(_mm256_set1_epi32(((uint32_t*)test_input[0])[i]), shufmask),andmask),zero256),masks[0]); + for (j=1; jn_segments; j++) { + c256 = _mm256_or_si256(_mm256_and_si256(_mm256_cmpeq_epi8(_mm256_andnot_si256(_mm256_shuffle_epi8(_mm256_set1_epi32(((uint32_t*)test_input[j])[i]), shufmask),andmask),zero256),masks[j]),c256); + } + ((__m256i *)c)[i] = c256; + } + + for (i=(block_length>>5)<<5;in_segments; j++) { + + temp = (test_input[j][i/8]&(128>>(i&7)))>>(7-(i&7)); + //printf("c(%d,%d)=%d\n",j,i,temp); + c[i] |= (temp << j); + } + } +#else + AssertFatal(1==0,"Need AVX2 for this\n"); +#endif +#endif + + if(impp->tinput != NULL) stop_meas(impp->tinput); + + if ((BG==1 && Zc>176) || (BG==2 && Zc>64)) { + // extend matrix + if(impp->tprep != NULL) start_meas(impp->tprep); + for (i1=0; i1 < ncols; i1++) + { + memcpy(&c_extension[2*i1*Zc], &c[i1*Zc], Zc*sizeof(unsigned char)); + memcpy(&c_extension[(2*i1+1)*Zc], &c[i1*Zc], Zc*sizeof(unsigned char)); + } + for (i1=1;i1tprep != NULL) stop_meas(impp->tprep); + //parity check part + if(impp->tparity != NULL) start_meas(impp->tparity); + encode_parity_check_part_optim(c_extension, d, BG, Zc, Kb); + if(impp->tparity != NULL) stop_meas(impp->tparity); + } + else { + if (encode_parity_check_part_orig(c, d, BG, Zc, Kb, block_length)!=0) { + printf("Problem with encoder\n"); + return(-1); + } + } + if(impp->toutput != NULL) start_meas(impp->toutput); + // information part and puncture columns + /* + memcpy(&channel_input[0], &c[2*Zc], (block_length-2*Zc)*sizeof(unsigned char)); + memcpy(&channel_input[block_length-2*Zc], &d[0], ((nrows-no_punctured_columns) * Zc-removed_bit)*sizeof(unsigned char)); + */ +#ifdef __AVX2__ + if ((((2*Zc)&31) == 0) && (((block_length-(2*Zc))&31) == 0)) { + //AssertFatal(((2*Zc)&31) == 0,"2*Zc needs to be a multiple of 32 for now\n"); + //AssertFatal(((block_length-(2*Zc))&31) == 0,"block_length-(2*Zc) needs to be a multiple of 32 for now\n"); + uint32_t l1 = (block_length-(2*Zc))>>5; + uint32_t l2 = ((nrows-no_punctured_columns) * Zc-removed_bit)>>5; + __m256i *c256p = (__m256i *)&c[2*Zc]; + __m256i *d256p = (__m256i *)&d[0]; + // if (((block_length-(2*Zc))&31)>0) l1++; + + for (i=0;in_segments;j++) ((__m256i *)channel_input[j])[i] = _mm256_and_si256(_mm256_srai_epi16(c256p[i],j),masks[0]); + + // if ((((nrows-no_punctured_columns) * Zc-removed_bit)&31)>0) l2++; + + for (i1=0;i1n_segments;j++) ((__m256i *)channel_input[j])[i] = _mm256_and_si256(_mm256_srai_epi16(d256p[i1],j),masks[0]); + } + else { +#ifdef DEBUG_LDPC + LOG_W(PHY,"using non-optimized version\n"); +#endif + // do non-SIMD version + for (i=0;i<(block_length-2*Zc);i++) + for (j=0; jn_segments; j++) + channel_input[j][i] = (c[2*Zc+i]>>j)&1; + for (i=0;i<((nrows-no_punctured_columns) * Zc-removed_bit);i++) + for (j=0; jn_segments; j++) + channel_input[j][block_length-2*Zc+i] = (d[i]>>j)&1; + } + +#else + AssertFatal(1==0,"Need AVX2 for now\n"); +#endif + + if(impp->toutput != NULL) stop_meas(impp->toutput); + return 0; +} + + diff --git a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8segmulti.c b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8segmulti.c new file mode 100644 index 0000000000..b21f875b32 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8segmulti.c @@ -0,0 +1,237 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*!\file ldpc_encoder2.c + * \brief Defines the optimized LDPC encoder + * \author Florian Kaltenberger, Raymond Knopp, Kien le Trung (Eurecom) + * \email openair_tech@eurecom.fr + * \date 27-03-2018 + * \version 1.0 + * \note + * \warning + */ + +#include +#include +#include +#include +#include +#include "assertions.h" +#include "common/utils/LOG/log.h" +#include "PHY/TOOLS/time_meas.h" +#include "openair1/PHY/CODING/nrLDPC_defs.h" + +//#define DEBUG_LDPC + +#include "ldpc_encode_parity_check.c" +#include "ldpc_generate_coefficient.c" + + +int nrLDPC_encod(unsigned char **test_input,unsigned char **channel_input,int Zc,int Kb,short block_length, short BG, encoder_implemparams_t *impp) +{ + + short nrows=0,ncols=0; + int i,i1,j,rate=3; + int no_punctured_columns,removed_bit; + //Table of possible lifting sizes + char temp; + int simd_size; + unsigned int macro_segment, macro_segment_end; + + + macro_segment = 8*impp->macro_num; + macro_segment_end = (impp->n_segments > 8*(impp->macro_num+1)) ? 8*(impp->macro_num+1) : impp->n_segments; + ///printf("macro_segment: %d\n", macro_segment); + ///printf("macro_segment_end: %d\n", macro_segment_end ); + +#ifdef __AVX2__ + __m256i shufmask = _mm256_set_epi64x(0x0303030303030303, 0x0202020202020202,0x0101010101010101, 0x0000000000000000); + __m256i andmask = _mm256_set1_epi64x(0x0102040810204080); // every 8 bits -> 8 bytes, pattern repeats. + __m256i zero256 = _mm256_setzero_si256(); + __m256i masks[8]; + register __m256i c256; + masks[0] = _mm256_set1_epi8(0x1); + masks[1] = _mm256_set1_epi8(0x2); + masks[2] = _mm256_set1_epi8(0x4); + masks[3] = _mm256_set1_epi8(0x8); + masks[4] = _mm256_set1_epi8(0x10); + masks[5] = _mm256_set1_epi8(0x20); + masks[6] = _mm256_set1_epi8(0x40); + masks[7] = _mm256_set1_epi8(0x80); +#endif + + + + //determine number of bits in codeword + if (BG==1) + { + nrows=46; //parity check bits + ncols=22; //info bits + rate=3; + } + else if (BG==2) + { + nrows=42; //parity check bits + ncols=10; // info bits + rate=5; + } + +#ifdef DEBUG_LDPC + LOG_D(PHY,"ldpc_encoder_optim_8seg: BG %d, Zc %d, Kb %d, block_length %d, segments %d\n",BG,Zc,Kb,block_length,n_segments); + LOG_D(PHY,"ldpc_encoder_optim_8seg: PDU (seg 0) %x %x %x %x\n",test_input[0][0],test_input[0][1],test_input[0][2],test_input[0][3]); +#endif + + AssertFatal(Zc>0,"no valid Zc found for block length %d\n",block_length); + + if ((Zc&31) > 0) simd_size = 16; + else simd_size = 32; + + unsigned char c[22*Zc] __attribute__((aligned(32))); //padded input, unpacked, max size + unsigned char d[46*Zc] __attribute__((aligned(32))); //coded parity part output, unpacked, max size + + unsigned char c_extension[2*22*Zc*simd_size] __attribute__((aligned(32))); //double size matrix of c + + // calculate number of punctured bits + no_punctured_columns=(int)((nrows-2)*Zc+block_length-block_length*rate)/Zc; + removed_bit=(nrows-no_punctured_columns-2) * Zc+block_length-(int)(block_length*rate); + //printf("%d\n",no_punctured_columns); + //printf("%d\n",removed_bit); + // unpack input + memset(c,0,sizeof(unsigned char) * ncols * Zc); + memset(d,0,sizeof(unsigned char) * nrows * Zc); + + if(impp->tinput != NULL) start_meas(impp->tinput); +#if 0 + for (i=0; i>(i&7); + //printf("c(%d,%d)=%d\n",j,i,temp); + c[i] |= (temp << (j-macro_segment)); + } + } +#else +#ifdef __AVX2__ + for (i=0; i>5; i++) { + c256 = _mm256_and_si256(_mm256_cmpeq_epi8(_mm256_andnot_si256(_mm256_shuffle_epi8(_mm256_set1_epi32(((uint32_t*)test_input[macro_segment])[i]), shufmask),andmask),zero256),masks[0]); + //for (j=1; j>5)<<5;i>(i&7)))>>(7-(i&7)); + //printf("c(%d,%d)=%d\n",j,i,temp); + c[i] |= (temp << (j-macro_segment)); + } + } +#else + AssertFatal(1==0,"Need AVX2 for this\n"); +#endif +#endif + + if(impp->tinput != NULL) stop_meas(impp->tinput); + + if ((BG==1 && Zc>176) || (BG==2 && Zc>64)) { + // extend matrix + if(impp->tprep != NULL) start_meas(impp->tprep); + for (i1=0; i1 < ncols; i1++) + { + memcpy(&c_extension[2*i1*Zc], &c[i1*Zc], Zc*sizeof(unsigned char)); + memcpy(&c_extension[(2*i1+1)*Zc], &c[i1*Zc], Zc*sizeof(unsigned char)); + } + for (i1=1;i1tprep != NULL) stop_meas(impp->tprep); + //parity check part + if(impp->tparity != NULL) start_meas(impp->tparity); + encode_parity_check_part_optim(c_extension, d, BG, Zc, Kb); + if(impp->tparity != NULL) stop_meas(impp->tparity); + } + else { + if (encode_parity_check_part_orig(c, d, BG, Zc, Kb, block_length)!=0) { + printf("Problem with encoder\n"); + return(-1); + } + } + if(impp->toutput != NULL) start_meas(impp->toutput); + // information part and puncture columns + /* + memcpy(&channel_input[0], &c[2*Zc], (block_length-2*Zc)*sizeof(unsigned char)); + memcpy(&channel_input[block_length-2*Zc], &d[0], ((nrows-no_punctured_columns) * Zc-removed_bit)*sizeof(unsigned char)); + */ +#ifdef __AVX2__ + if ((((2*Zc)&31) == 0) && (((block_length-(2*Zc))&31) == 0)) { + //AssertFatal(((2*Zc)&31) == 0,"2*Zc needs to be a multiple of 32 for now\n"); + //AssertFatal(((block_length-(2*Zc))&31) == 0,"block_length-(2*Zc) needs to be a multiple of 32 for now\n"); + uint32_t l1 = (block_length-(2*Zc))>>5; + uint32_t l2 = ((nrows-no_punctured_columns) * Zc-removed_bit)>>5; + __m256i *c256p = (__m256i *)&c[2*Zc]; + __m256i *d256p = (__m256i *)&d[0]; + // if (((block_length-(2*Zc))&31)>0) l1++; + + for (i=0;i0) l2++; + + for (i1=0;i1>(j-macro_segment))&1; + for (i=0;i<((nrows-no_punctured_columns) * Zc-removed_bit);i++) + //for (j=0; j>(j-macro_segment))&1; + } + +#else + AssertFatal(1==0,"Need AVX2 for now\n"); +#endif + + if(impp->toutput != NULL) stop_meas(impp->toutput); + return 0; +} + diff --git a/openair1/PHY/CODING/nrLDPC_extern.h b/openair1/PHY/CODING/nrLDPC_extern.h new file mode 100644 index 0000000000..c0bfa0fdd8 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_extern.h @@ -0,0 +1,35 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ +#include "openair1/PHY/CODING/nrLDPC_defs.h" + +#ifdef LDPC_LOADER +nrLDPC_decoderfunc_t nrLDPC_decoder; +nrLDPC_encoderfunc_t nrLDPC_encoder; +#else +/* functions to load the LDPC shared lib, implemented in openair1/PHY/CODING/nrLDPC_load.c */ +extern int load_nrLDPClib(void) ; +extern int load_nrLDPClib_ref(char *libversion, nrLDPC_encoderfunc_t * nrLDPC_encoder_ptr); // for ldpctest +/* ldpc coder/decoder functions, as loaded by load_nrLDPClib(). */ +extern nrLDPC_decoderfunc_t nrLDPC_decoder; +extern nrLDPC_encoderfunc_t nrLDPC_encoder; +// inline functions: +#include "openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h" +#endif \ No newline at end of file diff --git a/openair1/PHY/CODING/nrLDPC_load.c b/openair1/PHY/CODING/nrLDPC_load.c new file mode 100644 index 0000000000..a74bdf7bd1 --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_load.c @@ -0,0 +1,76 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file openair1/PHY/CODING/coding_nr_load.c + * \brief: load library implementing coding/decoding algorithms + * \author Francois TABURET + * \date 2020 + * \version 0.1 + * \company NOKIA BellLabs France + * \email: francois.taburet@nokia-bell-labs.com + * \note + * \warning + */ +#define _GNU_SOURCE +#include +#include +#include +#include "assertions.h" +#include "common/utils/LOG/log.h" +#define LDPC_LOADER +#include "PHY/CODING/nrLDPC_extern.h" +#include "common/config/config_userapi.h" +#include "common/utils/load_module_shlib.h" + + +/* function description array, to be used when loading the encoding/decoding shared lib */ +static loader_shlibfunc_t shlib_fdesc[2]; + +char *arg[64]={"ldpctest","-O","cmdlineonly::dbgl0"}; + +int load_nrLDPClib(void) { + char *ptr = (char*)config_get_if(); + if ( ptr==NULL ) {// phy simulators, config module possibly not loaded + load_configmodule(3,(char **)arg,CONFIG_ENABLECMDLINEONLY) ; + logInit(); + } + shlib_fdesc[0].fname = "nrLDPC_decod"; + shlib_fdesc[1].fname = "nrLDPC_encod"; + int ret=load_module_shlib("ldpc",shlib_fdesc,sizeof(shlib_fdesc)/sizeof(loader_shlibfunc_t),NULL); + AssertFatal( (ret >= 0),"Error loading ldpc decoder"); + nrLDPC_decoder = (nrLDPC_decoderfunc_t)shlib_fdesc[0].fptr; + nrLDPC_encoder = (nrLDPC_encoderfunc_t)shlib_fdesc[1].fptr; +return 0; +} + +int load_nrLDPClib_ref(char *libversion, nrLDPC_encoderfunc_t * nrLDPC_encoder_ptr) { + loader_shlibfunc_t shlib_encoder_fdesc; + + shlib_encoder_fdesc.fname = "nrLDPC_encod"; + char libpath[64]; + sprintf(libpath,"ldpc%s",libversion); + int ret=load_module_shlib(libpath,&shlib_encoder_fdesc,1,NULL); + AssertFatal( (ret >= 0),"Error loading ldpc encoder %s\n",libpath); + *nrLDPC_encoder_ptr = (nrLDPC_encoderfunc_t)shlib_encoder_fdesc.fptr; +return 0; +} + + diff --git a/openair1/PHY/NR_REFSIG/ptrs_nr.c b/openair1/PHY/NR_REFSIG/ptrs_nr.c new file mode 100644 index 0000000000..12f76b950f --- /dev/null +++ b/openair1/PHY/NR_REFSIG/ptrs_nr.c @@ -0,0 +1,423 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/********************************************************************** +* +* FILENAME : ptrs_nr.c +* +* MODULE : phase tracking reference signals +* +* DESCRIPTION : resource element mapping of ptrs sequences +* 3GPP TS 38.211 and 3GPP TS 38.214 +* +************************************************************************/ + +#include +#include +#include "dmrs_nr.h" +#include "PHY/NR_REFSIG/ptrs_nr.h" + +/***********************************************************************/ + + + //#define max(a,b) (((a) > (b)) ? (a) : (b)) + +// TS 38.211 Table 6.4.1.2.2.1-1: The parameter kRE_ref. +// The first 4 colomns are DM-RS Configuration type 1 and the last 4 colomns are DM-RS Configuration type 2. + +int16_t table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref [6][8] = { +{ 0, 2, 6, 8, 0, 1, 6, 7}, +{ 2, 4, 8, 10, 1, 6, 7, 0}, +{ 1, 3, 7, 9, 2, 3, 8, 9}, +{ 3, 5, 9, 11, 3, 8, 9, 2}, +{-1, -1, -1, -1, 4, 5, 10, 11}, +{-1, -1, -1, -1, 5, 10, 11, 4}, +}; + + +/******************************************************************* +* +* NAME : get_kRE_ref +* +* PARAMETERS : dmrs_antenna_port DMRS antenna port +* pusch_dmrs_type PUSCH DMRS type +* resourceElementOffset the parameter resourceElementOffset +* +* RETURN : the parameter k_RE_ref +* +* DESCRIPTION : 3GPP TS 38.211 Table 6.4.1.2.2.1-1 +* +*********************************************************************/ + +int16_t get_kRE_ref(uint8_t dmrs_antenna_port, uint8_t pusch_dmrs_type, uint8_t resourceElementOffset) { + + uint8_t colomn; + int16_t k_RE_ref; + + colomn = resourceElementOffset; + + if (pusch_dmrs_type == 2) + colomn += 4; + + k_RE_ref = table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref[dmrs_antenna_port][colomn]; + + AssertFatal(k_RE_ref>=0,"invalid k_RE_ref < 0. Check PTRS Configuration\n"); + + return k_RE_ref; +} + + +/******************************************************************* +* +* NAME : get_K_ptrs +* +* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration +* N_RB number of RBs scheduled for PUSCH +* +* RETURN : the parameter K_ptrs +* +* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-2 +* +*********************************************************************/ + +uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){ + + uint16_t nrb0, nrb1; + + nrb0 = ptrs_UplinkConfig->frequencyDensity.n_rb0; + nrb1 = ptrs_UplinkConfig->frequencyDensity.n_rb1; + + if (nrb0 == 0 || nrb0 == 0) + return 2; + + if (N_RB < nrb0){ + LOG_I(PHY,"PUSH PT-RS is not present.\n"); + return 0; + } + else if (N_RB >= nrb0 && N_RB < nrb1) + return 2; + else + return 4; +} + +/******************************************************************* +* +* NAME : set_ptrs_symb_idx +* +* PARAMETERS : ptrs_symbols PTRS OFDM symbol indicies bit mask +* duration_in_symbols number of scheduled PUSCH ofdm symbols +* start_symbol first ofdm symbol of PUSCH within slot +* L_ptrs the parameter L_ptrs +* ofdm_symbol_size FFT size +* +* RETURN : sets the bit map of PTRS ofdm symbol indicies +* +* DESCRIPTION : 3GPP TS 38.211 6.4.1.2.2.1 +* +*********************************************************************/ + +void set_ptrs_symb_idx(uint16_t *ptrs_symbols, + uint8_t duration_in_symbols, + uint8_t start_symbol, + uint8_t dmrs_type, + uint8_t L_ptrs, + uint8_t pusch_maxLength, + uint16_t ofdm_symbol_size) { + + uint8_t i, last_symbol, is_dmrs_symbol1, is_dmrs_symbol2; + int16_t l_ref; + + *ptrs_symbols = 0; + i = 0; + is_dmrs_symbol1 = 0; + is_dmrs_symbol2 = 0; + l_ref = start_symbol; + last_symbol = start_symbol + duration_in_symbols - 1; + + while ( (l_ref + i*L_ptrs) <= last_symbol) { + + is_dmrs_symbol1 = is_dmrs_symbol(max((l_ref + (i-1)*L_ptrs + 1), l_ref), + 0, + 0, + 0, + 0, + 0, + duration_in_symbols, + dmrs_type, + ofdm_symbol_size); + + is_dmrs_symbol2 = is_dmrs_symbol(l_ref + i*L_ptrs, + 0, + 0, + 0, + 0, + 0, + duration_in_symbols, + dmrs_type, + ofdm_symbol_size); + + if ( is_dmrs_symbol1 + is_dmrs_symbol2 > 0 ) { + + if (pusch_maxLength == 2) + l_ref = l_ref + i*L_ptrs + 1; + else + l_ref = l_ref + i*L_ptrs; + + i = 1; + + continue; + + } + + *ptrs_symbols = *ptrs_symbols | (1<<(l_ref + i*L_ptrs)); + i++; + } +} + +/******************************************************************* +* +* NAME : get_L_ptrs +* +* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration +* I_mcs MCS index used for PUSCH +* +* RETURN : the parameter L_ptrs +* +* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-1 +* +*********************************************************************/ + +uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs) { + + uint8_t mcs1, mcs2, mcs3; + + mcs1 = ptrs_UplinkConfig->timeDensity.ptrs_mcs1; + mcs2 = ptrs_UplinkConfig->timeDensity.ptrs_mcs2; + mcs3 = ptrs_UplinkConfig->timeDensity.ptrs_mcs3; + + if (mcs1 == 0 || mcs2 == 0 || mcs3 == 0) + return 1; + + if (I_mcs < mcs1){ + LOG_I(PHY,"PUSH PT-RS is not present.\n"); + return 0; + } + else if (I_mcs >= mcs1 && I_mcs < mcs2) + return 4; + else if (I_mcs >= mcs2 && I_mcs < mcs3) + return 2; + else + return 1; +} + +/******************************************************************* +* +* NAME : is_ptrs_subcarrier +* +* PARAMETERS : k subcarrier index +* K_ptrs the parameter K_ptrs +* n_rnti UE CRNTI +* N_RB number of RBs scheduled for PUSCH +* k_RE_ref the parameter k_RE_ref +* start_sc first subcarrier index +* ofdm_symbol_size FFT size +* +* RETURN : 1 if subcarrier k is PTRS, or 0 otherwise +* +* DESCRIPTION : 3GPP TS 38.211 6.4.1.2 Phase-tracking reference signal for PUSCH +* +*********************************************************************/ + +uint8_t is_ptrs_subcarrier(uint16_t k, uint8_t K_ptrs, uint16_t n_rnti, uint16_t N_RB, int16_t k_RE_ref, uint16_t start_sc, uint16_t ofdm_symbol_size) { + + uint16_t k_RB_ref, i, sc; + + i = 0; + sc = 0; + k_RB_ref = 0; + + if (N_RB % K_ptrs == 0) + k_RB_ref = n_rnti % K_ptrs; + else + k_RB_ref = n_rnti % (N_RB % K_ptrs); + + while (k > sc){ + + sc = (start_sc + k_RE_ref + (i*K_ptrs + k_RB_ref)*NR_NB_SC_PER_RB)%ofdm_symbol_size; + i++; + + } + + if (k == sc) + return 1; + else + return 0; + +} + +/******************************************************************* +* +* NAME : is_ptrs_symbol +* +* PARAMETERS : l ofdm symbol index within slot +* k subcarrier index +* n_rnti UE CRNTI +* N_RB number of RBs scheduled for PUSCH +* duration_in_symbols number of scheduled PUSCH ofdm symbols +* dmrs_antenna_port DMRS antenna port +* K_ptrs the parameter K_ptrs +* ptrs_symbols bit mask of ptrs +* start_sc first subcarrier index +* ofdm_symbol_size FFT size +* pusch_dmrs_type PUSCH DMRS type (1 or 2) +* ptrs_UplinkConfig PTRS uplink configuration +* +* RETURN : 0 if symbol(k,l) is data, or 1 if symbol(k,l) is ptrs +* +* DESCRIPTION : 3GPP TS 38.211 6.4.1.2 Phase-tracking reference signal for PUSCH +* +*********************************************************************/ + +uint8_t is_ptrs_symbol(uint8_t l, + uint16_t k, + uint16_t n_rnti, + uint16_t N_RB, + uint8_t duration_in_symbols, + uint8_t dmrs_antenna_port, + uint8_t K_ptrs, + uint16_t ptrs_symbols, + uint16_t start_sc, + uint16_t ofdm_symbol_size, + pusch_dmrs_type_t pusch_dmrs_type, + uint8_t resourceElementOffset) { + + uint8_t is_ptrs_freq, is_ptrs_time; + int16_t k_RE_ref; + + is_ptrs_freq = 0; + is_ptrs_time = 0; + + k_RE_ref = get_kRE_ref(dmrs_antenna_port, pusch_dmrs_type, resourceElementOffset); + + is_ptrs_freq = is_ptrs_subcarrier(k, K_ptrs, n_rnti, N_RB, k_RE_ref, start_sc, ofdm_symbol_size); + + if (is_ptrs_freq == 0) + return 0; + + if (((ptrs_symbols>>l)&1) == 1) + is_ptrs_time = 1; + + if (is_ptrs_time && is_ptrs_freq) + return 1; + else + return 0; + +} + +/* +int main(int argc, char const *argv[]) +{ + + dmrs_UplinkConfig_t dmrs_Uplink_Config; + ptrs_UplinkConfig_t ptrs_Uplink_Config; + uint8_t resourceElementOffset; + uint8_t dmrs_antenna_port; + uint8_t L_ptrs, K_ptrs; + int16_t k_RE_ref; + uint16_t N_RB, ptrs_symbols, ofdm_symbol_size, k; + uint8_t duration_in_symbols, I_mcs; + uint8_t start_symbol, l; + uint8_t ptrs_symbol_flag; + uint16_t n_rnti; + + dmrs_Uplink_Config.pusch_dmrs_type = pusch_dmrs_type1; + dmrs_Uplink_Config.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos1; + dmrs_Uplink_Config.pusch_maxLength = pusch_len2; + + ptrs_Uplink_Config.timeDensity.ptrs_mcs1 = 0; // setting MCS values to 0 indicate abscence of time_density field in the configuration + ptrs_Uplink_Config.timeDensity.ptrs_mcs2 = 0; + ptrs_Uplink_Config.timeDensity.ptrs_mcs3 = 0; + ptrs_Uplink_Config.frequencyDensity.n_rb0 = 0; // setting N_RB values to 0 indicate abscence of frequency_density field in the configuration + ptrs_Uplink_Config.frequencyDensity.n_rb1 = 0; + ptrs_Uplink_Config.resourceElementOffset = 0; + + n_rnti = 0x1234; + resourceElementOffset = 0; + ptrs_symbols = 0; + dmrs_antenna_port = 0; + N_RB = 50; + duration_in_symbols = 14; + ofdm_symbol_size = 2048; + I_mcs = 9; + start_symbol = 0; + ptrs_symbol_flag = 0; + + k_RE_ref = get_kRE_ref(dmrs_antenna_port, dmrs_Uplink_Config.pusch_dmrs_type, resourceElementOffset); + + K_ptrs = get_K_ptrs(&ptrs_Uplink_Config, N_RB); + + L_ptrs = get_L_ptrs(&ptrs_Uplink_Config, I_mcs); + + set_ptrs_symb_idx(&ptrs_symbols, + &ptrs_Uplink_Config, + &dmrs_Uplink_Config, + 1, + duration_in_symbols, + start_symbol, + L_ptrs, + ofdm_symbol_size); + + printf("PTRS OFDM symbol indicies: "); + + for (l = start_symbol; l < start_symbol + duration_in_symbols; l++){ + + ptrs_symbol_flag = is_ptrs_symbol(l, + 0, + n_rnti, + N_RB, + duration_in_symbols, + dmrs_antenna_port, + K_ptrs, + ptrs_symbols, + dmrs_Uplink_Config.pusch_dmrs_type, + &ptrs_Uplink_Config); + + if (ptrs_symbol_flag == 1) + printf(" %d ", l); + + } + + printf("\n"); + + printf("PTRS subcarrier indicies: "); + + for (k = 0; k < N_RB*12; k++){ + + if (is_ptrs_subcarrier(k, K_ptrs, n_rnti, N_RB, k_RE_ref) == 1) + printf(" %d ", k); + + } + + printf("\n"); + + return 0; +} +*/ diff --git a/openair1/PHY/NR_REFSIG/ptrs_nr.h b/openair1/PHY/NR_REFSIG/ptrs_nr.h new file mode 100644 index 0000000000..291ff4a555 --- /dev/null +++ b/openair1/PHY/NR_REFSIG/ptrs_nr.h @@ -0,0 +1,81 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/********************************************************************** +* +* FILENAME : dmrs.h +* +* MODULE : demodulation reference signals +* +* DESCRIPTION : generation of dmrs sequences for NR 5G +* 3GPP TS 38.211 +* +************************************************************************/ + +#ifndef PTRS_NR_H +#define PTRS_NR_H + +#include "PHY/defs_nr_UE.h" + +/************** CODE GENERATION ***********************************/ + +/************** DEFINE ********************************************/ + + +/************* STRUCTURES *****************************************/ + + +/************** VARIABLES *****************************************/ + +/************** FUNCTION ******************************************/ + +int16_t get_kRE_ref(uint8_t dmrs_antenna_port, uint8_t pusch_dmrs_type, uint8_t resourceElementOffset); + +uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB); + +void set_ptrs_symb_idx(uint16_t *ptrs_symbols, + uint8_t duration_in_symbols, + uint8_t start_symbol, + uint8_t dmrs_type, + uint8_t L_ptrs, + uint8_t pusch_maxLength, + uint16_t ofdm_symbol_size); + +uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs); + +uint8_t is_ptrs_subcarrier(uint16_t k, uint8_t K_ptrs, uint16_t n_rnti, uint16_t N_RB, int16_t k_RE_ref, uint16_t start_sc, uint16_t ofdm_symbol_size); + +uint8_t is_ptrs_symbol(uint8_t l, + uint16_t k, + uint16_t n_rnti, + uint16_t N_RB, + uint8_t duration_in_symbols, + uint8_t dmrs_antenna_port, + uint8_t K_ptrs, + uint16_t ptrs_symbols, + uint16_t start_sc, + uint16_t ofdm_symbol_size, + pusch_dmrs_type_t pusch_dmrs_type, + uint8_t resourceElementOffset); + + + +#endif /* PTRS_NR_H */ diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools_common.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools_common.c new file mode 100644 index 0000000000..d26a52f157 --- /dev/null +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools_common.c @@ -0,0 +1,62 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/NR_TRANSPORT/nr_dci_tools_common.c + * \brief + * \author + * \date 2018 + * \version 0.1 + * \company Eurecom + * \email: + * \note + * \warning + */ + +#include "nr_dci.h" + +//#define DEBUG_FILL_DCI + +#include "nr_dlsch.h" + + +void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) { + + uint8_t count=0, start=0, start_set=0; + + uint64_t bitmap = (((uint64_t)FreqDomainResource[0])<<37)| + (((uint64_t)FreqDomainResource[1])<<29)| + (((uint64_t)FreqDomainResource[2])<<21)| + (((uint64_t)FreqDomainResource[3])<<13)| + (((uint64_t)FreqDomainResource[4])<<5)| + (((uint64_t)FreqDomainResource[5])>>3); + + for (int i=0; i<45; i++) + if ((bitmap>>(44-i))&1) { + count++; + if (!start_set) { + start = i; + start_set = 1; + } + } + *rb_offset = 6*start; + *n_rb = 6*count; +} + diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c new file mode 100644 index 0000000000..5710499e1a --- /dev/null +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -0,0 +1,650 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/NR_TRANSPORT/nr_prach.c + * \brief Top-level routines for generating and decoding the PRACH physical channel V15.4 2018-12 + * \author R. Knopp + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ + +#include "PHY/defs_gNB.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" + +extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; +extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; +extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13]; +extern uint16_t NCS_unrestricted_delta_f_RA_5[16]; +extern uint16_t NCS_restricted_TypeA_delta_f_RA_5[16]; +extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14]; +extern uint16_t NCS_unrestricted_delta_f_RA_15[16]; +extern uint16_t prach_root_sequence_map_0_3[838]; +extern uint16_t prach_root_sequence_map_abc[138]; +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; +extern uint16_t nr_du[838]; +extern int16_t nr_ru[2*839]; + +void rx_nr_prach_ru(RU_t *ru, + int frame, + int subframe) { + + AssertFatal(ru!=NULL,"ru is null\n"); + + int16_t **rxsigF=NULL; + NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms; + int16_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; + int16_t *prach[ru->nb_rx]; + uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); + + rxsigF = ru->prach_rxsigF; + + AssertFatal(ru->if_south == LOCAL_RF,"we shouldn't call this if if_south != LOCAL_RF\n"); + for (int aa=0; aanb_rx; aa++) + prach[aa] = (int16_t*)&ru->common.rxdata[aa][(subframe*fp->samples_per_subframe)-ru->N_TA_offset]; + + + + int mu = fp->numerology_index; + int Ncp; + int16_t *prach2; + + + switch (prach_fmt) { + case 0: + Ncp = 3168; + break; + + case 1: + Ncp = 21024; + break; + + case 2: + Ncp = 4688; + break; + + case 3: + Ncp = 3168; + break; + + case 0xa1: + Ncp = 288/(1<N_RB_UL, ru->nb_rx, Ncp); + } + AssertFatal(mu==1,"only 30 kHz SCS handled for now\n"); + + // Note: Assumes PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below + int kbar = 1; + int K = 24; + if (prach_fmt == 3) { + K=4; + kbar=10; + } + else if (prach_fmt > 3) { + // Note: Assumes that PRACH SCS is same as PUSCH SCS + K=1; + kbar=2; + } + int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; + int k = (12*n_ra_prb) - 6*fp->N_RB_UL; + + int N_ZC = (prach_fmt<4)?839:139; + + if (k<0) k+=(fp->ofdm_symbol_size); + + k*=K; + k+=kbar; + int reps=1; + int dftlen=0; + + for (int aa=0; aanb_rx; aa++) { + AssertFatal(prach[aa]!=NULL,"prach[%d] is null\n",aa); + + + // do DFT + if (fp->N_RB_UL <= 100) + AssertFatal(1==0,"N_RB_UL %d not support for NR PRACH yet\n",fp->N_RB_UL); + else if (fp->N_RB_UL < 137) { + if (fp->threequarter_fs==0) { + //40 MHz @ 61.44 Ms/s + //50 MHz @ 61.44 Ms/s + prach2 = prach[aa] + (Ncp<<2); + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + dft49152(prach2,rxsigF[aa],1); + if (prach_fmt == 1 || prach_fmt == 2) { + dft49152(prach2+98304,rxsigF[aa]+98304,1); + reps++; + } + if (prach_fmt == 2) { + dft49152(prach2+(98304*2),rxsigF[aa]+(98304*2),1); + dft49152(prach2+(98304*3),rxsigF[aa]+(98304*3),1); + reps+=2; + } + if (prach_fmt == 3) { + for (int i=0;i<4;i++) dft12288(prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); + reps=4; + } + if (prach_fmt >3) { + dft2048(prach2,rxsigF[aa],1); + if (prach_fmt != 0xc0) { + dft2048(prach2+4096,rxsigF[aa]+4096,1); + reps++; + } + } + if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + dft2048(prach2+4096*2,rxsigF[aa]+4096*2,1); + dft2048(prach2+4096*3,rxsigF[aa]+4096*3,1); + reps+=2; + } + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); + dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); + reps+=2; + } + if (prach_fmt == 0xc2) { + for (int i=6;i<11;i++) dft2048(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + reps+=6; + } + } else { + // 40 MHz @ 46.08 Ms/s + prach2 = prach[aa] + (3*Ncp); + AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dft36864(prach2,rxsigF[aa],1); + reps++; + } + if (prach_fmt == 1 || prach_fmt == 2) { + dft36864(prach2+73728,rxsigF[aa]+73728,1); + reps++; + } + if (prach_fmt == 2) { + dft36864(prach2+(98304*2),rxsigF[aa]+(98304*2),1); + dft36864(prach2+(98304*3),rxsigF[aa]+(98304*3),1); + reps+=2; + } + if (prach_fmt == 3) { + for (int i=0;i<4;i++) dft9216(prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); + reps=4; + } + if (prach_fmt >3) { + dft1536(prach2,rxsigF[aa],1); + if (prach_fmt != 0xc0) { + dft1536(prach2+3072,rxsigF[aa]+3072,1); + reps++; + } + } + if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); + dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); + reps+=2; + } + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); + dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); + reps+=2; + } + if (prach_fmt == 0xc2) { + for (int i=6;i<11;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + reps+=6; + } + } + } + else if (fp->N_RB_UL <= 273) { + if (fp->threequarter_fs==0) { + prach2 = prach[aa] + (Ncp<<3); + dftlen=98304; + //80,90,100 MHz @ 61.44 Ms/s + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + dft98304(prach2,rxsigF[aa],1); + if (prach_fmt == 1 || prach_fmt == 2) { + dft98304(prach2+196608,rxsigF[aa]+196608,1); + reps++; + } + if (prach_fmt == 1 || prach_fmt == 2) { + dft98304(prach2+196608,rxsigF[aa]+196608,1); + dft98304(prach2+(196608*2),rxsigF[aa]+(196608*2),1); + reps+=2; + } + if (prach_fmt == 3) { + dft24576(prach2+(2*49152),rxsigF[aa]+(2*49152),1); + reps=4; + dftlen=24576; + } + if (prach_fmt >3) { + dftlen=4096; + dft4096(prach2,rxsigF[aa],1); + if (prach_fmt != 0xc0) { + dft4096(prach2+8192,rxsigF[aa]+8192,1); + reps++; + } + } + if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + dft4096(prach2+8192*2,rxsigF[aa]+8192*2,1); + dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); + reps+=2; + } + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); + dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); + reps+=2; + } + if (prach_fmt == 0xc2) { + for (int i=6;i<11;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); + reps+=6; + } + } else { + AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n"); + prach2 = prach[aa] + (6*Ncp); + // 80 MHz @ 46.08 Ms/s + dftlen=73728; + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dft73728(prach2,rxsigF[aa],1); + reps++; + } + if (prach_fmt == 1 || prach_fmt == 2) { + dft73728(prach2+(2*73728),rxsigF[aa]+(2*73728),1); + reps++; + } + if (prach_fmt == 3) { + dft73728(prach2+(4*73728),rxsigF[aa]+(4*73728),1); + reps=4; + dftlen=18432; + } + + if (prach_fmt >3) { + dftlen=3072; + dft3072(prach2,rxsigF[aa],1); + if (prach_fmt != 0xc0) { + dft3072(prach2+6144,rxsigF[aa]+6144,1); + reps++; + } + } + if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + dft3072(prach2+6144*2,rxsigF[aa]+6144*2,1); + dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); + reps+=2; + } + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); + dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); + reps+=2; + } + if (prach_fmt == 0xc2) { + for (int i=6;i<11;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); + reps+=6; + } + } + } + + //Coherent combining of PRACH repetitions (assumes channel does not change, to be revisted for "long" PRACH) + int16_t rxsigF_tmp[N_ZC<<1]; + // if (k+N_ZC > dftlen) { // PRACH signal is split around DC + int16_t *rxsigF2=rxsigF[aa]; + int k2=k<<1; + + for (int j=0;jprach_vars.rxsigF; + + uint8_t preamble_index; + uint16_t NCS=99,NCS2; + uint16_t preamble_offset=0,preamble_offset_old; + int16_t preamble_shift=0; + uint32_t preamble_shift2; + uint16_t preamble_index0=0,n_shift_ra=0,n_shift_ra_bar; + uint16_t d_start=0; + uint16_t numshift=0; + uint16_t *prach_root_sequence_map; + uint8_t not_found; + uint16_t u; + int16_t *Xu=0; + uint16_t offset; + uint16_t first_nonzero_root_idx=0; + uint8_t new_dft=0; + uint8_t aa; + int32_t lev; + int16_t levdB; + int log2_ifft_size=10; + int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32))); + int32_t *prach_ifft=(int32_t*)NULL; + + nr_frequency_range_e freq_range; + + AssertFatal(gNB!=NULL,"Can only be called from gNB\n"); + fp = &gNB->frame_parms; + nb_rx = fp->nb_antennas_rx; + + frame_type = fp->frame_type; + freq_range = fp->freq_range; + rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; + prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; + Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; + restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; + + + uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,freq_range); + uint16_t N_ZC = (prach_fmt <4)?839:139; + + AssertFatal(gNB!=NULL,"gNB is null\n"); + + prach_ifft = gNB->prach_vars.prach_ifft; + prachF = gNB->prach_vars.prachF; + if (LOG_DEBUGFLAG(PRACH)){ + if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, prach_ConfigIndex %d , rootSequenceIndex %d\n", subframe,fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart,prach_ConfigIndex,rootSequenceIndex); + } + + + + + + + int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME + if (prach_fmt<3){ + if (restricted_set == 0) { + NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; + } else { + if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME + if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME + } + } + if (prach_fmt==3){ + if (restricted_set == 0) { + NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; + } else { + if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME + if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME + } + } + if (prach_fmt>3){ + NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; + } + + AssertFatal(NCS!=99,"NCS has not been set\n"); + + if (gNB) start_meas(&gNB->rx_prach); + + + prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; + + // PDP is oversampled, e.g. 1024 sample instead of 839 + // Adapt the NCS (zero-correlation zones) with oversampling factor e.g. 1024/839 + NCS2 = (N_ZC==839) ? ((NCS<<10)/839) : ((NCS<<8)/139); + + if (NCS2==0) NCS2 = N_ZC; + + + preamble_offset_old = 99; + + + *max_preamble_energy=0; + for (preamble_index=0 ; preamble_index<64 ; preamble_index++) { + + if (LOG_DEBUGFLAG(PRACH)){ + int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); + if (en>60) LOG_I(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index); + } + if (restricted_set == 0) { + // This is the relative offset in the root sequence table (5.7.2-4 from 36.211) for the given preamble index + preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); + + if (preamble_offset != preamble_offset_old) { + preamble_offset_old = preamble_offset; + new_dft = 1; + // This is the \nu corresponding to the preamble index + preamble_shift = 0; + } + + else { + preamble_shift -= NCS; + + if (preamble_shift < 0) + preamble_shift+=N_ZC; + } + } else { // This is the high-speed case + new_dft = 0; + + // set preamble_offset to initial rootSequenceIndex and look if we need more root sequences for this + // preamble index and find the corresponding cyclic shift + // Check if all shifts for that root have been processed + if (preamble_index0 == numshift) { + not_found = 1; + new_dft = 1; + preamble_index0 -= numshift; + (preamble_offset==0 && numshift==0) ? (preamble_offset) : (preamble_offset++); + + while (not_found == 1) { + // current root depending on rootSequenceIndex + int index = (rootSequenceIndex + preamble_offset) % N_ZC; + + if (prach_fmt<4) { + // prach_root_sequence_map points to prach_root_sequence_map0_3 + DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); + } else { + // prach_root_sequence_map points to prach_root_sequence_map4 + DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); + } + u = prach_root_sequence_map[index]; + + uint16_t n_group_ra = 0; + + if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { + n_shift_ra = nr_du[u]/NCS; + d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); + n_group_ra = N_ZC/d_start; + n_shift_ra_bar = max(0,(N_ZC-(nr_du[u]<<1)-(n_group_ra*d_start))/N_ZC); + } else if ( (nr_du[u]>=(N_ZC/3)) && (nr_du[u]<=((N_ZC - NCS)>>1)) ) { + n_shift_ra = (N_ZC - (nr_du[u]<<1))/NCS; + d_start = N_ZC - (nr_du[u]<<1) + (n_shift_ra * NCS); + n_group_ra = nr_du[u]/d_start; + n_shift_ra_bar = min(n_shift_ra,max(0,(nr_du[u]- (n_group_ra*d_start))/NCS)); + } else { + n_shift_ra = 0; + n_shift_ra_bar = 0; + } + + // This is the number of cyclic shifts for the current root u + numshift = (n_shift_ra*n_group_ra) + n_shift_ra_bar; + // skip to next root and recompute parameters if numshift==0 + (numshift>0) ? (not_found = 0) : (preamble_offset++); + } + } + + + if (n_shift_ra>0) + preamble_shift = -((d_start * (preamble_index0/n_shift_ra)) + ((preamble_index0%n_shift_ra)*NCS)); // minus because the channel is h(t -\tau + Cv) + else + preamble_shift = 0; + + if (preamble_shift < 0) + preamble_shift+=N_ZC; + + preamble_index0++; + + if (preamble_index == 0) + first_nonzero_root_idx = preamble_offset; + } + + // Compute DFT of RX signal (conjugate input, results in conjugate output) for each new rootSequenceIndex + if (LOG_DEBUGFLAG(PRACH)) { + int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); + if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, NCS_config %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", + frame,subframe,preamble_index,NCS,Ncs_config,N_ZC/NCS,preamble_offset,preamble_shift,en); + } + + if (new_dft == 1) { + new_dft = 0; + + Xu=(int16_t*)gNB->X_u[preamble_offset-first_nonzero_root_idx]; + memset(prach_ifft,0,((N_ZC==839) ? 2048 : 256)*sizeof(int32_t)); + + + memset(prachF, 0, sizeof(int16_t)*2*1024 ); + if (LOG_DUMPFLAG(PRACH)) { + LOG_M("prach_rxF0.m","prach_rxF0",rxsigF[0],N_ZC,1,1); + LOG_M("prach_rxF1.m","prach_rxF1",rxsigF[1],6144,1,1); + } + + for (aa=0;aa>15); + prachF[offset+1] = (int16_t)(((int32_t)Xu[offset]*rxsigF[aa][offset+1] - (int32_t)Xu[offset+1]*rxsigF[aa][offset])>>15); + } + + // Now do IFFT of size 1024 (N_ZC=839) or 256 (N_ZC=139) + if (N_ZC == 839) { + log2_ifft_size = 10; + idft1024(prachF,prach_ifft_tmp,1); + // compute energy and accumulate over receive antennas + for (i=0;i<2048;i++) + prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[i<<1] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; + } else { + idft256(prachF,prach_ifft_tmp,1); + log2_ifft_size = 8; + // compute energy and accumulate over receive antennas and repetitions for BR + for (i=0;i<256;i++) + prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[(i<<1)] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; + } + + if (LOG_DUMPFLAG(PRACH)) { + if (aa==0) LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); + if (aa==1) LOG_M("prach_rxF_comp1.m","prach_rxF_comp1",prachF,1024,1,1); + } + }// antennas_rx + } // new dft + + // check energy in nth time shift, for + + preamble_shift2 = ((preamble_shift==0) ? 0 : ((preamble_shift<*max_preamble_energy) { + *max_preamble_energy = levdB; + *max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate + *max_preamble = preamble_index; + } + } + }// preamble_index + + if (LOG_DUMPFLAG(PRACH)) { + int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); + if (en>60) { + int k = (12*n_ra_prb) - 6*fp->N_RB_UL; + + if (k<0) k+=fp->ofdm_symbol_size; + + k*=12; + k+=13; + k*=2; + + + LOG_M("rxsigF.m","prach_rxF",&rxsigF[0][0],12288,1,1); + LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); + LOG_M("Xu.m","xu",Xu,N_ZC,1,1); + LOG_M("prach_ifft0.m","prach_t0",prach_ifft,1024,1,1); + } + } /* LOG_DUMPFLAG(PRACH) */ + if (gNB) stop_meas(&gNB->rx_prach); + +} + diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.h b/openair1/PHY/NR_TRANSPORT/nr_prach.h new file mode 100644 index 0000000000..1e2b758035 --- /dev/null +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.h @@ -0,0 +1,891 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/LTE_TRANSPORT/prach_common.c + * \brief Common routines for UE/eNB PRACH physical channel V8.6 2009-03 + * \author Agustin Mico Pereperez + * \date 2018 + * \version 0.1 + * \company + * \email: + * \note + * \warning + */ + +int16_t nr_ru[2*839]; // quantized roots of unity +uint32_t nr_ZC_inv[839]; // multiplicative inverse for roots u +uint16_t nr_du[838]; + +/************************************* +* The following tables defined for NR +**************************************/ +// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz +uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419}; +uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A +uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B + +// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz +uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419}; +uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A +uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B + +// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} +uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; + +//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 +uint16_t prach_root_sequence_map_0_3[838] = { +129, 710, 140, 699, 120, 719, 210, 629, 168, 671, 84 , 755, 105, 734, 93 , 746, 70 , 769, 60 , 779, +2 , 837, 1 , 838, 56 , 783, 112, 727, 148, 691, 80 , 759, 42 , 797, 40 , 799, 35 , 804, 73 , 766, +146, 693, 31 , 808, 28 , 811, 30 , 809, 27 , 812, 29 , 810, 24 , 815, 48 , 791, 68 , 771, 74 , 765, +178, 661, 136, 703, 86 , 753, 78 , 761, 43 , 796, 39 , 800, 20 , 819, 21 , 818, 95 , 744, 202, 637, +190, 649, 181, 658, 137, 702, 125, 714, 151, 688, 217, 622, 128, 711, 142, 697, 122, 717, 203, 636, +118, 721, 110, 729, 89 , 750, 103, 736, 61 , 778, 55 , 784, 15 , 824, 14 , 825, 12 , 827, 23 , 816, +34 , 805, 37 , 802, 46 , 793, 207, 632, 179, 660, 145, 694, 130, 709, 223, 616, 228, 611, 227, 612, +132, 707, 133, 706, 143, 696, 135, 704, 161, 678, 201, 638, 173, 666, 106, 733, 83 , 756, 91 , 748, +66 , 773, 53 , 786, 10 , 829, 9 , 830, 7 , 832, 8 , 831, 16 , 823, 47 , 792, 64 , 775, 57 , 782, +104, 735, 101, 738, 108, 731, 208, 631, 184, 655, 197, 642, 191, 648, 121, 718, 141, 698, 149, 690, +216, 623, 218, 621, 152, 687, 144, 695, 134, 705, 138, 701, 199, 640, 162, 677, 176, 663, 119, 720, +158, 681, 164, 675, 174, 665, 171, 668, 170, 669, 87 , 752, 169, 670, 88 , 751, 107, 732, 81 , 758, +82 , 757, 100, 739, 98 , 741, 71 , 768, 59 , 780, 65 , 774, 50 , 789, 49 , 790, 26 , 813, 17 , 822, +13 , 826, 6 , 833, 5 , 834, 33 , 806, 51 , 788, 75 , 764, 99 , 740, 96 , 743, 97 , 742, 166, 673, +172, 667, 175, 664, 187, 652, 163, 676, 185, 654, 200, 639, 114, 725, 189, 650, 115, 724, 194, 645, +195, 644, 192, 647, 182, 657, 157, 682, 156, 683, 211, 628, 154, 685, 123, 716, 139, 700, 212, 627, +153, 686, 213, 626, 215, 624, 150, 689, 225, 614, 224, 615, 221, 618, 220, 619, 127, 712, 147, 692, +124, 715, 193, 646, 205, 634, 206, 633, 116, 723, 160, 679, 186, 653, 167, 672, 79 , 760, 85 , 754, +77 , 762, 92 , 747, 58 , 781, 62 , 777, 69 , 770, 54 , 785, 36 , 803, 32 , 807, 25 , 814, 18 , 821, +11 , 828, 4 , 835, 3 , 836, 19 , 820, 22 , 817, 41 , 798, 38 , 801, 44 , 795, 52 , 787, 45 , 794, +63 , 776, 67 , 772, 72 , 767, 76 , 763, 94 , 745, 102, 737, 90 , 749, 109, 730, 165, 674, 111, 728, +209, 630, 204, 635, 117, 722, 188, 651, 159, 680, 198, 641, 113, 726, 183, 656, 180, 659, 177, 662, +196, 643, 155, 684, 214, 625, 126, 713, 131, 708, 219, 620, 222, 617, 226, 613, 230, 609, 232, 607, +262, 577, 252, 587, 418, 421, 416, 423, 413, 426, 411, 428, 376, 463, 395, 444, 283, 556, 285, 554, +379, 460, 390, 449, 363, 476, 384, 455, 388, 451, 386, 453, 361, 478, 387, 452, 360, 479, 310, 529, +354, 485, 328, 511, 315, 524, 337, 502, 349, 490, 335, 504, 324, 515, 323, 516, 320, 519, 334, 505, +359, 480, 295, 544, 385, 454, 292, 547, 291, 548, 381, 458, 399, 440, 380, 459, 397, 442, 369, 470, +377, 462, 410, 429, 407, 432, 281, 558, 414, 425, 247, 592, 277, 562, 271, 568, 272, 567, 264, 575, +259, 580, 237, 602, 239, 600, 244, 595, 243, 596, 275, 564, 278, 561, 250, 589, 246, 593, 417, 422, +248, 591, 394, 445, 393, 446, 370, 469, 365, 474, 300, 539, 299, 540, 364, 475, 362, 477, 298, 541, +312, 527, 313, 526, 314, 525, 353, 486, 352, 487, 343, 496, 327, 512, 350, 489, 326, 513, 319, 520, +332, 507, 333, 506, 348, 491, 347, 492, 322, 517, 330, 509, 338, 501, 341, 498, 340, 499, 342, 497, +301, 538, 366, 473, 401, 438, 371, 468, 408, 431, 375, 464, 249, 590, 269, 570, 238, 601, 234, 605, +257, 582, 273, 566, 255, 584, 254, 585, 245, 594, 251, 588, 412, 427, 372, 467, 282, 557, 403, 436, +396, 443, 392, 447, 391, 448, 382, 457, 389, 450, 294, 545, 297, 542, 311, 528, 344, 495, 345, 494, +318, 521, 331, 508, 325, 514, 321, 518, 346, 493, 339, 500, 351, 488, 306, 533, 289, 550, 400, 439, +378, 461, 374, 465, 415, 424, 270, 569, 241, 598, 231, 608, 260, 579, 268, 571, 276, 563, 409, 430, +398, 441, 290, 549, 304, 535, 308, 531, 358, 481, 316, 523, 293, 546, 288, 551, 284, 555, 368, 471, +253, 586, 256, 583, 263, 576, 242, 597, 274, 565, 402, 437, 383, 456, 357, 482, 329, 510, 317, 522, +307, 532, 286, 553, 287, 552, 266, 573, 261, 578, 236, 603, 303, 536, 356, 483, 355, 484, 405, 434, +404, 435, 406, 433, 235, 604, 267, 572, 302, 537, 309, 530, 265, 574, 233, 606, 367, 472, 296, 543, +336, 503, 305, 534, 373, 466, 280, 559, 279, 560, 419, 420, 240, 599, 258, 581, 229, 610 +}; +// Table 6.3.3.1-4: Mapping from logical index i to sequence number u for preamble formats with L_RA = 139 +uint16_t prach_root_sequence_map_abc[138] = { +1 , 138, 2 , 137, 3 , 136, 4 , 135, 5 , 134, 6 , 133, 7 , 132, 8 , 131, 9 , 130, 10, 129, +11, 128, 12, 127, 13, 126, 14, 125, 15, 124, 16, 123, 17, 122, 18, 121, 19, 120, 20, 119, +21, 118, 22, 117, 23, 116, 24, 115, 25, 114, 26, 113, 27, 112, 28, 111, 29, 110, 30, 109, +31, 108, 32, 107, 33, 106, 34, 105, 35, 104, 36, 103, 37, 102, 38, 101, 39, 100, 40, 99 , +41, 98 , 42, 97 , 43, 96 , 44, 95 , 45, 94 , 46, 93 , 47, 92 , 48, 91 , 49, 90 , 50, 89 , +51, 88 , 52, 87 , 53, 86 , 54, 85 , 55, 84 , 56, 83 , 57, 82 , 58, 81 , 59, 80 , 60, 79 , +61, 78 , 62, 77 , 63, 76 , 64, 75 , 65, 74 , 66, 73 , 67, 72 , 68, 71 , 69, 70 +}; + +// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink +// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. +// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. +// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6 +int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = { +//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration +{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 +{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 +{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 +{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 +{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 +{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 +{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 +{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 +{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 +{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 +{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 +{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 +{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 +{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9 +{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 +{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 +{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 +{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 +{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 +{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 +{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 +{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 +{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 +{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 +{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 +{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 +{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4 +{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6 +{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 +{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 +{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7 +{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7 +{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8 +{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9 +{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 +{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 +{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 +{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 +{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 +{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 +{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 +{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 +{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 +{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 +{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 +{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7 +{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 +{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 +{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9 +{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 +{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 +{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 +{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 +{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 +{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 +{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 +{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 +{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 +{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 +{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 +{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 +{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 +{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9 +{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 +{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 +{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 +{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 +{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 +{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 +{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 +{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 +{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 +{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 +{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 +{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 +{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 +{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 +{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 +{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6 +{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7 +{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7 +{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8 +{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9 +{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 +{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 +{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 +{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 +{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 +{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 +{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 +{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 +{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 +{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 +{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 +{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 +{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9 +}; +// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum +int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = { +//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration +{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) +{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) +{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) +{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) +{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) +{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) +{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) +{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) +{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) +{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) +{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) +{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) +{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) +{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) +{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) +{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) +{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9) +{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) +{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) +{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6) +{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6) +{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6) +{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6) +{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6) +{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6) +{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) +{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) +{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) +{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) +{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) +{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) +{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) +{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) +{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) +{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) +{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) +{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) +{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) +{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) +{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) +{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) +{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) +{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) +{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9) +{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9) +{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9) +{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9) +{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9) +{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9) +{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9) +{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9) +{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9) +{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) +{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9) +{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9) +{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9) +{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9) +{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9) +{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9) +{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9) +{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9) +{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9) +{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9) +{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9) +{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) +{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9) +{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2) +{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7) +{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7) +{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) +{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9) +{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) +{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9) +{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9) +{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) +{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) +{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) +{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2) +{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7) +{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7) +{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) +{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9) +{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9) +{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) +{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) +{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) +{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) +{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) +{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) +{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) +{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9) +{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9) +{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9) +{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9) +{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9) +{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9) +{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9) +{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1) +{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2) +{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4) +{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7) +{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9) +{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9) +{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9) +{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9) +{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9) +{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9) +{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) +{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) +{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) +{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) +{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) +{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) +{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9) +{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) +{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9) +{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9) +{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9) +{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) +{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9) +{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9) +{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9) +{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) +{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9) +{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9) +{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9) +{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9) +{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9) +{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9) +{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9) +{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) +{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) +{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) +{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) +{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) +{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) +{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9) +{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9) +{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) +{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9) +{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) +{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9) +{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) +{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9) +{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) +{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) +{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) +{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) +{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9) +{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) +{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) +{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9) +}; +// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum +int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { +//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration +{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39) +{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39) +{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7) +{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39) +{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39) +{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39) +{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) +{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39) +{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39) +{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39) +{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39) +{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39) +{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7) +{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39) +{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39) +{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39) +{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39) +{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39) +{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13) +{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13) +{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) +{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39) +{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39) +{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) +{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13) +{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) +{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) +{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) +{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39) +{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13) +{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) +{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) +{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) +{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) +{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7) +{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) +{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) +{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) +{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) +{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) +{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) +{0xb4, -1, 16, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 16, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 8, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 8, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) +{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 4, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 4, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39) +{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39) +{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39) +{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39) +{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39) +{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) +{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39) +{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39) +{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19) +{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13) +{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 586406201480, 2, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) +{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) +{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39) +{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39) +{0xc0, -1, 16, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 16, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 8, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 8, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 8, 1, 2, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) +{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 4, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 4, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39) +{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) +{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7) +{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) +{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) +{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39) +{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) +{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39) +{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) +{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) +{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39) +{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) +{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) +{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) +{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) +{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) +{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) +{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) +{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) +{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) +{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) +{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39) +{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) +{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) +{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) +{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xa2, 0xb2, 16, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39) +{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39) +{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39) +{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39) +{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39) +{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39) +{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39) +{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) +{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) +{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39) +{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) +{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39) +{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39) +{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39) +}; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c new file mode 100644 index 0000000000..e1b80a87a2 --- /dev/null +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -0,0 +1,370 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/LTE_TRANSPORT/prach_common.c + * \brief Common routines for NR UE/gNB PRACH physical channel V15.4 2019-03 + * \author R. Knopp + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ +#include "PHY/sse_intrin.h" +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "PHY/impl_defs_nr.h" +#include "PHY/defs_nr_UE.h" +#include "PHY/NR_TRANSPORT/nr_prach.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "common/utils/LOG/log.h" +#include "common/utils/LOG/vcd_signal_dumper.h" + +#include "T.h" + +void init_nr_prach_tables(int N_ZC); + +void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { + + FILE *fd; + + fd = fopen("prach_config.txt","w"); + fprintf(fd,"prach_config: subframe = %d\n",subframe); + fprintf(fd,"prach_config: N_RB_UL = %d\n",frame_parms->N_RB_UL); + fprintf(fd,"prach_config: frame_type = %s\n",(frame_parms->frame_type==1) ? "TDD":"FDD"); + + if (frame_parms->frame_type==TDD) { + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.referenceSCS = %d\n",frame_parms->p_tdd_UL_DL_Configuration->referenceSubcarrierSpacing); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.dl_UL_TransmissionPeriodicity = %d\n",frame_parms->p_tdd_UL_DL_Configuration->dl_UL_TransmissionPeriodicity); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofDownlinkSlots = %d\n",frame_parms->p_tdd_UL_DL_Configuration->nrofDownlinkSlots); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofDownlinkSymbols = %d\n",frame_parms->p_tdd_UL_DL_Configuration->nrofDownlinkSymbols); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofUownlinkSlots = %d\n",frame_parms->p_tdd_UL_DL_Configuration->nrofDownlinkSlots); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofUownlinkSymbols = %d\n",frame_parms->p_tdd_UL_DL_Configuration->nrofDownlinkSymbols); + if (frame_parms->p_tdd_UL_DL_Configuration->p_next) { + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.referenceSCS2 = %d\n",frame_parms->p_tdd_UL_DL_Configuration->p_next->referenceSubcarrierSpacing); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.dl_UL_TransmissionPeriodicity2 = %d\n",frame_parms->p_tdd_UL_DL_Configuration->p_next->dl_UL_TransmissionPeriodicity); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofDownlinkSlots2 = %d\n",frame_parms->p_tdd_UL_DL_Configuration->p_next->nrofDownlinkSlots); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofDownlinkSymbols2 = %d\n",frame_parms->p_tdd_UL_DL_Configuration->p_next->nrofDownlinkSymbols); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofUownlinkSlots2 = %d\n",frame_parms->p_tdd_UL_DL_Configuration->p_next->nrofDownlinkSlots); + fprintf(fd,"prach_config: p_tdd_UL_DL_Configuration.nrofUownlinkSymbols2 = %d\n",frame_parms->p_tdd_UL_DL_Configuration->p_next->nrofDownlinkSymbols); + + } + } + + fprintf(fd,"prach_config: rootSequenceIndex = %d\n",frame_parms->prach_config_common.rootSequenceIndex); + fprintf(fd,"prach_config: prach_ConfigIndex = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex); + fprintf(fd,"prach_config: Ncs_config = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig); + fprintf(fd,"prach_config: highSpeedFlag = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.highSpeedFlag); + fprintf(fd,"prach_config: n_ra_prboffset = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.msg1_frequencystart); + fclose(fd); + +} + +// This function computes the du +void nr_fill_du(uint8_t prach_fmt) +{ + + uint16_t iu,u,p; + uint16_t N_ZC; + uint16_t *prach_root_sequence_map; + + if (prach_fmt<4) { + N_ZC = 839; + prach_root_sequence_map = prach_root_sequence_map_0_3; + } else { + N_ZC = 139; + prach_root_sequence_map = prach_root_sequence_map_abc; + } + + for (iu=0; iu<(N_ZC-1); iu++) { + + u=prach_root_sequence_map[iu]; + p=1; + + while (((u*p)%N_ZC)!=1) + p++; + + nr_du[u] = ((p<(N_ZC>>1)) ? p : (N_ZC-p)); + } + +} + +int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) { + + uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; + /* + // For FR1 paired + if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && + ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<slots_per_subframe; + // when were in the last slot of the subframe and this is a PRACH subframe ,return 1 + if (((slot%fp->slots_per_subframe) == fp->slots_per_subframe-1)&& + (is_nr_prach_subframe(fp,frame,subframe))) return (1); + else return(0); +} + +uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr) +{ + + if (frame_type==FDD) return (table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink + else if (fr==nr_FR1) return (table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum + else AssertFatal(1==0,"FR2 prach configuration not supported yet\n"); + // For FR2 not implemented. FIXME +} + +void compute_nr_prach_seq(uint16_t rootSequenceIndex, + uint8_t prach_ConfigIndex, + uint8_t zeroCorrelationZoneConfig, + uint8_t highSpeedFlag, + lte_frame_type_t frame_type, + nr_frequency_range_e fr, + uint32_t X_u[64][839]) +{ + + // Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC) + unsigned int k,inv_u,i,NCS=0,num_preambles; + int N_ZC; + uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,fr); + uint16_t *prach_root_sequence_map; + uint16_t u, preamble_offset; + uint16_t n_shift_ra,n_shift_ra_bar, d_start,numshift; + uint8_t not_found; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN); + +#ifdef NR_PRACH_DEBUG + LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach_fmt %x\n",zeroCorrelationZoneConfig, prach_fmt); +#endif + + + N_ZC = (prach_fmt < 4) ? 839 : 139; + //init_prach_tables(N_ZC); //moved to phy_init_lte_ue/eNB, since it takes to long in real-time + + init_nr_prach_tables(N_ZC); + + if (prach_fmt < 4) { + prach_root_sequence_map = prach_root_sequence_map_0_3; + } else { + // FIXME cannot be reached + prach_root_sequence_map = prach_root_sequence_map_abc; + } + + +#ifdef PRACH_DEBUG + LOG_I( PHY, "compute_prach_seq: done init prach_tables\n" ); +#endif + + + + + int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME + + if (highSpeedFlag== 0) { + +#ifdef PRACH_DEBUG + LOG_I(PHY,"Low speed prach : NCS_config %d\n",zeroCorrelationZoneConfig); +#endif + + AssertFatal(zeroCorrelationZoneConfig<=15, + "FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); + if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig]; + if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig]; + if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig]; + + num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC); + + if (NCS>0) num_preambles++; + + preamble_offset = 0; + } else { + +#ifdef PRACH_DEBUG + LOG_I( PHY, "high speed prach : NCS_config %"PRIu8"\n", zeroCorrelationZoneConfig ); +#endif + + AssertFatal(zeroCorrelationZoneConfig<=14, + "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); + if (prach_fmt<3){ + if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME + if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME + } + if (prach_fmt==3){ + if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME + if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME + } + if (prach_fmt>3){ + + } + + nr_fill_du(prach_fmt); + + num_preambles = 64; // compute ZC sequence for 64 possible roots + // find first non-zero shift root (stored in preamble_offset) + not_found = 1; + preamble_offset = 0; + + while (not_found == 1) { + // current root depending on rootSequenceIndex + int index = (rootSequenceIndex + preamble_offset) % N_ZC; + + if (prach_fmt<4) { + // prach_root_sequence_map points to prach_root_sequence_map0_3 + DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); + } else { + // prach_root_sequence_map points to prach_root_sequence_map4 + DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); + } + + u = prach_root_sequence_map[index]; + + uint16_t n_group_ra = 0; + + if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { + n_shift_ra = nr_du[u]/NCS; + d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); + n_group_ra = N_ZC/d_start; + n_shift_ra_bar = max(0,(N_ZC-(nr_du[u]<<1)-(n_group_ra*d_start))/N_ZC); + } else if ( (nr_du[u]>=(N_ZC/3)) && (nr_du[u]<=((N_ZC - NCS)>>1)) ) { + n_shift_ra = (N_ZC - (nr_du[u]<<1))/NCS; + d_start = N_ZC - (nr_du[u]<<1) + (n_shift_ra * NCS); + n_group_ra = nr_du[u]/d_start; + n_shift_ra_bar = min(n_shift_ra,max(0,(nr_du[u]- (n_group_ra*d_start))/NCS)); + } else { + n_shift_ra = 0; + n_shift_ra_bar = 0; + } + + // This is the number of cyclic shifts for the current root u + numshift = (n_shift_ra*n_group_ra) + n_shift_ra_bar; + + // skip to next root and recompute parameters if numshift==0 + if (numshift>0) + not_found = 0; + else + preamble_offset++; + } + } + +#ifdef PRACH_DEBUG + + if (NCS>0) + LOG_I( PHY, "Initializing %u preambles for PRACH (NCS_config %"PRIu8", NCS %u, N_ZC/NCS %u)\n", + num_preambles, zeroCorrelationZoneConfig, NCS, N_ZC/NCS ); + +#endif + + for (i=0; i +#include "nfapi_interface.h" + +// Functions below implement 36-211 and 36-212 + +/** @addtogroup _PHY_TRANSPORT_ + * @{ + */ + +/** \fn free_ue_dlsch(NR_UE_DLSCH_t *dlsch) + \brief This function frees memory allocated for a particular DLSCH at UE + @param dlsch Pointer to DLSCH to be removed +*/ +void free_nr_ue_dlsch(NR_UE_DLSCH_t *dlsch); + +/** \fn new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag) + \brief This function allocates structures for a particular DLSCH at UE + @returns Pointer to DLSCH to be removed + @param Kmimo Kmimo factor from 36-212/36-213 + @param Mdlharq Maximum number of HARQ rounds (36-212/36-213) + @param Nsoft Soft-LLR buffer size from UE-Category + @params N_RB_DL total number of resource blocks (determine the operating BW) + @param abstraction_flag Flag to indicate abstracted interface +*/ +NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag); + + +void free_nr_ue_ulsch(NR_UE_ULSCH_t *ulsch); + + +NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); + +void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); + +int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue, + unsigned char eNB_id, + uint8_t subframe, + unsigned char symbol); + +/** \brief Dump OCTAVE/MATLAB files for PMCH debugging + @param phy_vars_ue Pointer to UE variables + @param eNB_id index of eNB in ue variables + @param coded_bits_per_codeword G from 36.211 + @param subframe Index of subframe + @returns 0 on success +*/ +void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe); + + + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qpsk_qpsk(int16_t *stream0_in, + int16_t *stream1_in, + int16_t *stream0_out, + int16_t *rho01, + int32_t length); + +/** \brief This function perform LLR computation for dual-stream (QPSK/QPSK) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr128p pointer to pointer to symbol in dlsch_llr*/ +int32_t nr_dlsch_qpsk_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + int32_t **rho_i, + int16_t *dlsch_llr, + uint8_t symbol, + uint32_t len, + uint8_t first_symbol_flag, + uint16_t nb_rb, + uint16_t pbch_pss_sss_adj, + int16_t **llr128p); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/16QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qpsk_qam16(int16_t *stream0_in, + int16_t *stream1_in, + short *ch_mag_i, + int16_t *stream0_out, + int16_t *rho01, + int32_t length); + +/** \brief This function perform LLR computation for dual-stream (QPSK/16QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr128p pointer to pointer to symbol in dlsch_llr*/ +int32_t nr_dlsch_qpsk_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) + int32_t **rho_i, + int16_t *dlsch_llr, + uint8_t symbol, + uint8_t first_symbol_flag, + uint16_t nb_rb, + uint16_t pbch_pss_sss_adj, + int16_t **llr128p); + + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/64QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qpsk_qam64(int16_t *stream0_in, + int16_t *stream1_in, + short *ch_mag_i, + int16_t *stream0_out, + int16_t *rho01, + int32_t length); + +/** \brief This function perform LLR computation for dual-stream (QPSK/64QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr128p pointer to pointer to symbol in dlsch_llr*/ +int32_t nr_dlsch_qpsk_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) + int32_t **rho_i, + int16_t *dlsch_llr, + uint8_t symbol, + uint8_t first_symbol_flag, + uint16_t nb_rb, + uint16_t pbch_pss_sss_adj, + int16_t **llr128p); + + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/QPSK reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam16_qpsk(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *stream0_out, + short *rho01, + int length); +/** \brief This function perform LLR computation for dual-stream (16QAM/QPSK) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr16p pointer to pointer to symbol in dlsch_llr*/ +int nr_dlsch_16qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int **rxdataF_comp_i, + int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) + int **rho_i, + short *dlsch_llr, + unsigned char symbol, + unsigned char first_symbol_flag, + unsigned short nb_rb, + uint16_t pbch_pss_sss_adjust, + short **llr16p); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/16QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam16_qam16(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *ch_mag_i, + short *stream0_out, + short *rho01, + int length); + +/** \brief This function perform LLR computation for dual-stream (16QAM/16QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr16p pointer to pointer to symbol in dlsch_llr*/ +int nr_dlsch_16qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int **rxdataF_comp_i, + int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) + int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) + int **rho_i, + short *dlsch_llr, + unsigned char symbol, + uint32_t len, + unsigned char first_symbol_flag, + unsigned short nb_rb, + uint16_t pbch_pss_sss_adjust, + short **llr16p); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/64QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam16_qam64(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *ch_mag_i, + short *stream0_out, + short *rho01, + int length); + +/** \brief This function perform LLR computation for dual-stream (16QAM/64QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr16p pointer to pointer to symbol in dlsch_llr*/ +int nr_dlsch_16qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int **rxdataF_comp_i, + int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) + int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) + int **rho_i, + short *dlsch_llr, + unsigned char symbol, + unsigned char first_symbol_flag, + unsigned short nb_rb, + uint16_t pbch_pss_sss_adjust, + short **llr16p); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam64_qpsk(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *stream0_out, + short *rho01, + int length); + +/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr16p pointer to pointer to symbol in dlsch_llr*/ +int nr_dlsch_64qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int **rxdataF_comp_i, + int **dl_ch_mag, + int **rho_i, + short *dlsch_llr, + unsigned char symbol, + unsigned char first_symbol_flag, + unsigned short nb_rb, + uint16_t pbch_pss_sss_adjust, + short **llr16p); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam64_qam16(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *ch_mag_i, + short *stream0_out, + short *rho01, + int length); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam64_qam16_avx2(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *ch_mag_i, + short *stream0_out, + short *rho01, + int length); + +/** \brief This function perform LLR computation for dual-stream (64QAM/16QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr16p pointer to pointer to symbol in dlsch_llr*/ +int nr_dlsch_64qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int **rxdataF_comp_i, + int **dl_ch_mag, + int **dl_ch_mag_i, + int **rho_i, + short *dlsch_llr, + unsigned char symbol, + unsigned char first_symbol_flag, + unsigned short nb_rb, + uint16_t pbch_pss_sss_adjust, + short **llr16p); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam64_qam64(short *stream0_in, + short *stream1_in, + short *ch_mag, + short *ch_mag_i, + short *stream0_out, + short *rho01, + int length); + +/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. + @param stream0_in Input from channel compensated (MR combined) stream 0 + @param stream1_in Input from channel compensated (MR combined) stream 1 + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param stream0_out Output from LLR unit for stream0 + @param rho01 Cross-correlation between channels (MR combined) + @param length in complex channel outputs*/ +void qam64_qam64_avx2(int32_t *stream0_in, + int32_t *stream1_in, + int32_t *ch_mag, + int32_t *ch_mag_i, + int16_t *stream0_out, + int32_t *rho01, + int length); + +/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param ch_mag Input from scaled channel magnitude square of h0'*g0 + @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 + @param rho_i Correlation between channel of signal and inteference + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag flag to indicate this is the first symbol of the dlsch + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr16p pointer to pointer to symbol in dlsch_llr*/ +int nr_dlsch_64qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int **rxdataF_comp_i, + int **dl_ch_mag, + int **dl_ch_mag_i, + int **rho_i, + short *dlsch_llr, + unsigned char symbol, + uint32_t len, + unsigned char first_symbol_flag, + unsigned short nb_rb, + uint16_t pbch_pss_sss_adjust, + //short **llr16p, + uint32_t llr_offset); + + +/** \brief This function generates log-likelihood ratios (decoder input) for single-stream QPSK received waveforms. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param dlsch_llr llr output + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS + @param llr128p pointer to pointer to symbol in dlsch_llr + @param beamforming_mode beamforming mode +*/ +int32_t nr_dlsch_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int16_t *dlsch_llr, + uint8_t symbol, + uint32_t len, + uint8_t first_symbol_flag, + uint16_t nb_rb, + uint8_t beamforming_mode); + +/** + \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param dlsch_llr llr output + @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation and weighted for mid-point in 16QAM constellation + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adjust Adjustment factor in RE for PBCH/PSS/SSS allocations + @param llr128p pointer to pointer to symbol in dlsch_llr + @param beamforming_mode beamforming mode +*/ + +int32_t nr_dlsch_qpsk_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, + int **rxdataF_comp, + int32_t **sic_buffer, + int **rho_i, + short *dlsch_llr, + uint8_t num_pdcch_symbols, + uint16_t nb_rb, + uint8_t subframe, + uint16_t mod_order_0, + uint32_t rb_alloc); + +void nr_dlsch_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int16_t *dlsch_llr, + int32_t **dl_ch_mag, + uint8_t symbol, + uint32_t len, + uint8_t first_symbol_flag, + uint16_t nb_rb, + int16_t **llr32p, + uint8_t beamforming_mode); +/** + \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param dlsch_llr llr output + @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by first mid-point of 64-QAM constellation + @param dl_ch_magb Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by second mid-point of 64-QAM constellation + @param symbol OFDM symbol index in sub-frame + @param first_symbol_flag + @param nb_rb number of RBs for this allocation + @param pbch_pss_sss_adjust PBCH/PSS/SSS RE adjustment (in REs) + @param beamforming_mode beamforming mode +*/ +void nr_dlsch_16qam_llr_SIC (NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **sic_buffer, //Q15 + int32_t **rho_i, + int16_t *dlsch_llr, + uint8_t num_pdcch_symbols, + int32_t **dl_ch_mag, + uint16_t nb_rb, + uint8_t subframe, + uint16_t mod_order_0, + uint32_t rb_alloc); + +void dlsch_64qam_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **sic_buffer, //Q15 + int32_t **rho_i, + int16_t *dlsch_llr, + uint8_t num_pdcch_symbols, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint16_t nb_rb, + uint8_t subframe, + uint16_t mod_order_0, + uint32_t rb_alloc); + +void nr_dlsch_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int16_t *dlsch_llr, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint8_t symbol, + uint32_t len, + uint8_t first_symbol_flag, + uint16_t nb_rb, + uint32_t llr_offset, + uint8_t beamforming_mode); + + +/** \fn dlsch_siso(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + uint8_t l, + uint16_t nb_rb) + \brief This function does the first stage of llr computation for SISO, by just extracting the pilots, PBCH and primary/secondary synchronization sequences. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param l symbol in sub-frame + @param nb_rb Number of RBs in this allocation +*/ + +void dlsch_siso(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + uint8_t l, + uint16_t nb_rb); + +/** \fn dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint8_t symbol, + uint16_t nb_rb) + \brief This function does Alamouti combining on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position + @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position + @param symbol Symbol in sub-frame + @param nb_rb Number of RBs in this allocation +*/ +void dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint8_t symbol, + uint16_t nb_rb); + +/** \fn dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint8_t symbol, + uint16_t nb_rb) + \brief This function does antenna selection (based on antenna cycling pattern) on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. Note that this is not LTE, it is just included for comparison purposes. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position + @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position + @param symbol Symbol in sub-frame + @param nb_rb Number of RBs in this allocation +*/ +void dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint8_t symbol, + uint16_t nb_rb); + +/** \fn dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + int32_t **rho, + int32_t **rho_i, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + uint8_t symbol, + uint16_t nb_rb, + uint8_t dual_stream_UE) + + \brief This function does maximal-ratio combining for dual-antenna receivers. + @param frame_parms Frame descriptor structure + @param rxdataF_comp Compensated channel output + @param rxdataF_comp_i Compensated channel output for interference + @param rho Cross correlation between spatial channels + @param rho_i Cross correlation between signal and inteference channels + @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position + @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position + @param symbol Symbol in sub-frame + @param nb_rb Number of RBs in this allocation + @param dual_stream_UE Flag to indicate dual-stream detection +*/ +void dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, + int32_t **rxdataF_comp, + int32_t **rxdataF_comp_i, + int32_t **rho, + int32_t **rho_i, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + int32_t **dl_ch_mag_i, + int32_t **dl_ch_magb_i, + uint8_t symbol, + uint16_t nb_rb, + uint8_t dual_stream_UE); + +void dlsch_detection_mrc_TM34(NR_DL_FRAME_PARMS *frame_parms, + NR_UE_PDSCH *lte_ue_pdsch_vars, + int harq_pid, + int round, + unsigned char symbol, + unsigned short nb_rb, + unsigned char dual_stream_UE); + +/** \fn dlsch_extract_rbs_single(int32_t **rxdataF, + int32_t **dl_ch_estimates, + int32_t **rxdataF_ext, + int32_t **dl_ch_estimates_ext, + uint16_t pmi, + uint8_t *pmi_ext, + uint32_t *rb_alloc, + uint8_t symbol, + uint8_t subframe, + NR_DL_FRAME_PARMS *frame_parms) + \brief This function extracts the received resource blocks, both channel estimates and data symbols, + for the current allocation and for single antenna eNB transmission. + @param rxdataF Raw FFT output of received signal + @param dl_ch_estimates Channel estimates of current slot + @param rxdataF_ext FFT output for RBs in this allocation + @param dl_ch_estimates_ext Channel estimates for RBs in this allocation + @param pmi subband Precoding matrix indicator + @param pmi_ext Extracted PMI for chosen RBs + @param rb_alloc RB allocation vector + @param symbol Symbol to extract + @param subframe Subframe number + @param vrb_type Flag to indicate distributed VRB type + @param high_speed_flag + @param frame_parms Pointer to frame descriptor +*/ +/*uint16_t nr_dlsch_extract_rbs_single(int32_t **rxdataF, + int32_t **dl_ch_estimates, + int32_t **rxdataF_ext, + int32_t **dl_ch_estimates_ext, + uint16_t pmi, + uint8_t *pmi_ext, + uint32_t *rb_alloc, + uint8_t symbol, + uint8_t subframe, + uint32_t high_speed_flag, + NR_DL_FRAME_PARMS *frame_parms);*/ + +unsigned short nr_dlsch_extract_rbs_single(int **rxdataF, + int **dl_ch_estimates, + int **rxdataF_ext, + int **dl_ch_estimates_ext, + unsigned short pmi, + unsigned char *pmi_ext, + unsigned char symbol, + uint8_t pilots, + unsigned short start_rb, + unsigned short nb_pdsch_rb, + unsigned char nr_tti_rx, + uint32_t high_speed_flag, + NR_DL_FRAME_PARMS *frame_parms); + +/** \fn dlsch_extract_rbs_dual(int32_t **rxdataF, + int32_t **dl_ch_estimates, + int32_t **rxdataF_ext, + int32_t **dl_ch_estimates_ext, + uint16_t pmi, + uint8_t *pmi_ext, + uint32_t *rb_alloc, + uint8_t symbol, + NR_DL_FRAME_PARMS *frame_parms) + \brief This function extracts the received resource blocks, both channel estimates and data symbols, + for the current allocation and for dual antenna eNB transmission. + @param rxdataF Raw FFT output of received signal + @param dl_ch_estimates Channel estimates of current slot + @param rxdataF_ext FFT output for RBs in this allocation + @param dl_ch_estimates_ext Channel estimates for RBs in this allocation + @param pmi subband Precoding matrix indicator + @param pmi_ext Extracted PMI for chosen RBs + @param rb_alloc RB allocation vector + @param symbol Symbol to extract + @param subframe Subframe index + @param high_speed_flag + @param frame_parms Pointer to frame descriptor +*/ +unsigned short nr_dlsch_extract_rbs_dual(int **rxdataF, + int **dl_ch_estimates, + int **rxdataF_ext, + int **dl_ch_estimates_ext, + unsigned short pmi, + unsigned char *pmi_ext, + unsigned char symbol, + uint8_t pilots, + unsigned short start_rb, + unsigned short nb_rb_pdsch, + unsigned char nr_tti_rx, + uint32_t high_speed_flag, + NR_DL_FRAME_PARMS *frame_parms, + MIMO_mode_t mimo_mode); + +/** \fn dlsch_extract_rbs_TM7(int32_t **rxdataF, + int32_t **dl_bf_ch_estimates, + int32_t **rxdataF_ext, + int32_t **dl_bf_ch_estimates_ext, + uint32_t *rb_alloc, + uint8_t symbol, + uint8_t subframe, + uint32_t high_speed_flag, + NR_DL_FRAME_PARMS *frame_parms) + \brief This function extracts the received resource blocks, both channel estimates and data symbols, + for the current allocation and for single antenna eNB transmission. + @param rxdataF Raw FFT output of received signal + @param dl_bf_ch_estimates Beamforming channel estimates of current slot + @param rxdataF_ext FFT output for RBs in this allocation + @param dl_bf_ch_estimates_ext Beamforming channel estimates for RBs in this allocation + @param rb_alloc RB allocation vector + @param symbol Symbol to extract + @param subframe Subframe number + @param high_speed_flag + @param frame_parms Pointer to frame descriptor +*/ +uint16_t dlsch_extract_rbs_TM7(int32_t **rxdataF, + int32_t **dl_bf_ch_estimates, + int32_t **rxdataF_ext, + int32_t **dl_bf_ch_estimates_ext, + uint32_t *rb_alloc, + uint8_t symbol, + uint8_t subframe, + uint32_t high_speed_flag, + NR_DL_FRAME_PARMS *frame_parms); + +/** \brief This function performs channel compensation (matched filtering) on the received RBs for this allocation. In addition, it computes the squared-magnitude of the channel with weightings for 16QAM/64QAM detection as well as dual-stream detection (cross-correlation) + @param rxdataF_ext Frequency-domain received signal in RBs to be demodulated + @param dl_ch_estimates_ext Frequency-domain channel estimates in RBs to be demodulated + @param dl_ch_mag First Channel magnitudes (16QAM/64QAM) + @param dl_ch_magb Second weighted Channel magnitudes (64QAM) + @param rxdataF_comp Compensated received waveform + @param rho Cross-correlation between two spatial channels on each RX antenna + @param frame_parms Pointer to frame descriptor + @param symbol Symbol on which to operate + @param first_symbol_flag set to 1 on first DLSCH symbol + @param mod_order Modulation order of allocation + @param nb_rb Number of RBs in allocation + @param output_shift Rescaling for compensated output (should be energy-normalizing) + @param phy_measurements Pointer to UE PHY measurements +*/ +void nr_dlsch_channel_compensation(int32_t **rxdataF_ext, + int32_t **dl_ch_estimates_ext, + int32_t **dl_ch_mag, + int32_t **dl_ch_magb, + int32_t **rxdataF_comp, + int32_t **rho, + NR_DL_FRAME_PARMS *frame_parms, + uint8_t symbol, + uint8_t start_symbol, + uint8_t first_symbol_flag, + uint8_t mod_order, + uint16_t nb_rb, + uint8_t output_shift, + PHY_NR_MEASUREMENTS *phy_measurements); + +void nr_dlsch_channel_compensation_core(int **rxdataF_ext, + int **dl_ch_estimates_ext, + int **dl_ch_mag, + int **dl_ch_magb, + int **rxdataF_comp, + int **rho, + unsigned char n_tx, + unsigned char n_rx, + unsigned char mod_order, + unsigned char output_shift, + int length, + int start_point); + +void nr_dlsch_deinterleaving(uint8_t symbol, + uint8_t start_symbol, + uint16_t L, + uint16_t *llr, + uint16_t *llr_deint, + uint16_t nb_rb_pdsch); + +void dlsch_dual_stream_correlation(NR_DL_FRAME_PARMS *frame_parms, + unsigned char symbol, + unsigned short nb_rb, + int **dl_ch_estimates_ext, + int **dl_ch_estimates_ext_i, + int **dl_ch_rho_ext, + unsigned char output_shift); + +void dlsch_dual_stream_correlationTM34(NR_DL_FRAME_PARMS *frame_parms, + unsigned char symbol, + unsigned short nb_rb, + int **dl_ch_estimates_ext, + int **dl_ch_estimates_ext_i, + int **dl_ch_rho_ext, + unsigned char output_shift0, + unsigned char output_shift1); +//This function is used to compute multiplications in Hhermitian * H matrix +void conjch0_mult_ch1(int *ch0, + int *ch1, + int32_t *ch0conj_ch1, + unsigned short nb_rb, + unsigned char output_shift0); + +void construct_HhH_elements(int *ch0conj_ch0, + int *ch1conj_ch1, + int *ch2conj_ch2, + int *ch3conj_ch3, + int *ch0conj_ch1, + int *ch1conj_ch0, + int *ch2conj_ch3, + int *ch3conj_ch2, + int32_t *after_mf_00, + int32_t *after_mf_01, + int32_t *after_mf_10, + int32_t *after_mf_11, + unsigned short nb_rb); + +void squared_matrix_element(int32_t *Hh_h_00, + int32_t *Hh_h_00_sq, + unsigned short nb_rb); + +void dlsch_channel_level_TM34_meas(int *ch00, + int *ch01, + int *ch10, + int *ch11, + int *avg_0, + int *avg_1, + unsigned short nb_rb); + +void nr_dlsch_channel_level_median(int **dl_ch_estimates_ext, + int32_t *median, + int n_tx, + int n_rx, + int length, + int start_point); + +void nr_dlsch_detection_mrc_core(int **rxdataF_comp, + int **rxdataF_comp_i, + int **rho, + int **rho_i, + int **dl_ch_mag, + int **dl_ch_magb, + int **dl_ch_mag_i, + int **dl_ch_magb_i, + unsigned char n_tx, + unsigned char n_rx, + int length, + int start_point); + +void det_HhH(int32_t *after_mf_00, + int32_t *after_mf_01, + int32_t *after_mf_10, + int32_t *after_mf_11, + int32_t *det_fin_128, + unsigned short nb_rb); + +void numer(int32_t *Hh_h_00_sq, + int32_t *Hh_h_01_sq, + int32_t *Hh_h_10_sq, + int32_t *Hh_h_11_sq, + int32_t *num_fin, + unsigned short nb_rb); + +uint8_t rank_estimation_tm3_tm4(int *dl_ch_estimates_00, + int *dl_ch_estimates_01, + int *dl_ch_estimates_10, + int *dl_ch_estimates_11, + unsigned short nb_rb); + +void dlsch_channel_compensation_TM56(int **rxdataF_ext, + int **dl_ch_estimates_ext, + int **dl_ch_mag, + int **dl_ch_magb, + int **rxdataF_comp, + unsigned char *pmi_ext, + NR_DL_FRAME_PARMS *frame_parms, + PHY_NR_MEASUREMENTS *phy_measurements, + int eNB_id, + unsigned char symbol, + unsigned char mod_order, + unsigned short nb_rb, + unsigned char output_shift, + unsigned char dl_power_off); + + +void dlsch_channel_compensation_TM34(NR_DL_FRAME_PARMS *frame_parms, + NR_UE_PDSCH *lte_ue_pdsch_vars, + PHY_NR_MEASUREMENTS *phy_measurements, + int eNB_id, + unsigned char symbol, + unsigned char mod_order0, + unsigned char mod_order1, + int harq_pid, + int round, + MIMO_mode_t mimo_mode, + unsigned short nb_rb, + unsigned char output_shift0, + unsigned char output_shift1); + + +/** \brief This function computes the average channel level over all allocated RBs and antennas (TX/RX) in order to compute output shift for compensated signal + @param dl_ch_estimates_ext Channel estimates in allocated RBs + @param frame_parms Pointer to frame descriptor + @param avg Pointer to average signal strength + @param pilots_flag Flag to indicate pilots in symbol + @param nb_rb Number of allocated RBs +*/ +void nr_dlsch_channel_level(int **dl_ch_estimates_ext, + NR_DL_FRAME_PARMS *frame_parms, + int32_t *avg, + uint8_t symbol, + uint32_t len, + unsigned short nb_rb); + + +void dlsch_channel_level_TM34(int **dl_ch_estimates_ext, + NR_DL_FRAME_PARMS *frame_parms, + unsigned char *pmi_ext, + int *avg_0, + int *avg_1, + uint8_t symbol, + unsigned short nb_rb, + MIMO_mode_t mimo_mode); + + +void dlsch_channel_level_TM56(int32_t **dl_ch_estimates_ext, + NR_DL_FRAME_PARMS *frame_parms, + unsigned char *pmi_ext, + int32_t *avg, + uint8_t symbol_mod, + uint16_t nb_rb); + +void dlsch_channel_level_TM7(int32_t **dl_bf_ch_estimates_ext, + NR_DL_FRAME_PARMS *frame_parms, + int32_t *avg, + uint8_t pilots_flag, + uint16_t nb_rb); + +void nr_dlsch_scale_channel(int32_t **dl_ch_estimates_ext, + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_DLSCH_t **dlsch_ue, + uint8_t symbol, + uint8_t start_symbol, + uint16_t nb_rb); + +/** \brief This is the top-level entry point for DLSCH decoding in UE. It should be replicated on several + threads (on multi-core machines) corresponding to different HARQ processes. The routine first + computes the segmentation information, followed by rate dematching and sub-block deinterleaving the of the + received LLRs computed by dlsch_demodulation for each transport block segment. It then calls the + turbo-decoding algorithm for each segment and stops after either after unsuccesful decoding of at least + one segment or correct decoding of all segments. Only the segment CRCs are check for the moment, the + overall CRC is ignored. Finally transport block reassembly is performed. + @param phy_vars_ue Pointer to ue variables + @param dlsch_llr Pointer to LLR values computed by dlsch_demodulation + @param lte_frame_parms Pointer to frame descriptor + @param dlsch Pointer to DLSCH descriptor + @param frame Frame number + @param subframe Subframe number + @param num_pdcch_symbols Number of PDCCH symbols + @param is_crnti indicates if PDSCH belongs to a CRNTI (necessary for parallelizing decoding threads) + @param llr8_flag If 1, indicate that the 8-bit turbo decoder should be used + @returns 0 on success, 1 on unsuccessful decoding +*/ + +uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, + short *dlsch_llr, + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_DLSCH_t *dlsch, + NR_DL_UE_HARQ_t *harq_process, + uint32_t frame, + uint16_t nb_symb_sch, + uint8_t nr_tti_rx, + uint8_t harq_pid, + uint8_t is_crnti, + uint8_t llr8_flag); + +int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, + NR_DL_FRAME_PARMS* frame_parms, + uint8_t harq_pid); + +/*! \brief Perform PUSCH scrambling. TS 38.211 V15.4.0 subclause 6.3.1.1 + @param[in] in Pointer to input bits + @param[in] size of input bits + @param[in] Nid cell id + @param[in] n_RNTI CRNTI + @param[out] out the scrambled bits +*/ + +void nr_pusch_codeword_scrambling(uint8_t *in, + uint16_t size, + uint32_t Nid, + uint32_t n_RNTI, + uint32_t* out); + + +uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, + UE_nr_rxtx_proc_t *proc, + int eNB_id, + short *dlsch_llr, + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_DLSCH_t *dlsch, + NR_DL_UE_HARQ_t *harq_process, + uint32_t frame, + uint16_t nb_symb_sch, + uint8_t nr_tti_rx, + uint8_t harq_pid, + uint8_t is_crnti, + uint8_t llr8_flag); + +void *nr_dlsch_decoding_2thread0(void *arg); + +void *nr_dlsch_decoding_2thread1(void *arg); + +void nr_dlsch_unscrambling(int16_t* llr, + uint32_t size, + uint8_t q, + uint32_t Nid, + uint32_t n_RNTI); + +uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue, + uint8_t subframe, + PDSCH_t dlsch_id, + uint8_t eNB_id); + +/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs + - RB extraction (signal and channel estimates) + - channel compensation (matched filtering) + - RE extraction (pilot, PBCH, synch. signals) + - antenna combining (MRC, Alamouti, cycling) + - LLR computation + This function supports TM1, 2, 3, 5, and 6. + @param PHY_VARS_NR_UE Pointer to PHY variables + @param type Type of PDSCH (SI_PDSCH,RA_PDSCH,PDSCH,PMCH) + @param eNB_id eNb index (Nid1) 0,1,2 + @param eNB_id_i Interfering eNB index (Nid1) 0,1,2, or 3 in case of MU-MIMO IC receiver + @param subframe Subframe number + @param symbol Symbol on which to act (within sub-frame) + @param first_symbol_flag set to 1 on first DLSCH symbol + @param rx_type. rx_type=RX_IC_single_stream will enable interference cancellation of a second stream when decoding the first stream. In case of TM1, 2, 5, and this can cancel interference from a neighbouring cell given by eNB_id_i. In case of TM5, eNB_id_i should be set to n_connected_eNB to perform multi-user interference cancellation. In case of TM3, eNB_id_i should be set to eNB_id to perform co-channel interference cancellation; this option should be used together with an interference cancellation step [...]. In case of TM3, if rx_type=RX_IC_dual_stream, both streams will be decoded by applying the IC single stream receiver twice. + @param i_mod Modulation order of the interfering stream +*/ +int32_t nr_rx_pdsch(PHY_VARS_NR_UE *phy_vars_ue, + PDSCH_t type, + uint8_t eNB_id, + uint8_t eNB_id_i, + uint32_t frame, + uint8_t subframe, + uint8_t symbol, + uint8_t first_symbol_flag, + RX_type_t rx_type, + uint8_t i_mod, + uint8_t harq_pid); + +int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, + uint32_t frame, + uint8_t nr_tti_rx, + uint8_t eNB_id, + MIMO_mode_t mimo_mode, + uint32_t high_speed_flag, + uint8_t is_secondary_ue, + int nb_coreset_active, + uint16_t symbol_mon, + NR_SEARCHSPACE_TYPE_t searchSpaceType); + +/*! \brief Extract PSS and SSS resource elements + @param phy_vars_ue Pointer to UE variables + @param[out] pss_ext contain the PSS signals after the extraction + @param[out] sss_ext contain the SSS signals after the extraction + @returns 0 on success +*/ +int pss_sss_extract(PHY_VARS_NR_UE *phy_vars_ue, + int32_t pss_ext[4][72], + int32_t sss_ext[4][72], + uint8_t subframe); + +/*! \brief Extract only PSS resource elements + @param phy_vars_ue Pointer to UE variables + @param[out] pss_ext contain the PSS signals after the extraction + @returns 0 on success +*/ +int pss_only_extract(PHY_VARS_NR_UE *phy_vars_ue, + int32_t pss_ext[4][72], + uint8_t subframe); + +/*! \brief Extract only SSS resource elements + @param phy_vars_ue Pointer to UE variables + @param[out] sss_ext contain the SSS signals after the extraction + @returns 0 on success +*/ +int sss_only_extract(PHY_VARS_NR_UE *phy_vars_ue, + int32_t sss_ext[4][72], + uint8_t subframe); + +/*! \brief Performs detection of SSS to find cell ID and other framing parameters (FDD/TDD, normal/extended prefix) + @param phy_vars_ue Pointer to UE variables + @param tot_metric Pointer to variable containing maximum metric under framing hypothesis (to be compared to other hypotheses + @param flip_max Pointer to variable indicating if start of frame is in second have of RX buffer (i.e. PSS/SSS is flipped) + @param phase_max Pointer to variable (0 ... 6) containing rought phase offset between PSS and SSS (can be used for carrier + frequency adjustment. 0 means -pi/3, 6 means pi/3. + @returns 0 on success +*/ +int rx_sss(PHY_VARS_NR_UE *phy_vars_ue,int32_t *tot_metric,uint8_t *flip_max,uint8_t *phase_max); + +/*! \brief receiver for the PBCH + \returns number of tx antennas or -1 if error +*/ +int nr_rx_pbch( PHY_VARS_NR_UE *ue, + UE_nr_rxtx_proc_t *proc, + NR_UE_PBCH *nr_ue_pbch_vars, + NR_DL_FRAME_PARMS *frame_parms, + uint8_t eNB_id, + uint8_t i_ssb, + MIMO_mode_t mimo_mode, + uint32_t high_speed_flag); + +int nr_pbch_detection(UE_nr_rxtx_proc_t *proc, + PHY_VARS_NR_UE *ue, + int pbch_initial_symbol, + runmode_t mode); + +uint16_t rx_pbch_emul(PHY_VARS_NR_UE *phy_vars_ue, + uint8_t eNB_id, + uint8_t pbch_phase); + + +/*! \brief PBCH unscrambling + This is similar to pbch_scrabling with the difference that inputs are signed s16s (llr values) and instead of flipping bits we change signs. + \param frame_parms Pointer to frame descriptor + \param llr Output of the demodulator + \param length Length of the sequence + \param frame_mod4 Frame number modulo 4*/ +void pbch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, + int8_t* llr, + uint32_t length, + uint8_t frame_mod4); + + +void generate_64qam_table(void); +void generate_16qam_table(void); +void generate_qpsk_table(void); + +uint16_t extract_crc(uint8_t *dci,uint8_t DCI_LENGTH); + +/*! \brief LLR from two streams. This function takes two streams (qpsk modulated) and calculates the LLR, considering one stream as interference. + \param stream0_in pointer to first stream0 + \param stream1_in pointer to first stream1 + \param stream0_out pointer to output stream + \param rho01 pointer to correlation matrix + \param length*/ +void qpsk_qpsk_TM3456(short *stream0_in, + short *stream1_in, + short *stream0_out, + short *rho01, + int length + ); + +/** \brief Attempt decoding of a particular DCI with given length and format. + @param DCI_LENGTH length of DCI in bits + @param DCI_FMT Format of DCI + @param e e-sequence (soft bits) + @param decoded_output Output of Viterbi decoder +*/ +void dci_decoding(uint8_t DCI_LENGTH, + uint8_t DCI_FMT, + int8_t *e, + uint8_t *decoded_output); + +/** \brief Do 36.213 DCI decoding procedure by searching different RNTI options and aggregation levels. Currently does + not employ the complexity reducing procedure based on RNTI. + @param phy_vars_ue UE variables + @param dci_alloc Pointer to DCI_ALLOC_t array to store results for DLSCH/ULSCH programming + @param do_common If 1 perform search in common search-space else ue-specific search-space + @param eNB_id eNB Index on which to act + @param subframe Index of subframe + @returns bitmap of occupied CCE positions (i.e. those detected) +*/ +uint16_t dci_decoding_procedure(PHY_VARS_NR_UE *phy_vars_ue, + DCI_ALLOC_t *dci_alloc, + int do_common, + int16_t eNB_id, + uint8_t subframe); + +uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_NR_UE *ue, + DCI_ALLOC_t *dci_alloc, + uint8_t DCIFormat, + uint8_t agregationLevel, + int16_t eNB_id, + uint8_t subframe); + +uint16_t dci_decoding_procedure_emul(NR_UE_PDCCH **lte_ue_pdcch_vars, + uint8_t num_ue_spec_dci, + uint8_t num_common_dci, + DCI_ALLOC_t *dci_alloc_tx, + DCI_ALLOC_t *dci_alloc_rx, + int16_t eNB_id); + +/** \brief Compute Q (modulation order) based on I_MCS PDSCH. Implements table 7.1.7.1-1 from 36.213. + @param I_MCS */ +uint8_t get_Qm(uint8_t I_MCS); + +/** \brief Compute Q (modulation order) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213. + @param I_MCS */ +uint8_t get_Qm_ul(uint8_t I_MCS); + +/** \brief Compute I_TBS (transport-block size) based on I_MCS for PDSCH. Implements table 7.1.7.1-1 from 36.213. + @param I_MCS */ +uint8_t get_I_TBS(uint8_t I_MCS); + +/** \brief Compute I_TBS (transport-block size) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213. + @param I_MCS */ +unsigned char get_I_TBS_UL(unsigned char I_MCS); + +/** \brief Compute Q (modulation order) based on downlink I_MCS. Implements table 7.1.7.1-1 from 36.213. + @param I_MCS + @param nb_rb + @return Transport block size */ +uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb); + +/** \brief Compute Q (modulation order) based on uplink I_MCS. Implements table 7.1.7.1-1 from 36.213. + @param I_MCS + @param nb_rb + @return Transport block size */ +uint32_t get_TBS_UL(uint8_t mcs, uint16_t nb_rb); + +/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type + @param N_RB_DL number of PRB on DL + @param indicator for even/odd slot + @param vrb vrb index + @param Ngap Gap indicator +*/ +uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap); + +/* \brief Return prb for a given vrb index + @param vrb_type VRB type (0=localized,1=distributed) + @param rb_alloc_dci rballoc field from DCI +*/ +uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci); + + +/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type + @returns Transmission mode (1-7) +*/ +uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti); + + +/* \brief + @param ra_header Header of resource allocation (0,1) (See sections 7.1.6.1/7.1.6.2 of 36.213 Rel8.6) + @param rb_alloc Bitmap allocation from DCI (format 1,2) + @returns number of physical resource blocks +*/ +uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL); + +int get_G(NR_DL_FRAME_PARMS *frame_parms,uint16_t nb_rb,uint32_t *rb_alloc,uint8_t mod_order,uint8_t Nl,uint8_t num_pdcch_symbols,int frame,uint8_t subframe, uint8_t beamforming_mode); + +int adjust_G(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe); +int adjust_G2(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe,uint8_t symbol); + + +#ifndef modOrder +#define modOrder(I_MCS,I_TBS) ((I_MCS-I_TBS)*2+2) // Find modulation order from I_TBS and I_MCS +#endif + +/** \fn uint8_t I_TBS2I_MCS(uint8_t I_TBS); + \brief This function maps I_tbs to I_mcs according to Table 7.1.7.1-1 in 3GPP TS 36.213 V8.6.0. Where there is two supported modulation orders for the same I_TBS then either high or low modulation is chosen by changing the equality of the two first comparisons in the if-else statement. + \param I_TBS Index of Transport Block Size + \return I_MCS given I_TBS +*/ +uint8_t I_TBS2I_MCS(uint8_t I_TBS); + +/** \fn uint8_t SE2I_TBS(float SE, + uint8_t N_PRB, + uint8_t symbPerRB); + \brief This function maps a requested throughput in number of bits to I_tbs. The throughput is calculated as a function of modulation order, RB allocation and number of symbols per RB. The mapping orginates in the "Transport block size table" (Table 7.1.7.2.1-1 in 3GPP TS 36.213 V8.6.0) + \param SE Spectral Efficiency (before casting to integer, multiply by 1024, remember to divide result by 1024!) + \param N_PRB Number of PhysicalResourceBlocks allocated \sa lte_frame_parms->N_RB_DL + \param symbPerRB Number of symbols per resource block allocated to this channel + \return I_TBS given an SE and an N_PRB +*/ +uint8_t SE2I_TBS(float SE, + uint8_t N_PRB, + uint8_t symbPerRB); +/** \brief This function generates the sounding reference symbol (SRS) for the uplink according to 36.211 v8.6.0. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence. + @param frame_parms LTE DL Frame Parameters + @param soundingrs_ul_config_dedicated Dynamic configuration from RRC during Connection Establishment + @param txdataF pointer to the frequency domain TX signal + @returns 0 on success*/ +int generate_srs(NR_DL_FRAME_PARMS *frame_parms, + SOUNDINGRS_UL_CONFIG_DEDICATED *soundingrs_ul_config_dedicated, + int *txdataF, + int16_t amp, + uint32_t subframe); + + +/*! + \brief This function is similar to generate_srs_tx but generates a conjugate sequence for channel estimation. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence. + @param phy_vars_ue Pointer to PHY_VARS structure + @param eNB_id Index of destination eNB for this SRS + @param amp Linear amplitude of SRS + @param subframe Index of subframe on which to act + @returns 0 on success, -1 on error with message +*/ + +int32_t generate_srs_tx(PHY_VARS_NR_UE *phy_vars_ue, + uint8_t eNB_id, + int16_t amp, + uint32_t subframe); + +/*! + \brief This function generates the downlink reference signal for the PUSCH according to 36.211 v8.6.0. The DRS occuies the RS defined by rb_alloc and the symbols 2 and 8 for extended CP and 3 and 10 for normal CP. +*/ + +int32_t generate_drs_pusch(PHY_VARS_NR_UE *phy_vars_ue, + UE_nr_rxtx_proc_t *proc, + uint8_t eNB_id, + int16_t amp, + uint32_t subframe, + uint32_t first_rb, + uint32_t nb_rb, + uint8_t ant); + +/*! + \brief This function initializes the Group Hopping, Sequence Hopping and nPRS sequences for PUCCH/PUSCH according to 36.211 v8.6.0. It should be called after configuration of UE (reception of SIB2/3) and initial configuration of eNB (or after reconfiguration of cell-specific parameters). + @param frame_parms Pointer to a NR_DL_FRAME_PARMS structure (eNB or UE)*/ +void init_ul_hopping(NR_DL_FRAME_PARMS *frame_parms); + + +/*! + \brief This function implements the initialization of paging parameters for UE (See Section 7, 36.304).It must be called after setting IMSImod1024 during UE startup and after receiving SIB2 + @param ue Pointer to UE context + @param defaultPagingCycle T from 36.304 (0=32,1=64,2=128,3=256) + @param nB nB from 36.304 (0=4T,1=2T,2=T,3=T/2,4=T/4,5=T/8,6=T/16,7=T/32*/ +int init_ue_paging_info(PHY_VARS_NR_UE *ue, long defaultPagingCycle, long nB); + +int32_t compareints (const void * a, const void * b); + + +void ulsch_modulation(int32_t **txdataF, + int16_t amp, + frame_t frame, + uint32_t subframe, + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_ULSCH_t *ulsch); + + + + + + +int generate_ue_dlsch_params_from_dci(int frame, + uint8_t subframe, + void *dci_pdu, + rnti_t rnti, + DCI_format_t dci_format, + NR_UE_PDCCH *pdcch_vars, + NR_UE_PDSCH *pdsch_vars, + NR_UE_DLSCH_t **dlsch, + NR_DL_FRAME_PARMS *frame_parms, + PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, + uint16_t si_rnti, + uint16_t ra_rnti, + uint16_t p_rnti, + uint8_t beamforming_mode, + uint16_t tc_rnti); + + +int generate_ue_ulsch_params_from_dci(void *dci_pdu, + rnti_t rnti, + uint8_t subframe, + DCI_format_t dci_format, + PHY_VARS_NR_UE *phy_vars_ue, + UE_nr_rxtx_proc_t *proc, + uint16_t si_rnti, + uint16_t ra_rnti, + uint16_t p_rnti, + uint16_t cba_rnti, + uint8_t eNB_id, + uint8_t use_srs); + +int32_t generate_ue_ulsch_params_from_rar(PHY_VARS_NR_UE *phy_vars_ue, + UE_nr_rxtx_proc_t *proc, + uint8_t eNB_id); +double sinr_eff_cqi_calc(PHY_VARS_NR_UE *phy_vars_ue, + uint8_t eNB_id, + uint8_t subframe); + +uint8_t sinr2cqi(double sinr,uint8_t trans_mode); + + +int dump_dci(NR_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci); + +int dump_ue_stats(PHY_VARS_NR_UE *phy_vars_ue, UE_nr_rxtx_proc_t *proc, char* buffer, int length, runmode_t mode, int input_level_dBm); + +void init_transport_channels(uint8_t); + +void generate_RIV_tables(void); + +/*! + \brief This function performs the initial cell search procedure - PSS detection, SSS detection and PBCH detection. At the + end, the basic frame parameters are known (Frame configuration - TDD/FDD and cyclic prefix length, + N_RB_DL, PHICH_CONFIG and Nid_cell) and the UE can begin decoding PDCCH and DLSCH SI to retrieve the rest. Once these + parameters are know, the routine calls some basic initialization routines (cell-specific reference signals, etc.) + @param phy_vars_ue Pointer to UE variables + @param mode current running mode +*/ +int nr_initial_sync(UE_nr_rxtx_proc_t *proc, + PHY_VARS_NR_UE *phy_vars_ue, runmode_t mode); + + +/*! + \brief Encoding of PUSCH/ACK/RI/ACK from 36-212. + @param a Pointer to ulsch SDU + @param frame_parms Pointer to Frame parameters + @param ulsch Pointer to ulsch descriptor + @param harq_pid HARQ process ID + @param tmode Transmission mode (1-7) + @param control_only_flag Generate PUSCH with control information only + @param Nbundled Parameter for ACK/NAK bundling (36.213 Section 7.3) +*/ +uint32_t ulsch_encoding(uint8_t *a, + PHY_VARS_NR_UE *phy_vars_ue, + uint8_t harq_pid, + uint8_t eNB_id, + uint8_t subframe_rx, + uint8_t tmode, + uint8_t control_only_flag, + uint8_t Nbundled); + +void print_CQI(void *o,UCI_format_t uci_format,uint8_t eNB_id,int N_RB_DL); + +void fill_CQI(NR_UE_ULSCH_t *ulsch,PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id, uint8_t harq_pid,int N_RB_DL, rnti_t rnti, uint8_t trans_mode,double sinr_eff); + +void reset_cba_uci(void *o); + +/** \brief This routine computes the subband PMI bitmap based on measurements (0,1,2,3 for rank 0 and 0,1 for rank 1) in the format needed for UCI + @param meas pointer to measurements + @param eNB_id eNB_id + @param nb_subbands number of subbands + @returns subband PMI bitmap +*/ +uint16_t quantize_subband_pmi(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,int nb_subbands); + +int32_t pmi_convert_rank1_from_rank2(uint16_t pmi_alloc, int tpmi, int nb_rb); + +uint16_t quantize_subband_pmi2(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t a_id,int nb_subbands); + + + +uint64_t cqi2hex(uint32_t cqi); + +uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs); + + +/** \brief This routine extracts a single subband PMI from a bitmap coming from UCI or the pmi_extend function + @param N_RB_DL number of resource blocks + @param mimo_mode + @param pmi_alloc subband PMI bitmap + @param rb resource block for which to extract PMI + @returns subband PMI +*/ +uint8_t get_pmi(uint8_t N_RB_DL,MIMO_mode_t mode, uint32_t pmi_alloc,uint16_t rb); + +int get_nCCE_offset_l1(int *CCE_table, + const unsigned char L, + const int nCCE, + const int common_dci, + const unsigned short rnti, + const unsigned char subframe); + +uint16_t get_nCCE(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi); + +uint16_t get_nquad(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi); + +uint8_t get_mi(NR_DL_FRAME_PARMS *frame,uint8_t subframe); + +uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe); + +uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); + +void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); + +void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, + uint8_t subframe, + int8_t* llr, + uint32_t length); + + + +void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, + int mbsfn_flag, + NR_UE_DLSCH_t *dlsch, + int G, + int16_t* llr, + uint8_t q, + uint8_t Ns); + +void init_ncs_cell(NR_DL_FRAME_PARMS *frame_parms,uint8_t ncs_cell[20][7]); + +void generate_pucch1x(int32_t **txdataF, + NR_DL_FRAME_PARMS *frame_parms, + uint8_t ncs_cell[20][7], + PUCCH_FMT_t fmt, + PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + uint16_t n1_pucch, + uint8_t shortened_format, + uint8_t *payload, + int16_t amp, + uint8_t subframe); + +void generate_pucch2x(int32_t **txdataF, + NR_DL_FRAME_PARMS *fp, + uint8_t ncs_cell[20][7], + PUCCH_FMT_t fmt, + PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + uint16_t n2_pucch, + uint8_t *payload, + int A, + int B2, + int16_t amp, + uint8_t subframe, + uint16_t rnti); + +void generate_pucch3x(int32_t **txdataF, + NR_DL_FRAME_PARMS *frame_parms, + uint8_t ncs_cell[20][7], + PUCCH_FMT_t fmt, + PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + uint16_t n3_pucch, + uint8_t shortened_format, + uint8_t *payload, + int16_t amp, + uint8_t subframe, + uint16_t rnti); + + +void init_ulsch_power_LUT(void); + +/*! + \brief Check for PRACH TXop in subframe + @param frame_parms Pointer to NR_DL_FRAME_PARMS + @param frame frame index to check + @param subframe subframe index to check + @returns 0 on success +*/ +int is_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,frame_t frame, uint8_t subframe); + +/*! + \brief Generate PRACH waveform + @param phy_vars_ue Pointer to ue top-level descriptor + @param eNB_id Index of destination eNB + @param subframe subframe index to operate on + @param index of preamble (0-63) + @param Nf System frame number + @returns 0 on success + +*/ +int32_t generate_prach(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe,uint16_t Nf); + + +/*! + \brief Helper for MAC, returns number of available PRACH in TDD for a particular configuration index + @param frame_parms Pointer to NR_DL_FRAME_PARMS structure + @returns 0-5 depending on number of available prach +*/ +uint8_t get_num_prach_tdd(module_id_t Mod_id); + +/*! + \brief Return the PRACH format as a function of the Configuration Index and Frame type. + @param prach_ConfigIndex PRACH Configuration Index + @param frame_type 0-FDD, 1-TDD + @returns 0-1 accordingly +*/ +uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type); + +uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr); + +/*! + \brief Helper for MAC, returns frequency index of PRACH resource in TDD for a particular configuration index + @param frame_parms Pointer to NR_DL_FRAME_PARMS structure + @returns 0-5 depending on number of available prach +*/ +uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index); + +/*! + \brief Comp ute DFT of PRACH ZC sequences. Used for generation of prach in UE and reception of PRACH in eNB. + @param rootSequenceIndex PRACH root sequence + #param prach_ConfigIndex PRACH Configuration Index + @param zeroCorrelationZoneConfig PRACH ncs_config + @param highSpeedFlat PRACH High-Speed Flag + @param frame_type TDD/FDD flag + @param Xu DFT output +*/ +void compute_prach_seq(uint16_t rootSequenceIndex, + uint8_t prach_ConfigIndex, + uint8_t zeroCorrelationZoneConfig, + uint8_t highSpeedFlag, + lte_frame_type_t frame_type, + uint32_t X_u[64][839]); + + +void init_prach_tables(int N_ZC); + +void init_unscrambling_lut(void); +void init_scrambling_lut(void); + +/*! + \brief Return the status of MBSFN in this frame/subframe + @param frame Frame index + @param subframe Subframe index + @param frame_parms Pointer to frame parameters + @returns 1 if subframe is for MBSFN +*/ +int is_pmch_subframe(frame_t frame, int subframe, NR_DL_FRAME_PARMS *frame_parms); + +uint8_t is_not_pilot(uint8_t pilots, uint8_t re, uint8_t nushift, uint8_t use2ndpilots); + +uint8_t is_not_UEspecRS(int8_t lprime, uint8_t re, uint8_t nushift, uint8_t Ncp, uint8_t beamforming_mode); + +uint32_t dlsch_decoding_abstraction(double *dlsch_MIPB, + NR_DL_FRAME_PARMS *lte_frame_parms, + NR_UE_DLSCH_t *dlsch, + uint8_t subframe, + uint8_t num_pdcch_symbols); + +// DL power control functions +double get_pa_dB(uint8_t pa); + + +double computeRhoA_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, + NR_UE_DLSCH_t *dlsch_ue, + uint8_t dl_power_off, + uint8_t n_antenna_port); + +double computeRhoB_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, + PDSCH_CONFIG_COMMON *pdsch_config_common, + uint8_t n_antenna_port, + NR_UE_DLSCH_t *dlsch_ue, + uint8_t dl_power_off); + +/*void compute_sqrt_RhoAoRhoB(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, + PDSCH_CONFIG_COMMON *pdsch_config_common, + uint8_t n_antenna_port, + NR_UE_DLSCH_t *dlsch_ue); +*/ + +uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms, + uint8_t prach_ConfigIndex, + uint8_t n_ra_prboffset, + uint8_t tdd_mapindex, uint16_t Nf); + +void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, + int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common); + + +uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset); + +int nr_rx_pdsch(PHY_VARS_NR_UE *ue, + PDSCH_t type, + unsigned char eNB_id, + unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference + uint32_t frame, + uint8_t nr_tti_rx, + unsigned char symbol, + unsigned char first_symbol_flag, + RX_type_t rx_type, + unsigned char i_mod, + unsigned char harq_pid); + +uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) ; + +uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, + short *dlsch_llr, + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_DLSCH_t *dlsch, + NR_DL_UE_HARQ_t *harq_process, + uint32_t frame, + uint16_t nb_symb_sch, + uint8_t nr_tti_rx, + uint8_t harq_pid, + uint8_t is_crnti, + uint8_t llr8_flag); + +/**@}*/ +#endif diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c new file mode 100644 index 0000000000..b9a8ba94f1 --- /dev/null +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -0,0 +1,141 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file nr_prach_procedures.c + * \brief Implementation of gNB prach procedures from 38.213 LTE specifications + * \author R. Knopp, + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ + +#include "PHY/defs_gNB.h" +#include "PHY/phy_extern.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "nfapi_nr_interface_scf.h" +#include "fapi_nr_l1.h" +#include "nfapi_pnf.h" +#include "common/utils/LOG/log.h" +#include "common/utils/LOG/vcd_signal_dumper.h" + + +#include "assertions.h" +#include "msc.h" + +#include + +#include "intertask_interface.h" + +extern uint32_t nfapi_mode; + +extern int oai_nfapi_nr_rach_ind(nfapi_rach_indication_t *rach_ind); + + +void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { + uint16_t max_preamble[4],max_preamble_energy[4],max_preamble_delay[4]; + uint16_t i; + + + gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles=0; + + RU_t *ru; + int aa=0; + int ru_aa; + + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PRACH_RX,1); + + + + for (i=0;inum_RU;i++) { + ru=gNB->RU_list[i]; + for (ru_aa=0,aa=0;ru_aanb_rx;ru_aa++,aa++) { + gNB->prach_vars.rxsigF[aa] = gNB->RU_list[i]->prach_rxsigF[ru_aa]; + } + } + + rx_nr_prach(gNB, + frame, + subframe, + &max_preamble[0], + &max_preamble_energy[0], + &max_preamble_delay[0] + ); + + LOG_D(PHY,"[RAPROC] Frame %d, subframe %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", + frame,subframe, + max_preamble[0], + max_preamble_energy[0]/10, + max_preamble_delay[0], + gNB->prach_energy_counter); + + if ((gNB->prach_energy_counter == 100) && + (max_preamble_energy[0] > gNB->measurements.prach_I0+100)) { + + LOG_I(PHY,"[gNB %d][RAPROC] Frame %d, subframe %d Initiating RA procedure with preamble %d, energy %d.%d dB, delay %d\n", + gNB->Mod_id, + frame, + subframe, + max_preamble[0], + max_preamble_energy[0]/10, + max_preamble_energy[0]%10, + max_preamble_delay[0]); + + T(T_ENB_PHY_INITIATE_RA_PROCEDURE, T_INT(gNB->Mod_id), T_INT(frame), T_INT(subframe), + T_INT(max_preamble[0]), T_INT(max_preamble_energy[0]), T_INT(max_preamble_delay[0])); + + + gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles = 1; + gNB->UL_INFO.rach_ind.rach_indication_body.preamble_list = &gNB->preamble_list[0]; + gNB->UL_INFO.rach_ind.rach_indication_body.tl.tag = NFAPI_RACH_INDICATION_BODY_TAG; + gNB->UL_INFO.rach_ind.header.message_id = NFAPI_RACH_INDICATION; + gNB->UL_INFO.rach_ind.sfn_sf = frame<<4 | subframe; + + gNB->preamble_list[0].preamble_rel8.tl.tag = NFAPI_PREAMBLE_REL8_TAG; + gNB->preamble_list[0].preamble_rel8.timing_advance = max_preamble_delay[0]; + gNB->preamble_list[0].preamble_rel8.preamble = max_preamble[0]; + gNB->preamble_list[0].preamble_rel8.rnti = 1+subframe; // note: fid is implicitly 0 here + gNB->preamble_list[0].instance_length = 0; //don't know exactly what this is + + if (nfapi_mode == 1) { // If NFAPI PNF then we need to send the message to the VNF + + LOG_D(PHY,"Filling NFAPI indication for NR RACH : SFN_SF:%d TA %d, Preamble %d, rnti %x\n", + NFAPI_SFNSF2DEC(gNB->UL_INFO.rach_ind.sfn_sf), + gNB->preamble_list[0].preamble_rel8.timing_advance, + gNB->preamble_list[0].preamble_rel8.preamble, + gNB->preamble_list[0].preamble_rel8.rnti); + AssertFatal(1==0,"shouldn't be here yet..\n"); + //oai_nfapi_nr_rach_ind(&gNB->UL_INFO.rach_ind); + + gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles = 0; + } + } // max_preamble_energy > prach_I0 + 100 + else { + gNB->measurements.prach_I0 = ((gNB->measurements.prach_I0*900)>>10) + ((max_preamble_energy[0]*124)>>10); + if (frame==0) LOG_I(PHY,"prach_I0 = %d.%d dB\n",gNB->measurements.prach_I0/10,gNB->measurements.prach_I0%10); + if (gNB->prach_energy_counter < 100) gNB->prach_energy_counter++; + } + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PRACH_RX,0); +} diff --git a/openair1/SCHED_NR/phy_frame_config_nr.c b/openair1/SCHED_NR/phy_frame_config_nr.c new file mode 100644 index 0000000000..fa22e43661 --- /dev/null +++ b/openair1/SCHED_NR/phy_frame_config_nr.c @@ -0,0 +1,435 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*********************************************************************** +* +* FILENAME : phy_frame_configuration_nr.c +* +* DESCRIPTION : functions related to FDD/TDD configuration for NR +* see TS 38.213 11.1 Slot configuration +* and TS 38.331 for RRC configuration +* +************************************************************************/ + +#include "SCHED_NR_UE/defs.h" +#include "PHY/defs_nr_UE.h" +#include "SCHED_NR_UE/phy_frame_config_nr.h" +#include "PHY/impl_defs_nr.h" +#include "PHY/impl_defs_top.h" + +/******************************************************************* +* +* NAME : set_tdd_configuration +* +* PARAMETERS : pointer to frame configuration +* +* OUTPUT: table of uplink symbol for each slot for 2 frames +* +* RETURN : 0 if tdd has been properly configurated +* -1 tdd configuration can not be done +* +* DESCRIPTION : generate bit map for uplink symbol for each slot for several frames +* see TS 38.213 11.1 Slot configuration +* +*********************************************************************/ + +int set_tdd_config_nr( nfapi_nr_config_request_scf_t *cfg, + int mu, + int nrofDownlinkSlots, int nrofDownlinkSymbols, + int nrofUplinkSlots, int nrofUplinkSymbols) { + int slot_number = 0; + int nb_periods_per_frame; + int nb_slots_to_set = TDD_CONFIG_NB_FRAMES*(1<tdd_table.tdd_period.value) { + case 0: + nb_periods_per_frame = 20; // 10ms/0p5ms + break; + + case 1: + nb_periods_per_frame = 16; // 10ms/0p625ms + break; + + case 2: + nb_periods_per_frame = 10; // 10ms/1ms + break; + + case 3: + nb_periods_per_frame = 8; // 10ms/1p25ms + break; + + case 4: + nb_periods_per_frame = 5; // 10ms/2ms + break; + + case 5: + nb_periods_per_frame = 4; // 10ms/2p5ms + break; + + case 6: + nb_periods_per_frame = 2; // 10ms/5ms + break; + + case 7: + nb_periods_per_frame = 1; // 10ms/10ms + break; + + default: + AssertFatal(1==0,"Undefined tdd period %d\n", cfg->tdd_table.tdd_period.value); + } + + int nb_slots_per_period = ((1<tdd_table.max_tdd_periodicity_list = (nfapi_nr_max_tdd_periodicity_t *) malloc(nb_slots_to_set*sizeof(nfapi_nr_max_tdd_periodicity_t)); + + for(int memory_alloc =0 ; memory_alloctdd_table.max_tdd_periodicity_list[memory_alloc].max_num_of_symbol_per_slot_list = (nfapi_nr_max_num_of_symbol_per_slot_t *) malloc(NR_NUMBER_OF_SYMBOLS_PER_SLOT*sizeof( + nfapi_nr_max_num_of_symbol_per_slot_t)); + + while(slot_number != nb_slots_to_set) { + if(nrofDownlinkSlots != 0) { + for (int number_of_symbol = 0; number_of_symbol < nrofDownlinkSlots*NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol%NR_NUMBER_OF_SYMBOLS_PER_SLOT].slot_config.value= 0; + + if((number_of_symbol+1)%NR_NUMBER_OF_SYMBOLS_PER_SLOT == 0) + slot_number++; + } + } + + if (nrofDownlinkSymbols != 0 || nrofUplinkSymbols != 0) { + for(int number_of_symbol =0; number_of_symbol < nrofDownlinkSymbols; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value= 0; + } + + for(int number_of_symbol = nrofDownlinkSymbols; number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT-nrofUplinkSymbols; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value= 2; + } + + for(int number_of_symbol = NR_NUMBER_OF_SYMBOLS_PER_SLOT-nrofUplinkSymbols; number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value= 1; + } + + slot_number++; + } + + if(nrofUplinkSlots != 0) { + for (int number_of_symbol = 0; number_of_symbol < nrofUplinkSlots*NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol%NR_NUMBER_OF_SYMBOLS_PER_SLOT].slot_config.value= 1; + + if((number_of_symbol+1)%NR_NUMBER_OF_SYMBOLS_PER_SLOT == 0) + slot_number++; + } + } + } + + /* + while(slot_number != nb_slots_to_set) { + for (int number_of_slot = 0; number_of_slot < nrofDownlinkSlots; number_of_slot++) { + frame_parms->tdd_uplink_nr[slot_number] = NR_TDD_DOWNLINK_SLOT; + printf("slot %d set as downlink\n",slot_number); + slot_number++; + } + + if (nrofDownlinkSymbols != 0 || nrofUplinkSymbols != 0) { + frame_parms->tdd_uplink_nr[slot_number] = (1<tdd_uplink_nr[slot_number] = NR_TDD_UPLINK_SLOT; + printf("slot %d set as uplink\n",slot_number); + slot_number++; + } + + if (p_tdd_ul_dl_configuration->nrofUplinkSymbols != 0) { + LOG_E(PHY,"set_tdd_configuration_nr: uplink symbol for slot is not supported for tdd configuration \n"); + return (-1); + } + } + + if (frame_parms->p_tdd_UL_DL_ConfigurationCommon2 != NULL) { + LOG_E(PHY,"set_tdd_configuration_nr: additionnal tdd configuration 2 is not supported for tdd configuration \n"); + return (-1); + }*/ + return (0); +} + +/******************************************************************* +* +* NAME : add_tdd_dedicated_configuration_nr +* +* PARAMETERS : pointer to frame configuration +* +* OUTPUT: table of uplink symbol for each slot for several frames +* +* RETURN : 0 if tdd has been properly configurated +* -1 tdd configuration can not be done +* +* DESCRIPTION : generate bit map for uplink symbol for each slot for several frames +* see TS 38.213 11.1 Slot configuration +* +*********************************************************************/ + +void add_tdd_dedicated_configuration_nr(NR_DL_FRAME_PARMS *frame_parms, int slotIndex, int nrofDownlinkSymbols, int nrofUplinkSymbols) { + TDD_UL_DL_SlotConfig_t *p_TDD_UL_DL_ConfigDedicated = frame_parms->p_TDD_UL_DL_ConfigDedicated; + TDD_UL_DL_SlotConfig_t *p_previous_TDD_UL_DL_ConfigDedicated; + int next = 0; + + while (p_TDD_UL_DL_ConfigDedicated != NULL) { + p_previous_TDD_UL_DL_ConfigDedicated = p_TDD_UL_DL_ConfigDedicated; + p_TDD_UL_DL_ConfigDedicated = (TDD_UL_DL_SlotConfig_t *)(p_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig); + next = 1; + } + + p_TDD_UL_DL_ConfigDedicated = calloc( 1, sizeof(TDD_UL_DL_SlotConfig_t)); + + //printf("allocate pt %p \n", p_TDD_UL_DL_ConfigDedicated); + if (p_TDD_UL_DL_ConfigDedicated == NULL) { + printf("Error test_frame_configuration: memory allocation problem \n"); + assert(0); + } + + if (next == 0) { + frame_parms->p_TDD_UL_DL_ConfigDedicated = p_TDD_UL_DL_ConfigDedicated; + } else { + p_previous_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig = (struct TDD_UL_DL_SlotConfig_t *)p_TDD_UL_DL_ConfigDedicated; + } + + p_TDD_UL_DL_ConfigDedicated->slotIndex = slotIndex; + p_TDD_UL_DL_ConfigDedicated->nrofDownlinkSymbols = nrofDownlinkSymbols; + p_TDD_UL_DL_ConfigDedicated->nrofUplinkSymbols = nrofUplinkSymbols; +} + +/******************************************************************* +* +* NAME : set_tdd_configuration_dedicated_nr +* +* PARAMETERS : pointer to frame configuration +* +* OUTPUT: table of uplink symbol for each slot for several frames +* +* RETURN : 0 if tdd has been properly configurated +* -1 tdd configuration can not be done +* +* DESCRIPTION : generate bit map for uplink symbol for each slot for several frames +* see TS 38.213 11.1 Slot configuration +* +*********************************************************************/ + +int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms) { + TDD_UL_DL_SlotConfig_t *p_current_TDD_UL_DL_SlotConfig; + p_current_TDD_UL_DL_SlotConfig = frame_parms->p_TDD_UL_DL_ConfigDedicated; + NR_TST_PHY_PRINTF("\nSet tdd dedicated configuration\n "); + + while(p_current_TDD_UL_DL_SlotConfig != NULL) { + int slot_index = p_current_TDD_UL_DL_SlotConfig->slotIndex; + + if (slot_index < TDD_CONFIG_NB_FRAMES*(frame_parms->ttis_per_subframe * NR_NUMBER_OF_SUBFRAMES_PER_FRAME)) { + if (p_current_TDD_UL_DL_SlotConfig->nrofDownlinkSymbols != 0) { + if (p_current_TDD_UL_DL_SlotConfig->nrofDownlinkSymbols == NR_TDD_SET_ALL_SYMBOLS) { + if (p_current_TDD_UL_DL_SlotConfig->nrofUplinkSymbols == 0) { + frame_parms->tdd_uplink_nr[slot_index] = NR_TDD_DOWNLINK_SLOT; + NR_TST_PHY_PRINTF(" DL[%d] ", slot_index); + } else { + LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd downlink & uplink symbol configuration is not supported \n"); + return (-1); + } + } else { + LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd downlink symbol configuration is not supported \n"); + return (-1); + } + } else if (p_current_TDD_UL_DL_SlotConfig->nrofUplinkSymbols != 0) { + if (p_current_TDD_UL_DL_SlotConfig->nrofUplinkSymbols == NR_TDD_SET_ALL_SYMBOLS) { + frame_parms->tdd_uplink_nr[slot_index] = NR_TDD_UPLINK_SLOT; + NR_TST_PHY_PRINTF(" UL[%d] ", slot_index); + } else { + LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd uplink symbol configuration is not supported \n"); + return (-1); + } + } else { + LOG_E(PHY,"set_tdd_configuration_dedicated_nr: no tdd symbol configuration is specified \n"); + return (-1); + } + } else { + LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd slot index exceeds maximum value \n"); + return (-1); + } + + p_current_TDD_UL_DL_SlotConfig = (TDD_UL_DL_SlotConfig_t *)(p_current_TDD_UL_DL_SlotConfig->p_next_TDD_UL_DL_SlotConfig); + } + + NR_TST_PHY_PRINTF("\n"); + return (0); +} + +/******************************************************************* +* +* NAME : set_tdd_configuration +* +* PARAMETERS : pointer to tdd common configuration +* pointer to tdd common configuration2 +* pointer to tdd dedicated configuration +* +* OUTPUT: table of uplink symbol for each slot for 2 frames +* +* RETURN : 0 if srs sequence has been successfully generated +* -1 if sequence can not be properly generated +* +* DESCRIPTION : generate bit map for uplink symbol for each slot for 2 frames +* see TS 38.213 11.1 Slot configuration +* +*********************************************************************/ + +int nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti) { + /* for FFD all slot can be considered as an uplink */ + int mu = cfg->ssb_config.scs_common.value,check_slot=0; + + if (cfg->cell_config.frame_duplex_type.value == FDD) { + return (NR_UPLINK_SLOT | NR_DOWNLINK_SLOT ); + } + + if (nr_frame%2 == 0) { + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config.value==1) { + check_slot++; + } + } + + if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { + return (NR_UPLINK_SLOT); + } + + check_slot = 0; + + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config.value==0) { + check_slot++; + } + } + + if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { + return (NR_DOWNLINK_SLOT); + } else { + return (NR_MIXED_SLOT); + } + } else { + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[((1<tdd_table.max_tdd_periodicity_list[((1<p_tdd_UL_DL_Configuration; + free_tdd_configuration_dedicated_nr(frame_parms); + + if (p_tdd_UL_DL_Configuration != NULL) { + frame_parms->p_tdd_UL_DL_Configuration = NULL; + free(p_tdd_UL_DL_Configuration); + } + + for (int number_of_slot = 0; number_of_slot < NR_MAX_SLOTS_PER_FRAME; number_of_slot++) { + frame_parms->tdd_uplink_nr[number_of_slot] = NR_TDD_DOWNLINK_SLOT; + } +} + +/******************************************************************* +* +* NAME : free_tdd_configuration_dedicated_nr +* +* PARAMETERS : pointer to frame configuration +* +* RETURN : none +* +* DESCRIPTION : free structure related to tdd dedicated configuration +* +*********************************************************************/ + +void free_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms) { + TDD_UL_DL_SlotConfig_t *p_current_TDD_UL_DL_ConfigDedicated = frame_parms->p_TDD_UL_DL_ConfigDedicated; + TDD_UL_DL_SlotConfig_t *p_next_TDD_UL_DL_ConfigDedicated; + int next = 0; + + if (p_current_TDD_UL_DL_ConfigDedicated != NULL) { + do { + if (p_current_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig != NULL) { + next = 1; + p_next_TDD_UL_DL_ConfigDedicated = (TDD_UL_DL_SlotConfig_t *)(p_current_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig); + p_current_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig = NULL; + //printf("free pt %p \n", p_current_TDD_UL_DL_ConfigDedicated); + free(p_current_TDD_UL_DL_ConfigDedicated); + p_current_TDD_UL_DL_ConfigDedicated = p_next_TDD_UL_DL_ConfigDedicated; + } else { + if (p_current_TDD_UL_DL_ConfigDedicated != NULL) { + frame_parms->p_TDD_UL_DL_ConfigDedicated = NULL; + //printf("free pt %p \n", p_current_TDD_UL_DL_ConfigDedicated); + free(p_current_TDD_UL_DL_ConfigDedicated); + next = 0; + } + } + } while (next); + } +} + diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c new file mode 100644 index 0000000000..5c00352515 --- /dev/null +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -0,0 +1,666 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +#include +#include +#include + +#include "common/config/config_userapi.h" +#include "common/utils/LOG/log.h" +#include "common/ran_context.h" + +#include "SIMULATION/TOOLS/sim.h" +#include "SIMULATION/RF/rf.h" +#include "PHY/types.h" +#include "PHY/defs_gNB.h" +#include "PHY/defs_nr_UE.h" +#include "SCHED_NR/sched_nr.h" +#include "SCHED_NR_UE/phy_frame_config_nr.h" +#include "PHY/phy_vars_nr_ue.h" + +#include "PHY/NR_REFSIG/refsig_defs_ue.h" +#include "PHY/NR_REFSIG/nr_mod_table.h" +#include "PHY/MODULATION/modulation_eNB.h" +#include "PHY/MODULATION/modulation_UE.h" +#include "PHY/INIT/phy_init.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" +#include "OCG_vars.h" + +#include + +PHY_VARS_gNB *gNB; +PHY_VARS_NR_UE *UE; +RAN_CONTEXT_t RC; +RU_t *ru; + +double cpuf; + +extern uint16_t prach_root_sequence_map0_3[838]; + +void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); + +uint16_t NB_UE_INST=1; +volatile int oai_exit=0; + +void exit_function(const char* file, const char* function, const int line,const char *s) { + const char * msg= s==NULL ? "no comment": s; + printf("Exiting at: %s:%d %s(), %s\n", file, line, function, msg); + exit(-1); +} + + +int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe) { + AssertFatal(1==0,"Shouldn't be here ...\n"); + return 0; +} + +uint8_t nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, + sub_frame_t subframe, uint8_t eNB_index, + uint8_t *ulsch_buffer, uint16_t buflen, uint8_t *access_mode) {return(0);} + +int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);} + +openair0_config_t openair0_cfg[MAX_CARDS]; +uint8_t nfapi_mode=0; +NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);} +int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } + +uint64_t get_softmodem_optmask(void) { + return 0; +} + +int main(int argc, char **argv) +{ + + char c; + + int i,aa,aarx; + double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0,ue_speed0=0.0,ue_speed1=0.0; + uint8_t snr1set=0; + uint8_t ue_speed1set=0; + int **txdata; + double **s_re,**s_im,**r_re,**r_im; + double iqim=0.0; + int trial; //, ntrials=1; + uint8_t transmission_mode = 1,n_tx=1,n_rx=1; + uint16_t Nid_cell=0; + + uint8_t awgn_flag=0; + uint8_t hs_flag=0; + int n_frames=1; + channel_desc_t *UE2gNB; + uint32_t nsymb,tx_lev; //,tx_lev_dB; + // int8_t interf1=-19,interf2=-19; + NR_DL_FRAME_PARMS *frame_parms; + + SCM_t channel_model=Rayleigh1; + + // uint8_t abstraction_flag=0,calibration_flag=0; + // double prach_sinr; + int N_RB_UL=273; + uint32_t prach_errors=0; + uint8_t subframe=9; + uint16_t preamble_energy_list[64],preamble_tx=50,preamble_delay_list[64]; + uint16_t preamble_max,preamble_energy_max; + PRACH_RESOURCES_t prach_resources; + //uint8_t prach_fmt; + //int N_ZC; + int delay = 0; + double delay_avg=0; + double ue_speed = 0; + int NCS_config = 13,rootSequenceIndex=0; + int threequarter_fs = 0; + int mu=1; + uint64_t SSB_positions=0x01; + + int loglvl=OAILOG_INFO; + + cpuf = get_cpu_freq_GHz(); + + + if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) { + exit_fun("[SOFTMODEM] Error, configuration module init failed\n"); + } + + randominit(0); + + + while ((c = getopt (argc, argv, "hHaA:Cr:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) { + switch (c) { + case 'a': + printf("Running AWGN simulation\n"); + awgn_flag = 1; + /* ntrials not used later, no need to set */ + //ntrials=1; + break; + + case 'd': + delay = atoi(optarg); + break; + + case 'g': + switch((char)*optarg) { + case 'A': + channel_model=SCM_A; + break; + + case 'B': + channel_model=SCM_B; + break; + + case 'C': + channel_model=SCM_C; + break; + + case 'D': + channel_model=SCM_D; + break; + + case 'E': + channel_model=EPA; + break; + + case 'F': + channel_model=EVA; + break; + + case 'G': + channel_model=ETU; + break; + + case 'H': + channel_model=Rayleigh8; + + case 'I': + channel_model=Rayleigh1; + + case 'J': + channel_model=Rayleigh1_corr; + + case 'K': + channel_model=Rayleigh1_anticorr; + + case 'L': + channel_model=Rice8; + + case 'M': + channel_model=Rice1; + + case 'N': + channel_model=Rayleigh1_800; + break; + + default: + msg("Unsupported channel model!\n"); + exit(-1); + } + + break; + + case 'E': + threequarter_fs=1; + break; + + case 'n': + n_frames = atoi(optarg); + break; + + case 's': + snr0 = atof(optarg); + msg("Setting SNR0 to %f\n",snr0); + break; + + case 'S': + snr1 = atof(optarg); + snr1set=1; + msg("Setting SNR1 to %f\n",snr1); + break; + + case 'p': + preamble_tx=atoi(optarg); + break; + + case 'v': + ue_speed0 = atoi(optarg); + break; + + case 'V': + ue_speed1 = atoi(optarg); + ue_speed1set = 1; + break; + + case 'Z': + NCS_config = atoi(optarg); + + if ((NCS_config > 15) || (NCS_config < 0)) + printf("Illegal NCS_config %d, (should be 0-15)\n",NCS_config); + + break; + + case 'H': + printf("High-Speed Flag enabled\n"); + hs_flag = 1; + break; + + case 'L': + rootSequenceIndex = atoi(optarg); + + if ((rootSequenceIndex < 0) || (rootSequenceIndex > 837)) + printf("Illegal rootSequenceNumber %d, (should be 0-837)\n",rootSequenceIndex); + + break; + + case 'x': + transmission_mode=atoi(optarg); + + if ((transmission_mode!=1) && + (transmission_mode!=2) && + (transmission_mode!=6)) { + msg("Unsupported transmission mode %d\n",transmission_mode); + exit(-1); + } + + break; + + case 'y': + n_tx=atoi(optarg); + + if ((n_tx==0) || (n_tx>2)) { + msg("Unsupported number of tx antennas %d\n",n_tx); + exit(-1); + } + + break; + + case 'z': + n_rx=atoi(optarg); + + if ((n_rx==0) || (n_rx>2)) { + msg("Unsupported number of rx antennas %d\n",n_rx); + exit(-1); + } + + break; + + case 'N': + Nid_cell = atoi(optarg); + break; + + case 'R': + N_RB_UL = atoi(optarg); + break; + + case 'F': + break; + + default: + case 'h': + printf("%s -h(elp) -a(wgn on) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", + argv[0]); + printf("-h This message\n"); + printf("-a Use AWGN channel and not multipath\n"); + printf("-n Number of frames to simulate\n"); + printf("-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated\n"); + printf("-S Ending SNR, runs from SNR0 to SNR1\n"); + printf("-g [A,B,C,D,E,F,G,I,N] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) or Rayleigh1 (I) or Rayleigh1_800 (N) models (ignores delay spread and Ricean factor)\n"); + printf("-z Number of RX antennas used in gNB\n"); + printf("-N Nid_cell\n"); + printf("-O oversampling factor (1,2,4,8,16)\n"); + // printf("-f PRACH format (0=1,1=2,2=3,3=4)\n"); + printf("-d Channel delay \n"); + printf("-v Starting UE velocity in km/h, runs from 'v' to 'v+50km/h'. If n_frames is 1 just 'v' is simulated \n"); + printf("-V Ending UE velocity in km/h, runs from 'v' to 'V'"); + printf("-L rootSequenceIndex (0-837)\n"); + printf("-Z NCS_config (ZeroCorrelationZone) (0-15)\n"); + printf("-H Run with High-Speed Flag enabled \n"); + printf("-R Number of PRB (6,15,25,50,75,100)\n"); + printf("-F Input filename (.txt format) for RX conformance testing\n"); + exit (-1); + break; + } + } + + logInit(); + + set_glog(loglvl); + T_stdout = 1; + + SET_LOG_DEBUG(PRACH); + + if (snr1set==0) { + if (n_frames==1) + snr1 = snr0+.1; + else + snr1 = snr0+5.0; + } + + RC.gNB = (PHY_VARS_gNB**) malloc(2*sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); + memset(RC.gNB[0],0,sizeof(PHY_VARS_gNB)); + + RC.ru = (RU_t**) malloc(2*sizeof(RU_t *)); + RC.ru[0] = (RU_t*) malloc(sizeof(RU_t )); + memset(RC.ru[0],0,sizeof(RU_t)); + RC.nb_RU = 1; + + gNB = RC.gNB[0]; + ru = RC.ru[0]; + + + if (ue_speed1set==0) { + if (n_frames==1) + ue_speed1 = ue_speed0+10; + else + ue_speed1 = ue_speed0+50; + } + + printf("SNR0 %f, SNR1 %f\n",snr0,snr1); + + frame_parms = &gNB->frame_parms; + + + + s_re = malloc(2*sizeof(double*)); + s_im = malloc(2*sizeof(double*)); + r_re = malloc(2*sizeof(double*)); + r_im = malloc(2*sizeof(double*)); + + frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) + frame_parms->nb_antennas_tx = n_tx; + frame_parms->nb_antennas_rx = n_rx; + frame_parms->N_RB_DL = N_RB_UL; + frame_parms->N_RB_UL = N_RB_UL; + frame_parms->threequarter_fs = threequarter_fs; + + + nr_phy_config_request_sim(gNB,N_RB_UL,N_RB_UL,mu,Nid_cell,SSB_positions); + + frame_parms->frame_type = TDD; + frame_parms->freq_range = nr_FR1; + + nsymb = (frame_parms->Ncp == 0) ? 14 : 12; + + printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d,Frame type %s, Frequency Range %s\n",NUMBER_OF_OFDM_CARRIERS, + frame_parms->Ncp,frame_parms->samples_per_subframe,frame_parms->frame_type == FDD ? "FDD" : "TDD", frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2"); + + ru->nr_frame_parms=frame_parms; + ru->if_south = LOCAL_RF; + ru->nb_tx = n_tx; + ru->nb_rx = n_rx; + + RC.nb_nr_L1_inst=1; + phy_init_nr_gNB(gNB,0,0); + nr_phy_init_RU(ru); + set_tdd_config_nr(&gNB->gNB_config, 5000, + 7, 6, + 2, 4); + + //configure UE + UE = malloc(sizeof(PHY_VARS_NR_UE)); + memset((void*)UE,0,sizeof(PHY_VARS_NR_UE)); + PHY_vars_UE_g = malloc(2*sizeof(PHY_VARS_NR_UE**)); + PHY_vars_UE_g[0] = malloc(2*sizeof(PHY_VARS_NR_UE*)); + PHY_vars_UE_g[0][0] = UE; + memcpy(&UE->frame_parms,frame_parms,sizeof(NR_DL_FRAME_PARMS)); + if (init_nr_ue_signal(UE, 1, 0) != 0) + { + printf("Error at UE NR initialisation\n"); + exit(-1); + } + + txdata = UE->common_vars.txdata; + printf("txdata %p\n",&txdata[0][subframe*frame_parms->samples_per_subframe]); + + double fs,bw; + + + bw = N_RB_UL*(180e3)*(1<frame_parms.numerology_index); + AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n",gNB->frame_parms.numerology_index,N_RB_UL); + if (bw <= 30.72e6) fs = 30.72e6; + else if (bw <= 61.44e6) fs = 61.44e6; + else if (bw <= 122.88e6) fs = 122.88e6; + LOG_I(PHY,"Running with bandwidth %f Hz, fs %f samp/s, FRAME_LENGTH_COMPLEX_SAMPLES %d\n",bw,fs,FRAME_LENGTH_COMPLEX_SAMPLES); + + + UE2gNB = new_channel_desc_scm(UE->frame_parms.nb_antennas_tx, + gNB->frame_parms.nb_antennas_rx, + channel_model, + fs, + bw, + 0.0, + delay, + 0); + + if (UE2gNB==NULL) { + printf("Problem generating channel model. Exiting.\n"); + exit(-1); + } + + for (i=0; i<2; i++) { + + s_re[i] = malloc(FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + bzero(s_re[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + s_im[i] = malloc(FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + bzero(s_im[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + + r_re[i] = malloc(FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + bzero(r_re[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + r_im[i] = malloc(FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + bzero(r_im[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); + } + + UE->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex; + UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98; + UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config; + UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag; + UE->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0; + UE->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0; + + + gNB->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex; + gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98; + gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config; + gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag; + gNB->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0; + gNB->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0; + + gNB->proc.slot_rx = subframe<<1; + + gNB->common_vars.rxdata = ru->common.rxdata; + + + compute_nr_prach_seq(gNB->frame_parms.prach_config_common.rootSequenceIndex, + gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, + gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, + gNB->frame_parms.frame_type, + gNB->frame_parms.freq_range, + gNB->X_u); + + compute_nr_prach_seq(UE->frame_parms.prach_config_common.rootSequenceIndex, + UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, + UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, + UE->frame_parms.frame_type, + UE->frame_parms.freq_range, + UE->X_u); + + + + UE->prach_vars[0]->amp = AMP; + + UE->prach_resources[0] = &prach_resources; + + if (preamble_tx == 99) + preamble_tx = (uint16_t)(taus()&0x3f); + + if (n_frames == 1) + printf("raPreamble %d\n",preamble_tx); + + UE->prach_resources[0]->ra_PreambleIndex = preamble_tx; + UE->prach_resources[0]->ra_TDD_map_index = 0; + + /*tx_lev = generate_nr_prach(UE, + 0, //gNB_id, + subframe, + 0); //Nf */ //commented for testing purpose + + UE_nr_rxtx_proc_t proc={0}; + nr_ue_prach_procedures(UE,&proc,0,0,0); + + + /* tx_lev_dB not used later, no need to set */ + //tx_lev_dB = (unsigned int) dB_fixed(tx_lev); + + LOG_M("txsig0.m","txs0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1); + //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); + + // multipath channel + dump_nr_prach_config(&gNB->frame_parms,subframe); + + for (i=0; i<2*frame_parms->samples_per_subframe; i++) { + for (aa=0; aa<1; aa++) { + if (awgn_flag == 0) { + s_re[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); + s_im[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + } else { + for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { + if (aa==0) { + r_re[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); + r_im[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + } else { + r_re[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); + r_im[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + } + } + } + } + } + + + + for (SNR=snr0; SNRmax_Doppler = 1.9076e9*(ue_speed/3.6)/3e8; + printf("n_frames %d SNR %f\n",n_frames,SNR); + prach_errors=0; + + for (trial=0; trialsamples_per_subframe,0); + } + + if (n_frames==1) { + printf("rx_level data symbol %f, tx_lev %f\n", + 10*log10(signal_energy_fp(r_re,r_im,1,OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES,0)), + 10*log10(tx_lev)); + } + + for (i=0; isamples_per_subframe; i++) { + for (aa=0; aaframe_parms.nb_antennas_rx; aa++) { + + ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + } + } + uint16_t preamble_rx; + rx_nr_prach_ru(ru, + 0, + subframe); + gNB->prach_vars.rxsigF = ru->prach_rxsigF; + + rx_nr_prach(gNB, + 0, + subframe, + &preamble_rx, + preamble_energy_list, + preamble_delay_list); + + if (preamble_rx!=preamble_tx) + prach_errors++; + else { + delay_avg += (double)preamble_delay_list[preamble_tx]; + } + + if (n_frames==1) { + printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy_list[0],preamble_delay_list[0]); + + + LOG_M("prach0.m","prach0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1); + LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0],24576,1,1); + LOG_M("rxsig0.m","rxs0", + &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe], + frame_parms->samples_per_subframe,1,1); + LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0],839*4,1,1); + LOG_M("prach_preamble.m","prachp",&gNB->X_u[0],839,1,1); + } + } + + printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); + //printf("(%f,%f)\n",ue_speed,(double)prach_errors/(double)n_frames); + } // UE Speed loop + + //printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); + // printf("(%f,%f)\n",SNR,(double)prach_errors/(double)n_frames); + } //SNR loop + + + for (i=0; i<2; i++) { + free(s_re[i]); + free(s_im[i]); + free(r_re[i]); + free(r_im[i]); + } + + free(s_re); + free(s_im); + free(r_re); + free(r_im); + + + return(0); + +} + + + +/* + for (i=1;i<4;i++) + memcpy((void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[i*12*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*2], + (void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[0], + 12*OFDM_SYMBOL_SIZE_SAMPLES_NO_PREFIX*2); +*/ + diff --git a/openair1/SIMULATION/NR_PHY/reconfig.raw b/openair1/SIMULATION/NR_PHY/reconfig.raw new file mode 100644 index 0000000000000000000000000000000000000000..59b524fbbaf41e4dc0b6aadc51b902d781116b4f GIT binary patch literal 479 zcmZvXF=!J}0EYi}?{ax>G}d=0UjAmZpy?1wqoHAVn}JNC$_P8qbu9h~QQvv??8KmoBX}?rz_=eIN7J#-PoS@HD3gnT`rmkaW1L9b8B?Mc0ne|h3^N(7BY zkP@+@RKe`|t^_2=CenhQlDGdi+gL2$Fw8!dQThmaiH(evzVb!P-*X1W9)9lhkUf^; z20=B-ME#a`pV0@h4Pxxn7&vej-Hd3{I=uJ-oCGOpCub5y=MJ&%cJ!xG{}6E~8qqW& rpj~8=u$iJp4Z4NQY1mv*vm;f7lV$hZ_N)ErU6YQ&DfG?JT}%B1IwqM- literal 0 HcmV?d00001 diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c new file mode 100644 index 0000000000..396e06ff09 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -0,0 +1,183 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/* \file nr_ue_dci_configuration.c + * \brief functions for generating dci search procedures based on RRC Serving Cell Group Configuration + * \author R. Knopp + * \date 2020 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ + +#include "mac_proto.h" +#include "mac_defs.h" +#include "assertions.h" +#include "LAYER2/NR_MAC_UE/mac_extern.h" +#include "mac_defs.h" +#include + +#ifdef NR_PDCCH_DCI_TOOLS_DEBUG +#define LOG_DCI_D(a...) printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) ->" a) +#else +#define LOG_DCI_D(a...) +#endif +#define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a) + + +void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) { + + LOG_D(MAC,"Filling search candidates for DCI\n"); + + rel15->number_of_candidates=3; + rel15->CCE[0]=0; + rel15->L[0]=4; + rel15->CCE[1]=4; + rel15->L[1]=4; + rel15->CCE[2]=8; + rel15->L[2]=4; + +} + +void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) { + + // check if DL slot + if (is_nr_DL_slot(mac->scc,slot)==1) { + + // get BWP 1, Coreset 0, SearchSpace 0 + if (mac->DLbwp[0]==NULL) { + AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); + AssertFatal(mac->scd->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n", + mac->scd->downlinkBWP_ToAddModList->list.count); + mac->DLbwp[0] = mac->scd->downlinkBWP_ToAddModList->list.array[0]; + AssertFatal(mac->DLbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); + AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config!=NULL,"pdcch_Config is null\n"); + AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL,"controlResourceSetToAddModList is null\n"); + AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count==1,"controlResourceSetToAddModList->list.count=%d\n", + mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count); + mac->coreset[0][0] = mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; + AssertFatal(mac->coreset[0][0]!=NULL,"coreset[0][0] is null\n"); + + AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + NR_SearchSpace_t *ss; + int ss_id=0; + AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.countDLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count); + for (int i=0;iDLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + AssertFatal(*ss->controlResourceSetId == mac->coreset[0][0]->controlResourceSetId,"ss->controlResourceSetId is unknown\n"); + mac->SSpace[0][0][ss_id] = ss; + ss_id++; + } + } + if (mac->ULbwp[0]==NULL) { + AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList!=NULL,"uplinkBWP_ToAddModList is null\n"); + AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count==1,"uplinkBWP_ToAddModList->list->count is %d\n", + mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count); + mac->ULbwp[0] = mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; + AssertFatal(mac->ULbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); + } + // check search spaces + + int ss_id=0; + fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; + int sps =mac->DLbwp[0]->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + + while(mac->SSpace[0][0][ss_id]!=NULL && + ss_id < mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count) { + + AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); + + ss_id++; + } + if (mac->ra_state == WAIT_RAR) { + // check for RAR + rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); + dl_config->number_pdus = dl_config->number_pdus + 1; + } + else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) { + rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + rel15->rnti = mac->t_crnti; + dl_config->number_pdus = dl_config->number_pdus + 1; + } + if (mac->crnti>0) { + rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + rel15->rnti = mac->crnti; + rel15->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + rel15->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + rel15->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; + // get UE-specific search space + for (ss_id=0;ss_idSSpace[0][0][ss_id]!=NULL;ss_id++) + if (mac->SSpace[0][0][ss_id]->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) break; + AssertFatal(ss_idSSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | + (mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + + for (int i=0; i>(sps-1-i))&1) { + rel15->coreset.StartSymbolIndex=i; + break; + } + rel15->coreset.duration = mac->coreset[0][0]->duration; + for (int i=0;i<6;i++) + rel15->coreset.frequency_domain_resource[i] = mac->coreset[0][0]->frequencyDomainResources.buf[i]; + + rel15->coreset.CceRegMappingType = mac->coreset[0][0]->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? + FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; + if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) { + rel15->coreset.RegBundleSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize); + rel15->coreset.InterleaverSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize); + AssertFatal(mac->scc->physCellId != NULL,"mac->scc->physCellId is null\n"); + rel15->coreset.ShiftIndex = mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex : *mac->scc->physCellId; + } + else { + rel15->coreset.RegBundleSize = 0; + rel15->coreset.InterleaverSize = 0; + rel15->coreset.ShiftIndex = 0; + } + rel15->coreset.CoreSetType = 1; + rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; + if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) + rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; + else + rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; + fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); + rel15->dci_format = NR_DL_DCI_FORMAT_1_0; + rel15->dci_length = nr_dci_size(rel15->dci_format,NR_RNTI_C,rel15->BWPSize); + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; + dl_config->number_pdus = dl_config->number_pdus + 1; + } + } +} + + + + diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c new file mode 100644 index 0000000000..e4e3ac05df --- /dev/null +++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c @@ -0,0 +1,153 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/* file: nr_compute_tbs.c + purpose: Compute NR TBS + author: Hongzhi WANG (TCL) +*/ +#define INDEX_MAX_TBS_TABLE (93) + +#include "common/utils/nr/nr_common.h" +#include + +//Table 5.1.2.2-2 +uint16_t Tbstable_nr[INDEX_MAX_TBS_TABLE] = {24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,208,224,240,256,272,288,304,320,336,352,368,384,408,432,456,480,504,528,552,576,608,640,672,704,736,768,808,848,888,928,984,1032,1064,1128,1160,1192,1224,1256,1288,1320,1352,1416,1480,1544,1608,1672,1736,1800,1864,1928,2024,2088,2152,2216,2280,2408,2472,2536,2600,2664,2728,2792,2856,2976,3104,3240,3368,3496,3624,3752,3824}; + +uint16_t NPRB_LBRM[7] = {32,66,107,135,162,217,273}; + +uint32_t nr_compute_tbs(uint16_t Qm, + uint16_t R, + uint16_t nb_rb, + uint16_t nb_symb_sch, + uint16_t nb_dmrs_prb, + uint16_t nb_rb_oh, + uint8_t Nl) +{ + + uint16_t nbp_re, nb_re; + uint32_t nr_tbs=0; + uint32_t Ninfo, Np_info, C; + uint8_t n, scale; + + nbp_re = 12 * nb_symb_sch - nb_dmrs_prb - nb_rb_oh; + + nb_re = min(156, nbp_re) * nb_rb; + + scale = (R>1024)?11:10; + + // Intermediate number of information bits + Ninfo = (nb_re * R * Qm * Nl)>>scale; + + if (Ninfo <=3824) { + n = max(3, floor(log2(Ninfo)) - 6); + Np_info = max(24, (Ninfo>>n)<= Np_info){ + nr_tbs = Tbstable_nr[i]; + break; + } + } + } + else { + n = log2(Ninfo-24)-5; + Np_info = max(3840, (ROUNDIDIV((Ninfo-24),(1< 8424){ + C = CEILIDIV((Np_info+24),8424); + nr_tbs = (C<<3)*CEILIDIV((Np_info+24),(C<<3)) - 24; + } + else { + nr_tbs = ((CEILIDIV((Np_info+24),8))<<3) - 24; + } + + } + + } + //printf("Ninfo %d nbp_re %d nb_re %d Qm %d, R %d, tbs %d\n", Ninfo, nbp_re, nb_re, Qm, R, nr_tbs); + return nr_tbs; +} + + +//tbslbrm calculation according to 5.4.2.1 of 38.212 +uint32_t nr_compute_tbslbrm(uint16_t table, + uint16_t nb_rb, + uint8_t Nl, + uint8_t C) +{ + + uint16_t R, nb_re; + uint16_t nb_rb_lbrm=0; + uint8_t Qm; + int i; + uint32_t nr_tbs=0; + uint32_t Ninfo, Np_info; + uint8_t n; + + for (i=0; i<7; i++) { + if (NPRB_LBRM[i] >= nb_rb){ + nb_rb_lbrm = NPRB_LBRM[i]; + break; + } + } + + Qm = ((table == 1)? 8 : 6); + R = 948; + nb_re = 156 * nb_rb_lbrm; + + // Intermediate number of information bits + Ninfo = (nb_re * R * Qm * Nl)>>10; + + if (Ninfo <=3824) { + n = max(3, floor(log2(Ninfo)) - 6); + Np_info = max(24, (Ninfo>>n)<= Np_info){ + nr_tbs = Tbstable_nr[i]; + break; + } + } + } + else { + n = log2(Ninfo-24)-5; + Np_info = max(3840, (ROUNDIDIV((Ninfo-24),(1< 8424){ + nr_tbs = (C<<3)*CEILIDIV((Np_info+24),(C<<3)) - 24; + } + else { + nr_tbs = ((CEILIDIV((Np_info+24),8))<<3) - 24; + } + + } + + } + return nr_tbs; + +} diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h new file mode 100644 index 0000000000..6b043963b0 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h @@ -0,0 +1,70 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file mac.h +* \brief MAC data structures, constant, and function prototype +* \author Navid Nikaein and Raymond Knopp, WIE-TAI CHEN +* \date Dec. 2019 +* \version 0.1 +* \company Eurecom +* \email raymond.knopp@eurecom.fr + +*/ + +#ifndef __LAYER2_NR_MAC_COMMON_H__ +#define __LAYER2_NR_MAC_COMMON_H__ + +uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); + +uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); + +uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); + +int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols); + +typedef enum { + NR_DL_DCI_FORMAT_1_0 = 0, + NR_DL_DCI_FORMAT_1_1, + NR_DL_DCI_FORMAT_2_0, + NR_DL_DCI_FORMAT_2_1, + NR_DL_DCI_FORMAT_2_2, + NR_DL_DCI_FORMAT_2_3, + NR_UL_DCI_FORMAT_0_0, + NR_UL_DCI_FORMAT_0_1 +} nr_dci_format_t; + +typedef enum { + NR_RNTI_new = 0, + NR_RNTI_C, + NR_RNTI_RA, + NR_RNTI_P, + NR_RNTI_CS, + NR_RNTI_TC, + NR_RNTI_SP_CSI, + NR_RNTI_SI, + NR_RNTI_SFI, + NR_RNTI_INT, + NR_RNTI_TPC_PUSCH, + NR_RNTI_TPC_PUCCH, + NR_RNTI_TPC_SRS +} nr_rnti_type_t; + +#endif diff --git a/openair2/RRC/LTE/rrc_eNB_endc.c b/openair2/RRC/LTE/rrc_eNB_endc.c new file mode 100644 index 0000000000..3d3d9787b5 --- /dev/null +++ b/openair2/RRC/LTE/rrc_eNB_endc.c @@ -0,0 +1,243 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +#include "rrc_defs.h" +#include "rrc_extern.h" +#include "rrc_eNB_UE_context.h" +#include "common/ran_context.h" +#include "LTE_DL-DCCH-Message.h" + +#include +#include +#include +#include +#include +#include + +extern RAN_CONTEXT_t RC; +extern mui_t rrc_eNB_mui; + +int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, + rrc_eNB_ue_context_t *ue_context, + unsigned char *buffer, + int buffer_size, + OCTET_STRING_t *scg_group_config, + OCTET_STRING_t *scg_RB_config) +{ + asn_enc_rval_t enc_rval; + LTE_DL_DCCH_Message_t dl_dcch_msg; + LTE_RRCConnectionReconfiguration_t *r; + int trans_id; + LTE_RadioResourceConfigDedicated_t rrcd; +#if 0 + LTE_DRB_ToAddModList_t drb_list; + struct LTE_DRB_ToAddMod drb; + long eps_bearer_id; + struct LTE_RLC_Config rlc; + long lcid; + struct LTE_LogicalChannelConfig lc; +#endif + LTE_DRB_ToReleaseList_t drb_list; + LTE_DRB_Identity_t drb; + struct LTE_LogicalChannelConfig__ul_SpecificParameters ul_params; + long lcg; + struct LTE_RadioResourceConfigDedicated__mac_MainConfig mac; + struct LTE_MAC_MainConfig__ext4 mac_ext4; + struct LTE_MAC_MainConfig__ext4__dualConnectivityPHR dc_phr; + + memset(&rrcd, 0, sizeof(rrcd)); + memset(&drb_list, 0, sizeof(drb_list)); + memset(&drb, 0, sizeof(drb)); +#if 0 + memset(&rlc, 0, sizeof(rlc)); + memset(&lc, 0, sizeof(lc)); +#endif + memset(&ul_params, 0, sizeof(ul_params)); + memset(&mac, 0, sizeof(mac)); + memset(&mac_ext4, 0, sizeof(mac_ext4)); + memset(&dc_phr, 0, sizeof(dc_phr)); + + trans_id = rrc_eNB_get_next_transaction_identifier(ctxt->module_id); + + memset(&dl_dcch_msg,0,sizeof(LTE_DL_DCCH_Message_t)); + + dl_dcch_msg.message.present = LTE_DL_DCCH_MessageType_PR_c1; + dl_dcch_msg.message.choice.c1.present = LTE_DL_DCCH_MessageType__c1_PR_rrcConnectionReconfiguration; + + r = &dl_dcch_msg.message.choice.c1.choice.rrcConnectionReconfiguration; + + r->rrc_TransactionIdentifier = trans_id; + r->criticalExtensions.present = LTE_RRCConnectionReconfiguration__criticalExtensions_PR_c1; + r->criticalExtensions.choice.c1.present = LTE_RRCConnectionReconfiguration__criticalExtensions__c1_PR_rrcConnectionReconfiguration_r8; + r->criticalExtensions.choice.c1.choice.rrcConnectionReconfiguration_r8.radioResourceConfigDedicated = &rrcd; + +#if 0 + rrcd.drb_ToAddModList = &drb_list; + + eps_bearer_id = 5; + drb.eps_BearerIdentity = &eps_bearer_id; + drb.drb_Identity = 5; + drb.rlc_Config = &rlc; + lcid = 4; + drb.logicalChannelIdentity = &lcid; + drb.logicalChannelConfig = &lc; + + ASN_SEQUENCE_ADD(&drb_list.list, &drb); + + rlc.present = LTE_RLC_Config_PR_am; + rlc.choice.am.ul_AM_RLC.t_PollRetransmit = LTE_T_PollRetransmit_ms50; + rlc.choice.am.ul_AM_RLC.pollPDU = LTE_PollPDU_p16; + rlc.choice.am.ul_AM_RLC.pollByte = LTE_PollByte_kBinfinity; + rlc.choice.am.ul_AM_RLC.maxRetxThreshold = LTE_UL_AM_RLC__maxRetxThreshold_t8; + rlc.choice.am.dl_AM_RLC.t_Reordering = LTE_T_Reordering_ms35; + rlc.choice.am.dl_AM_RLC.t_StatusProhibit = LTE_T_StatusProhibit_ms25; + + lc.ul_SpecificParameters = &ul_params; +#endif + + /* release drb 1 */ + drb = 1; + ASN_SEQUENCE_ADD(&drb_list.list, &drb); + rrcd.drb_ToReleaseList = &drb_list; + + ul_params.priority = 12; + ul_params.prioritisedBitRate = LTE_LogicalChannelConfig__ul_SpecificParameters__prioritisedBitRate_kBps8; + ul_params.bucketSizeDuration = LTE_LogicalChannelConfig__ul_SpecificParameters__bucketSizeDuration_ms300; + lcg = 3; + ul_params.logicalChannelGroup = &lcg; + + rrcd.mac_MainConfig = &mac; + + mac.present = LTE_RadioResourceConfigDedicated__mac_MainConfig_PR_explicitValue; + mac.choice.explicitValue.timeAlignmentTimerDedicated = LTE_TimeAlignmentTimer_sf10240; + mac.choice.explicitValue.ext4 = &mac_ext4; + + mac_ext4.dualConnectivityPHR = &dc_phr; + + dc_phr.present = LTE_MAC_MainConfig__ext4__dualConnectivityPHR_PR_setup; + dc_phr.choice.setup.phr_ModeOtherCG_r12 = LTE_MAC_MainConfig__ext4__dualConnectivityPHR__setup__phr_ModeOtherCG_r12_virtual; + + /* NR config */ + struct LTE_RRCConnectionReconfiguration_v890_IEs cr_890; + struct LTE_RRCConnectionReconfiguration_v920_IEs cr_920; + struct LTE_RRCConnectionReconfiguration_v1020_IEs cr_1020; + struct LTE_RRCConnectionReconfiguration_v1130_IEs cr_1130; + struct LTE_RRCConnectionReconfiguration_v1250_IEs cr_1250; + struct LTE_RRCConnectionReconfiguration_v1310_IEs cr_1310; + struct LTE_RRCConnectionReconfiguration_v1430_IEs cr_1430; + struct LTE_RRCConnectionReconfiguration_v1510_IEs cr_1510; + struct LTE_RRCConnectionReconfiguration_v1510_IEs__nr_Config_r15 nr; + + memset(&cr_890, 0, sizeof(cr_890)); + memset(&cr_920, 0, sizeof(cr_920)); + memset(&cr_1020, 0, sizeof(cr_1020)); + memset(&cr_1130, 0, sizeof(cr_1130)); + memset(&cr_1250, 0, sizeof(cr_1250)); + memset(&cr_1310, 0, sizeof(cr_1310)); + memset(&cr_1430, 0, sizeof(cr_1430)); + memset(&cr_1510, 0, sizeof(cr_1510)); + memset(&nr, 0, sizeof(nr)); + + r->criticalExtensions.choice.c1.choice.rrcConnectionReconfiguration_r8.nonCriticalExtension = &cr_890; + cr_890.nonCriticalExtension = &cr_920; + cr_920.nonCriticalExtension = &cr_1020; + cr_1020.nonCriticalExtension = &cr_1130; + cr_1130.nonCriticalExtension = &cr_1250; + cr_1250.nonCriticalExtension = &cr_1310; + cr_1310.nonCriticalExtension = &cr_1430; + cr_1430.nonCriticalExtension = &cr_1510; + + cr_1510.nr_Config_r15 = &nr; + nr.present = LTE_RRCConnectionReconfiguration_v1510_IEs__nr_Config_r15_PR_setup; + nr.choice.setup.endc_ReleaseAndAdd_r15 = 0; /* FALSE */ + + OCTET_STRING_t dummy_scg_conf; + unsigned char scg_conf_buf[4] = { 0, 0, 0, 0 }; + if (scg_group_config!=NULL) + nr.choice.setup.nr_SecondaryCellGroupConfig_r15 = scg_group_config; //&scg_conf; + else{ + nr.choice.setup.nr_SecondaryCellGroupConfig_r15 = &dummy_scg_conf; + dummy_scg_conf.buf = scg_conf_buf; + dummy_scg_conf.size = 4; + } + +#ifdef DEBUG_SCG_CONFIG + { + int size_s = nr.choice.setup.nr_SecondaryCellGroupConfig_r15->size; + int i; + LOG_I(RRC, "Dumping nr_SecondaryCellGroupConfig: %d", size_s); + for (i=0; ibuf[i]); + printf("\n"); + + } +#endif + + + long sk_counter = 0; + cr_1510.sk_Counter_r15 = &sk_counter; + + OCTET_STRING_t dummy_nr1_conf; + unsigned char nr1_buf[4] = { 0, 0, 0, 0 }; + + if(scg_RB_config!=NULL) + cr_1510.nr_RadioBearerConfig1_r15 = scg_RB_config; + else{ + cr_1510.nr_RadioBearerConfig1_r15 = &dummy_nr1_conf; + dummy_nr1_conf.buf = nr1_buf; + dummy_nr1_conf.size = 4; + } + +#ifdef DEBUG_SCG_CONFIG + { + int size_s = cr_1510.nr_RadioBearerConfig1_r15->size; + int i; + LOG_I(RRC, "Dumping nr_RadioBearerConfig1: %d", size_s); + for (i=0; ibuf[i]); + printf("\n"); + + } +#endif + + +#if 0 + OCTET_STRING_t nr2_conf; + unsigned char nr2_buf[4] = { 0, 0, 0, 0 }; + cr_1510.nr_RadioBearerConfig2_r15 = &nr2_conf; + nr2_conf.buf = nr2_buf; + nr2_conf.size = 4; +#endif + + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_DL_DCCH_Message, + NULL, + (void *)&dl_dcch_msg, + buffer, + buffer_size); + +{ +int len = (enc_rval.encoded + 7) / 8; +int i; +printf("len = %d\n", len); +for (i = 0; i < len; i++) printf(" %2.2x", buffer[i]); +printf("\n"); +} + + return (enc_rval.encoded + 7) / 8; +} diff --git a/openair2/RRC/NR/rrc_gNB_UE_context.c b/openair2/RRC/NR/rrc_gNB_UE_context.c new file mode 100644 index 0000000000..b5fb50f509 --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_UE_context.c @@ -0,0 +1,223 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_UE_context.h + * \brief rrc procedures for UE context + * \author Lionel GAUTHIER + * \date 2015 + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr + */ + +#include +#include +#include +#include + +#include "common/utils/LOG/log.h" +#include "rrc_gNB_UE_context.h" +#include "msc.h" + + +//------------------------------------------------------------------------------ +void nr_uid_linear_allocator_init( + nr_uid_allocator_t *const uid_pP +) +//------------------------------------------------------------------------------ +{ + memset(uid_pP, 0, sizeof(nr_uid_allocator_t)); +} + +//------------------------------------------------------------------------------ +uid_nr_t nr_uid_linear_allocator_new(gNB_RRC_INST *const rrc_instance_pP) +//------------------------------------------------------------------------------ +{ + unsigned int i; + unsigned int bit_index = 1; + uid_nr_t uid = 0; + nr_uid_allocator_t *uia_p = &rrc_instance_pP->uid_allocator; + + for (i=0; i < UID_LINEAR_ALLOCATOR_BITMAP_SIZE; i++) { + if (uia_p->bitmap[i] != UINT_MAX) { + bit_index = 1; + uid = 0; + + while ((uia_p->bitmap[i] & bit_index) == bit_index) { + bit_index = bit_index << 1; + uid += 1; + } + + uia_p->bitmap[i] |= bit_index; + return uid + (i*sizeof(unsigned int)*8); + } + } + + return UINT_MAX; +} + + +//------------------------------------------------------------------------------ +void +nr_uid_linear_allocator_free( + gNB_RRC_INST *rrc_instance_pP, + uid_nr_t uidP +) +//------------------------------------------------------------------------------ +{ + unsigned int i = uidP/sizeof(unsigned int)/8; + unsigned int bit = uidP % (sizeof(unsigned int) * 8); + unsigned int value = ~(0x00000001 << bit); + + if (i < UID_LINEAR_ALLOCATOR_BITMAP_SIZE) { + rrc_instance_pP->uid_allocator.bitmap[i] &= value; + } +} + + +//------------------------------------------------------------------------------ +int rrc_gNB_compare_ue_rnti_id( + struct rrc_gNB_ue_context_s *c1_pP, struct rrc_gNB_ue_context_s *c2_pP) +//------------------------------------------------------------------------------ +{ + if (c1_pP->ue_id_rnti > c2_pP->ue_id_rnti) { + return 1; + } + + if (c1_pP->ue_id_rnti < c2_pP->ue_id_rnti) { + return -1; + } + + return 0; +} + +/* Generate the tree management functions */ +RB_GENERATE(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s, entries, + rrc_gNB_compare_ue_rnti_id); + + + +//------------------------------------------------------------------------------ +struct rrc_gNB_ue_context_s * +rrc_gNB_allocate_new_UE_context( + gNB_RRC_INST *rrc_instance_pP +) +//------------------------------------------------------------------------------ +{ + struct rrc_gNB_ue_context_s *new_p; + new_p = (struct rrc_gNB_ue_context_s * )malloc(sizeof(struct rrc_gNB_ue_context_s)); + + if (new_p == NULL) { + LOG_E(RRC, "Cannot allocate new ue context\n"); + return NULL; + } + + memset(new_p, 0, sizeof(struct rrc_gNB_ue_context_s)); + new_p->local_uid = nr_uid_linear_allocator_new(rrc_instance_pP); + + for(int i = 0; i < NB_RB_MAX; i++) { + new_p->ue_context.e_rab[i].xid = -1; + new_p->ue_context.modify_e_rab[i].xid = -1; + } + + LOG_I(NR_RRC,"Returning new UE context at %p\n",new_p); + return(new_p); +} + + +//------------------------------------------------------------------------------ +struct rrc_gNB_ue_context_s * +rrc_gNB_get_ue_context( + gNB_RRC_INST *rrc_instance_pP, + rnti_t rntiP) +//------------------------------------------------------------------------------ +{ + rrc_gNB_ue_context_t temp; + memset(&temp, 0, sizeof(struct rrc_gNB_ue_context_s)); + /* gNB ue rrc id = 24 bits wide */ + temp.ue_id_rnti = rntiP; + struct rrc_gNB_ue_context_s *ue_context_p = NULL; + ue_context_p = RB_FIND(rrc_nr_ue_tree_s, &rrc_instance_pP->rrc_ue_head, &temp); + + if ( ue_context_p != NULL) { + return ue_context_p; + } else { + RB_FOREACH(ue_context_p, rrc_nr_ue_tree_s, &(rrc_instance_pP->rrc_ue_head)) { + if (ue_context_p->ue_context.rnti == rntiP) { + return ue_context_p; + } + } + return NULL; + } +} + +void rrc_gNB_free_mem_UE_context( + const protocol_ctxt_t *const ctxt_pP, + struct rrc_gNB_ue_context_s *const ue_context_pP +) +//----------------------------------------------------------------------------- +{ + + LOG_T(RRC, + PROTOCOL_RRC_CTXT_UE_FMT" Clearing UE context 0x%p (free internal structs)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + ue_context_pP); + + ASN_STRUCT_FREE_CONTENTS_ONLY(asn_DEF_LTE_SCellToAddMod_r10, &ue_context_pP->ue_context.sCell_config[0]); + ASN_STRUCT_FREE_CONTENTS_ONLY(asn_DEF_LTE_SCellToAddMod_r10, &ue_context_pP->ue_context.sCell_config[1]); + + // empty the internal fields of the UE context here +} + +//------------------------------------------------------------------------------ +void rrc_gNB_remove_ue_context( + const protocol_ctxt_t *const ctxt_pP, + gNB_RRC_INST *rrc_instance_pP, + struct rrc_gNB_ue_context_s *ue_context_pP) +//------------------------------------------------------------------------------ +{ + if (rrc_instance_pP == NULL) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Bad RRC instance\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP)); + return; + } + + if (ue_context_pP == NULL) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Trying to free a NULL UE context\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP)); + return; + } + + RB_REMOVE(rrc_nr_ue_tree_s, &rrc_instance_pP->rrc_ue_head, ue_context_pP); + MSC_LOG_EVENT( + MSC_RRC_ENB, + "0 Removed UE %"PRIx16" ", + ue_context_pP->ue_context.rnti); + rrc_gNB_free_mem_UE_context(ctxt_pP, ue_context_pP); + nr_uid_linear_allocator_free(rrc_instance_pP, ue_context_pP->local_uid); + free(ue_context_pP); + rrc_instance_pP->Nb_ue --; + LOG_I(RRC, + PROTOCOL_RRC_CTXT_UE_FMT" Removed UE context\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP)); +} + + diff --git a/openair2/RRC/NR/rrc_gNB_UE_context.h b/openair2/RRC/NR/rrc_gNB_UE_context.h new file mode 100644 index 0000000000..4681cabb8f --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_UE_context.h @@ -0,0 +1,80 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_eNB_UE_context.h + * \brief rrc procedures for UE context + * \author Lionel GAUTHIER + * \date 2015 + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr + */ +#ifndef __RRC_ENB_UE_CONTEXT_H__ +#include "collection/tree.h" +#include "COMMON/platform_types.h" +#include "nr_rrc_defs.h" + + +void +nr_uid_linear_allocator_init( + nr_uid_allocator_t* const uid_pP +); + +uid_t +nr_uid_linear_allocator_new( + gNB_RRC_INST* rrc_instance_pP +); + + +void +nr_uid_linear_allocator_free( + gNB_RRC_INST* rrc_instance_pP, + uid_t uidP +); + + + + +int rrc_gNB_compare_ue_rnti_id( + struct rrc_gNB_ue_context_s* c1_pP, + struct rrc_gNB_ue_context_s* c2_pP +); + +RB_PROTOTYPE(rrc_ue_tree_s, rrc_gNB_ue_context_s, entries, rrc_gNB_compare_ue_rnti_id); + +struct rrc_gNB_ue_context_s* +rrc_gNB_allocate_new_UE_context( + gNB_RRC_INST* rrc_instance_pP +); + +struct rrc_gNB_ue_context_s* +rrc_gNB_get_ue_context( + gNB_RRC_INST* rrc_instance_pP, + rnti_t rntiP +); + +void rrc_gNB_remove_ue_context( + const protocol_ctxt_t* const ctxt_pP, + gNB_RRC_INST* rrc_instance_pP, + struct rrc_gNB_ue_context_s* ue_context_pP +); + +#endif diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c new file mode 100644 index 0000000000..581015db56 --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -0,0 +1,127 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_internode.c + * \brief rrc internode procedures for gNB + * \author Raymond Knopp + * \date 2019 + * \version 1.0 + * \company Eurecom + * \email: raymond.knopp@eurecom.fr + */ +#ifndef RRC_GNB_INTERNODE_C +#define RRC_GNB_INTERNODE_C + +#include "nr_rrc_defs.h" +#include "NR_RRCReconfiguration.h" +#include "NR_UE-NR-Capability.h" +#include "NR_CG-ConfigInfo.h" +#include "NR_UE-CapabilityRAT-ContainerList.h" +#include "LTE_UE-CapabilityRAT-ContainerList.h" +#include "NR_CG-Config.h" + +int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo) { + + if (CG_ConfigInfo->criticalExtensions.present == NR_CG_ConfigInfo__criticalExtensions_PR_c1) { + if (CG_ConfigInfo->criticalExtensions.choice.c1) { + if (CG_ConfigInfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo) { + NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; + if (cg_ConfigInfo->ue_CapabilityInfo) { + // Decode UE-CapabilityRAT-ContainerList + LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList=NULL; + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, + (void**)&UE_CapabilityRAT_ContainerList, + cg_ConfigInfo->ue_CapabilityInfo->buf, + cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); + } + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList); + } + if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); + } + else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); + } + else { + LOG_E(RRC,"c1 extension not found, returning\n"); + return(-1); + } + } else { + LOG_E(RRC,"Ignoring unknown CG_ConfigInfo extensions\n"); + return(-1); + } + return(0); +} + + +int generate_CG_Config(gNB_RRC_INST *rrc, + NR_CG_Config_t *cg_Config, + NR_RRCReconfiguration_t *reconfig, + NR_RadioBearerConfig_t *rbconfig) { + + + cg_Config->criticalExtensions.present = NR_CG_Config__criticalExtensions_PR_c1; + cg_Config->criticalExtensions.choice.c1 = calloc(1,sizeof(*cg_Config->criticalExtensions.choice.c1)); + cg_Config->criticalExtensions.choice.c1->present = NR_CG_Config__criticalExtensions__c1_PR_cg_Config; + cg_Config->criticalExtensions.choice.c1->choice.cg_Config = calloc(1,sizeof(NR_CG_Config_IEs_t)); + char buffer[1024]; + int total_size; + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RRCReconfiguration, NULL, (void *)reconfig, buffer, 1024); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig = calloc(1,sizeof(OCTET_STRING_t)); + OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig, + (const char *)buffer, + (enc_rval.encoded+7)>>3); + total_size = (enc_rval.encoded+7)>>3; + + LOG_I(RRC,"Dumping NR_RRCReconfiguration message (%jd bytes)\n",(enc_rval.encoded+7)>>3); + for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { + printf("%02x",((uint8_t *)buffer)[i]); + } + printf("\n"); + FILE *fd = fopen("reconfig.raw","w"); + fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fclose(fd); + + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, NULL, (void *)rbconfig, buffer, 1024); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config = calloc(1,sizeof(OCTET_STRING_t)); + OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config, + (const char *)buffer, + (enc_rval.encoded+7)>>3); + LOG_I(RRC,"Dumping scg_RB_Config message (%jd bytes)\n",(enc_rval.encoded+7)>>3); + for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { + printf("%02x",((uint8_t*)buffer)[i]); + } + printf("\n"); + fd = fopen("rbconfig.raw","w"); + fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fclose(fd); + total_size = total_size + ((enc_rval.encoded+7)>>3); + + return(total_size); +} + +#endif diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c new file mode 100644 index 0000000000..cf48aef459 --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -0,0 +1,159 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_nsa.c + * \brief rrc NSA procedures for gNB + * \author Raymond Knopp + * \date 2019 + * \version 1.0 + * \company Eurecom + * \email: raymond.knopp@eurecom.fr + */ +#ifndef RRC_GNB_NSA_C +#define RRC_GNB_NSA_C + +#include "nr_rrc_defs.h" +#include "NR_RRCReconfiguration.h" +#include "NR_UE-NR-Capability.h" +//#include "NR_UE-CapabilityRAT-ContainerList.h" +#include "LTE_UE-CapabilityRAT-ContainerList.h" +#include "NR_CG-Config.h" +#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" + +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) { + + struct rrc_gNB_ue_context_s *ue_context_p = NULL; + OCTET_STRING_t *ueCapabilityRAT_Container_nr; + OCTET_STRING_t *ueCapabilityRAT_Container_MRDC; + int list_size; + AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n"); + AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count); + for (int i=0;ilist.array[i]->rat_Type == LTE_RAT_Type_nr) ueCapabilityRAT_Container_nr = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; + else if (UE_CapabilityRAT_ContainerList->list.array[i]->rat_Type == LTE_RAT_Type_eutra_nr) ueCapabilityRAT_Container_MRDC = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; + } + + AssertFatal(ueCapabilityRAT_Container_nr!=NULL,"ueCapabilityRAT_Container_nr is NULL\n"); + AssertFatal(ueCapabilityRAT_Container_MRDC!=NULL,"ueCapabilityRAT_Container_MRDC is NULL\n"); + // decode and store capabilities + ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); + + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_NR_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_nr, + ueCapabilityRAT_Container_nr->buf, + ueCapabilityRAT_Container_nr->size, 0, 0); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, + ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + AssertFatal(1==0,"exiting\n"); + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_MRDC_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_MRDC, + ueCapabilityRAT_Container_MRDC->buf, + ueCapabilityRAT_Container_MRDC->size, 0, 0); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, + ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + AssertFatal(1==0,"exiting\n"); + } + + // dump ue_capabilities + + if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } + + if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } + + rrc_add_nsa_user(rrc,ue_context_p); +} + +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p) { + +// generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) + + rrc_gNB_carrier_data_t *carrier=&rrc->carrier; + + MessageDef *msg; + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); + +// NR RRCReconfiguration + + AssertFatal(rrc->Nb_ue < MAX_NR_RRC_UE_CONTEXTS,"cannot add another UE\n"); + + ue_context_p->ue_context.reconfig = calloc(1,sizeof(NR_RRCReconfiguration_t)); + ue_context_p->ue_context.secondaryCellGroup = calloc(1,sizeof(NR_CellGroupConfig_t)); + memset((void*)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); + ue_context_p->ue_context.reconfig->rrc_TransactionIdentifier=0; + ue_context_p->ue_context.reconfig->criticalExtensions.present = NR_RRCReconfiguration__criticalExtensions_PR_rrcReconfiguration; + NR_RRCReconfiguration_IEs_t *reconfig_ies=calloc(1,sizeof(NR_RRCReconfiguration_IEs_t)); + ue_context_p->ue_context.reconfig->criticalExtensions.choice.rrcReconfiguration = reconfig_ies; + carrier->initial_csi_index[rrc->Nb_ue] = 0; + fill_default_reconfig(carrier->servingcellconfigcommon, + reconfig_ies, + ue_context_p->ue_context.secondaryCellGroup, + carrier->pdsch_AntennaPorts, + carrier->initial_csi_index[rrc->Nb_ue]); + + ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); + + fill_default_rbconfig(ue_context_p->ue_context.rb_config); + ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; + NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); + memset((void*)CG_Config,0,sizeof(*CG_Config)); + int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + + //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size + // Send to X2 entity to transport to MeNB + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_Config, + NULL, + (void *)CG_Config, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, + 1024); + + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = (enc_rval.encoded+7)>>3; + + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(0), msg); //Check right id instead of hardcoding + + rrc->Nb_ue++; + // configure MAC and RLC + rrc_mac_config_req_gNB(rrc->module_id, + rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.pdsch_AntennaPorts, + NULL, + 1, // add_ue flag + ue_context_p->ue_id_rnti, + ue_context_p->ue_context.secondaryCellGroup); +} + + +#endif diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c new file mode 100644 index 0000000000..1df17a19aa --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -0,0 +1,2085 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_reconfig.c + * \brief rrc gNB RRCreconfiguration support routines + * \author Raymond Knopp + * \date 2019 + * \version 1.0 + * \company Eurecom + * \email: raymond.knopp@eurecom.fr + */ +#ifndef RRC_GNB_NSA_C +#define RRC_GNB_NSA_C + +#include "NR_ServingCellConfigCommon.h" +#include "NR_RRCReconfiguration.h" +#include "NR_RRCReconfiguration-IEs.h" +#include "NR_CellGroupConfig.h" +#include "NR_MAC-CellGroupConfig.h" +#include "NR_BSR-Config.h" +#include "NR_PDSCH-ServingCellConfig.h" +#include "NR_RLC-BearerConfig.h" +#include "BOOLEAN.h" +#include "assertions.h" +#include "common/utils/nr/nr_common.h" +#include "SIMULATION/TOOLS/sim.h" +#include "executables/softmodem-common.h" + +#define false 0 +#define true 1 + + +void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, + NR_CellGroupConfig_t *secondaryCellGroup, + int scg_id, + int servCellIndex, + int n_physical_antenna_ports, + int initial_csi_index) { + AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); + AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); + + memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t)); + secondaryCellGroup->cellGroupId = scg_id; + + NR_RLC_BearerConfig_t *RLC_BearerConfig = calloc(1,sizeof(*RLC_BearerConfig)); + + RLC_BearerConfig->logicalChannelIdentity = 4; + RLC_BearerConfig->servedRadioBearer = calloc(1,sizeof(*RLC_BearerConfig->servedRadioBearer)); + RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; + + RLC_BearerConfig->servedRadioBearer->choice.drb_Identity=1; + RLC_BearerConfig->reestablishRLC=calloc(1,sizeof(*RLC_BearerConfig->reestablishRLC)); + *RLC_BearerConfig->reestablishRLC=NR_RLC_BearerConfig__reestablishRLC_true; + RLC_BearerConfig->rlc_Config=calloc(1,sizeof(*RLC_BearerConfig->rlc_Config)); + RLC_BearerConfig->rlc_Config->present = NR_RLC_Config_PR_am; + RLC_BearerConfig->rlc_Config->choice.am = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am)); + RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength)); + *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; + RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.t_PollRetransmit = NR_T_PollRetransmit_ms45; + RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollPDU = NR_PollPDU_p64; + RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollByte = NR_PollByte_kB500; + RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.maxRetxThreshold = NR_UL_AM_RLC__maxRetxThreshold_t32; + + RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength)); + *RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; + RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_Reassembly = NR_T_Reassembly_ms15; + RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_StatusProhibit = NR_T_StatusProhibit_ms15; + + RLC_BearerConfig->mac_LogicalChannelConfig = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig)); + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters)); + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->priority = 1; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->prioritisedBitRate = NR_LogicalChannelConfig__ul_SpecificParameters__prioritisedBitRate_infinity; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->bucketSizeDuration = NR_LogicalChannelConfig__ul_SpecificParameters__bucketSizeDuration_ms50; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->allowedServingCells = NULL; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->allowedSCS_List = NULL; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->maxPUSCH_Duration = NULL; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->configuredGrantType1Allowed = NULL; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelGroup = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelGroup)); + *RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelGroup = 1; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->schedulingRequestID = NULL; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_Mask = false; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_DelayTimerApplied = false; + RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->bitRateQueryProhibitTimer = NULL; + + secondaryCellGroup->rlc_BearerToAddModList = calloc(1,sizeof(*secondaryCellGroup->rlc_BearerToAddModList)); + ASN_SEQUENCE_ADD(&secondaryCellGroup->rlc_BearerToAddModList->list, RLC_BearerConfig); + + secondaryCellGroup->mac_CellGroupConfig=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig)); + secondaryCellGroup->mac_CellGroupConfig->drx_Config = NULL; + secondaryCellGroup->mac_CellGroupConfig->schedulingRequestConfig = NULL; + secondaryCellGroup->mac_CellGroupConfig->bsr_Config=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->bsr_Config)); + secondaryCellGroup->mac_CellGroupConfig->bsr_Config->periodicBSR_Timer = NR_BSR_Config__periodicBSR_Timer_sf80; + secondaryCellGroup->mac_CellGroupConfig->bsr_Config->retxBSR_Timer = NR_BSR_Config__retxBSR_Timer_sf320; + secondaryCellGroup->mac_CellGroupConfig->tag_Config=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->tag_Config)); + secondaryCellGroup->mac_CellGroupConfig->tag_Config->tag_ToReleaseList = NULL; + secondaryCellGroup->mac_CellGroupConfig->tag_Config->tag_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->tag_Config->tag_ToAddModList)); + struct NR_TAG *tag=calloc(1,sizeof(*tag)); + tag->tag_Id = 0; + tag->timeAlignmentTimer = NR_TimeAlignmentTimer_infinity; + ASN_SEQUENCE_ADD(&secondaryCellGroup->mac_CellGroupConfig->tag_Config->tag_ToAddModList->list,tag); + secondaryCellGroup->mac_CellGroupConfig->phr_Config = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->phr_Config)); + secondaryCellGroup->mac_CellGroupConfig->phr_Config->present = NR_SetupRelease_PHR_Config_PR_setup; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup)); + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_PeriodicTimer = NR_PHR_Config__phr_PeriodicTimer_sf20; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ProhibitTimer = NR_PHR_Config__phr_ProhibitTimer_sf0; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Tx_PowerFactorChange = NR_PHR_Config__phr_Tx_PowerFactorChange_dB3; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->multiplePHR=false; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false; + secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real; + + secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false; + secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL; + + + secondaryCellGroup->physicalCellGroupConfig = calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig)); + + secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH=NULL; + secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUSCH=NULL; + secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1)); + *secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=20; + secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; + secondaryCellGroup->physicalCellGroupConfig->tpc_SRS_RNTI=NULL; + secondaryCellGroup->physicalCellGroupConfig->tpc_PUCCH_RNTI=NULL; + secondaryCellGroup->physicalCellGroupConfig->tpc_PUSCH_RNTI=NULL; + secondaryCellGroup->physicalCellGroupConfig->sp_CSI_RNTI=NULL; + secondaryCellGroup->physicalCellGroupConfig->cs_RNTI=NULL; + secondaryCellGroup->physicalCellGroupConfig->ext1=NULL; + + secondaryCellGroup->spCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig)); + secondaryCellGroup->spCellConfig->servCellIndex = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->servCellIndex)); + *secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex; + secondaryCellGroup->spCellConfig->reconfigurationWithSync=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->reconfigurationWithSync)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon=servingcellconfigcommon; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity=(get_softmodem_params()->phy_test==1) ? 0x1234 : (taus()&0xffff); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; + + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants)); + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->present = NR_SetupRelease_RLF_TimersAndConstants_PR_setup; + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup)); + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->t310 = NR_RLF_TimersAndConstants__t310_ms2000; + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->n310 = NR_RLF_TimersAndConstants__n310_n10; + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->n311 = NR_RLF_TimersAndConstants__n311_n1; + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1 = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1)); + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1->t311_v1530 = NR_RLF_TimersAndConstants__ext1__t311_v1530_ms30000; + + secondaryCellGroup->spCellConfig->rlmInSyncOutOfSyncThreshold = NULL; + + + + secondaryCellGroup->spCellConfig->spCellConfigDedicated = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->tdd_UL_DL_ConfigurationDedicated = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdcch_Config=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); + + NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); + tci0->tci_StateId=0; + tci0->qcl_Type1.cell=NULL; + tci0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci0->qcl_Type1.bwp_Id)); + *tci0->qcl_Type1.bwp_Id=1; + tci0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci0->qcl_Type1.referenceSignal.choice.csi_rs = 2; + tci0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci0); + + NR_TCI_State_t*tci1=calloc(1,sizeof(*tci1)); + tci1->tci_StateId=1; + tci1->qcl_Type1.cell=NULL; + tci1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci1->qcl_Type1.bwp_Id)); + *tci1->qcl_Type1.bwp_Id=1; + tci1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci1->qcl_Type1.referenceSignal.choice.csi_rs = 6; + tci1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci1); + + NR_TCI_State_t*tci2=calloc(1,sizeof(*tci2)); + tci2->tci_StateId=2; + tci2->qcl_Type1.cell=NULL; + tci2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci2->qcl_Type1.bwp_Id)); + *tci2->qcl_Type1.bwp_Id=1; + tci2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci2->qcl_Type1.referenceSignal.choice.csi_rs = 10; + tci2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci2); + + NR_TCI_State_t *tci3=calloc(1,sizeof(*tci3)); + tci3->tci_StateId=3; + tci3->qcl_Type1.cell=NULL; + tci3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci3->qcl_Type1.bwp_Id)); + *tci3->qcl_Type1.bwp_Id=1; + tci3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci3->qcl_Type1.referenceSignal.choice.csi_rs = 14; + tci3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci3); + + NR_TCI_State_t*tci4=calloc(1,sizeof(*tci4)); + tci4->tci_StateId=4; + tci4->qcl_Type1.cell=NULL; + tci4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci4->qcl_Type1.bwp_Id)); + *tci4->qcl_Type1.bwp_Id=1; + tci4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci4->qcl_Type1.referenceSignal.choice.csi_rs = 18; + tci4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci4); + + NR_TCI_State_t*tci5=calloc(1,sizeof(*tci5)); + tci5->tci_StateId=5; + tci5->qcl_Type1.cell=NULL; + tci5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci5->qcl_Type1.bwp_Id)); + *tci5->qcl_Type1.bwp_Id=1; + tci5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci5->qcl_Type1.referenceSignal.choice.csi_rs = 22; + tci5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci5); + + NR_TCI_State_t*tci6=calloc(1,sizeof(*tci6)); + tci6->tci_StateId=6; + tci6->qcl_Type1.cell=NULL; + tci6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci6->qcl_Type1.bwp_Id)); + *tci6->qcl_Type1.bwp_Id=1; + tci6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci6->qcl_Type1.referenceSignal.choice.csi_rs = 26; + tci6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci6); + + NR_TCI_State_t*tci7=calloc(1,sizeof(*tci7)); + tci7->tci_StateId=7; + tci7->qcl_Type1.cell=NULL; + tci7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci7->qcl_Type1.bwp_Id)); + *tci7->qcl_Type1.bwp_Id=1; + tci7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci7->qcl_Type1.referenceSignal.choice.csi_rs = 30; + tci7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci7); + + NR_TCI_State_t*tci8=calloc(1,sizeof(*tci8)); + tci8->tci_StateId=8; + tci8->qcl_Type1.cell=NULL; + tci8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci8->qcl_Type1.bwp_Id)); + *tci8->qcl_Type1.bwp_Id=1; + tci8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci8->qcl_Type1.referenceSignal.choice.ssb = 0; + tci8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci8); + + NR_TCI_State_t*tci9=calloc(1,sizeof(*tci9)); + tci9->tci_StateId=9; + tci9->qcl_Type1.cell=NULL; + tci9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci9->qcl_Type1.bwp_Id)); + *tci9->qcl_Type1.bwp_Id=1; + tci9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci9->qcl_Type1.referenceSignal.choice.ssb = 1; + tci9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci9); + + NR_TCI_State_t*tci10=calloc(1,sizeof(*tci10)); + tci10->tci_StateId=10; + tci10->qcl_Type1.cell=NULL; + tci10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci10->qcl_Type1.bwp_Id)); + *tci10->qcl_Type1.bwp_Id=1; + tci10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci10->qcl_Type1.referenceSignal.choice.ssb = 2; + tci10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci10); + + NR_TCI_State_t*tci11=calloc(1,sizeof(*tci11)); + tci11->tci_StateId=11; + tci11->qcl_Type1.cell=NULL; + tci11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci11->qcl_Type1.bwp_Id)); + *tci11->qcl_Type1.bwp_Id=1; + tci11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci11->qcl_Type1.referenceSignal.choice.ssb = 3; + tci11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci11); + + NR_TCI_State_t*tci12=calloc(1,sizeof(*tci12)); + tci12->tci_StateId=12; + tci12->qcl_Type1.cell=NULL; + tci12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci12->qcl_Type1.bwp_Id)); + *tci12->qcl_Type1.bwp_Id=1; + tci12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci12->qcl_Type1.referenceSignal.choice.ssb = 4; + tci12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci12); + + NR_TCI_State_t*tci13=calloc(1,sizeof(*tci13)); + tci13->tci_StateId=13; + tci13->qcl_Type1.cell=NULL; + tci13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci13->qcl_Type1.bwp_Id)); + *tci13->qcl_Type1.bwp_Id=1; + tci13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci13->qcl_Type1.referenceSignal.choice.ssb = 5; + tci13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci13); + + NR_TCI_State_t*tci14=calloc(1,sizeof(*tci14)); + tci14->tci_StateId=14; + tci14->qcl_Type1.cell=NULL; + tci14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci14->qcl_Type1.bwp_Id)); + *tci14->qcl_Type1.bwp_Id=1; + tci14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci14->qcl_Type1.referenceSignal.choice.ssb = 6; + tci14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci14); + + NR_TCI_State_t*tci15=calloc(1,sizeof(*tci15)); + tci15->tci_StateId=15; + tci15->qcl_Type1.cell=NULL; + tci15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci15->qcl_Type1.bwp_Id)); + *tci15->qcl_Type1.bwp_Id=1; + tci15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci15->qcl_Type1.referenceSignal.choice.ssb = 7; + tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); + + NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); + bwp->bwp_Id=1; + bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common)); + // copy common BWP size from initial BWP except for bandwdith + memcpy((void*)&bwp->bwp_Common->genericParameters, + &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, + sizeof(bwp->bwp_Common->genericParameters)); + bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); + + + bwp->bwp_Common->pdcch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon)); + bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); + + NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); + ss->searchSpaceId = 1; + ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); + *ss->controlResourceSetId=0; + ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); + ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss->duration=NULL; + ss->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss->monitoringSymbolsWithinSlot)); + ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); + // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed + ss->monitoringSymbolsWithinSlot->buf[1] = 0; + ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); + ss->monitoringSymbolsWithinSlot->size = 2; + ss->monitoringSymbolsWithinSlot->bits_unused = 2; + ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); + ss->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; + ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss->searchSpaceType = calloc(1,sizeof(*ss->searchSpaceType)); + ss->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; + ss->searchSpaceType->choice.common=calloc(1,sizeof(*ss->searchSpaceType->choice.common)); + ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); + + ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,ss); + + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->pagingSearchSpace=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); + *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; + + bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); + bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; + bwp->bwp_Common->pdsch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup)); + bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)); + + // copy PDSCH TimeDomainResourceAllocation from InitialBWP + + NR_PDSCH_TimeDomainResourceAllocation_t *pdschi; + for (int i=0;idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;i++) { + pdschi= calloc(1,sizeof(*pdschi)); + AssertFatal(servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0!=NULL,"element %d is null\n",i); + + pdschi->k0 = calloc(1,sizeof(*pdschi->k0)); + *pdschi->k0 = *servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + pdschi->mappingType = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; + pdschi->startSymbolAndLength = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,pdschi); + } + + bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated)); + + bwp->bwp_Dedicated->pdcch_Config=calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config)); + bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; + bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); + NR_ControlResourceSet_t *coreset0 = calloc(1,sizeof(*coreset0)); + coreset0->controlResourceSetId=1; + // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, + coreset0->frequencyDomainResources.buf = calloc(1,6); + coreset0->frequencyDomainResources.buf[0] = 0xff; + coreset0->frequencyDomainResources.buf[1] = 0xff; + coreset0->frequencyDomainResources.buf[2] = 0; + coreset0->frequencyDomainResources.buf[3] = 0; + coreset0->frequencyDomainResources.buf[4] = 0; + coreset0->frequencyDomainResources.buf[5] = 0; + coreset0->frequencyDomainResources.size = 6; + coreset0->frequencyDomainResources.bits_unused = 3; + coreset0->duration=1; + coreset0->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; + coreset0->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; + + coreset0->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset0->tci_StatesPDCCH_ToAddList)); + NR_TCI_StateId_t *tci[8]; + for (int i=0;i<8;i++) { + tci[i]=calloc(1,sizeof(*tci[i])); + *tci[i] = i; + ASN_SEQUENCE_ADD(&coreset0->tci_StatesPDCCH_ToAddList->list,tci[i]); + } + coreset0->tci_StatesPDCCH_ToReleaseList = NULL; + coreset0->tci_PresentInDCI = NULL; + coreset0->pdcch_DMRS_ScramblingID = NULL; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, + coreset0); + + bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); + NR_SearchSpace_t *ss3 = calloc(1,sizeof(*ss3)); + NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); + ss3->searchSpaceId=3; + ss3->controlResourceSetId=calloc(1,sizeof(*ss3->controlResourceSetId)); + *ss3->controlResourceSetId=1; + ss3->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss3->monitoringSlotPeriodicityAndOffset)); + ss3->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss3->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; + ss3->duration=NULL; + ss3->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss3->monitoringSymbolsWithinSlot)); + ss3->monitoringSymbolsWithinSlot->buf = calloc(1,2); + ss3->monitoringSymbolsWithinSlot->size = 2; + ss3->monitoringSymbolsWithinSlot->bits_unused = 2; + ss3->monitoringSymbolsWithinSlot->buf[0]=0xc0; + ss3->monitoringSymbolsWithinSlot->buf[1]=0x0; + ss3->nrofCandidates=calloc(1,sizeof(*ss3->nrofCandidates)); + ss3->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss3->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss3->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; + ss3->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss3->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss3->searchSpaceType=calloc(1,sizeof(*ss3->searchSpaceType)); + ss3->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; + ss3->searchSpaceType->choice.common = calloc(1,sizeof(*ss3->searchSpaceType->choice.common)); + ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0=calloc(1,sizeof(*ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); + ss3->searchSpaceType->choice.common->dci_Format2_0=NULL; + ss3->searchSpaceType->choice.common->dci_Format2_2=NULL; + ss3->searchSpaceType->choice.common->dci_Format2_3=NULL; + + ss2->searchSpaceId=2; + ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); + *ss2->controlResourceSetId=1; + ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); + ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; + ss2->duration=NULL; + ss2->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss2->monitoringSymbolsWithinSlot)); + ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); + ss2->monitoringSymbolsWithinSlot->size = 2; + ss2->monitoringSymbolsWithinSlot->bits_unused = 2; + ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; + ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; + ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); + ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss2->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss2->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; + ss2->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss2->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); + ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); + ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; + + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, + ss3); + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, + ss2); + + + bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToReleaseList = NULL; + + bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); + + bwp->bwp_Dedicated->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; + bwp->bwp_Dedicated->pdsch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); + + NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); + tcid0->tci_StateId=0; + tcid0->qcl_Type1.cell=NULL; + tcid0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid0->qcl_Type1.bwp_Id)); + *tcid0->qcl_Type1.bwp_Id=1; + tcid0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid0->qcl_Type1.referenceSignal.choice.csi_rs = 2; + tcid0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid0); + + NR_TCI_State_t*tcid1=calloc(1,sizeof(*tcid1)); + tcid1->tci_StateId=0; + tcid1->qcl_Type1.cell=NULL; + tcid1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid1->qcl_Type1.bwp_Id)); + *tcid1->qcl_Type1.bwp_Id=1; + tcid1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid1->qcl_Type1.referenceSignal.choice.csi_rs = 6; + tcid1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid1); + + NR_TCI_State_t*tcid2=calloc(1,sizeof(*tcid2)); + tcid2->tci_StateId=2; + tcid2->qcl_Type1.cell=NULL; + tcid2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid2->qcl_Type1.bwp_Id)); + *tcid2->qcl_Type1.bwp_Id=1; + tcid2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid2->qcl_Type1.referenceSignal.choice.csi_rs = 10; + tcid2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid2); + + NR_TCI_State_t*tcid3=calloc(1,sizeof(*tcid3)); + tcid3->tci_StateId=3; + tcid3->qcl_Type1.cell=NULL; + tcid3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid3->qcl_Type1.bwp_Id)); + *tcid3->qcl_Type1.bwp_Id=1; + tcid3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid3->qcl_Type1.referenceSignal.choice.csi_rs = 14; + tcid3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid3); + + NR_TCI_State_t*tcid4=calloc(1,sizeof(*tcid4)); + tcid4->tci_StateId=4; + tcid4->qcl_Type1.cell=NULL; + tcid4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid4->qcl_Type1.bwp_Id)); + *tcid4->qcl_Type1.bwp_Id=1; + tcid4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid4->qcl_Type1.referenceSignal.choice.csi_rs = 18; + tcid4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid4); + + NR_TCI_State_t*tcid5=calloc(1,sizeof(*tcid5)); + tcid5->tci_StateId=5; + tcid5->qcl_Type1.cell=NULL; + tcid5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid5->qcl_Type1.bwp_Id)); + *tcid5->qcl_Type1.bwp_Id=1; + tcid5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid5->qcl_Type1.referenceSignal.choice.csi_rs = 22; + tcid5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid5); + + NR_TCI_State_t*tcid6=calloc(1,sizeof(*tcid6)); + tcid6->tci_StateId=6; + tcid6->qcl_Type1.cell=NULL; + tcid6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid6->qcl_Type1.bwp_Id)); + *tcid6->qcl_Type1.bwp_Id=1; + tcid6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid6->qcl_Type1.referenceSignal.choice.csi_rs = 26; + tcid6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid6); + + NR_TCI_State_t*tcid7=calloc(1,sizeof(*tcid7)); + tcid7->tci_StateId=7; + tcid7->qcl_Type1.cell=NULL; + tcid7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid7->qcl_Type1.bwp_Id)); + *tcid7->qcl_Type1.bwp_Id=1; + tcid7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid7->qcl_Type1.referenceSignal.choice.csi_rs = 30; + tcid7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid7); + + NR_TCI_State_t*tcid8=calloc(1,sizeof(*tcid8)); + tcid8->tci_StateId=8; + tcid8->qcl_Type1.cell=NULL; + tcid8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid8->qcl_Type1.bwp_Id)); + *tcid8->qcl_Type1.bwp_Id=1; + tcid8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid8->qcl_Type1.referenceSignal.choice.ssb = 0; + tcid8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid8); + + NR_TCI_State_t*tcid9=calloc(1,sizeof(*tcid9)); + tcid9->tci_StateId=9; + tcid9->qcl_Type1.cell=NULL; + tcid9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid9->qcl_Type1.bwp_Id)); + *tcid9->qcl_Type1.bwp_Id=1; + tcid9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid9->qcl_Type1.referenceSignal.choice.ssb = 1; + tcid9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid9); + + NR_TCI_State_t*tcid10=calloc(1,sizeof(*tcid10)); + tcid10->tci_StateId=10; + tcid10->qcl_Type1.cell=NULL; + tcid10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid10->qcl_Type1.bwp_Id)); + *tcid10->qcl_Type1.bwp_Id=1; + tcid10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid10->qcl_Type1.referenceSignal.choice.ssb = 2; + tcid10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid10); + + NR_TCI_State_t*tcid11=calloc(1,sizeof(*tcid11)); + tcid11->tci_StateId=11; + tcid11->qcl_Type1.cell=NULL; + tcid11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid11->qcl_Type1.bwp_Id)); + *tcid11->qcl_Type1.bwp_Id=1; + tcid11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid11->qcl_Type1.referenceSignal.choice.ssb = 3; + tcid11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid11); + + NR_TCI_State_t*tcid12=calloc(1,sizeof(*tcid12)); + tcid12->tci_StateId=12; + tcid12->qcl_Type1.cell=NULL; + tcid12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid12->qcl_Type1.bwp_Id)); + *tcid12->qcl_Type1.bwp_Id=1; + tcid12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid12->qcl_Type1.referenceSignal.choice.ssb = 4; + tcid12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid12); + + NR_TCI_State_t*tcid13=calloc(1,sizeof(*tcid13)); + tcid13->tci_StateId=13; + tcid13->qcl_Type1.cell=NULL; + tcid13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid13->qcl_Type1.bwp_Id)); + *tcid13->qcl_Type1.bwp_Id=1; + tcid13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid13->qcl_Type1.referenceSignal.choice.ssb = 5; + tcid13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid13); + + NR_TCI_State_t*tcid14=calloc(1,sizeof(*tcid14)); + tcid14->tci_StateId=14; + tcid14->qcl_Type1.cell=NULL; + tcid14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid14->qcl_Type1.bwp_Id)); + *tcid14->qcl_Type1.bwp_Id=1; + tcid14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid14->qcl_Type1.referenceSignal.choice.ssb = 6; + tcid14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid14); + + NR_TCI_State_t*tcid15=calloc(1,sizeof(*tcid15)); + tcid15->tci_StateId=15; + tcid15->qcl_Type1.cell=NULL; + tcid15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid15->qcl_Type1.bwp_Id)); + *tcid15->qcl_Type1.bwp_Id=1; + tcid15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; + tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); + + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + + bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; + + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); + *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); + *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; + + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); + + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); + + NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP = initialUplinkBWP; + initialUplinkBWP->pucch_Config = NULL; + initialUplinkBWP->pusch_Config = calloc(1,sizeof(*initialUplinkBWP->pusch_Config)); + initialUplinkBWP->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; + NR_PUSCH_Config_t *pusch_Config = calloc(1,sizeof(*pusch_Config)); + initialUplinkBWP->pusch_Config->choice.setup = pusch_Config; + pusch_Config->txConfig=calloc(1,sizeof(*pusch_Config->txConfig)); + *pusch_Config->txConfig= NR_PUSCH_Config__txConfig_codebook; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA = NULL; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB)); + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->present = NR_SetupRelease_DMRS_UplinkConfig_PR_setup; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + NR_DMRS_UplinkConfig->dmrs_Type = NULL; + NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; + NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; + NR_DMRS_UplinkConfig->maxLength=NULL; + NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); + NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0 = NULL; + NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1 = NULL; + NR_DMRS_UplinkConfig->transformPrecodingEnabled = NULL; + pusch_Config->pusch_PowerControl = calloc(1,sizeof(*pusch_Config->pusch_PowerControl)); + pusch_Config->pusch_PowerControl->tpc_Accumulation = NULL; + pusch_Config->pusch_PowerControl->msg3_Alpha = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->msg3_Alpha)); + *pusch_Config->pusch_PowerControl->msg3_Alpha = NR_Alpha_alpha1; + pusch_Config->pusch_PowerControl->p0_NominalWithoutGrant = NULL; + pusch_Config->pusch_PowerControl->p0_AlphaSets = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->p0_AlphaSets)); + NR_P0_PUSCH_AlphaSet_t *aset = calloc(1,sizeof(*aset)); + aset->p0_PUSCH_AlphaSetId=0; + aset->p0=calloc(1,sizeof(*aset->p0)); + *aset->p0 = 0; + aset->alpha=calloc(1,sizeof(*aset->alpha)); + *aset->alpha=NR_Alpha_alpha1; + ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->p0_AlphaSets->list,aset); + pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList)); + NR_PUSCH_PathlossReferenceRS_t *pl = calloc(1,sizeof(*pl)); + pl->pusch_PathlossReferenceRS_Id=0; + pl->referenceSignal.present = NR_PUSCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; + pl->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList->list,pl); + pusch_Config->pusch_PowerControl->pathlossReferenceRSToReleaseList = NULL; + pusch_Config->pusch_PowerControl->twoPUSCH_PC_AdjustmentStates = NULL; + pusch_Config->pusch_PowerControl->deltaMCS = NULL; + pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToAddModList = NULL; + pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToReleaseList = NULL; + pusch_Config->frequencyHopping=NULL; + pusch_Config->frequencyHoppingOffsetLists=NULL; + pusch_Config->resourceAllocation = NR_PUSCH_Config__resourceAllocation_resourceAllocationType1; + pusch_Config->pusch_TimeDomainAllocationList = NULL; + pusch_Config->pusch_AggregationFactor=NULL; + pusch_Config->mcs_Table=NULL; + pusch_Config->mcs_TableTransformPrecoder=NULL; + pusch_Config->transformPrecoder=calloc(1,sizeof(*pusch_Config->transformPrecoder)); + *pusch_Config->transformPrecoder = NR_PUSCH_Config__transformPrecoder_disabled; + pusch_Config->codebookSubset=calloc(1,sizeof(*pusch_Config->codebookSubset)); + *pusch_Config->codebookSubset = NR_PUSCH_Config__codebookSubset_nonCoherent; + pusch_Config->maxRank=calloc(1,sizeof(*pusch_Config->maxRank)); + *pusch_Config->maxRank= 1; + pusch_Config->rbg_Size=NULL; + pusch_Config->uci_OnPUSCH=NULL; + pusch_Config->tp_pi2BPSK=NULL; + + initialUplinkBWP->srs_Config = calloc(1,sizeof(*initialUplinkBWP->srs_Config)); + initialUplinkBWP->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; + NR_SRS_Config_t *srs_Config = calloc(1,sizeof(*srs_Config)); + initialUplinkBWP->srs_Config->choice.setup=srs_Config; + srs_Config->srs_ResourceSetToReleaseList=NULL; + srs_Config->srs_ResourceSetToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceSetToAddModList)); + NR_SRS_ResourceSet_t *srs_resset0=calloc(1,sizeof(*srs_resset0)); + srs_resset0->srs_ResourceSetId = 0; + srs_resset0->srs_ResourceIdList=calloc(1,sizeof(*srs_resset0->srs_ResourceIdList)); + NR_SRS_ResourceId_t *srs_resset0_id=calloc(1,sizeof(*srs_resset0_id)); + *srs_resset0_id=0; + ASN_SEQUENCE_ADD(&srs_resset0->srs_ResourceIdList->list,srs_resset0_id); + srs_Config->srs_ResourceToReleaseList=NULL; + srs_resset0->resourceType.present = NR_SRS_ResourceSet__resourceType_PR_aperiodic; + srs_resset0->resourceType.choice.aperiodic = calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic)); + srs_resset0->resourceType.choice.aperiodic->aperiodicSRS_ResourceTrigger=1; + srs_resset0->resourceType.choice.aperiodic->csi_RS=NULL; + srs_resset0->resourceType.choice.aperiodic->slotOffset= calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic->slotOffset)); + *srs_resset0->resourceType.choice.aperiodic->slotOffset=2; + srs_resset0->resourceType.choice.aperiodic->ext1=NULL; + srs_resset0->usage=NR_SRS_ResourceSet__usage_codebook; + srs_resset0->alpha = calloc(1,sizeof(*srs_resset0->alpha)); + *srs_resset0->alpha = NR_Alpha_alpha1; + srs_resset0->p0=calloc(1,sizeof(*srs_resset0->p0)); + *srs_resset0->p0=-80; + srs_resset0->pathlossReferenceRS=NULL; + srs_resset0->srs_PowerControlAdjustmentStates=NULL; + ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceSetToAddModList->list,srs_resset0); + srs_Config->srs_ResourceToReleaseList=NULL; + srs_Config->srs_ResourceToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceToAddModList)); + NR_SRS_Resource_t *srs_res0=calloc(1,sizeof(*srs_res0)); + srs_res0->srs_ResourceId=0; + srs_res0->nrofSRS_Ports=NR_SRS_Resource__nrofSRS_Ports_port1; + srs_res0->ptrs_PortIndex=NULL; + srs_res0->transmissionComb.present=NR_SRS_Resource__transmissionComb_PR_n2; + srs_res0->transmissionComb.choice.n2=calloc(1,sizeof(*srs_res0->transmissionComb.choice.n2)); + srs_res0->transmissionComb.choice.n2->combOffset_n2=0; + srs_res0->transmissionComb.choice.n2->cyclicShift_n2=0; + srs_res0->resourceMapping.startPosition=2; + srs_res0->resourceMapping.nrofSymbols=NR_SRS_Resource__resourceMapping__nrofSymbols_n1; + srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; + srs_res0->freqDomainPosition=0; + srs_res0->freqDomainShift=0; + srs_res0->freqHopping.c_SRS = 61; + srs_res0->freqHopping.b_SRS=0; + srs_res0->freqHopping.b_hop=0; + srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; + srs_res0->resourceType.present= NR_SRS_Resource__resourceType_PR_aperiodic; + srs_res0->resourceType.choice.aperiodic=calloc(1,sizeof(*srs_res0->resourceType.choice.aperiodic)); + srs_res0->sequenceId=40; + srs_res0->spatialRelationInfo=calloc(1,sizeof(*srs_res0->spatialRelationInfo)); + srs_res0->spatialRelationInfo->servingCellId=NULL; + srs_res0->spatialRelationInfo->referenceSignal.present=NR_SRS_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; + srs_res0->spatialRelationInfo->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); + NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); + ubwp->bwp_Id=1; + ubwp->bwp_Common = calloc(1,sizeof(*ubwp->bwp_Common)); + // copy bwp_Common from Initial UL BWP except for bandwidth + memcpy((void*)&ubwp->bwp_Common->genericParameters, + (void*)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, + sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); + ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); + + ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; + ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; + ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; + + ubwp->bwp_Dedicated = calloc(1,sizeof(*ubwp->bwp_Dedicated)); + ubwp->bwp_Dedicated->pucch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pucch_Config)); + ubwp->bwp_Dedicated->pucch_Config->present = NR_SetupRelease_PUCCH_Config_PR_setup; + NR_PUCCH_Config_t *pucch_Config = calloc(1,sizeof(*pucch_Config)); + ubwp->bwp_Dedicated->pucch_Config->choice.setup=pucch_Config; + pucch_Config->resourceSetToAddModList = calloc(1,sizeof(*pucch_Config->resourceSetToAddModList)); + pucch_Config->resourceSetToReleaseList = NULL; + NR_PUCCH_ResourceSet_t *pucchresset0=calloc(1,sizeof(*pucchresset0)); + NR_PUCCH_ResourceSet_t *pucchresset1=calloc(1,sizeof(*pucchresset1)); + pucchresset0->pucch_ResourceSetId = 0; + NR_PUCCH_ResourceId_t *pucchresset0id0=calloc(1,sizeof(*pucchresset0id0)); + NR_PUCCH_ResourceId_t *pucchresset0id1=calloc(1,sizeof(*pucchresset0id1)); + *pucchresset0id0=1; + ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id0); + *pucchresset0id1=2; + ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id1); + pucchresset0->maxPayloadMinus1=NULL; + + ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset0); + + pucchresset1->pucch_ResourceSetId = 1; + NR_PUCCH_ResourceId_t *pucchresset1id0=calloc(1,sizeof(*pucchresset1id0)); + NR_PUCCH_ResourceId_t *pucchresset1id1=calloc(1,sizeof(*pucchresset1id1)); + *pucchresset1id0=3; + ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id0); + *pucchresset1id1=4; + ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id1); + pucchresset1->maxPayloadMinus1=NULL; + ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset1); + + pucch_Config->resourceToAddModList = calloc(1,sizeof(*pucch_Config->resourceToAddModList)); + pucch_Config->resourceToReleaseList = NULL; + NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0)); + NR_PUCCH_Resource_t *pucchres1=calloc(1,sizeof(*pucchres1)); + NR_PUCCH_Resource_t *pucchres2=calloc(1,sizeof(*pucchres2)); + NR_PUCCH_Resource_t *pucchres3=calloc(1,sizeof(*pucchres3)); + pucchres0->pucch_ResourceId=1; + pucchres0->startingPRB=48; + pucchres0->intraSlotFrequencyHopping=NULL; + pucchres0->secondHopPRB=NULL; + pucchres0->format.present= NR_PUCCH_Resource__format_PR_format0; + pucchres0->format.choice.format0=calloc(1,sizeof(*pucchres0->format.choice.format0)); + pucchres0->format.choice.format0->initialCyclicShift=0; + pucchres0->format.choice.format0->nrofSymbols=1; + pucchres0->format.choice.format0->startingSymbolIndex=13; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres0); + + pucchres1->pucch_ResourceId=2; + pucchres1->startingPRB=48; + pucchres1->intraSlotFrequencyHopping=NULL; + pucchres1->secondHopPRB=NULL; + pucchres1->format.present= NR_PUCCH_Resource__format_PR_format0; + pucchres1->format.choice.format0=calloc(1,sizeof(*pucchres1->format.choice.format0)); + pucchres1->format.choice.format0->initialCyclicShift=0; + pucchres1->format.choice.format0->nrofSymbols=1; + pucchres1->format.choice.format0->startingSymbolIndex=12; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres1); + + pucchres2->pucch_ResourceId=3; + pucchres2->startingPRB=40; + pucchres2->intraSlotFrequencyHopping=NULL; + pucchres2->secondHopPRB=NULL; + pucchres2->format.present= NR_PUCCH_Resource__format_PR_format2; + pucchres2->format.choice.format2=calloc(1,sizeof(*pucchres2->format.choice.format2)); + pucchres2->format.choice.format2->nrofPRBs=16; + pucchres2->format.choice.format2->nrofSymbols=1; + pucchres2->format.choice.format2->startingSymbolIndex=13; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres2); + + pucchres3->pucch_ResourceId=4; + pucchres3->startingPRB=40; + pucchres3->intraSlotFrequencyHopping=NULL; + pucchres3->secondHopPRB=NULL; + pucchres3->format.present= NR_PUCCH_Resource__format_PR_format2; + pucchres3->format.choice.format2=calloc(1,sizeof(*pucchres3->format.choice.format2)); + pucchres3->format.choice.format2->nrofPRBs=16; + pucchres3->format.choice.format2->nrofSymbols=1; + pucchres3->format.choice.format2->startingSymbolIndex=12; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres3); + + pucch_Config->format2=calloc(1,sizeof(*pucch_Config->format2)); + pucch_Config->format2->present=NR_SetupRelease_PUCCH_FormatConfig_PR_setup; + NR_PUCCH_FormatConfig_t *pucchfmt2 = calloc(1,sizeof(*pucchfmt2)); + pucch_Config->format2->choice.setup = pucchfmt2; + pucchfmt2->interslotFrequencyHopping=NULL; + pucchfmt2->additionalDMRS=NULL; + pucchfmt2->maxCodeRate=calloc(1,sizeof(*pucchfmt2->maxCodeRate)); + *pucchfmt2->maxCodeRate=NR_PUCCH_MaxCodeRate_zeroDot15; + pucchfmt2->nrofSlots=NULL; + pucchfmt2->pi2BPSK=NULL; + pucchfmt2->simultaneousHARQ_ACK_CSI=NULL; + pucch_Config->schedulingRequestResourceToAddModList=NULL; + pucch_Config->schedulingRequestResourceToReleaseList=NULL; + pucch_Config->multi_CSI_PUCCH_ResourceList=NULL; + pucch_Config->dl_DataToUL_ACK = calloc(1,sizeof(*pucch_Config->dl_DataToUL_ACK)); + long *delay[8]; + for (int i=0;i<8;i++) { + delay[i] = calloc(1,sizeof(*delay[i])); + *delay[i] = (i<6) ? (i+2) : 0; + ASN_SEQUENCE_ADD(&pucch_Config->dl_DataToUL_ACK->list,delay[i]); + } + pucch_Config->spatialRelationInfoToAddModList = calloc(1,sizeof(*pucch_Config->spatialRelationInfoToAddModList)); + NR_PUCCH_SpatialRelationInfo_t *pucchspatial = calloc(1,sizeof(*pucchspatial)); + pucchspatial->pucch_SpatialRelationInfoId = 1; + pucchspatial->servingCellId = NULL; + pucchspatial->referenceSignal.present = NR_PUCCH_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; + pucchspatial->referenceSignal.choice.csi_RS_Index = 0; + pucchspatial->pucch_PathlossReferenceRS_Id = 0; + pucchspatial->p0_PUCCH_Id = 1; + pucchspatial->closedLoopIndex = NR_PUCCH_SpatialRelationInfo__closedLoopIndex_i0; + ASN_SEQUENCE_ADD(&pucch_Config->spatialRelationInfoToAddModList->list,pucchspatial); + pucch_Config->spatialRelationInfoToReleaseList=NULL; + pucch_Config->pucch_PowerControl=calloc(1,sizeof(*pucch_Config->pucch_PowerControl)); + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = 0; + pucch_Config->pucch_PowerControl->p0_Set = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->p0_Set)); + NR_P0_PUCCH_t *p00 = calloc(1,sizeof(*p00)); + p00->p0_PUCCH_Id=1; + p00->p0_PUCCH_Value = 0; + ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->p0_Set->list,p00); + pucch_Config->pucch_PowerControl->pathlossReferenceRSs = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->pathlossReferenceRSs)); + NR_PUCCH_PathlossReferenceRS_t *pucchPLRef=calloc(1,sizeof(*pucchPLRef)); + pucchPLRef->pucch_PathlossReferenceRS_Id=0; + pucchPLRef->referenceSignal.present = NR_PUCCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; + pucchPLRef->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->pathlossReferenceRSs->list,pucchPLRef); + + // copy pusch_Config from dedicated initialBWP + ubwp->bwp_Dedicated->pusch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pusch_Config)); + ubwp->bwp_Dedicated->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; + ubwp->bwp_Dedicated->pusch_Config->choice.setup = pusch_Config; + + ubwp->bwp_Dedicated->configuredGrantConfig = NULL; + ubwp->bwp_Dedicated->srs_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->srs_Config)); + ubwp->bwp_Dedicated->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; + ubwp->bwp_Dedicated->srs_Config->choice.setup = srs_Config; + + ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; + + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); + NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; + pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; + pdsch_servingcellconfig->xOverhead = NULL; + pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; + pdsch_servingcellconfig->pucch_Cell= NULL; + pdsch_servingcellconfig->ext1=calloc(1,sizeof(*pdsch_servingcellconfig->ext1)); + pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1,sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers)); + *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; + pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + + + NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; + csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); + + NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); + nzpres0->nzp_CSI_RS_ResourceId=0; + nzpres0->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf = calloc(1,1); + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.size = 1; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.bits_unused = 2; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf[0]=1<<2; + nzpres0->resourceMapping.nrofPorts = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__nrofPorts_p1 : NR_CSI_RS_ResourceMapping__nrofPorts_p2; + nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain=7; + nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres0->resourceMapping.cdm_Type = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__cdm_Type_noCDM : NR_CSI_RS_ResourceMapping__cdm_Type_fd_CDM2; + nzpres0->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_one; + nzpres0->resourceMapping.density.choice.one=(NULL_t)0; + nzpres0->resourceMapping.freqBand.startingRB=0; + nzpres0->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres0->powerControlOffset=13; + nzpres0->powerControlOffsetSS=NULL; + nzpres0->scramblingID=40; + nzpres0->periodicityAndOffset = calloc(1,sizeof(*nzpres0->periodicityAndOffset)); + nzpres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; + nzpres0->periodicityAndOffset->choice.slots320 = 2; + nzpres0->qcl_InfoPeriodicCSI_RS=NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres0); + + if (n_physical_antenna_ports > 1) { + NR_NZP_CSI_RS_Resource_t *nzpres2 = calloc(1,sizeof(*nzpres2)); + nzpres2->nzp_CSI_RS_ResourceId=2; + nzpres2->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres2->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres2->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres2->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres2->resourceMapping.density.choice.three=(NULL_t)0; + nzpres2->resourceMapping.freqBand.startingRB=0; + nzpres2->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres2->powerControlOffset=0; + nzpres2->powerControlOffsetSS=calloc(1,sizeof(*nzpres2->powerControlOffsetSS)); + *nzpres2->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres2->scramblingID=40; + nzpres2->periodicityAndOffset = calloc(1,sizeof(*nzpres2->periodicityAndOffset)); + nzpres2->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres2->periodicityAndOffset->choice.slots160 = 25; + nzpres2->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres2->qcl_InfoPeriodicCSI_RS)); + *nzpres2->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres2); + + + NR_NZP_CSI_RS_Resource_t *nzpres3 = calloc(1,sizeof(*nzpres3)); + nzpres3->nzp_CSI_RS_ResourceId=3; + nzpres3->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres3->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres3->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres3->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres3->resourceMapping.density.choice.three=(NULL_t)0; + nzpres3->resourceMapping.freqBand.startingRB=0; + nzpres3->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres3->powerControlOffset=0; + nzpres3->powerControlOffsetSS=calloc(1,sizeof(*nzpres3->powerControlOffsetSS)); + *nzpres3->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres3->scramblingID=40; + nzpres3->periodicityAndOffset = calloc(1,sizeof(*nzpres3->periodicityAndOffset)); + nzpres3->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres3->periodicityAndOffset->choice.slots160 = 25; + nzpres3->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres3->qcl_InfoPeriodicCSI_RS)); + *nzpres3->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres3); + } + if (n_physical_antenna_ports > 3) { + NR_NZP_CSI_RS_Resource_t *nzpres4 = calloc(1,sizeof(*nzpres4)); + nzpres4->nzp_CSI_RS_ResourceId=4; + nzpres4->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres4->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres4->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres4->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres4->resourceMapping.density.choice.three=(NULL_t)0; + nzpres4->resourceMapping.freqBand.startingRB=0; + nzpres4->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres4->powerControlOffset=0; + nzpres4->powerControlOffsetSS=calloc(1,sizeof(*nzpres4->powerControlOffsetSS)); + *nzpres4->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres4->scramblingID=40; + nzpres4->periodicityAndOffset = calloc(1,sizeof(*nzpres4->periodicityAndOffset)); + nzpres4->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres4->periodicityAndOffset->choice.slots160 = 26; + nzpres4->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres4->qcl_InfoPeriodicCSI_RS)); + *nzpres4->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres4); + + NR_NZP_CSI_RS_Resource_t *nzpres5 = calloc(1,sizeof(*nzpres5)); + nzpres5->nzp_CSI_RS_ResourceId=5; + nzpres5->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres5->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres5->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres5->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres5->resourceMapping.density.choice.three=(NULL_t)0; + nzpres5->resourceMapping.freqBand.startingRB=0; + nzpres5->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres5->powerControlOffset=0; + nzpres5->powerControlOffsetSS=calloc(1,sizeof(*nzpres5->powerControlOffsetSS)); + *nzpres5->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres5->scramblingID=40; + nzpres5->periodicityAndOffset = calloc(1,sizeof(*nzpres5->periodicityAndOffset)); + nzpres5->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres5->periodicityAndOffset->choice.slots160 = 26; + nzpres5->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres5->qcl_InfoPeriodicCSI_RS)); + *nzpres5->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres5); + } + if (n_physical_antenna_ports > 7) { + NR_NZP_CSI_RS_Resource_t *nzpres6 = calloc(1,sizeof(*nzpres6)); + nzpres6->nzp_CSI_RS_ResourceId=6; + nzpres6->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres6->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres6->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres6->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres6->resourceMapping.density.choice.three=(NULL_t)0; + nzpres6->resourceMapping.freqBand.startingRB=0; + nzpres6->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres6->powerControlOffset=0; + nzpres6->powerControlOffsetSS=calloc(1,sizeof(*nzpres6->powerControlOffsetSS)); + *nzpres6->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres6->scramblingID=40; + nzpres6->periodicityAndOffset = calloc(1,sizeof(*nzpres6->periodicityAndOffset)); + nzpres6->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres6->periodicityAndOffset->choice.slots160 = 25; + nzpres6->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres6->qcl_InfoPeriodicCSI_RS)); + *nzpres6->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres6); + + NR_NZP_CSI_RS_Resource_t *nzpres7 = calloc(1,sizeof(*nzpres7)); + nzpres7->nzp_CSI_RS_ResourceId=7; + nzpres7->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres7->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres7->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres7->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres7->resourceMapping.density.choice.three=(NULL_t)0; + nzpres7->resourceMapping.freqBand.startingRB=0; + nzpres7->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres7->powerControlOffset=0; + nzpres7->powerControlOffsetSS=calloc(1,sizeof(*nzpres7->powerControlOffsetSS)); + *nzpres7->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres7->scramblingID=40; + nzpres7->periodicityAndOffset = calloc(1,sizeof(*nzpres7->periodicityAndOffset)); + nzpres7->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres7->periodicityAndOffset->choice.slots160 = 25; + nzpres7->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres7->qcl_InfoPeriodicCSI_RS)); + *nzpres7->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres7); + NR_NZP_CSI_RS_Resource_t *nzpres8 = calloc(1,sizeof(*nzpres8)); + nzpres8->nzp_CSI_RS_ResourceId=8; + nzpres8->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres8->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres8->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres8->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres8->resourceMapping.density.choice.three=(NULL_t)0; + nzpres8->resourceMapping.freqBand.startingRB=0; + nzpres8->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres8->powerControlOffset=0; + nzpres8->powerControlOffsetSS=calloc(1,sizeof(*nzpres8->powerControlOffsetSS)); + *nzpres8->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres8->scramblingID=40; + nzpres8->periodicityAndOffset = calloc(1,sizeof(*nzpres8->periodicityAndOffset)); + nzpres8->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres8->periodicityAndOffset->choice.slots160 = 26; + nzpres8->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres8->qcl_InfoPeriodicCSI_RS)); + *nzpres8->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres8); + + NR_NZP_CSI_RS_Resource_t *nzpres9 = calloc(1,sizeof(*nzpres9)); + nzpres9->nzp_CSI_RS_ResourceId=9; + nzpres9->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres9->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres9->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres9->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres9->resourceMapping.density.choice.three=(NULL_t)0; + nzpres9->resourceMapping.freqBand.startingRB=0; + nzpres9->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres9->powerControlOffset=0; + nzpres9->powerControlOffsetSS=calloc(1,sizeof(*nzpres9->powerControlOffsetSS)); + *nzpres9->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres9->scramblingID=40; + nzpres9->periodicityAndOffset = calloc(1,sizeof(*nzpres9->periodicityAndOffset)); + nzpres9->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres9->periodicityAndOffset->choice.slots160 = 26; + nzpres9->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres9->qcl_InfoPeriodicCSI_RS)); + *nzpres9->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres9); + } + if (n_physical_antenna_ports > 15) { + NR_NZP_CSI_RS_Resource_t *nzpres10 = calloc(1,sizeof(*nzpres10)); + nzpres10->nzp_CSI_RS_ResourceId=10; + nzpres10->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres10->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres10->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres10->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres10->resourceMapping.density.choice.three=(NULL_t)0; + nzpres10->resourceMapping.freqBand.startingRB=0; + nzpres10->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres10->powerControlOffset=0; + nzpres10->powerControlOffsetSS=calloc(1,sizeof(*nzpres10->powerControlOffsetSS)); + *nzpres10->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres10->scramblingID=40; + nzpres10->periodicityAndOffset = calloc(1,sizeof(*nzpres10->periodicityAndOffset)); + nzpres10->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres10->periodicityAndOffset->choice.slots160 = 25; + nzpres10->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres10->qcl_InfoPeriodicCSI_RS)); + *nzpres10->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres10); + + NR_NZP_CSI_RS_Resource_t *nzpres11 = calloc(1,sizeof(*nzpres11)); + nzpres11->nzp_CSI_RS_ResourceId=11; + nzpres11->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres11->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres11->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres11->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres11->resourceMapping.density.choice.three=(NULL_t)0; + nzpres11->resourceMapping.freqBand.startingRB=0; + nzpres11->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres11->powerControlOffset=0; + nzpres11->powerControlOffsetSS=calloc(1,sizeof(*nzpres11->powerControlOffsetSS)); + *nzpres11->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres11->scramblingID=40; + nzpres11->periodicityAndOffset = calloc(1,sizeof(*nzpres11->periodicityAndOffset)); + nzpres11->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres11->periodicityAndOffset->choice.slots160 = 25; + nzpres11->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres11->qcl_InfoPeriodicCSI_RS)); + *nzpres11->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres11); + NR_NZP_CSI_RS_Resource_t *nzpres12 = calloc(1,sizeof(*nzpres12)); + nzpres12->nzp_CSI_RS_ResourceId=12; + nzpres12->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres12->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres12->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres12->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres12->resourceMapping.density.choice.three=(NULL_t)0; + nzpres12->resourceMapping.freqBand.startingRB=0; + nzpres12->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres12->powerControlOffset=0; + nzpres12->powerControlOffsetSS=calloc(1,sizeof(*nzpres12->powerControlOffsetSS)); + *nzpres12->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres12->scramblingID=40; + nzpres12->periodicityAndOffset = calloc(1,sizeof(*nzpres12->periodicityAndOffset)); + nzpres12->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres12->periodicityAndOffset->choice.slots160 = 26; + nzpres12->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres12->qcl_InfoPeriodicCSI_RS)); + *nzpres12->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres12); + + NR_NZP_CSI_RS_Resource_t *nzpres13 = calloc(1,sizeof(*nzpres13)); + nzpres13->nzp_CSI_RS_ResourceId=13; + nzpres13->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres13->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres13->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres13->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres13->resourceMapping.density.choice.three=(NULL_t)0; + nzpres13->resourceMapping.freqBand.startingRB=0; + nzpres13->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres13->powerControlOffset=0; + nzpres13->powerControlOffsetSS=calloc(1,sizeof(*nzpres13->powerControlOffsetSS)); + *nzpres13->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres13->scramblingID=40; + nzpres13->periodicityAndOffset = calloc(1,sizeof(*nzpres13->periodicityAndOffset)); + nzpres13->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres13->periodicityAndOffset->choice.slots160 = 26; + nzpres13->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres13->qcl_InfoPeriodicCSI_RS)); + *nzpres13->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres13); + NR_NZP_CSI_RS_Resource_t *nzpres14 = calloc(1,sizeof(*nzpres14)); + nzpres14->nzp_CSI_RS_ResourceId=14; + nzpres14->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres14->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres14->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres14->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres14->resourceMapping.density.choice.three=(NULL_t)0; + nzpres14->resourceMapping.freqBand.startingRB=0; + nzpres14->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres14->powerControlOffset=0; + nzpres14->powerControlOffsetSS=calloc(1,sizeof(*nzpres14->powerControlOffsetSS)); + *nzpres14->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres14->scramblingID=40; + nzpres14->periodicityAndOffset = calloc(1,sizeof(*nzpres14->periodicityAndOffset)); + nzpres14->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres14->periodicityAndOffset->choice.slots160 = 25; + nzpres14->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres14->qcl_InfoPeriodicCSI_RS)); + *nzpres14->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres14); + + NR_NZP_CSI_RS_Resource_t *nzpres15 = calloc(1,sizeof(*nzpres15)); + nzpres15->nzp_CSI_RS_ResourceId=15; + nzpres15->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres15->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres15->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres15->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres15->resourceMapping.density.choice.three=(NULL_t)0; + nzpres15->resourceMapping.freqBand.startingRB=0; + nzpres15->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres15->powerControlOffset=0; + nzpres15->powerControlOffsetSS=calloc(1,sizeof(*nzpres15->powerControlOffsetSS)); + *nzpres15->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres15->scramblingID=40; + nzpres15->periodicityAndOffset = calloc(1,sizeof(*nzpres15->periodicityAndOffset)); + nzpres15->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres15->periodicityAndOffset->choice.slots160 = 25; + nzpres15->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres15->qcl_InfoPeriodicCSI_RS)); + *nzpres15->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres15); + NR_NZP_CSI_RS_Resource_t *nzpres16 = calloc(1,sizeof(*nzpres16)); + nzpres16->nzp_CSI_RS_ResourceId=16; + nzpres16->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres16->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain=5; + nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres16->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres16->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres16->resourceMapping.density.choice.three=(NULL_t)0; + nzpres16->resourceMapping.freqBand.startingRB=0; + nzpres16->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres16->powerControlOffset=0; + nzpres16->powerControlOffsetSS=calloc(1,sizeof(*nzpres16->powerControlOffsetSS)); + *nzpres16->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres16->scramblingID=40; + nzpres16->periodicityAndOffset = calloc(1,sizeof(*nzpres16->periodicityAndOffset)); + nzpres16->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres16->periodicityAndOffset->choice.slots160 = 26; + nzpres16->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres16->qcl_InfoPeriodicCSI_RS)); + *nzpres16->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres16); + + NR_NZP_CSI_RS_Resource_t *nzpres17 = calloc(1,sizeof(*nzpres17)); + nzpres17->nzp_CSI_RS_ResourceId=9; + nzpres17->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres17->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain=9; + nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres17->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres17->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres17->resourceMapping.density.choice.three=(NULL_t)0; + nzpres17->resourceMapping.freqBand.startingRB=0; + nzpres17->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres17->powerControlOffset=0; + nzpres17->powerControlOffsetSS=calloc(1,sizeof(*nzpres17->powerControlOffsetSS)); + *nzpres17->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres17->scramblingID=40; + nzpres17->periodicityAndOffset = calloc(1,sizeof(*nzpres17->periodicityAndOffset)); + nzpres17->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres17->periodicityAndOffset->choice.slots160 = 26; + nzpres17->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres17->qcl_InfoPeriodicCSI_RS)); + *nzpres17->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres17); + } + + if (n_physical_antenna_ports > 16) AssertFatal(1==0,"Fill in for more than 16 antenna elements\n"); + + csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList)); + csi_MeasConfig->nzp_CSI_RS_ResourceSetToReleaseList = NULL; + NR_NZP_CSI_RS_ResourceSet_t *nzpresset0=calloc(1,sizeof(*nzpresset0)); + nzpresset0->nzp_CSI_ResourceSetId=0; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset00=calloc(1,sizeof(*nzpresset00)); + *nzpresset00=0; + ASN_SEQUENCE_ADD(&nzpresset0->nzp_CSI_RS_Resources.list,nzpresset00); + nzpresset0->repetition=NULL; + nzpresset0->aperiodicTriggeringOffset=NULL; + nzpresset0->trs_Info=NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset0); + if (n_physical_antenna_ports > 1) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset3=calloc(1,sizeof(*nzpresset3)); + nzpresset3->nzp_CSI_ResourceSetId=3; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset30=calloc(1,sizeof(*nzpresset30)); + *nzpresset30=2; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset30); + if (n_physical_antenna_ports > 3) { + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset31=calloc(1,sizeof(*nzpresset31)); + *nzpresset31=3; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset31); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset32=calloc(1,sizeof(*nzpresset32)); + *nzpresset32=4; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset32); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset33=calloc(1,sizeof(*nzpresset33)); + *nzpresset33=5; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset33); + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); + } + nzpresset3->repetition=calloc(1,sizeof(*nzpresset3->repetition)); + *nzpresset3->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset3->aperiodicTriggeringOffset=NULL; + nzpresset3->trs_Info=calloc(1,sizeof(*nzpresset3->trs_Info)); + *nzpresset3->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); + } + + if (n_physical_antenna_ports > 7) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset4=calloc(1,sizeof(*nzpresset4)); + nzpresset4->nzp_CSI_ResourceSetId=4; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset40=calloc(1,sizeof(*nzpresset40)); + *nzpresset40=6; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset40); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset41=calloc(1,sizeof(*nzpresset41)); + *nzpresset41=7; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset41); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset42=calloc(1,sizeof(*nzpresset42)); + *nzpresset42=8; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset42); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset43=calloc(1,sizeof(*nzpresset43)); + *nzpresset43=9; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset43); + nzpresset4->repetition=calloc(1,sizeof(*nzpresset4->repetition)); + *nzpresset4->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset4->aperiodicTriggeringOffset=NULL; + nzpresset4->trs_Info=calloc(1,sizeof(*nzpresset4->trs_Info)); + *nzpresset4->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset4); + } + if (n_physical_antenna_ports > 15) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset5=calloc(1,sizeof(*nzpresset5)); + nzpresset5->nzp_CSI_ResourceSetId=5; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset50=calloc(1,sizeof(*nzpresset50)); + *nzpresset50=10; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset50); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset51=calloc(1,sizeof(*nzpresset51)); + *nzpresset51=11; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset51); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset52=calloc(1,sizeof(*nzpresset52)); + *nzpresset52=12; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset52); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset53=calloc(1,sizeof(*nzpresset53)); + *nzpresset53=13; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset53); + nzpresset5->repetition=calloc(1,sizeof(*nzpresset5->repetition)); + *nzpresset5->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset5->aperiodicTriggeringOffset=NULL; + nzpresset5->trs_Info=calloc(1,sizeof(*nzpresset5->trs_Info)); + *nzpresset5->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset5); + } + + csi_MeasConfig->csi_IM_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceToAddModList)); + csi_MeasConfig->csi_IM_ResourceToReleaseList = NULL; + NR_CSI_IM_Resource_t *imres0 = calloc(1,sizeof(*imres0)); + imres0->csi_IM_ResourceId=0; + imres0->csi_IM_ResourceElementPattern=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern)); + imres0->csi_IM_ResourceElementPattern->present = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern_PR_pattern1 ; + imres0->csi_IM_ResourceElementPattern->choice.pattern1=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern->choice.pattern1)); + imres0->csi_IM_ResourceElementPattern->choice.pattern1->subcarrierLocation_p1 = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern__pattern1__subcarrierLocation_p1_s4; + imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; + imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); + imres0->freqBand->startingRB=0; + imres0->freqBand->nrofRBs=276; + imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); + imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; + imres0->periodicityAndOffset->choice.slots320 = 2; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceToAddModList->list,imres0); + csi_MeasConfig->csi_IM_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceSetToAddModList)); + csi_MeasConfig->csi_IM_ResourceSetToReleaseList = NULL; + NR_CSI_IM_ResourceSet_t *imresset0 = calloc(1,sizeof(*imresset0)); + imresset0->csi_IM_ResourceSetId=0; + NR_CSI_IM_ResourceId_t *imresset00=calloc(1,sizeof(*imresset00)); + *imresset00=0; + ASN_SEQUENCE_ADD(&imresset0->csi_IM_Resources.list,imresset00); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceSetToAddModList->list,imresset0); + + csi_MeasConfig->csi_SSB_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_SSB_ResourceSetToAddModList)); + csi_MeasConfig->csi_SSB_ResourceSetToReleaseList = NULL; + NR_CSI_SSB_ResourceSet_t *ssbresset0 = calloc(1,sizeof(*ssbresset0)); + ssbresset0->csi_SSB_ResourceSetId=0; + NR_SSB_Index_t *ssbresset00=calloc(1,sizeof(*ssbresset00)); + *ssbresset00=0; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset00); + if (n_physical_antenna_ports > 1) { + NR_SSB_Index_t *ssbresset01=calloc(1,sizeof(*ssbresset01)); + *ssbresset01=1; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset01); + } + if (n_physical_antenna_ports > 3) { + NR_SSB_Index_t *ssbresset02=calloc(1,sizeof(*ssbresset02)); + *ssbresset02=2; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset02); + NR_SSB_Index_t *ssbresset03=calloc(1,sizeof(*ssbresset03)); + *ssbresset03=3; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset03); + } + if (n_physical_antenna_ports > 7) { + NR_SSB_Index_t *ssbresset04=calloc(1,sizeof(*ssbresset04)); + *ssbresset04=4; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset04); + NR_SSB_Index_t *ssbresset05=calloc(1,sizeof(*ssbresset05)); + *ssbresset05=5; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset05); + NR_SSB_Index_t *ssbresset06=calloc(1,sizeof(*ssbresset06)); + *ssbresset06=6; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset06); + NR_SSB_Index_t *ssbresset07=calloc(1,sizeof(*ssbresset07)); + *ssbresset07=7; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset07); + } + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_SSB_ResourceSetToAddModList->list,ssbresset0); + + csi_MeasConfig->csi_ResourceConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ResourceConfigToAddModList)); + csi_MeasConfig->csi_ResourceConfigToReleaseList = NULL; + NR_CSI_ResourceConfig_t *csires0 = calloc(1,sizeof(*csires0)); + csires0->csi_ResourceConfigId=0; + csires0->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires00 = calloc(1,sizeof(*csires00)); + *csires00 = 0; + ASN_SEQUENCE_ADD(&csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires00); + csires0->bwp_Id = 1; + csires0->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires0); + + NR_CSI_ResourceConfig_t *csires11 = calloc(1,sizeof(*csires11)); + csires11->csi_ResourceConfigId=11; + csires11->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_csi_IM_ResourceSetList; + csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList = calloc(1,sizeof(*csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList)); + NR_NZP_CSI_RS_ResourceSetId_t *csires110 = calloc(1,sizeof(*csires110)); + *csires110 = 0; + ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); + csires11->bwp_Id = 1; + csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + + NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); + csires10->csi_ResourceConfigId=10; + csires10->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires100 = calloc(1,sizeof(*csires100)); + *csires100 = 0; + ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); + csires10->bwp_Id = 1; + csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + + NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); + csires2->csi_ResourceConfigId=2; + csires2->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires20 = calloc(1,sizeof(*csires20)); + *csires20 = 0; + ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); + csires2->bwp_Id = 1; + csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + + NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); + csires3->csi_ResourceConfigId=3; + csires3->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires30 = calloc(1,sizeof(*csires30)); + *csires30 = 0; + ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); + csires3->bwp_Id = 1; + csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + + NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); + csires4->csi_ResourceConfigId=4; + csires4->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires40 = calloc(1,sizeof(*csires40)); + *csires40 = 0; + ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); + csires4->bwp_Id = 1; + csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + + NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); + csires5->csi_ResourceConfigId=5; + csires5->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires50 = calloc(1,sizeof(*csires50)); + *csires50 = 0; + ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); + csires5->bwp_Id = 1; + csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + + NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); + csires6->csi_ResourceConfigId=6; + csires6->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires60 = calloc(1,sizeof(*csires60)); + *csires60 = 0; + ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); + csires6->bwp_Id = 1; + csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + + NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); + csires7->csi_ResourceConfigId=7; + csires7->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires70 = calloc(1,sizeof(*csires70)); + *csires70 = 0; + ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); + csires7->bwp_Id = 1; + csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + + NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); + csires8->csi_ResourceConfigId=8; + csires8->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires80 = calloc(1,sizeof(*csires80)); + *csires80 = 0; + ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); + csires8->bwp_Id = 1; + csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + + NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); + csires9->csi_ResourceConfigId=9; + csires9->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires90 = calloc(1,sizeof(*csires90)); + *csires90 = 0; + ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); + csires9->bwp_Id = 1; + csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + + csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); + csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; + NR_CSI_ReportConfig_t *csirep0 = calloc(1,sizeof(*csirep0)); + csirep0->reportConfigId=0; + csirep0->carrier=NULL; + csirep0->resourcesForChannelMeasurement=0; + csirep0->csi_IM_ResourcesForInterference=calloc(1,sizeof(*csirep0->csi_IM_ResourcesForInterference)); + *csirep0->csi_IM_ResourcesForInterference=11; + csirep0->nzp_CSI_RS_ResourcesForInterference=NULL; + csirep0->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; + csirep0->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep0->reportConfigType.choice.periodic)); + csirep0->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; + csirep0->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 9; + + NR_PUCCH_CSI_Resource_t *pucchcsires0 = calloc(1,sizeof(*pucchcsires0)); + pucchcsires0->uplinkBandwidthPartId=1; + pucchcsires0->pucch_Resource=11; + ASN_SEQUENCE_ADD(&csirep0->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires0); + csirep0->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI; + csirep0->reportQuantity.choice.cri_RI_PMI_CQI = (NULL_t)0; + csirep0->reportFreqConfiguration = calloc(1,sizeof(*csirep0->reportFreqConfiguration)); + csirep0->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; + csirep0->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; + csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); + + + AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); + int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id-1]->bwp_Common->genericParameters.locationAndBandwidth,275); + int sbsize = get_subband_size(NPRB,0); + int numsb = NPRB/sbsize; + if (NPRB%sbsize == 0) numsb++; + csirep0->reportFreqConfiguration->csi_ReportingBand->present= NR_CSI_ReportConfig__reportFreqConfiguration__csi_ReportingBand_PR_NOTHING+(numsb-2); + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size=numsb/8; + if ((numsb&7) > 0) csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size++; + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused = (8-(numsb&7))&7; + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf=malloc(csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size); + for (int i=0;ireportFreqConfiguration->csi_ReportingBand->choice.subbands18.size;i++) + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[i]=0xff; + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size-1]&=~((1<reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused)-1); + + csirep0->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; + csirep0->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; + csirep0->codebookConfig=calloc(1,sizeof(*csirep0->codebookConfig)); + csirep0->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; + csirep0->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1)); + csirep0->codebookConfig->codebookType.choice.type1->subType.present = NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present=NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= + calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; + //'111111'B + + + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B + + csirep0->codebookConfig->codebookType.choice.type1->codebookMode=1; + csirep0->dummy = NULL; + csirep0->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; + csirep0->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep0->groupBasedBeamReporting.choice.disabled)); + csirep0->groupBasedBeamReporting.choice.disabled->nrofReportedRS = NULL; + csirep0->cqi_Table = calloc(1,sizeof(*csirep0->cqi_Table)); + *csirep0->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; + csirep0->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; + csirep0->non_PMI_PortIndication = NULL; + csirep0->ext1 = NULL; + + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep0); + + NR_CSI_ReportConfig_t *csirep1 = calloc(1,sizeof(*csirep1)); + csirep1->reportConfigId=2; + csirep1->carrier=NULL; + csirep1->resourcesForChannelMeasurement=initial_csi_index; + csirep1->csi_IM_ResourcesForInterference=NULL; + csirep1->nzp_CSI_RS_ResourcesForInterference=NULL; + csirep1->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; + csirep1->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep1->reportConfigType.choice.periodic)); + csirep1->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; + csirep1->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 49; + NR_PUCCH_CSI_Resource_t *pucchcsires1 = calloc(1,sizeof(*pucchcsires1)); + pucchcsires1->uplinkBandwidthPartId=1; + pucchcsires1->pucch_Resource=12; + ASN_SEQUENCE_ADD(&csirep1->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires1); + csirep1->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP; + csirep1->reportQuantity.choice.ssb_Index_RSRP=(NULL_t)0; + csirep1->reportFreqConfiguration = calloc(1,sizeof(*csirep1->reportFreqConfiguration)); + csirep1->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; + csirep1->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; + csirep1->reportFreqConfiguration->csi_ReportingBand=NULL; + csirep1->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; + csirep1->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; + csirep1->codebookConfig=calloc(1,sizeof(*csirep1->codebookConfig)); + csirep1->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; + csirep1->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1)); + csirep1->codebookConfig->codebookType.choice.type1->subType.present=NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present=NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= + calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; + //'111111'B + + + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B + + csirep1->codebookConfig->codebookType.choice.type1->codebookMode=1; + csirep1->dummy = NULL; + csirep1->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; + csirep1->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled)); + csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS = calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS)); + *csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS=NR_CSI_ReportConfig__groupBasedBeamReporting__disabled__nrofReportedRS_n2; + // this corresponds to: + //if the UE is configured with the higher layer parameter groupBasedBeamReporting set to 'disabled', the UE is not required to update measurements for more than 64 CSI-RS and/or SSB resources, and the UE shall report in a single report nrofReportedRS (higher layer configured) different CRI or SSBRI for each report setting. + + csirep1->cqi_Table = calloc(1,sizeof(*csirep1->cqi_Table)); + *csirep1->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; + csirep1->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; + csirep1->non_PMI_PortIndication = NULL; + csirep1->ext1 = NULL; + + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep1); + + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->sCellDeactivationTimer=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->tag_Id=0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->dummy=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; + +} +void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon, + NR_RRCReconfiguration_IEs_t *reconfig, + NR_CellGroupConfig_t *secondaryCellGroup, + int n_physical_antenna_ports, + int initial_csi_index) { + + AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); + AssertFatal(reconfig!=NULL,"reconfig is null\n"); + AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); + + // radioBearerConfig + reconfig->radioBearerConfig=NULL; + // secondaryCellGroup + fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); + xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); + + char scg_buffer[1024]; + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); + + + reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup)); + OCTET_STRING_fromBuf(reconfig->secondaryCellGroup, + (const char*)scg_buffer, + (enc_rval.encoded+7)>>3); + // measConfig + reconfig->measConfig=NULL; + // lateNonCriticalExtension + reconfig->lateNonCriticalExtension = NULL; + // nonCriticalExtension + reconfig->nonCriticalExtension = NULL; +} + +void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { + + rbconfig->srb_ToAddModList = NULL; + rbconfig->srb3_ToRelease = NULL; + rbconfig->drb_ToAddModList = calloc(1,sizeof(*rbconfig->drb_ToAddModList)); + NR_DRB_ToAddMod_t *drb_ToAddMod = calloc(1,sizeof(*drb_ToAddMod)); + drb_ToAddMod->cnAssociation = calloc(1,sizeof(*drb_ToAddMod->cnAssociation)); + drb_ToAddMod->cnAssociation->present = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + drb_ToAddMod->cnAssociation->choice.eps_BearerIdentity=5; + drb_ToAddMod->drb_Identity = 1; + drb_ToAddMod->reestablishPDCP = NULL; + drb_ToAddMod->recoverPDCP = NULL; + drb_ToAddMod->pdcp_Config = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config)); + drb_ToAddMod->pdcp_Config->drb = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb)); + drb_ToAddMod->pdcp_Config->drb->discardTimer = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->discardTimer)); + *drb_ToAddMod->pdcp_Config->drb->discardTimer=NR_PDCP_Config__drb__discardTimer_ms30; + drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL)); + *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL)); + *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + drb_ToAddMod->pdcp_Config->drb->headerCompression.present = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + drb_ToAddMod->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + + drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL; + drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL; + drb_ToAddMod->pdcp_Config->drb->outOfOrderDelivery=NULL; + drb_ToAddMod->pdcp_Config->moreThanOneRLC = NULL; + + drb_ToAddMod->pdcp_Config->t_Reordering = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->t_Reordering)); + *drb_ToAddMod->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0; + drb_ToAddMod->pdcp_Config->ext1 = NULL; + + ASN_SEQUENCE_ADD(&rbconfig->drb_ToAddModList->list,drb_ToAddMod); + + rbconfig->drb_ToReleaseList = NULL; + + rbconfig->securityConfig = calloc(1,sizeof(*rbconfig->securityConfig)); + rbconfig->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(*rbconfig->securityConfig->securityAlgorithmConfig)); + rbconfig->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rbconfig->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm=NULL; + rbconfig->securityConfig->keyToUse = calloc(1,sizeof(*rbconfig->securityConfig->keyToUse)); + *rbconfig->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; + + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); +} +#endif diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.master.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.master.conf new file mode 100644 index 0000000000..c0decd362f --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.master.conf @@ -0,0 +1,298 @@ +Active_eNBs = ( "eNB-Eurecom-LTEBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +eNBs = +( + { + ////////// Identification parameters: + eNB_ID = 0xe01; + + cell_type = "CELL_MACRO_ENB"; + + eNB_name = "eNB-Eurecom-LTEBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ( { mcc = 208; mnc = 93; mnc_length = 2; } ); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "3GPP_eNODEB"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + frame_type = "FDD"; + tdd_config = 3; + tdd_config_s = 0; + prefix_type = "NORMAL"; + eutra_band = 7; + downlink_frequency = 2685000000L; + uplink_frequency_offset = -120000000; + Nid_cell = 1; + N_RB_DL = 50; + Nid_cell_mbsfn = 0; + nb_antenna_ports = 1; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + tx_gain = 90; + rx_gain = 125; + pbch_repetition = "FALSE"; + prach_root = 0; + prach_config_index = 0; + prach_high_speed = "DISABLE"; + prach_zero_correlation = 1; + prach_freq_offset = 2; + pucch_delta_shift = 1; + pucch_nRB_CQI = 0; + pucch_nCS_AN = 0; + pucch_n1_AN = 0; + pdsch_referenceSignalPower = -27; + pdsch_p_b = 0; + pusch_n_SB = 1; + pusch_enable64QAM = "DISABLE"; + pusch_hoppingMode = "interSubFrame"; + pusch_hoppingOffset = 0; + pusch_groupHoppingEnabled = "ENABLE"; + pusch_groupAssignment = 0; + pusch_sequenceHoppingEnabled = "DISABLE"; + pusch_nDMRS1 = 1; + phich_duration = "NORMAL"; + phich_resource = "ONESIXTH"; + srs_enable = "DISABLE"; + /* srs_BandwidthConfig =; + srs_SubframeConfig =; + srs_ackNackST =; + srs_MaxUpPts =;*/ + + pusch_p0_Nominal = -96; + pusch_alpha = "AL1"; + pucch_p0_Nominal = -104; + msg3_delta_Preamble = 6; + pucch_deltaF_Format1 = "deltaF2"; + pucch_deltaF_Format1b = "deltaF3"; + pucch_deltaF_Format2 = "deltaF0"; + pucch_deltaF_Format2a = "deltaF0"; + pucch_deltaF_Format2b = "deltaF0"; + + rach_numberOfRA_Preambles = 64; + rach_preamblesGroupAConfig = "DISABLE"; + /* + rach_sizeOfRA_PreamblesGroupA = ; + rach_messageSizeGroupA = ; + rach_messagePowerOffsetGroupB = ; + */ + rach_powerRampingStep = 4; + rach_preambleInitialReceivedTargetPower = -108; + rach_preambleTransMax = 10; + rach_raResponseWindowSize = 10; + rach_macContentionResolutionTimer = 48; + rach_maxHARQ_Msg3Tx = 4; + + pcch_default_PagingCycle = 128; + pcch_nB = "oneT"; + bcch_modificationPeriodCoeff = 2; + ue_TimersAndConstants_t300 = 1000; + ue_TimersAndConstants_t301 = 1000; + ue_TimersAndConstants_t310 = 1000; + ue_TimersAndConstants_t311 = 10000; + ue_TimersAndConstants_n310 = 20; + ue_TimersAndConstants_n311 = 1; + ue_TransmissionMode = 1; + + //Parameters for SIB18 + rxPool_sc_CP_Len = "normal"; + rxPool_sc_Period = "sf40"; + rxPool_data_CP_Len = "normal"; + rxPool_ResourceConfig_prb_Num = 20; + rxPool_ResourceConfig_prb_Start = 5; + rxPool_ResourceConfig_prb_End = 44; + rxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + rxPool_ResourceConfig_offsetIndicator_choice = 0; + rxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; +/* rxPool_dataHoppingConfig_hoppingParameter = 0; + rxPool_dataHoppingConfig_numSubbands = "ns1"; + rxPool_dataHoppingConfig_rbOffset = 0; + rxPool_commTxResourceUC-ReqAllowed = "TRUE"; +*/ + // Parameters for SIB19 + discRxPool_cp_Len = "normal" + discRxPool_discPeriod = "rf32" + discRxPool_numRetx = 1; + discRxPool_numRepetition = 2; + discRxPool_ResourceConfig_prb_Num = 5; + discRxPool_ResourceConfig_prb_Start = 3; + discRxPool_ResourceConfig_prb_End = 21; + discRxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + discRxPool_ResourceConfig_offsetIndicator_choice = 0; + discRxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; + + } + ); + + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "enp0s31f6"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.188/23"; + ENB_INTERFACE_NAME_FOR_S1U = "enp0s31f6"; + ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.188/23"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + + ENB_IPV4_ADDRESS_FOR_X2C = "192.168.12.188/23"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + } +); + +DU = ( + { + DU_INTERFACE_NAME_FOR_F1U = "lo"; + DU_IPV4_ADDRESS_FOR_F1U = "127.0.0.1/16"; + DU_PORT_FOR_F1U = 22100; + F1_U_DU_TRANSPORT_TYPE = "TCP"; + } + ); + +CU = ( + { + CU_INTERFACE_NAME_FOR_F1U = "lo"; + CU_IPV4_ADDRESS_FOR_F1U = "127.0.0.1"; //Address to search the DU + CU_PORT_FOR_F1U = 22100; + F1_U_CU_TRANSPORT_TYPE = "TCP"; // One of TCP/UDP/SCTP + DU_TYPE = "LTE"; + }//, +// { +// CU_INTERFACE_NAME_FOR_F1U = "eth0"; +// CU_IPV4_ADDRESS_FOR_F1U = "10.64.93.142"; //Address to search the DU +// CU_PORT_FOR_F1U = 2211; +// F1_U_CU_TRANSPORT_TYPE = "TCP"; // One of TCP/UDP/SCTP +// DU_TYPE = "WiFi"; +// } + ); + + CU_BALANCING = "ALL"; + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 200; + puCch10xSnr = 200; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 125; + eNB_instances = [0]; + + } +); + +NETWORK_CONTROLLER : +{ + FLEXRAN_ENABLED = "no"; + FLEXRAN_INTERFACE_NAME = "lo"; + FLEXRAN_IPV4_ADDRESS = "127.0.0.1"; + FLEXRAN_PORT = 2210; + FLEXRAN_CACHE = "/mnt/oai_agent_cache"; + FLEXRAN_AWAIT_RECONF = "no"; +}; + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf new file mode 100644 index 0000000000..1363be3bce --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf @@ -0,0 +1,271 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is pointA + 23 PRBs@120kHz SCS (same as initial BWP) + absoluteFrequencySSB = 2077907; + dl_frequencyBand = 257; + # this is 27.900 GHz + dl_absoluteFrequencyPointA = 2077499; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 3; + dl_carrierBandwidth = 32; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 8525; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 3; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 257; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 3; + ul_carrierBandwidth = 32; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 8525; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 3; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 3; + ssb_PositionsInBurst_Bitmap = 0x100000001L; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 3; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 3; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 5; + nrofDownlinkSlots = 10; + nrofDownlinkSymbols = 0; + nrofUplinkSlots = 10; + nrofUplinkSymbols = 0; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1; + nb_rx = 1; + att_tx = 0; + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2"; + if_freq = 5300000000; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf new file mode 100644 index 0000000000..1fbc8e30ef --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf @@ -0,0 +1,270 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is pointA + 23 PRBs@120kHz SCS (same as initial BWP) + absoluteFrequencySSB = 2078315; + dl_frequencyBand = 257; + # this is 27.900 GHz + dl_absoluteFrequencyPointA = 2077499; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 3; + dl_carrierBandwidth = 66; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 3; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 257; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 3; + ul_carrierBandwidth = 66; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 3; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 3; + ssb_PositionsInBurst_Bitmap = 1; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 3; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 30; + nrofDownlinkSymbols = 0; + nrofUplinkSlots = 10; + nrofUplinkSymbols = 0; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + sdr_addrs = "type=n300"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band261.tm1.32PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band261.tm1.32PRB.usrpn300.conf new file mode 100644 index 0000000000..72a27cc1e7 --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band261.tm1.32PRB.usrpn300.conf @@ -0,0 +1,271 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 600; + + plmn_list = ({mcc = 311; mnc = 480; mnc_length = 3;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is pointA + 23 PRBs@120kHz SCS (same as initial BWP) + absoluteFrequencySSB = 2071241; + dl_frequencyBand = 261; + # this is 27.900 GHz + dl_absoluteFrequencyPointA = 2070833; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 3; + dl_carrierBandwidth = 32; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 8525; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 3; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 261; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 3; + ul_carrierBandwidth = 32; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 8525; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 3; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 3; + ssb_PositionsInBurst_Bitmap = 0x100000001L; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 3; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 3; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 5; + nrofDownlinkSlots = 10; + nrofDownlinkSymbols = 0; + nrofUplinkSlots = 10; + nrofUplinkSymbols = 0; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1; + nb_rx = 1; + att_tx = 0; + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2"; + if_freq = 5124520000L; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.30kHz,usrpb2x0.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.30kHz,usrpb2x0.conf new file mode 100644 index 0000000000..ff8e261783 --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.30kHz,usrpb2x0.conf @@ -0,0 +1,283 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 31; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 10; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641272; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=13 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 0; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 5; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 0; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.12.196"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.12.111/24"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.slave.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.slave.conf new file mode 100644 index 0000000000..771f5d1839 --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.slave.conf @@ -0,0 +1,284 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 642016; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 217; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 217; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 15; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 2; + nrofDownlinkSymbols = 1; + nrofUplinkSlots = 7; + nrofUplinkSymbols = 7; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.12.188"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "enp0s31f6"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.75/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.75/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.12.75/23"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + sdr_addrs = "addr=192.168.20.2,mgmt_addr=192.168.20.2"; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; From 02dc4ba8ce0ff8936df6580f5cf71e4fffa5653a Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Wed, 13 May 2020 22:27:36 +0800 Subject: [PATCH 07/70] configured LDPC on CPU and GPU --- .../gnb.band78.tm1.106PRB.usrpn300.conf | 339 +- ci-scripts/main.py | 11 +- ci-scripts/oai-ci-vm-tool | 2 +- ci-scripts/runTestOnVM.sh | 96 +- ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml | 6 +- cmake_targets/CMakeLists.txt | 141 +- cmake_targets/autotests/test_case_list.xml | 49 +- cmake_targets/build_oai | 4 + cmake_targets/tools/build_helper | 4 +- common/config/config_userapi.c | 4 +- common/ran_context.h | 4 +- common/utils/LOG/vcd_signal_dumper.c | 3 +- common/utils/LOG/vcd_signal_dumper.h | 1 + common/utils/T/T_defs.h | 2 +- common/utils/T/T_messages.txt | 5 + common/utils/telnetsrv/telnetsrv.c | 20 +- executables/nr-gnb.c | 400 +- executables/nr-ru.c | 350 +- executables/nr-softmodem-common.h | 3 +- executables/nr-softmodem.c | 122 +- executables/nr-softmodem.h | 2 +- executables/nr-ue.c | 384 +- executables/nr-uesoftmodem.c | 97 +- executables/nr-uesoftmodem.h | 14 +- executables/softmodem-common.c | 2 +- executables/softmodem-common.h | 6 +- nfapi/oai_integration/nfapi_vnf.c | 10 +- .../nfapi/public_inc/fapi_nr_ue_constants.h | 7 +- .../nfapi/public_inc/fapi_nr_ue_interface.h | 255 +- .../nfapi/public_inc/nfapi_nr_interface.h | 298 +- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 638 ++- .../vnf/public_inc/nfapi_vnf_interface.h | 5 +- nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c | 2 +- openair1/PHY/CODING/TESTBENCH/ldpctest.c | 42 +- openair1/PHY/CODING/TESTBENCH/polartest.c | 2 +- openair1/PHY/CODING/coding_defs.h | 6 +- .../PHY/CODING/nrLDPC_decoder/nrLDPC_cnProc.h | 14 +- .../CODING/nrLDPC_decoder/nrLDPC_decoder.c | 6 +- .../CODING/nrLDPC_decoder/nrLDPC_decoder.h | 46 - .../PHY/CODING/nrLDPC_decoder/nrLDPC_defs.h | 201 - .../PHY/CODING/nrLDPC_decoder/nrLDPC_init.h | 2 +- .../CODING/nrLDPC_decoder/nrLDPC_init_mem.h | 1 - .../PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h | 21 +- .../PHY/CODING/nrLDPC_decoder/nrLDPC_types.h | 5 +- .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu | 10 - .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h | 14 +- .../CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h | 12 +- openair1/PHY/CODING/nrLDPC_encoder/defs.h | 54 - .../PHY/CODING/nrLDPC_encoder/ldpc_encoder.c | 252 +- .../PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c | 10 +- .../ldpc_generate_coefficient.c | 244 +- .../PHY/CODING/nrPolar_tools/nr_polar_defs.h | 4 +- openair1/PHY/CODING/nr_compute_tbs.c | 151 - openair1/PHY/CODING/nr_polar_init.c | 14 +- openair1/PHY/CODING/nr_rate_matching.c | 366 +- openair1/PHY/CODING/nr_segmentation.c | 16 +- openair1/PHY/INIT/lte_parms.c | 2 + openair1/PHY/INIT/nr_init.c | 453 +- openair1/PHY/INIT/nr_init_ru.c | 21 +- openair1/PHY/INIT/nr_init_ue.c | 94 +- openair1/PHY/INIT/nr_parms.c | 321 +- openair1/PHY/INIT/phy_init.h | 7 +- openair1/PHY/MODULATION/modulation_UE.h | 6 + openair1/PHY/MODULATION/nr_modulation.c | 7 +- openair1/PHY/MODULATION/slot_fep_nr.c | 200 +- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 34 +- openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h | 14 +- openair1/PHY/NR_REFSIG/dmrs_nr.c | 15 +- openair1/PHY/NR_REFSIG/dmrs_nr.h | 3 +- openair1/PHY/NR_REFSIG/nr_gold.c | 66 +- openair1/PHY/NR_REFSIG/nr_gold_ue.c | 4 +- openair1/PHY/NR_REFSIG/nr_refsig.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_dci.c | 314 +- openair1/PHY/NR_TRANSPORT/nr_dci.h | 20 +- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 511 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 260 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.h | 41 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 248 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c | 60 +- openair1/PHY/NR_TRANSPORT/nr_pbch.c | 31 +- openair1/PHY/NR_TRANSPORT/nr_pss.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c | 12 +- openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h | 4 +- openair1/PHY/NR_TRANSPORT/nr_sss.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c | 183 +- openair1/PHY/NR_TRANSPORT/nr_transport.h | 31 +- .../NR_TRANSPORT/nr_transport_common_proto.h | 20 +- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 26 +- openair1/PHY/NR_TRANSPORT/nr_ulsch.h | 9 +- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 217 +- .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 388 +- .../nr_dl_channel_estimation.c | 19 +- openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h | 7 +- .../PHY/NR_UE_ESTIMATION/nr_ue_measurements.c | 633 +-- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 1663 +----- openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c | 1018 +--- .../PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 281 +- .../NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 210 +- .../nr_dlsch_llr_computation.c | 14 +- .../PHY/NR_UE_TRANSPORT/nr_initial_sync.c | 27 +- openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c | 20 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 1343 ++--- openair1/PHY/NR_UE_TRANSPORT/nr_prach.h | 891 ---- .../NR_UE_TRANSPORT/nr_transport_proto_ue.h | 86 +- .../PHY/NR_UE_TRANSPORT/nr_transport_ue.h | 20 +- .../PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c | 123 +- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 146 +- openair1/PHY/NR_UE_TRANSPORT/pss_nr.c | 6 +- openair1/PHY/NR_UE_TRANSPORT/sss_nr.c | 2 +- openair1/PHY/TOOLS/Makefile | 8 +- openair1/PHY/TOOLS/lte_dfts.c | 114 +- openair1/PHY/TOOLS/nr_phy_scope.c | 107 +- openair1/PHY/TOOLS/nr_phy_scope.h | 1 + openair1/PHY/TOOLS/tools_defs.h | 17 +- openair1/PHY/defs_RU.h | 4 + openair1/PHY/defs_common.h | 5 + openair1/PHY/defs_gNB.h | 211 +- openair1/PHY/defs_nr_UE.h | 85 +- openair1/PHY/defs_nr_common.h | 82 +- openair1/PHY/impl_defs_nr.h | 76 +- openair1/PHY/impl_defs_top.h | 4 +- openair1/SCHED_NR/fapi_nr_l1.c | 169 +- openair1/SCHED_NR/fapi_nr_l1.h | 11 +- openair1/SCHED_NR/nr_ru_procedures.c | 314 +- openair1/SCHED_NR/phy_frame_config_nr.h | 4 +- openair1/SCHED_NR/phy_procedures_nr_common.c | 9 - openair1/SCHED_NR/phy_procedures_nr_gNB.c | 337 +- openair1/SCHED_NR/sched_nr.h | 16 +- openair1/SCHED_NR_UE/defs.h | 3 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 87 +- openair1/SCHED_NR_UE/phy_frame_config_nr.c | 342 -- openair1/SCHED_NR_UE/phy_frame_config_nr.h | 12 - openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 699 ++- .../SCHED_NR_UE/pucch_power_control_ue_nr.c | 23 +- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 18 +- openair1/SCHED_UE/phy_procedures_lte_ue.c | 2 +- .../SIMULATION/ETH_TRANSPORT/netlink_init.c | 20 +- openair1/SIMULATION/ETH_TRANSPORT/proto.h | 2 +- openair1/SIMULATION/LTE_PHY/prachsim.c | 4 +- openair1/SIMULATION/NR_PHY/dlschsim.c | 47 +- openair1/SIMULATION/NR_PHY/dlsim.c | 831 +-- .../SIMULATION/NR_PHY/nr_dummy_functions.c | 2 +- openair1/SIMULATION/NR_PHY/nr_unitary_defs.h | 168 + openair1/SIMULATION/NR_PHY/pbchsim.c | 117 +- openair1/SIMULATION/NR_PHY/pucchsim.c | 12 +- openair1/SIMULATION/NR_PHY/ulschsim.c | 61 +- openair1/SIMULATION/NR_PHY/ulsim.c | 226 +- .../NR_UE_PHY/unit_tests/src/pss_util_test.c | 2 +- openair2/COMMON/platform_constants.h | 9 +- openair2/COMMON/rrc_messages_types.h | 193 +- openair2/COMMON/s1ap_messages_types.h | 19 +- openair2/COMMON/x2ap_messages_def.h | 5 + openair2/COMMON/x2ap_messages_types.h | 114 +- openair2/ENB_APP/enb_config.c | 7 +- openair2/ENB_APP/enb_paramdef.h | 3 + openair2/GNB_APP/RRC_nr_paramsvalues.h | 379 +- openair2/GNB_APP/gnb_app.c | 30 +- openair2/GNB_APP/gnb_config.c | 2779 ++-------- openair2/GNB_APP/gnb_config.h | 1 + openair2/GNB_APP/gnb_paramdef.h | 686 +-- openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 49 +- openair2/LAYER2/MAC/ue_procedures.c | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 686 ++- openair2/LAYER2/NR_MAC_UE/config_ue.c | 437 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 178 +- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 85 +- openair2/LAYER2/NR_MAC_UE/main_ue_nr.c | 16 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 4551 ++++++++++------- openair2/LAYER2/NR_MAC_gNB/config.c | 459 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 139 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 90 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 1151 +++-- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 1156 ++++- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 13 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 146 +- openair2/LAYER2/NR_MAC_gNB/main.c | 108 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 177 +- openair2/LAYER2/PDCP_v10.1.0/pdcp.c | 6 +- openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c | 6 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 210 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.h | 10 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 113 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h | 6 +- openair2/PHY_INTERFACE/phy_stub_UE.c | 1679 +++--- openair2/RRC/LTE/MESSAGES/asn1_msg.c | 92 + openair2/RRC/LTE/MESSAGES/asn1_msg.h | 7 + openair2/RRC/LTE/rrc_defs.h | 6 +- openair2/RRC/LTE/rrc_eNB.c | 319 +- openair2/RRC/LTE/rrc_proto.h | 6 + openair2/RRC/NR/L2_nr_interface.c | 2 +- openair2/RRC/NR/MESSAGES/asn1_msg.c | 651 +-- openair2/RRC/NR/MESSAGES/asn1_msg.h | 37 +- openair2/RRC/NR/nr_rrc_config.c | 136 - openair2/RRC/NR/nr_rrc_defs.h | 56 +- openair2/RRC/NR/nr_rrc_proto.h | 35 + openair2/RRC/NR/rrc_gNB.c | 247 +- openair2/RRC/NR_UE/main_ue.c | 9 +- openair2/RRC/NR_UE/rrc_UE.c | 115 +- openair2/RRC/NR_UE/rrc_defs.h | 7 +- openair2/RRC/NR_UE/rrc_proto.h | 4 +- openair2/X2AP/x2ap_eNB.c | 107 +- openair2/X2AP/x2ap_eNB_decoder.c | 18 +- openair2/X2AP/x2ap_eNB_encoder.c | 4 +- openair2/X2AP/x2ap_eNB_generate_messages.c | 701 ++- openair2/X2AP/x2ap_eNB_generate_messages.h | 11 +- openair2/X2AP/x2ap_eNB_handler.c | 702 ++- openair2/X2AP/x2ap_ids.h | 3 +- openair3/NAS/COMMON/UTIL/nas_log.h | 9 +- openair3/NAS/UE/EMM/SecurityModeControl.c | 2 +- openair3/NAS/UE/nas_itti_messaging.c | 4 +- openair3/NAS/UE/nas_itti_messaging.h | 2 +- openair3/UTILS/conversions.h | 10 +- targets/ARCH/COMMON/common_lib.c | 35 +- targets/ARCH/COMMON/common_lib.h | 18 + targets/ARCH/COMMON/record_player.h | 15 +- targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 67 +- targets/ARCH/iqplayer/iqplayer_lib.c | 14 +- targets/ARCH/rfsimulator/simulator.c | 2 +- targets/COMMON/openairinterface5g_limits.h | 10 - .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 346 +- .../CONF/gnb.band78.tm1.106PRB.usrpx300.conf | 340 +- .../CONF/gnb.band78.tm1.217PRB.usrpn300.conf | 355 +- .../CONF/gnb.band78.tm1.217PRB.usrpx300.conf | 340 +- .../CONF/gnb.band78.tm1.273PRB.usrpn300.conf | 328 +- .../CONF/gnb.band78.tm1.beamw.usrpn300.conf | 291 -- targets/RT/USER/lte-ru.c | 14 +- targets/RT/USER/lte-softmodem.c | 2 +- targets/RT/USER/lte-softmodem.h | 2 +- targets/RT/USER/lte-ue.c | 81 +- targets/RT/USER/lte-uesoftmodem.c | 2 +- 230 files changed, 18984 insertions(+), 21450 deletions(-) delete mode 100644 openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h delete mode 100644 openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_defs.h delete mode 100644 openair1/PHY/CODING/nrLDPC_encoder/defs.h delete mode 100644 openair1/PHY/CODING/nr_compute_tbs.c delete mode 100644 openair1/PHY/NR_UE_TRANSPORT/nr_prach.h delete mode 100644 openair1/SCHED_NR_UE/phy_frame_config_nr.c delete mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.beamw.usrpn300.conf diff --git a/ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf b/ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf index e71bb00ffb..d92804ae44 100644 --- a/ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf @@ -21,183 +21,166 @@ gNBs = ////////// Physical parameters: - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = -120000000; - Nid_cell = 0; - N_RB_DL = 106; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x01; - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; + #spCellConfigCommon - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; + physCellId = 0; - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641032; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } # ------- SCTP definitions SCTP : @@ -254,8 +237,8 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "addr=192.168.20.2,second_addr=192.168.10.2,mgmt_addr=192.168.20.2,clock_source=external,time_source=external"; - + sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2"; + clock_src = "external"; } ); @@ -268,16 +251,6 @@ THREAD_STRUCT = ( } ); -NETWORK_CONTROLLER : -{ - FLEXRAN_ENABLED = "no"; - FLEXRAN_INTERFACE_NAME = "lo"; - FLEXRAN_IPV4_ADDRESS = "127.0.0.1"; - FLEXRAN_PORT = 2210; - FLEXRAN_CACHE = "/mnt/oai_agent_cache"; - FLEXRAN_AWAIT_RECONF = "no"; -}; - log_config : { global_log_level ="info"; diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 95360cae8f..21d51105f8 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -1044,6 +1044,12 @@ class SSHConnection(): logging.debug('Found a N3xx device --> resetting it') self.command('cd ' + self.UESourceCodePath, '\$', 5) # Initialize_OAI_UE_args usually start with -C and followed by the location in repository + # in case of NR-UE, we may have rrc_config_path (Temporary?) + modifiedUeOptions = str(self.Initialize_OAI_UE_args) + if self.air_interface == 'nr': + result = re.search('--rrc_config_path ', modifiedUeOptions) + if result is not None: + modifiedUeOptions = modifiedUeOptions.replace('rrc_config_path ', 'rrc_config_path ' + self.UESourceCodePath + '/') self.command('source oaienv', '\$', 5) self.command('cd cmake_targets/ran_build/build', '\$', 5) if self.air_interface == 'lte': @@ -1058,7 +1064,7 @@ class SSHConnection(): self.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) self.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5) self.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) - self.command('echo "ulimit -c unlimited && ./'+ self.air_interface +'-uesoftmodem ' + self.Initialize_OAI_UE_args + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + self.command('echo "ulimit -c unlimited && ./'+ self.air_interface +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) self.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) self.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) self.UELogFile = 'ue_' + self.testCase_id + '.log' @@ -1105,6 +1111,9 @@ class SSHConnection(): if result is not None: self.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT -r *-uesoftmodem', '\$', 4) time.sleep(3) + outterLoopCounter = outterLoopCounter - 1 + if (outterLoopCounter == 0): + doOutterLoop = False continue if self.air_interface == 'nr': fullSyncStatus = True diff --git a/ci-scripts/oai-ci-vm-tool b/ci-scripts/oai-ci-vm-tool index 485c22902e..9d6349077f 100755 --- a/ci-scripts/oai-ci-vm-tool +++ b/ci-scripts/oai-ci-vm-tool @@ -182,7 +182,7 @@ function variant__v2__basic_sim { } function variant__v3__phy_sim { - NB_PATTERN_FILES=12 + NB_PATTERN_FILES=13 BUILD_OPTIONS="--phy_simulators" VM_MEMORY=8192 VM_DISK=20 diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index d46ed07bbb..502c1a5d47 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -613,8 +613,11 @@ function start_epc { echo "############################################################" echo "echo \"cd /opt/hss_sim0609\"" > $LOC_EPC_VM_CMDS echo "cd /opt/hss_sim0609" >> $LOC_EPC_VM_CMDS - echo "echo \"sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real\"" >> $LOC_EPC_VM_CMDS - echo "sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real" >> $LOC_EPC_VM_CMDS + echo "sudo rm -f hss.log" >> $LOC_EPC_VM_CMDS + #echo "echo \"sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real\"" >> $LOC_EPC_VM_CMDS + #echo "sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real" >> $LOC_EPC_VM_CMDS + echo "echo \"screen -dm -S simulated_hss ./starthss_real\"" >> $LOC_EPC_VM_CMDS + echo "sudo su -c \"screen -dm -S simulated_hss ./starthss_real\"" >> $LOC_EPC_VM_CMDS echo "echo \"cd /opt/ltebox/tools/\"" >> $LOC_EPC_VM_CMDS echo "cd /opt/ltebox/tools/" >> $LOC_EPC_VM_CMDS @@ -870,9 +873,9 @@ function start_l2_sim_ue { echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then - echo "echo \"ulimit -c unlimited && ./lte-uesoftmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --L2-emul 3 --num-ues $LOC_NB_UES --nums_ue_thread $LOC_NB_UES --nokrnmod 1 --log_config.global_log_options level,nocolor --noS1\" > ./my-lte-softmodem-run.sh " >> $1 + echo "echo \"ulimit -c unlimited && ./lte-uesoftmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --L2-emul 3 --num-ues $LOC_NB_UES --nums_ue_thread 1 --nokrnmod 1 --log_config.global_log_options level,nocolor --noS1\" > ./my-lte-softmodem-run.sh " >> $1 else - echo "echo \"ulimit -c unlimited && ./lte-uesoftmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --L2-emul 3 --num-ues $LOC_NB_UES --nums_ue_thread $LOC_NB_UES --nokrnmod 1 --log_config.global_log_options level,nocolor\" > ./my-lte-softmodem-run.sh " >> $1 + echo "echo \"ulimit -c unlimited && ./lte-uesoftmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --L2-emul 3 --num-ues $LOC_NB_UES --nums_ue_thread 1 --nokrnmod 1 --log_config.global_log_options level,nocolor\" > ./my-lte-softmodem-run.sh " >> $1 fi echo "chmod 775 ./my-lte-softmodem-run.sh" >> $1 echo "cat ./my-lte-softmodem-run.sh" >> $1 @@ -905,8 +908,9 @@ function start_l2_sim_ue { else echo "L2-SIM UE is sync'ed w/ eNB" fi - local max_interfaces_to_check=1 - if [ $LOC_S1_CONFIGURATION -eq 0 ]; then max_interfaces_to_check=$LOC_NB_UES; fi + local max_interfaces_to_check=$LOC_NB_UES + #local max_interfaces_to_check=1 + #if [ $LOC_S1_CONFIGURATION -eq 0 ]; then max_interfaces_to_check=$LOC_NB_UES; fi local j="1" while [ $j -le $max_interfaces_to_check ] do @@ -1195,7 +1199,7 @@ function start_rf_sim_gnb { echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then - echo "echo \"RFSIMULATOR=server ./nr-softmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --log_config.global_log_options level,nocolor --parallel-config PARALLEL_SINGLE_THREAD --noS1 --nokrnmod 1 --rfsim\" > ./my-nr-softmodem-run.sh " >> $1 + echo "echo \"RFSIMULATOR=server ./nr-softmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --log_config.global_log_options level,nocolor --parallel-config PARALLEL_SINGLE_THREAD --noS1 --nokrnmod 1 --rfsim --phy-test\" > ./my-nr-softmodem-run.sh " >> $1 fi echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1 echo "cat ./my-nr-softmodem-run.sh" >> $1 @@ -1270,7 +1274,7 @@ function start_rf_sim_nr_ue { echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then - echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --numerology 1 -C ${LOC_FREQUENCY}000000 -r $LOC_PRB --nokrnmod 1 --rfsim --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 + echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/ci-scripts/rrc-files --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 fi echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1 echo "cat ./my-nr-softmodem-run.sh" >> $1 @@ -1281,7 +1285,7 @@ function start_rf_sim_nr_ue { rm $1 local i="0" - echo "egrep -c \"rfsimulator: Success\" /home/ubuntu/tmp/cmake_targets/log/$LOC_LOG_FILE" > $1 + echo "egrep -c \"Initial sync: pbch decoded sucessfully\" /home/ubuntu/tmp/cmake_targets/log/$LOC_LOG_FILE" > $1 while [ $i -lt 10 ] do sleep 5 @@ -2214,15 +2218,41 @@ function run_test_on_vm { if [ $S1_NOS1_CFG -eq 1 ] then - get_ue_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR 1 echo "############################################################" echo "${CN_CONFIG} : Pinging the EPC from UE(s)" echo "############################################################" - PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_epc.log - ping_epc_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR $REAL_EPC_IP_ADDR $PING_LOG_FILE 1 0 - scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC - check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + echo " --- Sequentially ---" + local j="1" + while [ $j -le $INT_NB_UES ] + do + PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_epc_seq_from_ue${j}.log + ping_epc_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR $REAL_EPC_IP_ADDR $PING_LOG_FILE ${j} 0 + scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC + check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + j=$[$j+1] + done + if [ $INT_NB_UES -gt 1 ] + then + echo " --- In parallel ---" + j="1" + while [ $j -le $INT_NB_UES ] + do + PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_epc_para_from_ue${j}.log + ping_epc_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR $REAL_EPC_IP_ADDR $PING_LOG_FILE ${j} 1 + j=$[$j+1] + done + sleep 25 + j="1" + while [ $j -le $INT_NB_UES ] + do + PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_epc_para_from_ue${j}.log + scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC + tail -3 $ARCHIVES_LOC/$PING_LOG_FILE + check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + j=$[$j+1] + done + fi else get_enb_noS1_ip_addr $ENB_VM_CMDS $ENB_VM_IP_ADDR @@ -2267,10 +2297,38 @@ function run_test_on_vm { echo "############################################################" echo "${CN_CONFIG} : Pinging the UE(s) from EPC" echo "############################################################" - PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_ue.log - ping_ue_ip_addr $EPC_VM_CMDS $EPC_VM_IP_ADDR $UE_IP_ADDR $PING_LOG_FILE 0 - scp -o StrictHostKeyChecking=no ubuntu@$EPC_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC - check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + echo " --- Sequentially ---" + local j="1" + while [ $j -le $INT_NB_UES ] + do + get_ue_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR $j + PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_from_epc_seq_ue${j}.log + ping_ue_ip_addr $EPC_VM_CMDS $EPC_VM_IP_ADDR $UE_IP_ADDR $PING_LOG_FILE 0 + scp -o StrictHostKeyChecking=no ubuntu@$EPC_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC + check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + j=$[$j+1] + done + if [ $INT_NB_UES -gt 1 ] + then + echo " --- In parallel ---" + j="1" + while [ $j -le $INT_NB_UES ] + do + get_ue_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR $j + PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_from_epc_para_ue${j}.log + ping_ue_ip_addr $EPC_VM_CMDS $EPC_VM_IP_ADDR $UE_IP_ADDR $PING_LOG_FILE 1 + j=$[$j+1] + done + sleep 25 + j="1" + while [ $j -le $INT_NB_UES ] + do + PING_LOG_FILE=${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping_from_epc_para_ue${j}.log + scp -o StrictHostKeyChecking=no ubuntu@$EPC_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC + check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + j=$[$j+1] + done + fi else echo "############################################################" echo "${CN_CONFIG} : Pinging the UE(s) from eNB" @@ -2310,7 +2368,7 @@ function run_test_on_vm { fi fi - if [ $S1_NOS1_CFG -eq 2 ] + if [ $S1_NOS1_CFG -eq 0 ] then get_enb_noS1_ip_addr $ENB_VM_CMDS $ENB_VM_IP_ADDR echo "############################################################" diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml index 03220ec286..f3e80c576a 100644 --- a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml +++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml @@ -24,7 +24,7 @@ run-oai-gnb-nr-ue Run-gNB-and-NR-UE tasks - 4 + 2 090101 000001 090102 000002 090108 090109 @@ -33,7 +33,7 @@ Initialize_eNB Initialize gNB USRP - -O ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf + -O ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test NR @@ -52,7 +52,7 @@ Initialize_OAI_UE Initialize NR UE USRP - -C 3510000000 --numerology 1 -r 106 --phy-test --usrp-args "addr=192.168.30.2,clock_source=external,time_source=external" --threadoffset 16 + --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path ci-scripts/rrc-files NR diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index a7d8a34ffc..72c7d319db 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -146,7 +146,7 @@ endfunction() #set(CMAKE_BUILD_TYPE "Debug") if (CMAKE_BUILD_TYPE STREQUAL "") - set(CMAKE_BUILD_TYPE "Release") + set(CMAKE_BUILD_TYPE "RelWithDebInfo") endif() message("CMAKE_BUILD_TYPE is ${CMAKE_BUILD_TYPE}") add_list_string_option(CMAKE_BUILD_TYPE "RelWithDebInfo" "Choose the type of build, options are: None(CMAKE_CXX_FLAGS or CMAKE_C_FLAGS used) Debug Release RelWithDebInfo MinSizeRel." Debug Release RelWithDebInfo MinSizeRel) @@ -245,6 +245,7 @@ set (FIRMWARE_VERSION "No svn information") add_definitions("-DFIRMWARE_VERSION=\"${FIRMWARE_VERSION}\"") add_definitions("-DPACKAGE_VERSION=\"Branch: ${GIT_BRANCH} Abrev. Hash: ${GIT_COMMIT_HASH} Date: ${GIT_COMMIT_DATE}\"") add_definitions("-DPACKAGE_BUGREPORT=\"openair4g-devel@lists.eurecom.fr\"") +#add_definitions("-DEMIT_ASN_DEBUG=1") # Debug related options @@ -330,7 +331,7 @@ set (NR_RRC_ASN1_VERSION "NR_Rel15" ) make_version(NR_RRC_VERSION 15 6 0) set (NR_RRC_GRAMMAR ${OPENAIR2_DIR}/RRC/NR/MESSAGES/asn1c/ASN1_files/nr-rrc-15.6.0.asn1) add_definitions(-DNR_RRC_VERSION=${NR_RRC_VERSION}) -set (NR_RRC_FULL_DIR ${asn1_generated_dir}/${NR_RRC_ASN1_VERSION}) +set (NR_RRC_FULL_DIR ${asn1_generated_dir}/RRC_${NR_RRC_ASN1_VERSION}) # Warning: if you modify ASN.1 source file to generate new C files, cmake should be re-run instead of make execute_process(COMMAND ${OPENAIR_CMAKE}/tools/make_asn1c_includes.sh "${NR_RRC_FULL_DIR}" "${NR_RRC_GRAMMAR}" "NR_" "-findirect-choice" @@ -1199,6 +1200,8 @@ set(SCHED_NR_SRC ${OPENAIR1_DIR}/SCHED_NR/fapi_nr_l1.c ${OPENAIR1_DIR}/SCHED_NR/phy_procedures_nr_common.c ${OPENAIR1_DIR}/SCHED_NR/phy_procedures_nr_gNB.c + ${OPENAIR1_DIR}/SCHED_NR/nr_prach_procedures.c + ${OPENAIR1_DIR}/SCHED_NR/phy_frame_config_nr.c ) add_library(SCHED_NR_LIB ${SCHED_NR_SRC}) @@ -1224,7 +1227,7 @@ set(SCHED_SRC_NR_UE ${OPENAIR1_DIR}/SCHED_NR_UE/phy_procedures_nr_ue.c ${OPENAIR1_DIR}/SCHED_NR/phy_procedures_nr_common.c ${OPENAIR1_DIR}/SCHED_NR_UE/fapi_nr_ue_l1.c - ${OPENAIR1_DIR}/SCHED_NR_UE/phy_frame_config_nr.c + ${OPENAIR1_DIR}/SCHED_NR/phy_frame_config_nr.c ${OPENAIR1_DIR}/SCHED_NR_UE/harq_nr.c ${OPENAIR1_DIR}/SCHED_NR_UE/pucch_uci_ue_nr.c ${OPENAIR1_DIR}/SCHED_NR_UE/pucch_power_control_ue_nr.c @@ -1317,15 +1320,36 @@ set(PHY_SMALLBLOCKSRC set(PHY_TURBOIF ${OPENAIR1_DIR}/PHY/CODING/coding_load.c ) -set(PHY_LDPCSRC + +set(PHY_LDPC_ORIG_SRC ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c - ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c - ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_generate_coefficient.c ) +set(PHY_LDPC_OPTIM_SRC + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim.c +) +set(PHY_LDPC_OPTIM8SEG_SRC + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8seg.c +) +set(PHY_LDPC_OPTIM8SEGMULTI_SRC + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder_optim8segmulti.c +) +set(PHY_NR_CODINGIF + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_load.c; +) + +add_library(ldpc_orig MODULE ${PHY_LDPC_ORIG_SRC} ) +add_library(ldpc_optim MODULE ${PHY_LDPC_OPTIM_SRC} ) +add_library(ldpc_optim8seg MODULE ${PHY_LDPC_OPTIM8SEG_SRC} ) +add_library(ldpc MODULE ${PHY_LDPC_OPTIM8SEGMULTI_SRC} ) + add_library(coding MODULE ${PHY_TURBOSRC} ) + set(PHY_SRC_COMMON ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/lte_mcs.c @@ -1353,7 +1377,6 @@ set(PHY_SRC_COMMON ${OPENAIR1_DIR}/PHY/LTE_REFSIG/lte_ul_ref.c ${OPENAIR1_DIR}/PHY/CODING/lte_segmentation.c ${OPENAIR1_DIR}/PHY/CODING/nr_segmentation.c - ${OPENAIR1_DIR}/PHY/CODING/nr_compute_tbs.c ${OPENAIR1_DIR}/PHY/CODING/nr_rate_matching.c ${OPENAIR1_DIR}/PHY/CODING/ccoding_byte.c ${OPENAIR1_DIR}/PHY/CODING/ccoding_byte_lte.c @@ -1466,6 +1489,11 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/INIT/lte_init_ue.c ) + set(PHY_NR_SRC_COMMON + ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_prach_common.c + ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dci_tools_common.c + ) + set(PHY_NR_SRC ${OPENAIR1_DIR}/PHY/INIT/nr_init.c ${OPENAIR1_DIR}/PHY/INIT/nr_parms.c @@ -1482,11 +1510,13 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch.c ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_tbs_tools.c ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_sch_dmrs.c + ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_prach.c ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch_llr_computation.c ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c + ${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c ${OPENAIR1_DIR}/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c ${OPENAIR1_DIR}/PHY/NR_ESTIMATION/nr_adjust_sync_gNB.c @@ -1504,10 +1534,9 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/TOOLS/lut.c ${PHY_POLARSRC} ${PHY_SMALLBLOCKSRC} - ${PHY_LDPCSRC} + ${PHY_NR_CODINGIF} ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/pucch_rx.c ) - set(PHY_NR_UE_SRC ${OPENAIR1_DIR}/PHY/INIT/nr_parms.c ${OPENAIR1_DIR}/PHY/MODULATION/nr_modulation.c @@ -1522,6 +1551,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_dlsch_llr_computation.c ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_tbs_tools.c + ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_prach_common.c ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_sch_dmrs.c ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/ ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -1533,6 +1563,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_REFSIG/ul_ref_seq_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c + ${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold_ue.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c @@ -1555,7 +1586,7 @@ set(PHY_SRC_UE # ${OPENAIR1_DIR}/SIMULATION/NR_UE_PHY/unit_tests/src/pucch_uci_test.c ${PHY_POLARSRC} ${PHY_SMALLBLOCKSRC} - ${PHY_LDPCSRC} + ${PHY_NR_CODINGIF} ) @@ -1578,6 +1609,7 @@ add_library(PHY ${PHY_SRC}) add_dependencies(PHY rrc_flag) add_library(PHY_UE ${PHY_SRC_UE}) add_dependencies(PHY_UE rrc_flag) +add_library(PHY_NR_COMMON ${PHY_NR_SRC_COMMON}) add_library(PHY_NR ${PHY_NR_SRC}) add_library(PHY_NR_UE ${PHY_NR_UE_SRC}) @@ -1677,6 +1709,7 @@ set(L2_SRC ${PDCP_DIR}/pdcp_netlink.c # ${RRC_DIR}/rrc_UE.c ${RRC_DIR}/rrc_eNB.c + ${RRC_DIR}/rrc_eNB_endc.c ${RRC_DIR}/rrc_eNB_S1AP.c ${RRC_DIR}/rrc_eNB_M2AP.c ${RRC_DIR}/rrc_eNB_UE_context.c @@ -1696,6 +1729,10 @@ set(L2_NR_SRC ${NR_RRC_DIR}/nr_rrc_common.c ${NR_RRC_DIR}/L2_nr_interface.c ${NR_RRC_DIR}/nr_rrc_config.c + ${NR_RRC_DIR}/rrc_gNB_nsa.c + ${NR_RRC_DIR}/rrc_gNB_internode.c + ${NR_RRC_DIR}/rrc_gNB_reconfig.c + ${NR_RRC_DIR}/rrc_gNB_UE_context.c ) set(L2_SRC_UE @@ -1784,6 +1821,7 @@ set (MAC_NR_SRC_UE ${NR_UE_MAC_DIR}/mac_vars.c ${NR_UE_MAC_DIR}/main_ue_nr.c ${NR_UE_MAC_DIR}/nr_ue_procedures.c + ${NR_UE_MAC_DIR}/nr_ue_dci_configuration.c ) set (ENB_APP_SRC @@ -1844,7 +1882,7 @@ add_dependencies(L2_UE rrc_flag s1ap_flag x2_flag) add_library( NR_L2_UE ${NR_L2_SRC_UE} ${MAC_NR_SRC_UE} ) -add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_COMMON/nr_mac_common.c ) +add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_COMMON/nr_mac_common.c ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c) include_directories("${OPENAIR2_DIR}/NR_UE_PHY_INTERFACE") include_directories("${OPENAIR2_DIR}/LAYER2/NR_MAC_UE") @@ -2484,7 +2522,7 @@ add_dependencies(lte-softmodem rrc_flag s1ap_flag x2_flag oai_iqplayer) target_link_libraries (lte-softmodem -Wl,--start-group - RRC_LIB S1AP_LIB S1AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB SCHED_RU_LIB + RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB SCHED_RU_LIB PHY_COMMON PHY PHY_RU LFDS L2 L2_LTE NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB LFDS7 ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} ${FSPT_MSG_LIB} ${PROTO_AGENT_LIB} -Wl,--end-group z dl) @@ -2588,6 +2626,7 @@ add_executable(nr-softmodem ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c ${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${GTPU_need_ITTI} ${XFORMS_SOURCE_NR} ${T_SOURCE} @@ -2597,7 +2636,7 @@ add_executable(nr-softmodem target_link_libraries (nr-softmodem -Wl,--start-group - UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_RU LFDS GTPV1U SECU_CN SECU_OSA + UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS GTPV1U SECU_CN SECU_OSA ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} LFDS7 ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB L2 L2_NR MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB X2AP_LIB X2AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB M3AP_LIB M3AP_ENB ${PROTO_AGENT_LIB} ${FSPT_MSG_LIB} @@ -2608,7 +2647,7 @@ target_link_libraries (nr-softmodem pthread m ${CONFIG_LIB} rt crypt ${CRYPTO_LI target_link_libraries (nr-softmodem ${LIB_LMS_LIBRARIES}) target_link_libraries (nr-softmodem ${T_LIB}) - +add_dependencies( nr-softmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc ) # nr-uesoftmodem is UE implementation ####################################### @@ -2624,11 +2663,13 @@ add_executable(nr-uesoftmodem ${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c ${OPENAIR_TARGETS}/ARCH/COMMON/record_player.c ${OPENAIR2_DIR}/RRC/NAS/nas_config.c + ${OPENAIR2_DIR}/LAYER2/NR_MAC_COMMON/nr_mac_common.c ${OPENAIR2_DIR}/RRC/NAS/rb_config.c ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c ${OPENAIR3_DIR}/NAS/UE/nas_ue_task.c ${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${XFORMS_SOURCE_NR} ${T_SOURCE} ${UTIL_SRC} @@ -2640,7 +2681,7 @@ target_link_libraries (nr-uesoftmodem -Wl,--start-group RRC_LIB NR_RRC_LIB SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT UDP SCHED_RU_LIB SCHED_UE_LIB SCHED_NR_UE_LIB ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} LFDS7 ${ATLAS_LIBRARIES} - PHY_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS L2_UE NR_L2_UE MAC_NR_COMMON S1AP_LIB S1AP_ENB + PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS L2_UE NR_L2_UE MAC_NR_COMMON S1AP_LIB S1AP_ENB NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB -Wl,--end-group z dl) @@ -2649,7 +2690,7 @@ target_link_libraries (nr-uesoftmodem pthread m ${CONFIG_LIB} rt crypt ${CRYPTO_ target_link_libraries (nr-uesoftmodem ${LIB_LMS_LIBRARIES}) target_link_libraries (nr-uesoftmodem ${T_LIB}) - +add_dependencies( nr-uesoftmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc ) # USIM process ################# @@ -2696,25 +2737,33 @@ target_link_libraries (dlsim_tm4 add_executable(polartest ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/polartest.c + ${OPENAIR_DIR}/common/utils/backtrace.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${OPENAIR_DIR}/common/utils/system.c ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(polartest - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE CONFIG_LIB -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} dl ) add_executable(smallblocktest ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/smallblocktest.c + ${OPENAIR_DIR}/common/utils/backtrace.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c + ${OPENAIR_DIR}/common/utils/system.c ${T_SOURCE} ${SHLIB_LOADER_SOURCES} - ) +) + + target_link_libraries(smallblocktest - -Wl,--start-group UTIL SIMU PHY_NR CONFIG_LIB -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} dl ) +<<<<<<< HEAD ################################################### # For CUDA library ################################################### @@ -2723,15 +2772,26 @@ CUDA_ADD_LIBRARY(LDPC_CU ) cuda_add_executable(ldpctest +======= +add_executable(ldpctest + ${PHY_NR_CODINGIF} +>>>>>>> origin/develop ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) +<<<<<<< HEAD target_link_libraries(ldpctest -ldl -Wl,--start-group LDPC_CU UTIL SIMU PHY_NR CONFIG_LIB -Wl,--end-group +======= +add_dependencies( ldpctest ldpc_orig ldpc_optim ldpc_optim8seg ldpc ) + +target_link_libraries(ldpctest + -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group +>>>>>>> origin/develop m pthread ${ATLAS_LIBRARIES} dl ) #add_executable(ldpctest @@ -2752,7 +2812,7 @@ add_executable(nr_dlschsim ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_dlschsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) @@ -2764,35 +2824,50 @@ add_executable(nr_pbchsim ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_pbchsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) #PUCCH ---> Prashanth add_executable(nr_pucchsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/pucchsim.c + ${OPENAIR_DIR}/common/utils/backtrace.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${OPENAIR_DIR}/common/utils/system.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_pucchsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) -#PUCCH ---> Prashanth add_executable(nr_dlsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c + ${OPENAIR_DIR}/executables/softmodem-common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_dlsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) +target_compile_definitions(nr_dlsim PUBLIC -DPHYSICAL_SIMULATOR) + +add_executable(nr_prachsim + ${OPENAIR1_DIR}/SIMULATION/NR_PHY/prachsim.c + ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c + ${OPENAIR1_DIR}/SCHED_NR/phy_procedures_nr_common.c + ${UTIL_SRC} + ${T_SOURCE} + ${SHLIB_LOADER_SOURCES}) +target_link_libraries(nr_prachsim + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl) add_executable(nr_ulschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/ulschsim.c @@ -2802,22 +2877,24 @@ add_executable(nr_ulschsim ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_ulschsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) add_executable(nr_ulsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/ulsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c + ${OPENAIR_DIR}/executables/softmodem-common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_ulsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) - +target_compile_definitions(nr_ulsim PUBLIC -DPHYSICAL_SIMULATOR) foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim prachsim syncsim) @@ -2832,9 +2909,10 @@ foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim pr ${NFAPI_USER_DIR}/nfapi.c ) target_link_libraries (${myExe} - -Wl,--start-group SIMU UTIL SCHED_LIB SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON PHY PHY_UE PHY_RU LFDS ${ITTI_LIB} LFDS7 -Wl,--end-group + -Wl,--start-group SIMU UTIL SCHED_LIB SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON PHY_NR_COMMON PHY PHY_UE PHY_RU LFDS ${ITTI_LIB} LFDS7 -Wl,--end-group pthread m rt ${CONFIG_LIB} ${ATLAS_LIBRARIES} ${XFORMS_LIBRARIES} ${T_LIB} dl ) + endforeach(myExe) add_executable(test_epc_generate_scenario @@ -2865,7 +2943,7 @@ add_executable(test_epc_play_scenario ) target_include_directories(test_epc_play_scenario PUBLIC /usr/local/share/asn1c) target_link_libraries (test_epc_play_scenario - -Wl,--start-group RRC_LIB S1AP_LIB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB F1AP_LIB F1AP GTPV1U LIB_NAS_UE SECU_CN UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB PHY_COMMON PHY PHY_UE LFDS ${ITTI_LIB} ${MSC_LIB} -Wl,--end-group pthread m rt crypt sctp ${LIBXML2_LIBRARIES} ${LIBXSLT_LIBRARIES} ${CRYPTO_LIBRARIES} ${OPENSSL_LIBRARIES} ${NETTLE_LIBRARIES} ${CONFIG_LIB} + -Wl,--start-group RRC_LIB S1AP_LIB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB F1AP_LIB F1AP GTPV1U LIB_NAS_UE SECU_CN UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB PHY_NR_COMMON PHY_COMMON PHY PHY_UE LFDS ${ITTI_LIB} ${MSC_LIB} -Wl,--end-group pthread m rt crypt sctp ${LIBXML2_LIBRARIES} ${LIBXSLT_LIBRARIES} ${CRYPTO_LIBRARIES} ${OPENSSL_LIBRARIES} ${NETTLE_LIBRARIES} ${CONFIG_LIB} ) @@ -2909,9 +2987,10 @@ if (${T_TRACER}) coding FLPT_MSG ASYNC_IF FLEXRAN_AGENT HASHTABLE MSC UTIL OMG_SUMO SECU_OSA SECU_CN SCHED_LIB SCHED_NR_LIB SCHED_RU_LIB SCHED_UE_LIB SCHED_NR_UE_LIB default_sched remote_sched RAL NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_VNF_LIB NFAPI_USER_LIB - PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_UE PHY_RU PHY_MEX + PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_COMMON PHY_NR_UE PHY_RU PHY_MEX L2 L2_LTE L2_NR L2_UE NR_L2_UE MAC_NR_COMMON MAC_NR MAC_UE_NR - CN_UTILS GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU SIMU_ETH OPENAIR0_LIB) + CN_UTILS GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU SIMU_ETH OPENAIR0_LIB + ldpc_orig ldpc_optim ldpc_optim8seg ldpc) if (TARGET ${i}) add_dependencies(${i} generate_T) endif() diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index c4f15c3a16..b3954db1fd 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1082,32 +1082,31 @@ nr_dlsim Test cases. (Test1: 106 PRB), (Test2: 217 PRB), (Test3: 273 PRB), - (Test4: 106 PRB 12 CSET-Offset), - (Test5: 217 PRB 48 CSET-Offset), - (Test6: 106 PRB 25 PDSCH-Offset), - (Test7: 106 PRB 51 PDSCH-Offset), - (Test8: 217 PRB 100 PDSCH-PRBs), - (Test9: 217 PRB 80 PDSCH-Offset), - (Test10: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset), - (Test11: 106 PRBs 50 PDSCH-PRBs MCS Index 28 + (Test4: 106 PRB 25 PDSCH-Offset), + (Test5: 106 PRB 51 PDSCH-Offset), + (Test6: 217 PRB 100 PDSCH-PRBs), + (Test7: 217 PRB 80 PDSCH-Offset), + (Test8: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset), + (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27) + (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash $OPENAIR_DIR/targets/bin/nr_dlsim.Rel15 - -n100 -R106 -b106 - -n100 -R217 -b217 - -n100 -R273 -b273 - -n100 -R106 -o12 - -n100 -R217 -o48 - -n100 -R106 -a25 - -n100 -R106 -a51 - -n100 -R217 -b100 - -n100 -R217 -a80 - -n100 -R217 -a110 -b100 - -n100 -e28 - nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 + -n100 -R106 -b106 -s5 + -n100 -R217 -b217 -s5 + -n100 -R273 -b273 -s5 + -n100 -R106 -a25 -s5 + -n100 -R106 -a51 -s5 + -n100 -R217 -b100 -s5 + -n100 -R217 -a80 -s5 + -n100 -R217 -a110 -s5 -b100 + -n100 -e27 -s30 + -n100 -e16 -s10 + + nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 PDSCH test OK segmentation fault|assertion|exiting|fatal 3 @@ -1249,11 +1248,11 @@ $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash $OPENAIR_DIR/targets/bin/nr_ulsim.Rel15 - -f100 -m9 -r106 -s10 - -f100 -m16 -s20 - -f100 -m28 -s30 - -f100 -m9 -R217 -r217 -s10 - -f100 -m9 -R273 -r273 -s10 + -n100 -m9 -r106 -s0 + -n100 -m16 -s10 + -n100 -m28 -s20 + -n100 -m9 -R217 -r217 -s0 + -n100 -m9 -R273 -r273 -s0 nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5 PUSCH test OK segmentation fault|assertion|exiting|fatal diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 829c4a0f6b..78769ed8d4 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -697,8 +697,12 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim +<<<<<<< HEAD #simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim" simlist="ldpctest" +======= + simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" +>>>>>>> origin/develop for f in $simlist ; do compilations \ phy_simulators $f \ diff --git a/cmake_targets/tools/build_helper b/cmake_targets/tools/build_helper index 6ed17649cc..818b1fd79c 100755 --- a/cmake_targets/tools/build_helper +++ b/cmake_targets/tools/build_helper @@ -102,8 +102,8 @@ check_supported_distribution() { "ubuntu14.04") return 0 ;; "fedora24") return 0 ;; "rhel7") return 0 ;; - "rhel7.6") return 0 ;; - "rhel7.7") return 0 ;; + "rhel7.6") return 0 ;; + "rhel7.7") return 0 ;; "centos7") return 0 ;; esac return 1 diff --git a/common/config/config_userapi.c b/common/config/config_userapi.c index 67fdc2c920..33d6408828 100644 --- a/common/config/config_userapi.c +++ b/common/config/config_userapi.c @@ -45,7 +45,8 @@ configmodule_interface_t *config_get_if(void) { if (cfgptr == NULL) { - CONFIG_PRINTF_ERROR("[CONFIG] %s %d config module not initialized\n",__FILE__,__LINE__); + if (isLogInitDone()) + LOG_W(ENB_APP,"[CONFIG] %s %d config module not initialized\n",__FILE__,__LINE__); } return cfgptr; @@ -223,7 +224,6 @@ int config_get(paramdef_t *params, int numparams, char *prefix) { } configmodule_interface_t *cfgif = config_get_if(); - if (cfgif != NULL) { ret = config_get_if()->get(params, numparams, prefix); diff --git a/common/ran_context.h b/common/ran_context.h index abe482c742..8262f5dd55 100644 --- a/common/ran_context.h +++ b/common/ran_context.h @@ -85,8 +85,6 @@ typedef struct { int nb_nr_L1_inst; /// Number of Component Carriers per instance in this node int *nb_L1_CC; - /// Number of NR Component Carriers per instance in this node - int *nb_nr_L1_CC; /// Number of RU instances in this node int nb_RU; /// FlexRAN context variables @@ -94,7 +92,7 @@ typedef struct { /// eNB context variables struct PHY_VARS_eNB_s ***eNB; /// gNB context variables - struct PHY_VARS_gNB_s ***gNB; + struct PHY_VARS_gNB_s **gNB; /// NB_IoT L1 context variables struct PHY_VARS_eNB_NB_IoT_s **L1_NB_IoT; /// RRC context variables diff --git a/common/utils/LOG/vcd_signal_dumper.c b/common/utils/LOG/vcd_signal_dumper.c index 9327b6e77a..0043eb3238 100644 --- a/common/utils/LOG/vcd_signal_dumper.c +++ b/common/utils/LOG/vcd_signal_dumper.c @@ -514,7 +514,8 @@ const char* eurecomFunctionsNames[] = { /*NR softmodem signal*/ "wakeup_txfh", "gNB_thread_rxtx0", - "gNB_thread_rxtx1" + "gNB_thread_rxtx1", + "ru_thread_tx_wait" }; struct vcd_module_s vcd_modules[] = { diff --git a/common/utils/LOG/vcd_signal_dumper.h b/common/utils/LOG/vcd_signal_dumper.h index 9383b39b1e..20588bb828 100644 --- a/common/utils/LOG/vcd_signal_dumper.h +++ b/common/utils/LOG/vcd_signal_dumper.h @@ -507,6 +507,7 @@ typedef enum { VCD_SIGNAL_DUMPER_FUNCTIONS_WAKEUP_TXFH, VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX0, VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX1, + VCD_SIGNAL_DUMPER_FUNCTIONS_RU_TX_WAIT, VCD_SIGNAL_DUMPER_FUNCTIONS_END } vcd_signal_dump_functions; diff --git a/common/utils/T/T_defs.h b/common/utils/T/T_defs.h index b59fae2a0c..4cb4bf2bba 100644 --- a/common/utils/T/T_defs.h +++ b/common/utils/T/T_defs.h @@ -73,7 +73,7 @@ typedef struct { } T_cache_t; /* number of VCD functions (to be kept up to date! see in T_messages.txt) */ -#define VCD_NUM_FUNCTIONS (247) +#define VCD_NUM_FUNCTIONS (248) /* number of VCD variables (to be kept up to date! see in T_messages.txt) */ #define VCD_NUM_VARIABLES (186) diff --git a/common/utils/T/T_messages.txt b/common/utils/T/T_messages.txt index 387257d145..f8b746669c 100644 --- a/common/utils/T/T_messages.txt +++ b/common/utils/T/T_messages.txt @@ -3378,3 +3378,8 @@ ID = VCD_FUNCTION_gNB_PROC_RXTX1 GROUP = ALL:VCD:ENB:VCD_FUNCTION FORMAT = int,value VCD_NAME = gNB_thread_rxtx1 +ID = VCD_FUNCTION_RU_TX_WAIT + DESC = VCD function RU_TX_WAIT + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = ru_thread_tx_wait diff --git a/common/utils/telnetsrv/telnetsrv.c b/common/utils/telnetsrv/telnetsrv.c index 10163b22b5..06a5d350c7 100644 --- a/common/utils/telnetsrv/telnetsrv.c +++ b/common/utils/telnetsrv/telnetsrv.c @@ -377,6 +377,14 @@ int setgetvar(int moduleindex,char getorset,char *params) { client_printf("%hi\n",*(short *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); break; + case TELNET_VARTYPE_INT8: + client_printf("%i\n",(int)(*(int8_t *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr))); + break; + + case TELNET_VARTYPE_UINT: + client_printf("%u\n",*(unsigned int *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); + break; + case TELNET_VARTYPE_DOUBLE: client_printf("%g\n",*(double *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); break; @@ -405,7 +413,17 @@ int setgetvar(int moduleindex,char getorset,char *params) { *(short *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr) = (short)strtol(varval,NULL,0); client_printf("%hi\n",*(short *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); break; - + + case TELNET_VARTYPE_INT8: + *(char *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr) = (char)strtol(varval,NULL,0); + client_printf("%i\n",*(int *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); + break; + + case TELNET_VARTYPE_UINT: + *(unsigned int *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr) = (unsigned int)strtol(varval,NULL,0); + client_printf("%u\n",*(unsigned int *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); + break; + case TELNET_VARTYPE_DOUBLE: *(double *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr) = strtod(varval,NULL); client_printf("%g\n",*(double *)(telnetparams.CmdParsers[moduleindex].var[i].varvalptr)); diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index fc012b0ab2..e03700e4f5 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -101,8 +101,8 @@ extern openair0_config_t openair0_cfg[MAX_CARDS]; extern int transmission_mode; -uint16_t sl_ahead=6; -uint16_t sf_ahead=6; +extern uint16_t sf_ahead; +extern uint16_t sl_ahead; //pthread_t main_gNB_thread; time_stats_t softmodem_stats_mt; // main thread @@ -144,10 +144,14 @@ extern void add_subframe(uint16_t *frameP, uint16_t *subframeP, int offset); static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_tx, int slot_tx, char *thread_name) { + + sl_ahead = sf_ahead*gNB->frame_parms.slots_per_subframe; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; + start_meas(&softmodem_stats_rxtx_sf); // ******************************************************************* - + // NFAPI not yet supported for NR - this code has to be revised if (nfapi_mode == 1) { // I am a PNF and I need to let nFAPI know that we have a (sub)frame tick //add_subframe(&frame, &subframe, 4); @@ -173,20 +177,18 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t frame_tx, slot_tx); } } - - /// NR disabling // **************************************** - // Common RX procedures subframe n + T(T_GNB_PHY_DL_TICK, T_INT(gNB->Mod_id), T_INT(frame_tx), T_INT(slot_tx)); -/* + + /* // if this is IF5 or 3GPP_gNB if (gNB && gNB->RU_list && gNB->RU_list[0] && gNB->RU_list[0]->function < NGFI_RAU_IF4p5) { wakeup_prach_gNB(gNB,NULL,proc->frame_rx,proc->slot_rx); } + */ - // UE-specific RX processing for subframe n - if (nfapi_mode == 0 || nfapi_mode == 1) */ - + // Call the scheduler pthread_mutex_lock(&gNB->UL_INFO_mutex); gNB->UL_INFO.frame = frame_rx; gNB->UL_INFO.slot = slot_rx; @@ -194,22 +196,30 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t gNB->UL_INFO.CC_id = gNB->CC_id; gNB->if_inst->NR_UL_indication(&gNB->UL_INFO); pthread_mutex_unlock(&gNB->UL_INFO_mutex); + + // RX processing + int tx_slot_type = nr_slot_select(cfg,frame_tx,slot_tx); + int rx_slot_type = nr_slot_select(cfg,frame_rx,slot_rx); - /// end - // ***************************************** - // TX processing for subframe n+sl_ahead - // run PHY TX procedures the one after the other for all CCs to avoid race conditions - // (may be relaxed in the future for performance reasons) - // ***************************************** - //if (wait_CCs(proc)<0) return(-1); + if (rx_slot_type == NR_UPLINK_SLOT || rx_slot_type == NR_MIXED_SLOT) { + // UE-specific RX processing for subframe n + // TODO: check if this is correct for PARALLEL_RU_L1_TRX_SPLIT + phy_procedures_gNB_uespec_RX(gNB, frame_rx, slot_rx); + } if (oai_exit) return(-1); - //if (slot_rx == NR_UPLINK_SLOT || gNB->frame_parms.frame_type == FDD) - phy_procedures_gNB_uespec_RX(gNB, frame_rx, slot_rx); + // ***************************************** + // TX processing for subframe n+sf_ahead + // run PHY TX procedures the one after the other for all CCs to avoid race conditions + // (may be relaxed in the future for performance reasons) + // ***************************************** + + if (tx_slot_type == NR_DOWNLINK_SLOT || tx_slot_type == NR_MIXED_SLOT) { - if(get_thread_parallel_conf() != PARALLEL_RU_L1_TRX_SPLIT) { - phy_procedures_gNB_TX(gNB, frame_tx,slot_tx, 1); + if(get_thread_parallel_conf() != PARALLEL_RU_L1_TRX_SPLIT) { + phy_procedures_gNB_TX(gNB, frame_tx,slot_tx, 1); + } } stop_meas( &softmodem_stats_rxtx_sf ); @@ -388,14 +398,15 @@ void gNB_top(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, char *string, struct RU_proc_t *ru_proc=&ru->proc; proc->frame_rx = frame_rx; proc->slot_rx = slot_rx; + sl_ahead = sf_ahead*fp->slots_per_subframe; if (!oai_exit) { T(T_ENB_MASTER_TICK, T_INT(0), T_INT(proc->frame_rx), T_INT(proc->slot_rx)); - L1_proc->timestamp_tx = ru_proc->timestamp_rx + (sl_ahead*fp->samples_per_slot); + L1_proc->timestamp_tx = ru_proc->timestamp_rx + (sf_ahead*fp->samples_per_subframe); L1_proc->frame_rx = ru_proc->frame_rx; L1_proc->slot_rx = ru_proc->tti_rx; - L1_proc->frame_tx = (L1_proc->slot_rx > (fp->slots_per_frame-1-sl_ahead)) ? (L1_proc->frame_rx+1)&1023 : L1_proc->frame_rx; - L1_proc->slot_tx = (L1_proc->slot_rx + sl_ahead)%fp->slots_per_frame; + L1_proc->frame_tx = (L1_proc->slot_rx > (fp->slots_per_frame-1-(fp->slots_per_subframe*sf_ahead))) ? (L1_proc->frame_rx+1)&1023 : L1_proc->frame_rx; + L1_proc->slot_tx = (L1_proc->slot_rx + (fp->slots_per_subframe*sf_ahead))%fp->slots_per_frame; if (rxtx(gNB,L1_proc->frame_rx,L1_proc->slot_rx,L1_proc->frame_tx,L1_proc->slot_tx,string) < 0) LOG_E(PHY,"gNB %d CC_id %d failed during execution\n",gNB->Mod_id,gNB->CC_id); @@ -558,7 +569,7 @@ int wakeup_rxtx(PHY_VARS_gNB *gNB,RU_t *ru) { abstime.tv_sec += 1; } - // wake up TX for subframe n+sl_ahead + // wake up TX for subframe n+sf_ahead // lock the TX mutex and make sure the thread is ready AssertFatal((ret=pthread_mutex_timedlock(&L1_proc->mutex, &abstime)) == 0,"mutex_lock returns %d\n", ret); @@ -574,15 +585,15 @@ int wakeup_rxtx(PHY_VARS_gNB *gNB,RU_t *ru) { // TS_rx is the last received timestamp (start of 1st slot), TS_tx is the desired // transmitted timestamp of the next TX slot (first). // The last (TS_rx mod samples_per_frame) was n*samples_per_tti, - // we want to generate subframe (n+sl_ahead), so TS_tx = TX_rx+sl_ahead*samples_per_tti, - // and proc->slot_tx = proc->slot_rx+sl_ahead - L1_proc->timestamp_tx = ru_proc->timestamp_rx + (sl_ahead*fp->samples_per_slot); + // we want to generate subframe (n+sf_ahead), so TS_tx = TX_rx+sf_ahead*samples_per_tti, + // and proc->slot_tx = proc->slot_rx+sf_ahead + L1_proc->timestamp_tx = ru_proc->timestamp_rx + (sf_ahead*fp->samples_per_subframe); L1_proc->frame_rx = ru_proc->frame_rx; L1_proc->slot_rx = ru_proc->tti_rx; - L1_proc->frame_tx = (L1_proc->slot_rx > (fp->slots_per_frame-1-sl_ahead)) ? (L1_proc->frame_rx+1)&1023 : L1_proc->frame_rx; - L1_proc->slot_tx = (L1_proc->slot_rx + sl_ahead)%fp->slots_per_frame; + L1_proc->frame_tx = (L1_proc->slot_rx > (fp->slots_per_frame-1-(fp->slots_per_subframe*sf_ahead))) ? (L1_proc->frame_rx+1)&1023 : L1_proc->frame_rx; + L1_proc->slot_tx = (L1_proc->slot_rx + (fp->slots_per_subframe*sf_ahead))%fp->slots_per_frame; - LOG_D(PHY,"wakeupL1: passing parameter IC = %d, RX: %d.%d, TX: %d.%d to L1 sl_ahead = %d\n", L1_proc->instance_cnt, L1_proc->frame_rx, L1_proc->slot_rx, L1_proc->frame_tx, L1_proc->slot_tx, sl_ahead); + LOG_D(PHY,"wakeupL1: passing parameter IC = %d, RX: %d.%d, TX: %d.%d to L1 sf_ahead = %d\n", L1_proc->instance_cnt, L1_proc->frame_rx, L1_proc->slot_rx, L1_proc->frame_tx, L1_proc->slot_tx, sf_ahead); pthread_mutex_unlock( &L1_proc->mutex ); @@ -719,64 +730,62 @@ static void* process_stats_thread(void* param) { void init_gNB_proc(int inst) { int i=0; - int CC_id; + int CC_id = 0; PHY_VARS_gNB *gNB; gNB_L1_proc_t *proc; gNB_L1_rxtx_proc_t *L1_proc,*L1_proc_tx; - LOG_I(PHY,"%s(inst:%d) RC.nb_nr_CC[inst]:%d \n",__FUNCTION__,inst,RC.nb_nr_CC[inst]); - - for (CC_id=0; CC_idproc; - L1_proc = &proc->L1_proc; - L1_proc_tx = &proc->L1_proc_tx; - L1_proc->instance_cnt = -1; - L1_proc_tx->instance_cnt = -1; - L1_proc->instance_cnt_RUs = 0; - L1_proc_tx->instance_cnt_RUs = 0; - proc->instance_cnt_prach = -1; - proc->instance_cnt_asynch_rxtx = -1; - proc->CC_id = CC_id; - proc->first_rx =1; - proc->first_tx =1; - proc->RU_mask =0; - proc->RU_mask_tx = (1<num_RU)-1; - proc->RU_mask_prach =0; - pthread_mutex_init( &gNB->UL_INFO_mutex, NULL); - pthread_mutex_init( &L1_proc->mutex, NULL); - pthread_mutex_init( &L1_proc_tx->mutex, NULL); - pthread_cond_init( &L1_proc->cond, NULL); - pthread_cond_init( &L1_proc_tx->cond, NULL); - pthread_mutex_init( &proc->mutex_prach, NULL); - pthread_mutex_init( &proc->mutex_asynch_rxtx, NULL); - pthread_mutex_init( &proc->mutex_RU,NULL); - pthread_mutex_init( &proc->mutex_RU_tx,NULL); - pthread_mutex_init( &proc->mutex_RU_PRACH,NULL); - pthread_cond_init( &proc->cond_prach, NULL); - pthread_cond_init( &proc->cond_asynch_rxtx, NULL); - LOG_I(PHY,"gNB->single_thread_flag:%d\n", gNB->single_thread_flag); - - if (get_thread_parallel_conf() == PARALLEL_RU_L1_SPLIT || get_thread_parallel_conf() == PARALLEL_RU_L1_TRX_SPLIT) { - threadCreate( &L1_proc->pthread, gNB_L1_thread, gNB, "L1_proc", -1, OAI_PRIORITY_RT ); - threadCreate( &L1_proc_tx->pthread, gNB_L1_thread_tx, gNB,"L1_proc_tx", -1, OAI_PRIORITY_RT); - } - - if(opp_enabled == 1) threadCreate(&proc->L1_stats_thread, process_stats_thread,(void *)gNB, "time_meas", -1, OAI_PRIORITY_RT_LOW); - //pthread_create( &proc->pthread_prach, attr_prach, gNB_thread_prach, gNB ); - char name[16]; - - if (gNB->single_thread_flag==0) { - snprintf( name, sizeof(name), "L1 %d", i ); - pthread_setname_np( L1_proc->pthread, name ); - snprintf( name, sizeof(name), "L1TX %d", i ); - pthread_setname_np( L1_proc_tx->pthread, name ); - } - - AssertFatal(proc->instance_cnt_prach == -1,"instance_cnt_prach = %d\n",proc->instance_cnt_prach); + + proc = &gNB->proc; + L1_proc = &proc->L1_proc; + L1_proc_tx = &proc->L1_proc_tx; + L1_proc->instance_cnt = -1; + L1_proc_tx->instance_cnt = -1; + L1_proc->instance_cnt_RUs = 0; + L1_proc_tx->instance_cnt_RUs = 0; + proc->instance_cnt_prach = -1; + proc->instance_cnt_asynch_rxtx = -1; + proc->CC_id = CC_id; + proc->first_rx =1; + proc->first_tx =1; + proc->RU_mask =0; + proc->RU_mask_tx = (1<num_RU)-1; + proc->RU_mask_prach =0; + pthread_mutex_init( &gNB->UL_INFO_mutex, NULL); + pthread_mutex_init( &L1_proc->mutex, NULL); + pthread_mutex_init( &L1_proc_tx->mutex, NULL); + pthread_cond_init( &L1_proc->cond, NULL); + pthread_cond_init( &L1_proc_tx->cond, NULL); + pthread_mutex_init( &proc->mutex_prach, NULL); + pthread_mutex_init( &proc->mutex_asynch_rxtx, NULL); + pthread_mutex_init( &proc->mutex_RU,NULL); + pthread_mutex_init( &proc->mutex_RU_tx,NULL); + pthread_mutex_init( &proc->mutex_RU_PRACH,NULL); + pthread_cond_init( &proc->cond_prach, NULL); + pthread_cond_init( &proc->cond_asynch_rxtx, NULL); + LOG_I(PHY,"gNB->single_thread_flag:%d\n", gNB->single_thread_flag); + + if (get_thread_parallel_conf() == PARALLEL_RU_L1_SPLIT || get_thread_parallel_conf() == PARALLEL_RU_L1_TRX_SPLIT) { + threadCreate( &L1_proc->pthread, gNB_L1_thread, gNB, "L1_proc", -1, OAI_PRIORITY_RT ); + threadCreate( &L1_proc_tx->pthread, gNB_L1_thread_tx, gNB,"L1_proc_tx", -1, OAI_PRIORITY_RT); } + + if(opp_enabled == 1) threadCreate(&proc->L1_stats_thread, process_stats_thread,(void *)gNB, "time_meas", -1, OAI_PRIORITY_RT_LOW); + //pthread_create( &proc->pthread_prach, attr_prach, gNB_thread_prach, gNB ); + char name[16]; + + if (gNB->single_thread_flag==0) { + snprintf( name, sizeof(name), "L1 %d", i ); + pthread_setname_np( L1_proc->pthread, name ); + snprintf( name, sizeof(name), "L1TX %d", i ); + pthread_setname_np( L1_proc_tx->pthread, name ); + } + + AssertFatal(proc->instance_cnt_prach == -1,"instance_cnt_prach = %d\n",proc->instance_cnt_prach); /* setup PHY proc TX sync mechanism */ pthread_mutex_init(&sync_phy_proc.mutex_phy_proc_tx, NULL); @@ -795,52 +804,51 @@ void kill_gNB_proc(int inst) { gNB_L1_proc_t *proc; gNB_L1_rxtx_proc_t *L1_proc, *L1_proc_tx; - for (int CC_id=0; CC_idproc; - L1_proc = &proc->L1_proc; - L1_proc_tx = &proc->L1_proc_tx; - LOG_I(PHY, "Killing TX CC_id %d inst %d\n", CC_id, inst ); - - if (get_thread_parallel_conf() == PARALLEL_RU_L1_SPLIT || get_thread_parallel_conf() == PARALLEL_RU_L1_TRX_SPLIT) { - pthread_mutex_lock(&L1_proc->mutex); - L1_proc->instance_cnt = 0; - pthread_cond_signal(&L1_proc->cond); - pthread_mutex_unlock(&L1_proc->mutex); - pthread_mutex_lock(&L1_proc_tx->mutex); - L1_proc_tx->instance_cnt = 0; - pthread_cond_signal(&L1_proc_tx->cond); - pthread_mutex_unlock(&L1_proc_tx->mutex); - } - - proc->instance_cnt_prach = 0; - pthread_cond_signal( &proc->cond_prach ); - pthread_cond_signal( &proc->cond_asynch_rxtx ); - pthread_cond_broadcast(&sync_phy_proc.cond_phy_proc_tx); - // LOG_D(PHY, "joining pthread_prach\n"); - // pthread_join( proc->pthread_prach, (void**)&status ); - LOG_I(PHY, "Destroying prach mutex/cond\n"); - pthread_mutex_destroy( &proc->mutex_prach ); - pthread_cond_destroy( &proc->cond_prach ); - LOG_I(PHY, "Destroying UL_INFO mutex\n"); - pthread_mutex_destroy(&gNB->UL_INFO_mutex); - - if (get_thread_parallel_conf() == PARALLEL_RU_L1_SPLIT || get_thread_parallel_conf() == PARALLEL_RU_L1_TRX_SPLIT) { - LOG_I(PHY, "Joining L1_proc mutex/cond\n"); - pthread_join( L1_proc->pthread, (void **)&status ); - LOG_I(PHY, "Joining L1_proc_tx mutex/cond\n"); - pthread_join( L1_proc_tx->pthread, (void **)&status ); - } - - LOG_I(PHY, "Destroying L1_proc mutex/cond\n"); - pthread_mutex_destroy( &L1_proc->mutex ); - pthread_cond_destroy( &L1_proc->cond ); - LOG_I(PHY, "Destroying L1_proc_tx mutex/cond\n"); - pthread_mutex_destroy( &L1_proc_tx->mutex ); - pthread_cond_destroy( &L1_proc_tx->cond ); - pthread_mutex_destroy( &proc->mutex_RU ); - pthread_mutex_destroy( &proc->mutex_RU_tx ); + gNB=RC.gNB[inst]; + proc = &gNB->proc; + L1_proc = &proc->L1_proc; + L1_proc_tx = &proc->L1_proc_tx; + LOG_I(PHY, "Killing TX inst %d\n",inst ); + + if (get_thread_parallel_conf() == PARALLEL_RU_L1_SPLIT || get_thread_parallel_conf() == PARALLEL_RU_L1_TRX_SPLIT) { + pthread_mutex_lock(&L1_proc->mutex); + L1_proc->instance_cnt = 0; + pthread_cond_signal(&L1_proc->cond); + pthread_mutex_unlock(&L1_proc->mutex); + pthread_mutex_lock(&L1_proc_tx->mutex); + L1_proc_tx->instance_cnt = 0; + pthread_cond_signal(&L1_proc_tx->cond); + pthread_mutex_unlock(&L1_proc_tx->mutex); } + + proc->instance_cnt_prach = 0; + pthread_cond_signal( &proc->cond_prach ); + pthread_cond_signal( &proc->cond_asynch_rxtx ); + pthread_cond_broadcast(&sync_phy_proc.cond_phy_proc_tx); + // LOG_D(PHY, "joining pthread_prach\n"); + // pthread_join( proc->pthread_prach, (void**)&status ); + LOG_I(PHY, "Destroying prach mutex/cond\n"); + pthread_mutex_destroy( &proc->mutex_prach ); + pthread_cond_destroy( &proc->cond_prach ); + LOG_I(PHY, "Destroying UL_INFO mutex\n"); + pthread_mutex_destroy(&gNB->UL_INFO_mutex); + + if (get_thread_parallel_conf() == PARALLEL_RU_L1_SPLIT || get_thread_parallel_conf() == PARALLEL_RU_L1_TRX_SPLIT) { + LOG_I(PHY, "Joining L1_proc mutex/cond\n"); + pthread_join( L1_proc->pthread, (void **)&status ); + LOG_I(PHY, "Joining L1_proc_tx mutex/cond\n"); + pthread_join( L1_proc_tx->pthread, (void **)&status ); + } + + LOG_I(PHY, "Destroying L1_proc mutex/cond\n"); + pthread_mutex_destroy( &L1_proc->mutex ); + pthread_cond_destroy( &L1_proc->cond ); + LOG_I(PHY, "Destroying L1_proc_tx mutex/cond\n"); + pthread_mutex_destroy( &L1_proc_tx->mutex ); + pthread_cond_destroy( &L1_proc_tx->cond ); + pthread_mutex_destroy( &proc->mutex_RU ); + pthread_mutex_destroy( &proc->mutex_RU_tx ); + } @@ -872,48 +880,41 @@ void print_opp_meas(void) { /// eNB kept in function name for nffapi calls, TO FIX void init_eNB_afterRU(void) { - int inst,CC_id,ru_id,i,aa; + int inst,ru_id,i,aa; PHY_VARS_gNB *gNB; LOG_I(PHY,"%s() RC.nb_nr_inst:%d\n", __FUNCTION__, RC.nb_nr_inst); for (inst=0; instnum_RU>0,"Number of RU attached to gNB %d is zero\n",gNB->Mod_id); - // map antennas and PRACH signals to gNB RX - if (0) AssertFatal(gNB->num_RU>0,"Number of RU attached to gNB %d is zero\n",gNB->Mod_id); + LOG_I(PHY,"Mapping RX ports from %d RUs to gNB %d\n",gNB->num_RU,gNB->Mod_id); + LOG_I(PHY,"gNB->num_RU:%d\n", gNB->num_RU); - LOG_I(PHY,"Mapping RX ports from %d RUs to gNB %d\n",gNB->num_RU,gNB->Mod_id); - //LOG_I(PHY,"Overwriting gNB->prach_vars.rxsigF[0]:%p\n", gNB->prach_vars.rxsigF[0]); - // gNB->prach_vars.rxsigF[0] = (int16_t **)malloc16(64*sizeof(int16_t *)); - LOG_I(PHY,"gNB->num_RU:%d\n", gNB->num_RU); - - for (ru_id=0,aa=0; ru_idnum_RU; ru_id++) { - AssertFatal(gNB->RU_list[ru_id]->common.rxdataF!=NULL, - "RU %d : common.rxdataF is NULL\n", - gNB->RU_list[ru_id]->idx); - AssertFatal(gNB->RU_list[ru_id]->prach_rxsigF!=NULL, - "RU %d : prach_rxsigF is NULL\n", - gNB->RU_list[ru_id]->idx); - - for (i=0; iRU_list[ru_id]->nb_rx; aa++,i++) { - LOG_I(PHY,"Attaching RU %d antenna %d to gNB antenna %d\n",gNB->RU_list[ru_id]->idx,i,aa); - // gNB->prach_vars.rxsigF[0][aa] = gNB->RU_list[ru_id]->prach_rxsigF[i]; - gNB->common_vars.rxdataF[aa] = gNB->RU_list[ru_id]->common.rxdataF[i]; - } + for (ru_id=0,aa=0; ru_idnum_RU; ru_id++) { + AssertFatal(gNB->RU_list[ru_id]->common.rxdataF!=NULL, + "RU %d : common.rxdataF is NULL\n", + gNB->RU_list[ru_id]->idx); + AssertFatal(gNB->RU_list[ru_id]->prach_rxsigF!=NULL, + "RU %d : prach_rxsigF is NULL\n", + gNB->RU_list[ru_id]->idx); + + for (i=0; iRU_list[ru_id]->nb_rx; aa++,i++) { + LOG_I(PHY,"Attaching RU %d antenna %d to gNB antenna %d\n",gNB->RU_list[ru_id]->idx,i,aa); + gNB->prach_vars.rxsigF[aa] = gNB->RU_list[ru_id]->prach_rxsigF[i]; + gNB->common_vars.rxdataF[aa] = gNB->RU_list[ru_id]->common.rxdataF[i]; } - - /* TODO: review this code, there is something wrong. - * In monolithic mode, we come here with nb_antennas_rx == 0 - * (not tested in other modes). - */ - //init_precoding_weights(RC.gNB[inst][CC_id]); } + /* TODO: review this code, there is something wrong. + * In monolithic mode, we come here with nb_antennas_rx == 0 + * (not tested in other modes). + */ + //init_precoding_weights(RC.gNB[inst]); init_gNB_proc(inst); } @@ -926,51 +927,52 @@ void init_eNB_afterRU(void) { } void init_gNB(int single_thread_flag,int wait_for_sync) { - int CC_id; + int inst; PHY_VARS_gNB *gNB; - LOG_I(PHY,"[nr-softmodem.c] gNB structure about to be allocated RC.nb_nr_L1_inst:%d RC.nb_nr_L1_CC[0]:%d\n",RC.nb_nr_L1_inst,RC.nb_nr_L1_CC[0]); - if (RC.gNB == NULL) RC.gNB = (PHY_VARS_gNB ***) malloc(RC.nb_nr_L1_inst*sizeof(PHY_VARS_gNB **)); - - LOG_I(PHY,"[lte-softmodem.c] gNB structure RC.gNB allocated\n"); - - for (inst=0; instabstraction_flag = 0; - gNB->single_thread_flag = single_thread_flag; - /*nr_polar_init(&gNB->nrPolar_params, - NR_POLAR_PBCH_MESSAGE_TYPE, - NR_POLAR_PBCH_PAYLOAD_BITS, - NR_POLAR_PBCH_AGGREGATION_LEVEL);*/ - LOG_I(PHY,"Initializing gNB %d CC_id %d single_thread_flag:%d\n",inst,CC_id,single_thread_flag); -#ifndef OCP_FRAMEWORK - LOG_I(PHY,"Initializing gNB %d CC_id %d\n",inst,CC_id); -#endif - LOG_I(PHY,"Registering with MAC interface module\n"); - AssertFatal((gNB->if_inst = NR_IF_Module_init(inst))!=NULL,"Cannot register interface"); - gNB->if_inst->NR_Schedule_response = nr_schedule_response; - gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; - memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); - memset((void *)&gNB->UL_tti_req,0,sizeof(nfapi_nr_ul_tti_request_t)); - //memset((void *)&gNB->Sched_INFO,0,sizeof(gNB->Sched_INFO)); - LOG_I(PHY,"Setting indication lists\n"); - gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = gNB->rx_pdu_list; - gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = gNB->crc_pdu_list; - gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list; - gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = gNB->harq_pdu_list; - gNB->UL_INFO.cqi_ind.cqi_pdu_list = gNB->cqi_pdu_list; - gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list; - - gNB->prach_energy_counter = 0; + if (RC.gNB == NULL) { + RC.gNB = (PHY_VARS_gNB **) malloc((1+RC.nb_nr_L1_inst)*sizeof(PHY_VARS_gNB *)); + for (inst=0; instabstraction_flag = 0; + gNB->single_thread_flag = single_thread_flag; + /*nr_polar_init(&gNB->nrPolar_params, + NR_POLAR_PBCH_MESSAGE_TYPE, + NR_POLAR_PBCH_PAYLOAD_BITS, + NR_POLAR_PBCH_AGGREGATION_LEVEL);*/ + LOG_I(PHY,"Initializing gNB %d single_thread_flag:%d\n",inst,gNB->single_thread_flag); +#ifndef OCP_FRAMEWORK + LOG_I(PHY,"Initializing gNB %d\n",inst); +#endif + + LOG_I(PHY,"Registering with MAC interface module (before %p)\n",gNB->if_inst); + AssertFatal((gNB->if_inst = NR_IF_Module_init(inst))!=NULL,"Cannot register interface"); + LOG_I(PHY,"Registering with MAC interface module (after %p)\n",gNB->if_inst); + gNB->if_inst->NR_Schedule_response = nr_schedule_response; + gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; + memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); + LOG_I(PHY,"Setting indication lists\n"); + gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = gNB->rx_pdu_list; + gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = gNB->crc_pdu_list; + gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list; + gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = gNB->harq_pdu_list; + gNB->UL_INFO.cqi_ind.cqi_pdu_list = gNB->cqi_pdu_list; + gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list; + gNB->prach_energy_counter = 0; + } + + LOG_I(PHY,"[nr-softmodem.c] gNB structure allocated\n"); } diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 0003cf770d..fe10988462 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -50,6 +50,7 @@ #include #include #include +#include #undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all @@ -130,7 +131,8 @@ void configure_rru(int idx, void *arg); int attach_rru(RU_t *ru); int connect_rau(RU_t *ru); -extern uint16_t sl_ahead; +uint16_t sf_ahead; +uint16_t sl_ahead; extern int emulate_rf; extern int numerology; @@ -296,29 +298,24 @@ int connect_rau(RU_t *ru) /* Southbound Fronthaul functions, RCC/RAU */ // southbound IF5 fronthaul for 16-bit OAI format -static inline void fh_if5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) +void fh_if5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) { if (ru == RC.ru[0]) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, ru->proc.timestamp_tx&0xffffffff ); send_IF5(ru, timestamp, slot, &ru->seqno, IF5_RRH_GW_DL); } -// southbound IF5 fronthaul for Mobipass packet format -static inline void fh_if5_mobipass_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) -{ - if (ru == RC.ru[0]) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, ru->proc.timestamp_tx&0xffffffff ); - - send_IF5(ru, timestamp, slot, &ru->seqno, IF5_MOBIPASS); -} - // southbound IF4p5 fronthaul -static inline void fh_if4p5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) +void fh_if4p5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) { + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; if (ru == RC.ru[0]) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, ru->proc.timestamp_tx&0xffffffff ); LOG_D(PHY,"Sending IF4p5 for frame %d subframe %d\n",ru->proc.frame_tx,ru->proc.tti_tx); - if (nr_slot_select(&ru->gNB_list[0]->gNB_config,ru->proc.tti_tx,frame)!=SF_UL) send_IF4p5(ru,frame, slot, IF4p5_PDLFFT); + + if ((nr_slot_select(cfg,ru->proc.frame_tx,ru->proc.tti_tx)&NR_DOWNLINK_SLOT) > 0) + send_IF4p5(ru,frame, slot, IF4p5_PDLFFT); } /*************************************************************/ @@ -332,8 +329,9 @@ void fh_if5_south_in(RU_t *ru, NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; RU_proc_t *proc = &ru->proc; recv_IF5(ru, &proc->timestamp_rx, *tti, IF5_RRH_GW_UL); - proc->frame_rx = (proc->timestamp_rx / (fp->samples_per_slot*20))&1023; - proc->tti_rx = (proc->timestamp_rx / fp->samples_per_slot)%20; + proc->frame_rx = (proc->timestamp_rx / (fp->samples_per_subframe*10))&1023; + uint32_t idx_sf = proc->timestamp_rx / fp->samples_per_subframe; + proc->tti_rx = (idx_sf * fp->slots_per_subframe + (int)round((float)(proc->timestamp_rx % fp->samples_per_subframe) / fp->samples_per_slot0))%(fp->slots_per_frame); if (proc->first_rx == 0) { if (proc->tti_rx != *tti) { @@ -391,12 +389,12 @@ void fh_if4p5_south_in(RU_t *ru, } while(proc->symbol_mask[sl] != symbol_mask_full); //caculate timestamp_rx, timestamp_tx based on frame and subframe - proc->tti_rx = sl; - proc->frame_rx = f; - proc->timestamp_rx = ((proc->frame_rx * fp->slots_per_frame) + proc->tti_rx ) * fp->samples_per_slot ; + proc->tti_rx = sl; + proc->frame_rx = f; + proc->timestamp_rx = (proc->frame_rx * fp->samples_per_subframe * 10) + fp->get_samples_slot_timestamp(proc->tti_rx, fp, 0); // proc->timestamp_tx = proc->timestamp_rx + (4*fp->samples_per_subframe); - proc->tti_tx = (sl+sl_ahead)%fp->slots_per_frame; - proc->frame_tx = (sl>(fp->slots_per_frame-sl_ahead)) ? (f+1)&1023 : f; + proc->tti_tx = (sl+(fp->slots_per_subframe*sf_ahead))%fp->slots_per_frame; + proc->frame_tx = (sl>(fp->slots_per_frame-1-(fp->slots_per_subframe*sf_ahead))) ? (f+1)&1023 : f; if (proc->first_rx == 0) { if (proc->tti_rx != *slot) { @@ -503,8 +501,9 @@ void fh_if5_north_asynch_in(RU_t *ru,int *frame,int *slot) { openair0_timestamp timestamp_tx; recv_IF5(ru, ×tamp_tx, *slot, IF5_RRH_GW_DL); // printf("Received subframe %d (TS %llu) from RCC\n",tti_tx,timestamp_tx); - tti_tx = (timestamp_tx/fp->samples_per_slot)%fp->slots_per_frame; - frame_tx = (timestamp_tx/(fp->samples_per_slot*fp->slots_per_frame))&1023; + frame_tx = (timestamp_tx / (fp->samples_per_subframe*10))&1023; + uint32_t idx_sf = timestamp_tx / fp->samples_per_subframe; + tti_tx = (idx_sf * fp->slots_per_subframe + (int)round((float)(timestamp_tx % fp->samples_per_subframe) / fp->samples_per_slot0))%(fp->slots_per_frame); if (proc->first_tx != 0) { *slot = tti_tx; @@ -520,7 +519,7 @@ void fh_if5_north_asynch_in(RU_t *ru,int *frame,int *slot) { void fh_if4p5_north_asynch_in(RU_t *ru,int *frame,int *slot) { NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; RU_proc_t *proc = &ru->proc; uint16_t packet_type; uint32_t symbol_number,symbol_mask,symbol_mask_full=0; @@ -533,10 +532,10 @@ void fh_if4p5_north_asynch_in(RU_t *ru,int *frame,int *slot) { do { recv_IF4p5(ru, &frame_tx, &slot_tx, &packet_type, &symbol_number); - if ((nr_slot_select(cfg,slot_tx,frame_tx) == SF_DL) && (symbol_number == 0)) start_meas(&ru->rx_fhaul); + if (((nr_slot_select(cfg,frame_tx,slot_tx) & NR_DOWNLINK_SLOT) > 0) && (symbol_number == 0)) start_meas(&ru->rx_fhaul); - LOG_D(PHY,"subframe %d (%d): frame %d, subframe %d, symbol %d\n", - *slot,nr_slot_select(cfg,*slot,*frame),frame_tx,slot_tx,symbol_number); + LOG_D(PHY,"slot %d (%d): frame %d, slot %d, symbol %d\n", + *slot,nr_slot_select(cfg,frame_tx,*slot),frame_tx,slot_tx,symbol_number); if (proc->first_tx != 0) { *frame = frame_tx; @@ -555,14 +554,14 @@ void fh_if4p5_north_asynch_in(RU_t *ru,int *frame,int *slot) { } else AssertFatal(1==0,"Illegal IF4p5 packet type (should only be IF4p5_PDLFFT%d\n",packet_type); } while (symbol_mask != symbol_mask_full); - if (nr_slot_select(cfg,slot_tx,frame_tx) == SF_DL) stop_meas(&ru->rx_fhaul); + if ((nr_slot_select(cfg,frame_tx,slot_tx) & NR_DOWNLINK_SLOT)>0) stop_meas(&ru->rx_fhaul); - proc->tti_tx = slot_tx; - proc->frame_tx = frame_tx; + proc->tti_tx = slot_tx; + proc->frame_tx = frame_tx; if ((frame_tx == 0)&&(slot_tx == 0)) proc->frame_tx_unwrap += 1024; - proc->timestamp_tx = ((((uint64_t)frame_tx + (uint64_t)proc->frame_tx_unwrap) * fp->slots_per_frame) + (uint64_t)slot_tx) * (uint64_t)fp->samples_per_slot; + proc->timestamp_tx = (((uint64_t)frame_tx + (uint64_t)proc->frame_tx_unwrap) * fp->samples_per_subframe * 10) + fp->get_samples_slot_timestamp(slot_tx, fp, 0); LOG_D(PHY,"RU %d/%d TST %llu, frame %d, subframe %d\n",ru->idx,0,(long long unsigned int)proc->timestamp_tx,frame_tx,slot_tx); // dump VCD output for first RU in list @@ -604,7 +603,7 @@ void fh_if4p5_north_out(RU_t *ru) { stop_meas(&ru->tx_fhaul); } -static void *emulatedRF_thread(void *param) { +void *emulatedRF_thread(void *param) { RU_proc_t *proc = (RU_proc_t *) param; int microsec = 500; // length of time to sleep, in miliseconds struct timespec req = {0}; @@ -629,26 +628,27 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { void *rxp[ru->nb_rx]; unsigned int rxs; int i; + uint32_t samples_per_slot = fp->get_samples_per_slot(*slot,fp); openair0_timestamp ts,old_ts; AssertFatal(*slotslots_per_frame && *slot>=0, "slot %d is illegal (%d)\n",*slot,fp->slots_per_frame); for (i=0; inb_rx; i++) - rxp[i] = (void *)&ru->common.rxdata[i][*slot*fp->samples_per_slot]; + rxp[i] = (void *)&ru->common.rxdata[i][fp->get_samples_slot_timestamp(*slot,fp,0)]; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_READ, 1 ); old_ts = proc->timestamp_rx; - LOG_D(PHY,"Reading %d samples for slot %d (%p)\n",fp->samples_per_slot,*slot,rxp[0]); + LOG_D(PHY,"Reading %d samples for slot %d (%p)\n",samples_per_slot,*slot,rxp[0]); if(emulate_rf) { wait_on_condition(&proc->mutex_emulateRF,&proc->cond_emulateRF,&proc->instance_cnt_emulateRF,"emulatedRF_thread"); release_thread(&proc->mutex_emulateRF,&proc->instance_cnt_emulateRF,"emulatedRF_thread"); - rxs = fp->samples_per_slot; + rxs = samples_per_slot; ts = old_ts + rxs; } else { rxs = ru->rfdevice.trx_read_func(&ru->rfdevice, &ts, rxp, - fp->samples_per_slot, + samples_per_slot, ru->nb_rx); } @@ -658,21 +658,22 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { //AssertFatal(rxs == fp->samples_per_subframe, //"rx_rf: Asked for %d samples, got %d from USRP\n",fp->samples_per_subframe,rxs); - if (rxs != fp->samples_per_slot) LOG_E(PHY, "rx_rf: Asked for %d samples, got %d from USRP\n",fp->samples_per_slot,rxs); + if (rxs != samples_per_slot) LOG_E(PHY, "rx_rf: Asked for %d samples, got %d from USRP\n",samples_per_slot,rxs); if (proc->first_rx == 1) { ru->ts_offset = proc->timestamp_rx; proc->timestamp_rx = 0; } else { - if (proc->timestamp_rx - old_ts != fp->samples_per_slot) { - LOG_D(PHY,"rx_rf: rfdevice timing drift of %"PRId64" samples (ts_off %"PRId64")\n",proc->timestamp_rx - old_ts - fp->samples_per_slot,ru->ts_offset); - ru->ts_offset += (proc->timestamp_rx - old_ts - fp->samples_per_slot); + if (proc->timestamp_rx - old_ts != fp->get_samples_per_slot((*slot-1)%fp->slots_per_frame,fp)) { + LOG_D(PHY,"rx_rf: rfdevice timing drift of %"PRId64" samples (ts_off %"PRId64")\n",proc->timestamp_rx - old_ts - samples_per_slot,ru->ts_offset); + ru->ts_offset += (proc->timestamp_rx - old_ts - samples_per_slot); proc->timestamp_rx = ts-ru->ts_offset; } } - proc->frame_rx = (proc->timestamp_rx / (fp->samples_per_slot*fp->slots_per_frame))&1023; - proc->tti_rx = (proc->timestamp_rx / fp->samples_per_slot)%fp->slots_per_frame; + proc->frame_rx = (proc->timestamp_rx / (fp->samples_per_subframe*10))&1023; + uint32_t idx_sf = proc->timestamp_rx / fp->samples_per_subframe; + proc->tti_rx = (idx_sf * fp->slots_per_subframe + (int)round((float)(proc->timestamp_rx % fp->samples_per_subframe) / fp->samples_per_slot0))%(fp->slots_per_frame); // synchronize first reception to frame 0 subframe 0 LOG_D(PHY,"RU %d/%d TS %llu (off %d), frame %d, slot %d.%d / %d\n", ru->idx, @@ -688,7 +689,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { if (proc->first_rx == 0) { if (proc->tti_rx != *slot) { - LOG_E(PHY,"Received Timestamp (%llu) doesn't correspond to the time we think it is (proc->tti_rx %d, subframe %d)\n",(long long unsigned int)proc->timestamp_rx,proc->tti_rx,*slot); + LOG_E(PHY,"Received Timestamp (%llu) doesn't correspond to the time we think it is (proc->tti_rx %d, slot %d)\n",(long long unsigned int)proc->timestamp_rx,proc->tti_rx,*slot); exit_fun("Exiting"); } @@ -705,7 +706,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { //printf("timestamp_rx %lu, frame %d(%d), subframe %d(%d)\n",ru->timestamp_rx,proc->frame_rx,frame,proc->tti_rx,subframe); VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TS, proc->timestamp_rx&0xffffffff ); - if (rxs != fp->samples_per_slot) { + if (rxs != samples_per_slot) { //exit_fun( "problem receiving samples" ); LOG_E(PHY, "problem receiving samples\n"); } @@ -715,69 +716,83 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { RU_proc_t *proc = &ru->proc; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - //nfapi_nr_config_request_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; void *txp[ru->nb_tx]; unsigned int txs; - int i; + int i,txsymb; T(T_ENB_PHY_OUTPUT_SIGNAL, T_INT(0), T_INT(0), T_INT(frame), T_INT(slot), - T_INT(0), T_BUFFER(&ru->common.txdata[0][slot * fp->samples_per_slot], fp->samples_per_slot * 4)); - int sf_extension = 0; - //nr_subframe_t SF_type = nr_slot_select(cfg,slot%fp->slots_per_frame,frame); + T_INT(0), T_BUFFER(&ru->common.txdata[0][fp->get_samples_slot_timestamp(slot,fp,0)], fp->samples_per_subframe * 4)); - if ((slot == 0) || - (slot == 1) || IS_SOFTMODEM_RFSIM ) { - int siglen=fp->samples_per_slot; - int flags; - if (slot==0) - flags = 2; - else if (slot==1) - flags=3; - else - flags=4; + int slot_type = nr_slot_select(cfg,frame,slot%fp->slots_per_frame); + int prevslot_type = nr_slot_select(cfg,frame,(slot+(fp->slots_per_frame-1))%fp->slots_per_frame); + int nextslot_type = nr_slot_select(cfg,frame,(slot+1)%fp->slots_per_frame); + int sf_extension = 0; //sf_extension = ru->sf_extension; + int siglen=fp->get_samples_per_slot(slot,fp); + int flags=1; - /* - if (SF_type == SF_S) { - siglen = fp->dl_symbols_in_S_subframe*(fp->ofdm_symbol_size+fp->nb_prefix_samples0); - flags=3; // end of burst - } - if ((fp->frame_type == TDD) && - (SF_type == SF_DL)&& - (prevSF_type == SF_UL) && - (nextSF_type == SF_DL)) { - flags = 2; // start of burst - sf_extension = ru->N_TA_offset<<1; - } + //nr_subframe_t SF_type = nr_slot_select(cfg,slot%fp->slots_per_frame); + if (slot_type == NR_DOWNLINK_SLOT || slot_type == NR_MIXED_SLOT || IS_SOFTMODEM_RFSIM) { - if ((cfg->subframe_config.duplex_mode == TDD) && - (SF_type == SF_DL)&& - (prevSF_type == SF_UL) && - (nextSF_type == SF_UL)) { - flags = 4; // start of burst and end of burst (only one DL SF between two UL) - sf_extension = ru->N_TA_offset<<1; - } */ - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_RU, frame ); - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU, slot ); - - for (i=0; inb_tx; i++){ - txp[i] = (void *)&ru->common.txdata[i][(slot*fp->samples_per_slot)-sf_extension]; + if(slot_type == NR_MIXED_SLOT) { + txsymb = 0; + for(int symbol_count =0;symbol_counttdd_table.max_tdd_periodicity_list[slot].max_num_of_symbol_per_slot_list[symbol_count].slot_config.value==0) + txsymb++; + } + AssertFatal(txsymb>0,"illegal txsymb %d\n",txsymb); + if(slot%(fp->slots_per_subframe/2)) + siglen = txsymb * (fp->ofdm_symbol_size + fp->nb_prefix_samples); + else + siglen = (fp->ofdm_symbol_size + fp->nb_prefix_samples0) + (txsymb - 1) * (fp->ofdm_symbol_size + fp->nb_prefix_samples); + //+ ru->end_of_burst_delay; + flags=3; // end of burst } + if (cfg->cell_config.frame_duplex_type.value == TDD && + slot_type == NR_DOWNLINK_SLOT && + prevslot_type == NR_UPLINK_SLOT) { + flags = 2; // start of burst + } - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, (timestamp-ru->openair0_cfg.tx_sample_advance)&0xffffffff ); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 1 ); - // prepare tx buffer pointers - start_meas(&ru->tx_fhaul); - txs = ru->rfdevice.trx_write_func(&ru->rfdevice, - timestamp+ru->ts_offset-ru->openair0_cfg.tx_sample_advance-sf_extension, - txp, - siglen+sf_extension, - ru->nb_tx, - flags); - stop_meas(&ru->tx_fhaul); - LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, subframe %d\n",ru->idx, - (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0 ); - AssertFatal(txs == siglen+sf_extension,"TX : Timeout (sent %u/%d)\n", txs, siglen); + if (cfg->cell_config.frame_duplex_type.value == TDD && + slot_type == NR_DOWNLINK_SLOT && + nextslot_type == NR_UPLINK_SLOT) { + flags = 3; // end of burst + } + + if (fp->freq_range==nr_FR2) { + // the beam index is written in bits 8-10 of the flags + // bit 11 enables the gpio programming + int beam=0; + if (slot==0) beam = 11; //3 for boresight & 8 to enable + /* + if (slot==0 || slot==40) beam=0&8; + if (slot==10 || slot==50) beam=1&8; + if (slot==20 || slot==60) beam=2&8; + if (slot==30 || slot==70) beam=3&8; + */ + flags |= beam<<8; + } + + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_WRITE_FLAGS, flags ); + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_RU, frame ); + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU, slot ); + for (i=0; inb_tx; i++) + txp[i] = (void *)&ru->common.txdata[i][fp->get_samples_slot_timestamp(slot,fp,0)-sf_extension]; + + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, (timestamp-ru->openair0_cfg.tx_sample_advance)&0xffffffff ); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 1 ); + // prepare tx buffer pointers + txs = ru->rfdevice.trx_write_func(&ru->rfdevice, + timestamp+ru->ts_offset-ru->openair0_cfg.tx_sample_advance-sf_extension, + txp, + siglen+sf_extension, + ru->nb_tx, + flags); + LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %d\n",ru->idx, + (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0 ); + AssertFatal(txs == siglen+sf_extension,"TX : Timeout (sent %u/%d)\n", txs, siglen); } } @@ -789,11 +804,12 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { * \param param is a \ref gNB_L1_proc_t structure which contains the info what to process. * \returns a pointer to an int. The storage is not on the heap and must not be freed. */ -static void *ru_thread_asynch_rxtx( void *param ) { +void *ru_thread_asynch_rxtx( void *param ) { static int ru_thread_asynch_rxtx_status; RU_t *ru = (RU_t *)param; RU_proc_t *proc = &ru->proc; - int subframe=0, frame=0; + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + int slot=0, frame=0; // wait for top-level synchronization and do one acquisition to get timestamp for setting frame/subframe wait_sync("ru_thread_asynch_rxtx"); // wait for top-level synchronization and do one acquisition to get timestamp for setting frame/subframe @@ -803,22 +819,20 @@ static void *ru_thread_asynch_rxtx( void *param ) { while (!oai_exit) { - if (subframe==9) { - subframe=0; + if (slot==ru->nr_frame_parms->slots_per_frame) { + slot=0; frame++; frame&=1023; } else { - subframe++; + slot++; } LOG_D(PHY,"ru_thread_asynch_rxtx: Waiting on incoming fronthaul\n"); - // asynchronous receive from south (Mobipass) - if (ru->fh_south_asynch_in) ru->fh_south_asynch_in(ru,&frame,&subframe); // asynchronous receive from north (RRU IF4/IF5) - else if (ru->fh_north_asynch_in) { - if (nr_slot_select(&ru->gNB_list[0]->gNB_config,subframe,frame)!=SF_UL) - ru->fh_north_asynch_in(ru,&frame,&subframe); + if (ru->fh_north_asynch_in) { + if ((nr_slot_select(cfg,frame,slot) & NR_DOWNLINK_SLOT)>0) + ru->fh_north_asynch_in(ru,&frame,&slot); } else AssertFatal(1==0,"Unknown function in ru_thread_asynch_rxtx\n"); } @@ -834,7 +848,7 @@ static void *ru_thread_asynch_rxtx( void *param ) { * \param param is a \ref RU_proc_t structure which contains the info what to process. * \returns a pointer to an int. The storage is not on the heap and must not be freed. */ -static void *ru_thread_prach( void *param ) { +void *ru_thread_prach( void *param ) { static int ru_thread_prach_status; RU_t *ru = (RU_t *)param; RU_proc_t *proc = (RU_proc_t *)&ru->proc; @@ -1004,7 +1018,7 @@ void wakeup_gNB_L1s(RU_t *ru) { } } -static inline int wakeup_prach_ru(RU_t *ru) { +int wakeup_prach_ru(RU_t *ru) { struct timespec wait; wait.tv_sec=0; wait.tv_nsec=5000000L; @@ -1039,10 +1053,10 @@ static inline int wakeup_prach_ru(RU_t *ru) { void fill_rf_config(RU_t *ru, char *rf_config_file) { int i; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_t *gNB_config = &ru->gNB_list[0]->gNB_config; //tmp index + nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; //tmp index openair0_config_t *cfg = &ru->openair0_cfg; - int N_RB = gNB_config->rf_config.dl_carrier_bandwidth.value; - int mu = gNB_config->subframe_config.numerology_index_mu.value; + int mu = gNB_config->ssb_config.scs_common.value; + int N_RB = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; if (mu == NR_MU_0) { //or if LTE if(N_RB == 100) { @@ -1111,11 +1125,23 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) { } else { AssertFatal(0==1,"N_RB %d not yet supported for numerology %d\n",N_RB,mu); } + } else if (mu == NR_MU_3) { + if (N_RB == 66) { + cfg->sample_rate = 122.88e6; + cfg->samples_per_frame = 1228800; + cfg->tx_bw = 100e6; + cfg->rx_bw = 100e6; + } else if(N_RB == 32) { + cfg->sample_rate=61.44e6; + cfg->samples_per_frame = 614400; + cfg->tx_bw = 50e6; + cfg->rx_bw = 50e6; + } } else { AssertFatal(0 == 1,"Numerology %d not supported for the moment\n",mu); } - if (gNB_config->subframe_config.duplex_mode.value==TDD) + if (gNB_config->cell_config.frame_duplex_type.value==TDD) cfg->duplex_mode = duplex_mode_TDD; else //FDD cfg->duplex_mode = duplex_mode_FDD; @@ -1126,8 +1152,14 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) { cfg->rx_num_channels=ru->nb_rx; for (i=0; inb_tx; i++) { - cfg->tx_freq[i] = (double)fp->dl_CarrierFreq; - cfg->rx_freq[i] = (double)fp->ul_CarrierFreq; + if (ru->if_frequency == 0) { + cfg->tx_freq[i] = (double)fp->dl_CarrierFreq; + cfg->rx_freq[i] = (double)fp->ul_CarrierFreq; + } + else { + cfg->tx_freq[i] = (double)ru->if_frequency; + cfg->rx_freq[i] = (double)(ru->if_frequency+fp->ul_CarrierFreq-fp->dl_CarrierFreq); + } cfg->tx_gain[i] = ru->att_tx; cfg->rx_gain[i] = ru->max_rxgain-ru->att_rx; cfg->configFilename = rf_config_file; @@ -1199,7 +1231,7 @@ int setup_RU_buffers(RU_t *ru) { return(0); } -static void *ru_stats_thread(void *param) { +void *ru_stats_thread(void *param) { RU_t *ru = (RU_t *)param; wait_sync("ru_stats_thread"); @@ -1230,7 +1262,7 @@ static void *ru_stats_thread(void *param) { return(NULL); } -static void *ru_thread_tx( void *param ) { +void *ru_thread_tx( void *param ) { RU_t *ru = (RU_t *)param; RU_proc_t *proc = &ru->proc; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; @@ -1250,7 +1282,10 @@ static void *ru_thread_tx( void *param ) { LOG_D(PHY,"ru_thread_tx: Waiting for TX processing\n"); // wait until eNBs are finished subframe RX n and TX n+4 + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_RU_TX_WAIT, 1 ); wait_on_condition(&proc->mutex_gNBs,&proc->cond_gNBs,&proc->instance_cnt_gNBs,"ru_thread_tx"); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_RU_TX_WAIT, 0 ); ret = pthread_mutex_lock(&proc->mutex_gNBs); AssertFatal(ret == 0,"mutex_lock return %d\n",ret); @@ -1345,12 +1380,12 @@ static void *ru_thread_tx( void *param ) { // the thread can now be woken up if (L1_proc->instance_cnt_RUs == -1) { L1_proc->instance_cnt_RUs = 0; + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_UE,L1_proc->instance_cnt_RUs); AssertFatal(pthread_cond_signal(&L1_proc->cond_RUs) == 0, "ERROR pthread_cond_signal for gNB_L1_thread\n"); } //else AssertFatal(1==0,"gNB TX thread is not ready\n"); ret = pthread_mutex_unlock(&L1_proc->mutex_RUs_tx); AssertFatal(ret == 0,"mutex_unlock returns %d\n",ret); - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_UE,L1_proc->instance_cnt_RUs); } } } @@ -1359,7 +1394,7 @@ static void *ru_thread_tx( void *param ) { return 0; } -static void *ru_thread( void *param ) { +void *ru_thread( void *param ) { static int ru_thread_status; RU_t *ru = (RU_t *)param; RU_proc_t *proc = &ru->proc; @@ -1372,6 +1407,8 @@ static void *ru_thread( void *param ) { int i = 0; int aa; + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + // set default return value ru_thread_status = 0; // set default return value @@ -1417,6 +1454,7 @@ static void *ru_thread( void *param ) { } } + sf_ahead = (uint16_t) ceil((float)6/(0x01<numerology_index)); LOG_I(PHY, "Signaling main thread that RU %d is ready\n",ru->idx); pthread_mutex_lock(&RC.ru_mutex); RC.ru_mask &= ~(1<idx); @@ -1468,12 +1506,12 @@ static void *ru_thread( void *param ) { if (ru->fh_south_in) ru->fh_south_in(ru,&frame,&slot); else AssertFatal(1==0, "No fronthaul interface at south port"); - LOG_D(PHY,"AFTER fh_south_in - SFN/SL:%d%d RU->proc[RX:%d.%d TX:%d.%d] RC.gNB[0][0]:[RX:%d%d TX(SFN):%d]\n", + LOG_D(PHY,"AFTER fh_south_in - SFN/SL:%d%d RU->proc[RX:%d.%d TX:%d.%d] RC.gNB[0]:[RX:%d%d TX(SFN):%d]\n", frame,slot, proc->frame_rx,proc->tti_rx, proc->frame_tx,proc->tti_tx, - RC.gNB[0][0]->proc.frame_rx,RC.gNB[0][0]->proc.slot_rx, - RC.gNB[0][0]->proc.frame_tx); + RC.gNB[0]->proc.frame_rx,RC.gNB[0]->proc.slot_rx, + RC.gNB[0]->proc.frame_tx); /* LOG_D(PHY,"RU thread (do_prach %d, is_prach_subframe %d), received frame %d, subframe %d\n", ru->do_prach, @@ -1490,19 +1528,21 @@ static void *ru_thread( void *param ) { // do RX front-end processing (frequency-shift, dft) if needed - if (proc->tti_rx == NR_UPLINK_SLOT || fp->frame_type == FDD) { + int slot_type = nr_slot_select(cfg,proc->frame_rx,proc->tti_rx); + if (slot_type == NR_UPLINK_SLOT || slot_type == NR_MIXED_SLOT) { + //if (proc->tti_rx==8) { if (ru->feprx) ru->feprx(ru,proc->tti_rx); + //LOG_M("rxdata.m","rxs",ru->common.rxdata[0],1228800,1,1); + LOG_D(PHY,"RU proc: frame_rx = %d, tti_rx = %d\n", proc->frame_rx, proc->tti_rx); + LOG_D(PHY,"Copying rxdataF from RU to gNB\n"); + + for (aa=0;aanb_rx;aa++) + memcpy((void*)RC.gNB[0]->common_vars.rxdataF[aa], + (void*)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t)); } - LOG_D(PHY,"RU proc: frame_rx = %d, tti_rx = %d\n", proc->frame_rx, proc->tti_rx); - LOG_D(PHY,"Copying rxdataF from RU to gNB\n"); - - for (aa=0;aanb_rx;aa++) - memcpy((void*)RC.gNB[0][0]->common_vars.rxdataF[aa], - (void*)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t)); - // At this point, all information for subframe has been received on FH interface // wakeup all gNB processes waiting for this RU @@ -1814,19 +1854,19 @@ int check_capabilities(RU_t *ru,RRU_capabilities_t *cap) FH_fmt_options_t fmt = cap->FH_fmt; int i; int found_band=0; - LOG_I(PHY,"RRU %d, num_bands %d, looking for band %d\n",ru->idx,cap->num_bands,ru->nr_frame_parms->eutra_band); + LOG_I(PHY,"RRU %d, num_bands %d, looking for band %d\n",ru->idx,cap->num_bands,ru->nr_frame_parms->nr_band); for (i=0; inum_bands; i++) { LOG_I(PHY,"band %d on RRU %d\n",cap->band_list[i],ru->idx); - if (ru->nr_frame_parms->eutra_band == cap->band_list[i]) { + if (ru->nr_frame_parms->nr_band == cap->band_list[i]) { found_band=1; break; } } if (found_band == 0) { - LOG_I(PHY,"Couldn't find target EUTRA band %d on RRU %d\n",ru->nr_frame_parms->eutra_band,ru->idx); + LOG_I(PHY,"Couldn't find target NR band %d on RRU %d\n",ru->nr_frame_parms->nr_band,ru->idx); return(-1); } @@ -1871,7 +1911,7 @@ void configure_ru(int idx, RU_t *ru = RC.ru[idx]; RRU_config_t *config = (RRU_config_t *)arg; RRU_capabilities_t *capabilities = (RRU_capabilities_t *)arg; - nfapi_nr_config_request_t *gNB_config = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; int ret; LOG_I(PHY, "Received capabilities from RRU %d\n",idx); @@ -1883,19 +1923,19 @@ void configure_ru(int idx, ru->nb_tx = capabilities->nb_tx[0]; ru->nb_rx = capabilities->nb_rx[0]; // Pass configuration to RRU - LOG_I(PHY, "Using %s fronthaul (%d), band %d \n",ru_if_formats[ru->if_south],ru->if_south,ru->nr_frame_parms->eutra_band); + LOG_I(PHY, "Using %s fronthaul (%d), band %d \n",ru_if_formats[ru->if_south],ru->if_south,ru->nr_frame_parms->nr_band); // wait for configuration config->FH_fmt = ru->if_south; config->num_bands = 1; - config->band_list[0] = ru->nr_frame_parms->eutra_band; + config->band_list[0] = ru->nr_frame_parms->nr_band; config->tx_freq[0] = ru->nr_frame_parms->dl_CarrierFreq; config->rx_freq[0] = ru->nr_frame_parms->ul_CarrierFreq; //config->tdd_config[0] = ru->nr_frame_parms->tdd_config; //config->tdd_config_S[0] = ru->nr_frame_parms->tdd_config_S; config->att_tx[0] = ru->att_tx; config->att_rx[0] = ru->att_rx; - config->N_RB_DL[0] = gNB_config->rf_config.dl_carrier_bandwidth.value; - config->N_RB_UL[0] = gNB_config->rf_config.ul_carrier_bandwidth.value; + config->N_RB_DL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; + config->N_RB_UL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; config->threequarter_fs[0] = ru->nr_frame_parms->threequarter_fs; /* if (ru->if_south==REMOTE_IF4p5) { config->prach_FreqOffset[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset; @@ -1910,22 +1950,23 @@ void configure_rru(int idx, void *arg) { RRU_config_t *config = (RRU_config_t *)arg; RU_t *ru = RC.ru[idx]; - nfapi_nr_config_request_t *gNB_config = &ru->gNB_list[0]->gNB_config; - ru->nr_frame_parms->eutra_band = config->band_list[0]; + nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; + ru->nr_frame_parms->nr_band = config->band_list[0]; ru->nr_frame_parms->dl_CarrierFreq = config->tx_freq[0]; ru->nr_frame_parms->ul_CarrierFreq = config->rx_freq[0]; if (ru->nr_frame_parms->dl_CarrierFreq == ru->nr_frame_parms->ul_CarrierFreq) { - gNB_config->subframe_config.duplex_mode.value = TDD; + gNB_config->cell_config.frame_duplex_type.value = TDD; //ru->nr_frame_parms->tdd_config = config->tdd_config[0]; //ru->nr_frame_parms->tdd_config_S = config->tdd_config_S[0]; } else - gNB_config->subframe_config.duplex_mode.value = FDD; + gNB_config->cell_config.frame_duplex_type.value = FDD; ru->att_tx = config->att_tx[0]; ru->att_rx = config->att_rx[0]; - gNB_config->rf_config.dl_carrier_bandwidth.value = config->N_RB_DL[0]; - gNB_config->rf_config.ul_carrier_bandwidth.value = config->N_RB_UL[0]; + int mu = gNB_config->ssb_config.scs_common.value; + gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0]; + gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0]; ru->nr_frame_parms->threequarter_fs = config->threequarter_fs[0]; //ru->nr_frame_parms->pdsch_config_common.referenceSignalPower = ru->max_pdschReferenceSignalPower-config->att_tx[0]; @@ -2117,8 +2158,6 @@ void set_function_spec_param(RU_t *ru) { } // switch on interface type } -extern void RCconfig_RU(void); - void init_NR_RU(char *rf_config_file) { int ru_id; @@ -2137,10 +2176,6 @@ void init_NR_RU(char *rf_config_file) RCconfig_RU(); LOG_I(PHY,"number of L1 instances %d, number of RU %d, number of CPU cores %d\n",RC.nb_nr_L1_inst,RC.nb_RU,get_nprocs()); - if (RC.nb_nr_CC != 0) - for (i=0; inum_RU=0; - LOG_D(PHY,"Process RUs RC.nb_RU:%d\n",RC.nb_RU); for (ru_id=0; ru_idnum_gNB > 0) { - LOG_D(PHY, "%s() RC.ru[%d].num_gNB:%d ru->gNB_list[0]:%p RC.gNB[0][0]:%p rf_config_file:%s\n", __FUNCTION__, ru_id, ru->num_gNB, ru->gNB_list[0], RC.gNB[0][0], ru->rf_config_file); + LOG_D(PHY, "%s() RC.ru[%d].num_gNB:%d ru->gNB_list[0]:%p RC.gNB[0]:%p rf_config_file:%s\n", __FUNCTION__, ru_id, ru->num_gNB, ru->gNB_list[0], RC.gNB[0], ru->rf_config_file); if (ru->gNB_list[0] == 0) { LOG_E(PHY,"%s() DJP - ru->gNB_list ru->num_gNB are not initialized - so do it manually\n", __FUNCTION__); - ru->gNB_list[0] = RC.gNB[0][0]; + ru->gNB_list[0] = RC.gNB[0]; ru->num_gNB=1; // // DJP - feptx_prec() / feptx_ofdm() parses the gNB_list (based on num_gNB) and copies the txdata_F to txdata in RU @@ -2167,7 +2202,7 @@ void init_NR_RU(char *rf_config_file) } } - gNB_RC = RC.gNB[0][0]; + gNB_RC = RC.gNB[0]; gNB0 = ru->gNB_list[0]; fp = ru->nr_frame_parms; LOG_D(PHY, "RU FUnction:%d ru->if_south:%d\n", ru->function, ru->if_south); @@ -2239,7 +2274,7 @@ void RCconfig_RU(void) else RC.ru[j]->num_gNB = 0; - for (i=0; inum_gNB; i++) RC.ru[j]->gNB_list[i] = RC.gNB[RUParamList.paramarray[j][RU_ENB_LIST_IDX].iptr[i]][0]; + for (i=0; inum_gNB; i++) RC.ru[j]->gNB_list[i] = RC.gNB[RUParamList.paramarray[j][RU_ENB_LIST_IDX].iptr[i]]; if (config_isparamset(RUParamList.paramarray[j], RU_SDR_ADDRS)) { RC.ru[j]->openair0_cfg.sdr_addrs = strdup(*(RUParamList.paramarray[j][RU_SDR_ADDRS].strptr)); @@ -2332,18 +2367,14 @@ void RCconfig_RU(void) RC.ru[j]->if_south = REMOTE_IF4p5; RC.ru[j]->function = NGFI_RAU_IF4p5; RC.ru[j]->eth_params.transp_preference = ETH_RAW_IF4p5_MODE; - } else if (strcmp(*(RUParamList.paramarray[j][RU_TRANSPORT_PREFERENCE_IDX].strptr), "raw_if5_mobipass") == 0) { - RC.ru[j]->if_south = REMOTE_IF5; - RC.ru[j]->function = NGFI_RAU_IF5; - RC.ru[j]->if_timing = synch_to_other; - RC.ru[j]->eth_params.transp_preference = ETH_RAW_IF5_MOBIPASS; - } + } } /* strcmp(local_rf, "yes") != 0 */ RC.ru[j]->nb_tx = *(RUParamList.paramarray[j][RU_NB_TX_IDX].uptr); RC.ru[j]->nb_rx = *(RUParamList.paramarray[j][RU_NB_RX_IDX].uptr); RC.ru[j]->att_tx = *(RUParamList.paramarray[j][RU_ATT_TX_IDX].uptr); RC.ru[j]->att_rx = *(RUParamList.paramarray[j][RU_ATT_RX_IDX].uptr); + RC.ru[j]->if_frequency = *(RUParamList.paramarray[j][RU_IF_FREQUENCY].u64ptr); if (config_isparamset(RUParamList.paramarray[j], RU_BF_WEIGHTS_LIST_IDX)) { RC.ru[j]->nb_bfw = RUParamList.paramarray[j][RU_BF_WEIGHTS_LIST_IDX].numelt; @@ -2359,3 +2390,4 @@ void RCconfig_RU(void) return; } + diff --git a/executables/nr-softmodem-common.h b/executables/nr-softmodem-common.h index e6aafafeb9..ccb3f28d98 100644 --- a/executables/nr-softmodem-common.h +++ b/executables/nr-softmodem-common.h @@ -83,6 +83,7 @@ #define CONFIG_HLP_TNOFORK "to ease debugging with gdb\n" #define CONFIG_HLP_DISABLNBIOT "disable nb-iot, even if defined in config\n" #define CONFIG_HLP_DISABLETIMECORR "disable UE timing correction\n" +#define CONFIG_HLP_RRC_CFG_PATH "path for RRC configuration\n" #define CONFIG_HLP_NUMEROLOGY "adding numerology for 5G\n" #define CONFIG_HLP_EMULATE_RF "Emulated RF enabled(disable by defult)\n" @@ -126,7 +127,7 @@ extern pthread_mutex_t sync_mutex; extern int sync_var; -extern uint32_t downlink_frequency[MAX_NUM_CCs][4]; +extern uint64_t downlink_frequency[MAX_NUM_CCs][4]; extern int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; extern int rx_input_level_dBm; diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index df6c48d866..04c515e556 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -84,6 +84,7 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "executables/softmodem-common.h" #include "executables/thread-common.h" #include "NB_IoT_interface.h" +#include "x2ap_eNB.h" short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,16384,-16384,-16384,16384,-16384,-16384,7327,7327,7327,21981,21981,7327,21981,21981,7327,-7327,7327,-21981,21981,-7327,21981,-21981,-7327,7327,-7327,21981,-21981,7327,-21981,21981,-7327,-7327,-7327,-21981,-21981,-7327,-21981,-21981,10726,10726,10726,3576,3576,10726,3576,3576,10726,17876,10726,25027,3576,17876,3576,25027,17876,10726,17876,3576,25027,10726,25027,3576,17876,17876,17876,25027,25027,17876,25027,25027,10726,-10726,10726,-3576,3576,-10726,3576,-3576,10726,-17876,10726,-25027,3576,-17876,3576,-25027,17876,-10726,17876,-3576,25027,-10726,25027,-3576,17876,-17876,17876,-25027,25027,-17876,25027,-25027,-10726,10726,-10726,3576,-3576,10726,-3576,3576,-10726,17876,-10726,25027,-3576,17876,-3576,25027,-17876,10726,-17876,3576,-25027,10726,-25027,3576,-17876,17876,-17876,25027,-25027,17876,-25027,25027,-10726,-10726,-10726,-3576,-3576,-10726,-3576,-3576,-10726,-17876,-10726,-25027,-3576,-17876,-3576,-25027,-17876,-10726,-17876,-3576,-25027,-10726,-25027,-3576,-17876,-17876,-17876,-25027,-25027,-17876,-25027,-25027,8886,8886,8886,12439,12439,8886,12439,12439,8886,5332,8886,1778,12439,5332,12439,1778,5332,8886,5332,12439,1778,8886,1778,12439,5332,5332,5332,1778,1778,5332,1778,1778,8886,19547,8886,15993,12439,19547,12439,15993,8886,23101,8886,26655,12439,23101,12439,26655,5332,19547,5332,15993,1778,19547,1778,15993,5332,23101,5332,26655,1778,23101,1778,26655,19547,8886,19547,12439,15993,8886,15993,12439,19547,5332,19547,1778,15993,5332,15993,1778,23101,8886,23101,12439,26655,8886,26655,12439,23101,5332,23101,1778,26655,5332,26655,1778,19547,19547,19547,15993,15993,19547,15993,15993,19547,23101,19547,26655,15993,23101,15993,26655,23101,19547,23101,15993,26655,19547,26655,15993,23101,23101,23101,26655,26655,23101,26655,26655,8886,-8886,8886,-12439,12439,-8886,12439,-12439,8886,-5332,8886,-1778,12439,-5332,12439,-1778,5332,-8886,5332,-12439,1778,-8886,1778,-12439,5332,-5332,5332,-1778,1778,-5332,1778,-1778,8886,-19547,8886,-15993,12439,-19547,12439,-15993,8886,-23101,8886,-26655,12439,-23101,12439,-26655,5332,-19547,5332,-15993,1778,-19547,1778,-15993,5332,-23101,5332,-26655,1778,-23101,1778,-26655,19547,-8886,19547,-12439,15993,-8886,15993,-12439,19547,-5332,19547,-1778,15993,-5332,15993,-1778,23101,-8886,23101,-12439,26655,-8886,26655,-12439,23101,-5332,23101,-1778,26655,-5332,26655,-1778,19547,-19547,19547,-15993,15993,-19547,15993,-15993,19547,-23101,19547,-26655,15993,-23101,15993,-26655,23101,-19547,23101,-15993,26655,-19547,26655,-15993,23101,-23101,23101,-26655,26655,-23101,26655,-26655,-8886,8886,-8886,12439,-12439,8886,-12439,12439,-8886,5332,-8886,1778,-12439,5332,-12439,1778,-5332,8886,-5332,12439,-1778,8886,-1778,12439,-5332,5332,-5332,1778,-1778,5332,-1778,1778,-8886,19547,-8886,15993,-12439,19547,-12439,15993,-8886,23101,-8886,26655,-12439,23101,-12439,26655,-5332,19547,-5332,15993,-1778,19547,-1778,15993,-5332,23101,-5332,26655,-1778,23101,-1778,26655,-19547,8886,-19547,12439,-15993,8886,-15993,12439,-19547,5332,-19547,1778,-15993,5332,-15993,1778,-23101,8886,-23101,12439,-26655,8886,-26655,12439,-23101,5332,-23101,1778,-26655,5332,-26655,1778,-19547,19547,-19547,15993,-15993,19547,-15993,15993,-19547,23101,-19547,26655,-15993,23101,-15993,26655,-23101,19547,-23101,15993,-26655,19547,-26655,15993,-23101,23101,-23101,26655,-26655,23101,-26655,26655,-8886,-8886,-8886,-12439,-12439,-8886,-12439,-12439,-8886,-5332,-8886,-1778,-12439,-5332,-12439,-1778,-5332,-8886,-5332,-12439,-1778,-8886,-1778,-12439,-5332,-5332,-5332,-1778,-1778,-5332,-1778,-1778,-8886,-19547,-8886,-15993,-12439,-19547,-12439,-15993,-8886,-23101,-8886,-26655,-12439,-23101,-12439,-26655,-5332,-19547,-5332,-15993,-1778,-19547,-1778,-15993,-5332,-23101,-5332,-26655,-1778,-23101,-1778,-26655,-19547,-8886,-19547,-12439,-15993,-8886,-15993,-12439,-19547,-5332,-19547,-1778,-15993,-5332,-15993,-1778,-23101,-8886,-23101,-12439,-26655,-8886,-26655,-12439,-23101,-5332,-23101,-1778,-26655,-5332,-26655,-1778,-19547,-19547,-19547,-15993,-15993,-19547,-15993,-15993,-19547,-23101,-19547,-26655,-15993,-23101,-15993,-26655,-23101,-19547,-23101,-15993,-26655,-19547,-26655,-15993,-23101,-23101,-23101,-26655,-26655,-23101,-26655,-26655}; @@ -109,7 +110,7 @@ int single_thread_flag=1; static int8_t threequarter_fs=0; -uint32_t downlink_frequency[MAX_NUM_CCs][4]; +uint64_t downlink_frequency[MAX_NUM_CCs][4]; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; //Temp fix for inexistent NR upper layer @@ -200,7 +201,7 @@ char uecap_xer_in=0; uint8_t abstraction_flag=0; /* forward declarations */ -void set_default_frame_parms(nfapi_nr_config_request_t *config[MAX_NUM_CCs], NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]); +void set_default_frame_parms(nfapi_nr_config_request_scf_t *config[MAX_NUM_CCs], NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]); /*---------------------BMC: timespec helpers -----------------------------*/ @@ -385,6 +386,18 @@ int create_gNB_tasks(uint32_t gnb_nb) { LOG_E(GNB_APP, "Create task for gNB APP failed\n"); return -1; } + if(itti_create_task(TASK_SCTP, sctp_eNB_task, NULL) < 0){ + LOG_E(SCTP, "Create task for SCTP failed\n"); + return -1; + } + if (is_x2ap_enabled()) { + if(itti_create_task(TASK_X2AP, x2ap_task, NULL) < 0){ + LOG_E(X2AP, "Create task for X2AP failed\n"); + } + } + else { + LOG_I(X2AP, "X2AP is disabled.\n"); + } } /* @@ -453,18 +466,18 @@ static void get_options(void) { } -void set_default_frame_parms(nfapi_nr_config_request_t *config[MAX_NUM_CCs], - NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]) +void set_default_frame_parms(nfapi_nr_config_request_scf_t *config[MAX_NUM_CCs], + NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]) { for (int CC_id=0; CC_idsubframe_config.numerology_index_mu.value =1; - config[CC_id]->subframe_config.duplex_mode.value = 1; //FDD - config[CC_id]->subframe_config.dl_cyclic_prefix_type.value = 0; //NORMAL - config[CC_id]->rf_config.dl_carrier_bandwidth.value = 106; - config[CC_id]->rf_config.ul_carrier_bandwidth.value = 106; - config[CC_id]->sch_config.physical_cell_id.value = 0; + config[CC_id] = (nfapi_nr_config_request_scf_t *) malloc(sizeof(nfapi_nr_config_request_scf_t)); + config[CC_id]->ssb_config.scs_common.value = 1; + config[CC_id]->cell_config.frame_duplex_type.value = 1; //FDD + //config[CC_id]->subframe_config.dl_cyclic_prefix_type.value = 0; //NORMAL + config[CC_id]->carrier_config.dl_grid_size[1].value = 106; + config[CC_id]->carrier_config.ul_grid_size[1].value = 106; + config[CC_id]->cell_config.phy_cell_id.value = 0; ///dl frequency to be filled in /* //Set some default values that may be overwritten while reading options frame_parms[CC_id]->frame_type = FDD; @@ -476,7 +489,7 @@ void set_default_frame_parms(nfapi_nr_config_request_t *config[MAX_NUM_CCs], frame_parms[CC_id]->Ncp_UL = NORMAL; frame_parms[CC_id]->Nid_cell = 0; frame_parms[CC_id]->num_MBSFN_config = 0; - frame_parms[CC_id]->nb_antenna_ports_eNB = 1; + frame_parms[CC_id]->nb_antenna_ports_gNB = 1; frame_parms[CC_id]->nb_antennas_tx = 1; frame_parms[CC_id]->nb_antennas_rx = 1; @@ -553,8 +566,8 @@ void init_openair0(void) { openair0_cfg[card].duplex_mode = duplex_mode_FDD; printf("HW: Configuring card %d, nb_antennas_tx/rx %d/%d\n",card, - RC.gNB[0][0]->gNB_config.rf_config.tx_antenna_ports.value, - RC.gNB[0][0]->gNB_config.rf_config.tx_antenna_ports.value ); + RC.gNB[0]->gNB_config.rf_config.tx_antenna_ports.value, + RC.gNB[0]->gNB_config.rf_config.tx_antenna_ports.value ); openair0_cfg[card].Mod_id = 0; openair0_cfg[card].num_rb_dl=config[0]->rf_config.dl_carrier_bandwidth.value; @@ -562,8 +575,8 @@ void init_openair0(void) { openair0_cfg[card].clock_source = clock_source; - openair0_cfg[card].tx_num_channels=min(2,RC.gNB[0][0]->gNB_config.rf_config.tx_antenna_ports.value ); - openair0_cfg[card].rx_num_channels=min(2,RC.gNB[0][0]->gNB_config.rf_config.tx_antenna_ports.value ); + openair0_cfg[card].tx_num_channels=min(2,RC.gNB[0]->gNB_config.rf_config.tx_antenna_ports.value ); + openair0_cfg[card].rx_num_channels=min(2,RC.gNB[0]->gNB_config.rf_config.tx_antenna_ports.value ); for (i=0; i<4; i++) { @@ -579,7 +592,7 @@ void init_openair0(void) { openair0_cfg[card].autocal[i] = 1; openair0_cfg[card].tx_gain[i] = tx_gain[0][i]; - openair0_cfg[card].rx_gain[i] = RC.gNB[0][0]->rx_total_gain_dB; + openair0_cfg[card].rx_gain[i] = RC.gNB[0]->rx_total_gain_dB; openair0_cfg[card].configFilename = get_softmodem_params()->rf_config_file; @@ -608,7 +621,7 @@ void wait_RUs(void) { } void wait_gNBs(void) { - int i,j; + int i; int waiting=1; while (waiting==1) { @@ -617,13 +630,10 @@ void wait_gNBs(void) { waiting=0; for (i=0; iconfigured==0) { - waiting=1; - break; - } + if (RC.gNB[i]->configured==0) { + waiting=1; + break; } } } @@ -682,10 +692,9 @@ int stop_L1L2(module_id_t gnb_id) { kill_NR_RU_proc(gnb_id); oai_exit = 0; - for (int cc_id = 0; cc_id < RC.nb_nr_CC[gnb_id]; cc_id++) { - //free_transport(RC.gNB[gnb_id][cc_id]); - phy_free_nr_gNB(RC.gNB[gnb_id][cc_id]); - } + //free_transport(RC.gNB[gnb_id]); + phy_free_nr_gNB(RC.gNB[gnb_id]); + nr_phy_free_RU(RC.ru[gnb_id]); free_lte_top(); @@ -703,14 +712,13 @@ int restart_L1L2(module_id_t gnb_id) { /* block threads */ sync_var = -1; - for (cc_id = 0; cc_id < RC.nb_nr_L1_CC[gnb_id]; cc_id++) { - RC.gNB[gnb_id][cc_id]->configured = 0; - } + RC.gNB[gnb_id]->configured = 0; + RC.ru_mask |= (1 << ru->idx); /* copy the changed frame parameters to the RU */ /* TODO this should be done for all RUs associated to this gNB */ - memcpy(&ru->nr_frame_parms, &RC.gNB[gnb_id][0]->frame_parms, sizeof(NR_DL_FRAME_PARMS)); + memcpy(&ru->nr_frame_parms, &RC.gNB[gnb_id]->frame_parms, sizeof(NR_DL_FRAME_PARMS)); set_function_spec_param(RC.ru[gnb_id]); LOG_I(GNB_APP, "attempting to create ITTI tasks\n"); @@ -784,9 +792,10 @@ void init_pdcp(void) { }*/ } + int main( int argc, char **argv ) { - int i, ru_id, CC_id = 0; + int ru_id, CC_id = 0; start_background_system(); ///static configuration for NR at the moment @@ -859,11 +868,13 @@ if(!IS_SOFTMODEM_NOS1) } /* Start the agent. If it is turned off in the configuration, it won't start */ + /* RCconfig_nr_flexran(); for (i = 0; i < RC.nb_nr_L1_inst; i++) { flexran_agent_start(i); } +*/ // init UE_PF_PO and mutex lock pthread_mutex_init(&ue_pf_po_mutex, NULL); @@ -871,38 +882,8 @@ if(!IS_SOFTMODEM_NOS1) mlockall(MCL_CURRENT | MCL_FUTURE); pthread_cond_init(&sync_cond,NULL); pthread_mutex_init(&sync_mutex, NULL); -/*#ifdef XFORMS - int UE_id; - if (do_forms==1) { - fl_initialize (&argc, argv, NULL, 0, 0); - form_stats_l2 = create_form_stats_form(); - fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats"); - form_stats = create_form_stats_form(); - fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats"); - - for(UE_id=0; UE_idphy_scope_gnb, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - - if (otg_enabled) { - fl_set_button(form_gnb[CC_id][UE_id]->button_0,1); - fl_set_object_label(form_gnb[CC_id][UE_id]->button_0,"DL Traffic ON"); - } else { - fl_set_button(form_gnb[CC_id][UE_id]->button_0,0); - fl_set_object_label(form_gnb[CC_id][UE_id]->button_0,"DL Traffic OFF"); - } - } // CC_id - } // UE_id - - threadCreate(&forms_thread, scope_thread, NULL, "scope", -1, OAI_PRIORITY_RT_LOW); - printf("Scope thread created, ret=%d\n",ret); - } - -#endif*/ - usleep(10*1000); + usleep(1000); if (nfapi_mode) { printf("NFAPI*** - mutex and cond created - will block shortly for completion of PNF connection\n"); @@ -972,6 +953,13 @@ if(!IS_SOFTMODEM_NOS1) // once all RUs are ready initialize the rest of the gNBs ((dependence on final RU parameters after configuration) printf("ALL RUs ready - init gNBs\n"); + if (do_forms==1) { + scopeParms_t p; + p.argc=&argc; + p.argv=argv; + startScope(&p); + } + if (nfapi_mode != 1 && nfapi_mode != 2) { printf("Not NFAPI mode - call init_eNB_afterRU()\n"); init_eNB_afterRU(); @@ -1028,10 +1016,8 @@ if(!IS_SOFTMODEM_NOS1) /* release memory used by the RU/gNB threads (incomplete), after all * threads have been stopped (they partially use the same memory) */ for (int inst = 0; inst < NB_gNB_INST; inst++) { - for (int cc_id = 0; cc_id < RC.nb_nr_CC[inst]; cc_id++) { - //free_transport(RC.gNB[inst][cc_id]); - phy_free_nr_gNB(RC.gNB[inst][cc_id]); - } + //free_transport(RC.gNB[inst]); + phy_free_nr_gNB(RC.gNB[inst]); } for (int inst = 0; inst < NB_RU; inst++) { diff --git a/executables/nr-softmodem.h b/executables/nr-softmodem.h index 20316bff2e..27e3ba1e3e 100644 --- a/executables/nr-softmodem.h +++ b/executables/nr-softmodem.h @@ -22,7 +22,7 @@ {"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&wait_for_sync, defintval:0, TYPE_INT, 0}, \ {"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \ {"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \ - {"C" , CONFIG_HLP_DLF, 0, uptr:&(downlink_frequency[0][0]), defuintval:DEFAULT_DLF, TYPE_UINT, 0}, \ + {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:DEFAULT_DLF, TYPE_UINT64, 0}, \ {"a" , CONFIG_HLP_CHOFF, 0, iptr:&chain_offset, defintval:0, TYPE_INT, 0}, \ {"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:(uint32_t *)&do_forms, defintval:0, TYPE_INT8, 0}, \ {"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, i8ptr:&threequarter_fs, defintval:0, TYPE_INT8, 0}, \ diff --git a/executables/nr-ue.c b/executables/nr-ue.c index b4af0f68ea..131710ee02 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -136,14 +136,12 @@ typedef enum { } sync_mode_t; -PHY_VARS_NR_UE *init_nr_ue_vars(NR_DL_FRAME_PARMS *frame_parms, - uint8_t UE_id, - uint8_t abstraction_flag) - +void init_nr_ue_vars(PHY_VARS_NR_UE *ue, + NR_DL_FRAME_PARMS *frame_parms, + uint8_t UE_id, + uint8_t abstraction_flag) { - PHY_VARS_NR_UE *ue; - ue = (PHY_VARS_NR_UE *)malloc(sizeof(PHY_VARS_NR_UE)); - memset(ue,0,sizeof(PHY_VARS_NR_UE)); + memcpy(&(ue->frame_parms), frame_parms, sizeof(NR_DL_FRAME_PARMS)); ue->Mod_id = UE_id; @@ -153,7 +151,6 @@ PHY_VARS_NR_UE *init_nr_ue_vars(NR_DL_FRAME_PARMS *frame_parms, init_nr_ue_signal(ue,1,abstraction_flag); // intialize transport init_nr_ue_transport(ue,abstraction_flag); - return(ue); } /*! @@ -175,22 +172,19 @@ static void UE_synch(void *arg) { int freq_offset=0; UE->is_synchronized = 0; - if (UE->UE_scan == 0) { - get_band(downlink_frequency[CC_id][0], &UE->frame_parms.eutra_band, &uplink_frequency_offset[CC_id][0], &UE->frame_parms.frame_type); - LOG_I( PHY, "[SCHED][UE] Check absolute frequency DL %"PRIu32", UL %"PRIu32" (oai_exit %d, rx_num_channels %d)\n", - downlink_frequency[0][0], downlink_frequency[0][0]+uplink_frequency_offset[0][0], + LOG_I( PHY, "[SCHED][UE] Check absolute frequency DL %"PRIu64", UL %"PRIu64" (oai_exit %d, rx_num_channels %d)\n", + UE->frame_parms.dl_CarrierFreq, UE->frame_parms.ul_CarrierFreq, oai_exit, openair0_cfg[0].rx_num_channels); for (i=0; irf_map.card].rx_num_channels; i++) { - openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i]; - openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = - downlink_frequency[CC_id][i]+uplink_frequency_offset[CC_id][i]; + openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = UE->frame_parms.dl_CarrierFreq; + openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = UE->frame_parms.ul_CarrierFreq; openair0_cfg[UE->rf_map.card].autocal[UE->rf_map.chain+i] = 1; - if (uplink_frequency_offset[CC_id][i] != 0) // + if (UE->frame_parms.frame_type == FDD) openair0_cfg[UE->rf_map.card].duplex_mode = duplex_mode_FDD; - else //FDD + else openair0_cfg[UE->rf_map.card].duplex_mode = duplex_mode_TDD; } @@ -248,13 +242,14 @@ static void UE_synch(void *arg) { if (nr_initial_sync( &syncD->proc, UE, UE->mode,2) == 0) { freq_offset = UE->common_vars.freq_offset; // frequency offset computed with pss in initial sync - hw_slot_offset = (UE->rx_offset<<1) / UE->frame_parms.samples_per_slot; - LOG_I(PHY,"Got synch: hw_slot_offset %d, carrier off %d Hz, rxgain %d (DL %u, UL %u), UE_scan_carrier %d\n", + hw_slot_offset = ((UE->rx_offset<<1) / UE->frame_parms.samples_per_subframe * UE->frame_parms.slots_per_subframe) + + round((float)((UE->rx_offset<<1) % UE->frame_parms.samples_per_subframe)/UE->frame_parms.samples_per_slot0); + LOG_I(PHY,"Got synch: hw_slot_offset %d, carrier off %d Hz, rxgain %d (DL %lu, UL %lu), UE_scan_carrier %d\n", hw_slot_offset, freq_offset, UE->rx_total_gain_dB, - downlink_frequency[0][0]+freq_offset, - downlink_frequency[0][0]+uplink_frequency_offset[0][0]+freq_offset, + UE->frame_parms.dl_CarrierFreq+freq_offset, + UE->frame_parms.ul_CarrierFreq+freq_offset, UE->UE_scan_carrier ); // rerun with new cell parameters and frequency-offset @@ -267,8 +262,8 @@ static void UE_synch(void *arg) { openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] -= abs(freq_offset); openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = - openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i]+uplink_frequency_offset[CC_id][i]; - downlink_frequency[CC_id][i] = openair0_cfg[CC_id].rx_freq[i]; + openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i]+(UE->frame_parms.ul_CarrierFreq-UE->frame_parms.dl_CarrierFreq); + UE->frame_parms.dl_CarrierFreq = openair0_cfg[CC_id].rx_freq[i]; } // reconfigure for potentially different bandwidth @@ -300,6 +295,12 @@ static void UE_synch(void *arg) { openair0_cfg[UE->rf_map.card].tx_bw=10.0e6; // openair0_cfg[0].rx_gain[0] -= 0; break; + + case 66: + openair0_cfg[UE->rf_map.card].sample_rate=122.88e6; + openair0_cfg[UE->rf_map.card].rx_bw=100.e6; + openair0_cfg[UE->rf_map.card].tx_bw=100.e6; + break; } if (UE->mode != loop_through_memory) { @@ -327,15 +328,15 @@ static void UE_synch(void *arg) { freq_offset += 100; freq_offset *= -1; - LOG_I(PHY, "[initial_sync] trying carrier off %d Hz, rxgain %d (DL %u, UL %u)\n", + LOG_I(PHY, "[initial_sync] trying carrier off %d Hz, rxgain %d (DL %lu, UL %lu)\n", freq_offset, UE->rx_total_gain_dB, - downlink_frequency[0][0]+freq_offset, - downlink_frequency[0][0]+uplink_frequency_offset[0][0]+freq_offset ); + UE->frame_parms.dl_CarrierFreq+freq_offset, + UE->frame_parms.ul_CarrierFreq+freq_offset ); for (i=0; irf_map.card].rx_num_channels; i++) { - openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i]+freq_offset; - openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i]+uplink_frequency_offset[CC_id][i]+freq_offset; + openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = UE->frame_parms.dl_CarrierFreq+freq_offset; + openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = UE->frame_parms.ul_CarrierFreq+freq_offset; openair0_cfg[UE->rf_map.card].rx_gain[UE->rf_map.chain+i] = UE->rx_total_gain_dB;//-USRP_GAIN_OFFSET; if (UE->UE_scan_carrier==1) @@ -355,45 +356,43 @@ static void UE_synch(void *arg) { } } -void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { - - nr_dcireq_t dcireq; - nr_scheduled_response_t scheduled_response; +void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { uint32_t nb_rb, start_rb; uint8_t nb_symb_sch, start_symbol, mcs, precod_nbr_layers, harq_pid, rvidx; uint16_t n_rnti; - // Process Rx data for one sub-frame - if (slot_select_nr(&UE->frame_parms, proc->frame_tx, proc->nr_tti_tx) & NR_DOWNLINK_SLOT) { - //TODO: all of this has to be moved to the MAC!!! + nr_dcireq_t dcireq; + nr_scheduled_response_t scheduled_response; + + // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI + if (proc->nr_tti_tx == 8 || UE->frame_parms.frame_type == FDD){ + dcireq.module_id = UE->Mod_id; dcireq.gNB_index = 0; dcireq.cc_id = 0; dcireq.frame = proc->frame_rx; dcireq.slot = proc->nr_tti_rx; - nr_ue_dcireq(&dcireq); //to be replaced with function pointer later - scheduled_response.dl_config = &dcireq.dl_config_req; + scheduled_response.dl_config = NULL; scheduled_response.ul_config = &dcireq.ul_config_req; scheduled_response.tx_request = NULL; scheduled_response.module_id = UE->Mod_id; scheduled_response.CC_id = 0; scheduled_response.frame = proc->frame_rx; scheduled_response.slot = proc->nr_tti_rx; - //--------------------------Temporary configuration-----------------------------// n_rnti = 0x1234; nb_rb = 50; start_rb = 0; nb_symb_sch = 12; - start_symbol = 0; + start_symbol = 2; precod_nbr_layers = 1; mcs = 9; harq_pid = 0; rvidx = 0; - //------------------------------------------------------------------------------// + //------------------------------------------------------------------------------// - scheduled_response.ul_config->sfn_slot = NR_UPLINK_SLOT; + scheduled_response.ul_config->slot = 8; scheduled_response.ul_config->number_pdus = 1; scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.rnti = n_rnti; @@ -406,8 +405,53 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.rv = rvidx; scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers; scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid; - nr_ue_scheduled_response(&scheduled_response); + nr_ue_scheduled_response(&scheduled_response); + + if (UE->mode != loop_through_memory) { + uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx]; + phy_procedures_nrUE_TX(UE,proc,0,thread_id); + } + } +} + +void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { + + nr_dcireq_t dcireq; + nr_scheduled_response_t scheduled_response; + uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period; + + //program DCI for slot 1 + //TODO: all of this has to be moved to the MAC!!! + if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || UE->frame_parms.frame_type == FDD){ + dcireq.module_id = UE->Mod_id; + dcireq.gNB_index = 0; + dcireq.cc_id = 0; + dcireq.frame = proc->frame_rx; + dcireq.slot = proc->nr_tti_rx; + nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + + // we should have received a DL DCI here, so configure DL accordingly + scheduled_response.dl_config = &dcireq.dl_config_req; + scheduled_response.ul_config = NULL; + scheduled_response.tx_request = NULL; + scheduled_response.module_id = UE->Mod_id; + scheduled_response.CC_id = 0; + if (!((proc->frame_rx)%(1<<(ssb_period-1)))) { + if(proc->frame_rx > dcireq.dl_config_req.sfn) + UE->frame_gap = proc->frame_rx - dcireq.dl_config_req.sfn; + if(proc->frame_rx < dcireq.dl_config_req.sfn) + UE->frame_gap = dcireq.dl_config_req.sfn - proc->frame_rx; + proc->frame_rx = dcireq.dl_config_req.sfn; + } + scheduled_response.frame = proc->frame_rx; + scheduled_response.slot = proc->nr_tti_rx; + + nr_ue_scheduled_response(&scheduled_response); + } + + // Process Rx data for one sub-frame + if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 ) { #ifdef UE_SLOT_PARALLELISATION phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL ); #else @@ -416,14 +460,15 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { LOG_D(PHY,"phy_procedures_nrUE_RX: slot:%d, time %lu\n", proc->nr_tti_rx, (rdtsc()-a)/3500); //printf(">>> nr_ue_pdcch_procedures ended\n"); #endif - if(IS_SOFTMODEM_NOS1){ //&& proc->nr_tti_rx==1 - //Hardcoded rnti value - protocol_ctxt_t ctxt; - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, UE->Mod_id, ENB_FLAG_NO, - 0x1234, proc->frame_rx, - proc->nr_tti_rx, 0); - pdcp_run(&ctxt); - } + + if(IS_SOFTMODEM_NOS1){ //&& proc->nr_tti_rx==1 + //Hardcoded rnti value + protocol_ctxt_t ctxt; + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, UE->Mod_id, ENB_FLAG_NO, + 0x1234, proc->frame_rx, + proc->nr_tti_rx, 0); + pdcp_run(&ctxt); + } } @@ -458,11 +503,10 @@ typedef struct processingData_s { } processingData_t; void UE_processing(void *arg) { - uint8_t thread_id; processingData_t *rxtxD=(processingData_t *) arg; UE_nr_rxtx_proc_t *proc = &rxtxD->proc; PHY_VARS_NR_UE *UE = rxtxD->UE; - processSlotRX(UE, proc); + uint8_t gNB_id = 0; // params for UL time alignment procedure @@ -472,18 +516,6 @@ void UE_processing(void *arg) { int slot_tx = proc->nr_tti_tx; int frame_tx = proc->frame_tx; - //printf(">>> mac ended\n"); - // Prepare the future Tx data -/* -#ifndef NO_RAT_NR - - if (slot_select_nr(&UE->frame_parms, proc->frame_tx, proc->nr_tti_tx) & NR_UPLINK_SLOT) -#else - if ((subframe_select( &UE->frame_parms, proc->subframe_tx) == SF_UL) || - (UE->frame_parms.frame_type == FDD) ) -#endif -*/ - /* UL time alignment // If the current tx frame and slot match the TA configuration in ul_time_alignment // then timing advance is processed and set to be applied in the next UL transmission */ @@ -500,80 +532,60 @@ void UE_processing(void *arg) { } } - if (proc->nr_tti_tx == NR_UPLINK_SLOT || UE->frame_parms.frame_type == FDD){ + processSlotRX(UE, proc); - thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx]; + processSlotTX(UE, proc); - - if (UE->mode != loop_through_memory) - phy_procedures_nrUE_TX(UE,proc,gNB_id,thread_id); - - } - - //phy_procedures_UE_TX(UE,proc,0,0,UE->mode,no_relay); - -#if 0 - - if ((subframe_select( &UE->frame_parms, proc->subframe_tx) == SF_S) && - (UE->frame_parms.frame_type == TDD)) - if (UE->mode != loop_through_memory) - //phy_procedures_UE_S_TX(UE,0,0,no_relay); - updateTimes(current, &t3, 10000, timing_proc_name); - -#endif } -void readFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { - void *rxp[NB_ANTENNAS_RX]; +void dummyWrite(PHY_VARS_NR_UE *UE,openair0_timestamp timestamp, int writeBlockSize) { void *dummy_tx[UE->frame_parms.nb_antennas_tx]; for (int i=0; iframe_parms.nb_antennas_tx; i++) - dummy_tx[i]=malloc16_clear(UE->frame_parms.samples_per_subframe*4); + dummy_tx[i]=malloc16_clear(writeBlockSize*4); - for(int x=0; x<20; x++) { // two frames for initial sync - for (int i=0; iframe_parms.nb_antennas_rx; i++) - rxp[i] = ((void *)&UE->common_vars.rxdata[i][0]) + 4*x*UE->frame_parms.samples_per_subframe; - - AssertFatal( UE->frame_parms.samples_per_subframe == - UE->rfdevice.trx_read_func(&UE->rfdevice, - timestamp, - rxp, - UE->frame_parms.samples_per_subframe, - UE->frame_parms.nb_antennas_rx), ""); - } + AssertFatal( writeBlockSize == + UE->rfdevice.trx_write_func(&UE->rfdevice, + timestamp, + dummy_tx, + writeBlockSize, + UE->frame_parms.nb_antennas_tx, + 4),""); for (int i=0; iframe_parms.nb_antennas_tx; i++) free(dummy_tx[i]); } -void trashFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { - void *dummy_tx[UE->frame_parms.nb_antennas_tx]; +void readFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp, bool toTrash) { - for (int i=0; iframe_parms.nb_antennas_tx; i++) - dummy_tx[i]=malloc16_clear(UE->frame_parms.samples_per_subframe*4); + void *rxp[NB_ANTENNAS_RX]; - void *dummy_rx[UE->frame_parms.nb_antennas_rx]; + for(int x=0; x<20; x++) { // two frames for initial sync + for (int slot=0; slotframe_parms.slots_per_subframe; slot ++ ) { + for (int i=0; iframe_parms.nb_antennas_rx; i++) { + if (toTrash) + rxp[i]=malloc16(UE->frame_parms.get_samples_per_slot(slot,&UE->frame_parms)*4); + else + rxp[i] = ((void *)&UE->common_vars.rxdata[i][0]) + + 4*((x*UE->frame_parms.samples_per_subframe)+ + UE->frame_parms.get_samples_slot_timestamp(slot,&UE->frame_parms,0)); + } + + AssertFatal( UE->frame_parms.get_samples_per_slot(slot,&UE->frame_parms) == + UE->rfdevice.trx_read_func(&UE->rfdevice, + timestamp, + rxp, + UE->frame_parms.get_samples_per_slot(slot,&UE->frame_parms), + UE->frame_parms.nb_antennas_rx), ""); - for (int i=0; iframe_parms.nb_antennas_rx; i++) - dummy_rx[i]=malloc16(UE->frame_parms.samples_per_subframe*4); - - for (int sf=0; sfrfdevice.trx_read_func(&UE->rfdevice, - timestamp, - dummy_rx, - UE->frame_parms.samples_per_subframe, - UE->frame_parms.nb_antennas_rx); - if (IS_SOFTMODEM_RFSIM ) { - usleep(1000); // slow down, as would do actual rf to let cpu for the synchro thread + if (IS_SOFTMODEM_RFSIM) + dummyWrite(UE,*timestamp, UE->frame_parms.get_samples_per_slot(slot,&UE->frame_parms)); + if (toTrash) + for (int i=0; iframe_parms.nb_antennas_rx; i++) + free(rxp[i]); } } - for (int i=0; iframe_parms.nb_antennas_tx; i++) - free(dummy_tx[i]); - - for (int i=0; iframe_parms.nb_antennas_rx; i++) - free(dummy_rx[i]); } void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { @@ -581,22 +593,21 @@ void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode); void *dummy_tx[UE->frame_parms.nb_antennas_tx]; - for (int i=0; iframe_parms.nb_antennas_tx; i++) - dummy_tx[i]=malloc16_clear(UE->frame_parms.samples_per_subframe*4); - + *timestamp += UE->frame_parms.get_samples_per_slot(1,&UE->frame_parms); for ( int size=UE->rx_offset ; size > 0 ; size -= UE->frame_parms.samples_per_subframe ) { int unitTransfer=size>UE->frame_parms.samples_per_subframe ? UE->frame_parms.samples_per_subframe : size ; + // we write before read becasue gNB waits for UE to write and both executions halt + // this happens here as the read size is samples_per_subframe which is very much larger than samp_per_slot + if (IS_SOFTMODEM_RFSIM) dummyWrite(UE,*timestamp, unitTransfer); AssertFatal(unitTransfer == UE->rfdevice.trx_read_func(&UE->rfdevice, timestamp, (void **)UE->common_vars.rxdata, unitTransfer, UE->frame_parms.nb_antennas_rx),""); + *timestamp += unitTransfer; // this does not affect the read but needed for RFSIM write } - for (int i=0; iframe_parms.nb_antennas_tx; i++) - free(dummy_tx[i]); - } int computeSamplesShift(PHY_VARS_NR_UE *UE) { @@ -622,6 +633,22 @@ int computeSamplesShift(PHY_VARS_NR_UE *UE) { return 0; } +static inline int get_firstSymSamp(uint16_t slot, NR_DL_FRAME_PARMS *fp) { + if (fp->numerology_index == 0) + return fp->nb_prefix_samples0 + fp->ofdm_symbol_size; + int num_samples = (slot%(fp->slots_per_subframe/2)) ? fp->nb_prefix_samples : fp->nb_prefix_samples0; + num_samples += fp->ofdm_symbol_size; + return num_samples; +} + +static inline int get_readBlockSize(uint16_t slot, NR_DL_FRAME_PARMS *fp) { + int rem_samples = fp->get_samples_per_slot(slot, fp) - get_firstSymSamp(slot, fp); + int next_slot_first_symbol = 0; + if (slot < (fp->slots_per_frame-1)) + next_slot_first_symbol = get_firstSymSamp(slot+1, fp); + return rem_samples + next_slot_first_symbol; +} + void *UE_thread(void *arg) { //this thread should be over the processing thread to keep in real time PHY_VARS_NR_UE *UE = (PHY_VARS_NR_UE *) arg; @@ -629,7 +656,6 @@ void *UE_thread(void *arg) { openair0_timestamp timestamp; void *rxp[NB_ANTENNAS_RX], *txp[NB_ANTENNAS_TX]; int start_rx_stream = 0; - const uint16_t table_sf_slot[20] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9}; AssertFatal(0== openair0_device_load(&(UE->rfdevice), &openair0_cfg[0]), ""); UE->rfdevice.host_type = RAU_HOST; AssertFatal(UE->rfdevice.trx_start_func(&UE->rfdevice) == 0, "Could not start the device\n"); @@ -639,13 +665,14 @@ void *UE_thread(void *arg) { int thread_idx=0; notifiedFIFO_t freeBlocks; initNotifiedFIFO_nothreadSafe(&freeBlocks); + NR_UE_MAC_INST_t *mac = get_mac_inst(0); for (int i=0; iframe_parms.slots_per_subframe; + const int nb_slot_frame = UE->frame_parms.slots_per_frame; int absolute_slot=0, decoded_frame_rx=INT_MAX, trashed_frames=0; while (!oai_exit) { @@ -656,11 +683,11 @@ void *UE_thread(void *arg) { syncRunning=false; syncData_t *tmp=(syncData_t *)NotifiedFifoData(res); // shift the frame index with all the frames we trashed meanwhile we perform the synch search - decoded_frame_rx=(tmp->proc.decoded_frame_rx+trashed_frames) % MAX_FRAME_NUMBER; + decoded_frame_rx=(tmp->proc.decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER; delNotifiedFIFO_elt(res); } else { - trashFrame(UE, ×tamp); - trashed_frames++; + readFrame(UE, ×tamp, true); + trashed_frames+=2; continue; } } @@ -668,7 +695,7 @@ void *UE_thread(void *arg) { AssertFatal( !syncRunning, "At this point synchronization can't be running\n"); if (!UE->is_synchronized) { - readFrame(UE, ×tamp); + readFrame(UE, ×tamp, false); notifiedFIFO_elt_t *Msg=newNotifiedFIFO_elt(sizeof(syncData_t),0,&nf,UE_synch); syncData_t *syncMsg=(syncData_t *)NotifiedFifoData(Msg); syncMsg->UE=UE; @@ -695,7 +722,7 @@ void *UE_thread(void *arg) { // and we shifted above to the first slot of next frame decoded_frame_rx++; // we do ++ first in the regular processing, so it will be begin of frame; - absolute_slot=decoded_frame_rx*nb_slot_frame + nb_slot_frame -1; + absolute_slot=decoded_frame_rx*nb_slot_frame -1; continue; } @@ -715,11 +742,11 @@ void *UE_thread(void *arg) { curMsg->UE->current_thread_id[slot_nr] = thread_idx; curMsg->proc.CC_id = 0; curMsg->proc.nr_tti_rx= slot_nr; - curMsg->proc.subframe_rx=table_sf_slot[slot_nr]; + curMsg->proc.subframe_rx=slot_nr/(nb_slot_frame/10); curMsg->proc.nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame; curMsg->proc.subframe_tx=curMsg->proc.nr_tti_rx; - curMsg->proc.frame_rx = ( absolute_slot/nb_slot_frame ) % MAX_FRAME_NUMBER; - curMsg->proc.frame_tx = ( (absolute_slot + DURATION_RX_TO_TX) /nb_slot_frame ) % MAX_FRAME_NUMBER; + curMsg->proc.frame_rx = ((absolute_slot/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER; + curMsg->proc.frame_tx = (((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER; curMsg->proc.decoded_frame_rx=-1; //LOG_I(PHY,"Process slot %d thread Idx %d total gain %d\n", slot_nr, thread_idx, UE->rx_total_gain_dB); @@ -732,26 +759,25 @@ void *UE_thread(void *arg) { }*/ #endif + int firstSymSamp = get_firstSymSamp(slot_nr, &UE->frame_parms); for (int i=0; iframe_parms.nb_antennas_rx; i++) - rxp[i] = (void *)&UE->common_vars.rxdata[i][UE->frame_parms.ofdm_symbol_size+ - UE->frame_parms.nb_prefix_samples0+ - slot_nr*UE->frame_parms.samples_per_slot]; + rxp[i] = (void *)&UE->common_vars.rxdata[i][firstSymSamp+ + UE->frame_parms.get_samples_slot_timestamp(slot_nr,&UE->frame_parms,0)]; for (int i=0; iframe_parms.nb_antennas_tx; i++) - txp[i] = (void *)&UE->common_vars.txdata[i][((curMsg->proc.nr_tti_rx + DURATION_RX_TO_TX)%nb_slot_frame)*UE->frame_parms.samples_per_slot]; + txp[i] = (void *)&UE->common_vars.txdata[i][UE->frame_parms.get_samples_slot_timestamp( + ((curMsg->proc.nr_tti_rx + DURATION_RX_TO_TX)%nb_slot_frame),&UE->frame_parms,0)]; int readBlockSize, writeBlockSize; if (slot_nr<(nb_slot_frame - 1)) { - readBlockSize=UE->frame_parms.samples_per_slot; - writeBlockSize=UE->frame_parms.samples_per_slot; + readBlockSize=get_readBlockSize(slot_nr, &UE->frame_parms); + writeBlockSize=UE->frame_parms.get_samples_per_slot(curMsg->proc.nr_tti_tx,&UE->frame_parms); } else { UE->rx_offset_diff = computeSamplesShift(UE); - readBlockSize=UE->frame_parms.samples_per_slot - - UE->frame_parms.ofdm_symbol_size - - UE->frame_parms.nb_prefix_samples0 - + readBlockSize=get_readBlockSize(slot_nr, &UE->frame_parms) - UE->rx_offset_diff; - writeBlockSize=UE->frame_parms.samples_per_slot - + writeBlockSize=UE->frame_parms.get_samples_per_slot(curMsg->proc.nr_tti_tx,&UE->frame_parms) - UE->rx_offset_diff; } @@ -762,33 +788,20 @@ void *UE_thread(void *arg) { readBlockSize, UE->frame_parms.nb_antennas_rx),""); -if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX - 1)%20) AssertFatal( writeBlockSize == UE->rfdevice.trx_write_func(&UE->rfdevice, timestamp+ - (DURATION_RX_TO_TX*UE->frame_parms.samples_per_slot) - - UE->frame_parms.ofdm_symbol_size-UE->frame_parms.nb_prefix_samples0 - + UE->frame_parms.get_samples_slot_timestamp(slot_nr, + &UE->frame_parms,DURATION_RX_TO_TX) - firstSymSamp - openair0_cfg[0].tx_sample_advance, txp, writeBlockSize, UE->frame_parms.nb_antennas_tx, - 2),""); - -if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20) - AssertFatal( writeBlockSize == - UE->rfdevice.trx_write_func(&UE->rfdevice, - timestamp+ - (DURATION_RX_TO_TX*UE->frame_parms.samples_per_slot) - - UE->frame_parms.ofdm_symbol_size-UE->frame_parms.nb_prefix_samples0 - - openair0_cfg[0].tx_sample_advance, - txp, - writeBlockSize, - UE->frame_parms.nb_antennas_tx, - 3),""); + 1),""); if( slot_nr==(nb_slot_frame-1)) { // read in first symbol of next frame and adjust for timing drift - int first_symbols=writeBlockSize-readBlockSize; + int first_symbols=UE->frame_parms.ofdm_symbol_size+UE->frame_parms.nb_prefix_samples0; // first symbol of every frames if ( first_symbols > 0 ) AssertFatal(first_symbols == @@ -802,8 +815,9 @@ if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20) } curMsg->proc.timestamp_tx = timestamp+ - (DURATION_RX_TO_TX*UE->frame_parms.samples_per_slot)- - UE->frame_parms.ofdm_symbol_size-UE->frame_parms.nb_prefix_samples0; + UE->frame_parms.get_samples_slot_timestamp(slot_nr, + &UE->frame_parms,DURATION_RX_TO_TX) - firstSymSamp; + notifiedFIFO_elt_t *res; while (nbSlotProcessing >= RX_NB_TH) { @@ -812,7 +826,8 @@ if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20) processingData_t *tmp=(processingData_t *)res->msgData; if (tmp->proc.decoded_frame_rx != -1) - decoded_frame_rx=tmp->proc.decoded_frame_rx; + decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx); + //decoded_frame_rx=tmp->proc.decoded_frame_rx; pushNotifiedFIFO_nothreadSafe(&freeBlocks,res); } @@ -838,7 +853,8 @@ if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20) processingData_t *tmp=(processingData_t *)res->msgData; if (tmp->proc.decoded_frame_rx != -1) - decoded_frame_rx=tmp->proc.decoded_frame_rx; + decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx); + //decoded_frame_rx=tmp->proc.decoded_frame_rx; pushNotifiedFIFO_nothreadSafe(&freeBlocks,res); } @@ -847,30 +863,27 @@ if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20) return NULL; } -void init_NR_UE(int nb_inst) { +void init_NR_UE(int nb_inst, char* rrc_config_path) { int inst; NR_UE_MAC_INST_t *mac_inst; + NR_UE_RRC_INST_t* rrc_inst; + + for (inst=0; inst < nb_inst; inst++) { + AssertFatal((rrc_inst = nr_l3_init_ue(rrc_config_path)) != NULL, "can not initialize RRC module\n"); + AssertFatal((mac_inst = nr_l2_init_ue(rrc_inst)) != NULL, "can not initialize L2 module\n"); + AssertFatal((mac_inst->if_module = nr_ue_if_module_init(inst)) != NULL, "can not initialize IF module\n"); + } +} + +void init_NR_UE_threads(int nb_inst) { + int inst; + pthread_t threads[nb_inst]; for (inst=0; inst < nb_inst; inst++) { PHY_VARS_NR_UE *UE = PHY_vars_UE_g[inst][0]; - AssertFatal((UE->if_inst = nr_ue_if_module_init(inst)) != NULL, "can not initial IF module\n"); - nr_l3_init_ue(); - nr_l2_init_ue(); - mac_inst = get_mac_inst(inst); - mac_inst->if_module = UE->if_inst; - // Initial bandwidth part configuration -- full carrier bandwidth - mac_inst->initial_bwp_dl.bwp_id = 0; - mac_inst->initial_bwp_dl.location = 0; - mac_inst->initial_bwp_dl.scs = UE->frame_parms.subcarrier_spacing; - mac_inst->initial_bwp_dl.N_RB = UE->frame_parms.N_RB_DL; - mac_inst->initial_bwp_dl.cyclic_prefix = UE->frame_parms.Ncp; - mac_inst->initial_bwp_ul.bwp_id = 0; - mac_inst->initial_bwp_ul.location = 0; - mac_inst->initial_bwp_ul.scs = UE->frame_parms.subcarrier_spacing; - mac_inst->initial_bwp_ul.N_RB = UE->frame_parms.N_RB_UL; - mac_inst->initial_bwp_ul.cyclic_prefix = UE->frame_parms.Ncp; - LOG_I(PHY,"Initializing UE Threads for instance %d (%p,%p)...\n",inst,PHY_vars_UE_g[inst],PHY_vars_UE_g[inst][0]); + + LOG_I(PHY,"Intializing UE Threads for instance %d (%p,%p)...\n",inst,PHY_vars_UE_g[inst],PHY_vars_UE_g[inst][0]); threadCreate(&threads[inst], UE_thread, (void *)UE, "UEthread", -1, OAI_PRIORITY_RT_MAX); #ifdef UE_DLSCH_PARALLELISATION @@ -879,8 +892,6 @@ void init_NR_UE(int nb_inst) { #endif } - - printf("UE threads created by %ld\n", gettid()); } /* HACK: this function is needed to compile the UE @@ -895,4 +906,3 @@ int8_t find_dlsch(uint16_t rnti, } void multicast_link_write_sock(int groupP, char *dataP, uint32_t sizeP) {} - diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index e0cb380365..53e407923f 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -133,7 +133,7 @@ static double snr_dB=20; int threequarter_fs=0; -uint32_t downlink_frequency[MAX_NUM_CCs][4]; +uint64_t downlink_frequency[MAX_NUM_CCs][4]; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; //int32_t uplink_counter = 0; @@ -221,6 +221,8 @@ tpool_t *Tpool_dl; char *usrp_args=NULL; +char *rrc_config_path=NULL; + /* forward declarations */ void set_default_frame_parms(NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]); @@ -472,7 +474,7 @@ void set_default_frame_parms(NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]) { for (CC_id=0; CC_ideutra_band = 78; + frame_parms[CC_id]->nr_band = 78; frame_parms[CC_id]->frame_type = FDD; frame_parms[CC_id]->tdd_config = 3; //frame_parms[CC_id]->tdd_config_S = 0; @@ -482,7 +484,7 @@ void set_default_frame_parms(NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]) { //frame_parms[CC_id]->Ncp_UL = NORMAL; frame_parms[CC_id]->Nid_cell = 0; //frame_parms[CC_id]->num_MBSFN_config = 0; - frame_parms[CC_id]->nb_antenna_ports_eNB = 1; + frame_parms[CC_id]->nb_antenna_ports_gNB = 1; frame_parms[CC_id]->nb_antennas_tx = 1; frame_parms[CC_id]->nb_antennas_rx = 1; //frame_parms[CC_id]->nushift = 0; @@ -500,8 +502,25 @@ void init_openair0(void) { for (card=0; cardthreequarter_fs; + numerology = frame_parms[0]->numerology_index; - if(frame_parms[0]->N_RB_DL == 217) { + if(frame_parms[0]->N_RB_DL == 66) { + if (numerology==3) { + openair0_cfg[card].sample_rate=122.88e6; + openair0_cfg[card].samples_per_frame = 1228800; + } else { + LOG_E(PHY,"Unsupported numerology! FR2 supports only 120KHz SCS for now.\n"); + exit(-1); + } + }else if(frame_parms[0]->N_RB_DL == 32) { + if (numerology==3) { + openair0_cfg[card].sample_rate=61.44e6; + openair0_cfg[card].samples_per_frame = 614400; + } else { + LOG_E(PHY,"Unsupported numerology! FR2 supports only 120KHz SCS for now.\n"); + exit(-1); + } + }else if(frame_parms[0]->N_RB_DL == 217) { if (numerology==1) { if (frame_parms[0]->threequarter_fs) { openair0_cfg[card].sample_rate=92.16e6; @@ -584,12 +603,12 @@ void init_openair0(void) { for (i=0; i<4; i++) { if (iul_CarrierFreq; else openair0_cfg[card].tx_freq[i]=0.0; if (idl_CarrierFreq; else openair0_cfg[card].rx_freq[i]=0.0; @@ -669,13 +688,20 @@ int main( int argc, char **argv ) { itti_init(TASK_MAX, THREAD_MAX, MESSAGES_ID_MAX, tasks_info, messages_info); init_opt() ; - if(IS_SOFTMODEM_NOS1) - init_pdcp(); + load_nrLDPClib(); if (ouput_vcd) { vcd_signal_dumper_init("/tmp/openair_dump_nrUE.vcd"); } + #ifndef PACKAGE_VERSION +# define PACKAGE_VERSION "UNKNOWN-EXPERIMENTAL" +#endif + LOG_I(HW, "Version: %s\n", PACKAGE_VERSION); + + init_NR_UE(1,rrc_config_path); + if(IS_SOFTMODEM_NOS1) + init_pdcp(); /* #ifdef PDCP_USE_NETLINK netlink_init(); @@ -684,20 +710,6 @@ int main( int argc, char **argv ) { #endif #endif */ - #ifndef PACKAGE_VERSION -# define PACKAGE_VERSION "UNKNOWN-EXPERIMENTAL" -#endif - LOG_I(HW, "Version: %s\n", PACKAGE_VERSION); - - // init the parameters - for (int CC_id=0; CC_idnb_antennas_tx = nb_antenna_tx; - frame_parms[CC_id]->nb_antennas_rx = nb_antenna_rx; - frame_parms[CC_id]->nb_antenna_ports_eNB = 1; //initial value overwritten by initial sync later - frame_parms[CC_id]->threequarter_fs = threequarter_fs; - LOG_I(PHY,"Set nb_rx_antenna %d , nb_tx_antenna %d \n",frame_parms[CC_id]->nb_antennas_rx, frame_parms[CC_id]->nb_antennas_tx); - get_band(downlink_frequency[CC_id][0], &frame_parms[CC_id]->eutra_band, &uplink_frequency_offset[CC_id][0], &frame_parms[CC_id]->frame_type); - } NB_UE_INST=1; NB_INST=1; @@ -705,17 +717,38 @@ int main( int argc, char **argv ) { PHY_vars_UE_g[0] = malloc(sizeof(PHY_VARS_NR_UE *)*MAX_NUM_CCs); for (int CC_id=0; CC_idofdm_symbol_size); - nr_init_frame_parms_ue(frame_parms[CC_id],numerology,NORMAL,frame_parms[CC_id]->N_RB_DL,(frame_parms[CC_id]->N_RB_DL-20)>>1,0); - PHY_vars_UE_g[0][CC_id] = init_nr_ue_vars(frame_parms[CC_id], 0,abstraction_flag); - UE[CC_id] = PHY_vars_UE_g[0][CC_id]; + printf("frame_parms %d\n",frame_parms[CC_id]->ofdm_symbol_size); + frame_parms[CC_id]->nb_antennas_tx = nb_antenna_tx; + frame_parms[CC_id]->nb_antennas_rx = nb_antenna_rx; + frame_parms[CC_id]->nb_antenna_ports_gNB = 1; //initial value overwritten by initial sync later + frame_parms[CC_id]->threequarter_fs = threequarter_fs; + LOG_I(PHY,"Set nb_rx_antenna %d , nb_tx_antenna %d \n",frame_parms[CC_id]->nb_antennas_rx, frame_parms[CC_id]->nb_antennas_tx); + PHY_vars_UE_g[0][CC_id] = (PHY_VARS_NR_UE *)malloc(sizeof(PHY_VARS_NR_UE)); + + UE[CC_id] = PHY_vars_UE_g[0][CC_id]; + memset(UE[CC_id],0,sizeof(PHY_VARS_NR_UE)); + + NR_UE_MAC_INST_t *mac = get_mac_inst(0); + if(mac->if_module != NULL && mac->if_module->phy_config_request != NULL) + mac->if_module->phy_config_request(&mac->phy_config); + + fapi_nr_config_request_t *nrUE_config = &UE[CC_id]->nrUE_config; + nr_init_frame_parms_ue(frame_parms[CC_id],nrUE_config,NORMAL); + + // Overwrite DL frequency (for FR2 testing) + if (downlink_frequency[0][0]!=0) + frame_parms[CC_id]->dl_CarrierFreq = downlink_frequency[0][0]; + + init_nr_ue_vars(UE[CC_id],frame_parms[CC_id],0,abstraction_flag); if (get_softmodem_params()->phy_test==1) UE[CC_id]->mac_enabled = 0; else UE[CC_id]->mac_enabled = 1; + UE[CC_id]->mac_enabled = 1; + UE[CC_id]->if_inst = nr_ue_if_module_init(0); UE[CC_id]->UE_scan = UE_scan; UE[CC_id]->UE_scan_carrier = UE_scan_carrier; UE[CC_id]->UE_fo_compensation = UE_fo_compensation; @@ -723,13 +756,6 @@ int main( int argc, char **argv ) { UE[CC_id]->no_timing_correction = UE_no_timing_correction; printf("UE[%d]->mode = %d\n",CC_id,mode); - for (uint8_t i=0; imac_enabled == 1) - UE[CC_id]->pdcch_vars[i][0]->crnti = 0x1234; - else - UE[CC_id]->pdcch_vars[i][0]->crnti = 0x1235; - } - UE[CC_id]->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off; UE[CC_id]->tx_power_max_dBm = tx_max_power[CC_id]; @@ -764,11 +790,14 @@ int main( int argc, char **argv ) { #else PHY_vars_UE_g[0][CC_id]->hw_timing_advance = 160; #endif + } + init_NR_UE_threads(1); + printf("UE threads created by %ld\n", gettid()); + // wait for end of program printf("TYPE TO TERMINATE\n"); - init_NR_UE(1); while(true) sleep(3600); diff --git a/executables/nr-uesoftmodem.h b/executables/nr-uesoftmodem.h index 38c4c1b607..7fad43e897 100644 --- a/executables/nr-uesoftmodem.h +++ b/executables/nr-uesoftmodem.h @@ -54,8 +54,6 @@ {"usrp-args", CONFIG_HLP_USRP_ARGS, 0, strptr:(char **)&usrp_args, defstrval:"type=b200", TYPE_STRING, 0} \ } -#define DEFAULT_DLF 2680000000 - /*----------------------------------------------------------------------------------------------------------------------------------------------------*/ /* command line parameters common to eNodeB and UE */ /* optname helpstr paramflags XXXptr defXXXval type numelt */ @@ -65,7 +63,7 @@ {"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \ {"nr-dlsch-demod-shift", CONFIG_HLP_DLSHIFT, 0, iptr:(int32_t *)&nr_dlsch_demod_shift, defintval:0, TYPE_INT, 0}, \ {"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \ - {"C" , CONFIG_HLP_DLF, 0, uptr:&(downlink_frequency[0][0]), defuintval:2680000000, TYPE_UINT, 0}, \ + {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:0,TYPE_UINT64, 0}, \ {"a" , CONFIG_HLP_CHOFF, 0, iptr:&chain_offset, defintval:0, TYPE_INT, 0}, \ {"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:&do_forms, defintval:0, TYPE_INT, 0}, \ {"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, iptr:&threequarter_fs, defintval:0, TYPE_INT, 0}, \ @@ -74,13 +72,14 @@ {"q" , CONFIG_HLP_STMON, PARAMFLAG_BOOL, iptr:&opp_enabled, defintval:0, TYPE_INT, 0}, \ {"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, iptr:&tddflag, defintval:0, TYPE_INT, 0}, \ {"V" , CONFIG_HLP_VCD, PARAMFLAG_BOOL, iptr:&vcdflag, defintval:0, TYPE_INT, 0}, \ - {"numerology" , CONFIG_HLP_NUMEROLOGY, PARAMFLAG_BOOL, iptr:&numerology, defintval:0, TYPE_INT, 0}, \ + {"numerology" , CONFIG_HLP_NUMEROLOGY, 0, iptr:&numerology, defintval:0, TYPE_INT, 0}, \ {"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \ {"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)¶llel_config, defstrval:NULL, TYPE_STRING, 0}, \ {"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \ {"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \ {"nbiot-disable", CONFIG_HLP_DISABLNBIOT, PARAMFLAG_BOOL, iptr:&nonbiotflag, defintval:0, TYPE_INT, 0}, \ - {"ue-timing-correction-disable", CONFIG_HLP_DISABLETIMECORR, PARAMFLAG_BOOL, iptr:&UE_no_timing_correction, defintval:0, TYPE_INT, 0} \ + {"ue-timing-correction-disable", CONFIG_HLP_DISABLETIMECORR, PARAMFLAG_BOOL, iptr:&UE_no_timing_correction, defintval:0, TYPE_INT, 0}, \ + {"rrc_config_path", CONFIG_HLP_RRC_CFG_PATH,0, strptr:(char **)&rrc_config_path, defstrval:"./", TYPE_STRING, 0} \ } @@ -92,11 +91,12 @@ extern int T_dont_fork; // In nr-ue.c extern int setup_nr_ue_buffers(PHY_VARS_NR_UE **phy_vars_ue, openair0_config_t *openair0_cfg); extern void fill_ue_band_info(void); -extern void init_NR_UE(int); +extern void init_NR_UE(int, char*); +extern void init_NR_UE_threads(int); extern void reset_opp_meas(void); extern void print_opp_meas(void); void *UE_thread(void *arg); -PHY_VARS_NR_UE *init_nr_ue_vars(NR_DL_FRAME_PARMS *frame_parms, uint8_t UE_id, uint8_t abstraction_flag); +void init_nr_ue_vars(PHY_VARS_NR_UE *ue, NR_DL_FRAME_PARMS *frame_parms, uint8_t UE_id, uint8_t abstraction_flag); extern tpool_t *Tpool; extern tpool_t *Tpool_dl; #endif diff --git a/executables/softmodem-common.c b/executables/softmodem-common.c index 0c4032c41b..f714fa2bd4 100644 --- a/executables/softmodem-common.c +++ b/executables/softmodem-common.c @@ -144,7 +144,6 @@ void get_common_options(uint32_t execmask) { if(worker_config != NULL) set_worker_conf(worker_config); } - void softmodem_printresources(int sig, telnet_printfunc_t pf) { struct rusage usage; struct timespec stop; @@ -204,3 +203,4 @@ void set_softmodem_sighandler(void) { signal(SIGTERM, signal_handler); signal(SIGABRT, signal_handler); } + diff --git a/executables/softmodem-common.h b/executables/softmodem-common.h index c9a24577dc..cfed951469 100644 --- a/executables/softmodem-common.h +++ b/executables/softmodem-common.h @@ -108,7 +108,7 @@ extern "C" {"clock", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \ {"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&WAIT_FOR_SYNC, defintval:0, TYPE_INT, 0}, \ {"single-thread-enable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&SINGLE_THREAD_FLAG, defintval:0, TYPE_INT, 0}, \ - {"C" , CONFIG_HLP_DLF, 0, uptr:&(downlink_frequency[0][0]), defuintval:2680000000, TYPE_UINT, 0}, \ + {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:0, TYPE_UINT64, 0}, \ {"a" , CONFIG_HLP_CHOFF, 0, iptr:&CHAIN_OFFSET, defintval:0, TYPE_INT, 0}, \ {"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:(uint32_t *)&do_forms, defintval:0, TYPE_INT8, 0}, \ {"q" , CONFIG_HLP_STMON, PARAMFLAG_BOOL, iptr:&opp_enabled, defintval:0, TYPE_INT, 0}, \ @@ -189,7 +189,7 @@ extern "C" typedef struct { uint64_t optmask; - THREAD_STRUCT thread_struct; + //THREAD_STRUCT thread_struct; char rf_config_file[1024]; int phy_test; uint8_t usim_test; @@ -212,7 +212,7 @@ extern void get_common_options(uint32_t execmask); extern char *get_softmodem_function(uint64_t *sofmodemfunc_mask_ptr); #define SOFTMODEM_RTSIGNAL (SIGRTMIN+1) extern void set_softmodem_sighandler(void); -extern uint32_t downlink_frequency[MAX_NUM_CCs][4]; +extern uint64_t downlink_frequency[MAX_NUM_CCs][4]; #ifdef __cplusplus } #endif diff --git a/nfapi/oai_integration/nfapi_vnf.c b/nfapi/oai_integration/nfapi_vnf.c index a0574221f5..7ab8be5746 100644 --- a/nfapi/oai_integration/nfapi_vnf.c +++ b/nfapi/oai_integration/nfapi_vnf.c @@ -31,7 +31,7 @@ #include #include -#include "nfapi_nr_interface.h" +#include "nfapi_nr_interface_scf.h" #include "nfapi_vnf_interface.h" #include "nfapi.h" #include "vendor_ext.h" @@ -1169,7 +1169,7 @@ int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return retval; } -int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) +int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_tti_request_t *dl_config_req) { nfapi_vnf_p7_config_t *p7_config = vnf.p7_vnfs[0].config; @@ -1177,9 +1177,9 @@ int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) int retval = nfapi_vnf_p7_nr_dl_config_req(p7_config, dl_config_req); - dl_config_req->dl_config_request_body.number_dci = 0; - dl_config_req->dl_config_request_body.number_pdu = 0; - dl_config_req->dl_config_request_body.number_pdsch_rnti = 0; + dl_config_req->dl_tti_request_body.nPDUs = 0; + dl_config_req->dl_tti_request_body.nGroup = 0; + if (retval!=0) { LOG_E(PHY, "%s() Problem sending retval:%d\n", __FUNCTION__, retval); diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h index babcc6404f..cbcd26c3e3 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h @@ -8,6 +8,9 @@ #define FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET 16 #define FAPI_NR_MAX_NUM_CANDIDATE_BEAMS 16 #define FAPI_NR_MAX_RA_OCCASION_PER_CSIRS 64 +// Constants Defined in 38.213 +#define FAPI_NR_MAX_CORESET_PER_BWP 3 +#define FAPI_NR_MAX_SS_PER_CORESET 10 /// RX_IND @@ -41,8 +44,8 @@ #define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02 -#define CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01 -#define CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02 +#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01 +#define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02 #define PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE 0x01 #define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02 diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 838e52dada..576144e1df 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -1,5 +1,4 @@ -/* - * Copyright 2017 Cisco Systems, Inc. +/*Copyright 2017 Cisco Systems, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -32,77 +31,7 @@ typedef signed char int8_t; */ -typedef struct { - uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS: - uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213] - uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1: - uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213] - uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits - uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3 - uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND: - uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND: - uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND: - uint8_t short_messages ; // 9 SHORT_MESSAGES: - uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered - // (NOTE 1) If DCI format 0_0 is monitored in common search space - // and if the number of information bits in the DCI format 0_0 prior to padding - // is larger than the payload size of the DCI format 1_0 monitored in common search space - // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 - // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0 - uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - // where I the number of entries in the higher layer parameter pusch-AllocationList - uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] - uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set - uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER: - uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 - uint8_t tb1_mcs ; // 18 TB1_MCS: - uint8_t tb1_ndi ; // 19 TB1_NDI: - uint8_t tb1_rv ; // 20 TB1_RV: - uint8_t tb2_mcs ; // 21 TB2_MCS: - uint8_t tb2_ndi ; // 22 TB2_NDI: - uint8_t tb2_rv ; // 23 TB2_RV: - uint8_t mcs ; // 24 MCS: - uint8_t ndi ; // 25 NDI: - uint8_t rv ; // 26 RV: - uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER: - uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI - // 0 otherwise - uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK - uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks - uint8_t tb_scaling ; // 31 TB_SCALING: - uint8_t tpc_pusch ; // 32 TPC_PUSCH: - uint8_t tpc_pucch ; // 33 TPC_PUCCH: - uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND: - uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: - uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND: - uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS: - uint8_t antenna_ports ; // 38 ANTENNA_PORTS: - uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits - uint8_t srs_request ; // 40 SRS_REQUEST: - uint8_t tpc_cmd ; // 41 TPC_CMD: - uint8_t csi_request ; // 42 CSI_REQUEST: - uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH - uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator - uint8_t ptrs_dmrs ; // 45 PTRS_DMRS: - uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND: - uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding - // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise - uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH - uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space - // and if the number of information bits in the DCI format 0_0 prior to padding - // is less than the payload size of the DCI format 1_0 monitored in common search space - // zeros shall be appended to the DCI format 0_0 - // until the payload size equals that of the DCI format 1_0 - uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0: - uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX: - uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0: - uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX - uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX - uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI -} fapi_nr_dci_pdu_rel15_t; + @@ -121,16 +50,14 @@ typedef struct { typedef struct { /// frequency_domain_resource; - //uint32_t rb_start; - //uint32_t rb_end; - uint64_t frequency_domain_resource; - uint16_t rb_offset; - + uint8_t frequency_domain_resource[6]; + uint8_t StartSymbolIndex; uint8_t duration; - uint8_t cce_reg_mapping_type; // interleaved or noninterleaved - uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type - uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type - uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type + uint8_t CceRegMappingType; // interleaved or noninterleaved + uint8_t RegBundleSize; // valid if CCE to REG mapping type is interleaved type + uint8_t InterleaverSize; // valid if CCE to REG mapping type is interleaved type + uint8_t ShiftIndex; // valid if CCE to REG mapping type is interleaved type + uint8_t CoreSetType; uint8_t precoder_granularity; uint16_t pdcch_dmrs_scrambling_id; @@ -155,13 +82,16 @@ typedef struct { int n_CCE; // N_CCE is L, or number of CCEs for DCI int N_CCE; - fapi_nr_dci_pdu_rel15_t dci; + uint8_t payloadSize; + uint8_t payloadBits[16]; + //fapi_nr_dci_pdu_rel15_t dci; } fapi_nr_dci_indication_pdu_t; /// typedef struct { - uint32_t sfn_slot; + uint16_t SFN; + uint8_t slot; uint16_t number_of_dcis; fapi_nr_dci_indication_pdu_t dci_list[10]; } fapi_nr_dci_indication_t; @@ -199,7 +129,8 @@ typedef struct { /// #define NFAPI_RX_IND_MAX_PDU 100 typedef struct { - uint32_t sfn_slot; + uint16_t sfn; + uint16_t slot; uint16_t number_pdus; fapi_nr_rx_indication_body_t rx_indication_body[NFAPI_RX_IND_MAX_PDU]; } fapi_nr_rx_indication_t; @@ -218,7 +149,8 @@ typedef struct { /// typedef struct { - uint32_t sfn_slot; + uint16_t sfn; + uint16_t slot; fapi_nr_tx_config_t tx_config; uint16_t number_of_pdus; fapi_nr_tx_request_body_t *tx_request_body; @@ -374,7 +306,8 @@ typedef struct { } fapi_nr_ul_config_request_pdu_t; typedef struct { - uint32_t sfn_slot; + uint16_t sfn; + uint16_t slot; uint8_t number_pdus; fapi_nr_ul_config_request_pdu_t ul_config_list[FAPI_NR_UL_CONFIG_LIST_NUM]; } fapi_nr_ul_config_request_t; @@ -382,16 +315,15 @@ typedef struct { typedef struct { uint16_t rnti; - + uint16_t BWPSize; + uint16_t BWPStart; + uint8_t SubcarrierSpacing; fapi_nr_coreset_t coreset; - uint16_t N_RB_BWP; - uint32_t duration; - uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16 - uint16_t monitoring_symbols_within_slot; - // DCI foramt-specific - uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16 - uint8_t format_2_3_monitorying_periodicity; - uint8_t format_2_3_number_of_candidates; + uint8_t number_of_candidates; + uint16_t CCE[64]; + uint8_t L[64]; + uint8_t dci_length; + uint8_t dci_format; } fapi_nr_dl_config_dci_dl_pdu_rel15_t; typedef struct { @@ -404,12 +336,16 @@ typedef struct{ typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t; //typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t; typedef struct { - uint8_t bandwidth_part_ind; + uint16_t BWPSize; + uint16_t BWPStart; + uint8_t SubcarrierSpacing; uint16_t number_rbs; uint16_t start_rb; uint8_t frame_offset; uint16_t number_symbols; uint16_t start_symbol; + uint16_t dlDmrsSymbPos; + uint8_t dmrsConfigType; uint8_t prb_bundling_size_ind; uint8_t rate_matching_ind; uint8_t zp_csi_rs_trigger; @@ -450,7 +386,8 @@ typedef struct { } fapi_nr_dl_config_request_pdu_t; typedef struct { - uint32_t sfn_slot; + uint16_t sfn; + uint16_t slot; uint8_t number_pdus; fapi_nr_dl_config_request_pdu_t dl_config_list[FAPI_NR_DL_CONFIG_LIST_NUM]; } fapi_nr_dl_config_request_t; @@ -544,20 +481,6 @@ typedef struct { uint8_t p0_nominal; } fapi_nr_pucch_config_common_t; -typedef struct { - - uint8_t subcarrier_spacing_common; - uint8_t ssb_subcarrier_offset; - uint8_t dmrs_type_a_position; - uint8_t pdcch_config_sib1; - uint8_t cell_barred; - uint8_t intra_frequency_reselection; - - uint16_t system_frame_number; - uint8_t ssb_index; - uint8_t half_frame_bit; -} fapi_nr_pbch_config_t; - typedef struct { fapi_nr_pdcch_config_common_t pdcch_config_common; @@ -907,10 +830,115 @@ typedef struct { #define FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED 0x08 #define FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED 0x10 +typedef struct +{ + uint16_t dl_bandwidth;//Carrier bandwidth for DL in MHz [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400 + uint32_t dl_frequency; //Absolute frequency of DL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000 + uint16_t dl_k0[5];//𝑘_{0}^{𝜇} for each of the numerologies [38.211, sec 5.3.1] Value: 0 ->23699 + uint16_t dl_grid_size[5];//Grid size 𝑁_{𝑔𝑟𝑖𝑑}^{𝑠𝑖𝑧𝑒,𝜇} for each of the numerologies [38.211, sec 4.4.2] Value: 0->275 0 = this numerology not used + uint16_t num_tx_ant;//Number of Tx antennas + uint16_t uplink_bandwidth;//Carrier bandwidth for UL in MHz. [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400 + uint32_t uplink_frequency;//Absolute frequency of UL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000 + uint16_t ul_k0[5];//𝑘0 𝜇 for each of the numerologies [38.211, sec 5.3.1] Value: : 0 ->23699 + uint16_t ul_grid_size[5];//Grid size 𝑁𝑔𝑟𝑖𝑑 𝑠𝑖𝑧𝑒,𝜇 for each of the numerologies [38.211, sec 4.4.2]. Value: 0->275 0 = this numerology not used + uint16_t num_rx_ant;// + uint8_t frequency_shift_7p5khz;//Indicates presence of 7.5KHz frequency shift. Value: 0 = false 1 = true + +} fapi_nr_ue_carrier_config_t; + +typedef struct +{ + uint8_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007 + uint8_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD + +} fapi_nr_cell_config_t; + +typedef struct +{ + uint32_t ss_pbch_power;//SSB Block Power Value: TBD (-60..50 dBm) + uint8_t bch_payload;//Defines option selected for generation of BCH payload, see Table 3-13 (v0.0.011 Value: 0: MAC generates the full PBCH payload 1: PHY generates the timing PBCH bits 2: PHY generates the full PBCH payload + uint8_t scs_common;//subcarrierSpacing for common, used for initial access and broadcast message. [38.211 sec 4.2] Value:0->3 + +} fapi_nr_ssb_config_t; + +typedef struct +{ + uint32_t ssb_mask;//Bitmap for actually transmitted SSB. MSB->LSB of first 32 bit number corresponds to SSB 0 to SSB 31 MSB->LSB of second 32 bit number corresponds to SSB 32 to SSB 63 Value for each bit: 0: not transmitted 1: transmitted + +} fapi_nr_ssb_mask_size_2_t; + +typedef struct +{ + int8_t beam_id[64];//BeamID for each SSB in SsbMask. For example, if SSB mask bit 26 is set to 1, then BeamId[26] will be used to indicate beam ID of SSB 26. Value: from 0 to 63 + +} fapi_nr_ssb_mask_size_64_t; + +typedef struct +{ + uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Given in PRB [38.211, section 4.4.4.2] Value: 0->2199 + uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block [38.213, sec 4.1] Values: 0 = 0dB + uint8_t ssb_period;//SSB periodicity in msec Value: 0: ms5 1: ms10 2: ms20 3: ms40 4: ms80 5: ms160 + uint8_t ssb_subcarrier_offset;//ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (38.211, section 7.4.3.1) Value: 0->31 + uint32_t MIB;//MIB payload, where the 24 MSB are used and represent the MIB in [38.331 MIB IE] and represent 0 1 2 3 1 , , , ,..., A− a a a a a [38.212, sec 7.1.1] + fapi_nr_ssb_mask_size_2_t ssb_mask_list[2]; + fapi_nr_ssb_mask_size_64_t* ssb_beam_id_list;//64 + uint8_t ss_pbch_multiple_carriers_in_a_band;//0 = disabled 1 = enabled + uint8_t multiple_cells_ss_pbch_in_a_carrier;//Indicates that multiple cells will be supported in a single carrier 0 = disabled 1 = enabled + +} fapi_nr_ssb_table_t; + +typedef struct +{ + uint8_t slot_config;//For each symbol in each slot a uint8_t value is provided indicating: 0: DL slot 1: UL slot 2: Guard slot + +} fapi_nr_max_num_of_symbol_per_slot_t; + +typedef struct +{ + fapi_nr_max_num_of_symbol_per_slot_t* max_num_of_symbol_per_slot_list; + +} fapi_nr_max_tdd_periodicity_t; + +typedef struct +{ + uint8_t tdd_period;//DL UL Transmission Periodicity. Value:0: ms0p5 1: ms0p625 2: ms1 3: ms1p25 4: ms2 5: ms2p5 6: ms5 7: ms10 8: ms3 9: ms4 + fapi_nr_max_tdd_periodicity_t* max_tdd_periodicity_list; + +} fapi_nr_tdd_table_t; + +typedef struct +{ + uint8_t num_prach_fd_occasions; + uint16_t prach_root_sequence_index;//Starting logical root sequence index, 𝑖, equivalent to higher layer parameter prach-RootSequenceIndex [38.211, sec 6.3.3.1] Value: 0 -> 837 + uint8_t num_root_sequences;//Number of root sequences for a particular FD occasion that are required to generate the necessary number of preambles + uint16_t k1;//Frequency offset (from UL bandwidth part) for each FD. [38.211, sec 6.3.3.2] Value: from 0 to 272 + uint8_t prach_zero_corr_conf;//PRACH Zero CorrelationZone Config which is used to dervive 𝑁𝑐𝑠 [38.211, sec 6.3.3.1] Value: from 0 to 15 + uint8_t num_unused_root_sequences;//Number of unused sequences available for noise estimation per FD occasion. At least one unused root sequence is required per FD occasion. + uint8_t* unused_root_sequences_list;//Unused root sequence or sequences per FD occasion. Required for noise estimation. + +} fapi_nr_num_prach_fd_occasions_t; + +typedef struct +{ + uint8_t prach_sequence_length;//RACH sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence + uint8_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value:0->4 + uint8_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B + uint8_t num_prach_fd_occasions;//Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8 + fapi_nr_num_prach_fd_occasions_t* num_prach_fd_occasions_list; + uint8_t ssb_per_rach;//SSB-per-RACH-occasion Value: 0: 1/8 1:1/4, 2:1/2 3:1 4:2 5:4, 6:8 7:16 + uint8_t prach_multiple_carriers_in_a_band;//0 = disabled 1 = enabled + +} fapi_nr_prach_config_t; + typedef struct { uint32_t config_mask; - fapi_nr_pbch_config_t pbch_config; // MIB + fapi_nr_ue_carrier_config_t carrier_config; + fapi_nr_cell_config_t cell_config; + fapi_nr_ssb_config_t ssb_config; + fapi_nr_ssb_table_t ssb_table; + fapi_nr_tdd_table_t tdd_table; + fapi_nr_prach_config_t prach_config; fapi_nr_dl_bwp_common_config_t dl_bwp_common; fapi_nr_dl_bwp_dedicated_config_t dl_bwp_dedicated; @@ -921,3 +949,4 @@ typedef struct { } fapi_nr_config_request_t; #endif + diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h index a6cb7262a4..5fe1c53a54 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h @@ -11,43 +11,16 @@ #include "nfapi_interface.h" - #define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5 #define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64 #define NFAPI_NR_MAX_NB_CORESETS 12 #define NFAPI_NR_MAX_NB_SEARCH_SPACES 40 -// Extension to the generic structures for single tlv values -typedef struct { - nfapi_tl_t tl; - int32_t value; -} nfapi_int32_tlv_t; -typedef struct { - nfapi_tl_t tl; - uint32_t value; -} nfapi_uint32_tlv_t; - -/*typedef struct { - nfapi_tl_t tl; - int64_t value; -} nfapi_int64_tlv_t;*/ - -typedef struct { - nfapi_tl_t tl; - uint64_t value; -} nfapi_uint64_tlv_t; // nFAPI enums -typedef enum { - NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0, - NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_NBCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_NPDCCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_NDLSCH_PDU_TYPE -} nfapi_nr_dl_config_pdu_type_e; + + //These TLVs are used exclusively by nFAPI typedef struct @@ -106,37 +79,6 @@ typedef struct // P5 Message Structures -typedef struct{ - nfapi_tl_t tl; - uint16_t corset_ID; ///// L1 parameter 'CORESET-ID' - uint16_t freq_dom; ///// L1 parameter 'CORESET-freq-dom' - uint16_t duration; ///// L1 parameter 'CORESET-time-duration' - uint16_t reg_type; ///// L1 parameter 'CORESET-CCE-REG-mapping-type' - uint16_t reg_bundlesize; ///// L1 parameter 'CORESET-REG-bundle-size' - uint16_t interleaversize; ///// L1 parameter 'CORESET-interleaver-size' - uint16_t shiftindex; ///// L1 parameter 'CORESET-shift-index' - uint16_t precodergranularity; ///// L1 parameter 'CORESET-precoder-granuality' - uint16_t tci_stateId; ///// L1 parameter 'TCI-StatesPDCCH' - uint16_t tci_present; ///// L1 parameter 'TCI-PresentInDCI' - uint16_t dmrs_scramblingID; ///// L1 parameter 'PDCCH-DMRS-Scrambling-ID' -} nfapi_nr_ControlResourcesSet_t; - -typedef struct{ - nfapi_tl_t tl; - nfapi_nr_ControlResourcesSet_t coreset; - uint16_t monitoringSlotPeriodicityAndOffset; ///// L1 parameters 'Montoring-periodicity-PDCCH-slot' - uint16_t monitoringSymbolsWithinSlot; ///// L1 parameter 'Montoring-symbols-PDCCH-within-slot' - uint16_t nrofCand_aggLevel1; ///// L1 parameter 'Aggregation-level-1' - uint16_t nrofCand_aggLevel2; ///// L1 parameter 'Aggregation-level-2' - uint16_t nrofCand_aggLevel4; ///// L1 parameter 'Aggregation-level-4' - uint16_t nrofCand_aggLevel8; ///// L1 parameter 'Aggregation-level-8' - uint16_t nrofCand_aggLevel16; ///// L1 parameter 'Aggregation-level-16' - uint16_t sfi_agg_fmt2_0; ///// L1 parameters 'SFI-Num-PDCCH-cand' and 'SFI-Aggregation-Level' - uint16_t monitoringperiodicity_fmt2_3; ///// L1 parameter 'SRS-monitoring-periodicity' - uint16_t nrof_candidates_fmt_2_3; ///// L1 parameter 'SRS-Num-PDCCH-cand' -} nfapi_nr_SearchSpace_t; - - typedef struct { nfapi_uint16_tlv_t numerology_index_mu; nfapi_uint16_tlv_t duplex_mode; @@ -154,10 +96,6 @@ typedef struct { typedef struct { nfapi_uint16_tlv_t dl_carrier_bandwidth; nfapi_uint16_tlv_t ul_carrier_bandwidth; - nfapi_uint16_tlv_t dl_bwp_subcarrierspacing; - nfapi_uint16_tlv_t ul_bwp_subcarrierspacing; - nfapi_uint16_tlv_t dl_locationandbandwidth; - nfapi_uint16_tlv_t ul_locationandbandwidth; nfapi_uint16_tlv_t dl_absolutefrequencypointA; nfapi_uint16_tlv_t ul_absolutefrequencypointA; nfapi_uint16_tlv_t dl_offsettocarrier; @@ -173,6 +111,8 @@ typedef struct { #define NFAPI_NR_RF_CONFIG_UL_CARRIER_BANDWIDTH_TAG 0x500B #define NFAPI_NR_RF_CONFIG_DL_SUBCARRIERSPACING_TAG 0x500C #define NFAPI_NR_RF_CONFIG_UL_SUBCARRIERSPACING_TAG 0x500D +#define NFAPI_NR_RF_CONFIG_DL_OFFSETTOCARRIER_TAG 0x500E +#define NFAPI_NR_RF_CONFIG_UL_OFFSETTOCARRIER_TAG 0x500F typedef struct { nfapi_uint16_tlv_t physical_cell_id; @@ -183,9 +123,25 @@ typedef struct { nfapi_uint16_tlv_t ssb_periodicity; nfapi_uint16_tlv_t ss_pbch_block_power; nfapi_uint16_tlv_t n_ssb_crb; - nfapi_uint16_tlv_t rmsi_pdcch_config; } nfapi_nr_sch_config_t; +typedef struct { + nfapi_uint16_tlv_t dl_bandwidth; + nfapi_uint16_tlv_t ul_bandwidth; + nfapi_uint16_tlv_t dl_offset; + nfapi_uint16_tlv_t ul_offset; + nfapi_uint16_tlv_t dl_subcarrierSpacing; + nfapi_uint16_tlv_t ul_subcarrierSpacing; +} nfapi_nr_initialBWP_config_t; + +#define NFAPI_INITIALBWP_DL_BANDWIDTH_TAG 0x5010 +#define NFAPI_INITIALBWP_DL_OFFSET_TAG 0x5011 +#define NFAPI_INITIALBWP_DL_SUBCARRIERSPACING_TAG 0x5012 +#define NFAPI_INITIALBWP_UL_BANDWIDTH_TAG 0x5013 +#define NFAPI_INITIALBWP_UL_OFFSET_TAG 0x5014 +#define NFAPI_INITIALBWP_UL_SUBCARRIERSPACING_TAG 0x5015 + + #define NFAPI_NR_SCH_CONFIG_PHYSICAL_CELL_ID_TAG 0x501E #define NFAPI_NR_SCH_CONFIG_HALF_FRAME_INDEX_TAG 0x501F #define NFAPI_NR_SCH_CONFIG_SSB_SUBCARRIER_OFFSET_TAG 0x5020 @@ -193,25 +149,15 @@ typedef struct { #define NFAPI_NR_SCH_CONFIG_SSB_PERIODICITY 0x5022 #define NFAPI_NR_SCH_CONFIG_SS_PBCH_BLOCK_POWER 0x5023 #define NFAPI_NR_SCH_CONFIG_N_SSB_CRB 0x5024 +#define NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS 16 +#define NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS 16 typedef struct { - nfapi_uint16_tlv_t data_scrambling_id; - nfapi_uint16_tlv_t dmrs_typeA_position; - nfapi_uint16_tlv_t dmrs_additional_position; - nfapi_uint16_tlv_t dmrs_type; - nfapi_uint16_tlv_t dmrs_max_length; - nfapi_uint16_tlv_t mapping_type; - nfapi_uint16_tlv_t resource_allocation; - nfapi_uint16_tlv_t time_allocation_list; - nfapi_uint16_tlv_t mcs_table; - nfapi_uint16_tlv_t aggregation_factor; - nfapi_uint16_tlv_t prb_bundling_type; - nfapi_uint16_tlv_t rbg_size; - nfapi_uint16_tlv_t vrb_to_prb_interleaver; - nfapi_uint16_tlv_t code_block_groug_transmission; - nfapi_uint16_tlv_t x_overhead; - nfapi_uint16_tlv_t max_dci_codewords; - + nfapi_uint16_tlv_t dmrs_TypeA_Position; + nfapi_uint16_tlv_t num_PDSCHTimeDomainResourceAllocations; + nfapi_uint16_tlv_t PDSCHTimeDomainResourceAllocation_k0[NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS]; + nfapi_uint16_tlv_t PDSCHTimeDomainResourceAllocation_mappingType[NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS]; + nfapi_uint16_tlv_t PDSCHTimeDomainResourceAllocation_startSymbolAndLength[NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS]; } nfapi_nr_pdsch_config_t; #define NFAPI_NR_PDSCH_CONFIG_TAG @@ -221,43 +167,64 @@ typedef struct { nfapi_uint16_tlv_t prach_msg1_SubcarrierSpacing; ///// L1 parameter 'prach-Msg1SubcarrierSpacing' nfapi_uint16_tlv_t restrictedSetConfig; nfapi_uint16_tlv_t msg3_transformPrecoding; ///// L1 parameter 'msg3-tp' + nfapi_uint16_tlv_t ssb_perRACH_OccasionAndCB_PreamblesPerSSB; + nfapi_uint16_tlv_t ra_ContentionResolutionTimer; + nfapi_uint16_tlv_t rsrp_ThresholdSSB; /////////////////--------------------NR RACH-ConfigGeneric--------------------///////////////// nfapi_uint16_tlv_t prach_ConfigurationIndex; ///// L1 parameter 'PRACHConfigurationIndex' nfapi_uint16_tlv_t prach_msg1_FDM; ///// L1 parameter 'prach-FDM' nfapi_uint16_tlv_t prach_msg1_FrequencyStart; ///// L1 parameter 'prach-frequency-start' nfapi_uint16_tlv_t zeroCorrelationZoneConfig; nfapi_uint16_tlv_t preambleReceivedTargetPower; + nfapi_uint16_tlv_t preambleTransMax; + nfapi_uint16_tlv_t powerRampingStep; + nfapi_uint16_tlv_t ra_ResponseWindow; } nfapi_nr_rach_config_t; typedef struct { nfapi_uint16_tlv_t groupHoppingEnabledTransformPrecoding; ///// L1 parameter 'Group-hopping-enabled-Transform-precoding' nfapi_uint16_tlv_t msg3_DeltaPreamble; ///// L1 parameter 'Delta-preamble-msg3' nfapi_uint16_tlv_t p0_NominalWithGrant; ///// L1 parameter 'p0-nominal-pusch-withgrant' - nfapi_uint16_tlv_t TimeDomainResourceAllocation_k2; ///// L1 parameter 'K2' - nfapi_uint16_tlv_t TimeDomainResourceAllocation_mappingType; ///// L1 parameter 'Mapping-type' + nfapi_uint16_tlv_t dmrs_TypeA_Position; + nfapi_uint16_tlv_t num_PUSCHTimeDomainResourceAllocations; + nfapi_uint16_tlv_t PUSCHTimeDomainResourceAllocation_k2[NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; ///// L1 parameter 'K2' + nfapi_uint16_tlv_t PUSCHTimeDomainResourceAllocation_mappingType[NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; ///// L1 parameter 'Mapping-type' + nfapi_uint16_tlv_t PUSCHTimeDomainResourceAllocation_startSymbolAndLength[NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; } nfapi_nr_pusch_config_t; typedef struct { + uint8_t pucch_resource_common; nfapi_uint16_tlv_t pucch_GroupHopping; ///// L1 parameter 'PUCCH-GroupHopping' nfapi_uint16_tlv_t p0_nominal; ///// L1 parameter 'p0-nominal-pucch' } nfapi_nr_pucch_config_t; + typedef struct { nfapi_tl_t tl; - nfapi_nr_SearchSpace_t sib1searchSpace; - nfapi_nr_SearchSpace_t sibssearchSpace; - nfapi_nr_SearchSpace_t ra_SearchSpace; + + nfapi_uint16_tlv_t controlResourceSetZero; + nfapi_uint16_tlv_t searchSpaceZero; + + // nfapi_nr_SearchSpace_t sib1searchSpace; + // nfapi_nr_SearchSpace_t sibssearchSpace; + // nfapi_nr_SearchSpace_t ra_SearchSpace; }nfapi_nr_pdcch_config_t; typedef struct { //NR TDD-UL-DL-ConfigCommon ///// L1 parameter 'UL-DL-configuration-common' - nfapi_uint16_tlv_t subcarrierspacing; ///// L1 parameter 'reference-SCS' + nfapi_uint16_tlv_t referenceSubcarrierSpacing; ///// L1 parameter 'reference-SCS' nfapi_uint16_tlv_t dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity' nfapi_uint16_tlv_t nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots' nfapi_uint16_tlv_t nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common' nfapi_uint16_tlv_t nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots' nfapi_uint16_tlv_t nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common' + nfapi_uint16_tlv_t Pattern2Present; + nfapi_uint16_tlv_t Pattern2_dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity' + nfapi_uint16_tlv_t Pattern2_nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots' + nfapi_uint16_tlv_t Pattern2_nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common' + nfapi_uint16_tlv_t Pattern2_nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots' + nfapi_uint16_tlv_t Pattern2_nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common' } nfapi_nr_tdd_ul_dl_config_t; typedef struct { @@ -287,6 +254,7 @@ typedef struct { nfapi_nr_subframe_config_t subframe_config; nfapi_nr_rf_config_t rf_config; nfapi_nr_sch_config_t sch_config; + nfapi_nr_initialBWP_config_t initialBWP_config; nfapi_nr_pdsch_config_t pdsch_config; nfapi_nr_rach_config_t rach_config; nfapi_nr_pusch_config_t pusch_config; @@ -426,13 +394,9 @@ typedef enum { NFAPI_NR_MCS_TABLE_QAM256 } nfapi_nr_pdsch_mcs_table_e; -typedef enum { - NFAPI_NR_DMRS_TYPE1=0, - NFAPI_NR_DMRS_TYPE2 -} nfapi_nr_dmrs_type_e; - // P7 Sub Structures +/* typedef struct { nfapi_tl_t tl; @@ -495,9 +459,12 @@ uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 uint16_t padding; } nfapi_nr_dl_config_dci_dl_pdu_rel15_t; - +*/ //#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x???? + + +/* typedef struct{ nfapi_tl_t tl; uint8_t coreset_id; @@ -532,11 +499,13 @@ typedef struct{ uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS]; } nfapi_nr_search_space_t; + typedef struct { nfapi_tl_t tl; uint16_t rnti; uint8_t rnti_type; uint8_t dci_format; + uint16_t cce_index; /// Number of CRB in BWP that this DCI configures uint16_t n_RB_BWP; uint8_t config_type; @@ -561,118 +530,7 @@ typedef struct { nfapi_bf_vector_t bf_vector; } nfapi_nr_dl_config_pdcch_parameters_rel15_t; -typedef struct { - nfapi_tl_t tl; - uint16_t length; - int16_t pdu_index; - uint16_t transmission_power; -} nfapi_nr_dl_config_bch_pdu_rel15_t; -#define NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG 0x5025 - -typedef struct { - nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15; -} nfapi_nr_dl_config_bch_pdu; - -typedef struct { - nfapi_tl_t tl; - uint16_t length; - uint8_t pdu_index; - uint16_t rnti; - uint16_t nb_mod_symbols; - uint8_t time_allocation_type; - uint8_t freq_allocation_type; - uint16_t start_prb; - uint16_t n_prb; - uint8_t start_symbol; - uint8_t nb_symbols; - uint8_t mcs_idx; - uint8_t mcs_table; - uint8_t ndi; - uint8_t nb_codewords; - uint8_t nb_layers; - uint16_t coding_rate; - uint8_t modulation; - uint8_t modulation_order; - uint32_t transport_block_size; - uint8_t nb_re_dmrs; - uint8_t time_alloc_list_flag; - uint8_t time_alloc_list; - uint8_t rbg_list; - uint8_t virtual_resource_block_assignment_flag; - uint32_t resource_block_coding; - uint8_t redundancy_version; - uint8_t transport_blocks; - uint8_t transmission_scheme; - uint8_t number_of_subbands; - uint8_t codebook_index[NFAPI_MAX_NUM_SUBBANDS]; - uint8_t ue_category_capacity; - uint8_t pa; - uint8_t delta_power_offset_index; - uint8_t ngap; - uint8_t transmission_mode; - uint8_t num_bf_prb_per_subband; - uint8_t num_bf_vector; - nfapi_bf_vector_t bf_vector[NFAPI_MAX_BF_VECTORS]; -}nfapi_nr_dl_config_dlsch_pdu_rel15_t; -#define NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG - -typedef struct { - nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15; -} nfapi_nr_dl_config_dlsch_pdu; - -typedef struct { - nfapi_tl_t tl; - nfapi_nr_search_space_t pagingSearchSpace; - nfapi_nr_coreset_t pagingControlResourceSets; -}nfapi_nr_dl_config_pch_pdu_rel15_t; - -typedef struct { - -} nfapi_nr_dl_config_nbch_pdu_rel15_t; - -typedef struct { - -} nfapi_nr_dl_config_npdcch_pdu_rel15_t; - -typedef struct { - -} nfapi_nr_dl_config_ndlsch_pdu_rel15_t; - -typedef struct { - nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15; -} nfapi_nr_dl_config_dci_dl_pdu; - - -typedef struct { - uint8_t pdu_type; - uint8_t pdu_size; - - union { - nfapi_nr_dl_config_dci_dl_pdu dci_dl_pdu; - nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15; - nfapi_nr_dl_config_dlsch_pdu dlsch_pdu; - nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15; - nfapi_nr_dl_config_nbch_pdu_rel15_t nbch_pdu_rel15; - nfapi_nr_dl_config_npdcch_pdu_rel15_t npdcch_pdu_rel15; - nfapi_nr_dl_config_ndlsch_pdu_rel15_t ndlsch_pdu_rel15; - }; -} nfapi_nr_dl_config_request_pdu_t; - -typedef struct { - nfapi_tl_t tl; - uint8_t number_dci; - uint8_t number_pdu; - uint8_t number_pdsch_rnti; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu_list; -} nfapi_nr_dl_config_request_body_t; - -typedef struct { - nfapi_p7_message_header_t header; - uint16_t sfn_sf; - nfapi_nr_dl_config_request_body_t dl_config_request_body; - nfapi_vendor_extension_tlv_t vendor_extension; -} nfapi_nr_dl_config_request_t; +*/ typedef enum {nr_pusch_freq_hopping_disabled = 0 , @@ -711,9 +569,37 @@ typedef struct { uint8_t beta_offset_ind; } nfapi_nr_ul_config_ulsch_pdu_rel15_t; + + + + typedef struct { uint16_t rnti; nfapi_nr_ul_config_ulsch_pdu_rel15_t ulsch_pdu_rel15; } nfapi_nr_ul_config_ulsch_pdu; +typedef struct { + uint8_t pdu_type; + uint8_t pdu_size; + + union { + // nfapi_nr_ul_config_uci_pdu uci_pdu; + nfapi_nr_ul_config_ulsch_pdu ulsch_pdu; + // nfapi_nr_ul_config_srs_pdu srs_pdu; + }; +} nfapi_nr_ul_config_request_pdu_t; + +typedef struct { + nfapi_tl_t tl; + uint8_t number_pdu; + nfapi_nr_ul_config_request_pdu_t *ul_config_pdu_list; +} nfapi_nr_ul_config_request_body_t; + +typedef struct { + nfapi_p7_message_header_t header; + uint16_t sfn_sf; + nfapi_nr_ul_config_request_body_t ul_config_request_body; + nfapi_vendor_extension_tlv_t vendor_extension; +} nfapi_nr_ul_config_request_t; + #endif diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 1eea6474f3..f69c928ed2 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -22,7 +22,6 @@ #define NFAPI_MAX_NUM_GROUPS 8 #define NFAPI_MAX_NUM_CB 8 -/* // Extension to the generic structures for single tlv values typedef struct { nfapi_tl_t tl; @@ -33,7 +32,34 @@ typedef struct { nfapi_tl_t tl; uint32_t value; } nfapi_uint32_tlv_t; -*/ + +typedef struct { + nfapi_tl_t tl; + int64_t value; +} nfapi_int64_tlv_t; + +typedef struct { + nfapi_tl_t tl; + uint64_t value; +} nfapi_uint64_tlv_t; + +typedef enum { + NFAPI_NR_DMRS_TYPE1=0, + NFAPI_NR_DMRS_TYPE2 +} nfapi_nr_dmrs_type_e; + + +typedef struct { + /// Value: 0 -> 1, 0: Payload is carried directly in the value field, 1: Pointer to payload is in the value field + uint16_t tag; + /// Length of the actual payload in bytes, without the padding bytes Value: 0 → 65535 + uint16_t length; + union { + uint32_t *ptr; + uint32_t direct[16384]; + } value; +} nfapi_nr_tx_data_request_tlv_t; + // 2019.8 // SCF222_5G-FAPI_PHY_SPI_Specificayion.pdf Section 3.2 @@ -67,12 +93,6 @@ typedef enum { //3.3.1 PARAM -typedef struct { - nfapi_tl_t tl; - uint16_t value; - -} nfapi_nr_param_tlv_t; - //same with nfapi_param_request_t typedef struct { nfapi_p4_p5_message_header_t header; @@ -85,12 +105,12 @@ typedef enum { } nfapi_nr_param_errors_e; -typedef struct { +/*typedef struct { nfapi_nr_param_errors_e error_code; //Number of TLVs contained in the message body. uint8_t number_of_tlvs; nfapi_nr_param_tlv_t TLV; -} nfapi_nr_param_response_t; +} nfapi_nr_param_response_t;*/ //PARAM and CONFIG TLVs are used in the PARAM and CONFIG message exchanges, respectively @@ -100,7 +120,7 @@ typedef struct { //table 3-9 -#define NFAPI_NR_PARAM_TLV_RELEASE_CAPABILITY_TAG 0x0001 +#define NFAPI_NR_PARAM_TLV_RELEASE_CAPABILITY_TAG 0x0001 #define NFAPI_NR_PARAM_TLV_PHY_STATE_TAG 0x0002 #define NFAPI_NR_PARAM_TLV_SKIP_BLANK_DL_CONFIG_TAG 0x0003 #define NFAPI_NR_PARAM_TLV_SKIP_BLANK_UL_CONFIG_TAG 0x0004 @@ -157,123 +177,113 @@ typedef struct { typedef struct { - uint16_t release_capability; //TAG 0x0001 - uint16_t phy_state; - uint8_t skip_blank_dl_config; - uint8_t skip_blank_ul_config; - uint16_t num_config_tlvs_to_report; - nfapi_nr_param_tlv_t* config_tlvs_to_report_list; + nfapi_uint16_tlv_t release_capability; //TAG 0x0001 + nfapi_uint16_tlv_t phy_state; + nfapi_uint8_tlv_t skip_blank_dl_config; + nfapi_uint8_tlv_t skip_blank_ul_config; + nfapi_uint16_tlv_t num_config_tlvs_to_report; + nfapi_uint8_tlv_t* config_tlvs_to_report_list; } nfapi_nr_cell_param_t; //table 3-10 Carrier parameters typedef struct { - uint8_t cyclic_prefix;//TAG 0x0006 - uint8_t supported_subcarrier_spacings_dl; - uint16_t supported_bandwidth_dl; - uint8_t supported_subcarrier_spacings_ul; - uint16_t supported_bandwidth_ul; + nfapi_uint8_tlv_t cyclic_prefix;//TAG 0x0006 + nfapi_uint16_tlv_t supported_subcarrier_spacings_dl; + nfapi_uint16_tlv_t supported_bandwidth_dl; + nfapi_uint8_tlv_t supported_subcarrier_spacings_ul; + nfapi_uint16_tlv_t supported_bandwidth_ul; } nfapi_nr_carrier_param_t; //table 3-11 PDCCH parameters typedef struct { - uint8_t cce_mapping_type; - uint8_t coreset_outside_first_3_of_ofdm_syms_of_slot; - uint8_t coreset_precoder_granularity_coreset; - uint8_t pdcch_mu_mimo; - uint8_t pdcch_precoder_cycling; - uint8_t max_pdcch_per_slot;//TAG 0x0010 + nfapi_uint8_tlv_t cce_mapping_type; + nfapi_uint8_tlv_t coreset_outside_first_3_of_ofdm_syms_of_slot; + nfapi_uint8_tlv_t coreset_precoder_granularity_coreset; + nfapi_uint8_tlv_t pdcch_mu_mimo; + nfapi_uint8_tlv_t pdcch_precoder_cycling; + nfapi_uint8_tlv_t max_pdcch_per_slot;//TAG 0x0010 } nfapi_nr_pdcch_param_t; //table 3-12 PUCCH parameters typedef struct { - uint8_t pucch_formats; - uint8_t max_pucchs_per_slot; + nfapi_uint8_tlv_t pucch_formats; + nfapi_uint8_tlv_t max_pucchs_per_slot; } nfapi_nr_pucch_param_t; //table 3-13 PDSCH parameters typedef struct { - uint8_t pdsch_mapping_type; - uint8_t pdsch_allocation_types; - uint8_t pdsch_vrb_to_prb_mapping; - uint8_t pdsch_cbg; - uint8_t pdsch_dmrs_config_types; - uint8_t pdsch_dmrs_max_length; - uint8_t pdsch_dmrs_additional_pos; - uint8_t max_pdsch_tbs_per_slot; - uint8_t max_number_mimo_layers_pdsch; - uint8_t supported_max_modulation_order_dl; - uint8_t max_mu_mimo_users_dl; - uint8_t pdsch_data_in_dmrs_symbols; - uint8_t premption_support;//TAG 0x001F - uint8_t pdsch_non_slot_support; + nfapi_uint8_tlv_t pdsch_mapping_type; + nfapi_uint8_tlv_t pdsch_allocation_types; + nfapi_uint8_tlv_t pdsch_vrb_to_prb_mapping; + nfapi_uint8_tlv_t pdsch_cbg; + nfapi_uint8_tlv_t pdsch_dmrs_config_types; + nfapi_uint8_tlv_t pdsch_dmrs_max_length; + nfapi_uint8_tlv_t pdsch_dmrs_additional_pos; + nfapi_uint8_tlv_t max_pdsch_tbs_per_slot; + nfapi_uint8_tlv_t max_number_mimo_layers_pdsch; + nfapi_uint8_tlv_t supported_max_modulation_order_dl; + nfapi_uint8_tlv_t max_mu_mimo_users_dl; + nfapi_uint8_tlv_t pdsch_data_in_dmrs_symbols; + nfapi_uint8_tlv_t premption_support;//TAG 0x001F + nfapi_uint8_tlv_t pdsch_non_slot_support; } nfapi_nr_pdsch_param_t; //table 3-14 typedef struct { - uint8_t uci_mux_ulsch_in_pusch; - uint8_t uci_only_pusch; - uint8_t pusch_frequency_hopping; - uint8_t pusch_dmrs_config_types; - uint8_t pusch_dmrs_max_len; - uint8_t pusch_dmrs_additional_pos; - uint8_t pusch_cbg; - uint8_t pusch_mapping_type; - uint8_t pusch_allocation_types; - uint8_t pusch_vrb_to_prb_mapping; - //uint8 ? ↓ see table 3-14 - uint8_t pusch_max_ptrs_ports; - uint8_t max_pduschs_tbs_per_slot; - uint8_t max_number_mimo_layers_non_cb_pusch; - uint8_t supported_modulation_order_ul; - uint8_t max_mu_mimo_users_ul; - uint8_t dfts_ofdm_support; - uint8_t pusch_aggregation_factor;//TAG 0x0031 + nfapi_uint8_tlv_t uci_mux_ulsch_in_pusch; + nfapi_uint8_tlv_t uci_only_pusch; + nfapi_uint8_tlv_t pusch_frequency_hopping; + nfapi_uint8_tlv_t pusch_dmrs_config_types; + nfapi_uint8_tlv_t pusch_dmrs_max_len; + nfapi_uint8_tlv_t pusch_dmrs_additional_pos; + nfapi_uint8_tlv_t pusch_cbg; + nfapi_uint8_tlv_t pusch_mapping_type; + nfapi_uint8_tlv_t pusch_allocation_types; + nfapi_uint8_tlv_t pusch_vrb_to_prb_mapping; + nfapi_uint8_tlv_t pusch_max_ptrs_ports; + nfapi_uint8_tlv_t max_pduschs_tbs_per_slot; + nfapi_uint8_tlv_t max_number_mimo_layers_non_cb_pusch; + nfapi_uint8_tlv_t supported_modulation_order_ul; + nfapi_uint8_tlv_t max_mu_mimo_users_ul; + nfapi_uint8_tlv_t dfts_ofdm_support; + nfapi_uint8_tlv_t pusch_aggregation_factor;//TAG 0x0031 } nfapi_nr_pusch_param_t; //table 3-15 typedef struct { - uint8_t prach_long_formats; - uint8_t prach_short_formats; - uint8_t prach_restricted_sets; - uint8_t max_prach_fd_occasions_in_a_slot; - + nfapi_uint8_tlv_t prach_long_formats; + nfapi_uint8_tlv_t prach_short_formats; + nfapi_uint8_tlv_t prach_restricted_sets; + nfapi_uint8_tlv_t max_prach_fd_occasions_in_a_slot; } nfapi_nr_prach_param_t; //table 3-16 typedef struct { - uint8_t rssi_measurement_support; + nfapi_uint8_tlv_t rssi_measurement_support; } nfapi_nr_measurement_param_t; //-------------------------------------------// //3.3.2 CONFIG -typedef struct { - nfapi_tl_t tl; - uint16_t value; -} nfapi_nr_config_tlv_t; -typedef struct { - uint8_t number_of_tlvs; - nfapi_nr_config_tlv_t tlv; -} nfapi_nr_config_request_scf_t; typedef enum { NFAPI_NR_CONFIG_MSG_OK = 0, - NFAPI_NR_CONFIG_MSG_INVALID_CONFIG //The configuration provided has missing mandatory TLVs, or TLVs that are invalid or unsupported in this state. + NFAPI_NR_CONFIG_MSG_INVALID_CONFIG //The configuration provided has missing mandatory TLVs, or TLVs that are invalid or unsupported in this state. } nfapi_nr_config_errors_e; -typedef struct { +/*typedef struct { nfapi_nr_config_errors_e error_code; uint8_t number_of_invalid_tlvs_that_can_only_be_configured_in_idle; uint8_t unmber_of_missing_tlvs; @@ -283,7 +293,7 @@ typedef struct { nfapi_nr_config_tlv_t* tlv_invalid_running_list; nfapi_nr_config_tlv_t* tlv_missing_list; -} nfapi_nr_config_response_t; +} nfapi_nr_config_response_t;*/ //nfapi_nr_config_tlv_format_t carrier config ~ precoding config: @@ -336,34 +346,34 @@ typedef struct { //table 3-21 typedef struct { - uint16_t dl_bandwidth;//Carrier bandwidth for DL in MHz [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400 - uint32_t dl_frequency; //Absolute frequency of DL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000 - uint16_t dl_k0[5];//𝑘_{0}^{𝜇} for each of the numerologies [38.211, sec 5.3.1] Value: 0 ->23699 - uint16_t dl_grid_size[5];//Grid size 𝑁_{𝑔𝑟𝑖𝑑}^{𝑠𝑖𝑧𝑒,𝜇} for each of the numerologies [38.211, sec 4.4.2] Value: 0->275 0 = this numerology not used - uint16_t num_tx_ant;//Number of Tx antennas - uint16_t uplink_bandwidth;//Carrier bandwidth for UL in MHz. [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400 - uint32_t uplink_frequency;//Absolute frequency of UL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000 - uint16_t ul_k0[5];//𝑘0 𝜇 for each of the numerologies [38.211, sec 5.3.1] Value: : 0 ->23699 - uint16_t ul_grid_size[5];//Grid size 𝑁𝑔𝑟𝑖𝑑 𝑠𝑖𝑧𝑒,𝜇 for each of the numerologies [38.211, sec 4.4.2]. Value: 0->275 0 = this numerology not used - uint16_t num_rx_ant;// - uint8_t frequency_shift_7p5khz;//Indicates presence of 7.5KHz frequency shift. Value: 0 = false 1 = true + nfapi_uint16_tlv_t dl_bandwidth;//Carrier bandwidth for DL in MHz [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400 + nfapi_uint32_tlv_t dl_frequency; //Absolute frequency of DL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000 + nfapi_uint16_tlv_t dl_k0[5];//𝑘_{0}^{𝜇} for each of the numerologies [38.211, sec 5.3.1] Value: 0 ->23699 + nfapi_uint16_tlv_t dl_grid_size[5];//Grid size 𝑁_{𝑔𝑟𝑖𝑑}^{𝑠𝑖𝑧𝑒,𝜇} for each of the numerologies [38.211, sec 4.4.2] Value: 0->275 0 = this numerology not used + nfapi_uint16_tlv_t num_tx_ant;//Number of Tx antennas + nfapi_uint16_tlv_t uplink_bandwidth;//Carrier bandwidth for UL in MHz. [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400 + nfapi_uint32_tlv_t uplink_frequency;//Absolute frequency of UL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000 + nfapi_uint16_tlv_t ul_k0[5];//𝑘0 𝜇 for each of the numerologies [38.211, sec 5.3.1] Value: : 0 ->23699 + nfapi_uint16_tlv_t ul_grid_size[5];//Grid size 𝑁𝑔𝑟𝑖𝑑 𝑠𝑖𝑧𝑒,𝜇 for each of the numerologies [38.211, sec 4.4.2]. Value: 0->275 0 = this numerology not used + nfapi_uint16_tlv_t num_rx_ant;// + nfapi_uint8_tlv_t frequency_shift_7p5khz;//Indicates presence of 7.5KHz frequency shift. Value: 0 = false 1 = true } nfapi_nr_carrier_config_t; //table 3-22 typedef struct { - uint8_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007 - uint8_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD + nfapi_uint8_tlv_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007 + nfapi_uint8_tlv_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD } nfapi_nr_cell_config_t; //table 3-23 typedef struct { - uint32_t ss_pbch_power;//SSB Block Power Value: TBD (-60..50 dBm) - uint8_t bch_payload;//Defines option selected for generation of BCH payload, see Table 3-13 (v0.0.011 Value: 0: MAC generates the full PBCH payload 1: PHY generates the timing PBCH bits 2: PHY generates the full PBCH payload - uint8_t scs_common;//subcarrierSpacing for common, used for initial access and broadcast message. [38.211 sec 4.2] Value:0->3 + nfapi_uint32_tlv_t ss_pbch_power;//SSB Block Power Value: TBD (-60..50 dBm) + nfapi_uint8_tlv_t bch_payload;//Defines option selected for generation of BCH payload, see Table 3-13 (v0.0.011 Value: 0: MAC generates the full PBCH payload 1: PHY generates the timing PBCH bits 2: PHY generates the full PBCH payload + nfapi_uint8_tlv_t scs_common;//subcarrierSpacing for common, used for initial access and broadcast message. [38.211 sec 4.2] Value:0->3 } nfapi_nr_ssb_config_t; @@ -375,51 +385,51 @@ typedef struct typedef struct { uint8_t num_prach_fd_occasions; - uint16_t prach_root_sequence_index;//Starting logical root sequence index, 𝑖, equivalent to higher layer parameter prach-RootSequenceIndex [38.211, sec 6.3.3.1] Value: 0 -> 837 - uint8_t num_root_sequences;//Number of root sequences for a particular FD occasion that are required to generate the necessary number of preambles - uint16_t k1;//Frequency offset (from UL bandwidth part) for each FD. [38.211, sec 6.3.3.2] Value: from 0 to 272 - uint8_t prach_zero_corr_conf;//PRACH Zero CorrelationZone Config which is used to dervive 𝑁𝑐𝑠 [38.211, sec 6.3.3.1] Value: from 0 to 15 - uint8_t num_unused_root_sequences;//Number of unused sequences available for noise estimation per FD occasion. At least one unused root sequence is required per FD occasion. - uint8_t* unused_root_sequences_list;//Unused root sequence or sequences per FD occasion. Required for noise estimation. + nfapi_uint16_tlv_t prach_root_sequence_index;//Starting logical root sequence index, 𝑖, equivalent to higher layer parameter prach-RootSequenceIndex [38.211, sec 6.3.3.1] Value: 0 -> 837 + nfapi_uint8_tlv_t num_root_sequences;//Number of root sequences for a particular FD occasion that are required to generate the necessary number of preambles + nfapi_uint16_tlv_t k1;//Frequency offset (from UL bandwidth part) for each FD. [38.211, sec 6.3.3.2] Value: from 0 to 272 + nfapi_uint8_tlv_t prach_zero_corr_conf;//PRACH Zero CorrelationZone Config which is used to dervive 𝑁𝑐𝑠 [38.211, sec 6.3.3.1] Value: from 0 to 15 + nfapi_uint8_tlv_t num_unused_root_sequences;//Number of unused sequences available for noise estimation per FD occasion. At least one unused root sequence is required per FD occasion. + nfapi_uint8_tlv_t* unused_root_sequences_list;//Unused root sequence or sequences per FD occasion. Required for noise estimation. } nfapi_nr_num_prach_fd_occasions_t; typedef struct { - uint8_t prach_sequence_length;//RACH sequence length. Long or Short sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence - uint8_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value:0->4 - uint8_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B - uint8_t num_prach_fd_occasions;//Number of RACH frequency domain occasions. Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8 + nfapi_uint8_tlv_t prach_sequence_length;//RACH sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence + nfapi_uint8_tlv_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value:0->4 + nfapi_uint8_tlv_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B + nfapi_uint8_tlv_t num_prach_fd_occasions;//Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8 nfapi_nr_num_prach_fd_occasions_t* num_prach_fd_occasions_list; - uint8_t ssb_per_rach;//SSB-per-RACH-occasion Value: 0: 1/8 1:1/4, 2:1/2 3:1 4:2 5:4, 6:8 7:16 - uint8_t prach_multiple_carriers_in_a_band;//0 = disabled 1 = enabled + nfapi_uint8_tlv_t ssb_per_rach;//SSB-per-RACH-occasion Value: 0: 1/8 1:1/4, 2:1/2 3:1 4:2 5:4, 6:8 7:16 + nfapi_uint8_tlv_t prach_multiple_carriers_in_a_band;//0 = disabled 1 = enabled } nfapi_nr_prach_config_t; //table 3-25 typedef struct { - uint32_t ssb_mask;//Bitmap for actually transmitted SSB. MSB->LSB of first 32 bit number corresponds to SSB 0 to SSB 31 MSB->LSB of second 32 bit number corresponds to SSB 32 to SSB 63 Value for each bit: 0: not transmitted 1: transmitted + nfapi_uint32_tlv_t ssb_mask;//Bitmap for actually transmitted SSB. MSB->LSB of first 32 bit number corresponds to SSB 0 to SSB 31 MSB->LSB of second 32 bit number corresponds to SSB 32 to SSB 63 Value for each bit: 0: not transmitted 1: transmitted } nfapi_nr_ssb_mask_size_2_t; typedef struct { - uint8_t beam_id[64];//BeamID for each SSB in SsbMask. For example, if SSB mask bit 26 is set to 1, then BeamId[26] will be used to indicate beam ID of SSB 26. Value: from 0 to 63 + nfapi_uint8_tlv_t beam_id[64];//BeamID for each SSB in SsbMask. For example, if SSB mask bit 26 is set to 1, then BeamId[26] will be used to indicate beam ID of SSB 26. Value: from 0 to 63 } nfapi_nr_ssb_mask_size_64_t; typedef struct { - uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Given in PRB [38.211, section 4.4.4.2] Value: 0->2199 - uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block [38.213, sec 4.1] Values: 0 = 0dB - uint8_t ssb_period;//SSB periodicity in msec Value: 0: ms5 1: ms10 2: ms20 3: ms40 4: ms80 5: ms160 - uint8_t ssb_subcarrier_offset;//ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (38.211, section 7.4.3.1) Value: 0->31 - uint32_t MIB;//MIB payload, where the 24 MSB are used and represent the MIB in [38.331 MIB IE] and represent 0 1 2 3 1 , , , ,..., A− a a a a a [38.212, sec 7.1.1] - nfapi_nr_ssb_mask_size_2_t* ssb_mask_size_2_list;//2 - nfapi_nr_ssb_mask_size_64_t* ssb_mask_size_64_list;//64 - uint8_t ss_pbch_multiple_carriers_in_a_band;//0 = disabled 1 = enabled - uint8_t multiple_cells_ss_pbch_in_a_carrier;//Indicates that multiple cells will be supported in a single carrier 0 = disabled 1 = enabled + nfapi_uint16_tlv_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Given in PRB [38.211, section 4.4.4.2] Value: 0->2199 + nfapi_uint8_tlv_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block [38.213, sec 4.1] Values: 0 = 0dB + nfapi_uint8_tlv_t ssb_period;//SSB periodicity in msec Value: 0: ms5 1: ms10 2: ms20 3: ms40 4: ms80 5: ms160 + nfapi_uint8_tlv_t ssb_subcarrier_offset;//ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (38.211, section 7.4.3.1) Value: 0->31 + nfapi_uint32_tlv_t MIB;//MIB payload, where the 24 MSB are used and represent the MIB in [38.331 MIB IE] and represent 0 1 2 3 1 , , , ,..., A− a a a a a [38.212, sec 7.1.1] + nfapi_nr_ssb_mask_size_2_t ssb_mask_list[2]; + nfapi_nr_ssb_mask_size_64_t* ssb_beam_id_list;//64 + nfapi_uint8_tlv_t ss_pbch_multiple_carriers_in_a_band;//0 = disabled 1 = enabled + nfapi_uint8_tlv_t multiple_cells_ss_pbch_in_a_carrier;//Indicates that multiple cells will be supported in a single carrier 0 = disabled 1 = enabled } nfapi_nr_ssb_table_t; @@ -428,7 +438,7 @@ typedef struct //? typedef struct { - uint8_t slot_config;//For each symbol in each slot a uint8_t value is provided indicating: 0: DL slot 1: UL slot 2: Guard slot + nfapi_uint8_tlv_t slot_config;//For each symbol in each slot a uint8_t value is provided indicating: 0: DL slot 1: UL slot 2: Guard slot } nfapi_nr_max_num_of_symbol_per_slot_t; @@ -440,7 +450,7 @@ typedef struct typedef struct { - uint8_t tdd_period;//DL UL Transmission Periodicity. Value:0: ms0p5 1: ms0p625 2: ms1 3: ms1p25 4: ms2 5: ms2p5 6: ms5 7: ms10 + nfapi_uint8_tlv_t tdd_period;//DL UL Transmission Periodicity. Value:0: ms0p5 1: ms0p625 2: ms1 3: ms1p25 4: ms2 5: ms2p5 6: ms5 7: ms10 8: ms3 9: ms4 nfapi_nr_max_tdd_periodicity_t* max_tdd_periodicity_list; } nfapi_nr_tdd_table_t; @@ -448,10 +458,23 @@ typedef struct //table 3-27 typedef struct { - uint8_t rssi_measurement;//RSSI measurement unit. See Table 3-16 for RSSI definition. Value: 0: Do not report RSSI 1: dBm 2: dBFS + nfapi_uint8_tlv_t rssi_measurement;//RSSI measurement unit. See Table 3-16 for RSSI definition. Value: 0: Do not report RSSI 1: dBm 2: dBFS } nfapi_nr_measurement_config_t; + +typedef struct { + uint8_t num_tlv; + nfapi_nr_carrier_config_t carrier_config; + nfapi_nr_cell_config_t cell_config; + nfapi_nr_ssb_config_t ssb_config; + nfapi_nr_prach_config_t prach_config; + nfapi_nr_ssb_table_t ssb_table; + nfapi_nr_tdd_table_t tdd_table; + nfapi_nr_measurement_config_t measurement_config; +} nfapi_nr_config_request_scf_t; + + //------------------------------// //3.3.3 START @@ -573,17 +596,29 @@ typedef struct }nfapi_nr_tx_precoding_and_beamforming_number_of_prgs_t; +/* //table 3-43 typedef struct { - uint16_t num_prgs;/*Number of PRGs spanning this allocation. -Value : 1->275 */ - uint16_t prg_size;/*Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 */ + uint16_t num_prgs;//Number of PRGs spanning this allocation. Value : 1->275 + uint16_t prg_size;//Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 //watchout: dig_bf_interfaces here, in table 3-53 it's dig_bf_interface uint8_t dig_bf_interfaces;//Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 nfapi_nr_tx_precoding_and_beamforming_number_of_prgs_t* prgs_list;// }nfapi_nr_tx_precoding_and_beamforming_t; +*/ + +typedef struct { + /// Number of PRGs spanning this allocation. Value : 1->275 + uint16_t numPRGs; + /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 + uint16_t prgSize; + /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 + uint8_t digBFInterfaces; + uint16_t PMIdx[275]; + uint16_t *beamIdx[275]; +} nfapi_nr_tx_precoding_and_beamforming_t; //table 3-37 @@ -606,33 +641,154 @@ SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */ } nfapi_nr_dl_dci_pdu_t; -//table 3-36 -typedef struct -{ - uint16_t bwp_size;//Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP Value: 1->275 - uint16_t bwp_start;//bandwidth part start RB index from reference CRB [TS38.213 sec 12] Value: 0->274 - uint8_t subcarrier_spacing;//subcarrierSpacing [TS38.211 sec 4.2] Value:0->4 - uint8_t cyclic_prefix;//Cyclic prefix type [TS38.211 sec 4.2] 0: Normal; 1: Extended - //Coreset [TS38.211 sec 7.3.2.2] - uint8_t start_symbol_index;//Starting OFDM symbol for the CORESET Value: 0->13 - uint8_t duration_symbols;/* Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter 𝑁𝑠𝑦𝑚𝑏 𝐶𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3*/ - uint8_t freq_domain_resource[6];/* Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter N^{CORESET}_{RB} [TS38.211 sec 7.3.2.2] - Bitmap of uint8 array. 45 bits.*/ - uint8_t cce_reg_mapping_type;/*CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved */ - uint8_t reg_bundle_size;/*The number of REGs in a bundle. Must be 6 for -cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if -duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 */ - uint8_t interleaver_size;//The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 - uint8_t core_set_type;//[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET) - uint16_t shift_index;//[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275 - uint8_t precoder_granularity;//Granularity of precoding [TS38.211 sec 7.3.2.2] 0: sameAsRegBundle 1: allContiguousRBs - uint16_t num_dl_dci;//Number of DCIs in this CORESET. Value: 0->MaxDciPerSlot - nfapi_nr_dl_dci_pdu_t* dl_dci_list; +typedef struct { + /// Number of PRGs spanning this allocation. Value : 1->275 + uint16_t numPRGs; + /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 + uint16_t prgSize; + /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 + uint8_t digBFInterfaces; + uint16_t PMIdx[275]; + uint16_t *beamIdx[275]; +} nr_beamforming_t; + +#define MAX_DCI_CORESET 8 +#define DCI_PAYLOAD_BYTE_LEN 8 + +typedef struct { + ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 + uint16_t BWPSize; + ///bandwidth part start RB index from reference CRB, [TS38.213 sec 12], Value: 0->274 + uint16_t BWPStart; + ///subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 + uint8_t SubcarrierSpacing; + ///Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended + uint8_t CyclicPrefix; + ///Starting OFDM symbol for the CORESET, Value: 0->13 + uint8_t StartSymbolIndex; +///Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter 𝑁𝑠𝑦𝑚𝑏_𝐶𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3 + uint8_t DurationSymbols; + ///Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter CORE SET RB N [TS38.211 sec 7.3.2.2] Bitmap of uint8 array. 45 bits. + uint8_t FreqDomainResource[6]; + ///CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved + uint8_t CceRegMappingType; + ///The number of REGs in a bundle. Must be 6 for cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 + uint8_t RegBundleSize; + ///The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 CoreSetType + uint8_t InterleaverSize; + ///[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET) + uint8_t CoreSetType; + ///[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275 + uint16_t ShiftIndex; + ///Granularity of precoding [TS38.211 sec 7.3.2.2] Field Type Description 0: sameAsRegBundle 1: allContiguousRBs + uint8_t precoderGranularity; + ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot + uint16_t numDlDci; + ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. + uint16_t RNTI[MAX_DCI_CORESET]; + ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 + uint16_t ScramblingId[MAX_DCI_CORESET]; + ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 + uint16_t ScramblingRNTI[MAX_DCI_CORESET]; + ///CCE start Index used to send the DCI Value: 0->135 + uint8_t CceIndex[MAX_DCI_CORESET]; + ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 + uint8_t AggregationLevel[MAX_DCI_CORESET]; + ///Precoding and Beamforming structure See Table 3-43 + nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; + ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps + uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; + ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB + uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; +///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8 + uint16_t PayloadSizeBits[MAX_DCI_CORESET]; + ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB + uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; +} nfapi_nr_dl_tti_pdcch_pdu_rel15_t; + +typedef struct { + uint16_t pduBitmap; + uint16_t rnti; + uint16_t pduIndex; + // BWP [TS38.213 sec 12] + /// Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP, Value: 1->275 + uint16_t BWPSize; + /// bandwidth part start RB index from reference CRB [TS38.213 sec 12],Value: 0->274 + uint16_t BWPStart; + /// subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 + uint8_t SubcarrierSpacing; + /// Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended + uint8_t CyclicPrefix; + // Codeword information + /// Number of code words for this RNTI (UE), Value: 1 -> 2 + uint8_t NrOfCodewords; + /// Target coding rate [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1]. This is the number of information bits per 1024 coded bits expressed in 0.1 bit units + uint16_t targetCodeRate[2]; + /// QAM modulation [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1], Value: 2,4,6,8 + uint8_t qamModOrder[2]; + /// MCS index [TS38.214, sec 5.1.3.1], should match value sent in DCI Value : 0->31 + uint8_t mcsIndex[2]; + /// MCS-Table-PDSCH [TS38.214, sec 5.1.3.1] 0: notqam256, 1: qam256, 2: qam64LowSE + uint8_t mcsTable[2]; + /// Redundancy version index [TS38.212, Table 5.4.2.1-2 and 38.214, Table 5.1.2.1-2], should match value sent in DCI Value : 0->3 + uint8_t rvIndex[2]; + /// Transmit block size (in bytes) [TS38.214 sec 5.1.3.2], Value: 0->65535 + uint32_t TBSize[2]; + /// dataScramblingIdentityPdsch [TS38.211, sec 7.3.1.1], It equals the higher-layer parameter Datascrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id. Value: 0->65535 + uint16_t dataScramblingId; + /// Number of layers [TS38.211, sec 7.3.1.3]. Value : 1->8 + uint8_t nrOfLayers; + /// PDSCH transmission schemes [TS38.214, sec5.1.1] 0: Up to 8 transmission layers + uint8_t transmissionScheme; + /// Reference point for PDSCH DMRS "k" - used for tone mapping [TS38.211, sec 7.4.1.1.2] Resource block bundles [TS38.211, sec 7.3.1.6] Value: 0 -> 1 If 0, the 0 reference point for PDSCH DMRS is at Point A [TS38.211 sec 4.4.4.2]. Resource block bundles generated per sub-bullets 2 and 3 in [TS38.211, sec 7.3.1.6]. For sub-bullet 2, the start of bandwidth part must be set to the start of actual bandwidth part +NstartCORESET and the bandwidth of the bandwidth part must be set to the bandwidth of the initial bandwidth part. If 1, the DMRS reference point is at the lowest VRB/PRB of the allocation. Resource block bundles generated per sub-bullets 1 [TS38.211, sec 7.3.1.6] + uint8_t refPoint; + // DMRS [TS38.211 sec 7.4.1.1] + /// DMRS symbol positions [TS38.211, sec 7.4.1.1.2 and Tables 7.4.1.1.2-3 and 7.4.1.1.2-4] Bitmap occupying the 14 LSBs with: bit 0: first symbol and for each bit 0: no DMRS 1: DMRS + uint16_t dlDmrsSymbPos; + /// DL DMRS config type [TS38.211, sec 7.4.1.1.2] 0: type 1, 1: type 2 + uint8_t dmrsConfigType; + /// DL-DMRS-Scrambling-ID [TS38.211, sec 7.4.1.1.2 ] If provided by the higher-layer and the PDSCH is scheduled by PDCCH with CRC scrambled by CRNTI or CS-RNTI, otherwise, L2 should set this to physical cell id. Value: 0->65535 + uint16_t dlDmrsScramblingId; + /// DMRS sequence initialization [TS38.211, sec 7.4.1.1.2]. Should match what is sent in DCI 1_1, otherwise set to 0. Value : 0->1 + uint8_t SCID; + /// Number of DM-RS CDM groups without data [TS38.212 sec 7.3.1.2.2] [TS38.214 Table 4.1-1] it determines the ratio of PDSCH EPRE to DM-RS EPRE. Value: 1->3 + uint8_t numDmrsCdmGrpsNoData; + /// DMRS ports. [TS38.212 7.3.1.2.2] provides description between DCI 1-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used + uint16_t dmrsPorts; + // Pdsch Allocation in frequency domain [TS38.214, sec 5.1.2.2] + /// Resource Allocation Type [TS38.214, sec 5.1.2.2] 0: Type 0, 1: Type 1 + uint8_t resourceAlloc; + /// For resource alloc type 0. TS 38.212 V15.0.x, 7.3.1.2.2 bitmap of RBs, 273 rounded up to multiple of 32. This bitmap is in units of VRBs. LSB of byte 0 of the bitmap represents the first RB of the bwp + uint8_t rbBitmap[36]; + /// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The starting resource block within the BWP for this PDSCH. Value: 0->274 + uint16_t rbStart; + /// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The number of resource block within for this PDSCH. Value: 1->275 + uint16_t rbSize; + /// VRB-to-PRB-mapping [TS38.211, sec 7.3.1.6] 0: non-interleaved 1: interleaved with RB size 2 2: Interleaved with RB size 4 + uint8_t VRBtoPRBMapping; + // Resource Allocation in time domain [TS38.214, sec 5.1.2.1] + /// Start symbol index of PDSCH mapping from the start of the slot, S. [TS38.214, Table 5.1.2.1-1] Value: 0->13 + uint8_t StartSymbolIndex; + /// PDSCH duration in symbols, L [TS38.214, Table 5.1.2.1-1] Value: 1->14 + uint8_t NrOfSymbols; + // PTRS [TS38.214, sec 5.1.6.3] + /// PT-RS antenna ports [TS38.214, sec 5.1.6.3] [TS38.211, table 7.4.1.2.2-1] Bitmap occupying the 6 LSBs with: bit 0: antenna port 1000 bit 5: antenna port 1005 and for each bit 0: PTRS port not used 1: PTRS port used + uint8_t PTRSPortIndex ; + /// PT-RS time density [TS38.214, table 5.1.6.3-1] 0: 1 1: 2 2: 4 + uint8_t PTRSTimeDensity; + /// PT-RS frequency density [TS38.214, table 5.1.6.3-2] 0: 2 1: 4 + uint8_t PTRSFreqDensity; + /// PT-RS resource element offset [TS38.211, table 7.4.1.2.2-1] Value: 0->3 + uint8_t PTRSReOffset; + /// PT-RS-to-PDSCH EPRE ratio [TS38.214, table 4.1-2] Value :0->3 + uint8_t nEpreRatioOfPDSCHToPTRS; + // Beamforming + nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming; +}nfapi_nr_dl_tti_pdsch_pdu_rel15_t; -} nfapi_nr_pdcch_pdu_t; //for pdsch_pdu: - +/* typedef struct { uint16_t target_code_rate;// @@ -692,31 +848,32 @@ typedef struct uint32_t dl_tb_crc;//TB CRC: to be used in the last CB, applicable only if last CB is present } nfapi_nr_dlsch_pdu_t; +*/ //for csi-rs_pdu: //table 3-39 typedef struct { -uint16_t bwp_size;// -uint16_t bwp_start;// -uint8_t subcarrier_spacing;// -uint8_t cyclic_prefix;// -uint16_t start_rb; -uint16_t nr_of_rbs; -uint8_t csi_type;//Value: 0:TRS 1:CSI-RS NZP 2:CSI-RS ZP -uint8_t row;//Row entry into the CSI Resource location table. [TS38.211, sec 7.4.1.5.3 and table 7.4.1.5.3-1] Value: 1-18 -uint16_t freq_domain;//Value: Up to the 12 LSBs, actual size is determined by the Row parameter -uint8_t symb_l0;//The time domain location l0 and firstOFDMSymbolInTimeDomain Value: 0->13 -uint8_t symb_l1;// -uint8_t cdm_type; -uint8_t freq_density;//The density field, p and comb offset (for dot5).0: dot5 (even RB), 1: dot5 (odd RB), 2: one, 3: three -uint16_t scramb_id;//ScramblingID of the CSI-RS [TS38.214, sec 5.2.2.3.1] Value: 0->1023 -//tx power info -uint8_t power_control_offset;//Ratio of PDSCH EPRE to NZP CSI-RSEPRE Value :0->23 representing -8 to 15 dB in 1dB steps -uint8_t power_control_offset_ss;//Ratio of SSB/PBCH block EPRE to NZP CSI-RS EPRES 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB + uint16_t bwp_size;// + uint16_t bwp_start;// + uint8_t subcarrier_spacing;// + uint8_t cyclic_prefix;// + uint16_t start_rb; + uint16_t nr_of_rbs; + uint8_t csi_type;//Value: 0:TRS 1:CSI-RS NZP 2:CSI-RS ZP + uint8_t row;//Row entry into the CSI Resource location table. [TS38.211, sec 7.4.1.5.3 and table 7.4.1.5.3-1] Value: 1-18 + uint16_t freq_domain;//Value: Up to the 12 LSBs, actual size is determined by the Row parameter + uint8_t symb_l0;//The time domain location l0 and firstOFDMSymbolInTimeDomain Value: 0->13 + uint8_t symb_l1;// + uint8_t cdm_type; + uint8_t freq_density;//The density field, p and comb offset (for dot5).0: dot5 (even RB), 1: dot5 (odd RB), 2: one, 3: three + uint16_t scramb_id;//ScramblingID of the CSI-RS [TS38.214, sec 5.2.2.3.1] Value: 0->1023 + //tx power info + uint8_t power_control_offset;//Ratio of PDSCH EPRE to NZP CSI-RSEPRE Value :0->23 representing -8 to 15 dB in 1dB steps + uint8_t power_control_offset_ss;//Ratio of SSB/PBCH block EPRE to NZP CSI-RS EPRES 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB -} nfapi_nr_csi_rs_pdu_t; +} nfapi_nr_dl_tti_csi_rs_pdu_rel15_t; //for ssb_pdu: @@ -743,27 +900,85 @@ typedef struct } nfapi_nr_bch_payload_t; -typedef struct -{ - uint16_t phys_cell_id;//0~1007 - uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block 0 = 0dB 1 = 3dB - uint8_t ssb_block_index;//SS/PBCH block index within a SSB burst set. Required for PBCH DMRS scrambling. Value: 0->63 (Lmax) - uint8_t ssb_subcarrier_offset;// - uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Value: 0->2199 - uint8_t bch_payload_flag;//A value indicating how the BCH payload is generated. This should match the PARAM/CONFIG TLVs. Value: 0: MAC generates the full PBCH payload, see Table 3-41, where bchPayload has 31 bits 1: PHY generates the timing PBCH bits, see Table 3-41, where the bchPayload has 24 bits 2: PHY generates the full PBCH payload - nfapi_nr_bch_payload_t bch_payload; +typedef struct { + /// Physical Cell ID Value 0~>1007 + uint16_t PhysCellId; + ///PSS EPRE to SSS EPRE in a SS/PBCH block 0 = 0dB 1 = 3dB + uint8_t BetaPss; + ///SS/PBCH block index within a SSB burst set. Required for PBCH DMRS scrambling. Value: 0->63 (Lmax) + uint8_t SsbBlockIndex; + /// ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (TS38.211, section 7.4.3.1) Value: 0->31 + uint8_t SsbSubcarrierOffset; + ///Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Value: 0->2199 + uint16_t ssbOffsetPointA; + /// A value indicating how the BCH payload is generated. This should match the PARAM/CONFIG TLVs. Value: 0: MAC generates the full PBCH payload, see Table 3-41, where bchPayload has 31 bits 1: PHY generates the timing PBCH bits, see Table 3-41, where the bchPayload has 24 bits 2: PHY generates the full PBCH payload + uint8_t bchPayloadFlag; + uint32_t bchPayload; nfapi_nr_tx_precoding_and_beamforming_t precoding_and_beamforming; +} nfapi_nr_dl_tti_ssb_pdu_rel15_t; -} nfapi_nr_ssb_pdu_t; +typedef struct { + nfapi_nr_dl_tti_ssb_pdu_rel15_t ssb_pdu_rel15; +} nfapi_nr_dl_tti_ssb_pdu; +typedef struct { + nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_rs_pdu_rel15; +} nfapi_nr_dl_tti_csi_rs_pdu; + +typedef struct { + nfapi_nr_dl_tti_pdsch_pdu_rel15_t pdsch_pdu_rel15; +} nfapi_nr_dl_tti_pdsch_pdu; + +typedef struct { + nfapi_nr_dl_tti_pdcch_pdu_rel15_t pdcch_pdu_rel15; +} nfapi_nr_dl_tti_pdcch_pdu; + +typedef struct { + uint16_t PDUType; + uint16_t PDUSize; + + union { + nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu; + nfapi_nr_dl_tti_pdsch_pdu pdsch_pdu; + nfapi_nr_dl_tti_csi_rs_pdu csi_rs_pdu; + nfapi_nr_dl_tti_ssb_pdu ssb_pdu; + }; +} nfapi_nr_dl_tti_request_pdu_t; + +#define NFAPI_NR_MAX_DL_TTI_PDUS 32 +typedef struct { + /// Number of PDUs that are included in this message. All PDUs in the message are numbered in order. Value 0 -> 255 + uint8_t nPDUs; + /// Number of UEs in the Group included in this message. Value 0 -> 255 + uint8_t nGroup; + /// List containing PDUs + nfapi_nr_dl_tti_request_pdu_t dl_tti_pdu_list[NFAPI_NR_MAX_DL_TTI_PDUS]; + /// Number of UE in this group. For SU-MIMO, one group includes one UE only. For MU-MIMO, one group includes up to 12 UEs. Value 1 -> 12 + uint8_t nUe[256]; + /// This value is an index for number of PDU identified by nPDU in this message Value: 0 -> 255 + uint8_t PduIdx[256][12]; +} nfapi_nr_dl_tti_request_body_t; + +typedef struct { + nfapi_p7_message_header_t header; + /// System Frame Number (0-1023) + uint16_t SFN; + /// Slot number (0-319) + uint16_t Slot; + nfapi_nr_dl_tti_request_body_t dl_tti_request_body; + nfapi_vendor_extension_tlv_t vendor_extension; +} nfapi_nr_dl_tti_request_t; + +/* typedef struct { - nfapi_nr_pdcch_pdu_t* pdcch_pdu; - nfapi_nr_dlsch_pdu_t* dlsch_pdu;//pdsch_pdu; - nfapi_nr_csi_rs_pdu_t* csi_rs_pdu; - nfapi_nr_ssb_pdu_t* ssb_pdu; + nfapi_nr_dl_tti_pdcch_pdu* pdcch_pdu; + nfapi_nr_dl_tti_pdsch_pdu* pdsch_pdu; + nfapi_nr_dl_tti_csi_rs_pdu_t* csi_rs_pdu; + nfapi_nr_dl_tti_ssb_pdu_t* ssb_pdu; } nfapi_nr_dl_pdu_configuration_t; - +*/ + /* typedef struct { uint16_t pdu_type;//0: PDCCH PDU 1: PDSCH PDU 2: CSI-RS PDU 3: SSB PDU, @@ -771,6 +986,7 @@ typedef struct nfapi_nr_dl_pdu_configuration_t* dl_pdu_configuration; } nfapi_nr_dl_tti_request_number_of_pdus_t; + typedef struct { @@ -795,9 +1011,10 @@ typedef struct { nfapi_nr_dl_tti_request_number_of_groups_t* groups_list; } nfapi_nr_dl_tti_request_t; +*/ // Section 3.4.3 ul_tti_request - + //for prach_pdu: typedef struct { @@ -905,10 +1122,10 @@ typedef struct uint16_t data_scrambling_id; uint8_t nrOfLayers; //DMRS - uint8_t ul_dmrs_symb_pos; + uint16_t ul_dmrs_symb_pos; uint8_t dmrs_config_type; uint16_t ul_dmrs_scrambling_id; - uint8_t scid;// + uint8_t scid; uint8_t num_dmrs_cdm_grps_no_data; uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] @@ -1015,6 +1232,13 @@ typedef struct // +typedef enum { + NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE = 0, + NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE = 1, + NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE = 2, + NFAPI_NR_DL_TTI_SSB_PDU_TYPE = 3, +} nfapi_nr_dl_tti_pdu_type_e; + typedef enum { NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE=0, NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE, @@ -1050,8 +1274,8 @@ typedef struct } nfapi_nr_ul_tti_request_number_of_groups_t; typedef struct { - uint16_t sfn; //0->1023 - uint16_t slot;//0->319 + uint16_t SFN; //0->1023 + uint16_t Slot;//0->319 uint8_t n_pdus;//Number of PDUs that are included in this message. All PDUs in the message are numbered in order. Value 0 -> 255 uint8_t rach_present;//Indicates if a RACH PDU will be included in this message. 0: no RACH in this slot 1: RACH in this slot uint8_t n_ulsch;//Number of ULSCH PDUs that are included in this message. @@ -1059,13 +1283,13 @@ typedef struct { uint8_t n_group;//Number of UE Groups included in this message. Value 0 -> 8 nfapi_nr_ul_tti_request_number_of_pdus_t pdus_list[NFAPI_MAX_NUM_UL_PDU]; nfapi_nr_ul_tti_request_number_of_groups_t groups_list[NFAPI_MAX_NUM_GROUPS]; - } nfapi_nr_ul_tti_request_t; //3.4.4 ul_dci_request //table 3-54 +/* typedef struct { uint16_t pdu_type;//0: PDCCH PDU @@ -1082,6 +1306,25 @@ typedef struct nfapi_nr_ul_dci_request_number_of_pdus_t* pdu_list; } nfapi_nr_ul_dci_request_t; +*/ + + // normally one PDU per coreset per BWP +#define NFAPI_NR_MAX_UL_DCI_PDUS 4 + +typedef struct { + /// only possible value 0: PDCCH PDU + uint16_t PDUType; + ///Size of the PDU control information (in bytes). This length value includes the 4 bytes required for the PDU type and PDU size parameters. Value 0 -> 65535 + uint16_t PDUSize; + nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu; +} nfapi_nr_ul_dci_request_pdus_t; + +typedef struct { + uint16_t SFN; + uint16_t Slot; + uint8_t numPdus; + nfapi_nr_ul_dci_request_pdus_t ul_dci_pdu_list[NFAPI_NR_MAX_UL_DCI_PDUS]; +} nfapi_nr_ul_dci_request_t; //3.4.5 slot_errors typedef enum { @@ -1098,6 +1341,7 @@ typedef enum { } nfapi_nr_slot_errors_dl_tti_e; + typedef enum { NFAPI_NR_SLOT_UL_DCI_MSG_INVALID_STATE, NFAPI_NR_SLOT_UL_DCI_MSG_INVALID_SFN, @@ -1108,23 +1352,23 @@ typedef enum { //3.4.6 tx_data_request //table 3-58 - +#define NFAPI_NR_MAX_TX_REQUEST_TLV 2 typedef struct { - uint16_t pdu_length; - uint16_t pdu_index; - uint32_t num_tlv; - //! fixme - nfapi_int32_tlv_t* tlvs; //nfapi_int32_tlv_t tlvs[num_tlv] + uint16_t PDU_length; + uint16_t PDU_index; + uint32_t num_TLV; + nfapi_nr_tx_data_request_tlv_t TLVs[NFAPI_NR_MAX_TX_REQUEST_TLV]; } nfapi_nr_pdu_t; +#define NFAPI_NR_MAX_TX_REQUEST_PDUS 16 typedef struct { - uint16_t sfn; - uint16_t slot; - uint16_t number_of_pdus; - nfapi_nr_pdu_t* pdu_list; + uint16_t SFN; + uint16_t Slot; + uint16_t Number_of_PDUs; + nfapi_nr_pdu_t pdu_list[NFAPI_NR_MAX_TX_REQUEST_PDUS]; } nfapi_nr_tx_data_request_t; diff --git a/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h b/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h index 5d463afdae..5abf6b75c3 100644 --- a/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h +++ b/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h @@ -18,7 +18,8 @@ #define _NFAPI_VNF_INTERFACE_H_ #include "nfapi_interface.h" -#include "nfapi_nr_interface.h" +#include "nfapi_nr_interface_scf.h" + #include "debug.h" #include "netinet/in.h" @@ -938,7 +939,7 @@ int nfapi_vnf_p7_del_pnf(nfapi_vnf_p7_config_t* config, int phy_id); * may be released after this function call has returned or at a later pointer */ int nfapi_vnf_p7_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_dl_config_request_t* req); -int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_config_request_t* req); +int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_tti_request_t* req); /*! Send the UL_CONFIG.request * \param config A pointer to the vnf p7 configuration diff --git a/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c b/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c index 8b60122483..35bd5e4c1b 100644 --- a/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c +++ b/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c @@ -482,7 +482,7 @@ int nfapi_vnf_p7_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_dl_config_re return vnf_p7_pack_and_send_p7_msg(vnf_p7, &req->header); } -int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_config_request_t* req) +int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_tti_request_t* req) { //NFAPI_TRACE(NFAPI_TRACE_INFO, "%s(config:%p req:%p)\n", __FUNCTION__, config, req); diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index 3d3e920216..732cc75d6c 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -18,6 +18,17 @@ * For more information about the OpenAirInterface (OAI) Software Alliance: * contact@openairinterface.org */ +// add GPU mode (-G 1) + + /*! \file PHY/CODING/TESTBENCH/ldpctest.c + * \brief Merge remote-tracking branch 'origin/develop' into NCTU_OpinConnect_LDPC + * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ #include #include @@ -104,7 +115,8 @@ int test_ldpc(short No_iteration, unsigned int *crc_misses, time_stats_t *time_optim, time_stats_t *time_decoder, - n_iter_stats_t *dec_iter) + n_iter_stats_t *dec_iter, + short run_cuda) { //clock initiate //time_stats_t time,time_optim,tinput,tprep,tparity,toutput, time_decoder; @@ -401,15 +413,21 @@ int test_ldpc(short No_iteration, // decoder supports BG2, Z=128 & 256 //esimated_output=ldpc_decoder(channel_output_fixed, block_length, No_iteration, (double)((float)nom_rate/(float)denom_rate)); ///nrLDPC_decoder(&decParams, channel_output_fixed, estimated_output, NULL); -#ifdef __NR_LDPC_DECODER_LYC__H__ +//#ifdef __NR_LDPC_DECODER_LYC__H__RUN__ + if(run_cuda){ + printf("run ldpc by cuda\n"); start_meas(time_decoder); n_iter = nrLDPC_decoder_LYC(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length, time_decoder); stop_meas(time_decoder); -#else + } +//#else + else{ + printf("run ldpc by cpu\n"); start_meas(time_decoder); n_iter = nrLDPC_decoder(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], p_nrLDPC_procBuf, p_decoder_profiler); stop_meas(time_decoder); -#endif + } +//#endif } //for (i=(Kb+nrows) * Zc-5;i<(Kb+nrows) * Zc;i++) @@ -512,7 +530,7 @@ int main(int argc, char *argv[]) unsigned int errors, errors_bit, crc_misses; double errors_bit_uncoded; short block_length=8448; // decoder supports length: 1201 -> 1280, 2401 -> 2560 - + short run_cuda = 0; short No_iteration=5; int n_segments=1; //double rate=0.333; @@ -534,7 +552,7 @@ int main(int argc, char *argv[]) short BG=0,Zc,Kb; - while ((c = getopt (argc, argv, "q:r:s:S:l:n:d:i:t:u:h")) != -1) + while ((c = getopt (argc, argv, "q:r:s:S:l:n:d:i:t:u:h:G:")) != -1) switch (c) { case 'q': @@ -544,7 +562,10 @@ int main(int argc, char *argv[]) case 'r': nom_rate = atoi(optarg); break; - + case 'G': + run_cuda = atoi(optarg); + break; + case 'd': denom_rate = atoi(optarg); break; @@ -576,6 +597,7 @@ int main(int argc, char *argv[]) case 'u': test_uncoded = atoi(optarg); break; + case 'h': default: @@ -594,6 +616,7 @@ int main(int argc, char *argv[]) printf("-t SNR simulation step, Default: 0.1\n"); printf("-i Max decoder iterations, Default: 5\n"); printf("-u Set SNR per coded bit, Default: 0\n"); + printf("-G set 1 to run cuda for ldpc \n"); exit(1); break; } @@ -603,7 +626,7 @@ int main(int argc, char *argv[]) printf("block length %d: \n", block_length); printf("n_trials %d: \n", n_trials); printf("SNR0 %f: \n", SNR0); - + @@ -677,7 +700,8 @@ int main(int argc, char *argv[]) &crc_misses, time_optim, time_decoder, - dec_iter); + dec_iter, + run_cuda); printf("SNR %f, BLER %f (%u/%d)\n", SNR, (float)decoded_errors[i]/(float)n_trials, decoded_errors[i], n_trials); printf("SNR %f, BER %f (%u/%d)\n", SNR, (float)errors_bit/(float)n_trials/(float)block_length/(double)n_segments, decoded_errors[i], n_trials); diff --git a/openair1/PHY/CODING/TESTBENCH/polartest.c b/openair1/PHY/CODING/TESTBENCH/polartest.c index 7fcaa0646c..806d8de28c 100644 --- a/openair1/PHY/CODING/TESTBENCH/polartest.c +++ b/openair1/PHY/CODING/TESTBENCH/polartest.c @@ -175,7 +175,7 @@ if (logFlag){ double channelOutput[coderLength]; //add noise int16_t channelOutput_int16[coderLength]; - t_nrPolar_params *currentPtr = nr_polar_params(polarMessageType, testLength, aggregation_level); + t_nrPolar_params *currentPtr = nr_polar_params(polarMessageType, testLength, aggregation_level, 1, NULL); #ifdef DEBUG_DCI_POLAR_PARAMS uint32_t dci_pdu[4]; diff --git a/openair1/PHY/CODING/coding_defs.h b/openair1/PHY/CODING/coding_defs.h index 540fd3b263..9b111309cd 100644 --- a/openair1/PHY/CODING/coding_defs.h +++ b/openair1/PHY/CODING/coding_defs.h @@ -481,6 +481,8 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, uint8_t *w, uint8_t *e, uint8_t C, + uint32_t F, + uint32_t Foffset, uint8_t rvidx, uint32_t E); @@ -493,7 +495,9 @@ int nr_rate_matching_ldpc_rx(uint8_t Ilbrm, uint8_t C, uint8_t rvidx, uint8_t clear, - uint32_t E); + uint32_t E, + uint32_t F, + uint32_t Foffset); decoder_if_t phy_threegpplte_turbo_decoder; decoder_if_t phy_threegpplte_turbo_decoder8; diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_cnProc.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_cnProc.h index a3d829883d..db9d6e4119 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_cnProc.h +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_cnProc.h @@ -88,23 +88,29 @@ static inline void nrLDPC_cnProc_BG2(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf* p_pr // Set of results pointer to correct BN address p_cnProcBufResBit = p_cnProcBufRes + (j*bitOffsetInGroup); + __m256i *pj0 = &p_cnProcBuf[lut_idxCnProcG3[j][0]]; + __m256i *pj1 = &p_cnProcBuf[lut_idxCnProcG3[j][1]]; + // Loop over CNs for (i=0; i #include -#include "nrLDPC_defs.h" +#include "nrLDPCdecoder_defs.h" #include "nrLDPC_types.h" #include "nrLDPC_init.h" #include "nrLDPC_mPass.h" @@ -39,7 +39,7 @@ #include "nrLDPC_bnProc.h" #define NR_LDPC_ENABLE_PARITY_CHECK -//#define NR_LDPC_PROFILER_DETAIL +#define NR_LDPC_PROFILER_DETAIL #ifdef NR_LDPC_DEBUG_MODE #include "nrLDPC_tools/nrLDPC_debug.h" @@ -47,7 +47,7 @@ static inline uint32_t nrLDPC_decoder_core(int8_t* p_llr, int8_t* p_out, t_nrLDPC_procBuf* p_procBuf, uint32_t numLLR, t_nrLDPC_lut* p_lut, t_nrLDPC_dec_params* p_decParams, t_nrLDPC_time_stats* p_profiler); -int32_t nrLDPC_decoder(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, t_nrLDPC_procBuf* p_procBuf, t_nrLDPC_time_stats* p_profiler) +int32_t nrLDPC_decod(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, t_nrLDPC_procBuf* p_procBuf, t_nrLDPC_time_stats* p_profiler) { uint32_t numLLR; uint32_t numIter = 0; diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h deleted file mode 100644 index 4d2401db83..0000000000 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*!\file nrLDPC_decoder.h - * \brief Defines the LDPC decoder core prototypes - * \author Sebastian Wagner (TCL Communications) Email: - * \date 27-03-2018 - * \version 1.0 - * \note - * \warning - */ - -#ifndef __NR_LDPC_DECODER__H__ -#define __NR_LDPC_DECODER__H__ - -#include "nrLDPC_types.h" -#include "nrLDPC_init_mem.h" - -/** - \brief LDPC decoder - \param p_decParams LDPC decoder parameters - \param p_llr Input LLRs - \param p_llrOut Output vector - \param p_profiler LDPC profiler statistics -*/ -int32_t nrLDPC_decoder(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_llrOut, t_nrLDPC_procBuf* p_procBuf, t_nrLDPC_time_stats* p_profiler); - -#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_defs.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_defs.h deleted file mode 100644 index 940d842550..0000000000 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_defs.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*!\file nrLDPC_defs.h - * \brief Defines all constants and buffers for the LDPC decoder - * \author Sebastian Wagner (TCL Communications) Email: - * \date 27-03-2018 - * \version 1.0 - * \note - * \warning - */ - -#ifndef __NR_LDPC_DEFS__H__ -#define __NR_LDPC_DEFS__H__ - -// ============================================================================== -// DEFINES - -/** Maximum lifting size */ -#define NR_LDPC_ZMAX 384 - -/** Number of columns in BG1 */ -#define NR_LDPC_NCOL_BG1 68 -/** Number of rows in BG1 */ -#define NR_LDPC_NROW_BG1 46 -/** Number of edges/entries in BG1 */ -#define NR_LDPC_NUM_EDGE_BG1 316 -/** Number of check node (CN) groups in BG1 - A CN group is defined by its number of connected bit nodes. */ -#define NR_LDPC_NUM_CN_GROUPS_BG1 9 -/** First column in BG1 that is connected to only a single CN */ -#define NR_LDPC_START_COL_PARITY_BG1 26 - -/** Number of columns in BG1 for rate 1/3 = 22/(68-2) */ -#define NR_LDPC_NCOL_BG1_R13 NR_LDPC_NCOL_BG1 -/** Number of columns in BG1 for rate 2/3 = 22/(35-2) */ -#define NR_LDPC_NCOL_BG1_R23 35 -/** Number of columns in BG1 for rate 8/9 ~ 22/(27-2) */ -#define NR_LDPC_NCOL_BG1_R89 27 - -/** Number of bit node (BN) groups in BG1 for rate 1/3 - A BN group is defined by its number of connected CNs. */ -#define NR_LDPC_NUM_BN_GROUPS_BG1_R13 30 -/** Number of bit node (BN) groups in BG1 for rate 2/3 */ -#define NR_LDPC_NUM_BN_GROUPS_BG1_R23 8 -/** Number of bit node (BN) groups in BG1 for rate 8/9 */ -#define NR_LDPC_NUM_BN_GROUPS_BG1_R89 5 - -/** Number of columns in BG2 */ -#define NR_LDPC_NCOL_BG2 52 -/** Number of rows in BG2 */ -#define NR_LDPC_NROW_BG2 42 -/** Number of edges/entries in BG2 */ -#define NR_LDPC_NUM_EDGE_BG2 197 -/** Number of check node (CN) groups in BG2 - A CN group is defined by its number of connected bit nodes. */ -#define NR_LDPC_NUM_CN_GROUPS_BG2 6 -/** First column in BG2 that is connected to only a single CN */ -#define NR_LDPC_START_COL_PARITY_BG2 14 - -/** Number of columns in BG2 for rate 1/5 = 10/(52-2) */ -#define NR_LDPC_NCOL_BG2_R15 NR_LDPC_NCOL_BG2 -/** Number of columns in BG2 for rate 1/3 = 10/(32-2) */ -#define NR_LDPC_NCOL_BG2_R13 32 -/** Number of columns in BG2 for rate 2/3 = 10/(17-2) */ -#define NR_LDPC_NCOL_BG2_R23 17 - -/** Number of bit node (BN) groups in BG2 for rate 1/5 - A BN group is defined by its number of connected CNs. */ -#define NR_LDPC_NUM_BN_GROUPS_BG2_R15 23 -/** Number of bit node (BN) groups in BG2 for rate 1/3 */ -#define NR_LDPC_NUM_BN_GROUPS_BG2_R13 10 -/** Number of bit node (BN) groups in BG2 for rate 2/3 */ -#define NR_LDPC_NUM_BN_GROUPS_BG2_R23 6 - -/** Worst case size of the CN processing buffer */ -#define NR_LDPC_SIZE_CN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX -/** Worst case size of the BN processing buffer */ -#define NR_LDPC_SIZE_BN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX - -/** Maximum number of possible input LLR = NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX */ -#define NR_LDPC_MAX_NUM_LLR 26112 - -// ============================================================================== -// GLOBAL CONSTANT VARIABLES - -/** Start addresses for the cnProcBuf for each CN group in BG1*/ -static const uint32_t lut_startAddrCnGroups_BG1[NR_LDPC_NUM_CN_GROUPS_BG1] = {0, 1152, 8832, 43392, 61824, 75264, 81408, 88320, 92160}; -/** Start addresses for the cnProcBuf for each CN group in BG2*/ -static const uint32_t lut_startAddrCnGroups_BG2[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 6912, 37632, 54912, 61824, 67968}; - -/** Number of BNs of CN group for BG1. - E.g. 10 means that there is a CN group where every CN is connected to 10 BNs */ -static const uint8_t lut_numBnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {3, 4, 5, 6, 7, 8, 9, 10, 19}; -/** Number of rows/CNs in every CN group for rate = 1/3 BG1, e.g. 5 rows of CNs connected to 4 BNs */ -static const uint8_t lut_numCnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 5, 18, 8, 5, 2, 2, 1, 4}; -/** Number of rows/CNs in every CN group for rate = 2/3 BG1, e.g. 3 rows of CNs connected to 7 BNs */ -static const uint8_t lut_numCnInCnGroups_BG1_R23[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 3, 2, 2, 1, 4}; -/** Number of rows/CNs in every CN group for rate = 8/9 BG1, e.g. 4 rows of CNs connected to 19 BNs */ -static const uint8_t lut_numCnInCnGroups_BG1_R89[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 0, 0, 0, 0, 4}; - -/** Number of connected BNs for every column in BG1 rate = 1/3, e.g. in first column all BNs are connected to 30 CNs */ -static const uint8_t lut_numEdgesPerBn_BG1_R13[NR_LDPC_START_COL_PARITY_BG1] = {30, 28, 7, 11, 9, 4, 8, 12, 8, 7, 12, 10, 12, 11, 10, 7, 10, 10, 13, 7, 8, 11, 12, 5, 6, 6}; -/** Number of connected BNs for every column in BG1 rate = 2/3, e.g. in first column all BNs are connected to 12 CNs */ -static const uint8_t lut_numEdgesPerBn_BG1_R23[NR_LDPC_START_COL_PARITY_BG1] = {12, 11, 4, 5, 5, 3, 4, 5, 5, 3, 6, 6, 6, 6, 5, 3, 6, 5, 6, 4, 5, 6, 6, 3, 3, 2}; -/** Number of connected BNs for every column in BG1 rate = 8/9, e.g. in first column all BNs are connected to 5 CNs */ -static const uint8_t lut_numEdgesPerBn_BG1_R89[NR_LDPC_START_COL_PARITY_BG1] = {5, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2}; - -/** Number of BNs of CN group for BG2. - E.g. 3 means that there is a CN group where every CN is connected to 3 BNs */ -static const uint8_t lut_numBnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {3, 4, 5, 6, 8, 10}; -/** Number of rows/CNs in every CN group for rate = 1/5 BG2, e.g. 6 rows of CNs connected to 3 BNs */ -static const uint8_t lut_numCnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {6, 20, 9, 3, 2, 2}; -/** Number of rows/CNs in every CN group for rate = 1/3 BG2, e.g. 8 rows of CNs connected to 4 BNs */ -static const uint8_t lut_numCnInCnGroups_BG2_R13[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 8, 7, 3, 2, 2}; -/** Number of rows/CNs in every CN group for rate = 2/3 BG2, e.g. 1 row of CNs connected to 4 BNs */ -static const uint8_t lut_numCnInCnGroups_BG2_R23[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 1, 0, 2, 2, 2}; - -/** Number of connected BNs for every column in BG2 rate = 1/5, e.g. in first column all BNs are connected to 22 CNs */ -static const uint8_t lut_numEdgesPerBn_BG2_R15[NR_LDPC_START_COL_PARITY_BG2] = {22, 23, 10, 5, 5, 14, 7, 13, 6, 8, 9, 16, 9, 12}; -/** Number of connected BNs for every column in BG2 rate = 1/3, e.g. in first column all BNs are connected to 14 CNs */ -static const uint8_t lut_numEdgesPerBn_BG2_R13[NR_LDPC_START_COL_PARITY_BG2] = {14, 16, 2, 4, 4, 6, 6, 8, 6, 6, 6, 13, 5, 7}; -/** Number of connected BNs for every column in BG2 rate = 2/3, e.g. in first column all BNs are connected to 6 CNs */ -static const uint8_t lut_numEdgesPerBn_BG2_R23[NR_LDPC_START_COL_PARITY_BG2] = { 6, 5, 2, 3, 3, 4, 3, 4, 3, 4, 3, 5, 2, 2}; - -// Number of groups for bit node processing -/** Number of connected CNs for every column/BN in BG1 for rate = 1/3, Worst case is BG1 with up to 30 CNs connected to one BN - E.g. 42 parity BNs connected to single CN */ - // BG1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 -static const uint8_t lut_numBnInBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {42, 0, 0, 1, 1, 2, 4, 3, 1, 4, 3, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}; -/** Number of connected CNs for every column/BN in BG1 for rate = 2/3 */ -static const uint8_t lut_numBnInBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 9, 1, 5, 3, 7, 8, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -/** Number of connected CNs for every column/BN in BG1 for rate = 8/9 */ -static const uint8_t lut_numBnInBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 1, 3,21, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -/** Number of connected CNs for every column/BN in BG2 for rate = 1/5, Worst case is BG1 with up to 30 CNs connected to one BN - E.g. 38 parity BNs connected to single CN */ - // BG2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 -static const uint8_t lut_numBnInBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {38, 0, 0, 0, 2, 1, 1, 1, 2, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0}; -/** Number of connected CNs for every column/BN in BG2 for rate = 1/3 */ -static const uint8_t lut_numBnInBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {18, 1, 0, 2, 1, 5, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -/** Number of connected CNs for every column/BN in BG2 for rate = 2/3 */ -static const uint8_t lut_numBnInBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 3, 3, 5, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -// Start addresses for the bnProcBuf for each BN group -// BG1 -/** Start address for every BN group within the BN processing buffer for BG1 rate = 1/3 */ -static const uint32_t lut_startAddrBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 17664, 19584, 24192, 34944, 44160, 47616, 62976, 75648, 94080, 99072, 109824}; -/** Start address for every BN group within the BN processing buffer for BG1 rate = 2/3 */ -static const uint32_t lut_startAddrBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 4224, 9984, 14592, 28032, 46464, 50688}; -/** Start address for every BN group within the BN processing buffer for BG1 rate = 8/9 */ -static const uint32_t lut_startAddrBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 2688, 26880, 28416}; - -/** Start address for every BN group within the LLR processing buffer for BG1 rate = 1/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 16512, 16896, 17664, 19200, 20352, 20736, 22272, 23424, 24960, 25344, 25728}; -/** Start address for every BN group within the LLR processing buffer for BG1 rate = 2/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 3840, 5760, 6912, 9600, 12672, 13056}; -/** Start address for every BN group within the LLR processing buffer for BG1 rate = 8/9 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 1536, 9600, 9984}; - -// BG2 -/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/5 */ -static const uint32_t lut_startAddrBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 18432, 20736, 23424, 26496, 33408, 37248, 41856, 46848, 52224, 58368, 66816}; -/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/3 */ -static const uint32_t lut_startAddrBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7680, 10752, 12672, 24192, 26880, 29952, 34944, 40320}; -/** Start address for every BN group within the BN processing buffer for BG2 rate = 2/3 */ -static const uint32_t lut_startAddrBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 3456, 9216, 13824, 17664}; - -/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/5 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 15360, 15744, 16128, 16512, 17280, 17664, 18048, 18432, 18816, 19200, 19584}; -/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7296, 8064, 8448, 10368, 10752, 11136, 11520, 11904}; -/** Start address for every BN group within the LLR processing buffer for BG2 rate = 2/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 2304, 4224, 5376, 6144}; - -/** Vector of 32 '1' in int8 for application with AVX2 */ -static const int8_t ones256_epi8[32] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; -/** Vector of 32 '0' in int8 for application with AVX2 */ -static const int8_t zeros256_epi8[32] __attribute__ ((aligned(32))) = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; -/** Vector of 32 '127' in int8 for application with AVX2 */ -static const int8_t maxLLR256_epi8[32] __attribute__ ((aligned(32))) = {127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127}; - -#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init.h index 82462c6d95..ea031dc2da 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init.h +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init.h @@ -32,7 +32,7 @@ #define __NR_LDPC_INIT__H__ #include "nrLDPC_lut.h" -#include "nrLDPC_defs.h" +#include "nrLDPCdecoder_defs.h" /** \brief Initializes the decoder and sets correct LUTs diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h index bdaa118e1f..3292c0debe 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_init_mem.h @@ -32,7 +32,6 @@ #define __NR_LDPC_INIT_MEM__H__ #include -#include "nrLDPC_defs.h" #include "nrLDPC_types.h" #ifndef malloc32_clear diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h index 66715618d0..10b45ac0e7 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h @@ -32,7 +32,7 @@ #define __NR_LDPC_MPASS__H__ #include -#include "nrLDPC_defs.h" +#include "nrLDPCdecoder_defs.h" /** \brief Circular memcpy @@ -521,7 +521,6 @@ static inline void nrLDPC_cn2bnProcBuf_BG2(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf for (j=0; j<3; j++) { p_cnProcBufRes = &cnProcBufRes[lut_startAddrCnGroups[0] + j*bitOffsetInGroup]; - for (i=0; i #include #include diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h index c9eb785595..5602ccecdd 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h @@ -4,23 +4,13 @@ #include "nrLDPC_types.h" #include "nrLDPC_init_mem.h" -/*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h - * \brief LDPC implementation on Quadro p5000 by NCTU OpinCommect - * \author NCTU OpinConnect Terng-Yin Hsu/Yu-Chi Liang/Kai-Tai Yang/Yan-Bo Lin - * \email tyhsu@cs.nctu.edu.tw - * \date 13-05-2020 - * \version - * \note - * \warning - */ - -/** +/*** \brief LDPC decoder \param p_decParams LDPC decoder parameters \param p_llr Input LLRs \param p_llrOut Output vector \param p_profiler LDPC profiler statistics -*/ +****/ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder); diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h index 541ab25ea6..de17d8be07 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h @@ -19,16 +19,6 @@ * contact@openairinterface.org */ -/*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h - * \brief LDPC implementation on Quadro p5000 by NCTU OpinCommect - * \author NCTU OpinConnect Terng-Yin Hsu/Yu-Chi Liang/Kai-Tai Yang/Yan-Bo Lin - * \email tyhsu@cs.nctu.edu.tw - * \date 13-05-2020 - * \version - * \note - * \warning - */ - /*!\file nrLDPC_defs.h * \brief Defines all constants and buffers for the LDPC decoder * \author Sebastian Wagner (TCL Communications) Email: @@ -36,7 +26,7 @@ * \version 1.0 * \note * \warning - */ +* */ #ifndef __NR_LDPC_DEFS__H__ #define __NR_LDPC_DEFS__H__ diff --git a/openair1/PHY/CODING/nrLDPC_encoder/defs.h b/openair1/PHY/CODING/nrLDPC_encoder/defs.h deleted file mode 100644 index 85cb852fe5..0000000000 --- a/openair1/PHY/CODING/nrLDPC_encoder/defs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*!\file defs.h - * \brief LDPC encoder forward declarations - * \author Florian Kaltenberger, Raymond Knopp, Kien le Trung (Eurecom) - * \email openair_tech@eurecom.fr - * \date 27-03-2018 - * \version 1.0 - * \note - * \warning - */ - -#include "PHY/TOOLS/time_meas.h" - -/*ldpc_encoder.c*/ -int encode_parity_check_part_orig(unsigned char *c,unsigned char *d, short BG,short Zc,short Kb,short block_length); - -/*ldpc_encoder2.c*/ -void encode_parity_check_part_optim(uint8_t *c,uint8_t *d, short BG,short Zc,short Kb); -int ldpc_encoder_optim(unsigned char *test_input,unsigned char *channel_input,int Zc,int Kb,short block_length,short BG,time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput); -int ldpc_encoder_optim_8seg(unsigned char **test_input,unsigned char **channel_input,int Zc,int Kb,short block_length,short BG,int n_segments,time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput); -int ldpc_encoder_optim_8seg_multi(unsigned char **test_input,unsigned char **channel_input,int Zc,int Kb,short block_length, short BG, int n_segments,unsigned int macro_num, time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput); - -/*ldpc_generate_coefficient.c*/ -int ldpc_encoder_orig(unsigned char *test_input,unsigned char *channel_input,int Zc,int Kb,short block_length,short BG,unsigned char gen_code); - -/* -int encode_parity_check_part(unsigned char *c,unsigned char *d, short BG,short Zc,short Kb); -int encode_parity_check_part_orig(unsigned char *c,unsigned char *d, short BG,short Zc,short Kb,short block_length); -int ldpc_encoder(unsigned char *test_input,unsigned char *channel_input,short block_length, double rate); -int ldpc_encoder_orig(unsigned char *test_input,unsigned char *channel_input,short block_length,int nom_rate,int denom_rate,unsigned char gen_code); -int ldpc_encoder_multi_segment(unsigned char **test_input,unsigned char **channel_input,short block_length,double rate,uint8_t n_segments); -int ldpc_encoder_optim(unsigned char *test_input,unsigned char *channel_input,short block_length,int nom_rate,int denom_rate,time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput); -int ldpc_encoder_optim_8seg(unsigned char **test_input,unsigned char **channel_input,short block_length,int nom_rate,int denom_rate,int n_segments,time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput); -*/ diff --git a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c index 6ded22d8ca..76f92574ba 100644 --- a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c +++ b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c @@ -37,77 +37,247 @@ #include #include #include "defs.h" +#include "assertions.h" +#include "openair1/PHY/CODING/nrLDPC_defs.h" +#include "ldpc_generate_coefficient.c" -short *choose_generator_matrix(short BG,short Zc); -extern short no_shift_values_BG1[1012],pointer_shift_values_BG1[1012],no_shift_values_BG2[2109],pointer_shift_values_BG2[2019]; -int encode_parity_check_part_orig(unsigned char *c,unsigned char *d, short BG,short Zc,short Kb,short block_length) +int ldpc_encoder_orig(unsigned char *test_input,unsigned char *channel_input,int Zc,int Kb,short block_length, short BG,unsigned char gen_code) { - short *Gen_shift_values=choose_generator_matrix(BG,Zc); - short *no_shift_values, *pointer_shift_values; - int no_punctured_columns; - short nrows,ncols,rate=3; - int i1,i2,i3,i4,i5,temp_prime; + unsigned char c[22*384]; //padded input, unpacked, max size + unsigned char d[68*384]; //coded output, unpacked, max size unsigned char channel_temp,temp; + short *Gen_shift_values, *no_shift_values, *pointer_shift_values; + short nrows = 46;//parity check bits + short ncols = 22;//info bits + + + int i,i1,i2,i3,i4,i5,temp_prime,var; + int no_punctured_columns,removed_bit,rate=3; + int nind=0; + int indlist[1000]; + int indlist2[1000]; + + //determine number of bits in codeword + //if (block_length>3840) + if (BG==1) + { + nrows=46; //parity check bits + ncols=22; //info bits + rate=3; + } + //else if (block_length<=3840) + else if (BG==2) + { + //BG=2; + nrows=42; //parity check bits + ncols=10; // info bits + rate=5; + } + + Gen_shift_values=choose_generator_matrix(BG,Zc); + if (Gen_shift_values==NULL) { + printf("ldpc_encoder_orig: could not find generator matrix\n"); + return(-1); + } + + //printf("ldpc_encoder_orig: BG %d, Zc %d, Kb %d\n",BG, Zc, Kb); + + // load base graph of generator matrix if (BG==1) { no_shift_values=(short *) no_shift_values_BG1; pointer_shift_values=(short *) pointer_shift_values_BG1; - nrows=46; //parity check bits - ncols=22; //info bits - rate=3; } else if (BG==2) { no_shift_values=(short *) no_shift_values_BG2; pointer_shift_values=(short *) pointer_shift_values_BG2; - nrows=42; //parity check bits - ncols=10; //info bits - rate=5; } else { - printf("problem with BG\n"); - return(-1); + AssertFatal(0,"BG %d is not supported yet\n",BG); } - - + no_punctured_columns=(int)((nrows-2)*Zc+block_length-block_length*rate)/Zc; + removed_bit=(nrows-no_punctured_columns-2) * Zc+block_length-(block_length*rate); + //printf("%d\n",no_punctured_columns); + //printf("%d\n",removed_bit); + // unpack input + memset(c,0,sizeof(unsigned char) * ncols * Zc); + memset(d,0,sizeof(unsigned char) * nrows * Zc); - //printf("no_punctured_columns = %d\n",no_punctured_columns); - - for (i2=0; i2 < Zc; i2++) + for (i=0; i>7&1; + c[i]=(test_input[i/8]&(128>>(i&7)))>>(7-(i&7)); + } - //rotate matrix here - for (i5=0; i5 < Kb; i5++) - { - temp = c[i5*Zc]; - memmove(&c[i5*Zc], &c[i5*Zc+1], (Zc-1)*sizeof(unsigned char)); - c[i5*Zc+Zc-1] = temp; + // parity check part + + if (gen_code==1) + { + char fname[100]; + sprintf(fname,"ldpc_BG%d_Zc%d_byte.c",BG,Zc); + FILE *fd=fopen(fname,"w"); + AssertFatal(fd!=NULL,"cannot open %s\n",fname); + sprintf(fname,"ldpc_BG%d_Zc%d_16bit.c",BG,Zc); + FILE *fd2=fopen(fname,"w"); + AssertFatal(fd2!=NULL,"cannot open %s\n",fname); + + int shift; + char data_type[100]; + char xor_command[100]; + int mask; + + + + + fprintf(fd,"#include \"PHY/sse_intrin.h\"\n"); + fprintf(fd2,"#include \"PHY/sse_intrin.h\"\n"); + + if ((Zc&31)==0) { + shift=5; // AVX2 - 256-bit SIMD + mask=31; + strcpy(data_type,"__m256i"); + strcpy(xor_command,"_mm256_xor_si256"); } + else if ((Zc&15)==0) { + shift=4; // SSE4 - 128-bit SIMD + mask=15; + strcpy(data_type,"__m128i"); + strcpy(xor_command,"_mm_xor_si128"); - // calculate each row in base graph - for (i1=0; i1 < nrows-no_punctured_columns; i1++) + } + else if ((Zc&7)==0) { + shift=3; // MMX - 64-bit SIMD + mask=7; + strcpy(data_type,"__m64"); + strcpy(xor_command,"_mm_xor_si64"); + } + else { + shift=0; // no SIMD + mask=0; + strcpy(data_type,"uint8_t"); + strcpy(xor_command,"scalar_xor"); + fprintf(fd,"#define scalar_xor(a,b) ((a)^(b))\n"); + fprintf(fd2,"#define scalar_xor(a,b) ((a)^(b))\n"); + } + fprintf(fd,"// generated code for Zc=%d, byte encoding\n",Zc); + fprintf(fd2,"// generated code for Zc=%d, 16bit encoding\n",Zc); + fprintf(fd,"static inline void ldpc_BG%d_Zc%d_byte(uint8_t *c,uint8_t *d) {\n",BG,Zc); + fprintf(fd2,"static inline void ldpc_BG%d_Zc%d_16bit(uint16_t *c,uint16_t *d) {\n",BG,Zc); + fprintf(fd," %s *csimd=(%s *)c,*dsimd=(%s *)d;\n\n",data_type,data_type,data_type); + fprintf(fd2," %s *csimd=(%s *)c,*dsimd=(%s *)d;\n\n",data_type,data_type,data_type); + fprintf(fd," %s *c2,*d2;\n\n",data_type); + fprintf(fd2," %s *c2,*d2;\n\n",data_type); + fprintf(fd," int i2;\n"); + fprintf(fd2," int i2;\n"); + fprintf(fd," for (i2=0; i2<%d; i2++) {\n",Zc>>shift); + if (shift > 0) + fprintf(fd2," for (i2=0; i2<%d; i2++) {\n",Zc>>(shift-1)); + for (i2=0; i2 < 1; i2++) { - channel_temp=0; - for (i3=0; i3 < Kb; i3++) - { - temp_prime=i1 * ncols + i3; + //t=Kb*Zc+i2; + + // calculate each row in base graph + - for (i4=0; i4 < no_shift_values[temp_prime]; i4++) + fprintf(fd," c2=&csimd[i2];\n"); + fprintf(fd," d2=&dsimd[i2];\n"); + fprintf(fd2," c2=&csimd[i2];\n"); + fprintf(fd2," d2=&dsimd[i2];\n"); + + for (i1=0; i1 < nrows; i1++) + + { + channel_temp=0; + fprintf(fd,"\n//row: %d\n",i1); + fprintf(fd2,"\n//row: %d\n",i1); + fprintf(fd," d2[%d]=",(Zc*i1)>>shift); + fprintf(fd2," d2[%d]=",(Zc*i1)>>(shift-1)); + + nind=0; + + for (i3=0; i3 < ncols; i3++) { - channel_temp = channel_temp ^ c[ i3*Zc + Gen_shift_values[ pointer_shift_values[temp_prime]+i4 ] ]; + temp_prime=i1 * ncols + i3; + + + for (i4=0; i4 < no_shift_values[temp_prime]; i4++) + { + + var=(int)((i3*Zc + (Gen_shift_values[ pointer_shift_values[temp_prime]+i4 ]+1)%Zc)/Zc); + int index =var*2*Zc + (i3*Zc + (Gen_shift_values[ pointer_shift_values[temp_prime]+i4 ]+1)%Zc) % Zc; + + indlist[nind] = ((index&mask)*((2*Zc)>>shift)*Kb)+(index>>shift); + indlist2[nind++] = ((index&(mask>>1))*((2*Zc)>>(shift-1))*Kb)+(index>>(shift-1)); + + } + + } + for (i4=0;i4gen_code); +} \ No newline at end of file diff --git a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c index ef207b6cdc..5ab55514ce 100644 --- a/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c +++ b/openair1/PHY/CODING/nrLDPC_encoder/ldpc_encoder2.c @@ -487,10 +487,10 @@ int ldpc_encoder_optim_8seg_multi(unsigned char **test_input,unsigned char **cha macro_segment = 8*macro_num; - // macro_segment_end = (n_segments > 8*(macro_num+1)) ? 8*(macro_num+1) : n_segments; - macro_segment_end = macro_segment + (n_segments > 8 ? 8 : n_segments); - ///printf("macro_segment: %d\n", macro_segment); - ///printf("macro_segment_end: %d\n", macro_segment_end ); + macro_segment_end = (n_segments > 8*(macro_num+1)) ? 8*(macro_num+1) : n_segments; + //macro_segment_end = macro_segment + (n_segments > 8 ? 8 : n_segments); + //printf("macro_segment: %d\n", macro_segment); + //printf("macro_segment_end: %d\n", macro_segment_end ); #ifdef __AVX2__ __m256i shufmask = _mm256_set_epi64x(0x0303030303030303, 0x0202020202020202,0x0101010101010101, 0x0000000000000000); @@ -564,7 +564,7 @@ int ldpc_encoder_optim_8seg_multi(unsigned char **test_input,unsigned char **cha for (i=0; i>5; i++) { c256 = _mm256_and_si256(_mm256_cmpeq_epi8(_mm256_andnot_si256(_mm256_shuffle_epi8(_mm256_set1_epi32(((uint32_t*)test_input[macro_segment])[i]), shufmask),andmask),zero256),masks[0]); //for (j=1; j #include "Gen_shift_value.h" #include "assertions.h" -#include "defs.h" -short *choose_generator_matrix(short BG,short Zc) +static inline short *choose_generator_matrix(short BG,short Zc) { short *Gen_shift_values = NULL; @@ -361,237 +360,70 @@ short *choose_generator_matrix(short BG,short Zc) return Gen_shift_values; } -int ldpc_encoder_orig(unsigned char *test_input,unsigned char *channel_input,int Zc,int Kb,short block_length, short BG,unsigned char gen_code) +static inline int encode_parity_check_part_orig(unsigned char *c,unsigned char *d, short BG,short Zc,short Kb,short block_length) { - unsigned char c[22*384]; //padded input, unpacked, max size - unsigned char d[68*384]; //coded output, unpacked, max size + short *Gen_shift_values=choose_generator_matrix(BG,Zc); + short *no_shift_values, *pointer_shift_values; + int no_punctured_columns; + short nrows,ncols,rate=3; + int i1,i2,i3,i4,i5,temp_prime; unsigned char channel_temp,temp; - short *Gen_shift_values, *no_shift_values, *pointer_shift_values; - short nrows = 46;//parity check bits - short ncols = 22;//info bits - - - int i,i1,i2,i3,i4,i5,temp_prime,var; - int no_punctured_columns,removed_bit,rate=3; - int nind=0; - int indlist[1000]; - int indlist2[1000]; - - //determine number of bits in codeword - //if (block_length>3840) - if (BG==1) - { - nrows=46; //parity check bits - ncols=22; //info bits - rate=3; - } - //else if (block_length<=3840) - else if (BG==2) - { - //BG=2; - nrows=42; //parity check bits - ncols=10; // info bits - rate=5; - } - - Gen_shift_values=choose_generator_matrix(BG,Zc); - if (Gen_shift_values==NULL) { - printf("ldpc_encoder_orig: could not find generator matrix\n"); - return(-1); - } - - //printf("ldpc_encoder_orig: BG %d, Zc %d, Kb %d\n",BG, Zc, Kb); - - // load base graph of generator matrix if (BG==1) { no_shift_values=(short *) no_shift_values_BG1; pointer_shift_values=(short *) pointer_shift_values_BG1; + nrows=46; //parity check bits + ncols=22; //info bits + rate=3; } else if (BG==2) { no_shift_values=(short *) no_shift_values_BG2; pointer_shift_values=(short *) pointer_shift_values_BG2; + nrows=42; //parity check bits + ncols=10; //info bits + rate=5; } else { - AssertFatal(0,"BG %d is not supported yet\n",BG); + printf("problem with BG\n"); + return(-1); } - + + no_punctured_columns=(int)((nrows-2)*Zc+block_length-block_length*rate)/Zc; - removed_bit=(nrows-no_punctured_columns-2) * Zc+block_length-(block_length*rate); - //printf("%d\n",no_punctured_columns); - //printf("%d\n",removed_bit); - // unpack input - memset(c,0,sizeof(unsigned char) * ncols * Zc); - memset(d,0,sizeof(unsigned char) * nrows * Zc); - for (i=0; i>7&1; - c[i]=(test_input[i/8]&(128>>(i&7)))>>(7-(i&7)); - } + //t=Kb*Zc+i2; - // parity check part - - if (gen_code==1) - { - char fname[100]; - sprintf(fname,"ldpc_BG%d_Zc%d_byte.c",BG,Zc); - FILE *fd=fopen(fname,"w"); - AssertFatal(fd!=NULL,"cannot open %s\n",fname); - sprintf(fname,"ldpc_BG%d_Zc%d_16bit.c",BG,Zc); - FILE *fd2=fopen(fname,"w"); - AssertFatal(fd2!=NULL,"cannot open %s\n",fname); - - int shift; - char data_type[100]; - char xor_command[100]; - int mask; - - - - - fprintf(fd,"#include \"PHY/sse_intrin.h\"\n"); - fprintf(fd2,"#include \"PHY/sse_intrin.h\"\n"); - - if ((Zc&31)==0) { - shift=5; // AVX2 - 256-bit SIMD - mask=31; - strcpy(data_type,"__m256i"); - strcpy(xor_command,"_mm256_xor_si256"); - } - else if ((Zc&15)==0) { - shift=4; // SSE4 - 128-bit SIMD - mask=15; - strcpy(data_type,"__m128i"); - strcpy(xor_command,"_mm_xor_si128"); - - } - else if ((Zc&7)==0) { - shift=3; // MMX - 64-bit SIMD - mask=7; - strcpy(data_type,"__m64"); - strcpy(xor_command,"_mm_xor_si64"); - } - else { - shift=0; // no SIMD - mask=0; - strcpy(data_type,"uint8_t"); - strcpy(xor_command,"scalar_xor"); - fprintf(fd,"#define scalar_xor(a,b) ((a)^(b))\n"); - fprintf(fd2,"#define scalar_xor(a,b) ((a)^(b))\n"); - } - fprintf(fd,"// generated code for Zc=%d, byte encoding\n",Zc); - fprintf(fd2,"// generated code for Zc=%d, 16bit encoding\n",Zc); - fprintf(fd,"static inline void ldpc_BG%d_Zc%d_byte(uint8_t *c,uint8_t *d) {\n",BG,Zc); - fprintf(fd2,"static inline void ldpc_BG%d_Zc%d_16bit(uint16_t *c,uint16_t *d) {\n",BG,Zc); - fprintf(fd," %s *csimd=(%s *)c,*dsimd=(%s *)d;\n\n",data_type,data_type,data_type); - fprintf(fd2," %s *csimd=(%s *)c,*dsimd=(%s *)d;\n\n",data_type,data_type,data_type); - fprintf(fd," %s *c2,*d2;\n\n",data_type); - fprintf(fd2," %s *c2,*d2;\n\n",data_type); - fprintf(fd," int i2;\n"); - fprintf(fd2," int i2;\n"); - fprintf(fd," for (i2=0; i2<%d; i2++) {\n",Zc>>shift); - if (shift > 0) - fprintf(fd2," for (i2=0; i2<%d; i2++) {\n",Zc>>(shift-1)); - for (i2=0; i2 < 1; i2++) + //rotate matrix here + for (i5=0; i5 < Kb; i5++) { - //t=Kb*Zc+i2; - - // calculate each row in base graph - - - fprintf(fd," c2=&csimd[i2];\n"); - fprintf(fd," d2=&dsimd[i2];\n"); - fprintf(fd2," c2=&csimd[i2];\n"); - fprintf(fd2," d2=&dsimd[i2];\n"); - - for (i1=0; i1 < nrows; i1++) - - { - channel_temp=0; - fprintf(fd,"\n//row: %d\n",i1); - fprintf(fd2,"\n//row: %d\n",i1); - fprintf(fd," d2[%d]=",(Zc*i1)>>shift); - fprintf(fd2," d2[%d]=",(Zc*i1)>>(shift-1)); - - nind=0; - - for (i3=0; i3 < ncols; i3++) - { - temp_prime=i1 * ncols + i3; - - - for (i4=0; i4 < no_shift_values[temp_prime]; i4++) - { - - var=(int)((i3*Zc + (Gen_shift_values[ pointer_shift_values[temp_prime]+i4 ]+1)%Zc)/Zc); - int index =var*2*Zc + (i3*Zc + (Gen_shift_values[ pointer_shift_values[temp_prime]+i4 ]+1)%Zc) % Zc; - - indlist[nind] = ((index&mask)*((2*Zc)>>shift)*Kb)+(index>>shift); - indlist2[nind++] = ((index&(mask>>1))*((2*Zc)>>(shift-1))*Kb)+(index>>(shift-1)); - - } - - - } - for (i4=0;i41024)?11:10; - - // Intermediate number of information bits - Ninfo = (nb_re * R * Qm * Nl)>>scale; - - if (Ninfo <=3824) { - n = max(3, floor(log2(Ninfo)) - 6); - Np_info = max(24, (Ninfo>>n)<= Np_info){ - nr_tbs = Tbstable_nr[i]; - break; - } - } - } - else { - n = log2(Ninfo-24)-5; - Np_info = max(3840, (ROUNDIDIV((Ninfo-24),(1< 8424){ - C = CEILIDIV((Np_info+24),8424); - nr_tbs = (C<<3)*CEILIDIV((Np_info+24),(C<<3)) - 24; - } - else { - nr_tbs = ((CEILIDIV((Np_info+24),8))<<3) - 24; - } - - } - - } - //printf("Ninfo %d nbp_re %d nb_re %d Qm %d, R %d, tbs %d\n", Ninfo, nbp_re, nb_re, Qm, R, nr_tbs); - return nr_tbs; -} - - -//tbslbrm calculation according to 5.4.2.1 of 38.212 -uint32_t nr_compute_tbslbrm(uint16_t table, - uint16_t nb_rb, - uint8_t Nl, - uint8_t C) -{ - - uint16_t R, nb_re; - uint16_t nb_rb_lbrm=0; - uint8_t Qm; - int i; - uint32_t nr_tbs=0; - uint32_t Ninfo, Np_info; - uint8_t n; - - for (i=0; i<7; i++) { - if (NPRB_LBRM[i] >= nb_rb){ - nb_rb_lbrm = NPRB_LBRM[i]; - break; - } - } - - Qm = ((table == 1)? 8 : 6); - R = 948; - nb_re = 156 * nb_rb_lbrm; - - // Intermediate number of information bits - Ninfo = (nb_re * R * Qm * Nl)>>10; - - if (Ninfo <=3824) { - n = max(3, floor(log2(Ninfo)) - 6); - Np_info = max(24, (Ninfo>>n)<= Np_info){ - nr_tbs = Tbstable_nr[i]; - break; - } - } - } - else { - n = log2(Ninfo-24)-5; - Np_info = max(3840, (ROUNDIDIV((Ninfo-24),(1< 8424){ - nr_tbs = (C<<3)*CEILIDIV((Np_info+24),(C<<3)) - 24; - } - else { - nr_tbs = ((CEILIDIV((Np_info+24),8))<<3) - 24; - } - - } - - } - return nr_tbs; - -} diff --git a/openair1/PHY/CODING/nr_polar_init.c b/openair1/PHY/CODING/nr_polar_init.c index efc78d91fd..f6a06b3f7f 100644 --- a/openair1/PHY/CODING/nr_polar_init.c +++ b/openair1/PHY/CODING/nr_polar_init.c @@ -40,7 +40,8 @@ static int intcmp(const void *p1,const void *p2) { static void nr_polar_init(t_nrPolar_params * *polarParams, int8_t messageType, uint16_t messageLength, - uint8_t aggregation_level) { + uint8_t aggregation_level, + int decoder_flag) { t_nrPolar_params *currentPtr = *polarParams; uint16_t aggregation_prime = nr_polar_aggregation_prime(aggregation_level); @@ -150,7 +151,7 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, newPolarInitNode->i_bil, newPolarInitNode->encoderLength); free(J); - build_decoder_tree(newPolarInitNode); + if (decoder_flag == 1) build_decoder_tree(newPolarInitNode); build_polar_tables(newPolarInitNode); init_polar_deinterleaver_table(newPolarInitNode); //printf("decoder tree nodes %d\n",newPolarInitNode->tree.num_nodes); @@ -183,10 +184,13 @@ void nr_polar_print_polarParams(t_nrPolar_params *polarParams) { t_nrPolar_params *nr_polar_params (int8_t messageType, uint16_t messageLength, - uint8_t aggregation_level) { + uint8_t aggregation_level, + int decoding_flag, + t_nrPolar_params **polarList_ext) { static t_nrPolar_params *polarList = NULL; - nr_polar_init(&polarList, messageType,messageLength,aggregation_level); - t_nrPolar_params *polarParams=polarList; + nr_polar_init(polarList_ext != NULL ? polarList_ext : &polarList, + messageType,messageLength,aggregation_level,decoding_flag); + t_nrPolar_params *polarParams=polarList_ext != NULL ? *polarList_ext : polarList; const int tag=messageType * messageLength * nr_polar_aggregation_prime(aggregation_level); while (polarParams != NULL) { diff --git a/openair1/PHY/CODING/nr_rate_matching.c b/openair1/PHY/CODING/nr_rate_matching.c index 9d50b4678b..0cffc2d852 100644 --- a/openair1/PHY/CODING/nr_rate_matching.c +++ b/openair1/PHY/CODING/nr_rate_matching.c @@ -32,23 +32,281 @@ uint8_t index_k0[2][4] = {{0,17,33,56},{0,13,25,43}}; - void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f) { uint32_t EQm; EQm = E/Qm; memset(f,0,E*sizeof(uint8_t)); + uint8_t *e0,*e1,*e2,*e3,*e4,*e5,*e6,*e7; + uint8_t *fp; +#if 0 //def __AVX2__ + __m256i tmp0,tmp1,tmp2,tmp0b,tmp1b,tmp3,tmp4,tmp5; + __m256i *e0_256,*e1_256,*e2_256,*e3_256,*e4_256,*e5_256,*e6_256,*e7_256; - for (int j = 0; j< EQm; j++){ - for (int i = 0; i< Qm; i++){ - f[(i+j*Qm)] = e[(i*EQm + j)]; - } + __m256i *f_256=(__m256i *)f; + + uint8_t *fp2; + switch(Qm) { + case 2: + e0=e; + e1=e0+EQm; + e0_256=(__m256i *)e0; + e1_256=(__m256i *)e1; + for (int k=0,j=0;j>5;j++,k+=2) { + f_256[k] = _mm256_unpacklo_epi8(e0_256[j],e1_256[j]); + f_256[k+1] = _mm256_unpackhi_epi8(e0_256[j],e1_256[j]); + } + break; + case 4: + e0=e; + e1=e0+EQm; + e2=e1+EQm; + e3=e2+EQm; + e0_256=(__m256i *)e0; + e1_256=(__m256i *)e1; + e2_256=(__m256i *)e2; + e3_256=(__m256i *)e3; + for (int k=0,j=0;j>5;j++,k+=4) { + tmp0 = _mm256_unpacklo_epi8(e0_256[j],e1_256[j]); // e0(i) e1(i) e0(i+1) e1(i+1) .... e0(i+15) e1(i+15) + tmp1 = _mm256_unpacklo_epi8(e2_256[j],e3_256[j]); // e2(i) e3(i) e2(i+1) e3(i+1) .... e2(i+15) e3(i+15) + f_256[k] = _mm256_unpacklo_epi8(tmp0,tmp1); // e0(i) e1(i) e2(i) e3(i) ... e0(i+7) e1(i+7) e2(i+7) e3(i+7) + f_256[k+1] = _mm256_unpackhi_epi8(tmp0,tmp1); // e0(i+8) e1(i+8) e2(i+8) e3(i+8) ... e0(i+15) e1(i+15) e2(i+15) e3(i+15) + tmp0 = _mm256_unpackhi_epi8(e0_256[j],e1_256[j]); // e0(i+16) e1(i+16) e0(i+17) e1(i+17) .... e0(i+31) e1(i+31) + tmp1 = _mm256_unpackhi_epi8(e2_256[j],e3_256[j]); // e2(i+16) e3(i+16) e2(i+17) e3(i+17) .... e2(i+31) e3(i+31) + f_256[k+2] = _mm256_unpacklo_epi8(tmp0,tmp1); + f_256[k+3] = _mm256_unpackhi_epi8(tmp0,tmp1); + } + break; + case 6: + e0=e; + e1=e0+EQm; + e2=e1+EQm; + e3=e2+EQm; + e4=e3+EQm; + e5=e4+EQm; + e0_256=(__m256i *)e0; + e1_256=(__m256i *)e1; + e2_256=(__m256i *)e2; + e3_256=(__m256i *)e3; + e4_256=(__m256i *)e4; + e5_256=(__m256i *)e5; + + for (int j=0,k=0;j>5;j++,k+=192) { + fp = f+k; + fp2 = fp+96; + + tmp0 = _mm256_unpacklo_epi8(e0_256[j],e1_256[j]); // e0(i) e1(i) e0(i+1) e1(i+1) .... e0(i+15) e1(i+15) + tmp1 = _mm256_unpacklo_epi8(e2_256[j],e3_256[j]); // e2(i) e3(i) e2(i+1) e3(i+1) .... e2(i+15) e3(i+15) + tmp0b = _mm256_unpacklo_epi16(tmp0,tmp1); // e0(i) e1(i) e2(i) e3(i) ... e0(i+7) e1(i+7) e2(i+7) e3(i+7) + tmp1b = _mm256_unpackhi_epi16(tmp0,tmp1); // e0(i+8) e1(i+8) e2(i+8) e3(i+8) ... e0(i+15) e1(i+15) e2(i+15) e3(i+15) + tmp0 = _mm256_unpacklo_epi8(e4_256[j],e5_256[j]); // e4(i) e5(i) e4(i+1) e5(i+1) .... e4(i+15) e5(i+15) + *((uint32_t*)fp) = _mm256_extract_epi32(tmp0b,0); + *((uint16_t*)(fp+4)) = _mm256_extract_epi16(tmp0,0); + *((uint32_t*)(fp+6)) = _mm256_extract_epi32(tmp0b,1); + *((uint16_t*)(fp+10)) = _mm256_extract_epi16(tmp0,1); + *((uint32_t*)(fp+12)) = _mm256_extract_epi32(tmp0b,2); + *((uint16_t*)(fp+16)) = _mm256_extract_epi16(tmp0,2); + *((uint32_t*)(fp+18)) = _mm256_extract_epi32(tmp0b,3); + *((uint16_t*)(fp+22)) = _mm256_extract_epi16(tmp0,3); + *((uint32_t*)(fp+24)) = _mm256_extract_epi32(tmp0b,4); + *((uint16_t*)(fp+26)) = _mm256_extract_epi16(tmp0,4); + *((uint32_t*)(fp+30)) = _mm256_extract_epi32(tmp0b,5); + *((uint16_t*)(fp+34)) = _mm256_extract_epi16(tmp0,5); + *((uint32_t*)(fp+36)) = _mm256_extract_epi32(tmp0,6); + *((uint16_t*)(fp+40)) = _mm256_extract_epi16(tmp0,6); + *((uint32_t*)(fp+42)) = _mm256_extract_epi32(tmp0b,7); + *((uint16_t*)(fp+46)) = _mm256_extract_epi16(tmp0,7); + + *((uint32_t*)(fp+48)) = _mm256_extract_epi32(tmp1b,0); + *((uint16_t*)(fp+52)) = _mm256_extract_epi16(tmp0,8); + *((uint32_t*)(fp+56)) = _mm256_extract_epi32(tmp1b,1); + *((uint16_t*)(fp+60)) = _mm256_extract_epi16(tmp0,9); + *((uint32_t*)(fp+62)) = _mm256_extract_epi32(tmp1b,2); + *((uint16_t*)(fp+66)) = _mm256_extract_epi16(tmp0,10); + *((uint32_t*)(fp+68)) = _mm256_extract_epi32(tmp1b,3); + *((uint16_t*)(fp+72)) = _mm256_extract_epi16(tmp0,11); + *((uint32_t*)(fp+74)) = _mm256_extract_epi32(tmp1b,4); + *((uint16_t*)(fp+76)) = _mm256_extract_epi16(tmp0,12); + *((uint32_t*)(fp+80)) = _mm256_extract_epi32(tmp1b,5); + *((uint16_t*)(fp+82)) = _mm256_extract_epi16(tmp0,13); + *((uint32_t*)(fp+86)) = _mm256_extract_epi32(tmp1b,6); + *((uint16_t*)(fp+90)) = _mm256_extract_epi16(tmp0,14); + *((uint32_t*)(fp+92)) = _mm256_extract_epi32(tmp1b,7); + *((uint16_t*)(fp+94)) = _mm256_extract_epi16(tmp0,15); + + tmp0 = _mm256_unpackhi_epi8(e0_256[j],e1_256[j]); // e0(i+16) e1(i+16) e0(i+17) e1(i+17) .... e0(i+31) e1(i+31) + tmp1 = _mm256_unpackhi_epi8(e2_256[j],e3_256[j]); // e2(i+16) e3(i+16) e2(i+17) e3(i+17) .... e2(i+31) e3(i+31) + tmp0b = _mm256_unpacklo_epi16(tmp0,tmp1); // e0(i+16) e1(i+16) e2(i+16) e3(i+16) ... e0(i+23) e1(i+23) e2(i+23) e3(i+23) + tmp1b = _mm256_unpackhi_epi16(tmp0,tmp1); // e0(i+24) e1(i+24) e2(i+24) e3(i+24) ... e0(i+31) e1(i+31) e2(i+31) e3(i+31) + tmp0 = _mm256_unpackhi_epi8(e4_256[j],e5_256[j]); // e4(i+16) e5(i+16) e4(i+17) e5(i+17) .... e4(i+31) e5(i+31) + *((uint32_t*)fp2) = _mm256_extract_epi32(tmp0b,0); + *((uint16_t*)(fp2+4)) = _mm256_extract_epi16(tmp0,0); + *((uint32_t*)(fp2+6)) = _mm256_extract_epi32(tmp0b,1); + *((uint16_t*)(fp2+10)) = _mm256_extract_epi16(tmp0,1); + *((uint32_t*)(fp2+12)) = _mm256_extract_epi32(tmp0b,2); + *((uint16_t*)(fp2+16)) = _mm256_extract_epi16(tmp0,2); + *((uint32_t*)(fp2+18)) = _mm256_extract_epi32(tmp0b,3); + *((uint16_t*)(fp2+22)) = _mm256_extract_epi16(tmp0,3); + *((uint32_t*)(fp2+24)) = _mm256_extract_epi32(tmp0b,4); + *((uint16_t*)(fp2+26)) = _mm256_extract_epi16(tmp0,4); + *((uint32_t*)(fp2+30)) = _mm256_extract_epi32(tmp0b,5); + *((uint16_t*)(fp2+34)) = _mm256_extract_epi16(tmp0,5); + *((uint32_t*)(fp2+36)) = _mm256_extract_epi32(tmp0,6); + *((uint16_t*)(fp2+40)) = _mm256_extract_epi16(tmp0,6); + *((uint32_t*)(fp2+42)) = _mm256_extract_epi32(tmp0b,7); + *((uint16_t*)(fp2+46)) = _mm256_extract_epi16(tmp0,7); + + *((uint32_t*)(fp2+48)) = _mm256_extract_epi32(tmp1b,0); + *((uint16_t*)(fp2+52)) = _mm256_extract_epi16(tmp0,8); + *((uint32_t*)(fp2+56)) = _mm256_extract_epi32(tmp1b,1); + *((uint16_t*)(fp2+60)) = _mm256_extract_epi16(tmp0,9); + *((uint32_t*)(fp2+62)) = _mm256_extract_epi32(tmp1b,2); + *((uint16_t*)(fp2+66)) = _mm256_extract_epi16(tmp0,10); + *((uint32_t*)(fp2+68)) = _mm256_extract_epi32(tmp1b,3); + *((uint16_t*)(fp2+72)) = _mm256_extract_epi16(tmp0,11); + *((uint32_t*)(fp2+74)) = _mm256_extract_epi32(tmp1b,4); + *((uint16_t*)(fp2+76)) = _mm256_extract_epi16(tmp0,12); + *((uint32_t*)(fp2+80)) = _mm256_extract_epi32(tmp1b,5); + *((uint16_t*)(fp2+82)) = _mm256_extract_epi16(tmp0,13); + *((uint32_t*)(fp2+86)) = _mm256_extract_epi32(tmp1b,6); + *((uint16_t*)(fp2+90)) = _mm256_extract_epi16(tmp0,14); + *((uint32_t*)(fp2+92)) = _mm256_extract_epi32(tmp1b,7); + *((uint16_t*)(fp2+94)) = _mm256_extract_epi16(tmp0,15); + } + break; + case 8: + e0=e; + e1=e0+EQm; + e2=e1+EQm; + e3=e2+EQm; + e4=e3+EQm; + e5=e4+EQm; + e6=e5+EQm; + e7=e6+EQm; + + e0_256=(__m256i *)e0; + e1_256=(__m256i *)e1; + e2_256=(__m256i *)e2; + e3_256=(__m256i *)e3; + e4_256=(__m256i *)e4; + e5_256=(__m256i *)e5; + e6_256=(__m256i *)e6; + e7_256=(__m256i *)e7; + for (int k=0,j=0;j>5;j++,k+=8) { + tmp0 = _mm256_unpacklo_epi8(e0_256[j],e1_256[j]); // e0(i) e1(i) e0(i+1) e1(i+1) .... e0(i+15) e1(i+15) + tmp1 = _mm256_unpacklo_epi8(e2_256[j],e3_256[j]); // e2(i) e3(i) e2(i+1) e3(i+1) .... e2(i+15) e3(i+15) + tmp2 = _mm256_unpacklo_epi8(e4_256[j],e5_256[j]); // e4(i) e5(i) e4(i+1) e5(i+1) .... e4(i+15) e5(i+15) + tmp3 = _mm256_unpacklo_epi8(e6_256[j],e7_256[j]); // e6(i) e7(i) e6(i+1) e7(i+1) .... e6(i+15) e7(i+15) + tmp4 = _mm256_unpacklo_epi16(tmp0,tmp1); // e0(i) e1(i) e2(i) e3(i) ... e0(i+7) e1(i+7) e2(i+7) e3(i+7) + tmp5 = _mm256_unpacklo_epi16(tmp2,tmp3); // e4(i) e5(i) e6(i) e7(i) ... e4(i+7) e5(i+7) e6(i+7) e7(i+7) + f_256[k] = _mm256_unpacklo_epi16(tmp4,tmp5); // e0(i) e1(i) e2(i) e3(i) e4(i) e5(i) e6(i) e7(i)... e0(i+3) e1(i+3) e2(i+3) e3(i+3) e4(i+3) e5(i+3) e6(i+3) e7(i+3)) + f_256[k+1] = _mm256_unpackhi_epi16(tmp4,tmp5); // e0(i+4) e1(i+4) e2(i+4) e3(i+4) e4(i+4) e5(i+4) e6(i+4) e7(i+4)... e0(i+7) e1(i+7) e2(i+7) e3(i+7) e4(i+7) e5(i+7) e6(i+7) e7(i+7)) + + tmp4 = _mm256_unpackhi_epi16(tmp0,tmp1); // e0(i+8) e1(i+8) e2(i+8) e3(i+8) ... e0(i+15) e1(i+15) e2(i+15) e3(i+15) + tmp5 = _mm256_unpackhi_epi16(tmp2,tmp3); // e4(i+8) e5(i+8) e6(i+8) e7(i+8) ... e4(i+15) e5(i+15) e6(i+15) e7(i+15) + f_256[k+2] = _mm256_unpacklo_epi16(tmp4,tmp5); // e0(i+8) e1(i+8) e2(i+8) e3(i+8) e4(i+8) e5(i+8) e6(i+8) e7(i+8)... e0(i+11) e1(i+11) e2(i+11) e3(i+11) e4(i+11) e5(i+11) e6(i+11) e7(i+11)) + f_256[k+3] = _mm256_unpackhi_epi16(tmp4,tmp5); // e0(i+12) e1(i+12) e2(i+12) e3(i+12) e4(i+12) e5(i+12) e6(i+12) e7(i+12)... e0(i+15) e1(i+15) e2(i+15) e3(i+15) e4(i+15) e5(i+15) e6(i+15) e7(i+15)) + + tmp0 = _mm256_unpackhi_epi8(e0_256[j],e1_256[j]); // e0(i+16) e1(i+16) e0(i+17) e1(i+17) .... e0(i+31) e1(i+31) + tmp1 = _mm256_unpackhi_epi8(e2_256[j],e3_256[j]); // e2(i+16) e3(i+16) e2(i+17) e3(i+17) .... e2(i+31) e3(i+31) + tmp2 = _mm256_unpackhi_epi8(e4_256[j],e5_256[j]); // e4(i+16) e5(i+16) e4(i+17) e5(i+17) .... e4(i+31) e5(i+31) + tmp3 = _mm256_unpackhi_epi8(e6_256[j],e7_256[j]); // e6(i+16) e7(i+16) e6(i+17) e7(i+17) .... e6(i+31) e7(i+31) + tmp4 = _mm256_unpacklo_epi16(tmp0,tmp1); // e0(i+!6) e1(i+16) e2(i+16) e3(i+16) ... e0(i+23) e1(i+23) e2(i+23) e3(i+23) + tmp5 = _mm256_unpacklo_epi16(tmp2,tmp3); // e4(i+16) e5(i+16) e6(i+16) e7(i+16) ... e4(i+23) e5(i+23) e6(i+23) e7(i+23) + f_256[k+4] = _mm256_unpacklo_epi16(tmp4,tmp5); // e0(i+16) e1(i+16) e2(i+16) e3(i+16) e4(i+16) e5(i+16) e6(i+16) e7(i+16)... e0(i+19) e1(i+19) e2(i+19) e3(i+19) e4(i+19) e5(i+19) e6(i+19) e7(i+19)) + f_256[k+5] = _mm256_unpackhi_epi16(tmp4,tmp5); // e0(i+20) e1(i+20) e2(i+20) e3(i+20) e4(i+20) e5(i+20) e6(i+20) e7(i+20)... e0(i+23) e1(i+23) e2(i+23) e3(i+23) e4(i+23) e5(i+23) e6(i+23) e7(i+23)) + + tmp4 = _mm256_unpackhi_epi16(tmp0,tmp1); // e0(i+24) e1(i+24) e2(i+24) e3(i+24) ... e0(i+31) e1(i+31) e2(i+31) e3(i+31) + tmp5 = _mm256_unpackhi_epi16(tmp2,tmp3); // e4(i+24) e5(i+24) e6(i+24) e7(i+24) ... e4(i+31) e5(i+31) e6(i+31) e7(i+31) + f_256[k+6] = _mm256_unpacklo_epi16(tmp4,tmp5); // e0(i+24) e1(i+24) e2(i+24) e3(i+24) e4(i+24) e5(i+24) e6(i+24) e7(i+24)... e0(i+27) e1(i+27) e2(i+27) e3(i+27) e4(i+27) e5(i+27) e6(i+27) e7(i+27)) + f_256[k+7] = _mm256_unpackhi_epi16(tmp4,tmp5); // e0(i+28) e1(i+28) e2(i+28) e3(i+28) e4(i+28) e5(i+28) e6(i+28) e7(i+28)... e0(i+31) e1(i+31) e2(i+31) e3(i+31) e4(i+31) e5(i+31) e6(i+31) e7(i+31)) + } + break; + default: AssertFatal(1==0,"Should be here!\n"); } +#else + //original unoptimized loops + /* + for (int j = 0; j< EQm; j++,j2+=2){ + for (int i = 0; i< Qm; i++){ + f[(i+j*Qm)] = e[(i*EQm + j)]; + } + } + */ + + int j2=0; + fp=f; + switch (Qm) { + case 2: + e0=e; + e1=e0+EQm; + for (int j = 0; j< EQm; j++,j2+=2){ + fp=&f[j2]; + fp[0] = e0[j]; + fp[1] = e1[j]; + } + break; + case 4: + e0=e; + e1=e0+EQm; + e2=e1+EQm; + e3=e2+EQm; + for (int j = 0; j< EQm; j++,j2+=4){ + fp=&f[j2]; + fp[0] = e0[j]; + fp[1] = e1[j]; + fp[2] = e2[j]; + fp[3] = e3[j]; + } + break; + case 6: + e0=e; + e1=e0+EQm; + e2=e1+EQm; + e3=e2+EQm; + e4=e3+EQm; + e5=e4+EQm; + fp = f; + for (int j = 0; j< EQm; j++){ + *fp++ = e0[j]; + *fp++ = e1[j]; + *fp++ = e2[j]; + *fp++ = e3[j]; + *fp++ = e4[j]; + *fp++ = e5[j]; + } + break; + case 8: + e0=e; + e1=e0+EQm; + e2=e1+EQm; + e3=e2+EQm; + e4=e3+EQm; + e5=e4+EQm; + e6=e5+EQm; + e7=e6+EQm; + for (int j = 0; j< EQm; j++,j2+=8){ + fp=&f[j2]; + fp[0] = e0[j]; + fp[1] = e1[j]; + fp[2] = e2[j]; + fp[3] = e3[j]; + fp[4] = e4[j]; + fp[5] = e5[j]; + fp[6] = e6[j]; + fp[7] = e7[j]; + } + break; + default: AssertFatal(1==0,"Should never be here!\n"); + } +#endif } + + void nr_deinterleaving_ldpc(uint32_t E, uint8_t Qm, int16_t *e,int16_t *f) { @@ -71,10 +329,12 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, uint8_t *w, uint8_t *e, uint8_t C, + uint32_t F, + uint32_t Foffset, uint8_t rvidx, uint32_t E) { - uint32_t Ncb,ind,k,Nref,N; + uint32_t Ncb,ind,k=0,Nref,N; if (C==0) { printf("nr_rate_matching: invalid parameters (C %d\n",C); @@ -94,21 +354,36 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, ind = (index_k0[BG-1][rvidx]*Ncb/N)*Z; #ifdef RM_DEBUG - printf("nr_rate_matching_ldpc: E %d, k0 %d, Ncb %d, rvidx %d\n", E, ind, Ncb, rvidx); + printf("nr_rate_matching_ldpc: E %d, F %d, Foffset %d, k0 %d, Ncb %d, rvidx %d\n", E, F, Foffset,ind, Ncb, rvidx); #endif + AssertFatal(Foffset <= E,"Foffset %d > E %d\n",Foffset,E); + AssertFatal(Foffset <= Ncb,"Foffset %d > Ncb %d\n",Foffset,Ncb); - k=0; + if (ind >= Foffset && ind < (F+Foffset)) ind = F+Foffset; - for (; (ind E %d\n",Foffset,E); + AssertFatal(Foffset <= Ncb,"Foffset %d > Ncb %d\n",Foffset,Ncb); #ifdef RM_DEBUG printf("nr_rate_matching_ldpc_rx: Clear %d, E %d, k0 %d, Ncb %d, rvidx %d\n", clear, E, ind, Ncb, rvidx); #endif - if (clear==1) - memset(w,0,Ncb*sizeof(int16_t)); + if (clear==1) memset(w,0,Ncb*sizeof(int16_t)); k=0; + if (ind < Foffset) + for (; (ind",k,ind,w[ind],soft_input[k]); +#endif + w[ind]+=soft_input[k++]; +#ifdef RM_DEBUG + printf("%d\n",w[ind]); +#endif + } + if (ind >= Foffset && ind < Foffset+F) ind=Foffset+F; + for (; (ind",k,ind,w[ind],soft_input[k]); +#endif w[ind] += soft_input[k++]; #ifdef RM_DEBUG - printf("RM_RX k%d Ind: %d (%d)\n",k-1,ind,w[ind]); -#endif - } - -#ifdef RM_DEBUG - else { - printf("RM_RX Ind: %d NULL %d\n",ind,nulled); - nulled++; - } - + printf("%d\n",w[ind]); #endif } - if (rvidx !=0){ while(k",k,ind,w[ind],soft_input[k]); #endif - } - + w[ind]+=soft_input[k++]; #ifdef RM_DEBUG - else { - printf("RM_RX Ind: %d NULL %d\n",ind,nulled); - nulled++; - } - + printf("%d\n",w[ind]); +#endif + } + for (ind=Foffset+F; (ind",k,ind,w[ind],soft_input[k]); +#endif + w[ind] += soft_input[k++]; +#ifdef RM_DEBUG + printf("%d\n",w[ind]); #endif } } - } + return 0; } diff --git a/openair1/PHY/CODING/nr_segmentation.c b/openair1/PHY/CODING/nr_segmentation.c index 90586e24d4..1d80a83131 100644 --- a/openair1/PHY/CODING/nr_segmentation.c +++ b/openair1/PHY/CODING/nr_segmentation.c @@ -30,13 +30,13 @@ //#define DEBUG_SEGMENTATION int32_t nr_segmentation(unsigned char *input_buffer, - unsigned char **output_buffers, - unsigned int B, - unsigned int *C, - unsigned int *K, - unsigned int *Zout, // [hna] Zout is Zc - unsigned int *F, - uint8_t BG) + unsigned char **output_buffers, + unsigned int B, + unsigned int *C, + unsigned int *K, + unsigned int *Zout, // [hna] Zout is Zc + unsigned int *F, + uint8_t BG) { unsigned int L,Bprime,Z,r,Kcb,Kb,k,s,crc,Kprime; @@ -63,7 +63,7 @@ int32_t nr_segmentation(unsigned char *input_buffer, #endif } - if ((*C)>MAX_NUM_DLSCH_SEGMENTS) { + if ((*C)>MAX_NUM_NR_DLSCH_SEGMENTS) { LOG_E(PHY,"nr_segmentation.c: too many segments %d, B %d, L %d, Bprime %d\n",*C,B,L,Bprime); return(-1); } diff --git a/openair1/PHY/INIT/lte_parms.c b/openair1/PHY/INIT/lte_parms.c index a3ca8421b3..12a5646df6 100644 --- a/openair1/PHY/INIT/lte_parms.c +++ b/openair1/PHY/INIT/lte_parms.c @@ -161,6 +161,8 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms, if (frame_parms->frame_type == TDD) set_S_config(frame_parms); + frame_parms->samples_per_subframe=frame_parms->samples_per_tti; + frame_parms->samples_per_slot=frame_parms->samples_per_tti>>1; // frame_parms->tdd_config=3; return(0); } diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index f0ad3cbaae..1c0d5a6aca 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -31,6 +31,7 @@ #include "TDD-Config.h" #include "MBSFN-SubframeConfigList.h"*/ #include "openair1/PHY/defs_RU.h" +#include "openair1/PHY/CODING/nrLDPC_extern.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "assertions.h" #include @@ -43,34 +44,30 @@ /* extern uint32_t from_nrarfcn(int nr_bandP,uint32_t dl_nrarfcn); -extern int32_t get_nr_uldl_offset(int nr_bandP);*/ -extern openair0_config_t openair0_cfg[MAX_CARDS]; -int l1_north_init_gNB() -{ - if (RC.nb_nr_L1_inst > 0 && RC.nb_nr_L1_CC != NULL && RC.gNB != NULL) { +extern int32_t get_nr_uldl_offset(int nr_bandP); +extern openair0_config_t openair0_cfg[MAX_CARDS]; +*/ + +int l1_north_init_gNB() { + + if (RC.nb_nr_L1_inst > 0 && RC.gNB != NULL) { + AssertFatal(RC.nb_nr_L1_inst>0,"nb_nr_L1_inst=%d\n",RC.nb_nr_L1_inst); - AssertFatal(RC.nb_nr_L1_CC!=NULL,"nb_nr_L1_CC is null\n"); AssertFatal(RC.gNB!=NULL,"RC.gNB is null\n"); LOG_I(PHY,"%s() RC.nb_nr_L1_inst:%d\n", __FUNCTION__, RC.nb_nr_L1_inst); for (int i=0; i0,"RC.nb_nr_L1_CC[%d]=%d\n",i,RC.nb_nr_L1_CC[i]); - LOG_I(PHY,"%s() RC.nb_nr_L1_CC[%d]:%d\n", __FUNCTION__, i, RC.nb_nr_L1_CC[i]); - for (int j=0; jif_inst = NR_IF_Module_init(i))<0) return(-1); - - LOG_I(PHY,"%s() RC.gNB[%d][%d] installing callbacks\n", __FUNCTION__, i, j); - RC.gNB[i][j]->if_inst->NR_PHY_config_req = nr_phy_config_request; - RC.gNB[i][j]->if_inst->NR_Schedule_response = nr_schedule_response; - } + if ((RC.gNB[i]->if_inst = NR_IF_Module_init(i))<0) return(-1); + + LOG_I(PHY,"%s() RC.gNB[%d] installing callbacks\n", __FUNCTION__, i); + RC.gNB[i]->if_inst->NR_PHY_config_req = nr_phy_config_request; + RC.gNB[i]->if_inst->NR_Schedule_response = nr_schedule_response; } } else { - LOG_I(PHY,"%s() Not installing PHY callbacks - RC.nb_nr_L1_inst:%d RC.nb_nr_L1_CC:%p RC.gNB:%p\n", __FUNCTION__, RC.nb_nr_L1_inst, RC.nb_nr_L1_CC, RC.gNB); + LOG_I(PHY,"%s() Not installing PHY callbacks - RC.nb_nr_L1_inst:%d RC.gNB:%p\n", __FUNCTION__, RC.nb_nr_L1_inst, RC.gNB); } return(0); @@ -82,19 +79,20 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, unsigned char abstraction_flag) { // shortcuts NR_DL_FRAME_PARMS *const fp = &gNB->frame_parms; - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; NR_gNB_COMMON *const common_vars = &gNB->common_vars; + NR_gNB_PRACH *const prach_vars = &gNB->prach_vars; NR_gNB_PUSCH **const pusch_vars = gNB->pusch_vars; /*LTE_eNB_SRS *const srs_vars = gNB->srs_vars; LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/ int i; + int Ptx=cfg->carrier_config.num_tx_ant.value; + int Prx=cfg->carrier_config.num_rx_ant.value; + AssertFatal(Ptx>0 && Ptx<9,"Ptx %d is not supported\n",Ptx); + AssertFatal(Prx>0 && Prx<9,"Prx %d is not supported\n",Prx); LOG_I(PHY,"[gNB %d] %s() About to wait for gNB to be configured\n", gNB->Mod_id, __FUNCTION__); - gNB->total_dlsch_bitrate = 0; - gNB->total_transmitted_bits = 0; - gNB->total_system_throughput = 0; - gNB->check_for_MUMIMO_transmissions=0; while(gNB->configured == 0) usleep(10000); @@ -115,6 +113,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, LOG_D(PHY,"[MSC_NEW][FRAME 00000][PHY_gNB][MOD %02"PRIu8"][]\n", gNB->Mod_id); crcTableInit(); init_dfts(); + load_nrLDPClib(); // PBCH DMRS gold sequences generation nr_init_pbch_dmrs(gNB); //PDCCH DMRS init @@ -132,7 +131,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } } - nr_init_pdcch_dmrs(gNB, cfg->sch_config.physical_cell_id.value); + nr_init_pdcch_dmrs(gNB, cfg->cell_config.phy_cell_id.value); nr_init_pbch_interleaver(gNB->nr_pbch_interleaver); //PDSCH DMRS init gNB->nr_gold_pdsch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***)); @@ -153,38 +152,52 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } } - //------------- config PUSCH DMRS parameters(to be updated from RRC)--------------// - gNB->dmrs_UplinkConfig.pusch_dmrs_type = pusch_dmrs_type1; - gNB->dmrs_UplinkConfig.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0; - gNB->dmrs_UplinkConfig.pusch_maxLength = pusch_len1; - //--------------------------------------------------------------------------------// - nr_init_pdsch_dmrs(gNB, cfg->sch_config.physical_cell_id.value); + nr_init_pdsch_dmrs(gNB, cfg->cell_config.phy_cell_id.value); - // default values until overwritten by RRCConnectionReconfiguration + //PUSCH DMRS init + gNB->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(2*sizeof(uint32_t ***)); + uint32_t ****pusch_dmrs = gNB->nr_gold_pusch_dmrs; - for (i=0;ipusch_config.pusch_TimeDomainResourceAllocation[i] = (PUSCH_TimeDomainResourceAllocation_t *)malloc16(sizeof(PUSCH_TimeDomainResourceAllocation_t)); - gNB->pusch_config.pusch_TimeDomainResourceAllocation[i]->mappingType = typeB; + for(int nscid=0; nscid<2; nscid++) { + pusch_dmrs[nscid] = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **)); + AssertFatal(pusch_dmrs[nscid]!=NULL, "NR init: pusch_dmrs for nscid %d - malloc failed\n", nscid); + + for (int slot=0; slotslots_per_frame; slot++) { + pusch_dmrs[nscid][slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *)); + AssertFatal(pusch_dmrs[nscid][slot]!=NULL, "NR init: pusch_dmrs for slot %d - malloc failed\n", slot); + + for (int symb=0; symbsymbols_per_slot; symb++) { + pusch_dmrs[nscid][slot][symb] = (uint32_t *)malloc16(NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t)); + AssertFatal(pusch_dmrs[nscid][slot][symb]!=NULL, "NR init: pusch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); + } + } } + uint32_t Nid_pusch[2] = {cfg->cell_config.phy_cell_id.value,cfg->cell_config.phy_cell_id.value}; + nr_gold_pusch(gNB, &Nid_pusch[0]); + /// Transport init necessary for NR synchro init_nr_transport(gNB); - gNB->first_run_I0_measurements = 1; ///This flag used to be static. With multiple gNBs this does no longer work, hence we put it in the structure. However it has to be initialized with 1, which is performed here. - common_vars->rxdata = (int32_t **)malloc16(15*sizeof(int32_t*)); - common_vars->txdataF = (int32_t **)malloc16(15*sizeof(int32_t*)); - common_vars->rxdataF = (int32_t **)malloc16(15*sizeof(int32_t*)); + gNB->first_run_I0_measurements = 1; - for (i=0;i<15;i++){ + common_vars->rxdata = (int32_t **)malloc16(Prx*sizeof(int32_t*)); + common_vars->txdataF = (int32_t **)malloc16(Ptx*sizeof(int32_t*)); + common_vars->rxdataF = (int32_t **)malloc16(Prx*sizeof(int32_t*)); + + for (i=0;itxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP - common_vars->rxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); - common_vars->rxdata[i] = (int32_t*)malloc16_clear(fp->samples_per_frame*sizeof(int32_t)); - LOG_D(PHY,"[INIT] common_vars->txdataF[%d] = %p (%lu bytes)\n", - i,common_vars->txdataF[i], - fp->samples_per_frame_wCP*sizeof(int32_t)); + i,common_vars->txdataF[i], + fp->samples_per_frame_wCP*sizeof(int32_t)); + } + for (i=0;irxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); + common_vars->rxdata[i] = (int32_t*)malloc16_clear(fp->samples_per_frame*sizeof(int32_t)); + } + // Channel estimates for SRS /* @@ -207,112 +220,76 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, for (UE_id=0; UE_idofdm_symbol_size*sizeof(int32_t)); } - +*/ // PRACH prach_vars->prachF = (int16_t *)malloc16_clear( 1024*2*sizeof(int16_t) ); - // assume maximum of 64 RX antennas for PRACH receiver - prach_vars->prach_ifft[0] = (int32_t **)malloc16_clear(64*sizeof(int32_t *)); + prach_vars->rxsigF = (int16_t **)malloc16_clear(Prx*sizeof(int16_t*)); + /* + for (i=0;irxsigF[i] = (int16_t *)malloc16_clear( 1024*2*sizeof(int16_t) ); + } + */ + prach_vars->prach_ifft = (int32_t *)malloc16_clear(1024*2*sizeof(int32_t)); - for (i=0; i<64; i++) prach_vars->prach_ifft[0][i] = (int32_t *)malloc16_clear(1024*2*sizeof(int32_t)); + int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value; - prach_vars->rxsigF[0] = (int16_t **)malloc16_clear(64*sizeof(int16_t *)); -*/ + printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]); + for (int ULSCH_id=0; ULSCH_iddlsch[0][0]->harq_processes[0]); + pusch_vars[ULSCH_id] = (NR_gNB_PUSCH *)malloc16_clear( sizeof(NR_gNB_PUSCH) ); + pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_estimates = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_estimates_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_estimates_time = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->rxdataF_comp = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_mag0 = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_magb0 = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_mag = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); + pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear(Prx*sizeof(int32_t*) ); - for (int UE_id=0; UE_idrxdataF_ext = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->rxdataF_ext2 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_estimates = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_estimates_ext = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_estimates_time = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->rxdataF_comp = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_mag0 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_magb0 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_mag = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->ul_ch_magb = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) ); - pusch_vars[UE_id]->rho = (int32_t **)malloc16_clear( fp->nb_antennas_rx*sizeof(int32_t*) ); - - for (i=0; inb_antennas_rx; i++) { - // RK 2 times because of output format of FFT! - // FIXME We should get rid of this - pusch_vars[UE_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12*fp->symbols_per_slot ); - pusch_vars[UE_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12*fp->symbols_per_slot ); - pusch_vars[UE_id]->ul_ch_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12*fp->symbols_per_slot ); - pusch_vars[UE_id]->ul_ch_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12*fp->symbols_per_slot ); - pusch_vars[UE_id]->ul_ch_estimates_time[i] = (int32_t *)malloc16_clear( 2*sizeof(int32_t)*fp->ofdm_symbol_size ); - pusch_vars[UE_id]->rxdataF_comp[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12*fp->symbols_per_slot ); - pusch_vars[UE_id]->ul_ch_mag0[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12 ); - pusch_vars[UE_id]->ul_ch_magb0[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12 ); - pusch_vars[UE_id]->ul_ch_mag[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12 ); - pusch_vars[UE_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*cfg->rf_config.ul_carrier_bandwidth.value*12 ); - pusch_vars[UE_id]->rho[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*(fp->N_RB_UL*12*7*2) ); + printf("ULSCH_id %d (before rx antenna alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]); + for (i=0; irxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); + pusch_vars[ULSCH_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); + pusch_vars[ULSCH_id]->ul_ch_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); + pusch_vars[ULSCH_id]->ul_ch_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); + pusch_vars[ULSCH_id]->ul_ch_estimates_time[i] = (int32_t *)malloc16_clear( 2*sizeof(int32_t)*fp->ofdm_symbol_size ); + pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*2*fp->symbols_per_slot ); // max intensity in freq is 1 sc every 2 RBs + pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*2*fp->symbols_per_slot ); + pusch_vars[ULSCH_id]->rxdataF_comp[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); + pusch_vars[ULSCH_id]->ul_ch_mag0[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 ); + pusch_vars[ULSCH_id]->ul_ch_magb0[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 ); + pusch_vars[ULSCH_id]->ul_ch_mag[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 ); + pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 ); + pusch_vars[ULSCH_id]->rho[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*(fp->N_RB_UL*12*7*2) ); } - - pusch_vars[UE_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear - } //UE_id + printf("ULSCH_id %d (before llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]); + pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear + printf("ULSCH_id %d (after llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]); + } //ulsch_id /* - for (UE_id=0; UE_idUE_stats_ptr[UE_id] = &gNB->UE_stats[UE_id]; + for (ulsch_id=0; ulsch_idUE_stats_ptr[ulsch_id] = &gNB->UE_stats[ulsch_id]; */ - gNB->pdsch_config_dedicated->p_a = dB0; //defaul value until overwritten by RRCConnectionReconfiguration + printf("After ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]); return (0); } -/* -void phy_config_request(PHY_Config_t *phy_config) { - - uint8_t Mod_id = phy_config->Mod_id; - int CC_id = phy_config->CC_id; - nfapi_nr_config_request_t *cfg = phy_config->cfg; - - NR_DL_FRAME_PARMS *fp; - PHICH_RESOURCE_t phich_resource_table[4]={oneSixth,half,one,two}; - int eutra_band = cfg->nfapi_config.rf_bands.rf_band[0]; - int dl_Bandwidth = cfg->rf_config.dl_carrier_bandwidth.value; - int ul_Bandwidth = cfg->rf_config.ul_carrier_bandwidth.value; - int Nid_cell = cfg->sch_config.physical_cell_id.value; - int Ncp = cfg->subframe_config.dl_cyclic_prefix_type.value; - int p_eNB = cfg->rf_config.tx_antenna_ports.value; - uint32_t dl_CarrierFreq = cfg->nfapi_config.earfcn.value; - - LOG_I(PHY,"Configuring MIB for instance %d, CCid %d : (band %d,N_RB_DL %d, N_RB_UL %d, Nid_cell %d,gNB_tx_antenna_ports %d,Ncp %d,DL freq %u)\n", - Mod_id, CC_id, eutra_band, dl_Bandwidth, ul_Bandwidth, Nid_cell, p_eNB,Ncp,dl_CarrierFreq ); - - AssertFatal(RC.gNB != NULL, "PHY instance pointer doesn't exist\n"); - AssertFatal(RC.gNB[Mod_id] != NULL, "PHY instance %d doesn't exist\n",Mod_id); - AssertFatal(RC.gNB[Mod_id][CC_id] != NULL, "PHY instance %d, CCid %d doesn't exist\n",Mod_id,CC_id); - - - if (RC.gNB[Mod_id][CC_id]->configured == 1) - { - LOG_E(PHY,"Already eNB already configured, do nothing\n"); - return; - } - - RC.gNB[Mod_id][CC_id]->mac_enabled = 1; - - fp = &RC.gNB[Mod_id][CC_id]->frame_parms; - - fp->threequarter_fs = 0; - - nr_init_frame_parms(fp,1); - - RC.gNB[Mod_id][CC_id]->configured = 1; - LOG_I(PHY,"gNB %d/%d configured\n",Mod_id,CC_id); -}*/ - void phy_free_nr_gNB(PHY_VARS_gNB *gNB) { //NR_DL_FRAME_PARMS* const fp = &gNB->frame_parms; - //nfapi_nr_config_request_t *cfg = &gNB->gNB_config; NR_gNB_COMMON *const common_vars = &gNB->common_vars; NR_gNB_PUSCH **const pusch_vars = gNB->pusch_vars; /*LTE_eNB_SRS *const srs_vars = gNB->srs_vars; LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/ uint32_t ***pdcch_dmrs = gNB->nr_gold_pdcch_dmrs; + int Ptx=gNB->gNB_config.carrier_config.num_tx_ant.value; - for (int i = 0; i < 15; i++) { + for (int i = 0; i < Ptx; i++) { free_and_zero(common_vars->txdataF[i]); /* rxdataF[i] is not allocated -> don't free */ } @@ -344,36 +321,40 @@ void phy_free_nr_gNB(PHY_VARS_gNB *gNB) free_and_zero(prach_vars->prach_ifft[0]); free_and_zero(prach_vars->rxsigF[0]); */ - for (int UE_id=0; UE_idrxdataF_ext[i]); - free_and_zero(pusch_vars[UE_id]->rxdataF_ext2[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_estimates[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_estimates_ext[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_estimates_time[i]); - free_and_zero(pusch_vars[UE_id]->rxdataF_comp[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_mag0[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_magb0[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_mag[i]); - free_and_zero(pusch_vars[UE_id]->ul_ch_magb[i]); - free_and_zero(pusch_vars[UE_id]->rho[i]); + free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext[i]); + free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext2[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_ext[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_time[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext[i]); + free_and_zero(pusch_vars[ULSCH_id]->rxdataF_comp[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_mag0[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_magb0[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_mag[i]); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_magb[i]); + free_and_zero(pusch_vars[ULSCH_id]->rho[i]); } - free_and_zero(pusch_vars[UE_id]->rxdataF_ext); - free_and_zero(pusch_vars[UE_id]->rxdataF_ext2); - free_and_zero(pusch_vars[UE_id]->ul_ch_estimates); - free_and_zero(pusch_vars[UE_id]->ul_ch_estimates_ext); - free_and_zero(pusch_vars[UE_id]->ul_ch_estimates_time); - free_and_zero(pusch_vars[UE_id]->rxdataF_comp); - free_and_zero(pusch_vars[UE_id]->ul_ch_mag0); - free_and_zero(pusch_vars[UE_id]->ul_ch_magb0); - free_and_zero(pusch_vars[UE_id]->ul_ch_mag); - free_and_zero(pusch_vars[UE_id]->ul_ch_magb); - free_and_zero(pusch_vars[UE_id]->rho); + free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext); + free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext2); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_ext); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_time); + free_and_zero(pusch_vars[ULSCH_id]->rxdataF_comp); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_mag0); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_magb0); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_mag); + free_and_zero(pusch_vars[ULSCH_id]->ul_ch_magb); + free_and_zero(pusch_vars[ULSCH_id]->rho); - free_and_zero(pusch_vars[UE_id]->llr); - free_and_zero(pusch_vars[UE_id]); - } //UE_id + free_and_zero(pusch_vars[ULSCH_id]->llr); + free_and_zero(pusch_vars[ULSCH_id]); + } //ULSCH_id /* for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) gNB->UE_stats_ptr[UE_id] = NULL; */ @@ -396,103 +377,127 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, uint64_t position_in_burst) { NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; - nfapi_nr_config_request_t *gNB_config = &gNB->gNB_config; + nfapi_nr_config_request_scf_t *gNB_config = &gNB->gNB_config; //overwrite for new NR parameters - gNB_config->nfapi_config.rf_bands.rf_band[0] = 78; - gNB_config->nfapi_config.nrarfcn.value = 620000; - gNB_config->subframe_config.numerology_index_mu.value = mu; - gNB_config->subframe_config.duplex_mode.value = TDD; - gNB_config->rf_config.dl_carrier_bandwidth.value = N_RB_DL; - gNB_config->rf_config.ul_carrier_bandwidth.value = N_RB_UL; - gNB_config->sch_config.half_frame_index.value = 0; - gNB_config->sch_config.ssb_subcarrier_offset.value = 0; - gNB_config->sch_config.n_ssb_crb.value = (N_RB_DL-20); - gNB_config->sch_config.ssb_subcarrier_offset.value = 0; - gNB_config->sch_config.physical_cell_id.value = Nid_cell; - gNB_config->sch_config.ssb_scg_position_in_burst.value = position_in_burst; - gNB_config->subframe_config.dl_cyclic_prefix_type.value = (fp->Ncp == NORMAL) ? NFAPI_CP_NORMAL : NFAPI_CP_EXTENDED; + + uint64_t rev_burst=0; + for (int i=0; i<64; i++) + rev_burst |= (((position_in_burst>>(63-i))&0x01)<cell_config.phy_cell_id.value = Nid_cell; + gNB_config->ssb_config.scs_common.value = mu; + gNB_config->ssb_table.ssb_subcarrier_offset.value = 0; + gNB_config->ssb_table.ssb_offset_point_a.value = (N_RB_DL-20)>>1; + gNB_config->ssb_table.ssb_mask_list[1].ssb_mask.value = (rev_burst)&(0xFFFFFFFF); + gNB_config->ssb_table.ssb_mask_list[0].ssb_mask.value = (rev_burst>>32)&(0xFFFFFFFF); + gNB_config->cell_config.frame_duplex_type.value = TDD; + gNB_config->ssb_table.ssb_period.value = 1; //10ms + gNB_config->carrier_config.dl_grid_size[mu].value = N_RB_DL; + gNB_config->carrier_config.ul_grid_size[mu].value = N_RB_UL; + gNB_config->carrier_config.num_tx_ant.value = fp->nb_antennas_tx; + gNB_config->carrier_config.num_rx_ant.value = fp->nb_antennas_rx; + + gNB_config->tdd_table.tdd_period.value = 0; + //gNB_config->subframe_config.dl_cyclic_prefix_type.value = (fp->Ncp == NORMAL) ? NFAPI_CP_NORMAL : NFAPI_CP_EXTENDED; gNB->mac_enabled = 1; fp->dl_CarrierFreq = 3500000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value); fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000); + fp->nr_band = 78; fp->threequarter_fs= 0; + + gNB_config->carrier_config.dl_bandwidth.value = config_bandwidth(mu, N_RB_DL, fp->nr_band); + nr_init_frame_parms(gNB_config, fp); gNB->configured = 1; LOG_I(PHY,"gNB configured\n"); } -void nr_phy_config_request(NR_PHY_Config_t *phy_config) -{ - uint8_t Mod_id = phy_config->Mod_id; - int CC_id = phy_config->CC_id; - NR_DL_FRAME_PARMS *fp = &RC.gNB[Mod_id][CC_id]->frame_parms; - nfapi_nr_config_request_t *gNB_config = &RC.gNB[Mod_id][CC_id]->gNB_config; - gNB_config->nfapi_config.rf_bands.rf_band[0] = phy_config->cfg->nfapi_config.rf_bands.rf_band[0]; //22 - gNB_config->nfapi_config.nrarfcn.value = phy_config->cfg->nfapi_config.nrarfcn.value; //6600 - gNB_config->subframe_config.numerology_index_mu.value = phy_config->cfg->subframe_config.numerology_index_mu.value;//1 - gNB_config->rf_config.dl_carrier_bandwidth.value = phy_config->cfg->rf_config.dl_carrier_bandwidth.value;//106; - gNB_config->rf_config.ul_carrier_bandwidth.value = phy_config->cfg->rf_config.ul_carrier_bandwidth.value;//106; - gNB_config->sch_config.half_frame_index.value = 0; - gNB_config->sch_config.ssb_subcarrier_offset.value = phy_config->cfg->sch_config.ssb_subcarrier_offset.value;//0; - gNB_config->sch_config.n_ssb_crb.value = (phy_config->cfg->rf_config.dl_carrier_bandwidth.value-20); - gNB_config->sch_config.physical_cell_id.value = phy_config->cfg->sch_config.physical_cell_id.value; - gNB_config->sch_config.ssb_scg_position_in_burst.value= phy_config->cfg->sch_config.ssb_scg_position_in_burst.value; - gNB_config->sch_config.ssb_periodicity.value = phy_config->cfg->sch_config.ssb_periodicity.value; +void nr_phy_config_request(NR_PHY_Config_t *phy_config) { + uint8_t Mod_id = phy_config->Mod_id; + NR_DL_FRAME_PARMS *fp = &RC.gNB[Mod_id]->frame_parms; + nfapi_nr_config_request_scf_t *gNB_config = &RC.gNB[Mod_id]->gNB_config; - if (phy_config->cfg->subframe_config.duplex_mode.value == 0) { - gNB_config->subframe_config.duplex_mode.value = FDD; - } else { - gNB_config->subframe_config.duplex_mode.value = TDD; + /* + gNB_config->cell_config.phy_cell_id.value = phy_config->cfg->cell_config.phy_cell_id.value; + gNB_config->carrier_config.dl_frequency.value = phy_config->cfg->carrier_config.dl_frequency.value; + gNB_config->carrier_config.uplink_frequency.value = phy_config->cfg->carrier_config.uplink_frequency.value; + gNB_config->ssb_config.scs_common.value = phy_config->cfg->ssb_config.scs_common.value; + gNB_config->carrier_config.dl_bandwidth.value = phy_config->cfg->carrier_config.dl_bandwidth.value; + gNB_config->carrier_config.uplink_bandwidth.value = phy_config->cfg->carrier_config.uplink_bandwidth.value; + gNB_config->ssb_table.ssb_subcarrier_offset.value = phy_config->cfg->ssb_table.ssb_subcarrier_offset.value; + gNB_config->ssb_table.ssb_offset_point_a.value = phy_config->cfg->ssb_table.ssb_offset_point_a.value; + gNB_config->ssb_table.ssb_mask_list[0].ssb_mask.value = phy_config->cfg->ssb_table.ssb_mask_list[0].ssb_mask.value; + gNB_config->ssb_table.ssb_mask_list[1].ssb_mask.value = phy_config->cfg->ssb_table.ssb_mask_list[1].ssb_mask.value; + gNB_config->ssb_table.ssb_period.value = phy_config->cfg->ssb_table.ssb_period.value; + for (int i=0; i<5; i++) { + gNB_config->carrier_config.dl_grid_size[i].value = phy_config->cfg->carrier_config.dl_grid_size[i].value; + gNB_config->carrier_config.ul_grid_size[i].value = phy_config->cfg->carrier_config.ul_grid_size[i].value; + gNB_config->carrier_config.dl_k0[i].value = phy_config->cfg->carrier_config.dl_k0[i].value; + gNB_config->carrier_config.ul_k0[i].value = phy_config->cfg->carrier_config.ul_k0[i].value; } - RC.gNB[Mod_id][CC_id]->mac_enabled = 1; - fp->dl_CarrierFreq = from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value); - get_band(fp->dl_CarrierFreq, &gNB_config->nfapi_config.rf_bands.rf_band[0], &uplink_frequency_offset[CC_id][0], &fp->frame_type); - fp->ul_CarrierFreq = fp->dl_CarrierFreq + uplink_frequency_offset[CC_id][0]; - fp->threequarter_fs = openair0_cfg[0].threequarter_fs; - LOG_I(PHY,"Configuring MIB for instance %d, CCid %d : (band %d,N_RB_DL %d, N_RB_UL %d, Nid_cell %d,DL freq %u, UL freq %u)\n", + + if (phy_config->cfg->cell_config.frame_duplex_type.value == 0) { + gNB_config->cell_config.frame_duplex_type.value = FDD; + } else { + gNB_config->cell_config.frame_duplex_type.value = TDD; + } + + memcpy((void*)&gNB_config->prach_config,(void*)&phy_config->cfg->prach_config,sizeof(phy_config->cfg->prach_config)); + memcpy((void*)&gNB_config->tdd_table,(void*)&phy_config->cfg->tdd_table,sizeof(phy_config->cfg->tdd_table)); + */ + memcpy((void*)gNB_config,phy_config->cfg,sizeof(*phy_config->cfg)); + RC.gNB[Mod_id]->mac_enabled = 1; + + uint64_t dl_bw_khz = (12*gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value)*(15<ssb_config.scs_common.value); + fp->dl_CarrierFreq = ((dl_bw_khz>>1) + gNB_config->carrier_config.dl_frequency.value)*1000 ; + + int32_t dlul_offset = 0; + lte_frame_type_t frame_type = 0; + + get_band(fp->dl_CarrierFreq,&fp->nr_band,&dlul_offset,&frame_type); + + uint64_t ul_bw_khz = (12*gNB_config->carrier_config.ul_grid_size[gNB_config->ssb_config.scs_common.value].value)*(15<ssb_config.scs_common.value); + fp->ul_CarrierFreq = ((ul_bw_khz>>1) + gNB_config->carrier_config.uplink_frequency.value)*1000 ; + + AssertFatal(fp->ul_CarrierFreq==(fp->dl_CarrierFreq+dlul_offset), "Disagreement in uplink frequency for band %d\n", fp->nr_band); + + fp->threequarter_fs = openair0_cfg[0].threequarter_fs; + LOG_I(PHY,"Configuring MIB for instance %d, : (Nid_cell %d,DL freq %llu, UL freq %llu)\n", Mod_id, - CC_id, - gNB_config->nfapi_config.rf_bands.rf_band[0], - gNB_config->rf_config.dl_carrier_bandwidth.value, - gNB_config->rf_config.ul_carrier_bandwidth.value, - gNB_config->sch_config.physical_cell_id.value, - fp->dl_CarrierFreq, - fp->ul_CarrierFreq); + gNB_config->cell_config.phy_cell_id.value, + (unsigned long long)fp->dl_CarrierFreq, + (unsigned long long)fp->ul_CarrierFreq); nr_init_frame_parms(gNB_config, fp); + - if (RC.gNB[Mod_id][CC_id]->configured == 1) { + if (RC.gNB[Mod_id]->configured == 1) { LOG_E(PHY,"Already gNB already configured, do nothing\n"); return; } - RC.gNB[Mod_id][CC_id]->configured = 1; - LOG_I(PHY,"gNB %d/%d configured\n",Mod_id,CC_id); + RC.gNB[Mod_id]->configured = 1; + LOG_I(PHY,"gNB %d configured\n",Mod_id); } void init_nr_transport(PHY_VARS_gNB *gNB) { int i; int j; NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; LOG_I(PHY, "Initialise nr transport\n"); + uint16_t grid_size = cfg->carrier_config.dl_grid_size[fp->numerology_index].value; for (i=0; idlsch[i][j] = new_gNB_dlsch(1,16,NSOFT,0,fp,cfg); - - if (!gNB->dlsch[i][j]) { - LOG_E(PHY,"Can't get gNB dlsch structures for UE %d \n", i); - exit(-1); - }/* else { - gNB->dlsch[i][j]->rnti=0; - LOG_D(PHY,"dlsch[%d][%d] => %p rnti:%d\n",i,j,gNB->dlsch[i][j], gNB->dlsch[i][j]->rnti); - }*/ + gNB->dlsch[i][j] = new_gNB_dlsch(fp,1,16,NSOFT,0,grid_size); + AssertFatal(gNB->dlsch[i][j]!=NULL,"Can't initialize dlsch %d \n", i); } } @@ -519,8 +524,8 @@ void init_nr_transport(PHY_VARS_gNB *gNB) { rel15_ul->rnti = 0x1234; rel15_ul->ulsch_pdu_rel15.start_rb = 0; rel15_ul->ulsch_pdu_rel15.number_rbs = 50; - rel15_ul->ulsch_pdu_rel15.start_symbol = 0; - rel15_ul->ulsch_pdu_rel15.number_symbols = 14; + rel15_ul->ulsch_pdu_rel15.start_symbol = 2; + rel15_ul->ulsch_pdu_rel15.number_symbols = 12; rel15_ul->ulsch_pdu_rel15.length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; rel15_ul->ulsch_pdu_rel15.Qm = 2; rel15_ul->ulsch_pdu_rel15.R = 679; @@ -534,18 +539,8 @@ void init_nr_transport(PHY_VARS_gNB *gNB) { } - gNB->dlsch_SI = new_gNB_dlsch(1,8,NSOFT, 0, fp, cfg); - LOG_D(PHY,"gNB %d.%d : SI %p\n",gNB->Mod_id,gNB->CC_id,gNB->dlsch_SI); - gNB->dlsch_ra = new_gNB_dlsch(1,8,NSOFT, 0, fp, cfg); - LOG_D(PHY,"gNB %d.%d : RA %p\n",gNB->Mod_id,gNB->CC_id,gNB->dlsch_ra); gNB->rx_total_gain_dB=130; - for(i=0; imu_mimo_mode[i].dl_pow_off = 2; - gNB->check_for_total_transmissions = 0; - gNB->check_for_MUMIMO_transmissions = 0; - gNB->FULL_MUMIMO_transmissions = 0; - gNB->check_for_SUMIMO_transmissions = 0; //fp->pucch_config_common.deltaPUCCH_Shift = 1; } diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index e8828d805c..2dcf035866 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -41,6 +41,13 @@ int nr_phy_init_RU(RU_t *ru) { LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d\n",ru_if_types[ru->if_south],ru->nb_tx); + nfapi_nr_config_request_scf_t *cfg; + ru->nb_log_antennas=0; + for (int n=0;ngNB_config; + if (cfg->carrier_config.num_tx_ant.value > ru->nb_log_antennas) ru->nb_log_antennas = cfg->carrier_config.num_tx_ant.value; + } + AssertFatal(ru->nb_log_antennas > 0 && ru->nb_log_antennas < 13, "ru->nb_log_antennas %d ! \n",ru->nb_log_antennas); if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals // Time-domain signals ru->common.txdata = (int32_t**)malloc16(ru->nb_tx*sizeof(int32_t*)); @@ -75,8 +82,8 @@ int nr_phy_init_RU(RU_t *ru) { // allocate precoding input buffers (TX) - ru->common.txdataF = (int32_t **)malloc16(15*sizeof(int32_t*)); - for(i=0; i< 15; ++i) ru->common.txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP + ru->common.txdataF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t*)); + for(i=0; i< ru->nb_tx; ++i) ru->common.txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP // allocate IFFT input buffers (TX) ru->common.txdataF_BF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t*)); @@ -98,7 +105,6 @@ int nr_phy_init_RU(RU_t *ru) { // AssertFatal(ru->nb_rx <= sizeof(ru->prach_rxsigF) / sizeof(ru->prach_rxsigF[0]), // "nb_antennas_rx too large"); ru->prach_rxsigF = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*)); - for (j=0;j<4;j++) ru->prach_rxsigF_br[j] = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*)); for (i=0; inb_rx; i++) { ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*2*sizeof(int16_t) ); @@ -111,8 +117,8 @@ int nr_phy_init_RU(RU_t *ru) { LOG_E(PHY,"[INIT] %s() RC.nb_nr_L1_inst:%d \n", __FUNCTION__, RC.nb_nr_L1_inst); int beam_count = 0; - if (ru->nb_tx>1) { - for (p=0;pLmax;p++) { + if (ru->nb_log_antennas>1) { + for (p=0;pnb_log_antennas;p++) { if ((fp->L_ssb >> p) & 0x01) beam_count++; } @@ -120,7 +126,7 @@ int nr_phy_init_RU(RU_t *ru) { int l_ind = 0; for (i=0; iLmax;p++) { + for (p=0;pnb_log_antennas;p++) { if ((fp->L_ssb >> p) & 0x01) { ru->beam_weights[i][p] = (int32_t **)malloc16_clear(ru->nb_tx*sizeof(int32_t*)); for (j=0; jnb_tx; j++) { @@ -177,9 +183,6 @@ void nr_phy_free_RU(RU_t *ru) for (i = 0; i < ru->nb_rx; i++) { free_and_zero(ru->prach_rxsigF[i]); } - for (j = 0; j < 4; j++) free_and_zero(ru->prach_rxsigF_br[j]); - free_and_zero(ru->prach_rxsigF); - /* ru->prach_rxsigF_br is not allocated -> don't free */ for (i = 0; i < RC.nb_nr_L1_inst; i++) { for (p = 0; p < 15; p++) { diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index 461f441b2c..4ed5be2119 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -651,17 +651,16 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, int i,j,k,l,slot,symb,q; int eNB_id; int th_id; - int n_ssb_crb=(fp->N_RB_DL-20); - int k_ssb=0; uint32_t ****pusch_dmrs; uint16_t N_n_scid[2] = {0,1}; // [HOTFIX] This is a temporary implementation of scramblingID0 and scramblingID1 which are given by DMRS-UplinkConfig int n_scid; abstraction_flag = 0; fp->nb_antennas_tx = 1; fp->nb_antennas_rx=1; + dmrs_UplinkConfig_t *dmrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig; + ptrs_UplinkConfig_t *ptrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig; printf("Initializing UE vars (abstraction %"PRIu8") for eNB TXant %"PRIu8", UE RXant %"PRIu8"\n",abstraction_flag,fp->nb_antennas_tx,fp->nb_antennas_rx); //LOG_D(PHY,"[MSC_NEW][FRAME 00000][PHY_UE][MOD %02u][]\n", ue->Mod_id+NB_eNB_INST); - nr_init_frame_parms_ue(fp,NR_MU_1,NORMAL,fp->N_RB_DL,n_ssb_crb,k_ssb); phy_init_nr_top(ue); // many memory allocation sizes are hard coded AssertFatal( fp->nb_antennas_rx <= 2, "hard coded allocation for ue_common_vars->dl_ch_estimates[eNB_id]" ); @@ -711,9 +710,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, } //------------- config DMRS parameters--------------// - ue->dmrs_UplinkConfig.pusch_dmrs_type = pusch_dmrs_type1; - ue->dmrs_UplinkConfig.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0; - ue->dmrs_UplinkConfig.pusch_maxLength = pusch_len1; + dmrs_Uplink_Config->pusch_dmrs_type = pusch_dmrs_type1; + dmrs_Uplink_Config->pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0; + dmrs_Uplink_Config->pusch_maxLength = pusch_len1; //-------------------------------------------------// ue->dmrs_DownlinkConfig.pdsch_dmrs_type = pdsch_dmrs_type1; ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition = pdsch_dmrs_pos0; @@ -743,6 +742,23 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, /////////// //////////////////////////////////////////////////////////////////////////////////////////// + /////////////////////////PUSCH PTRS init///////////////////////// + /////////// + + ue->ptrs_configured = 0; // flag to be toggled by RCC + + //------------- config PTRS parameters--------------// + ptrs_Uplink_Config->timeDensity.ptrs_mcs1 = 0; // setting MCS values to 0 indicate abscence of time_density field in the configuration + ptrs_Uplink_Config->timeDensity.ptrs_mcs2 = 0; + ptrs_Uplink_Config->timeDensity.ptrs_mcs3 = 0; + ptrs_Uplink_Config->frequencyDensity.n_rb0 = 0; // setting N_RB values to 0 indicate abscence of frequency_density field in the configuration + ptrs_Uplink_Config->frequencyDensity.n_rb1 = 0; + ptrs_Uplink_Config->resourceElementOffset = 0; + //-------------------------------------------------// + + /////////// + //////////////////////////////////////////////////////////////////////////////////////////// + for (i=0; i<10; i++) ue->tx_power_dBm[i]=-127; @@ -933,7 +949,7 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, ue->init_averaging = 1; // default value until overwritten by RRCConnectionReconfiguration - if (fp->nb_antenna_ports_eNB==2) + if (fp->nb_antenna_ports_gNB==2) ue->pdsch_config_dedicated->p_a = dBm3; else ue->pdsch_config_dedicated->p_a = dB0; @@ -944,7 +960,6 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, // enable MIB/SIB decoding by default ue->decode_MIB = 1; ue->decode_SIB = 1; - ue->ssb_periodicity = 5; // initialization of ssb periodicity to 5ms according to TS38.213 section 4.1 init_prach_tables(839); return 0; } @@ -963,7 +978,7 @@ void init_nr_ue_transport(PHY_VARS_NR_UE *ue, ue->dlsch_SI[i] = new_nr_ue_dlsch(1,1,NSOFT,MAX_LDPC_ITERATIONS,ue->frame_parms.N_RB_DL, abstraction_flag); ue->dlsch_ra[i] = new_nr_ue_dlsch(1,1,NSOFT,MAX_LDPC_ITERATIONS,ue->frame_parms.N_RB_DL, abstraction_flag); - ue->transmission_mode[i] = ue->frame_parms.nb_antenna_ports_eNB==1 ? 1 : 2; + ue->transmission_mode[i] = ue->frame_parms.nb_antenna_ports_gNB==1 ? 1 : 2; } //ue->frame_parms.pucch_config_common.deltaPUCCH_Shift = 1; @@ -990,51 +1005,54 @@ void phy_init_nr_top(PHY_VARS_NR_UE *ue) { void set_default_frame_parms_single(nfapi_nr_config_request_t *config, NR_DL_FRAME_PARMS *frame_parms) { - //int CC_id; - //for (CC_id=0; CC_idsubframe_config.numerology_index_mu.value =1; config->subframe_config.duplex_mode.value = 1; //FDD config->subframe_config.dl_cyclic_prefix_type.value = 0; //NORMAL - config->rf_config.dl_carrier_bandwidth.value = 106; - config->rf_config.ul_carrier_bandwidth.value = 106; + config->rf_config.dl_carrier_bandwidth.value = 100; + config->rf_config.ul_carrier_bandwidth.value = 100; config->sch_config.physical_cell_id.value = 0; + frame_parms->frame_type = FDD; - frame_parms->tdd_config = 3; //frame_parms[CC_id]->tdd_config_S = 0; - frame_parms->N_RB_DL = 100; - frame_parms->N_RB_UL = 100; + frame_parms->N_RB_DL = 106; + frame_parms->N_RB_UL = 106; frame_parms->Ncp = NORMAL; //frame_parms[CC_id]->Ncp_UL = NORMAL; frame_parms->Nid_cell = 0; //frame_parms[CC_id]->num_MBSFN_config = 0; - frame_parms->nb_antenna_ports_eNB = 1; + frame_parms->nb_antenna_ports_gNB = 1; frame_parms->nb_antennas_tx = 1; frame_parms->nb_antennas_rx = 1; + //frame_parms[CC_id]->nushift = 0; + ///frame_parms[CC_id]->phich_config_common.phich_resource = oneSixth; //frame_parms[CC_id]->phich_config_common.phich_duration = normal; + // UL RS Config /*frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift = 1;//n_DMRS1 set to 0 - frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.groupHoppingEnabled = 1; - frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled = 0; - frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH = 0; - - frame_parms[CC_id]->pusch_config_common.n_SB = 1; - frame_parms[CC_id]->pusch_config_common.hoppingMode = 0; - frame_parms[CC_id]->pusch_config_common.pusch_HoppingOffset = 0; - frame_parms[CC_id]->pusch_config_common.enable64QAM = 0; - - frame_parms[CC_id]->prach_config_common.rootSequenceIndex=22; - frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=1; - frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.prach_ConfigIndex=0; - frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.highSpeedFlag=0; - frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.prach_FreqOffset=0;*/ + frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.groupHoppingEnabled = 1; + frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled = 0; + frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH = 0; + + frame_parms[CC_id]->pusch_config_common.n_SB = 1; + frame_parms[CC_id]->pusch_config_common.hoppingMode = 0; + frame_parms[CC_id]->pusch_config_common.pusch_HoppingOffset = 0; + frame_parms[CC_id]->pusch_config_common.enable64QAM = 0; + + frame_parms[CC_id]->prach_config_common.rootSequenceIndex=22; + frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=1; + frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.prach_ConfigIndex=0; + frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.highSpeedFlag=0; + frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.prach_FreqOffset=0;*/ + // NR: Init to legacy LTE 20Mhz params - frame_parms->numerology_index = 0; - frame_parms->ttis_per_subframe = 1; - frame_parms->slots_per_tti = 2; - //} + frame_parms->numerology_index = 0; + frame_parms->ttis_per_subframe = 1; + frame_parms->slots_per_tti = 2; + + } diff --git a/openair1/PHY/INIT/nr_parms.c b/openair1/PHY/INIT/nr_parms.c index a5475a1555..c3fe9c54b1 100644 --- a/openair1/PHY/INIT/nr_parms.c +++ b/openair1/PHY/INIT/nr_parms.c @@ -21,16 +21,20 @@ #include "phy_init.h" #include "common/utils/LOG/log.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" /// Subcarrier spacings in Hz indexed by numerology index uint32_t nr_subcarrier_spacing[MAX_NUM_SUBCARRIER_SPACING] = {15e3, 30e3, 60e3, 120e3, 240e3}; -uint16_t nr_slots_per_subframe[MAX_NUM_SUBCARRIER_SPACING] = {1, 2, 4, 16, 32}; +uint16_t nr_slots_per_subframe[MAX_NUM_SUBCARRIER_SPACING] = {1, 2, 4, 8, 16}; -int nr_get_ssb_start_symbol(NR_DL_FRAME_PARMS *fp, uint8_t i_ssb, uint8_t half_frame_index) + +int nr_get_ssb_start_symbol(NR_DL_FRAME_PARMS *fp) { int mu = fp->numerology_index; + uint8_t half_frame_index = fp->half_frame_bit; + uint8_t i_ssb = fp->ssb_index; int symbol = 0; uint8_t n, n_temp; nr_ssb_type_e type = fp->ssb_type; @@ -79,62 +83,8 @@ int nr_get_ssb_start_symbol(NR_DL_FRAME_PARMS *fp, uint8_t i_ssb, uint8_t half_f return symbol; } -int nr_is_ssb_slot(nfapi_nr_config_request_t *cfg, int slot, int frame) +void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu, uint16_t bw) { - - uint8_t n_hf; - uint16_t p,mu,hf_slots; - uint64_t ssb_map; - int rel_slot; - - mu = cfg->subframe_config.numerology_index_mu.value; - - ssb_map = cfg->sch_config.ssb_scg_position_in_burst.value; - p = cfg->sch_config.ssb_periodicity.value; - n_hf = cfg->sch_config.half_frame_index.value; - - // if SSB periodicity is 5ms, they are transmitted in both half frames - if ( (p>10) && (frame%(p/10)) ) - return 0; - else { - hf_slots = (10<>1; // number of slots per half frame - // if SSB periodicity is 5ms, they are transmitted in both half frames - if ( p == 5) { - if (slot> rel_slot*2) & 0x01) || ((ssb_map >> (1+rel_slot*2)) & 0x01) ); - } -} - - -int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, - int mu, - int Ncp, - int N_RB_DL) - -{ - -#if DISABLE_LOG_X - printf("Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, N_RB_DL, Ncp); -#else - LOG_I(PHY,"Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, N_RB_DL, Ncp); -#endif - - if (Ncp == NFAPI_CP_EXTENDED) - AssertFatal(mu == NR_MU_2,"Invalid cyclic prefix %d for numerology index %d\n", Ncp, mu); - - fp->numerology_index = mu; - fp->Ncp = Ncp; - fp->N_RB_DL = N_RB_DL; - switch(mu) { case NR_MU_0: //15kHz scs @@ -148,24 +98,22 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, fp->slots_per_subframe = nr_slots_per_subframe[NR_MU_1]; // selection of SS block pattern according to TS 38101-1 Table 5.4.3.3-1 for SCS 30kHz - if (fp->eutra_band == 5 || fp->eutra_band == 66) - fp->ssb_type = nr_ssb_type_B; + if (fp->nr_band == 5 || fp->nr_band == 66) + fp->ssb_type = nr_ssb_type_B; else{ - if (fp->eutra_band == 41 || ( fp->eutra_band > 76 && fp->eutra_band < 80) ) - fp->ssb_type = nr_ssb_type_C; + if (fp->nr_band == 41 || ( fp->nr_band > 76 && fp->nr_band < 80) ) + fp->ssb_type = nr_ssb_type_C; else - AssertFatal(1==0,"NR Operating Band n%d not available for SS block SCS with mu=%d\n", fp->eutra_band, mu); + AssertFatal(1==0,"NR Operating Band n%d not available for SS block SCS with mu=%d\n", fp->nr_band, mu); } - switch(N_RB_DL){ - case 11: - case 24: - case 38: - case 78: - case 51: - case 65: - - case 106: //40 MHz + switch(bw){ + case 5: + case 15: + case 20: + case 25: + case 30: + case 40: //40 MHz if (fp->threequarter_fs) { fp->ofdm_symbol_size = 1536; fp->first_carrier_offset = 900; //1536 - ( (106*12) / 2 ) @@ -180,11 +128,11 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, } break; - case 133: - case 162: - case 189: + case 50: + case 60: + case 70: - case 217: //80 MHz + case 80: //80 MHz if (fp->threequarter_fs) { fp->ofdm_symbol_size = 3072; fp->first_carrier_offset = 1770; //3072 - ( (217*12) / 2 ) @@ -199,22 +147,22 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, } break; - case 245: - AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for N_RB %d and MU %d\n",N_RB_DL,mu); + case 90: + AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for %d MHz band and MU %d\n",bw,mu); fp->ofdm_symbol_size = 4096; fp->first_carrier_offset = 2626; //4096 - ( (245*12) / 2 ) fp->nb_prefix_samples0 = 352; fp->nb_prefix_samples = 288; break; - case 273: - AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for N_RB %d and MU %d\n",N_RB_DL,mu); + case 100: + AssertFatal(fp->threequarter_fs==0,"3/4 sampling impossible for %d MHz band and MU %d\n",bw,mu); fp->ofdm_symbol_size = 4096; fp->first_carrier_offset = 2458; //4096 - ( (273*12) / 2 ) fp->nb_prefix_samples0 = 352; fp->nb_prefix_samples = 288; break; default: - AssertFatal(1==0,"Number of resource blocks %d undefined for mu %d, frame parms = %p\n", N_RB_DL, mu, fp); + AssertFatal(1==0,"%d MHz band undefined for mu %d, frame parms = %p\n", bw, mu, fp); } break; @@ -222,21 +170,21 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, fp->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_2]; fp->slots_per_subframe = nr_slots_per_subframe[NR_MU_2]; - switch(N_RB_DL){ //FR1 bands only - case 11: - case 18: - case 38: - case 24: - case 31: - case 51: - case 65: - case 79: - case 93: - case 107: - case 121: - case 135: + switch(bw){ //FR1 bands only + case 10: + case 15: + case 20: + case 25: + case 30: + case 40: + case 50: + case 60: + case 70: + case 80: + case 90: + case 100: default: - AssertFatal(1==0,"Number of resource blocks %d undefined for mu %d, frame parms = %p\n", N_RB_DL, mu, fp); + AssertFatal(1==0,"%d MHz band undefined for mu %d, frame parms = %p\n", bw, mu, fp); } break; @@ -244,6 +192,22 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, fp->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_3]; fp->slots_per_subframe = nr_slots_per_subframe[NR_MU_3]; fp->ssb_type = nr_ssb_type_D; + switch(bw){ + case 100: + fp->ofdm_symbol_size = 1024; + fp->first_carrier_offset = 628; //1024 - ( (66*12) / 2 ) + fp->nb_prefix_samples0 = 136; + fp->nb_prefix_samples = 72; + break; + case 50: + fp->ofdm_symbol_size = 512; + fp->first_carrier_offset = 320; //1024 - ( (66*12) / 2 ) + fp->nb_prefix_samples0 = 68; + fp->nb_prefix_samples = 36; + break; + default: + AssertFatal(1==0,"%d MHz band undefined for mu %d, frame parms = %p\n", bw, mu, fp); + } break; case NR_MU_4: @@ -255,10 +219,63 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, default: AssertFatal(1==0,"Invalid numerology index %d", mu); } +} + +uint32_t get_samples_per_slot(int slot, NR_DL_FRAME_PARMS* fp) +{ + uint32_t samp_count; + + if(fp->numerology_index == 0) + samp_count = fp->samples_per_subframe; + else + samp_count = (slot%(fp->slots_per_subframe/2)) ? fp->samples_per_slotN0 : fp->samples_per_slot0; + + return samp_count; +} + +uint32_t get_samples_slot_timestamp(int slot, NR_DL_FRAME_PARMS* fp, uint8_t sl_ahead) +{ + uint32_t samp_count = 0; + + if(!sl_ahead) { + for(uint8_t idx_slot = 0; idx_slot < slot; idx_slot++) + samp_count += fp->get_samples_per_slot(idx_slot, fp); + } else { + for(uint8_t idx_slot = slot; idx_slot < slot+sl_ahead; idx_slot++) + samp_count += fp->get_samples_per_slot(idx_slot, fp); + } + return samp_count; +} + +int nr_init_frame_parms(nfapi_nr_config_request_scf_t* cfg, + NR_DL_FRAME_PARMS *fp) +{ + + fp->frame_type = cfg->cell_config.frame_duplex_type.value; + fp->L_ssb = (((uint64_t) cfg->ssb_table.ssb_mask_list[0].ssb_mask.value)<<32) | cfg->ssb_table.ssb_mask_list[1].ssb_mask.value ; + fp->N_RB_DL = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value; + fp->N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value; + + int Ncp = NFAPI_CP_NORMAL; + int mu = cfg!= NULL ? cfg->ssb_config.scs_common.value : 0; + +#if DISABLE_LOG_X + printf("Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, fp->N_RB_DL, Ncp); +#else + LOG_I(PHY,"Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, fp->N_RB_DL, Ncp); +#endif + + if (Ncp == NFAPI_CP_EXTENDED) + AssertFatal(mu == NR_MU_2,"Invalid cyclic prefix %d for numerology index %d\n", Ncp, mu); + + fp->half_frame_bit = 0; // half frame bit initialized to 0 here + fp->numerology_index = mu; + + set_scs_parameters(fp, mu, cfg->carrier_config.dl_bandwidth.value); fp->slots_per_frame = 10* fp->slots_per_subframe; - fp->nb_antenna_ports_eNB = 1; // default value until overwritten by RRCConnectionReconfiguration + fp->nb_antenna_ports_gNB = 1; // default value until overwritten by RRCConnectionReconfiguration fp->nb_antennas_rx = 1; // default value until overwritten by RRCConnectionReconfiguration fp->nb_antennas_tx = 1; // default value until overwritten by RRCConnectionReconfiguration @@ -266,12 +283,17 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, fp->samples_per_subframe_wCP = fp->ofdm_symbol_size * fp->symbols_per_slot * fp->slots_per_subframe; fp->samples_per_frame_wCP = 10 * fp->samples_per_subframe_wCP; fp->samples_per_slot_wCP = fp->symbols_per_slot*fp->ofdm_symbol_size; - fp->samples_per_slot = fp->nb_prefix_samples0 + ((fp->symbols_per_slot-1)*fp->nb_prefix_samples) + (fp->symbols_per_slot*fp->ofdm_symbol_size); - fp->samples_per_subframe = (fp->samples_per_subframe_wCP + (fp->nb_prefix_samples0 * fp->slots_per_subframe) + - (fp->nb_prefix_samples * fp->slots_per_subframe * (fp->symbols_per_slot - 1))); + fp->samples_per_slotN0 = (fp->nb_prefix_samples + fp->ofdm_symbol_size) * fp->symbols_per_slot; + fp->samples_per_slot0 = fp->nb_prefix_samples0 + ((fp->symbols_per_slot-1)*fp->nb_prefix_samples) + (fp->symbols_per_slot*fp->ofdm_symbol_size); + fp->samples_per_subframe = (fp->nb_prefix_samples0 + fp->ofdm_symbol_size) * 2 + + (fp->nb_prefix_samples + fp->ofdm_symbol_size) * (fp->symbols_per_slot * fp->slots_per_subframe - 2); + fp->get_samples_per_slot = &get_samples_per_slot; + fp->get_samples_slot_timestamp = &get_samples_slot_timestamp; fp->samples_per_frame = 10 * fp->samples_per_subframe; fp->freq_range = (fp->dl_CarrierFreq < 6e9)? nr_FR1 : nr_FR2; + fp->Ncp = Ncp; + // definition of Lmax according to ts 38.213 section 4.1 if (fp->dl_CarrierFreq < 6e9) { if(fp->frame_type && (fp->ssb_type==2)) @@ -283,35 +305,92 @@ int nr_init_frame_parms0(NR_DL_FRAME_PARMS *fp, } fp->N_ssb = 0; - for (int p=0; pLmax; p++) + int num_tx_ant = (cfg == NULL) ? fp->Lmax : cfg->carrier_config.num_tx_ant.value; + + for (int p=0; pN_ssb += ((fp->L_ssb >> p) & 0x01); return 0; -} -int nr_init_frame_parms(nfapi_nr_config_request_t* config, - NR_DL_FRAME_PARMS *fp) -{ - - fp->eutra_band = config->nfapi_config.rf_bands.rf_band[0]; - fp->frame_type = config->subframe_config.duplex_mode.value; - fp->L_ssb = config->sch_config.ssb_scg_position_in_burst.value; - return nr_init_frame_parms0(fp, - config->subframe_config.numerology_index_mu.value, - config->subframe_config.dl_cyclic_prefix_type.value, - config->rf_config.dl_carrier_bandwidth.value); } int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp, - int mu, - int Ncp, - int N_RB_DL, - int n_ssb_crb, - int ssb_subcarrier_offset) + fapi_nr_config_request_t* config, + int Ncp) { - /*n_ssb_crb and ssb_subcarrier_offset are given in 15kHz SCS*/ - nr_init_frame_parms0(fp,mu,Ncp,N_RB_DL); - fp->ssb_start_subcarrier = (12 * n_ssb_crb + ssb_subcarrier_offset)/(1<carrier_config.dl_grid_size[config->ssb_config.scs_common])*(15<ssb_config.scs_common); + fp->dl_CarrierFreq = ((dl_bw_khz>>1) + config->carrier_config.dl_frequency)*1000 ; + + uint64_t ul_bw_khz = (12*config->carrier_config.ul_grid_size[config->ssb_config.scs_common])*(15<ssb_config.scs_common); + fp->ul_CarrierFreq = ((ul_bw_khz>>1) + config->carrier_config.uplink_frequency)*1000 ; + + fp->numerology_index = config->ssb_config.scs_common; + fp->N_RB_UL = config->carrier_config.ul_grid_size[fp->numerology_index]; + fp->N_RB_DL = config->carrier_config.dl_grid_size[fp->numerology_index]; + + int32_t uplink_frequency_offset = 0; + + get_band(fp->dl_CarrierFreq, &fp->nr_band, &uplink_frequency_offset, &fp->frame_type); + + AssertFatal(fp->frame_type==config->cell_config.frame_duplex_type, "Invalid duplex type in config request file for band %d\n", fp->nr_band); + AssertFatal(fp->ul_CarrierFreq==(fp->dl_CarrierFreq+uplink_frequency_offset), "Disagreement in uplink frequency for band %d\n", fp->nr_band); + +#if DISABLE_LOG_X + printf("Initializing UE frame parms for mu %d, N_RB %d, Ncp %d\n",fp->numerology_index, fp->N_RB_DL, Ncp); +#else + LOG_I(PHY,"Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",fp->numerology_index, fp->N_RB_DL, Ncp); +#endif + + if (Ncp == NFAPI_CP_EXTENDED) + AssertFatal(fp->numerology_index == NR_MU_2,"Invalid cyclic prefix %d for numerology index %d\n", Ncp, fp->numerology_index); + + fp->Ncp = Ncp; + + set_scs_parameters(fp,fp->numerology_index,config->carrier_config.dl_bandwidth); + + fp->slots_per_frame = 10* fp->slots_per_subframe; + + fp->nb_antenna_ports_gNB = 1; // default value until overwritten by RRCConnectionReconfiguration + fp->nb_antennas_rx = 1; // default value until overwritten by RRCConnectionReconfiguration + fp->nb_antennas_tx = 1; // default value until overwritten by RRCConnectionReconfiguration + + fp->symbols_per_slot = ((Ncp == NORMAL)? 14 : 12); // to redefine for different slot formats + fp->samples_per_subframe_wCP = fp->ofdm_symbol_size * fp->symbols_per_slot * fp->slots_per_subframe; + fp->samples_per_frame_wCP = 10 * fp->samples_per_subframe_wCP; + fp->samples_per_slot_wCP = fp->symbols_per_slot*fp->ofdm_symbol_size; + fp->samples_per_slotN0 = (fp->nb_prefix_samples + fp->ofdm_symbol_size) * fp->symbols_per_slot; + fp->samples_per_slot0 = fp->nb_prefix_samples0 + ((fp->symbols_per_slot-1)*fp->nb_prefix_samples) + (fp->symbols_per_slot*fp->ofdm_symbol_size); + fp->samples_per_subframe = (fp->nb_prefix_samples0 + fp->ofdm_symbol_size) * 2 + + (fp->nb_prefix_samples + fp->ofdm_symbol_size) * (fp->symbols_per_slot * fp->slots_per_subframe - 2); + fp->get_samples_per_slot = &get_samples_per_slot; + fp->get_samples_slot_timestamp = &get_samples_slot_timestamp; + fp->samples_per_frame = 10 * fp->samples_per_subframe; + fp->freq_range = (fp->dl_CarrierFreq < 6e9)? nr_FR1 : nr_FR2; + + uint8_t sco = 0; + if (((fp->freq_range == nr_FR1) && (config->ssb_table.ssb_subcarrier_offset<24)) || + ((fp->freq_range == nr_FR2) && (config->ssb_table.ssb_subcarrier_offset<12)) ) + sco = config->ssb_table.ssb_subcarrier_offset; + + fp->ssb_start_subcarrier = (12 * config->ssb_table.ssb_offset_point_a + sco); + + // definition of Lmax according to ts 38.213 section 4.1 + if (fp->dl_CarrierFreq < 6e9) { + if(fp->frame_type && (fp->ssb_type==2)) + fp->Lmax = (fp->dl_CarrierFreq < 2.4e9)? 4 : 8; + else + fp->Lmax = (fp->dl_CarrierFreq < 3e9)? 4 : 8; + } else { + fp->Lmax = 64; + } + + fp->L_ssb = (((uint64_t) config->ssb_table.ssb_mask_list[1].ssb_mask)<<32) | config->ssb_table.ssb_mask_list[1].ssb_mask; + + fp->N_ssb = 0; + for (int p=0; pLmax; p++) + fp->N_ssb += ((fp->L_ssb >> p) & 0x01); + return 0; } @@ -326,8 +405,8 @@ void nr_dump_frame_parms(NR_DL_FRAME_PARMS *fp) LOG_I(PHY,"fp->samples_per_frame_wCP=%d\n",fp->samples_per_frame_wCP); LOG_I(PHY,"fp->samples_per_subframe=%d\n",fp->samples_per_subframe); LOG_I(PHY,"fp->samples_per_frame=%d\n",fp->samples_per_frame); - LOG_I(PHY,"fp->dl_CarrierFreq=%u\n",fp->dl_CarrierFreq); - LOG_I(PHY,"fp->ul_CarrierFreq=%u\n",fp->ul_CarrierFreq); + LOG_I(PHY,"fp->dl_CarrierFreq=%lu\n",fp->dl_CarrierFreq); + LOG_I(PHY,"fp->ul_CarrierFreq=%lu\n",fp->ul_CarrierFreq); } diff --git a/openair1/PHY/INIT/phy_init.h b/openair1/PHY/INIT/phy_init.h index 05d3b6c73f..1862d5f8e0 100644 --- a/openair1/PHY/INIT/phy_init.h +++ b/openair1/PHY/INIT/phy_init.h @@ -392,10 +392,9 @@ void phy_config_update_sib13_request(PHY_Config_t *phy_config); int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms,uint8_t osf); void dump_frame_parms(LTE_DL_FRAME_PARMS *frame_parms); -int nr_get_ssb_start_symbol(NR_DL_FRAME_PARMS *fp, uint8_t i_ssb, uint8_t half_frame_index); -int nr_is_ssb_slot(nfapi_nr_config_request_t *cfg, int slot, int frame); -int nr_init_frame_parms(nfapi_nr_config_request_t *config, NR_DL_FRAME_PARMS *frame_parms); -int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *frame_parms,int mu,int Ncp,int N_RB_DL,int n_ssb_crb,int ssb_subcarrier_offset); +int nr_get_ssb_start_symbol(NR_DL_FRAME_PARMS *fp); +int nr_init_frame_parms(nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms); +int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *frame_parms,fapi_nr_config_request_t *config,int Ncp); int init_nr_ue_signal(PHY_VARS_NR_UE *ue,int nb_connected_eNB,uint8_t abstraction_flag); void init_nr_ue_transport(PHY_VARS_NR_UE *ue,int abstraction_flag); void nr_dump_frame_parms(NR_DL_FRAME_PARMS *frame_parms); diff --git a/openair1/PHY/MODULATION/modulation_UE.h b/openair1/PHY/MODULATION/modulation_UE.h index 1199a91baa..228299095f 100644 --- a/openair1/PHY/MODULATION/modulation_UE.h +++ b/openair1/PHY/MODULATION/modulation_UE.h @@ -54,6 +54,12 @@ int nr_slot_fep(PHY_VARS_NR_UE *phy_vars_ue, int sample_offset, int no_prefix); +int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, + unsigned char symbol, + unsigned char Ns, + int sample_offset, + int no_prefix); + int slot_fep_mbsfn(PHY_VARS_UE *phy_vars_ue, unsigned char l, int subframe, diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index 57bca9e2ec..5c8fce3c38 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -51,9 +51,10 @@ void nr_modulation(uint32_t *in, } void nr_layer_mapping(int16_t **mod_symbs, - uint8_t n_layers, - uint16_t n_symbs, - int16_t **tx_layers) { + uint8_t n_layers, + uint16_t n_symbs, + int16_t **tx_layers) { + LOG_D(PHY,"Doing layer mapping for %d layers, %d symbols\n",n_layers,n_symbs); switch (n_layers) { diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 11aaf1f78e..f2e5d24bad 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -46,6 +46,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, unsigned char aa; unsigned int nb_prefix_samples; unsigned int nb_prefix_samples0; + unsigned int abs_symbol; if (ue->is_synchronized) { nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples); nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples0); @@ -109,7 +110,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, if (no_prefix) { slot_offset = frame_parms->ofdm_symbol_size * (frame_parms->symbols_per_slot) * (Ns); } else { - slot_offset = (frame_parms->samples_per_slot) * (Ns); + slot_offset = frame_parms->get_samples_slot_timestamp(Ns,frame_parms,0); } /*if (l<0 || l>=7-frame_parms->Ncp) { @@ -117,15 +118,15 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, return(-1); }*/ - if (Ns<0 || Ns>=20) { - printf("slot_fep: Ns must be between 0 and 19\n"); + if (Ns<0 || Ns>(frame_parms->slots_per_frame-1)) { + printf("slot_fep: Ns must be between 0 and %d\n",frame_parms->slots_per_frame-1); return(-1); } for (aa=0; aanb_antennas_rx; aa++) { memset(&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],0,frame_parms->ofdm_symbol_size*sizeof(int)); - rx_offset = sample_offset + slot_offset + nb_prefix_samples0 - SOFFSET; + rx_offset = sample_offset + slot_offset - SOFFSET; // Align with 256 bit // rx_offset = rx_offset&0xfffffff8; @@ -135,8 +136,16 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, ue->proc.proc_rxtx[(Ns)&1].frame_rx, Ns, symbol, nb_prefix_samples, nb_prefix_samples0, slot_offset, sample_offset, rx_offset, frame_length_samples); #endif - if (symbol==0) { + abs_symbol = Ns * frame_parms->symbols_per_slot + symbol; + + for (int idx_symb = Ns*frame_parms->symbols_per_slot; idx_symb < abs_symbol; idx_symb++) + rx_offset += (idx_symb%(0x7<numerology_index)) ? nb_prefix_samples : nb_prefix_samples0; + rx_offset += frame_parms->ofdm_symbol_size * symbol; + + if (abs_symbol%(0x7<numerology_index)) { + + rx_offset += nb_prefix_samples; if (rx_offset > (frame_length_samples - frame_parms->ofdm_symbol_size)) memcpy((short*) &common_vars->rxdata[aa][frame_length_samples], (short*) &common_vars->rxdata[aa][0], @@ -161,9 +170,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, } } else { - rx_offset += (frame_parms->ofdm_symbol_size+nb_prefix_samples)*symbol; - // + (frame_parms->ofdm_symbol_size+nb_prefix_samples)*(l-1); - + rx_offset += nb_prefix_samples0; if (rx_offset > (frame_length_samples - frame_parms->ofdm_symbol_size)) memcpy((void *) &common_vars->rxdata[aa][frame_length_samples], (void *) &common_vars->rxdata[aa][0], @@ -197,6 +204,181 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, } +#ifdef DEBUG_FEP + printf("slot_fep: done\n"); +#endif + return(0); +} + +int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, + unsigned char symbol, + unsigned char Ns, + int sample_offset, + int no_prefix) +{ + NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms; + NR_UE_COMMON *common_vars = &ue->common_vars; + unsigned char aa; + unsigned int nb_prefix_samples; + unsigned int nb_prefix_samples0; + unsigned int abs_symbol; + if (ue->is_synchronized) { + nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples); + nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples0); + } + else { + nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples); + nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples); + } + //unsigned int subframe_offset;//,subframe_offset_F; + unsigned int slot_offset; + //int i; + unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10; + unsigned int rx_offset; + + + void (*dft)(int16_t *,int16_t *, int); + int tmp_dft_in[8192] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs + + switch (frame_parms->ofdm_symbol_size) { + case 128: + dft = dft128; + break; + + case 256: + dft = dft256; + break; + + case 512: + dft = dft512; + break; + + case 1024: + dft = dft1024; + break; + + case 1536: + dft = dft1536; + break; + + case 2048: + dft = dft2048; + break; + + case 3072: + dft = dft3072; + break; + + case 4096: + dft = dft4096; + break; + + case 8192: + dft = dft8192; + break; + + default: + printf("unsupported ofdm symbol size \n"); + assert(0); + } + + if (no_prefix) { + slot_offset = frame_parms->ofdm_symbol_size * (frame_parms->symbols_per_slot) * (Ns); + } else { + slot_offset = frame_parms->get_samples_slot_timestamp(Ns,frame_parms,0); + } + + /*if (l<0 || l>=7-frame_parms->Ncp) { + printf("slot_fep: l must be between 0 and %d\n",7-frame_parms->Ncp); + return(-1); + }*/ + + if (Ns<0 || Ns>(frame_parms->slots_per_frame-1)) { + printf("slot_fep: Ns must be between 0 and %d\n",frame_parms->slots_per_frame-1); + return(-1); + } + + for (aa=0; aanb_antennas_rx; aa++) { + memset(&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],0,frame_parms->ofdm_symbol_size*sizeof(int)); + + rx_offset = sample_offset + slot_offset - SOFFSET; + // Align with 256 bit + // rx_offset = rx_offset&0xfffffff8; + +#ifdef DEBUG_FEP + // if (ue->frame <100) + /*LOG_I(PHY,*/printf("slot_fep: frame %d: slot %d, symbol %d, nb_prefix_samples %u, nb_prefix_samples0 %u, slot_offset %u, sample_offset %d,rx_offset %u, frame_length_samples %u\n", + ue->proc.proc_rxtx[(Ns)&1].frame_rx, Ns, symbol, nb_prefix_samples, nb_prefix_samples0, slot_offset, sample_offset, rx_offset, frame_length_samples); +#endif + + abs_symbol = Ns * frame_parms->symbols_per_slot + symbol; + + for (int idx_symb = Ns*frame_parms->symbols_per_slot; idx_symb < abs_symbol; idx_symb++) + rx_offset += (abs_symbol%(0x7<numerology_index)) ? nb_prefix_samples : nb_prefix_samples0; + + rx_offset += frame_parms->ofdm_symbol_size * symbol; + + if (abs_symbol%(0x7<numerology_index)) { + + rx_offset += nb_prefix_samples; + if (rx_offset > (frame_length_samples - frame_parms->ofdm_symbol_size)) + memcpy((short*) &common_vars->rxdata[aa][frame_length_samples], + (short*) &common_vars->rxdata[aa][0], + frame_parms->ofdm_symbol_size*sizeof(int)); + + if ((rx_offset&7)!=0) { // if input to dft is not 256-bit aligned, issue for size 6,15 and 25 PRBs + memcpy((void *)tmp_dft_in, + (void *) &common_vars->rxdata[aa][rx_offset], + frame_parms->ofdm_symbol_size*sizeof(int)); + dft((int16_t *)tmp_dft_in, + (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); + } else { // use dft input from RX buffer directly +#if UE_TIMING_TRACE + start_meas(&ue->rx_dft_stats); +#endif + + dft((int16_t *) &common_vars->rxdata[aa][rx_offset], + (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); +#if UE_TIMING_TRACE + stop_meas(&ue->rx_dft_stats); +#endif + } + } else { + + rx_offset += nb_prefix_samples0; + if (rx_offset > (frame_length_samples - frame_parms->ofdm_symbol_size)) + memcpy((void *) &common_vars->rxdata[aa][frame_length_samples], + (void *) &common_vars->rxdata[aa][0], + frame_parms->ofdm_symbol_size*sizeof(int)); +#if UE_TIMING_TRACE + start_meas(&ue->rx_dft_stats); +#endif + + if ((rx_offset&7)!=0) { // if input to dft is not 128-bit aligned, issue for size 6 and 15 PRBs + memcpy((void *)tmp_dft_in, + (void *) &common_vars->rxdata[aa][rx_offset], + frame_parms->ofdm_symbol_size*sizeof(int)); + dft((int16_t *)tmp_dft_in, + (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); + } else { // use dft input from RX buffer directly + + dft((int16_t *) &common_vars->rxdata[aa][rx_offset], + (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); + } +#if UE_TIMING_TRACE + stop_meas(&ue->rx_dft_stats); +#endif + + + } + + #ifdef DEBUG_FEP + // if (ue->frame <100) + printf("slot_fep: frame %d: symbol %d rx_offset %u\n", ue->proc.proc_rxtx[(Ns)&1].frame_rx, symbol, rx_offset); + #endif + } + + #ifdef DEBUG_FEP printf("slot_fep: done\n"); #endif @@ -258,7 +440,7 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, break; } - slot_offset = Ns * frame_parms->samples_per_slot; + slot_offset = frame_parms->get_samples_slot_timestamp(Ns,frame_parms,0); if(symbol == 0) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index ab6ccd929b..0d7732599f 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -31,22 +31,19 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, - uint8_t gNB_offset, unsigned char Ns, unsigned short p, unsigned char symbol, unsigned short bwp_start_subcarrier, - unsigned short nb_rb_pusch, - dmrs_UplinkConfig_t *dmrs_UplinkConfig) -{ + nfapi_nr_pusch_pdu_t *pusch_pdu) { + int pilot[3280] __attribute__((aligned(16))); unsigned char aarx; unsigned short k; unsigned int pilot_cnt,re_cnt; int16_t ch[2],ch_r[2],ch_l[2],*pil,*rxF,*ul_ch; int16_t *fl,*fm,*fr,*fml,*fmr,*fmm,*fdcl,*fdcr,*fdclh,*fdcrh; - int ch_offset,symbol_offset, length_dmrs, UE_id = 0; - unsigned short n_idDMRS[2] = {0,1}; //to update from pusch config + int ch_offset,symbol_offset, UE_id = 0; int32_t **ul_ch_estimates_time = gNB->pusch_vars[UE_id]->ul_ch_estimates_time; __m128i *ul_ch_128; @@ -71,9 +68,11 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, k = bwp_start_subcarrier; int re_offset = k; + uint16_t nb_rb_pusch = pusch_pdu->rb_size; + /* #ifdef DEBUG_CH - printf("PUSCH Channel Estimation : gNB_offset %d ch_offset %d, symbol_offset %d OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n", gNB_offset,ch_offset,symbol_offset,gNB->frame_parms.ofdm_symbol_size, + printf("PUSCH Channel Estimation : ch_offset %d, symbol_offset %d OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n", ,ch_offset,symbol_offset,gNB->frame_parms.ofdm_symbol_size, gNB->frame_parms.Ncp,l,Ns,k, symbol); #endif */ @@ -117,21 +116,17 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// - length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; - - nr_gold_pusch(gNB, symbol, n_idDMRS, length_dmrs); - - nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch[gNB_offset][Ns][0], &pilot[0], 1000, 0, nb_rb_pusch, dmrs_UplinkConfig->pusch_dmrs_type); + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->dmrs_config_type); //------------------------------------------------// for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { - pil = (int16_t *)&pilot[0]; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)]; - ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; + pil = (int16_t *)&pilot[0]; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)]; + ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; - memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size)); + memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size)); #ifdef DEBUG_PUSCH printf("ch est pilot addr %p RB_DL %d\n",&pilot[0], gNB->frame_parms.N_RB_UL); @@ -141,8 +136,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #endif //if ((gNB->frame_parms.N_RB_UL&1)==0) { - - if (dmrs_UplinkConfig->pusch_dmrs_type == pusch_dmrs_type1){ + if (pusch_pdu->dmrs_config_type == pusch_dmrs_type1){ // Treat first 2 pilots specially (left edge) ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); @@ -237,10 +231,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, } // Treat first 2 pilots specially (right edge) - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH - printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); #endif multadd_real_vector_complex_scalar(fm, ch, diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h b/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h index cc84f2292c..a7789c9224 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h @@ -39,14 +39,12 @@ \param nb_rb_pusch, number of allocated RBs for this UE */ - int32_t nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, - uint8_t gNB_offset, - unsigned char Ns, - unsigned short p, - unsigned char symbol, - unsigned short bwp_start_subcarrier, - unsigned short nb_rb_pusch, - dmrs_UplinkConfig_t *dmrs_UplinkConfig); +int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, + unsigned char Ns, + unsigned short p, + unsigned char symbol, + unsigned short bwp_start_subcarrier, + nfapi_nr_pusch_pdu_t *pusch_pdu); int nr_est_timing_advance_pusch(PHY_VARS_gNB* phy_vars_gNB, int UE_id); diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c index 67118f35a9..ed37a79d0f 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.c +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c @@ -128,22 +128,21 @@ uint8_t is_dmrs_symbol(uint8_t l, uint16_t n, uint8_t delta, uint8_t duration_in_symbols, - dmrs_UplinkConfig_t *dmrs_UplinkConfig, - uint8_t mapping_type, + uint8_t dmrs_type, uint16_t ofdm_symbol_size) { - uint8_t is_dmrs_freq, is_dmrs_time, dmrs_type, l0; + uint8_t is_dmrs_freq, is_dmrs_time, l0; int32_t l_prime_mask; - pusch_dmrs_AdditionalPosition_t additional_pos; + pusch_dmrs_AdditionalPosition_t additional_pos = pusch_dmrs_pos0; + pusch_maxLength_t pusch_maxLength = pusch_len1; + uint8_t mapping_type = typeB; is_dmrs_freq = 0; is_dmrs_time = 0; - dmrs_type = dmrs_UplinkConfig->pusch_dmrs_type; - additional_pos = dmrs_UplinkConfig->pusch_dmrs_AdditionalPosition; l0 = get_l0_ul(mapping_type, 2); - l_prime_mask = get_l_prime(duration_in_symbols, mapping_type, additional_pos, dmrs_UplinkConfig->pusch_maxLength); + l_prime_mask = get_l_prime(duration_in_symbols, mapping_type, additional_pos, pusch_maxLength); if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%ofdm_symbol_size)) is_dmrs_freq = 1; @@ -157,7 +156,7 @@ uint8_t is_dmrs_symbol(uint8_t l, } else if ( (l==l0) || (((l_prime_mask>>l)&1) == 1 && l!=0) ) is_dmrs_time = 1; - if (dmrs_UplinkConfig->pusch_maxLength == pusch_len2){ + if (pusch_maxLength == pusch_len2){ if (((l_prime_mask>>(l-1))&1) == 1 && l!=0 && l!=1) is_dmrs_time = 1; diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.h b/openair1/PHY/NR_REFSIG/dmrs_nr.h index de77a8a6ce..f1dfffff8b 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.h +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.h @@ -66,8 +66,7 @@ uint8_t is_dmrs_symbol(uint8_t l, uint16_t n, uint8_t delta, uint8_t duration_in_symbols, - dmrs_UplinkConfig_t *dmrs_UplinkConfig, - uint8_t mapping_type, + uint8_t dmrs_type, uint16_t ofdm_symbol_size); #undef EXTERN diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c index 48fcd04a0f..472d03e649 100644 --- a/openair1/PHY/NR_REFSIG/nr_gold.c +++ b/openair1/PHY/NR_REFSIG/nr_gold.c @@ -26,11 +26,11 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB) unsigned int x1, x2; uint16_t Nid, i_ssb, i_ssb2; unsigned char Lmax, l, n_hf, N_hf; - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; uint8_t reset; - Nid = cfg->sch_config.physical_cell_id.value; + Nid = cfg->cell_config.phy_cell_id.value; Lmax = fp->Lmax; N_hf = (Lmax == 4)? 2:1; @@ -65,7 +65,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) for (uint8_t symb=0; symbsymbols_per_slot; symb++) { reset = 1; - x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1) + (Nid<<1)); + x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1)) + (Nid<<1); for (uint32_t n=0; nsymbols_per_slot; symb++) { reset = 1; x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid)); + LOG_D(PHY,"DMRS slot %d, symb %d x2 %x\n",slot,symb,x2); for (uint32_t n=0; nframe_parms; + unsigned short l; for (nscid=0; nscid<2; nscid++) { - if (n_idDMRS) - nid = n_idDMRS[nscid]; - else - nid = gNB->frame_parms.Nid_cell; - - //printf("gold pdsch nid %d lbar %d\n",nid,lbar); - - for (ns=0; ns<20; ns++) { - - for (l=0; l>1) ^ (x2>>2) ^ (x2>>3))<<31); - - // skip first 50 double words (1600 bits) - for (n=1; n<50; n++) { - x1 = (x1>>1) ^ (x1>>4); - x1 = x1 ^ (x1<<31) ^ (x1<<28); - x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4); - x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28); - //printf("x1 : %x, x2 : %x\n",x1,x2); - } + nid = Nid[nscid]; + for (ns=0; nsslots_per_frame; ns++) { + for (l=0; lsymbols_per_slot; l++) { + reset = 1; + x2 = ((1<<17) * (fp->symbols_per_slot*ns+l+1) * ((nid<<1)+1) +((nid<<1)+nscid)); + LOG_D(PHY,"DMRS slot %d, symb %d x2 %x\n",ns,l,x2); for (n=0; n>1) ^ (x1>>4); - x1 = x1 ^ (x1<<31) ^ (x1<<28); - x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4); - x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28); - gNB->nr_gold_pusch[nscid][ns][l][n] = x1^x2; - // if ((ns==2)&&(l==0)) - //printf("n=%d : c %x\n",n,x1^x2); + gNB->nr_gold_pusch_dmrs[nscid][ns][l][n] = lte_gold_generic(&x1, &x2, reset); + reset = 0; } - } } } -} \ No newline at end of file +} diff --git a/openair1/PHY/NR_REFSIG/nr_gold_ue.c b/openair1/PHY/NR_REFSIG/nr_gold_ue.c index 9793899dd4..39ab13b1f1 100644 --- a/openair1/PHY/NR_REFSIG/nr_gold_ue.c +++ b/openair1/PHY/NR_REFSIG/nr_gold_ue.c @@ -100,7 +100,7 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue, x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4); x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28); ue->nr_gold_pdcch[0][ns][l][n] = x1^x2; - //printf("n=%d : c %x\n",n,x1^x2); + // if (ns==1 && l==0) printf("n=%d : c %x\n",n,x1^x2); } } } @@ -133,7 +133,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue, x2tmp0 = ((14*ns+(lbar+l)+1)*((nid<<1)+1))<<17; x2 = (x2tmp0+(nid<<1)+nscid)%(1<<31); //cinit - + LOG_D(PHY,"UE DMRS slot %d, symb %d, lbar %d, x2 %x, nscid %d\n",ns,l,lbar,x2,nscid); //printf("ns %d gold pdsch x2 %d\n",ns,x2); x1 = 1+ (1<<31); diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h index 754edfef64..5af0e88099 100644 --- a/openair1/PHY/NR_REFSIG/nr_refsig.h +++ b/openair1/PHY/NR_REFSIG/nr_refsig.h @@ -39,7 +39,7 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB); void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid); void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid); -void nr_gold_pusch(PHY_VARS_gNB* gNB, unsigned short lbar,unsigned short *n_idDMRS, unsigned short length_dmrs); +void nr_gold_pusch(PHY_VARS_gNB* gNB, uint32_t *Nid); int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned int Ns, diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 06e3948b64..d62687bd9c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -42,8 +42,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, nfapi_nr_rnti_type_e rnti_type, - uint16_t N_RB, - nfapi_nr_config_request_t *config) { + uint16_t N_RB) { uint16_t size = 0; switch(format) { @@ -52,7 +51,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, config) - size; // Padding to match 1_0 size + size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; @@ -138,7 +137,6 @@ void nr_pdcch_scrambling(uint32_t *in, uint32_t x1, x2, s=0; reset = 1; x2 = (n_RNTI<<16) + Nid; - for (int i=0; i>(i&0x1f))&1) ^ ((s>>(i&0x1f))&1))<<(i&0x1f); - //printf("nr_pdcch_scrambling: in %d seq 0x%08x => out %d\n",((*in)>>(i&0x1f))&1,s,((*out)>>(i&0x1f))&1); } } -uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc, + +uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, + nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu, uint32_t **gold_pdcch_dmrs, int32_t *txdataF, int16_t amp, - NR_DL_FRAME_PARMS frame_parms, - nfapi_nr_config_request_t config) { + NR_DL_FRAME_PARMS frame_parms) { + int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1]; // 3 for the max coreset duration uint16_t cset_start_sc; uint8_t cset_start_symb, cset_nsymb; int k,l,k_prime,dci_idx, dmrs_idx; - nr_cce_t cce; - nr_reg_t reg; - nr_reg_t reg_mapping_list[NR_MAX_PDCCH_AGG_LEVEL*NR_NB_REG_PER_CCE]; - nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params = dci_alloc.pdcch_params; + /*First iteration: single DCI*/ - /*The coreset is initialised - * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0 - * or the rb_offset for other coresets - * in time: by its first slot and its first symbol*/ - if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1) { + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15=NULL; + + + // find coreset descriptor + + int rb_offset; + int n_rb; + + AssertFatal(pdcch_pdu!=NULL || ul_dci_pdu!=NULL,"At least one pointer has to be !NULL\n"); + AssertFatal(pdcch_pdu==NULL || ul_dci_pdu==NULL,"Can't handle both DL and UL DCI in same slot\n"); + + + if (pdcch_pdu) pdcch_pdu_rel15 = &pdcch_pdu->pdcch_pdu_rel15; + else if (ul_dci_pdu) pdcch_pdu_rel15 = &ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15; + + get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); + + // compute rb_offset and n_prb based on frequency allocation + + if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) { cset_start_sc = frame_parms.first_carrier_offset + (frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB + - pdcch_params.rb_offset)*NR_NB_SC_PER_RB; + rb_offset)*NR_NB_SC_PER_RB; } else - cset_start_sc = frame_parms.first_carrier_offset + pdcch_params.rb_offset*NR_NB_SC_PER_RB; + cset_start_sc = frame_parms.first_carrier_offset + rb_offset*NR_NB_SC_PER_RB; - cset_start_symb = pdcch_params.first_symbol; - cset_nsymb = pdcch_params.n_symb; - dci_idx = 0; - LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb); - // DMRS length is per OFDM symbol - uint32_t dmrs_length = (pdcch_params.precoder_granularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS)? - (pdcch_params.n_rb*6) : (dci_alloc.L*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) - uint32_t encoded_length = dci_alloc.L*108; //2(QPSK)*9(per RB)*6(REG per CCE) - LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d\n", dmrs_length, encoded_length); - dmrs_length += pdcch_params.rb_offset*6; // To accommodate more DMRS symbols in case of rb offset - - /// DMRS QPSK modulation - for (int symb=cset_start_symb; symbnumDlDci;d++) { + /*The coreset is initialised + * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0 + * or the rb_offset for other coresets + * in time: by its first slot and its first symbol*/ + cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex; + cset_nsymb = pdcch_pdu_rel15->DurationSymbols; + dci_idx = 0; + LOG_D(PHY, "Coreset rb_offset %d, nb_rb %d\n",rb_offset,n_rb); + LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb); + // DMRS length is per OFDM symbol + AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED, + "Interleaved CCE REG MAPPING not supported\n"); + uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)? + (n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) + uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) + LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType); + dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset + + /// DMRS QPSK modulation + for (int symb=cset_start_symb; symbDurationSymbols; symb++) { + + nr_modulation(gold_pdcch_dmrs[symb], dmrs_length, DMRS_MOD_ORDER, mod_dmrs[symb]); //Qm = 2 as DMRS is QPSK modulated + #ifdef DEBUG_PDCCH_DMRS - - for (int i=0; i>1; i++) - printf("symb %d i %d gold seq 0x%08x mod_dmrs %d %d\n", symb, i, - gold_pdcch_dmrs[symb][i>>5], mod_dmrs[symb][i<<1], mod_dmrs[symb][(i<<1)+1] ); - + + for (int i=0; i>1; i++) + printf("symb %d i %d gold seq 0x%08x mod_dmrs %d %d\n", symb, i, + gold_pdcch_dmrs[symb][i>>5], mod_dmrs[symb][i<<1], mod_dmrs[symb][(i<<1)+1] ); + #endif - } - - /// DCI payload processing - // CRC attachment + Scrambling + Channel coding + Rate matching - uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; - uint16_t n_RNTI = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.rnti:0; - uint16_t Nid = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? - pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value; - t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_alloc.size, dci_alloc.L); - polar_encoder_fast(dci_alloc.dci_pdu, encoder_output, pdcch_params.rnti, 1, currentPtr); + } + + /// DCI payload processing + // CRC attachment + Scrambling + Channel coding + Rate matching + uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; + uint16_t n_RNTI = pdcch_pdu_rel15->RNTI[d]; + uint16_t Nid = pdcch_pdu_rel15->ScramblingId[d]; + + t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, + pdcch_pdu_rel15->PayloadSizeBits[d], + pdcch_pdu_rel15->AggregationLevel[d], + 0,NULL); + polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr); #ifdef DEBUG_CHANNEL_CODING - printf("polar rnti %d\n",pdcch_params.rnti); - printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", - dci_alloc.dci_pdu[0], dci_alloc.dci_pdu[1]); - printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5); + printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]); + printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", + ((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]); + printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5); + + for (int i=0; i>5; i++) + printf("[%d]->0x%08x \t", i,encoder_output[i]); - for (int i=0; i>5; i++) - printf("[%d]->0x%08x \t", i,encoder_output[i]); - - printf("\n"); + printf("\n"); #endif - /// Scrambling - uint32_t scrambled_output[NR_MAX_DCI_SIZE_DWORD]= {0}; - nr_pdcch_scrambling(encoder_output, encoded_length, Nid, n_RNTI, scrambled_output); + /// Scrambling + uint32_t scrambled_output[NR_MAX_DCI_SIZE_DWORD]= {0}; + nr_pdcch_scrambling(encoder_output, encoded_length, Nid, n_RNTI, scrambled_output); #ifdef DEBUG_CHANNEL_CODING - printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\t [4]->0x%08x\t [5]->0x%08x\t \ + printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\t [4]->0x%08x\t [5]->0x%08x\t \ [6]->0x%08x \t [7]->0x%08x \t [8]->0x%08x \t [9]->0x%08x\t [10]->0x%08x\t [11]->0x%08x\n", - scrambled_output[0], scrambled_output[1], scrambled_output[2], scrambled_output[3], scrambled_output[4],scrambled_output[5], - scrambled_output[6], scrambled_output[7], scrambled_output[8], scrambled_output[9], scrambled_output[10],scrambled_output[11] ); + scrambled_output[0], scrambled_output[1], scrambled_output[2], scrambled_output[3], scrambled_output[4],scrambled_output[5], + scrambled_output[6], scrambled_output[7], scrambled_output[8], scrambled_output[9], scrambled_output[10],scrambled_output[11] ); #endif - /// QPSK modulation - int16_t mod_dci[NR_MAX_DCI_SIZE>>1]; - nr_modulation(scrambled_output, encoded_length, DMRS_MOD_ORDER, mod_dci); //Qm = 2 as DMRS is QPSK modulated + /// QPSK modulation + int16_t mod_dci[NR_MAX_DCI_SIZE>>1]; + nr_modulation(scrambled_output, encoded_length, DMRS_MOD_ORDER, mod_dci); //Qm = 2 as DMRS is QPSK modulated #ifdef DEBUG_DCI - - for (int i=0; i>1; i++) - printf("i %d mod_dci %d %d\n", i, mod_dci[i<<1], mod_dci[(i<<1)+1] ); - + + for (int i=0; i>1; i++) + printf("i %d mod_dci %d %d\n", i, mod_dci[i<<1], mod_dci[(i<<1)+1] ); + #endif + + /// Resource mapping + + if (cset_start_sc >= frame_parms.ofdm_symbol_size) + cset_start_sc -= frame_parms.ofdm_symbol_size; + + /*Reorder REG list for a freq first mapping*/ + uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE; + uint8_t reg_idx0 = pdcch_pdu_rel15->CceIndex[d]*NR_NB_REG_PER_CCE; - /// Resource mapping - - if (cset_start_sc >= frame_parms.ofdm_symbol_size) - cset_start_sc -= frame_parms.ofdm_symbol_size; - - /*Reorder REG list for a freq first mapping*/ - uint8_t nb_regs = dci_alloc.L*NR_NB_REG_PER_CCE; - - for (int cce_idx=0; cce_idx>1) * mod_dmrs[l][dmrs_idx<<1]) >> 15; - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp>>1) * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; -#ifdef DEBUG_PDCCH_DMRS - printf("symbol %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); -#endif - k+=4; - - if (k >= frame_parms.ofdm_symbol_size) - k -= frame_parms.ofdm_symbol_size; - - dmrs_idx++; - } - } - } - - /*Now mapping the encoded DCI based on newly constructed REG list - * and the DMRS for the precoder granularity same as REG bundle*/ - for (int reg_idx=0; reg_idx= frame_parms.ofdm_symbol_size) - k -= frame_parms.ofdm_symbol_size; - - l = cset_start_symb + reg.symb_idx; - - // dmrs index depends on reference point for k according to 38.211 7.4.1.3.2 - if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) - dmrs_idx = (reg.reg_idx/cset_nsymb)*3; - else - dmrs_idx = ((reg.reg_idx/cset_nsymb)+pdcch_params.rb_offset)*3; - - k_prime = 0; - - for (int m=0; m>1) * mod_dmrs[l][dmrs_idx<<1]) >> 15; - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp>>1) * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; -#ifdef DEBUG_PDCCH_DMRS - printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); -#endif - dmrs_idx++; - } - - k_prime++; - } else { // DCI payload - ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dci[dci_idx<<1]) >> 15; - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dci[(dci_idx<<1) + 1]) >> 15; -#ifdef DEBUG_DCI - printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); -#endif - dci_idx++; - } - - k++; - + /*Mapping the encoded DCI along with the DMRS */ + for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) { + k = cset_start_sc + (12*reg_idx/cset_nsymb); + if (k >= frame_parms.ofdm_symbol_size) - k -= frame_parms.ofdm_symbol_size; - } - } - + k -= frame_parms.ofdm_symbol_size; + + l = cset_start_symb + ((reg_idx/cset_nsymb)%cset_nsymb); + + // dmrs index depends on reference point for k according to 38.211 7.4.1.3.2 + if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) + dmrs_idx = (reg_idx/cset_nsymb)*3; + else + dmrs_idx = ((reg_idx/cset_nsymb)+rb_offset)*3; + + k_prime = 0; + + for (int m=0; mCceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) { + ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (2*amp * mod_dmrs[l][dmrs_idx<<1]) >> 15; + ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (2*amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; +#ifdef DEBUG_PDCCH_DMRS + printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], + ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); +#endif + dmrs_idx++; + } + + k_prime++; + } else { // DCI payload + ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dci[dci_idx<<1]) >> 15; + ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dci[(dci_idx<<1) + 1]) >> 15; +#ifdef DEBUG_DCI + printf("PDCCH: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], + ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); +#endif + dci_idx++; + } + + k++; + + if (k >= frame_parms.ofdm_symbol_size) + k -= frame_parms.ofdm_symbol_size; + } // m + } // reg_idx + } // for (int d=0;dnumDlDci;d++) return 0; } + diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index d1a0eb7a23..047139aa63 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -27,15 +27,14 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, nfapi_nr_rnti_type_e rnti_type, - uint16_t N_RB, - nfapi_nr_config_request_t *config); + uint16_t N_RB); -uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc, +uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, + nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu, uint32_t **gold_pdcch_dmrs, int32_t *txdataF, int16_t amp, - NR_DL_FRAME_PARMS frame_parms, - nfapi_nr_config_request_t config); + NR_DL_FRAME_PARMS frame_parms); void nr_pdcch_scrambling(uint32_t *in, uint32_t size, @@ -45,11 +44,14 @@ void nr_pdcch_scrambling(uint32_t *in, void nr_fill_dci(PHY_VARS_gNB *gNB, int frame, - int slot, - NR_gNB_DCI_ALLOC_t *dci_alloc, - nfapi_nr_dl_config_dci_dl_pdu *pdu); + int slot); -void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t *dci_alloc, uint16_t n_shift, uint8_t m); +void nr_fill_ul_dci(PHY_VARS_gNB *gNB, + int frame, + int slot); +void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m); + +void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset); #endif //__PHY_NR_TRANSPORT_DCI__H diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index c33e5fd34b..ccec73d40e 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -36,11 +36,14 @@ #include "nr_dlsch.h" -void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) { +/* + Original version to keep code for Y that needs to be moved to MAC + +void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint16_t n_shift, uint8_t m) { nr_cce_t* cce; nr_reg_t* reg; - nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params = &dci_alloc->pdcch_params; + nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu = gNB->pdcch_pdu.pdcch; uint8_t L = dci_alloc->L; uint8_t bsize = pdcch_params->reg_bundle_size; @@ -54,7 +57,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); N_cce = N_reg / NR_NB_REG_PER_CCE; - /*Max number of candidates per aggregation level -- SIB1 configured search space only*/ + //Max number of candidates per aggregation level -- SIB1 configured search space only M_s_max = (L==4)?4:(L==8)?2:1; if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON) @@ -113,6 +116,84 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m } } +*/ + +void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { + + nr_cce_t* cce; + nr_reg_t* reg; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu_rel15 = &gNB->pdcch_pdu->pdcch_pdu_rel15; + int bsize = pdcch_pdu_rel15->RegBundleSize; + int R = pdcch_pdu_rel15->InterleaverSize; + int n_shift = pdcch_pdu_rel15->ShiftIndex; + + + //Max number of candidates per aggregation level -- SIB1 configured search space only + + + int n_rb,rb_offset; + + get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); + + + int N_reg = n_rb * pdcch_pdu_rel15->DurationSymbols; + int C; + + for (int d=0;dnumDlDci;d++) { + int L = pdcch_pdu_rel15->AggregationLevel[d]; + + if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) + AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); + + if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { + uint16_t assertFatalCond = (N_reg%(bsize*R)); + AssertFatal(assertFatalCond == 0,"CCE to REG interleaving: Invalid configuration leading to non integer C (N_reg %us, bsize %d R %d)\n",N_reg, bsize, R); + C = N_reg/(bsize*R); + } + + LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->CceIndex[d]); + for (uint8_t cce_idx=0; cce_idxcce_list[d][cce_idx]; + cce->cce_idx = pdcch_pdu_rel15->CceIndex[d] + cce_idx; + LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); + + if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { + LOG_D(PHY, "Interleaved CCE to REG mapping\n"); + uint8_t j = cce->cce_idx, j_prime; + uint8_t r,c,idx; + + for (uint8_t bundle_idx=0; bundle_idxreg_list[reg_idx]; + reg->reg_idx = bsize*idx + reg_idx; + reg->start_sc_idx = (reg->reg_idx/pdcch_pdu_rel15->DurationSymbols) * NR_NB_SC_PER_RB; + reg->symb_idx = reg->reg_idx % pdcch_pdu_rel15->DurationSymbols; + LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); + } + } + } + else { // NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED + LOG_D(PHY, "Non interleaved CCE to REG mapping\n"); + for (uint8_t reg_idx=0; reg_idxreg_list[reg_idx]; + reg->reg_idx = cce->cce_idx*NR_NB_REG_PER_CCE + reg_idx; + reg->start_sc_idx = (reg->reg_idx/pdcch_pdu_rel15->DurationSymbols) * NR_NB_SC_PER_RB; + reg->symb_idx = reg->reg_idx % pdcch_pdu_rel15->DurationSymbols; + LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); + } + + } + + } + } +} + /*static inline uint64_t dci_field(uint64_t field, uint8_t size) { uint64_t ret = 0; for (int i=0; idci_pdu; - memset((void*)dci_pdu,0,2*sizeof(uint64_t)); - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdcch_pdu->dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &pdcch_pdu->pdcch_params_rel15; - - - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &gNB->pdcch_pdu->pdcch_pdu_rel15; NR_gNB_DLSCH_t *dlsch; + for (int i=0;inumDlDci;i++) { - uint16_t N_RB = params_rel15->n_RB_BWP; - uint8_t fsize=0, pos=0, cand_idx=0; + uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; - - int dlsch_id = find_nr_dlsch(params_rel15->rnti,gNB,SEARCH_EXIST_OR_FREE); - if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ - LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",params_rel15->rnti,dlsch_id); - return; - } - - dlsch = gNB->dlsch[dlsch_id][0]; - - dlsch->slot_tx[slot] = 1; - dlsch->harq_ids[frame%2][slot] = pdu_rel15->harq_pid; - AssertFatal(pdu_rel15->harq_pid < 8 && pdu_rel15->harq_pid >= 0, - "illegal harq_pid %d\n",pdu_rel15->harq_pid); - - dlsch->harq_mask |= (1<harq_pid); - dlsch->rnti = params_rel15->rnti; - - dci_alloc->L = 8; - memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); - dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format, - dci_alloc->pdcch_params.rnti_type, - N_RB, - cfg); - - AssertFatal(dci_alloc->size<=64, "DCI sizes above 64 bits not yet supported"); - n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? - cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index; - nr_fill_cce_list(dci_alloc, n_shift, cand_idx); - - /// Payload generation - switch(params_rel15->dci_format) { - - - case NFAPI_NR_DL_DCI_FORMAT_1_0: - switch(params_rel15->rnti_type) { - case NFAPI_NR_RNTI_RA: - - // Freq domain assignment - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - pos=fsize; - *dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<size-pos)); -#ifdef DEBUG_FILL_DCI - printf("frequency-domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu); -#endif - // Time domain assignment - pos+=4; - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("time-domain assignment %d (3 bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,dci_alloc->size-pos,*dci_pdu); -#endif - // VRB to PRB mapping - - pos++; - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,dci_alloc->size-pos,*dci_pdu); -#endif - // MCS - pos+=5; - *dci_pdu |= ((uint64_t)pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("mcs %d (5 bits)=> %d (0x%lx)\n",pdu_rel15->mcs,dci_alloc->size-pos,*dci_pdu); -#endif - // TB scaling - pos+=2; - *dci_pdu |= ((uint64_t)pdu_rel15->tb_scaling&0x3)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("tb_scaling %d (2 bits)=> %d (0x%lx)\n",pdu_rel15->tb_scaling,dci_alloc->size-pos,*dci_pdu); -#endif - break; - - case NFAPI_NR_RNTI_C: - - // indicating a DL DCI format 1bit - pos++; - *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("Format indicator %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->format_indicator,1,dci_alloc->size-pos,*dci_pdu); -#endif - - // Freq domain assignment (275rb >> fsize = 16) - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - pos+=fsize; - *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment&((1<size-pos)); - -#ifdef DEBUG_FILL_DCI - printf("Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu); -#endif - - uint16_t is_ra = 1; - for (int i=0; ifrequency_domain_assignment>>i)&1)) { - is_ra = 0; - break; + int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE); + if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ + LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->RNTI[i],dlsch_id); + return; } - if (is_ra) //fsize are all 1 38.212 p86 - { - // ra_preamble_index 6 bits - pos+=6; - *dci_pdu |= ((pdu_rel15->ra_preamble_index&0x3f)<<(dci_alloc->size-pos)); + + dlsch = gNB->dlsch[dlsch_id][0]; + int harq_pid = 0;//extract_harq_pid(i,pdu_rel15); - // UL/SUL indicator 1 bit - pos++; - *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos); + dlsch->slot_tx[slot] = 1; + dlsch->harq_ids[frame%2][slot] = harq_pid; + AssertFatal(harq_pid < 8 && harq_pid >= 0, + "illegal harq_pid %d\n",harq_pid); + + dlsch->harq_mask |= (1<rnti = pdcch_pdu_rel15->RNTI[i]; + + nr_fill_cce_list(gNB,0); + /* + LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]); + LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); + */ + + } + +} +void nr_fill_ul_dci(PHY_VARS_gNB *gNB, + int frame, + int slot) { + + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &gNB->ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15; + + + for (int i=0;inumDlDci;i++) { + + uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + + // if there's no DL DCI then generate CCE list + if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0); + /* + LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]); + LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); + */ - // SS/PBCH index 6 bits - pos+=6; - *dci_pdu |= ((pdu_rel15->ss_pbch_index&0x3f)<<(dci_alloc->size-pos)); - - // prach_mask_index 4 bits - pos+=4; - *dci_pdu |= ((pdu_rel15->prach_mask_index&0xf)<<(dci_alloc->size-pos)); - - } //end if - - else { - - // Time domain assignment 4bit - - pos+=4; - *dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("Time domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,4,dci_alloc->size-pos,*dci_pdu); -#endif - - // VRB to PRB mapping 1bit - pos++; - *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("VRB to PRB %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,1,dci_alloc->size-pos,*dci_pdu); -#endif - - // MCS 5bit //bit over 32, so dci_pdu ++ - pos+=5; - *dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("MCS %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->mcs,5,dci_alloc->size-pos,*dci_pdu); -#endif - - // New data indicator 1bit - pos++; - *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("NDI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->ndi,1,dci_alloc->size-pos,*dci_pdu); -#endif - - // Redundancy version 2bit - pos+=2; - *dci_pdu |= (pdu_rel15->rv&0x3)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - printf("RV %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->rv,2,dci_alloc->size-pos,*dci_pdu); -#endif - - // HARQ process number 4bit - pos+=4; - *dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("HARQ_PID %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->harq_pid,4,dci_alloc->size-pos,*dci_pdu); -#endif - - // Downlink assignment index 2bit - pos+=2; - *dci_pdu |= ((pdu_rel15->dai&3)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("DAI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->dai,2,dci_alloc->size-pos,*dci_pdu); -#endif - - // TPC command for scheduled PUCCH 2bit - pos+=2; - *dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("TPC %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->tpc,2,dci_alloc->size-pos,*dci_pdu); -#endif - - // PUCCH resource indicator 3bit - pos+=3; - *dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("PUCCH RI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pucch_resource_indicator,3,dci_alloc->size-pos,*dci_pdu); -#endif - - // PDSCH-to-HARQ_feedback timing indicator 3bit - pos+=3; - *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - printf("PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_alloc->size-pos,*dci_pdu); -#endif - - } //end else - break; - - case NFAPI_NR_RNTI_P: - - // Short Messages Indicator – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++); - // Short Messages – 8 bits - for (int i=0; i<8; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++); - // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - - // TB scaling 2 bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++); - - - break; - - case NFAPI_NR_RNTI_SI: - // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); - // MCS 5bit //bit over 32, so dci_pdu ++ - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - - break; - - case NFAPI_NR_RNTI_TC: - // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); - // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); - // MCS 5bit //bit over 32, so dci_pdu ++ - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // New data indicator 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); - - // Downlink assignment index – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++); - - // TPC command for scheduled PUCCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); - - - // LOG_D(PHY, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", - // dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]); - - - // PDSCH-to-HARQ_feedback timing indicator – 3 bits - for (int i=0; i<3; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); - - break; - } - break; - - case NFAPI_NR_UL_DCI_FORMAT_0_0: - switch(params_rel15->rnti_type) - { - case NFAPI_NR_RNTI_C: - // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); - // Freq domain assignment max 16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // New data indicator 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); - - // TPC command for scheduled PUSCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); - - // Padding bits - for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++); - - // UL/SUL indicator – 1 bit - if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); - - break; - - case NFAPI_NR_RNTI_TC: - - // indicating a DL DCI format 1bit - *dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); - // Freq domain assignment max 16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // New data indicator 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); - - // TPC command for scheduled PUSCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); - - // Padding bits - for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++); - - // UL/SUL indicator – 1 bit - if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); - - break; - } - break; } - LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]); - LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); - } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 7502d5d4a4..4518280f6b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -65,178 +65,230 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, } +void nr_pdsch_codeword_scrambling_optim(uint8_t *in, + uint32_t size, + uint8_t q, + uint32_t Nid, + uint32_t n_RNTI, + uint32_t* out) { + + uint32_t x1, x2, s=0,in32; + + x2 = (n_RNTI<<15) + (q<<14) + Nid; + + s=lte_gold_generic(&x1, &x2, 1); + +#if defined(__AVX2__) + for (int i=0; i<((size>>5)+((size&0x1f) > 0 ? 1 : 0)); i++) { + in32=_mm256_movemask_epi8(_mm256_slli_epi16(((__m256i*)in)[i],7)); + out[i]=(in32^s); + // printf("in[%d] %x => %x\n",i,in32,out[i]); + s=lte_gold_generic(&x1, &x2, 0); + } +#elif defined(__SSE4__) + _m128i *in128; + for (int i=0; i<((size>>5)+((size&0x1f) > 0 ? 1 : 0)); i++) { + in128=&((__m128i*)in)[i<<1]; + ((uint16_t*)&in32)[0] = _mm128_movemask_epi8(_mm256_slli_epi16(in128[0],7)); + ((uint16_t*)&in32)[1] = _mm128_movemask_epi8(_mm256_slli_epi16(in128[1],7)); + out[i]=(in32^s); + s=lte_gold_generic(&x1, &x2, 0); + } + //#elsif defined(__arm__) || defined(__aarch64) + +#else + nr_pdsch_codeword_scrambling(in, + size, + q, + Nid, + n_RNTI, + out); +#endif +} + uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, - NR_gNB_DCI_ALLOC_t *dci_alloc, uint32_t ***pdsch_dmrs, int32_t** txdataF, int16_t amp, int frame, uint8_t slot, NR_DL_FRAME_PARMS *frame_parms, - nfapi_nr_config_request_t *config, + int xOverhead, time_stats_t *dlsch_encoding_stats, time_stats_t *dlsch_scrambling_stats, - time_stats_t *dlsch_modulation_stats) { + time_stats_t *dlsch_modulation_stats, + time_stats_t *tinput, + time_stats_t *tprep, + time_stats_t *tparity, + time_stats_t *toutput, + time_stats_t *dlsch_rate_matching_stats, + time_stats_t *dlsch_interleaving_stats, + time_stats_t *dlsch_segmentation_stats) { - NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[dci_alloc->harq_pid]; - nfapi_nr_dl_config_dlsch_pdu_rel15_t *rel15 = &harq->dlsch_pdu.dlsch_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params = dci_alloc->pdcch_params; + int harq_pid = 0; + NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid]; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs; int16_t **tx_layers = (int16_t**)dlsch->txdataF; int8_t Wf[2], Wt[2], l0, l_prime[2], delta; - uint16_t nb_symbols = rel15->nb_mod_symbols; - uint8_t Qm = rel15->modulation_order; - uint32_t encoded_length = nb_symbols*Qm; + uint8_t dmrs_Type = rel15->dmrsConfigType; + int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4; + uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1; + int16_t mod_dmrs[n_dmrs<<1]; + + uint16_t nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; + uint8_t Qm = rel15->qamModOrder[0]; + uint32_t encoded_length = nb_re*Qm; /// CRC, coding, interleaving and rate matching AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n"); start_meas(dlsch_encoding_stats); - nr_dlsch_encoding(harq->pdu, frame, slot, dlsch, frame_parms); + nr_dlsch_encoding(harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput, + dlsch_rate_matching_stats, + dlsch_interleaving_stats, + dlsch_segmentation_stats); stop_meas(dlsch_encoding_stats); #ifdef DEBUG_DLSCH -printf("PDSCH encoding:\nPayload:\n"); -for (int i=0; iB>>7; i++) { - for (int j=0; j<16; j++) - printf("0x%02x\t", harq->pdu[(i<<4)+j]); + printf("PDSCH encoding:\nPayload:\n"); + for (int i=0; iB>>7; i++) { + for (int j=0; j<16; j++) + printf("0x%02x\t", harq->pdu[(i<<4)+j]); + printf("\n"); + } + printf("\nEncoded payload:\n"); + for (int i=0; i>3; i++) { + for (int j=0; j<8; j++) + printf("%d", harq->f[(i<<3)+j]); + printf("\t"); + } printf("\n"); -} -printf("\nEncoded payload:\n"); -for (int i=0; i>3; i++) { - for (int j=0; j<8; j++) - printf("%d", harq->f[(i<<3)+j]); - printf("\t"); -} -printf("\n"); #endif + + /// scrambling start_meas(dlsch_scrambling_stats); - for (int q=0; qnb_codewords; q++) + for (int q=0; qNrOfCodewords; q++) memset((void*)scrambled_output[q], 0, (encoded_length>>5)*sizeof(uint32_t)); - uint16_t n_RNTI = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? \ - ((pdcch_params.scrambling_id==0)?pdcch_params.rnti:0) : 0; - uint16_t Nid = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? \ - pdcch_params.scrambling_id : config->sch_config.physical_cell_id.value; - for (int q=0; qnb_codewords; q++) - nr_pdsch_codeword_scrambling(harq->f, - encoded_length, - q, - Nid, - n_RNTI, - scrambled_output[q]); - + for (int q=0; qNrOfCodewords; q++) + nr_pdsch_codeword_scrambling_optim(harq->f, + encoded_length, + q, + rel15->dlDmrsScramblingId, + rel15->rnti, + scrambled_output[q]); + stop_meas(dlsch_scrambling_stats); #ifdef DEBUG_DLSCH -printf("PDSCH scrambling:\n"); -for (int i=0; i>8; i++) { - for (int j=0; j<8; j++) - printf("0x%08x\t", scrambled_output[0][(i<<3)+j]); - printf("\n"); -} + printf("PDSCH scrambling:\n"); + for (int i=0; i>8; i++) { + for (int j=0; j<8; j++) + printf("0x%08x\t", scrambled_output[0][(i<<3)+j]); + printf("\n"); + } #endif /// Modulation start_meas(dlsch_modulation_stats); - for (int q=0; qnb_codewords; q++) + for (int q=0; qNrOfCodewords; q++) nr_modulation(scrambled_output[q], encoded_length, Qm, mod_symbs[q]); stop_meas(dlsch_modulation_stats); #ifdef DEBUG_DLSCH -printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_symbols); -for (int i=0; i>3; i++) { - for (int j=0; j<8; j++) { - printf("%d %d\t", mod_symbs[0][((i<<3)+j)<<1], mod_symbs[0][(((i<<3)+j)<<1)+1]); - } - printf("\n"); -} -#endif - - - /// Layer mapping - nr_layer_mapping(mod_symbs, - rel15->nb_layers, - nb_symbols, - tx_layers); -#ifdef DEBUG_DLSCH -printf("Layer mapping (%d layers):\n", rel15->nb_layers); -for (int l=0; lnb_layers; l++) - for (int i=0; i<(nb_symbols/rel15->nb_layers)>>3; i++) { + printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_re); + for (int i=0; i>3; i++) { for (int j=0; j<8; j++) { - printf("%d %d\t", tx_layers[l][((i<<3)+j)<<1], tx_layers[l][(((i<<3)+j)<<1)+1]); + printf("%d %d\t", mod_symbs[0][((i<<3)+j)<<1], mod_symbs[0][(((i<<3)+j)<<1)+1]); } printf("\n"); } #endif - /// Antenna port mapping - //to be moved to init phase potentially, for now tx_layers 1-8 are mapped on antenna ports 1000-1007 - - /// DMRS QPSK modulation - uint16_t n_dmrs = ((rel15->n_prb+rel15->start_prb)*rel15->nb_re_dmrs)<<1; - int16_t mod_dmrs[n_dmrs<<1]; - uint8_t dmrs_type = config->pdsch_config.dmrs_type.value; - uint8_t mapping_type = config->pdsch_config.mapping_type.value; - - l0 = get_l0(mapping_type, 2);//config->pdsch_config.dmrs_typeA_position.value); - nr_modulation(pdsch_dmrs[l0][0], n_dmrs, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated + /// Layer mapping + nr_layer_mapping(mod_symbs, + rel15->nrOfLayers, + nb_re, + tx_layers); #ifdef DEBUG_DLSCH -printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_type); -for (int i=0; i>4; i++) { - for (int j=0; j<8; j++) { - printf("%d %d\t", mod_dmrs[((i<<3)+j)<<1], mod_dmrs[(((i<<3)+j)<<1)+1]); - } - printf("\n"); -} + printf("Layer mapping (%d layers):\n", rel15->nrOfLayers); + for (int l=0; lnrOfLayers; l++) + for (int i=0; i<(nb_re/rel15->nrOfLayers)>>3; i++) { + printf("layer %d, Re %d..%d : ",l,i<<3,(i<<3)+7); + for (int j=0; j<8; j++) { + printf("l%d %d\t", tx_layers[l][((i<<3)+j)<<1], tx_layers[l][(((i<<3)+j)<<1)+1]); + } + printf("\n"); + } #endif - + /// Antenna port mapping + //to be moved to init phase potentially, for now tx_layers 1-8 are mapped on antenna ports 1000-1007 + + /// DMRS QPSK modulation + + + l0 = get_l0(rel15->dlDmrsSymbPos); + nr_modulation(pdsch_dmrs[l0][0], n_dmrs, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated + +#ifdef DEBUG_DLSCH + printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_Type); + for (int i=0; i>4; i++) { + for (int j=0; j<8; j++) { + printf("%d %d\t", mod_dmrs[((i<<3)+j)<<1], mod_dmrs[(((i<<3)+j)<<1)+1]); + } + printf("\n"); + } +#endif + + /// Resource mapping - + // Non interleaved VRB to PRB mapping - uint16_t start_sc = frame_parms->first_carrier_offset + rel15->start_prb*NR_NB_SC_PER_RB; + uint16_t start_sc = frame_parms->first_carrier_offset + rel15->rbStart*NR_NB_SC_PER_RB; if (start_sc >= frame_parms->ofdm_symbol_size) start_sc -= frame_parms->ofdm_symbol_size; #ifdef DEBUG_DLSCH_MAPPING - printf("PDSCH resource mapping started (start SC %d\tstart symbol %d\tN_PRB %d\tnb_symbols %d)\n", - start_sc, rel15->start_symbol, rel15->n_prb, rel15->nb_symbols); + printf("PDSCH resource mapping started (start SC %d\tstart symbol %d\tN_PRB %d\tnb_re %d,nb_layers %d)\n", + start_sc, rel15->StartSymbolIndex, rel15->rbSize, nb_re,rel15->nrOfLayers); #endif - for (int ap=0; apnb_layers; ap++) { + for (int ap=0; apnrOfLayers; ap++) { // DMRS params for this ap - get_Wt(Wt, ap, dmrs_type); - get_Wf(Wf, ap, dmrs_type); - delta = get_delta(ap, dmrs_type); + get_Wt(Wt, ap, dmrs_Type); + get_Wf(Wf, ap, dmrs_Type); + delta = get_delta(ap, dmrs_Type); l_prime[0] = 0; // single symbol ap 0 uint8_t dmrs_symbol = l0+l_prime[0]; #ifdef DEBUG_DLSCH_MAPPING -printf("DMRS params for ap %d: Wt %d %d \t Wf %d %d \t delta %d \t l_prime %d \t l0 %d\tDMRS symbol %d\n", -ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol); + printf("DMRS Type %d params for ap %d: Wt %d %d \t Wf %d %d \t delta %d \t l_prime %d \t l0 %d\tDMRS symbol %d\n", + 1+dmrs_Type,ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol); #endif uint8_t k_prime=0; uint16_t m=0, n=0, dmrs_idx=0, k=0; - int txdataF_offset = (slot%2)*frame_parms->samples_per_slot_wCP; - if (dmrs_type == NFAPI_NR_DMRS_TYPE1) // another if condition to be included to check pdsch config type (reference of k) - dmrs_idx = rel15->start_prb*6; - else - dmrs_idx = rel15->start_prb*4; - for (int l=rel15->start_symbol; lstart_symbol+rel15->nb_symbols; l++) { + int txdataF_offset = (slot%2)*frame_parms->samples_per_slot_wCP; + if (dmrs_Type == NFAPI_NR_DMRS_TYPE1) // another if condition to be included to check pdsch config type (reference of k) + dmrs_idx = rel15->rbStart*6; + else + dmrs_idx = rel15->rbStart*4; + + for (int l=rel15->StartSymbolIndex; lStartSymbolIndex+rel15->NrOfSymbols; l++) { k = start_sc; - for (int i=0; in_prb*NR_NB_SC_PER_RB; i++) { - if ((l == dmrs_symbol) && (k == ((start_sc+get_dmrs_freq_idx(n, k_prime, delta, dmrs_type))%(frame_parms->ofdm_symbol_size)))) { + for (int i=0; irbSize*NR_NB_SC_PER_RB; i++) { + if ((l == dmrs_symbol) && (k == ((start_sc+get_dmrs_freq_idx(n, k_prime, delta, dmrs_Type))%(frame_parms->ofdm_symbol_size)))) { ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (Wt[l_prime[0]]*Wf[k_prime]*amp*mod_dmrs[dmrs_idx<<1]) >> 15; ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (Wt[l_prime[0]]*Wf[k_prime]*amp*mod_dmrs[(dmrs_idx<<1) + 1]) >> 15; #ifdef DEBUG_DLSCH_MAPPING -printf("dmrs_idx %d\t l %d \t k %d \t k_prime %d \t n %d \t txdataF: %d %d\n", -dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], -((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); + printf("dmrs_idx %d\t l %d \t k %d \t k_prime %d \t n %d \t txdataF: %d %d\n", + dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); #endif dmrs_idx++; k_prime++; @@ -249,9 +301,9 @@ dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; #ifdef DEBUG_DLSCH_MAPPING -printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", + printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], -((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); #endif m++; } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h index 77d5c6802f..f48905b68c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h @@ -36,10 +36,10 @@ #include "PHY/defs_gNB.h" void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config, - nfapi_nr_dl_config_dci_dl_pdu dci_pdu, - nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu); + nfapi_nr_dl_tti_pdcch_pdu dci_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu); -void nr_check_time_alloc(uint8_t S, uint8_t L, nfapi_nr_config_request_t config); +void nr_check_time_alloc(uint8_t S, uint8_t L,nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15,nfapi_nr_config_request_t *cfg); uint16_t get_RIV(uint16_t rb_start, uint16_t L, uint16_t N_RB); @@ -51,7 +51,10 @@ void nr_get_rbg_parms(NR_BWP_PARMS* bwp, uint8_t config_type); void nr_get_rbg_list(uint32_t bitmap, uint8_t n_rbg, uint8_t* rbg_list); -void nr_get_PRG_parms(NR_BWP_PARMS* bwp, NR_gNB_DCI_ALLOC_t dci_alloc, uint8_t prb_bundling_type); + +uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx); + +uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx); void nr_pdsch_codeword_scrambling(uint8_t *in, uint32_t size, @@ -63,24 +66,31 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, void nr_fill_dlsch(PHY_VARS_gNB *gNB, int frame, int slot, - nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, unsigned char *sdu); uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, - NR_gNB_DCI_ALLOC_t *dci_alloc, uint32_t ***pdsch_dmrs, int32_t** txdataF, int16_t amp, int frame, uint8_t slot, NR_DL_FRAME_PARMS *frame_parms, - nfapi_nr_config_request_t *config, + int xOverhead, time_stats_t *dlsch_encoding_stats, time_stats_t *dlsch_scrambling_stats, - time_stats_t *dlsch_modulation_stats); + time_stats_t *dlsch_modulation_stats, + time_stats_t *tinput, + time_stats_t *tprep, + time_stats_t *tparity, + time_stats_t *toutput, + time_stats_t *dlsch_rate_matching_stats, + time_stats_t *dlsch_interleaving_stats, + time_stats_t *dlsch_segmentation_stats); -void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr); + +void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB); void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch); @@ -89,9 +99,16 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch); int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type); int nr_dlsch_encoding(unsigned char *a,int frame, - uint8_t slot, - NR_gNB_DLSCH_t *dlsch, - NR_DL_FRAME_PARMS* frame_parms); + uint8_t slot, + NR_gNB_DLSCH_t *dlsch, + NR_DL_FRAME_PARMS* frame_parms, + time_stats_t *tinput, + time_stats_t *tprep, + time_stats_t *tparity, + time_stats_t *toutput, + time_stats_t *dlsch_rate_matching_stats, + time_stats_t *dlsch_interleaving_stats, + time_stats_t *dlsch_segmentation_stats); void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index dae5586224..856a7863f4 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -35,12 +35,12 @@ #include "PHY/CODING/coding_extern.h" #include "PHY/CODING/coding_defs.h" #include "PHY/CODING/lte_interleaver_inline.h" -#include "PHY/CODING/nrLDPC_encoder/defs.h" +#include "PHY/CODING/nrLDPC_extern.h" #include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" +#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "SCHED_NR/sched_nr.h" -#include "defs.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "common/utils/LOG/log.h" #include @@ -48,43 +48,71 @@ //#define DEBUG_DLSCH_CODING //#define DEBUG_DLSCH_FREE 1 -void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr) + +void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) { int i; int r; - + NR_gNB_DLSCH_t *dlsch = *dlschptr; + + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated if (dlsch) { + + if (N_RB != 273) { + a_segments = a_segments*N_RB; + a_segments = a_segments/273; + } + + uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment + + #ifdef DEBUG_DLSCH_FREE - printf("Freeing dlsch %p\n",dlsch); + LOG_D(PHY,"Freeing dlsch %p\n",dlsch); #endif for (i=0; iMdlharq; i++) { #ifdef DEBUG_DLSCH_FREE - printf("Freeing dlsch process %d\n",i); + LOG_D(PHY,"Freeing dlsch process %d\n",i); #endif if (dlsch->harq_processes[i]) { #ifdef DEBUG_DLSCH_FREE - printf("Freeing dlsch process %d (%p)\n",i,dlsch->harq_processes[i]); + LOG_D(PHY,"Freeing dlsch process %d (%p)\n",i,dlsch->harq_processes[i]); #endif if (dlsch->harq_processes[i]->b) { - free16(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES); //this should be MAX_NR_DLSCH_PAYLOAD_BYTES + free16(dlsch->harq_processes[i]->b,dlsch_bytes); dlsch->harq_processes[i]->b = NULL; #ifdef DEBUG_DLSCH_FREE - printf("Freeing dlsch process %d b (%p)\n",i,dlsch->harq_processes[i]->b); + LOG_D(PHY,"Freeing dlsch process %d b (%p)\n",i,dlsch->harq_processes[i]->b); +#endif + } + + if (dlsch->harq_processes[i]->e) { + free16(dlsch->harq_processes[i]->e,14*N_RB*12*8); + dlsch->harq_processes[i]->e = NULL; +#ifdef DEBUG_DLSCH_FREE + printf("Freeing dlsch process %d e (%p)\n",i,dlsch->harq_processes[i]->e); +#endif + } + + if (dlsch->harq_processes[i]->f) { + free16(dlsch->harq_processes[i]->f,14*N_RB*12*8); + dlsch->harq_processes[i]->f = NULL; +#ifdef DEBUG_DLSCH_FREE + printf("Freeing dlsch process %d f (%p)\n",i,dlsch->harq_processes[i]->f); #endif } #ifdef DEBUG_DLSCH_FREE - printf("Freeing dlsch process %d c (%p)\n",i,dlsch->harq_processes[i]->c); + LOG_D(PHY,"Freeing dlsch process %d c (%p)\n",i,dlsch->harq_processes[i]->c); #endif - for (r=0; rharq_processes[i]->c[r]); + LOG_D(PHY,"Freeing dlsch process %d c[%d] (%p)\n",i,r,dlsch->harq_processes[i]->c[r]); #endif if (dlsch->harq_processes[i]->c[r]) { @@ -108,31 +136,27 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr) } -NR_gNB_DLSCH_t *new_gNB_dlsch(unsigned char Kmimo, +NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms, + unsigned char Kmimo, unsigned char Mdlharq, uint32_t Nsoft, - uint8_t abstraction_flag, - NR_DL_FRAME_PARMS *frame_parms, - nfapi_nr_config_request_t *config) + uint8_t abstraction_flag, + uint16_t N_RB) { NR_gNB_DLSCH_t *dlsch; unsigned char exit_flag = 0,i,r,aa,layer; int re; - unsigned char bw_scaling =1; - uint16_t N_RB = config->rf_config.dl_carrier_bandwidth.value; + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated - switch (N_RB) { + if (N_RB != 273) { + a_segments = a_segments*N_RB; + a_segments = a_segments/273; + } - case 106: - bw_scaling =2; - break; - - default: - bw_scaling =1; - break; - } + uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment + dlsch = (NR_gNB_DLSCH_t *)malloc16(sizeof(NR_gNB_DLSCH_t)); if (dlsch) { @@ -145,12 +169,12 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(unsigned char Kmimo, for (layer=0; layerue_spec_bf_weights[layer] = (int32_t**)malloc16(64*sizeof(int32_t*)); - for (aa=0; aa<64; aa++) { + for (aa=0; aa<64; aa++) { dlsch->ue_spec_bf_weights[layer][aa] = (int32_t *)malloc16(OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES*sizeof(int32_t)); for (re=0;reue_spec_bf_weights[layer][aa][re] = 0x00007fff; } - } + } dlsch->txdataF[layer] = (int32_t *)malloc16((NR_MAX_PDSCH_ENCODED_LENGTH/NR_MAX_NB_LAYERS)*sizeof(int32_t)); // NR_MAX_NB_LAYERS is already included in NR_MAX_PDSCH_ENCODED_LENGTH } @@ -171,31 +195,31 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(unsigned char Kmimo, for (i=0; iharq_processes[i] = (NR_DL_gNB_HARQ_t *)malloc16(sizeof(NR_DL_gNB_HARQ_t)); - LOG_T(PHY, "Required mem size %d (bw scaling %d), dlsch->harq_processes[%d] %p\n", - MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling,bw_scaling, i,dlsch->harq_processes[i]); + LOG_T(PHY, "Required mem size %d dlsch->harq_processes[%d] %p\n", + dlsch_bytes, i,dlsch->harq_processes[i]); if (dlsch->harq_processes[i]) { bzero(dlsch->harq_processes[i],sizeof(NR_DL_gNB_HARQ_t)); // dlsch->harq_processes[i]->first_tx=1; - dlsch->harq_processes[i]->b = (unsigned char*)malloc16(MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling); - dlsch->harq_processes[i]->pdu = (uint8_t*)malloc16(MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling); + dlsch->harq_processes[i]->b = (unsigned char*)malloc16(dlsch_bytes); + dlsch->harq_processes[i]->pdu = (uint8_t*)malloc16(dlsch_bytes); if (dlsch->harq_processes[i]->pdu) { - bzero(dlsch->harq_processes[i]->pdu,MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling); - nr_emulate_dlsch_payload(dlsch->harq_processes[i]->pdu, (MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling)>>3); + bzero(dlsch->harq_processes[i]->pdu,dlsch_bytes); + nr_emulate_dlsch_payload(dlsch->harq_processes[i]->pdu, (dlsch_bytes)>>3); } else { - printf("Can't allocate PDU\n"); + LOG_D(PHY,"Can't allocate PDU\n"); exit_flag=1; } if (dlsch->harq_processes[i]->b) { - bzero(dlsch->harq_processes[i]->b,MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling); + bzero(dlsch->harq_processes[i]->b,dlsch_bytes); } else { - printf("Can't get b\n"); + LOG_D(PHY,"Can't get b\n"); exit_flag=1; } if (abstraction_flag==0) { - for (r=0; rharq_processes[i]->c[r]) { bzero(dlsch->harq_processes[i]->c[r],8448); } else { - printf("Can't get c\n"); + LOG_D(PHY,"Can't get c\n"); exit_flag=2; } if (dlsch->harq_processes[i]->d[r]) { bzero(dlsch->harq_processes[i]->d[r],(3*8448)); } else { - printf("Can't get d\n"); + LOG_D(PHY,"Can't get d\n"); exit_flag=2; } } + dlsch->harq_processes[i]->e = (uint8_t*)malloc16(14*N_RB*12*8); + if (dlsch->harq_processes[i]->e) { + bzero(dlsch->harq_processes[i]->e,14*N_RB*12*8); + } else { + printf("Can't get e\n"); + exit_flag=1; + } + dlsch->harq_processes[i]->f = (uint8_t*)malloc16(14*N_RB*12*8); + if (dlsch->harq_processes[i]->f) { + bzero(dlsch->harq_processes[i]->f,14*N_RB*12*8); + } else { + printf("Can't get f\n"); + exit_flag=1; + } } } else { - printf("Can't get harq_p %d\n",i); + LOG_D(PHY,"Can't get harq_p %d\n",i); exit_flag=3; } } @@ -233,7 +271,9 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(unsigned char Kmimo, LOG_D(PHY,"new_gNB_dlsch exit flag %d, size of %ld\n", exit_flag, sizeof(NR_gNB_DLSCH_t)); - free_gNB_dlsch(&dlsch); + + free_gNB_dlsch(&dlsch,N_RB); + return(NULL); @@ -261,7 +301,7 @@ void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch) dlsch->harq_processes[i]->round = 0; for (j=0; j<96; j++) - for (r=0; rharq_processes[i]->d[r]) dlsch->harq_processes[i]->d[r][j] = NR_NULL; @@ -274,59 +314,54 @@ int nr_dlsch_encoding(unsigned char *a, int frame, uint8_t slot, NR_gNB_DLSCH_t *dlsch, - NR_DL_FRAME_PARMS* frame_parms) + NR_DL_FRAME_PARMS* frame_parms, + time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput, + time_stats_t *dlsch_rate_matching_stats,time_stats_t *dlsch_interleaving_stats, + time_stats_t *dlsch_segmentation_stats) { unsigned int G; unsigned int crc=1; - uint8_t harq_pid = dlsch->harq_ids[frame&2][slot]; + uint8_t harq_pid = dlsch->harq_ids[frame%2][slot]; AssertFatal(harq_pid<8 && harq_pid>=0,"illegal harq_pid %d\b",harq_pid); - nfapi_nr_dl_config_dlsch_pdu_rel15_t rel15 = dlsch->harq_processes[harq_pid]->dlsch_pdu.dlsch_pdu_rel15; - uint16_t nb_rb = rel15.n_prb; - uint8_t nb_symb_sch = rel15.nb_symbols; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15; + uint16_t nb_rb = rel15->rbSize; + uint8_t nb_symb_sch = rel15->NrOfSymbols; uint32_t A, Z, Kb, F=0; uint32_t *Zc = &Z; - uint8_t mod_order = rel15.modulation_order; + uint8_t mod_order = rel15->qamModOrder[0]; uint16_t Kr=0,r; uint32_t r_offset=0; - //uint8_t *d_tmp[MAX_NUM_DLSCH_SEGMENTS]; uint8_t BG=1; uint32_t E; uint8_t Ilbrm = 1; uint32_t Tbslbrm = 950984; //max tbs - uint8_t nb_re_dmrs = rel15.nb_re_dmrs; - uint16_t R=rel15.coding_rate; - uint16_t length_dmrs = 1; + uint8_t nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4; + uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos); + uint16_t R=rel15->targetCodeRate[0]; float Coderate = 0.0; uint8_t Nl = 4; - /* - uint8_t *channel_input[MAX_NUM_DLSCH_SEGMENTS]; //unsigned char - for(j=0;jTBSize[0]<<3; - G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs,mod_order,rel15.nb_layers); + G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs,mod_order,rel15->nrOfLayers); LOG_D(PHY,"dlsch coding A %d G %d mod_order %d\n", A,G, mod_order); // if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet if (dlsch->harq_processes[harq_pid]->round == 0) { // this is a new packet #ifdef DEBUG_DLSCH_CODING - printf("encoding thinks this is a new packet \n"); + LOG_D(PHY,"encoding thinks this is a new packet \n"); #endif - /* + /* int i; - printf("dlsch (tx): \n"); + LOG_D(PHY,"dlsch (tx): \n"); for (i=0;i<(A>>3);i++) - printf("%02x.",a[i]); - printf("\n"); - */ + LOG_D(PHY,"%02x\n",a[i]); + LOG_D(PHY,"\n"); + */ if (A > 3824) { // Add 24-bit crc (polynomial A) to payload @@ -340,7 +375,7 @@ int nr_dlsch_encoding(unsigned char *a, dlsch->harq_processes[harq_pid]->B = A+24; // dlsch->harq_processes[harq_pid]->b = a; - AssertFatal((A/8)+4 <= MAX_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_DLSCH_PAYLOAD_BYTES); + AssertFatal((A/8)+4 <= MAX_NR_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_NR_DLSCH_PAYLOAD_BYTES); memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+4); // why is this +4 if the CRC is only 3 bytes? } @@ -355,7 +390,7 @@ int nr_dlsch_encoding(unsigned char *a, dlsch->harq_processes[harq_pid]->B = A+16; // dlsch->harq_processes[harq_pid]->b = a; - AssertFatal((A/8)+3 <= MAX_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_DLSCH_PAYLOAD_BYTES); + AssertFatal((A/8)+3 <= MAX_NR_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_NR_DLSCH_PAYLOAD_BYTES); memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc } @@ -369,6 +404,7 @@ int nr_dlsch_encoding(unsigned char *a, else BG = 1; + start_meas(dlsch_segmentation_stats); Kb = nr_segmentation(dlsch->harq_processes[harq_pid]->b, dlsch->harq_processes[harq_pid]->c, dlsch->harq_processes[harq_pid]->B, @@ -377,7 +413,7 @@ int nr_dlsch_encoding(unsigned char *a, Zc, &dlsch->harq_processes[harq_pid]->F, BG); - + stop_meas(dlsch_segmentation_stats); F = dlsch->harq_processes[harq_pid]->F; Kr = dlsch->harq_processes[harq_pid]->K; @@ -392,21 +428,28 @@ int nr_dlsch_encoding(unsigned char *a, //d_tmp[r] = &dlsch->harq_processes[harq_pid]->d[r][0]; //channel_input[r] = &dlsch->harq_processes[harq_pid]->d[r][0]; #ifdef DEBUG_DLSCH_CODING - printf("Encoder: B %d F %d \n",dlsch->harq_processes[harq_pid]->B, dlsch->harq_processes[harq_pid]->F); - printf("start ldpc encoder segment %d/%d\n",r,dlsch->harq_processes[harq_pid]->C); - printf("input %d %d %d %d %d \n", dlsch->harq_processes[harq_pid]->c[r][0], dlsch->harq_processes[harq_pid]->c[r][1], dlsch->harq_processes[harq_pid]->c[r][2],dlsch->harq_processes[harq_pid]->c[r][3], dlsch->harq_processes[harq_pid]->c[r][4]); + LOG_D(PHY,"Encoder: B %d F %d \n",dlsch->harq_processes[harq_pid]->B, dlsch->harq_processes[harq_pid]->F); + LOG_D(PHY,"start ldpc encoder segment %d/%d\n",r,dlsch->harq_processes[harq_pid]->C); + LOG_D(PHY,"input %d %d %d %d %d \n", dlsch->harq_processes[harq_pid]->c[r][0], dlsch->harq_processes[harq_pid]->c[r][1], dlsch->harq_processes[harq_pid]->c[r][2],dlsch->harq_processes[harq_pid]->c[r][3], dlsch->harq_processes[harq_pid]->c[r][4]); for (int cnt =0 ; cnt < 22*(*Zc)/8; cnt ++){ - printf("%d ", dlsch->harq_processes[harq_pid]->c[r][cnt]); + LOG_D(PHY,"%d ", dlsch->harq_processes[harq_pid]->c[r][cnt]); } - printf("\n"); + LOG_D(PHY,"\n"); #endif //ldpc_encoder_orig((unsigned char*)dlsch->harq_processes[harq_pid]->c[r],dlsch->harq_processes[harq_pid]->d[r],*Zc,Kb,Kr,BG,0); //ldpc_encoder_optim((unsigned char*)dlsch->harq_processes[harq_pid]->c[r],(unsigned char*)&dlsch->harq_processes[harq_pid]->d[r][0],*Zc,Kb,Kr,BG,NULL,NULL,NULL,NULL); } + encoder_implemparams_t impp; + impp.n_segments=dlsch->harq_processes[harq_pid]->C; + impp.tprep = tprep; + impp.tinput = tinput; + impp.tparity = tparity; + impp.toutput = toutput; for(int j=0;j<(dlsch->harq_processes[harq_pid]->C/8+1);j++) { - ldpc_encoder_optim_8seg_multi(dlsch->harq_processes[harq_pid]->c,dlsch->harq_processes[harq_pid]->d,*Zc,Kb,Kr,BG,dlsch->harq_processes[harq_pid]->C,j,NULL,NULL,NULL,NULL); + impp.macro_num=j; + nrLDPC_encoder(dlsch->harq_processes[harq_pid]->c,dlsch->harq_processes[harq_pid]->d,*Zc,Kb,Kr,BG,&impp); } @@ -419,34 +462,40 @@ int nr_dlsch_encoding(unsigned char *a, for (r=0; rharq_processes[harq_pid]->C; r++) { - if (dlsch->harq_processes[harq_pid]->F>0) { + if (F>0) { for (int k=(Kr-F-2*(*Zc)); kharq_processes[harq_pid]->d[r][k] = NR_NULL; //if (k<(Kr-F+8)) //printf("r %d filler bits [%d] = %d \n", r,k, dlsch->harq_processes[harq_pid]->d[r][k]); } } -#ifdef DEBUG_DLSCH_CODING - printf("Rate Matching, Code segment %d (coded bits (G) %u, unpunctured/repeated bits per code segment %d, mod_order %d, nb_rb %d)...\n", - r, - G, - Kr*3, - mod_order,nb_rb); -#endif + #ifdef DEBUG_DLSCH_CODING - printf("rvidx in encoding = %d\n", rel15.redundancy_version); + LOG_D(PHY,"rvidx in encoding = %d\n", rel15->rvIndex[0]); #endif - E = nr_get_E(G, dlsch->harq_processes[harq_pid]->C, mod_order, rel15.nb_layers, r); + E = nr_get_E(G, dlsch->harq_processes[harq_pid]->C, mod_order, rel15->nrOfLayers, r); + + //#ifdef DEBUG_DLSCH_CODING + LOG_D(PHY,"Rate Matching, Code segment %d/%d (coded bits (G) %u, E %d, Filler bits %d, Filler offset %d mod_order %d, nb_rb %d)...\n", + r, + dlsch->harq_processes[harq_pid]->C, + G, + E, + F, + Kr-F-2*(*Zc), + mod_order,nb_rb); // for tbslbrm calculation according to 5.4.2.1 of 38.212 - if (rel15.nb_layers < Nl) - Nl = rel15.nb_layers; + if (rel15->nrOfLayers < Nl) + Nl = rel15->nrOfLayers; - Tbslbrm = nr_compute_tbslbrm(rel15.mcs_table,nb_rb,Nl,dlsch->harq_processes[harq_pid]->C); + Tbslbrm = nr_compute_tbslbrm(rel15->mcsTable[0],nb_rb,Nl,dlsch->harq_processes[harq_pid]->C); + start_meas(dlsch_rate_matching_stats); nr_rate_matching_ldpc(Ilbrm, Tbslbrm, BG, @@ -454,19 +503,22 @@ int nr_dlsch_encoding(unsigned char *a, dlsch->harq_processes[harq_pid]->d[r], dlsch->harq_processes[harq_pid]->e+r_offset, dlsch->harq_processes[harq_pid]->C, - rel15.redundancy_version, + F, + Kr-F-2*(*Zc), + rel15->rvIndex[0], E); - + stop_meas(dlsch_rate_matching_stats); #ifdef DEBUG_DLSCH_CODING for (int i =0; i<16; i++) printf("output ratematching e[%d]= %d r_offset %u\n", i,dlsch->harq_processes[harq_pid]->e[i+r_offset], r_offset); #endif - nr_interleaving_ldpc(E, - mod_order, - dlsch->harq_processes[harq_pid]->e+r_offset, - dlsch->harq_processes[harq_pid]->f+r_offset); - + start_meas(dlsch_interleaving_stats); + nr_interleaving_ldpc(E, + mod_order, + dlsch->harq_processes[harq_pid]->e+r_offset, + dlsch->harq_processes[harq_pid]->f+r_offset); + stop_meas(dlsch_interleaving_stats); #ifdef DEBUG_DLSCH_CODING for (int i =0; i<16; i++) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c index 9736e97e34..2e6fc707bd 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c @@ -27,6 +27,7 @@ * \company Eurecom * \email: desouza@eurecom.fr * \note + * \warning */ @@ -46,6 +47,7 @@ uint8_t nr_pdsch_default_time_alloc_C_L[15] = {2,2,2,2,2,4,4,4,4,4,7,12,11,6,6}; /// Time domain allocation routines +/* void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config, nfapi_nr_dl_config_dci_dl_pdu dci_pdu, nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu) { @@ -73,9 +75,9 @@ void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config, case NFAPI_NR_RNTI_RA: case NFAPI_NR_RNTI_TC: - /*AssertFatal(dci_alloc.pdcch_params.common_search_space_type == NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_1, - "Invalid common search space type %d for RNTI %d, expected %d\n",dci_alloc.pdcch_params.common_search_space_type, - NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_1, dci_alloc.rnti_type);*/ + //AssertFatal(dci_alloc.pdcch_params.common_search_space_type == NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_1, + //"Invalid common search space type %d for RNTI %d, expected %d\n",dci_alloc.pdcch_params.common_search_space_type, + //NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_1, dci_alloc.rnti_type); *alloc_type = (alloc_list_flag) ? NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_ALLOC_LIST : NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_A; break; @@ -94,6 +96,7 @@ void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config, } } + uint16_t get_SLIV(uint8_t S, uint8_t L) { return ( (uint16_t)(((L-1)<=7)? (14*(L-1)+S) : (14*(15-L)+(13-S))) ); } @@ -104,26 +107,26 @@ static inline uint8_t get_K0(uint8_t row_idx, uint8_t time_alloc_type) { ((row_idx==6)||(row_idx==7)||(row_idx==15))? 1 : 0); } -/*ideally combine the calculation of L in the same function once the right struct is defined*/ -uint8_t nr_get_S(uint8_t row_idx, uint8_t CP, uint8_t time_alloc_type, uint8_t dmrs_typeA_position) { +// ideally combine the calculation of L in the same function once the right struct is defined +uint8_t nr_get_S(uint8_t row_idx, uint8_t CP, uint8_t time_alloc_type, uint8_t dmrs_TypeA_Position) { uint8_t idx; //uint8_t S; switch(time_alloc_type) { case NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_A: - idx = (row_idx>7)? (row_idx+6) : (((row_idx-1)<<1)-1+((dmrs_typeA_position==2)?0:1)); + idx = (row_idx>7)? (row_idx+6) : (((row_idx-1)<<1)-1+((dmrs_TypeA_Position==2)?0:1)); return ((CP==NFAPI_CP_NORMAL)?nr_pdsch_default_time_alloc_A_S_nCP[idx] : nr_pdsch_default_time_alloc_A_S_eCP[idx]); break; case NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_B: - idx = (row_idx<14)? (row_idx-1) : (row_idx == 14)? row_idx-1+((dmrs_typeA_position==2)?0:1) : 15; + idx = (row_idx<14)? (row_idx-1) : (row_idx == 14)? row_idx-1+((dmrs_TypeA_Position==2)?0:1) : 15; return (nr_pdsch_default_time_alloc_B_S[idx]); break; case NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_C: AssertFatal((row_idx!=6)&&(row_idx!=7)&&(row_idx<17), "Invalid row index %d in %s %s\n", row_idx, __FUNCTION__, __FILE__); - idx = (row_idx<6)? (row_idx-1) : (row_idx<14)? (row_idx-3) : (row_idx == 14)? row_idx-3+((dmrs_typeA_position==2)?0:1) : (row_idx-2); + idx = (row_idx<6)? (row_idx-1) : (row_idx<14)? (row_idx-3) : (row_idx == 14)? row_idx-3+((dmrs_TypeA_Position==2)?0:1) : (row_idx-2); break; default: @@ -132,16 +135,17 @@ uint8_t nr_get_S(uint8_t row_idx, uint8_t CP, uint8_t time_alloc_type, uint8_t d return 0; // temp warning fix } -void nr_check_time_alloc(uint8_t S, uint8_t L, nfapi_nr_config_request_t config) { - switch (config.subframe_config.dl_cyclic_prefix_type.value) { +void nr_check_time_alloc(uint8_t S, uint8_t L,nfapi_nr_dl_config_dlsch_pdu_rel15_t *rel15,nfapi_nr_config_request_t *cfg) { + + switch (cfg->subframe_config.dl_cyclic_prefix_type.value) { case NFAPI_CP_NORMAL: - if (config.pdsch_config.mapping_type.value == NFAPI_NR_PDSCH_MAPPING_TYPE_A) { + if (rel15->mapping_type == NFAPI_NR_PDSCH_MAPPING_TYPE_A) { AssertFatal(S<4, "Invalid value of S(%d) for mapping type A and normal CP\n", S); if (S==3) - AssertFatal(config.pdsch_config.mapping_type.value == 3, "Invalid S %d for dmrs_typeA_position %d\n", - S, config.pdsch_config.dmrs_typeA_position.value); + AssertFatal(rel15->dmrs_TypeA_Position == 3, "Invalid S %d for dmrs_TypeA_Position %d\n", + S, rel15->dmrs_TypeA_Position); AssertFatal((L>2)&&(L<15), "Invalid L %d for mapping type A and normal CP\n", L); @@ -157,12 +161,12 @@ void nr_check_time_alloc(uint8_t S, uint8_t L, nfapi_nr_config_request_t config) break; case NFAPI_CP_EXTENDED: - if (config.pdsch_config.mapping_type.value == NFAPI_NR_PDSCH_MAPPING_TYPE_A) { + if (rel15->mapping_type == NFAPI_NR_PDSCH_MAPPING_TYPE_A) { AssertFatal(S<4, "Invalid value of S(%d) for mapping type A and extended CP\n", S); if (S==3) - AssertFatal(config.pdsch_config.dmrs_typeA_position.value == 3, "Invalid S %d for dmrs_typeA_position %d\n", - S, config.pdsch_config.dmrs_typeA_position.value); + AssertFatal(rel15->dmrs_TypeA_Position == 3, "Invalid S %d for dmrs_TypeA_Position %d\n", + S, rel15->dmrs_TypeA_Position); AssertFatal((L>2)&&(L<13), "Invalid L %d for mapping type A and extended CP\n", L); @@ -241,6 +245,7 @@ void nr_get_PRG_parms(NR_BWP_PARMS* bwp, NR_gNB_DCI_ALLOC_t dci_alloc, uint8_t p LOG_I(PHY, "PRG parameters for BWP %d location %d N_RB %d:\n", bwp->bwp_id, bwp->location, bwp->N_RB); LOG_I(PHY, "P_prime %d\t start size %d\t endsize %d\t N_PRG %d\n", prg_parms->P_prime, prg_parms->start_size, prg_parms->end_size, prg_parms->N_PRG); } +*/ /// Payload emulation void nr_emulate_dlsch_payload(uint8_t* pdu, uint16_t size) { @@ -292,10 +297,10 @@ int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { void nr_fill_dlsch(PHY_VARS_gNB *gNB, int frame, int slot, - nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu) { - nfapi_nr_dl_config_dlsch_pdu_rel15_t *rel15 = &dlsch_pdu->dlsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &pdsch_pdu->pdsch_pdu_rel15; int dlsch_id = find_nr_dlsch(rel15->rnti,gNB,SEARCH_EXIST); AssertFatal( (dlsch_id>=0) && (dlsch_iddlsch[dlsch_id][0]; NR_DL_gNB_HARQ_t **harq = dlsch->harq_processes; /// DLSCH struct - memcpy((void*)&harq[dlsch->harq_ids[frame%2][slot]]->dlsch_pdu, (void*)dlsch_pdu, sizeof(nfapi_nr_dl_config_dlsch_pdu)); + memcpy((void*)&harq[dlsch->harq_ids[frame%2][slot]]->pdsch_pdu, (void*)pdsch_pdu, sizeof(nfapi_nr_dl_tti_pdsch_pdu)); + gNB->num_pdsch_rnti++; AssertFatal(sdu!=NULL,"sdu is null\n"); harq[dlsch->harq_ids[frame%2][slot]]->pdu = sdu; @@ -327,23 +333,9 @@ void nr_fill_ulsch(PHY_VARS_gNB *gNB, ulsch->harq_mask |= 1<harq_process_id[slot] = harq_pid; - nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch->harq_processes[harq_pid]->ulsch_pdu; + memcpy((void*)&ulsch->harq_processes[harq_pid]->ulsch_pdu, (void*)ulsch_pdu, sizeof(nfapi_nr_pusch_pdu_t)); LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); - - - //FK this is still a bad hack. We need to replace the L1 FAPI structures with the new scf ones as well. - rel15_ul->rnti = ulsch_pdu->rnti; - rel15_ul->ulsch_pdu_rel15.start_rb = ulsch_pdu->rb_start; - rel15_ul->ulsch_pdu_rel15.number_rbs = ulsch_pdu->rb_size; - rel15_ul->ulsch_pdu_rel15.start_symbol = ulsch_pdu->start_symbol_index; - rel15_ul->ulsch_pdu_rel15.number_symbols = ulsch_pdu->nr_of_symbols; - rel15_ul->ulsch_pdu_rel15.length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; - rel15_ul->ulsch_pdu_rel15.Qm = ulsch_pdu->qam_mod_order; - rel15_ul->ulsch_pdu_rel15.mcs = ulsch_pdu->mcs_index; - rel15_ul->ulsch_pdu_rel15.rv = ulsch_pdu->pusch_data.rv_index; - rel15_ul->ulsch_pdu_rel15.n_layers = ulsch_pdu->nrOfLayers; - rel15_ul->ulsch_pdu_rel15.R = ulsch_pdu->target_code_rate; } diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index af83c17fc1..b6a4787193 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -50,13 +50,13 @@ int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, - nfapi_nr_config_request_t *config, + nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms) { int k,l; //int16_t a; int16_t mod_dmrs[NR_PBCH_DMRS_LENGTH<<1]; uint8_t idx=0; - uint8_t nushift = config->sch_config.physical_cell_id.value &3; + uint8_t nushift = config->cell_config.phy_cell_id.value &3; LOG_D(PHY, "PBCH DMRS mapping started at symbol %d shift %d\n", ssb_start_symbol+1, nushift); /// QPSK modulation @@ -220,16 +220,14 @@ void nr_init_pbch_interleaver(uint8_t *interleaver) { } int nr_generate_pbch(NR_gNB_PBCH *pbch, - uint8_t *pbch_pdu, + nfapi_nr_dl_tti_ssb_pdu *ssb_pdu, uint8_t *interleaver, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, uint8_t n_hf, - uint8_t Lmax, - uint8_t ssb_index, int sfn, - nfapi_nr_config_request_t *config, + nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms) { int k,l,m; //int16_t a; @@ -243,17 +241,18 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, ///Payload generation memset((void *)pbch, 0, sizeof(NR_gNB_PBCH)); pbch->pbch_a=0; - + uint8_t ssb_index = frame_parms->ssb_index; + uint8_t *pbch_pdu = (uint8_t*)&ssb_pdu->ssb_pdu_rel15.bchPayload; + uint8_t Lmax = frame_parms->Lmax; for (int i=0; ipbch_a |= ((pbch_pdu[2-(i>>3)]>>(7-(i&7)))&1)<pbch_a |= ((pbch_pdu[i>>3]>>(7-(i&7)))&1)<pbch_a); -#endif + #endif // Extra byte generation for (int i=0; i<4; i++) @@ -265,7 +264,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, for (int i=0; i<3; i++) pbch->pbch_a |= ((ssb_index>>(5-i))&1)<<(29+i); // resp. 6th, 5th and 4th bits of ssb_index else - pbch->pbch_a |= ((config->sch_config.ssb_subcarrier_offset.value>>4)&1)<<29; //MSB of k_SSB (bit index 4) + pbch->pbch_a |= ((config->ssb_table.ssb_subcarrier_offset.value>>4)&1)<<29; //MSB of k_SSB (bit index 4) LOG_D(PHY,"After extra byte: pbch_a = 0x%08x\n",pbch->pbch_a); @@ -287,7 +286,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, M = (Lmax == 64)? (NR_POLAR_PBCH_PAYLOAD_BITS - 6) : (NR_POLAR_PBCH_PAYLOAD_BITS - 3); nushift = (((sfn>>2)&1)<<1) ^ ((sfn>>1)&1); pbch->pbch_a_prime = 0; - nr_pbch_scrambling(pbch, (uint32_t)config->sch_config.physical_cell_id.value, nushift, M, NR_POLAR_PBCH_PAYLOAD_BITS, 0, unscrambling_mask); + nr_pbch_scrambling(pbch, (uint32_t)config->cell_config.phy_cell_id.value, nushift, M, NR_POLAR_PBCH_PAYLOAD_BITS, 0, unscrambling_mask); #ifdef DEBUG_PBCH_ENCODING printf("Payload scrambling: nushift %d M %d sfn3 %d sfn2 %d\n", nushift, M, (sfn>>2)&1, (sfn>>1)&1); printf("pbch_a_prime: 0x%08x\n", pbch->pbch_a_prime); @@ -299,7 +298,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, /// CRC, coding and rate matching polar_encoder_fast (&a_reversed, (uint32_t *)pbch->pbch_e, 0, 0, - nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL) + nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0,NULL) ); #ifdef DEBUG_PBCH_ENCODING printf("Channel coding:\n"); @@ -312,7 +311,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, /// Scrambling M = NR_POLAR_PBCH_E; nushift = (Lmax==4)? ssb_index&3 : ssb_index&7; - nr_pbch_scrambling(pbch, (uint32_t)config->sch_config.physical_cell_id.value, nushift, M, NR_POLAR_PBCH_E, 1, 0); + nr_pbch_scrambling(pbch, (uint32_t)config->cell_config.phy_cell_id.value, nushift, M, NR_POLAR_PBCH_E, 1, 0); #ifdef DEBUG_PBCH_ENCODING printf("Scrambling:\n"); @@ -333,7 +332,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, } /// Resource mapping - nushift = config->sch_config.physical_cell_id.value &3; + nushift = config->cell_config.phy_cell_id.value &3; // PBCH modulated symbols are mapped within the SSB block on symbols 1, 2, 3 excluding the subcarriers used for the PBCH DMRS ///symbol 1 [0:239] -- 180 mod symbols k = frame_parms->first_carrier_offset + frame_parms->ssb_start_subcarrier; diff --git a/openair1/PHY/NR_TRANSPORT/nr_pss.c b/openair1/PHY/NR_TRANSPORT/nr_pss.c index e0d7b6ae33..be9e011e60 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pss.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pss.c @@ -28,7 +28,7 @@ int nr_generate_pss( int16_t *d_pss, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, - nfapi_nr_config_request_t* config, + nfapi_nr_config_request_scf_t* config, NR_DL_FRAME_PARMS *frame_parms) { int i,k,l,m; @@ -36,7 +36,7 @@ int nr_generate_pss( int16_t *d_pss, int16_t x[NR_PSS_LENGTH]; const int x_initial[7] = {0, 1, 1 , 0, 1, 1, 1}; - uint8_t Nid2 = config->sch_config.physical_cell_id.value % 3; + uint8_t Nid2 = config->cell_config.phy_cell_id.value % 3; /// Sequence generation for (i=0; i < 7; i++) diff --git a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c index 63922c8c65..04045380eb 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c +++ b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c @@ -84,8 +84,14 @@ uint16_t get_dmrs_freq_idx(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t d return dmrs_idx; } -uint8_t get_l0(uint8_t mapping_type, uint8_t dmrs_typeA_position) { - - return ((mapping_type==NFAPI_NR_PDSCH_MAPPING_TYPE_A)?dmrs_typeA_position:0); +uint8_t get_l0(uint16_t dlDmrsSymbPos) { + uint16_t mask=dlDmrsSymbPos; + int l0; + for (l0=0;l0<14;l0++) { + if ((mask&1) == 1) break; + mask>>=1; + } + AssertFatal(l0 < 4,"impossible l0 %d\n",l0); + return (l0); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h index 8278742a48..2b25464b84 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h +++ b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h @@ -48,6 +48,6 @@ uint8_t get_delta(uint8_t ap, uint8_t config); uint16_t get_dmrs_freq_idx(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t dmrs_type); -uint8_t get_l0(uint8_t mapping_type, uint8_t dmrs_typeA_position); +uint8_t get_l0(uint16_t dlDmrsSymbPos); -#endif +#endif \ No newline at end of file diff --git a/openair1/PHY/NR_TRANSPORT/nr_sss.c b/openair1/PHY/NR_TRANSPORT/nr_sss.c index 154aca9ffe..7d8b551d7c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_sss.c +++ b/openair1/PHY/NR_TRANSPORT/nr_sss.c @@ -27,7 +27,7 @@ int nr_generate_sss( int16_t *d_sss, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, - nfapi_nr_config_request_t* config, + nfapi_nr_config_request_scf_t* config, NR_DL_FRAME_PARMS *frame_parms) { int i,k,l; @@ -39,7 +39,7 @@ int nr_generate_sss( int16_t *d_sss, const int x1_initial[7] = { 1, 0, 0, 0, 0, 0, 0 }; /// Sequence generation - Nid = config->sch_config.physical_cell_id.value; + Nid = config->cell_config.phy_cell_id.value; Nid2 = Nid % 3; Nid1 = (Nid - Nid2)/3; diff --git a/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c b/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c index 10ac17acab..ea8e39488e 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c @@ -33,187 +33,6 @@ #include "nr_transport_common_proto.h" #include "PHY/CODING/coding_defs.h" -//Table 5.1.3.1-1 of 38.214 -uint16_t Table_51311[29][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616}, - {4,658},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}}; - -//Table 5.1.3.1-2 of 38.214 -// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point -uint16_t Table_51312[28][2] = {{2,120},{2,193},{2,308},{2,449},{2,602},{4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{6,466},{6,517},{6,567},{6,616},{6,666}, - {6,719},{6,772},{6,822},{6,873},{8,1365},{8,711},{8,754},{8,797},{8,841},{8,885},{8,1833},{8,948}}; - -//Table 5.1.3.1-3 of 38.214 -uint16_t Table_51313[29][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{4,340}, - {4,378},{4,434},{4,490},{4,553},{4,616},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666}, {6,719}, {6,772}}; - -//Table 6.1.4.1-1 of 38.214 TODO fix for tp-pi2BPSK -uint16_t Table_61411[28][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616}, - {4,658},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}}; - -//Table 6.1.4.1-2 of 38.214 TODO fix for tp-pi2BPSK -uint16_t Table_61412[28][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679}, - {4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{4,699},{4,772},{6,567},{6,616},{6,666}, {6,772}}; - - -uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) { - switch(table_idx) { - case 0: - return (Table_51311[Imcs][0]); - break; - - case 1: - return (Table_51312[Imcs][0]); - break; - - case 2: - return (Table_51313[Imcs][0]); - break; - - default: - AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx); - } -} - -uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx) { - switch(table_idx) { - case 0: - return (Table_51311[Imcs][1]); - break; - - case 1: - return (Table_51312[Imcs][1]); - break; - - case 2: - return (Table_51313[Imcs][1]); - break; - - default: - AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx); - } -} - -uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) { - switch(table_idx) { - case 0: - return (Table_51311[Imcs][0]); - break; - - case 1: - return (Table_51312[Imcs][0]); - break; - - case 2: - return (Table_51313[Imcs][0]); - break; - - case 3: - return (Table_61411[Imcs][0]); - break; - - case 4: - return (Table_61412[Imcs][0]); - break; - - default: - AssertFatal(0, "Invalid MCS table index %d (expected in range [1,2])\n", table_idx); - } -} - -uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) { - switch(table_idx) { - case 0: - return (Table_51311[Imcs][1]); - break; - - case 1: - return (Table_51312[Imcs][1]); - break; - - case 2: - return (Table_51313[Imcs][1]); - break; - - case 3: - return (Table_61411[Imcs][1]); - break; - - case 4: - return (Table_61412[Imcs][1]); - break; - - default: - AssertFatal(0, "Invalid MCS table index %d (expected in range [1,2])\n", table_idx); - } -} - -static inline uint8_t is_codeword_disabled(uint8_t format, uint8_t Imcs, uint8_t rv) { - return ((format==NFAPI_NR_DL_DCI_FORMAT_1_1)&&(Imcs==26)&&(rv==1)); -} - -static inline uint8_t get_table_idx(uint8_t mcs_table, uint8_t dci_format, uint8_t rnti_type, uint8_t ss_type) { - if ((mcs_table == NFAPI_NR_MCS_TABLE_QAM256) && (dci_format == NFAPI_NR_DL_DCI_FORMAT_1_1) && ((rnti_type==NFAPI_NR_RNTI_C)||(rnti_type==NFAPI_NR_RNTI_CS))) - return 2; - else if ((mcs_table == NFAPI_NR_MCS_TABLE_QAM64_LOW_SE) && (rnti_type!=NFAPI_NR_RNTI_new) && (rnti_type==NFAPI_NR_RNTI_C) && (ss_type==NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)) - return 3; - else if (rnti_type==NFAPI_NR_RNTI_new) - return 3; - else if ((mcs_table == NFAPI_NR_MCS_TABLE_QAM256) && (rnti_type==NFAPI_NR_RNTI_CS) && (dci_format == NFAPI_NR_DL_DCI_FORMAT_1_1)) - return 2; // Condition mcs_table not configured in sps_config necessary here but not yet implemented - /*else if((mcs_table == NFAPI_NR_MCS_TABLE_QAM64_LOW_SE) && (rnti_type==NFAPI_NR_RNTI_CS)) - * table_idx = 3; - * Note: the commented block refers to the case where the mcs_table is from sps_config*/ - else - return 1; -} - -void nr_get_tbs_dl(nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, - nfapi_nr_dl_config_dci_dl_pdu dci_pdu, - nfapi_nr_config_request_t config) { - - LOG_D(MAC, "TBS calculation\n"); - - nfapi_nr_dl_config_pdcch_parameters_rel15_t params_rel15 = dci_pdu.pdcch_params_rel15; - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_rel15 = &dlsch_pdu->dlsch_pdu_rel15; - uint8_t rnti_type = params_rel15.rnti_type; - uint16_t N_PRB_oh = ((rnti_type==NFAPI_NR_RNTI_SI)||(rnti_type==NFAPI_NR_RNTI_RA)||(rnti_type==NFAPI_NR_RNTI_P))? 0 : \ - (config.pdsch_config.x_overhead.value); - uint8_t N_PRB_DMRS = (config.pdsch_config.dmrs_type.value == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 - uint8_t N_sh_symb = dlsch_rel15->nb_symbols; - uint8_t Imcs = dlsch_rel15->mcs_idx; - uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; - LOG_D(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh); - - uint16_t R; - uint32_t TBS=0; - uint8_t table_idx, Qm; - - /*uint8_t mcs_table = config.pdsch_config.mcs_table.value; - uint8_t ss_type = params_rel15.search_space_type; - uint8_t dci_format = params_rel15.dci_format; - get_table_idx(mcs_table, dci_format, rnti_type, ss_type);*/ - table_idx = 0; - R = nr_get_code_rate_dl(Imcs, table_idx); - Qm = nr_get_Qm_dl(Imcs, table_idx); - - TBS = nr_compute_tbs(Qm, - R, - dlsch_rel15->n_prb, - N_sh_symb, - N_PRB_DMRS, - N_PRB_oh, - dlsch_rel15->nb_layers); - - dlsch_rel15->coding_rate = R; - dlsch_rel15->modulation_order = Qm; - dlsch_rel15->transport_block_size = TBS; - dlsch_rel15->nb_re_dmrs = N_PRB_DMRS; - dlsch_rel15->nb_mod_symbols = N_RE_prime*dlsch_rel15->n_prb*dlsch_rel15->nb_codewords; - dlsch_rel15->mcs_table = table_idx; - - LOG_D(MAC, "TBS %d : N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n", - TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx, dlsch_rel15->nb_mod_symbols); -} uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) { uint32_t G; @@ -227,7 +46,7 @@ uint32_t nr_get_E(uint32_t G, uint8_t C, uint8_t Qm, uint8_t Nl, uint8_t r) { AssertFatal(Nl>0,"Nl is 0\n"); AssertFatal(Qm>0,"Qm is 0\n"); - + LOG_D(PHY,"nr_get_E : (G %d, C %d, Qm %d, Nl %d, r %d)\n",G, C, Qm, Nl, r); if (r <= Cprime - ((G/(Nl*Qm))%Cprime) - 1) E = Nl*Qm*(G/(Nl*Qm*Cprime)); else diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h index 23413f591c..be73875058 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport.h @@ -23,6 +23,7 @@ #define __NR_TRANSPORT__H__ #include "PHY/defs_gNB.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" #define NR_PBCH_PDU_BITS 24 @@ -36,7 +37,7 @@ int nr_generate_pss( int16_t *d_pss, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, - nfapi_nr_config_request_t *config, + nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms); /*! @@ -49,7 +50,7 @@ int nr_generate_sss( int16_t *d_sss, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, - nfapi_nr_config_request_t *config, + nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms); /*! @@ -62,7 +63,7 @@ int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, - nfapi_nr_config_request_t *config, + nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms); /*! @@ -85,16 +86,14 @@ void nr_pbch_scrambling(NR_gNB_PBCH *pbch, @returns 0 on success */ int nr_generate_pbch(NR_gNB_PBCH *pbch, - uint8_t *pbch_pdu, + nfapi_nr_dl_tti_ssb_pdu *ssb_pdu, uint8_t *interleaver, int32_t *txdataF, int16_t amp, uint8_t ssb_start_symbol, uint8_t n_hf, - uint8_t Lmax, - uint8_t ssb_index, int sfn, - nfapi_nr_config_request_t *config, + nfapi_nr_config_request_scf_t *config, NR_DL_FRAME_PARMS *frame_parms); /*! @@ -105,11 +104,23 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, */ void nr_init_pbch_interleaver(uint8_t *interleaver); -NR_gNB_DLSCH_t *new_gNB_dlsch(unsigned char Kmimo, +NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms, + unsigned char Kmimo, unsigned char Mdlharq, uint32_t Nsoft, uint8_t abstraction_flag, - NR_DL_FRAME_PARMS *frame_parms, - nfapi_nr_config_request_t *config); + uint16_t N_RB); + +void rx_nr_prach(PHY_VARS_gNB *gNB, + int frame, + int subframe, + uint16_t *max_preamble, + uint16_t *max_preamble_energy, + uint16_t *max_preamble_delay + ); + +void rx_nr_prach_ru(RU_t *ru, + int frame, + int subframe); #endif /*__NR_TRANSPORT__H__*/ diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h index 6a88203f8c..762346048f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h @@ -23,7 +23,7 @@ /*! \file PHY/NR_TRANSPORT/nr_transport_common_proto.h * \brief Some support routines * \author -* \date 2018 +* \date 2019 * \version 0.1 * \company Eurecom * \email: @@ -36,29 +36,13 @@ #include "PHY/defs_nr_common.h" -#define MAX_NUM_NR_DLSCH_SEGMENTS 16 -#define MAX_NUM_NR_ULSCH_SEGMENTS MAX_NUM_NR_DLSCH_SEGMENTS - -#define MAX_NR_DLSCH_PAYLOAD_BYTES (MAX_NUM_NR_DLSCH_SEGMENTS*1056) -#define MAX_NR_ULSCH_PAYLOAD_BYTES (MAX_NUM_NR_ULSCH_SEGMENTS*1056) - -#define MAX_NUM_NR_CHANNEL_BITS (14*273*12*6) // 14 symbols, 273 RB -#define MAX_NUM_NR_RE (14*273*12) #define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1 #define NR_PUSCH_y 3 // UCI placeholder bit -/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ -uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); -uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); -/** \brief Computes Q based on I_MCS PDSCH and table_idx for uplink. Implements MCS Tables from 38.214. */ -uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx); -uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); -void nr_get_tbs_dl(nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, - nfapi_nr_dl_config_dci_dl_pdu dci_pdu, - nfapi_nr_config_request_t config); + /** \brief Computes available bits G. */ uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch, uint8_t nb_re_dmrs, uint16_t length_dmrs, uint8_t Qm, uint8_t Nl); diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index 4c8d8650e3..9ce56421fc 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -65,20 +65,12 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, @param is_dmrs_symbol, flag to indicate wether this OFDM symbol contains DMRS symbols or not. */ -void nr_ulsch_extract_rbs_single(int **rxdataF, - int **ul_ch_estimates, - int **rxdataF_ext, - int **ul_ch_estimates_ext, - uint32_t rxdataF_ext_offset, - // unsigned int *rb_alloc, [hna] Resource Allocation Type 1 is assumed only for the moment +void nr_ulsch_extract_rbs_single(int32_t **rxdataF, + NR_gNB_PUSCH *pusch_vars, unsigned char symbol, - unsigned short start_rb, - unsigned short nb_rb_pusch, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t dmrs_symbol, - uint16_t number_symbols, - uint8_t mapping_type, - dmrs_UplinkConfig_t *dmrs_UplinkConfig); + uint8_t is_dmrs_symbol, + nfapi_nr_pusch_pdu_t *pusch_pdu, + NR_DL_FRAME_PARMS *frame_parms); void nr_ulsch_scale_channel(int32_t **ul_ch_estimates_ext, NR_DL_FRAME_PARMS *frame_parms, @@ -212,3 +204,11 @@ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); + +void rx_nr_prach(PHY_VARS_gNB *gNB, + int frame, + int subframe, + uint16_t *max_preamble, + uint16_t *max_preamble_energy, + uint16_t *max_preamble_delay + ); diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.h b/openair1/PHY/NR_TRANSPORT/nr_ulsch.h index 76a2b2b075..7ff52ae692 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.h @@ -32,9 +32,9 @@ #include "PHY/defs_gNB.h" -void free_gNB_ulsch(NR_gNB_ULSCH_t **ulsch); +void free_gNB_ulsch(NR_gNB_ULSCH_t **ulsch,uint8_t N_RB_UL); -NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint8_t N_RB_UL, uint8_t abstraction_flag); +NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint16_t N_RB_UL, uint8_t abstraction_flag); /*! \brief Perform PUSCH decoding. TS 38.212 V15.4.0 subclause 6.2 @@ -53,12 +53,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, uint8_t UE_id, short *ulsch_llr, NR_DL_FRAME_PARMS *frame_parms, + nfapi_nr_pusch_pdu_t *pusch_pdu, uint32_t frame, - uint16_t nb_symb_sch, - uint16_t nb_re_dmrs, uint8_t nr_tti_rx, uint8_t harq_pid, - uint8_t is_crnti); + uint32_t G); /*! \brief Perform PUSCH unscrambling. TS 38.211 V15.4.0 subclause 6.3.1.1 diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index 3945439a45..e8a961360f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -37,8 +37,7 @@ #include "PHY/CODING/coding_extern.h" #include "PHY/CODING/coding_defs.h" #include "PHY/CODING/lte_interleaver_inline.h" -#include "PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h" -#include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" +#include "PHY/CODING/nrLDPC_extern.h" #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" @@ -58,29 +57,45 @@ static uint64_t nb_error_decod =0; //extern double cpuf; -void free_gNB_ulsch(NR_gNB_ULSCH_t **ulschptr) { +void free_gNB_ulsch(NR_gNB_ULSCH_t **ulschptr,uint8_t N_RB_UL) +{ + int i,r; + uint16_t a_segments = MAX_NUM_NR_ULSCH_SEGMENTS; //number of segments to be allocated NR_gNB_ULSCH_t *ulsch = *ulschptr; if (ulsch) { + if (N_RB_UL != 273) { + a_segments = a_segments*N_RB_UL; + a_segments = a_segments/273; + } + + uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment + for (i=0; iharq_processes[i]) { if (ulsch->harq_processes[i]->b) { - free16(ulsch->harq_processes[i]->b,MAX_NR_ULSCH_PAYLOAD_BYTES); + free16(ulsch->harq_processes[i]->b,ulsch_bytes); ulsch->harq_processes[i]->b = NULL; } - for (r=0; rharq_processes[i]->c[r],(8448)*sizeof(uint8_t)); ulsch->harq_processes[i]->c[r] = NULL; } - for (r=0; rharq_processes[i]->d[r]) { free16(ulsch->harq_processes[i]->d[r],(68*384)*sizeof(int16_t)); ulsch->harq_processes[i]->d[r] = NULL; } } - for (r=0; r<(MAX_NUM_NR_ULSCH_SEGMENTS); r++) { + for (r=0; rharq_processes[i]->w[r]) { + free16(ulsch->harq_processes[i]->w[r],(3*(6144+64))*sizeof(int16_t)); + ulsch->harq_processes[i]->w[r] = NULL; + } + } + for (r=0; rharq_processes[i]->p_nrLDPC_procBuf[r]){ nrLDPC_free_mem(ulsch->harq_processes[i]->p_nrLDPC_procBuf[r]); ulsch->harq_processes[i]->p_nrLDPC_procBuf[r] = NULL; @@ -96,23 +111,20 @@ void free_gNB_ulsch(NR_gNB_ULSCH_t **ulschptr) { } -NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint8_t N_RB_UL, uint8_t abstraction_flag) +NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint16_t N_RB_UL, uint8_t abstraction_flag) { NR_gNB_ULSCH_t *ulsch; uint8_t exit_flag = 0,i,r; - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_ULSCH_SEGMENTS; //number of segments to be allocated - switch (N_RB_UL) { - case 106: - bw_scaling =2; - break; - - default: - bw_scaling =1; - break; + if (N_RB_UL != 273) { + a_segments = a_segments*N_RB_UL; + a_segments = a_segments/273; } + uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment + ulsch = (NR_gNB_ULSCH_t *)malloc16(sizeof(NR_gNB_ULSCH_t)); if (ulsch) { @@ -130,15 +142,15 @@ NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint8_t N_RB_UL, uint8 memset(ulsch->harq_processes[i],0,sizeof(NR_UL_gNB_HARQ_t)); - ulsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_NR_ULSCH_PAYLOAD_BYTES/bw_scaling); + ulsch->harq_processes[i]->b = (uint8_t*)malloc16(ulsch_bytes); if (ulsch->harq_processes[i]->b) - memset(ulsch->harq_processes[i]->b,0,MAX_NR_ULSCH_PAYLOAD_BYTES/bw_scaling); + memset(ulsch->harq_processes[i]->b,0,ulsch_bytes); else exit_flag=3; if (abstraction_flag == 0) { - for (r=0; rharq_processes[i]->p_nrLDPC_procBuf[r] = nrLDPC_init_mem(); @@ -155,6 +167,13 @@ NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint8_t N_RB_UL, uint8 memset(ulsch->harq_processes[i]->d[r],0,(68*384)*sizeof(int16_t)); else exit_flag=2; + + ulsch->harq_processes[i]->w[r] = (int16_t*)malloc16((3*(6144+64))*sizeof(int16_t)); + + if (ulsch->harq_processes[i]->w[r]) + memset(ulsch->harq_processes[i]->w[r],0,(3*(6144+64))*sizeof(int16_t)); + else + exit_flag=2; } } } else { @@ -165,9 +184,8 @@ NR_gNB_ULSCH_t *new_gNB_ulsch(uint8_t max_ldpc_iterations,uint8_t N_RB_UL, uint8 if (exit_flag==0) return(ulsch); } - printf("new_gNB_ulsch with size %zu: exit_flag = %hhu\n",sizeof(NR_UL_gNB_HARQ_t), exit_flag); - free_gNB_ulsch(&ulsch); + free_gNB_ulsch(&ulsch,N_RB_UL); return(NULL); } @@ -263,7 +281,7 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch) /// Temporary h sequence to flag PUSCH_x/PUSCH_y symbols which are not scrambled //uint8_t h[MAX_NUM_CHANNEL_BITS]; /// soft bits for each received segment ("w"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) - //int16_t w[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; + //int16_t w[MAX_NUM_NR_ULSCH_SEGMENTS][3*(6144+64)]; } } } @@ -277,15 +295,13 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, uint8_t UE_id, short *ulsch_llr, NR_DL_FRAME_PARMS *frame_parms, + nfapi_nr_pusch_pdu_t *pusch_pdu, uint32_t frame, - uint16_t nb_symb_sch, - uint16_t nb_re_dmrs, uint8_t nr_tti_rx, uint8_t harq_pid, - uint8_t is_crnti) -{ + uint32_t G) { + uint32_t A,E; - uint32_t G; uint32_t ret, offset; int32_t no_iteration_ldpc, length_dec; uint32_t r,r_offset=0,Kr=8424,Kr_bytes,K_bytes_F,err_flag=0; @@ -299,7 +315,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, NR_gNB_ULSCH_t *ulsch = phy_vars_gNB->ulsch[UE_id][0]; NR_UL_gNB_HARQ_t *harq_process = ulsch->harq_processes[harq_pid]; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *nfapi_ulsch_pdu_rel15 = &harq_process->ulsch_pdu.ulsch_pdu_rel15; t_nrLDPC_dec_params decParams; t_nrLDPC_dec_params* p_decParams = &decParams; @@ -319,13 +334,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, double Coderate = 0.0; // ------------------------------------------------------------------ - uint16_t nb_rb = nfapi_ulsch_pdu_rel15->number_rbs; - uint16_t number_symbols = nfapi_ulsch_pdu_rel15->number_symbols; - uint8_t Qm = nfapi_ulsch_pdu_rel15->Qm; - uint16_t R = nfapi_ulsch_pdu_rel15->R; - uint8_t mcs = nfapi_ulsch_pdu_rel15->mcs; - uint8_t n_layers = nfapi_ulsch_pdu_rel15->n_layers; - uint8_t length_dmrs = nfapi_ulsch_pdu_rel15->length_dmrs; + uint16_t nb_rb = pusch_pdu->rb_size; + uint8_t Qm = pusch_pdu->qam_mod_order; + uint16_t R = pusch_pdu->target_code_rate; + uint8_t mcs = pusch_pdu->mcs_index; + uint8_t n_layers = pusch_pdu->nrOfLayers; // ------------------------------------------------------------------ uint32_t i,j; @@ -345,19 +358,20 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } // harq_process->trials[nfapi_ulsch_pdu_rel15->round]++; - harq_process->TBS = nr_compute_tbs(Qm, R, nb_rb, number_symbols, nb_re_dmrs*length_dmrs, 0, n_layers); + harq_process->TBS = pusch_pdu->pusch_data.tb_size; - A = harq_process->TBS; + A = (harq_process->TBS)<<3; ret = ulsch->max_ldpc_iterations + 1; - G = nr_get_G(nb_rb, number_symbols, nb_re_dmrs, length_dmrs, Qm, n_layers); - - LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d, nb_re_dmrs %d, Qm %d, n_layers %d\n",harq_pid,A,G, mcs, n_layers, nb_symb_sch,nb_rb, nb_re_dmrs, Qm, n_layers); + LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_rb %d, Qm %d, n_layers %d\n",harq_pid,A,G, mcs, n_layers, nb_rb, Qm, n_layers); if (harq_process->round == 0) { // This is a new packet, so compute quantities regarding segmentation - harq_process->B = A+24; + if (A > 3824) + harq_process->B = A+24; + else + harq_process->B = A+16; if (R<1024) Coderate = (float) R /(float) 1024; @@ -394,20 +408,20 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } } - // [hna] Perform nr_segmenation with input and output set to NULL to calculate only (B, C, K, Z, F) - nr_segmentation(NULL, - NULL, - harq_process->B, - &harq_process->C, - &harq_process->K, - &harq_process->Z, // [hna] Z is Zc - &harq_process->F, - p_decParams->BG); + // [hna] Perform nr_segmenation with input and output set to NULL to calculate only (B, C, K, Z, F) + nr_segmentation(NULL, + NULL, + harq_process->B, + &harq_process->C, + &harq_process->K, + &harq_process->Z, // [hna] Z is Zc + &harq_process->F, + p_decParams->BG); #ifdef DEBUG_ULSCH_DECODING printf("ulsch decoding nr segmentation Z %d\n", harq_process->Z); if (!frame%100) - printf("K %d C %d Z %d nl %d \n", harq_process->K, harq_process->C, harq_process->Z, harq_process->Nl); + printf("K %d C %d Z %d\n", harq_process->K, harq_process->C, harq_process->Z); #endif } p_decParams->Z = harq_process->Z; @@ -419,21 +433,15 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, err_flag = 0; r_offset = 0; - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_ULSCH_SEGMENTS; //number of segments to be allocated - switch (frame_parms->N_RB_UL) { - - case 106: - bw_scaling =2; - break; - - default: - bw_scaling =1; - break; + if (nb_rb != 273) { + a_segments = a_segments*nb_rb; + a_segments = a_segments/273; } - if (harq_process->C > MAX_NUM_NR_ULSCH_SEGMENTS/bw_scaling) { - LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,MAX_NUM_NR_ULSCH_SEGMENTS/bw_scaling); + if (harq_process->C > a_segments) { + LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,a_segments); return (ulsch->max_ldpc_iterations + 1); } #ifdef DEBUG_ULSCH_DECODING @@ -448,7 +456,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, K_bytes_F = Kr_bytes-(harq_process->F>>3); for (r=0; rC; r++) { - E = nr_get_E(G, harq_process->C, nfapi_ulsch_pdu_rel15->Qm, nfapi_ulsch_pdu_rel15->n_layers, r); + E = nr_get_E(G, harq_process->C, Qm, n_layers, r); #if gNB_TIMING_TRACE start_meas(ulsch_deinterleaving_stats); @@ -461,7 +469,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, //////////////////////////// ulsch_llr =====> harq_process->e ////////////////////////////// nr_deinterleaving_ldpc(E, - nfapi_ulsch_pdu_rel15->Qm, + Qm, harq_process->e[r], ulsch_llr+r_offset); @@ -481,10 +489,10 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, harq_pid,r, G, Kr*3, harq_process->TBS, - nfapi_ulsch_pdu_rel15->Qm, - nfapi_ulsch_pdu_rel15->number_rbs, - nfapi_ulsch_pdu_rel15->n_layers, - nfapi_ulsch_pdu_rel15->rv, + Qm, + nb_rb, + n_layers, + pusch_pdu->pusch_data.rv_index, harq_process->round); #endif ////////////////////////////////////////////////////////////////////////////////////////// @@ -496,7 +504,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ///////////////////////// harq_process->e =====> harq_process->d ///////////////////////// - Tbslbrm = nr_compute_tbslbrm(0,nb_rb,nfapi_ulsch_pdu_rel15->n_layers,harq_process->C); + Tbslbrm = nr_compute_tbslbrm(0,nb_rb,n_layers,harq_process->C); if (nr_rate_matching_ldpc_rx(Ilbrm, Tbslbrm, @@ -505,9 +513,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, harq_process->d[r], harq_process->e[r], harq_process->C, - nfapi_ulsch_pdu_rel15->rv, + pusch_pdu->pusch_data.rv_index, (harq_process->round==0)?1:0, - E)==-1) { + E, + harq_process->F, + Kr-harq_process->F-2*(p_decParams->Z))==-1) { #if gNB_TIMING_TRACE stop_meas(ulsch_rate_unmatching_stats); #endif @@ -540,7 +550,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, // printf("done\n"); if (harq_process->C == 1) { - crc_type = CRC24_A; + if (A > 3824) + crc_type = CRC24_A; + else + crc_type = CRC16; + length_dec = harq_process->B; } else { @@ -565,7 +579,9 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } AssertFatal(kc!=255,""); - for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) { + j+=(harq_process->F>>3); + // for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) { + for (i=Kr_bytes; i < ((kc*p_decParams->Z)>>3); i++, j++) { pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } @@ -637,7 +653,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, int32_t tti_rx_prev = nr_tti_rx - 1; if (tti_rx_prev < 0) { frame_rx_prev--; - tti_rx_prev += 10*frame_parms->ttis_per_subframe; + tti_rx_prev += frame_parms->slots_per_frame; } frame_rx_prev = frame_rx_prev%1024; @@ -661,13 +677,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ulsch->harq_mask &= ~(1 << harq_pid); } - if(is_crnti) { - LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", - phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS); - } + // LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", + // phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS); harq_process->handled = 1; - return (ulsch->max_ldpc_iterations + 1); + ret = ulsch->max_ldpc_iterations + 1; } else { @@ -684,31 +698,28 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, // harq_process->harq_ack.harq_id = harq_pid; // harq_process->harq_ack.send_harq_status = 1; - if(is_crnti) - { - LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); - } - } - - // Reassembly of Transport block here - offset = 0; - Kr = harq_process->K; - Kr_bytes = Kr>>3; - - for (r=0; rC; r++) { - - memcpy(harq_process->b+offset, - harq_process->c[r], - Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0)); - - offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0)); + // LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); + // Reassembly of Transport block here + offset = 0; + Kr = harq_process->K; + Kr_bytes = Kr>>3; + + for (r=0; rC; r++) { + + memcpy(harq_process->b+offset, + harq_process->c[r], + Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0)); + + offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0)); + #ifdef DEBUG_ULSCH_DECODING - printf("Segment %u : Kr = %u bytes\n", r, Kr_bytes); - printf("copied %d bytes to b sequence (harq_pid %d)\n", (Kr_bytes - (harq_process->F>>3)-((harq_process->C>1)?3:0)), harq_pid); - printf("b[0] = %x, c[%d] = %x\n", harq_process->b[offset], harq_process->F>>3, harq_process->c[r]); + printf("Segment %u : Kr = %u bytes\n", r, Kr_bytes); + printf("copied %d bytes to b sequence (harq_pid %d)\n", (Kr_bytes - (harq_process->F>>3)-((harq_process->C>1)?3:0)), harq_pid); + printf("b[0] = %x, c[%d] = %x\n", harq_process->b[offset], harq_process->F>>3, harq_process->c[r]); #endif - + + } } #ifdef DEBUG_ULSCH_DECODING diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index eb35fd7dc6..bce8ddcc29 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -4,6 +4,7 @@ #include "PHY/impl_defs_top.h" #include "PHY/NR_TRANSPORT/nr_sch_dmrs.h" #include "PHY/NR_REFSIG/dmrs_nr.h" +#include "PHY/NR_REFSIG/ptrs_nr.h" #include "PHY/NR_ESTIMATION/nr_ul_estimation.h" #include "PHY/defs_nr_common.h" @@ -221,77 +222,97 @@ void nr_idft(uint32_t *z, uint32_t Msc_PUSCH) } -void nr_ulsch_extract_rbs_single(int **rxdataF, - int **ul_ch_estimates, - int **rxdataF_ext, - int **ul_ch_estimates_ext, - uint32_t rxdataF_ext_offset, - // unsigned int *rb_alloc, [hna] Resource Allocation Type 1 is assumed only for the moment + +void nr_ulsch_extract_rbs_single(int32_t **rxdataF, + NR_gNB_PUSCH *pusch_vars, unsigned char symbol, - unsigned short start_rb, - unsigned short nb_rb_pusch, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t dmrs_symbol, - uint16_t number_symbols, - uint8_t mapping_type, - dmrs_UplinkConfig_t *dmrs_UplinkConfig) + uint8_t is_dmrs_symbol, + nfapi_nr_pusch_pdu_t *pusch_pdu, + NR_DL_FRAME_PARMS *frame_parms) { unsigned short start_re, re, nb_re_pusch; unsigned char aarx; + uint8_t K_ptrs; uint32_t rxF_ext_index = 0; uint32_t ul_ch0_ext_index = 0; uint32_t ul_ch0_index = 0; - uint8_t is_dmrs_symbol_flag, k_prime; - uint16_t n=0; - + uint32_t ul_ch0_ptrs_ext_index = 0; + uint32_t ul_ch0_ptrs_index = 0; + uint8_t is_ptrs_symbol_flag,k_prime; + uint16_t n=0, num_ptrs_symbols; int16_t *rxF,*rxF_ext; int *ul_ch0,*ul_ch0_ext; + int *ul_ch0_ptrs,*ul_ch0_ptrs_ext; + uint16_t n_rnti = pusch_pdu->rnti; + uint8_t delta = 0; #ifdef DEBUG_RB_EXT printf("--------------------symbol = %d-----------------------\n", symbol); - printf("--------------------ch_ext_index = %d-----------------------\n", symbol*NR_NB_SC_PER_RB * nb_rb_pusch); + printf("--------------------ch_ext_index = %d-----------------------\n", symbol*NR_NB_SC_PER_RB * pusch_pdu->rb_size); #endif - start_re = (frame_parms->first_carrier_offset + (start_rb * NR_NB_SC_PER_RB))%frame_parms->ofdm_symbol_size; - - nb_re_pusch = NR_NB_SC_PER_RB * nb_rb_pusch; - is_dmrs_symbol_flag = 0; + uint8_t is_dmrs_re; + start_re = (frame_parms->first_carrier_offset + (pusch_pdu->rb_start * NR_NB_SC_PER_RB))%frame_parms->ofdm_symbol_size; + nb_re_pusch = NR_NB_SC_PER_RB * pusch_pdu->rb_size; + is_ptrs_symbol_flag = 0; + num_ptrs_symbols = 0; + + K_ptrs = (pusch_pdu->pusch_ptrs.ptrs_freq_density)?4:2; for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) { rxF = (int16_t *)&rxdataF[aarx][symbol * frame_parms->ofdm_symbol_size]; - rxF_ext = (int16_t *)&rxdataF_ext[aarx][symbol * nb_re_pusch]; // [hna] rxdataF_ext isn't contiguous in order to solve an alignment problem ib llr computation in case of mod_order = 4, 6 + rxF_ext = (int16_t *)&pusch_vars->rxdataF_ext[aarx][symbol * nb_re_pusch]; // [hna] rxdataF_ext isn't contiguous in order to solve an alignment problem ib llr computation in case of mod_order = 4, 6 - ul_ch0 = &ul_ch_estimates[aarx][dmrs_symbol*frame_parms->ofdm_symbol_size]; // update channel estimates if new dmrs symbol are available + ul_ch0 = &pusch_vars->ul_ch_estimates[aarx][pusch_vars->dmrs_symbol*frame_parms->ofdm_symbol_size]; // update channel estimates if new dmrs symbol are available - ul_ch0_ext = &ul_ch_estimates_ext[aarx][symbol*nb_re_pusch]; + ul_ch0_ext = &pusch_vars->ul_ch_estimates_ext[aarx][symbol*nb_re_pusch]; + + ul_ch0_ptrs = &pusch_vars->ul_ch_ptrs_estimates[aarx][pusch_vars->ptrs_symbol_index*frame_parms->ofdm_symbol_size]; // update channel estimates if new dmrs symbol are available + + ul_ch0_ptrs_ext = &pusch_vars->ul_ch_ptrs_estimates_ext[aarx][symbol*nb_re_pusch]; n = 0; k_prime = 0; for (re = 0; re < nb_re_pusch; re++) { - is_dmrs_symbol_flag = is_dmrs_symbol(symbol, - (start_re + re)%frame_parms->ofdm_symbol_size, - start_re, - k_prime, - n, - 0, - number_symbols, - dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); + if (is_dmrs_symbol) + is_dmrs_re = (re == get_dmrs_freq_idx_ul(n, k_prime, delta, pusch_pdu->dmrs_config_type)); + else + is_dmrs_re = 0; + + if ( ((pusch_pdu->pdu_bit_map)>>2)& 0x01 ) { + is_ptrs_symbol_flag = is_ptrs_symbol(symbol, + (start_re + re)%frame_parms->ofdm_symbol_size, + n_rnti, + pusch_pdu->rb_size, + pusch_pdu->nr_of_symbols, + aarx, + K_ptrs, + pusch_vars->ptrs_symbols, + start_re, + frame_parms->ofdm_symbol_size, + pusch_pdu->dmrs_config_type, + pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset); + + if (is_ptrs_symbol_flag == 1) + num_ptrs_symbols++; + + } + #ifdef DEBUG_RB_EXT printf("re = %d, is_dmrs_symbol_flag = %d, symbol = %d\n", re, is_dmrs_symbol_flag, symbol); #endif - if ( is_dmrs_symbol_flag == 0 ) { + if ( is_dmrs_re == 0 && is_ptrs_symbol_flag == 0) { rxF_ext[rxF_ext_index] = (rxF[ ((start_re + re)*2) % (frame_parms->ofdm_symbol_size*2)]); rxF_ext[rxF_ext_index + 1] = (rxF[(((start_re + re)*2) + 1) % (frame_parms->ofdm_symbol_size*2)]); ul_ch0_ext[ul_ch0_ext_index] = ul_ch0[ul_ch0_index]; + ul_ch0_ptrs_ext[ul_ch0_ptrs_ext_index] = ul_ch0_ptrs[ul_ch0_ptrs_index]; #ifdef DEBUG_RB_EXT printf("rxF_ext[%d] = %d\n", rxF_ext_index, rxF_ext[rxF_ext_index]); @@ -299,6 +320,7 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, #endif ul_ch0_ext_index++; + ul_ch0_ptrs_ext_index++; rxF_ext_index +=2; } else { k_prime++; @@ -306,8 +328,12 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, n+=(k_prime)?0:1; } ul_ch0_index++; + ul_ch0_ptrs_index++; } } + + pusch_vars->ptrs_sc_per_ofdm_symbol = num_ptrs_symbols; + } void nr_ulsch_scale_channel(int **ul_ch_estimates_ext, @@ -334,7 +360,7 @@ void nr_ulsch_scale_channel(int **ul_ch_estimates_ext, ch_amp128 = _mm_set1_epi16(ch_amp); // Q3.13 - for (aatx=0; aatx < frame_parms->nb_antenna_ports_eNB; aatx++) { + for (aatx=0; aatx < frame_parms->nb_antenna_ports_gNB; aatx++) { for (aarx=0; aarx < frame_parms->nb_antennas_rx; aarx++) { ul_ch128 = (__m128i *)&ul_ch_estimates_ext[aarx][symbol*nb_rb*NR_NB_SC_PER_RB]; @@ -420,7 +446,7 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, symbol_mod = (symbol>=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol; - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) for (aarx=0; aarxnb_antennas_rx; aarx++) { //clear average level avg128U = vdupq_n_s32(0); @@ -436,7 +462,7 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, avg128U = vqaddq_s32(avg128U, vmull_s16(ul_ch128[2], ul_ch128[2])); avg128U = vqaddq_s32(avg128U, vmull_s16(ul_ch128[3], ul_ch128[3])); - if (((symbol_mod == 0) || (symbol_mod == (frame_parms->Ncp-1)))&&(frame_parms->nb_antenna_ports_eNB!=1)) { + if (((symbol_mod == 0) || (symbol_mod == (frame_parms->Ncp-1)))&&(frame_parms->nb_antenna_ports_gNB!=1)) { ul_ch128+=4; } else { avg128U = vqaddq_s32(avg128U, vmull_s16(ul_ch128[4], ul_ch128[4])); @@ -469,18 +495,17 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, } void nr_ulsch_channel_compensation(int **rxdataF_ext, - int **ul_ch_estimates_ext, - int **ul_ch_mag, - int **ul_ch_magb, - int **rxdataF_comp, - int **rho, - NR_DL_FRAME_PARMS *frame_parms, - unsigned char symbol, - uint8_t is_dmrs_symbol, - unsigned char mod_order, - unsigned short nb_rb, - unsigned char output_shift) -{ + int **ul_ch_estimates_ext, + int **ul_ch_mag, + int **ul_ch_magb, + int **rxdataF_comp, + int **rho, + NR_DL_FRAME_PARMS *frame_parms, + unsigned char symbol, + uint8_t is_dmrs_symbol, + unsigned char mod_order, + unsigned short nb_rb, + unsigned char output_shift) { #ifdef DEBUG_CH_COMP int16_t *rxF, *ul_ch; @@ -782,7 +807,7 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, symbol_mod = (symbol>=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol; if ((symbol_mod == 0) || (symbol_mod == (4-frame_parms->Ncp))) { - if (frame_parms->nb_antenna_ports_eNB==1) { // 10 out of 12 so don't reduce size + if (frame_parms->nb_antenna_ports_gNB==1) { // 10 out of 12 so don't reduce size nb_rb=1+(5*nb_rb/6); } else { @@ -790,7 +815,7 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, } } - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) { + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { if (mod_order == 4) { QAM_amp128 = vmovq_n_s16(QAM16_n1); // 2/sqrt(10) QAM_amp128b = vmovq_n_s16(0); @@ -1001,139 +1026,150 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, unsigned char harq_pid) { - uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol - NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu.ulsch_pdu_rel15; + uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag, ptrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol uint32_t nb_re_pusch, bwp_start_subcarrier; - uint8_t mapping_type; + uint8_t L_ptrs = 0; // PTRS parameter int avgs; int avg[4]; + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; + nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; dmrs_symbol_flag = 0; + ptrs_symbol_flag = 0; first_symbol_flag = 0; - mapping_type = gNB->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; + gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0; - if (mapping_type == typeB) { + if(symbol == rel15_ul->start_symbol_index){ + gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0; + gNB->pusch_vars[UE_id]->dmrs_symbol = 0; + gNB->pusch_vars[UE_id]->cl_done = 0; + gNB->pusch_vars[UE_id]->ptrs_symbols = 0; + first_symbol_flag = 1; - if(symbol == rel15_ul->start_symbol){ - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0; - gNB->pusch_vars[UE_id]->dmrs_symbol = 0; - first_symbol_flag = 1; + if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu + L_ptrs = 1<<(rel15_ul->pusch_ptrs.ptrs_time_density); + + set_ptrs_symb_idx(&gNB->pusch_vars[UE_id]->ptrs_symbols, + rel15_ul->nr_of_symbols, + rel15_ul->start_symbol_index, + rel15_ul->dmrs_config_type, + L_ptrs, + 1, // only dmrs of length 1 is currently supported + frame_parms->ofdm_symbol_size); } - - bwp_start_subcarrier = (rel15_ul->start_rb*NR_NB_SC_PER_RB + frame_parms->first_carrier_offset) % frame_parms->ofdm_symbol_size; - - dmrs_symbol_flag = is_dmrs_symbol(symbol, - 0, - 0, - 0, - 0, - 0, - rel15_ul->number_symbols, - &gNB->dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); - - if (dmrs_symbol_flag == 1){ - nb_re_pusch = rel15_ul->number_rbs * ((gNB->dmrs_UplinkConfig.pusch_dmrs_type==pusch_dmrs_type1)?6:8); - gNB->pusch_vars[UE_id]->dmrs_symbol = symbol; - } else { - nb_re_pusch = rel15_ul->number_rbs * NR_NB_SC_PER_RB; - } - - - //---------------------------------------------------------- - //--------------------- Channel estimation --------------------- - //---------------------------------------------------------- - - if (dmrs_symbol_flag == 1) - nr_pusch_channel_estimation(gNB, - 0, - nr_tti_rx, - 0, // p - symbol, - bwp_start_subcarrier, - rel15_ul->number_rbs, - &gNB->dmrs_UplinkConfig); - - //---------------------------------------------------------- - //--------------------- RBs extraction --------------------- - //---------------------------------------------------------- - - nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, - gNB->pusch_vars[UE_id]->ul_ch_estimates, - gNB->pusch_vars[UE_id]->rxdataF_ext, - gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - gNB->pusch_vars[UE_id]->rxdataF_ext_offset, - // rb_alloc, [hna] Resource Allocation Type 1 is assumed only for the moment - symbol, - rel15_ul->start_rb, - rel15_ul->number_rbs, - frame_parms, - gNB->pusch_vars[UE_id]->dmrs_symbol, - rel15_ul->number_symbols, - mapping_type, - &gNB->dmrs_UplinkConfig); - - nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - frame_parms, - gNB->ulsch[UE_id], - symbol, - dmrs_symbol_flag, - rel15_ul->number_rbs, - gNB->dmrs_UplinkConfig.pusch_dmrs_type); - - if (first_symbol_flag==1) { - - nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - frame_parms, - avg, - symbol, - nb_re_pusch, - rel15_ul->number_rbs); - avgs = 0; - - for (aatx=0;aatxnb_antennas_tx;aatx++) - for (aarx=0;aarxnb_antennas_rx;aarx++) - avgs = cmax(avgs,avg[(aatx<<1)+aarx]); - - gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; - - } - - nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, - gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - gNB->pusch_vars[UE_id]->ul_ch_mag0, - gNB->pusch_vars[UE_id]->ul_ch_magb0, - gNB->pusch_vars[UE_id]->rxdataF_comp, - (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[UE_id]->rho : NULL, - frame_parms, - symbol, - dmrs_symbol_flag, - rel15_ul->Qm, - rel15_ul->number_rbs, - gNB->pusch_vars[UE_id]->log2_maxh); - - #ifdef NR_SC_FDMA - nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->number_rbs * NR_NB_SC_PER_RB], nb_re_pusch); - #endif - - //---------------------------------------------------------- - //-------------------- LLRs computation -------------------- - //---------------------------------------------------------- - - nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->number_rbs * NR_NB_SC_PER_RB], - gNB->pusch_vars[UE_id]->ul_ch_mag0, - gNB->pusch_vars[UE_id]->ul_ch_magb0, - &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->Qm], - rel15_ul->number_rbs, - nb_re_pusch, - symbol, - rel15_ul->Qm); - - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch; - } else { - LOG_E(PHY, "PUSCH mapping type A is not supported \n"); } + + bwp_start_subcarrier = (rel15_ul->rb_start*NR_NB_SC_PER_RB + frame_parms->first_carrier_offset) % frame_parms->ofdm_symbol_size; + + dmrs_symbol_flag = ((rel15_ul->ul_dmrs_symb_pos)>>symbol)&0x01; + + if (dmrs_symbol_flag == 1){ + nb_re_pusch = rel15_ul->rb_size * ((rel15_ul->dmrs_config_type==pusch_dmrs_type1)?6:8); + gNB->pusch_vars[UE_id]->dmrs_symbol = symbol; + } else { + nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; + } + + if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu + ptrs_symbol_flag = is_ptrs_symbol(symbol, + 0, + rel15_ul->rnti, + rel15_ul->rb_size, + rel15_ul->nr_of_symbols, + 0, + (rel15_ul->pusch_ptrs.ptrs_freq_density)?4:2, + gNB->pusch_vars[UE_id]->ptrs_symbols, + 0, + frame_parms->ofdm_symbol_size, + rel15_ul->dmrs_config_type, + rel15_ul->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset); + } + + if (ptrs_symbol_flag == 1){ + gNB->pusch_vars[UE_id]->ptrs_symbol_index = symbol; + } + + + //---------------------------------------------------------- + //--------------------- Channel estimation --------------------- + //---------------------------------------------------------- + + if (dmrs_symbol_flag == 1) + nr_pusch_channel_estimation(gNB, + nr_tti_rx, + 0, // p + symbol, + bwp_start_subcarrier, + rel15_ul); + + //---------------------------------------------------------- + //--------------------- RBs extraction --------------------- + //---------------------------------------------------------- + + nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, + gNB->pusch_vars[UE_id], + symbol, + dmrs_symbol_flag, + rel15_ul, + frame_parms); + + nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, + frame_parms, + gNB->ulsch[UE_id], + symbol, + dmrs_symbol_flag, + rel15_ul->rb_size, + rel15_ul->dmrs_config_type); + + + if (first_symbol_flag==1) { + + nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, + frame_parms, + avg, + symbol, + nb_re_pusch, + rel15_ul->rb_size); + avgs = 0; + + for (aatx=0;aatxnb_antennas_tx;aatx++) + for (aarx=0;aarxnb_antennas_rx;aarx++) + avgs = cmax(avgs,avg[(aatx<<1)+aarx]); + + gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; + + } + + nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, + gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, + gNB->pusch_vars[UE_id]->ul_ch_mag0, + gNB->pusch_vars[UE_id]->ul_ch_magb0, + gNB->pusch_vars[UE_id]->rxdataF_comp, + (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[UE_id]->rho : NULL, + frame_parms, + symbol, + dmrs_symbol_flag, + rel15_ul->qam_mod_order, + rel15_ul->rb_size, + gNB->pusch_vars[UE_id]->log2_maxh); + +#ifdef NR_SC_FDMA + nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); +#endif + + //---------------------------------------------------------- + //-------------------- LLRs computation -------------------- + //---------------------------------------------------------- + + nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], + gNB->pusch_vars[UE_id]->ul_ch_mag0, + gNB->pusch_vars[UE_id]->ul_ch_magb0, + &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order], + rel15_ul->rb_size, + nb_re_pusch, + symbol, + rel15_ul->qam_mod_order); + + gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch - gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol; } diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c index 09dadabaa5..be5c754beb 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c @@ -206,9 +206,6 @@ int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue, int16_t ch[2],*pil,*rxF,*dl_ch,*fl,*fm,*fr; int ch_offset,symbol_offset; //int slot_pbch; - //fapi_nr_pbch_config_t *pbch_config = &ue->nrUE_config.pbch_config; - // initialized to 5ms in nr_init_ue for scenarios where UE is not configured (otherwise acquired by cell configuration from gNB or LTE) - //uint8_t ssb_periodicity = 10;// ue->ssb_periodicity; //uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1]; @@ -452,7 +449,7 @@ int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue, { // do ifft of channel estimate for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) - for (p=0; pframe_parms.nb_antenna_ports_eNB; p++) { + for (p=0; pframe_parms.nb_antenna_ports_gNB; p++) { if (ue->pbch_vars[eNB_offset]->dl_ch_estimates[(p<<1)+aarx]) { LOG_D(PHY,"Channel Impulse Computation Slot %d ThreadId %d Symbol %d ch_offset %d\n", Ns, ue->current_thread_id[Ns], symbol, ch_offset); @@ -475,7 +472,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, unsigned short coreset_start_subcarrier, unsigned short nb_rb_coreset) { - int pilot[200] __attribute__((aligned(16))); + unsigned char aarx; unsigned short k; unsigned int pilot_cnt; @@ -484,12 +481,9 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, //uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1]; - uint8_t nushift; int **dl_ch_estimates =ue->pdcch_vars[ue->current_thread_id[Ns]][eNB_offset]->dl_ch_estimates; int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF; - nushift = 1; - ue->frame_parms.nushift = nushift; if (ue->high_speed_flag == 0) // use second channel estimate position for temporary storage ch_offset = ue->frame_parms.ofdm_symbol_size ; @@ -510,14 +504,15 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, fr = filt16a_r1; - // generate pilot + // generate pilot + int pilot[nb_rb_coreset * 3] __attribute__((aligned(16))); nr_pdcch_dmrs_rx(ue,eNB_offset,Ns,ue->nr_gold_pdcch[eNB_offset][Ns][symbol], &pilot[0],2000,nb_rb_coreset); for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { pil = (int16_t *)&pilot[0]; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)]; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+1)]; dl_ch = (int16_t *)&dl_ch_estimates[aarx][ch_offset]; memset(dl_ch,0,4*(ue->frame_parms.ofdm_symbol_size)); @@ -588,7 +583,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, if (k >= ue->frame_parms.ofdm_symbol_size){ k-=ue->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)];} + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+1)];} ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); @@ -622,7 +617,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PDCCH - printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); #endif multadd_real_vector_complex_scalar(fr, diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h index ba328e39ec..af06f9a98f 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h @@ -90,11 +90,6 @@ void phy_adjust_gain_nr(PHY_VARS_NR_UE *ue, uint32_t rx_power_fil_dB, uint8_t eNB_id); -/*! \brief Function to return the path-loss based on the UE cell-specific reference signal strength and transmission power of eNB -@param Mod_id Module ID for UE -@param eNB_index Index of eNB on which to act -@returns Path loss in dB - */ -int16_t nr_get_PL(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index); +int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index); #endif diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c index ac9713fec2..aa1e2b5ade 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c @@ -19,8 +19,6 @@ * contact@openairinterface.org */ -// this function fills the PHY_vars->PHY_measurement structure - #include "PHY/defs_nr_UE.h" #include "PHY/phy_extern_nr_ue.h" #include "common/utils/LOG/log.h" @@ -57,649 +55,28 @@ void print_ints(char *s,int *x) } #endif -int16_t nr_get_PL(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index) +int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index) { - PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; /* - int RSoffset; - - if (ue->frame_parms.mode1_flag == 1) RSoffset = 6; else RSoffset = 3; */ - /* LOG_D(PHY,"nr_get_PL : rsrp %f dBm/RE (%f), eNB power %d dBm/RE\n", + /* LOG_D(PHY,"get_nr_PL : rsrp %f dBm/RE (%f), eNB power %d dBm/RE\n", (1.0*dB_fixed_times10(ue->measurements.rsrp[eNB_index])-(10.0*ue->rx_total_gain_dB))/10.0, 10*log10((double)ue->measurements.rsrp[eNB_index]), ue->frame_parms.pdsch_config_common.referenceSignalPower);*/ - return((int16_t)(((10*ue->rx_total_gain_dB) - - dB_fixed_times10(ue->measurements.rsrp[eNB_index]))/10)); + return((int16_t)(((10*ue->rx_total_gain_dB) - dB_fixed_times10(ue->measurements.rsrp[gNB_index]))/10)); // dB_fixed_times10(RSoffset*12*ue_g[Mod_id][CC_id]->frame_parms.N_RB_DL) + //(ue->frame_parms.pdsch_config_common.referenceSignalPower*10))/10)); } -#if 0 -uint8_t get_n_adj_cells (module_id_t Mod_id,uint8_t CC_id) -{ - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) - return ue->measurements.n_adj_cells; - else - return 0; -} - -uint32_t get_rx_total_gain_dB (module_id_t Mod_id,uint8_t CC_id) -{ - - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) - return ue->rx_total_gain_dB; - - return 0xFFFFFFFF; -} -uint32_t get_RSSI (module_id_t Mod_id,uint8_t CC_id) -{ - - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) - return ue->measurements.rssi; - - return 0xFFFFFFFF; -} -double get_RSRP(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - AssertFatal(PHY_vars_UE_g!=NULL,"PHY_vars_UE_g is null\n"); - AssertFatal(PHY_vars_UE_g[Mod_id]!=NULL,"PHY_vars_UE_g[%d] is null\n",Mod_id); - AssertFatal(PHY_vars_UE_g[Mod_id][CC_id]!=NULL,"PHY_vars_UE_g[%d][%d] is null\n",Mod_id,CC_id); - - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) - return ((dB_fixed_times10(ue->measurements.rsrp[eNB_index]))/10.0- - get_rx_total_gain_dB(Mod_id,0) - - 10*log10(ue->frame_parms.N_RB_DL*12)); - return -140.0; -} - -uint32_t get_RSRQ(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) - return ue->measurements.rsrq[eNB_index]; - - return 0xFFFFFFFF; -} - -int8_t set_RSRP_filtered(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index,float rsrp) -{ - - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) { - ue->measurements.rsrp_filtered[eNB_index]=rsrp; - return 0; - } - - LOG_W(PHY,"[UE%d] could not set the rsrp\n",Mod_id); - return -1; -} - -int8_t set_RSRQ_filtered(module_id_t Mod_id,uint8_t CC_id,uint8_t eNB_index,float rsrq) -{ - - PHY_VARS_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - if (ue) { - ue->measurements.rsrq_filtered[eNB_index]=rsrq; - return 0; - } - - LOG_W(PHY,"[UE%d] could not set the rsrq\n",Mod_id); - return -1; - -} -#endif - -#if 0 -void ue_rrc_measurements(PHY_VARS_UE *ue, - uint8_t slot, - uint8_t abstraction_flag) -{ - - uint8_t subframe = slot>>1; - int aarx,rb; - uint8_t pss_symb; - uint8_t sss_symb; - - int32_t **rxdataF; - int16_t *rxF,*rxF_pss,*rxF_sss; - - uint16_t Nid_cell = ue->frame_parms.Nid_cell; - uint8_t eNB_offset,nu,l,nushift,k; - uint16_t off; - uint8_t previous_thread_id = ue->current_thread_id[subframe]==0 ? (RX_NB_TH-1):(ue->current_thread_id[subframe]-1); - - //uint8_t isPss; // indicate if this is a slot for extracting PSS - //uint8_t isSss; // indicate if this is a slot for extracting SSS - //int32_t pss_ext[4][72]; // contain the extracted 6*12 REs for mapping the PSS - //int32_t sss_ext[4][72]; // contain the extracted 6*12 REs for mapping the SSS - //int32_t (*xss_ext)[72]; // point to either pss_ext or sss_ext for common calculation - //int16_t *re,*im; // real and imag part of each 32-bit xss_ext[][] value - - //LOG_I(PHY,"UE RRC MEAS Start Subframe %d Frame Type %d slot %d \n",subframe,ue->frame_parms.frame_type,slot); - for (eNB_offset = 0; eNB_offset<1+ue->measurements.n_adj_cells; eNB_offset++) { - - if (eNB_offset==0) { - ue->measurements.rssi = 0; - //ue->measurements.n0_power_tot = 0; - - if (abstraction_flag == 0) { - if ( ((ue->frame_parms.frame_type == FDD) && ((subframe == 0) || (subframe == 5))) || - ((ue->frame_parms.frame_type == TDD) && ((subframe == 1) || (subframe == 6))) - ) - { // FDD PSS/SSS, compute noise in DTX REs - if (ue->frame_parms.Ncp == NORMAL) { - for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { - if(ue->frame_parms.frame_type == FDD) - { - rxF_sss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(5*ue->frame_parms.ofdm_symbol_size)]; - rxF_pss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(6*ue->frame_parms.ofdm_symbol_size)]; - } - else - { - rxF_sss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[previous_thread_id].rxdataF[aarx][(13*ue->frame_parms.ofdm_symbol_size)]; - rxF_pss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(2*ue->frame_parms.ofdm_symbol_size)]; - } - //-ve spectrum from SSS - - //+ve spectrum from SSS - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+70]*rxF_sss[2+70])+((int32_t)rxF_sss[2+69]*rxF_sss[2+69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+68]*rxF_sss[2+68])+((int32_t)rxF_sss[2+67]*rxF_sss[2+67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+66]*rxF_sss[2+66])+((int32_t)rxF_sss[2+65]*rxF_sss[2+65])); - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+64]*rxF_sss[2+64])+((int32_t)rxF_sss[2+63]*rxF_sss[2+63])); - // printf("sssp32 %d\n",ue->measurements.n0_power[aarx]); - //+ve spectrum from PSS - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+70]*rxF_pss[2+70])+((int32_t)rxF_pss[2+69]*rxF_pss[2+69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+68]*rxF_pss[2+68])+((int32_t)rxF_pss[2+67]*rxF_pss[2+67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+66]*rxF_pss[2+66])+((int32_t)rxF_pss[2+65]*rxF_pss[2+65])); - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+64]*rxF_pss[2+64])+((int32_t)rxF_pss[2+63]*rxF_pss[2+63])); - // printf("pss32 %d\n",ue->measurements.n0_power[aarx]); //-ve spectrum from PSS - if(ue->frame_parms.frame_type == FDD) - { - rxF_sss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(6*ue->frame_parms.ofdm_symbol_size)]; - rxF_pss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(7*ue->frame_parms.ofdm_symbol_size)]; - } - else - { - rxF_sss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[previous_thread_id].rxdataF[aarx][(14*ue->frame_parms.ofdm_symbol_size)]; - rxF_pss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(3*ue->frame_parms.ofdm_symbol_size)]; - } - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-72]*rxF_pss[-72])+((int32_t)rxF_pss[-71]*rxF_pss[-71])); - // printf("pssm36 %d\n",ue->measurements.n0_power[aarx]); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-70]*rxF_pss[-70])+((int32_t)rxF_pss[-69]*rxF_pss[-69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-68]*rxF_pss[-68])+((int32_t)rxF_pss[-67]*rxF_pss[-67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-66]*rxF_pss[-66])+((int32_t)rxF_pss[-65]*rxF_pss[-65])); - - ue->measurements.n0_power[aarx] = (((int32_t)rxF_sss[-70]*rxF_sss[-70])+((int32_t)rxF_sss[-69]*rxF_sss[-69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[-68]*rxF_sss[-68])+((int32_t)rxF_sss[-67]*rxF_sss[-67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[-66]*rxF_sss[-66])+((int32_t)rxF_sss[-65]*rxF_sss[-65])); - - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-64]*rxF_pss[-64])+((int32_t)rxF_pss[-63]*rxF_pss[-63])); - // printf("pssm32 %d\n",ue->measurements.n0_power[aarx]); - ue->measurements.n0_power_dB[aarx] = (unsigned short) dB_fixed(ue->measurements.n0_power[aarx]/12); - ue->measurements.n0_power_tot /*+=*/ = ue->measurements.n0_power[aarx]; - } - - //LOG_I(PHY,"Subframe %d RRC UE MEAS Noise Level %d \n", subframe, ue->measurements.n0_power_tot); - - ue->measurements.n0_power_tot_dB = (unsigned short) dB_fixed(ue->measurements.n0_power_tot/(12*aarx)); - ue->measurements.n0_power_tot_dBm = ue->measurements.n0_power_tot_dB - ue->rx_total_gain_dB - dB_fixed(ue->frame_parms.ofdm_symbol_size); - } else { - LOG_E(PHY, "Not yet implemented: noise power calculation when prefix length == EXTENDED\n"); - } - } - else if ((ue->frame_parms.frame_type == TDD) && - ((subframe == 1) || (subframe == 6))) { // TDD PSS/SSS, compute noise in DTX REs // 2016-09-29 wilson fix incorrect noise power calculation - - - pss_symb = 2; - sss_symb = ue->frame_parms.symbols_per_tti-1; - if (ue->frame_parms.Ncp==NORMAL) { - for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { - - rxdataF = ue->common_vars.common_vars_rx_data_per_thread[(ue->current_thread_id[subframe])].rxdataF; - rxF_pss = (int16_t *) &rxdataF[aarx][((pss_symb*(ue->frame_parms.ofdm_symbol_size)))]; - - rxdataF = ue->common_vars.common_vars_rx_data_per_thread[previous_thread_id].rxdataF; - rxF_sss = (int16_t *) &rxdataF[aarx][((sss_symb*(ue->frame_parms.ofdm_symbol_size)))]; - - //-ve spectrum from SSS - // printf("slot %d: SSS DTX: %d,%d, non-DTX %d,%d\n",slot,rxF_pss[-72],rxF_pss[-71],rxF_pss[-36],rxF_pss[-35]); - - // ue->measurements.n0_power[aarx] = (((int32_t)rxF_pss[-72]*rxF_pss[-72])+((int32_t)rxF_pss[-71]*rxF_pss[-71])); - // printf("sssn36 %d\n",ue->measurements.n0_power[aarx]); - ue->measurements.n0_power[aarx] = (((int32_t)rxF_pss[-70]*rxF_pss[-70])+((int32_t)rxF_pss[-69]*rxF_pss[-69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-68]*rxF_pss[-68])+((int32_t)rxF_pss[-67]*rxF_pss[-67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-66]*rxF_pss[-66])+((int32_t)rxF_pss[-65]*rxF_pss[-65])); - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-64]*rxF_pss[-64])+((int32_t)rxF_pss[-63]*rxF_pss[-63])); - // printf("sssm32 %d\n",ue->measurements.n0_power[aarx]); - //+ve spectrum from SSS - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+70]*rxF_sss[2+70])+((int32_t)rxF_sss[2+69]*rxF_sss[2+69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+68]*rxF_sss[2+68])+((int32_t)rxF_sss[2+67]*rxF_sss[2+67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+66]*rxF_sss[2+66])+((int32_t)rxF_sss[2+65]*rxF_sss[2+65])); - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_sss[2+64]*rxF_sss[2+64])+((int32_t)rxF_sss[2+63]*rxF_sss[2+63])); - // printf("sssp32 %d\n",ue->measurements.n0_power[aarx]); - //+ve spectrum from PSS - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+70]*rxF_pss[2+70])+((int32_t)rxF_pss[2+69]*rxF_pss[2+69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+68]*rxF_pss[2+68])+((int32_t)rxF_pss[2+67]*rxF_pss[2+67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+66]*rxF_pss[2+66])+((int32_t)rxF_pss[2+65]*rxF_pss[2+65])); - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[2+64]*rxF_pss[2+64])+((int32_t)rxF_pss[2+63]*rxF_pss[2+63])); - // printf("pss32 %d\n",ue->measurements.n0_power[aarx]); //-ve spectrum from PSS - rxF_pss = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(7*ue->frame_parms.ofdm_symbol_size)]; - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-72]*rxF_pss[-72])+((int32_t)rxF_pss[-71]*rxF_pss[-71])); - // printf("pssm36 %d\n",ue->measurements.n0_power[aarx]); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-70]*rxF_pss[-70])+((int32_t)rxF_pss[-69]*rxF_pss[-69])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-68]*rxF_pss[-68])+((int32_t)rxF_pss[-67]*rxF_pss[-67])); - ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-66]*rxF_pss[-66])+((int32_t)rxF_pss[-65]*rxF_pss[-65])); - // ue->measurements.n0_power[aarx] += (((int32_t)rxF_pss[-64]*rxF_pss[-64])+((int32_t)rxF_pss[-63]*rxF_pss[-63])); - // printf("pssm32 %d\n",ue->measurements.n0_power[aarx]); - ue->measurements.n0_power_dB[aarx] = (unsigned short) dB_fixed(ue->measurements.n0_power[aarx]/12); - ue->measurements.n0_power_tot /*+=*/ = ue->measurements.n0_power[aarx]; - } - - ue->measurements.n0_power_tot_dB = (unsigned short) dB_fixed(ue->measurements.n0_power_tot/(12*aarx)); - ue->measurements.n0_power_tot_dBm = ue->measurements.n0_power_tot_dB - ue->rx_total_gain_dB - dB_fixed(ue->frame_parms.ofdm_symbol_size); - - //LOG_I(PHY,"Subframe %d RRC UE MEAS Noise Level %d \n", subframe, ue->measurements.n0_power_tot); - - } - } - } - } - // recompute nushift with eNB_offset corresponding to adjacent eNB on which to perform channel estimation - // printf("[PHY][UE %d] Frame %d slot %d Doing ue_rrc_measurements rsrp/rssi (Nid_cell %d, Nid2 %d, nushift %d, eNB_offset %d)\n",ue->Mod_id,ue->frame,slot,Nid_cell,Nid2,nushift,eNB_offset); - if (eNB_offset > 0) - Nid_cell = ue->measurements.adj_cell_id[eNB_offset-1]; - - - nushift = Nid_cell%6; - - - - ue->measurements.rsrp[eNB_offset] = 0; - - - if (abstraction_flag == 0) { - - // compute RSRP using symbols 0 and 4-frame_parms->Ncp - - for (l=0,nu=0; l<=(4-ue->frame_parms.Ncp); l+=(4-ue->frame_parms.Ncp),nu=3) { - k = (nu + nushift)%6; - //#ifdef DEBUG_MEAS_RRC - LOG_D(PHY,"[UE %d] Frame %d subframe %d Doing ue_rrc_measurements rsrp/rssi (Nid_cell %d, nushift %d, eNB_offset %d, k %d, l %d)\n",ue->Mod_id,ue->proc.proc_rxtx[subframe&1].frame_rx,subframe,Nid_cell,nushift, - eNB_offset,k,l); - //#endif - - for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { - rxF = (int16_t *)&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF[aarx][(l*ue->frame_parms.ofdm_symbol_size)]; - off = (ue->frame_parms.first_carrier_offset+k)<<1; - - if (l==(4-ue->frame_parms.Ncp)) { - for (rb=0; rbframe_parms.N_RB_DL; rb++) { - - // printf("rb %d, off %d, off2 %d\n",rb,off,off2); - - ue->measurements.rsrp[eNB_offset] += (((int32_t)(rxF[off])*rxF[off])+((int32_t)(rxF[off+1])*rxF[off+1])); - // printf("rb %d, off %d : %d\n",rb,off,((((int32_t)rxF[off])*rxF[off])+((int32_t)(rxF[off+1])*rxF[off+1]))); - // if ((ue->frame_rx&0x3ff) == 0) - // printf("rb %d, off %d : %d\n",rb,off,((rxF[off]*rxF[off])+(rxF[off+1]*rxF[off+1]))); - - - off+=12; - - if (off>=(ue->frame_parms.ofdm_symbol_size<<1)) - off = (1+k)<<1; - - ue->measurements.rsrp[eNB_offset] += (((int32_t)(rxF[off])*rxF[off])+((int32_t)(rxF[off+1])*rxF[off+1])); - // printf("rb %d, off %d : %d\n",rb,off,(((int32_t)(rxF[off])*rxF[off])+((int32_t)(rxF[off+1])*rxF[off+1]))); - /* - if ((ue->frame_rx&0x3ff) == 0) - printf("rb %d, off %d : %d\n",rb,off,((rxF[off]*rxF[off])+(rxF[off+1]*rxF[off+1]))); - */ - off+=12; - - if (off>=(ue->frame_parms.ofdm_symbol_size<<1)) - off = (1+k)<<1; - - } - - /* - if ((eNB_offset==0)&&(l==0)) { - for (i=0;i<6;i++,off2+=4) - ue->measurements.rssi += ((rxF[off2]*rxF[off2])+(rxF[off2+1]*rxF[off2+1])); - if (off2==(ue->frame_parms.ofdm_symbol_size<<2)) - off2=4; - for (i=0;i<6;i++,off2+=4) - ue->measurements.rssi += ((rxF[off2]*rxF[off2])+(rxF[off2+1]*rxF[off2+1])); - } - */ - // printf("slot %d, rb %d => rsrp %d, rssi %d\n",slot,rb,ue->measurements.rsrp[eNB_offset],ue->measurements.rssi); - } - } - } - - // 2 RE per PRB - // ue->measurements.rsrp[eNB_offset]/=(24*ue->frame_parms.N_RB_DL); - ue->measurements.rsrp[eNB_offset]/=(2*ue->frame_parms.N_RB_DL*ue->frame_parms.ofdm_symbol_size); - // LOG_I(PHY,"eNB: %d, RSRP: %d \n",eNB_offset,ue->measurements.rsrp[eNB_offset]); - if (eNB_offset == 0) { - // ue->measurements.rssi/=(24*ue->frame_parms.N_RB_DL); - // ue->measurements.rssi*=rx_power_correction; - // ue->measurements.rssi=ue->measurements.rsrp[0]*24/2; - ue->measurements.rssi=ue->measurements.rsrp[0]*(12*ue->frame_parms.N_RB_DL); - } - - if (ue->measurements.rssi>0) - ue->measurements.rsrq[eNB_offset] = 100*ue->measurements.rsrp[eNB_offset]*ue->frame_parms.N_RB_DL/ue->measurements.rssi; - else - ue->measurements.rsrq[eNB_offset] = -12000; - - //((200*ue->measurements.rsrq[eNB_offset]) + ((1024-200)*100*ue->measurements.rsrp[eNB_offset]*ue->frame_parms.N_RB_DL/ue->measurements.rssi))>>10; - } else { // Do abstraction of RSRP and RSRQ - ue->measurements.rssi = ue->measurements.rx_power_avg[0]; - // dummay value for the moment - ue->measurements.rsrp[eNB_offset] = -93 ; - ue->measurements.rsrq[eNB_offset] = 3; - - } - - //#ifdef DEBUG_MEAS_RRC - - // if (slot == 0) { - - if (eNB_offset == 0) - - LOG_D(PHY,"[UE %d] Frame %d, subframe %d RRC Measurements => rssi %3.1f dBm (digital: %3.1f dB, gain %d), N0 %d dBm\n",ue->Mod_id, - ue->proc.proc_rxtx[subframe&1].frame_rx,subframe,10*log10(ue->measurements.rssi)-ue->rx_total_gain_dB, - 10*log10(ue->measurements.rssi), - ue->rx_total_gain_dB, - ue->measurements.n0_power_tot_dBm); - - LOG_D(PHY,"[UE %d] Frame %d, subframe %d RRC Measurements (idx %d, Cell id %d) => rsrp: %3.1f dBm/RE (%d), rsrq: %3.1f dB\n", - ue->Mod_id, - ue->proc.proc_rxtx[subframe&1].frame_rx,subframe,eNB_offset, - (eNB_offset>0) ? ue->measurements.adj_cell_id[eNB_offset-1] : ue->frame_parms.Nid_cell, - 10*log10(ue->measurements.rsrp[eNB_offset])-ue->rx_total_gain_dB, - ue->measurements.rsrp[eNB_offset], - (10*log10(ue->measurements.rsrq[eNB_offset]))); - //LOG_D(PHY,"RSRP_total_dB: %3.2f \n",(dB_fixed_times10(ue->measurements.rsrp[eNB_offset])/10.0)-ue->rx_total_gain_dB-dB_fixed(ue->frame_parms.N_RB_DL*12)); - - //LOG_D(PHY,"RSRP_dB: %3.2f \n",(dB_fixed_times10(ue->measurements.rsrp[eNB_offset])/10.0)); - //LOG_D(PHY,"gain_loss_dB: %d \n",ue->rx_total_gain_dB); - //LOG_D(PHY,"gain_fixed_dB: %d \n",dB_fixed(ue->frame_parms.N_RB_DL*12)); - - // } - - //#endif - } - -} -#endif - -#if 0 -void conjch0_mult_ch1(int *ch0, - int *ch1, - int32_t *ch0conj_ch1, - unsigned short nb_rb, - unsigned char output_shift0) -{ - //This function is used to compute multiplications in Hhermitian * H matrix - unsigned short rb; - __m128i *dl_ch0_128,*dl_ch1_128, *ch0conj_ch1_128, mmtmpD0,mmtmpD1,mmtmpD2,mmtmpD3; - - dl_ch0_128 = (__m128i *)ch0; - dl_ch1_128 = (__m128i *)ch1; - - ch0conj_ch1_128 = (__m128i *)ch0conj_ch1; - - for (rb=0; rb<3*nb_rb; rb++) { - - mmtmpD0 = _mm_madd_epi16(dl_ch0_128[0],dl_ch1_128[0]); - mmtmpD1 = _mm_shufflelo_epi16(dl_ch0_128[0],_MM_SHUFFLE(2,3,0,1)); - mmtmpD1 = _mm_shufflehi_epi16(mmtmpD1,_MM_SHUFFLE(2,3,0,1)); - mmtmpD1 = _mm_sign_epi16(mmtmpD1,*(__m128i*)&conjugate[0]); - mmtmpD1 = _mm_madd_epi16(mmtmpD1,dl_ch1_128[0]); - mmtmpD0 = _mm_srai_epi32(mmtmpD0,output_shift0); - mmtmpD1 = _mm_srai_epi32(mmtmpD1,output_shift0); - mmtmpD2 = _mm_unpacklo_epi32(mmtmpD0,mmtmpD1); - mmtmpD3 = _mm_unpackhi_epi32(mmtmpD0,mmtmpD1); - - ch0conj_ch1_128[0] = _mm_packs_epi32(mmtmpD2,mmtmpD3); - -#ifdef DEBUG_RANK_EST - printf("\n Computing conjugates \n"); - print_shorts("ch0:",(int16_t*)&dl_ch0_128[0]); - print_shorts("ch1:",(int16_t*)&dl_ch1_128[0]); - print_shorts("pack:",(int16_t*)&ch0conj_ch1_128[0]); -#endif - - dl_ch0_128+=1; - dl_ch1_128+=1; - ch0conj_ch1_128+=1; - } - _mm_empty(); - _m_empty(); -} - -void construct_HhH_elements(int *ch0conj_ch0, //00_00 - int *ch1conj_ch1,//01_01 - int *ch2conj_ch2,//11_11 - int *ch3conj_ch3,//10_10 - int *ch0conj_ch1,//00_01 - int *ch1conj_ch0,//01_00 - int *ch2conj_ch3,//10_11 - int *ch3conj_ch2,//11_10 - int32_t *after_mf_00, - int32_t *after_mf_01, - int32_t *after_mf_10, - int32_t *after_mf_11, - unsigned short nb_rb) -{ - unsigned short rb; - __m128i *ch0conj_ch0_128, *ch1conj_ch1_128, *ch2conj_ch2_128, *ch3conj_ch3_128; - __m128i *ch0conj_ch1_128, *ch1conj_ch0_128, *ch2conj_ch3_128, *ch3conj_ch2_128; - __m128i *after_mf_00_128, *after_mf_01_128, *after_mf_10_128, *after_mf_11_128; - - ch0conj_ch0_128 = (__m128i *)ch0conj_ch0; - ch1conj_ch1_128 = (__m128i *)ch1conj_ch1; - ch2conj_ch2_128 = (__m128i *)ch2conj_ch2; - ch3conj_ch3_128 = (__m128i *)ch3conj_ch3; - ch0conj_ch1_128 = (__m128i *)ch0conj_ch1; - ch1conj_ch0_128 = (__m128i *)ch1conj_ch0; - ch2conj_ch3_128 = (__m128i *)ch2conj_ch3; - ch3conj_ch2_128 = (__m128i *)ch3conj_ch2; - after_mf_00_128 = (__m128i *)after_mf_00; - after_mf_01_128 = (__m128i *)after_mf_01; - after_mf_10_128 = (__m128i *)after_mf_10; - after_mf_11_128 = (__m128i *)after_mf_11; - - for (rb=0; rb<3*nb_rb; rb++) { - - after_mf_00_128[0] =_mm_adds_epi16(ch0conj_ch0_128[0],ch3conj_ch3_128[0]);// _mm_adds_epi32(ch0conj_ch0_128[0], ch3conj_ch3_128[0]); //00_00 + 10_10 - after_mf_11_128[0] =_mm_adds_epi16(ch1conj_ch1_128[0], ch2conj_ch2_128[0]); //01_01 + 11_11 - after_mf_01_128[0] =_mm_adds_epi16(ch0conj_ch1_128[0], ch2conj_ch3_128[0]);//00_01 + 10_11 - after_mf_10_128[0] =_mm_adds_epi16(ch1conj_ch0_128[0], ch3conj_ch2_128[0]);//01_00 + 11_10 - -#ifdef DEBUG_RANK_EST - printf(" \n construct_HhH_elements \n"); - print_shorts("ch0conj_ch0_128:",(int16_t*)&ch0conj_ch0_128[0]); - print_shorts("ch1conj_ch1_128:",(int16_t*)&ch1conj_ch1_128[0]); - print_shorts("ch2conj_ch2_128:",(int16_t*)&ch2conj_ch2_128[0]); - print_shorts("ch3conj_ch3_128:",(int16_t*)&ch3conj_ch3_128[0]); - print_shorts("ch0conj_ch1_128:",(int16_t*)&ch0conj_ch1_128[0]); - print_shorts("ch1conj_ch0_128:",(int16_t*)&ch1conj_ch0_128[0]); - print_shorts("ch2conj_ch3_128:",(int16_t*)&ch2conj_ch3_128[0]); - print_shorts("ch3conj_ch2_128:",(int16_t*)&ch3conj_ch2_128[0]); - print_shorts("after_mf_00_128:",(int16_t*)&after_mf_00_128[0]); - print_shorts("after_mf_01_128:",(int16_t*)&after_mf_01_128[0]); - print_shorts("after_mf_10_128:",(int16_t*)&after_mf_10_128[0]); - print_shorts("after_mf_11_128:",(int16_t*)&after_mf_11_128[0]); -#endif - - ch0conj_ch0_128+=1; - ch1conj_ch1_128+=1; - ch2conj_ch2_128+=1; - ch3conj_ch3_128+=1; - ch0conj_ch1_128+=1; - ch1conj_ch0_128+=1; - ch2conj_ch3_128+=1; - ch3conj_ch2_128+=1; - - after_mf_00_128+=1; - after_mf_01_128+=1; - after_mf_10_128+=1; - after_mf_11_128+=1; - } - _mm_empty(); - _m_empty(); -} - - -void squared_matrix_element(int32_t *Hh_h_00, - int32_t *Hh_h_00_sq, - unsigned short nb_rb) -{ - unsigned short rb; - __m128i *Hh_h_00_128,*Hh_h_00_sq_128; - - Hh_h_00_128 = (__m128i *)Hh_h_00; - Hh_h_00_sq_128 = (__m128i *)Hh_h_00_sq; - - for (rb=0; rb<3*nb_rb; rb++) { - - Hh_h_00_sq_128[0] = _mm_madd_epi16(Hh_h_00_128[0],Hh_h_00_128[0]); - -#ifdef DEBUG_RANK_EST - printf("\n Computing squared_matrix_element \n"); - print_shorts("Hh_h_00_128:",(int16_t*)&Hh_h_00_128[0]); - print_ints("Hh_h_00_sq_128:",(int32_t*)&Hh_h_00_sq_128[0]); -#endif - - Hh_h_00_sq_128+=1; - Hh_h_00_128+=1; - } - _mm_empty(); - _m_empty(); -} - - - -void det_HhH(int32_t *after_mf_00, - int32_t *after_mf_01, - int32_t *after_mf_10, - int32_t *after_mf_11, - int32_t *det_fin, - unsigned short nb_rb) - -{ - unsigned short rb; - __m128i *after_mf_00_128,*after_mf_01_128, *after_mf_10_128, *after_mf_11_128, ad_re_128, bc_re_128; - __m128i *det_fin_128, det_128; - - after_mf_00_128 = (__m128i *)after_mf_00; - after_mf_01_128 = (__m128i *)after_mf_01; - after_mf_10_128 = (__m128i *)after_mf_10; - after_mf_11_128 = (__m128i *)after_mf_11; - - det_fin_128 = (__m128i *)det_fin; - - for (rb=0; rb<3*nb_rb; rb++) { - - ad_re_128 = _mm_madd_epi16(after_mf_00_128[0],after_mf_11_128[0]); - bc_re_128 = _mm_madd_epi16(after_mf_01_128[0],after_mf_01_128[0]); - det_128 = _mm_sub_epi32(ad_re_128, bc_re_128); - det_fin_128[0] = _mm_abs_epi32(det_128); - -#ifdef DEBUG_RANK_EST - printf("\n Computing denominator \n"); - print_shorts("after_mf_00_128:",(int16_t*)&after_mf_00_128[0]); - print_shorts("after_mf_01_128:",(int16_t*)&after_mf_01_128[0]); - print_shorts("after_mf_10_128:",(int16_t*)&after_mf_10_128[0]); - print_shorts("after_mf_11_128:",(int16_t*)&after_mf_11_128[0]); - print_ints("ad_re_128:",(int32_t*)&ad_re_128); - print_ints("bc_re_128:",(int32_t*)&bc_re_128); - print_ints("det_fin_128:",(int32_t*)&det_fin_128[0]); -#endif - - det_fin_128+=1; - after_mf_00_128+=1; - after_mf_01_128+=1; - after_mf_10_128+=1; - after_mf_11_128+=1; - } - _mm_empty(); - _m_empty(); -} - -void numer(int32_t *Hh_h_00_sq, - int32_t *Hh_h_01_sq, - int32_t *Hh_h_10_sq, - int32_t *Hh_h_11_sq, - int32_t *num_fin, - unsigned short nb_rb) - -{ - unsigned short rb; - __m128i *h_h_00_sq_128, *h_h_01_sq_128, *h_h_10_sq_128, *h_h_11_sq_128; - __m128i *num_fin_128, sq_a_plus_sq_d_128, sq_b_plus_sq_c_128; - - h_h_00_sq_128 = (__m128i *)Hh_h_00_sq; - h_h_01_sq_128 = (__m128i *)Hh_h_01_sq; - h_h_10_sq_128 = (__m128i *)Hh_h_10_sq; - h_h_11_sq_128 = (__m128i *)Hh_h_11_sq; - - num_fin_128 = (__m128i *)num_fin; - - for (rb=0; rb<3*nb_rb; rb++) { - - sq_a_plus_sq_d_128 = _mm_add_epi32(h_h_00_sq_128[0],h_h_11_sq_128[0]); - sq_b_plus_sq_c_128 = _mm_add_epi32(h_h_01_sq_128[0],h_h_10_sq_128[0]); - num_fin_128[0] = _mm_add_epi32(sq_a_plus_sq_d_128, sq_b_plus_sq_c_128); - -#ifdef DEBUG_RANK_EST - printf("\n Computing numerator \n"); - print_ints("h_h_00_sq_128:",(int32_t*)&h_h_00_sq_128[0]); - print_ints("h_h_01_sq_128:",(int32_t*)&h_h_01_sq_128[0]); - print_ints("h_h_10_sq_128:",(int32_t*)&h_h_10_sq_128[0]); - print_ints("h_h_11_sq_128:",(int32_t*)&h_h_11_sq_128[0]); - print_shorts("sq_a_plus_sq_d_128:",(int16_t*)&sq_a_plus_sq_d_128); - print_shorts("sq_b_plus_sq_c_128:",(int16_t*)&sq_b_plus_sq_c_128); - print_shorts("num_fin_128:",(int16_t*)&num_fin_128[0]); -#endif - - num_fin_128+=1; - h_h_00_sq_128+=1; - h_h_01_sq_128+=1; - h_h_10_sq_128+=1; - h_h_11_sq_128+=1; - } - _mm_empty(); - _m_empty(); -} - -#endif void nr_ue_measurements(PHY_VARS_NR_UE *ue, unsigned int subframe_offset, @@ -735,7 +112,7 @@ void nr_ue_measurements(PHY_VARS_NR_UE *ue, for (eNB_id=0; eNB_idn_connected_eNB; eNB_id++) { for (aarx=0; aarxnb_antennas_rx; aarx++) { - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) { + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { ue->measurements.rx_spatial_power[eNB_id][aatx][aarx] = (signal_energy_nodc(&ue->pdsch_vars[ue->current_thread_id[subframe]][0]->dl_ch_estimates[eNB_id][ch_offset], (50*12))); @@ -816,4 +193,4 @@ void nr_ue_measurements(PHY_VARS_NR_UE *ue, _mm_empty(); _m_empty(); #endif -} +} \ No newline at end of file diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index 69077f0276..ef22b61260 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -39,13 +39,12 @@ #include "PHY/phy_extern_nr_ue.h" #include "PHY/CODING/coding_extern.h" #include "PHY/sse_intrin.h" +#include "PHY/NR_TRANSPORT/nr_dci.h" #include "assertions.h" #include "T.h" -//#define DEBUG_DCI_ENCODING 1 //#define DEBUG_DCI_DECODING 1 -//#define DEBUG_PHY //#define NR_LTE_PDCCH_DCI_SWITCH #define NR_PDCCH_DCI_RUN // activates new nr functions @@ -61,7 +60,6 @@ #endif #define NR_NBR_CORESET_ACT_BWP 3 // The number of CoreSets per BWP is limited to 3 (including initial CORESET: ControlResourceId 0) #define NR_NBR_SEARCHSPACE_ACT_BWP 10 // The number of SearSpaces per BWP is limited to 10 (including initial SEARCHSPACE: SearchSpaceId 0) -#define PDCCH_TEST_POLAR_TEMP_FIX #ifdef LOG_I @@ -152,7 +150,7 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr, for (int i=0; i<9; i++) { z[index_z + i] = llr[index_llr + i]; - LOG_DDD("[reg=%d,bundle_j=%d] z[%d]=(%d,%d) <-> \t[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d) \n", + LOG_D(PHY,"[reg=%d,bundle_j=%d] z[%d]=(%d,%d) <-> \t[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d) \n", reg,bundle_j,(index_z + i),*(int16_t *) &z[index_z + i],*(1 + (int16_t *) &z[index_z + i]), f_reg,f_bundle_j,(index_llr + i),*(int16_t *) &llr[index_llr + i], *(1 + (int16_t *) &llr[index_llr + i])); } @@ -305,9 +303,8 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, int32_t **rxdataF_ext, int32_t **dl_ch_estimates_ext, uint8_t symbol, - uint32_t high_speed_flag, NR_DL_FRAME_PARMS *frame_parms, - uint64_t coreset_freq_dom, + uint8_t *coreset_freq_dom, uint32_t coreset_nbr_rb, uint32_t n_BWP_start) { /* @@ -328,27 +325,18 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, // after removing the 3 DMRS RE, the RB contains 9 RE with PDCCH #define NBR_RE_PER_RB_WITHOUT_DMRS 9 uint16_t c_rb, nb_rb = 0; - // this variable will be incremented by 1 each time a bit set to '0' is found in coreset_freq_dom bitmap - uint16_t offset_discontiguous=0; //uint8_t rb_count_bit; - uint8_t i, j, aarx, bitcnt_coreset_freq_dom=0; + uint8_t i, j, aarx; int32_t *dl_ch0, *dl_ch0_ext, *rxF, *rxF_ext; - c_rb = n_BWP_start; // c_rb is the common resource block: RB within the BWP #ifdef DEBUG_DCI_DECODING uint8_t symbol_mod = (symbol >= (7 - frame_parms->Ncp)) ? symbol - (7 - frame_parms->Ncp) : symbol; LOG_I(PHY, "extract_rbs_single: symbol_mod %d\n",symbol_mod); #endif for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) { - if (high_speed_flag == 1) { - dl_ch0 = &dl_ch_estimates[aarx][(symbol * (frame_parms->ofdm_symbol_size))]; - LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][ (symbol * (frame_parms->ofdm_symbol_size (%d))) = (%d)]\n", - aarx,frame_parms->ofdm_symbol_size,(symbol * (frame_parms->ofdm_symbol_size))); - } else { - dl_ch0 = &dl_ch_estimates[aarx][0]; - LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][0]\n",aarx); - } + dl_ch0 = &dl_ch_estimates[aarx][0]; + LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][0]\n",aarx); dl_ch0_ext = &dl_ch_estimates_ext[aarx][symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)]; LOG_DDD("dl_ch0_ext = &dl_ch_estimates_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n", @@ -356,10 +344,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, rxF_ext = &rxdataF_ext[aarx][symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)]; LOG_DDD("rxF_ext = &rxdataF_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n", aarx,symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)); - LOG_DDD("(for symbol=%d, aarx=%d), symbol_mod=%d, nushiftmod3=%d \n", - symbol,aarx, - (symbol >= (7 - frame_parms->Ncp)) ? symbol - (7 - frame_parms->Ncp) : symbol, - frame_parms->nushift % 3); + /* * The following for loop handles treatment of PDCCH contained in table rxdataF (in frequency domain) * In NR the PDCCH IQ symbols are contained within RBs in the CORESET defined by higher layers which is located within the BWP @@ -377,25 +362,15 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, * then the IQ symbol is going to be found at the position 0+c_rb-N_RB_DL/2 in rxdataF and * we have to point the pointer at (1+c_rb-N_RB_DL/2) in rxdataF */ - LOG_DDD("n_BWP_start=%u, coreset_nbr_rb=%u\n",n_BWP_start,coreset_nbr_rb); - for (c_rb = n_BWP_start; c_rb < (n_BWP_start + coreset_nbr_rb + (BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN * offset_discontiguous)); c_rb++) { - //c_rb_tmp = 0; - if (((c_rb - n_BWP_start) % BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN)==0) { - bitcnt_coreset_freq_dom ++; + LOG_DDD("n_BWP_start=%d, coreset_nbr_rb=%d\n",n_BWP_start,coreset_nbr_rb); + int c_rb_by6; + c_rb = n_BWP_start; + for (int rb=0;rb>3] & (1<<(c_rb_by6&7))) == 0) c_rb+=6; - while ((((coreset_freq_dom & 0x1FFFFFFFFFFF) >> (CORESET_FREQ_DOMAIN_BITMAP_SIZE - (n_BWP_start/BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN) - bitcnt_coreset_freq_dom)) & 0x1)== 0) { // 46 -> 45 is number of bits in coreset_freq_dom - // next 6 RB are not part of the CORESET within the BWP as bit in coreset_freq_dom is set to 0 - bitcnt_coreset_freq_dom ++; - //c_rb_tmp = c_rb_tmp + 6; - c_rb = c_rb + BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN; - offset_discontiguous ++; - LOG_DDD("we entered here as coreset_freq_dom=%lx (bit %d) is 0, coreset_freq_domain is discontiguous\n",coreset_freq_dom, - (46 - bitcnt_coreset_freq_dom)); - } - } - - //c_rb = c_rb + c_rb_tmp; LOG_DDD("c_rb=%d\n",c_rb); rxF=NULL; @@ -423,45 +398,30 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { //if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): odd case rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))]; - LOG_DDD("in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", +#ifdef NR_PDCCH_DCI_DEBUG + LOG_D(PHY,"in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))); +#endif } if ((c_rb > (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { // number of RBs is odd and c_rb is higher than half system bandwidth + 1 // if these conditions are true the pointer has to be situated at the 1st part of the rxdataF just after the first IQ symbols of the RB containing DC rxF = &rxdataF[aarx][(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol - LOG_DDD("in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - frame_parms->N_RB_DL) - 5 + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", +#ifdef NR_PDCCH_DCI_DEBUG + LOG_D(PHY,"in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - frame_parms->N_RB_DL) - 5 + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", c_rb,aarx,(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size)))); +#endif } if ((c_rb == (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { // treatment of RB containing the DC // if odd number RBs in system bandwidth and first RB to be treated is higher than middle system bandwidth (around DC) // we have to treat the RB in two parts: first part from i=0 to 5, the data is at the end of rxdataF (pointing at the end of the table) rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))]; - LOG_DDD("in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", +#ifdef NR_PDCCH_DCI_DEBUG + LOG_D(PHY,"in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))); - /*if (symbol_mod > 300) { // this if is going to be removed as DM-RS signals are present in all symbols of PDCCH - for (i = 0; i < 6; i++) { - dl_ch0_ext[i] = dl_ch0[i]; - rxF_ext[i] = rxF[i]; - } - rxF = &rxdataF[aarx][(symbol * (frame_parms->ofdm_symbol_size))]; // we point at the 1st part of the rxdataF in symbol - #ifdef NR_PDCCH_DCI_DEBUG - LOG_DDD("in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(symbol * (frame_parms->ofdm_symbol_size)) = (%d)]\n", - c_rb,aarx,(symbol * (frame_parms->ofdm_symbol_size))); - #endif - for (; i < 12; i++) { - dl_ch0_ext[i] = dl_ch0[i]; - rxF_ext[i] = rxF[(1 + i - 6)]; - } - nb_rb++; - dl_ch0_ext += 12; - rxF_ext += 12; - dl_ch0 += 12; - rxF += 7; - c_rb++; - } else {*/ +#endif j = 0; for (i = 0; i < 6; i++) { //treating first part of the RB note that i=5 would correspond to DC. We treat it in NR @@ -474,9 +434,10 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, // then we point at the begining of the symbol part of rxdataF do process second part of RB rxF = &rxdataF[aarx][((symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol - LOG_DDD("in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(symbol * (frame_parms->ofdm_symbol_size)) = (%d)]\n", +#ifdef NR_PDCCH_DCI_DEBUG + LOG_D(PHY,"in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(symbol * (frame_parms->ofdm_symbol_size)) = (%d)]\n", c_rb,aarx,(symbol * (frame_parms->ofdm_symbol_size))); - +#endif for (; i < 12; i++) { if ((i != 9)) { dl_ch0_ext[j] = dl_ch0[i]; @@ -494,33 +455,27 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, //n_BWP_start++; // We have to increment this variable here to be consequent in the for loop afterwards //} } else { // treatment of any RB that does not contain the DC - /*if (symbol_mod > 300) { - memcpy(dl_ch0_ext, dl_ch0, 12 * sizeof(int32_t)); - for (i = 0; i < 12; i++) { - rxF_ext[i] = rxF[i]; - } - nb_rb++; - dl_ch0_ext += 12; - rxF_ext += 12; - dl_ch0 += 12; - //rxF += 12; - } else {*/ j = 0; for (i = 0; i < 12; i++) { if ((i != 1) && (i != 5) && (i != 9)) { rxF_ext[j] = rxF[i]; - LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n", +#ifdef NR_PDCCH_DCI_DEBUG + LOG_D(PHY,"RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n", c_rb, i, j, *(short *) &rxF_ext[j],*(1 + (short *) &rxF_ext[j]), i, *(short *) &rxF[i], *(1 + (short *) &rxF[i])); +#endif dl_ch0_ext[j] = dl_ch0[i]; + //LOG_DDD("ch %d => dl_ch0(%d,%d)\n", i, *(short *) &dl_ch0[i], *(1 + (short*) &dl_ch0[i])); //printf("\t-> dl_ch0[%d] => dl_ch0_ext[%d](%d,%d)\n", i,j, *(short *) &dl_ch0[i], *(1 + (short*) &dl_ch0[i])); j++; } else { - LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n", +#ifdef NR_PDCCH_DCI_DEBUG + LOG_D(PHY,"RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n", c_rb, i, j, *(short *) &rxF_ext[j], *(1 + (short *) &rxF_ext[j]), i, *(short *) &rxF[i], *(1 + (short *) &rxF[i])); +#endif } } @@ -704,204 +659,119 @@ void pdcch_siso(NR_DL_FRAME_PARMS *frame_parms, } #endif - - - - #ifdef NR_PDCCH_DCI_RUN int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, - uint32_t frame, - uint8_t nr_tti_rx, - uint8_t eNB_id, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag, - uint8_t is_secondary_ue, - int nb_coreset_active, - uint16_t symbol_mon, - NR_SEARCHSPACE_TYPE_t searchSpaceType) { + uint32_t frame, + uint32_t slot) { + NR_UE_COMMON *common_vars = &ue->common_vars; NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms; - NR_UE_PDCCH **pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]]; - NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]; - int do_common; - - if (searchSpaceType == common) do_common=1; - - if (searchSpaceType == ue_specific) do_common=0; + NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[slot]][0]; + fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; uint8_t log2_maxh, aarx; int32_t avgs; int32_t avgP[4]; - // number of RB (1 symbol) or REG (12 RE) in one CORESET: higher-layer parameter CORESET-freq-dom - // (bit map 45 bits: each bit indicates 6 RB in CORESET -> 1 bit MSB indicates PRB 0..6 are part of CORESET) - uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources; - // number of symbols in CORESET: higher-layer parameter CORESET-time-dur {1,2,3} - int coreset_time_dur = pdcch_vars2->coreset[nb_coreset_active].duration; - // depends on higher-layer parameter CORESET-shift-index {0,1,...,274} - int n_shift = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex; - // higher-layer parameter CORESET-REG-bundle-size (for non-interleaved L = 6 / for interleaved L {2,6}) - NR_UE_CORESET_REG_bundlesize_t reg_bundle_size_L = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize; - // higher-layer parameter CORESET-interleaver-size {2,3,6} - NR_UE_CORESET_interleaversize_t coreset_interleaver_size_R= pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize; - //NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity; - //int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH; - //int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI; - uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID; - // The UE can be assigned 4 different BWP but only one active at a time. - // For each BWP the number of CORESETs is limited to 3 (including initial CORESET Id=0 -> ControlResourceSetId (0..maxNrofControlReourceSets-1) (0..12-1) - //uint32_t n_BWP_start = 0; - //uint32_t n_rb_offset = 0; - uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset/*+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)*/; - // start time position for CORESET - // parameter symbol_mon is a 14 bits bitmap indicating monitoring symbols within a slot - uint8_t start_symbol = 0; + for (int i=0;inb_search_space;i++) { - // at the moment we are considering that the PDCCH is always starting at symbol 0 of current slot - // the following code to initialize start_symbol must be activated once we implement PDCCH demapping on symbol not equal to 0 (considering symbol_mon) - for (int i=0; i < 14; i++) { - if (((symbol_mon >> (i+1))&0x1) != 0) { - start_symbol = i; - i=14; - } - } + rel15 = &pdcch_vars->pdcch_config[i]; + int n_rb,rb_offset; + get_coreset_rballoc(rel15->coreset.frequency_domain_resource,&n_rb,&rb_offset); + for (int s=rel15->coreset.StartSymbolIndex; s<(rel15->coreset.StartSymbolIndex+rel15->coreset.duration); s++) { + LOG_D(PHY,"in nr_pdcch_extract_rbs_single(rxdataF -> rxdataF_ext || dl_ch_estimates -> dl_ch_estimates_ext)\n"); - LOG_DD("symbol_mon=(%u) and start_symbol=(%u)\n",symbol_mon,start_symbol); - LOG_DD("coreset_freq_dom=(%lu) n_rb_offset=(%u) coreset_time_dur=(%d) n_shift=(%d) reg_bundle_size_L=(%d) coreset_interleaver_size_R=(%d) scrambling_ID=(%d) \n", - coreset_freq_dom,n_rb_offset,coreset_time_dur,n_shift,reg_bundle_size_L,coreset_interleaver_size_R,pdcch_DMRS_scrambling_id); - // - // according to 38.213 v15.1.0: a PDCCH monitoring pattern within a slot, - // indicating first symbol(s) of the control resource set within a slot - // for PDCCH monitoring, by higher layer parameter monitoringSymbolsWithinSlot - // - // at the moment we do not implement this and start_symbol is always 0 - // note that the bitmap symbol_mon may indicate several monitoring times within a same slot (symbols 0..13) - // this may lead to a modification in ue scheduler - // indicates the number of active CORESETs for the current BWP to decode PDCCH: max is 3 (this variable is not useful here, to be removed) - //uint8_t coreset_nbr_act; - // indicates the number of REG contained in the PDCCH (number of RBs * number of symbols, in CORESET) - uint32_t coreset_nbr_rb = 0; - // for (int j=0; j < coreset_nbr_act; j++) { - // for each active CORESET (max number of active CORESETs in a BWP is 3), - // we calculate the number of RB for each CORESET bitmap - LOG_DD("coreset_freq_dom=(%lu)\n",coreset_freq_dom); - int i; //for each bit in the coreset_freq_dom bitmap + nr_pdcch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[slot]].rxdataF, + pdcch_vars->dl_ch_estimates, + pdcch_vars->rxdataF_ext, + pdcch_vars->dl_ch_estimates_ext, + s, + frame_parms, + rel15->coreset.frequency_domain_resource, + n_rb, + rel15->BWPStart); - for (i = 0; i < 45; i++) { - // this loop counts each bit of the bit map coreset_freq_dom, and increments nbr_RB_coreset for each bit set to '1' - if (((coreset_freq_dom & 0x1FFFFFFFFFFF) >> i) & 0x1) coreset_nbr_rb++; - } + LOG_D(PHY,"we enter nr_pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",*avgP); + LOG_D(PHY,"in nr_pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n"); + // compute channel level based on ofdm symbol 0 + nr_pdcch_channel_level(pdcch_vars->dl_ch_estimates_ext, + frame_parms, + avgP, + n_rb); + avgs = 0; - coreset_nbr_rb = 6 * coreset_nbr_rb; // coreset_nbr_rb has to be multiplied by 6 to indicate the number of PRB or REG(=12 RE) within the CORESET - LOG_DD("coreset_freq_dom=(%lu,%lx), coreset_nbr_rb=%u\n", coreset_freq_dom,coreset_freq_dom,coreset_nbr_rb); - LOG_DD("coreset_nbr_rb=%u, coreset_nbr_reg=%u, coreset_C=(%u/(%d*%d))=%u\n", - coreset_nbr_rb, - coreset_time_dur * coreset_nbr_rb, - coreset_time_dur * coreset_nbr_rb, - reg_bundle_size_L,coreset_interleaver_size_R, - (uint32_t)((coreset_time_dur * coreset_nbr_rb) / (reg_bundle_size_L * coreset_interleaver_size_R)) ); + for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) + avgs = cmax(avgs, avgP[aarx]); - for (int s = start_symbol; s < (start_symbol + coreset_time_dur); s++) { - LOG_DD("we enter nr_pdcch_extract_rbs_single(is_secondary_ue=%d) to remove DM-RS PDCCH\n", - is_secondary_ue); - LOG_DD("in nr_pdcch_extract_rbs_single(rxdataF -> rxdataF_ext || dl_ch_estimates -> dl_ch_estimates_ext)\n"); - nr_pdcch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF, - pdcch_vars[eNB_id]->dl_ch_estimates, - pdcch_vars[eNB_id]->rxdataF_ext, - pdcch_vars[eNB_id]->dl_ch_estimates_ext, - s, - high_speed_flag, - frame_parms, - coreset_freq_dom, - coreset_nbr_rb, - n_rb_offset); - LOG_DD("we enter nr_pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",*avgP); - LOG_DD("in nr_pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n"); - // compute channel level based on ofdm symbol 0 - nr_pdcch_channel_level(pdcch_vars[eNB_id]->dl_ch_estimates_ext, - frame_parms, - avgP, - coreset_nbr_rb); - avgs = 0; - - for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) - avgs = cmax(avgs, avgP[aarx]); - - log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx; + log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx; #ifdef UE_DEBUG_TRACE - LOG_D(PHY,"nr_tti_rx %d: pdcch log2_maxh = %d (%d,%d)\n",nr_tti_rx,log2_maxh,avgP[0],avgs); + LOG_D(PHY,"slot %d: pdcch log2_maxh = %d (%d,%d)\n",slot,log2_maxh,avgP[0],avgs); #endif #if T_TRACER - T(T_UE_PHY_PDCCH_ENERGY, T_INT(eNB_id), T_INT(0), T_INT(frame%1024), T_INT(nr_tti_rx), - T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3])); + T(T_UE_PHY_PDCCH_ENERGY, T_INT(0), T_INT(0), T_INT(frame%1024), T_INT(slot), + T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3])); #endif - LOG_DD("we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n",log2_maxh); - LOG_DD("in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n"); - // compute LLRs for ofdm symbol 0 only - nr_pdcch_channel_compensation(pdcch_vars[eNB_id]->rxdataF_ext, - pdcch_vars[eNB_id]->dl_ch_estimates_ext, - pdcch_vars[eNB_id]->rxdataF_comp, - NULL, - frame_parms, - s, - log2_maxh, - coreset_nbr_rb); // log2_maxh+I0_shift -#ifdef DEBUG_PHY + LOG_D(PHY,"we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n",log2_maxh); + LOG_D(PHY,"in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n"); + // compute LLRs for ofdm symbol 0 only + nr_pdcch_channel_compensation(pdcch_vars->rxdataF_ext, + pdcch_vars->dl_ch_estimates_ext, + pdcch_vars->rxdataF_comp, + NULL, + frame_parms, + s, + log2_maxh, + n_rb); // log2_maxh+I0_shift + if (frame_parms->nb_antennas_rx > 1) { + LOG_D(PHY,"we enter nr_pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n", frame_parms->nb_antennas_rx); + nr_pdcch_detection_mrc(frame_parms, pdcch_vars->rxdataF_comp,s); + } - if (nr_tti_rx==5) - write_output("rxF_comp_d.m","rxF_c_d",&pdcch_vars[eNB_id]->rxdataF_comp[0][s*frame_parms->N_RB_DL*12],frame_parms->N_RB_DL*12,1,1); - -#endif - - if (frame_parms->nb_antennas_rx > 1) { - LOG_DD("we enter nr_pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n", - frame_parms->nb_antennas_rx); - nr_pdcch_detection_mrc(frame_parms, pdcch_vars[eNB_id]->rxdataF_comp,s); - } - - LOG_DD("we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n",s); - LOG_DD("in nr_pdcch_llr(rxdataF_comp -> llr)\n"); - nr_pdcch_llr(frame_parms, - pdcch_vars[eNB_id]->rxdataF_comp, - pdcch_vars[eNB_id]->llr, - s, - coreset_nbr_rb); + LOG_D(PHY,"we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n",s); + LOG_D(PHY,"in nr_pdcch_llr(rxdataF_comp -> llr)\n"); + nr_pdcch_llr(frame_parms, + pdcch_vars->rxdataF_comp, + pdcch_vars->llr, + s, + n_rb); #if T_TRACER - /* - T(T_UE_PHY_PDCCH_IQ, T_INT(frame_parms->N_RB_DL), T_INT(frame_parms->N_RB_DL), - T_INT(n_pdcch_symbols), - T_BUFFER(pdcch_vars[eNB_id]->rxdataF_comp, frame_parms->N_RB_DL*12*n_pdcch_symbols* 4)); - */ + + // T(T_UE_PHY_PDCCH_IQ, T_INT(frame_parms->N_RB_DL), T_INT(frame_parms->N_RB_DL), + // T_INT(n_pdcch_symbols), + // T_BUFFER(pdcch_vars[eNB_id]->rxdataF_comp, frame_parms->N_RB_DL*12*n_pdcch_symbols* 4)); + #endif #ifdef DEBUG_DCI_DECODING - printf("demapping: nr_tti_rx %d, mi %d, tdd_config %d\n",nr_tti_rx,get_mi(frame_parms,nr_tti_rx),frame_parms->tdd_config); + printf("demapping: slot %d, mi %d\n",slot,get_mi(frame_parms,slot)); #endif - } + } - LOG_DD("we enter nr_pdcch_demapping_deinterleaving()\n"); - nr_pdcch_demapping_deinterleaving((uint32_t *) pdcch_vars[eNB_id]->llr, - (uint32_t *) pdcch_vars[eNB_id]->e_rx, - frame_parms, - coreset_time_dur, - coreset_nbr_rb, - reg_bundle_size_L, - coreset_interleaver_size_R, - n_shift); - nr_pdcch_unscrambling(pdcch_vars[eNB_id]->crnti, - frame_parms, - nr_tti_rx, - pdcch_vars[eNB_id]->e_rx, - coreset_time_dur*coreset_nbr_rb*9*2, - // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72, - pdcch_DMRS_scrambling_id, - do_common); - LOG_DD("we end nr_pdcch_unscrambling()\n"); - LOG_DD("Ending nr_rx_pdcch() function\n"); + LOG_D(PHY,"we enter nr_pdcch_demapping_deinterleaving()\n"); + nr_pdcch_demapping_deinterleaving((uint32_t *) pdcch_vars->llr, + (uint32_t *) pdcch_vars->e_rx, + frame_parms, + rel15->coreset.duration, + n_rb, + rel15->coreset.RegBundleSize, + rel15->coreset.InterleaverSize, + rel15->coreset.ShiftIndex); + /* + nr_pdcch_unscrambling(rel15->rnti, + frame_parms, + slot, + pdcch_vars->e_rx, + rel15->coreset.duration*n_rb*9*2, + // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72, + rel15->coreset.pdcch_dmrs_scrambling_id); + */ + LOG_D(PHY,"we end nr_pdcch_unscrambling()\n"); + LOG_D(PHY,"Ending nr_rx_pdcch() function\n"); + + } return (0); } + #endif - - void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, uint8_t *e, @@ -929,64 +799,29 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms, #ifdef NR_PDCCH_DCI_RUN -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, - int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common) { +void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, + int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id) { int i; uint8_t reset; uint32_t x1, x2, s = 0; uint16_t n_id; //{0,1,...,65535} uint32_t n_rnti; reset = 1; - // x1 is set in first call to lte_gold_generic //do_common=1; - if (do_common) { - n_id = frame_parms->Nid_cell; - n_rnti = 0; - } else { n_id = pdcch_DMRS_scrambling_id; n_rnti = (uint32_t)crnti; - } - //x2 = ((n_rnti * (1 << 16)) + n_id)%(1 << 31); - //uint32_t puissance_2_16 = ((1<<16)*n_rnti)+n_id; - //uint32_t puissance_2_31= (1<<30)*2; - //uint32_t calc_x2=puissance_2_16%puissance_2_31; x2 = (((1<<16)*n_rnti)+n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3 - // x2 = (nr_tti_rx << 9) + frame_parms->Nid_cell; //this is c_init in 36.211 Sec 6.8.2 - //LOG_DDD(" (c_init=%d, n_id=%d, n_rnti=%d, length=%d)\n",x2,n_id,n_rnti,length); for (i = 0; i < length; i++) { if ((i & 0x1f) == 0) { s = lte_gold_generic(&x1, &x2, reset); - //LOG_DDD("lte_gold[%d]=%x\n",i,s); reset = 0; } - /* - #ifdef NR_PDCCH_DCI_DEBUG - if (i%2 == 0) LOG_DDD(" unscrambling %d : scrambled_z=%d, => ", - i,*(char*) &z[(int)floor(i/2)]); - if (i%2 == 1) LOG_DDD(" unscrambling %d : scrambled_z=%d, => ", - i,*(1 + (char*) &z[(int)floor(i/2)])); - #endif - if (((s >> (i % 32)) & 1) == 1){ - if (i%2 == 0) *(char*) &z[(int)floor(i/2)] = -(*(char*) &z[(int)floor(i/2)]); - if (i%2 == 1) *(1 + (char*) &z[(int)floor(i/2)]) = -(*(1 + (char*) &z[(int)floor(i/2)])); - } - //llr[i] = -llr[i]; - //llr[i] = (-1)*llr[i]; - #ifdef NR_PDCCH_DCI_DEBUG - if (i%2 == 0) printf("unscrambled_z=%d\n",*(char*) &z[(int)floor(i/2)]); - if (i%2 == 1) printf("unscrambled_z=%d\n",*(1 + (char*) &z[(int)floor(i/2)])); - #endif - */ - LOG_DDD(" unscrambling %d : scrambled_z=%d, => ", - i,z[i]); - - if (((s >> (i % 32)) & 1) == 1) z[i] = -z[i]; - - LOG_DDD("unscrambled_z=%d\n",z[i]); + if (((s >> (i % 32)) & 1) == 1) z2[i] = -z[i]; + else z2[i]=z[i]; } } @@ -994,6 +829,56 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8 #ifdef NR_PDCCH_DCI_RUN +uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, + int frame, + int slot, + fapi_nr_dci_indication_t *dci_ind) { + + NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[slot]][0]; + fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; + for (int i=0;inb_search_space;i++) { + + rel15 = &pdcch_vars->pdcch_config[i]; + int dci_length = rel15->dci_length; + int16_t tmp_e[16*108]; + + for (int j=0;jnumber_of_candidates;j++) { + LOG_D(PHY,"Trying DCI candidate %d, CCE %d (%d), L %d\n",j,rel15->CCE[j],rel15->CCE[j]*9*6*2,rel15->L[j]); + int CCEind = rel15->CCE[j]; + int L = rel15->L[j]; + uint64_t dci_estimation[2]= {0}; + const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList); + + nr_pdcch_unscrambling(rel15->rnti, + &ue->frame_parms, + slot, + &pdcch_vars->e_rx[CCEind*108], + tmp_e, + L*108, + // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72, + rel15->coreset.pdcch_dmrs_scrambling_id); + + uint16_t crc = polar_decoder_int16(tmp_e, + dci_estimation, + 1, + currentPtrDCI); + LOG_D(PHY,"Decoded crc %x\n",crc); + if (crc == rel15->rnti) { + dci_ind->SFN = frame; + dci_ind->slot = slot; + dci_ind->dci_list[dci_ind->number_of_dcis].rnti = rel15->rnti; + dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind; + dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format; + dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length; + memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8); + dci_ind->number_of_dcis++; + } + } + } + return(dci_ind->number_of_dcis); +} + +/* void nr_dci_decoding_procedure0(int s, int p, int coreset_time_dur, @@ -1056,24 +941,24 @@ void nr_dci_decoding_procedure0(int s, // (1 bit set to '1' corresponds to 6 RB and 1 CCE = 6 RB) LOG_DDD("nCCE[%d]=%d\n",p,nCCE[p]); - /* if (nCCE > get_nCCE(3, frame_parms, 1)) { - LOG_D(PHY, - "skip DCI decoding: nCCE=%d > get_nCCE(3,frame_parms,1)=%d\n", - nCCE, get_nCCE(3, frame_parms, 1)); - return; - } + // if (nCCE > get_nCCE(3, frame_parms, 1)) { + //LOG_D(PHY, + //"skip DCI decoding: nCCE=%d > get_nCCE(3,frame_parms,1)=%d\n", + //nCCE, get_nCCE(3, frame_parms, 1)); + //return; + // } - if (nCCE < L2) { - LOG_D(PHY, "skip DCI decoding: nCCE=%d < L2=%d\n", nCCE, L2); - return; - } +// if (nCCE < L2) { +// LOG_D(PHY, "skip DCI decoding: nCCE=%d < L2=%d\n", nCCE, L2); +// return; +// } + +// if (mode == NO_DCI) { +// LOG_D(PHY, "skip DCI decoding: expect no DCIs at nr_tti_rx %d\n", +// nr_tti_rx); +// return; +// } - if (mode == NO_DCI) { - LOG_D(PHY, "skip DCI decoding: expect no DCIs at nr_tti_rx %d\n", - nr_tti_rx); - return; - } - */ if (do_common == 1) { Yk = 0; @@ -1146,9 +1031,9 @@ void nr_dci_decoding_procedure0(int s, } LOG_DDD("L2(%d) | nCCE[%d](%d) | Yk(%u) | nb_candidates(%u)\n", L2, p, nCCE[p], Yk, nb_candidates); - /* for (CCEind=0; - CCEind nCCE[p]) // nb_candidates = nCCE[p] / L2; // In the next code line there is maybe a bug. The spec is not comparing Table 10.1-2 with nb_candidates, but with total number of candidates for all s and all p @@ -1225,35 +1110,35 @@ void nr_dci_decoding_procedure0(int s, // for (int m=0; m < (nCCE[p]*6*9*2); m++) LOG_DDD("(polar decoding)-> polar intput (with coreset_time_dur=%d, coreset_nbr_rb=%d, p=%d, CCEind=%u): \n", coreset_time_dur,coreset_nbr_rb,p,CCEind); - /* - int reg_p=0,reg_e=0; - for (int m=0; m < (L2*6); m++){ - reg_p = (((int)floor(m/coreset_time_dur))+((m%coreset_time_dur)*(L2*6/coreset_time_dur)))*9*2; - reg_e = m*9*2; - for (int i=0; i<9*2; i++){ + + //int reg_p=0,reg_e=0; + //for (int m=0; m < (L2*6); m++){ + //reg_p = (((int)floor(m/coreset_time_dur))+((m%coreset_time_dur)*(L2*6/coreset_time_dur)))*9*2; + //reg_e = m*9*2; + //for (int i=0; i<9*2; i++){ //polar_input[reg_p+i] = (pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]>0) ? (1.0):(-1.0); - polar_input[reg_e+i] = (pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]>0) ? (1/sqrt(2)):((-1)/sqrt(2)); + //polar_input[reg_e+i] = (pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]>0) ? (1/sqrt(2)):((-1)/sqrt(2)); //printf("\t m=%d \tpolar_input[%d]=%lf <-> e_rx[%d]=%d\n",m,reg_e+i,polar_input[reg_e+i], // ((CCEind*9*6*2) + reg_e + i),pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]); //printf("\t m=%d \tpolar_input[%d]=%lf <-> e_rx[%d]=%d\n",m,reg_p+i,polar_input[reg_p+i], // ((CCEind*9*6*2) + reg_e + i),pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]); - } - } + //} + //} - #ifdef NR_PDCCH_DCI_DEBUG - printf("\n"); - int j=0; - uint32_t polar_hex[27] = {0}; - for (int i=0; ie_rx[CCEind*9*6*2], dci_estimation, 1, @@ -1412,42 +1297,42 @@ void nr_dci_decoding_procedure0(int s, // store first nCCE of group for PUCCH transmission of ACK/NAK pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; - /* if (crc == si_rnti) { - dci_alloc[*dci_cnt].format = format_si; - *dci_cnt = *dci_cnt + 1; - } else if (crc == p_rnti) { - dci_alloc[*dci_cnt].format = format_p; - *dci_cnt = *dci_cnt + 1; - } else if (crc == ra_rnti) { - dci_alloc[*dci_cnt].format = format_ra; - // store first nCCE of group for PUCCH transmission of ACK/NAK - pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; - *dci_cnt = *dci_cnt + 1; - } else if (crc == pdcch_vars[eNB_id]->crnti) { + // if (crc == si_rnti) { + // dci_alloc[*dci_cnt].format = format_si; + // *dci_cnt = *dci_cnt + 1; + // } else if (crc == p_rnti) { + // dci_alloc[*dci_cnt].format = format_p; + // *dci_cnt = *dci_cnt + 1; + // } else if (crc == ra_rnti) { + // dci_alloc[*dci_cnt].format = format_ra; + // // store first nCCE of group for PUCCH transmission of ACK/NAK + // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; + // *dci_cnt = *dci_cnt + 1; + // } else if (crc == pdcch_vars[eNB_id]->crnti) { - if ((mode & UL_DCI) && (format_c == format0) - && ((dci_decoded_output[current_thread_id][0] & 0x80) - == 0)) { // check if pdu is format 0 or 1A - if (*format0_found == 0) { - dci_alloc[*dci_cnt].format = format0; - *format0_found = 1; - *dci_cnt = *dci_cnt + 1; - pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; - } - } else if (format_c == format0) { // this is a format 1A DCI - dci_alloc[*dci_cnt].format = format1A; - *dci_cnt = *dci_cnt + 1; - pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; - } else { - // store first nCCE of group for PUCCH transmission of ACK/NAK - if (*format_c_found == 0) { - dci_alloc[*dci_cnt].format = format_c; - *dci_cnt = *dci_cnt + 1; - *format_c_found = 1; - pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; - } - } - }*/ + // if ((mode & UL_DCI) && (format_c == format0) + // && ((dci_decoded_output[current_thread_id][0] & 0x80) + // == 0)) { // check if pdu is format 0 or 1A + // if (*format0_found == 0) { + // dci_alloc[*dci_cnt].format = format0; + // *format0_found = 1; + // *dci_cnt = *dci_cnt + 1; + // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; + // } + // } else if (format_c == format0) { // this is a format 1A DCI + // dci_alloc[*dci_cnt].format = format1A; + // *dci_cnt = *dci_cnt + 1; + // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; + // } else { + // // store first nCCE of group for PUCCH transmission of ACK/NAK + // if (*format_c_found == 0) { + // dci_alloc[*dci_cnt].format = format_c; + // *dci_cnt = *dci_cnt + 1; + // *format_c_found = 1; + // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind; + // } + // } + // } //LOG_I(PHY,"DCI decoding CRNTI [format: %d, nCCE[nr_tti_rx: %d]: %d ], AggregationLevel %d \n",format_c, nr_tti_rx, pdcch_vars[eNB_id]->nCCE[nr_tti_rx],L2); // memcpy(&dci_alloc[*dci_cnt].dci_pdu[0],dci_decoded_output,sizeof_bytes); switch (1 << L) { @@ -1484,1045 +1369,30 @@ void nr_dci_decoding_procedure0(int s, printf("\n"); } - /* - if ( agregationLevel != 0xFF && - (format_c == format0 && m==0 && si_rnti != SI_RNTI)) - { - //Only valid for OAI : Save some processing time when looking for DCI format0. From the log we see the DCI only on candidate 0. - return; - } - */ + + // if ( agregationLevel != 0xFF && + // (format_c == format0 && m==0 && si_rnti != SI_RNTI)) + // { + // //Only valid for OAI : Save some processing time when looking for DCI format0. From the log we see the DCI only on candidate 0. + // return; + // } + } // candidate loop LOG_DDD("end candidate loop\n"); } - -#endif - - - - - -/*void dci_decoding_procedure0(NR_UE_PDCCH **pdcch_vars, - int do_common, - dci_detect_mode_t mode, - uint8_t nr_tti_rx, - DCI_ALLOC_t *dci_alloc, - int16_t eNB_id, - uint8_t current_thread_id, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t mi, - uint16_t si_rnti, - uint16_t ra_rnti, - uint16_t p_rnti, - uint8_t L, - uint8_t format_si, - uint8_t format_p, - uint8_t format_ra, - uint8_t format_c, - uint8_t sizeof_bits, - uint8_t sizeof_bytes, - uint8_t *dci_cnt, - uint8_t *format0_found, - uint8_t *format_c_found, - uint32_t *CCEmap0, - uint32_t *CCEmap1, - uint32_t *CCEmap2) - { - - uint16_t crc,CCEind,nCCE; - uint32_t *CCEmap=NULL,CCEmap_mask=0; - int L2=(1<num_pdcch_symbols,frame_parms,mi); - - if (nCCE > get_nCCE(3,frame_parms,1)) { - LOG_D(PHY,"skip DCI decoding: nCCE=%d > get_nCCE(3,frame_parms,1)=%d\n", nCCE, get_nCCE(3,frame_parms,1)); - return; - } - - if (nCCEcrnti; - - for (i=0; i<=nr_tti_rx; i++) - Yk = (Yk*39827)%65537; - - Yk = Yk % (nCCE/L2); - - switch (L2) { - case 1: - case 2: - nb_candidates = 6; - break; - - case 4: - case 8: - nb_candidates = 2; - break; - - default: - DevParam(L2, do_common, eNB_id); - break; - } - } - - // for (CCEind=0; - // CCEind nCCE) - nb_candidates = nCCE/L2; - - for (m=0; mmacphy_exit("Illegal CCEind\n"); - return; // not reached - } - - switch (L2) { - case 1: - CCEmap_mask = (1<<(CCEind&0x1f)); - break; - - case 2: - CCEmap_mask = (3<<(CCEind&0x1f)); - break; - - case 4: - CCEmap_mask = (0xf<<(CCEind&0x1f)); - break; - - case 8: - CCEmap_mask = (0xff<<(CCEind&0x1f)); - break; - - default: - LOG_E( PHY, "Illegal L2 value %d\n", L2 ); - mac_xface->macphy_exit( "Illegal L2\n" ); - return; // not reached - } - - CCEmap_cand = (*CCEmap)&CCEmap_mask; - - // CCE is not allocated yet - - if (CCEmap_cand == 0) { - #ifdef DEBUG_DCI_DECODING - - if (do_common == 1) - LOG_I(PHY,"[DCI search nPdcch %d - common] Attempting candidate %d Aggregation Level %d DCI length %d at CCE %d/%d (CCEmap %x,CCEmap_cand %x)\n", - pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask); - else - LOG_I(PHY,"[DCI search nPdcch %d - ue spec] Attempting candidate %d Aggregation Level %d DCI length %d at CCE %d/%d (CCEmap %x,CCEmap_cand %x) format %d\n", - pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask,format_c); - - #endif - - dci_decoding(sizeof_bits, - L, - &pdcch_vars[eNB_id]->e_rx[CCEind*72], - &dci_decoded_output[current_thread_id][0]); - - // for (i=0;i<3+(sizeof_bits>>3);i++) - // printf("dci_decoded_output[%d] => %x\n",i,dci_decoded_output[i]); - - crc = (crc16(&dci_decoded_output[current_thread_id][0],sizeof_bits)>>16) ^ extract_crc(&dci_decoded_output[current_thread_id][0],sizeof_bits); - #ifdef DEBUG_DCI_DECODING - printf("crc =>%x\n",crc); - #endif - - if (((L>1) && ((crc == si_rnti)|| (crc == p_rnti)|| (crc == ra_rnti)))|| - (crc == pdcch_vars[eNB_id]->crnti)) { - dci_alloc[*dci_cnt].dci_length = sizeof_bits; - dci_alloc[*dci_cnt].rnti = crc; - dci_alloc[*dci_cnt].L = L; - dci_alloc[*dci_cnt].firstCCE = CCEind; - - //printf("DCI FOUND !!! crc =>%x, sizeof_bits %d, sizeof_bytes %d \n",crc, sizeof_bits, sizeof_bytes); - if (sizeof_bytes<=4) { - dci_alloc[*dci_cnt].dci_pdu[3] = dci_decoded_output[current_thread_id][0]; - dci_alloc[*dci_cnt].dci_pdu[2] = dci_decoded_output[current_thread_id][1]; - dci_alloc[*dci_cnt].dci_pdu[1] = dci_decoded_output[current_thread_id][2]; - dci_alloc[*dci_cnt].dci_pdu[0] = dci_decoded_output[current_thread_id][3]; - #ifdef DEBUG_DCI_DECODING - printf("DCI => %x,%x,%x,%x\n",dci_decoded_output[current_thread_id][0], - dci_decoded_output[current_thread_id][1], - dci_decoded_output[current_thread_id][2], - dci_decoded_output[current_thread_id][3]); - #endif - } else { - dci_alloc[*dci_cnt].dci_pdu[7] = dci_decoded_output[current_thread_id][0]; - dci_alloc[*dci_cnt].dci_pdu[6] = dci_decoded_output[current_thread_id][1]; - dci_alloc[*dci_cnt].dci_pdu[5] = dci_decoded_output[current_thread_id][2]; - dci_alloc[*dci_cnt].dci_pdu[4] = dci_decoded_output[current_thread_id][3]; - dci_alloc[*dci_cnt].dci_pdu[3] = dci_decoded_output[current_thread_id][4]; - dci_alloc[*dci_cnt].dci_pdu[2] = dci_decoded_output[current_thread_id][5]; - dci_alloc[*dci_cnt].dci_pdu[1] = dci_decoded_output[current_thread_id][6]; - dci_alloc[*dci_cnt].dci_pdu[0] = dci_decoded_output[current_thread_id][7]; - #ifdef DEBUG_DCI_DECODING - printf("DCI => %x,%x,%x,%x,%x,%x,%x,%x\n", - dci_decoded_output[current_thread_id][0],dci_decoded_output[current_thread_id][1],dci_decoded_output[current_thread_id][2],dci_decoded_output[current_thread_id][3], - dci_decoded_output[current_thread_id][4],dci_decoded_output[current_thread_id][5],dci_decoded_output[current_thread_id][6],dci_decoded_output[current_thread_id][7]); - #endif - } - - if (crc==si_rnti) { - dci_alloc[*dci_cnt].format = format_si; - *dci_cnt = *dci_cnt+1; - } else if (crc==p_rnti) { - dci_alloc[*dci_cnt].format = format_p; - *dci_cnt = *dci_cnt+1; - } else if (crc==ra_rnti) { - dci_alloc[*dci_cnt].format = format_ra; - // store first nCCE of group for PUCCH transmission of ACK/NAK - pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind; - *dci_cnt = *dci_cnt+1; - } else if (crc==pdcch_vars[eNB_id]->crnti) { - - if ((mode&UL_DCI)&&(format_c == format0)&&((dci_decoded_output[current_thread_id][0]&0x80)==0)) {// check if pdu is format 0 or 1A - if (*format0_found == 0) { - dci_alloc[*dci_cnt].format = format0; - *format0_found = 1; - *dci_cnt = *dci_cnt+1; - pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind; - } - } else if (format_c == format0) { // this is a format 1A DCI - dci_alloc[*dci_cnt].format = format1A; - *dci_cnt = *dci_cnt+1; - pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind; - } else { - // store first nCCE of group for PUCCH transmission of ACK/NAK - if (*format_c_found == 0) { - dci_alloc[*dci_cnt].format = format_c; - *dci_cnt = *dci_cnt+1; - *format_c_found = 1; - pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind; - } - } - } - - //LOG_I(PHY,"DCI decoding CRNTI [format: %d, nCCE[nr_tti_rx: %d]: %d ], AggregationLevel %d \n",format_c, nr_tti_rx, pdcch_vars[eNB_id]->nCCE[nr_tti_rx],L2); - // memcpy(&dci_alloc[*dci_cnt].dci_pdu[0],dci_decoded_output,sizeof_bytes); - - - - switch (1<pdcch_vars[ue->current_thread_id[nr_tti_rx]]; - NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms; - uint8_t mi = get_mi(&ue->frame_parms,nr_tti_rx); - uint16_t ra_rnti=99; - uint8_t format0_found=0,format_c_found=0; - uint8_t tmode = ue->transmission_mode[eNB_id]; - uint8_t frame_type = frame_parms->frame_type; - uint8_t format0_size_bits=0,format0_size_bytes=0; - uint8_t format1_size_bits=0,format1_size_bytes=0; - dci_detect_mode_t mode = dci_detect_mode_select(&ue->frame_parms,nr_tti_rx); - - switch (frame_parms->N_RB_DL) { - case 6: - if (frame_type == TDD) { - format0_size_bits = sizeof_DCI0_1_5MHz_TDD_1_6_t; - format0_size_bytes = sizeof(DCI0_1_5MHz_TDD_1_6_t); - format1_size_bits = sizeof_DCI1_1_5MHz_TDD_t; - format1_size_bytes = sizeof(DCI1_1_5MHz_TDD_t); - - } else { - format0_size_bits = sizeof_DCI0_1_5MHz_FDD_t; - format0_size_bytes = sizeof(DCI0_1_5MHz_FDD_t); - format1_size_bits = sizeof_DCI1_1_5MHz_FDD_t; - format1_size_bytes = sizeof(DCI1_1_5MHz_FDD_t); - } - - break; - - case 25: - default: - if (frame_type == TDD) { - format0_size_bits = sizeof_DCI0_5MHz_TDD_1_6_t; - format0_size_bytes = sizeof(DCI0_5MHz_TDD_1_6_t); - format1_size_bits = sizeof_DCI1_5MHz_TDD_t; - format1_size_bytes = sizeof(DCI1_5MHz_TDD_t); - } else { - format0_size_bits = sizeof_DCI0_5MHz_FDD_t; - format0_size_bytes = sizeof(DCI0_5MHz_FDD_t); - format1_size_bits = sizeof_DCI1_5MHz_FDD_t; - format1_size_bytes = sizeof(DCI1_5MHz_FDD_t); - } - - break; - - case 50: - if (frame_type == TDD) { - format0_size_bits = sizeof_DCI0_10MHz_TDD_1_6_t; - format0_size_bytes = sizeof(DCI0_10MHz_TDD_1_6_t); - format1_size_bits = sizeof_DCI1_10MHz_TDD_t; - format1_size_bytes = sizeof(DCI1_10MHz_TDD_t); - - } else { - format0_size_bits = sizeof_DCI0_10MHz_FDD_t; - format0_size_bytes = sizeof(DCI0_10MHz_FDD_t); - format1_size_bits = sizeof_DCI1_10MHz_FDD_t; - format1_size_bytes = sizeof(DCI1_10MHz_FDD_t); - } - - break; - - case 100: - if (frame_type == TDD) { - format0_size_bits = sizeof_DCI0_20MHz_TDD_1_6_t; - format0_size_bytes = sizeof(DCI0_20MHz_TDD_1_6_t); - format1_size_bits = sizeof_DCI1_20MHz_TDD_t; - format1_size_bytes = sizeof(DCI1_20MHz_TDD_t); - } else { - format0_size_bits = sizeof_DCI0_20MHz_FDD_t; - format0_size_bytes = sizeof(DCI0_20MHz_FDD_t); - format1_size_bits = sizeof_DCI1_20MHz_FDD_t; - format1_size_bytes = sizeof(DCI1_20MHz_FDD_t); - } - - break; - } - - if (ue->prach_resources[eNB_id]) - ra_rnti = ue->prach_resources[eNB_id]->ra_RNTI; - - // Now check UE_SPEC format0/1A ue_spec search spaces at aggregation 8 - dci_decoding_procedure0(pdcch_vars,0,mode, - nr_tti_rx, - dci_alloc, - eNB_id, - ue->current_thread_id[nr_tti_rx], - frame_parms, - mi, - ((ue->decode_SIB == 1) ? SI_RNTI : 0), - ra_rnti, - P_RNTI, - agregationLevel, - format1A, - format1A, - format1A, - format0, - format0_size_bits, - format0_size_bytes, - &dci_cnt, - &format0_found, - &format_c_found, - &CCEmap0, - &CCEmap1, - &CCEmap2); - - if ((CCEmap0==0xffff)|| - ((format0_found==1)&&(format_c_found==1))) - return(dci_cnt); - - if (DCIFormat == 1) - { - if ((tmode < 3) || (tmode == 7)) { - //printf("Crnti decoding frame param agregation %d DCI %d \n",agregationLevel,DCIFormat); - - // Now check UE_SPEC format 1 search spaces at aggregation 1 - - //printf("[DCI search] Format 1/1A aggregation 1\n"); - - old_dci_cnt=dci_cnt; - dci_decoding_procedure0(pdcch_vars,0,mode,nr_tti_rx, - dci_alloc, - eNB_id, - ue->current_thread_id[nr_tti_rx], - frame_parms, - mi, - ((ue->decode_SIB == 1) ? SI_RNTI : 0), - ra_rnti, - P_RNTI, - 0, - format1A, - format1A, - format1A, - format1, - format1_size_bits, - format1_size_bytes, - &dci_cnt, - &format0_found, - &format_c_found, - &CCEmap0, - &CCEmap1, - &CCEmap2); - - if ((CCEmap0==0xffff) || - (format_c_found==1)) - return(dci_cnt); - - if (dci_cnt>old_dci_cnt) - return(dci_cnt); - - //printf("Crnti 1 decoding frame param agregation %d DCI %d \n",agregationLevel,DCIFormat); - - } - else - { - AssertFatal(0,"Other Transmission mode not yet coded\n"); - } - } - else - { - AssertFatal(0,"DCI format %d not yet implemented \n",DCIFormat); - } - - return(dci_cnt); - - } */ - -#ifdef NR_PDCCH_DCI_RUN - -uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue, - uint16_t eNB_id, - uint8_t nr_tti_rx, - int p, - crc_scrambled_t crc_scrambled, - uint16_t n_RB_ULBWP, - uint16_t n_RB_DLBWP, - uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], - uint8_t format) { - LOG_DDD("crc_scrambled=%d, n_RB_ULBWP=%d, n_RB_DLBWP=%d\n",crc_scrambled,n_RB_ULBWP,n_RB_DLBWP); - /* - * function nr_dci_format_size calculates and returns the size in bits of a determined format - * it also returns an bi-dimensional array 'dci_fields_sizes' with x rows and y columns, where: - * x is the number of fields defined in TS 38.212 subclause 7.3.1 (Each field is mapped in the order in which it appears in the description in the specification) - * y is the number of formats - * e.g.: dci_fields_sizes[10][0] contains the size in bits of the field FREQ_DOM_RESOURCE_ASSIGNMENT_UL for format 0_0 - */ - // pdsch_config contains the PDSCH-Config IE is used to configure the UE specific PDSCH parameters (TS 38.331) - PDSCH_Config_t pdsch_config = ue->PDSCH_Config; - // pusch_config contains the PUSCH-Config IE is used to configure the UE specific PUSCH parameters (TS 38.331) - PUSCH_Config_t pusch_config = ue->pusch_config; - PUCCH_Config_t pucch_config_dedicated = ue->pucch_config_dedicated_nr[eNB_id]; - crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig = ue->crossCarrierSchedulingConfig; - dmrs_UplinkConfig_t dmrs_UplinkConfig = ue->dmrs_UplinkConfig; - dmrs_DownlinkConfig_t dmrs_DownlinkConfig = ue->dmrs_DownlinkConfig; - csi_MeasConfig_t csi_MeasConfig = ue->csi_MeasConfig; - PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig= ue->PUSCH_ServingCellConfig; - PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig= ue->PDSCH_ServingCellConfig; - NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]; - // 1 CARRIER_IN - // crossCarrierSchedulingConfig from higher layers, variable crossCarrierSchedulingConfig indicates if 'cross carrier scheduling' is enabled or not: - // if No cross carrier scheduling: number of bits for CARRIER_IND is 0 - // if Cross carrier scheduling: number of bits for CARRIER_IND is 3 - // The IE CrossCarrierSchedulingConfig is used to specify the configuration when the cross-carrier scheduling is used in a cell - uint8_t crossCarrierSchedulingConfig_ind = 0; - - if (crossCarrierSchedulingConfig.schedulingCellInfo.other.cif_InSchedulingCell !=0 ) crossCarrierSchedulingConfig_ind=1; - - // 2 SUL_IND_0_1, // 40 SRS_REQUEST, // 50 SUL_IND_0_0 - // UL/SUL indicator (TS 38.331, supplementary uplink is indicated in higher layer parameter ServCellAdd-SUL from IE ServingCellConfig and ServingCellConfigCommon): - // 0 bit for UEs not configured with SUL in the cell or UEs configured with SUL in the cell but only PUCCH carrier in the cell is configured for PUSCH transmission - // 1 bit for UEs configured with SUL in the cell as defined in Table 7.3.1.1.1-1 - // sul_ind indicates whether SUL is configured in cell or not - uint8_t sul_ind=ue->supplementaryUplink.supplementaryUplink; // this value will be 0 or 1 depending on higher layer parameter ServCellAdd-SUL. FIXME!!! - // 7 BANDWIDTH_PART_IND - // number of UL BWPs configured by higher layers - uint8_t n_UL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!! - n_UL_BWP_RRC = ((n_UL_BWP_RRC > 3)?n_UL_BWP_RRC:(n_UL_BWP_RRC+1)); - // number of DL BWPs configured by higher layers - uint8_t n_DL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!! - n_DL_BWP_RRC = ((n_DL_BWP_RRC > 3)?n_DL_BWP_RRC:(n_DL_BWP_RRC+1)); - // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL - // if format0_0, only resource allocation type 1 is allowed - // if format0_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 6.1.2.2.1 - // for PUSCH hopping with resource allocation type 1 - // n_UL_hopping = 1 if the higher layer parameter frequencyHoppingOffsetLists contains two offset values - // n_UL_hopping = 2 if the higher layer parameter frequencyHoppingOffsetLists contains four offset values - uint8_t n_UL_hopping=pusch_config.n_frequencyHoppingOffsetLists; - - if (n_UL_hopping == 2) { - n_UL_hopping = 1; - } else if (n_UL_hopping == 4) { - n_UL_hopping = 2; - } else { - n_UL_hopping = 0; - } - - ul_resourceAllocation_t ul_resource_allocation_type = pusch_config.ul_resourceAllocation; - uint8_t ul_res_alloc_type_0 = 0; - uint8_t ul_res_alloc_type_1 = 0; - - if (ul_resource_allocation_type == ul_resourceAllocationType0) ul_res_alloc_type_0 = 1; - - if (ul_resource_allocation_type == ul_resourceAllocationType1) ul_res_alloc_type_1 = 1; - - if (ul_resource_allocation_type == ul_dynamicSwitch) { - ul_res_alloc_type_0 = 1; - ul_res_alloc_type_1 = 1; - } - - uint8_t n_bits_freq_dom_res_assign_ul=0,n_ul_RGB_tmp; - - if (ul_res_alloc_type_0 == 1) { // implementation of Table 6.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1 - // config1: PUSCH-Config IE contains rbg-Size ENUMERATED {config1 config2} - ul_rgb_Size_t config = pusch_config.ul_rgbSize; - uint8_t nominal_RBG_P = (config==ul_rgb_config1?2:4); - - if (n_RB_ULBWP > 36) nominal_RBG_P = (config==ul_rgb_config1?4:8); - - if (n_RB_ULBWP > 72) nominal_RBG_P = (config==ul_rgb_config1?8:16); - - if (n_RB_ULBWP > 144) nominal_RBG_P = 16; - - n_bits_freq_dom_res_assign_ul = (uint8_t)ceil((n_RB_ULBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0??? - n_ul_RGB_tmp = n_bits_freq_dom_res_assign_ul; - } - - if (ul_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_ul = (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping; - - if ((ul_res_alloc_type_0 == 1) && (ul_res_alloc_type_1 == 1)) - n_bits_freq_dom_res_assign_ul = ((n_bits_freq_dom_res_assign_ul>n_ul_RGB_tmp)?(n_bits_freq_dom_res_assign_ul+1):(n_ul_RGB_tmp+1)); - - // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL - // if format1_0, only resource allocation type 1 is allowed - // if format1_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 5.1.2.2.1 - dl_resourceAllocation_t dl_resource_allocation_type = pdsch_config.dl_resourceAllocation; - uint8_t dl_res_alloc_type_0 = 0; - uint8_t dl_res_alloc_type_1 = 0; - - if (dl_resource_allocation_type == dl_resourceAllocationType0) dl_res_alloc_type_0 = 1; - - if (dl_resource_allocation_type == dl_resourceAllocationType1) dl_res_alloc_type_1 = 1; - - if (dl_resource_allocation_type == dl_dynamicSwitch) { - dl_res_alloc_type_0 = 1; - dl_res_alloc_type_1 = 1; - } - - uint8_t n_bits_freq_dom_res_assign_dl=0,n_dl_RGB_tmp; - - if (dl_res_alloc_type_0 == 1) { // implementation of Table 5.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1 - // config1: PDSCH-Config IE contains rbg-Size ENUMERATED {config1, config2} - dl_rgb_Size_t config = pdsch_config.dl_rgbSize; - uint8_t nominal_RBG_P = (config==dl_rgb_config1?2:4); - - if (n_RB_DLBWP > 36) nominal_RBG_P = (config==dl_rgb_config1?4:8); - - if (n_RB_DLBWP > 72) nominal_RBG_P = (config==dl_rgb_config1?8:16); - - if (n_RB_DLBWP > 144) nominal_RBG_P = 16; - - n_bits_freq_dom_res_assign_dl = (uint8_t)ceil((n_RB_DLBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0??? - n_dl_RGB_tmp = n_bits_freq_dom_res_assign_dl; - } - - if (dl_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_dl = (uint8_t)(ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2))); - - if ((dl_res_alloc_type_0 == 1) && (dl_res_alloc_type_1 == 1)) - n_bits_freq_dom_res_assign_dl = ((n_bits_freq_dom_res_assign_dl>n_dl_RGB_tmp)?(n_bits_freq_dom_res_assign_dl+1):(n_dl_RGB_tmp+1)); - - // 12 TIME_DOM_RESOURCE_ASSIGNMENT - uint8_t pusch_alloc_list = pusch_config.n_push_alloc_list; - uint8_t pdsch_alloc_list = pdsch_config.n_pdsh_alloc_list; - // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] - static_bundleSize_t static_prb_BundlingType = pdsch_config.prbBundleType.staticBundling; - bundleSizeSet1_t dynamic_prb_BundlingType1 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet1; - bundleSizeSet2_t dynamic_prb_BundlingType2 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet2; - uint8_t prb_BundlingType_size=0; - - if ((static_prb_BundlingType==st_n4)||(static_prb_BundlingType==st_wideband)) prb_BundlingType_size=0; - - if ((dynamic_prb_BundlingType1==dy_1_n4)||(dynamic_prb_BundlingType1==dy_1_wideband)||(dynamic_prb_BundlingType1==dy_1_n2_wideband)||(dynamic_prb_BundlingType1==dy_1_n4_wideband)|| - (dynamic_prb_BundlingType2==dy_2_n4)||(dynamic_prb_BundlingType2==dy_2_wideband)) prb_BundlingType_size=1; - - // 15 RATE_MATCHING_IND FIXME!!! - // according to TS 38.212: Rate matching indicator – 0, 1, or 2 bits according to higher layer parameter rateMatchPattern - uint8_t rateMatching_bits = pdsch_config.n_rateMatchPatterns; - // 16 ZP_CSI_RS_TRIGGER FIXME!!! - // 0, 1, or 2 bits as defined in Subclause 5.1.4.2 of [6, TS 38.214]. - // is the number of ZP CSI-RS resource sets in the higher layer parameter zp-CSI-RS-Resource - uint8_t n_zp_bits = pdsch_config.n_zp_CSI_RS_ResourceId; - // 17 FREQ_HOPPING_FLAG - // freqHopping is defined by higher layer parameter frequencyHopping from IE PUSCH-Config. Values are ENUMERATED{mode1, mode2} - frequencyHopping_t f_hopping = pusch_config.frequencyHopping; - uint8_t freqHopping = 0; - - if ((f_hopping==f_hop_mode1)||(f_hopping==f_hop_mode2)) freqHopping = 1; - - // 28 DAI - pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook = pdsch_config.pdsch_HARQ_ACK_Codebook; - uint8_t n_dai = 0; - uint8_t n_serving_cell_dl = 1; // this is hardcoded to 1 as we need to get this value from RRC higher layers parameters. FIXME!!! - - if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl == 1)) n_dai = 2; - - if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl > 1)) n_dai = 4; - - // 29 FIRST_DAI - uint8_t codebook_HARQ_ACK = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI. - - if (pdsch_HARQ_ACK_Codebook == semiStatic) codebook_HARQ_ACK = 1; - - if (pdsch_HARQ_ACK_Codebook == dynamic) codebook_HARQ_ACK = 2; - - // 30 SECOND_DAI - uint8_t n_HARQ_ACK_sub_codebooks = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI. FIXME!!! - // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND - uint8_t pdsch_harq_t_ind = (uint8_t)ceil(log2(pucch_config_dedicated.dl_DataToUL_ACK[0])); - // 36 SRS_RESOURCE_IND - // n_SRS is the number of configured SRS resources in the SRS resource set associated with the higher layer parameter usage of value 'codeBook' or 'nonCodeBook' - // from SRS_ResourceSet_t type we should get the information of the usage parameter (with possible values beamManagement, codebook, nonCodebook, antennaSwitching) - // at frame_parms->srs_nr->p_SRS_ResourceSetList[]->usage - uint8_t n_SRS = ue->srs.number_srs_Resource_Set; - // 37 PRECOD_NBR_LAYERS - // 38 ANTENNA_PORTS - txConfig_t txConfig = pusch_config.txConfig; - transformPrecoder_t transformPrecoder = pusch_config.transformPrecoder; - codebookSubset_t codebookSubset = pusch_config.codebookSubset; - uint8_t maxRank = pusch_config.maxRank; - uint8_t num_antenna_ports = 1; // this is hardcoded. We need to get the real value FIXME!!! - uint8_t precond_nbr_layers_bits = 0; - uint8_t antenna_ports_bits_ul = 0; - - // searching number of bits at tables 7.3.1.1.2-2/3/4/5 from TS 38.212 subclause 7.3.1.1.2 - if (txConfig == txConfig_codebook) { - if (num_antenna_ports == 4) { - if ((transformPrecoder == transformPrecoder_disabled) && ((maxRank == 2)||(maxRank == 3)||(maxRank == 4))) { // Table 7.3.1.1.2-2 - if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=6; - - if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=5; - - if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=4; - } - - if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-3 - if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=5; - - if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=4; - - if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2; - } - } - - if (num_antenna_ports == 2) { - if ((transformPrecoder == transformPrecoder_disabled) && (maxRank == 2)) { // Table 7.3.1.1.2-4 - if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=4; - - if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2; - } - - if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-5 - if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=3; - - if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=1; - } - } - } - - if (txConfig == txConfig_nonCodebook) { - } - - // searching number of bits at tables 7.3.1.1.2-6/7/8/9/10/11/12/13/14/15/16/17/18/19 - if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)) { - if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 2; - - if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4; - - if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 3; - - if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4; - } - - if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type2)) { - if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 4; - - if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 5; - } - - // for format 1_1 number of bits as defined by Tables 7.3.1.2.2-1/2/3/4 - uint8_t antenna_ports_bits_dl = 0; - - if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 4; // Table 7.3.1.2.2-1 - - if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-2 - - if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-3 - - if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 6; // Table 7.3.1.2.2-4 - - // 39 TCI - uint8_t tci_bits=0; - - if (pdcch_vars2->coreset[p].tciPresentInDCI == tciPresentInDCI_enabled) tci_bits=3; - - // 42 CSI_REQUEST - // reportTriggerSize is defined in the CSI-MeasConfig IE (TS 38.331). - // Size of CSI request field in DCI (bits). Corresponds to L1 parameter 'ReportTriggerSize' (see 38.214, section 5.2) - uint8_t reportTriggerSize = csi_MeasConfig.reportTriggerSize; // value from 0..6 - // 43 CBGTI - // for format 0_1 - uint8_t maxCodeBlockGroupsPerTransportBlock = 0; - - if (PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock != 0) - maxCodeBlockGroupsPerTransportBlock = (uint8_t)PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock; - - // for format 1_1, as defined in Subclause 5.1.7 of [6, TS38.214] - uint8_t maxCodeBlockGroupsPerTransportBlock_dl = 0; - - if (PDSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock_dl != 0) - maxCodeBlockGroupsPerTransportBlock_dl = pdsch_config.maxNrofCodeWordsScheduledByDCI; // FIXME!!! - - // 44 CBGFI - uint8_t cbgfi_bit = PDSCH_ServingCellConfig.codeBlockGroupFlushIndicator; - // 45 PTRS_DMRS - // 0 bit if PTRS-UplinkConfig is not configured and transformPrecoder=disabled, or if transformPrecoder=enabled, or if maxRank=1 - // 2 bits otherwise - uint8_t ptrs_dmrs_bits=0; //FIXME!!! - // 46 BETA_OFFSET_IND - // at IE PUSCH-Config, beta_offset indicator – 0 if the higher layer parameter betaOffsets = semiStatic; otherwise 2 bits - // uci-OnPUSCH - // Selection between and configuration of dynamic and semi-static beta-offset. If the field is absent or released, the UE applies the value 'semiStatic' and the BetaOffsets - uint8_t betaOffsets = 0; - - if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_semiStatic); - - if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_dynamic) betaOffsets = 2; - - // 47 DMRS_SEQ_INI - uint8_t dmrs_seq_ini_bits_ul = 0; - uint8_t dmrs_seq_ini_bits_dl = 0; - - //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-UplinkConfig - if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.scramblingID0 != 0) && (dmrs_UplinkConfig.scramblingID1 != 0)) dmrs_seq_ini_bits_ul = 1; - - //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-DownlinkConfig - if ((dmrs_DownlinkConfig.scramblingID0 != 0) && (dmrs_DownlinkConfig.scramblingID0 != 0)) dmrs_seq_ini_bits_dl = 1; - - /* - * For format 2_2 - * - * This format supports power control commands for semi-persistent scheduling. - * As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH) - * - * This format will be implemented in the future FIXME!!! - * - */ - // 5 BLOCK_NUMBER: The parameter tpc-PUSCH or tpc-PUCCH provided by higher layers determines the index to the block number for an UL of a cell - // The following fields are defined for each block: Closed loop indicator and TPC command - // 6 CLOSE_LOOP_IND - // 41 TPC_CMD - uint8_t tpc_cmd_bit_2_2 = 2; - /* - * For format 2_3 - * - * This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control - * either because independent control is desirable or because the device is configured without PUCCH and PUSCH - * - * This format will be implemented in the future FIXME!!! - * - */ - // 40 SRS_REQUEST - // 41 TPC_CMD - uint8_t tpc_cmd_bit_2_3 = 0; - uint8_t dci_field_size_table [NBR_NR_DCI_FIELDS][NBR_NR_FORMATS] = { // This table contains the number of bits for each field (row) contained in each dci format (column). - // The values of the variables indicate field sizes in number of bits - //Format0_0 Format0_1 Format1_0 Format1_1 Formats2_0/1/2/3 - { - 1, 1, (((crc_scrambled == _p_rnti) || (crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti)) ? 0:1), - 1, 0,0,0,0 - }, // 0 IDENTIFIER_DCI_FORMATS: - { - 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3), - 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3), - 0,0,0,0 - }, // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213] - {0, (sul_ind == 0)?0:1, 0, 0, 0,0,0,0}, // 2 SUL_IND_0_1: - {0, 0, 0, 0, 1,0,0,0}, // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213] - {0, 0, 0, 0, 0,1,0,0}, // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits - {0, 0, 0, 0, 0,0,0,0}, // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3 - {0, 0, 0, 0, 0,0,1,0}, // 6 CLOSE_LOOP_IND - { - 0, (uint8_t)ceil(log2(n_UL_BWP_RRC)), - 0, (uint8_t)ceil(log2(n_DL_BWP_RRC)), - 0,0,0,0 - }, // 7 BANDWIDTH_PART_IND: - { - 0, 0, ((crc_scrambled == _p_rnti) ? 2:0), - 0, 0,0,0,0 - }, // 8 SHORT_MESSAGE_IND 2 bits if crc scrambled with P-RNTI - { - 0, 0, ((crc_scrambled == _p_rnti) ? 8:0), - 0, 0,0,0,0 - }, // 9 SHORT_MESSAGES 8 bit8 if crc scrambled with P-RNTI - { - (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping, - n_bits_freq_dom_res_assign_ul, - 0, 0, 0,0,0,0 - }, // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered - // (NOTE 1) If DCI format 0_0 is monitored in common search space - // and if the number of information bits in the DCI format 0_0 prior to padding - // is larger than the payload size of the DCI format 1_0 monitored in common search space - // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 - // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0 - { - 0, 0, (uint8_t)ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2)), - n_bits_freq_dom_res_assign_dl, - 0,0,0,0 - }, // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - { - 4, (uint8_t)log2(pusch_alloc_list), - 4, (uint8_t)log2(pdsch_alloc_list), - 0,0,0,0 - }, // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - // where I the number of entries in the higher layer parameter pusch-AllocationList - { - 0, 0, 1, (((dl_res_alloc_type_0==1) &&(dl_res_alloc_type_1==0))?0:1), - 0,0,0,0 - }, // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - {0, 0, 0, prb_BundlingType_size, 0,0,0,0}, // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] - {0, 0, 0, rateMatching_bits, 0,0,0,0}, // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set - {0, 0, 0, n_zp_bits, 0,0,0,0}, // 16 ZP_CSI_RS_TRIGGER: - { - 1, (((ul_res_alloc_type_0==1) &&(ul_res_alloc_type_1==0))||(freqHopping == 0))?0:1, - 0, 0, 0,0,0,0 - }, // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 - {0, 0, 0, 5, 0,0,0,0}, // 18 TB1_MCS: - {0, 0, 0, 1, 0,0,0,0}, // 19 TB1_NDI: - {0, 0, 0, 2, 0,0,0,0}, // 20 TB1_RV: - {0, 0, 0, 5, 0,0,0,0}, // 21 TB2_MCS: - {0, 0, 0, 1, 0,0,0,0}, // 22 TB2_NDI: - {0, 0, 0, 2, 0,0,0,0}, // 23 TB2_RV: - {5, 5, 5, 0, 0,0,0,0}, // 24 MCS: - {1, 1, (crc_scrambled == _c_rnti)?1:0,0, 0,0,0,0}, // 25 NDI: - { - 2, 2, (((crc_scrambled == _c_rnti) || (crc_scrambled == _si_rnti)) ? 2:0), - 0, 0,0,0,0 - }, // 26 RV: - {4, 4, (crc_scrambled == _c_rnti)?4:0,4, 0,0,0,0}, // 27 HARQ_PROCESS_NUMBER: - {0, 0, (crc_scrambled == _c_rnti)?2:0,n_dai, 0,0,0,0}, // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI - // 0 otherwise - {0, codebook_HARQ_ACK, 0, 0, 0,0,0,0}, // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK // 2 bits for dynamic HARQ-ACK codebook with single HARQ-ACK codebook - { - 0, (((codebook_HARQ_ACK == 2) &&(n_HARQ_ACK_sub_codebooks==2))?2:0), - 0, 0, 0,0,0,0 - }, // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks // 0 bits otherwise - { - 0, 0, (((crc_scrambled == _p_rnti) || (crc_scrambled == _ra_rnti)) ? 2:0), - 0, 0,0,0,0 - }, // 31 TB_SCALING - {2, 2, 0, 0, 0,0,0,0}, // 32 TPC_PUSCH: - {0, 0, (crc_scrambled == _c_rnti)?2:0,2, 0,0,0,0}, // 33 TPC_PUCCH: - {0, 0, (crc_scrambled == _c_rnti)?3:0,3, 0,0,0,0}, // 34 PUCCH_RESOURCE_IND: - {0, 0, (crc_scrambled == _c_rnti)?3:0,pdsch_harq_t_ind, 0,0,0,0}, // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: - {0, (uint8_t)log2(n_SRS), 0, 0, 0,0,0,0}, // 36 SRS_RESOURCE_IND: - {0, precond_nbr_layers_bits, 0, 0, 0,0,0,0}, // 37 PRECOD_NBR_LAYERS: - {0, antenna_ports_bits_ul, 0, antenna_ports_bits_dl, 0,0,0,0}, // 38 ANTENNA_PORTS: - {0, 0, 0, tci_bits, 0,0,0,0}, // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits - {0, (sul_ind == 0)?2:3, 0, (sul_ind == 0)?2:3, 0,0,0,2}, // 40 SRS_REQUEST: - { - 0, 0, 0, 0, 0,0,tpc_cmd_bit_2_2, - tpc_cmd_bit_2_3 - }, - // 41 TPC_CMD: - {0, reportTriggerSize, 0, 0, 0,0,0,0}, // 42 CSI_REQUEST: - { - 0, maxCodeBlockGroupsPerTransportBlock, - 0, maxCodeBlockGroupsPerTransportBlock_dl, - 0,0,0,0 - }, // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH - {0, 0, 0, cbgfi_bit, 0,0,0,0}, // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator - {0, ptrs_dmrs_bits, 0, 0, 0,0,0,0}, // 45 PTRS_DMRS: - {0, betaOffsets, 0, 0, 0,0,0,0}, // 46 BETA_OFFSET_IND: - {0, dmrs_seq_ini_bits_ul, 0, dmrs_seq_ini_bits_dl, 0,0,0,0}, // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding - // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise - {0, 1, 0, 0, 0,0,0,0}, // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH - {0, 0, 0, 0, 0,0,0,0}, // 49 PADDING_NR_DCI: - // (NOTE 2) If DCI format 0_0 is monitored in common search space - // and if the number of information bits in the DCI format 0_0 prior to padding - // is less than the payload size of the DCI format 1_0 monitored in common search space - // zeros shall be appended to the DCI format 0_0 - // until the payload size equals that of the DCI format 1_0 - {(sul_ind == 0)?0:1, 0, 0, 0, 0,0,0,0}, // 50 SUL_IND_0_0: - {0, 0, 0, 0, 0,0,0,0}, // 51 RA_PREAMBLE_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) - {0, 0, 0, 0, 0,0,0,0}, // 52 SUL_IND_1_0 (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) - {0, 0, 0, 0, 0,0,0,0}, // 53 SS_PBCH_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) - {0, 0, 0, 0, 0,0,0,0}, // 54 PRACH_MASK_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) - { - 0, 0, ((crc_scrambled == _p_rnti)?6:(((crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti))?16:0)), - 0, 0,0,0,0 - } // 55 RESERVED_NR_DCI - }; - // NOTE 1: adjustments in freq_dom_resource_assignment_UL to be done if necessary - // NOTE 2: adjustments in padding to be done if necessary - uint8_t dci_size [8] = {0,0,0,0,0,0,0,0}; // will contain size for each format - - for (int i=0 ; i position in table is 2) - dci_fields_sizes[j][i] = dci_field_size_table[j][i]; // dci_fields_sizes[j] contains the sizes of each field (j) for a determined format i - //} - } - - LOG_DDD("(nr_dci_format_size) dci_size[%d]=%d for n_RB_ULBWP=%d\n", - i,dci_size[i],n_RB_ULBWP); - } - - LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n"); - -#ifdef NR_PDCCH_DCI_DEBUG - for (int j=0; j dci_size[2])) { - dci_field_size_table[SUL_IND_0_0][0] = 0; - dci_size[0]=dci_size[0]-1; - } - - // if ((format == format0_0) || (format == format1_0)) { - // According to Section 7.3.1.1.1 in TS 38.212 - // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding - // is less than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell, - // zeros shall be appended to the DCI format 0_0 until the payload size equals that of the DCI format 1_0. - if (dci_size[0] < dci_size[2]) { // '0' corresponding to index for format0_0 and '2' corresponding to index of format1_0 - //if (format == format0_0) { - dci_fields_sizes[PADDING_NR_DCI][0] = dci_size[2] - dci_size[0]; - dci_size[0] = dci_size[2]; - LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]); - //} - } - - // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding - // is larger than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell, - // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 is reduced - // such that the size of DCI format 0_0 equals to the size of the DCI format 1_0.. - if (dci_size[0] > dci_size[2]) { - //if (format == format0_0) { - dci_fields_sizes[FREQ_DOM_RESOURCE_ASSIGNMENT_UL][0] -= (dci_size[0] - dci_size[2]); - dci_size[0] = dci_size[2]; - LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]); - //} - } - - /* - * TS 38.212 subclause 7.3.1.1.2 - * For a UE configured with SUL in a cell: - * if PUSCH is configured to be transmitted on both the SUL and the non-SUL of the cell and - * if the number of information bits in format 0_1 for the SUL - * is not equal to the number of information bits in format 0_1 for the non-SUL, - * zeros shall be appended to smaller format 0_1 until the payload size equals that of the larger format 0_1 - * - * Not implemented. FIXME!!! - * - */ - // } - LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n"); - -#ifdef NR_PDCCH_DCI_DEBUG - for (int j=0; j" a) -#else -#define LOG_DCI_D(a...) -#endif -#define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a) -typedef unsigned __int128 uint128_t; -int8_t nr_delta_PUSCH_abs[4] = {-4,-1,1,4}; -int8_t nr_delta_PUSCH_acc[4] = {-1,0,1,3}; -int8_t *nr_delta_PUCCH_lut = nr_delta_PUSCH_acc; -#ifdef NR_PDCCH_DCI_TOOLS - -uint16_t nr_dci_field(uint64_t dci_pdu[2], - uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS], - uint8_t dci_field) { - int dci_size=0; - - for (int i=0; i 64 bits, not supported for now\n", - dci_size); - uint16_t first_bit_position = dci_size; - - for (int i=0; i<=dci_field ; i++) { - first_bit_position = first_bit_position - dci_fields_sizes[i]; - } - - /*uint16_t tmp1 = ((*dci_pdu>>first_bit_position)&((1<>i)&1)<<(dci_fields_sizes[dci_field]-i-1);*/ - return ((uint16_t)(*dci_pdu>>first_bit_position)&((1< (1 1010 1000 1001 0000 0000 0111 1000 1001 1010 0) - * then we will do a right-shit of dci_length-13 positions -> (1 1010 1000 1001). And this is the content of the freq_dom_resource_assignment_DL field - * - * - * At the moment we have implemented the following formats: - * - * Format 0_0, that contains the following fields according to Specification 38.212 V15.1.1 Section 7.3.1 - * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 32 TPC_PUSCH: - * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space - * 50 SUL_IND_0_0: - * - * Format 0_1, that contains the following fields - * with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 1 CARRIER_IND - * 2 SUL_IND_0_1 - * 7 BANDWIDTH_PART_IND - * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 29 FIRST_DAI - * 30 SECOND_DAI - * 32 TPC_PUSCH: - * 36 SRS_RESOURCE_IND: - * 37 PRECOD_NBR_LAYERS: - * 38 ANTENNA_PORTS: - * 40 SRS_REQUEST: - * 42 CSI_REQUEST: - * 43 CBGTI - * 45 PTRS_DMRS - * 46 BETA_OFFSET_IND - * 47 DMRS_SEQ_INI - * 48 UL_SCH_IND - * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space - * - * Format 1_0, that contains the following fields - * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - * 33 TPC_PUCCH: - * 34 PUCCH_RESOURCE_IND: - * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: - * 55 RESERVED_NR_DCI - * - * If the CRC of the DCI format 1_0 is scrambled by C-RNTI and the "Frequency domain resource assignment" field are of all ones, - * the DCI format 1_0 is for random access procedure initiated by a PDCCH order. - * This is not implemented, but the fields are already included: FIXME!!! - * - * with CRC scrambled by P-RNTI - * 8 SHORT_MESSAGE_IND - * 9 SHORT_MESSAGES - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 31 TB_SCALING - * 55 RESERVED_NR_DCI - * - * with CRC scrambled by SI-RNTI - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 26 RV: - * 55 RESERVED_NR_DCI - * - * with CRC scrambled by RA-RNTI - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 31 TB_SCALING - * 55 RESERVED_NR_DCI - * - * with CRC scrambled by TC-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - * 33 TPC_PUCCH: - * - * Format 1_1, that contains the following fields - * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 1 CARRIER_IND: - * 7 BANDWIDTH_PART_IND: - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 14 PRB_BUNDLING_SIZE_IND: - * 15 RATE_MATCHING_IND: - * 16 ZP_CSI_RS_TRIGGER: - * 18 TB1_MCS: - * 19 TB1_NDI: - * 20 TB1_RV: - * 21 TB2_MCS: - * 22 TB2_NDI: - * 23 TB2_RV: - * 27 HARQ_PROCESS_NUMBER: - * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - * 33 TPC_PUCCH: - * 34 PUCCH_RESOURCE_IND: - * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: - * 38 ANTENNA_PORTS: - * 39 TCI: - * 40 SRS_REQUEST: - * 43 CBGTI: - * 44 CBGFI: - * 47 DMRS_SEQ_INI: - * - * We have not implemented the following formats: - * - * Format 2_0 - * Used for notifying the slot format - * - * Format 2_1 - * Used for notifying the PRB(s) and OFDM symbol(s) where UE may assume no transmission is intended for the UE - * - * Format 2_2 - * This format supports power control commands for semi-persistent scheduling. - * As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH) - * This format will be implemented in the future FIXME!!! - * - * Format 2_3 - * This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control - * either because independent control is desirable or because the device is configured without PUCCH and PUSCH - * This format will be implemented in the future FIXME!!! - * - */ - uint8_t dci_fields_sizes_format[NBR_NR_DCI_FIELDS] = {0}; - - for (int m=0; m> (DCI_MAX_SIZE - dci_length); // this variable will help to remove the bits of other fields when left-switching - uint8_t dci_field=0; - // uint8_t sizes_count=0; - // uint8_t left_shift=0; - LOG_DCI_D("Entering function nr_extract_dci_info() with dci_pdu=%lx %lx dci_length=%d\n", - dci_pdu[0],dci_pdu[1], dci_length); - LOG_DCI_D("for format %d, dci_fields_sizes {",dci_format); -#ifdef NR_PDCCH_DCI_TOOLS_DEBUG - - for (int i=0; iDCINdi; - - /* - * Some dci fields need to be interpreted before the others. - */ - if (dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format] != 0) { // E.g: 27 HARQ_PROCESS_NUMBER (27 is the position in dci_fields_sizes array for field HARQ_PROCESS_NUMBER) - //for (int i=0; i<=HARQ_PROCESS_NUMBER; i++) left_shift = left_shift + dci_fields_sizes[i][dci_format]; - nr_pdci_info_extracted->harq_process_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,HARQ_PROCESS_NUMBER); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format])); - //left_shift = 0; - LOG_DCI_D("nr_pdci_info_extracted->harq_process_number=%x\n",nr_pdci_info_extracted->harq_process_number); - } - - /* - if ((dci_format == format1_0) || (dci_format == format1_1)) { - if (rnti==crc_scrambled_values[_SI_RNTI_]) { - ue->dlsch_SI[eNB_id]->active = 1; - } else if (rnti==crc_scrambled_values[_P_RNTI_]) { - ue->dlsch_p[eNB_id]->active = 1; - } else if (rnti==crc_scrambled_values[_RA_RNTI_]) { - ue->dlsch_ra[eNB_id]->active = 1; - } else { - pdlsch0->active = 1; - } - pdlsch0->rnti = rnti; - pdlsch0_harq->codeword = 0; - pdlsch0_harq->Nl = 1; - // pdlsch0_harq->mimo_mode = frame_parms->mode1_flag == 1 ?SISO : ALAMOUTI; - pdlsch0_harq->dl_power_off = 1; //no power offset - - if ((rnti==crc_scrambled_values[_SI_RNTI_]) || (rnti==crc_scrambled_values[_P_RNTI_]) || (rnti==crc_scrambled_values[_RA_RNTI_])) { - pdlsch0_harq->round = 0; - pdlsch0_harq->status = ACTIVE; - } else { - } - } - */ - for (dci_field=0; dci_fieldidentifier_dci_formats = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->identifier_dci_formats=%x\n",nr_pdci_info_extracted->identifier_dci_formats); - break; - - case CARRIER_IND: // 1 CARRIER_IND: (field defined for -,format0_1,-,format1_1,-,-,-,-) - // 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213] - nr_pdci_info_extracted->carrier_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->carrier_ind=%x\n",nr_pdci_info_extracted->carrier_ind); - break; - - case SUL_IND_0_1: // 2 SUL_IND_0_1: (field defined for -,format0_1,-,-,-,-,-,-) - nr_pdci_info_extracted->sul_ind_0_1 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->sul_ind_0_1=%x\n",nr_pdci_info_extracted->sul_ind_0_1); - break; - - case SLOT_FORMAT_IND: // 3 SLOT_FORMAT_IND: (field defined for -,-,-,-,format2_0,-,-,-) - // size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213] - nr_pdci_info_extracted->slot_format_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->slot_format_ind=%x\n",nr_pdci_info_extracted->slot_format_ind); - break; - - case PRE_EMPTION_IND: // 4 PRE_EMPTION_IND: (field defined for -,-,-,-,-,format2_1,-,-) - // size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits - nr_pdci_info_extracted->pre_emption_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->pre_emption_ind=%x\n",nr_pdci_info_extracted->pre_emption_ind); - break; - - case BLOCK_NUMBER: // 5 BLOCK_NUMBER: (field defined for -,-,-,-,-,-,-,format2_3) - // starting position of a block is determined by the parameter startingBitOfFormat2_3 - nr_pdci_info_extracted->block_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->block_number=%x\n",nr_pdci_info_extracted->block_number); - break; - - case CLOSE_LOOP_IND: // 6 CLOSE_LOOP_IND: (field defined for -,-,-,-,-,-,format2_2,-) - // The parameter xxx provided by higher layers determines the index to the TPC command number for an UL of a cell. Each TPC command number is 2 bits - nr_pdci_info_extracted->close_loop_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->close_loop_ind=%x\n",nr_pdci_info_extracted->close_loop_ind); - break; - - case BANDWIDTH_PART_IND: // 7 BANDWIDTH_PART_IND: (field defined for -,format0_1,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->bandwidth_part_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->bandwidth_part_ind=%x\n",nr_pdci_info_extracted->bandwidth_part_ind); - break; - - case SHORT_MESSAGE_IND: // 8 SHORT_MESSAGE_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-) - nr_pdci_info_extracted->short_message_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->short_message_ind=%x\n",nr_pdci_info_extracted->short_message_ind); - break; - - case SHORT_MESSAGES: // 9 SHORT_MESSAGES: (field defined for -,-,format1_0,format1_1,-,-,-,-) - nr_pdci_info_extracted->short_messages = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->short_messages=%x\n",nr_pdci_info_extracted->short_messages); - break; - - case FREQ_DOM_RESOURCE_ASSIGNMENT_UL: // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: (field defined for format0_0,format0_1,-,-,-,-,-,-) - // PUSCH hopping with resource allocation type 1 not considered - // According to 38.214 V15.1.0 Section 6.1.2.2 Two uplink resource allocation schemes, type 0 and type 1, are supported. - // The UE shall assume that when the scheduling PDCCH is received with DCI format 0_0, then uplink resource allocation type 1 is used. - nr_pdci_info_extracted->freq_dom_resource_assignment_UL = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - /*if (dci_format == format0_1){ // uplink resource allocation type 0 or 1 can be used - } - if (dci_format == format0_0){ // only uplink resource allocation type 1 - // At the moment we are supporting only format 1_0 (and not format 1_1), so we only support resource allocation type 1 (and not type 0). - // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV): - // RIV = n_RB_ULBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_ULBWP/2) - // RIV = n_RB_ULBWP * (n_RB_ULBWP - l_RB + 1) + (n_RB_ULBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_ULBWP/2) - // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_ULBWP/2) - l_RB = floor(nr_pdci_info_extracted->freq_dom_resource_assignment_DL/n_RB_ULBWP) + 1; - start_RB = nr_pdci_info_extracted->freq_dom_resource_assignment_DL%n_RB_ULBWP; - // if (l_RB - 1) > floor (n_RB_ULBWP/2) we need to recalculate them using the following lines - tmp_RIV = n_RB_ULBWP * (l_RB - 1) + start_RB; - if (tmp_RIV != nr_pdci_info_extracted->freq_dom_resource_assignment_DL) { // then (l_RB - 1) > floor (n_RB_ULBWP/2) and we need to recalculate l_RB and start_RB - l_RB = n_RB_ULBWP - l_RB + 2; - start_RB = n_RB_ULBWP - start_RB - 1; - } - ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_rb = start_RB; - ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->nb_rb = l_RB; - }*/ - LOG_DCI_D("nr_pdci_info_extracted->freq_dom_resource_assignment_UL=%x\n",nr_pdci_info_extracted->freq_dom_resource_assignment_UL); - //LOG_DCI_D("l_RB=%d, start_RB=%d, n_RB_DLBWP=%d\n",l_RB,start_RB,n_RB_ULBWP); - break; - - case FREQ_DOM_RESOURCE_ASSIGNMENT_DL: // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: (field defined for -,-,format1_0,format1_1,-,-,-,-) - // According to 38.214 V15.1.0 Section 5.1.2.2 Two downlink resource allocation schemes, type 0 and type 1, are supported. - // The UE shall assume that when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used. - nr_pdci_info_extracted->freq_dom_resource_assignment_DL = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - /*if (dci_format == format1_1){ // uplink resource allocation type 0 or 1 can be used - } - if (dci_format == format1_0){ // only uplink resource allocation type 1 - // At the moment we are supporting only format 0_0 (and not format 0_1), so we only support resource allocation type 1 (and not type 0). - // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV): - // RIV = n_RB_DLBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_DLBWP/2) - // RIV = n_RB_DLBWP * (n_RB_DLBWP - l_RB + 1) + (n_RB_DLBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_DLBWP/2) - // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_DLBWP/2) - l_RB = floor(nr_pdci_info_extracted->freq_dom_resource_assignment_DL/n_RB_DLBWP) + 1; - start_RB = nr_pdci_info_extracted->freq_dom_resource_assignment_DL%n_RB_DLBWP; - // if (l_RB - 1) > floor (n_RB_DLBWP/2) we need to recalculate them using the following lines - tmp_RIV = n_RB_DLBWP * (l_RB - 1) + start_RB; - if (tmp_RIV != nr_pdci_info_extracted->freq_dom_resource_assignment_DL) { // then (l_RB - 1) > floor (n_RB_DLBWP/2) and we need to recalculate l_RB and start_RB - l_RB = n_RB_DLBWP - l_RB + 2; - start_RB = n_RB_DLBWP - start_RB - 1; - } - pdlsch0_harq->nb_rb = l_RB; - pdlsch0->current_harq_pid = nr_pdci_info_extracted->harq_process_number; - pdlsch0->active = 1; - pdlsch0->rnti = rnti; - }*/ - LOG_DCI_D("nr_pdci_info_extracted->freq_dom_resource_assignment_DL=%x, RIV = %d\n",nr_pdci_info_extracted->freq_dom_resource_assignment_DL,nr_pdci_info_extracted->freq_dom_resource_assignment_DL); - //LOG_DCI_D("l_RB=%d, start_RB=%d, n_RB_DLBWP=%d\n",l_RB,start_RB,n_RB_DLBWP); - /* - * According to TC 38.212 Subclause 7.3.1.2.1 (V15.2.0) (not implemented FIXME!!!) - * If the CRC of the DCI format 1_0 is scrambled by C-RNTI - * and the "Frequency domain resource assignment" field are of all ones, - * the DCI format 1_0 is for random access procedure initiated by a PDCCH order, - * with all remaining fields set as follows: - * - Random Access Preamble index (6 bits) - * - UL/SUL indicator (1 bit) - * - SS/PBCH index (6 bits) - * - PRACH Mask index (4 bits) - * - Reserved bits (10 bits) - * - */ - /* - * The following commented code is used to verify that l_RB and start_RB are correctly calculated - * - * - printf("\ns_RB\t"); - n_RB_DLBWP = 20; - for (int k = 0 ; k < n_RB_DLBWP; k++) printf("%d\t",k); - printf("\nl_RB"); - for (int j = 1 ; j <= n_RB_DLBWP; j++){ // l_RB - printf("\n%d\t",j); - for (int i = 0 ; i < n_RB_DLBWP; i++) { // start_RB - if ((j-1) <= (floor(n_RB_DLBWP/2)) && ((j+i) <= n_RB_DLBWP)) { - tmp_RIV = n_RB_DLBWP * (j - 1) + i; - l_RB = floor(tmp_RIV/n_RB_DLBWP) + 1; - start_RB = tmp_RIV%n_RB_DLBWP; - printf("%d(%d,%d) ",tmp_RIV,l_RB,start_RB); - } - if ((j-1) > (floor(n_RB_DLBWP/2)) && ((j+i) <= n_RB_DLBWP)) { - tmp_RIV = n_RB_DLBWP * (n_RB_DLBWP - j + 1) + (n_RB_DLBWP - 1 - i); - //l_RB = floor(tmp_RIV/n_RB_DLBWP) + 1; - //start_RB = tmp_RIV%n_RB_DLBWP; - l_RB = n_RB_DLBWP - (floor(tmp_RIV/n_RB_DLBWP) + 1) + 2; - start_RB = n_RB_DLBWP - (tmp_RIV%n_RB_DLBWP) - 1; - printf("%d*(%d,%d) ",tmp_RIV,l_RB,start_RB); - } - } - }*/ - break; - - case TIME_DOM_RESOURCE_ASSIGNMENT: // 12 TIME_DOM_RESOURCE_ASSIGNMENT: (field defined for format0_0,format0_1,format1_0,format1_1,-,-,-,-) - // 0, 1, 2, 3, or 4 bits as defined in: - // Subclause 6.1.2.1 of [6, TS 38.214] for formats format0_0,format0_1 - // Subclause 5.1.2.1 of [6, TS 38.214] for formats format1_0,format1_1 - // The bitwidth for this field is determined as log2(I) bits, - // where I the number of entries in the higher layer parameter pusch-AllocationList - nr_pdci_info_extracted->time_dom_resource_assignment = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - /*if (dci_format == format0_0 || dci_format == format0_1){ // Subclause 6.1.2.1 of [6, TS 38.214] - k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][0]; - sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][1]; - sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - // k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0]; - // sliv_S = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1]; - // sliv_L = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - - } - if (dci_format == format1_0 || dci_format == format1_1){ // Subclause 5.1.2.1 of [6, TS 38.214] - // the Time domain resource assignment field of the DCI provides a row index of a higher layer configured table pdsch-symbolAllocation - // FIXME! To clarify which parameters to update after reception of row index - k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][0]; - sliv_S = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][1]; - sliv_L = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - // k_offset = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0]; - // sliv_S = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1]; - // sliv_L = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - // k_offset = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][0]; - // sliv_S = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][1]; - // sliv_L = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - // k_offset = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][0]; - // sliv_S = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][1]; - // sliv_L = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - }*/ - LOG_DCI_D("nr_pdci_info_extracted->time_dom_resource_assignment=%x\n",nr_pdci_info_extracted->time_dom_resource_assignment); - break; - - case VRB_TO_PRB_MAPPING: // 13 VRB_TO_PRB_MAPPING: (field defined for -,format0_1,format1_0,format1_1,-,-,-,-) - //0 bit if resource allocation type 0 - //1 bit if resource allocation type 1 - //Table 7.3.1.1.2-33: VRB-to-PRB mapping - // 0 Non-interleaved - // 1 Interleaved - nr_pdci_info_extracted->vrb_to_prb_mapping = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (nr_pdci_info_extracted->vrb_to_prb_mapping == 0) { // Non-interleaved - //} else { // Interleaved - // format 0_1 defined in TS 38.211 Section 6.3.1.7 - // formats 1_0 and 1_1 not defined yet - //} - LOG_DCI_D("nr_pdci_info_extracted->vrb_to_prb_mapping=%x\n",nr_pdci_info_extracted->vrb_to_prb_mapping); - break; - - case PRB_BUNDLING_SIZE_IND: // 14 PRB_BUNDLING_SIZE_IND: (field defined for -,-,-,format1_1,-,-,-,-) - // 0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] - nr_pdci_info_extracted->prb_bundling_size_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->prb_bundling_size_ind=%x\n",nr_pdci_info_extracted->prb_bundling_size_ind); - break; - - case RATE_MATCHING_IND: // 15 RATE_MATCHING_IND: (field defined for -,-,-,format1_1,-,-,-,-) - // 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set - nr_pdci_info_extracted->rate_matching_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->rate_matching_ind=%x\n",nr_pdci_info_extracted->rate_matching_ind); - break; - - case ZP_CSI_RS_TRIGGER: // 16 ZP_CSI_RS_TRIGGER: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->zp_csi_rs_trigger = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->zp_csi_rs_trigger=%x\n",nr_pdci_info_extracted->zp_csi_rs_trigger); - break; - - case FREQ_HOPPING_FLAG: // 17 FREQ_HOPPING_FLAG: (field defined for format0_0,format0_1,-,-,-,-,-,-) - // 0 bit if only resource allocation type 0 - // 1 bit otherwise, only applicable to resource allocation type 1, as defined in Subclause 6.3 of [6, TS 38.214] - nr_pdci_info_extracted->freq_hopping_flag = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (nr_pdci_info_extracted->freq_hopping_flag != 0) { // PUSCH frequency hopping is performed (only resource allocation type 1) - //} else { // PUSCH frequency hopping is not performed (only resource allocation type 1) - // At the moment PUSCH hopping is not implemented. We are considering that the bit is present and the value is '0' - //} - LOG_DCI_D("nr_pdci_info_extracted->freq_hopping_flag=%x\n",nr_pdci_info_extracted->freq_hopping_flag); - break; - - case TB1_MCS: // 18 TB1_MCS: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->tb1_mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (nr_pdci_info_extracted->mcs < 29) pdlsch0_harq->mcs = nr_pdci_info_extracted->tb1_mcs; - LOG_DCI_D("nr_pdci_info_extracted->tb1_mcs=%x\n",nr_pdci_info_extracted->tb1_mcs); - break; - - case TB1_NDI: // 19 TB1_NDI: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->tb1_ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0_harq->DCINdi = nr_pdci_info_extracted->tb1_ndi; - LOG_DCI_D("nr_pdci_info_extracted->tb1_ndi=%x\n",nr_pdci_info_extracted->tb1_ndi); - break; - - case TB1_RV: // 20 TB1_RV: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->tb1_rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0_harq->rvidx = nr_pdci_info_extracted->tb1_rv; - LOG_DCI_D("nr_pdci_info_extracted->tb1_rv=%x\n",nr_pdci_info_extracted->tb1_rv); - break; - - case TB2_MCS: // 21 TB2_MCS: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->tb2_mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (nr_pdci_info_extracted->mcs < 29) pdlsch0_harq->mcs = nr_pdci_info_extracted->tb2_mcs; - LOG_DCI_D("nr_pdci_info_extracted->tb2_mcs=%x\n",nr_pdci_info_extracted->tb2_mcs); - break; - - case TB2_NDI: // 22 TB2_NDI: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->tb2_ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0_harq->DCINdi = nr_pdci_info_extracted->tb2_ndi; - LOG_DCI_D("nr_pdci_info_extracted->tb2_ndi=%x\n",nr_pdci_info_extracted->tb2_ndi); - break; - - case TB2_RV: // 23 TB2_RV: (field defined for -,-,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->tb2_rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0_harq->rvidx = nr_pdci_info_extracted->tb2_rv; - LOG_DCI_D("nr_pdci_info_extracted->tb2_rv=%x\n",nr_pdci_info_extracted->tb2_rv); - break; - - case MCS: // 24 MCS: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-) - nr_pdci_info_extracted->mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (nr_pdci_info_extracted->mcs < 29) { - // if (dci_format == format0_0 || dci_format == format0_1) - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->mcs = nr_pdci_info_extracted->mcs; - // else - // pdlsch0_harq->mcs = nr_pdci_info_extracted->mcs; - //} else { - // return(0); - //} - LOG_DCI_D("nr_pdci_info_extracted->mcs=%x\n",nr_pdci_info_extracted->mcs); - break; - - case NDI: // 25 NDI: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-) - nr_pdci_info_extracted->ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (dci_format == format0_0 || dci_format == format0_1) { - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi = nr_pdci_info_extracted->ndi; - // if (ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_tx==1) { - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_tx=0; - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi= nr_pdci_info_extracted->ndi; - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->round = 0; - // } else { - // if (ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi != nr_pdci_info_extracted->ndi) { // new SDU opportunity - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi= nr_pdci_info_extracted->ndi; - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->round = 0; - // } - // } - //} else { - // if (rnti == crc_scrambled_values[_TC_RNTI_]) { //fix for standalone Contention Resolution Id - // pdlsch0_harq->DCINdi = (uint8_t)-1; - // } else { - // if ((prev_ndi != nr_pdci_info_extracted->ndi) || (pdlsch0_harq->first_tx==1)) { - // pdlsch0_harq->round = 0; - // pdlsch0_harq->first_tx = 0; - // pdlsch0_harq->status = ACTIVE; - // } - // pdlsch0_harq->DCINdi = nr_pdci_info_extracted->ndi; - // } - //} - LOG_DCI_D("nr_pdci_info_extracted->ndi=%x\n",nr_pdci_info_extracted->ndi); - break; - - case RV: // 26 RV: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-) - nr_pdci_info_extracted->rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //if (dci_format == format0_0 || dci_format == format0_1) - // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->rvidx = nr_pdci_info_extracted->rv; - //else - // pdlsch0_harq->rvidx = nr_pdci_info_extracted->rv; - //if ((prev_ndi == nr_pdci_info_extracted->ndi) && (pdlsch0_harq->rvidx != 0)) { // NDI has not been toggled but rv was increased by eNB: retransmission - // if (pdlsch0_harq->status == SCH_IDLE) { - // packet was actually decoded in previous transmission (ACK was missed by eNB) - // however, the round is not a good check as it might have been decoded in a retransmission prior to this one. - // skip pdsch decoding and report ack - // pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.ack = 1; - // pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.send_harq_status; -#if 0 - // pdlsch0->active = 0; - // pdlsch0->harq_ack[nr_tti_rx].ack = 1; - // pdlsch0->harq_ack[nr_tti_rx].harq_id = nr_pdci_info_extracted->harq_process_number; - // pdlsch0->harq_ack[nr_tti_rx].send_harq_status = 1; -#endif - // } else { // normal retransmission, nothing special to do - // } - //} else { - // pdlsch0_harq->status = ACTIVE; - //} - LOG_DCI_D("nr_pdci_info_extracted->rv=%x\n",nr_pdci_info_extracted->rv); - break; - - case HARQ_PROCESS_NUMBER: // 27 HARQ_PROCESS_NUMBER: (field defined for format0_0,format0_1,format1_0,format1_1,-,-,-,-) - nr_pdci_info_extracted->harq_process_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0->current_harq_pid = nr_pdci_info_extracted->harq_process_number; - LOG_DCI_D("nr_pdci_info_extracted->harq_process_number=%x\n",nr_pdci_info_extracted->harq_process_number); - break; - - case DAI_: // 28 DAI_: (field defined for -,-,format1_0,format1_1,-,-,-,-) - // For format1_0: 2 bits as defined in Subclause 9.1.3 at TS 38.213 - // For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI - // 0 otherwise - nr_pdci_info_extracted->dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.vDAI_DL = nr_pdci_info_extracted->dai+1; - //pdlsch0->harq_ack[nr_tti_rx].vDAI_DL = nr_pdci_info_extracted->dai+1; - LOG_DCI_D("nr_pdci_info_extracted->dai=%x\n",nr_pdci_info_extracted->dai); - break; - - case FIRST_DAI: // 29 FIRST_DAI: (field defined for -,format0_1,-,-,-,-,-,-) - // (1 or 2 bits) 1 bit for semi-static HARQ-ACK - nr_pdci_info_extracted->first_dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->first_dai=%x\n",nr_pdci_info_extracted->first_dai); - break; - - case SECOND_DAI: // 30 SECOND_DAI: (field defined for -,format0_1,-,-,-,-,-,-) - // (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks - nr_pdci_info_extracted->second_dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->second_dai=%x\n",nr_pdci_info_extracted->second_dai); - break; - - case TB_SCALING: // 31 TB_SCALING: (field defined for -,format0_1,-,-,-,-,-,-) - // (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks - nr_pdci_info_extracted->tb_scaling = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->tb_scaling=%x\n",nr_pdci_info_extracted->tb_scaling); - break; - - case TPC_PUSCH: // 32 TPC_PUSCH: (field defined for format0_0,format0_1,-,-,-,-,-,-) - // defined in Subclause 7.1.1 TS 38.213 - nr_pdci_info_extracted->tpc_pusch = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC = nr_pdci_info_extracted->tpc_pusch; - //if (ue->ul_power_control_dedicated[eNB_id].accumulationEnabled == 1) { - // ulsch0->f_pusch += nr_delta_PUSCH_acc[ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC]; - //} else { - // ulsch0->f_pusch = nr_delta_PUSCH_abs[ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC]; - //} - LOG_DCI_D("nr_pdci_info_extracted->tpc_pusch=%x\n",nr_pdci_info_extracted->tpc_pusch); - break; - - case TPC_PUCCH: // 33 TPC_PUCCH: (field defined for -,-,format1_0,format1_1,-,-,-,-) - // defined in Subclause 7.2.1 TS 38.213 - nr_pdci_info_extracted->tpc_pucch = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - //pdlsch0_harq->delta_PUCCH = nr_delta_PUCCH_lut[nr_pdci_info_extracted->tpc_pucch &3]; - LOG_DCI_D("nr_pdci_info_extracted->tpc_pucch=%x\n",nr_pdci_info_extracted->tpc_pucch); - break; - - case PUCCH_RESOURCE_IND: // 34 PUCCH_RESOURCE_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-) - // defined in Subclause 9.2.3 TS 38.213 - // PUCCH_RESOURCE_IND points to PUCCH-ResourceId, but PUCCH-ResourceId is not defined yet - nr_pdci_info_extracted->pucch_resource_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->pucch_resource_ind=%x\n",nr_pdci_info_extracted->pucch_resource_ind); - break; - - case PDSCH_TO_HARQ_FEEDBACK_TIME_IND: // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-) - // defined in Subclause 9.2.3 TS 38.213 - // PDSCH_TO_HARQ_FEEDBACK_TIME_IND points to DL-data-DL-acknowledgement, but DL-data-DL-acknowledgement is not defined yet - nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind=%x\n",nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind); - break; - - case SRS_RESOURCE_IND: // 36 SRS_RESOURCE_IND: (field defined for -,format0_1,-,-,-,-,-,-) - nr_pdci_info_extracted->srs_resource_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->srs_resource_ind=%x\n",nr_pdci_info_extracted->srs_resource_ind); - break; - - case PRECOD_NBR_LAYERS: // 37 PRECOD_NBR_LAYERS: (field defined for -,format0_1,-,-,-,-,-,-) - nr_pdci_info_extracted->precod_nbr_layers = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->precod_nbr_layers=%x\n",nr_pdci_info_extracted->precod_nbr_layers); - break; - - case ANTENNA_PORTS: // 38 ANTENNA_PORTS: (field defined for -,format0_1,-,format1_1,-,-,-,-) - nr_pdci_info_extracted->antenna_ports = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->antenna_ports=%x\n",nr_pdci_info_extracted->antenna_ports); - break; - - case TCI: // 39 TCI: (field defined for -,-,-,format1_1,-,-,-,-) - // 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits - nr_pdci_info_extracted->tci = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->tci=%x\n",nr_pdci_info_extracted->tci); - break; - - case SRS_REQUEST: // 40 SRS_REQUEST: (field defined for -,format0_1,-,format1_1,-,-,-,format2_3) - nr_pdci_info_extracted->srs_request = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->srs_request=%x\n",nr_pdci_info_extracted->srs_request); - break; - - case TPC_CMD: // 41 TPC_CMD: (field defined for -,-,-,-,-,-,-,format2_3) - nr_pdci_info_extracted->tpc_cmd = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->tpc_cmd=%x\n",nr_pdci_info_extracted->tpc_cmd); - break; - - case CSI_REQUEST: // 42 CSI_REQUEST: (field defined for -,format0_1,-,-,-,-,-,-) - nr_pdci_info_extracted->csi_request = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->csi_request=%x\n",nr_pdci_info_extracted->csi_request); - break; - - case CBGTI: // 43 CBGTI: (field defined for -,format0_1,-,format1_1,-,-,-,-) - // 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH - nr_pdci_info_extracted->cbgti = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->cbgti=%x\n",nr_pdci_info_extracted->cbgti); - break; - - case CBGFI: // 44 CBGFI: (field defined for -,-,-,format1_1,-,-,-,-) - // 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator - nr_pdci_info_extracted->cbgfi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->cbgfi=%x\n",nr_pdci_info_extracted->cbgfi); - break; - - case PTRS_DMRS: // 45 PTRS_DMRS: (field defined for -,format0_1,-,-,-,-,-,-) - nr_pdci_info_extracted->ptrs_dmrs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->ptrs_dmrs=%x\n",nr_pdci_info_extracted->ptrs_dmrs); - break; - - case BETA_OFFSET_IND: // 46 BETA_OFFSET_IND: (field defined for -,format0_1,-,-,-,-,-,-) - nr_pdci_info_extracted->beta_offset_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->beta_offset_ind=%x\n",nr_pdci_info_extracted->beta_offset_ind); - break; - - case DMRS_SEQ_INI: // 47 DMRS_SEQ_INI: (field defined for -,format0_1,-,format1_1,-,-,-,-) - // 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise - nr_pdci_info_extracted->dmrs_seq_ini = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->dmrs_seq_ini=%x\n",nr_pdci_info_extracted->dmrs_seq_ini); - break; - - case UL_SCH_IND: // 48 UL_SCH_IND: (field defined for -,format0_1,-,-,-,-,-,-) - // value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH - nr_pdci_info_extracted->ul_sch_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->dmrs_seq_ini=%x\n",nr_pdci_info_extracted->ul_sch_ind); - break; - - case PADDING_NR_DCI: // 49 PADDING_NR_DCI: (field defined for format0_0,-,format1_0,-,-,-,-,-) - // (Note 2) If DCI format 0_0 is monitored in common search space - nr_pdci_info_extracted->padding_nr_dci = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->padding=%x\n",nr_pdci_info_extracted->padding_nr_dci); - break; - - case SUL_IND_0_0: // 50 SUL_IND_0_0: (field defined for format0_0,-,-,-,-,-,-,-) - nr_pdci_info_extracted->sul_ind_0_0 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->sul_ind_0_0=%x\n",nr_pdci_info_extracted->sul_ind_0_0); - break; - - case RA_PREAMBLE_INDEX: // 51 RA_PREAMBLE_INDEX: (field defined for format0_0,-,-,-,-,-,-,-) - nr_pdci_info_extracted->ra_preamble_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->ra_preamble_index=%x\n",nr_pdci_info_extracted->ra_preamble_index); - break; - - case SUL_IND_1_0: // 52 SUL_IND_1_0: (field defined for -,-,format1_0,-,-,-,-,-) - nr_pdci_info_extracted->sul_ind_1_0 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->sul_ind_1_0=%x\n",nr_pdci_info_extracted->sul_ind_1_0); - break; - - case SS_PBCH_INDEX: // 53 SS_PBCH_INDEX: (field defined for -,-,format1_0,-,-,-,-,-) - nr_pdci_info_extracted->ss_pbch_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->ss_pbch_index=%x\n",nr_pdci_info_extracted->ss_pbch_index); - break; - - case PRACH_MASK_INDEX: // 54 PRACH_MASK_INDEX: (field defined for -,-,-,format1_0,-,-,-,-) - nr_pdci_info_extracted->prach_mask_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->prach_mask_index=%x\n",nr_pdci_info_extracted->prach_mask_index); - break; - - case RESERVED_NR_DCI: // 55 RESERVED_NR_DCI: (field defined for -,-,-,format1_0,-,-,-,-) - nr_pdci_info_extracted->reserved_nr_dci = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field); - //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format])); - LOG_DCI_D("nr_pdci_info_extracted->reserved_nr_dci=%x\n",nr_pdci_info_extracted->reserved_nr_dci); - break; - } - } - } - - LOG_DCI_D("Ending function nr_extract_dci_info()\n"); - return(1); -} - -#endif - -#ifdef NR_PDCCH_DCI_TOOLS - -int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, - uint8_t eNB_id, - int frame, - uint8_t nr_tti_rx, - uint64_t dci_pdu[2], - uint16_t rnti, - uint8_t dci_length, - NR_DCI_format_t dci_format, - NR_DL_FRAME_PARMS *frame_parms, - PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], - uint16_t n_RB_ULBWP, - uint16_t n_RB_DLBWP, - uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES], - fapi_nr_dci_pdu_rel15_t *nr_dci_info_extracted) { - /* - * Note only format0_0 and format1_0 are implemented - */ - uint8_t frame_type=frame_parms->frame_type; - uint8_t status=0; - LOG_DCI_PARM("dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",dci_format,rnti,dci_length,dci_pdu[0], - dci_pdu[1]); - memset(nr_dci_info_extracted,0,sizeof(*nr_dci_info_extracted)); - LOG_DCI_PARM("Entering function nr_extract_dci_info(dci_format=%d) \n",dci_format); - status = nr_extract_dci_info(ue, - eNB_id, - frame_type, - dci_length, - rnti, - dci_pdu, - nr_dci_info_extracted,//&nr_dci_info_extracted, - dci_fields_sizes, - dci_format, - nr_tti_rx, - n_RB_ULBWP, - n_RB_DLBWP, - crc_scrambled_values); - - if(status == 0) { - LOG_DCI_PARM("bad DCI %d !!! \n",dci_format); - return(-1); - } - - LOG_DCI_PARM("Ending function nr_extract_dci_info()\n"); - //fill - return(0); -} - -#endif uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t nr_tti_rx) { /* @@ -984,77 +71,14 @@ uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8 uint8_t ret = 255; uint8_t subframe = nr_tti_rx>>((int)(log2 (frame_parms->ttis_per_subframe))); + AssertFatal(1==0,"Not ready for this ...\n"); if (frame_parms->frame_type == FDD) { ret = (((frame<<1)+nr_tti_rx)&7); } else { - switch (frame_parms->tdd_config) { - case 1: - if ((subframe==2) || - (subframe==3) || - (subframe==7) || - (subframe==8)) - switch (subframe) { - case 2: - case 3: - ret = (subframe-2); - break; - case 7: - case 8: - ret = (subframe-5); - break; - - default: - LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config); - ret = (255); - break; - } - - break; - - case 2: - if ((subframe!=2) && (subframe!=7)) { - LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config); - //mac_xface->macphy_exit("subframe2_harq_pid, Illegal subframe"); - ret = (255); - } - - ret = (subframe/7); - break; - - case 3: - if ((subframe<2) || (subframe>4)) { - LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config); - ret = (255); - } - - ret = (subframe-2); - break; - - case 4: - if ((subframe<2) || (subframe>3)) { - LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config); - ret = (255); - } - - ret = (subframe-2); - break; - - case 5: - if (subframe!=2) { - LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config); - ret = (255); - } - - ret = (subframe-2); - break; - - default: - LOG_E(PHY,"subframe2_harq_pid, Unsupported TDD mode %d\n",frame_parms->tdd_config); - ret = (255); - } } + if (ret == 255) { LOG_E(PHY, "invalid harq_pid(%d) at SFN/SF = %d/%d\n", ret, frame, subframe); //mac_xface->macphy_exit("invalid harq_pid"); @@ -1063,48 +87,14 @@ uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8 return ret; } - uint8_t nr_pdcch_alloc2ul_subframe(NR_DL_FRAME_PARMS *frame_parms,uint8_t n) { - uint8_t ul_subframe = 255; - if ((frame_parms->frame_type == TDD) && - (frame_parms->tdd_config == 1) && - ((n==1)||(n==6))) // tdd_config 0,1 SF 1,5 - ul_subframe = ((n+6)%10); - else if ((frame_parms->frame_type == TDD) && - (frame_parms->tdd_config == 6) && - ((n==0)||(n==1)||(n==5)||(n==6))) - ul_subframe = ((n+7)%10); - else if ((frame_parms->frame_type == TDD) && - (frame_parms->tdd_config == 6) && - (n==9)) // tdd_config 6 SF 9 - ul_subframe = ((n+5)%10); - else - ul_subframe = ((n+4)%10); + AssertFatal(1==0,"Not ready for this\n"); - LOG_D(PHY, "subframe %d: PUSCH subframe = %d\n", n, ul_subframe); - return ul_subframe; } uint32_t nr_pdcch_alloc2ul_frame(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t n) { - uint32_t ul_frame = 255; - if ((frame_parms->frame_type == TDD) && - (frame_parms->tdd_config == 1) && - ((n==1)||(n==6))) // tdd_config 0,1 SF 1,5 - ul_frame = (frame + (n==1 ? 0 : 1)); - else if ((frame_parms->frame_type == TDD) && - (frame_parms->tdd_config == 6) && - ((n==0)||(n==1)||(n==5)||(n==6))) - ul_frame = (frame + (n>=5 ? 1 : 0)); - else if ((frame_parms->frame_type == TDD) && - (frame_parms->tdd_config == 6) && - (n==9)) // tdd_config 6 SF 9 - ul_frame = (frame+1); - else - ul_frame = (frame+(n>=6 ? 1 : 0)); + AssertFatal(1==0,"Not ready for this\n"); - LOG_D(PHY, "frame %d subframe %d: PUSCH frame = %d\n", frame, n, ul_frame); - return ul_frame; } - diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index b3a95e313e..00167507ce 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -41,12 +41,11 @@ #include "SCHED_NR_UE/defs.h" #include "SIMULATION/TOOLS/sim.h" #include "executables/nr-uesoftmodem.h" -#include "PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h" -#include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" +#include "PHY/CODING/nrLDPC_extern.h" //#define DEBUG_DLSCH_DECODING //#define ENABLE_PHY_PAYLOAD_DEBUG 1 -#define OAI_LDPC_MAX_NUM_LLR 27000//26112 // NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX +//#define OAI_LDPC_MAX_NUM_LLR 27000//26112 // NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX static uint64_t nb_total_decod =0; static uint64_t nb_error_decod =0; @@ -57,31 +56,46 @@ int nbDlProcessing =0; //extern double cpuf; -void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr) +void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr,uint8_t N_RB_DL) { int i,r; + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated NR_UE_DLSCH_t *dlsch=*dlschptr; + if (dlsch) { + if (N_RB_DL != 273) { + a_segments = a_segments*N_RB_DL; + a_segments = a_segments/273; + } + + uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment + for (i=0; iMdlharq; i++) { if (dlsch->harq_processes[i]) { if (dlsch->harq_processes[i]->b) { - free16(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES); + free16(dlsch->harq_processes[i]->b,dlsch_bytes); dlsch->harq_processes[i]->b = NULL; } - for (r=0; rharq_processes[i]->c[r],1056); dlsch->harq_processes[i]->c[r] = NULL; } - for (r=0; rharq_processes[i]->d[r]) { - free16(dlsch->harq_processes[i]->d[r],(3*8448)*sizeof(short)); + free16(dlsch->harq_processes[i]->d[r],(5*8448)*sizeof(short)); dlsch->harq_processes[i]->d[r] = NULL; } - for (r=0; r<(MAX_NUM_NR_DLSCH_SEGMENTS); r++) { + for (r=0; rharq_processes[i]->w[r]) { + free16(dlsch->harq_processes[i]->w[r],(5*8448)*sizeof(short)); + dlsch->harq_processes[i]->w[r] = NULL; + } + + for (r=0; rharq_processes[i]->p_nrLDPC_procBuf[r]){ nrLDPC_free_mem(dlsch->harq_processes[i]->p_nrLDPC_procBuf[r]); dlsch->harq_processes[i]->p_nrLDPC_procBuf[r] = NULL; @@ -98,31 +112,20 @@ void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr) } } -NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_ldpc_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag) +NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_ldpc_iterations,uint16_t N_RB_DL, uint8_t abstraction_flag) { NR_UE_DLSCH_t *dlsch; uint8_t exit_flag = 0,i,r; - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated - switch (N_RB_DL) { - case 6: - bw_scaling =16; - break; + if (N_RB_DL != 273) { + a_segments = a_segments*N_RB_DL; + a_segments = (a_segments/273)+1; + } - case 25: - bw_scaling =4; - break; - - case 50: - bw_scaling =2; - break; - - default: - bw_scaling =1; - break; - } + uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment dlsch = (NR_UE_DLSCH_t *)malloc16(sizeof(NR_UE_DLSCH_t)); @@ -141,15 +144,15 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint if (dlsch->harq_processes[i]) { memset(dlsch->harq_processes[i],0,sizeof(NR_DL_UE_HARQ_t)); dlsch->harq_processes[i]->first_tx=1; - dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling); + dlsch->harq_processes[i]->b = (uint8_t*)malloc16(dlsch_bytes); if (dlsch->harq_processes[i]->b) - memset(dlsch->harq_processes[i]->b,0,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling); + memset(dlsch->harq_processes[i]->b,0,dlsch_bytes); else exit_flag=3; if (abstraction_flag == 0) { - for (r=0; rharq_processes[i]->p_nrLDPC_procBuf[r] = nrLDPC_init_mem(); dlsch->harq_processes[i]->c[r] = (uint8_t*)malloc16(1056); @@ -158,10 +161,17 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint else exit_flag=2; - dlsch->harq_processes[i]->d[r] = (short*)malloc16((3*8448)*sizeof(short)); + dlsch->harq_processes[i]->d[r] = (short*)malloc16((5*8448)*sizeof(short)); if (dlsch->harq_processes[i]->d[r]) - memset(dlsch->harq_processes[i]->d[r],0,(3*8448)*sizeof(short)); + memset(dlsch->harq_processes[i]->d[r],0,(5*8448)*sizeof(short)); + else + exit_flag=2; + + dlsch->harq_processes[i]->w[r] = (short*)malloc16((5*8448)*sizeof(short)); + + if (dlsch->harq_processes[i]->w[r]) + memset(dlsch->harq_processes[i]->w[r],0,(5*8448)*sizeof(short)); else exit_flag=2; } @@ -176,7 +186,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint } printf("new_ue_dlsch with size %zu: exit_flag = %u\n",sizeof(NR_DL_UE_HARQ_t), exit_flag); - free_nr_ue_dlsch(&dlsch); + free_nr_ue_dlsch(&dlsch,N_RB_DL); return(NULL); } @@ -228,7 +238,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, int32_t no_iteration_ldpc, length_dec; uint32_t r,r_offset=0,Kr=8424,Kr_bytes,K_bytes_F,err_flag=0; uint8_t crc_type; - int8_t llrProcBuf[OAI_LDPC_MAX_NUM_LLR] __attribute__ ((aligned(32))); + int8_t llrProcBuf[NR_LDPC_MAX_NUM_LLR] __attribute__ ((aligned(32))); t_nrLDPC_dec_params decParams; t_nrLDPC_dec_params* p_decParams = &decParams; t_nrLDPC_time_stats procTime; @@ -239,20 +249,24 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, return(dlsch->max_ldpc_iterations + 1); } t_nrLDPC_procBuf** p_nrLDPC_procBuf = harq_process->p_nrLDPC_procBuf; + int16_t z [68*384]; int8_t l [68*384]; //__m128i l; //int16_t inv_d [68*384]; uint8_t kc; - uint8_t Ilbrm = 1; - uint32_t Tbslbrm; //= 950984; - uint16_t nb_rb; //= 30; - double Coderate; //= 0.0; - //nfapi_nr_config_request_t *cfg = &phy_vars_ue->nrUE_config; - //uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value; - uint8_t nb_re_dmrs = 6; //(dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; - uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value; + uint8_t Ilbrm = 0; + + uint32_t Tbslbrm;// = 950984; + uint16_t nb_rb;// = 30; + double Coderate;// = 0.0; + + uint8_t dmrs_Type = harq_process->dmrsConfigType; + AssertFatal(dmrs_Type == 1 || dmrs_Type == 2,"Illegal dmrs_type %d\n",dmrs_Type); + uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4; + uint16_t dmrs_length = get_num_dmrs(harq_process->dlDmrsSymbPos); + AssertFatal(dmrs_length == 1 || dmrs_length == 2,"Illegal dmrs_length %d\n",dmrs_length); uint32_t i,j; @@ -304,16 +318,16 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, harq_process->Nl); A = harq_process->TBS; ret = dlsch->max_ldpc_iterations + 1; dlsch->last_iteration_cnt = ret; - harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, harq_process->Qm,harq_process->Nl); + harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, harq_process->Qm,harq_process->Nl); G = harq_process->G; - LOG_I(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); + LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d nb_re_dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, nb_re_dmrs,harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); if ((harq_process->R)<1024) Coderate = (float) (harq_process->R) /(float) 1024; @@ -388,20 +402,15 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, err_flag = 0; r_offset = 0; - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated - switch (frame_parms->N_RB_DL) { - case 106: - bw_scaling =2; - break; + if (nb_rb != 273) { + a_segments = a_segments*nb_rb; + a_segments = a_segments/273; + } - default: - bw_scaling =1; - break; - } - - if (harq_process->C > MAX_NUM_NR_DLSCH_SEGMENTS/bw_scaling) { - LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,MAX_NUM_NR_DLSCH_SEGMENTS/bw_scaling); + if (harq_process->C > a_segments) { + LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,a_segments); return((1+dlsch->max_ldpc_iterations)); } @@ -427,6 +436,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DEINTERLEAVING, VCD_FUNCTION_IN); + nr_deinterleaving_ldpc(E, harq_process->Qm, harq_process->w[r], // [hna] w is e @@ -445,9 +455,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, start_meas(dlsch_rate_unmatching_stats); #endif -#ifdef DEBUG_DLSCH_DECODING - LOG_D(PHY,"HARQ_PID %d Rate Matching Segment %d (coded bits %d,unpunctured/repeated bits %d, TBS %d, mod_order %d, nb_rb %d, Nl %d, rv %d, round %d)...\n", - harq_pid,r, G, + LOG_D(PHY,"HARQ_PID %d Rate Matching Segment %d (coded bits %d,E %d, F %d,unpunctured/repeated bits %d, TBS %d, mod_order %d, nb_rb %d, Nl %d, rv %d, round %d)...\n", + harq_pid,r, G,E,harq_process->F, Kr*3, harq_process->TBS, harq_process->Qm, @@ -455,7 +464,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, harq_process->Nl, harq_process->rvidx, harq_process->round); -#endif + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_RATE_MATCHING, VCD_FUNCTION_IN); @@ -464,6 +473,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, else Tbslbrm = nr_compute_tbslbrm(harq_process->mcs_table,nb_rb,4,harq_process->C); + if (nr_rate_matching_ldpc_rx(Ilbrm, Tbslbrm, p_decParams->BG, @@ -473,7 +483,9 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, harq_process->C, harq_process->rvidx, (harq_process->round==0)?1:0, - E)==-1) { + E, + harq_process->F, + Kr-harq_process->F-2*(p_decParams->Z))==-1) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_RATE_MATCHING, VCD_FUNCTION_OUT); #if UE_TIMING_TRACE stop_meas(dlsch_rate_unmatching_stats); @@ -487,6 +499,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, #endif } + //for (int i =0; i<16; i++) // printf("rx output ratematching d[%d]= %d r_offset %d\n", i,harq_process->d[r][i], r_offset); @@ -495,12 +508,12 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, #ifdef DEBUG_DLSCH_DECODING if (r==0) { write_output("decoder_llr.m","decllr",dlsch_llr,G,1,0); - write_output("decoder_in.m","dec",&harq_process->d[0][0],(3*8*Kr_bytes)+12,1,0); + write_output("decoder_in.m","dec",&harq_process->d[0][0],E,1,0); } printf("decoder input(segment %u) :",r); int i; - for (i=0;i<(3*8*Kr_bytes)+12;i++) + for (i=0;id[r][i]); printf("\n"); #endif @@ -531,18 +544,21 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, //LOG_E(PHY,"AbsSubframe %d.%d Start LDPC segment %d/%d A %d ",frame%1024,nr_tti_rx,r,harq_process->C-1, A); - printf("harq process dr iteration %d\n", p_decParams->numMaxIter); + //printf("harq process dr iteration %d\n", p_decParams->numMaxIter); memset(pv,0,2*harq_process->Z*sizeof(int16_t)); //memset(pl,0,2*p_decParams->Z*sizeof(int8_t)); memset((pv+K_bytes_F),127,harq_process->F*sizeof(int16_t)); + for (i=((2*p_decParams->Z)>>3), j = 0; i < K_bytes_F; i++, j++) { pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } - - for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) + // Kbytes_F = Kr_bytes - F>>3 + j+=(harq_process->F>>3); + // for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) + for (i=Kr_bytes; i < ((kc*p_decParams->Z)>>3); i++,j++) { pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } @@ -552,6 +568,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, pl[j] = _mm_packs_epi16(pv[i],pv[i+1]); } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_LDPC, VCD_FUNCTION_IN); no_iteration_ldpc = nrLDPC_decoder(p_decParams, @@ -559,21 +576,21 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, llrProcBuf, p_nrLDPC_procBuf[r], p_procTime); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_LDPC, VCD_FUNCTION_OUT); // Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) { - printf("\x1B[34m" "Segment %u CRC OK\n\033[0m",r); + LOG_D(PHY,"Segment %u CRC OK\n\033[0m",r); //Temporary hack no_iteration_ldpc = dlsch->max_ldpc_iterations; ret = no_iteration_ldpc; } else { - printf("\x1B[33m" "Segment %d CRC NOK\n",r); + LOG_D(PHY,"CRC NOK\n\033[0m"); ret = 1 + dlsch->max_ldpc_iterations; } + nb_total_decod++; if (no_iteration_ldpc > dlsch->max_ldpc_iterations){ nb_error_decod++; @@ -615,7 +632,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, if ((err_flag == 0) && (ret>=(1+dlsch->max_ldpc_iterations))) {// a Code segment is in error so break; - LOG_I(PHY,"AbsSubframe %d.%d CRC failed, segment %d/%d \n",frame%1024,nr_tti_rx,r,harq_process->C-1); + LOG_D(PHY,"AbsSubframe %d.%d CRC failed, segment %d/%d \n",frame%1024,nr_tti_rx,r,harq_process->C-1); err_flag = 1; } } @@ -630,7 +647,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, if (err_flag == 1) { //#if UE_DEBUG_TRACE - LOG_I(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n", + LOG_D(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n", phy_vars_ue->Mod_id, frame, nr_tti_rx, harq_pid,harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs,Kr,r,harq_process->round); //#endif harq_process->harq_ack.ack = 0; @@ -647,15 +664,15 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, if(is_crnti) { - LOG_I(PHY,"[UE %d] DLSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", + LOG_D(PHY,"[UE %d] DLSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,dlsch->Mdlharq,harq_process->TBS); } return((1 + dlsch->max_ldpc_iterations)); } else { //#if UE_DEBUG_TRACE - LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d harq_process->round %d\n", - phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb, harq_process->round); + LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d harq_process->round %d\n", + phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb, harq_process->round); //#endif harq_process->status = SCH_IDLE; @@ -664,12 +681,12 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, harq_process->harq_ack.harq_id = harq_pid; harq_process->harq_ack.send_harq_status = 1; - //LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d)\n", + //LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d)\n", // phy_vars_ue->Mod_id, frame, subframe, harq_pid, harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs); if(is_crnti) { - LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); + LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); } //LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for subframe %d (pid %d, round %d)\n",phy_vars_ue->Mod_id,subframe,harq_pid,harq_process->round); @@ -691,8 +708,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, for (r=0; rC; r++) { memcpy(harq_process->b+offset, - harq_process->c[r], - Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0)); + harq_process->c[r], + Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0)); offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0)); #ifdef DEBUG_DLSCH_DECODING @@ -752,7 +769,6 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, uint32_t A,E; uint32_t G; uint32_t ret,offset; - //short dummy_w[MAX_NUM_DLSCH_SEGMENTS][3*(8448+64)]; uint32_t r,r_offset=0,Kr=8424,Kr_bytes,err_flag=0,K_bytes_F; uint8_t crc_type; //UE_rxtx_proc_t *proc = &phy_vars_ue->proc; @@ -765,7 +781,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, t_nrLDPC_dec_params* p_decParams = &decParams; t_nrLDPC_time_stats procTime; t_nrLDPC_time_stats* p_procTime =&procTime ; - int8_t llrProcBuf[OAI_LDPC_MAX_NUM_LLR] __attribute__ ((aligned(32))); + int8_t llrProcBuf[NR_LDPC_MAX_NUM_LLR] __attribute__ ((aligned(32))); if (!harq_process) { printf("dlsch_decoding.c: NULL harq_process pointer\n"); return(dlsch->max_ldpc_iterations); @@ -782,10 +798,12 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, uint32_t Tbslbrm = 950984; uint16_t nb_rb = 30; double Coderate = 0.0; + uint8_t dmrs_type = harq_process->dmrsConfigType; //nfapi_nr_config_request_t *cfg = &phy_vars_ue->nrUE_config; //uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value; - uint8_t nb_re_dmrs = 6; //(dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; - uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value; + + uint8_t nb_re_dmrs = (dmrs_type==1)?6:4; + uint16_t length_dmrs = get_num_dmrs(harq_process->dlDmrsSymbPos); uint32_t i,j; // int nbDlProcessing =0; @@ -841,14 +859,14 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, A = harq_process->TBS; - ret = dlsch->max_ldpc_iterations; + ret = dlsch->max_ldpc_iterations + 1; + dlsch->last_iteration_cnt = ret; harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, harq_process->Qm,harq_process->Nl); G = harq_process->G; - LOG_D(PHY,"DLSCH Decoding main, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); - + LOG_D(PHY,"DLSCH Decoding main, harq_pid %d TBS %d G %d, nb_re_dmrs %d, length_dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, nb_re_dmrs, length_dmrs, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); proc->decoder_main_available = 1; proc->decoder_thread_available = 0; @@ -910,9 +928,10 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, &harq_process->F, p_decParams->BG); - p_decParams->Z = harq_process->Z; } + + p_decParams->Z = harq_process->Z; //printf("coderate %f kc %d \n", Coderate, kc); p_decParams->numMaxIter = dlsch->max_ldpc_iterations; @@ -921,20 +940,15 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, err_flag = 0; r_offset = 0; - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated - switch (frame_parms->N_RB_DL) { - case 106: - bw_scaling =2; - break; + if (nb_rb != 273) { + a_segments = a_segments*nb_rb; + a_segments = a_segments/273; + } - default: - bw_scaling =1; - break; - } - - if (harq_process->C > MAX_NUM_DLSCH_SEGMENTS/bw_scaling) { - LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,MAX_NUM_DLSCH_SEGMENTS/bw_scaling); + if (harq_process->C > a_segments) { + LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,a_segments); return((1+dlsch->max_ldpc_iterations)); } #ifdef DEBUG_DLSCH_DECODING @@ -1050,7 +1064,9 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, harq_process->C, harq_process->rvidx, (harq_process->round==0)?1:0, - E)==-1) { + E, + harq_process->F, + Kr-harq_process->F-2*(p_decParams->Z))==-1) { #if UE_TIMING_TRACE stop_meas(dlsch_rate_unmatching_stats); #endif @@ -1109,7 +1125,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, if (err_flag == 0) { /* - LOG_I(PHY, "LDPC algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n", + LOG_D(PHY, "LDPC algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n", Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS, harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations); */ @@ -1133,11 +1149,13 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } - for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) + j+=(harq_process->F>>3); + // for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) + for (i=Kr_bytes; i < ((kc*p_decParams->Z)>>3); i++,j++) { pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } - + for (i=0, j=0; j < ((kc*p_decParams->Z)>>4); i+=2, j++) { pl[j] = _mm_packs_epi16(pv[i],pv[i+1]); @@ -1222,7 +1240,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, if (err_flag == 1) { #if UE_DEBUG_TRACE - LOG_I(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n", + LOG_D(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n", phy_vars_ue->Mod_id, frame, nr_tti_rx, harq_pid,harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs,Kr,r,harq_process->round); #endif harq_process->harq_ack.ack = 0; @@ -1246,7 +1264,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, return((1+dlsch->max_ldpc_iterations)); } else { #if UE_DEBUG_TRACE - LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d\n", + LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d\n", phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb); #endif @@ -1336,7 +1354,7 @@ void nr_dlsch_decoding_process(void *arg) t_nrLDPC_dec_params* p_decParams = &decParams; t_nrLDPC_time_stats procTime; t_nrLDPC_time_stats* p_procTime =&procTime ; - int8_t llrProcBuf[OAI_LDPC_MAX_NUM_LLR] __attribute__ ((aligned(32))); + int8_t llrProcBuf[NR_LDPC_MAX_NUM_LLR] __attribute__ ((aligned(32))); t_nrLDPC_procBuf* p_nrLDPC_procBuf; int16_t z [68*384]; int8_t l [68*384]; @@ -1372,7 +1390,6 @@ void nr_dlsch_decoding_process(void *arg) uint32_t A,E; uint32_t G; uint32_t ret,offset; -// short dummy_w[MAX_NUM_DLSCH_SEGMENTS][3*(8448+64)]; uint32_t r,r_offset=0,Kr,Kr_bytes,err_flag=0,K_bytes_F; uint8_t crc_type; uint8_t C,Cprime; @@ -1425,7 +1442,7 @@ void nr_dlsch_decoding_process(void *arg) harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, harq_process->Qm,harq_process->Nl); G = harq_process->G; - LOG_I(PHY,"DLSCH Decoding process, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); + LOG_D(PHY,"DLSCH Decoding process, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); if ((harq_process->R)<1024) Coderate = (float) (harq_process->R) /(float) 1024; @@ -1465,7 +1482,7 @@ void nr_dlsch_decoding_process(void *arg) } harq_process->round =0; - if (harq_process->round == 0) { + // if (harq_process->round == 0) { // This is a new packet, so compute quantities regarding segmentation if (A > 3824) harq_process->B = A+24; @@ -1483,7 +1500,7 @@ void nr_dlsch_decoding_process(void *arg) p_decParams->Z = harq_process->Z; - } + // } //printf("round %d Z %d K %d BG %d\n", harq_process->round, p_decParams->Z, harq_process->K, p_decParams->BG); @@ -1501,20 +1518,15 @@ void nr_dlsch_decoding_process(void *arg) //r_offset = 0; /* - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_DLSCH_SEGMENTS; //number of segments to be allocated - switch (frame_parms->N_RB_DL) { - case 106: - bw_scaling =2; - break; + if (nb_rb != 273) { + a_segments = a_segments*nb_rb; + a_segments = a_segments/273; + } - default: - bw_scaling =1; - break; - } - - if (harq_process->C > MAX_NUM_DLSCH_SEGMENTS/bw_scaling) { - LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,MAX_NUM_DLSCH_SEGMENTS/bw_scaling); + if (harq_process->C > a_segments) { + LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,a_segments); return((1+dlsch->max_ldpc_iterations)); }*/ #ifdef DEBUG_DLSCH_DECODING @@ -1595,7 +1607,9 @@ void nr_dlsch_decoding_process(void *arg) harq_process->C, harq_process->rvidx, (harq_process->round==0)?1:0, - E)==-1) { + E, + harq_process->F, + Kr-harq_process->F-2*(p_decParams->Z))==-1) { #if UE_TIMING_TRACE stop_meas(dlsch_rate_unmatching_stats); #endif @@ -1644,7 +1658,7 @@ void nr_dlsch_decoding_process(void *arg) if (err_flag == 0) { /* - LOG_I(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n", + LOG_D(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n", Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS, harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations); */ @@ -1656,10 +1670,11 @@ void nr_dlsch_decoding_process(void *arg) start_meas(dlsch_turbo_decoding_stats); #endif // LOG_D(PHY,"AbsSubframe %d.%d Start turbo segment %d/%d \n",frame%1024,subframe,r,harq_process->C-1); - - /*for (int cnt =0; cnt < (kc-2)*p_decParams->Z; cnt++){ +/* + for (int cnt =0; cnt < (kc-2)*p_decParams->Z; cnt++){ inv_d[cnt] = (1)*harq_process->d[r][cnt]; - }*/ + } +*/ memset(pv,0,2*p_decParams->Z*sizeof(int16_t)); //memset(pl,0,2*p_decParams->Z*sizeof(int8_t)); @@ -1670,9 +1685,11 @@ void nr_dlsch_decoding_process(void *arg) pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } - for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) + j+=(harq_process->F>>3); + // for (i=Kr_bytes,j=K_bytes_F-((2*p_decParams->Z)>>3); i < ((kc*p_decParams->Z)>>3); i++, j++) + for (i=Kr_bytes; i < ((kc*p_decParams->Z)>>3); i++,j++) { - pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); + pv[i]= _mm_loadu_si128((__m128i*)(&harq_process->d[r][8*j])); } for (i=0, j=0; j < ((kc*p_decParams->Z)>>4); i+=2, j++) @@ -1688,16 +1705,16 @@ void nr_dlsch_decoding_process(void *arg) // Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) { - printf("Segment %u CRC OK\n",r); + LOG_D(PHY,"Segment %u CRC OK\n",r); ret = 2; } else { - printf("Segment %d CRC NOK\n",r); + LOG_D(PHY,"Segment %u CRC NOK\n",r); ret = 1+dlsch->max_ldpc_iterations; } if (no_iteration_ldpc > 10) - printf("Error number of iteration LPDC %d\n", no_iteration_ldpc); + LOG_D(PHY,"Error number of iteration LPDC %d\n", no_iteration_ldpc); //else //printf("OK number of iteration LPDC %d\n", no_iteration_ldpc); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index 1089c08542..c704efdb1f 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -101,16 +101,16 @@ static void nr_dlsch_layer_demapping(int16_t **llr_cw, int16_t **llr_layers); int nr_rx_pdsch(PHY_VARS_NR_UE *ue, - PDSCH_t type, - unsigned char eNB_id, - unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference - uint32_t frame, - uint8_t nr_tti_rx, - unsigned char symbol, - unsigned char first_symbol_flag, - RX_type_t rx_type, - unsigned char i_mod, - unsigned char harq_pid) + PDSCH_t type, + unsigned char eNB_id, + unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference + uint32_t frame, + uint8_t nr_tti_rx, + unsigned char symbol, + unsigned char first_symbol_flag, + RX_type_t rx_type, + unsigned char i_mod, + unsigned char harq_pid) { NR_UE_COMMON *common_vars = &ue->common_vars; @@ -151,7 +151,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, //int16_t *pllr_symbol_cw1_deint; uint32_t llr_offset_symbol; //uint16_t bundle_L = 2; - uint8_t l0 =2, pilots=0; + uint8_t pilots=0; uint16_t n_tx=1, n_rx=1; int32_t median[16]; uint32_t len; @@ -234,7 +234,6 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, start_rb = dlsch0_harq->start_rb; nb_rb_pdsch = dlsch0_harq->nb_rb; - l0 = dlsch0_harq->start_symbol; DevAssert(dlsch0_harq); round = dlsch0_harq->round; @@ -286,9 +285,9 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, printf("Demod dlsch0_harq->pmi_alloc %d\n", dlsch0_harq->pmi_alloc); #endif - pilots = (symbol==l0) ? 1 : 0; + pilots = ((1<dlDmrsSymbPos)>0 ? 1 : 0; - if (frame_parms->nb_antenna_ports_eNB>1 && beamforming_mode==0) { + if (frame_parms->nb_antenna_ports_gNB>1 && beamforming_mode==0) { #ifdef DEBUG_DLSCH_MOD LOG_I(PHY,"dlsch: using pmi %x (%p)\n",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc),dlsch[0]); #endif @@ -297,19 +296,19 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); #endif nb_rb = nr_dlsch_extract_rbs_dual(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF, - pdsch_vars[eNB_id]->dl_ch_estimates, - pdsch_vars[eNB_id]->rxdataF_ext, - pdsch_vars[eNB_id]->dl_ch_estimates_ext, - dlsch0_harq->pmi_alloc, - pdsch_vars[eNB_id]->pmi_ext, - symbol, - pilots, - start_rb, - nb_rb_pdsch, - nr_tti_rx, - ue->high_speed_flag, - frame_parms, - dlsch0_harq->mimo_mode); + pdsch_vars[eNB_id]->dl_ch_estimates, + pdsch_vars[eNB_id]->rxdataF_ext, + pdsch_vars[eNB_id]->dl_ch_estimates_ext, + dlsch0_harq->pmi_alloc, + pdsch_vars[eNB_id]->pmi_ext, + symbol, + pilots, + start_rb, + nb_rb_pdsch, + nr_tti_rx, + ue->high_speed_flag, + frame_parms, + dlsch0_harq->mimo_mode); #ifdef DEBUG_DLSCH_MOD printf("dlsch: using pmi %lx, pmi_ext ",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc)); for (rb=0;rbmimo_mode); } - } else if (beamforming_mode==0) { //else if nb_antennas_ports_eNB==1 && beamforming_mode == 0 + } else if (beamforming_mode==0) { //else if nb_antennas_ports_gNB==1 && beamforming_mode == 0 //printf("start nr dlsch extract nr_tti_rx %d thread id %d \n", nr_tti_rx, ue->current_thread_id[nr_tti_rx]); nb_rb = nr_dlsch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF, - pdsch_vars[eNB_id]->dl_ch_estimates, - pdsch_vars[eNB_id]->rxdataF_ext, - pdsch_vars[eNB_id]->dl_ch_estimates_ext, - dlsch0_harq->pmi_alloc, - pdsch_vars[eNB_id]->pmi_ext, - symbol, - pilots, - start_rb, - nb_rb_pdsch, - nr_tti_rx, - ue->high_speed_flag, - frame_parms); + pdsch_vars[eNB_id]->dl_ch_estimates, + pdsch_vars[eNB_id]->rxdataF_ext, + pdsch_vars[eNB_id]->dl_ch_estimates_ext, + dlsch0_harq->pmi_alloc, + pdsch_vars[eNB_id]->pmi_ext, + symbol, + pilots, + start_rb, + nb_rb_pdsch, + nr_tti_rx, + ue->high_speed_flag, + frame_parms); } /*else if(beamforming_mode>7) { LOG_W(PHY,"dlsch_demodulation: beamforming mode not supported yet.\n"); @@ -375,31 +374,31 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, return(-1); } - len = (symbol==l0)? (nb_rb*6):(nb_rb*12); - + len = (pilots==1)? (nb_rb*6):(nb_rb*12); + #if UE_TIMING_TRACE - stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); + stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); #if DISABLE_LOG_X - printf("[AbsSFN %u.%d] Slot%d Symbol %d Flag %d type %d: Pilot/Data extraction %5.2f \n", - frame,nr_tti_rx,slot,symbol,ue->high_speed_flag,type,ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot].p_time/(cpuf*1000.0)); + printf("[AbsSFN %u.%d] Slot%d Symbol %d Flag %d type %d: Pilot/Data extraction %5.2f \n", + frame,nr_tti_rx,slot,symbol,ue->high_speed_flag,type,ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot].p_time/(cpuf*1000.0)); #else - LOG_I(PHY, "[AbsSFN %u.%d] Slot%d Symbol %d Flag %d type %d: Pilot/Data extraction %5.2f \n", - frame,nr_tti_rx,slot,symbol,ue->high_speed_flag,type,ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot].p_time/(cpuf*1000.0)); + LOG_I(PHY, "[AbsSFN %u.%d] Slot%d Symbol %d Flag %d type %d: Pilot/Data extraction %5.2f \n", + frame,nr_tti_rx,slot,symbol,ue->high_speed_flag,type,ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot].p_time/(cpuf*1000.0)); #endif #endif - + #if UE_TIMING_TRACE - start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); + start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); #endif - n_tx = frame_parms->nb_antenna_ports_eNB; + n_tx = frame_parms->nb_antenna_ports_gNB; n_rx = frame_parms->nb_antennas_rx; - + nr_dlsch_scale_channel(pdsch_vars[eNB_id]->dl_ch_estimates_ext, - frame_parms, - dlsch, - symbol, - pilots, - nb_rb); + frame_parms, + dlsch, + symbol, + pilots, + nb_rb); #if UE_TIMING_TRACE stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); @@ -417,17 +416,17 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, if (beamforming_mode==0){ if (dlsch0_harq->mimo_modedl_ch_estimates_ext, - frame_parms, - avg, - symbol, - len, - nb_rb); + frame_parms, + avg, + symbol, + len, + nb_rb); avgs = 0; - for (aatx=0;aatxnb_antenna_ports_eNB;aatx++) + for (aatx=0;aatxnb_antenna_ports_gNB;aatx++) for (aarx=0;aarxnb_antennas_rx;aarx++) avgs = cmax(avgs,avg[(aatx<<1)+aarx]); - pdsch_vars[eNB_id]->log2_maxh = (log2_approx(avgs)/2)+1; + pdsch_vars[eNB_id]->log2_maxh = (log2_approx(avgs)/2)+3; } else if (dlsch0_harq->mimo_mode == NR_DUALSTREAM) { @@ -450,14 +449,14 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, } } -#ifdef UE_DEBUG_TRACE - LOG_I(PHY,"[DLSCH] AbsSubframe %d.%d log2_maxh = %d [log2_maxh0 %d log2_maxh1 %d] (%d,%d)\n", - frame%1024,nr_tti_rx, pdsch_vars[eNB_id]->log2_maxh, - pdsch_vars[eNB_id]->log2_maxh0, - pdsch_vars[eNB_id]->log2_maxh1, - avg[0],avgs); + //#ifdef UE_DEBUG_TRACE + LOG_D(PHY,"[DLSCH] AbsSubframe %d.%d log2_maxh = %d [log2_maxh0 %d log2_maxh1 %d] (%d,%d)\n", + frame%1024,nr_tti_rx, pdsch_vars[eNB_id]->log2_maxh, + pdsch_vars[eNB_id]->log2_maxh0, + pdsch_vars[eNB_id]->log2_maxh1, + avg[0],avgs); //LOG_D(PHY,"[DLSCH] mimo_mode = %d\n", dlsch0_harq->mimo_mode); -#endif + //#endif //wait until pdcch is decoded //proc->channel_level = 1; @@ -648,13 +647,14 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, #endif #if UE_TIMING_TRACE + start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]); #endif //printf("LLR dlsch0_harq->Qm %d rx_type %d cw0 %d cw1 %d symbol %d \n",dlsch0_harq->Qm,rx_type,codeword_TB0,codeword_TB1,symbol); // compute LLRs // -> // compute @pointer where llrs should filled for this ofdm-symbol - pdsch_vars[eNB_id]->llr_offset[l0-1] = 0; + if (first_symbol_flag==1) pdsch_vars[eNB_id]->llr_offset[symbol-1] = 0; llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1]; //pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0]; //pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1]; @@ -1148,7 +1148,7 @@ void nr_dlsch_channel_compensation(int **rxdataF_ext, __m128i mmtmpD0,mmtmpD1,mmtmpD2,mmtmpD3,QAM_amp128,QAM_amp128b; QAM_amp128b = _mm_setzero_si128(); - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) { + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { if (mod_order == 4) { QAM_amp128 = _mm_set1_epi16(QAM16_n1); // 2/sqrt(10) QAM_amp128b = _mm_setzero_si128(); @@ -1400,7 +1400,7 @@ void nr_dlsch_channel_compensation(int **rxdataF_ext, symbol_mod = (symbol>=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol; if ((symbol_mod == 0) || (symbol_mod == (4-frame_parms->Ncp))) { - if (frame_parms->nb_antenna_ports_eNB==1) { // 10 out of 12 so don't reduce size + if (frame_parms->nb_antenna_ports_gNB==1) { // 10 out of 12 so don't reduce size nb_rb=1+(5*nb_rb/6); } else { @@ -1408,7 +1408,7 @@ void nr_dlsch_channel_compensation(int **rxdataF_ext, } } - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) { + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { if (mod_order == 4) { QAM_amp128 = vmovq_n_s16(QAM16_n1); // 2/sqrt(10) QAM_amp128b = vmovq_n_s16(0); @@ -1789,11 +1789,11 @@ void nr_dlsch_channel_compensation_core(int **rxdataF_ext, void nr_dlsch_scale_channel(int **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t **dlsch_ue, - uint8_t symbol, - uint8_t pilots, - unsigned short nb_rb) + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_DLSCH_t **dlsch_ue, + uint8_t symbol, + uint8_t pilots, + unsigned short nb_rb) { #if defined(__x86_64__)||defined(__i386__) @@ -1809,14 +1809,14 @@ void nr_dlsch_scale_channel(int **dl_ch_estimates_ext, // Determine scaling amplitude based the symbol -ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rho_a)); + ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rho_a)); LOG_D(PHY,"Scaling PDSCH Chest in OFDM symbol %d by %d, pilots %d nb_rb %d NCP %d symbol %d\n",symbol,ch_amp,pilots,nb_rb,frame_parms->Ncp,symbol); // printf("Scaling PDSCH Chest in OFDM symbol %d by %d\n",symbol_mod,ch_amp); ch_amp128 = _mm_set1_epi16(ch_amp); // Q3.13 - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) { + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { for (aarx=0; aarxnb_antennas_rx; aarx++) { dl_ch128=(__m128i *)&dl_ch_estimates_ext[(aatx<<1)+aarx][symbol*nb_rb*12]; @@ -1849,11 +1849,11 @@ ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rh //compute average channel_level on each (TX,RX) antenna pair void nr_dlsch_channel_level(int **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - int32_t *avg, - uint8_t symbol, - uint32_t len, - unsigned short nb_rb) + NR_DL_FRAME_PARMS *frame_parms, + int32_t *avg, + uint8_t symbol, + uint32_t len, + unsigned short nb_rb) { #if defined(__x86_64__)||defined(__i386__) @@ -1864,10 +1864,11 @@ void nr_dlsch_channel_level(int **dl_ch_estimates_ext, //nb_rb*nre = y * 2^x int16_t x = factor2(len); + //x = (x>4) ? 4 : x; int16_t y = (len)>>x; - //printf("nb_rb*nre = %d = %d * 2^(%d)\n",nb_rb*nre,y,x); + //printf("len = %d = %d * 2^(%d)\n",len,y,x); - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) for (aarx=0; aarxnb_antennas_rx; aarx++) { //clear average level avg128D = _mm_setzero_si128(); @@ -1876,29 +1877,10 @@ void nr_dlsch_channel_level(int **dl_ch_estimates_ext, dl_ch128=(__m128i *)&dl_ch_estimates_ext[(aatx<<1)+aarx][symbol*nb_rb*12]; for (rb=0;rbNcp-1)))&&(frame_parms->nb_antenna_ports_eNB!=1)) { - dl_ch128+=2; - } - else {*/ - avg128D = _mm_add_epi32(avg128D,_mm_srai_epi16(_mm_madd_epi16(dl_ch128[2],dl_ch128[2]),x)); - //avg128D = _mm_add_epi32(avg128D,_mm_madd_epi16(dl_ch128[2],_mm_srai_epi16(_mm_mulhi_epi16(dl_ch128[2], coeff128),15))); - dl_ch128+=3; - // } - /* - if (rb==0) { - print_shorts("dl_ch128",&dl_ch128[0]); - print_shorts("dl_ch128",&dl_ch128[1]); - print_shorts("dl_ch128",&dl_ch128[2]); - } - */ + avg128D = _mm_add_epi32(avg128D,_mm_srai_epi16(_mm_madd_epi16(dl_ch128[2],dl_ch128[2]),x)); + dl_ch128+=3; } avg[(aatx<<1)+aarx] =(((int32_t*)&avg128D)[0] + @@ -1920,7 +1902,7 @@ void nr_dlsch_channel_level(int **dl_ch_estimates_ext, symbol_mod = (symbol>=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol; - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++) + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) for (aarx=0; aarxnb_antennas_rx; aarx++) { //clear average level avg128D = vdupq_n_s32(0); @@ -1936,7 +1918,7 @@ void nr_dlsch_channel_level(int **dl_ch_estimates_ext, avg128D = vqaddq_s32(avg128D,vmull_s16(dl_ch128[2],dl_ch128[2])); avg128D = vqaddq_s32(avg128D,vmull_s16(dl_ch128[3],dl_ch128[3])); - if (((symbol_mod == 0) || (symbol_mod == (frame_parms->Ncp-1)))&&(frame_parms->nb_antenna_ports_eNB!=1)) { + if (((symbol_mod == 0) || (symbol_mod == (frame_parms->Ncp-1)))&&(frame_parms->nb_antenna_ports_gNB!=1)) { dl_ch128+=4; } else { avg128D = vqaddq_s32(avg128D,vmull_s16(dl_ch128[4],dl_ch128[4])); @@ -2030,7 +2012,7 @@ void nr_dlsch_channel_level_median(int **dl_ch_estimates_ext, int32x4_t norm128D; int16x4_t *dl_ch128; - for (aatx=0; aatxnb_antenna_ports_eNB; aatx++){ + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++){ for (aarx=0; aarxnb_antennas_rx; aarx++) { max = 0; min = 0; @@ -2602,7 +2584,7 @@ void dump_dlsch2(PHY_VARS_UE *ue,uint8_t eNB_id,uint8_t nr_tti_rx,unsigned int * write_output(fname,vname,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dl_ch_estimates_ext[1],12*N_RB_DL*nsymb,1,1); } - if (ue->frame_parms.nb_antenna_ports_eNB == 2) { + if (ue->frame_parms.nb_antenna_ports_gNB == 2) { sprintf(fname,"dlsch%d_ch_r%d_ext10.m",eNB_id,round); sprintf(vname,"dl%d_ch_r%d_ext10",eNB_id,round); write_output(fname,vname,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dl_ch_estimates_ext[2],12*N_RB_DL*nsymb,1,1); @@ -2636,7 +2618,7 @@ void dump_dlsch2(PHY_VARS_UE *ue,uint8_t eNB_id,uint8_t nr_tti_rx,unsigned int * sprintf(fname,"dlsch%d_rxF_r%d_comp0.m",eNB_id,round); sprintf(vname,"dl%d_rxF_r%d_comp0",eNB_id,round); write_output(fname,vname,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp0[0],12*N_RB_DL*nsymb,1,1); - if (ue->frame_parms.nb_antenna_ports_eNB == 2) { + if (ue->frame_parms.nb_antenna_ports_gNB == 2) { sprintf(fname,"dlsch%d_rxF_r%d_comp1.m",eNB_id,round); sprintf(vname,"dl%d_rxF_r%d_comp1",eNB_id,round); write_output(fname,vname,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp1[harq_pid][round][0],12*N_RB_DL*nsymb,1,1); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_llr_computation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_llr_computation.c index 35458f330f..ce1c0df156 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_llr_computation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_llr_computation.c @@ -980,7 +980,7 @@ void nr_dlsch_64qam_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { amp_tmp = 0x1fff;//dlsch0->sqrt_rho_b; already taken into account - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) len = nb_rb*8 - (2*pbch_pss_sss_adjust/3); else len = nb_rb*10 - (5*pbch_pss_sss_adjust/6); @@ -1379,7 +1379,7 @@ int nr_dlsch_qpsk_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { // if symbol has pilots - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) // in 2 antenna ports we have 8 REs per symbol per RB len = (nb_rb*8) - (2*pbch_pss_sss_adjust/3); else @@ -1661,7 +1661,7 @@ int nr_dlsch_qpsk_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { // if symbol has pilots - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) // in 2 antenna ports we have 8 REs per symbol per RB len = (nb_rb*8) - (2*pbch_pss_sss_adjust/3); else @@ -2427,7 +2427,7 @@ int nr_dlsch_16qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { // if symbol has pilots - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) // in 2 antenna ports we have 8 REs per symbol per RB len = (nb_rb*8) - (2*pbch_pss_sss_adjust/3); else @@ -3602,7 +3602,7 @@ int nr_dlsch_16qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { // if symbol has pilots - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) // in 2 antenna ports we have 8 REs per symbol per RB len = (nb_rb*8) - (2*pbch_pss_sss_adjust/3); else @@ -5164,7 +5164,7 @@ int nr_dlsch_64qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { // if symbol has pilots - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) // in 2 antenna ports we have 8 REs per symbol per RB len = (nb_rb*8) - (2*pbch_pss_sss_adjust/3); else @@ -6707,7 +6707,7 @@ int nr_dlsch_64qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, if ((symbol_mod==0) || (symbol_mod==(4-frame_parms->Ncp))) { // if symbol has pilots - if (frame_parms->nb_antenna_ports_eNB!=1) + if (frame_parms->nb_antenna_ports_gNB!=1) // in 2 antenna ports we have 8 REs per symbol per RB len = (nb_rb*8) - (2*pbch_pss_sss_adjust/3); else diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c index fc4fff1c40..61748a8e56 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c @@ -176,7 +176,7 @@ int nr_pbch_detection(UE_nr_rxtx_proc_t * proc, PHY_VARS_NR_UE *ue, int pbch_ini if (ret==0) { - frame_parms->nb_antenna_ports_eNB = 1; //pbch_tx_ant; + frame_parms->nb_antenna_ports_gNB = 1; //pbch_tx_ant; // set initial transmission mode to 1 or 2 depending on number of detected TX antennas //frame_parms->mode1_flag = (pbch_tx_ant==1); @@ -213,18 +213,9 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, NR_DL_FRAME_PARMS *fp = &ue->frame_parms; int ret=-1; int rx_power=0; //aarx, - //nfapi_nr_config_request_t* config; - int n_ssb_crb=(fp->N_RB_DL-20); - // First try TDD normal prefix, mu 1 - fp->Ncp=NORMAL; - fp->frame_type=TDD; - // FK: added N_RB_DL paramter here as this function shares code with the gNB where it is needed. We should rewrite this function for the UE. - nr_init_frame_parms_ue(fp,NR_MU_1,NORMAL,fp->N_RB_DL,n_ssb_crb,0); LOG_D(PHY,"nr_initial sync ue RB_DL %d\n", fp->N_RB_DL); - - /* Initial synchronisation * * 1 radio frame = 10 ms @@ -264,7 +255,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, double s_time = 1/(1.0e3*fp->samples_per_subframe); // sampling time double off_angle = -2*M_PI*s_time*(ue->common_vars.freq_offset); // offset rotation angle compensation per sample - int start = ue->ssb_offset; // start for offset correction is at ssb_offset (pss time position) + int start = is*fp->samples_per_frame+ue->ssb_offset; // start for offset correction is at ssb_offset (pss time position) int end = start + 4*(fp->ofdm_symbol_size + fp->nb_prefix_samples); // loop over samples in 4 symbols (ssb size), including prefix for(int n=start; nssb_offset, + is*fp->samples_per_frame+ue->ssb_offset, 0); #ifdef DEBUG_INITIAL_SYNCH @@ -312,7 +303,13 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, // sync at symbol ue->symbol_offset // computing the offset wrt the beginning of the frame sync_pos_frame = (fp->ofdm_symbol_size + fp->nb_prefix_samples0)+((ue->symbol_offset)-1)*(fp->ofdm_symbol_size + fp->nb_prefix_samples); - ue->rx_offset = ue->ssb_offset - sync_pos_frame; + + if (ue->ssb_offset < sync_pos_frame) + ue->rx_offset = fp->samples_per_frame - sync_pos_frame + ue->ssb_offset; + else + ue->rx_offset = ue->ssb_offset - sync_pos_frame; + + ue->init_sync_frame = is; } nr_gold_pdcch(ue,0, 2); @@ -406,7 +403,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, fp->N_RB_DL, fp->phich_config_common.phich_duration, phich_string[fp->phich_config_common.phich_resource], - fp->nb_antenna_ports_eNB);*/ + fp->nb_antenna_ports_gNB);*/ #if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) LOG_I(PHY, "[UE %d] Measured Carrier Frequency %.0f Hz (offset %d Hz)\n", diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c index 0e7bedfb78..60306d8e53 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c @@ -430,7 +430,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, //uint32_t pbch_a_prime; int16_t *pbch_e_rx; uint8_t *decoded_output = nr_ue_pbch_vars->decoded_output; - uint8_t nushift,n_hf,ssb_index; + uint8_t nushift; uint16_t M; uint8_t Lmax=frame_parms->Lmax; //uint16_t crc; @@ -538,7 +538,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, uint32_t unscrambling_mask = (Lmax==64)?0x100006D:0x1000041; nr_pbch_unscrambling(nr_ue_pbch_vars,frame_parms->Nid_cell,nushift,M,NR_POLAR_PBCH_E,0,0); //polar decoding de-rate matching - const t_nrPolar_params *currentPtr = nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL); + const t_nrPolar_params *currentPtr = nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,1,&ue->polarList); decoderState = polar_decoder_int16(pbch_e_rx,(uint64_t *)&nr_ue_pbch_vars->pbch_a_prime,0,currentPtr); if(decoderState) return(decoderState); @@ -578,15 +578,21 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, for (int i=0; i<3; i++) decoded_output[i] = (uint8_t)((payload>>((3-i)<<3))&0xff); - n_hf = ((nr_ue_pbch_vars->xtra_byte>>4)&0x01); // computing the half frame index from the extra byte + frame_parms->half_frame_bit = ((nr_ue_pbch_vars->xtra_byte>>4)&0x01); // computing the half frame index from the extra byte - ssb_index = i_ssb; // ssb index corresponds to i_ssb for Lmax = 4,8 + frame_parms->ssb_index = i_ssb; // ssb index corresponds to i_ssb for Lmax = 4,8 if (Lmax == 64) { // for Lmax = 64 ssb index 4th,5th and 6th bits are in extra byte for (int i=0; i<3; i++) - ssb_index += (((nr_ue_pbch_vars->xtra_byte>>(7-i))&0x01)<<(3+i)); + frame_parms->ssb_index += (((nr_ue_pbch_vars->xtra_byte>>(7-i))&0x01)<<(3+i)); } - ue->symbol_offset = nr_get_ssb_start_symbol(frame_parms, ssb_index, n_hf); + ue->symbol_offset = nr_get_ssb_start_symbol(frame_parms); + + uint8_t frame_number_4lsb = 0; + for (int i=0; i<4; i++) + frame_number_4lsb |= ((nr_ue_pbch_vars->xtra_byte>>i)&1)<<(3-i); + + proc->decoded_frame_rx = frame_number_4lsb; #ifdef DEBUG_PBCH printf("xtra_byte %x payload %x\n", nr_ue_pbch_vars->xtra_byte, payload); @@ -602,7 +608,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance dl_indication.dci_ind = NULL; - dl_indication.proc=proc; // needed to signal back the frame number -> FIXME + dl_indication.proc=proc; dl_indication.module_id=0; dl_indication.cc_id=proc->CC_id; diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index f4f4ac8926..f407119024 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -30,20 +30,11 @@ * \warning */ #include "PHY/sse_intrin.h" -//#include "PHY/defs_common.h" -//#include "PHY/phy_extern.h" -//#include "PHY/phy_extern_ue.h" #include "common/utils/LOG/vcd_signal_dumper.h" -//#include "PHY/defs.h" #include "PHY/impl_defs_nr.h" -//#include "PHY/defs_nr_common.h" #include "PHY/defs_nr_UE.h" -#include "PHY/NR_UE_TRANSPORT/nr_prach.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" -//#include "PHY/extern.h" -//#include "LAYER2/MAC/extern.h" -//#include "PHY/NR_UE_TRANSPORT/pucch_nr.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" @@ -52,514 +43,27 @@ -#define NR_PRACH_DEBUG 1 +extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; +extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; +extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13]; +extern uint16_t NCS_unrestricted_delta_f_RA_5[16]; +extern uint16_t NCS_restricted_TypeA_delta_f_RA_5[16]; +extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14]; +extern uint16_t NCS_unrestricted_delta_f_RA_15[16]; +extern uint16_t prach_root_sequence_map_0_3[838]; +extern uint16_t prach_root_sequence_map_abc[138]; +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; +extern uint16_t nr_du[838]; +extern int16_t nr_ru[2*839]; -void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) -{ - FILE *fd; - fd = fopen("prach_config.txt","w"); - fprintf(fd,"prach_config: subframe = %d\n",subframe); - fprintf(fd,"prach_config: N_RB_UL = %d\n",frame_parms->N_RB_UL); - fprintf(fd,"prach_config: frame_type = %s\n",(frame_parms->frame_type==1) ? "TDD":"FDD"); - if(frame_parms->frame_type==1) fprintf(fd,"prach_config: tdd_config = %d\n",frame_parms->tdd_config); - - fprintf(fd,"prach_config: rootSequenceIndex = %d\n",frame_parms->prach_config_common.rootSequenceIndex); - fprintf(fd,"prach_config: prach_ConfigIndex = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex); - fprintf(fd,"prach_config: Ncs_config = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig); - fprintf(fd,"prach_config: highSpeedFlag = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.highSpeedFlag); - fprintf(fd,"prach_config: n_ra_prboffset = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset); - fclose(fd); - -} - -// This function computes the du -void nr_fill_du(uint8_t prach_fmt) -{ - - uint16_t iu,u,p; - uint16_t N_ZC; - uint16_t *prach_root_sequence_map; - - if (prach_fmt<4) { - N_ZC = 839; - prach_root_sequence_map = prach_root_sequence_map_0_3; - } else { - N_ZC = 139; - prach_root_sequence_map = prach_root_sequence_map_abc; - } - - for (iu=0; iu<(N_ZC-1); iu++) { - - u=prach_root_sequence_map[iu]; - p=1; - - while (((u*p)%N_ZC)!=1) - p++; - - nr_du[u] = ((p<(N_ZC>>1)) ? p : (N_ZC-p)); - } - -} - -#if 0 -uint8_t get_num_prach_tdd(module_id_t Mod_id) -{ - NR_DL_FRAME_PARMS *fp = &PHY_vars_UE_g[Mod_id][0]->frame_parms; - return(tdd_preamble_map[fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex][fp->tdd_config].num_prach); -} - -uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index) -{ - NR_DL_FRAME_PARMS *fp = &PHY_vars_UE_g[Mod_id][0]->frame_parms; - return(tdd_preamble_map[fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex][fp->tdd_config].map[tdd_map_index].f_ra); -} -#endif - -uint16_t get_nr_prach_fmt(uint8_t prach_ConfigIndex) -{ - //return (table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink - return (table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum - // For FR2 not implemented. FIXME -} - -#if 0 -uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type) -{ - - if (frame_type == FDD) // FDD - return(prach_ConfigIndex>>4); - - else { - if (prach_ConfigIndex < 20) - return (0); - - if (prach_ConfigIndex < 30) - return (1); - - if (prach_ConfigIndex < 40) - return (2); - - if (prach_ConfigIndex < 48) - return (3); - else - return (4); - } -} - -uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms, - uint8_t prach_ConfigIndex, - uint8_t n_ra_prboffset, - uint8_t tdd_mapindex, uint16_t Nf, uint16_t prach_fmt) -{ - lte_frame_type_t frame_type = frame_parms->frame_type; - uint8_t tdd_config = frame_parms->tdd_config; - - uint8_t n_ra_prb; - uint8_t f_ra,t1_ra; - uint8_t Nsp=2; - - if (frame_type == TDD) { // TDD - - if (tdd_preamble_map[prach_ConfigIndex][tdd_config].num_prach==0) { - LOG_E(PHY, "Illegal prach_ConfigIndex %"PRIu8"", prach_ConfigIndex); - return(-1); - } - - // adjust n_ra_prboffset for frequency multiplexing (p.36 36.211) - f_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[tdd_mapindex].f_ra; - - if (prach_fmt < 4) { - if ((f_ra&1) == 0) { - n_ra_prb = n_ra_prboffset + 6*(f_ra>>1); - } else { - n_ra_prb = frame_parms->N_RB_UL - 6 - n_ra_prboffset + 6*(f_ra>>1); - } - } else { - if ((tdd_config >2) && (tdd_config<6)) - Nsp = 2; - - t1_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[0].t1_ra; - - if ((((Nf&1)*(2-Nsp)+t1_ra)&1) == 0) { - n_ra_prb = 6*f_ra; - } else { - n_ra_prb = frame_parms->N_RB_UL - 6*(f_ra+1); - } - } - } - else { //FDD - n_ra_prb = n_ra_prboffset; - } - return(n_ra_prb); -} -#endif //0 - -int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) { - - uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; -/* - // For FR1 paired - if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && - ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - uint8_t tdd_config = frame_parms->tdd_config; - uint8_t t0_ra; - uint8_t t1_ra; - uint8_t t2_ra; - - int prach_mask = 0; - - if (frame_parms->frame_type == FDD) { //FDD - //implement Table 5.7.1-2 from 36.211 (Rel-10, p.41) - if ((((frame&1) == 1) && (subframe < 9)) || - (((frame&1) == 0) && (subframe == 9))) // This is an odd frame, ignore even-only PRACH frames - if (((prach_ConfigIndex&0xf)<3) || // 0,1,2,16,17,18,32,33,34,48,49,50 - ((prach_ConfigIndex&0x1f)==18) || // 18,50 - ((prach_ConfigIndex&0xf)==15)) // 15,47 - return(0); - - switch (prach_ConfigIndex&0x1f) { - case 0: - case 3: - if (subframe==1) prach_mask = 1; - break; - - case 1: - case 4: - if (subframe==4) prach_mask = 1; - break; - - case 2: - case 5: - if (subframe==7) prach_mask = 1; - break; - - case 6: - if ((subframe==1) || (subframe==6)) prach_mask=1; - break; - - case 7: - if ((subframe==2) || (subframe==7)) prach_mask=1; - break; - - case 8: - if ((subframe==3) || (subframe==8)) prach_mask=1; - break; - - case 9: - if ((subframe==1) || (subframe==4) || (subframe==7)) prach_mask=1; - break; - - case 10: - if ((subframe==2) || (subframe==5) || (subframe==8)) prach_mask=1; - break; - - case 11: - if ((subframe==3) || (subframe==6) || (subframe==9)) prach_mask=1; - break; - - case 12: - if ((subframe&1)==0) prach_mask=1; - break; - - case 13: - if ((subframe&1)==1) prach_mask=1; - break; - - case 14: - prach_mask=1; - break; - - case 15: - if (subframe==9) prach_mask=1; - break; - } - } else { // TDD - - AssertFatal(prach_ConfigIndex<64, - "Illegal prach_ConfigIndex %d for ",prach_ConfigIndex); - AssertFatal(tdd_preamble_map[prach_ConfigIndex][tdd_config].num_prach>0, - "Illegal prach_ConfigIndex %d for ",prach_ConfigIndex); - - t0_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[0].t0_ra; - t1_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[0].t1_ra; - t2_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[0].t2_ra; -#ifdef PRACH_DEBUG - LOG_I(PHY,"[PRACH] Checking for PRACH format (ConfigIndex %d) in TDD subframe %d (%d,%d,%d)\n", - prach_ConfigIndex, - subframe, - t0_ra,t1_ra,t2_ra); -#endif - - if ((((t0_ra == 1) && ((frame &1)==0))|| // frame is even and PRACH is in even frames - ((t0_ra == 2) && ((frame &1)==1))|| // frame is odd and PRACH is in odd frames - (t0_ra == 0)) && // PRACH is in all frames - (((subframe<5)&&(t1_ra==0)) || // PRACH is in 1st half-frame - (((subframe>4)&&(t1_ra==1))))) { // PRACH is in 2nd half-frame - if ((prach_ConfigIndex<48) && // PRACH only in normal UL subframe - (((subframe%5)-2)==t2_ra)) prach_mask=1; - else if ((prach_ConfigIndex>47) && (((subframe%5)-1)==t2_ra)) prach_mask=1; // PRACH can be in UpPTS - } - } - - return(prach_mask); -} - -int is_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) { - - uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - int prach_mask = is_prach_subframe0(frame_parms,prach_ConfigIndex,frame,subframe); - - int i; - - for (i=0;i<4;i++) { - if (frame_parms->prach_emtc_config_common.prach_ConfigInfo.prach_CElevel_enable[i] == 1) - prach_mask|=(is_prach_subframe0(frame_parms,frame_parms->prach_emtc_config_common.prach_ConfigInfo.prach_ConfigIndex[i],frame,subframe)<<(i+1)); - } - return(prach_mask); -} -#endif //0 - -void compute_nr_prach_seq(uint16_t rootSequenceIndex, - uint8_t prach_ConfigIndex, - uint8_t zeroCorrelationZoneConfig, - uint8_t highSpeedFlag, - lte_frame_type_t frame_type, - uint32_t X_u[64][839]) -{ - - // Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC) - unsigned int k,inv_u,i,NCS=0,num_preambles; - int N_ZC; - uint8_t prach_fmt = get_prach_fmt(prach_ConfigIndex,frame_type); - uint16_t *prach_root_sequence_map; - uint16_t u, preamble_offset; - uint16_t n_shift_ra,n_shift_ra_bar, d_start,numshift; - uint8_t not_found; - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN); - -#ifdef PRACH_DEBUG - LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach_fmt %d\n",zeroCorrelationZoneConfig, prach_fmt); -#endif - - AssertFatal(prach_fmt<4, - "PRACH sequence is only precomputed for prach_fmt<4 (have %"PRIu8")\n", prach_fmt ); - N_ZC = (prach_fmt < 4) ? 839 : 139; - //init_prach_tables(N_ZC); //moved to phy_init_lte_ue/eNB, since it takes to long in real-time - - if (prach_fmt < 4) { - prach_root_sequence_map = prach_root_sequence_map_0_3; - } else { - // FIXME cannot be reached - prach_root_sequence_map = prach_root_sequence_map_abc; - } - - -#ifdef PRACH_DEBUG - LOG_I( PHY, "compute_prach_seq: done init prach_tables\n" ); -#endif - - - - - int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - if (highSpeedFlag== 0) { - -#ifdef PRACH_DEBUG - LOG_I(PHY,"Low speed prach : NCS_config %d\n",zeroCorrelationZoneConfig); -#endif - - AssertFatal(zeroCorrelationZoneConfig<=15, - "FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig]; - if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig]; - if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig]; - - num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC); - - if (NCS>0) num_preambles++; - - preamble_offset = 0; - } else { - -#ifdef PRACH_DEBUG - LOG_I( PHY, "high speed prach : NCS_config %"PRIu8"\n", zeroCorrelationZoneConfig ); -#endif - - AssertFatal(zeroCorrelationZoneConfig<=14, - "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - if (prach_fmt<3){ - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME - } - if (prach_fmt==3){ - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME - } - if (prach_fmt>3){ - - } - //NCS = NCS_restricted[zeroCorrelationZoneConfig]; - nr_fill_du(prach_fmt); - - num_preambles = 64; // compute ZC sequence for 64 possible roots - // find first non-zero shift root (stored in preamble_offset) - not_found = 1; - preamble_offset = 0; - - while (not_found == 1) { - // current root depending on rootSequenceIndex - int index = (rootSequenceIndex + preamble_offset) % N_ZC; - - if (prach_fmt<4) { - // prach_root_sequence_map points to prach_root_sequence_map0_3 - DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); - } else { - // prach_root_sequence_map points to prach_root_sequence_map4 - DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); - } - - u = prach_root_sequence_map[index]; - - uint16_t n_group_ra = 0; - - if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { - n_shift_ra = nr_du[u]/NCS; - d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); - n_group_ra = N_ZC/d_start; - n_shift_ra_bar = max(0,(N_ZC-(nr_du[u]<<1)-(n_group_ra*d_start))/N_ZC); - } else if ( (nr_du[u]>=(N_ZC/3)) && (nr_du[u]<=((N_ZC - NCS)>>1)) ) { - n_shift_ra = (N_ZC - (nr_du[u]<<1))/NCS; - d_start = N_ZC - (nr_du[u]<<1) + (n_shift_ra * NCS); - n_group_ra = nr_du[u]/d_start; - n_shift_ra_bar = min(n_shift_ra,max(0,(nr_du[u]- (n_group_ra*d_start))/NCS)); - } else { - n_shift_ra = 0; - n_shift_ra_bar = 0; - } - - // This is the number of cyclic shifts for the current root u - numshift = (n_shift_ra*n_group_ra) + n_shift_ra_bar; - - // skip to next root and recompute parameters if numshift==0 - if (numshift>0) - not_found = 0; - else - preamble_offset++; - } - } - -#ifdef PRACH_DEBUG - - if (NCS>0) - LOG_I( PHY, "Initializing %u preambles for PRACH (NCS_config %"PRIu8", NCS %u, N_ZC/NCS %u)\n", - num_preambles, zeroCorrelationZoneConfig, NCS, N_ZC/NCS ); - -#endif - - for (i=0; iframe_parms.frame_type; //uint8_t tdd_config = ue->frame_parms.tdd_config; - uint16_t rootSequenceIndex = ue->frame_parms.prach_config_common.rootSequenceIndex; - uint8_t prach_ConfigIndex = ue->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - uint8_t Ncs_config = ue->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - uint8_t restricted_set = ue->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag; - //uint8_t n_ra_prboffset = ue->frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset; + NR_DL_FRAME_PARMS *fp=&ue->frame_parms; + uint16_t rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; + uint8_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; + uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; + uint8_t restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; uint8_t preamble_index = ue->prach_resources[eNB_id]->ra_PreambleIndex; //uint8_t tdd_mapindex = ue->prach_resources[eNB_id]->ra_TDD_map_index; int16_t *prachF = ue->prach_vars[eNB_id]->prachF; - static int16_t prach_tmp[45600*4] __attribute__((aligned(32))); + int16_t prach_tmp[98304*2*4] __attribute__((aligned(32))); int16_t *prach = prach_tmp; int16_t *prach2; int16_t amp = ue->prach_vars[eNB_id]->amp; int16_t Ncp; - uint8_t n_ra_prb; uint16_t NCS=0; uint16_t *prach_root_sequence_map; uint16_t preamble_offset,preamble_shift; uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar; uint16_t d_start,numshift; - uint16_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex); + uint16_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); //uint8_t Nsp=2; //uint8_t f_ra,t1_ra; uint16_t N_ZC = (prach_fmt<4)?839:139; uint8_t not_found; - int k; int16_t *Xu; uint16_t u; int32_t Xu_re,Xu_im; @@ -601,9 +103,9 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, int i, prach_len=0; uint16_t first_nonzero_root_idx=0; -#if defined(EXMIMO) || defined(OAI_USRP) - prach_start = (ue->rx_offset+subframe*ue->frame_parms.samples_per_tti-ue->hw_timing_advance-ue->N_TA_offset); -#ifdef PRACH_DEBUG +#if defined(OAI_USRP) + prach_start = (ue->rx_offset+subframe*fp->samples_per_subframe-ue->hw_timing_advance-ue->N_TA_offset); +#ifdef NR_PRACH_DEBUG LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, prach_start, ue->rx_offset, @@ -612,14 +114,14 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, #endif if (prach_start<0) - prach_start+=(ue->frame_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); + prach_start+=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); - if (prach_start>=(ue->frame_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)) - prach_start-=(ue->frame_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); + if (prach_start>=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)) + prach_start-=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); #else //normal case (simulation) - prach_start = subframe*ue->frame_parms.samples_per_tti-ue->N_TA_offset; - LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, + prach_start = subframe*fp->samples_per_subframe-ue->N_TA_offset; + LOG_D(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, prach_start, ue->rx_offset, ue->hw_timing_advance, @@ -657,47 +159,8 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; } - n_ra_prb = ue->frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset; -// n_ra_prb = get_nr_prach_prb_offset(&(ue->frame_parms), -// ue->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, -// ue->frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset, -// tdd_mapindex, -// Nf, -// prach_fmt); prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; - /* - // this code is not part of get_prach_prb_offset - if (frame_type == TDD) { // TDD - - if (tdd_preamble_map[prach_ConfigIndex][tdd_config].num_prach==0) { - LOG_E( PHY, "[PHY][UE %"PRIu8"] Illegal prach_ConfigIndex %"PRIu8" for ", ue->Mod_id, prach_ConfigIndex ); - } - - // adjust n_ra_prboffset for frequency multiplexing (p.36 36.211) - f_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[tdd_mapindex].f_ra; - - if (prach_fmt < 4) { - if ((f_ra&1) == 0) { - n_ra_prb = n_ra_prboffset + 6*(f_ra>>1); - } else { - n_ra_prb = ue->frame_parms.N_RB_UL - 6 - n_ra_prboffset + 6*(f_ra>>1); - } - } else { - if ((tdd_config >2) && (tdd_config<6)) - Nsp = 2; - - t1_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[0].t1_ra; - - if ((((Nf&1)*(2-Nsp)+t1_ra)&1) == 0) { - n_ra_prb = 6*f_ra; - } else { - n_ra_prb = ue->frame_parms.N_RB_UL - 6*(f_ra+1); - } - } - } - */ - // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); @@ -707,7 +170,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, preamble_shift *= NCS; } else { // This is the high-speed case -#ifdef PRACH_DEBUG +#ifdef NR_PRACH_DEBUG LOG_I(PHY,"[UE %d] High-speed mode, NCS_config %d\n",ue->Mod_id,Ncs_config); #endif @@ -766,36 +229,75 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, } // now generate PRACH signal -#ifdef PRACH_DEBUG +#ifdef NR_PRACH_DEBUG if (NCS>0) - LOG_I(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, NCS %d (NCS_config %d, N_ZC/NCS %d) n_ra_prb %d: Preamble_offset %d, Preamble_shift %d\n", - rootSequenceIndex,preamble_index,NCS,Ncs_config,N_ZC/NCS,n_ra_prb, + LOG_D(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, prach_ConfigIndex %d, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", + rootSequenceIndex,preamble_index,prach_fmt,prach_ConfigIndex,NCS,Ncs_config,N_ZC/NCS, preamble_offset,preamble_shift); #endif // nsymb = (frame_parms->Ncp==0) ? 14:12; // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*subframe*nsymb; + int kbar = 1; + int K = 24; + if (prach_fmt == 3) { + K=4; + kbar=10; + } + else if (prach_fmt > 3) { + // Note: Assumes that PRACH SCS is same as PUSCH SCS + K=1; + kbar=2; + } + int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; + int k = (12*n_ra_prb) - 6*fp->N_RB_UL; - k = (12*n_ra_prb) - 6*ue->frame_parms.N_RB_UL; + k = (12*n_ra_prb) - 6*fp->N_RB_UL; - if (k<0) - k+=ue->frame_parms.ofdm_symbol_size; + if (k<0) k+=fp->ofdm_symbol_size; - k*=12; - k+=13; + k*=K; + k+=kbar; + + LOG_D(PHY,"placing prach in position %d\n",k); + k*=2; Xu = (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx]; - /* - k+=(12*ue->frame_parms.first_carrier_offset); - if (k>(12*ue->frame_parms.ofdm_symbol_size)) - k-=(12*ue->frame_parms.ofdm_symbol_size); - */ - k*=2; + /******************************************************** + * + * In function init_prach_tables: + * to compute quantized roots of unity ru(n) = 32767 * exp j*[ (2 * PI * n) / N_ZC ] + * + * In compute_prach_seq: + * to calculate Xu = DFT xu = xu (inv_u*k) * Xu[0] (This is a Zadoff-Chou sequence property: DFT ZC sequence is another ZC sequence) + * + * In generate_prach: + * to do the cyclic-shifted DFT by multiplying Xu[k] * ru[k*preamble_shift] as: + * If X[k] = DFT x(n) -> X_shifted[k] = DFT x(n+preamble_shift) = X[k] * exp -j*[ (2*PI*k*preamble_shift) / N_ZC ] + * + *********************************************************/ - switch (ue->frame_parms.N_RB_UL) { + AssertFatal(prach_fmt>3,"prach_fmt<=3: Fix this for other formats\n"); + int dftlen=2048; + if (fp->N_RB_UL >= 137) dftlen=4096; + if (fp->threequarter_fs==1) dftlen=(3*dftlen)/4; + + for (offset=0,offset2=0; offset= N_ZC) + offset2 -= N_ZC; + + Xu_re = (((int32_t)Xu[offset<<1]*amp)>>15); + Xu_im = (((int32_t)Xu[1+(offset<<1)]*amp)>>15); + prachF[k++]= ((Xu_re*nr_ru[offset2<<1]) - (Xu_im*nr_ru[1+(offset2<<1)]))>>15; + prachF[k++]= ((Xu_im*nr_ru[offset2<<1]) + (Xu_re*nr_ru[1+(offset2<<1)]))>>15; + if (k==dftlen) k=0; + } + + switch (fp->N_RB_UL) { case 6: memset((void*)prachF,0,4*1536); break; @@ -817,7 +319,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, break; case 100: - if (ue->frame_parms.threequarter_fs == 0) + if (fp->threequarter_fs == 0) memset((void*)prachF,0,4*24576); else memset((void*)prachF,0,4*18432); @@ -828,34 +330,6 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, break; } - /******************************************************** - * - * In function init_prach_tables: - * to compute quantized roots of unity ru(n) = 32767 * exp j*[ (2 * PI * n) / N_ZC ] - * - * In compute_prach_seq: - * to calculate Xu = DFT xu = xu (inv_u*k) * Xu[0] (This is a Zadoff-Chou sequence property: DFT ZC sequence is another ZC sequence) - * - * In generate_prach: - * to do the cyclic-shifted DFT by multiplying Xu[k] * ru[k*preamble_shift] as: - * If X[k] = DFT x(n) -> X_shifted[k] = DFT x(n+preamble_shift) = X[k] * exp -j*[ (2*PI*k*preamble_shift) / N_ZC ] - * - *********************************************************/ - - for (offset=0,offset2=0; offset= N_ZC) - offset2 -= N_ZC; - - Xu_re = (((int32_t)Xu[offset<<1]*amp)>>15); - Xu_im = (((int32_t)Xu[1+(offset<<1)]*amp)>>15); - prachF[k++]= ((Xu_re*nr_ru[offset2<<1]) - (Xu_im*nr_ru[1+(offset2<<1)]))>>15; - prachF[k++]= ((Xu_im*nr_ru[offset2<<1]) + (Xu_re*nr_ru[1+(offset2<<1)]))>>15; - - if (k==(12*2*ue->frame_parms.ofdm_symbol_size)) - k=0; - } - int mu = 1; // numerology is hardcoded. FIXME!!! switch (prach_fmt) { case 0: @@ -863,7 +337,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, break; case 1: - Ncp = 21024; + Ncp = 2*21024; break; case 2: @@ -914,254 +388,415 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, Ncp = 3168; break; } -#if 0 // code for LTE - switch (prach_fmt) { - case 0: - Ncp = 3168; - break; - case 1: - case 3: - Ncp = 21024; - break; - case 2: - Ncp = 6240; - break; - - case 4: - Ncp = 448; - break; - - default: - Ncp = 3168; - break; + if (fp->N_RB_UL <= 100) + AssertFatal(1==0,"N_RB_UL %d not supported for NR PRACH yet\n",fp->N_RB_UL); + else if (fp->N_RB_UL < 137) { // 46.08 or 61.44 Ms/s + if (fp->threequarter_fs==0) { //61.44 Ms/s + Ncp<<=1; + // This is after cyclic prefix (Ncp<<1 samples for 30.72 Ms/s, Ncp<<2 samples for 61.44 Ms/s + prach2 = prach+(Ncp<<1); + if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft49152(prachF,prach2,1); + // here we have |empty | Prach49152| + memmove(prach,prach+(49152<<1),(Ncp<<3)); + // here we have |Prefix | Prach49152| + prach_len = 49152+Ncp; + dftlen=49152; + } + else if (prach_fmt == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft49152(prachF,prach2,1); + memmove(prach2+(49152<<1),prach2,(49152<<2)); + // here we have |empty | Prach49152 | Prach49152| + memmove(prach,prach+(49152<<2),(Ncp<<3)); + // here we have |Prefix | Prach49152 | Prach49152| + prach_len = (49152*2)+Ncp; + dftlen=49152; + } + else if (prach_fmt == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft49152(prachF,prach2,1); + memmove(prach2+(49152<<1),prach2,(49152<<2)); + // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 + memmove(prach2+(49152<<2),prach2,(49152<<3)); + // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152 + memmove(prach,prach+(49152<<3),(Ncp<<3)); + // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152 + prach_len = (49152*4)+Ncp; + dftlen=49152; + } + else if (prach_fmt == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s + idft12288(prachF,prach2,1); + memmove(prach2+(12288<<1),prach2,(12288<<2)); + // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 + memmove(prach2+(12288<<2),prach2,(12288<<3)); + // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288 + memmove(prach,prach+(12288<<3),(Ncp<<3)); + // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288 + prach_len = (12288*4)+Ncp; + dftlen=12288; + } + else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + dftlen=2048; + // here we have |empty | Prach2048 | + if (prach_fmt != 0xc0) { + memmove(prach2+(2048<<1),prach2,(2048<<2)); + prach_len = (2048*2)+Ncp; + } + else prach_len = (2048*1)+Ncp; + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | + } + else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x2048 + idft2048(prachF,prach2,1); + dftlen=2048; + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | + prach_len = (2048*4)+Ncp; + } + else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x2048 + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + dftlen=2048; + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 + memmove(prach2+((2048<<1)*3),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | + prach_len = (2048*6)+Ncp; + } + else if (prach_fmt == 0xb4) { // 12x2048 + idft2048(prachF,prach2,1); + dftlen=2048; + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 + memmove(prach2+(2048<<3),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 + memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| + prach_len = (2048*12)+Ncp; + } + + } + else { // 46.08 Ms/s + Ncp = (Ncp*3)/2; + prach2 = prach+(Ncp<<1); + if (prach_fmt == 0) { + idft36864(prachF,prach2,1); + dftlen=36864; + // here we have |empty | Prach73728| + memmove(prach,prach+(36864<<1),(Ncp<<2)); + // here we have |Prefix | Prach73728| + prach_len = (36864*1)+Ncp; + } + else if (prach_fmt == 1) { + idft36864(prachF,prach2,1); + dftlen=36864; + memmove(prach2+(36864<<1),prach2,(36864<<2)); + // here we have |empty | Prach73728 | Prach73728| + memmove(prach,prach+(36864<<2),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| + prach_len = (36864*2)+Ncp; + } + if (prach_fmt == 2) { + idft36864(prachF,prach2,1); + dftlen=36864; + memmove(prach2+(36864<<1),prach2,(36864<<2)); + // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 + memmove(prach2+(36864<<2),prach2,(36864<<3)); + // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 + memmove(prach,prach+(36864<<3),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 + prach_len = (36864*4)+Ncp; + } + else if (prach_fmt == 3) { + idft9216(prachF,prach2,1); + dftlen=36864; + memmove(prach2+(9216<<1),prach2,(9216<<2)); + // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216 + memmove(prach2+(9216<<2),prach2,(9216<<3)); + // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216 + memmove(prach,prach+(9216<<3),(Ncp<<2)); + // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216 + prach_len = (9216*4)+Ncp; + } + else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + idft1536(prachF,prach2,1); + dftlen=1536; + // here we have |empty | Prach1536 | + if (prach_fmt != 0xc0) + memmove(prach2+(1536<<1),prach2,(1536<<2)); + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | + prach_len = (1536*2)+Ncp; + } + else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536 + idft1536(prachF,prach2,1); + dftlen=1536; + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | + prach_len = (1536*4)+Ncp; + } + else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x1536 + idft1536(prachF,prach2,1); + dftlen=1536; + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 + memmove(prach2+((1536<<1)*3),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | + prach_len = (1536*6)+Ncp; + } + else if (prach_fmt == 0xb4) { // 12x1536 + idft1536(prachF,prach2,1); + dftlen=1536; + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 + memmove(prach2+(1536<<3),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 + memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| + prach_len = (1536*12)+Ncp; + } + } } + else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s + if (fp->threequarter_fs==0) { //122.88 Ms/s + Ncp<<=2; + prach2 = prach+(Ncp<<1); + if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s + idft98304(prachF,prach2,1); + dftlen=98304; + // here we have |empty | Prach98304| + memmove(prach,prach+(98304<<1),(Ncp<<2)); + // here we have |Prefix | Prach98304| + prach_len = (98304*1)+Ncp; + } + else if (prach_fmt == 1) { + idft98304(prachF,prach2,1); + dftlen=98304; + memmove(prach2+(98304<<1),prach2,(98304<<2)); + // here we have |empty | Prach98304 | Prach98304| + memmove(prach,prach+(98304<<2),(Ncp<<2)); + // here we have |Prefix | Prach98304 | Prach98304| + prach_len = (98304*2)+Ncp; + } + else if (prach_fmt == 2) { + idft98304(prachF,prach2,1); + dftlen=98304; + memmove(prach2+(98304<<1),prach2,(98304<<2)); + // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304 + memmove(prach2+(98304<<2),prach2,(98304<<3)); + // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304 + memmove(prach,prach+(98304<<3),(Ncp<<2)); + // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304 + prach_len = (98304*4)+Ncp; + } + else if (prach_fmt == 3) { // 4x6144, Ncp 3168 + idft24576(prachF,prach2,1); + dftlen=24576; + memmove(prach2+(24576<<1),prach2,(24576<<2)); + // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576 + memmove(prach2+(24576<<2),prach2,(24576<<3)); + // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576 + memmove(prach,prach+(24576<<3),(Ncp<<2)); + // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576 + prach_len = (24576*4)+(Ncp<<1); + } + else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + idft4096(prachF,prach2,1); + dftlen=4096; + // here we have |empty | Prach4096 | + if (prach_fmt != 0xc0) { + memmove(prach2+(4096<<1),prach2,(4096<<2)); + prach_len = (4096*2)+Ncp; + } + else prach_len = (4096*1)+Ncp; + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) | - switch (ue->frame_parms.N_RB_UL) { - case 6: - Ncp>>=4; - prach+=4; // makes prach2 aligned to 128-bit - break; - - case 15: - Ncp>>=3; - break; - - case 25: - Ncp>>=2; - break; - - case 50: - Ncp>>=1; - break; - - case 75: - Ncp=(Ncp*3)>>2; - break; - } -#endif - if (ue->frame_parms.threequarter_fs == 1) - Ncp=(Ncp*3)>>2; - - prach2 = prach+(Ncp<<1); - - // do IDFT - switch (ue->frame_parms.N_RB_UL) { - case 6: - if (prach_fmt == 4) { - idft256(prachF,prach2,1); - memmove( prach, prach+512, Ncp<<2 ); - prach_len = 256+Ncp; - } else { - idft1536(prachF,prach2,1); - memmove( prach, prach+3072, Ncp<<2 ); - prach_len = 1536+Ncp; - - if (prach_fmt>1) { - memmove( prach2+3072, prach2, 6144 ); - prach_len = 2*1536+Ncp; + } + else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x4096 + idft4096(prachF,prach2,1); + dftlen=4096; + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | + prach_len = (4096*4)+Ncp; + } + else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x4096 + idft4096(prachF,prach2,1); + dftlen=4096; + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 + memmove(prach2+((4096<<1)*3),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | + prach_len = (4096*6)+Ncp; + } + else if (prach_fmt == 0xb4) { // 12x4096 + idft4096(prachF,prach2,1); + dftlen=4096; + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 + memmove(prach2+(4096<<3),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 + memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| + prach_len = (4096*12)+Ncp; } } - - break; - - case 15: - if (prach_fmt == 4) { - idft512(prachF,prach2,1); - //TODO: account for repeated format in dft output - memmove( prach, prach+1024, Ncp<<2 ); - prach_len = 512+Ncp; - } else { - idft3072(prachF,prach2,1); - memmove( prach, prach+6144, Ncp<<2 ); - prach_len = 3072+Ncp; - - if (prach_fmt>1) { - memmove( prach2+6144, prach2, 12288 ); - prach_len = 2*3072+Ncp; + else { // 92.16 Ms/s + Ncp = (Ncp*3); + prach2 = prach+(Ncp<<1); + if (prach_fmt == 0) { + idft73728(prachF,prach2,1); + dftlen=73728; + // here we have |empty | Prach73728| + memmove(prach,prach+(73728<<1),(Ncp<<4)); + // here we have |Prefix | Prach73728| + prach_len = (73728*1)+Ncp; + } + else if (prach_fmt == 1) { + idft73728(prachF,prach2,1); + dftlen=73728; + memmove(prach2+(73728<<1),prach2,(73728<<2)); + // here we have |empty | Prach73728 | Prach73728| + memmove(prach,prach+(73728<<2),(Ncp<<4)); + // here we have |Prefix | Prach73728 | Prach73728| + prach_len = (73728*2)+Ncp; + } + if (prach_fmt == 2) { + idft73728(prachF,prach2,1); + dftlen=73728; + memmove(prach2+(73728<<1),prach2,(73728<<2)); + // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 + memmove(prach2+(73728<<2),prach2,(73728<<3)); + // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 + memmove(prach,prach+(73728<<3),(Ncp<<4)); + // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 + prach_len = (73728*4)+Ncp; + } + else if (prach_fmt == 3) { + idft18432(prachF,prach2,1); + dftlen=18432; + memmove(prach2+(18432<<1),prach2,(18432<<2)); + // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 + memmove(prach2+(18432<<2),prach2,(18432<<3)); + // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432 + memmove(prach,prach+(18432<<3),(Ncp<<4)); + // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432 + prach_len = (18432*4)+Ncp; + } + else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + idft3072(prachF,prach2,1); + dftlen=3072; + // here we have |empty | Prach3072 | + if (prach_fmt != 0xc0) { + memmove(prach2+(3072<<1),prach2,(3072<<2)); + prach_len = (3072*2)+Ncp; + } + else prach_len = (3072*1)+Ncp; + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | + } + else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x3072 + idft3072(prachF,prach2,1); + dftlen=3072; + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 + memmove(prach2+((3072<<1)*3),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | + prach_len = (3072*6)+Ncp; + } + else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x3072 + idft3072(prachF,prach2,1); + dftlen=3072; + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | + prach_len = (3072*4)+Ncp; + } + else if (prach_fmt == 0xb4) { // 12x3072 + idft3072(prachF,prach2,1); + dftlen=3072; + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 + memmove(prach2+(3072<<3),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 + memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| + prach_len = (3072*12)+Ncp; } } + } - break; - case 25: - default: - if (prach_fmt == 4) { - idft1024(prachF,prach2,1); - memmove( prach, prach+2048, Ncp<<2 ); - prach_len = 1024+Ncp; - } else { - idft6144(prachF,prach2,1); - /*for (i=0;i<6144*2;i++) - prach2[i]<<=1;*/ - memmove( prach, prach+12288, Ncp<<2 ); - prach_len = 6144+Ncp; - if (prach_fmt>1) { - memmove( prach2+12288, prach2, 24576 ); - prach_len = 2*6144+Ncp; - } - } - break; - - case 50: - if (prach_fmt == 4) { - idft2048(prachF,prach2,1); - memmove( prach, prach+4096, Ncp<<2 ); - prach_len = 2048+Ncp; - } else { - idft12288(prachF,prach2,1); - memmove( prach, prach+24576, Ncp<<2 ); - prach_len = 12288+Ncp; - - if (prach_fmt>1) { - memmove( prach2+24576, prach2, 49152 ); - prach_len = 2*12288+Ncp; - } - } - - break; - - case 75: - if (prach_fmt == 4) { - idft3072(prachF,prach2,1); - //TODO: account for repeated format in dft output - memmove( prach, prach+6144, Ncp<<2 ); - prach_len = 3072+Ncp; - } else { - idft18432(prachF,prach2,1); - memmove( prach, prach+36864, Ncp<<2 ); - prach_len = 18432+Ncp; - - if (prach_fmt>1) { - memmove( prach2+36834, prach2, 73728 ); - prach_len = 2*18432+Ncp; - } - } - - break; - - case 100: - if (ue->frame_parms.threequarter_fs == 0) { - if (prach_fmt == 4) { - idft4096(prachF,prach2,1); - memmove( prach, prach+8192, Ncp<<2 ); - prach_len = 4096+Ncp; - } else { - idft24576(prachF,prach2,1); - memmove( prach, prach+49152, Ncp<<2 ); - prach_len = 24576+Ncp; - if (prach_fmt>1) { - memmove( prach2+49152, prach2, 98304 ); - prach_len = 2* 24576+Ncp; - } - } - } - else { - if (prach_fmt == 4) { - idft3072(prachF,prach2,1); - //TODO: account for repeated format in dft output - memmove( prach, prach+6144, Ncp<<2 ); - prach_len = 3072+Ncp; - } else { - idft18432(prachF,prach2,1); - memmove( prach, prach+36864, Ncp<<2 ); - prach_len = 18432+Ncp; - printf("Generated prach for 100 PRB, 3/4 sampling\n"); - if (prach_fmt>1) { - memmove( prach2+36834, prach2, 73728 ); - prach_len = 2*18432+Ncp; - } - } - } - break; - - case 106: - if (prach_fmt == 0) { - idft24576(prachF,prach2,1); - memmove(prach, prach+49152, Ncp<<2); - prach_len = 24576+Ncp; - } - if (prach_fmt == 1) { - idft24576(prachF,prach2,1); - memmove(prach2+49152, prach2, 98304); - memmove(prach, prach+49152, Ncp<<2); - prach_len = 2 * 24576 + Ncp; - } - if (prach_fmt == 2) { - idft24576(prachF,prach2,1); - memmove(prach2+49152, prach2, 98304); - memmove(prach2+98304, prach2, 98304); - memmove(prach, prach+49152, Ncp<<2); - prach_len = 4 * 24576 + Ncp; - } - if (prach_fmt == 3) { - idft6144(prachF,prach2,1); - memmove(prach2+6144, prach2, 12288); - memmove(prach2+12288, prach2, 12288); - memmove(prach, prach+12288, Ncp<<2); - prach_len = 4 * 6144 + Ncp; - } -// For FR2 - if (prach_fmt == 0xa1) { // we consider numderology mu = 1 - idft1024(prachF,prach2,1); - memmove(prach2+2048, prach2, 4096); - memmove(prach, prach+2048, Ncp<<2); - prach_len = 2 * 1024 + Ncp; - } -#if 0 - if (prach_fmt == 0xa2) { - } - if (prach_fmt == 0xa3) { - } - if (prach_fmt == 0xb1) { - } - if (prach_fmt == 0xb2) { - } - if (prach_fmt == 0xb3) { - } - if (prach_fmt == 0xb4) { - } - if (prach_fmt == 0xc0) { - } - if (prach_fmt == 0xc2) { - } -#endif - break; - } - - //LOG_I(PHY,"prach_len=%d\n",prach_len); - -// AssertFatal(prach_fmt<4, -// "prach_fmt4 not fully implemented" ); -#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) +#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) int j; - int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*ue->frame_parms.samples_per_tti; - LOG_I( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow ); + int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe; + LOG_D( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow ); - for (i=prach_start,j=0; iframe_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME,prach_start+prach_len); i++,j++) { + for (i=prach_start,j=0; isamples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME,prach_start+prach_len); i++,j++) { ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; } @@ -1170,24 +805,14 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; } -#if defined(EXMIMO) - // handle switch before 1st TX subframe, guarantee that the slot prior to transmission is switch on - for (k=prach_start - (ue->frame_parms.samples_per_tti>>1) ; kcommon_vars.txdata[0][k+ue->frame_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME] &= 0xFFFEFFFE; - else if (k>(ue->frame_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)) - ue->common_vars.txdata[0][k-ue->frame_parms.samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME] &= 0xFFFEFFFE; - else - ue->common_vars.txdata[0][k] &= 0xFFFEFFFE; - } -#endif #else + LOG_D( PHY, "prach_start=%d\n", prach_start); + for (i=0; icommon_vars.txdata[0][prach_start]))[2*i] = prach[2*i]; ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1]; } - #endif @@ -1195,7 +820,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, #if defined(PRACH_WRITE_OUTPUT_DEBUG) LOG_M("prach_txF0.m","prachtxF0",prachF,prach_len-Ncp,1,1); LOG_M("prach_tx0.m","prachtx0",prach+(Ncp<<1),prach_len-Ncp,1,1); - LOG_M("txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][0]),2*ue->frame_parms.samples_per_tti,1,1); + LOG_M("txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]),fp->samples_per_subframe,1,1); exit(-1); #endif diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.h b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.h deleted file mode 100644 index 1e2b758035..0000000000 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.h +++ /dev/null @@ -1,891 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*! \file PHY/LTE_TRANSPORT/prach_common.c - * \brief Common routines for UE/eNB PRACH physical channel V8.6 2009-03 - * \author Agustin Mico Pereperez - * \date 2018 - * \version 0.1 - * \company - * \email: - * \note - * \warning - */ - -int16_t nr_ru[2*839]; // quantized roots of unity -uint32_t nr_ZC_inv[839]; // multiplicative inverse for roots u -uint16_t nr_du[838]; - -/************************************* -* The following tables defined for NR -**************************************/ -// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz -uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419}; -uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A -uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B - -// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz -uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419}; -uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A -uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B - -// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} -uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; - -//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 -uint16_t prach_root_sequence_map_0_3[838] = { -129, 710, 140, 699, 120, 719, 210, 629, 168, 671, 84 , 755, 105, 734, 93 , 746, 70 , 769, 60 , 779, -2 , 837, 1 , 838, 56 , 783, 112, 727, 148, 691, 80 , 759, 42 , 797, 40 , 799, 35 , 804, 73 , 766, -146, 693, 31 , 808, 28 , 811, 30 , 809, 27 , 812, 29 , 810, 24 , 815, 48 , 791, 68 , 771, 74 , 765, -178, 661, 136, 703, 86 , 753, 78 , 761, 43 , 796, 39 , 800, 20 , 819, 21 , 818, 95 , 744, 202, 637, -190, 649, 181, 658, 137, 702, 125, 714, 151, 688, 217, 622, 128, 711, 142, 697, 122, 717, 203, 636, -118, 721, 110, 729, 89 , 750, 103, 736, 61 , 778, 55 , 784, 15 , 824, 14 , 825, 12 , 827, 23 , 816, -34 , 805, 37 , 802, 46 , 793, 207, 632, 179, 660, 145, 694, 130, 709, 223, 616, 228, 611, 227, 612, -132, 707, 133, 706, 143, 696, 135, 704, 161, 678, 201, 638, 173, 666, 106, 733, 83 , 756, 91 , 748, -66 , 773, 53 , 786, 10 , 829, 9 , 830, 7 , 832, 8 , 831, 16 , 823, 47 , 792, 64 , 775, 57 , 782, -104, 735, 101, 738, 108, 731, 208, 631, 184, 655, 197, 642, 191, 648, 121, 718, 141, 698, 149, 690, -216, 623, 218, 621, 152, 687, 144, 695, 134, 705, 138, 701, 199, 640, 162, 677, 176, 663, 119, 720, -158, 681, 164, 675, 174, 665, 171, 668, 170, 669, 87 , 752, 169, 670, 88 , 751, 107, 732, 81 , 758, -82 , 757, 100, 739, 98 , 741, 71 , 768, 59 , 780, 65 , 774, 50 , 789, 49 , 790, 26 , 813, 17 , 822, -13 , 826, 6 , 833, 5 , 834, 33 , 806, 51 , 788, 75 , 764, 99 , 740, 96 , 743, 97 , 742, 166, 673, -172, 667, 175, 664, 187, 652, 163, 676, 185, 654, 200, 639, 114, 725, 189, 650, 115, 724, 194, 645, -195, 644, 192, 647, 182, 657, 157, 682, 156, 683, 211, 628, 154, 685, 123, 716, 139, 700, 212, 627, -153, 686, 213, 626, 215, 624, 150, 689, 225, 614, 224, 615, 221, 618, 220, 619, 127, 712, 147, 692, -124, 715, 193, 646, 205, 634, 206, 633, 116, 723, 160, 679, 186, 653, 167, 672, 79 , 760, 85 , 754, -77 , 762, 92 , 747, 58 , 781, 62 , 777, 69 , 770, 54 , 785, 36 , 803, 32 , 807, 25 , 814, 18 , 821, -11 , 828, 4 , 835, 3 , 836, 19 , 820, 22 , 817, 41 , 798, 38 , 801, 44 , 795, 52 , 787, 45 , 794, -63 , 776, 67 , 772, 72 , 767, 76 , 763, 94 , 745, 102, 737, 90 , 749, 109, 730, 165, 674, 111, 728, -209, 630, 204, 635, 117, 722, 188, 651, 159, 680, 198, 641, 113, 726, 183, 656, 180, 659, 177, 662, -196, 643, 155, 684, 214, 625, 126, 713, 131, 708, 219, 620, 222, 617, 226, 613, 230, 609, 232, 607, -262, 577, 252, 587, 418, 421, 416, 423, 413, 426, 411, 428, 376, 463, 395, 444, 283, 556, 285, 554, -379, 460, 390, 449, 363, 476, 384, 455, 388, 451, 386, 453, 361, 478, 387, 452, 360, 479, 310, 529, -354, 485, 328, 511, 315, 524, 337, 502, 349, 490, 335, 504, 324, 515, 323, 516, 320, 519, 334, 505, -359, 480, 295, 544, 385, 454, 292, 547, 291, 548, 381, 458, 399, 440, 380, 459, 397, 442, 369, 470, -377, 462, 410, 429, 407, 432, 281, 558, 414, 425, 247, 592, 277, 562, 271, 568, 272, 567, 264, 575, -259, 580, 237, 602, 239, 600, 244, 595, 243, 596, 275, 564, 278, 561, 250, 589, 246, 593, 417, 422, -248, 591, 394, 445, 393, 446, 370, 469, 365, 474, 300, 539, 299, 540, 364, 475, 362, 477, 298, 541, -312, 527, 313, 526, 314, 525, 353, 486, 352, 487, 343, 496, 327, 512, 350, 489, 326, 513, 319, 520, -332, 507, 333, 506, 348, 491, 347, 492, 322, 517, 330, 509, 338, 501, 341, 498, 340, 499, 342, 497, -301, 538, 366, 473, 401, 438, 371, 468, 408, 431, 375, 464, 249, 590, 269, 570, 238, 601, 234, 605, -257, 582, 273, 566, 255, 584, 254, 585, 245, 594, 251, 588, 412, 427, 372, 467, 282, 557, 403, 436, -396, 443, 392, 447, 391, 448, 382, 457, 389, 450, 294, 545, 297, 542, 311, 528, 344, 495, 345, 494, -318, 521, 331, 508, 325, 514, 321, 518, 346, 493, 339, 500, 351, 488, 306, 533, 289, 550, 400, 439, -378, 461, 374, 465, 415, 424, 270, 569, 241, 598, 231, 608, 260, 579, 268, 571, 276, 563, 409, 430, -398, 441, 290, 549, 304, 535, 308, 531, 358, 481, 316, 523, 293, 546, 288, 551, 284, 555, 368, 471, -253, 586, 256, 583, 263, 576, 242, 597, 274, 565, 402, 437, 383, 456, 357, 482, 329, 510, 317, 522, -307, 532, 286, 553, 287, 552, 266, 573, 261, 578, 236, 603, 303, 536, 356, 483, 355, 484, 405, 434, -404, 435, 406, 433, 235, 604, 267, 572, 302, 537, 309, 530, 265, 574, 233, 606, 367, 472, 296, 543, -336, 503, 305, 534, 373, 466, 280, 559, 279, 560, 419, 420, 240, 599, 258, 581, 229, 610 -}; -// Table 6.3.3.1-4: Mapping from logical index i to sequence number u for preamble formats with L_RA = 139 -uint16_t prach_root_sequence_map_abc[138] = { -1 , 138, 2 , 137, 3 , 136, 4 , 135, 5 , 134, 6 , 133, 7 , 132, 8 , 131, 9 , 130, 10, 129, -11, 128, 12, 127, 13, 126, 14, 125, 15, 124, 16, 123, 17, 122, 18, 121, 19, 120, 20, 119, -21, 118, 22, 117, 23, 116, 24, 115, 25, 114, 26, 113, 27, 112, 28, 111, 29, 110, 30, 109, -31, 108, 32, 107, 33, 106, 34, 105, 35, 104, 36, 103, 37, 102, 38, 101, 39, 100, 40, 99 , -41, 98 , 42, 97 , 43, 96 , 44, 95 , 45, 94 , 46, 93 , 47, 92 , 48, 91 , 49, 90 , 50, 89 , -51, 88 , 52, 87 , 53, 86 , 54, 85 , 55, 84 , 56, 83 , 57, 82 , 58, 81 , 59, 80 , 60, 79 , -61, 78 , 62, 77 , 63, 76 , 64, 75 , 65, 74 , 66, 73 , 67, 72 , 68, 71 , 69, 70 -}; - -// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink -// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. -// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. -// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6 -int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = { -//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 -{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 -{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 -{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9 -{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 -{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 -{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 -{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 -{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 -{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 -{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 -{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4 -{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6 -{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 -{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 -{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7 -{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7 -{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8 -{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9 -{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 -{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 -{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 -{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7 -{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 -{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 -{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9 -{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 -{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 -{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 -{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 -{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 -{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 -{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9 -{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 -{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 -{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 -{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 -{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 -{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 -{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6 -{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7 -{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7 -{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8 -{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9 -{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 -{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 -{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 -{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9 -}; -// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum -int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = { -//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) -{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) -{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) -{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) -{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) -{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) -{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) -{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) -{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) -{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) -{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) -{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) -{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) -{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) -{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) -{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9) -{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) -{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) -{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6) -{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6) -{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6) -{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) -{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) -{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) -{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) -{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) -{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) -{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) -{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) -{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) -{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) -{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) -{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) -{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) -{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) -{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) -{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) -{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) -{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9) -{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9) -{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9) -{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9) -{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9) -{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) -{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9) -{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9) -{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9) -{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9) -{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9) -{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9) -{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) -{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9) -{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2) -{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7) -{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7) -{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) -{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9) -{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) -{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9) -{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9) -{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) -{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) -{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) -{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2) -{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7) -{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7) -{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) -{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9) -{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9) -{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9) -{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9) -{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1) -{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2) -{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4) -{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7) -{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9) -{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9) -{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9) -{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9) -{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) -{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9) -{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9) -{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9) -{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9) -{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9) -{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) -{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9) -{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9) -{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9) -{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9) -{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9) -{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9) -{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9) -{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) -{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9) -}; -// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum -int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { -//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39) -{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7) -{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39) -{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39) -{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7) -{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39) -{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39) -{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39) -{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39) -{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13) -{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13) -{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) -{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39) -{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39) -{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) -{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13) -{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) -{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13) -{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) -{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) -{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) -{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7) -{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xb4, -1, 16, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 16, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 8, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 8, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 4, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 4, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39) -{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39) -{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39) -{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19) -{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13) -{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 586406201480, 2, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) -{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) -{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39) -{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39) -{0xc0, -1, 16, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 16, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 8, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 8, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 8, 1, 2, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 4, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 4, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39) -{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7) -{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39) -{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39) -{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39) -{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) -{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) -{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) -{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) -{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) -{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) -{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39) -{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xa2, 0xb2, 16, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39) -{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39) -{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39) -{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39) -{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) -{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) -{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39) -}; diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index 348774b08a..35fe8bc899 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -47,7 +47,8 @@ \brief This function frees memory allocated for a particular DLSCH at UE @param dlsch Pointer to DLSCH to be removed */ -void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlsch); +void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlsch,uint8_t N_RB_DL); + /** \fn new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag) \brief This function allocates structures for a particular DLSCH at UE @@ -58,13 +59,12 @@ void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlsch); @params N_RB_DL total number of resource blocks (determine the operating BW) @param abstraction_flag Flag to indicate abstracted interface */ -NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag); +NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint16_t N_RB_DL, uint8_t abstraction_flag); -void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulsch); +void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulsch,unsigned char N_RB_UL); - -NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); +NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); @@ -1114,6 +1114,7 @@ void *nr_dlsch_decoding_2thread0(void *arg); void *nr_dlsch_decoding_2thread1(void *arg); + void nr_dlsch_unscrambling(int16_t* llr, uint32_t size, uint8_t q, @@ -1125,17 +1126,10 @@ uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue, PDSCH_t dlsch_id, uint8_t eNB_id); - int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, uint32_t frame, - uint8_t nr_tti_rx, - uint8_t eNB_id, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag, - uint8_t is_secondary_ue, - int nb_coreset_active, - uint16_t symbol_mon, - NR_SEARCHSPACE_TYPE_t searchSpaceType); + uint32_t slot); + /*! \brief Extract PSS and SSS resource elements @param phy_vars_ue Pointer to UE variables @@ -1545,10 +1539,9 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); -void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - uint8_t subframe, - int8_t* llr, - uint32_t length); +void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, + int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id); + @@ -1712,46 +1705,14 @@ uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms, uint8_t n_ra_prboffset, uint8_t tdd_mapindex, uint16_t Nf); -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, - int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common); - uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset); -uint8_t nr_dci_decoding_procedure(int s, - int p, - PHY_VARS_NR_UE *ue, - NR_DCI_ALLOC_t *dci_alloc, - NR_SEARCHSPACE_TYPE_t searchSpacetype, - int16_t eNB_id, - uint8_t nr_tti_rx, - uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], - uint16_t n_RB_ULBWP, - uint16_t n_RB_DLBWP, - crc_scrambled_t *crc_scrambled, - format_found_t *format_found, - uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]); +uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, + int frame, + int slot, + fapi_nr_dci_indication_t *dci_ind); -int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, - uint8_t eNB_id, - int frame, - uint8_t nr_tti_rx, - uint64_t dci_pdu[2], - uint16_t rnti, - uint8_t dci_length, - NR_DCI_format_t dci_format, - NR_UE_PDCCH *pdcch_vars, - NR_UE_PDSCH *pdsch_vars, - NR_UE_DLSCH_t **dlsch, - NR_UE_ULSCH_t *ulsch, - NR_DL_FRAME_PARMS *frame_parms, - PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - uint8_t beamforming_mode, - uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], - uint16_t n_RB_ULBWP, - uint16_t n_RB_DLBWP, - uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES], - NR_DCI_INFO_EXTRACTED_t *nr_dci_info_extracted); /** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs - RB extraction (signal and channel estimates) @@ -1795,20 +1756,11 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint8_t is_crnti, uint8_t llr8_flag); -int nr_extract_dci_info(PHY_VARS_NR_UE *ue, - uint8_t eNB_id, - lte_frame_type_t frame_type, - uint8_t dci_length, - uint16_t rnti, - uint64_t dci_pdu[2], - fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted, - uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], - NR_DCI_format_t dci_format, - uint8_t nr_tti_rx, - uint16_t n_RB_ULBWP, - uint16_t n_RB_DLBWP, - uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]); + + +int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf ); void *dlsch_thread(void *arg); /**@}*/ #endif + diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h index 39b037a600..fb560f229d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h @@ -42,6 +42,8 @@ #include "UTIL/LISTS/list.h" #endif +#include "LAYER2/NR_MAC_gNB/mac_proto.h" + //#include "../LTE_TRANSPORT/transport_common.h" // structures below implement 36-211 and 36-212 @@ -127,9 +129,9 @@ typedef struct { /// LDPC-code outputs uint8_t *d[MAX_NUM_NR_ULSCH_SEGMENTS]; /// LDPC-code outputs (TS 36.212 V15.4.0, Sec 5.3.2 p. 17) - uint8_t e[MAX_NUM_NR_CHANNEL_BITS] __attribute__((aligned(32))); + uint8_t *e; /// Rate matching (Interleaving) outputs (TS 36.212 V15.4.0, Sec 5.4.2.2 p. 30) - uint8_t f[MAX_NUM_NR_CHANNEL_BITS] __attribute__((aligned(32))); + uint8_t *f; /// Number of code segments uint32_t C; /// Number of bits in code segments @@ -240,6 +242,8 @@ typedef struct { int16_t Po_SRS; /// num active cba group uint8_t num_active_cba_groups; + /// bit mask of PT-RS ofdm symbol indicies + uint16_t ptrs_symbols; /// num dci found for cba //uint8_t num_cba_dci[10]; /// allocated CBA RNTI @@ -278,13 +282,13 @@ typedef struct { /// MIMO mode for this DLSCH MIMO_nrmode_t mimo_mode; /// soft bits for each received segment ("w"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) - int16_t w[MAX_NUM_NR_DLSCH_SEGMENTS][3*8448]; + int16_t *w[MAX_NUM_NR_DLSCH_SEGMENTS]; /// for abstraction soft bits for each received segment ("w"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) //double w_abs[MAX_NUM_NR_DLSCH_SEGMENTS][3*8448]; /// soft bits for each received segment ("d"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) int16_t *d[MAX_NUM_NR_DLSCH_SEGMENTS]; /// LDPC processing buffers - t_nrLDPC_procBuf* p_nrLDPC_procBuf[MAX_NUM_DLSCH_SEGMENTS]; + t_nrLDPC_procBuf* p_nrLDPC_procBuf[MAX_NUM_NR_DLSCH_SEGMENTS]; /// Number of code segments uint32_t C; /// Number of bits in code segments @@ -299,12 +303,20 @@ typedef struct { int8_t delta_PUCCH; /// Number of soft channel bits uint32_t G; + /// Start PRB of BWP + uint16_t BWPStart; + /// Number of PRBs in BWP + uint16_t BWPSize; /// Current Number of RBs uint16_t nb_rb; /// Starting RB number uint16_t start_rb; /// Number of Symbols uint16_t nb_symbols; + /// DMRS symbol positions + uint16_t dlDmrsSymbPos; + /// DMRS Configuration Type + uint8_t dmrsConfigType; /// Starting Symbol number uint16_t start_symbol; /// Current subband PMI allocation diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c index 2eb6dcd7fe..55bac90520 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c @@ -36,13 +36,14 @@ #include "PHY/CODING/coding_defs.h" #include "PHY/CODING/coding_extern.h" #include "PHY/CODING/lte_interleaver_inline.h" -#include "PHY/CODING/nrLDPC_encoder/defs.h" +#include "PHY/CODING/nrLDPC_extern.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_ue.h" #include "common/utils/LOG/vcd_signal_dumper.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" +void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulschptr,unsigned char N_RB_UL) -void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulschptr) { int i, r; NR_UE_ULSCH_t *ulsch = *ulschptr; @@ -52,18 +53,35 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulschptr) printf("Freeing ulsch %p\n",ulsch); #endif + uint16_t a_segments = MAX_NUM_NR_ULSCH_SEGMENTS; //number of segments to be allocated + + if (N_RB_UL != 273) { + a_segments = a_segments*N_RB_UL; + a_segments = a_segments/273; + } + + uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment + for (i=0; iharq_processes[i]) { if (ulsch->harq_processes[i]->a) { - free16(ulsch->harq_processes[i]->a,MAX_NR_ULSCH_PAYLOAD_BYTES); + free16(ulsch->harq_processes[i]->a,ulsch_bytes); ulsch->harq_processes[i]->a = NULL; } if (ulsch->harq_processes[i]->b) { - free16(ulsch->harq_processes[i]->b,MAX_NR_ULSCH_PAYLOAD_BYTES); + free16(ulsch->harq_processes[i]->b,ulsch_bytes); ulsch->harq_processes[i]->b = NULL; } - for (r=0; rharq_processes[i]->e) { + free16(ulsch->harq_processes[i]->e,14*N_RB_UL*12*8); + ulsch->harq_processes[i]->e = NULL; + } + if (ulsch->harq_processes[i]->f) { + free16(ulsch->harq_processes[i]->f,14*N_RB_UL*12*8); + ulsch->harq_processes[i]->f = NULL; + } + for (r=0; rharq_processes[i]->c[r]) { free16(ulsch->harq_processes[i]->c[r],((r==0)?8:0) + 3+768); ulsch->harq_processes[i]->c[r] = NULL; @@ -87,24 +105,20 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulschptr) } -NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, +NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag) { NR_UE_ULSCH_t *ulsch; unsigned char exit_flag = 0,i,r; - unsigned char bw_scaling =1; + uint16_t a_segments = MAX_NUM_NR_ULSCH_SEGMENTS; //number of segments to be allocated - switch (N_RB_UL) { + if (N_RB_UL != 273) { + a_segments = a_segments*N_RB_UL; + a_segments = a_segments/273; + } - case 106: - bw_scaling =2; - break; - - default: - bw_scaling =1; - break; - } + uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment ulsch = (NR_UE_ULSCH_t *)malloc16(sizeof(NR_UE_ULSCH_t)); @@ -124,25 +138,25 @@ NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, // printf("ulsch->harq_processes[%d] %p\n",i,ulsch->harq_processes[i]); if (ulsch->harq_processes[i]) { memset(ulsch->harq_processes[i], 0, sizeof(NR_UL_UE_HARQ_t)); - ulsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_NR_ULSCH_PAYLOAD_BYTES/bw_scaling); - ulsch->harq_processes[i]->a = (unsigned char*)malloc16(MAX_NR_ULSCH_PAYLOAD_BYTES/bw_scaling); + ulsch->harq_processes[i]->b = (uint8_t*)malloc16(ulsch_bytes); + ulsch->harq_processes[i]->a = (unsigned char*)malloc16(ulsch_bytes); if (ulsch->harq_processes[i]->a) { - bzero(ulsch->harq_processes[i]->a,MAX_NR_ULSCH_PAYLOAD_BYTES/bw_scaling); + bzero(ulsch->harq_processes[i]->a,ulsch_bytes); } else { printf("Can't allocate PDU\n"); exit_flag=1; } if (ulsch->harq_processes[i]->b) - bzero(ulsch->harq_processes[i]->b,MAX_NR_ULSCH_PAYLOAD_BYTES/bw_scaling); + bzero(ulsch->harq_processes[i]->b,ulsch_bytes); else { LOG_E(PHY,"Can't get b\n"); exit_flag=1; } if (abstraction_flag==0) { - for (r=0; rharq_processes[i]->c[r] = (uint8_t*)malloc16(8448); ulsch->harq_processes[i]->d[r] = (uint8_t*)malloc16(68*384); //max size for coded output @@ -160,6 +174,20 @@ NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, exit_flag=2; } } + ulsch->harq_processes[i]->e = (uint8_t*)malloc16(14*N_RB_UL*12*8); + if (ulsch->harq_processes[i]->e) { + bzero(ulsch->harq_processes[i]->e,14*N_RB_UL*12*8); + } else { + printf("Can't get e\n"); + exit_flag=1; + } + ulsch->harq_processes[i]->f = (uint8_t*)malloc16(14*N_RB_UL*12*8); + if (ulsch->harq_processes[i]->f) { + bzero(ulsch->harq_processes[i]->f,14*N_RB_UL*12*8); + } else { + printf("Can't get f\n"); + exit_flag=1; + } } ulsch->harq_processes[i]->subframe_scheduling_flag = 0; @@ -180,7 +208,7 @@ NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, } LOG_E(PHY,"new_ue_ulsch exit flag, size of %d , %zu\n",exit_flag, sizeof(LTE_UE_ULSCH_t)); - free_nr_ue_ulsch(&ulsch); + free_nr_ue_ulsch(&ulsch,N_RB_UL); return(NULL); @@ -240,13 +268,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, /////////// ///////////////////////////////////////////////////////////////////////////////////////// - /* - uint8_t *channel_input[MAX_NUM_DLSCH_SEGMENTS]; //unsigned char - for(j=0;jNl = %d\n", nb_rb,nb_symb_sch, nb_re_dmrs,length_dmrs, harq_process->Nl); @@ -270,17 +292,35 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, printf("%02x.",a[i]); printf("\n"); */ - // Add 24-bit crc (polynomial A) to payload - crc = crc24a(harq_process->a,A)>>8; - harq_process->a[A>>3] = ((uint8_t*)&crc)[2]; - harq_process->a[1+(A>>3)] = ((uint8_t*)&crc)[1]; - harq_process->a[2+(A>>3)] = ((uint8_t*)&crc)[0]; - //printf("CRC %x (A %d)\n",crc,A); - //printf("a0 %d a1 %d a2 %d\n", a[A>>3], a[1+(A>>3)], a[2+(A>>3)]); + if (A > 3824) { + // Add 24-bit crc (polynomial A) to payload + crc = crc24a(harq_process->a,A)>>8; + harq_process->a[A>>3] = ((uint8_t*)&crc)[2]; + harq_process->a[1+(A>>3)] = ((uint8_t*)&crc)[1]; + harq_process->a[2+(A>>3)] = ((uint8_t*)&crc)[0]; + //printf("CRC %x (A %d)\n",crc,A); + //printf("a0 %d a1 %d a2 %d\n", a[A>>3], a[1+(A>>3)], a[2+(A>>3)]); - harq_process->B = A+24; + harq_process->B = A+24; - memcpy(harq_process->b,harq_process->a,(A/8)+4); + AssertFatal((A/8)+4 <= MAX_NR_ULSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_NR_ULSCH_PAYLOAD_BYTES); + + memcpy(harq_process->b,harq_process->a,(A/8)+4); + } + else { + // Add 16-bit crc (polynomial A) to payload + crc = crc16(harq_process->a,A)>>16; + harq_process->a[A>>3] = ((uint8_t*)&crc)[1]; + harq_process->a[1+(A>>3)] = ((uint8_t*)&crc)[0]; + //printf("CRC %x (A %d)\n",crc,A); + //printf("a0 %d a1 %d \n", a[A>>3], a[1+(A>>3)]); + + harq_process->B = A+16; + + AssertFatal((A/8)+3 <= MAX_NR_ULSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_NR_ULSCH_PAYLOAD_BYTES); + + memcpy(harq_process->b,harq_process->a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc + } /////////// /////////////////////////////////////////////////////////////////////////// @@ -353,8 +393,11 @@ opp_enabled=0; printf("%d \n", harq_process->d[0][cnt]); } printf("\n");*/ + encoder_implemparams_t impp; + impp.n_segments=harq_process->C; + impp.macro_num=0; - ldpc_encoder_optim_8seg(harq_process->c,harq_process->d,*pz,Kb,Kr,BG,harq_process->C,NULL,NULL,NULL,NULL); + nrLDPC_encoder(harq_process->c,harq_process->d,*pz,Kb,Kr,BG,&impp); //stop_meas(te_stats); //printf("end ldpc encoder -- output\n"); @@ -405,6 +448,8 @@ opp_enabled=0; harq_process->d[r], harq_process->e+r_offset, harq_process->C, + F, + Kr-F-2*(*pz), harq_process->rvidx, E); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index b912834f9d..f1d4a304f9 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -31,6 +31,7 @@ */ #include #include "PHY/NR_REFSIG/dmrs_nr.h" +#include "PHY/NR_REFSIG/ptrs_nr.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_ue.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/MODULATION/nr_modulation.h" @@ -105,27 +106,28 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, int32_t **txdataF; uint16_t start_sc, start_rb; int8_t Wf[2], Wt[2], l_prime[2], delta; - uint16_t n_dmrs, code_rate, number_dmrs_symbols; + uint16_t n_dmrs, code_rate, number_dmrs_symbols, k; uint8_t dmrs_type; - uint8_t mapping_type; int ap, start_symbol, Nid_cell, i; int sample_offsetF, N_RE_prime, N_PRB_oh; uint16_t n_rnti; uint8_t data_existing =0; + uint8_t L_ptrs, K_ptrs; // PTRS parameters + uint16_t beta_ptrs; // PTRS parameter related to power control NR_UE_ULSCH_t *ulsch_ue; NR_UL_UE_HARQ_t *harq_process_ul_ue; NR_DL_FRAME_PARMS *frame_parms = &UE->frame_parms; NR_UE_PUSCH *pusch_ue = UE->pusch_vars[thread_id][gNB_id]; uint8_t ulsch_input_buffer[MAX_ULSCH_PAYLOAD_BYTES]; + ptrs_UplinkConfig_t *ptrs_Uplink_Config = &UE->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig; num_of_codewords = 1; // tmp assumption n_rnti = 0x1234; Nid_cell = 0; N_PRB_oh = 0; // higher layer (RRC) parameter xOverhead in PUSCH-ServingCellConfig number_dmrs_symbols = 0; - - mapping_type = UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; + uint8_t mapping_type = UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; for (cwd_index = 0;cwd_index < num_of_codewords; cwd_index++) { @@ -135,23 +137,23 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, start_symbol = harq_process_ul_ue->start_symbol; for (i = start_symbol; i < start_symbol + harq_process_ul_ue->number_of_symbols; i++) - number_dmrs_symbols += is_dmrs_symbol(i, + number_dmrs_symbols += is_dmrs_symbol((mapping_type)?i-start_symbol:i, 0, 0, 0, 0, 0, harq_process_ul_ue->number_of_symbols, - &UE->dmrs_UplinkConfig, - mapping_type, + UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, frame_parms->ofdm_symbol_size); - ulsch_ue->length_dmrs = UE->dmrs_UplinkConfig.pusch_maxLength; + ulsch_ue->length_dmrs = number_dmrs_symbols; // pusch.MaxLenght is redundant here as number_dmrs_symbols + // contains all dmrs symbols even for double symbol dmrs ulsch_ue->rnti = n_rnti; ulsch_ue->Nid_cell = Nid_cell; - ulsch_ue->nb_re_dmrs = ((UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; + ulsch_ue->nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4); - N_RE_prime = NR_NB_SC_PER_RB*harq_process_ul_ue->number_of_symbols - ulsch_ue->nb_re_dmrs - N_PRB_oh; + N_RE_prime = NR_NB_SC_PER_RB*harq_process_ul_ue->number_of_symbols - ulsch_ue->nb_re_dmrs*number_dmrs_symbols - N_PRB_oh; harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*harq_process_ul_ue->nb_rb*num_of_codewords; @@ -172,6 +174,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, // to be removed later when MAC is ready if (harq_process_ul_ue != NULL){ + data_existing = 0; if (IS_SOFTMODEM_NOS1){ data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame, @@ -189,31 +192,22 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, printf("\n"); #endif } - //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity - else{ - //Use zeros for the header bytes in noS1 mode, in order to make sure that the LCID is not valid - //and block this traffic from being forwarded to the upper layers at the gNB - uint16_t payload_offset = 5; - LOG_D(PHY, "Random data to be tranmsitted: \n"); - //Give the header bytes some dummy value in order to block the random packet at the MAC layer of the receiver - for (i = 0; ia[i] = 0; + } + //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity + if (!IS_SOFTMODEM_NOS1 || !data_existing) { + //Use zeros for the header bytes in noS1 mode, in order to make sure that the LCID is not valid + //and block this traffic from being forwarded to the upper layers at the gNB + uint16_t payload_offset = 5; + LOG_D(PHY, "Random data to be tranmsitted: \n"); + //Give the header bytes some dummy value in order to block the random packet at the MAC layer of the receiver + for (i = 0; ia[i] = 0; - for (i = payload_offset; i < harq_process_ul_ue->TBS / 8; i++) { - harq_process_ul_ue->a[i] = (unsigned char) rand(); - //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); - } - } - } - //else if(uplink_counter == 0){ //if(!IS_SOFTMODEM_NOS1){ - else{ - LOG_D(PHY, "Random data to be tranmsitted: \n"); - for (i = 0; i < harq_process_ul_ue->TBS / 8; i++) { - harq_process_ul_ue->a[i] = (unsigned char) rand(); - //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); - } - //uplink_counter++; + for (i = payload_offset; i < harq_process_ul_ue->TBS / 8; i++) { + harq_process_ul_ue->a[i] = (unsigned char) rand(); + //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); } + } } else { LOG_E(PHY, "[phy_procedures_nrUE_TX] harq_process_ul_ue is NULL !!\n"); return; @@ -275,12 +269,41 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////DMRS Modulation///////////////////////// /////////// pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; - n_dmrs = (harq_process_ul_ue->nb_rb*ulsch_ue->nb_re_dmrs); + n_dmrs = (harq_process_ul_ue->nb_rb*ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs); int16_t mod_dmrs[n_dmrs<<1]; - dmrs_type = UE->dmrs_UplinkConfig.pusch_dmrs_type; + dmrs_type = UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type; /////////// //////////////////////////////////////////////////////////////////////// + + /////////////////////////PTRS parameters' initialization///////////////////////// + /////////// + + int16_t mod_ptrs[(harq_process_ul_ue->nb_rb/2)*(NR_SYMBOLS_PER_SLOT-1)*2]; // assume maximum number of PTRS per pusch allocation + K_ptrs = 0; // just to avoid a warning + + if (UE->ptrs_configured == 1) { + + K_ptrs = get_K_ptrs(ptrs_Uplink_Config, harq_process_ul_ue->nb_rb); + + L_ptrs = get_L_ptrs(ptrs_Uplink_Config, harq_process_ul_ue->mcs); + + beta_ptrs = 1; // temp value until power control is implemented + + ulsch_ue->ptrs_symbols = 0; + + set_ptrs_symb_idx(&ulsch_ue->ptrs_symbols, + harq_process_ul_ue->number_of_symbols, + start_symbol, + dmrs_type, + L_ptrs, + ulsch_ue->length_dmrs, + frame_parms->ofdm_symbol_size); + } + + /////////// + //////////////////////////////////////////////////////////////////////////////// + /////////////////////////ULSCH layer mapping///////////////////////// /////////// @@ -306,15 +329,14 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, for (l = start_symbol; l < start_symbol + harq_process_ul_ue->number_of_symbols; l++) { - is_dmrs = is_dmrs_symbol(l, + is_dmrs = is_dmrs_symbol((mapping_type)?l-start_symbol:l, 0, 0, 0, 0, 0, harq_process_ul_ue->number_of_symbols, - &UE->dmrs_UplinkConfig, - mapping_type, + dmrs_type, frame_parms->ofdm_symbol_size); if (is_dmrs == 1) @@ -357,35 +379,54 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t k_prime=0; - uint8_t is_dmrs; - uint16_t m=0, n=0, dmrs_idx=0, k=0; + uint8_t is_dmrs, is_ptrs; + uint8_t l_ref; + uint16_t m=0, n=0, dmrs_idx=0, ptrs_idx = 0; for (l=start_symbol; lnumber_of_symbols; l++) { k = start_sc; n = 0; dmrs_idx = 0; + l_ref = (mapping_type) ? l-start_symbol : l; for (i=0; inb_rb*NR_NB_SC_PER_RB; i++) { sample_offsetF = l*frame_parms->ofdm_symbol_size + k; is_dmrs = 0; + is_ptrs = 0; - is_dmrs = is_dmrs_symbol(l, + is_dmrs = is_dmrs_symbol(l_ref, k, start_sc, k_prime, n, delta, harq_process_ul_ue->number_of_symbols, - &UE->dmrs_UplinkConfig, - mapping_type, + dmrs_type, frame_parms->ofdm_symbol_size); + if (UE->ptrs_configured == 1){ + is_ptrs = is_ptrs_symbol(l, + k, + ulsch_ue->rnti, + harq_process_ul_ue->nb_rb, + harq_process_ul_ue->number_of_symbols, + ap, + K_ptrs, + ulsch_ue->ptrs_symbols, + start_sc, + frame_parms->ofdm_symbol_size, + UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, + ptrs_Uplink_Config->resourceElementOffset); + } + if (is_dmrs == 1) { - nr_modulation(pusch_dmrs[l][0], n_dmrs*2, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated + if (k == start_sc){ + nr_modulation(pusch_dmrs[l][0], n_dmrs*2, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated + } ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = (Wt[l_prime[0]]*Wf[k_prime]*AMP*mod_dmrs[dmrs_idx<<1]) >> 15; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = (Wt[l_prime[0]]*Wf[k_prime]*AMP*mod_dmrs[(dmrs_idx<<1) + 1]) >> 15; @@ -401,9 +442,19 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, k_prime++; k_prime&=1; n+=(k_prime)?0:1; - } - else { + } else if (is_ptrs == 1) { + + if (k == start_sc){ + nr_modulation(pusch_dmrs[l][0], harq_process_ul_ue->nb_rb/2, DMRS_MOD_ORDER, mod_ptrs); + } + + ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = (beta_ptrs*AMP*mod_ptrs[ptrs_idx<<1]) >> 15; + ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = (beta_ptrs*AMP*mod_ptrs[(ptrs_idx<<1) + 1]) >> 15; + + ptrs_idx++; + + } else { ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; @@ -454,7 +505,7 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, timing_advance = 0; #endif - tx_offset = slot*frame_parms->samples_per_slot - timing_advance; + tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0) - timing_advance; if (tx_offset < 0) tx_offset += frame_parms->samples_per_frame; @@ -484,6 +535,7 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, frame_parms); } } + /////////// //////////////////////////////////////////////////// return 0; diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c index b13cd008b5..e8eceb77a6 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c @@ -880,7 +880,7 @@ int pss_search_time_nr(int **rxdata, ///rx data in time domain /* perform correlation of rx data and pss sequence ie it is a dot product */ result = dot_product64((short*)primary_synchro_time_nr[pss_index], - (short*) &(rxdata[ar][n])+(is*frame_parms->samples_per_frame), + (short*) &(rxdata[ar][n+is*frame_parms->samples_per_frame]), frame_parms->ofdm_symbol_size, shift); pss_corr_ue[pss_index][n] += abs64(result); @@ -914,13 +914,13 @@ int pss_search_time_nr(int **rxdata, ///rx data in time domain int64_t result1,result2; // Computing cross-correlation at peak on half the symbol size for first half of data result1 = dot_product64((short*)primary_synchro_time_nr[pss_source], - (short*) &(rxdata[0][peak_position])+(is*frame_parms->samples_per_frame), + (short*) &(rxdata[0][peak_position+is*frame_parms->samples_per_frame]), frame_parms->ofdm_symbol_size>>1, shift); // Computing cross-correlation at peak on half the symbol size for data shifted by half symbol size // as it is real and complex it is necessary to shift by a value equal to symbol size to obtain such shift result2 = dot_product64((short*)primary_synchro_time_nr[pss_source]+(frame_parms->ofdm_symbol_size), - (short*) &(rxdata[0][peak_position])+(frame_parms->ofdm_symbol_size+(is*frame_parms->samples_per_frame)), + (short*) &(rxdata[0][peak_position+is*frame_parms->samples_per_frame])+frame_parms->ofdm_symbol_size, frame_parms->ofdm_symbol_size>>1, shift); diff --git a/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c index 3d36822956..44d500b0b7 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c @@ -341,7 +341,7 @@ int do_pss_sss_extract_nr(PHY_VARS_NR_UE *ue, pss_rxF_ext = &pss_ext[aarx][0]; sss_rxF_ext = &sss_ext[aarx][0]; - unsigned int k = frame_parms->first_carrier_offset + frame_parms->ssb_start_subcarrier + 56; + unsigned int k = frame_parms->first_carrier_offset + frame_parms->ssb_start_subcarrier + 56; if (k>= frame_parms->ofdm_symbol_size) k-=frame_parms->ofdm_symbol_size; for (int i=0; i < LENGTH_PSS_NR; i++) { diff --git a/openair1/PHY/TOOLS/Makefile b/openair1/PHY/TOOLS/Makefile index 870bcfe318..c71717dc87 100644 --- a/openair1/PHY/TOOLS/Makefile +++ b/openair1/PHY/TOOLS/Makefile @@ -2,13 +2,15 @@ lte_dfts_sse4: lte_dfts.c gcc-7 -O3 -std=gnu99 -msse4.1 -o lte_dfts_sse4 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS lte_dfts_avx2: lte_dfts.c - gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o lte_dfts_avx2 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS + gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o lte_dfts_avx2 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS lte_dfts_avx2.s: lte_dfts.c - gcc -O2 -std=gnu99 -mavx2 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS + gcc -O2 -std=gnu99 -mavx2 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS + lte_dfts_sse4.s: lte_dfts.c - gcc -O2 -std=gnu99 -msse4.1 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm # -DD256STATS #-DD64STATS + gcc -O2 -std=gnu99 -msse4.1 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS + dft_cycles_avx2: lte_dfts_avx2 ./lte_dfts_avx2 | egrep cycles diff --git a/openair1/PHY/TOOLS/lte_dfts.c b/openair1/PHY/TOOLS/lte_dfts.c index 59369a3bc0..2de8653ab3 100644 --- a/openair1/PHY/TOOLS/lte_dfts.c +++ b/openair1/PHY/TOOLS/lte_dfts.c @@ -2573,7 +2573,7 @@ const static int16_t tw64c[96] __attribute__((aligned(32))) = { #define simd256_q15_t __m256i #define shiftright_int16_simd256(a,shift) _mm256_srai_epi16(a,shift) #define set1_int16_simd256(a) _mm256_set1_epi16(a); -#define mulhi_int16_simd256(a,b) _mm256_slli_epi16(_mm256_mulhi_epi16(a,b),1); +#define mulhi_int16_simd256(a,b) _mm256_mulhrs_epi16(a,b); //_mm256_slli_epi16(_mm256_mulhi_epi16(a,b),1); #endif #elif defined(__arm__) @@ -4836,22 +4836,22 @@ void idft4096(int16_t *x,int16_t *y,int scale) if (scale>0) { for (i=0; i<64; i++) { - y128[0] = shiftright_int16(y128[0],1); - y128[1] = shiftright_int16(y128[1],1); - y128[2] = shiftright_int16(y128[2],1); - y128[3] = shiftright_int16(y128[3],1); - y128[4] = shiftright_int16(y128[4],1); - y128[5] = shiftright_int16(y128[5],1); - y128[6] = shiftright_int16(y128[6],1); - y128[7] = shiftright_int16(y128[7],1); - y128[8] = shiftright_int16(y128[8],1); - y128[9] = shiftright_int16(y128[9],1); - y128[10] = shiftright_int16(y128[10],1); - y128[11] = shiftright_int16(y128[11],1); - y128[12] = shiftright_int16(y128[12],1); - y128[13] = shiftright_int16(y128[13],1); - y128[14] = shiftright_int16(y128[14],1); - y128[15] = shiftright_int16(y128[15],1); + y128[0] = shiftright_int16(y128[0],scale); + y128[1] = shiftright_int16(y128[1],scale); + y128[2] = shiftright_int16(y128[2],scale); + y128[3] = shiftright_int16(y128[3],scale); + y128[4] = shiftright_int16(y128[4],scale); + y128[5] = shiftright_int16(y128[5],scale); + y128[6] = shiftright_int16(y128[6],scale); + y128[7] = shiftright_int16(y128[7],scale); + y128[8] = shiftright_int16(y128[8],scale); + y128[9] = shiftright_int16(y128[9],scale); + y128[10] = shiftright_int16(y128[10],scale); + y128[11] = shiftright_int16(y128[11],scale); + y128[12] = shiftright_int16(y128[12],scale); + y128[13] = shiftright_int16(y128[13],scale); + y128[14] = shiftright_int16(y128[14],scale); + y128[15] = shiftright_int16(y128[15],scale); y128+=16; } @@ -5692,6 +5692,18 @@ void dft6144(int16_t *input, int16_t *output,int scale) } +int16_t twa9216[6144] __attribute__((aligned(32))); +int16_t twb9216[6144] __attribute__((aligned(32))); +// 3072 x 3 +void dft9216(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + +void idft9216(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} int16_t twa12288[8192] __attribute__((aligned(32))); int16_t twb12288[8192] __attribute__((aligned(32))); @@ -6042,6 +6054,59 @@ void idft24576(int16_t *input, int16_t *output,int scale) } } +int16_t twa36864[24576] __attribute__((aligned(32))); +int16_t twb36884[24576] __attribute__((aligned(32))); +// 12288 x 3 +void dft36864(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} +void idft36864(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + +int16_t twa49152[32768] __attribute__((aligned(32))); +int16_t twb49152[32768] __attribute__((aligned(32))); +// 16384 x 3 +void dft49152(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + +void idft49152(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + +int16_t twa73728[49152] __attribute__((aligned(32))); +int16_t twb73728[49152] __attribute__((aligned(32))); +// 24576 x 3 +void dft73728(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + +void idft73728(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + + +int16_t twa98304[49152] __attribute__((aligned(32))); +int16_t twb98304[49152] __attribute__((aligned(32))); +// 32768 x 3 +void dft98304(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + +void idft98304(int16_t *input, int16_t *output,int scale) { + + AssertFatal(1==0,"Need to do this ..\n"); +} + + /// THIS SECTION IS FOR ALL PUSCH DFTS (i.e. radix 2^a * 3^b * 4^c * 5^d) /// They use twiddles for 4-way parallel DFTS (i.e. 4 DFTS with interleaved input/output) @@ -8526,6 +8591,8 @@ void dft1200(int16_t *x,int16_t *y,unsigned char scale_flag) } +//#define round trunc + void init_rad4(int N,int16_t *tw) { int16_t *twa = tw; @@ -8695,6 +8762,8 @@ void init_dfts(void) init_rad4_rep(1200,twa1200,twb1200,twc1200); } +//#undef round + #ifdef MR_MAIN #include #include @@ -8862,9 +8931,9 @@ int main(int argc, char**argv) time_stats_t ts; #ifdef __AVX2__ - simd256_q15_t x[4096],y[4096],tw0,tw1,tw2,tw3; + simd256_q15_t x[4096],x2[4096],y[4096],tw0,tw1,tw2,tw3; #else - simd_q15_t x[8192],y[8192],tw0,tw1,tw2,tw3; + simd_q15_t x[8192],x2[8192],y[8192],tw0,tw1,tw2,tw3; #endif int i; simd_q15_t *x128=(simd_q15_t*)x,*y128=(simd_q15_t*)y; @@ -9351,8 +9420,8 @@ int main(int argc, char**argv) write_output("x3072.m","x3072",x,3072,1,1); - memset((void*)x,0,2048*sizeof(int32_t)); - for (i=2;i<2402;i++) { + memset((void*)x,0,4096*sizeof(int32_t)); + for (i=0;i<2400;i++) { if ((taus() & 1)==0) ((int16_t*)x)[i] = 364; else @@ -9376,6 +9445,9 @@ int main(int argc, char**argv) LOG_M("y4096.m","y4096",y,4096,1,1); LOG_M("x4096.m","x4096",x,4096,1,1); + dft4096((int16_t *)y,(int16_t *)x2,1); + LOG_M("x4096_2.m","x4096_2",x2,4096,1,1); + // NR 160Mhz, 434 PRB, 3/4 sampling memset((void*)x, 0, 6144*sizeof(int32_t)); for (i=2;i<5010;i++) { diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 66ac415872..40803c30f4 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -152,36 +152,36 @@ FD_phy_scope_gnb *create_phy_scope_gnb( void ) void phy_scope_gNB(FD_phy_scope_gnb *form, PHY_VARS_gNB *phy_vars_gnb, + RU_t *phy_vars_ru, int UE_id) { - int i,i2,arx,atx,ind,k; + int i, arx; //int i,i2,arx,atx,ind,k; NR_DL_FRAME_PARMS *frame_parms = &phy_vars_gnb->frame_parms; int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE - int16_t **rxsig_t; - int16_t **chest_t=NULL; - int16_t **chest_f=NULL; - int16_t *pusch_llr=NULL; - int32_t *pusch_comp=NULL; - int32_t *pucch1_comp=NULL; - int32_t *pucch1_thres=NULL; - int32_t *pucch1ab_comp=NULL; - float Re,Im,ymax; + int16_t **rxsig_t, **rxsig_f; + // int16_t **chest_t=NULL; + // int16_t **chest_f=NULL; + // int16_t *pusch_llr=NULL; + // int32_t *pusch_comp=NULL; + // int32_t *pucch1_comp=NULL; + // int32_t *pucch1_thres=NULL; + // int32_t *pucch1ab_comp=NULL; + // float Re,Im,ymax; float *llr, *bit; - float I[nsymb_ce*2], Q[nsymb_ce*2]; - float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; - float rxsig_t_dB[nb_antennas_rx][FRAME_LENGTH_COMPLEX_SAMPLES]; - float chest_t_abs[nb_antennas_rx][frame_parms->ofdm_symbol_size]; - float *chest_f_abs; - float time[FRAME_LENGTH_COMPLEX_SAMPLES]; - float time2[2048]; - float freq[nsymb_ce*nb_antennas_rx*nb_antennas_tx]; - uint32_t total_dlsch_bitrate = phy_vars_gnb->total_dlsch_bitrate; + // float I[nsymb_ce*2], Q[nsymb_ce*2]; + // float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; + float *rxsig_t_dB[nb_antennas_rx]; + float *rxsig_f_dB[nb_antennas_rx]; + float time[frame_parms->samples_per_frame]; + // float freq[nsymb_ce*nb_antennas_rx*nb_antennas_tx]; + // uint32_t total_dlsch_bitrate = phy_vars_gnb->total_dlsch_bitrate; int coded_bits_per_codeword = 0; - uint8_t harq_pid; // in TDD config 3 it is sf-2, i.e., can be 0,1,2 + // uint8_t harq_pid; // in TDD config 3 it is sf-2, i.e., can be 0,1,2 int Qm = 2; + /* if (!RC.nrmac[0]->UE_list.active[UE_id]) return; @@ -191,14 +191,18 @@ void phy_scope_gNB(FD_phy_scope_gnb *form, //Qm = cmax(phy_vars_gnb->ulsch[UE_id][0]->harq_processes->Qm,Qm); } } - + */ coded_bits_per_codeword = frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti; - chest_f_abs = (float*) calloc(nsymb_ce*nb_antennas_rx*nb_antennas_tx,sizeof(float)); + for (arx=0; arxsamples_per_frame,sizeof(float)); + rxsig_f_dB[arx] = (float*) calloc(frame_parms->samples_per_slot_wCP,sizeof(float)); + } llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero bit = malloc(coded_bits_per_codeword*sizeof(float)); - rxsig_t = (int16_t**) phy_vars_gnb->common_vars.rxdata; + rxsig_t = (int16_t**) phy_vars_ru->common.rxdata; + rxsig_f = (int16_t**) phy_vars_ru->common.rxdataF; //chest_t = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates_time[eNB_id]; /* chest_t = (int16_t**) phy_vars_gnb->srs_vars[UE_id].srs_ch_estimates; chest_f = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates; @@ -212,25 +216,26 @@ void phy_scope_gNB(FD_phy_scope_gnb *form, // Received signal in time domain of receive antenna 0 if (rxsig_t != NULL) { if (rxsig_t[0] != NULL) { - for (i=0; isamples_per_frame; i++) { rxsig_t_dB[0][i] = 10*log10(1.0+(float) ((rxsig_t[0][2*i])*(rxsig_t[0][2*i])+(rxsig_t[0][2*i+1])*(rxsig_t[0][2*i+1]))); time[i] = (float) i; } - fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],FRAME_LENGTH_COMPLEX_SAMPLES,"","",""); + fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],frame_parms->samples_per_frame,"","",""); } for (arx=1; arxsamples_per_frame; i++) { rxsig_t_dB[arx][i] = 10*log10(1.0+(float) ((rxsig_t[arx][2*i])*(rxsig_t[arx][2*i])+(rxsig_t[arx][2*i+1])*(rxsig_t[arx][2*i+1]))); } - fl_add_xyplot_overlay(form->rxsig_t,arx,time,rxsig_t_dB[arx],FRAME_LENGTH_COMPLEX_SAMPLES,rx_antenna_colors[arx]); + fl_add_xyplot_overlay(form->rxsig_t,arx,time,rxsig_t_dB[arx],frame_parms->samples_per_frame,rx_antenna_colors[arx]); } } } + /* // Channel Impulse Response if (chest_t != NULL) { ymax = 0; @@ -268,12 +273,22 @@ void phy_scope_gNB(FD_phy_scope_gnb *form, // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); fl_set_xyplot_ybounds(form->chest_t,0,ymax); } - + */ + // Channel Frequency Response - if (chest_f != NULL) { - ind = 0; + if (rxsig_f != NULL) { + if (rxsig_f[0] != NULL) { + for (i=0; isamples_per_slot_wCP; i++) { + rxsig_f_dB[0][i] = 10*log10(1.0+(float) ((rxsig_f[0][2*i])*(rxsig_f[0][2*i])+(rxsig_f[0][2*i+1])*(rxsig_f[0][2*i+1]))); + time[i] = (float) i; + } + + fl_set_xyplot_data(form->chest_t,time,rxsig_f_dB[0],frame_parms->samples_per_slot_wCP,"","",""); + } + } + + /* - for (atx=0; atxpusch_tput,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","",""); // fl_get_xyplot_ybounds(form->pusch_tput,&ymin,&ymax); // fl_set_xyplot_ybounds(form->pusch_tput,0,ymax); + */ + fl_check_forms(); free(llr); free(bit); - free(chest_f_abs); } FD_phy_scope_nrue *create_phy_scope_nrue( void ) @@ -492,7 +508,7 @@ void phy_scope_nrUE(FD_phy_scope_nrue *form, //int nsymb_ce = frame_parms->ofdm_symbol_size;//*frame_parms->symbols_per_tti; int samples_per_frame = frame_parms->samples_per_frame; uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_eNB; + uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB; int16_t **rxsig_t; float **rxsig_t_dB; float *time; @@ -863,11 +879,10 @@ typedef struct { // current status is that every UE has a DL scope for a SINGLE eNB (gnb_id=0) // at eNB 0, an UL scope for every UE -//FD_phy_scope_gnb *form_gnb[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; -static FD_phy_scope_gnb *form_gnb[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; +FD_phy_scope_gnb *form_gnb[NUMBER_OF_UE_MAX]; //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; //char title[255]; -unsigned char scope_enb_num_ue = 2; +unsigned char scope_enb_num_ue = 1; //static pthread_t forms_thread; //xforms @@ -896,7 +911,7 @@ void reset_stats_gNB(FL_OBJECT *button, static void *scope_thread_gNB(void *arg) { - int UE_id, CC_id; + int UE_id; int ue_cnt=0; //# ifdef ENABLE_XFORMS_WRITE_STATS // FILE *gNB_stats = fopen("gNB_stats.txt", "w"); @@ -906,13 +921,11 @@ static void *scope_thread_gNB(void *arg) { ue_cnt=0; for(UE_id=0; UE_idargc, p->argv, NULL, 0, 0); + /* form_stats_l2 = create_form_stats_form(); fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats"); form_stats = create_form_stats_form(); fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats"); - + */ + for(int UE_id=0; UE_idphy_scope_gnb, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - } // CC_id + form_gnb[UE_id] = create_phy_scope_gnb(); + sprintf (title, "LTE UL SCOPE eNB for UE %d",UE_id); + fl_show_form (form_gnb[UE_id]->phy_scope_gnb, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); } // UE_id pthread_t forms_thread; diff --git a/openair1/PHY/TOOLS/nr_phy_scope.h b/openair1/PHY/TOOLS/nr_phy_scope.h index 770006d234..aaee08a554 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.h +++ b/openair1/PHY/TOOLS/nr_phy_scope.h @@ -78,6 +78,7 @@ FD_phy_scope_nrue * create_phy_scope_nrue( void ); void phy_scope_gNB(FD_phy_scope_gnb *form, PHY_VARS_gNB *phy_vars_gnb, + RU_t *phy_vars_ru, int UE_id); diff --git a/openair1/PHY/TOOLS/tools_defs.h b/openair1/PHY/TOOLS/tools_defs.h index 5ba956fd39..d753b501b6 100644 --- a/openair1/PHY/TOOLS/tools_defs.h +++ b/openair1/PHY/TOOLS/tools_defs.h @@ -36,8 +36,6 @@ extern "C" { #include #include "PHY/sse_intrin.h" -#define CEILIDIV(a,b) ((a+b-1)/b) -#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1)) struct complex { double x; @@ -205,6 +203,21 @@ void dft18432(int16_t *sigF,int16_t *sig,int scale); void dft24576(int16_t *sigF,int16_t *sig,int scale); +void dft49152(int16_t *sigF,int16_t *sig,int scale); +void idft49152(int16_t *sigF,int16_t *sig,int scale); + +void dft9216(int16_t *sigF,int16_t *sig,int scale); +void idft9216(int16_t *sigF,int16_t *sig,int scale); + +void dft36864(int16_t *sigF,int16_t *sig,int scale); +void idft36864(int16_t *sigF,int16_t *sig,int scale); + +void dft98304(int16_t *sigF,int16_t *sig,int scale); +void idft98304(int16_t *sigF,int16_t *sig,int scale); + +void dft73728(int16_t *sigF,int16_t *sig,int scale); +void idft73728(int16_t *sigF,int16_t *sig,int scale); + /*!\fn int32_t rotate_cpx_vector(int16_t *x,int16_t *alpha,int16_t *y,uint32_t N,uint16_t output_shift) This function performs componentwise multiplication of a vector with a complex scalar. diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h index 94afeed12f..10496ced20 100644 --- a/openair1/PHY/defs_RU.h +++ b/openair1/PHY/defs_RU.h @@ -468,6 +468,8 @@ typedef struct RU_t_s { int nb_rx; /// number of TX paths on device int nb_tx; + /// number of logical antennas at TX beamformer input + int nb_log_antennas; /// maximum PDSCH RS EPRE int max_pdschReferenceSignalPower; /// maximum RX gain @@ -604,6 +606,8 @@ typedef struct RU_t_s { int wakeup_L1_sleeptime; /// maximum number of sleeps int wakeup_L1_sleep_cnt_max; + /// DL IF frequency in Hz + uint64_t if_frequency; } RU_t; diff --git a/openair1/PHY/defs_common.h b/openair1/PHY/defs_common.h index 93dc8d6bd5..f52558b632 100644 --- a/openair1/PHY/defs_common.h +++ b/openair1/PHY/defs_common.h @@ -85,6 +85,7 @@ #define LTE_CE_OFFSET LTE_CE_FILTER_LENGTH #define TX_RX_SWITCH_SYMBOL (NUMBER_OF_SYMBOLS_PER_FRAME>>1) #define PBCH_PDU_SIZE 3 //bytes +#define NR_NUMBER_OF_SYMBOLS_PER_SLOT 14 #define PRACH_SYMBOL 3 //position of the UL PSS wrt 2nd slot of special subframe @@ -635,6 +636,10 @@ typedef struct LTE_DL_FRAME_PARMS { uint16_t first_carrier_offset_khz_1dot25; /// Number of samples in a subframe uint32_t samples_per_tti; + /// Number of samples in a subframe + uint32_t samples_per_subframe; + /// Number of samples in a slot + uint32_t samples_per_slot; /// Number of OFDM/SC-FDMA symbols in one subframe (to be modified to account for potential different in UL/DL) uint16_t symbols_per_tti; /// Number of OFDM symbols in DL portion of S-subframe diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index 3c0f0db8da..b5a24ca793 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -40,7 +40,7 @@ #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/impl_defs_top.h" #include "PHY/defs_common.h" -#include "PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h" +#include "PHY/CODING/nrLDPC_extern.h" #include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" #define MAX_NUM_RU_PER_gNB MAX_NUM_RU_PER_eNB @@ -61,29 +61,6 @@ typedef struct { } NR_PBCH_parms_t; -typedef struct { - /// Length of DCI payload in bits - uint16_t size; - /// Aggregation level - uint8_t L; - /// HARQ PID - uint8_t harq_pid; - /// PDCCH parameters - nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params; - /// CCE list - nr_cce_t cce_list[NR_MAX_PDCCH_AGG_LEVEL]; - /// DCI pdu - uint64_t dci_pdu[2]; -} NR_gNB_DCI_ALLOC_t; - - -typedef struct { - uint8_t num_dci; - uint8_t num_pdsch_rnti; - NR_gNB_DCI_ALLOC_t dci_alloc[256]; -} NR_gNB_PDCCH; - - typedef enum { NR_SCH_IDLE, NR_ACTIVE, @@ -94,7 +71,7 @@ typedef enum { typedef struct { /// Nfapi DLSCH PDU - nfapi_nr_dl_config_dlsch_pdu dlsch_pdu; + nfapi_nr_dl_tti_pdsch_pdu pdsch_pdu; /// pointer to pdu from MAC interface (this is "a" in 36.212) uint8_t *pdu; /// The payload + CRC size in bits, "B" from 36-212 @@ -112,11 +89,11 @@ typedef struct { /// MIMO mode for this DLSCH MIMO_mode_t mimo_mode; /// Concatenated sequences - uint8_t e[MAX_NUM_NR_CHANNEL_BITS] __attribute__((aligned(32))); + uint8_t *e; /// LDPC-code outputs uint8_t *d[MAX_NUM_NR_DLSCH_SEGMENTS]; /// Interleaver outputs - uint8_t f[MAX_NUM_NR_CHANNEL_BITS] __attribute__((aligned(32))); + uint8_t *f; /// Number of code segments uint32_t C; /// Number of bits in "small" code segments @@ -171,10 +148,21 @@ typedef struct { int16_t sqrt_rho_b; } NR_gNB_DLSCH_t; +typedef struct { + /// \brief ?. + /// first index: ? [0..1023] (hard coded) + int16_t *prachF; + /// \brief ?. + /// second index: rx antenna [0..63] (hard coded) \note Hard coded array size indexed by \c nb_antennas_rx. + /// third index: frequency-domain sample [0..ofdm_symbol_size*12[ + int16_t **rxsigF; + /// \brief local buffer to compute prach_ifft + int32_t *prach_ifft; +} NR_gNB_PRACH; typedef struct { /// Nfapi ULSCH PDU - nfapi_nr_ul_config_ulsch_pdu ulsch_pdu; + nfapi_nr_pusch_pdu_t ulsch_pdu; /// Frame where current HARQ round was sent uint32_t frame; /// Subframe where current HARQ round was sent @@ -285,7 +273,7 @@ typedef struct { /// Temporary h sequence to flag PUSCH_x/PUSCH_y symbols which are not scrambled uint8_t h[MAX_NUM_CHANNEL_BITS]; /// soft bits for each received segment ("w"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) - int16_t w[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; + int16_t *w[MAX_NUM_NR_ULSCH_SEGMENTS]; ////////////////////////////////////////////////////////////// } NR_UL_gNB_HARQ_t; @@ -375,6 +363,14 @@ typedef struct { /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx /// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[ int32_t **ul_ch_estimates_ext; + /// \brief Hold the PTRS phase estimates in frequency domain. + /// - first index: rx antenna id [0..nb_antennas_rx[ + /// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[ + int32_t **ul_ch_ptrs_estimates; + /// \brief Uplink phase estimates extracted in PRBS. + /// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx + /// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[ + int32_t **ul_ch_ptrs_estimates_ext; /// \brief Holds the compensated signal. /// - first index: rx antenna id [0..nb_antennas_rx[ /// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[ @@ -414,8 +410,16 @@ typedef struct { /// \brief llr values. /// - first index: ? [0..1179743] (hard coded) int16_t *llr; - // DMRS symbol index, to be updated every DMRS symbol within a slot. + /// DMRS symbol index, to be updated every DMRS symbol within a slot. uint8_t dmrs_symbol; + // PTRS symbol index, to be updated every PTRS symbol within a slot. + uint8_t ptrs_symbol_index; + /// bit mask of PT-RS ofdm symbol indicies + uint16_t ptrs_symbols; + // PTRS subcarriers per OFDM symbol + uint16_t ptrs_sc_per_ofdm_symbol; + /// flag to verify if channel level computation is done + uint8_t cl_done; } NR_gNB_PUSCH; @@ -612,7 +616,7 @@ typedef struct PHY_VARS_gNB_s { int rx_total_gain_dB; int (*nr_start_if)(struct RU_t_s *ru, struct PHY_VARS_gNB_s *gNB); uint8_t local_flag; - nfapi_nr_config_request_t gNB_config; + nfapi_nr_config_request_scf_t gNB_config; NR_DL_FRAME_PARMS frame_parms; PHY_MEASUREMENTS_gNB measurements; NR_IF_Module_t *if_inst; @@ -637,21 +641,21 @@ typedef struct PHY_VARS_gNB_s { //Sched_Rsp_t Sched_INFO; nfapi_nr_ul_tti_request_t UL_tti_req; - NR_gNB_PDCCH pdcch_vars; - NR_gNB_PBCH pbch; + nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu; + nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu; + nfapi_nr_dl_tti_ssb_pdu ssb_pdu; - NR_gNB_COMMON common_vars; - NR_gNB_PUSCH *pusch_vars[NUMBER_OF_UE_MAX]; + int num_pdsch_rnti; + NR_gNB_PBCH pbch; + nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL]; + NR_gNB_COMMON common_vars; + NR_gNB_PRACH prach_vars; + NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX]; NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords] NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p; NR_gNB_DLSCH_t *dlsch_PCH; -/* - LTE_eNB_UE_stats UE_stats[NUMBER_OF_UE_MAX]; - LTE_eNB_UE_stats *UE_stats_ptr[NUMBER_OF_UE_MAX]; -*/ uint8_t pbch_configured; - uint8_t pbch_pdu[4]; //PBCH_PDU_SIZE char gNB_generate_rar; /// NR synchronization sequences @@ -669,12 +673,15 @@ typedef struct PHY_VARS_gNB_s { /// PDSCH DMRS sequence uint32_t ****nr_gold_pdsch_dmrs; - + /// PUSCH DMRS - uint32_t nr_gold_pusch[2][20][2][NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD]; + uint32_t ****nr_gold_pusch_dmrs; /// Indicator set to 0 after first SR - uint8_t first_sr[NUMBER_OF_UE_MAX]; + uint8_t first_sr[NUMBER_OF_NR_SR_MAX]; + + /// PRACH root sequence + uint32_t X_u[64][839]; uint32_t max_peak_val; @@ -685,7 +692,6 @@ typedef struct PHY_VARS_gNB_s { /// N0 (used for abstraction) double N0; - unsigned char first_run_timing_advance[NUMBER_OF_UE_MAX]; unsigned char first_run_I0_measurements; @@ -703,96 +709,29 @@ typedef struct PHY_VARS_gNB_s { /// counter to average prach energh over first 100 prach opportunities int prach_energy_counter; - // PDSCH Variables - PDSCH_CONFIG_DEDICATED pdsch_config_dedicated[NUMBER_OF_UE_MAX]; - - // PUSCH Varaibles - PUSCH_CONFIG_DEDICATED pusch_config_dedicated[NUMBER_OF_UE_MAX]; - - PUSCH_Config_t pusch_config; - - // PUCCH variables - PUCCH_CONFIG_DEDICATED pucch_config_dedicated[NUMBER_OF_UE_MAX]; - - // UL-POWER-Control - UL_POWER_CONTROL_DEDICATED ul_power_control_dedicated[NUMBER_OF_UE_MAX]; - - // TPC - TPC_PDCCH_CONFIG tpc_pdcch_config_pucch[NUMBER_OF_UE_MAX]; - TPC_PDCCH_CONFIG tpc_pdcch_config_pusch[NUMBER_OF_UE_MAX]; - - // CQI reporting - CQI_REPORT_CONFIG cqi_report_config[NUMBER_OF_UE_MAX]; - - // SRS Variables - SOUNDINGRS_UL_CONFIG_DEDICATED soundingrs_ul_config_dedicated[NUMBER_OF_UE_MAX]; - - dmrs_UplinkConfig_t dmrs_UplinkConfig; - - dmrs_DownlinkConfig_t dmrs_DownlinkConfig; - - uint8_t ncs_cell[20][7]; - - // Scheduling Request Config - SCHEDULING_REQUEST_CONFIG scheduling_request_config[NUMBER_OF_UE_MAX]; - - // Transmission mode per UE - uint8_t transmission_mode[NUMBER_OF_UE_MAX]; - - /// cba_last successful reception for each group, used for collision detection - uint8_t cba_last_reception[4]; - - // Pointers for active physicalConfigDedicated to be applied in current slot - struct PhysicalConfigDedicated *physicalConfigDedicated[NUMBER_OF_UE_MAX]; - - - uint32_t rb_mask_ul[4]; - - /// Information regarding TM5 - MU_MIMO_mode mu_mimo_mode[NUMBER_OF_UE_MAX]; - - - /// target_ue_dl_mcs : only for debug purposes - uint32_t target_ue_dl_mcs; - /// target_ue_ul_mcs : only for debug purposes - uint32_t target_ue_ul_mcs; - /// target_ue_dl_rballoc : only for debug purposes - uint32_t ue_dl_rb_alloc; - /// target ul PRBs : only for debug - uint32_t ue_ul_nb_rb; - - ///check for Total Transmissions - uint32_t check_for_total_transmissions; - - ///check for MU-MIMO Transmissions - uint32_t check_for_MUMIMO_transmissions; - - ///check for SU-MIMO Transmissions - uint32_t check_for_SUMIMO_transmissions; - - ///check for FULL MU-MIMO Transmissions - uint32_t FULL_MUMIMO_transmissions; - - /// Counter for total bitrate, bits and throughput in downlink - uint32_t total_dlsch_bitrate; - uint32_t total_transmitted_bits; - uint32_t total_system_throughput; - - int hw_timing_advance; - + /* time_stats_t phy_proc; + */ time_stats_t phy_proc_tx; + /* time_stats_t phy_proc_rx; + */ time_stats_t rx_prach; - + /* time_stats_t ofdm_mod_stats; + */ time_stats_t dlsch_encoding_stats; time_stats_t dlsch_modulation_stats; time_stats_t dlsch_scrambling_stats; + time_stats_t tinput; + time_stats_t tprep; + time_stats_t tparity; + time_stats_t toutput; + time_stats_t dlsch_rate_matching_stats; - time_stats_t dlsch_turbo_encoding_stats; time_stats_t dlsch_interleaving_stats; - + time_stats_t dlsch_segmentation_stats; + /* time_stats_t rx_dft_stats; time_stats_t ulsch_channel_estimation_stats; time_stats_t ulsch_freq_offset_estimation_stats; @@ -803,29 +742,7 @@ typedef struct PHY_VARS_gNB_s { time_stats_t ulsch_deinterleaving_stats; time_stats_t ulsch_demultiplexing_stats; time_stats_t ulsch_llr_stats; - time_stats_t ulsch_tc_init_stats; - time_stats_t ulsch_tc_alpha_stats; - time_stats_t ulsch_tc_beta_stats; - time_stats_t ulsch_tc_gamma_stats; - time_stats_t ulsch_tc_ext_stats; - time_stats_t ulsch_tc_intl1_stats; - time_stats_t ulsch_tc_intl2_stats; - -#ifdef LOCALIZATION - /// time state for localization - time_stats_t localization_stats; -#endif - - int32_t pucch1_stats_cnt[NUMBER_OF_UE_MAX][10]; - int32_t pucch1_stats[NUMBER_OF_UE_MAX][10*1024]; - int32_t pucch1_stats_thres[NUMBER_OF_UE_MAX][10*1024]; - int32_t pucch1ab_stats_cnt[NUMBER_OF_UE_MAX][10]; - int32_t pucch1ab_stats[NUMBER_OF_UE_MAX][2*10*1024]; - int32_t pusch_stats_rb[NUMBER_OF_UE_MAX][10240]; - int32_t pusch_stats_round[NUMBER_OF_UE_MAX][10240]; - int32_t pusch_stats_mcs[NUMBER_OF_UE_MAX][10240]; - int32_t pusch_stats_bsr[NUMBER_OF_UE_MAX][10240]; - int32_t pusch_stats_BO[NUMBER_OF_UE_MAX][10240]; + */ } PHY_VARS_gNB; #endif diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index d72979262c..6f6c5ac8e9 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -45,6 +45,7 @@ #include #include "common_lib.h" #include "msc.h" +#include "fapi_nr_ue_interface.h" //#include #include "assertions.h" @@ -470,65 +471,7 @@ typedef struct { #ifdef NR_PDCCH_DEFS_NR_UE #define MAX_NR_DCI_DECODED_SLOT 10 // This value is not specified -#define NBR_NR_FORMATS 8 // The number of formats is 8 (0_0, 0_1, 1_0, 1_1, 2_0, 2_1, 2_2, 2_3) -#define NBR_NR_DCI_FIELDS 56 // The number of different dci fields defined in TS 38.212 subclause 7.3.1 -#define IDENTIFIER_DCI_FORMATS 0 -#define CARRIER_IND 1 -#define SUL_IND_0_1 2 -#define SLOT_FORMAT_IND 3 -#define PRE_EMPTION_IND 4 -#define BLOCK_NUMBER 5 -#define CLOSE_LOOP_IND 6 -#define BANDWIDTH_PART_IND 7 -#define SHORT_MESSAGE_IND 8 -#define SHORT_MESSAGES 9 -#define FREQ_DOM_RESOURCE_ASSIGNMENT_UL 10 -#define FREQ_DOM_RESOURCE_ASSIGNMENT_DL 11 -#define TIME_DOM_RESOURCE_ASSIGNMENT 12 -#define VRB_TO_PRB_MAPPING 13 -#define PRB_BUNDLING_SIZE_IND 14 -#define RATE_MATCHING_IND 15 -#define ZP_CSI_RS_TRIGGER 16 -#define FREQ_HOPPING_FLAG 17 -#define TB1_MCS 18 -#define TB1_NDI 19 -#define TB1_RV 20 -#define TB2_MCS 21 -#define TB2_NDI 22 -#define TB2_RV 23 -#define MCS 24 -#define NDI 25 -#define RV 26 -#define HARQ_PROCESS_NUMBER 27 -#define DAI_ 28 -#define FIRST_DAI 29 -#define SECOND_DAI 30 -#define TB_SCALING 31 -#define TPC_PUSCH 32 -#define TPC_PUCCH 33 -#define PUCCH_RESOURCE_IND 34 -#define PDSCH_TO_HARQ_FEEDBACK_TIME_IND 35 -#define SRS_RESOURCE_IND 36 -#define PRECOD_NBR_LAYERS 37 -#define ANTENNA_PORTS 38 -#define TCI 39 -#define SRS_REQUEST 40 -#define TPC_CMD 41 -#define CSI_REQUEST 42 -#define CBGTI 43 -#define CBGFI 44 -#define PTRS_DMRS 45 -#define BETA_OFFSET_IND 46 -#define DMRS_SEQ_INI 47 -#define UL_SCH_IND 48 -#define PADDING_NR_DCI 49 -#define SUL_IND_0_0 50 -#define RA_PREAMBLE_INDEX 51 -#define SUL_IND_1_0 52 -#define SS_PBCH_INDEX 53 -#define PRACH_MASK_INDEX 54 -#define RESERVED_NR_DCI 55 typedef enum { @@ -759,12 +702,6 @@ typedef struct { /// \brief PDCCH/DCI e-sequence (input to rate matching). /// - first index: ? [0..96*N_RB_DL[ int16_t *e_rx; - /// number of PDCCH symbols in current subframe - uint8_t num_pdcch_symbols; - /// Allocated CRNTI for UE - uint16_t crnti; - /// 1: the allocated crnti is Temporary C-RNTI / 0: otherwise - uint8_t crnti_is_temporary; /// Total number of PDU errors (diagnostic mode) uint32_t dci_errors; /// Total number of PDU received @@ -773,11 +710,14 @@ typedef struct { uint32_t dci_false; /// Total number of DCI missed (diagnostic mode) uint32_t dci_missed; - /// nCCE for PUCCH per subframe + /// nCCE for PDCCH per subframe uint8_t nCCE[10]; //Check for specific DCIFormat and AgregationLevel uint8_t dciFormat; uint8_t agregationLevel; + int nb_search_space; + fapi_nr_dl_config_dci_dl_pdu_rel15_t pdcch_config[FAPI_NR_MAX_SS_PER_CORESET]; + /* #ifdef NR_PDCCH_DEFS_NR_UE int nb_searchSpaces; // CORESET structure, where maximum number of CORESETs to be handled is 3 (according to 38.331 V15.1.0) @@ -788,7 +728,7 @@ typedef struct { int n_RB_BWP[NR_NBR_SEARCHSPACE_ACT_BWP]; uint32_t nb_search_space; -#endif + #endif*/ } NR_UE_PDCCH; #define PBCH_A 24 @@ -940,9 +880,10 @@ typedef struct { nr_ue_if_module_t *if_inst; - //nfapi_nr_config_request_t nrUE_config; <-- don't use config type for gNB!!! fapi_nr_config_request_t nrUE_config; + uint16_t frame_gap; + // the following structures are not part of PHY_vars_UE anymore as it is not thread safe. They are now on the stack of the functions that actually need them //nr_downlink_indication_t dl_indication; @@ -957,8 +898,9 @@ typedef struct { //fapi_nr_dci_indication_t dci_ind; // point to the current rxTx thread index - uint8_t current_thread_id[40]; + uint8_t current_thread_id[NR_MAX_SLOTS_PER_FRAME]; + t_nrPolar_params *polarList; NR_UE_PDSCH *pdsch_vars[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX+1]; // two RxTx Threads NR_UE_PDSCH_FLP *pdsch_vars_flp[NUMBER_OF_CONNECTED_eNB_MAX+1]; NR_UE_PDSCH *pdsch_vars_SI[NUMBER_OF_CONNECTED_eNB_MAX+1]; @@ -1012,6 +954,9 @@ typedef struct { /// PUSCH DMRS sequence uint32_t ****nr_gold_pusch_dmrs; + /// flag to indicate if PTRS is configured + uint8_t ptrs_configured; + uint32_t X_u[64][839]; uint32_t high_speed_flag; @@ -1064,12 +1009,13 @@ typedef struct { int current_dlsch_cqi[NUMBER_OF_CONNECTED_eNB_MAX]; unsigned char first_run_timing_advance[NUMBER_OF_CONNECTED_eNB_MAX]; uint8_t generate_prach; + uint8_t generate_nr_prach; uint8_t prach_cnt; uint8_t prach_PreambleIndex; // uint8_t prach_timer; uint8_t decode_SIB; uint8_t decode_MIB; - uint8_t ssb_periodicity; + uint8_t init_sync_frame; /// temporary offset during cell search prior to MIB decoding int ssb_offset; uint16_t symbol_offset; // offset in terms of symbols for detected ssb in sync @@ -1143,7 +1089,6 @@ typedef struct { crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig; supplementaryUplink_t supplementaryUplink; - dmrs_UplinkConfig_t dmrs_UplinkConfig; dmrs_DownlinkConfig_t dmrs_DownlinkConfig; csi_MeasConfig_t csi_MeasConfig; PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig; diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 048e48ae45..ccc79b7d47 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -35,7 +35,7 @@ #include "PHY/impl_defs_top.h" #include "defs_common.h" -#include "nfapi_nr_interface.h" +#include "nfapi_nr_interface_scf.h" #include "impl_defs_nr.h" #include "PHY/CODING/nrPolar_tools/nr_polar_defs.h" @@ -102,6 +102,15 @@ #define NR_MAX_PUSCH_ENCODED_LENGTH NR_MAX_PDSCH_ENCODED_LENGTH #define NR_MAX_PDSCH_TBS 3824 +#define MAX_NUM_NR_DLSCH_SEGMENTS 34 +#define MAX_NR_DLSCH_PAYLOAD_BYTES (MAX_NUM_NR_DLSCH_SEGMENTS*1056) + +#define MAX_NUM_NR_ULSCH_SEGMENTS MAX_NUM_NR_DLSCH_SEGMENTS +#define MAX_NR_ULSCH_PAYLOAD_BYTES (MAX_NUM_NR_ULSCH_SEGMENTS*1056) + +#define MAX_NUM_NR_CHANNEL_BITS (14*273*12*8) // 14 symbols, 273 RB +#define MAX_NUM_NR_RE (14*273*12) + typedef enum { NR_MU_0=0, NR_MU_1, @@ -190,35 +199,43 @@ typedef struct { } nr_cce_t; -/// PRACH-ConfigInfo from 36.331 RRC spec +/// PRACH-ConfigInfo from 38.331 RRC spec typedef struct { - /// Parameter: prach-ConfigurationIndex, see TS 36.211 (5.7.1). \vr{[0..63]} + /// Parameter: prach-ConfigurationIndex, see TS 38.211 (6.3.3.2). uint8_t prach_ConfigIndex; - /// Parameter: High-speed-flag, see TS 36.211 (5.7.2). \vr{[0..1]} 1 corresponds to Restricted set and 0 to Unrestricted set. + /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set. uint8_t highSpeedFlag; - /// Parameter: \f$N_\text{CS}\f$, see TS 36.211 (5.7.2). \vr{[0..15]}\n Refer to table 5.7.2-2 for preamble format 0..3 and to table 5.7.2-3 for preamble format 4. + /// Restricted Set Config (type A=0 , type B=1) TS 38.211 (6.3.3.1) + uint8_t restrictedSetConfig; + /// 38.211 (NCS 38.211 6.3.3.1). uint8_t zeroCorrelationZoneConfig; - /// Parameter: prach-FrequencyOffset, see TS 36.211 (5.7.1). \vr{[0..94]}\n For TDD the value range is dependent on the value of \ref prach_ConfigIndex. - uint8_t prach_FreqOffset; + /// see TS 38.211 (6.3.3.2). + uint8_t msg1_frequencystart; } NR_PRACH_CONFIG_INFO; /// PRACH-ConfigSIB or PRACH-Config typedef struct { - /// Parameter: RACH_ROOT_SEQUENCE, see TS 36.211 (5.7.1). \vr{[0..837]} + /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2). uint16_t rootSequenceIndex; - /// prach_Config_enabled=1 means enabled. \vr{[0..1]} + /// prach_Config_enabled=1 means enabled.} uint8_t prach_Config_enabled; /// PRACH Configuration Information NR_PRACH_CONFIG_INFO prach_ConfigInfo; } NR_PRACH_CONFIG_COMMON; -typedef struct NR_DL_FRAME_PARMS { +typedef struct NR_DL_FRAME_PARMS NR_DL_FRAME_PARMS; + +typedef uint32_t (*get_samples_per_slot_t)(int slot, NR_DL_FRAME_PARMS* fp); + +typedef uint32_t (*get_samples_slot_timestamp_t)(int slot, NR_DL_FRAME_PARMS* fp, uint8_t sl_ahead); + +struct NR_DL_FRAME_PARMS { /// frequency range nr_frequency_range_e freq_range; - /// Placeholder to replace overlapping fields below - nfapi_nr_rf_config_t rf_config; + // /// Placeholder to replace overlapping fields below + // nfapi_nr_rf_config_t rf_config; /// Placeholder to replace SSB overlapping fields below - nfapi_nr_sch_config_t sch_config; + // nfapi_nr_sch_config_t sch_config; /// Number of resource blocks (RB) in DL int N_RB_DL; /// Number of resource blocks (RB) in UL @@ -227,12 +244,12 @@ typedef struct NR_DL_FRAME_PARMS { uint8_t N_RBG; /// Total Number of Resource Block Groups SubSets: this is P uint8_t N_RBGS; - /// EUTRA Band - uint16_t eutra_band; + /// NR Band + uint16_t nr_band; /// DL carrier frequency - uint32_t dl_CarrierFreq; + uint64_t dl_CarrierFreq; /// UL carrier frequency - uint32_t ul_CarrierFreq; + uint64_t ul_CarrierFreq; /// TX attenuation uint32_t att_tx; /// RX attenuation @@ -240,11 +257,10 @@ typedef struct NR_DL_FRAME_PARMS { /// total Number of Resource Block Groups: this is ceil(N_PRB/P) /// Frame type (0 FDD, 1 TDD) lte_frame_type_t frame_type; - /// TDD subframe assignment (0-7) (default = 3) (254=RX only, 255=TX only) uint8_t tdd_config; - /// TDD S-subframe configuration (0-9) /// Cell ID uint16_t Nid_cell; + /// subcarrier spacing (15,30,60,120) uint32_t subcarrier_spacing; /// 3/4 sampling uint8_t threequarter_fs; @@ -260,12 +276,18 @@ typedef struct NR_DL_FRAME_PARMS { uint16_t symbols_per_slot; /// Number of slots per subframe uint16_t slots_per_subframe; - /// Number of slots per frame + /// Number of slots per frame uint16_t slots_per_frame; /// Number of samples in a subframe uint32_t samples_per_subframe; - /// Number of samples in a slot - uint32_t samples_per_slot; + /// Number of samples in current slot + get_samples_per_slot_t get_samples_per_slot; + /// Number of samples before slot + get_samples_slot_timestamp_t get_samples_slot_timestamp; + /// Number of samples in 0th and center slot of a subframe + uint32_t samples_per_slot0; + /// Number of samples in other slots of the subframe + uint32_t samples_per_slotN0; /// Number of OFDM/SC-FDMA symbols in one subframe (to be modified to account for potential different in UL/DL) uint16_t symbols_per_tti; /// Number of samples in a radio frame @@ -290,7 +312,7 @@ typedef struct NR_DL_FRAME_PARMS { /// Number of Receive antennas in node uint8_t nb_antennas_rx; /// Number of common transmit antenna ports in eNodeB (1 or 2) - uint8_t nb_antenna_ports_eNB; + uint8_t nb_antenna_ports_gNB; /// PRACH_CONFIG NR_PRACH_CONFIG_COMMON prach_config_common; /// Cyclic Prefix for DL (0=Normal CP, 1=Extended CP) @@ -299,17 +321,20 @@ typedef struct NR_DL_FRAME_PARMS { uint8_t nushift; /// SRS configuration from TS 38.331 RRC SRS_NR srs_nr; - + /// Power used by SSB in order to estimate signal strength and path loss + int ss_PBCH_BlockPower; /// for NR TDD management TDD_UL_DL_configCommon_t *p_tdd_UL_DL_Configuration; TDD_UL_DL_configCommon_t *p_tdd_UL_DL_ConfigurationCommon2; - TDD_UL_DL_SlotConfig_t *p_TDD_UL_DL_ConfigDedicated; + TDD_UL_DL_SlotConfig_t *p_TDD_UL_DL_ConfigDedicated; /// TDD configuration uint16_t tdd_uplink_nr[2*NR_MAX_SLOTS_PER_FRAME]; /* this is a bitmap of symbol of each slot given for 2 frames */ + uint8_t half_frame_bit; + //SSB related params /// Start in Subcarrier index of the SSB block uint16_t ssb_start_subcarrier; @@ -321,10 +346,12 @@ typedef struct NR_DL_FRAME_PARMS { uint64_t L_ssb; /// Total number of SSB transmitted uint8_t N_ssb; + /// SSB index + uint8_t ssb_index; /// PBCH polar encoder params t_nrPolar_params pbch_polar_params; -} NR_DL_FRAME_PARMS; +}; #define KHz (1000UL) #define MHz (1000*KHz) @@ -335,8 +362,9 @@ typedef struct nr_bandentry_s { uint64_t ul_max; uint64_t dl_min; uint64_t dl_max; - uint64_t N_OFFs_DL; uint64_t step_size; + uint64_t N_OFFs_DL; + uint8_t deltaf_raster; } nr_bandentry_t; typedef struct nr_band_info_s { diff --git a/openair1/PHY/impl_defs_nr.h b/openair1/PHY/impl_defs_nr.h index 6e13973dd9..44f2e314ea 100644 --- a/openair1/PHY/impl_defs_nr.h +++ b/openair1/PHY/impl_defs_nr.h @@ -67,33 +67,10 @@ EXTERN const uint8_t N_slot_subframe[MU_NUMBER] #endif ; -//#define RX_NB_TH_MAX 3 -//#define RX_NB_TH 3 - -#if 0 -#define LTE_SLOTS_PER_SUBFRAME (2) - -#define LTE_NUMBER_OF_SUBFRAMES_PER_FRAME (10) -#define LTE_SLOTS_PER_FRAME (20) -#define LTE_CE_FILTER_LENGTH (5) -#define LTE_CE_OFFSET (LTE_CE_FILTER_LENGTH) -#define TX_RX_SWITCH_SYMBOL (NUMBER_OF_SYMBOLS_PER_FRAME>>1) -#define PBCH_PDU_SIZE (3) //bytes - -#define PRACH_SYMBOL (3) //position of the UL PSS wrt 2nd slot of special subframe - -#define NUMBER_OF_FREQUENCY_GROUPS (lte_frame_parms->N_RB_DL) - -#define SSS_AMP (1148) - -#define MAX_NUM_PHICH_GROUPS (56) //110 RBs Ng=2, p.60 36-212, Sec. 6.9 - -#define MAX_MBSFN_AREA (8) - -#endif #define NB_DL_DATA_TO_UL_ACK (8) /* size of table TS 38.213 Table 9.2.3-1 */ + /*********************************************************************** * * FUNCTIONALITY : System information type 1 @@ -120,15 +97,11 @@ SystemInformationBlockType1_nr_t; #define NR_TDD_SET_ALL_SYMBOLS (0x3FFF) #define NR_DOWNLINK_SLOT (0x01) -#define NR_UPLINK_SLOT (0x03) +#define NR_UPLINK_SLOT (0x02) +#define NR_MIXED_SLOT (0x03) #define FRAME_DURATION_MICRO_SEC (10000) /* frame duration in microsecond */ -typedef enum { - SLOT_DL = 0, - SLOT_UL = 1, -} nr_slot_t; - typedef enum { ms0p5 = 500, /* duration is given in microsecond */ ms0p625 = 625, @@ -140,7 +113,7 @@ typedef enum { ms10 = 10000, } dl_UL_TransmissionPeriodicity_t; -typedef struct { +typedef struct TDD_UL_DL_configCommon_s { /// Reference SCS used to determine the time domain boundaries in the UL-DL pattern which must be common across all subcarrier specific /// virtual carriers, i.e., independent of the actual subcarrier spacing using for data transmission. /// Only the values 15 or 30 kHz (<6GHz), 60 or 120 kHz (>6GHz) are applicable. @@ -164,7 +137,7 @@ typedef struct { /// Corresponds to L1 parameter 'number-of-UL-symbols-common' (see 38.211, section FFS_Section) uint8_t nrofUplinkSymbols; /// \ for setting a sequence - struct TDD_UL_DL_configCommon_t *p_next_TDD_UL_DL_configCommon_t; + struct TDD_UL_DL_configCommon_s *p_next; } TDD_UL_DL_configCommon_t; typedef struct { @@ -363,9 +336,9 @@ typedef struct { /*********************************************************************** * -* FUNCTIONALITY : Packed Downlink Shared Channel PDSCH +* FUNCTIONALITY : Physical Downlink Shared Channel PDSCH * -* DESCRIPTION : interface description for PSCH configuration +* DESCRIPTION : interface description for PSDCH configuration * ************************************************************************/ @@ -510,9 +483,6 @@ typedef struct { uint8_t startSymbolAndLength; } PUSCH_TimeDomainResourceAllocation_t; ////////////////////////////////////////////////////////////////////////////////################################ -typedef struct { // The IE PTRS-UplinkConfig is used to configure uplink Phase-Tracking-Reference-Signals (PTRS) - -} ptrs_UplinkConfig_t; typedef enum{ maxCodeBlockGroupsPerTransportBlock_n2 = 2, maxCodeBlockGroupsPerTransportBlock_n4 = 4, @@ -530,8 +500,8 @@ typedef enum { pdsch_dmrs_type2 = 2 } pdsch_dmrs_type_t; typedef enum { - pusch_dmrs_type1 = 1, - pusch_dmrs_type2 = 2 + pusch_dmrs_type1 = 0, + pusch_dmrs_type2 = 1 } pusch_dmrs_type_t; typedef enum { pdsch_dmrs_pos0 = 0, @@ -544,6 +514,12 @@ typedef enum { pusch_dmrs_pos2 = 2, pusch_dmrs_pos3 = 3, } pusch_dmrs_AdditionalPosition_t; +typedef enum { + offset00 = 0, + offset01 = 1, + offset10 = 2, + offset11 = 3, +} ptrs_resource_elementoffset_t; typedef enum { pdsch_len1 = 1, pdsch_len2 = 2 @@ -552,6 +528,22 @@ typedef enum { pusch_len1 = 1, pusch_len2 = 2 } pusch_maxLength_t; +typedef struct { + uint8_t ptrs_mcs1; + uint8_t ptrs_mcs2; + uint8_t ptrs_mcs3; +} ptrs_time_density_t; +typedef struct { + uint16_t n_rb0; + uint16_t n_rb1; +} ptrs_frequency_density_t; +typedef struct { // The IE PTRS-UplinkConfig is used to configure uplink Phase-Tracking-Reference-Signals (PTRS) + uint8_t num_ptrs_ports; + ptrs_resource_elementoffset_t resourceElementOffset; + ptrs_time_density_t timeDensity; + ptrs_frequency_density_t frequencyDensity; + uint32_t ul_ptrs_power; +} ptrs_UplinkConfig_t; typedef struct { // The IE DMRS-DownlinkConfig is used to configure downlink demodulation reference signals for PDSCH pdsch_dmrs_type_t pdsch_dmrs_type; pdsch_dmrs_AdditionalPosition_t pdsch_dmrs_AdditionalPosition; @@ -563,6 +555,7 @@ typedef struct { // The IE DMRS-UplinkConfig is used to configure uplink demodul pusch_dmrs_type_t pusch_dmrs_type; pusch_dmrs_AdditionalPosition_t pusch_dmrs_AdditionalPosition; pusch_maxLength_t pusch_maxLength; + ptrs_UplinkConfig_t ptrs_UplinkConfig; uint16_t scramblingID0; uint16_t scramblingID1; } dmrs_UplinkConfig_t; @@ -647,6 +640,10 @@ typedef struct { * resourceAllocation */ ul_resourceAllocation_t ul_resourceAllocation; +/* + * DMRS-Uplinkconfig + */ + dmrs_UplinkConfig_t dmrs_UplinkConfig; /* * rgb_Size */ @@ -1112,6 +1109,7 @@ typedef struct { SchedulingRequestResourceConfig_t *sr_ResourceConfig[MAX_NR_OF_SR_CONFIG_PER_CELL_GROUP]; } scheduling_request_config_t; + #undef EXTERN #undef INIT_VARIABLES_PHY_IMPLEMENTATION_DEFS_NR_H #endif /* PHY_IMPL_DEFS_NR_H */ diff --git a/openair1/PHY/impl_defs_top.h b/openair1/PHY/impl_defs_top.h index 88a02c45c7..a4607d3106 100644 --- a/openair1/PHY/impl_defs_top.h +++ b/openair1/PHY/impl_defs_top.h @@ -149,10 +149,10 @@ #define OFDM_SYMBOL_SIZE_BYTES0 (OFDM_SYMBOL_SIZE_SAMPLES0*2) #define OFDM_SYMBOL_SIZE_BYTES_NO_PREFIX (OFDM_SYMBOL_SIZE_SAMPLES_NO_PREFIX*2) -#define SLOT_LENGTH_BYTES (frame_parms->samples_per_tti<<1) // 4 bytes * samples_per_tti/2 +#define SLOT_LENGTH_BYTES (frame_parms->samples_per_slot) // 4 bytes * samples_per_tti/2 #define SLOT_LENGTH_BYTES_NO_PREFIX (OFDM_SYMBOL_SIZE_BYTES_NO_PREFIX * NUMBER_OF_OFDM_SYMBOLS_PER_SLOT) -#define FRAME_LENGTH_COMPLEX_SAMPLES (frame_parms->samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME) +#define FRAME_LENGTH_COMPLEX_SAMPLES (frame_parms->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME) #define FRAME_LENGTH_SAMPLES (FRAME_LENGTH_COMPLEX_SAMPLES*2) #define FRAME_LENGTH_SAMPLES_NO_PREFIX (NUMBER_OF_SYMBOLS_PER_FRAME*OFDM_SYMBOL_SIZE_SAMPLES_NO_PREFIX) #define FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX (FRAME_LENGTH_SAMPLES_NO_PREFIX/2) diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 270ab5772c..5c145a3230 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -34,28 +34,21 @@ #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_dci.h" -int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req); -int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req); extern uint8_t nfapi_mode; -void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu, - uint8_t *sdu) +void handle_nr_nfapi_ssb_pdu(PHY_VARS_gNB *gNB,int frame,int slot, + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdu) { - AssertFatal(dl_config_pdu->bch_pdu_rel15.length == 3, "BCH PDU has length %d != 3\n", - dl_config_pdu->bch_pdu_rel15.length); + AssertFatal(dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag== 1, "bchPayloadFlat %d != 1\n", + dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag); - LOG_D(PHY,"pbch_pdu[0]: %x,pbch_pdu[1]: %x,gNB->pbch_pdu[2]: %x\n",sdu[0],sdu[1],sdu[2]); - gNB->pbch_pdu[0] = sdu[2]; - gNB->pbch_pdu[1] = sdu[1]; - gNB->pbch_pdu[2] = sdu[0]; - - // adjust transmit amplitude here based on NFAPI info + LOG_I(PHY,"%d.%d : pbch_pdu: %x\n",frame,slot,dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload); + memcpy((void*)&gNB->ssb_pdu,&dl_tti_pdu->ssb_pdu,sizeof(dl_tti_pdu->ssb_pdu)); } -/*void handle_nr_nfapi_dlsch_pdu(PHY_VARS_gNB *gNB,int frame,int subframe,gNB_L1_rxtx_proc_t *proc, +/*void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int subframe,gNB_L1_rxtx_proc_t *proc, uint8_t codeword_index, uint8_t *sdu) { @@ -85,7 +78,7 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, //AssertFatal(sdu!=NULL,"NFAPI: SFN/SF:%04d%d proc:TX:[frame %d subframe %d]: programming dlsch for round 0, rnti %x, UE_id %d, harq_pid %d : sdu is null for pdu_index %d dlsch0_harq[round:%d SFN/SF:%d%d pdu:%p mcs:%d ndi:%d pdschstart:%d]\n", // frame,subframe, // proc->frame_tx,proc->subframe_tx,rel8->rnti,UE_id,harq_pid, - // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index,dlsch0_harq->round,dlsch0_harq->frame,dlsch0_harq->subframe,dlsch0_harq->pdu,dlsch0_harq->mcs,dlsch0_harq->ndi,dlsch0_harq->pdsch_start); + // dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel8.pdu_index,dlsch0_harq->round,dlsch0_harq->frame,dlsch0_harq->subframe,dlsch0_harq->pdu,dlsch0_harq->mcs,dlsch0_harq->ndi,dlsch0_harq->pdsch_start); if (codeword_index == 0) dlsch0_harq->pdu = sdu; else dlsch1_harq->pdu = sdu; LOG_I(PHY, "SFN/SF: %d/%d DLSCH PDU filled \n",frame, subframe); @@ -94,29 +87,43 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, }*/ -void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB, - int frame, int slot, - nfapi_nr_dl_config_dci_dl_pdu *dci_dl_pdu) { - int idx = slot&1; - NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars; +void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, + int frame, int slot, + nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu) { - LOG_D(PHY,"Frame %d, Slot %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:slot_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,slot, pdcch_vars->num_dci, slot, idx, pdcch_vars->num_dci); + LOG_D(PHY,"Frame %d, Slot %d: DCI processing - proc:slot_tx:%d pdcch_pdu_rel15->numDlDci:%d\n",frame,slot, slot, pdcch_pdu->pdcch_pdu_rel15.numDlDci); // copy dci configuration into gNB structure - nr_fill_dci(gNB,frame,slot,&pdcch_vars->dci_alloc[pdcch_vars->num_dci],dci_dl_pdu); + gNB->pdcch_pdu = pdcch_pdu; + + nr_fill_dci(gNB,frame,slot); + - LOG_D(PHY,"Frame %d, Slot %d: DCI processing - populated pdcch_vars->dci_alloc[%d] proc:slot_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,slot, pdcch_vars->num_dci, slot, idx, pdcch_vars->num_dci); } +void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB, + int frame, int slot, + nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu) { -void handle_nr_nfapi_dlsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, - nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, + LOG_D(PHY,"Frame %d, Slot %d: UL DCI processing - proc:slot_tx:%d pdcch_pdu_rel15->numDlDci:%d\n",frame,slot, slot, ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15.numDlDci); + + // copy dci configuration into gNB structure + gNB->ul_dci_pdu = ul_dci_request_pdu; + + nr_fill_ul_dci(gNB,frame,slot); + + + +} + +void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu) { - nr_fill_dlsch(gNB,frame,slot,dlsch_pdu,sdu); + nr_fill_dlsch(gNB,frame,slot,pdsch_pdu,sdu); } @@ -125,99 +132,75 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ PHY_VARS_gNB *gNB; // copy data from L2 interface into L1 structures module_id_t Mod_id = Sched_INFO->module_id; - uint8_t CC_id = Sched_INFO->CC_id; - nfapi_nr_dl_config_request_t *DL_req = Sched_INFO->DL_req; - nfapi_tx_request_t *TX_req = Sched_INFO->TX_req; + nfapi_nr_dl_tti_request_t *DL_req = Sched_INFO->DL_req; + nfapi_nr_tx_data_request_t *TX_req = Sched_INFO->TX_req; nfapi_nr_ul_tti_request_t *UL_tti_req = Sched_INFO->UL_tti_req; + nfapi_nr_ul_dci_request_t *UL_dci_req = Sched_INFO->UL_dci_req; frame_t frame = Sched_INFO->frame; sub_frame_t slot = Sched_INFO->slot; AssertFatal(RC.gNB!=NULL,"RC.gNB is null\n"); AssertFatal(RC.gNB[Mod_id]!=NULL,"RC.gNB[%d] is null\n",Mod_id); - AssertFatal(RC.gNB[Mod_id][CC_id]!=NULL,"RC.gNB[%d][%d] is null\n",Mod_id,CC_id); - gNB = RC.gNB[Mod_id][CC_id]; + gNB = RC.gNB[Mod_id]; - uint8_t number_dl_pdu = DL_req->dl_config_request_body.number_pdu; - //uint8_t number_ul_pdu = UL_tti_req->n_pdus; + uint8_t number_dl_pdu = DL_req->dl_tti_request_body.nPDUs; + // uint8_t number_ul_pdu = 0; + uint8_t number_ul_dci_pdu = (UL_dci_req==NULL) ? 0 : UL_dci_req->numPdus; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu; - - int i; + // if (UL_tti_req != NULL) number_ul_pdu = UL_tti_req->n_pdus; - LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SF:%04d%d DL_req:SFN/SF:%04d%d:dl_pdu:%d tx_req:SFN/SF:%04d%d:pdus:%d \n", + LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;\n", frame,slot, - NFAPI_SFNSF2SFN(DL_req->sfn_sf),NFAPI_SFNSF2SF(DL_req->sfn_sf),number_dl_pdu, - NFAPI_SFNSF2SFN(TX_req->sfn_sf),NFAPI_SFNSF2SF(TX_req->sfn_sf),TX_req->tx_request_body.number_of_pdus); + DL_req->SFN,DL_req->Slot,number_dl_pdu, + TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs); - int do_oai =0; - int dont_send =0; - gNB->pdcch_vars.num_dci = 0; - gNB->pdcch_vars.num_pdsch_rnti = 0; + int pdcch_received=0; + gNB->num_pdsch_rnti=0; + gNB->pdcch_pdu = NULL; + gNB->pbch_configured=0; - gNB->pdcch_vars.num_dci=0; + for (int i=0;idl_tti_request_body.dl_tti_pdu_list[i]; + LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_tti_pdu->PDUType); + switch (dl_tti_pdu->PDUType) { + case NFAPI_NR_DL_TTI_SSB_PDU_TYPE: + gNB->pbch_configured=1; - for (i=0;idl_config_request_body.dl_config_pdu_list[i]; - LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type); - switch (dl_config_pdu->pdu_type) { - case NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE: - AssertFatal(dl_config_pdu->bch_pdu_rel15.pdu_index < TX_req->tx_request_body.number_of_pdus, - "bch_pdu_rel8.pdu_index>=TX_req->number_of_pdus (%d>%d)\n", - dl_config_pdu->bch_pdu_rel15.pdu_index, - TX_req->tx_request_body.number_of_pdus); - gNB->pbch_configured=1; - do_oai=1; + handle_nr_nfapi_ssb_pdu(gNB,frame,slot, + dl_tti_pdu); - handle_nr_nfapi_bch_pdu(gNB, - dl_config_pdu, - TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu_rel15.pdu_index].segments[0].segment_data); break; - case NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE: - handle_nfapi_nr_dci_dl_pdu(gNB, - frame, slot, - &dl_config_pdu->dci_dl_pdu); - gNB->pdcch_vars.num_dci++; - gNB->pdcch_vars.num_pdsch_rnti++; - do_oai=1; + case NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE: + AssertFatal(pdcch_received == 0, "pdcch_received is not 0, we can only handle one PDCCH PDU per slot\n"); + handle_nfapi_nr_pdcch_pdu(gNB, + frame, slot, + &dl_tti_pdu->pdcch_pdu); + + pdcch_received = 1; + break; - case NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE: + case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE: { - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_pdu->dlsch_pdu.dlsch_pdu_rel15; - uint16_t pdu_index = dlsch_pdu_rel15->pdu_index; - uint16_t tx_pdus = TX_req->tx_request_body.number_of_pdus; - uint16_t invalid_pdu = pdu_index == -1; - uint8_t *sdu = invalid_pdu ? NULL : pdu_index >= tx_pdus ? NULL : TX_req->tx_request_body.tx_pdu_list[pdu_index].segments[0].segment_data; - - AssertFatal(sdu!=NULL,"sdu is null, pdu_index %d, tx_pdus %d\n",pdu_index,tx_pdus); - handle_nr_nfapi_dlsch_pdu(gNB,frame,slot,&dl_config_pdu->dlsch_pdu, sdu); - do_oai=1; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel15; + uint16_t pduIndex = pdsch_pdu_rel15->pduIndex; + AssertFatal(TX_req->pdu_list[pduIndex].num_TLV == 1, "TX_req->pdu_list[%d].num_TLV %d != 1\n", + pduIndex,TX_req->pdu_list[pduIndex].num_TLV); + uint8_t *sdu = (uint8_t *)TX_req->pdu_list[pduIndex].TLVs[0].value.direct; + handle_nr_nfapi_pdsch_pdu(gNB,frame,slot,&dl_tti_pdu->pdsch_pdu, sdu); } } } - memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); + if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); - /* - // this is done in phy_procedures_gNB_uespec_RX now - for (i=0;ipdus_list[i].pdu_type); - switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - { - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame,slot,pusch_pdu); - } - } + for (int i=0;iul_dci_pdu_list[i]); } - */ - - if (nfapi_mode && do_oai && !dont_send) { - oai_nfapi_tx_req(Sched_INFO->TX_req); - oai_nfapi_nr_dl_config_req(Sched_INFO->DL_req); // DJP - .dl_config_request_body.dl_config_pdu_list[0]); // DJP - FIXME TODO - yuk - only copes with 1 pdu - } } diff --git a/openair1/SCHED_NR/fapi_nr_l1.h b/openair1/SCHED_NR/fapi_nr_l1.h index 60d9e55b1f..07509b3bb7 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.h +++ b/openair1/SCHED_NR/fapi_nr_l1.h @@ -34,15 +34,16 @@ #include "PHY/phy_extern.h" #include "SCHED_NR/sched_nr.h" #include "nfapi_nr_interface.h" +#include "nfapi_nr_interface_scf.h" void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO); -void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB, - int frame, int subframe, - nfapi_nr_dl_config_dci_dl_pdu *dcl_dl_pdu); +void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, + int frame, int subframe, + nfapi_nr_dl_tti_pdcch_pdu *dcl_dl_pdu); -void handle_nr_nfapi_dlsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, - nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, +void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu); void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t harq_pid); diff --git a/openair1/SCHED_NR/nr_ru_procedures.c b/openair1/SCHED_NR/nr_ru_procedures.c index 70f6630aa7..aefeec43e2 100644 --- a/openair1/SCHED_NR/nr_ru_procedures.c +++ b/openair1/SCHED_NR/nr_ru_procedures.c @@ -66,167 +66,197 @@ void nr_feptx0(RU_t *ru,int tti_tx,int first_symbol, int num_symbols, int aa) { //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+(first_symbol!=0?1:0) , 1 ); - slot_offset = slot*fp->samples_per_slot; + slot_offset = fp->get_samples_slot_timestamp(slot,fp,0); slot_offsetF = first_symbol*fp->ofdm_symbol_size; + int abs_first_symbol = slot*fp->symbols_per_slot; - if (first_symbol>0) slot_offset += (fp->ofdm_symbol_size*first_symbol) + (fp->nb_prefix_samples0) + (fp->nb_prefix_samples*(first_symbol-1)); + for (uint16_t idx_sym=abs_first_symbol; idx_symnumerology_index)) ? fp->nb_prefix_samples : fp->nb_prefix_samples0; + + slot_offset += fp->ofdm_symbol_size*first_symbol; LOG_D(PHY,"SFN/SF:RU:TX:%d/%d Generating slot %d (first_symbol %d num_symbols %d)\n",ru->proc.frame_tx, ru->proc.tti_tx,slot,first_symbol,num_symbols); - - if (fp->Ncp == 1) { + + if (fp->Ncp == 1) PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF], (int*)&ru->common.txdata[aa][slot_offset], fp->ofdm_symbol_size, num_symbols, fp->nb_prefix_samples, CYCLIC_PREFIX); - } else { - if (first_symbol==0) { - PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF], - (int*)&ru->common.txdata[aa][slot_offset], - fp->ofdm_symbol_size, - 1, - fp->nb_prefix_samples0, - CYCLIC_PREFIX); - PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF+fp->ofdm_symbol_size], - (int*)&ru->common.txdata[aa][slot_offset+fp->nb_prefix_samples0+fp->ofdm_symbol_size], - fp->ofdm_symbol_size, - num_symbols-1, - fp->nb_prefix_samples, - CYCLIC_PREFIX); + if (fp->numerology_index != 0) { + + if (!(slot%(fp->slots_per_subframe/2))&&(first_symbol==0)) { + PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF], + (int*)&ru->common.txdata[aa][slot_offset], + fp->ofdm_symbol_size, + 1, + fp->nb_prefix_samples0, + CYCLIC_PREFIX); + PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF+fp->ofdm_symbol_size], + (int*)&ru->common.txdata[aa][slot_offset+fp->nb_prefix_samples0+fp->ofdm_symbol_size], + fp->ofdm_symbol_size, + num_symbols-1, + fp->nb_prefix_samples, + CYCLIC_PREFIX); + } + else { + PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF], + (int*)&ru->common.txdata[aa][slot_offset], + fp->ofdm_symbol_size, + num_symbols, + fp->nb_prefix_samples, + CYCLIC_PREFIX); + } } + else { - PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF], - (int*)&ru->common.txdata[aa][slot_offset], - fp->ofdm_symbol_size, - num_symbols, - fp->nb_prefix_samples, - CYCLIC_PREFIX); + for (uint16_t idx_sym=abs_first_symbol; idx_symcommon.txdataF_BF[aa][slot_offsetF], + (int*)&ru->common.txdata[aa][slot_offset], + fp->ofdm_symbol_size, + 1, + fp->nb_prefix_samples, + CYCLIC_PREFIX); + slot_offset += fp->nb_prefix_samples+fp->ofdm_symbol_size; + } + else { + PHY_ofdm_mod(&ru->common.txdataF_BF[aa][slot_offsetF], + (int*)&ru->common.txdata[aa][slot_offset], + fp->ofdm_symbol_size, + 1, + fp->nb_prefix_samples0, + CYCLIC_PREFIX); + slot_offset += fp->nb_prefix_samples0+fp->ofdm_symbol_size; + } + } } } + + //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+(first_symbol!=0?1:0), 0); } void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx) { - nfapi_nr_config_request_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; RU_proc_t *proc = &ru->proc; RU_feptx_t *feptx = proc->feptx; PHY_VARS_gNB *gNB; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - + int slot = tti_tx; + int i = 0; int j = 0;//symbol - int aa = 0;//logical antenna number + int aa = 0;//physical antenna number int ret = 0; - int nb_antenna_ports = fp->L_ssb; int ofdm_mask_full = (1<<(ru->nb_tx*2))-1; int txdataF_offset = ((tti_tx%2)*fp->samples_per_slot_wCP); - if (nr_slot_select(cfg,slot,frame_tx) == SF_UL) return; - for (aa=0; aaLmax; aa++) { - memset(ru->common.txdataF[aa],0,fp->samples_per_slot_wCP*sizeof(int32_t)); - } + if (nr_slot_select(cfg,frame_tx,slot) == NR_UPLINK_SLOT) return; + for (aa=0; aanb_tx; aa++) memset(ru->common.txdataF[aa],0,fp->samples_per_slot_wCP*sizeof(int32_t)); start_meas(&ru->ofdm_total_stats); - if(ru->num_gNB != 0){//L1 RU on same machine - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM , 1 ); - for(j=0; j<2; ++j){//half slot - for(i=0; inb_tx; ++i){ - if(j == 0){ - AssertFatal((ret=pthread_mutex_lock(&feptx[i].mutex_feptx))==0,"mutex_lock return %d\n",ret); - feptx[i].aa = i; - feptx[i].index = i; - feptx[i].ru = ru; - feptx[i].symbol = 0; - feptx[i].slot = slot; - feptx[i].nb_antenna_ports = nb_antenna_ports; - feptx[i].instance_cnt_feptx = 0; - AssertFatal(pthread_cond_signal(&feptx[i].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n"); - AssertFatal((ret=pthread_mutex_unlock(&feptx[i].mutex_feptx))==0,"mutex_lock returns %d\n",ret); - }//first half - else{ - AssertFatal((ret=pthread_mutex_lock(&feptx[i+ru->nb_tx].mutex_feptx))==0,"mutex_lock return %d\n",ret); - feptx[i+ru->nb_tx].aa = i; - feptx[i+ru->nb_tx].index = i+ru->nb_tx; - feptx[i+ru->nb_tx].ru = ru; - feptx[i+ru->nb_tx].symbol = fp->symbols_per_slot>>1; - feptx[i+ru->nb_tx].slot = slot; - feptx[i+ru->nb_tx].nb_antenna_ports = nb_antenna_ports; - feptx[i+ru->nb_tx].instance_cnt_feptx = 0; - AssertFatal(pthread_cond_signal(&feptx[i+ru->nb_tx].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n"); - AssertFatal((ret=pthread_mutex_unlock(&feptx[i+ru->nb_tx].mutex_feptx))==0,"mutex_lock returns %d\n",ret); - }//second half - }//physical antenna - }//half slot - }//if L1 RU on same machine - else{//(RU only machine) - for(j=0; jsymbols_per_slot; ++j){ - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC+j , 1); - start_meas(&ru->txdataF_copy_stats); - if (ru->num_gNB == 1){ - gNB = ru->gNB_list[0]; - cfg = &gNB->gNB_config; - - for(i=0; icommon.txdataF[i][j*fp->ofdm_symbol_size], - (void*)&gNB->common_vars.txdataF[i][j*fp->ofdm_symbol_size + txdataF_offset], - fp->ofdm_symbol_size*sizeof(int32_t)); - } - - }//num_gNB == 1 - stop_meas(&ru->txdataF_copy_stats); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC+j , 0); + //if (nr_slot_select(cfg,frame_tx,slot)==NR_DOWNLINK_SLOT) { + if(ru->num_gNB != 0){//L1 RU on same machine VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM , 1 ); - - if (nr_slot_select(cfg,slot,frame_tx)==SF_DL) { - // If this is not an S-tti + for(j=0; j<2; ++j){//half slot for(i=0; inb_tx; ++i){ - if(j%2 == 0){ - while(feptx[i].instance_cnt_feptx != -1){ - usleep(5); - } + if(j == 0){ AssertFatal((ret=pthread_mutex_lock(&feptx[i].mutex_feptx))==0,"mutex_lock return %d\n",ret); feptx[i].aa = i; feptx[i].index = i; feptx[i].ru = ru; - feptx[i].symbol = j; + feptx[i].symbol = 0; feptx[i].slot = slot; - feptx[i].nb_antenna_ports = nb_antenna_ports; + feptx[i].nb_antenna_ports = ru->nb_tx; feptx[i].instance_cnt_feptx = 0; AssertFatal(pthread_cond_signal(&feptx[i].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n"); AssertFatal((ret=pthread_mutex_unlock(&feptx[i].mutex_feptx))==0,"mutex_lock returns %d\n",ret); - } + }//first half else{ - while(feptx[i+ru->nb_tx].instance_cnt_feptx != -1){ - usleep(5); - } AssertFatal((ret=pthread_mutex_lock(&feptx[i+ru->nb_tx].mutex_feptx))==0,"mutex_lock return %d\n",ret); feptx[i+ru->nb_tx].aa = i; feptx[i+ru->nb_tx].index = i+ru->nb_tx; feptx[i+ru->nb_tx].ru = ru; - feptx[i+ru->nb_tx].symbol = j; + feptx[i+ru->nb_tx].symbol = fp->symbols_per_slot>>1; feptx[i+ru->nb_tx].slot = slot; - feptx[i+ru->nb_tx].nb_antenna_ports = nb_antenna_ports; + feptx[i+ru->nb_tx].nb_antenna_ports = ru->nb_tx; feptx[i+ru->nb_tx].instance_cnt_feptx = 0; AssertFatal(pthread_cond_signal(&feptx[i+ru->nb_tx].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n"); AssertFatal((ret=pthread_mutex_unlock(&feptx[i+ru->nb_tx].mutex_feptx))==0,"mutex_lock returns %d\n",ret); - } - } - - }//if == SF_DL - else { - proc->feptx_mask = ofdm_mask_full; - } - }//jsymbols_per_slot - }//else (RU only machine) + }//second half + }//physical antenna + }//half slot + }//if L1 RU on same machine + else{//(RU only machine) + for(j=0; jsymbols_per_slot; ++j){ + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC+j , 1); + start_meas(&ru->txdataF_copy_stats); + if (ru->num_gNB == 1){ + gNB = ru->gNB_list[0]; + cfg = &gNB->gNB_config; + + for(i=0; inb_tx; ++i){ + memcpy((void*)&ru->common.txdataF[i][j*fp->ofdm_symbol_size], + (void*)&gNB->common_vars.txdataF[i][j*fp->ofdm_symbol_size + txdataF_offset], + fp->ofdm_symbol_size*sizeof(int32_t)); + } + + }//num_gNB == 1 + stop_meas(&ru->txdataF_copy_stats); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC+j , 0); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM , 1 ); + + if (nr_slot_select(cfg,slot,frame_tx)==SF_DL) { + // If this is not an S-tti + for(i=0; inb_tx; ++i){ + if(j%2 == 0){ + while(feptx[i].instance_cnt_feptx != -1){ + usleep(5); + } + AssertFatal((ret=pthread_mutex_lock(&feptx[i].mutex_feptx))==0,"mutex_lock return %d\n",ret); + feptx[i].aa = i; + feptx[i].index = i; + feptx[i].ru = ru; + feptx[i].symbol = j; + feptx[i].slot = slot; + feptx[i].nb_antenna_ports = ru->nb_tx; + feptx[i].instance_cnt_feptx = 0; + AssertFatal(pthread_cond_signal(&feptx[i].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n"); + AssertFatal((ret=pthread_mutex_unlock(&feptx[i].mutex_feptx))==0,"mutex_lock returns %d\n",ret); + } + else{ + while(feptx[i+ru->nb_tx].instance_cnt_feptx != -1){ + usleep(5); + } + AssertFatal((ret=pthread_mutex_lock(&feptx[i+ru->nb_tx].mutex_feptx))==0,"mutex_lock return %d\n",ret); + feptx[i+ru->nb_tx].aa = i; + feptx[i+ru->nb_tx].index = i+ru->nb_tx; + feptx[i+ru->nb_tx].ru = ru; + feptx[i+ru->nb_tx].symbol = j; + feptx[i+ru->nb_tx].slot = slot; + feptx[i+ru->nb_tx].nb_antenna_ports = ru->nb_tx; + feptx[i+ru->nb_tx].instance_cnt_feptx = 0; + AssertFatal(pthread_cond_signal(&feptx[i+ru->nb_tx].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n"); + AssertFatal((ret=pthread_mutex_unlock(&feptx[i+ru->nb_tx].mutex_feptx))==0,"mutex_lock returns %d\n",ret); + } + } + }//if == SF_DL + else { + proc->feptx_mask = ofdm_mask_full; + } + }//jsymbols_per_slot + }//else (RU only machine) + //} // wait all process to finish AssertFatal((ret=pthread_mutex_lock(&proc->mutex_feptx))==0,"mutex_lock return %d\n",ret); while (proc->feptx_mask != ofdm_mask_full) { @@ -256,14 +286,13 @@ static void *nr_feptx_thread(void *param) { int ofdm_mask_full; int txdataF_offset; int32_t *txdataF; - - while (!oai_exit) { - ret = 0; if (wait_on_condition(&feptx->mutex_feptx,&feptx->cond_feptx,&feptx->instance_cnt_feptx,"NR feptx thread")<0) break; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+feptx->index+1 , 1 ); + AssertFatal(feptx->ru->nb_log_antennas>0 && feptx->ru->nb_log_antennas < 13,"ru->nb_log_antennas is %d\n", feptx->ru->nb_log_antennas); + ru = feptx->ru; slot = feptx->slot; aa = feptx->aa; @@ -278,15 +307,10 @@ static void *nr_feptx_thread(void *param) { ////////////precoding//////////// VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC+feptx->index+1 , 1); start_meas(&ru->precoding_stats); - if (ru->nb_tx == 1) { - AssertFatal(fp->N_ssb==ru->nb_tx,"Attempting to transmit %d SSB while Nb_tx = %d",fp->N_ssb,ru->nb_tx); - for (int p=0; pLmax; p++) { - if ((fp->L_ssb >> p) & 0x01){ + if (ru->nb_tx == 1 && ru->nb_log_antennas == 1) { memcpy((void*)&ru->common.txdataF_BF[0][l*fp->ofdm_symbol_size], - (void*)&ru->gNB_list[0]->common_vars.txdataF[p][txdataF_offset + l*fp->ofdm_symbol_size], + (void*)&ru->gNB_list[0]->common_vars.txdataF[0][txdataF_offset + l*fp->ofdm_symbol_size], (fp->samples_per_slot_wCP>>1)*sizeof(int32_t)); - } - } } else { bw = ru->beam_weights[0]; @@ -324,15 +348,10 @@ static void *nr_feptx_thread(void *param) { else{ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC+feptx->index+1 , 1); start_meas(&ru->precoding_stats); - if (ru->nb_tx == 1) { - AssertFatal(fp->N_ssb==ru->nb_tx,"Attempting to transmit %d SSB while Nb_tx = %d",fp->N_ssb,ru->nb_tx); - for (int p=0; pLmax; p++) { - if ((fp->L_ssb >> p) & 0x01){ + if (ru->nb_tx == 1 && ru->nb_log_antennas) { memcpy((void*)&ru->common.txdataF_BF[0][l*fp->ofdm_symbol_size], - (void*)&ru->common.txdataF[p][l*fp->ofdm_symbol_size], + (void*)&ru->common.txdataF[0][l*fp->ofdm_symbol_size], fp->ofdm_symbol_size*sizeof(int32_t)); - } - } } else { bw = ru->beam_weights[0]; @@ -374,30 +393,32 @@ static void *nr_feptx_thread(void *param) { // seems to be hardcoded to numerology 1 (2 slots=1 subframe) void nr_feptx_ofdm(RU_t *ru,int frame_tx,int tti_tx) { + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms; - nfapi_nr_config_request_t *cfg = &ru->gNB_list[0]->gNB_config; + int cyclic_prefix_type = NFAPI_CP_NORMAL; unsigned int aa=0; int slot_sizeF = (fp->ofdm_symbol_size)* - ((cfg->subframe_config.dl_cyclic_prefix_type.value == 1) ? 12 : 14); + ((cyclic_prefix_type == 1) ? 12 : 14); int slot = tti_tx; - int *txdata = &ru->common.txdata[aa][slot*fp->samples_per_slot]; + int *txdata = &ru->common.txdata[aa][fp->get_samples_slot_timestamp(slot,fp,0)]; - if (nr_slot_select(cfg,slot, frame_tx) == SF_UL) return; + if (nr_slot_select(cfg,frame_tx,slot) == NR_UPLINK_SLOT) return; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM , 1 ); start_meas(&ru->ofdm_mod_stats); + // LOG_D(HW,"Frame %d: Generating slot %d\n",frame,next_slot); - nr_feptx0(ru,slot,0,fp->symbols_per_slot,aa); + nr_feptx0(ru,slot,0,NR_NUMBER_OF_SYMBOLS_PER_SLOT,aa); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM , 0 ); stop_meas(&ru->ofdm_mod_stats); LOG_D(PHY,"feptx_ofdm (TXPATH): frame %d, slot %d: txp (time %p) %d dB, txp (freq) %d dB\n", - frame_tx,slot,txdata,dB_fixed(signal_energy((int32_t*)txdata,fp->samples_per_slot)), - dB_fixed(signal_energy_nodc(ru->common.txdataF_BF[aa],2*slot_sizeF))); + frame_tx,slot,txdata,dB_fixed(signal_energy((int32_t*)txdata,fp->get_samples_per_slot( + slot,fp))),dB_fixed(signal_energy_nodc(ru->common.txdataF_BF[aa],2*slot_sizeF))); } @@ -420,39 +441,36 @@ void nr_init_feptx_thread(RU_t *ru) { } -void nr_feptx_prec(RU_t *ru,int frame,int tti_tx) { +void nr_feptx_prec(RU_t *ru,int frame_tx,int tti_tx) { int l,aa; PHY_VARS_gNB **gNB_list = ru->gNB_list,*gNB; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_t *cfg; + nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; int32_t ***bw; int i=0; + int slot_tx = tti_tx; + int txdataF_offset = ((tti_tx%2)*fp->samples_per_slot_wCP); start_meas(&ru->precoding_stats); + AssertFatal(ru->nb_log_antennas > 0,"ru->nb_log_antennas is 0!\n"); if (ru->num_gNB == 1){ gNB = gNB_list[0]; - cfg = &gNB->gNB_config; - if (nr_slot_select(cfg,tti_tx,frame) == SF_UL) return; - for(i=0; iLmax; ++i) + if (nr_slot_select(cfg,frame_tx,slot_tx) == NR_UPLINK_SLOT) return; + + for(i=0; inb_log_antennas; ++i) memcpy((void*)ru->common.txdataF[i], - (void*)gNB->common_vars.txdataF[i], + (void*)&gNB->common_vars.txdataF[i][txdataF_offset], fp->samples_per_slot_wCP*sizeof(int32_t)); - if (ru->nb_tx == 1) { + if (ru->nb_tx == 1 && ru->nb_log_antennas == 1) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC , 1); - AssertFatal(fp->N_ssb==ru->nb_tx,"Attempting to transmit %d SSB while Nb_tx = %d",fp->N_ssb,ru->nb_tx); - - for (int p=0; pLmax; p++) { - if ((fp->L_ssb >> p) & 0x01){ - memcpy((void*)ru->common.txdataF_BF[0], - (void*)ru->common.txdataF[p], - fp->samples_per_slot_wCP*sizeof(int32_t)); - } - } + memcpy((void*)ru->common.txdataF_BF[0], + (void*)ru->common.txdataF[0], + fp->samples_per_slot_wCP*sizeof(int32_t)); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC , 0); }// if (ru->nb_tx == 1) @@ -467,7 +485,7 @@ void nr_feptx_prec(RU_t *ru,int frame,int tti_tx) { tti_tx, l, aa, - fp->Lmax); + ru->nb_log_antennas); }// for (aa=0;aanb_tx;aa++) }// for (l=0;lsymbols_per_slot;l++) }// if (ru->nb_tx == 1) @@ -563,7 +581,7 @@ void nr_fep_full_2thread(RU_t *ru, int slot) { // NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; // if ((fp->frame_type == TDD) && - // (subframe_select(fp,proc->tti_rx) != SF_UL)) return; + // (subframe_select(fp,proc->tti_rx) != NR_UPLINK_SLOT)) return; if (ru->idx == 0) VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX, 1 ); @@ -622,7 +640,7 @@ void nr_fep_full(RU_t *ru, int slot) { NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; // if ((fp->frame_type == TDD) && - // (subframe_select(fp,proc->tti_rx) != SF_UL)) return; + // (subframe_select(fp,proc->tti_rx) != NR_UPLINK_SLOT)) return; start_meas(&ru->ofdm_demod_stats); if (ru->idx == 0) VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX, 1 ); diff --git a/openair1/SCHED_NR/phy_frame_config_nr.h b/openair1/SCHED_NR/phy_frame_config_nr.h index 80cf23b026..d1ec5c80d8 100644 --- a/openair1/SCHED_NR/phy_frame_config_nr.h +++ b/openair1/SCHED_NR/phy_frame_config_nr.h @@ -47,7 +47,7 @@ * @param nrofUplinkSymbols number of uplink symbols @returns 0 if tdd dedicated configuration has been properly set or -1 on error with message */ -int set_tdd_config_nr(NR_DL_FRAME_PARMS *frame_parms, int dl_UL_TransmissionPeriodicity, +int set_tdd_config_nr(nfapi_nr_config_request_scf_t *cfg, int mu, int nrofDownlinkSlots, int nrofDownlinkSymbols, int nrofUplinkSlots, int nrofUplinkSymbols); @@ -78,7 +78,7 @@ int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms); * @param nr_tti : slot number @returns nr_slot_t : downlink or uplink */ -nr_slot_t slot_select_nr(NR_DL_FRAME_PARMS *frame_parms, int nr_frame, int nr_tti); +nr_slot_t nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti); /** \brief This function frees tdd configuration for nr * @param frame_parms NR DL Frame parameters diff --git a/openair1/SCHED_NR/phy_procedures_nr_common.c b/openair1/SCHED_NR/phy_procedures_nr_common.c index f027c62ba0..8d1f615569 100755 --- a/openair1/SCHED_NR/phy_procedures_nr_common.c +++ b/openair1/SCHED_NR/phy_procedures_nr_common.c @@ -33,12 +33,3 @@ #include "sched_nr.h" #include "PHY/INIT/phy_init.h" -nr_subframe_t nr_slot_select(nfapi_nr_config_request_t *cfg, unsigned char slot, int frame) -{ - if (cfg->subframe_config.duplex_mode.value == FDD || slot == NR_DOWNLINK_SLOT || nr_is_ssb_slot(cfg,slot,frame)==1) - return(SF_DL); - else if (slot == NR_UPLINK_SLOT) - return (SF_UL); - - return -1; -} diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index fb6d1a6c37..d9a7ee3c69 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -49,103 +49,78 @@ #include "intertask_interface.h" +uint8_t SSB_Table[38]={0,2,4,6,8,10,12,14,254,254,16,18,20,22,24,26,28,30,254,254,32,34,36,38,40,42,44,46,254,254,48,50,52,54,56,58,60,62}; + extern uint8_t nfapi_mode; -/* -int return_ssb_type(nfapi_config_request_t *cfg) -{ - int mu = cfg->subframe_config.numerology_index_mu.value; - nr_ssb_type_e ssb_type; - switch(mu) { +void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME_PARMS *fp) { - case NR_MU_0: - ssb_type = nr_ssb_type_A; - break; + uint8_t sco = 0; + if (((fp->freq_range == nr_FR1) && (cfg->ssb_table.ssb_subcarrier_offset.value<24)) || + ((fp->freq_range == nr_FR2) && (cfg->ssb_table.ssb_subcarrier_offset.value<12)) ) + sco = cfg->ssb_table.ssb_subcarrier_offset.value; - case NR_MU_1: - ssb_type = nr_ssb_type_B; - break; - - case NR_MU_3: - ssb_type = nr_ssb_type_D; - break; - - case NR_MU_4: - ssb_type = nr_ssb_type_E; - break; - - default: - AssertFatal(0==1, "Invalid numerology index %d for the synchronization block\n", mu); - } - - LOG_D(PHY, "SSB type %d\n", ssb_type); - return ssb_type; - -}*/ - - - -void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_t *cfg, NR_DL_FRAME_PARMS *fp) { - fp->ssb_start_subcarrier = (12 * cfg->sch_config.n_ssb_crb.value + cfg->sch_config.ssb_subcarrier_offset.value)/(1<subframe_config.numerology_index_mu.value); - LOG_D(PHY, "SSB first subcarrier %d (%d,%d)\n", fp->ssb_start_subcarrier,cfg->sch_config.n_ssb_crb.value,cfg->sch_config.ssb_subcarrier_offset.value); + fp->ssb_start_subcarrier = (12 * cfg->ssb_table.ssb_offset_point_a.value + sco); + LOG_D(PHY, "SSB first subcarrier %d (%d,%d)\n", fp->ssb_start_subcarrier,cfg->ssb_table.ssb_offset_point_a.value,sco); } void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) { - NR_DL_FRAME_PARMS *fp=&gNB->frame_parms; - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; - int **txdataF = gNB->common_vars.txdataF; - uint8_t *pbch_pdu=&gNB->pbch_pdu[0]; - uint8_t ssb_index, n_hf; - int ssb_start_symbol, rel_slot; - int txdataF_offset = (slot%2)*fp->samples_per_slot_wCP; - uint16_t slots_per_hf = fp->slots_per_frame / 2; - n_hf = cfg->sch_config.half_frame_index.value; + NR_DL_FRAME_PARMS *fp=&gNB->frame_parms; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; + int **txdataF = gNB->common_vars.txdataF; + uint8_t ssb_index, n_hf; + uint16_t ssb_start_symbol, rel_slot; + int txdataF_offset = (slot%2)*fp->samples_per_slot_wCP; + uint16_t slots_per_hf = (fp->slots_per_frame)>>1; + + n_hf = fp->half_frame_bit; // if SSB periodicity is 5ms, they are transmitted in both half frames - if ( cfg->sch_config.ssb_periodicity.value == 5) { + if ( cfg->ssb_table.ssb_period.value == 0) { if (slot=0) { - for (int i=0; i<2; i++) { // max two SSB per frame - - ssb_index = i + 2*rel_slot; // computing the ssb_index - if ((fp->L_ssb >> ssb_index) & 0x01) { // generating the ssb only if the bit of L_ssb at current ssb index is 1 + if(rel_slot<38 && rel_slot>=0) { // there is no SSB beyond slot 37 + + for (int i=0; i<2; i++) { // max two SSB per frame + + ssb_index = i + SSB_Table[rel_slot]; // computing the ssb_index + + if ((ssb_index<64) && ((fp->L_ssb >> (63-ssb_index)) & 0x01)) { // generating the ssb only if the bit of L_ssb at current ssb index is 1 + fp->ssb_index = ssb_index; + int ssb_start_symbol_abs = nr_get_ssb_start_symbol(fp); // computing the starting symbol for current ssb + ssb_start_symbol = ssb_start_symbol_abs % fp->symbols_per_slot; // start symbol wrt slot + + nr_set_ssb_first_subcarrier(cfg, fp); // setting the first subcarrier - int ssb_start_symbol_abs = nr_get_ssb_start_symbol(fp, ssb_index, n_hf); // computing the starting symbol for current ssb - ssb_start_symbol = ssb_start_symbol_abs % 14; // start symbol wrt slot + LOG_D(PHY,"SS TX: frame %d, slot %d, start_symbol %d\n",frame,slot, ssb_start_symbol); + nr_generate_pss(gNB->d_pss, &txdataF[0][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); + nr_generate_sss(gNB->d_sss, &txdataF[0][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); + + if (cfg->carrier_config.num_tx_ant.value <= 4) + nr_generate_pbch_dmrs(gNB->nr_gold_pbch_dmrs[n_hf][ssb_index&7],&txdataF[0][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); + else + nr_generate_pbch_dmrs(gNB->nr_gold_pbch_dmrs[0][ssb_index&7],&txdataF[0][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); + + nr_generate_pbch(&gNB->pbch, + &gNB->ssb_pdu, + gNB->nr_pbch_interleaver, + &txdataF[0][txdataF_offset], + AMP, + ssb_start_symbol, + n_hf, frame, cfg, fp); - nr_set_ssb_first_subcarrier(cfg, fp); // setting the first subcarrier - - // it is supposed that each logical antenna port correspont to a different beam so each SSB is stored into its own index of txdataF - LOG_D(PHY,"SS TX: frame %d, slot %d, start_symbol %d\n",frame,slot, ssb_start_symbol); - nr_generate_pss(gNB->d_pss, &txdataF[ssb_index][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); - nr_generate_sss(gNB->d_sss, &txdataF[ssb_index][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); - - if (fp->Lmax == 4) - nr_generate_pbch_dmrs(gNB->nr_gold_pbch_dmrs[n_hf][ssb_index],&txdataF[ssb_index][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); - else - nr_generate_pbch_dmrs(gNB->nr_gold_pbch_dmrs[0][ssb_index],&txdataF[ssb_index][txdataF_offset], AMP, ssb_start_symbol, cfg, fp); - - nr_generate_pbch(&gNB->pbch, - pbch_pdu, - gNB->nr_pbch_interleaver, - &txdataF[ssb_index][txdataF_offset], - AMP, - ssb_start_symbol, - n_hf,fp->Lmax,ssb_index, - frame, cfg, fp); - } - } + } + } } } @@ -153,64 +128,71 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, int frame,int slot, int do_meas) { int aa; - uint8_t num_dci=0,num_pdsch_rnti; NR_DL_FRAME_PARMS *fp=&gNB->frame_parms; - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; int offset = gNB->CC_id; - uint8_t ssb_frame_periodicity; // every how many frames SSB are generated + uint8_t ssb_frame_periodicity = 1; // every how many frames SSB are generated int txdataF_offset = (slot%2)*fp->samples_per_slot_wCP; - if (cfg->sch_config.ssb_periodicity.value < 20) - ssb_frame_periodicity = 1; - else - ssb_frame_periodicity = (cfg->sch_config.ssb_periodicity.value)/10 ; // 10ms is the frame length + + + if (cfg->ssb_table.ssb_period.value > 1) + ssb_frame_periodicity = 1 <<(cfg->ssb_table.ssb_period.value -1) ; - if ((cfg->subframe_config.duplex_mode.value == TDD) && (nr_slot_select(cfg,slot,frame)==SF_UL)) return; + if ((cfg->cell_config.frame_duplex_type.value == TDD) && + (nr_slot_select(cfg,frame,slot) == NR_UPLINK_SLOT)) return; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,1); if (do_meas==1) start_meas(&gNB->phy_proc_tx); // clear the transmit data array for the current subframe - for (aa=0; aaLmax; aa++) { + for (aa=0; aacarrier_config.num_tx_ant.value; aa++) { memset(&gNB->common_vars.txdataF[aa][txdataF_offset],0,fp->samples_per_slot_wCP*sizeof(int32_t)); } VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,1); if (nfapi_mode == 0 || nfapi_mode == 1) { - if (!(frame%ssb_frame_periodicity)) // generate SSB only for given frames according to SSB periodicity + if ((!(frame%ssb_frame_periodicity))) // generate SSB only for given frames according to SSB periodicity nr_common_signal_procedures(gNB,frame, slot); } VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,0); - num_dci = gNB->pdcch_vars.num_dci; - num_pdsch_rnti = gNB->pdcch_vars.num_pdsch_rnti; - - for (int i=0; iMod_id, frame, slot, num_dci); + if (gNB->pdcch_pdu || gNB->ul_dci_pdu) { + LOG_D(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL DCI %d/%d)\n", + gNB->Mod_id, frame, slot, + gNB->ul_dci_pdu==NULL?0:gNB->ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15.numDlDci, + gNB->pdcch_pdu==NULL?0:gNB->pdcch_pdu->pdcch_pdu_rel15.numDlDci); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,1); - nr_generate_dci_top(gNB->pdcch_vars.dci_alloc[i], - gNB->nr_gold_pdcch_dmrs[slot], - &gNB->common_vars.txdataF[0][txdataF_offset], // hardcoded to beam 0 - AMP, *fp, *cfg); - + nr_generate_dci_top(gNB->pdcch_pdu, + gNB->ul_dci_pdu, + gNB->nr_gold_pdcch_dmrs[slot], + &gNB->common_vars.txdataF[0][txdataF_offset], + AMP, *fp); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0); } - - for (int i=0; inum_pdsch_rnti); + for (int i=0; inum_pdsch_rnti; i++) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1); - LOG_D(PHY, "PDSCH generation started (%d)\n", num_pdsch_rnti); nr_generate_pdsch(gNB->dlsch[i][0], - &gNB->pdcch_vars.dci_alloc[i], gNB->nr_gold_pdsch_dmrs[slot], gNB->common_vars.txdataF, - AMP, frame, slot, fp, cfg, + AMP, frame, slot, fp, 0, &gNB->dlsch_encoding_stats, &gNB->dlsch_scrambling_stats, - &gNB->dlsch_modulation_stats); + &gNB->dlsch_modulation_stats, + &gNB->tinput, + &gNB->tprep, + &gNB->tparity, + &gNB->toutput, + &gNB->dlsch_rate_matching_stats, + &gNB->dlsch_interleaving_stats, + &gNB->dlsch_segmentation_stats); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0); } @@ -218,86 +200,84 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, } -void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int UE_id, uint8_t harq_pid) + +/* + + if ((cfg->subframe_config.duplex_mode.value == TDD) && + ((nr_slot_select(fp,frame,slot)&NR_DOWNLINK_SLOT)==SF_DL)) return; + + // VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX,1); + + + if (do_prach_rx(fp,frame,slot)) L1_nr_prach_procedures(gNB,frame,slot/fp->slots_per_subframe); +*/ + +void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH_id, uint8_t harq_pid) { - NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *nfapi_ulsch_pdu_rel15 = &rel15_ul->ulsch_pdu_rel15; + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; + nfapi_nr_pusch_pdu_t *pusch_pdu = &gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->ulsch_pdu; uint8_t ret; uint8_t l, number_dmrs_symbols = 0; - uint8_t mapping_type; uint32_t G; - int Nid_cell = 0; // [hna] shouldn't be a local variable (should be signaled) uint16_t start_symbol, number_symbols, nb_re_dmrs; - mapping_type = gNB->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; - - start_symbol = nfapi_ulsch_pdu_rel15->start_symbol; - number_symbols = nfapi_ulsch_pdu_rel15->number_symbols; + start_symbol = pusch_pdu->start_symbol_index; + number_symbols = pusch_pdu->nr_of_symbols; for (l = start_symbol; l < start_symbol + number_symbols; l++) - number_dmrs_symbols += is_dmrs_symbol(l, - 0, - 0, - 0, - 0, - 0, - number_symbols, - &gNB->dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); + number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; - nb_re_dmrs = ((gNB->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; + nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4); - G = nr_get_G(nfapi_ulsch_pdu_rel15->number_rbs, + G = nr_get_G(pusch_pdu->rb_size, number_symbols, nb_re_dmrs, - nfapi_ulsch_pdu_rel15->length_dmrs, - nfapi_ulsch_pdu_rel15->Qm, - nfapi_ulsch_pdu_rel15->n_layers); + number_dmrs_symbols, // number of dmrs symbols irrespective of single or double symbol dmrs + pusch_pdu->qam_mod_order, + pusch_pdu->nrOfLayers); //---------------------------------------------------------- //------------------- ULSCH unscrambling ------------------- //---------------------------------------------------------- - nr_ulsch_unscrambling(gNB->pusch_vars[UE_id]->llr, + nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr, G, 0, - Nid_cell, - rel15_ul->rnti); + pusch_pdu->data_scrambling_id, + pusch_pdu->rnti); //---------------------------------------------------------- //--------------------- ULSCH decoding --------------------- //---------------------------------------------------------- ret = nr_ulsch_decoding(gNB, - UE_id, - gNB->pusch_vars[UE_id]->llr, - frame_parms, - frame_rx, - number_symbols, - nb_re_dmrs, - slot_rx, - harq_pid, - 0); + ULSCH_id, + gNB->pusch_vars[ULSCH_id]->llr, + frame_parms, + pusch_pdu, + frame_rx, + slot_rx, + harq_pid, + G); + - if (ret > gNB->ulsch[UE_id][0]->max_ldpc_iterations) - LOG_I(PHY, "ULSCH in error\n"); - //gNB->ulsch[UE_id+1][0]->harq_processes[harq_pid]->b - else if(gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->b!=NULL){ + if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations) + LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id); + //gNB->ulsch[ULSCH_id+1][0]->harq_processes[harq_pid]->b + else if(gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->b!=NULL){ LOG_I(PHY, "ULSCH received ok \n"); - if(IS_SOFTMODEM_NOS1){ //&& gNB->ulsch[UE_id][0]->rnti == 0x1234 - nr_fill_crc_indication (gNB,frame_rx, slot_rx, UE_id, 0); - nr_fill_rx_indication(gNB, frame_rx, slot_rx, UE_id, harq_pid); + if(IS_SOFTMODEM_NOS1){ //&& gNB->ulsch[ULSCH_id][0]->rnti == 0x1234 + nr_fill_crc_indication(gNB,frame_rx, slot_rx, ULSCH_id, 0); + nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); } } } -void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t harq_pid) +void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_id, uint8_t harq_pid) { // -------------------- // [hna] TO BE CLEANED @@ -308,32 +288,33 @@ void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, int timing_advance_update; int sync_pos; - NR_gNB_ULSCH_t *ulsch = gNB->ulsch[UE_id][0]; + uint16_t mu = gNB->frame_parms.numerology_index; + // pthread_mutex_lock(&gNB->UL_INFO_mutex); + NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ULSCH_id][0]; NR_UL_gNB_HARQ_t *harq_process = ulsch->harq_processes[harq_pid]; - uint16_t mu = gNB->gNB_config.subframe_config.numerology_index_mu.value; - pthread_mutex_lock(&gNB->UL_INFO_mutex); gNB->UL_INFO.rx_ind.sfn_sf = frame<<4| slot_rx; gNB->UL_INFO.rx_ind.rx_indication_body.tl.tag = NFAPI_RX_INDICATION_BODY_TAG; - gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list->rx_indication_rel8.length = gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->TBS>>3; + gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list->rx_indication_rel8.length = gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->TBS; pdu = &gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list[gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus]; - //pdu->rx_ue_information.handle = gNB->ulsch[UE_id+1][0]->handle; + //pdu->rx_ue_information.handle = gNB->ulsch[ULSCH_id+1][0]->handle; pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = gNB->ulsch[UE_id][0]->rnti; + pdu->rx_ue_information.rnti = gNB->ulsch[ULSCH_id][0]->rnti; pdu->rx_indication_rel8.tl.tag = NFAPI_RX_INDICATION_REL8_TAG; pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation - pdu->data = harq_process->b;//gNB->ulsch[UE_id+1][0]->harq_processes[harq_pid]->b; + pdu->data = harq_process->b;//gNB->ulsch[ULSCH_id+1][0]->harq_processes[harq_pid]->b; // estimate timing advance for MAC - sync_pos = nr_est_timing_advance_pusch(gNB, UE_id); + sync_pos = nr_est_timing_advance_pusch(gNB, ULSCH_id); timing_advance_update = sync_pos; // - gNB->frame_parms.nb_prefix_samples/4; //to check // printf("\x1B[33m" "timing_advance_update = %d\n" "\x1B[0m", timing_advance_update); - //pdu->data = gNB->ulsch[UE_id+1][0]->harq_processes[harq_pid]->b; - sync_pos = nr_est_timing_advance_pusch(gNB, UE_id); // estimate timing advance for MAC + + // pdu->data = gNB->ulsch[ULSCH_id+1][0]->harq_processes[harq_pid]->b; + sync_pos = nr_est_timing_advance_pusch(gNB, ULSCH_id); // estimate timing advance for MAC timing_advance_update = sync_pos * (1 << mu); // scale by the used scs numerology // scale the 16 factor in N_TA calculation in 38.213 section 4.2 according to the used FFT size @@ -342,6 +323,7 @@ void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, case 217: timing_advance_update /= 32; break; case 245: timing_advance_update /= 32; break; case 273: timing_advance_update /= 32; break; + case 66: timing_advance_update /= 12; break; default: abort(); } @@ -356,7 +338,7 @@ void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, pdu->rx_indication_rel8.timing_advance = timing_advance_update; // estimate UL_CQI for MAC (from antenna port 0 only) - int SNRtimes10 = dB_fixed_times10(gNB->pusch_vars[UE_id]->ulsch_power[0]) - 300;//(10*gNB->measurements.n0_power_dB[0]); + int SNRtimes10 = dB_fixed_times10(gNB->pusch_vars[ULSCH_id]->ulsch_power[0]) - 300;//(10*gNB->measurements.n0_power_dB[0]); if (SNRtimes10 < -640) pdu->rx_indication_rel8.ul_cqi=0; else if (SNRtimes10 > 635) pdu->rx_indication_rel8.ul_cqi=255; @@ -372,7 +354,7 @@ void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, pthread_mutex_unlock(&gNB->UL_INFO_mutex); } -void nr_fill_crc_indication (PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t crc_flag) { +void nr_fill_crc_indication (PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_id, uint8_t crc_flag) { pthread_mutex_lock(&gNB->UL_INFO_mutex); nfapi_crc_indication_pdu_t *pdu = &gNB->UL_INFO. crc_ind.crc_indication_body.crc_pdu_list[gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs]; gNB->UL_INFO.crc_ind.sfn_sf = frame<<4 | slot_rx; @@ -381,7 +363,7 @@ void nr_fill_crc_indication (PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_i pdu->instance_length = 0; // don't know what to do with this // pdu->rx_ue_information.handle = handle; pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = gNB->ulsch[UE_id][0]->rnti; + pdu->rx_ue_information.rnti = gNB->ulsch[ULSCH_id][0]->rnti; pdu->crc_indication_rel8.tl.tag = NFAPI_CRC_INDICATION_REL8_TAG; pdu->crc_indication_rel8.crc_flag = crc_flag; gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs++; @@ -420,24 +402,25 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) for (int i = 0; i < num_pusch_pdu; i++) { switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - { - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); + case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:{ + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); - - uint8_t UE_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); - uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; - uint8_t symbol_start = pusch_pdu->start_symbol_index; - uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; - - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, UE_id, frame_rx, slot_rx, symbol, harq_pid); - } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[UE_id]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[UE_id]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, UE_id, harq_pid); + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); + + uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); + uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; + uint8_t symbol_start = pusch_pdu->start_symbol_index; + uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; + + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); + nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC + nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); } } } diff --git a/openair1/SCHED_NR/sched_nr.h b/openair1/SCHED_NR/sched_nr.h index 5b53aa919a..5f54539b71 100644 --- a/openair1/SCHED_NR/sched_nr.h +++ b/openair1/SCHED_NR/sched_nr.h @@ -32,10 +32,10 @@ #include "PHY_INTERFACE/phy_interface.h" #include "SCHED/sched_eNB.h" #include "PHY/NR_TRANSPORT/nr_dci.h" +#include "phy_frame_config_nr.h" -nr_slot_t nr_slot_select (nfapi_nr_config_request_t *cfg, unsigned char slot, int frame); -void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_t *cfg, NR_DL_FRAME_PARMS *fp); +void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME_PARMS *fp); void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, int frame_tx, int slot_tx, int do_meas); void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx); void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx); @@ -54,16 +54,4 @@ void nr_fep_full_2thread(RU_t *ru, int slot); void feptx_prec(RU_t *ru,int frame_tx,int tti_tx); int nr_phy_init_RU(RU_t *ru); -void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, - nr_scs_e scs_common, - nr_scs_e pdcch_scs, - nr_frequency_range_e freq_range, - uint8_t rmsi_pdcch_config, - uint8_t ssb_idx, - uint8_t k_ssb, - uint16_t sfn_ssb, - uint8_t n_ssb, - uint16_t nb_slots_per_frame, - uint16_t N_RB); - #endif diff --git a/openair1/SCHED_NR_UE/defs.h b/openair1/SCHED_NR_UE/defs.h index 7a4a552483..e34ce2b6de 100644 --- a/openair1/SCHED_NR_UE/defs.h +++ b/openair1/SCHED_NR_UE/defs.h @@ -376,11 +376,10 @@ void nr_compute_srs_pos(lte_frame_type_t frameType,uint16_t isrs,uint16_t *psrsP void set_tx_harq_id(NR_UE_ULSCH_t *ulsch, int harq_pid, int slot_tx); int get_tx_harq_id(NR_UE_ULSCH_t *ulsch, int slot_tx); -int is_pbch_in_slot(fapi_nr_pbch_config_t *pbch_config, int frame, int slot, int periodicity, uint16_t slots_per_frame); +int is_pbch_in_slot(fapi_nr_config_request_t *config, int frame, int slot, NR_DL_FRAME_PARMS *fp); /*@}*/ #endif - diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 1b61260d10..69876159d6 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -51,10 +51,9 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) uint8_t cc_id = scheduled_response->CC_id; uint32_t i; int slot = scheduled_response->slot; - // Note: we have to handle the thread IDs for this. To be revisited completely. uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; - NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; + NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; @@ -66,40 +65,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) if(scheduled_response->dl_config != NULL){ fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config; + LOG_D(PHY,"Received %d DL pdus\n",dl_config->number_pdus); + pdcch_vars->nb_search_space = 0; for(i=0; inumber_pdus; ++i){ if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){ - pdcch_vars2->nb_search_space = pdcch_vars2->nb_search_space + 1; - fapi_nr_dl_config_dci_dl_pdu_rel15_t *dci_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15; - - pdcch_vars2->n_RB_BWP[i] = dci_config->N_RB_BWP; - pdcch_vars2->searchSpace[i].monitoringSymbolWithinSlot = dci_config->monitoring_symbols_within_slot; - - pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel1 = dci_config->number_of_candidates[0]; - pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel2 = dci_config->number_of_candidates[1]; - pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel4 = dci_config->number_of_candidates[2]; - pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel8 = dci_config->number_of_candidates[3]; - pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel16 = dci_config->number_of_candidates[4]; - - pdcch_vars2->coreset[i].duration = dci_config->coreset.duration; - - pdcch_vars2->coreset[i].frequencyDomainResources = dci_config->coreset.frequency_domain_resource; - pdcch_vars2->coreset[i].rb_offset = dci_config->coreset.rb_offset; - - if(dci_config->coreset.cce_reg_mapping_type == CCE_REG_MAPPING_TYPE_INTERLEAVED){ - pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = dci_config->coreset.cce_reg_interleaved_shift_index; - pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = dci_config->coreset.cce_reg_interleaved_reg_bundle_size; - pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = dci_config->coreset.cce_reg_interleaved_interleaver_size; - }else{ //CCE_REG_MAPPING_TYPE_NON_INTERLEAVED - pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = 0; - pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = 6; - pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = 1; - } - - pdcch_vars2->coreset[i].precoderGranularity = dci_config->coreset.precoder_granularity; - //pdcch_vars2->coreset[i].tciStatesPDCCH; - //pdcch_vars2->coreset[i].tciPresentInDCI; - pdcch_vars2->coreset[i].pdcchDMRSScramblingID = dci_config->coreset.pdcch_dmrs_scrambling_id; - + fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15; + memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config)); + pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1; + LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space); }else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH // dlsch config pdu @@ -113,11 +86,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; - + dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; + dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; + dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; + dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; dlsch0_harq->mcs = dlsch_config_pdu->mcs; dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; dlsch0_harq->rvidx = dlsch_config_pdu->rv; @@ -132,7 +108,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) } } }else{ - pdcch_vars2->nb_search_space = 0; + pdcch_vars->nb_search_space = 0; } if(scheduled_response->ul_config != NULL){ @@ -218,43 +194,10 @@ int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){ fapi_nr_config_request_t *nrUE_config = &PHY_vars_UE_g[phy_config->Mod_id][phy_config->CC_id]->nrUE_config; - if(phy_config != NULL){ - if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_PBCH){ - LOG_I(MAC,"[L1][IF module][PHY CONFIG]\n"); - LOG_I(MAC,"subcarrier spacing: %d\n", phy_config->config_req.pbch_config.subcarrier_spacing_common); - LOG_I(MAC,"ssb carrier offset: %d\n", phy_config->config_req.pbch_config.ssb_subcarrier_offset); - LOG_I(MAC,"dmrs type A position: %d\n", phy_config->config_req.pbch_config.dmrs_type_a_position); - LOG_I(MAC,"pdcch config sib1: %d\n", phy_config->config_req.pbch_config.pdcch_config_sib1); - LOG_I(MAC,"cell barred: %d\n", phy_config->config_req.pbch_config.cell_barred); - LOG_I(MAC,"intra frequency reselection: %d\n", phy_config->config_req.pbch_config.intra_frequency_reselection); - LOG_I(MAC,"system frame number: %d\n", phy_config->config_req.pbch_config.system_frame_number); - LOG_I(MAC,"ssb index: %d\n", phy_config->config_req.pbch_config.ssb_index); - LOG_I(MAC,"half frame bit: %d\n", phy_config->config_req.pbch_config.half_frame_bit); - LOG_I(MAC,"-------------------------------\n"); - - memcpy(&nrUE_config->pbch_config,&phy_config->config_req.pbch_config,sizeof(fapi_nr_pbch_config_t)); - - } - - if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_COMMON){ - - } - - if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_COMMON){ - - } - - if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED){ - - } - - if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED){ - - } - } + if(phy_config != NULL) + memcpy(nrUE_config,&phy_config->config_req,sizeof(fapi_nr_config_request_t)); - - return 0; } + diff --git a/openair1/SCHED_NR_UE/phy_frame_config_nr.c b/openair1/SCHED_NR_UE/phy_frame_config_nr.c deleted file mode 100644 index fc1c459ba4..0000000000 --- a/openair1/SCHED_NR_UE/phy_frame_config_nr.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*********************************************************************** -* -* FILENAME : phy_frame_configuration_nr.c -* -* DESCRIPTION : functions related to FDD/TDD configuration for NR -* see TS 38.213 11.1 Slot configuration -* and TS 38.331 for RRC configuration -* -************************************************************************/ - -#include "SCHED_NR_UE/defs.h" -#include "PHY/defs_nr_UE.h" -#include "SCHED_NR_UE/phy_frame_config_nr.h" - -/******************************************************************* -* -* NAME : set_tdd_configuration -* -* PARAMETERS : pointer to frame configuration -* -* OUTPUT: table of uplink symbol for each slot for 2 frames -* -* RETURN : 0 if tdd has been properly configurated -* -1 tdd configuration can not be done -* -* DESCRIPTION : generate bit map for uplink symbol for each slot for several frames -* see TS 38.213 11.1 Slot configuration -* -*********************************************************************/ - -int set_tdd_config_nr(NR_DL_FRAME_PARMS *frame_parms, int dl_UL_TransmissionPeriodicity, - int nrofDownlinkSlots, int nrofDownlinkSymbols, - int nrofUplinkSlots, int nrofUplinkSymbols) -{ - TDD_UL_DL_configCommon_t *p_tdd_ul_dl_configuration; - int slot_number = 0; - int nb_slots_to_set = TDD_CONFIG_NB_FRAMES*(frame_parms->ttis_per_subframe * LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); - - /* allocate buffer for configuration structure */ - p_tdd_ul_dl_configuration = calloc( 1, sizeof(TDD_UL_DL_configCommon_t)); - - if (p_tdd_ul_dl_configuration == NULL) { - printf("Error test_frame_configuration: memory allocation problem \n"); - assert(0); - } - else { - frame_parms->frame_type = TDD; - } - - p_tdd_ul_dl_configuration->dl_UL_TransmissionPeriodicity = dl_UL_TransmissionPeriodicity; - p_tdd_ul_dl_configuration->nrofDownlinkSlots = nrofDownlinkSlots; - p_tdd_ul_dl_configuration->nrofDownlinkSymbols = nrofDownlinkSymbols; - p_tdd_ul_dl_configuration->nrofUplinkSlots = nrofUplinkSlots; - p_tdd_ul_dl_configuration->nrofUplinkSymbols = nrofUplinkSymbols; - - frame_parms->p_tdd_UL_DL_Configuration = p_tdd_ul_dl_configuration; - - int nb_periods_per_frame = (FRAME_DURATION_MICRO_SEC/dl_UL_TransmissionPeriodicity); - - int nb_slots_per_period = (frame_parms->ttis_per_subframe * LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)/nb_periods_per_frame; - - if (nb_slots_per_period != (nrofDownlinkSlots + nrofUplinkSlots)) { - LOG_E(PHY,"set_tdd_configuration_nr: given period is inconsistent with current tdd configuration \n"); - return (-1); - } - - while(slot_number != nb_slots_to_set) { - - for (int number_of_slot = 0; number_of_slot < nrofDownlinkSlots; number_of_slot++) { - frame_parms->tdd_uplink_nr[slot_number] = NR_TDD_DOWNLINK_SLOT; - slot_number++; - } - - if (p_tdd_ul_dl_configuration->nrofDownlinkSymbols != 0) { - LOG_E(PHY,"set_tdd_configuration_nr: downlink symbol for slot is not supported for tdd configuration \n"); - return (-1); - } - - for (int number_of_slot = 0; number_of_slot < nrofUplinkSlots; number_of_slot++) { - frame_parms->tdd_uplink_nr[slot_number] = NR_TDD_UPLINK_SLOT; - slot_number++; - } - - if (p_tdd_ul_dl_configuration->nrofUplinkSymbols != 0) { - LOG_E(PHY,"set_tdd_configuration_nr: uplink symbol for slot is not supported for tdd configuration \n"); - return (-1); - } - } - - if (frame_parms->p_tdd_UL_DL_ConfigurationCommon2 != NULL) { - LOG_E(PHY,"set_tdd_configuration_nr: additionnal tdd configuration 2 is not supported for tdd configuration \n"); - return (-1); - } - - return (0); -} - -/******************************************************************* -* -* NAME : add_tdd_dedicated_configuration_nr -* -* PARAMETERS : pointer to frame configuration -* -* OUTPUT: table of uplink symbol for each slot for several frames -* -* RETURN : 0 if tdd has been properly configurated -* -1 tdd configuration can not be done -* -* DESCRIPTION : generate bit map for uplink symbol for each slot for several frames -* see TS 38.213 11.1 Slot configuration -* -*********************************************************************/ - -void add_tdd_dedicated_configuration_nr(NR_DL_FRAME_PARMS *frame_parms, int slotIndex, int nrofDownlinkSymbols, int nrofUplinkSymbols) -{ - TDD_UL_DL_SlotConfig_t *p_TDD_UL_DL_ConfigDedicated = frame_parms->p_TDD_UL_DL_ConfigDedicated; - TDD_UL_DL_SlotConfig_t *p_previous_TDD_UL_DL_ConfigDedicated; - int next = 0; - - while (p_TDD_UL_DL_ConfigDedicated != NULL) { - p_previous_TDD_UL_DL_ConfigDedicated = p_TDD_UL_DL_ConfigDedicated; - p_TDD_UL_DL_ConfigDedicated = (TDD_UL_DL_SlotConfig_t *)(p_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig); - next = 1; - } - - p_TDD_UL_DL_ConfigDedicated = calloc( 1, sizeof(TDD_UL_DL_SlotConfig_t)); - //printf("allocate pt %p \n", p_TDD_UL_DL_ConfigDedicated); - if (p_TDD_UL_DL_ConfigDedicated == NULL) { - printf("Error test_frame_configuration: memory allocation problem \n"); - assert(0); - } - - if (next == 0) { - frame_parms->p_TDD_UL_DL_ConfigDedicated = p_TDD_UL_DL_ConfigDedicated; - } - else { - p_previous_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig = (struct TDD_UL_DL_SlotConfig_t *)p_TDD_UL_DL_ConfigDedicated; - } - - p_TDD_UL_DL_ConfigDedicated->slotIndex = slotIndex; - p_TDD_UL_DL_ConfigDedicated->nrofDownlinkSymbols = nrofDownlinkSymbols; - p_TDD_UL_DL_ConfigDedicated->nrofUplinkSymbols = nrofUplinkSymbols; -} - -/******************************************************************* -* -* NAME : set_tdd_configuration_dedicated_nr -* -* PARAMETERS : pointer to frame configuration -* -* OUTPUT: table of uplink symbol for each slot for several frames -* -* RETURN : 0 if tdd has been properly configurated -* -1 tdd configuration can not be done -* -* DESCRIPTION : generate bit map for uplink symbol for each slot for several frames -* see TS 38.213 11.1 Slot configuration -* -*********************************************************************/ - -int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms) -{ - TDD_UL_DL_SlotConfig_t *p_current_TDD_UL_DL_SlotConfig; - - p_current_TDD_UL_DL_SlotConfig = frame_parms->p_TDD_UL_DL_ConfigDedicated; - - NR_TST_PHY_PRINTF("\nSet tdd dedicated configuration\n "); - - while(p_current_TDD_UL_DL_SlotConfig != NULL) { - int slot_index = p_current_TDD_UL_DL_SlotConfig->slotIndex; - if (slot_index < TDD_CONFIG_NB_FRAMES*(frame_parms->ttis_per_subframe * LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)) { - if (p_current_TDD_UL_DL_SlotConfig->nrofDownlinkSymbols != 0) { - if (p_current_TDD_UL_DL_SlotConfig->nrofDownlinkSymbols == NR_TDD_SET_ALL_SYMBOLS) { - if (p_current_TDD_UL_DL_SlotConfig->nrofUplinkSymbols == 0) { - frame_parms->tdd_uplink_nr[slot_index] = NR_TDD_DOWNLINK_SLOT; - NR_TST_PHY_PRINTF(" DL[%d] ", slot_index); - } - else { - LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd downlink & uplink symbol configuration is not supported \n"); - return (-1); - } - } - else { - LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd downlink symbol configuration is not supported \n"); - return (-1); - } - } - else if (p_current_TDD_UL_DL_SlotConfig->nrofUplinkSymbols != 0) { - if (p_current_TDD_UL_DL_SlotConfig->nrofUplinkSymbols == NR_TDD_SET_ALL_SYMBOLS) { - frame_parms->tdd_uplink_nr[slot_index] = NR_TDD_UPLINK_SLOT; - NR_TST_PHY_PRINTF(" UL[%d] ", slot_index); - } - else { - LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd uplink symbol configuration is not supported \n"); - return (-1); - } - } - else { - LOG_E(PHY,"set_tdd_configuration_dedicated_nr: no tdd symbol configuration is specified \n"); - return (-1); - } - } - else { - LOG_E(PHY,"set_tdd_configuration_dedicated_nr: tdd slot index exceeds maximum value \n"); - return (-1); - } - - p_current_TDD_UL_DL_SlotConfig = (TDD_UL_DL_SlotConfig_t *)(p_current_TDD_UL_DL_SlotConfig->p_next_TDD_UL_DL_SlotConfig); - } - NR_TST_PHY_PRINTF("\n"); - return (0); -} - -/******************************************************************* -* -* NAME : set_tdd_configuration -* -* PARAMETERS : pointer to tdd common configuration -* pointer to tdd common configuration2 -* pointer to tdd dedicated configuration -* -* OUTPUT: table of uplink symbol for each slot for 2 frames -* -* RETURN : 0 if srs sequence has been successfully generated -* -1 if sequence can not be properly generated -* -* DESCRIPTION : generate bit map for uplink symbol for each slot for 2 frames -* see TS 38.213 11.1 Slot configuration -* -*********************************************************************/ - -int slot_select_nr(NR_DL_FRAME_PARMS *frame_parms, int nr_frame, int nr_tti) -{ - /* for FFD all slot can be considered as an uplink */ - if (frame_parms->frame_type == FDD) { - return (NR_UPLINK_SLOT | NR_DOWNLINK_SLOT ); - } - - if (nr_frame%2 == 0) { - if (frame_parms->tdd_uplink_nr[nr_tti] == NR_TDD_UPLINK_SLOT) { - return (NR_UPLINK_SLOT); - } - else { - return (NR_DOWNLINK_SLOT); - } - } - else if ((frame_parms->tdd_uplink_nr[(frame_parms->ttis_per_subframe * LTE_NUMBER_OF_SUBFRAMES_PER_FRAME) + nr_tti] == NR_TDD_UPLINK_SLOT)) { - return (NR_UPLINK_SLOT); - } - else { - return (NR_DOWNLINK_SLOT); - } -} - -/******************************************************************* -* -* NAME : free_tdd_configuration_nr -* -* PARAMETERS : pointer to frame configuration -* -* RETURN : none -* -* DESCRIPTION : free structure related to tdd configuration -* -*********************************************************************/ - -void free_tdd_configuration_nr(NR_DL_FRAME_PARMS *frame_parms) -{ - TDD_UL_DL_configCommon_t *p_tdd_UL_DL_Configuration = frame_parms->p_tdd_UL_DL_Configuration; - - free_tdd_configuration_dedicated_nr(frame_parms); - - if (p_tdd_UL_DL_Configuration != NULL) { - frame_parms->p_tdd_UL_DL_Configuration = NULL; - free(p_tdd_UL_DL_Configuration); - } - - for (int number_of_slot = 0; number_of_slot < NR_MAX_SLOTS_PER_FRAME; number_of_slot++) { - frame_parms->tdd_uplink_nr[number_of_slot] = NR_TDD_DOWNLINK_SLOT; - } -} - -/******************************************************************* -* -* NAME : free_tdd_configuration_dedicated_nr -* -* PARAMETERS : pointer to frame configuration -* -* RETURN : none -* -* DESCRIPTION : free structure related to tdd dedicated configuration -* -*********************************************************************/ - -void free_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms) -{ - TDD_UL_DL_SlotConfig_t *p_current_TDD_UL_DL_ConfigDedicated = frame_parms->p_TDD_UL_DL_ConfigDedicated; - TDD_UL_DL_SlotConfig_t *p_next_TDD_UL_DL_ConfigDedicated; - int next = 0; - if (p_current_TDD_UL_DL_ConfigDedicated != NULL) { - do { - if (p_current_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig != NULL) { - next = 1; - p_next_TDD_UL_DL_ConfigDedicated = (TDD_UL_DL_SlotConfig_t *)(p_current_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig); - p_current_TDD_UL_DL_ConfigDedicated->p_next_TDD_UL_DL_SlotConfig = NULL; - //printf("free pt %p \n", p_current_TDD_UL_DL_ConfigDedicated); - free(p_current_TDD_UL_DL_ConfigDedicated); - p_current_TDD_UL_DL_ConfigDedicated = p_next_TDD_UL_DL_ConfigDedicated; - } - else { - if (p_current_TDD_UL_DL_ConfigDedicated != NULL) { - frame_parms->p_TDD_UL_DL_ConfigDedicated = NULL; - //printf("free pt %p \n", p_current_TDD_UL_DL_ConfigDedicated); - free(p_current_TDD_UL_DL_ConfigDedicated); - next = 0; - } - } - } while (next); - } -} - diff --git a/openair1/SCHED_NR_UE/phy_frame_config_nr.h b/openair1/SCHED_NR_UE/phy_frame_config_nr.h index 429dff221b..a939584584 100644 --- a/openair1/SCHED_NR_UE/phy_frame_config_nr.h +++ b/openair1/SCHED_NR_UE/phy_frame_config_nr.h @@ -36,18 +36,6 @@ /*************** FUNCTIONS *****************************************/ -/** \brief This function processes tdd dedicated configuration for nr - * @param frame_parms NR DL Frame parameters - * @param dl_UL_TransmissionPeriodicity periodicity - * @param nrofDownlinkSlots number of downlink slots - * @param nrofDownlinkSymbols number of downlink symbols - * @param nrofUplinkSlots number of uplink slots - * @param nrofUplinkSymbols number of uplink symbols - @returns 0 if tdd dedicated configuration has been properly set or -1 on error with message */ - -int set_tdd_config_nr(NR_DL_FRAME_PARMS *frame_parms, int dl_UL_TransmissionPeriodicity, - int nrofDownlinkSlots, int nrofDownlinkSymbols, - int nrofUplinkSlots, int nrofUplinkSymbols); /** \brief This function adds a slot configuration to current dedicated configuration for nr * @param frame_parms NR DL Frame parameters diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index d0272b5dd7..509f4b6021 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -49,7 +49,7 @@ //#include //#include "targets/RT/USER/nr-softmodem.h" #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" - +#include "PHY/NR_TRANSPORT/nr_dci.h" #ifdef EMOS #include "SCHED/phy_procedures_emos.h" #endif @@ -87,30 +87,15 @@ char nr_mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"}; extern double cpuf; + int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, uint32_t frame, - uint8_t nr_tti_rx, - uint8_t eNB_id, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag, - uint8_t is_secondary_ue, - int nb_coreset_active, - uint16_t symbol_mon, - NR_SEARCHSPACE_TYPE_t searchSpaceType); + uint32_t slot); -uint8_t nr_dci_decoding_procedure(int s, - int p, - PHY_VARS_NR_UE *ue, - NR_DCI_ALLOC_t *dci_alloc, - NR_SEARCHSPACE_TYPE_t searchSpacetype, - int16_t eNB_id, - uint8_t nr_tti_rx, - uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], - uint16_t n_RB_ULBWP, - uint16_t n_RB_DLBWP, - crc_scrambled_t *crc_scrambled, - format_found_t *format_found, - uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]); +uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, + int frame, + int nr_tti_rx, + fapi_nr_dci_indication_t *dci_ind); /* int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, @@ -136,7 +121,7 @@ int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, */ #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) -extern uint32_t downlink_frequency[MAX_NUM_CCs][4]; +extern uint64_t downlink_frequency[MAX_NUM_CCs][4]; #endif @@ -1404,137 +1389,6 @@ void ulsch_common_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_ } -void ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode) { - - int frame_tx = proc->frame_tx; - int nr_tti_tx = proc->nr_tti_tx; - int prach_power; - PRACH_RESOURCES_t prach_resources_local; - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); - - ue->generate_prach=0; - - if (ue->mac_enabled==0){ - ue->prach_resources[eNB_id] = &prach_resources_local; - prach_resources_local.ra_RNTI = 0xbeef; - prach_resources_local.ra_PreambleIndex = 0; - } - - if (ue->mac_enabled==1){ - // ask L2 for RACH transport - if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) { - LOG_D(PHY,"Getting PRACH resources\n"); - //ue->prach_resources[eNB_id] = mac_xface->ue_get_rach(ue->Mod_id, - ue->CC_id, - frame_tx, - eNB_id, - nr_tti_tx); - LOG_D(PHY,"Got prach_resources for eNB %d address %p, RRCCommon %p\n",eNB_id,ue->prach_resources[eNB_id],UE_mac_inst[ue->Mod_id].radioResourceConfigCommon); - LOG_D(PHY,"Prach resources %p\n",ue->prach_resources[eNB_id]); - } -} - -if (ue->prach_resources[eNB_id]!=NULL) { - - ue->generate_prach=1; - ue->prach_cnt=0; -#ifdef SMBV - ue->prach_resources[eNB_id]->ra_PreambleIndex = 19; -#endif -#ifdef OAI_EMU - ue->prach_PreambleIndex=ue->prach_resources[eNB_id]->ra_PreambleIndex; -#endif - - if (abstraction_flag == 0) { - - LOG_I(PHY,"mode %d\n",mode); - - if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) { - ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id); - } - else { - ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; - ue->prach_resources[eNB_id]->ra_PreambleIndex = 19; - } - - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n", - ue->Mod_id, - frame_tx, - nr_tti_tx, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id), - ue->tx_power_dBm[nr_tti_tx], - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, - ue->prach_resources[eNB_id]->ra_TDD_map_index, - ue->prach_resources[eNB_id]->ra_RNTI); - - ue->tx_total_RE[nr_tti_tx] = 96; - -#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) - ue->prach_vars[eNB_id]->amp = nr_get_tx_amp(ue->tx_power_dBm[nr_tti_tx], - ue->tx_power_max_dBm, - ue->frame_parms.N_RB_UL, - 6); -#else - ue->prach_vars[eNB_id]->amp = AMP; -#endif - if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", - ue->Mod_id, - proc->frame_rx, - proc->nr_tti_tx, - ue->tx_power_dBm[nr_tti_tx], - ue->prach_vars[eNB_id]->amp); - - - // start_meas(&ue->tx_prach); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); - prach_power = generate_prach(ue,eNB_id,nr_tti_tx,frame_tx); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); - // stop_meas(&ue->tx_prach); - LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", - ue->Mod_id, - nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id), - ue->tx_power_dBm[nr_tti_tx], - dB_fixed(prach_power), - ue->prach_vars[eNB_id]->amp); - } else { - UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1; - UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex; - } - - if (ue->mac_enabled==1){ - //mac_xface->Msg1_transmitted(ue->Mod_id, - ue->CC_id, - frame_tx, - eNB_id); - } - -LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n", - ue->Mod_id,frame_tx,nr_tti_tx,eNB_id, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id), - nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id)); - -} - - -// if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue -if (mode == calib_prach_tx) - ue->prach_resources[eNB_id]=NULL; - -LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_prach %d, prach_cnt %d\n", - ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_prach,ue->prach_cnt); - -ue->prach_cnt++; - -if (ue->prach_cnt==3) - ue->generate_prach=0; - -VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); -} - #endif @@ -1547,6 +1401,8 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com // scale the 16 factor in N_TA calculation in 38.213 section 4.2 according to the used FFT size switch (bwp_ul_NB_RB) { + case 32: bw_scaling = 4; break; + case 66: bw_scaling = 8; break; case 106: bw_scaling = 16; break; case 217: bw_scaling = 32; break; case 245: bw_scaling = 32; break; @@ -1932,7 +1788,7 @@ if (abstraction_flag == 0) { #endif #if T_TRACER T(T_UE_PHY_PUSCH_TX_POWER, T_INT(eNB_id),T_INT(Mod_id), T_INT(frame_tx%1024), T_INT(nr_tti_tx),T_INT(ue->tx_power_dBm[nr_tti_tx]), - T_INT(tx_amp),T_INT(ue->ulsch[eNB_id]->f_pusch),T_INT(nr_get_PL(Mod_id,0,eNB_id)),T_INT(nb_rb)); + T_INT(tx_amp),T_INT(ue->ulsch[eNB_id]->f_pusch),T_INT(get_nr_PL(Mod_id,0,eNB_id)),T_INT(nb_rb)); #endif #ifdef UE_DEBUG_TRACE @@ -2307,7 +2163,7 @@ void ue_pucch_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_ #endif #if T_TRACER T(T_UE_PHY_PUCCH_TX_POWER, T_INT(eNB_id),T_INT(Mod_id), T_INT(frame_tx%1024), T_INT(nr_tti_tx),T_INT(ue->tx_power_dBm[nr_tti_tx]), - T_INT(tx_amp),T_INT(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][eNB_id][0]->g_pucch),T_INT(nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id))); + T_INT(tx_amp),T_INT(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][eNB_id][0]->g_pucch),T_INT(get_nr_PL(ue->Mod_id,ue->CC_id,eNB_id))); #endif #ifdef UE_DEBUG_TRACE @@ -2415,7 +2271,7 @@ void ue_pucch_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_ #endif #if T_TRACER T(T_UE_PHY_PUCCH_TX_POWER, T_INT(eNB_id),T_INT(Mod_id), T_INT(frame_tx%1024), T_INT(nr_tti_tx),T_INT(ue->tx_power_dBm[nr_tti_tx]), - T_INT(tx_amp),T_INT(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][eNB_id][0]->g_pucch),T_INT(nr_get_PL(ue->Mod_id,ue->CC_id,eNB_id))); + T_INT(tx_amp),T_INT(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][eNB_id][0]->g_pucch),T_INT(get_nr_PL(ue->Mod_id,ue->CC_id,eNB_id))); #endif #ifdef UE_DEBUG_TRACE LOG_I(PHY,"[UE %d][RNTI %x] AbsSubFrame %d.%d Generating PUCCH 2 (RI or CQI), Po_PUCCH %d, isShortenPucch %d, amp %d\n", @@ -2508,7 +2364,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, gNB_id, &ue->frame_parms); - + //LOG_M("txdata.m","txs",ue->common_vars.txdata[0],1228800,1,1); /* @@ -2537,6 +2393,136 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode) { + + int frame_tx = proc->frame_tx; + int nr_tti_tx = proc->nr_tti_tx; + int prach_power; + uint16_t preamble_tx=50; + PRACH_RESOURCES_t prach_resources; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); + + ue->generate_nr_prach=0; + if (ue->mac_enabled==0){ + ue->prach_resources[eNB_id] = &prach_resources; + ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; + ue->prach_resources[eNB_id]->ra_TDD_map_index = 0; + } + + if (ue->mac_enabled==1){ + + // ask L2 for RACH transport + if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) { + LOG_D(PHY,"Getting PRACH resources\n"); + //ue->prach_resources[eNB_id] = mac_xface->ue_get_rach(ue->Mod_id,ue->CC_id,frame_tx,eNB_id,nr_tti_tx); + // LOG_D(PHY,"Got prach_resources for eNB %d address %p, RRCCommon %p\n",eNB_id,ue->prach_resources[eNB_id],UE_mac_inst[ue->Mod_id].radioResourceConfigCommon); + // LOG_D(PHY,"Prach resources %p\n",ue->prach_resources[eNB_id]); + } +} + +if (ue->prach_resources[eNB_id]!=NULL) { + + ue->generate_nr_prach=1; + ue->prach_cnt=0; +#ifdef SMBV +ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; +#endif + +#ifdef OAI_EMU + ue->prach_PreambleIndex=ue->prach_resources[eNB_id]->ra_PreambleIndex; +#endif + + if (abstraction_flag == 0) { + + LOG_I(PHY,"mode %d\n",mode); + + if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) { + + ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id); + } + else { + ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; + ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; + } + + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n", + ue->Mod_id, + frame_tx, + nr_tti_tx, + ue->prach_resources[eNB_id]->ra_PreambleIndex, + get_nr_PL(ue,eNB_id), + ue->tx_power_dBm[nr_tti_tx], + ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, + ue->prach_resources[eNB_id]->ra_TDD_map_index, + ue->prach_resources[eNB_id]->ra_RNTI); + + ue->tx_total_RE[nr_tti_tx] = 96; + +#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) + ue->prach_vars[eNB_id]->amp = get_tx_amp(ue->tx_power_dBm[nr_tti_tx], + ue->tx_power_max_dBm, + ue->frame_parms.N_RB_UL, + 6); +#else + ue->prach_vars[eNB_id]->amp = AMP; +#endif + if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", + ue->Mod_id, + proc->frame_rx, + proc->nr_tti_tx, + ue->tx_power_dBm[nr_tti_tx], + ue->prach_vars[eNB_id]->amp); + + + // start_meas(&ue->tx_prach); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); + +// prach_power = generate_nr_prach(ue,eNB_id,nr_tti_tx,frame_tx); +prach_power = generate_nr_prach(ue,0,9,0); //subframe number hardcoded according to the simulator + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); + // stop_meas(&ue->tx_prach); + LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", + ue->Mod_id, + get_nr_PL(ue,eNB_id), + ue->tx_power_dBm[nr_tti_tx], + dB_fixed(prach_power), + ue->prach_vars[eNB_id]->amp); + }/* else { + UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1; + UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex; + }*/ // commented for compiling as abstraction flag is 0 + + if (ue->mac_enabled==1){ + //mac_xface->Msg1_transmitted(ue->Mod_id,ue->CC_id,frame_tx,eNB_id); + } + +LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n", + ue->Mod_id,frame_tx,nr_tti_tx,eNB_id, + ue->prach_resources[eNB_id]->ra_PreambleIndex, + ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id), + get_nr_PL(ue,eNB_id)); + +} + + +// if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue +if (mode == calib_prach_tx) + ue->prach_resources[eNB_id]=NULL; + +LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", + ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_nr_prach,ue->prach_cnt); + +ue->prach_cnt++; + +if (ue->prach_cnt==3) + ue->generate_nr_prach=0; + +VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); +} + /* void phy_procedures_UE_S_TX(PHY_VARS_NR_UE *ue,uint8_t eNB_id,uint8_t abstraction_flag,relaying_type_t r_type) { @@ -2579,14 +2565,14 @@ void nr_ue_measurement_procedures(uint16_t l, // symbol index of each slot [0 if (l==2) { // UE measurements on symbol 0 LOG_D(PHY,"Calling measurements nr_tti_rx %d, rxdata %p\n",nr_tti_rx,ue->common_vars.rxdata); - +/* nr_ue_measurements(ue, 0, 0, 0, 0, nr_tti_rx); - +*/ //(nr_tti_rx*frame_parms->samples_per_tti+ue->rx_offset)%(frame_parms->samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME) #if T_TRACER @@ -2704,9 +2690,9 @@ void restart_phy(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc, uint8_t eNB_id,uint #endif //(0) void nr_ue_pbch_procedures(uint8_t eNB_id, - PHY_VARS_NR_UE *ue, - UE_nr_rxtx_proc_t *proc, - uint8_t abstraction_flag) + PHY_VARS_NR_UE *ue, + UE_nr_rxtx_proc_t *proc, + uint8_t abstraction_flag) { // int i; //int pbch_tx_ant=0; @@ -2728,7 +2714,7 @@ void nr_ue_pbch_procedures(uint8_t eNB_id, ue->pbch_vars[eNB_id], &ue->frame_parms, eNB_id, - ue->nrUE_config.pbch_config.ssb_index, + (ue->frame_parms.ssb_index)&7, SISO, ue->high_speed_flag); @@ -2809,10 +2795,15 @@ unsigned int nr_get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb #ifdef NR_PDCCH_SCHED -int nr_ue_pdcch_procedures(uint8_t eNB_id, - PHY_VARS_NR_UE *ue, - UE_nr_rxtx_proc_t *proc) +int nr_ue_pdcch_procedures(uint8_t gNB_id, + PHY_VARS_NR_UE *ue, + UE_nr_rxtx_proc_t *proc) { + int frame_rx = proc->frame_rx; + int nr_tti_rx = proc->nr_tti_rx; + unsigned int dci_cnt=0; + + /* // unsigned int dci_cnt=0, i; //removed for nr_ue_pdcch_procedures and added in the loop for nb_coreset_active #ifdef NR_PDCCH_SCHED_DEBUG printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_ue_pdcch_procedures() \n"); @@ -2821,10 +2812,10 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, int frame_rx = proc->frame_rx; int nr_tti_rx = proc->nr_tti_rx; NR_DCI_ALLOC_t dci_alloc_rx[8]; - /* - uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); - uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); - */ + + //uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); + //uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); + // table dci_fields_sizes_cnt contains dci_fields_sizes for each time a dci is decoded in the slot // each element represents the size in bits for each dci field, for each decoded dci -> [dci_cnt-1] @@ -2834,14 +2825,14 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, int nb_searchspace_active=0; NR_UE_PDCCH **pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]]; - NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]; + NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]; // s in TS 38.212 Subclause 10.1, for each active BWP the UE can deal with 10 different search spaces // Higher layers have updated the number of searchSpaces with are active in the current slot and this value is stored in variable nb_searchspace_total int nb_searchspace_total = pdcch_vars2->nb_search_space; - pdcch_vars[eNB_id]->crnti = 0x1234; //to be check how to set when using loop memory + pdcch_vars[gNB_id]->crnti = 0x1234; //to be check how to set when using loop memory - uint16_t c_rnti=pdcch_vars[eNB_id]->crnti; + uint16_t c_rnti=pdcch_vars[gNB_id]->crnti; uint16_t cs_rnti=0,new_rnti=0,tc_rnti=0; uint16_t p_rnti=P_RNTI; uint16_t si_rnti=SI_RNTI; @@ -2877,22 +2868,22 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, for (nb_searchspace_active=0; nb_searchspace_activesearchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset; - if (sl_period_offset_mon == nr_sl1) { - do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every slot - } else if (nr_tti_rx%(uint16_t)sl_period_offset_mon == pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset_offset) { - do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every monitoringSlotPeriodicityAndOffset slot with offset - }*/ - /* - * FIXME - * For PDCCH monitoring when overlap with SS/PBCH according to 38.213 v15.1.0 Section 10 - * To be implemented LATER !!! - */ + //NR_UE_SLOT_PERIOD_OFFSET_t sl_period_offset_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset; + //if (sl_period_offset_mon == nr_sl1) { + //do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every slot + //} else if (nr_tti_rx%(uint16_t)sl_period_offset_mon == pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset_offset) { + //do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every monitoringSlotPeriodicityAndOffset slot with offset + //} + + // FIXME + // For PDCCH monitoring when overlap with SS/PBCH according to 38.213 v15.1.0 Section 10 + // To be implemented LATER !!! + //int _offset,_index,_M; //int searchSpace_id = pdcch_vars2->searchSpace[nb_searchspace_active].searchSpaceId; @@ -2912,11 +2903,11 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, // at the moment we will not take into consideration this variable and we will consider that the OFDM symbol offset is always the first OFDM in a symbol uint16_t symbol_within_slot_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSymbolWithinSlot; // get the remaining parameters describing the current SEARCHSPACE: // FIXME! To be defined where we get this information from - /*NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L1 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel1; - NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L2 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel2; - NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L4 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel4; - NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L8 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel8; - NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L16 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel16;*/ + //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L1 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel1; + //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L2 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel2; + //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L4 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel4; + //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L8 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel8; + //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L16 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel16; // FIXME! A table of five enum elements // searchSpaceType indicates whether this is a common search space or a UE-specific search space //int searchSpaceType = pdcch_vars2->searchSpace[nb_searchspace_active].searchSpaceType.type; @@ -2926,27 +2917,27 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, searchSpaceType); #endif - /*while ((searchSpace_coreset_id != pdcch_vars2->coreset[nb_coreset_active].controlResourceSetId) && (nb_coreset_activecoreset[nb_coreset_active].controlResourceSetId) && (nb_coreset_active= nb_coreset_total) return 0; // the coreset_id could not be found. There is a problem - }*/ + } - /* - * we do not need these parameters yet - * + + //we do not need these parameters yet + // get the parameters describing the current CORESET - int coreset_duration = pdcch_vars2->coreset[nb_coreset_active].duration; - uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources; - int coreset_shift_index = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex; - NR_UE_CORESET_REG_bundlesize_t coreset_bundlesize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize; - NR_UE_CORESET_interleaversize_t coreset_interleaversize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize; - NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity; - int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH; - int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI; - uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID; - */ + //int coreset_duration = pdcch_vars2->coreset[nb_coreset_active].duration; + //uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources; + //int coreset_shift_index = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex; + // NR_UE_CORESET_REG_bundlesize_t coreset_bundlesize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize; + // NR_UE_CORESET_interleaversize_t coreset_interleaversize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize; + // NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity; + // int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH; + // int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI; + // uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID; + // A set of PDCCH candidates for a UE to monitor is defined in terms of PDCCH search spaces. // Searchspace types: @@ -2972,14 +2963,14 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_IN); #ifdef NR_PDCCH_SCHED_DEBUG - printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_rx_pdcch with eNB_id=%d (nb_coreset_active=%d, (symbol_within_slot_mon&0x3FFF)=%d, searchSpaceType=%d)\n", - eNB_id,nb_coreset_active,(symbol_within_slot_mon&0x3FFF), + printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_rx_pdcch with gNB_id=%d (nb_coreset_active=%d, (symbol_within_slot_mon&0x3FFF)=%d, searchSpaceType=%d)\n", + gNB_id,nb_coreset_active,(symbol_within_slot_mon&0x3FFF), searchSpaceType); #endif nr_rx_pdcch(ue, proc->frame_rx, nr_tti_rx, - eNB_id, + gNB_id, //(ue->frame_parms.mode1_flag == 1) ? SISO : ALAMOUTI, SISO, ue->high_speed_flag, @@ -2993,108 +2984,51 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, searchSpaceType); #endif - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN); + */ + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_IN); + nr_rx_pdcch(ue, + proc->frame_rx, + nr_tti_rx); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT); + - crc_scrambled_t crc_scrambled; - format_found_t format_found=255; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN); #ifdef NR_PDCCH_SCHED_DEBUG - printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure with eNB_id=%d (n_RB_ULBWP=%d, n_RB_DLBWP=%d, searchSpaceType=%d, nb_searchspace_active=%d, nb_coreset_active=%d)\n", - eNB_id, - pdcch_vars2->n_RB_BWP[nb_searchspace_active], - pdcch_vars2->n_RB_BWP[nb_searchspace_active], - searchSpaceType, - nb_searchspace_active, - nb_coreset_active); - + printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure with (nb_searchspace_active=%d)\n", + pdcch_vars->nb_search_space); #endif - - dci_cnt += nr_dci_decoding_procedure(nb_searchspace_active, - nb_coreset_active, - ue, - &dci_alloc_rx[dci_cnt], - searchSpaceType, // if we're in PUSCH don't listen to common search space, - // later when we need paging or RA during connection, update this ... - eNB_id, - nr_tti_rx, - dci_fields_sizes_cnt, - pdcch_vars2->n_RB_BWP[nb_searchspace_active], - pdcch_vars2->n_RB_BWP[nb_searchspace_active], - &crc_scrambled, - &format_found, - crc_scrambled_values); + fapi_nr_dci_indication_t dci_ind; + nr_downlink_indication_t dl_indication; + memset((void*)&dci_ind,0,sizeof(dci_ind)); + memset((void*)&dl_indication,0,sizeof(dl_indication)); + dci_cnt = nr_dci_decoding_procedure(ue, + proc->frame_rx, + nr_tti_rx, + &dci_ind); + #ifdef NR_PDCCH_SCHED_DEBUG - printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt); + LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt); #endif + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT); + //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT); - //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx); + for (int i=0; i rnti %x : format %d\n", + ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]], + i, + dci_ind.dci_list[i].rnti, + dci_ind.dci_list[i].dci_format); + } + ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]->dci_received += dci_cnt; + dci_ind.number_of_dcis = dci_cnt; /* - uint8_t *nCCE_current = &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->nCCE[nr_tti_rx]; - uint8_t *nCCE_dest = &ue->pdcch_vars[next1_thread_id][eNB_id]->nCCE[nr_tti_rx]; - uint8_t *nCCE_dest1 = &ue->pdcch_vars[next2_thread_id][eNB_id]->nCCE[nr_tti_rx]; - memcpy(nCCE_dest, nCCE_current, sizeof(uint8_t)); - memcpy(nCCE_dest1, nCCE_current, sizeof(uint8_t)); - - LOG_D(PHY,"current_thread %d next1_thread %d next2_thread %d \n", ue->current_thread_id[nr_tti_rx], next1_thread_id, next2_thread_id); - */ - - LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI found %i --> rnti %x / crnti %x : format %d\n", - ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[eNB_id]], - dci_cnt, - dci_alloc_rx[0].rnti, - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - dci_alloc_rx[0].format ); - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dci_received += dci_cnt; - -#ifdef EMOS - //emos_dump_UE.dci_cnt[nr_tti_rx] = dci_cnt; -#endif - - dci_ind.number_of_dcis = dci_cnt; - for (int i=0; idlsch_received[eNB_id]++; - - if (dci_alloc_rx[i].rnti == crc_scrambled_values[_SI_RNTI_]) - ue->dlsch_SI_received[eNB_id]++; - if (dci_alloc_rx[i].rnti == crc_scrambled_values[_P_RNTI_]) - ue->dlsch_p_received[eNB_id]++; - if (dci_alloc_rx[i].rnti == crc_scrambled_values[_RA_RNTI_]) - ue->dlsch_ra_received[eNB_id]++; - } - - if ((dci_alloc_rx[i].format == format2_0)){ - } - if ((dci_alloc_rx[i].format == format2_1)){ - } - if ((dci_alloc_rx[i].format == format2_2)){ - } - if ((dci_alloc_rx[i].format == format2_3)){ - } - if ((dci_alloc_rx[i].format == format0_1)){ // This format not implemented at a first time. FIXME - } - if ((dci_alloc_rx[i].format == format1_1)){ // This format not implemented at a first time. FIXME - } - - uint8_t status=0; - - LOG_D(PHY,"<-NR_PDCCH_PHY_PROCEDURES_UE (nr_ue_pdcch_procedures)-> dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",dci_alloc_rx[i].format,dci_alloc_rx[i].rnti,dci_alloc_rx[i].dci_length,dci_alloc_rx[i].dci_pdu[0],dci_alloc_rx[i].dci_pdu[1]); - memset(&dci_ind.dci_list[i].dci,0,sizeof(fapi_nr_dci_pdu_rel15_t)); dci_ind.dci_list[i].rnti = dci_alloc_rx[i].rnti; @@ -3103,7 +3037,7 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, dci_ind.dci_list[i].N_CCE = (int)dci_alloc_rx[i].L; status = nr_extract_dci_info(ue, - eNB_id, + gNB_id, ue->frame_parms.frame_type, dci_alloc_rx[i].dci_length, dci_alloc_rx[i].rnti, @@ -3123,36 +3057,15 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, LOG_D(PHY,"<-NR_PDCCH_PHY_PROCEDURES_UE (nr_ue_pdcch_procedures)-> Ending function nr_extract_dci_info()\n"); - /* - nr_generate_ue_ul_dlsch_params_from_dci(ue, - eNB_id, - frame_rx, - nr_tti_rx, - dci_alloc_rx[i].dci_pdu, - dci_alloc_rx[i].rnti, - dci_alloc_rx[i].dci_length, - dci_alloc_rx[i].format, - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id], - ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id], - ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id], - ue->ulsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0], - &ue->frame_parms, - ue->pdsch_config_dedicated, - ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id], - dci_fields_sizes_cnt[i], - pdcch_vars2->n_RB_BWP[nb_searchspace_active], - pdcch_vars2->n_RB_BWP[nb_searchspace_active], - crc_scrambled_values, - &nr_dci_info_extracted); - */ } // end for loop dci_cnt + */ // fill dl_indication message dl_indication.module_id = ue->Mod_id; dl_indication.cc_id = ue->CC_id; - dl_indication.gNB_index = eNB_id; + dl_indication.gNB_index = gNB_id; dl_indication.frame = frame_rx; dl_indication.slot = nr_tti_rx; dl_indication.rx_ind = NULL; //no data, only dci for now @@ -3164,10 +3077,8 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id, #if UE_TIMING_TRACE stop_meas(&ue->dlsch_rx_pdcch_stats); #endif + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES, VCD_FUNCTION_OUT); - - - } // end for loop nb_searchspace_active return(dci_cnt); } #endif // NR_PDCCH_SCHED @@ -3365,25 +3276,31 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB if (!dlsch1) { int harq_pid = dlsch0->current_harq_pid; + uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart; + // uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize; uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb; uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb; uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol; uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols; - LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1); + LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos); - for (m = s0; m < (s1 + s0); m++) { - - if (m==s0) + // do channel estimation for first DMRS only + for (m = s0; m < 3; m++) { + if (((1<harq_processes[harq_pid]->dlDmrsSymbPos) > 0) { nr_pdsch_channel_estimation(ue, 0 /*eNB_id*/, nr_tti_rx, 0 /*p*/, m, - ue->frame_parms.first_carrier_offset+pdsch_start_rb*12, + ue->frame_parms.first_carrier_offset+(BWPStart + pdsch_start_rb)*12, pdsch_nb_rb); - - + LOG_D(PHY,"Channel Estimation in symbol %d\n",m); + break; + } + } + for (m = s0; m < (s1 + s0); m++) { + dual_stream_UE = 0; eNB_id_i = eNB_id+1; i_mod = 0; @@ -3797,7 +3714,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, LOG_D(PHY," ------ end ldpc decoder for AbsSubframe %d.%d ------ \n", frame_rx, nr_tti_rx); - LOG_I(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS); + LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS); if(retmax_ldpc_iterations+1){ // fill dl_indication message @@ -3861,6 +3778,8 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, // scale the 16 factor in N_TA calculation in 38.213 section 4.2 according to the used FFT size switch (ue->frame_parms.N_RB_DL) { + case 32: bw_scaling = 4; break; + case 66: bw_scaling = 8; break; case 106: bw_scaling = 16; break; case 217: bw_scaling = 32; break; case 245: bw_scaling = 32; break; @@ -4243,20 +4162,20 @@ void *UE_thread_slot1_dl_processing(void *arg) { #endif -int is_pbch_in_slot(fapi_nr_pbch_config_t *pbch_config, int frame, int slot, int periodicity, uint16_t slots_per_frame) { +int is_pbch_in_slot(fapi_nr_config_request_t *config, int frame, int slot, NR_DL_FRAME_PARMS *fp) { - int ssb_slot_decoded = (pbch_config->ssb_index)/2; + int ssb_slot_decoded = (fp->ssb_index>>1) + ((fp->ssb_index>>4)<<1); //slot in which the decoded SSB can be found - if (periodicity == 5) { + if (config->ssb_table.ssb_period == 0) { // check for pbch in corresponding slot each half frame - if (pbch_config->half_frame_bit) - return(slot == ssb_slot_decoded || slot == ssb_slot_decoded - slots_per_frame/2); + if (fp->half_frame_bit) + return(slot == ssb_slot_decoded || slot == ssb_slot_decoded - fp->slots_per_frame/2); else - return(slot == ssb_slot_decoded || slot == ssb_slot_decoded + slots_per_frame/2); + return(slot == ssb_slot_decoded || slot == ssb_slot_decoded + fp->slots_per_frame/2); } else { // if the current frame is supposed to contain ssb - if (!((frame-(pbch_config->system_frame_number))%(periodicity/10))) + if (!(frame%(1<<(config->ssb_table.ssb_period-1)))) return(slot == ssb_slot_decoded); else return 0; @@ -4275,14 +4194,14 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, int slot_pbch; NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][0]; NR_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id]; + fapi_nr_config_request_t *cfg = &ue->nrUE_config; uint8_t harq_pid = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->current_harq_pid; NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; uint16_t start_symb_sch = dlsch0_harq->start_symbol; - uint8_t nb_symb_pdcch = pdcch_vars->coreset[0].duration; - uint8_t ssb_periodicity = 10;// ue->ssb_periodicity; // initialized to 5ms in nr_init_ue for scenarios where UE is not configured (otherwise acquired by cell configuration from gNB or LTE) + uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0; uint8_t dci_cnt = 0; - fapi_nr_pbch_config_t *pbch_config = &ue->nrUE_config.pbch_config; + NR_DL_FRAME_PARMS *fp = &ue->frame_parms; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_RX, VCD_FUNCTION_IN); @@ -4293,22 +4212,13 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); */ - uint8_t coreset_start=0, coreset_start_set=0; - uint16_t coreset_count = 0; - uint64_t coreset_freq_dom = pdcch_vars->coreset[0].frequencyDomainResources; - for (int i = 0; i < 45; i++) { - if (((coreset_freq_dom & 0x1FFFFFFFFFFF) >> (44-i)) & 0x1) { - if (!coreset_start_set) { - coreset_start = i; - coreset_start_set = 1; - } - coreset_count++; - } - } - uint16_t coreset_nb_rb = 6 * coreset_count; - uint16_t coreset_start_rb = 6 * coreset_start; + + int coreset_nb_rb=0; + int coreset_start_rb=0; + if (pdcch_vars->nb_search_space > 0) + get_coreset_rballoc(pdcch_vars->pdcch_config[0].coreset.frequency_domain_resource,&coreset_nb_rb,&coreset_start_rb); - slot_pbch = is_pbch_in_slot(pbch_config, frame_rx, nr_tti_rx, ssb_periodicity, ue->frame_parms.slots_per_frame); + slot_pbch = is_pbch_in_slot(cfg, frame_rx, nr_tti_rx, fp); // looking for pbch only in slot where it is supposed to be if ((ue->decode_MIB == 1) && slot_pbch) @@ -4318,7 +4228,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, for (int i=1; i<4; i++) { nr_slot_fep(ue, - (ue->symbol_offset+i)%(ue->frame_parms.symbols_per_slot), + (ue->symbol_offset+i)%(fp->symbols_per_slot), nr_tti_rx, 0, 0); @@ -4326,7 +4236,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, #if UE_TIMING_TRACE start_meas(&ue->dlsch_channel_estimation_stats); #endif - nr_pbch_channel_estimation(ue,0,nr_tti_rx,(ue->symbol_offset+i)%(ue->frame_parms.symbols_per_slot),i-1,(pbch_config->ssb_index)&7,pbch_config->half_frame_bit); + nr_pbch_channel_estimation(ue,0,nr_tti_rx,(ue->symbol_offset+i)%(fp->symbols_per_slot),i-1,(fp->ssb_index)&7,fp->half_frame_bit); #if UE_TIMING_TRACE stop_meas(&ue->dlsch_channel_estimation_stats); #endif @@ -4336,12 +4246,12 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (ue->no_timing_correction==0) { LOG_I(PHY,"start adjust sync slot = %d no timing %d\n", nr_tti_rx, ue->no_timing_correction); - nr_adjust_synch_ue(&ue->frame_parms, - ue, - eNB_id, - nr_tti_rx, - 0, - 16384); + nr_adjust_synch_ue(fp, + ue, + eNB_id, + nr_tti_rx, + 0, + 16384); } } @@ -4361,12 +4271,16 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, 0, 0); - nr_pdcch_channel_estimation(ue, - 0, - nr_tti_rx, - l, - ue->frame_parms.first_carrier_offset+coreset_start_rb*12, - coreset_nb_rb); + // note: this only works if RBs for PDCCH are contigous! + LOG_D(PHY,"pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d\n", + fp->first_carrier_offset,pdcch_vars->pdcch_config[0].BWPStart,coreset_start_rb); + if (coreset_nb_rb > 0) + nr_pdcch_channel_estimation(ue, + 0, + nr_tti_rx, + l, + fp->first_carrier_offset+(pdcch_vars->pdcch_config[0].BWPStart + coreset_start_rb)*12, + coreset_nb_rb); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_OUT); #if UE_TIMING_TRACE @@ -4382,7 +4296,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (dci_cnt > 0) { - LOG_I(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt); + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt); } else { LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx); @@ -4394,7 +4308,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx); //to update from pdsch config start_symb_sch = dlsch0_harq->start_symbol; - nr_gold_pdsch(ue,start_symb_sch,0, 1); + int symb_dmrs=-1; + for (int i=0;i<4;i++) if (((1<dlDmrsSymbPos) > 0) {symb_dmrs=i;break;} + AssertFatal(symb_dmrs>=0,"no dmrs in 0..3\n"); + LOG_D(PHY,"Initializing dmrs for symb %d DMRS mask %x\n",symb_dmrs,dlsch0_harq->dlDmrsSymbPos); + nr_gold_pdsch(ue,symb_dmrs,0, 1); nb_symb_sch = dlsch0_harq->nb_symbols; @@ -4430,11 +4348,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, nr_ue_measurement_procedures(2,ue,proc,eNB_id,nr_tti_rx,mode); /* - write_output("rxF.m","rxF",&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF[0][0],ue->frame_parms.ofdm_symbol_size*14,1,1); - write_output("rxF_ch.m","rxFch",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dl_ch_estimates[0][0],ue->frame_parms.ofdm_symbol_size*14,1,1); + write_output("rxF.m","rxF",&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF[0][0],fp->ofdm_symbol_size*14,1,1); + write_output("rxF_ch.m","rxFch",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dl_ch_estimates[0][0],fp->ofdm_symbol_size*14,1,1); write_output("rxF_ch_ext.m","rxFche",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dl_ch_estimates_ext[0][2*50*12],50*12,1,1); write_output("rxF_ext.m","rxFe",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_ext[0][0],50*12*14,1,1); - write_output("rxF_comp.m","rxFc",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp0[0][0],ue->frame_parms.N_RB_DL*12*14,1,1); + write_output("rxF_comp.m","rxFc",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp0[0][0],fp->N_RB_DL*12*14,1,1); write_output("rxF_llr.m","rxFllr",ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr[0],(nb_symb_sch-1)*50*12+50*6,1,0); */ @@ -4483,7 +4401,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, // do procedures for C-RNTI if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1) { - LOG_I(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx); + LOG_D(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_IN); #if UE_TIMING_TRACE @@ -4525,16 +4443,16 @@ start_meas(&ue->generic_stat); //write_output("decoder_llr.m","decllr",dlsch_llr,G,1,0); //write_output("llr.m","llr", &ue->pdsch_vars[eNB_id]->llr[0][0],(14*nb_rb*12*dlsch1_harq->Qm) - 4*(nb_rb*4*dlsch1_harq->Qm),1,0); - write_output("rxdataF0_current.m" , "rxdataF0", &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF[0][0],14*ue->frame_parms.ofdm_symbol_size,1,1); - //write_output("rxdataF0_previous.m" , "rxdataF0_prev_sss", &ue->common_vars.common_vars_rx_data_per_thread[next_thread_id].rxdataF[0][0],14*ue->frame_parms.ofdm_symbol_size,1,1); + write_output("rxdataF0_current.m" , "rxdataF0", &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF[0][0],14*fp->ofdm_symbol_size,1,1); + //write_output("rxdataF0_previous.m" , "rxdataF0_prev_sss", &ue->common_vars.common_vars_rx_data_per_thread[next_thread_id].rxdataF[0][0],14*fp->ofdm_symbol_size,1,1); - //write_output("rxdataF0_previous.m" , "rxdataF0_prev", &ue->common_vars.common_vars_rx_data_per_thread[next_thread_id].rxdataF[0][0],14*ue->frame_parms.ofdm_symbol_size,1,1); + //write_output("rxdataF0_previous.m" , "rxdataF0_prev", &ue->common_vars.common_vars_rx_data_per_thread[next_thread_id].rxdataF[0][0],14*fp->ofdm_symbol_size,1,1); - write_output("dl_ch_estimates.m", "dl_ch_estimates_sfn5", &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].dl_ch_estimates[0][0][0],14*ue->frame_parms.ofdm_symbol_size,1,1); - write_output("dl_ch_estimates_ext.m", "dl_ch_estimatesExt_sfn5", &ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_estimates_ext[0][0],14*ue->frame_parms.N_RB_DL*12,1,1); - write_output("rxdataF_comp00.m","rxdataF_comp00", &ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->rxdataF_comp0[0][0],14*ue->frame_parms.N_RB_DL*12,1,1); - //write_output("magDLFirst.m", "magDLFirst", &phy_vars_ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_mag0[0][0],14*frame_parms->N_RB_DL*12,1,1); - //write_output("magDLSecond.m", "magDLSecond", &phy_vars_ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_magb0[0][0],14*frame_parms->N_RB_DL*12,1,1); + write_output("dl_ch_estimates.m", "dl_ch_estimates_sfn5", &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].dl_ch_estimates[0][0][0],14*fp->ofdm_symbol_size,1,1); + write_output("dl_ch_estimates_ext.m", "dl_ch_estimatesExt_sfn5", &ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_estimates_ext[0][0],14*fp->N_RB_DL*12,1,1); + write_output("rxdataF_comp00.m","rxdataF_comp00", &ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->rxdataF_comp0[0][0],14*fp->N_RB_DL*12,1,1); + //write_output("magDLFirst.m", "magDLFirst", &phy_vars_ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_mag0[0][0],14*fp->N_RB_DL*12,1,1); + //write_output("magDLSecond.m", "magDLSecond", &phy_vars_ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_magb0[0][0],14*fp->N_RB_DL*12,1,1); AssertFatal (0,""); } @@ -4716,3 +4634,4 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, else return(0); } + diff --git a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c index d388d6877b..9632291e67 100644 --- a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c @@ -70,17 +70,17 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, uint8_t gNB_id, - UE_nr_rxtx_proc_t *proc, - pucch_format_nr_t pucch_format, - int nb_of_prbs, - int N_sc_ctrl_RB, - int N_symb_PUCCH, - int O_UCI, - int O_SR, - int O_CSI, - int O_ACK, + UE_nr_rxtx_proc_t *proc, + pucch_format_nr_t pucch_format, + int nb_of_prbs, + int N_sc_ctrl_RB, + int N_symb_PUCCH, + int O_UCI, + int O_SR, + int O_CSI, + int O_ACK, int O_CRC, - int n_HARQ_ACK) { + int n_HARQ_ACK) { int16_t P_O_NOMINAL_PUCCH = ue->pucch_config_common_nr[gNB_id].p0_nominal; PUCCH_PowerControl_t *power_config = &ue->pucch_config_dedicated_nr[gNB_id].pucch_PowerControl; @@ -104,7 +104,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, int P_O_PUCCH = P_O_NOMINAL_PUCCH + P_O_UE_PUCCH; - int16_t PL = nr_get_PL(ue->Mod_id, ue->CC_id, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */ + int16_t PL = get_nr_PL(ue, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */ int16_t delta_F_PUCCH = power_config->deltaF_PUCCH_f[pucch_format]; @@ -215,3 +215,4 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, return (pucch_power); } + diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 512db60510..326c617dfb 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -1,5 +1,4 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. * The OpenAirInterface Software Alliance licenses this file to You under @@ -213,11 +212,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /* sr_payload = 1 means that this is a positive SR, sr_payload = 0 means that it is a negative SR */ sr_payload = nr_ue_get_SR(Mod_id, - CC_id, - frame_tx, - gNB_id, - ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, - nr_tti_tx); // nr_tti_rx used for meas gap + CC_id, + frame_tx, + gNB_id, + 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + nr_tti_tx); // nr_tti_rx used for meas gap } else { sr_payload = 1; @@ -592,7 +591,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ case pucch_format2_nr: { nr_generate_pucch2(ue, - ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, ue->common_vars.txdataF, &ue->frame_parms, &ue->pucch_config_dedicated[gNB_id], @@ -610,7 +609,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ case pucch_format4_nr: { nr_generate_pucch3_4(ue, - ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, ue->common_vars.txdataF, &ue->frame_parms, format, @@ -1216,3 +1215,4 @@ void set_csi_nr(int csi_status, uint32_t csi_payload) } } + diff --git a/openair1/SCHED_UE/phy_procedures_lte_ue.c b/openair1/SCHED_UE/phy_procedures_lte_ue.c index 6d92beaddf..e0ea4ef2b2 100644 --- a/openair1/SCHED_UE/phy_procedures_lte_ue.c +++ b/openair1/SCHED_UE/phy_procedures_lte_ue.c @@ -74,7 +74,7 @@ extern double cpuf; void Msg1_transmitted(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint8_t eNB_id); void Msg3_transmitted(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint8_t eNB_id); -extern uint32_t downlink_frequency[MAX_NUM_CCs][4]; +extern uint64_t downlink_frequency[MAX_NUM_CCs][4]; void get_dumpparam(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, diff --git a/openair1/SIMULATION/ETH_TRANSPORT/netlink_init.c b/openair1/SIMULATION/ETH_TRANSPORT/netlink_init.c index dfb5578ba6..9b4aba46c3 100644 --- a/openair1/SIMULATION/ETH_TRANSPORT/netlink_init.c +++ b/openair1/SIMULATION/ETH_TRANSPORT/netlink_init.c @@ -58,7 +58,7 @@ struct iovec nas_iov_rx = {nl_rx_buf, sizeof(nl_rx_buf)}; int nas_sock_fd[MAX_MOBILES_PER_ENB]; -int nas_sock_mbms_fd[8]; +int nas_sock_mbms_fd; struct msghdr nas_msg_tx; struct msghdr nas_msg_rx; @@ -95,21 +95,20 @@ static int tun_alloc(char *dev) { } -int netlink_init_mbms_tun(char *ifprefix, int num_if) { +int netlink_init_mbms_tun(char *ifprefix) { int ret; char ifname[64]; - int i= num_if-1; - sprintf(ifname, "oaitun_%.3s%d",ifprefix,i+1); - nas_sock_mbms_fd[i] = tun_alloc(ifname); + sprintf(ifname, "oaitun_%.3s1",ifprefix); // added "1": for historical reasons + nas_sock_mbms_fd = tun_alloc(ifname); - if (nas_sock_mbms_fd[i] == -1) { + if (nas_sock_mbms_fd == -1) { printf("[NETLINK] Error opening socket %s (%d:%s)\n",ifname,errno, strerror(errno)); exit(1); } - printf("[NETLINK]Opened socket %s with fd %d\n",ifname,nas_sock_mbms_fd[i]); - ret = fcntl(nas_sock_mbms_fd[i],F_SETFL,O_NONBLOCK); + printf("[NETLINK]Opened socket %s with fd %d\n",ifname,nas_sock_mbms_fd); + ret = fcntl(nas_sock_mbms_fd,F_SETFL,O_NONBLOCK); if (ret == -1) { printf("[NETLINK] Error fcntl (%d:%s)\n",errno, strerror(errno)); @@ -123,7 +122,7 @@ int netlink_init_mbms_tun(char *ifprefix, int num_if) { nas_src_addr.nl_family = AF_NETLINK; nas_src_addr.nl_pid = 1;//getpid(); /* self pid */ nas_src_addr.nl_groups = 0; /* not in mcast groups */ - ret = bind(nas_sock_mbms_fd[i], (struct sockaddr *)&nas_src_addr, sizeof(nas_src_addr)); + ret = bind(nas_sock_mbms_fd, (struct sockaddr *)&nas_src_addr, sizeof(nas_src_addr)); memset(&nas_dest_addr, 0, sizeof(nas_dest_addr)); nas_dest_addr.nl_family = AF_NETLINK; nas_dest_addr.nl_pid = 0; /* For Linux Kernel */ @@ -165,7 +164,8 @@ int netlink_init_tun(char *ifprefix, int num_if) { exit(1); } - printf("[NETLINK]Opened socket %s with fd %d\n",ifname,nas_sock_fd[i]); + printf("[NETLINK]Opened socket %s with fd nas_sock_fd[%d]=%d\n", + ifname, i, nas_sock_fd[i]); ret = fcntl(nas_sock_fd[i],F_SETFL,O_NONBLOCK); if (ret == -1) { diff --git a/openair1/SIMULATION/ETH_TRANSPORT/proto.h b/openair1/SIMULATION/ETH_TRANSPORT/proto.h index 02f7925d93..e6159199d4 100644 --- a/openair1/SIMULATION/ETH_TRANSPORT/proto.h +++ b/openair1/SIMULATION/ETH_TRANSPORT/proto.h @@ -63,6 +63,6 @@ void clear_eNB_transport_info(uint8_t); void clear_UE_transport_info(uint8_t); int netlink_init(void); int netlink_init_tun(char *ifsuffix, int num_if); -int netlink_init_mbms_tun(char *ifsuffix, int num_if); +int netlink_init_mbms_tun(char *ifsuffix); #endif /* EMU_PROTO_H_ */ diff --git a/openair1/SIMULATION/LTE_PHY/prachsim.c b/openair1/SIMULATION/LTE_PHY/prachsim.c index 0771917bfb..c997aa7639 100644 --- a/openair1/SIMULATION/LTE_PHY/prachsim.c +++ b/openair1/SIMULATION/LTE_PHY/prachsim.c @@ -22,8 +22,8 @@ #include #include #include -#include "SIMULATION/TOOLS/defs.h" -#include "SIMULATION/RF/defs.h" +#include "SIMULATION/TOOLS/sim.h" +#include "SIMULATION/RF/rf.h" #include "PHY/types.h" #include "PHY/defs.h" #include "PHY/vars.h" diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index 6000c2e7bb..80b26c0bbd 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -59,6 +59,8 @@ double cpuf; uint8_t nfapi_mode = 0; uint16_t NB_UE_INST = 1; + + // needed for some functions PHY_VARS_NR_UE *PHY_vars_UE_g[1][1] = { { NULL } }; uint16_t n_rnti = 0x1234; @@ -90,14 +92,13 @@ int main(int argc, char **argv) //char input_val_str[50],input_val_str2[50]; //uint16_t NB_RB=25; SCM_t channel_model = AWGN; //Rayleigh1_anticorr; - uint16_t N_RB_DL = 106, mu = 1; + uint16_t N_RB_DL = 106, mu = 1; //unsigned char frame_type = 0; unsigned char pbch_phase = 0; int frame = 0, slot = 0; int frame_length_complex_samples; //int frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; - //nfapi_nr_config_request_t *gNB_config; uint8_t Kmimo = 0; uint32_t Nsoft = 0; double sigma; @@ -341,10 +342,9 @@ int main(int argc, char **argv) exit(-1); } - RC.gNB = (PHY_VARS_gNB ** *) malloc(sizeof(PHY_VARS_gNB **)); - RC.gNB[0] = (PHY_VARS_gNB **) malloc(sizeof(PHY_VARS_gNB *)); - RC.gNB[0][0] = malloc(sizeof(PHY_VARS_gNB)); - gNB = RC.gNB[0][0]; + RC.gNB = (PHY_VARS_gNB **) malloc(sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); + gNB = RC.gNB[0]; //gNB_config = &gNB->gNB_config; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; @@ -423,7 +423,7 @@ int main(int argc, char **argv) UE->dlsch_ra[0] = new_nr_ue_dlsch(1, 1, Nsoft, 5, N_RB_DL, 0); unsigned char harq_pid = 0; //dlsch->harq_ids[subframe]; NR_gNB_DLSCH_t *dlsch = gNB->dlsch[0][0]; - nfapi_nr_dl_config_dlsch_pdu_rel15_t *rel15 = &dlsch->harq_processes[harq_pid]->dlsch_pdu.dlsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15; //time_stats_t *rm_stats, *te_stats, *i_stats; uint8_t is_crnti = 0, llr8_flag = 0; unsigned int TBS = 8424; @@ -445,13 +445,16 @@ int main(int argc, char **argv) TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl); printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order); //dlsch->harq_ids[subframe]= 0; - rel15->n_prb = nb_rb; - rel15->nb_symbols = nb_symb_sch; - rel15->modulation_order = mod_order; - rel15->nb_layers = Nl; - rel15->nb_re_dmrs = nb_re_dmrs; - rel15->transport_block_size = TBS; - rel15->coding_rate = rate; + rel15->rbSize = nb_rb; + rel15->NrOfSymbols = nb_symb_sch; + rel15->qamModOrder[0] = mod_order; + rel15->nrOfLayers = Nl; + rel15->TBSize[0] = TBS>>3; + rel15->targetCodeRate[0] = rate; + rel15->NrOfCodewords = 1; + rel15->dmrsConfigType = NFAPI_NR_DMRS_TYPE1; + rel15->dlDmrsSymbPos = 4; + rel15->mcsIndex[0] = Imcs; double *modulated_input = malloc16(sizeof(double) * 16 * 68 * 384); // [hna] 16 segments, 68*Zc short *channel_output_fixed = malloc16(sizeof(short) * 16 * 68 * 384); short *channel_output_uncoded = malloc16(sizeof(unsigned short) * 16 * 68 * 384); @@ -472,6 +475,8 @@ int main(int argc, char **argv) harq_process->Qm = mod_order; harq_process->rvidx = rvidx; harq_process->R = rate; + harq_process->dmrsConfigType = 1; + harq_process->dlDmrsSymbPos = 4; printf("harq process ue mcs = %d Qm = %d, symb %d\n", harq_process->mcs, harq_process->Qm, nb_symb_sch); unsigned char *test_input; test_input = (unsigned char *) malloc16(sizeof(unsigned char) * TBS / 8); @@ -491,7 +496,7 @@ int main(int argc, char **argv) //printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32)); // generate signal if (input_fd == NULL) { - nr_dlsch_encoding(test_input, frame, slot, dlsch, frame_parms); + nr_dlsch_encoding(test_input, frame, slot, dlsch, frame_parms,NULL,NULL,NULL,NULL,NULL,NULL,NULL); } for (SNR = snr0; SNR < snr1; SNR += snr_step) { @@ -525,9 +530,11 @@ int main(int argc, char **argv) //printf("channel_output_fixed[%d]: %d\n",i,channel_output_fixed[i]); //channel_output_fixed[i] = (char)quantize(1,channel_output_fixed[i],qbits); - - //if (i<16) printf("channel_output_fixed[%d] = %d\n",i,channel_output_fixed[i]); - +/* + if (i<16) printf("input[%d] %f => channel_output_fixed[%d] = %d\n", + i,modulated_input[i], + i,channel_output_fixed[i]); +*/ //Uncoded BER if (channel_output_fixed[i] < 0) channel_output_uncoded[i] = 1; //QPSK demod @@ -621,9 +628,9 @@ int main(int argc, char **argv) for (i = 0; i < 2; i++) { printf("gNB %d\n", i); - free_gNB_dlsch(&(gNB->dlsch[0][i])); + free_gNB_dlsch(&(gNB->dlsch[0][i]),N_RB_DL); printf("UE %d\n", i); - free_nr_ue_dlsch(&(UE->dlsch[0][0][i])); + free_nr_ue_dlsch(&(UE->dlsch[0][0][i]),N_RB_DL); } for (i = 0; i < 2; i++) { diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 60b79c17c2..ebcedbaeb0 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -51,11 +51,23 @@ #include "SCHED_NR_UE/fapi_nr_ue_l1.h" #include "NR_PHY_INTERFACE/NR_IF_Module.h" #include "NR_UE_PHY_INTERFACE/NR_IF_Module.h" + +#include "LAYER2/NR_MAC_UE/mac_proto.h" +//#include "LAYER2/NR_MAC_gNB/mac_proto.h" +//#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" +#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_asn_constant.h" #include "RRC/NR/MESSAGES/asn1_msg.h" #include "openair1/SIMULATION/RF/rf.h" #include "openair1/SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" +//#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" + +#include "NR_RRCReconfiguration.h" +#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0)) +#include "SIMULATION/LTE_PHY/common_sim.h" + + PHY_VARS_gNB *gNB; PHY_VARS_NR_UE *UE; @@ -63,28 +75,64 @@ RAN_CONTEXT_t RC; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; double cpuf; + +int sf_ahead=4 ; +int sl_ahead=0; uint8_t nfapi_mode = 0; uint16_t NB_UE_INST = 1; +uint64_t downlink_frequency[MAX_NUM_CCs][4]; -//Dummy Functions -lte_subframe_t subframe_select(LTE_DL_FRAME_PARMS *frame_parms, unsigned char subframe) {return(SF_DL);} -//int rlc_module_init (int enb) {return(0);} -void pdcp_layer_init (void) {} -boolean_t pdcp_data_ind( const protocol_ctxt_t *const ctxt_pP, const srb_flag_t srb_flagP, const MBMS_flag_t MBMS_flagP, const rb_id_t rb_idP, - const sdu_size_t sdu_buffer_sizeP, mem_block_t *const sdu_buffer_pP) -{return (0);} +// dummy functions +int dummy_nr_ue_ul_indication(nr_uplink_indication_t *ul_info) { return(0); } -int rrc_init_nr_global_param (void) {return(0);} -void config_common(int Mod_idP,int CC_idP,int Nid_cell,int nr_bandP,uint64_t SSB_positions,uint16_t ssb_periodicity,uint64_t dl_CarrierFreqP,uint32_t dl_BandwidthP); -int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, - const int8_t channel, const uint8_t* pduP, const sdu_size_t pdu_len) {return(0);} -uint64_t get_softmodem_optmask(void) {return 0;} +void pdcp_run (const protocol_ctxt_t *const ctxt_pP) { return;} + +int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, + const int CC_id, + const uint8_t gNB_index, + const int8_t channel, + const uint8_t* pduP, + const sdu_size_t pdu_len) +{ + return 0; +} + + +void pdcp_layer_init(void) {} +boolean_t +pdcp_data_ind( + const protocol_ctxt_t *const ctxt_pP, + const srb_flag_t srb_flagP, + const MBMS_flag_t MBMS_flagP, + const rb_id_t rb_idP, + const sdu_size_t sdu_buffer_sizeP, + mem_block_t *const sdu_buffer_pP +) { return(false);} + +int rrc_init_nr_global_param(void){return(0);} + +void config_common(int Mod_idP, + int pdsch_AntennaPorts, + NR_ServingCellConfigCommon_t *scc + ); + +int generate_dlsch_header(unsigned char *mac_header, + unsigned char num_sdus, + unsigned short *sdu_lengths, + unsigned char *sdu_lcids, + unsigned char drx_cmd, + unsigned short timing_advance_cmd, + unsigned char *ue_cont_res_id, + unsigned char short_padding, + unsigned short post_padding){return 0;} void nr_ip_over_LTE_DRB_preconfiguration(void){} - // needed for some functions openair0_config_t openair0_cfg[MAX_CARDS]; + + + int main(int argc, char **argv) { char c; @@ -106,8 +154,6 @@ int main(int argc, char **argv) int trial, n_trials = 1, n_errors = 0, n_false_positive = 0; //int n_errors2, n_alamouti; uint8_t transmission_mode = 1,n_tx=1,n_rx=1; - uint16_t Nid_cell=0; - uint64_t SSB_positions=0x01; channel_desc_t *gNB2UE; //uint32_t nsymb,tx_lev,tx_lev1 = 0,tx_lev2 = 0; @@ -124,37 +170,26 @@ int main(int argc, char **argv) //double pbch_sinr; //int pbch_tx_ant; int N_RB_DL=106,mu=1; - nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config; - dlsch_config.start_prb = 0; - dlsch_config.n_prb = 50; - dlsch_config.start_symbol = 2; - dlsch_config.nb_symbols = 9; - dlsch_config.mcs_idx = 9; - - uint16_t ssb_periodicity = 10; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t dlsch_config; //unsigned char frame_type = 0; - unsigned char pbch_phase = 0; int frame=0,slot=1; int frame_length_complex_samples; int frame_length_complex_samples_no_prefix; - int slot_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; - nfapi_nr_config_request_t *gNB_config; UE_nr_rxtx_proc_t UE_proc; NR_Sched_Rsp_t Sched_INFO; gNB_MAC_INST *gNB_mac; NR_UE_MAC_INST_t *UE_mac; - - int ret; + int cyclic_prefix_type = NFAPI_CP_NORMAL; int run_initial_sync=0; int do_pdcch_flag=1; - uint16_t cset_offset = 0; - int loglvl=OAILOG_WARNING; + int loglvl=OAILOG_INFO; float target_error_rate = 0.01; + int css_flag=0; cpuf = get_cpu_freq_GHz(); @@ -164,17 +199,21 @@ int main(int argc, char **argv) randominit(0); - while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dP:IL:o:a:b:c:j:e:")) != -1) { - switch (c) { - /*case 'f': - write_output_file=1; - output_fd = fopen(optarg,"w"); + int mcsIndex_set=0,rbStart_set=0,rbSize_set=0; + int print_perf = 0; - if (output_fd==NULL) { + FILE *scg_fd=NULL; + + while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:")) != -1) { + switch (c) { + case 'f': + scg_fd = fopen(optarg,"r"); + + if (scg_fd==NULL) { printf("Error opening %s\n",optarg); exit(-1); } - break;*/ + break; /*case 'd': frame_type = 1; @@ -290,14 +329,6 @@ int main(int argc, char **argv) break; - case 'M': - SSB_positions = atoi(optarg); - break; - - case 'N': - Nid_cell = atoi(optarg); - break; - case 'R': N_RB_DL = atoi(optarg); break; @@ -313,44 +344,43 @@ int main(int argc, char **argv) break; case 'P': - pbch_phase = atoi(optarg); - - if (pbch_phase>3) - printf("Illegal PBCH phase (0-3) got %d\n",pbch_phase); - + print_perf=1; + opp_enabled=1; break; case 'I': run_initial_sync=1; target_error_rate=0.1; + slot = 0; break; case 'L': loglvl = atoi(optarg); break; - case 'o': - cset_offset = atoi(optarg); - break; + + case 'E': + css_flag=1; + break; + case 'a': - dlsch_config.start_prb = atoi(optarg); + dlsch_config.rbStart = atoi(optarg); + rbStart_set=1; break; case 'b': - dlsch_config.n_prb = atoi(optarg); - break; - - case 'c': - dlsch_config.start_symbol = atoi(optarg); - break; - - case 'j': - dlsch_config.nb_symbols = atoi(optarg); + dlsch_config.rbSize = atoi(optarg); + rbSize_set=1; break; case 'e': - dlsch_config.mcs_idx = atoi(optarg); + dlsch_config.mcsIndex[0] = atoi(optarg); + mcsIndex_set=1; + break; + + case 'm': + mu = atoi(optarg); break; default: @@ -365,19 +395,17 @@ int main(int argc, char **argv) printf("-S Ending SNR, runs from SNR0 to SNR1\n"); printf("-t Delay spread for multipath channel\n"); printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n"); - printf("-x Transmission mode (1,2,6 for the moment)\n"); - printf("-y Number of TX antennas used in eNB\n"); + printf("-y Number of TX antennas used in gNB\n"); printf("-z Number of RX antennas used in UE\n"); - //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n"); - //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); - printf("-M Multiple SSB positions in burst\n"); - printf("-N Nid_cell\n"); + //printf("-i Relative strength of first intefering gNB (in dB) - cell_id mod 3 = 1\n"); + //printf("-j Relative strength of second intefering gNB (in dB) - cell_id mod 3 = 2\n"); printf("-R N_RB_DL\n"); printf("-O oversampling factor (1,2,4,8,16)\n"); printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); - //printf("-f Output filename (.txt format) for Pe/SNR results\n"); + printf("-f raw file containing RRC configuration (generated by gNB)\n"); printf("-F Input filename (.txt format) for RX conformance testing\n"); + printf("-E used CSS scheduler\n"); printf("-o CORESET offset\n"); printf("-a Start PRB for PDSCH\n"); printf("-b Number of PRB for PDSCH\n"); @@ -388,35 +416,110 @@ int main(int argc, char **argv) break; } } - + logInit(); set_glog(loglvl); T_stdout = 1; + get_softmodem_params()->phy_test = 1; + if (snr1set==0) snr1 = snr0+10; - printf("Initializing gNodeB for mu %d, N_RB_DL %d\n",mu,N_RB_DL); - RC.gNB = (PHY_VARS_gNB***) malloc(sizeof(PHY_VARS_gNB **)); - RC.gNB[0] = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); - RC.gNB[0][0] = malloc(sizeof(PHY_VARS_gNB)); - memset(RC.gNB[0][0],0,sizeof(PHY_VARS_gNB)); + RC.gNB = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = (PHY_VARS_gNB*) malloc(sizeof(PHY_VARS_gNB )); + memset(RC.gNB[0],0,sizeof(PHY_VARS_gNB)); - gNB = RC.gNB[0][0]; - gNB_config = &gNB->gNB_config; + gNB = RC.gNB[0]; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; frame_parms->N_RB_DL = N_RB_DL; frame_parms->N_RB_UL = N_RB_DL; + RC.nb_nr_macrlc_inst = 1; + RC.nb_nr_mac_CC = (int*)malloc(RC.nb_nr_macrlc_inst*sizeof(int)); + for (i = 0; i < RC.nb_nr_macrlc_inst; i++) + RC.nb_nr_mac_CC[i] = 1; + mac_top_init_gNB(); + gNB_mac = RC.nrmac[0]; + gNB_RRC_INST rrc; + memset((void*)&rrc,0,sizeof(rrc)); + + /* + // read in SCGroupConfig + AssertFatal(scg_fd != NULL,"no reconfig.raw file\n"); + char buffer[1024]; + int msg_len=fread(buffer,1,1024,scg_fd); + NR_RRCReconfiguration_t *NR_RRCReconfiguration; + + printf("Decoding NR_RRCReconfiguration (%d bytes)\n",msg_len); + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_RRCReconfiguration, + (void **)&NR_RRCReconfiguration, + (uint8_t *)buffer, + msg_len); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_RRCReConfiguration decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_RRCReconfiguration, NR_RRCReconfiguration, 1 ); + exit(-1); + } + fclose(scg_fd); + + AssertFatal(NR_RRCReconfiguration->criticalExtensions.present == NR_RRCReconfiguration__criticalExtensions_PR_rrcReconfiguration,"wrong NR_RRCReconfiguration->criticalExstions.present type\n"); + + NR_RRCReconfiguration_IEs_t *reconfig_ies = NR_RRCReconfiguration->criticalExtensions.choice.rrcReconfiguration; + NR_CellGroupConfig_t *secondaryCellGroup; + dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_CellGroupConfig, + (void **)&secondaryCellGroup, + (uint8_t *)reconfig_ies->secondaryCellGroup->buf, + reconfig_ies->secondaryCellGroup->size); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_CellGroupConfig decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_CellGroupConfig, secondaryCellGroup, 1 ); + exit(-1); + } + + NR_ServingCellConfigCommon_t *scc = secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon; + */ + + + rrc.carrier.servingcellconfigcommon = calloc(1,sizeof(*rrc.carrier.servingcellconfigcommon)); + + NR_ServingCellConfigCommon_t *scc = rrc.carrier.servingcellconfigcommon; + NR_CellGroupConfig_t *secondaryCellGroup=calloc(1,sizeof(*secondaryCellGroup)); + prepare_scc(rrc.carrier.servingcellconfigcommon); + uint64_t ssb_bitmap; + fill_scc(rrc.carrier.servingcellconfigcommon,&ssb_bitmap,N_RB_DL,N_RB_DL,mu,mu); + + fill_default_secondaryCellGroup(scc, + secondaryCellGroup, + 0, + 1, + n_tx, + 0); + fix_scc(scc,ssb_bitmap); + + xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); + + AssertFatal((gNB->if_inst = NR_IF_Module_init(0))!=NULL,"Cannot register interface"); + gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; + // common configuration + rrc_mac_config_req_gNB(0,0,1,scc,0,0,NULL); + // UE dedicated configuration + rrc_mac_config_req_gNB(0,0,1,NULL,1,secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity,secondaryCellGroup); + phy_init_nr_gNB(gNB,0,0); + N_RB_DL = gNB->frame_parms.N_RB_DL; // stub to configure frame_parms - nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions); + // nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions); // call MAC to configure common parameters - phy_init_nr_gNB(gNB,0,0); - mac_top_init_gNB(); double fs,bw; @@ -436,6 +539,14 @@ int main(int argc, char **argv) fs = 61.44e6; bw = 40e6; } + else if (mu == 3 && N_RB_DL == 66) { + fs = 122.88e6; + bw = 100e6; + } + else if (mu == 3 && N_RB_DL == 32) { + fs = 61.44e6; + bw = 50e6; + } else AssertFatal(1==0,"Unsupported numerology for mu %d, N_RB %d\n",mu, N_RB_DL); gNB2UE = new_channel_desc_scm(n_tx, @@ -454,7 +565,6 @@ int main(int argc, char **argv) frame_length_complex_samples = frame_parms->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME; frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP*NR_NUMBER_OF_SUBFRAMES_PER_FRAME; - slot_length_complex_samples_no_prefix = frame_parms->samples_per_slot_wCP; s_re = malloc(2*sizeof(double*)); s_im = malloc(2*sizeof(double*)); @@ -510,21 +620,9 @@ int main(int argc, char **argv) nr_gold_pbch(UE); nr_gold_pdcch(UE,0,2); - RC.nb_nr_macrlc_inst = 1; - RC.nb_nr_mac_CC = (int*)malloc(RC.nb_nr_macrlc_inst*sizeof(int)); - for (i = 0; i < RC.nb_nr_macrlc_inst; i++) - RC.nb_nr_mac_CC[i] = 1; - mac_top_init_gNB(); - gNB_mac = RC.nrmac[0]; - - config_common(0,0,Nid_cell,78,SSB_positions,ssb_periodicity,(uint64_t)3640000000L,N_RB_DL); - config_nr_mib(0,0,1,kHz30,0,0,0,0,0); - - nr_l2_init_ue(); + nr_l2_init_ue(NULL); UE_mac = get_mac_inst(0); - UE->pdcch_vars[0][0]->crnti = 0x1234; - UE->if_inst = nr_ue_if_module_init(0); UE->if_inst->scheduled_response = nr_ue_scheduled_response; UE->if_inst->phy_config_request = nr_ue_phy_config_request; @@ -534,309 +632,250 @@ int main(int argc, char **argv) UE_mac->if_module = nr_ue_if_module_init(0); - unsigned int available_bits; + unsigned int available_bits=0; unsigned char *estimated_output_bit; unsigned char *test_input_bit; unsigned int errors_bit = 0; uint32_t errors_scrambling = 0; + test_input_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384); estimated_output_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384); - uint16_t rb_offset_count = cset_offset/6; - set_cset_offset(rb_offset_count); // generate signal - if (input_fd==NULL) { - gNB->pbch_configured = 1; - for (int i=0;i<4;i++) gNB->pbch_pdu[i]=i+1; - - nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config); - Sched_INFO.module_id = 0; - Sched_INFO.CC_id = 0; - Sched_INFO.frame = frame; - Sched_INFO.slot = slot; - Sched_INFO.DL_req = &gNB_mac->DL_req[0]; - Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0]; - Sched_INFO.HI_DCI0_req = NULL; - Sched_INFO.TX_req = &gNB_mac->TX_req[0]; - nr_schedule_response(&Sched_INFO); - - phy_procedures_gNB_TX(gNB,frame,slot,0); - - //nr_common_signal_procedures (gNB,frame,subframe); - int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP; - - LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1); - if (gNB->frame_parms.nb_antennas_tx>1) - LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1); - - int tx_offset = slot*frame_parms->samples_per_slot; - printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP); - - //TODO: loop over slots - for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { - if (gNB_config->subframe_config.dl_cyclic_prefix_type.value == 1) { - PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], - &txdata[aa][tx_offset], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); - } else { - nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], - &txdata[aa][tx_offset], - 14, - frame_parms); - } - } - } else { - printf("Reading %d samples from file to antenna buffer %d\n",frame_length_complex_samples,0); - - if (fread(txdata[0], - sizeof(int32_t), - frame_length_complex_samples, - input_fd) != frame_length_complex_samples) { - printf("error reading from file\n"); - //exit(-1); - } - } - - LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1); - if (gNB->frame_parms.nb_antennas_tx>1) - LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); - - if (output_fd) - fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); - - int txlev = signal_energy(&txdata[0][5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], - frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - - // printf("txlev %d (%f)\n",txlev,10*log10(txlev)); - - for (i=0; inb_antennas_tx; aa++) { - r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]); - r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]); - } - } - + AssertFatal(input_fd==NULL,"Not ready for input signal file\n"); + gNB->pbch_configured = 1; + gNB->ssb_pdu.ssb_pdu_rel15.bchPayload=0x001234; + + if (mcsIndex_set==0) dlsch_config.mcsIndex[0]=9; + + if (rbStart_set==0) dlsch_config.rbStart=0; + if (rbSize_set==0) dlsch_config.rbSize=N_RB_DL-dlsch_config.rbStart; //Configure UE - rrc_gNB_carrier_data_t carrier; - uint32_t pdcch_ConfigSIB1 = 0; - uint32_t ssb_SubcarrierOffset = 0; - carrier.MIB = (uint8_t*) malloc(4); - carrier.sizeof_MIB = do_MIB_NR(&carrier,0,ssb_SubcarrierOffset,pdcch_ConfigSIB1,30,2); + rrc.carrier.MIB = (uint8_t*) malloc(4); + rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0); - nr_rrc_mac_config_req_ue(0,0,0,carrier.mib.message.choice.mib,NULL,NULL,NULL); + nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig); - // Initial bandwidth part configuration -- full carrier bandwidth - UE_mac->initial_bwp_dl.bwp_id = 0; - UE_mac->initial_bwp_dl.location = 0; - UE_mac->initial_bwp_dl.scs = UE->frame_parms.subcarrier_spacing; - UE_mac->initial_bwp_dl.N_RB = UE->frame_parms.N_RB_DL; - UE_mac->initial_bwp_dl.cyclic_prefix = UE->frame_parms.Ncp; - - fapi_nr_dl_config_request_t *dl_config = &UE_mac->dl_config_request; - // Type0 PDCCH search space - dl_config->number_pdus = 1; - dl_config->dl_config_list[0].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.rnti = 0x1234; - - uint64_t mask = 0x0; - uint16_t num_rbs=24; - uint16_t rb_offset=gNB->pdcch_vars.dci_alloc[0].pdcch_params.rb_offset; - uint16_t cell_id=0; - uint16_t num_symbols=2; - for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs - mask = mask >> 1; - mask = mask | 0x100000000000; - } - uint16_t UE_rb_offset_count = rb_offset/6; - mask = mask >> UE_rb_offset_count; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.frequency_domain_resource = mask; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset - - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id; - - uint32_t number_of_search_space_per_slot=1; - uint32_t first_symbol_index=0; - uint32_t search_space_duration=0; // element of search space - uint32_t coreset_duration; // element of coreset - - coreset_duration = num_symbols * number_of_search_space_per_slot; - - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[0] = table_38213_10_1_1_c2[0]; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[1] = table_38213_10_1_1_c2[1]; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.duration = search_space_duration; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.N_RB_BWP = N_RB_DL; - - UE_mac->scheduled_response.dl_config = dl_config; - UE_mac->scheduled_response.ul_config = NULL; - UE_mac->scheduled_response.tx_request = NULL; - UE_mac->scheduled_response.module_id = 0; - UE_mac->scheduled_response.CC_id = 0; - UE_mac->scheduled_response.frame = frame; - UE_mac->scheduled_response.slot = slot; - - UE_mac->phy_config.config_req.pbch_config.system_frame_number = frame; - UE_mac->phy_config.config_req.pbch_config.ssb_index = 0; - UE_mac->phy_config.config_req.pbch_config.half_frame_bit = 0; + nr_dcireq_t dcireq; + nr_scheduled_response_t scheduled_response; + memset((void*)&dcireq,0,sizeof(dcireq)); + memset((void*)&scheduled_response,0,sizeof(scheduled_response)); + dcireq.module_id = 0; + dcireq.gNB_index = 0; + dcireq.cc_id = 0; + + scheduled_response.dl_config = &dcireq.dl_config_req; + scheduled_response.ul_config = &dcireq.ul_config_req; + scheduled_response.tx_request = NULL; + scheduled_response.module_id = 0; + scheduled_response.CC_id = 0; + scheduled_response.frame = frame; + scheduled_response.slot = slot; + nr_ue_phy_config_request(&UE_mac->phy_config); for (SNR = snr0; SNR < snr1; SNR += .2) { + varArray_t *table_tx=initVarArray(1000,sizeof(double)); + reset_meas(&gNB->phy_proc_tx); // total gNB tx + reset_meas(&gNB->dlsch_scrambling_stats); + reset_meas(&gNB->dlsch_interleaving_stats); + reset_meas(&gNB->dlsch_rate_matching_stats); + reset_meas(&gNB->dlsch_segmentation_stats); + reset_meas(&gNB->dlsch_modulation_stats); + reset_meas(&gNB->dlsch_encoding_stats); + reset_meas(&gNB->tinput); + reset_meas(&gNB->tprep); + reset_meas(&gNB->tparity); + reset_meas(&gNB->toutput); + n_errors = 0; //n_errors2 = 0; //n_alamouti = 0; - + errors_scrambling=0; n_false_positive = 0; for (trial = 0; trial < n_trials; trial++) { errors_bit = 0; //multipath channel //multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0); + + memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); + if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config); + else nr_schedule_css_dlsch_phytest(0,frame,slot); + + + Sched_INFO.module_id = 0; + Sched_INFO.CC_id = 0; + Sched_INFO.frame = frame; + Sched_INFO.slot = slot; + Sched_INFO.DL_req = &gNB_mac->DL_req[0]; + Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0]; + Sched_INFO.UL_dci_req = NULL; + Sched_INFO.TX_req = &gNB_mac->TX_req[0]; + nr_schedule_response(&Sched_INFO); + + if (run_initial_sync) + nr_common_signal_procedures(gNB,frame,slot); + else + phy_procedures_gNB_TX(gNB,frame,slot,0); + + int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP; + + if (n_trials==1) { + LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1); + if (gNB->frame_parms.nb_antennas_tx>1) + LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1); + } + int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP); + + //TODO: loop over slots + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { + + if (cyclic_prefix_type == 1) { + PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], + &txdata[aa][tx_offset], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); + } else { + nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], + &txdata[aa][tx_offset], + 14, + frame_parms); + } + } + + if (n_trials==1) { + LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1); + if (gNB->frame_parms.nb_antennas_tx>1) + LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); + } + if (output_fd) + fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); + + int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], + frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); + + // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev)); + + for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)); + i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0)); + i++) { + for (aa=0; aanb_antennas_tx; aa++) { + r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]); + r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]); + } + } + + NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15; //AWGN - sigma2_dB = 10 * log10((double)txlev) - SNR; + sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize))) - SNR; sigma2 = pow(10, sigma2_dB/10); - // printf("sigma2 %f (%f dB)\n",sigma2,sigma2_dB); - - for (i=0; iframe_parms.ofdm_symbol_size/(12*rel15.rbSize)); + + for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + iget_samples_slot_timestamp(slot+1,frame_parms,0); + i++) { for (aa=0; aanb_antennas_rx; aa++) { ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); } } - - if (n_trials == 1) { - - LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1); - if (UE->frame_parms.nb_antennas_rx>1) - LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1); - + + UE->rx_offset=0; + UE_proc.frame_rx = frame; + UE_proc.nr_tti_rx= slot; + UE_proc.subframe_rx = slot; + + dcireq.frame = frame; + dcireq.slot = slot; + + nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + nr_ue_scheduled_response(&scheduled_response); + + phy_procedures_nrUE_RX(UE, + &UE_proc, + 0, + do_pdcch_flag, + normal_txrx); + + if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= + UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) + n_errors++; + + //---------------------------------------------------------- + //---------------------- count errors ---------------------- + //---------------------------------------------------------- + + + + NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; + + int harq_pid = dlsch0->current_harq_pid; + NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; + + NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; + int16_t *UE_llr = pdsch_vars[0]->llr[0]; + + + uint32_t TBS = rel15.TBSize[0]; + uint16_t length_dmrs = 1; + uint16_t nb_rb = rel15.rbSize; + uint8_t nb_re_dmrs = rel15.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; + uint8_t mod_order = rel15.qamModOrder[0]; + uint8_t nb_symb_sch = rel15.NrOfSymbols; + + available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers); + + for (i = 0; i < available_bits; i++) { + + if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) || + ((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0))) + { + if(errors_scrambling == 0) { + LOG_D(PHY,"\n"); + LOG_D(PHY,"First bit in error in unscrambling = %d\n",i); + } + errors_scrambling++; + } + } - - if (UE->is_synchronized == 0) { - - UE_nr_rxtx_proc_t proc = {0}; - ret = nr_initial_sync(&proc, UE, normal_txrx, 1); - printf("nr_initial_sync1 returns %d\n", ret); - - if (ret < 0) - n_errors++; - - } else { // UE->is_synchronized != 0 - - UE->rx_offset = 0; - UE_proc.frame_rx = frame; - UE_proc.nr_tti_rx = slot; - UE_proc.subframe_rx = slot; - - nr_ue_scheduled_response(&UE_mac->scheduled_response); - - printf("Running phy procedures UE RX %d.%d\n", frame, slot); - - phy_procedures_nrUE_RX(UE, - &UE_proc, - 0, - do_pdcch_flag, - normal_txrx); - - if (n_trials == 1) { - - LOG_M("rxsigF0.m","rxsF0", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[0], slot_length_complex_samples_no_prefix, 1, 1); - if (UE->frame_parms.nb_antennas_rx > 1) - LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[1], slot_length_complex_samples_no_prefix, 1, 1); - - } - - if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= - UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) - n_errors++; - - //---------------------------------------------------------- - //---------------------- count errors ---------------------- - //---------------------------------------------------------- - - NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; - - NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; - int harq_pid = dlsch0->current_harq_pid; - NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; - - NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; - int16_t *UE_llr = pdsch_vars[0]->llr[0]; - - nfapi_nr_dl_config_dlsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[harq_pid]->dlsch_pdu.dlsch_pdu_rel15; - uint32_t TBS = rel15.transport_block_size; - uint16_t length_dmrs = 1; - uint16_t nb_rb = rel15.n_prb; - uint8_t nb_re_dmrs = rel15.nb_re_dmrs; - uint8_t mod_order = rel15.modulation_order; - uint8_t nb_symb_sch = rel15.nb_symbols; - - available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nb_layers); - - printf("\n"); - printf("available_bits = %u\n", available_bits); - - for (i = 0; i < available_bits; i++) { - - if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) || - ((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0))) - { - if(errors_scrambling == 0) { - printf("\n"); - printf("First bit in error in unscrambling = %d\n",i); - } - errors_scrambling++; - } - - } - - for (i = 0; i < TBS; i++) { - - estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7); - test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments - - if (estimated_output_bit[i] != test_input_bit[i]) { - if(errors_bit == 0) - printf("First bit in error in decoding = %d\n",i); - errors_bit++; - } - - } - - //////////////////////////////////////////////////////////// - - if (errors_scrambling > 0) { - if (n_trials == 1) - printf("errors_scrambling = %u (trial %d)\n", errors_scrambling, trial); - } - - if (errors_bit > 0) { - n_false_positive++; - if (n_trials == 1) - printf("errors_bit = %u (trial %d)\n", errors_bit, trial); - } - - printf("\n"); - - } // if (UE->is_synchronized == 0) - + for (i = 0; i < TBS; i++) { + + estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7); + test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments + + if (estimated_output_bit[i] != test_input_bit[i]) { + if(errors_bit == 0) + LOG_D(PHY,"First bit in error in decoding = %d (errors scrambling %d)\n",i,errors_scrambling); + errors_bit++; + } + + } + + //////////////////////////////////////////////////////////// + + if (errors_scrambling > 0) { + if (n_trials == 1) + printf("errors_scrambling = %d/%d (trial %d)\n", errors_scrambling, available_bits,trial); + } + + if (errors_bit > 0) { + n_false_positive++; + if (n_trials == 1) + printf("errors_bit = %u (trial %d)\n", errors_bit, trial); + } + } // noise trials printf("*****************************************\n"); @@ -844,15 +883,75 @@ int main(int argc, char **argv) (float) n_errors / (float) n_trials); printf("*****************************************\n"); printf("\n"); - - printf("SNR %f : n_errors (negative CRC) = %d/%d\n", SNR, n_errors, n_trials); + printf("SNR %f : n_errors (negative CRC) = %d/%d, Channel BER %e\n", SNR, n_errors, n_trials,(double)errors_scrambling/available_bits/n_trials); printf("\n"); + if (n_trials == 1) { + + LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1); + if (UE->frame_parms.nb_antennas_rx>1) + LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1); + LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1); + write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1); + break; + } + if ((float)n_errors/(float)n_trials <= target_error_rate) { printf("PDSCH test OK\n"); break; } + + if (print_perf==1) { + printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n", + 1000>>*scc->ssbSubcarrierSpacing,dlsch_config.rbSize,dlsch_config.mcsIndex[0], + gNB->dlsch[0][0]->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3, + gNB->dlsch[0][0]->harq_processes[0]->K, + gNB->dlsch[0][0]->harq_processes[0]->K/((gNB->dlsch[0][0]->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3)>3824?22:10)); + printDistribution(&gNB->phy_proc_tx,table_tx,"PHY proc tx"); + printStatIndent2(&gNB->dlsch_encoding_stats,"DLSCH encoding time"); + printStatIndent3(&gNB->dlsch_segmentation_stats,"DLSCH segmentation time"); + printStatIndent3(&gNB->tinput,"DLSCH LDPC input processing time"); + printStatIndent3(&gNB->tprep,"DLSCH LDPC input preparation time"); + printStatIndent3(&gNB->tparity,"DLSCH LDPC parity generation time"); + printStatIndent3(&gNB->toutput,"DLSCH LDPC output generation time"); + printStatIndent3(&gNB->dlsch_rate_matching_stats,"DLSCH Rate Mataching time"); + printStatIndent3(&gNB->dlsch_interleaving_stats, "DLSCH Interleaving time"); + printStatIndent2(&gNB->dlsch_modulation_stats,"DLSCH modulation time"); + printStatIndent2(&gNB->dlsch_scrambling_stats, "DLSCH scrambling time"); + + + printf("\nUE RX function statistics (per %d us slot)\n",1000>>*scc->ssbSubcarrierSpacing); + /* + printDistribution(&phy_proc_rx_tot, table_rx,"Total PHY proc rx"); + printStatIndent(&ue_front_end_tot,"Front end processing"); + printStatIndent(&dlsch_llr_tot,"rx_pdsch processing"); + printStatIndent2(&pdsch_procedures_tot,"pdsch processing"); + printStatIndent2(&dlsch_procedures_tot,"dlsch processing"); + printStatIndent2(&UE->crnti_procedures_stats,"C-RNTI processing"); + printStatIndent(&UE->ofdm_demod_stats,"ofdm demodulation"); + printStatIndent(&UE->dlsch_channel_estimation_stats,"DLSCH channel estimation time"); + printStatIndent(&UE->dlsch_freq_offset_estimation_stats,"DLSCH frequency offset estimation time"); + printStatIndent(&dlsch_decoding_tot, "DLSCH Decoding time "); + printStatIndent(&UE->dlsch_unscrambling_stats,"DLSCH unscrambling time"); + printStatIndent(&UE->dlsch_rate_unmatching_stats,"DLSCH Rate Unmatching"); + printf("|__ DLSCH Turbo Decoding(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n", + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus ? + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus : + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus, + UE->dlsch_tc_intl1_stats.trials/(double)UE->dlsch_tc_init_stats.trials, + (double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials*timeBase, + (int)((double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials), + UE->dlsch_turbo_decoding_stats.trials); + printStatIndent2(&UE->dlsch_tc_init_stats,"init"); + printStatIndent2(&UE->dlsch_tc_alpha_stats,"alpha"); + printStatIndent2(&UE->dlsch_tc_beta_stats,"beta"); + printStatIndent2(&UE->dlsch_tc_gamma_stats,"gamma"); + printStatIndent2(&UE->dlsch_tc_ext_stats,"ext"); + printStatIndent2(&UE->dlsch_tc_intl1_stats,"turbo internal interleaver"); + printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC"); + */ + } } // NSR for (i = 0; i < 2; i++) { @@ -878,5 +977,5 @@ int main(int argc, char **argv) fclose(input_fd); return(n_errors); - + } diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c index ae47b11b2f..c9253aeedf 100644 --- a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c +++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c @@ -2,7 +2,7 @@ int oai_nfapi_hi_dci0_req(nfapi_hi_dci0_request_t *hi_dci0_req) { re int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) { return(0); } int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return(0); } int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } -int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); } +//int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); } int32_t get_uldl_offset(int nr_bandP) { return(0); } NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);} int dummy_nr_ue_dl_indication(nr_downlink_indication_t *dl_info) { return(0); } diff --git a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h index 78596cc792..c7a30f826e 100644 --- a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h +++ b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h @@ -55,4 +55,172 @@ signed char quantize(double D, double x, unsigned char B) { return ((char) qxd); } +void fill_scc(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_RB_DL,int N_RB_UL,int mu_dl,int mu_ul) { + + *scc->physCellId=0; \ + // *scc->n_TimingAdvanceOffset=NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n0; + *scc->ssb_periodicityServingCell=NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms20; + scc->dmrs_TypeA_Position=NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2; + *scc->ssbSubcarrierSpacing=NR_SubcarrierSpacing_kHz30; + *scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=641032; + *scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=78; + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=640000; + scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0; + scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=NR_SubcarrierSpacing_kHz30; + + scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_DL; + scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth=13036; + scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing=mu_dl;//NR_SubcarrierSpacing_kHz30; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=12; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero=0; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->k0=0; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength=40; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->k0=0; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength=53; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->k0=0; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[3]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[3]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[4]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[4]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[5]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[5]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[5]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[6]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[6]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[7]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[7]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[8]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[8]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[9]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[9]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[9]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[10]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[10]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[11]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[11]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[12]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[12]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[12]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[13]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[13]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[14]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[14]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength=54; + *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[15]->k0=-1; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[15]->mappingType=NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[15]->startSymbolAndLength=54; + *scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]=78; + *scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA=-1; + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0; + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=NR_SubcarrierSpacing_kHz30; + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_UL; + *scc->uplinkConfigCommon->frequencyInfoUL->p_Max=20; + scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth=13036; + scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing=mu_ul;//NR_SubcarrierSpacing_kHz30; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex=98; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM=NR_RACH_ConfigGeneric__msg1_FDM_one; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart=0; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig=13; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower=-118; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleTransMax=NR_RACH_ConfigGeneric__preambleTransMax_n10; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.powerRampingStep=NR_RACH_ConfigGeneric__powerRampingStep_dB2; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow=NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present=NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_one; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.one=NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n64; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ra_ContentionResolutionTimer=NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf64; + *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB=19; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present=NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139=0; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig=NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2=2; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2=2; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength=69; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->k2=2; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[9]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[9]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[9]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->k2=33; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->startSymbolAndLength=55; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->msg3_DeltaPreamble=1; + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant=-90; + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_GroupHopping=NR_PUCCH_ConfigCommon__pucch_GroupHopping_neither; + *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId=40; + *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal=-90; + scc->ssb_PositionsInBurst->present=NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap; + *ssb_bitmap=0xff; + scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing=NR_SubcarrierSpacing_kHz30; + scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms5; + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots=7; + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols=6; + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots=2; + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols=4; + scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity=321; + + scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots=-1; + scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSymbols=-1; + scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSlots=-1; + scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSymbols=-1; + scc->ss_PBCH_BlockPower=20; + *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing=-1; +} + +void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap); +void prepare_scc(NR_ServingCellConfigCommon_t *scc); +s1ap_eNB_config_t s1ap_config; +uint32_t s1ap_generate_eNB_id(void) {return 0;} +void configure_nfapi_pnf(char *vnf_ip_addr, int vnf_p5_port, char *pnf_ip_addr, int pnf_p7_port, int vnf_p7_port) { return;} +void configure_nfapi_vnf(char *vnf_addr, int vnf_p5_port) { return;} + + #endif diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c index 58bf213e3a..99ca466fee 100644 --- a/openair1/SIMULATION/NR_PHY/pbchsim.c +++ b/openair1/SIMULATION/NR_PHY/pbchsim.c @@ -62,6 +62,50 @@ uint16_t NB_UE_INST = 1; openair0_config_t openair0_cfg[MAX_CARDS]; uint64_t get_softmodem_optmask(void) {return 0;} +void nr_phy_config_request_sim_pbchsim(PHY_VARS_gNB *gNB, + int N_RB_DL, + int N_RB_UL, + int mu, + int Nid_cell, + uint64_t position_in_burst) +{ + NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; + nfapi_nr_config_request_scf_t *gNB_config = &gNB->gNB_config; + //overwrite for new NR parameters + + uint64_t rev_burst=0; + for (int i=0; i<64; i++) + rev_burst |= (((position_in_burst>>(63-i))&0x01)<cell_config.phy_cell_id.value = Nid_cell; + gNB_config->ssb_config.scs_common.value = mu; + gNB_config->ssb_table.ssb_subcarrier_offset.value = 0; + gNB_config->ssb_table.ssb_offset_point_a.value = (N_RB_DL-20)>>1; + gNB_config->ssb_table.ssb_mask_list[1].ssb_mask.value = (rev_burst)&(0xFFFFFFFF); + gNB_config->ssb_table.ssb_mask_list[0].ssb_mask.value = (rev_burst>>32)&(0xFFFFFFFF); + gNB_config->cell_config.frame_duplex_type.value = TDD; + gNB_config->ssb_table.ssb_period.value = 1; //10ms + gNB_config->carrier_config.dl_grid_size[mu].value = N_RB_DL; + gNB_config->carrier_config.ul_grid_size[mu].value = N_RB_UL; + gNB_config->carrier_config.num_tx_ant.value = fp->nb_antennas_tx; + gNB_config->carrier_config.num_rx_ant.value = fp->nb_antennas_rx; + + gNB_config->tdd_table.tdd_period.value = 0; + //gNB_config->subframe_config.dl_cyclic_prefix_type.value = (fp->Ncp == NORMAL) ? NFAPI_CP_NORMAL : NFAPI_CP_EXTENDED; + + gNB->mac_enabled = 1; + fp->dl_CarrierFreq = 3500000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value); + fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000); + if (mu>2) fp->nr_band = 257; + else fp->nr_band = 78; + fp->threequarter_fs= 0; + + gNB_config->carrier_config.dl_bandwidth.value = config_bandwidth(mu, N_RB_DL, fp->nr_band); + + nr_init_frame_parms(gNB_config, fp); + gNB->configured = 1; + LOG_I(PHY,"gNB configured\n"); +} int main(int argc, char **argv) { char c; @@ -112,7 +156,6 @@ int main(int argc, char **argv) int frame_length_complex_samples; int frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; - nfapi_nr_config_request_t *gNB_config; int ret, payload_ret=0; int run_initial_sync=0; @@ -129,7 +172,7 @@ int main(int argc, char **argv) randominit(0); - while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:o:s:S:t:x:y:z:M:N:F:GR:dP:IL:")) != -1) { + while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:o:s:S:t:x:y:z:M:N:F:GR:dP:IL:m:")) != -1) { switch (c) { /*case 'f': write_output_file=1; @@ -304,6 +347,10 @@ int main(int argc, char **argv) loglvl = atoi(optarg); break; + case 'm': + mu = atoi(optarg); + break; + default: case 'h': printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", @@ -312,6 +359,7 @@ int main(int argc, char **argv) //printf("-p Use extended prefix mode\n"); //printf("-d Use TDD\n"); printf("-n Number of frames to simulate\n"); + printf("-m Numerology index\n"); printf("-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated\n"); printf("-S Ending SNR, runs from SNR0 to SNR1\n"); printf("-t Delay spread for multipath channel\n"); @@ -344,26 +392,27 @@ int main(int argc, char **argv) printf("Initializing gNodeB for mu %d, N_RB_DL %d\n",mu,N_RB_DL); - RC.gNB = (PHY_VARS_gNB***) malloc(sizeof(PHY_VARS_gNB **)); - RC.gNB[0] = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); - RC.gNB[0][0] = malloc(sizeof(PHY_VARS_gNB)); - gNB = RC.gNB[0][0]; - gNB_config = &gNB->gNB_config; + RC.gNB = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); + gNB = RC.gNB[0]; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; frame_parms->N_RB_DL = N_RB_DL; - frame_parms->N_RB_UL = N_RB_DL; frame_parms->Nid_cell = Nid_cell; frame_parms->nushift = Nid_cell%4; frame_parms->ssb_type = nr_ssb_type_C; - nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions); + nr_phy_config_request_sim_pbchsim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions); phy_init_nr_gNB(gNB,0,0); + nr_set_ssb_first_subcarrier(&gNB->gNB_config,frame_parms); - uint8_t n_hf = gNB_config->sch_config.half_frame_index.value; + uint8_t n_hf = 0; + int cyclic_prefix_type = NFAPI_CP_NORMAL; - double fs,bw,scs,eps; + double fs, eps; + double scs = 30000; + double bw = 100e6; switch (mu) { case 1: @@ -387,8 +436,17 @@ int main(int argc, char **argv) } else AssertFatal(1==0,"Unsupported numerology for mu %d, N_RB %d\n",mu, N_RB_DL); break; - } + + case 3: + scs = 120000; + if (N_RB_DL == 66) { + fs = 122.88e6; + bw = 100e6; + } + else AssertFatal(1==0,"Unsupported numerology for mu %d, N_RB %d\n",mu, N_RB_DL); + break; + } // cfo with respect to sub-carrier spacing eps = cfo/scs; @@ -470,27 +528,28 @@ int main(int argc, char **argv) // generate signal if (input_fd==NULL) { gNB->pbch_configured = 1; - for (int i=0;i<4;i++) gNB->pbch_pdu[i]=i+1; + + gNB->ssb_pdu.ssb_pdu_rel15.bchPayload = 0; for (int slot=0;slotslots_per_frame;slot++) { for (aa=0; aaframe_parms.nb_antennas_tx; aa++) memset(gNB->common_vars.txdataF[aa],0,frame_parms->samples_per_slot_wCP*sizeof(int32_t)); nr_common_signal_procedures (gNB,frame,slot); - + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { - if (gNB_config->subframe_config.dl_cyclic_prefix_type.value == 1) { + if (cyclic_prefix_type == 1) { PHY_ofdm_mod(gNB->common_vars.txdataF[aa], - &txdata[aa][slot*frame_parms->samples_per_slot], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); + &txdata[aa][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); } else { nr_normal_prefix_mod(gNB->common_vars.txdataF[aa], - &txdata[aa][slot*frame_parms->samples_per_slot], - 14, - frame_parms); + &txdata[aa][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)], + 14, + frame_parms); } } } @@ -578,7 +637,6 @@ int main(int argc, char **argv) if (gNB->frame_parms.nb_antennas_tx>1) LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1],frame_parms->samples_per_frame,1,1); } - if (UE->is_synchronized == 0) { UE_nr_rxtx_proc_t proc={0}; ret = nr_initial_sync(&proc, UE, normal_txrx,1); @@ -589,8 +647,10 @@ int main(int argc, char **argv) UE->rx_offset=0; uint8_t ssb_index = 0; while (!((SSB_positions >> ssb_index) & 0x01)) ssb_index++; // to select the first transmitted ssb - UE->symbol_offset = nr_get_ssb_start_symbol(frame_parms, ssb_index, n_hf); - int ssb_slot = (ssb_index/2)+(n_hf*frame_parms->slots_per_frame); + frame_parms->ssb_index = ssb_index; + UE->symbol_offset = nr_get_ssb_start_symbol(frame_parms); + + int ssb_slot = (ssb_index>>1)+(n_hf*frame_parms->slots_per_frame); for (int i=UE->symbol_offset+1; isymbol_offset+4; i++) { nr_slot_fep(UE, i%frame_parms->symbols_per_slot, @@ -618,11 +678,10 @@ int main(int argc, char **argv) uint8_t gNB_xtra_byte=0; for (int i=0; i<8; i++) gNB_xtra_byte |= ((gNB->pbch.pbch_a>>(31-i))&1)<<(7-i); - + payload_ret = (UE->pbch_vars[0]->xtra_byte == gNB_xtra_byte); for (i=0;i<3;i++){ - payload_ret += (UE->pbch_vars[0]->decoded_output[i] == gNB->pbch_pdu[2-i]); - //printf("pdu byte %d gNB: 0x%02x UE: 0x%02x\n",i,gNB->pbch_pdu[i], UE->rx_ind.rx_indication_body->mib_pdu.pdu[i]); + payload_ret += (UE->pbch_vars[0]->decoded_output[i] == (gNB->ssb_pdu.ssb_pdu_rel15.bchPayload>>(8*i))); } //printf("xtra byte gNB: 0x%02x UE: 0x%02x\n",gNB_xtra_byte, UE->rx_ind.rx_indication_body->mib_pdu.additional_bits); //printf("ret %d\n", payload_ret); diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index 6d590a2458..445c45693e 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -304,10 +304,11 @@ int main(int argc, char **argv) printf("Initializing gNodeB for mu %d, N_RB_DL %d\n",mu,N_RB_DL); - RC.gNB = (PHY_VARS_gNB***) malloc(sizeof(PHY_VARS_gNB **)); - RC.gNB[0] = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); - RC.gNB[0][0] = malloc(sizeof(PHY_VARS_gNB)); - gNB = RC.gNB[0][0]; + + RC.gNB = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); + gNB = RC.gNB[0]; + frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; @@ -315,6 +316,9 @@ int main(int argc, char **argv) frame_parms->N_RB_UL = N_RB_DL; frame_parms->Nid_cell = Nid_cell; + nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config; + cfg->carrier_config.num_tx_ant.value = n_tx; + cfg->carrier_config.num_rx_ant.value = n_rx; nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions); phy_init_nr_gNB(gNB,0,0); diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index f2783605fe..48ea26da8f 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -232,9 +232,9 @@ int main(int argc, char **argv) break; case 'R': - N_RB_DL = atoi(optarg); + N_RB_UL = atoi(optarg); #ifdef DEBUG_NR_ULSCHSIM - printf("N_RB_DL (-R) = %d\n", N_RB_DL); + printf("N_RB_UL (-R) = %d\n", N_RB_UL); #endif break; @@ -292,7 +292,7 @@ int main(int argc, char **argv) //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); printf("-M Multiple SSB positions in burst\n"); printf("-N Nid_cell\n"); - printf("-R N_RB_DL\n"); + printf("-R N_RB_UL\n"); printf("-F Input filename (.txt format) for RX conformance testing\n"); printf("-m\n"); printf("-l\n"); @@ -327,10 +327,11 @@ int main(int argc, char **argv) exit(-1); } - RC.gNB = (PHY_VARS_gNB ** *) malloc(sizeof(PHY_VARS_gNB **)); - RC.gNB[0] = (PHY_VARS_gNB **) malloc(sizeof(PHY_VARS_gNB *)); - RC.gNB[0][0] = malloc(sizeof(PHY_VARS_gNB)); - gNB = RC.gNB[0][0]; + + RC.gNB = (PHY_VARS_gNB **) malloc(sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); + gNB = RC.gNB[0]; + //gNB_config = &gNB->gNB_config; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; @@ -338,10 +339,11 @@ int main(int argc, char **argv) frame_parms->N_RB_DL = N_RB_DL; frame_parms->N_RB_UL = N_RB_UL; frame_parms->Ncp = extended_prefix_flag ? EXTENDED : NORMAL; - crcTableInit(); - nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_DL, mu, Nid_cell, SSB_positions); + memcpy(&gNB->frame_parms, frame_parms, sizeof(NR_DL_FRAME_PARMS)); + + nr_phy_config_request_sim(gNB, N_RB_UL, N_RB_UL, mu, Nid_cell, SSB_positions); phy_init_nr_gNB(gNB, 0, 0); @@ -369,7 +371,6 @@ int main(int argc, char **argv) } unsigned char harq_pid = 0; - uint8_t is_crnti = 0; unsigned int TBS = 8424; unsigned int available_bits; uint8_t nb_re_dmrs = 6; @@ -383,7 +384,7 @@ int main(int argc, char **argv) NR_gNB_ULSCH_t *ulsch_gNB = gNB->ulsch[UE_id][0]; NR_UL_gNB_HARQ_t *harq_process_gNB = ulsch_gNB->harq_processes[harq_pid]; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *rel15_ul = &harq_process_gNB->ulsch_pdu.ulsch_pdu_rel15; + nfapi_nr_pusch_pdu_t *rel15_ul = &harq_process_gNB->ulsch_pdu; NR_UE_ULSCH_t *ulsch_ue = UE->ulsch[0][0][0]; @@ -395,14 +396,15 @@ int main(int argc, char **argv) printf("\nAvailable bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order); /////////// setting rel15_ul parameters /////////// - rel15_ul->number_rbs = nb_rb; - rel15_ul->number_symbols = nb_symb_sch; - rel15_ul->Qm = mod_order; - rel15_ul->mcs = Imcs; - rel15_ul->rv = rvidx; - rel15_ul->n_layers = Nl; - rel15_ul->length_dmrs = length_dmrs; - rel15_ul->R = code_rate; + rel15_ul->rb_size = nb_rb; + rel15_ul->nr_of_symbols = nb_symb_sch; + rel15_ul->qam_mod_order = mod_order; + rel15_ul->mcs_index = Imcs; + rel15_ul->pusch_data.rv_index = rvidx; + rel15_ul->nrOfLayers = Nl; + //rel15_ul->length_dmrs = length_dmrs; + rel15_ul->target_code_rate = code_rate; + rel15_ul->pusch_data.tb_size = TBS>>3; /////////////////////////////////////////////////// double *modulated_input = malloc16(sizeof(double) * 16 * 68 * 384); // [hna] 16 segments, 68*Zc @@ -516,16 +518,24 @@ int main(int argc, char **argv) if (channel_output_uncoded[i] != ulsch_ue->harq_processes[harq_pid]->f[i]) errors_bit_uncoded = errors_bit_uncoded + 1; } - +/* printf("errors bits uncoded %u\n", errors_bit_uncoded); printf("\n"); +*/ #ifdef DEBUG_CODER printf("\n"); exit(-1); #endif - ret = nr_ulsch_decoding(gNB, UE_id, channel_output_fixed, frame_parms, - frame, nb_symb_sch, nb_re_dmrs, subframe, harq_pid, is_crnti); + uint32_t G = nr_get_G(rel15_ul->rb_size, + rel15_ul->nr_of_symbols, + nb_re_dmrs, + 1, // FIXME only single dmrs is implemented + rel15_ul->qam_mod_order, + rel15_ul->nrOfLayers); + + ret = nr_ulsch_decoding(gNB, UE_id, channel_output_fixed, frame_parms, rel15_ul, + frame, subframe, harq_pid, G); if (ret > ulsch_gNB->max_ldpc_iterations) n_errors++; @@ -541,13 +551,13 @@ int main(int argc, char **argv) errors_bit++; } } - +/* if (errors_bit > 0) { n_false_positive++; if (n_trials == 1) printf("errors_bit %u (trial %d)\n", errors_bit, trial); } - printf("\n"); + printf("\n");*/ } printf("*****************************************\n"); @@ -557,7 +567,7 @@ int main(int argc, char **argv) printf("*****************************************\n"); printf("\n"); - if (errors_bit == 0) { + if (n_errors == 0) { printf("PUSCH test OK\n"); printf("\n"); break; @@ -565,6 +575,7 @@ int main(int argc, char **argv) printf("\n"); } + if (output_fd) fclose(output_fd); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index adfb09ea6e..2adc67501a 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -52,7 +52,7 @@ #include "openair1/SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/RF/rf.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" +#include "openair2/RRC/NR/MESSAGES/asn1_msg.h" #include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" @@ -63,20 +63,39 @@ PHY_VARS_NR_UE *UE; RAN_CONTEXT_t RC; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; +int sf_ahead=4 ; +int sl_ahead=0; double cpuf; uint8_t nfapi_mode = 0; uint16_t NB_UE_INST = 1; +uint64_t downlink_frequency[MAX_NUM_CCs][4]; + -// dummy functions int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const int8_t channel, const uint8_t* pduP, const sdu_size_t pdu_len) { return 0; } -uint64_t get_softmodem_optmask(void) {return 0;} -//int rlc_module_init (int enb) {return(0);} +int generate_dlsch_header(unsigned char *mac_header, + unsigned char num_sdus, + unsigned short *sdu_lengths, + unsigned char *sdu_lcids, + unsigned char drx_cmd, + unsigned short timing_advance_cmd, + unsigned char *ue_cont_res_id, + unsigned char short_padding, + unsigned short post_padding){return 0;} void pdcp_layer_init (void) {} -boolean_t pdcp_data_ind( const protocol_ctxt_t *const ctxt_pP, const srb_flag_t srb_flagP, const MBMS_flag_t MBMS_flagP, const rb_id_t rb_idP, - const sdu_size_t sdu_buffer_sizeP, mem_block_t *const sdu_buffer_pP) -{return (0);} +boolean_t pdcp_data_ind( + const protocol_ctxt_t *const ctxt_pP, + const srb_flag_t srb_flagP, + const MBMS_flag_t MBMS_flagP, + const rb_id_t rb_idP, + const sdu_size_t sdu_buffer_sizeP, + mem_block_t *const sdu_buffer_pP +) { return(false);} + +void pdcp_run (const protocol_ctxt_t *const ctxt_pP) { return;} void nr_ip_over_LTE_DRB_preconfiguration(void){} +int rrc_init_nr_global_param(void){return(0);} + // needed for some functions uint16_t n_rnti = 0x1234; @@ -88,9 +107,9 @@ int main(int argc, char **argv) int i,sf; double SNR, snr0 = -2.0, snr1 = 2.0; double sigma, sigma_dB; - double snr_step = 0.1; + double snr_step = 1; uint8_t snr1set = 0; - int slot = 0; + int slot = 0, frame = 0; FILE *output_fd = NULL; //uint8_t write_output_file = 0; int trial, n_trials = 1, n_errors = 0, n_false_positive = 0, delay = 0; @@ -104,8 +123,7 @@ int main(int argc, char **argv) SCM_t channel_model = AWGN; //Rayleigh1_anticorr; uint16_t N_RB_DL = 106, N_RB_UL = 106, mu = 1; //unsigned char frame_type = 0; - int number_of_frames = 1; - int frame_length_complex_samples; + int frame_length_complex_samples,frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; int loglvl = OAILOG_WARNING; uint64_t SSB_positions=0x01; @@ -121,11 +139,13 @@ int main(int argc, char **argv) int32_t txlev; int start_rb = 0; int UE_id =0; // [hna] only works for UE_id = 0 because NUMBER_OF_NR_UE_MAX is set to 1 (phy_init_nr_gNB causes segmentation fault) - + float target_error_rate = 0.01; + cpuf = get_cpu_freq_GHz(); UE_nr_rxtx_proc_t UE_proc; + FILE *scg_fd=NULL; if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0 ) { @@ -147,19 +167,14 @@ int main(int argc, char **argv) break; case 'f': - number_of_frames = atoi(optarg); - break; + scg_fd = fopen(optarg, "r"); - /*case 'f': - write_output_file = 1; - output_fd = fopen(optarg, "w"); - - if (output_fd == NULL) { + if (scg_fd == NULL) { printf("Error opening %s\n", optarg); exit(-1); } - break;*/ + break; case 'g': switch ((char) *optarg) { @@ -316,10 +331,10 @@ int main(int argc, char **argv) //printf("-x Transmission mode (1,2,6 for the moment)\n"); printf("-y Number of TX antennas used in eNB\n"); printf("-z Number of RX antennas used in UE\n"); - printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); printf("-F Input filename (.txt format) for RX conformance testing\n"); + printf("-G raw file containing RRC configuration (generated by gNB)\n"); printf("-M Multiple SSB positions in burst\n"); printf("-N Nid_cell\n"); printf("-O oversampling factor (1,2,4,8,16)\n"); @@ -334,6 +349,8 @@ int main(int argc, char **argv) set_glog(loglvl); T_stdout = 1; + get_softmodem_params()->phy_test = 1; + if (snr1set == 0) snr1 = snr0 + 10; @@ -347,16 +364,16 @@ int main(int argc, char **argv) exit(-1); } - RC.gNB = (PHY_VARS_gNB ** *) malloc(sizeof(PHY_VARS_gNB **)); - RC.gNB[0] = (PHY_VARS_gNB **) malloc(sizeof(PHY_VARS_gNB *)); - RC.gNB[0][0] = malloc(sizeof(PHY_VARS_gNB)); - gNB = RC.gNB[0][0]; + RC.gNB = (PHY_VARS_gNB **) malloc(sizeof(PHY_VARS_gNB *)); + RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); + gNB = RC.gNB[0]; //gNB_config = &gNB->gNB_config; //memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = (nfapi_rx_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_rx_indication_pdu_t)); + gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = (nfapi_crc_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_crc_indication_pdu_t)); gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; - + gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs = 0; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; @@ -364,15 +381,48 @@ int main(int argc, char **argv) frame_parms->N_RB_UL = N_RB_UL; frame_parms->Ncp = extended_prefix_flag ? EXTENDED : NORMAL; - crcTableInit(); + RC.nb_nr_macrlc_inst = 1; + RC.nb_nr_mac_CC = (int*)malloc(RC.nb_nr_macrlc_inst*sizeof(int)); + for (i = 0; i < RC.nb_nr_macrlc_inst; i++) + RC.nb_nr_mac_CC[i] = 1; + mac_top_init_gNB(); + gNB_MAC_INST* gNB_mac = RC.nrmac[0]; + gNB_RRC_INST rrc; + memset((void*)&rrc,0,sizeof(rrc)); - nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_UL, mu, Nid_cell, SSB_positions); + rrc.carrier.servingcellconfigcommon = calloc(1,sizeof(*rrc.carrier.servingcellconfigcommon)); - phy_init_nr_gNB(gNB, 0, 0); - //init_eNB_afterRU(); + NR_ServingCellConfigCommon_t *scc = rrc.carrier.servingcellconfigcommon; + NR_CellGroupConfig_t *secondaryCellGroup=calloc(1,sizeof(*secondaryCellGroup)); + prepare_scc(rrc.carrier.servingcellconfigcommon); + uint64_t ssb_bitmap; + fill_scc(rrc.carrier.servingcellconfigcommon,&ssb_bitmap,N_RB_DL,N_RB_DL,mu,mu); + + fill_default_secondaryCellGroup(scc, + secondaryCellGroup, + 0, + 1, + n_tx, + 0); + fix_scc(scc,ssb_bitmap); + + xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); + + AssertFatal((gNB->if_inst = NR_IF_Module_init(0))!=NULL,"Cannot register interface"); + gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; + // common configuration + rrc_mac_config_req_gNB(0,0,1,scc,0,0,NULL); + // UE dedicated configuration + rrc_mac_config_req_gNB(0,0,1,NULL,1,secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity,secondaryCellGroup); + phy_init_nr_gNB(gNB,0,0); + N_RB_DL = gNB->frame_parms.N_RB_DL; + + //crcTableInit(); + + //nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_UL, mu, Nid_cell, SSB_positions); frame_length_complex_samples = frame_parms->samples_per_subframe; - //frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP; + frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP; //configure UE UE = malloc(sizeof(PHY_VARS_NR_UE)); @@ -389,7 +439,9 @@ int main(int argc, char **argv) } //nr_init_frame_parms_ue(&UE->frame_parms); - //init_nr_ue_transport(UE, 0); + init_nr_ue_transport(UE, 0); + + /* for (sf = 0; sf < 2; sf++) { for (i = 0; i < 2; i++) { @@ -399,9 +451,29 @@ int main(int argc, char **argv) printf("Can't get ue ulsch structures\n"); exit(-1); } - } } + */ + + nr_l2_init_ue(NULL); + NR_UE_MAC_INST_t* UE_mac = get_mac_inst(0); + + UE->if_inst = nr_ue_if_module_init(0); + UE->if_inst->scheduled_response = nr_ue_scheduled_response; + UE->if_inst->phy_config_request = nr_ue_phy_config_request; + UE->if_inst->dl_indication = nr_ue_dl_indication; + UE->if_inst->ul_indication = nr_ue_ul_indication; + + UE_mac->if_module = nr_ue_if_module_init(0); + + //Configure UE + rrc.carrier.MIB = (uint8_t*) malloc(4); + rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0); + + nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig); + + nr_ue_phy_config_request(&UE_mac->phy_config); + unsigned char harq_pid = 0; @@ -416,7 +488,6 @@ int main(int argc, char **argv) unsigned char *test_input_bit; uint32_t errors_decoding = 0; uint32_t errors_scrambling = 0; - uint32_t is_frame_in_error = 0; test_input_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384); estimated_output_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384); @@ -428,7 +499,7 @@ int main(int argc, char **argv) uint16_t number_dmrs_symbols = 0; unsigned int available_bits; uint8_t nb_re_dmrs; - uint8_t length_dmrs = UE->dmrs_UplinkConfig.pusch_maxLength; + uint8_t length_dmrs = UE->pusch_config.dmrs_UplinkConfig.pusch_maxLength; unsigned char mod_order; uint16_t code_rate; @@ -440,12 +511,11 @@ int main(int argc, char **argv) 0, 0, nb_symb_sch, - &UE->dmrs_UplinkConfig, - UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType, + UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, frame_parms->ofdm_symbol_size); mod_order = nr_get_Qm_ul(Imcs, 0); - nb_re_dmrs = ((UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1) ? 6 : 4) * number_dmrs_symbols; + nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1) ? 6 : 4) * number_dmrs_symbols; code_rate = nr_get_code_rate_ul(Imcs, 0); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, precod_nbr_layers); @@ -454,13 +524,6 @@ int main(int argc, char **argv) for (SNR = snr0; SNR < snr1; SNR += snr_step) { - printf("-------------------\n"); - printf("SNR %f\n", SNR); - printf("-------------------\n"); - - is_frame_in_error = 0; - for (int frame = 0; frame < number_of_frames; frame++) { - UE_proc.nr_tti_tx = slot; UE_proc.frame_tx = frame; @@ -481,8 +544,8 @@ int main(int argc, char **argv) /////////////////////////////////////////////////// */ - UL_tti_req->sfn = frame; - UL_tti_req->slot = slot; + UL_tti_req->SFN = frame; + UL_tti_req->Slot = slot; UL_tti_req->n_pdus = 1; UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); @@ -512,7 +575,7 @@ int main(int argc, char **argv) pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; pusch_pdu->pusch_data.new_data_indicator = 0; - pusch_pdu->pusch_data.tb_size = TBS; + pusch_pdu->pusch_data.tb_size = TBS>>3; pusch_pdu->pusch_data.num_cb = 0; @@ -526,7 +589,7 @@ int main(int argc, char **argv) scheduled_response.ul_config = &ul_config; scheduled_response.dl_config = NULL; - ul_config.sfn_slot = slot; + ul_config.slot = slot; ul_config.number_pdus = 1; ul_config.ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; ul_config.ul_config_list[0].ulsch_config_pdu.rnti = n_rnti; @@ -550,11 +613,12 @@ int main(int argc, char **argv) phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); - //LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1); + if (n_trials==1) + LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1); /////////// //////////////////////////////////////////////////// - tx_offset = slot*frame_parms->samples_per_slot; + tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); txlev = signal_energy_amp_shift(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); @@ -587,13 +651,21 @@ int main(int argc, char **argv) //---------------------------------------------------------- //------------------- gNB phy procedures ------------------- //---------------------------------------------------------- + gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; + gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs = 0; + phy_procedures_gNB_common_RX(gNB, frame, slot); - //LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0],frame_length_complex_samples_no_prefix,1,1); + if (n_trials==1) + LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0],frame_length_complex_samples_no_prefix,1,1); phy_procedures_gNB_uespec_RX(gNB, frame, slot); //////////////////////////////////////////////////////////// + if (gNB->ulsch[0][0]->last_iteration_cnt >= + gNB->ulsch[0][0]->max_ldpc_iterations+1) + n_errors++; + //---------------------------------------------------------- //----------------- count and print errors ----------------- //---------------------------------------------------------- @@ -603,14 +675,15 @@ int main(int argc, char **argv) if(((ulsch_ue[0]->g[i] == 0) && (gNB->pusch_vars[UE_id]->llr[i] <= 0)) || ((ulsch_ue[0]->g[i] == 1) && (gNB->pusch_vars[UE_id]->llr[i] >= 0))) { - if(errors_scrambling == 0) - printf("\x1B[34m" "[frame %d][trial %d]\t1st bit in error in unscrambling = %d\n" "\x1B[0m", frame, trial, i); + /*if(errors_scrambling == 0) + printf("\x1B[34m" "[frame %d][trial %d]\t1st bit in error in unscrambling = %d\n" "\x1B[0m", frame, trial, i);*/ errors_scrambling++; } } if (errors_scrambling > 0) { - printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in unscrambling = %d\n" "\x1B[0m", frame, trial, errors_scrambling); + if (n_trials==1) + printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in unscrambling = %d\n" "\x1B[0m", frame, trial, errors_scrambling); } for (i = 0; i < TBS; i++) { @@ -619,38 +692,39 @@ int main(int argc, char **argv) test_input_bit[i] = (ulsch_ue[0]->harq_processes[harq_pid]->b[i/8] & (1 << (i & 7))) >> (i & 7); if (estimated_output_bit[i] != test_input_bit[i]) { - if(errors_decoding == 0) - printf("\x1B[34m""[frame %d][trial %d]\t1st bit in error in decoding = %d\n" "\x1B[0m", frame, trial, i); + /*if(errors_decoding == 0) + printf("\x1B[34m""[frame %d][trial %d]\t1st bit in error in decoding = %d\n" "\x1B[0m", frame, trial, i);*/ errors_decoding++; } } if (errors_decoding > 0) { - is_frame_in_error = 1; n_false_positive++; - printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %d\n" "\x1B[0m", frame, trial, errors_decoding); - } else { - is_frame_in_error = 0; - break; - } - //////////////////////////////////////////////////////////// + if (n_trials==1) + printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %d\n" "\x1B[0m", frame, trial, errors_decoding); + } + } // trial loop - if (is_frame_in_error == 1) - break; - } // frame loop + printf("*****************************************\n"); + printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %d/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, n_trials); + printf("\n"); + printf("SNR %f: Channel BLER %e, Channel BER %e\n", SNR,(double)n_errors/n_trials,(double)errors_scrambling/available_bits/n_trials); + printf("*****************************************\n"); + printf("\n"); - if(is_frame_in_error == 0) - break; + if(n_trials==1) + break; + + if ((float)n_errors/(float)n_trials <= target_error_rate) { + printf("*************\n"); + printf("PUSCH test OK\n"); + printf("*************\n"); + break; + } + } // SNR loop - if(is_frame_in_error == 0) { - printf("\n"); - printf("*************\n"); - printf("PUSCH test OK\n"); - printf("*************\n"); - } - printf("\n"); free(test_input_bit); diff --git a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c index 3d5d483be8..fa8b49842f 100644 --- a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c +++ b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c @@ -237,7 +237,7 @@ int init_test(unsigned char N_tx, unsigned char N_rx, unsigned char transmission frame_parms->nb_antennas_tx = N_tx; frame_parms->nb_antennas_rx = N_rx; frame_parms->frame_type = frame_type; - frame_parms->nb_antenna_ports_eNB = 1; + frame_parms->nb_antenna_ports_gNB = 1; frame_parms->threequarter_fs = 0; frame_parms->numerology_index = NUMEROLOGY_INDEX_MAX_NR; int mu = 1; diff --git a/openair2/COMMON/platform_constants.h b/openair2/COMMON/platform_constants.h index 581ff39527..7a7e984aca 100644 --- a/openair2/COMMON/platform_constants.h +++ b/openair2/COMMON/platform_constants.h @@ -62,6 +62,7 @@ // overwrite the previous deinitions # define MAX_MODULES NB_MODULES_MAX +#define MAX_NR_RRC_UE_CONTEXTS 64 #ifndef UE_EXPANSION // TODO:L2 FAPI simulator. @@ -83,7 +84,7 @@ #else #define MAX_MOBILES_PER_ENB 4 #define MAX_MOBILES_PER_ENB_NB_IoT 4 - #define MAX_MOBILES_PER_GNB 4 + #define MAX_MOBILES_PER_GNB 2//16 #define MAX_eNB 2 #define MAX_gNB 2 #endif @@ -96,8 +97,10 @@ #define MAX_gNB 2 #endif -#define NUMBER_OF_NR_DLSCH_MAX 4 -#define NUMBER_OF_NR_ULSCH_MAX 4 +#define NUMBER_OF_NR_DLSCH_MAX 2//16 +#define NUMBER_OF_NR_ULSCH_MAX 2//16 +#define NUMBER_OF_NR_SR_MAX 16 + #define MAX_MANAGED_ENB_PER_MOBILE 2 #define MAX_MANAGED_GNB_PER_MOBILE 2 diff --git a/openair2/COMMON/rrc_messages_types.h b/openair2/COMMON/rrc_messages_types.h index 6c62d59d6d..68e1753448 100644 --- a/openair2/COMMON/rrc_messages_types.h +++ b/openair2/COMMON/rrc_messages_types.h @@ -41,7 +41,7 @@ #include "LTE_SL-PeriodComm-r12.h" #include "LTE_SL-DiscResourcePool-r12.h" #include "NR_RACH-ConfigCommon.h" - +#include "NR_ServingCellConfigCommon.h" //-------------------------------------------------------------------------------------------// // Messages for RRC logging #if defined(DISABLE_ITTI_XER_PRINT) @@ -400,194 +400,9 @@ typedef struct NRRrcConfigurationReq_s { uint16_t mcc[PLMN_LIST_MAX_SIZE]; uint16_t mnc[PLMN_LIST_MAX_SIZE]; uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE]; - int16_t nb_cc; - lte_frame_type_t frame_type[MAX_NUM_CCs]; - uint8_t tdd_config[MAX_NUM_CCs]; - uint8_t tdd_config_s[MAX_NUM_CCs]; - lte_prefix_type_t DL_prefix_type[MAX_NUM_CCs]; - lte_prefix_type_t UL_prefix_type[MAX_NUM_CCs]; - int16_t nr_band[MAX_NUM_CCs]; - uint64_t downlink_frequency[MAX_NUM_CCs]; - int32_t uplink_frequency_offset[MAX_NUM_CCs]; - int16_t Nid_cell[MAX_NUM_CCs];// for testing, change later - int16_t N_RB_DL[MAX_NUM_CCs];// for testing, change later - int nb_antenna_ports[MAX_NUM_CCs]; - - ///NR - //MIB - long MIB_subCarrierSpacingCommon[MAX_NUM_CCs]; - uint32_t MIB_ssb_SubcarrierOffset[MAX_NUM_CCs]; - long MIB_dmrs_TypeA_Position[MAX_NUM_CCs]; - uint32_t pdcch_ConfigSIB1[MAX_NUM_CCs]; - - //SIB1 - long SIB1_frequencyOffsetSSB[MAX_NUM_CCs]; - long SIB1_ssb_PeriodicityServingCell[MAX_NUM_CCs]; - long SIB1_ss_PBCH_BlockPower[MAX_NUM_CCs]; - //NR FrequencyInfoDL - long absoluteFrequencySSB[MAX_NUM_CCs]; - long DL_FreqBandIndicatorNR[MAX_NUM_CCs]; - long DL_absoluteFrequencyPointA[MAX_NUM_CCs]; - - //NR DL SCS-SpecificCarrier - long DL_offsetToCarrier[MAX_NUM_CCs]; - long DL_SCS_SubcarrierSpacing[MAX_NUM_CCs]; - long DL_carrierBandwidth[MAX_NUM_CCs]; - - //NR BWP-DownlinkCommon - uint32_t DL_locationAndBandwidth[MAX_NUM_CCs]; - long DL_BWP_SubcarrierSpacing[MAX_NUM_CCs]; - lte_prefix_type_t DL_BWP_prefix_type[MAX_NUM_CCs]; - - //NR FrequencyInfoUL - long UL_FreqBandIndicatorNR[MAX_NUM_CCs]; - long UL_absoluteFrequencyPointA[MAX_NUM_CCs]; - long UL_additionalSpectrumEmission[MAX_NUM_CCs]; - long UL_p_Max[MAX_NUM_CCs]; - long UL_frequencyShift7p5khz[MAX_NUM_CCs]; - - //NR UL SCS-SpecificCarrier - uint32_t UL_offsetToCarrier[MAX_NUM_CCs]; - long UL_SCS_SubcarrierSpacing[MAX_NUM_CCs]; - uint32_t UL_carrierBandwidth[MAX_NUM_CCs]; - - // NR BWP-UplinkCommon - uint32_t UL_locationAndBandwidth[MAX_NUM_CCs]; - long UL_BWP_SubcarrierSpacing[MAX_NUM_CCs]; - lte_prefix_type_t UL_BWP_prefix_type[MAX_NUM_CCs]; - long UL_timeAlignmentTimerCommon[MAX_NUM_CCs]; - long ServingCellConfigCommon_n_TimingAdvanceOffset[MAX_NUM_CCs]; - uint64_t ServingCellConfigCommon_ssb_PositionsInBurst_PR[MAX_NUM_CCs]; - long ServingCellConfigCommon_ssb_periodicityServingCell[MAX_NUM_CCs]; //ServingCellConfigCommon - long ServingCellConfigCommon_dmrs_TypeA_Position[MAX_NUM_CCs]; //ServingCellConfigCommon - long NIA_SubcarrierSpacing[MAX_NUM_CCs]; //ServingCellConfigCommon Used only for non-initial access - long ServingCellConfigCommon_ss_PBCH_BlockPower[MAX_NUM_CCs]; //ServingCellConfigCommon - - - //NR TDD-UL-DL-ConfigCommon - long referenceSubcarrierSpacing[MAX_NUM_CCs]; - long dl_UL_TransmissionPeriodicity[MAX_NUM_CCs]; - long nrofDownlinkSlots[MAX_NUM_CCs]; - long nrofDownlinkSymbols[MAX_NUM_CCs]; - long nrofUplinkSlots[MAX_NUM_CCs]; - long nrofUplinkSymbols[MAX_NUM_CCs]; - - //NR RACH-ConfigCommon - long rach_totalNumberOfRA_Preambles[MAX_NUM_CCs]; - long rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[MAX_NUM_CCs]; - long rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[MAX_NUM_CCs]; - long rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[MAX_NUM_CCs]; - long rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[MAX_NUM_CCs]; - long rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[MAX_NUM_CCs]; - long rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[MAX_NUM_CCs]; - uint32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four[MAX_NUM_CCs]; - uint32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight[MAX_NUM_CCs]; - uint32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen[MAX_NUM_CCs]; - BOOLEAN_t rach_groupBconfigured[MAX_NUM_CCs]; - long rach_ra_Msg3SizeGroupA[MAX_NUM_CCs]; - e_NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB rach_messagePowerOffsetGroupB[MAX_NUM_CCs]; - long rach_numberOfRA_PreamblesGroupA[MAX_NUM_CCs]; - long rach_ra_ContentionResolutionTimer[MAX_NUM_CCs]; - long rsrp_ThresholdSSB[MAX_NUM_CCs]; - long rsrp_ThresholdSSB_SUL[MAX_NUM_CCs]; - long prach_RootSequenceIndex_choice[MAX_NUM_CCs]; - uint32_t prach_RootSequenceIndex_l839[MAX_NUM_CCs]; - uint32_t prach_RootSequenceIndex_l139[MAX_NUM_CCs]; - long prach_msg1_SubcarrierSpacing[MAX_NUM_CCs]; - long restrictedSetConfig[MAX_NUM_CCs]; - long msg3_transformPrecoding[MAX_NUM_CCs]; - //ssb-perRACH-OccasionAndCB-PreamblesPerSSB not sure - - //NR RACH-ConfigGeneric - uint32_t prach_ConfigurationIndex[MAX_NUM_CCs]; - long prach_msg1_FDM[MAX_NUM_CCs]; - long prach_msg1_FrequencyStart[MAX_NUM_CCs]; - uint32_t zeroCorrelationZoneConfig[MAX_NUM_CCs]; - long preambleReceivedTargetPower[MAX_NUM_CCs]; - long preambleTransMax[MAX_NUM_CCs]; - long powerRampingStep[MAX_NUM_CCs]; - long ra_ResponseWindow[MAX_NUM_CCs]; - - //NR PUSCH-ConfigCommon - BOOLEAN_t groupHoppingEnabledTransformPrecoding[MAX_NUM_CCs]; - long msg3_DeltaPreamble[MAX_NUM_CCs]; - long p0_NominalWithGrant[MAX_NUM_CCs]; - - ///NR PUSCH-TimeDomainResourceAllocation - uint32_t PUSCH_TimeDomainResourceAllocation_k2[MAX_NUM_CCs]; - long PUSCH_TimeDomainResourceAllocation_mappingType[MAX_NUM_CCs]; - uint32_t PUSCH_TimeDomainResourceAllocation_startSymbolAndLength[MAX_NUM_CCs]; - - //NR PUCCH-ConfigCommon - uint32_t pucch_ResourceCommon[MAX_NUM_CCs]; - long pucch_GroupHopping[MAX_NUM_CCs]; - uint32_t hoppingId[MAX_NUM_CCs]; - long p0_nominal[MAX_NUM_CCs]; - - //NR PDSCH-ConfigCOmmon - //NR PDSCH-TimeDomainResourceAllocation - uint32_t PDSCH_TimeDomainResourceAllocation_k0[MAX_NUM_CCs]; - long PDSCH_TimeDomainResourceAllocation_mappingType[MAX_NUM_CCs]; - long PDSCH_TimeDomainResourceAllocation_startSymbolAndLength[MAX_NUM_CCs]; - - //NR RateMatchPattern is used to configure one rate matching pattern for PDSCH - long rateMatchPatternId[MAX_NUM_CCs]; - long RateMatchPattern_patternType[MAX_NUM_CCs]; - long symbolsInResourceBlock[MAX_NUM_CCs]; - long periodicityAndPattern[MAX_NUM_CCs]; - long RateMatchPattern_controlResourceSet[MAX_NUM_CCs]; ///ControlResourceSetId - long RateMatchPattern_subcarrierSpacing[MAX_NUM_CCs]; - long RateMatchPattern_mode[MAX_NUM_CCs]; - - //NR PDCCH-ConfigCommon - uint32_t controlResourceSetZero[MAX_NUM_CCs]; - uint32_t searchSpaceZero[MAX_NUM_CCs]; - long searchSpaceSIB1[MAX_NUM_CCs]; - long searchSpaceOtherSystemInformation[MAX_NUM_CCs]; - long pagingSearchSpace[MAX_NUM_CCs]; - long ra_SearchSpace[MAX_NUM_CCs]; - //NR PDCCH-ConfigCommon commonControlResourcesSets - long PDCCH_common_controlResourceSetId[MAX_NUM_CCs]; - long PDCCH_common_ControlResourceSet_duration[MAX_NUM_CCs]; - long PDCCH_cce_REG_MappingType[MAX_NUM_CCs]; - long PDCCH_reg_BundleSize[MAX_NUM_CCs]; - long PDCCH_interleaverSize[MAX_NUM_CCs]; - long PDCCH_shiftIndex[MAX_NUM_CCs]; - long PDCCH_precoderGranularity[MAX_NUM_CCs]; //Corresponds to L1 parameter 'CORESET-precoder-granuality' - long PDCCH_TCI_StateId[MAX_NUM_CCs]; - BOOLEAN_t tci_PresentInDCI[MAX_NUM_CCs]; - uint32_t PDCCH_DMRS_ScramblingID[MAX_NUM_CCs]; - - //NR PDCCH-ConfigCommon commonSearchSpaces - long SearchSpaceId[MAX_NUM_CCs]; - long commonSearchSpaces_controlResourceSetId[MAX_NUM_CCs]; - long SearchSpace_monitoringSlotPeriodicityAndOffset_choice[MAX_NUM_CCs]; - uint32_t SearchSpace_monitoringSlotPeriodicityAndOffset_value[MAX_NUM_CCs]; - uint32_t SearchSpace_duration[MAX_NUM_CCs]; - long SearchSpace_nrofCandidates_aggregationLevel1[MAX_NUM_CCs]; - long SearchSpace_nrofCandidates_aggregationLevel2[MAX_NUM_CCs]; - long SearchSpace_nrofCandidates_aggregationLevel4[MAX_NUM_CCs]; - long SearchSpace_nrofCandidates_aggregationLevel8[MAX_NUM_CCs]; - long SearchSpace_nrofCandidates_aggregationLevel16[MAX_NUM_CCs]; - long SearchSpace_searchSpaceType[MAX_NUM_CCs]; - long Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1[MAX_NUM_CCs]; - long Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2[MAX_NUM_CCs]; - long Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4[MAX_NUM_CCs]; - long Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8[MAX_NUM_CCs]; - long Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16[MAX_NUM_CCs]; - long Common_dci_Format2_3_monitoringPeriodicity[MAX_NUM_CCs]; - long Common_dci_Format2_3_nrofPDCCH_Candidates[MAX_NUM_CCs]; - long ue_Specific__dci_Formats[MAX_NUM_CCs]; - - //RateMatchPatternLTE-CRS - uint32_t RateMatchPatternLTE_CRS_carrierFreqDL[MAX_NUM_CCs]; - long RateMatchPatternLTE_CRS_carrierBandwidthDL[MAX_NUM_CCs]; - long RateMatchPatternLTE_CRS_nrofCRS_Ports[MAX_NUM_CCs]; - long RateMatchPatternLTE_CRS_v_Shift[MAX_NUM_CCs]; - long RateMatchPatternLTE_CRS_radioframeAllocationPeriod[MAX_NUM_CCs]; - uint32_t RateMatchPatternLTE_CRS_radioframeAllocationOffset[MAX_NUM_CCs]; - long RateMatchPatternLTE_CRS_subframeAllocation_choice[MAX_NUM_CCs]; - + NR_ServingCellConfigCommon_t *scc; + int ssb_SubcarrierOffset; + int pdsch_AntennaPorts; } gNB_RrcConfigurationReq; diff --git a/openair2/COMMON/s1ap_messages_types.h b/openair2/COMMON/s1ap_messages_types.h index 2615494d3b..aa718dbcf8 100644 --- a/openair2/COMMON/s1ap_messages_types.h +++ b/openair2/COMMON/s1ap_messages_types.h @@ -81,7 +81,8 @@ #ifndef OCP_FRAMEWORK typedef enum cell_type_e { CELL_MACRO_ENB, - CELL_HOME_ENB + CELL_HOME_ENB, + CELL_MACRO_GNB } cell_type_t; typedef enum paging_drx_e { @@ -272,6 +273,22 @@ typedef struct e_rab_setup_s { uint32_t gtp_teid; } e_rab_setup_t; +typedef struct e_rab_tobe_added_s { + /* Unique e_rab_id for the UE. */ + uint8_t e_rab_id; + + /* Unique drb_ID for the UE. */ + uint8_t drb_ID; + + /* The transport layer address for the IP packets */ + transport_layer_addr_t eNB_addr; + + /* S-GW Tunnel endpoint identifier */ + uint32_t gtp_teid; +} e_rab_tobe_added_t; + + + typedef struct e_rab_tobeswitched_s { /* Unique e_rab_id for the UE. */ uint8_t e_rab_id; diff --git a/openair2/COMMON/x2ap_messages_def.h b/openair2/COMMON/x2ap_messages_def.h index 6c2d56a942..8438fd1037 100644 --- a/openair2/COMMON/x2ap_messages_def.h +++ b/openair2/COMMON/x2ap_messages_def.h @@ -50,3 +50,8 @@ MESSAGE_DEF(X2AP_UE_CONTEXT_RELEASE , MESSAGE_PRIORITY_MED, x2ap_ue_ /*Senb bearer addition messages X2AP <-> RRC */ MESSAGE_DEF(X2AP_SENB_ADDITION_REQ , MESSAGE_PRIORITY_MED, x2ap_senb_addition_req_t , x2ap_senb_addition_req) + +/*SGnb bearer addition messages X2AP <-> RRC */ +MESSAGE_DEF(X2AP_ENDC_SGNB_ADDITION_REQ , MESSAGE_PRIORITY_MED, x2ap_ENDC_sgnb_addition_req_t , x2ap_ENDC_sgnb_addition_req) +MESSAGE_DEF(X2AP_ENDC_SGNB_ADDITION_REQ_ACK , MESSAGE_PRIORITY_MED, x2ap_ENDC_sgnb_addition_req_ACK_t , x2ap_ENDC_sgnb_addition_req_ACK) +MESSAGE_DEF(X2AP_ENDC_SGNB_RECONF_COMPLETE , MESSAGE_PRIORITY_MED, x2ap_ENDC_reconf_complete_t , x2ap_ENDC_sgnb_reconf_complete) diff --git a/openair2/COMMON/x2ap_messages_types.h b/openair2/COMMON/x2ap_messages_types.h index e502191d2b..ed3470a7d6 100644 --- a/openair2/COMMON/x2ap_messages_types.h +++ b/openair2/COMMON/x2ap_messages_types.h @@ -28,16 +28,19 @@ //-------------------------------------------------------------------------------------------// // Defines to access message fields. -#define X2AP_REGISTER_ENB_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_register_enb_req -#define X2AP_SETUP_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_setup_req -#define X2AP_SETUP_RESP(mSGpTR) (mSGpTR)->ittiMsg.x2ap_setup_resp -#define X2AP_HANDOVER_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_handover_req -#define X2AP_HANDOVER_REQ_ACK(mSGpTR) (mSGpTR)->ittiMsg.x2ap_handover_req_ack -#define X2AP_REGISTER_ENB_CNF(mSGpTR) (mSGpTR)->ittiMsg.x2ap_register_enb_cnf -#define X2AP_DEREGISTERED_ENB_IND(mSGpTR) (mSGpTR)->ittiMsg.x2ap_deregistered_enb_ind -#define X2AP_UE_CONTEXT_RELEASE(mSGpTR) (mSGpTR)->ittiMsg.x2ap_ue_context_release -#define X2AP_HANDOVER_CANCEL(mSGpTR) (mSGpTR)->ittiMsg.x2ap_handover_cancel -#define X2AP_SENB_ADDITION_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_senb_addition_req +#define X2AP_REGISTER_ENB_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_register_enb_req +#define X2AP_SETUP_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_setup_req +#define X2AP_SETUP_RESP(mSGpTR) (mSGpTR)->ittiMsg.x2ap_setup_resp +#define X2AP_HANDOVER_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_handover_req +#define X2AP_HANDOVER_REQ_ACK(mSGpTR) (mSGpTR)->ittiMsg.x2ap_handover_req_ack +#define X2AP_REGISTER_ENB_CNF(mSGpTR) (mSGpTR)->ittiMsg.x2ap_register_enb_cnf +#define X2AP_DEREGISTERED_ENB_IND(mSGpTR) (mSGpTR)->ittiMsg.x2ap_deregistered_enb_ind +#define X2AP_UE_CONTEXT_RELEASE(mSGpTR) (mSGpTR)->ittiMsg.x2ap_ue_context_release +#define X2AP_HANDOVER_CANCEL(mSGpTR) (mSGpTR)->ittiMsg.x2ap_handover_cancel +#define X2AP_SENB_ADDITION_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_senb_addition_req +#define X2AP_ENDC_SGNB_ADDITION_REQ(mSGpTR) (mSGpTR)->ittiMsg.x2ap_ENDC_sgnb_addition_req +#define X2AP_ENDC_SGNB_ADDITION_REQ_ACK(mSGpTR) (mSGpTR)->ittiMsg.x2ap_ENDC_sgnb_addition_req_ACK +#define X2AP_ENDC_SGNB_RECONF_COMPLETE(mSGpTR) (mSGpTR)->ittiMsg.x2ap_ENDC_sgnb_reconf_complete #define X2AP_MAX_NB_ENB_IP_ADDRESS 2 @@ -66,6 +69,13 @@ typedef enum { X2AP_TX2_RELOC_OVERALL_TIMEOUT } x2ap_handover_cancel_cause_t; +typedef enum { + X2AP_RECONF_RESPONSE_SUCCESS, + X2AP_RECONF_RESPONSE_REJECT + /* Extensions may appear below */ + +} x2ap_sgNB_reconf_response_information_t; + typedef struct x2ap_handover_cancel_s { int rnti; x2ap_handover_cancel_cause_t cause; @@ -286,7 +296,7 @@ typedef struct x2ap_senb_addition_req_ack_s { int MeNB_UE_X2_id; - int SeNB_UE_X2_id; + int SgNB_UE_X2_id; uint8_t nb_sCG_e_rabs_tobeadded; @@ -303,4 +313,86 @@ typedef struct x2ap_senb_addition_req_ack_s { } x2ap_senb_addition_req_ack_t; +typedef struct x2ap_ENDC_sgnb_addition_req_s { + int ue_x2_id; + + /* used for RRC->X2AP in source eNB */ + int rnti; + + security_capabilities_t security_capabilities; + + /* SgNB Security Key */ + uint8_t kgnb[32]; + + /*next_hop_chaining_coun */ + long int kgnb_ncc; + + /* UE aggregate maximum bitrate */ + ambr_t ue_ambr; + + uint8_t nb_e_rabs_tobeadded; + + /* list of e_rab to be added by RRC layers */ + e_rab_tobe_added_t e_rabs_tobeadded[S1AP_MAX_E_RAB]; + + /* list of e_rab to be setup by RRC layers */ + e_rab_t e_rab_param[S1AP_MAX_E_RAB]; + + x2ap_lastvisitedcell_info_t lastvisitedcell_info; + + uint8_t rrc_buffer[4096 /* arbitrary, big enough */]; + int rrc_buffer_size; + + int target_assoc_id; + + /*long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; + long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; + long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present;*/ + + +} x2ap_ENDC_sgnb_addition_req_t; + +typedef struct x2ap_ENDC_sgnb_addition_req_ACK_s { + int MeNB_ue_x2_id; + + int SgNB_ue_x2_id; + + /* used for X2AP->RRC in source eNB */ + int rnti; + + uint8_t nb_e_rabs_admitted_tobeadded; + + /* list of e_rab to be added by RRC layers */ + e_rab_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB]; + + /* list of e_rab to be setup by RRC layers */ + e_rab_t e_rab_param[S1AP_MAX_E_RAB]; + + x2ap_lastvisitedcell_info_t lastvisitedcell_info; + + uint8_t rrc_buffer[4096 /* arbitrary, big enough */]; + int rrc_buffer_size; + + int target_assoc_id; + + /*long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; + long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; + long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present;*/ + + +} x2ap_ENDC_sgnb_addition_req_ACK_t; + +typedef struct x2ap_ENDC_reconf_complete_s { + int MeNB_ue_x2_id; + + int SgNB_ue_x2_id; + + x2ap_sgNB_reconf_response_information_t reconf_response; + + uint8_t rrc_buffer[4096 /* arbitrary, big enough */]; + int rrc_buffer_size; + +} x2ap_ENDC_reconf_complete_t; + + #endif /* X2AP_MESSAGES_TYPES_H_ */ diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 02a3faf669..6dcc574746 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -2389,6 +2389,11 @@ int RCconfig_S1( S1AP_REGISTER_ENB_REQ (msg_p).cell_type = CELL_MACRO_ENB; } else if (strcmp(*(ENBParamList.paramarray[k][ENB_CELL_TYPE_IDX].strptr), "CELL_HOME_ENB") == 0) { S1AP_REGISTER_ENB_REQ (msg_p).cell_type = CELL_HOME_ENB; + // Temporary option to be able to parse an eNB configuration file which is treated as gNB from + // the X2AP layer and test the setup of an ENDC X2AP connection. To be removed when we are ready to + // parse an actual gNB configuration file wrt. the X2AP parameters instead. + } else if (strcmp(*(ENBParamList.paramarray[k][ENB_CELL_TYPE_IDX].strptr), "CELL_MACRO_GNB") == 0) { + S1AP_REGISTER_ENB_REQ (msg_p).cell_type = CELL_MACRO_GNB; } else { AssertFatal(0, "Failed to parse eNB configuration file %s, enb %u unknown value \"%s\" for cell_type choice: CELL_MACRO_ENB or CELL_HOME_ENB !\n", @@ -2618,7 +2623,7 @@ int RCconfig_X2(MessageDef *msg_p, uint32_t i) { X2AP_REGISTER_ENB_REQ (msg_p).cell_type = CELL_MACRO_ENB; } else if (strcmp(*(ENBParamList.paramarray[k][ENB_CELL_TYPE_IDX].strptr), "CELL_HOME_ENB") == 0) { X2AP_REGISTER_ENB_REQ (msg_p).cell_type = CELL_HOME_ENB; - } else { + }else { AssertFatal (0, "Failed to parse eNB configuration file %s, enb %u unknown value \"%s\" for cell_type choice: CELL_MACRO_ENB or CELL_HOME_ENB !\n", RC.config_file_name, i, *(ENBParamList.paramarray[k][ENB_CELL_TYPE_IDX].strptr)); diff --git a/openair2/ENB_APP/enb_paramdef.h b/openair2/ENB_APP/enb_paramdef.h index 373dbf9a4e..f91c7056c5 100644 --- a/openair2/ENB_APP/enb_paramdef.h +++ b/openair2/ENB_APP/enb_paramdef.h @@ -94,6 +94,7 @@ typedef enum { #define CONFIG_STRING_RU_END_OF_BURST_DELAY "end_of_burst_delay" #define CONFIG_STRING_RU_OTA_SYNC_ENABLE "ota_sync_enabled" #define CONFIG_STRING_RU_BF_WEIGHTS_LIST "bf_weights" +#define CONFIG_STRING_RU_IF_FREQUENCY "if_freq" #define RU_LOCAL_IF_NAME_IDX 0 #define RU_LOCAL_ADDRESS_IDX 1 @@ -120,6 +121,7 @@ typedef enum { #define RU_END_OF_BURST_DELAY_IDX 22 #define RU_OTA_SYNC_ENABLE_IDX 23 #define RU_BF_WEIGHTS_LIST_IDX 24 +#define RU_IF_FREQUENCY 25 /*-----------------------------------------------------------------------------------------------------------------------------------------*/ /* RU configuration parameters */ @@ -151,6 +153,7 @@ typedef enum { {CONFIG_STRING_RU_END_OF_BURST_DELAY, NULL, 0, uptr:NULL, defuintval:400, TYPE_UINT, 0}, \ {CONFIG_STRING_RU_OTA_SYNC_ENABLE, NULL, 0, strptr:NULL, defstrval:"no", TYPE_STRING, 0}, \ {CONFIG_STRING_RU_BF_WEIGHTS_LIST, NULL, 0, iptr:NULL, defintarrayval:DEFBFW, TYPE_INTARRAY, 0}, \ + {CONFIG_STRING_RU_IF_FREQUENCY, NULL, 0, u64ptr:NULL, defuintval:0, TYPE_UINT64, 0}, \ } /*---------------------------------------------------------------------------------------------------------------------------------------*/ diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h index 687851116c..82873f22b4 100644 --- a/openair2/GNB_APP/RRC_nr_paramsvalues.h +++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h @@ -32,63 +32,358 @@ #ifndef __NR_RRC_PARAMSVALUES__H__ #define __NR_RRC_PARAMSVALUES__H__ + +#include "common/config/config_paramdesc.h" +#include "NR_ServingCellConfigCommon.h" + /* cell configuration section name */ #define GNB_CONFIG_STRING_GNB_LIST "gNBs" -/* component carriers configuration section name */ -#define GNB_CONFIG_STRING_COMPONENT_CARRIERS "component_carriers" +#define GNB_CONFIG_STRING_SSBSUBCARRIEROFFSET "ssb_SubcarrierOffset" +#define GNB_CONFIG_STRING_PDSCHANTENNAPORTS "pdsch_AntennaPorts" +#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON "servingCellConfigCommon" +#define GNB_CONFIG_STRING_PHYSCELLID "physCellId" +#define GNB_CONFIG_STRING_NTIMINGADVANCEOFFSET "n_TimingAdvanceOffset" +#define GNB_CONFIG_STRING_SUBCARRIERSPACING "subcarrierSpacing" +#define GNB_CONFIG_STRING_ABSOLUTEFREQUENCYSSB "absoluteFrequencySSB" +#define GNB_CONFIG_STRING_DLFREQUENCYBAND "dl_frequencyBand" +#define GNB_CONFIG_STRING_DLABSOLUEFREQUENCYPOINTA "dl_absoluteFrequencyPointA" +#define GNB_CONFIG_STRING_DLOFFSETTOCARRIER "dl_offstToCarrier" +#define GNB_CONFIG_STRING_DLSUBCARRIERSPACING "dl_subcarrierSpacing" +#define GNB_CONFIG_STRING_DLCARRIERBANDWIDTH "dl_carrierBandwidth" -#define GNB_CONFIG_STRING_FRAME_TYPE "frame_type" -#define GNB_CONFIG_STRING_DL_PREFIX_TYPE "DL_prefix_type" -#define GNB_CONFIG_STRING_UL_PREFIX_TYPE "UL_prefix_type" -#define GNB_CONFIG_STRING_NR_BAND "nr_band" -#define GNB_CONFIG_STRING_DOWNLINK_FREQUENCY "downlink_frequency" -#define GNB_CONFIG_STRING_UPLINK_FREQUENCY_OFFSET "uplink_frequency_offset" -#define GNB_CONFIG_STRING_NID_CELL "Nid_cell" -#define GNB_CONFIG_STRING_N_RB_DL "N_RB_DL" +#define GNB_CONFIG_STRING_INITIALDLBWPLOCATIONANDBANDWIDTH "initialDLBWPlocationAndBandwidth" +#define GNB_CONFIG_STRING_INITIALDLBWPSUBCARRIERSPACING "initialDLBWPsubcarrierSpacing" +#define GNB_CONFIG_STRING_INITIALDLBWPCYCLICPREFIX "initialDLBWPcyclicPrefix" -#define FRAMETYPE_OKVALUES {"FDD","TDD"} -#define FRAMETYPE_MODVALUES { FDD, TDD} +#define GNB_CONFIG_STRING_INITIALDLBWPCONTROLRESOURCESETZERO "initialDLBWPcontrolResourceSetZero" +#define GNB_CONFIG_STRING_INITIALDLBWPSEARCHSPACEZERO "initialDLBWPsearchSpaceZero" -#define TDDCFG(A) TDD_Config__subframeAssignment_ ## A -#define TDDCONFIG_OKRANGE { TDDCFG(sa0), TDDCFG(sa6)} -#define TDDCFGS(A) TDD_Config__specialSubframePatterns_ ## A -#define TDDCONFIGS_OKRANGE { TDDCFGS(ssp0), TDDCFGS(ssp8)} +#define GNB_CONFIG_STRING_INITIALDLBWPK0_0 "initialDLBWPk0_0" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_0 "initialDLBWPmappingType_0" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0 "initialDLBWPstartSymbolAndLength_0" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_1 "initialDLBWPk0_1" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_1 "initialDLBWPmappingType_1" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_1 "initialDLBWPstartSymbolAndLength_1" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_2 "initialDLBWPk0_2" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_2 "initialDLBWPmappingType_2" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_2 "initialDLBWPstartSymbolAndLength_2" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_3 "initialDLBWPk0_3" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_3 "initialDLBWPmappingType_3" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_3 "initialDLBWPstartSymbolAndLength_3" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_4 "initialDLBWPk0_4" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_4 "initialDLBWPmappingType_4" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_4 "initialDLBWPstartSymbolAndLength_4" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_5 "initialDLBWPk0_5" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_5 "initialDLBWPmappingType_5" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_5 "initialDLBWPstartSymbolAndLength_5" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_6 "initialDLBWPk0_6" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_6 "initialDLBWPmappingType_6" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_6 "initialDLBWPstartSymbolAndLength_6" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_7 "initialDLBWPk0_7" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_7 "initialDLBWPmappingType_7" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_7 "initialDLBWPstartSymbolAndLength_7" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_8 "initialDLBWPk0_8" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_8 "initialDLBWPmappingType_8" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_8 "initialDLBWPstartSymbolAndLength_8" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_9 "initialDLBWPk0_9" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_9 "initialDLBWPmappingType_9" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_9 "initialDLBWPstartSymbolAndLength_9" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_10 "initialDLBWPk0_10" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_10 "initialDLBWPmappingType_10" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_10 "initialDLBWPstartSymbolAndLength_10" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_11 "initialDLBWPk0_11" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_11 "initialDLBWPmappingType_11" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_11 "initialDLBWPstartSymbolAndLength_11" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_12 "initialDLBWPk0_12" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_12 "initialDLBWPmappingType_12" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_12 "initialDLBWPstartSymbolAndLength_12" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_13 "initialDLBWPk0_13" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_13 "initialDLBWPmappingType_13" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_13 "initialDLBWPstartSymbolAndLength_13" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_14 "initialDLBWPk0_14" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_14 "initialDLBWPmappingType_14" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_14 "initialDLBWPstartSymbolAndLength_14" +#define GNB_CONFIG_STRING_INITIALDLBWPK0_15 "initialDLBWPk0_15" +#define GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_15 "initialDLBWPmappingType_15" +#define GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_15 "initialDLBWPstartSymbolAndLength_15" -#define PREFIX_OKVALUES {"NORMAL","EXTENDED"} -#define PREFIX_MODVALUES { NORMAL, EXTENDED} +#define GNB_CONFIG_STRING_ULFREQUENCYBAND "ul_frequencyBand" +#define GNB_CONFIG_STRING_ULABSOLUEFREQUENCYPOINTA "ul_absoluteFrequencyPointA" +#define GNB_CONFIG_STRING_ULOFFSETTOCARRIER "ul_offstToCarrier" +#define GNB_CONFIG_STRING_ULSUBCARRIERSPACING "ul_subcarrierSpacing" +#define GNB_CONFIG_STRING_ULCARRIERBANDWIDTH "ul_carrierBandwidth" -#define PREFIXUL_OKVALUES {"NORMAL","EXTENDED"} -#define PREFIXUL_MODVALUES { NORMAL, EXTENDED} +#define GNB_CONFIG_STRING_INITIALULBWPLOCATIONANDBANDWIDTH "initialULBWPlocationAndBandwidth" +#define GNB_CONFIG_STRING_INITIALULBWPSUBCARRIERSPACING "initialULBWPsubcarrierSpacing" -#define NRBDL_OKVALUES {6,15,25,50,75,100} +#define GNB_CONFIG_STRING_PMAX "pMax" +#define GNB_CONFIG_STRING_PRACHCONFIGURATIONINDEX "prach_ConfigurationIndex" +#define GNB_CONFIG_STRING_PRACHMSG1FDM "prach_msg1_FDM" +#define GNB_CONFIG_STRING_PRACHMSG1FREQUENCYSTART "prach_msg1_FrequencyStart" +#define GNB_CONFIG_STRING_ZEROCORRELATIONZONECONFIG "zeroCorrelationZoneConfig" +#define GNB_CONFIG_STRING_PREAMBLERECEIVEDTARGETPOWER "preambleReceivedTargetPower" +#define GNB_CONFIG_STRING_PREAMBLETRANSMAX "preambleTransMax" +#define GNB_CONFIG_STRING_POWERRAMPINGSTEP "powerRampingStep" +#define GNB_CONFIG_STRING_RARESPONSEWINDOW "ra_ResponseWindow" +#define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSBPR "ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR" +#define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSB "ssb_perRACH_OccasionAndCB_PreamblesPerSSB" +#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer" +#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB" +#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR" +#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex" +#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing" +#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" +#define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList" +#define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble" +#define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant" +#define GNB_CONFIG_STRING_PUCCHGROUPHOPPING "pucchGroupHopping" +#define GNB_CONFIG_STRING_HOPPINGID "hoppingId" +#define GNB_CONFIG_STRING_P0NOMINAL "p0_nominal" +#define GNB_CONFIG_STRING_INITIALULBWPK2_0 "initialULBWPk2_0" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0 "initialULBWPmappingType_0" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0 "initialULBWPstartSymbolAndLength_0" +#define GNB_CONFIG_STRING_INITIALULBWPK2_1 "initialULBWPk2_1" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_1 "initialULBWPmappingType_1" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_1 "initialULBWPstartSymbolAndLength_1" +#define GNB_CONFIG_STRING_INITIALULBWPK2_2 "initialULBWPk2_2" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_2 "initialULBWPmappingType_2" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_2 "initialULBWPstartSymbolAndLength_2" +#define GNB_CONFIG_STRING_INITIALULBWPK2_3 "initialULBWPk2_3" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_3 "initialULBWPmappingType_3" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_3 "initialULBWPstartSymbolAndLength_3" +#define GNB_CONFIG_STRING_INITIALULBWPK2_4 "initialULBWPk2_4" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4 "initialULBWPmappingType_4" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_4 "initialULBWPstartSymbolAndLength_4" +#define GNB_CONFIG_STRING_INITIALULBWPK2_5 "initialULBWPk2_5" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_5 "initialULBWPmappingType_5" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_5 "initialULBWPstartSymbolAndLength_5" +#define GNB_CONFIG_STRING_INITIALULBWPK2_6 "initialULBWPk2_6" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_6 "initialULBWPmappingType_6" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_6 "initialULBWPstartSymbolAndLength_6" +#define GNB_CONFIG_STRING_INITIALULBWPK2_7 "initialULBWPk2_7" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_7 "initialULBWPmappingType_7" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7 "initialULBWPstartSymbolAndLength_7" +#define GNB_CONFIG_STRING_INITIALULBWPK2_8 "initialULBWPk2_8" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_8 "initialULBWPmappingType_8" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_8 "initialULBWPstartSymbolAndLength_8" +#define GNB_CONFIG_STRING_INITIALULBWPK2_9 "initialULBWPk2_9" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_9 "initialULBWPmappingType_9" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_9 "initialULBWPstartSymbolAndLength_9" +#define GNB_CONFIG_STRING_INITIALULBWPK2_10 "initialULBWPk2_10" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_10 "initialULBWPmappingType_10" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_10 "initialULBWPstartSymbolAndLength_10" +#define GNB_CONFIG_STRING_INITIALULBWPK2_11 "initialULBWPk2_11" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_11 "initialULBWPmappingType_11" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_11 "initialULBWPstartSymbolAndLength_11" +#define GNB_CONFIG_STRING_INITIALULBWPK2_12 "initialULBWPk2_12" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_12 "initialULBWPmappingType_12" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_12 "initialULBWPstartSymbolAndLength_12" +#define GNB_CONFIG_STRING_INITIALULBWPK2_13 "initialULBWPk2_13" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_13 "initialULBWPmappingType_13" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_13 "initialULBWPstartSymbolAndLength_13" +#define GNB_CONFIG_STRING_INITIALULBWPK2_14 "initialULBWPk2_14" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14 "initialULBWPmappingType_14" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_14 "initialULBWPstartSymbolAndLength_14" +#define GNB_CONFIG_STRING_INITIALULBWPK2_15 "initialULBWPk2_15" +#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_15 "initialULBWPmappingType_15" +#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_15 "initialULBWPstartSymbolAndLength_15" -#define NRUETIMER_T300_OKVALUES {100,200,300,400,600,1000,1500,2000} -#define NRUETT300(A) NR_UE_TimersAndConstants__t300_ ## A -#define NRUETIMER_T300_MODVALUES { NRUETT300(ms100), NRUETT300(ms200), NRUETT300(ms300), NRUETT300(ms400), NRUETT300(ms600), NRUETT300(ms1000), NRUETT300(ms1500), NRUETT300(ms2000)} -#define NRUETIMER_T301_OKVALUES {100,200,300,400,600,1000,1500,2000} -#define NRUETT301(A) NR_UE_TimersAndConstants__t301_ ## A -#define NRUETIMER_T301_MODVALUES { NRUETT301(ms100), NRUETT301(ms200), NRUETT301(ms300), NRUETT301(ms400), NRUETT301(ms600), NRUETT301(ms1000), NRUETT301(ms1500), NRUETT301(ms2000)} +#define GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR "ssb_PositionsInBurst_PR" +#define GNB_CONFIG_STRING_SSBPOSITIONSINBURST "ssb_PositionsInBurst_Bitmap" +#define GNB_CONFIG_STRING_SSBPERIODICITYSERVINGCELL "ssb_periodicityServingCell" +#define GNB_CONFIG_STRING_DMRSTYPEAPOSITION "dmrs_TypeA_Position" +#define GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING "referenceSubcarrierSpacing" +#define GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY "dl_UL_TransmissionPeriodicity" +#define GNB_CONFIG_STRING_NROFDOWNLINKSLOTS "nrofDownlinkSlots" +#define GNB_CONFIG_STRING_NROFDOWNLINKSYMBOLS "nrofDownlinkSymbols" +#define GNB_CONFIG_STRING_NROFUPLINKSLOTS "nrofUplinkSlots" +#define GNB_CONFIG_STRING_NROFUPLINKSYMBOLS "nrofUplinkSymbols" +#define GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY2 "dl_UL_TransmissionPeriodicity2" +#define GNB_CONFIG_STRING_NROFDOWNLINKSLOTS2 "nrofDownlinkSlots2" +#define GNB_CONFIG_STRING_NROFDOWNLINKSYMBOLS2 "nrofDownlinkSymbols2" +#define GNB_CONFIG_STRING_NROFUPLINKSLOTS2 "nrofUplinkSlots2" +#define GNB_CONFIG_STRING_NROFUPLINKSYMBOLS2 "nrofUplinkSymbols2" +#define GNB_CONFIG_STRING_SSPBCHBLOCKPOWER "ssPBCH_BlockPower" + + +#define CARRIERBANDWIDTH_OKVALUES {11,18,24,25,31,32,38,51,52,65,66,78,79,93,106,107,121,132,133,135,160,162,189,216,217,245,264,270,273} + +/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Serving Cell Config Common configuration parameters */ +/* optname helpstr paramflags XXXptr defXXXval type numelt */ +/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define GNB_CONFIG_PHYSCELLID_IDX 0 +#define GNB_CONFIG_ABSOLUTEFREQUENCYSSB_IDX 5 +#define GNB_CONFIG_DLFREQUENCYBAND_IDX 6 +#define GNB_CONFIG_ABSOLUTEFREQUENCYPOINTA_IDX 7 +#define GNB_CONFIG_DLCARRIERBANDWIDTH_IDX 10 + + +#define SSBPARAMS_DESC {{GNB_CONFIG_STRING_SSBSUBCARRIEROFFSET,NULL,0,iptr:&ssb_SubcarrierOffset,defintval:0,TYPE_INT,0}} +#define PDSCHANTENNAPARAMS_DESC {{GNB_CONFIG_STRING_PDSCHANTENNAPORTS,NULL,0,iptr:&pdsch_AntennaPorts,defintval:1,TYPE_INT,0}} + +#define SCCPARAMS_DESC(scc) { \ +{GNB_CONFIG_STRING_PHYSCELLID,NULL,0,i64ptr:scc->physCellId,defint64val:0,TYPE_INT64,0/*0*/}, \ +{GNB_CONFIG_STRING_NTIMINGADVANCEOFFSET,NULL,0,i64ptr:scc->n_TimingAdvanceOffset,defint64val:NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n0,TYPE_INT64,0/*1*/},\ +{GNB_CONFIG_STRING_SSBPERIODICITYSERVINGCELL,NULL,0,i64ptr:scc->ssb_periodicityServingCell,defint64val:NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms20,TYPE_INT64,0/*2*/},\ +{GNB_CONFIG_STRING_DMRSTYPEAPOSITION,NULL,0,i64ptr:&scc->dmrs_TypeA_Position,defint64val:NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2,TYPE_INT64,0/*3*/},\ +{GNB_CONFIG_STRING_SUBCARRIERSPACING,NULL,0,i64ptr:scc->ssbSubcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0/*4*/},\ +{GNB_CONFIG_STRING_ABSOLUTEFREQUENCYSSB,NULL,0,i64ptr:scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB,defint64val:660960,TYPE_INT64,0/*5*/},\ +{GNB_CONFIG_STRING_DLFREQUENCYBAND,NULL,0,i64ptr:scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0],defint64val:78,TYPE_INT64,0/*6*/},\ +{GNB_CONFIG_STRING_DLABSOLUEFREQUENCYPOINTA,NULL,0,i64ptr:&scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA,defint64val:660000,TYPE_INT64,0/*7*/},\ +{GNB_CONFIG_STRING_DLOFFSETTOCARRIER,NULL,0,i64ptr:&scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier,defint64val:0,TYPE_INT64,0/*8*/},\ +{GNB_CONFIG_STRING_DLSUBCARRIERSPACING,NULL,0,i64ptr:&scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0/*9*/},\ +{GNB_CONFIG_STRING_DLCARRIERBANDWIDTH,NULL,0,i64ptr:&scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,defint64val:217,TYPE_INT64,0 /*10*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPLOCATIONANDBANDWIDTH,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,defint64val:13036,TYPE_INT64,0/*11*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSUBCARRIERSPACING,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0/*12*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPCONTROLRESOURCESETZERO,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero,defint64val:12,TYPE_INT64,0/*13*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSEARCHSPACEZERO,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero,defint64val:0,TYPE_INT64,0/*14*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_0,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->k0,defint64val:-1,TYPE_INT64,0/*15*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:-1,TYPE_INT64,0/*16*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:-1,TYPE_INT64,0/*17*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_1,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->k0,defint64val:-1,TYPE_INT64,0/*18*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*19*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPK0_2,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->k0,defint64val:-1,TYPE_INT64,0/*21*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*22*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*23*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_3,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[3]->k0,defint64val:-1,TYPE_INT64,0/*24*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_3,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[3]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*25*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_3,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*26*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_4,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[4]->k0,defint64val:-1,TYPE_INT64,0/*27*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*28*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_4,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*29*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_5,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[5]->k0,defint64val:-1,TYPE_INT64,0/*30*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_5,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[5]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*31*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_5,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[5]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*32*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_6,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[6]->k0,defint64val:-1,TYPE_INT64,0/*33*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_6,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[6]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*34*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_6,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*35*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_7,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[7]->k0,defint64val:-1,TYPE_INT64,0/*36*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_7,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[7]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*37*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*38*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_8,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[8]->k0,defint64val:-1,TYPE_INT64,0/*39*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_8,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[8]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*40*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_8,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*41*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_9,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[9]->k0,defint64val:-1,TYPE_INT64,0/*42*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_9,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[9]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*43*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_9,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[9]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*44*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_10,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[10]->k0,defint64val:-1,TYPE_INT64,0/*45*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_10,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[10]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*46*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_10,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*47*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_11,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[11]->k0,defint64val:-1,TYPE_INT64,0/*48*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_11,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[11]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*49*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_11,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*50*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPK0_12,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[12]->k0,defint64val:-1,TYPE_INT64,0/*51*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_12,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[12]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*52*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_12,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[12]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*53*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_13,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[13]->k0,defint64val:-1,TYPE_INT64,0/*54*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_13,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[13]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*55*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_13,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*56*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_14,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[14]->k0,defint64val:-1,TYPE_INT64,0/*57*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*58*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_14,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*59*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPK0_15,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[15]->k0,defint64val:-1,TYPE_INT64,0/*60*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_15,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[15]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*61*/},\ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_15,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[15]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*62*/},\ +{GNB_CONFIG_STRING_ULFREQUENCYBAND,NULL,0,i64ptr:scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0],defint64val:-1,TYPE_INT64,0/*63*/},\ +{GNB_CONFIG_STRING_ULABSOLUEFREQUENCYPOINTA,NULL,0,i64ptr:scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA,defint64val:-1,TYPE_INT64,0/*64*/},\ +{GNB_CONFIG_STRING_ULOFFSETTOCARRIER,NULL,0,i64ptr:&scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier,defint64val:0,TYPE_INT64,0/*65*/},\ +{GNB_CONFIG_STRING_ULSUBCARRIERSPACING,NULL,0,i64ptr:&scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0/*66*/},\ +{GNB_CONFIG_STRING_ULCARRIERBANDWIDTH,NULL,0,i64ptr:&scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,defint64val:217,TYPE_INT64,0/*67*/},\ +{GNB_CONFIG_STRING_PMAX,NULL,0,i64ptr:scc->uplinkConfigCommon->frequencyInfoUL->p_Max,defint64val:20,TYPE_INT64,0/*68*/},\ +{GNB_CONFIG_STRING_INITIALULBWPLOCATIONANDBANDWIDTH,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,defint64val:13036,TYPE_INT64,0/*69*/},\ +{GNB_CONFIG_STRING_INITIALULBWPSUBCARRIERSPACING,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0 /*70*/}, \ +{GNB_CONFIG_STRING_PRACHCONFIGURATIONINDEX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex,defint64val:98,TYPE_INT64,0/*71*/},\ +{GNB_CONFIG_STRING_PRACHMSG1FDM,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM,defint64val:NR_RACH_ConfigGeneric__msg1_FDM_one,TYPE_INT64,0/*72*/},\ +{GNB_CONFIG_STRING_PRACHMSG1FREQUENCYSTART,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart,defint64val:0,TYPE_INT64,0/*73*/},\ +{GNB_CONFIG_STRING_ZEROCORRELATIONZONECONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig,defint64val:13,TYPE_INT64,0/*74*/},\ +{GNB_CONFIG_STRING_PREAMBLERECEIVEDTARGETPOWER,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower,defintval:-118,TYPE_INT64,0/*75*/},\ +{GNB_CONFIG_STRING_PREAMBLETRANSMAX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleTransMax,defint64val:NR_RACH_ConfigGeneric__preambleTransMax_n10,TYPE_INT64,0/*76*/},\ +{GNB_CONFIG_STRING_POWERRAMPINGSTEP,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.powerRampingStep,defint64val:NR_RACH_ConfigGeneric__powerRampingStep_dB2,TYPE_INT64,0/*77*/},\ +{GNB_CONFIG_STRING_RARESPONSEWINDOW,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow,defint64val:NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20,TYPE_INT64,0/*78*/},\ +{GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSBPR,NULL,0,uptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present,defuintval:NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_one,TYPE_UINT,0/*79*/},\ +{GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSB,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.one,defint64val:NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n64,TYPE_INT64,0 /*80*/}, \ +{GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ra_ContentionResolutionTimer,defint64val:NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf64,TYPE_INT64,0/*81*/},\ +{GNB_CONFIG_STRING_RSRPTHRESHOLDSSB,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB,defint64val:19,TYPE_INT64,0/*82*/},\ +{GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR,NULL,0,uptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present,defuintval:NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139,TYPE_UINT,0/*83*/},\ +{GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139,defint64val:0,TYPE_INT64,0/*84*/},\ +{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*86*/},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*87*/},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*88*/},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*89*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_2,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_2,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_2,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_3,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_4,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*99*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_5,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_5,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_5,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_6,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_6,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_6,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_7,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*109*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPK2_8,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_9,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[9]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_9,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[9]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_9,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[9]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_10,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*119*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_12,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_12,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_12,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_13,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_14,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*129*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_15,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->k2,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_15,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_15,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_MSG3DELTAPREABMLE, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->msg3_DeltaPreamble,defint64val:1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_P0NOMINALWITHGRANT, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant,defint64val:1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_PUCCHGROUPHOPPING, NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_GroupHopping,defint64val:NR_PUCCH_ConfigCommon__pucch_GroupHopping_neither,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_HOPPINGID, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId,defint64val:40,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_P0NOMINAL, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal,defint64val:1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*139*/}, \ +{GNB_CONFIG_STRING_SSBPOSITIONSINBURST,NULL,0,u64ptr:&ssb_bitmap,defintval:0xff,TYPE_UINT64,0}, \ +{GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity,defint64val:NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p5,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFDOWNLINKSLOTS,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots,defint64val:7,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFDOWNLINKSYMBOLS,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols,defint64val:6,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFUPLINKSLOTS,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots,defint64val:2,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFUPLINKSYMBOLS,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols,defint64val:4,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity,defintval:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFDOWNLINKSLOTS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFDOWNLINKSYMBOLS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSymbols,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFUPLINKSLOTS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSlots,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_NROFUPLINKSYMBOLS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSymbols,defint64val:-1,TYPE_INT64,0},\ +{GNB_CONFIG_STRING_SSPBCHBLOCKPOWER,NULL,0,i64ptr:&scc->ss_PBCH_BlockPower,defint64val:20,TYPE_INT64,0}, \ +{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0/*86*/}} -#define NRUETIMER_T310_OKVALUES {0,50,100,200,500,1000,2000} -#define NRUETT310(A) NR_UE_TimersAndConstants__t310_ ## A -#define NRUETIMER_T310_MODVALUES { NRUETT310(ms0), NRUETT310(ms50), NRUETT310(ms100), NRUETT310(ms200), NRUETT310(ms500), NRUETT310(ms1000), NRUETT310(ms2000)} -#define NRUETIMER_T311_OKVALUES {1000,3000,5000,10000,15000,20000,30000} -#define NRUETT311(A) NR_UE_TimersAndConstants__t311_ ## A -#define NRUETIMER_T311_MODVALUES { NRUETT311(ms1000), NRUETT311(ms3000), NRUETT311(ms5000), NRUETT311(ms10000), NRUETT311(ms15000), NRUETT311(ms20000), NRUETT311(ms30000)} -#define NRUETIMER_T319_OKVALUES {100,200,300,400,600,1000,1500,2000} -#define NRUETT319(A) NR_UE_TimersAndConstants__t319_ ## A -#define NRUETIMER_T319_MODVALUES { NRUETT319(ms100), NRUETT319(ms200), NRUETT319(ms300), NRUETT319(ms400), NRUETT319(ms600), NRUETT319(ms1000), NRUETT319(ms1500), NRUETT319(ms2000} -#define NRUETIMER_N310_OKVALUES {1,2,3,4,6,8,10,20} -#define NRUETN310(A) NR_UE_TimersAndConstants__n310_ ## A -#define NRUETIMER_N310_MODVALUES { NRUETN310(n1), NRUETN310(n2), NRUETN310(n3), NRUETN310(n4), NRUETN310(n6), NRUETN310(n8), NRUETN310(n10), NRUETN310(n20)} -#define NRUETIMER_N311_OKVALUES {1,2,3,4,5,6,8,10} -#define NRUETN311(A) NR_UE_TimersAndConstants__n311_ ## A -#define NRUETIMER_N311_MODVALUES { NRUETN311(n1), NRUETN311(n2), NRUETN311(n3), NRUETN311(n4), NRUETN311(n5), NRUETN311(n6), NRUETN311(n8), NRUETN311(n10)} #endif diff --git a/openair2/GNB_APP/gnb_app.c b/openair2/GNB_APP/gnb_app.c index e6f84a8d13..f11e302771 100644 --- a/openair2/GNB_APP/gnb_app.c +++ b/openair2/GNB_APP/gnb_app.c @@ -37,6 +37,7 @@ #include "common/utils/LOG/log.h" +#include "x2ap_eNB.h" #include "intertask_interface.h" #include "s1ap_eNB.h" #include "sctp_eNB_task.h" @@ -45,13 +46,10 @@ extern unsigned char NB_gNB_INST; - extern RAN_CONTEXT_t RC; #define GNB_REGISTER_RETRY_DELAY 10 - - /*------------------------------------------------------------------------------*/ static void configure_nr_rrc(uint32_t gnb_id) { @@ -106,13 +104,34 @@ static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, } */ +/*------------------------------------------------------------------------------*/ +static uint32_t gNB_app_register_x2(uint32_t gnb_id_start, uint32_t gnb_id_end) { + uint32_t gnb_id; + MessageDef *msg_p; + uint32_t register_gnb_x2_pending = 0; + + for (gnb_id = gnb_id_start; (gnb_id < gnb_id_end) ; gnb_id++) { + { + msg_p = itti_alloc_new_message (TASK_GNB_APP, X2AP_REGISTER_ENB_REQ); + LOG_I(X2AP, "GNB_ID: %d \n", gnb_id); + RCconfig_NR_X2(msg_p, gnb_id); + itti_send_msg_to_task (TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p); + register_gnb_x2_pending++; + } + } + + return register_gnb_x2_pending; +} + /*------------------------------------------------------------------------------*/ void *gNB_app_task(void *args_p) { + uint32_t gnb_nb = RC.nb_nr_inst; uint32_t gnb_id_start = 0; uint32_t gnb_id_end = gnb_id_start + gnb_nb; + uint32_t x2_register_gnb_pending = 0; uint32_t gnb_id; MessageDef *msg_p = NULL; const char *msg_name = NULL; @@ -149,6 +168,11 @@ void *gNB_app_task(void *args_p) configure_nr_rrc(gnb_id); } + if (is_x2ap_enabled() ) { //&& !NODE_IS_DU(RC.rrc[0]->node_type) + LOG_I(X2AP, "X2AP enabled \n"); + x2_register_gnb_pending = gNB_app_register_x2 (gnb_id_start, gnb_id_end); + } + if (EPC_MODE_ENABLED) { /* Try to register each gNB */ //registered_gnb = 0; diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 7061423ba6..9355517072 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -55,6 +55,7 @@ //#include "RRC_config_tools.h" #include "gnb_paramdef.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_asn_constant.h" #include "executables/thread-common.h" #include "NR_SCS-SpecificCarrier.h" #include "NR_TDD-UL-DL-ConfigCommon.h" @@ -74,9 +75,219 @@ extern uint16_t sf_ahead; -extern int config_check_band_frequencies(int ind, int16_t band, uint32_t downlink_frequency, +extern int config_check_band_frequencies(int ind, int16_t band, uint64_t downlink_frequency, int32_t uplink_frequency_offset, uint32_t frame_type); +void prepare_scc(NR_ServingCellConfigCommon_t *scc) { + + NR_FreqBandIndicatorNR_t *dl_frequencyBandList,*ul_frequencyBandList; + struct NR_SCS_SpecificCarrier *dl_scs_SpecificCarrierList,*ul_scs_SpecificCarrierList; + struct NR_PDSCH_TimeDomainResourceAllocation *bwp_dl_timedomainresourceallocation; + struct NR_PUSCH_TimeDomainResourceAllocation *pusch_configcommontimedomainresourceallocation; + // struct NR_RateMatchPattern *ratematchpattern; + // NR_RateMatchPatternId_t *ratematchpatternid; + // NR_TCI_StateId_t *TCI_StateId; + // struct NR_ControlResourceSet *bwp_dl_controlresourceset; + // NR_SearchSpace_t *bwp_dl_searchspace; + + scc->physCellId = CALLOC(1,sizeof(NR_PhysCellId_t)); + scc->downlinkConfigCommon = CALLOC(1,sizeof(struct NR_DownlinkConfigCommon)); + scc->downlinkConfigCommon->frequencyInfoDL = CALLOC(1,sizeof(struct NR_FrequencyInfoDL)); + scc->downlinkConfigCommon->initialDownlinkBWP = CALLOC(1,sizeof(struct NR_BWP_DownlinkCommon)); + scc->uplinkConfigCommon = CALLOC(1,sizeof(struct NR_UplinkConfigCommon)); + scc->uplinkConfigCommon->frequencyInfoUL = CALLOC(1,sizeof(struct NR_FrequencyInfoUL)); + scc->uplinkConfigCommon->initialUplinkBWP = CALLOC(1,sizeof(struct NR_BWP_UplinkCommon)); + //scc->supplementaryUplinkConfig = CALLOC(1,sizeof(struct NR_UplinkConfigCommon)); + scc->ssb_PositionsInBurst = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__ssb_PositionsInBurst)); + scc->ssb_periodicityServingCell = CALLOC(1,sizeof(long)); + // scc->rateMatchPatternToAddModList = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToAddModList)); + // scc->rateMatchPatternToReleaseList = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToReleaseList)); + scc->ssbSubcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t)); + scc->tdd_UL_DL_ConfigurationCommon = CALLOC(1,sizeof(struct NR_TDD_UL_DL_ConfigCommon)); + scc->tdd_UL_DL_ConfigurationCommon->pattern2 = CALLOC(1,sizeof(struct NR_TDD_UL_DL_Pattern)); + + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB = CALLOC(1,sizeof(NR_ARFCN_ValueNR_t)); + + dl_frequencyBandList = CALLOC(1,sizeof(NR_FreqBandIndicatorNR_t)); + dl_scs_SpecificCarrierList = CALLOC(1,sizeof(struct NR_SCS_SpecificCarrier)); + + ASN_SEQUENCE_ADD(&scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list,dl_frequencyBandList); + ASN_SEQUENCE_ADD(&scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list,dl_scs_SpecificCarrierList); + // scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.cyclicPrefix = CALLOC(1,sizeof(long)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon = CALLOC(1,sizeof(struct NR_SetupRelease_PDCCH_ConfigCommon)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->present=NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; + scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PDCCH_ConfigCommon)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero = CALLOC(1,sizeof(long)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero = CALLOC(1,sizeof(long)); + // scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = CALLOC(1,sizeof(struct NR_ControlResourceSet)); + + // scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList = CALLOC(1,sizeof(struct NR_PDCCH_ConfigCommon__commonSearchSpaceList)); + // scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1 = CALLOC(1,sizeof(NR_SearchSpaceId_t)); + // scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation = CALLOC(1,sizeof(NR_SearchSpaceId_t)); + // scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->pagingSearchSpace = CALLOC(1,sizeof(NR_SearchSpaceId_t)); + // scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->ra_SearchSpace = CALLOC(1,sizeof(NR_SearchSpaceId_t)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon = CALLOC(1,sizeof(struct NR_SetupRelease_PDSCH_ConfigCommon)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PDSCH_ConfigCommon)); + scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = CALLOC(1,sizeof(struct NR_PDSCH_TimeDomainResourceAllocationList)); + // + for (int i=0;ik0 = CALLOC(1,sizeof(long)); + *bwp_dl_timedomainresourceallocation->k0=0; + ASN_SEQUENCE_ADD(&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list, + bwp_dl_timedomainresourceallocation); + } + + ul_frequencyBandList = CALLOC(1,sizeof(NR_FreqBandIndicatorNR_t)); + scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList = CALLOC(1,sizeof(struct NR_MultiFrequencyBandListNR)); + ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list,ul_frequencyBandList); + + scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA = CALLOC(1,sizeof(NR_ARFCN_ValueNR_t)); + // scc->uplinkConfigCommon->frequencyInfoUL->additionalSpectrumEmission = CALLOC(1,sizeof(NR_AdditionalSpectrumEmission_t)); + scc->uplinkConfigCommon->frequencyInfoUL->p_Max = CALLOC(1,sizeof(NR_P_Max_t)); + // scc->uplinkConfigCommon->frequencyInfoUL->frequencyShift7p5khz = CALLOC(1,sizeof(long)); + + // scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.cyclicPrefix = CALLOC(1,sizeof(long)); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon = CALLOC(1,sizeof(NR_SetupRelease_RACH_ConfigCommon_t)); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->present = NR_SetupRelease_RACH_ConfigCommon_PR_setup; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_RACH_ConfigCommon)); + // scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles = CALLOC(1,sizeof(long)); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB = CALLOC(1,sizeof(struct NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB)); + // scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->groupBconfigured = CALLOC(1,sizeof(struct NR_RACH_ConfigCommon__groupBconfigured)); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB = CALLOC(1,sizeof(NR_RSRP_Range_t)); + // scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB_SUL = CALLOC(1,sizeof(NR_RSRP_Range_t)); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t)); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = CALLOC(1,sizeof(long)); + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon = CALLOC(1,sizeof(NR_SetupRelease_PUSCH_ConfigCommon_t)); + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->present = NR_SetupRelease_PUSCH_ConfigCommon_PR_setup; + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PUSCH_ConfigCommon)); + + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->groupHoppingEnabledTransformPrecoding = CALLOC(1,sizeof(long)); + + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocationList)); + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->msg3_DeltaPreamble = CALLOC(1,sizeof(long)); + scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant = CALLOC(1,sizeof(long)); + + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon = CALLOC(1,sizeof(struct NR_SetupRelease_PUCCH_ConfigCommon)); + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->present= NR_SetupRelease_PUCCH_ConfigCommon_PR_setup; + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PUCCH_ConfigCommon)); + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal = CALLOC(1,sizeof(long)); + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon = CALLOC(1,sizeof(long)); + scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId = CALLOC(1,sizeof(long)); + + // scc->ssb_PositionsInBurst->choice.shortBitmap.buf = MALLOC(1); + // scc->ssb_PositionsInBurst->choice.mediumBitmap.buf = MALLOC(1); + // scc->ssb_PositionsInBurst->choice.longBitmap.buf = MALLOC(8); + + + ul_scs_SpecificCarrierList = CALLOC(1,sizeof(struct NR_SCS_SpecificCarrier)); + ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list,ul_scs_SpecificCarrierList); + + for (int i=0;ik2 = CALLOC(1,sizeof(long)); + *pusch_configcommontimedomainresourceallocation->k2=0; + ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_configcommontimedomainresourceallocation); + } + //ratematchpattern = CALLOC(1,sizeof(struct NR_RateMatchPattern)); + //ratematchpattern->patternType.choice.bitmaps = CALLOC(1,sizeof(struct NR_RateMatchPattern__patternType__bitmaps)); + //ratematchpattern->patternType.choice.bitmaps->resourceBlocks.buf = MALLOC(35); + //ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.oneSlot.buf = MALLOC(2); + //ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.buf = MALLOC(4); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern = CALLOC(1,sizeof(struct NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern)); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n2.buf = MALLOC(1); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n4.buf = MALLOC(1); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n5.buf = MALLOC(1); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n8.buf = MALLOC(1); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n10.buf = MALLOC(2); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.buf = MALLOC(3); + //ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf = MALLOC(5); + //ratematchpattern->subcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t)); + //ratematchpatternid = CALLOC(1,sizeof(NR_RateMatchPatternId_t)); + +} + + +void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { + + int ssbmaplen = (int)scc->ssb_PositionsInBurst->present; + uint8_t curr_bit; + + AssertFatal(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap || ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap || ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_longBitmap, "illegal ssbmaplen %d\n",ssbmaplen); + + // changing endianicity of ssbmap and filling the ssb_PositionsInBurst buffers + if(ssbmaplen==NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap){ + scc->ssb_PositionsInBurst->choice.shortBitmap.size = 1; + scc->ssb_PositionsInBurst->choice.shortBitmap.bits_unused = 4; + scc->ssb_PositionsInBurst->choice.shortBitmap.buf = CALLOC(1,1); + scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0] = 0; + for (int i=0; i<8; i++) { + if (issb_PositionsInBurst->choice.shortBitmap.bits_unused) + curr_bit = 0; + else + curr_bit = (ssbmap>>(7-i))&0x01; + scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0] |= curr_bit<ssb_PositionsInBurst->choice.mediumBitmap.size = 1; + scc->ssb_PositionsInBurst->choice.mediumBitmap.bits_unused = 0; + scc->ssb_PositionsInBurst->choice.mediumBitmap.buf = CALLOC(1,1); + scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = 0; + for (int i=0; i<8; i++) + scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] |= (((ssbmap>>(7-i))&0x01)<ssb_PositionsInBurst->choice.longBitmap.size = 8; + scc->ssb_PositionsInBurst->choice.longBitmap.bits_unused = 0; + scc->ssb_PositionsInBurst->choice.longBitmap.buf = CALLOC(1,8); + for (int j=0; j<8; j++) { + scc->ssb_PositionsInBurst->choice.longBitmap.buf[7-j] = 0; + curr_bit = (ssbmap>>(j<<3))&(0xff); + for (int i=0; i<8; i++) + scc->ssb_PositionsInBurst->choice.longBitmap.buf[7-j] |= (((curr_bit>>(7-i))&0x01)<uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA==-1) { + free(scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA); + scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA = NULL; + } + + // fix libconfig (asn1c uses long) + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower-=((long)1<<32); + *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant-=((long)1<<32); + *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal-=((long)1<<32); + + // fix DL and UL Allocation lists + + for (int i=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count-1;i>=0;i--) { + printf("Checking element %d : %ld\n",i,*scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0); + if (*scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0>32) { + printf("removing pdsch_TimeDomainAllocationList element %d\n",i); + free(scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0); + asn_sequence_del(&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,i,1); + printf("List size now %d\n",scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count); + } + } + + for (int i=scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count-1;i>=0;i--) { + if (*scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->k2>32) { + free(scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->k2); + asn_sequence_del(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,i,1); + } + } + if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity > 320 ) { + free(scc->tdd_UL_DL_ConfigurationCommon->pattern2); + scc->tdd_UL_DL_ConfigurationCommon->pattern2=NULL; + } + + if ((int)*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing == -1) { + free(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing); + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing=NULL; + } +} + void RCconfig_nr_flexran() { uint16_t i; @@ -85,91 +296,9 @@ void RCconfig_nr_flexran() /* this will possibly truncate the cell id (RRC assumes int32_t). * Both Nid_cell and gnb_id are signed in RRC case, but we use unsigned for * the bitshifting to work properly */ - int32_t Nid_cell = 0; uint16_t Nid_cell_tr = 0; uint32_t gnb_id = 0; - /* - * the only reason for all these variables is, that they are "hard-encoded" - * into the CCPARAMS_DESC macro and we need it for the Nid_cell variable ... - */ - char *frame_type, *DL_prefix_type, *UL_prefix_type, *SIB1_frequencyOffsetSSB, - *DL_SCS_SubcarrierSpacing, *DL_BWP_SubcarrierSpacing, *DL_BWP_prefix_type, - *UL_frequencyShift7p5khz, *UL_SCS_SubcarrierSpacing, *UL_BWP_SubcarrierSpacing, - *UL_BWP_prefix_type, *UL_timeAlignmentTimerCommon, - *ServingCellConfigCommon_n_TimingAdvanceOffset, - *NIA_SubcarrierSpacing, *referenceSubcarrierSpacing, *dl_UL_TransmissionPeriodicity, - *rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice, - *rach_groupBconfigured, *rach_messagePowerOffsetGroupB, - *prach_RootSequenceIndex_choice, *prach_msg1_SubcarrierSpacing, - *restrictedSetConfig, *msg3_transformPrecoding, *prach_msg1_FDM, - *powerRampingStep, *groupHoppingEnabledTransformPrecoding, - *PUSCH_TimeDomainResourceAllocation_mappingType, *pucch_GroupHopping, - *PDSCH_TimeDomainResourceAllocation_mappingType, *RateMatchPattern_patternType, - *symbolsInResourceBlock, *RateMatchPattern_subcarrierSpacing, *RateMatchPattern_mode, - *PDCCH_cce_REG_MappingType, *PDCCH_precoderGranularity, - *tci_PresentInDCI, *SearchSpace_monitoringSlotPeriodicityAndOffset_choice, - *SearchSpace_searchSpaceType, *ue_Specific__dci_Formats, - *RateMatchPatternLTE_CRS_subframeAllocation_choice; - - uint64_t downlink_frequency, ServingCellConfigCommon_ssb_PositionsInBurst_PR; - - int32_t nr_band, uplink_frequency_offset, N_RB_DL, nb_antenna_ports, - MIB_subCarrierSpacingCommon, MIB_ssb_SubcarrierOffset, MIB_dmrs_TypeA_Position, - pdcch_ConfigSIB1, SIB1_ssb_PeriodicityServingCell, SIB1_ss_PBCH_BlockPower, - absoluteFrequencySSB, DL_FreqBandIndicatorNR, - DL_absoluteFrequencyPointA, DL_offsetToCarrier, - DL_carrierBandwidth, DL_locationAndBandwidth, UL_FreqBandIndicatorNR, - UL_absoluteFrequencyPointA, UL_additionalSpectrumEmission, UL_p_Max, - UL_offsetToCarrier, UL_carrierBandwidth, - UL_locationAndBandwidth, ServingCellConfigCommon_ssb_periodicityServingCell, - ServingCellConfigCommon_dmrs_TypeA_Position, ServingCellConfigCommon_ss_PBCH_BlockPower, - nrofDownlinkSlots, nrofDownlinkSymbols, nrofUplinkSlots, nrofUplinkSymbols, - rach_totalNumberOfRA_Preambles, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight, - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen, - rach_ra_Msg3SizeGroupA, rach_numberOfRA_PreamblesGroupA, rach_ra_ContentionResolutionTimer, - rsrp_ThresholdSSB, rsrp_ThresholdSSB_SUL, prach_RootSequenceIndex_l839, - prach_RootSequenceIndex_l139, prach_ConfigurationIndex, prach_msg1_FrequencyStart, - zeroCorrelationZoneConfig, preambleReceivedTargetPower, preambleTransMax, - ra_ResponseWindow, msg3_DeltaPreamble, p0_NominalWithGrant, - PUSCH_TimeDomainResourceAllocation_k2, - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength, - pucch_ResourceCommon, hoppingId, p0_nominal, PDSCH_TimeDomainResourceAllocation_k0, - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength, - rateMatchPatternId, periodicityAndPattern, RateMatchPattern_controlResourceSet, - controlResourceSetZero, searchSpaceZero, - searchSpaceSIB1, searchSpaceOtherSystemInformation, pagingSearchSpace, - ra_SearchSpace, PDCCH_common_controlResourceSetId, - PDCCH_common_ControlResourceSet_duration, PDCCH_reg_BundleSize, PDCCH_interleaverSize, - PDCCH_shiftIndex, PDCCH_TCI_StateId, PDCCH_DMRS_ScramblingID, - SearchSpaceId, commonSearchSpaces_controlResourceSetId, - SearchSpace_monitoringSlotPeriodicityAndOffset_value, - SearchSpace_duration, - SearchSpace_nrofCandidates_aggregationLevel1, - SearchSpace_nrofCandidates_aggregationLevel2, - SearchSpace_nrofCandidates_aggregationLevel4, - SearchSpace_nrofCandidates_aggregationLevel8, - SearchSpace_nrofCandidates_aggregationLevel16, - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1, - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2, - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4, - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8, - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16, - Common_dci_Format2_3_monitoringPeriodicity, - Common_dci_Format2_3_nrofPDCCH_Candidates, - RateMatchPatternLTE_CRS_carrierFreqDL, - RateMatchPatternLTE_CRS_carrierBandwidthDL, - RateMatchPatternLTE_CRS_nrofCRS_Ports, - RateMatchPatternLTE_CRS_v_Shift, - RateMatchPatternLTE_CRS_radioframeAllocationPeriod, - RateMatchPatternLTE_CRS_radioframeAllocationOffset - ; /* get number of gNBs */ paramdef_t GNBSParams[] = GNBSPARAMS_DESC; @@ -180,15 +309,6 @@ void RCconfig_nr_flexran() paramdef_t GNBParams[] = GNBPARAMS_DESC; paramlist_def_t GNBParamList = {GNB_CONFIG_STRING_GNB_LIST, NULL, 0}; - /* for Nid_cell */ - checkedparam_t config_check_CCparams[] = NRCCPARAMS_CHECK; - paramdef_t CCsParams[] = NRCCPARAMS_DESC; - paramlist_def_t CCsParamList = {GNB_CONFIG_STRING_COMPONENT_CARRIERS, NULL, 0}; - /* map parameter checking array instances to parameter definition array instances */ - for (int I = 0; I < (sizeof(CCsParams) / sizeof(paramdef_t)); I++) { - CCsParams[I].chkPptr = &(config_check_CCparams[I]); - } - paramdef_t flexranParams[] = FLEXRANPARAMS_DESC; config_get(flexranParams, sizeof(flexranParams)/sizeof(paramdef_t), CONFIG_STRING_NETWORK_CONTROLLER_CONFIG); @@ -231,12 +351,6 @@ void RCconfig_nr_flexran() /* cell ID */ sprintf(aprefix, "%s.[%i]", GNB_CONFIG_STRING_GNB_LIST, i); - config_getlist(&CCsParamList, NULL, 0, aprefix); - if (CCsParamList.numelt > 0) { - sprintf(aprefix, "%s.[%i].%s.[%i]", GNB_CONFIG_STRING_GNB_LIST, i, GNB_CONFIG_STRING_COMPONENT_CARRIERS, 0); - config_get(CCsParams, sizeof(CCsParams)/sizeof(paramdef_t), aprefix); - Nid_cell_tr = (uint16_t) Nid_cell; - } RC.flexran[i]->mod_id = i; RC.flexran[i]->agent_id = (((uint64_t)i) << 48) | (((uint64_t)gnb_id) << 16) | ((uint64_t)Nid_cell_tr); @@ -259,16 +373,15 @@ void RCconfig_nr_flexran() } void RCconfig_NR_L1(void) { - int i,j; + int j; paramdef_t L1_Params[] = L1PARAMS_DESC; paramlist_def_t L1_ParamList = {CONFIG_STRING_L1_LIST,NULL,0}; if (RC.gNB == NULL) { - RC.gNB = (PHY_VARS_gNB ***)malloc((1+NUMBER_OF_gNB_MAX)*sizeof(PHY_VARS_gNB**)); + RC.gNB = (PHY_VARS_gNB **)malloc((1+NUMBER_OF_gNB_MAX)*sizeof(PHY_VARS_gNB*)); LOG_I(NR_PHY,"RC.gNB = %p\n",RC.gNB); - memset(RC.gNB,0,(1+NUMBER_OF_gNB_MAX)*sizeof(PHY_VARS_gNB**)); - RC.nb_nr_L1_CC = malloc((1+RC.nb_nr_L1_inst)*sizeof(int)); + memset(RC.gNB,0,(1+NUMBER_OF_gNB_MAX)*sizeof(PHY_VARS_gNB*)); } config_getlist( &L1_ParamList,L1_Params,sizeof(L1_Params)/sizeof(paramdef_t), NULL); @@ -276,35 +389,25 @@ void RCconfig_NR_L1(void) { if (L1_ParamList.numelt > 0) { for (j = 0; j < RC.nb_nr_L1_inst; j++) { - RC.nb_nr_L1_CC[j] = *(L1_ParamList.paramarray[j][L1_CC_IDX].uptr); if (RC.gNB[j] == NULL) { - RC.gNB[j] = (PHY_VARS_gNB **)malloc((1+MAX_NUM_CCs)*sizeof(PHY_VARS_gNB*)); + RC.gNB[j] = (PHY_VARS_gNB *)malloc(sizeof(PHY_VARS_gNB)); LOG_I(NR_PHY,"RC.gNB[%d] = %p\n",j,RC.gNB[j]); - memset(RC.gNB[j],0,(1+MAX_NUM_CCs)*sizeof(PHY_VARS_gNB*)); - } - - for (i=0;iMod_id = j; - RC.gNB[j][i]->CC_id = i; - } + memset(RC.gNB[j],0,sizeof(PHY_VARS_gNB)); + RC.gNB[j]->Mod_id = j; } if(strcmp(*(L1_ParamList.paramarray[j][L1_TRANSPORT_N_PREFERENCE_IDX].strptr), "local_mac") == 0) { //sf_ahead = 2; // Need 4 subframe gap between RX and TX }else if (strcmp(*(L1_ParamList.paramarray[j][L1_TRANSPORT_N_PREFERENCE_IDX].strptr), "nfapi") == 0) { - RC.gNB[j][0]->eth_params_n.local_if_name = strdup(*(L1_ParamList.paramarray[j][L1_LOCAL_N_IF_NAME_IDX].strptr)); - RC.gNB[j][0]->eth_params_n.my_addr = strdup(*(L1_ParamList.paramarray[j][L1_LOCAL_N_ADDRESS_IDX].strptr)); - RC.gNB[j][0]->eth_params_n.remote_addr = strdup(*(L1_ParamList.paramarray[j][L1_REMOTE_N_ADDRESS_IDX].strptr)); - RC.gNB[j][0]->eth_params_n.my_portc = *(L1_ParamList.paramarray[j][L1_LOCAL_N_PORTC_IDX].iptr); - RC.gNB[j][0]->eth_params_n.remote_portc = *(L1_ParamList.paramarray[j][L1_REMOTE_N_PORTC_IDX].iptr); - RC.gNB[j][0]->eth_params_n.my_portd = *(L1_ParamList.paramarray[j][L1_LOCAL_N_PORTD_IDX].iptr); - RC.gNB[j][0]->eth_params_n.remote_portd = *(L1_ParamList.paramarray[j][L1_REMOTE_N_PORTD_IDX].iptr); - RC.gNB[j][0]->eth_params_n.transp_preference = ETH_UDP_MODE; + RC.gNB[j]->eth_params_n.local_if_name = strdup(*(L1_ParamList.paramarray[j][L1_LOCAL_N_IF_NAME_IDX].strptr)); + RC.gNB[j]->eth_params_n.my_addr = strdup(*(L1_ParamList.paramarray[j][L1_LOCAL_N_ADDRESS_IDX].strptr)); + RC.gNB[j]->eth_params_n.remote_addr = strdup(*(L1_ParamList.paramarray[j][L1_REMOTE_N_ADDRESS_IDX].strptr)); + RC.gNB[j]->eth_params_n.my_portc = *(L1_ParamList.paramarray[j][L1_LOCAL_N_PORTC_IDX].iptr); + RC.gNB[j]->eth_params_n.remote_portc = *(L1_ParamList.paramarray[j][L1_REMOTE_N_PORTC_IDX].iptr); + RC.gNB[j]->eth_params_n.my_portd = *(L1_ParamList.paramarray[j][L1_LOCAL_N_PORTD_IDX].iptr); + RC.gNB[j]->eth_params_n.remote_portd = *(L1_ParamList.paramarray[j][L1_REMOTE_N_PORTD_IDX].iptr); + RC.gNB[j]->eth_params_n.transp_preference = ETH_UDP_MODE; //sf_ahead = 2; // Cannot cope with 4 subframes betweem RX and TX - set it to 2 @@ -322,7 +425,7 @@ void RCconfig_NR_L1(void) { mac_top_init_gNB(); - configure_nfapi_pnf(RC.gNB[j][0]->eth_params_n.remote_addr, RC.gNB[j][0]->eth_params_n.remote_portc, RC.gNB[j][0]->eth_params_n.my_addr, RC.gNB[j][0]->eth_params_n.my_portd, RC.gNB[j][0]->eth_params_n .remote_portd); + configure_nfapi_pnf(RC.gNB[j]->eth_params_n.remote_addr, RC.gNB[j]->eth_params_n.remote_portc, RC.gNB[j]->eth_params_n.my_addr, RC.gNB[j]->eth_params_n.my_portd, RC.gNB[j]->eth_params_n .remote_portd); }else { // other midhaul } }// for (j = 0; j < RC.nb_nr_L1_inst; j++) @@ -335,26 +438,13 @@ void RCconfig_NR_L1(void) { j = 0; - RC.nb_nr_L1_CC = malloc((1+RC.nb_nr_L1_inst)*sizeof(int)); // DJP - 1 lot then??? - - RC.nb_nr_L1_CC[j]=1; // DJP - hmmm if (RC.gNB[j] == NULL) { - RC.gNB[j] = (PHY_VARS_gNB **)malloc((1+MAX_NUM_CCs)*sizeof(PHY_VARS_gNB**)); + RC.gNB[j] = (PHY_VARS_gNB *)malloc(sizeof(PHY_VARS_gNB)); + memset((void*)RC.gNB[j],0,sizeof(PHY_VARS_gNB)); LOG_I(PHY,"RC.gNB[%d] = %p\n",j,RC.gNB[j]); - memset(RC.gNB[j],0,(1+MAX_NUM_CCs)*sizeof(PHY_VARS_gNB***)); - } - - for (i=0;iMod_id = j; - RC.gNB[j][i]->CC_id = i; - } - } // END for (i=0;iMod_id = j; + } } } @@ -421,218 +511,28 @@ void RCconfig_nr_macrlc() { void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) { int num_gnbs = 0; - int num_component_carriers = 0; - int j,k = 0; + char aprefix[MAX_OPTNAME_SIZE*2 + 8]; int32_t gnb_id = 0; - - int nb_cc = 0; - char* frame_type = NULL; - char* DL_prefix_type = NULL; - char* UL_prefix_type = NULL; - - int32_t nr_band = 0; - uint64_t downlink_frequency = 0; - int32_t uplink_frequency_offset = 0; - int32_t Nid_cell = 0; - int32_t N_RB_DL = 0; - int32_t nb_antenna_ports = 0; - - ///NR - //MIB - int32_t MIB_subCarrierSpacingCommon = 0; - int32_t MIB_ssb_SubcarrierOffset = 0; - int32_t MIB_dmrs_TypeA_Position = 0; - int32_t pdcch_ConfigSIB1 = 0; - - //SIB1 - char* SIB1_frequencyOffsetSSB = NULL; - int32_t SIB1_ssb_PeriodicityServingCell = 0; - int32_t SIB1_ss_PBCH_BlockPower = 0; - //DownlinkConfigCommon - //NR FrequencyInfoDL - int32_t absoluteFrequencySSB = 0; - int32_t DL_FreqBandIndicatorNR = 0; - int32_t DL_absoluteFrequencyPointA = 0; - - //NR DL SCS-SpecificCarrier - int32_t DL_offsetToCarrier = 0; - char* DL_SCS_SubcarrierSpacing = 0; - int32_t DL_carrierBandwidth = 0; - - // NR BWP-DownlinkCommon - int32_t DL_locationAndBandwidth = 0; - char* DL_BWP_SubcarrierSpacing = 0; - char* DL_BWP_prefix_type = NULL; - - //NR FrequencyInfoUL - int32_t UL_FreqBandIndicatorNR = 0; - int32_t UL_absoluteFrequencyPointA = 0; - int32_t UL_additionalSpectrumEmission = 0; - int32_t UL_p_Max = 0; - char* UL_frequencyShift7p5khz = 0; - - //NR UL SCS-SpecificCarrier - int32_t UL_offsetToCarrier = 0; - char* UL_SCS_SubcarrierSpacing = 0; - int32_t UL_carrierBandwidth = 0; - - // NR BWP-UplinkCommon - int32_t UL_locationAndBandwidth = 0; - char* UL_BWP_SubcarrierSpacing = 0; - char* UL_BWP_prefix_type = NULL; - char* UL_timeAlignmentTimerCommon = 0; - - char* ServingCellConfigCommon_n_TimingAdvanceOffset = 0; - uint64_t ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0; - int32_t ServingCellConfigCommon_ssb_periodicityServingCell = 0; - int32_t ServingCellConfigCommon_dmrs_TypeA_Position = 0; - char* NIA_SubcarrierSpacing = 0; - int32_t ServingCellConfigCommon_ss_PBCH_BlockPower = 0; - - //NR TDD-UL-DL-ConfigCommon - char* referenceSubcarrierSpacing = 0; - char* dl_UL_TransmissionPeriodicity = 0; - int32_t nrofDownlinkSlots = 0; - int32_t nrofDownlinkSymbols = 0; - int32_t nrofUplinkSlots = 0; - int32_t nrofUplinkSymbols = 0; - - //NR RACH-ConfigCommon - int32_t rach_totalNumberOfRA_Preambles = 0; - char* rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 0; - int32_t rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 0; - char* rach_groupBconfigured = NULL; - int32_t rach_ra_Msg3SizeGroupA = 0; - char* rach_messagePowerOffsetGroupB = NULL; - int32_t rach_numberOfRA_PreamblesGroupA = 0; - int32_t rach_ra_ContentionResolutionTimer = 0; - int32_t rsrp_ThresholdSSB = 0; - int32_t rsrp_ThresholdSSB_SUL = 0; - char* prach_RootSequenceIndex_choice = NULL; - int32_t prach_RootSequenceIndex_l839 = 0; - int32_t prach_RootSequenceIndex_l139 = 0; - char* prach_msg1_SubcarrierSpacing = NULL; - char* restrictedSetConfig = NULL; - char* msg3_transformPrecoding = NULL; - //ssb-perRACH-OccasionAndCB-PreamblesPerSSB not sure - - //NR RACH-ConfigGeneric - int32_t prach_ConfigurationIndex = 0; - char* prach_msg1_FDM = NULL; - int32_t prach_msg1_FrequencyStart = 0; - int32_t zeroCorrelationZoneConfig = 0; - int32_t preambleReceivedTargetPower = 0; - int32_t preambleTransMax = 0; - char* powerRampingStep = NULL; - int32_t ra_ResponseWindow = 0; - - //PUSCH-ConfigCommon - char* groupHoppingEnabledTransformPrecoding = NULL; - int32_t msg3_DeltaPreamble = 0; - int32_t p0_NominalWithGrant = 0; - - ///PUSCH-TimeDomainResourceAllocation - int32_t PUSCH_TimeDomainResourceAllocation_k2 = 0; - char* PUSCH_TimeDomainResourceAllocation_mappingType = NULL; - int32_t PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - - //PUCCH-ConfigCommon - int32_t pucch_ResourceCommon = 0; - char* pucch_GroupHopping = NULL; - int32_t hoppingId = 0; - int32_t p0_nominal = 0; - - //PDSCH-ConfigCOmmon - //PDSCH-TimeDomainResourceAllocation - int32_t PDSCH_TimeDomainResourceAllocation_k0 = 0; - char* PDSCH_TimeDomainResourceAllocation_mappingType = NULL; - int32_t PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - - //RateMatchPattern is used to configure one rate matching pattern for PDSCH - int32_t rateMatchPatternId = 0; - char* RateMatchPattern_patternType = NULL; - char* symbolsInResourceBlock = NULL; - int32_t periodicityAndPattern = 0; - int32_t RateMatchPattern_controlResourceSet = 0; - char* RateMatchPattern_subcarrierSpacing = NULL; - char* RateMatchPattern_mode = NULL; - - //PDCCH-ConfigCommon - int32_t controlResourceSetZero = 0; - int32_t searchSpaceZero = 0; - int32_t searchSpaceSIB1 = 0; - int32_t searchSpaceOtherSystemInformation = 0; - int32_t pagingSearchSpace = 0; - int32_t ra_SearchSpace = 0; - - //NR PDCCH-ConfigCommon commonControlResourcesSets - int32_t PDCCH_common_controlResourceSetId = 0; - int32_t PDCCH_common_ControlResourceSet_duration = 0; - char* PDCCH_cce_REG_MappingType = NULL; - int32_t PDCCH_reg_BundleSize = 0; - int32_t PDCCH_interleaverSize = 0; - int32_t PDCCH_shiftIndex = 0; - char* PDCCH_precoderGranularity = NULL; - int32_t PDCCH_TCI_StateId = 0; - char* tci_PresentInDCI = NULL; - int32_t PDCCH_DMRS_ScramblingID = 0; - - //NR PDCCH-ConfigCommon commonSearchSpaces - int32_t SearchSpaceId = 0; - int32_t commonSearchSpaces_controlResourceSetId = 0; - char* SearchSpace_monitoringSlotPeriodicityAndOffset_choice = NULL; - int32_t SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - int32_t SearchSpace_duration = 0; - int32_t SearchSpace_nrofCandidates_aggregationLevel1 = 0; - int32_t SearchSpace_nrofCandidates_aggregationLevel2 = 0; - int32_t SearchSpace_nrofCandidates_aggregationLevel4 = 0; - int32_t SearchSpace_nrofCandidates_aggregationLevel8 = 0; - int32_t SearchSpace_nrofCandidates_aggregationLevel16 = 0; - char* SearchSpace_searchSpaceType = NULL; - int32_t Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 0; - int32_t Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 0; - int32_t Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 0; - int32_t Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 0; - int32_t Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 0; - int32_t Common_dci_Format2_3_monitoringPeriodicity = 0; - int32_t Common_dci_Format2_3_nrofPDCCH_Candidates = 0; - char* ue_Specific__dci_Formats = NULL; - //NR RateMatchPatternLTE-CRS - int32_t RateMatchPatternLTE_CRS_carrierFreqDL = 0; - int32_t RateMatchPatternLTE_CRS_carrierBandwidthDL = 0; - int32_t RateMatchPatternLTE_CRS_nrofCRS_Ports = 0; - int32_t RateMatchPatternLTE_CRS_v_Shift = 0; - int32_t RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 0; - int32_t RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - char* RateMatchPatternLTE_CRS_subframeAllocation_choice = NULL; - - - /*int32_t srb1_timer_poll_retransmit = 0; - int32_t srb1_timer_reordering = 0; - int32_t srb1_timer_status_prohibit = 0; - int32_t srb1_poll_pdu = 0; - int32_t srb1_poll_byte = 0; - int32_t srb1_max_retx_threshold = 0;*/ - - //int32_t my_int; - + int k; paramdef_t GNBSParams[] = GNBSPARAMS_DESC; ////////// Identification parameters paramdef_t GNBParams[] = GNBPARAMS_DESC; paramlist_def_t GNBParamList = {GNB_CONFIG_STRING_GNB_LIST,NULL,0}; - ////////// Physical parameters - //checkedparam_t config_check_CCparams[] = NRCCPARAMS_CHECK; - paramdef_t CCsParams[] = NRCCPARAMS_DESC; - paramlist_def_t CCsParamList = {GNB_CONFIG_STRING_COMPONENT_CARRIERS,NULL,0}; - - //paramdef_t SRB1Params[] = GNBSRB1PARAMS_DESC; + + NR_ServingCellConfigCommon_t *scc = calloc(1,sizeof(NR_ServingCellConfigCommon_t)); + int ssb_SubcarrierOffset = 31; + int pdsch_AntennaPorts = 1; + uint64_t ssb_bitmap=0xff; + memset((void*)scc,0,sizeof(NR_ServingCellConfigCommon_t)); + prepare_scc(scc); + paramdef_t SCCsParams[] = SCCPARAMS_DESC(scc); + paramlist_def_t SCCsParamList = {GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON, NULL, 0}; + paramdef_t SSBsParams[] = SSBPARAMS_DESC; + paramlist_def_t SSBsParamList = {GNB_CONFIG_STRING_SSBSUBCARRIEROFFSET, NULL, 0}; + paramdef_t PDSCHANTENNAParams[] = PDSCHANTENNAPARAMS_DESC; + paramlist_def_t PDSCHANTENNAParamList = {GNB_CONFIG_STRING_PDSCHANTENNAPORTS, NULL, 0}; + ////////// Physical parameters + /* get global parameters, defined outside any section in the config file */ @@ -659,9 +559,12 @@ void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) { */ if (num_gnbs>0) { + + + // Output a list of all gNBs. ////////// Identification parameters config_getlist( &GNBParamList,GNBParams,sizeof(GNBParams)/sizeof(paramdef_t),NULL); - + if (GNBParamList.paramarray[i][GNB_GNB_ID_IDX].uptr == NULL) { // Calculate a default gNB ID if (EPC_MODE_ENABLED) { @@ -672,13 +575,33 @@ void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) { gnb_id = i; } } else { - gnb_id = *(GNBParamList.paramarray[i][GNB_GNB_ID_IDX].uptr); + gnb_id = *(GNBParamList.paramarray[i][GNB_GNB_ID_IDX].uptr); } - printf("NRRRC %u: Southbound Transport %s\n",i,*(GNBParamList.paramarray[i][GNB_TRANSPORT_S_PREFERENCE_IDX].strptr)); + sprintf(aprefix, "%s.[%i]", GNB_CONFIG_STRING_GNB_LIST, 0); + config_getlist(&SSBsParamList, NULL, 0, aprefix); + if (SSBsParamList.numelt > 0) config_get(SSBsParams,sizeof(SSBsParams)/sizeof(paramdef_t),aprefix); + config_getlist(&PDSCHANTENNAParamList, NULL, 0, aprefix); + if (PDSCHANTENNAParamList.numelt > 0) config_get(PDSCHANTENNAParams,sizeof(PDSCHANTENNAParams)/sizeof(paramdef_t),aprefix); + + + config_getlist(&SCCsParamList, NULL, 0, aprefix); + if (SCCsParamList.numelt > 0) { + sprintf(aprefix, "%s.[%i].%s.[%i]", GNB_CONFIG_STRING_GNB_LIST,0,GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON, 0); + config_get( SCCsParams,sizeof(SCCsParams)/sizeof(paramdef_t),aprefix); + LOG_I(RRC,"Read in ServingCellConfigCommon (PhysCellId %d, ABSFREQSSB %d, DLBand %d, ABSFREQPOINTA %d, DLBW %d,RACH_TargetReceivedPower %d\n", + (int)*scc->physCellId, + (int)*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB, + (int)*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0], + (int)scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA, + (int)scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth, + (int)scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower); + fix_scc(scc,ssb_bitmap); + } + printf("NRRRC %d: Southbound Transport %s\n",i,*(GNBParamList.paramarray[i][GNB_TRANSPORT_S_PREFERENCE_IDX].strptr)); if (strcmp(*(GNBParamList.paramarray[i][GNB_TRANSPORT_S_PREFERENCE_IDX].strptr), "local_mac") == 0) { - + } else if (strcmp(*(GNBParamList.paramarray[i][GNB_TRANSPORT_S_PREFERENCE_IDX].strptr), "cudu") == 0) { rrc->eth_params_s.local_if_name = strdup(*(GNBParamList.paramarray[i][GNB_LOCAL_S_IF_NAME_IDX].strptr)); rrc->eth_params_s.my_addr = strdup(*(GNBParamList.paramarray[i][GNB_LOCAL_S_ADDRESS_IDX].strptr)); @@ -690,16 +613,18 @@ void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) { rrc->eth_params_s.transp_preference = ETH_UDP_MODE; } else { // other midhaul } - + // search if in active list - + for (k=0; k 0) { - - char ccspath[MAX_OPTNAME_SIZE*2 + 16]; - - for (j = 0; j < CCsParamList.numelt ;j++) { - - sprintf(ccspath,"%s.%s.[%i]",gnbpath,GNB_CONFIG_STRING_COMPONENT_CARRIERS,j); - config_get( CCsParams,sizeof(CCsParams)/sizeof(paramdef_t),ccspath); - - nb_cc++; - - // NRRRC_CONFIGURATION_REQ (msg_p).tdd_config[j] = tdd_config; - // AssertFatal (tdd_config <= TDD_Config__subframeAssignment_sa6, - // "Failed to parse gNB configuration file %s, gnb %d illegal tdd_config %d (should be 0-%d)!", - // RC.config_file_name, i, tdd_config, TDD_Config__subframeAssignment_sa6); - - // NRRRC_CONFIGURATION_REQ (msg_p).tdd_config_s[j] = tdd_config_s; - // AssertFatal (tdd_config_s <= TDD_Config__specialSubframePatterns_ssp8, - // "Failed to parse gNB configuration file %s, gnb %d illegal tdd_config_s %d (should be 0-%d)!", - // RC.config_file_name, i, tdd_config_s, TDD_Config__specialSubframePatterns_ssp8); - - if (!DL_prefix_type){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d define %s: NORMAL,EXTENDED!\n", - RC.config_file_name, i, GNB_CONFIG_STRING_DL_PREFIX_TYPE); - }else if (strcmp(DL_prefix_type, "NORMAL") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_prefix_type[j] = NORMAL; - }else if (strcmp(DL_prefix_type, "EXTENDED") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_prefix_type[j] = EXTENDED; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for DL_prefix_type choice: NORMAL or EXTENDED !\n", - RC.config_file_name, i, DL_prefix_type); - } - - if (!UL_prefix_type){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d define %s: NORMAL,EXTENDED!\n", - RC.config_file_name, i, GNB_CONFIG_STRING_UL_PREFIX_TYPE); - }else if (strcmp(UL_prefix_type, "NORMAL") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_prefix_type[j] = NORMAL; - }else if (strcmp(UL_prefix_type, "EXTENDED") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_prefix_type[j] = EXTENDED; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for UL_prefix_type choice: NORMAL or EXTENDED !\n", - RC.config_file_name, i, UL_prefix_type); - } - - NRRRC_CONFIGURATION_REQ (msg_p).nr_band[j] = nr_band; - NRRRC_CONFIGURATION_REQ (msg_p).downlink_frequency[j] = (uint64_t) downlink_frequency; - NRRRC_CONFIGURATION_REQ (msg_p).uplink_frequency_offset[j] = (unsigned int) uplink_frequency_offset; - NRRRC_CONFIGURATION_REQ (msg_p).Nid_cell[j]= Nid_cell; - - if (Nid_cell>503) { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Nid_cell choice: 0...503 !\n", - RC.config_file_name, i, Nid_cell); - } - - NRRRC_CONFIGURATION_REQ (msg_p).N_RB_DL[j]= N_RB_DL; - //if(N_RB_DL == 217) sf_ahead = 2; - //else if(N_RB_DL == 106) sf_ahead = 4; - if ((N_RB_DL != 273) && (N_RB_DL != 217) && (N_RB_DL != 106)) - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for N_RB_DL choice: 106, 217 !\n", RC.config_file_name, i, N_RB_DL); - - /* - if ((N_RB_DL!=6) && (N_RB_DL!=15) && (N_RB_DL!=25) && (N_RB_DL!=50) && (N_RB_DL!=75) && (N_RB_DL!=100)) { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for N_RB_DL choice: 6,15,25,50,75,100 !\n", - RC.config_file_name, i, N_RB_DL); - } - */ - - if (strcmp(frame_type, "FDD") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).frame_type[j] = FDD; - }else if (strcmp(frame_type, "TDD") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).frame_type[j] = TDD; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for frame_type choice: FDD or TDD !\n", - RC.config_file_name, i, frame_type); - } - - if (!DL_prefix_type){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d define %s: NORMAL,EXTENDED!\n", - RC.config_file_name, i, GNB_CONFIG_STRING_DL_PREFIX_TYPE); - }else if (strcmp(DL_prefix_type, "NORMAL") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_prefix_type[j] = NORMAL; - }else if (strcmp(DL_prefix_type, "EXTENDED") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_prefix_type[j] = EXTENDED; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for DL_prefix_type choice: NORMAL or EXTENDED !\n", - RC.config_file_name, i, DL_prefix_type); - } - - if (!UL_prefix_type){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d define %s: NORMAL,EXTENDED!\n", - RC.config_file_name, i, GNB_CONFIG_STRING_UL_PREFIX_TYPE); - }else if (strcmp(UL_prefix_type, "NORMAL") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_prefix_type[j] = NORMAL; - }else if (strcmp(UL_prefix_type, "EXTENDED") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_prefix_type[j] = EXTENDED; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for UL_prefix_type choice: NORMAL or EXTENDED !\n", - RC.config_file_name, i, UL_prefix_type); - } - - NRRRC_CONFIGURATION_REQ (msg_p).nr_band[j] = nr_band; - NRRRC_CONFIGURATION_REQ (msg_p).downlink_frequency[j] = (uint64_t) downlink_frequency; - NRRRC_CONFIGURATION_REQ (msg_p).uplink_frequency_offset[j] = (unsigned int) uplink_frequency_offset; - - if (config_check_band_frequencies(j, - NRRRC_CONFIGURATION_REQ (msg_p).nr_band[j], - NRRRC_CONFIGURATION_REQ (msg_p).downlink_frequency[j], - NRRRC_CONFIGURATION_REQ (msg_p).uplink_frequency_offset[j], - NRRRC_CONFIGURATION_REQ (msg_p).frame_type[j])) { - AssertFatal(0, "error calling enb_check_band_frequencies\n"); - } - - if ((nb_antenna_ports <1) || (nb_antenna_ports > 2)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, enb %d unknown value \"%d\" for nb_antenna_ports choice: 1..2 !\n", - RC.config_file_name, i, nb_antenna_ports); - } - NRRRC_CONFIGURATION_REQ (msg_p).nb_antenna_ports[j] = nb_antenna_ports; - - - //////////////////////////////////////////////////////////////////////////////// - //---------------------------NR--------Configuration--------------------------// - //////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////MIB/////////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).MIB_subCarrierSpacingCommon[j] = MIB_subCarrierSpacingCommon; - if ((MIB_subCarrierSpacingCommon !=15) && (MIB_subCarrierSpacingCommon !=30) && (MIB_subCarrierSpacingCommon !=60) && (MIB_subCarrierSpacingCommon !=120)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for MIB_subCarrierSpacingCommon choice: 15,30,60,120 !\n", - RC.config_file_name, i, MIB_subCarrierSpacingCommon); - } - - NRRRC_CONFIGURATION_REQ (msg_p).MIB_ssb_SubcarrierOffset[j] = MIB_ssb_SubcarrierOffset; - if ((MIB_ssb_SubcarrierOffset <0) || (MIB_ssb_SubcarrierOffset > 15)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for MIB_ssb_SubcarrierOffset choice: 1..23 !\n", - RC.config_file_name, i, MIB_ssb_SubcarrierOffset); - } - - NRRRC_CONFIGURATION_REQ (msg_p).MIB_dmrs_TypeA_Position[j] = MIB_dmrs_TypeA_Position; - if ((MIB_dmrs_TypeA_Position !=2) && (MIB_dmrs_TypeA_Position !=3)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for MIB_dmrs_TypeA_Position choice:2,3 !\n", - RC.config_file_name, i, MIB_dmrs_TypeA_Position); - } - - NRRRC_CONFIGURATION_REQ (msg_p).pdcch_ConfigSIB1[j] = pdcch_ConfigSIB1; - if ((pdcch_ConfigSIB1 <0) || (pdcch_ConfigSIB1 > 255)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for pdcch_ConfigSIB1 choice: 0..3279165 !\n", - RC.config_file_name, i, pdcch_ConfigSIB1); - } - - ////////////////////////////////SIB1////////////////////////////// - - if (strcmp(SIB1_frequencyOffsetSSB , "khz-5") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).SIB1_frequencyOffsetSSB[j] = -5; - }else if (strcmp(SIB1_frequencyOffsetSSB , "khz5") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).SIB1_frequencyOffsetSSB[j] = 5; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for SIB1_frequencyOffsetSSB !\n", - RC.config_file_name, i, SIB1_frequencyOffsetSSB); - } - - NRRRC_CONFIGURATION_REQ (msg_p).SIB1_ssb_PeriodicityServingCell[j] = SIB1_ssb_PeriodicityServingCell; - if ((SIB1_ssb_PeriodicityServingCell !=5) && - (SIB1_ssb_PeriodicityServingCell !=10) && - (SIB1_ssb_PeriodicityServingCell !=20) && - (SIB1_ssb_PeriodicityServingCell !=40) && - (SIB1_ssb_PeriodicityServingCell !=80) && - (SIB1_ssb_PeriodicityServingCell !=160) ){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SIB1_ssb_PeriodicityServingCell choice: 5,10,20,40,80,160 !\n", - RC.config_file_name, i, SIB1_ssb_PeriodicityServingCell); - } - - NRRRC_CONFIGURATION_REQ (msg_p).SIB1_ss_PBCH_BlockPower[j] = SIB1_ss_PBCH_BlockPower; - if ((SIB1_ss_PBCH_BlockPower < -60) || (SIB1_ss_PBCH_BlockPower > 50)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SIB1_ss_PBCH_BlockPower choice: -60..50 !\n", - RC.config_file_name, i, SIB1_ss_PBCH_BlockPower); - } - - ////////////////////////////////NR FrequencyInfoDL////////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).absoluteFrequencySSB[j] = absoluteFrequencySSB; - if ((absoluteFrequencySSB <0) || (absoluteFrequencySSB > 3279165)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for absoluteFrequencySSB choice: 0..3279165 !\n", - RC.config_file_name, i, absoluteFrequencySSB); - } - - NRRRC_CONFIGURATION_REQ (msg_p).DL_FreqBandIndicatorNR[j] = DL_FreqBandIndicatorNR; - if ((DL_FreqBandIndicatorNR <1) || (DL_FreqBandIndicatorNR > 1024)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for DL_FreqBandIndicatorNR choice: 1..1024 !\n", - RC.config_file_name, i, DL_FreqBandIndicatorNR); - } - - NRRRC_CONFIGURATION_REQ (msg_p).DL_absoluteFrequencyPointA[j] = DL_absoluteFrequencyPointA; - if ((DL_absoluteFrequencyPointA <0) || (DL_absoluteFrequencyPointA > 3279165)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for DL_absoluteFrequencyPointA choice: 0..3279165 !\n", - RC.config_file_name, i, DL_absoluteFrequencyPointA); - } - - - /////////////////////////////////NR DL SCS-SpecificCarrier/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).DL_offsetToCarrier[j] = DL_offsetToCarrier; - if ((DL_offsetToCarrier <0) || (DL_offsetToCarrier > 2199)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for DL_offsetToCarrier choice: 0..11 !\n", - RC.config_file_name, i, DL_offsetToCarrier); - } - - if (strcmp(DL_SCS_SubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(DL_SCS_SubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(DL_SCS_SubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(DL_SCS_SubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(DL_SCS_SubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for DL_SCS_SubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, DL_SCS_SubcarrierSpacing); - } - - NRRRC_CONFIGURATION_REQ (msg_p).DL_carrierBandwidth[j] = DL_carrierBandwidth; - if ((DL_carrierBandwidth <1) || (DL_carrierBandwidth > 275)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for DL_carrierBandwidth choice: 1..275 !\n", - RC.config_file_name, i, DL_carrierBandwidth); - } - - /////////////////////////////////NR BWP-DownlinkCommon/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).DL_locationAndBandwidth[j] = DL_locationAndBandwidth; - if ((DL_locationAndBandwidth <0) || (DL_locationAndBandwidth > 37949)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for DL_locationAndBandwidth choice: 0..11 !\n", - RC.config_file_name, i, DL_locationAndBandwidth); - } - - if (strcmp(DL_BWP_SubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(DL_BWP_SubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(DL_BWP_SubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(DL_BWP_SubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(DL_BWP_SubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for DL_BWP_SubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, DL_BWP_SubcarrierSpacing); - } - - if (!DL_BWP_prefix_type){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d define %s: NORMAL,EXTENDED!\n", - RC.config_file_name, i, GNB_CONFIG_STRING_DL_PREFIX_TYPE); - }else if (strcmp(DL_BWP_prefix_type, "NORMAL") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_prefix_type[j] = NORMAL; - }else if (strcmp(DL_BWP_prefix_type, "EXTENDED") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).DL_BWP_prefix_type[j] = EXTENDED; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for DL_BWP_prefix_type choice: NORMAL or EXTENDED !\n", - RC.config_file_name, i, DL_BWP_prefix_type); - } - - /////////////////////////////////NR FrequencyInfoUL////////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).UL_FreqBandIndicatorNR[j] = UL_FreqBandIndicatorNR; - if ((UL_FreqBandIndicatorNR <1) || (UL_FreqBandIndicatorNR > 1024)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_FreqBandIndicatorNR choice: 1..1024 !\n", - RC.config_file_name, i, UL_FreqBandIndicatorNR); - } - - NRRRC_CONFIGURATION_REQ (msg_p).UL_absoluteFrequencyPointA[j] = UL_absoluteFrequencyPointA; - if ((UL_absoluteFrequencyPointA <0) || (UL_absoluteFrequencyPointA > 3279165)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_absoluteFrequencyPointA choice: 0..3279165 !\n", - RC.config_file_name, i, UL_absoluteFrequencyPointA); - } - - NRRRC_CONFIGURATION_REQ (msg_p).UL_additionalSpectrumEmission[j] = UL_additionalSpectrumEmission; - if ((UL_additionalSpectrumEmission <0) || (UL_additionalSpectrumEmission > 7)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_additionalSpectrumEmission choice: 0..7 !\n", - RC.config_file_name, i, UL_additionalSpectrumEmission); - } - - NRRRC_CONFIGURATION_REQ (msg_p).UL_p_Max[j] = UL_p_Max; - if ((UL_p_Max <-30) || (UL_p_Max > 33)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_p_Max choice: -30..33 !\n", - RC.config_file_name, i, UL_p_Max); - } - - if (strcmp(UL_frequencyShift7p5khz,"TRUE") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_frequencyShift7p5khz[j] = NR_FrequencyInfoUL__frequencyShift7p5khz_true; //enum true = 0 - }else{ - NRRRC_CONFIGURATION_REQ (msg_p).UL_frequencyShift7p5khz[j] = 1;//false - } - - /////////////////////////////////NR UL SCS-SpecificCarrier/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).UL_offsetToCarrier[j] = UL_offsetToCarrier; - if ((UL_offsetToCarrier <0) || (UL_offsetToCarrier > 2199)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_offsetToCarrier choice: 0..11 !\n", - RC.config_file_name, i, UL_offsetToCarrier); - } - - if (strcmp(UL_SCS_SubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(UL_SCS_SubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(UL_SCS_SubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(UL_SCS_SubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(UL_SCS_SubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_SCS_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for UL_SCS_SubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, UL_SCS_SubcarrierSpacing); - } - - NRRRC_CONFIGURATION_REQ (msg_p).UL_carrierBandwidth[j] = UL_carrierBandwidth; - if ((UL_carrierBandwidth <1) || (UL_carrierBandwidth > 275)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_carrierBandwidth choice: 1..275 !\n", - RC.config_file_name, i, UL_carrierBandwidth); - } - - /////////////////////////////////NR BWP-UplinkCommon/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).UL_locationAndBandwidth[j] = UL_locationAndBandwidth; - if ((UL_locationAndBandwidth <0) || (UL_locationAndBandwidth > 37949)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for UL_locationAndBandwidth choice: 0..11 !\n", - RC.config_file_name, i, UL_locationAndBandwidth); - } - - if (strcmp(UL_BWP_SubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(UL_BWP_SubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(UL_BWP_SubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(UL_BWP_SubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(UL_BWP_SubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for UL_BWP_SubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, UL_BWP_SubcarrierSpacing); - } - - if (!UL_BWP_prefix_type){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d define %s: NORMAL,EXTENDED!\n", - RC.config_file_name, i, GNB_CONFIG_STRING_DL_PREFIX_TYPE); - }else if (strcmp(UL_BWP_prefix_type, "NORMAL") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_prefix_type[j] = NORMAL; - }else if (strcmp(UL_BWP_prefix_type, "EXTENDED") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_BWP_prefix_type[j] = EXTENDED; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for UL_BWP_prefix_type choice: NORMAL or EXTENDED !\n", - RC.config_file_name, i, UL_BWP_prefix_type); - } - - if (strcmp(UL_timeAlignmentTimerCommon,"ms500")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms500; - }else if (strcmp(UL_timeAlignmentTimerCommon,"ms750")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms750; - }else if (strcmp(UL_timeAlignmentTimerCommon,"ms1280")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms1280; - }else if (strcmp(UL_timeAlignmentTimerCommon,"ms1920")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms1920; - }else if (strcmp(UL_timeAlignmentTimerCommon,"ms2560")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms2560; - }else if (strcmp(UL_timeAlignmentTimerCommon,"ms5120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms5120; - }else if (strcmp(UL_timeAlignmentTimerCommon,"ms10240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_ms10240; - }else if (strcmp(UL_timeAlignmentTimerCommon,"infinity")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).UL_timeAlignmentTimerCommon[j] = NR_TimeAlignmentTimer_infinity; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for UL_timeAlignmentTimerCommon choice: ms500,ms750,ms1280,ms1920,ms2560,ms5120,ms10240,infinity!\n", - RC.config_file_name, i, UL_timeAlignmentTimerCommon); - } - - if (strcmp(ServingCellConfigCommon_n_TimingAdvanceOffset,"n0")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_n_TimingAdvanceOffset[j] = NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n0; - }else if (strcmp(ServingCellConfigCommon_n_TimingAdvanceOffset,"n25600")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_n_TimingAdvanceOffset[j] = NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n25600; - }else if (strcmp(ServingCellConfigCommon_n_TimingAdvanceOffset,"n39936")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_n_TimingAdvanceOffset[j] = NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n39936; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for ServingCellConfigCommon_n_TimingAdvanceOffset choice n0,n25600,n39936!\n", - RC.config_file_name, i, ServingCellConfigCommon_n_TimingAdvanceOffset); - } - - - uint64_t t_freq; - if(nr_band == 41 || (nr_band > 76 && nr_band < 80)) - t_freq = 2400000000; - else - t_freq = 3000000000; - - if (downlink_frequency 15)) - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unvalid value \"%ld\" for ssb_PositionsInBurst at DL frequency %ld !\n", - RC.config_file_name, i, ServingCellConfigCommon_ssb_PositionsInBurst_PR, downlink_frequency); - else { - if(downlink_frequency<6000000000 && (ServingCellConfigCommon_ssb_PositionsInBurst_PR > 255)) - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unvalid value \"%ld\" for ssb_PositionsInBurst at DL frequency %ld !\n", - RC.config_file_name, i, ServingCellConfigCommon_ssb_PositionsInBurst_PR, downlink_frequency); - else - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_PositionsInBurst_PR[j] = ServingCellConfigCommon_ssb_PositionsInBurst_PR; - } - - switch (ServingCellConfigCommon_ssb_periodicityServingCell) { - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_periodicityServingCell[j] = NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms5; - break; - - case 10: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_periodicityServingCell[j] = NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms10; - break; - - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_periodicityServingCell[j] = NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms20; - break; - - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_periodicityServingCell[j] = NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms40; - break; - - case 80: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_periodicityServingCell[j] = NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms80; - break; - - case 160: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ssb_periodicityServingCell[j] = NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms160; - break; - - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for ServingCellConfigCommon_ssb_periodicityServingCell choice: -6,0,6 !\n", - RC.config_file_name, i, ServingCellConfigCommon_ssb_periodicityServingCell); - break; - } - - switch (ServingCellConfigCommon_dmrs_TypeA_Position) { - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_dmrs_TypeA_Position[j] = NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2; - break; - - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_dmrs_TypeA_Position[j] = NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3; - break; - - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for ServingCellConfigCommon_dmrs_TypeA_Position choice: 2,3 !\n", - RC.config_file_name, i, ServingCellConfigCommon_dmrs_TypeA_Position); - break; - } - - if (strcmp(NIA_SubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).NIA_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(NIA_SubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).NIA_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(NIA_SubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).NIA_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(NIA_SubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).NIA_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(NIA_SubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).NIA_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for NIA_SubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, NIA_SubcarrierSpacing); - } - - NRRRC_CONFIGURATION_REQ (msg_p).ServingCellConfigCommon_ss_PBCH_BlockPower[j] = ServingCellConfigCommon_ss_PBCH_BlockPower; - if ((ServingCellConfigCommon_ss_PBCH_BlockPower < -60) || (ServingCellConfigCommon_ss_PBCH_BlockPower > 50)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for ServingCellConfigCommon_ss_PBCH_BlockPower choice: 0..11 !\n", - RC.config_file_name, i, ServingCellConfigCommon_ss_PBCH_BlockPower); - } - - /////////////////////////////////NR TDD-UL-DL-ConfigCommon/////////////////////////// - if (strcmp(referenceSubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).referenceSubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(referenceSubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).referenceSubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(referenceSubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).referenceSubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(referenceSubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).referenceSubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(referenceSubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).referenceSubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for referenceSubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, referenceSubcarrierSpacing); - } - - if (strcmp(dl_UL_TransmissionPeriodicity,"ms0p5")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p5; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms0p625")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p625; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms1")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms1; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms1p25")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms1p25; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms2")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms2; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms2p5")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms2p5; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms5")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms5; - }else if (strcmp(dl_UL_TransmissionPeriodicity,"ms10")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).dl_UL_TransmissionPeriodicity[j] = NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms10; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for dl_UL_TransmissionPeriodicity choice: minusinfinity,ms0p5,ms0p625,ms1,ms1p25,ms2,ms2p5,ms5,ms10 !\n", - RC.config_file_name, i, dl_UL_TransmissionPeriodicity); - } - - NRRRC_CONFIGURATION_REQ (msg_p).nrofDownlinkSlots[j] = nrofDownlinkSlots; - if ((nrofDownlinkSlots < 0) || (nrofDownlinkSlots > 320)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for nrofDownlinkSlots choice: 0..320 !\n", - RC.config_file_name, i, nrofDownlinkSlots); - } - - NRRRC_CONFIGURATION_REQ (msg_p).nrofDownlinkSymbols[j] = nrofDownlinkSymbols; - if ((nrofDownlinkSymbols < 0) || (nrofDownlinkSymbols > 13)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for nrofDownlinkSymbols choice: 0..13 !\n", - RC.config_file_name, i, nrofDownlinkSymbols); - } - - NRRRC_CONFIGURATION_REQ (msg_p).nrofUplinkSlots[j] = nrofUplinkSlots; - if ((nrofUplinkSlots < 0) || (nrofUplinkSlots > 320)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for nrofUplinkSlots choice: 0..320 !\n", - RC.config_file_name, i, nrofUplinkSlots); - } - - NRRRC_CONFIGURATION_REQ (msg_p).nrofUplinkSymbols[j] = nrofUplinkSymbols; - if ((nrofUplinkSymbols < 0) || (nrofUplinkSymbols > 13)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for nrofUplinkSymbols choice: 0..13 !\n", - RC.config_file_name, i, nrofUplinkSymbols); - } - - /////////////////////////////////NR RACH-ConfigCommon/////////////////////////// - - NRRRC_CONFIGURATION_REQ (msg_p).rach_totalNumberOfRA_Preambles[j] = rach_totalNumberOfRA_Preambles; - if ((rach_totalNumberOfRA_Preambles <1) || (rach_totalNumberOfRA_Preambles>63)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_numberOfRA_Preambles choice: 1..63 !\n", - RC.config_file_name, i, rach_totalNumberOfRA_Preambles); - } - - if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"oneEighth")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_oneEighth; - switch (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth){ - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n8; - break; - case 12: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n12; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n16; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n20; - break; - case 24: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n24; - break; - case 28: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n28; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n32; - break; - case 36: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n36; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n40; - break; - case 44: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n44; - break; - case 48: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n48; - break; - case 52: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n52; - break; - case 56: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n56; - break; - case 60: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n60; - break; - case 64: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneEighth_n64; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth choice: 4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64!\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth); - break; - }//End oneEighth - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"oneFourth")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_oneFourth; - switch (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth){ - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n8; - break; - case 12: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n12; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n16; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n20; - break; - case 24: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n24; - break; - case 28: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n28; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n32; - break; - case 36: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n36; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n40; - break; - case 44: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n44; - break; - case 48: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n48; - break; - case 52: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n52; - break; - case 56: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n56; - break; - case 60: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n60; - break; - case 64: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneFourth_n64; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth choice: 4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64!\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth); - break; - }//End oneFourth - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"oneHalf")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_oneHalf; - switch (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf){ - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n8; - break; - case 12: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n12; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n16; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n20; - break; - case 24: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n24; - break; - case 28: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n28; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n32; - break; - case 36: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n36; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n40; - break; - case 44: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n44; - break; - case 48: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n48; - break; - case 52: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n52; - break; - case 56: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n56; - break; - case 60: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n60; - break; - case 64: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__oneHalf_n64; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf choice: 4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64!\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf); - break; - }//End oneHalf - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"one")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_one; - switch (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one){ - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n8; - break; - case 12: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n12; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n16; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n20; - break; - case 24: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n24; - break; - case 28: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n28; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n32; - break; - case 36: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n36; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n40; - break; - case 44: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n44; - break; - case 48: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n48; - break; - case 52: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n52; - break; - case 56: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n56; - break; - case 60: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n60; - break; - case 64: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__one_n64; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one choice: 4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64!\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one); - break; - }//End one - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"two")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_two; - switch (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one){ - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n8; - break; - case 12: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n12; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n16; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n20; - break; - case 24: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n24; - break; - case 28: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n28; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB__two_n32; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two choice: 4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64!\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two); - break; - }//End two - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"four")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_four; - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four[j] = rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four; - if ((rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four < 1) || (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four > 16)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four choice: 1..16 !\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four); - }//End four - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"eight")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_eight; - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight[j] = rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight; - if ((rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight < 1) || (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight > 8)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight choice: 1..8 !\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight); - }//End eight - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"sixteen")==0) { - - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_sixteen; - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen[j] = rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen; - if ((rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen < 1) || (rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen > 4)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen choice: 1..4 !\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen); - }//End sixteen - - }else if (strcmp(rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice,"NOTHING")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[j] = NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_NOTHING; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice: oneEighth,oneFourth,oneHalf,one,two,four,eight,sixteen !\n", - RC.config_file_name, i, rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice); - } - - if (strcmp(rach_groupBconfigured , "ENABLE") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_groupBconfigured [j] = TRUE; - - switch (rach_ra_Msg3SizeGroupA) { - case 56: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b56; - break; - case 144: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b144; - break; - case 208: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b208; - break; - case 256: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b256; - break; - case 282: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b282; - break; - case 480: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b480; - break; - case 640: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b640; - break; - case 800: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b800; - break; - case 1000: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_Msg3SizeGroupA[j] = NR_RACH_ConfigCommon__groupBconfigured__ra_Msg3SizeGroupA_b1000; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ra_Msg3SizeGroupA choice: 56,144,208,256,282,480,640,800,1000!\n", - RC.config_file_name, i, rach_ra_Msg3SizeGroupA); - break; - }// End switch (rach_ra_Msg3SizeGroupA) - - if (strcmp(rach_messagePowerOffsetGroupB,"minusinfinity")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_minusinfinity; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB0")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB0; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB5")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB5; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB8")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB8; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB10")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB10; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB12")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB12; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB15; - }else if (strcmp(rach_messagePowerOffsetGroupB,"dB18")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).rach_messagePowerOffsetGroupB[j] = NR_RACH_ConfigCommon__groupBconfigured__messagePowerOffsetGroupB_dB18; - }else{ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for rach_messagePowerOffsetGroupB choice: minusinfinity,dB0,dB5,dB8,dB10,dB12,dB15,dB18!\n", - RC.config_file_name, i, rach_messagePowerOffsetGroupB); - }// End if (strcmp(rach_messagePowerOffsetGroupB,"minusinfinity")==0) - - NRRRC_CONFIGURATION_REQ (msg_p).rach_numberOfRA_PreamblesGroupA[j] = rach_numberOfRA_PreamblesGroupA; - if ((rach_numberOfRA_PreamblesGroupA <1) || (rach_numberOfRA_PreamblesGroupA>64)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_numberOfRA_PreamblesGroupA choice: 1..63 !\n", - RC.config_file_name, i, rach_numberOfRA_PreamblesGroupA); - } - - }// End if (strcmp(rach_groupBconfigured , "ENABLE") == 0) - - switch (rach_ra_ContentionResolutionTimer) { - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf8; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf16; - break; - case 24: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf24; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf32; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf40; - break; - case 48: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf48; - break; - case 56: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf56; - break; - case 64: - NRRRC_CONFIGURATION_REQ (msg_p).rach_ra_ContentionResolutionTimer[j] = NR_RACH_ConfigCommon__ra_ContentionResolutionTimer_sf64; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rach_ra_ContentionResolutionTimer choice: 8,16,24,32,40,48,56,64!\n", - RC.config_file_name, i, rach_ra_ContentionResolutionTimer); - break; - }// End switch (rach_ra_ContentionResolutionTimer) - - - NRRRC_CONFIGURATION_REQ (msg_p).rsrp_ThresholdSSB[j] = rsrp_ThresholdSSB; - if ((rsrp_ThresholdSSB <0) || (rsrp_ThresholdSSB>124)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rsrp_ThresholdSSB choice: 0..124 !\n", - RC.config_file_name, i, rsrp_ThresholdSSB); - } - - NRRRC_CONFIGURATION_REQ (msg_p).rsrp_ThresholdSSB_SUL[j] = rsrp_ThresholdSSB_SUL; - if ((rsrp_ThresholdSSB_SUL <0) || (rsrp_ThresholdSSB_SUL>124)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rsrp_ThresholdSSB_SUL choice: 0..124 !\n", - RC.config_file_name, i, rsrp_ThresholdSSB_SUL); - } - - if (strcmp(prach_RootSequenceIndex_choice , "l839") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_RootSequenceIndex_choice[j] = NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l839; - NRRRC_CONFIGURATION_REQ (msg_p).prach_RootSequenceIndex_l839[j] = prach_RootSequenceIndex_l839; - }else if (strcmp(prach_RootSequenceIndex_choice , "l139") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).prach_RootSequenceIndex_choice[j] = NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139; - NRRRC_CONFIGURATION_REQ (msg_p).prach_RootSequenceIndex_l139[j] = prach_RootSequenceIndex_l139; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for prach_RootSequenceIndex_choice !\n", - RC.config_file_name, i, prach_RootSequenceIndex_choice); - } - - if (strcmp(prach_msg1_SubcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(prach_msg1_SubcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(prach_msg1_SubcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(prach_msg1_SubcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(prach_msg1_SubcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_SubcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for prach_msg1_SubcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, prach_msg1_SubcarrierSpacing); - } - - if (strcmp(restrictedSetConfig , "unrestrictedSet") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).restrictedSetConfig[j] = NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet; - }else if (strcmp(restrictedSetConfig , "restrictedSetTypeA") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).restrictedSetConfig[j] = NR_RACH_ConfigCommon__restrictedSetConfig_restrictedSetTypeA; - }else if (strcmp(restrictedSetConfig , "restrictedSetTypeB") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).restrictedSetConfig[j] = NR_RACH_ConfigCommon__restrictedSetConfig_restrictedSetTypeB; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for restrictedSetConfig !\n", - RC.config_file_name, i, restrictedSetConfig); - } - - if (strcmp(msg3_transformPrecoding , "ENABLE") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).msg3_transformPrecoding[j] = TRUE; - } - - ////////////////////////////////NR RACH-ConfigGeneric////////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).prach_ConfigurationIndex[j] = prach_ConfigurationIndex; - if ((prach_ConfigurationIndex <0) || (prach_ConfigurationIndex>255)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for prach_ConfigurationIndex choice: 0..255 !\n", - RC.config_file_name, i, prach_ConfigurationIndex); - } - - if (strcmp(prach_msg1_FDM , "one") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_FDM[j] = NR_RACH_ConfigGeneric__msg1_FDM_one; - }else if (strcmp(prach_msg1_FDM , "two") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_FDM[j] = NR_RACH_ConfigGeneric__msg1_FDM_two; - }else if (strcmp(prach_msg1_FDM , "four") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_FDM[j] = NR_RACH_ConfigGeneric__msg1_FDM_four; - }else if (strcmp(prach_msg1_FDM , "eight") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_FDM[j] = NR_RACH_ConfigGeneric__msg1_FDM_eight; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for prach_msg1_FDM !\n", - RC.config_file_name, i, prach_msg1_FDM); - } - - NRRRC_CONFIGURATION_REQ (msg_p).prach_msg1_FrequencyStart[j] = prach_msg1_FrequencyStart; - if ((prach_msg1_FrequencyStart <0) || (prach_msg1_FrequencyStart>274)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for prach_msg1_FrequencyStart choice: 0..274 !\n", - RC.config_file_name, i, prach_msg1_FrequencyStart); - } - - NRRRC_CONFIGURATION_REQ (msg_p).zeroCorrelationZoneConfig[j] = zeroCorrelationZoneConfig; - if ((zeroCorrelationZoneConfig <0) || (zeroCorrelationZoneConfig>15)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for zeroCorrelationZoneConfig choice: 0..15 !\n", - RC.config_file_name, i, zeroCorrelationZoneConfig); - } - - NRRRC_CONFIGURATION_REQ (msg_p).preambleReceivedTargetPower[j] = preambleReceivedTargetPower; - if ((preambleReceivedTargetPower <-200) || (preambleReceivedTargetPower>-74)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for preambleReceivedTargetPower choice: -200..-74 !\n", - RC.config_file_name, i, preambleReceivedTargetPower); - } - - switch (preambleTransMax) { - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n5; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n6; - break; - case 7: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n7; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n8; - break; - case 10: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n10; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n20; - break; - case 50: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n50; - break; - case 100: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n100; - break; - case 200: - NRRRC_CONFIGURATION_REQ (msg_p).preambleTransMax[j] = NR_RACH_ConfigGeneric__preambleTransMax_n200; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for preambleTransMax choice: 3,4,5,6,7,8,10,20,50,100,200 !\n", - RC.config_file_name, i, preambleTransMax); - break; - } - - if (strcmp(powerRampingStep , "dB0") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).powerRampingStep[j] = NR_RACH_ConfigGeneric__powerRampingStep_dB0; - }else if (strcmp(powerRampingStep , "dB2") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).powerRampingStep[j] = NR_RACH_ConfigGeneric__powerRampingStep_dB2; - }else if (strcmp(powerRampingStep , "dB4") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).powerRampingStep[j] = NR_RACH_ConfigGeneric__powerRampingStep_dB4; - }else if (strcmp(powerRampingStep , "dB6") == 0) { - NRRRC_CONFIGURATION_REQ (msg_p).powerRampingStep[j] = NR_RACH_ConfigGeneric__powerRampingStep_dB6; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for powerRampingStep !\n", - RC.config_file_name, i, powerRampingStep); - } - - switch (ra_ResponseWindow) { - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8; - break; - case 10: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40; - break; - case 80: - NRRRC_CONFIGURATION_REQ (msg_p).ra_ResponseWindow[j] = NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for ra_ResponseWindow choice: 1,2,4,8,10,20,40,80 !\n", - RC.config_file_name, i, ra_ResponseWindow); - break; - } - - /////////////////////////////////NR PUSCH-ConfigCommon/////////////////////////// - if (strcmp(groupHoppingEnabledTransformPrecoding , "ENABLE") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).groupHoppingEnabledTransformPrecoding[j] = TRUE; - } - - NRRRC_CONFIGURATION_REQ (msg_p).msg3_DeltaPreamble[j] = msg3_DeltaPreamble; - if ((msg3_DeltaPreamble <-1) || (msg3_DeltaPreamble>6)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for msg3_DeltaPreamble choice: -1..6 !\n", - RC.config_file_name, i, msg3_DeltaPreamble); - } - - NRRRC_CONFIGURATION_REQ (msg_p).p0_NominalWithGrant[j] = p0_NominalWithGrant; - if ((p0_NominalWithGrant <-202) || (p0_NominalWithGrant>24)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for p0_NominalWithGrant choice: -202..24 !\n", - RC.config_file_name, i, p0_NominalWithGrant); - } - - /////////////////////////////////NR PUSCH-TimeDomainResourceAllocation/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).PUSCH_TimeDomainResourceAllocation_k2[j] = PUSCH_TimeDomainResourceAllocation_k2; - if ((PUSCH_TimeDomainResourceAllocation_k2 <0) || (PUSCH_TimeDomainResourceAllocation_k2>32)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PUSCH_TimeDomainResourceAllocation_k2 choice: 0..7 !\n", - RC.config_file_name, i, PUSCH_TimeDomainResourceAllocation_k2); - } - - if (strcmp(PUSCH_TimeDomainResourceAllocation_mappingType , "typeA") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PUSCH_TimeDomainResourceAllocation_mappingType[j] = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA; - }else if (strcmp(PUSCH_TimeDomainResourceAllocation_mappingType , "typeB") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PUSCH_TimeDomainResourceAllocation_mappingType[j] = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for PUSCH_TimeDomainResourceAllocation_mappingType !\n", - RC.config_file_name, i, PUSCH_TimeDomainResourceAllocation_mappingType); - } - - NRRRC_CONFIGURATION_REQ (msg_p).PUSCH_TimeDomainResourceAllocation_startSymbolAndLength[j] = PUSCH_TimeDomainResourceAllocation_startSymbolAndLength; - if ((PUSCH_TimeDomainResourceAllocation_startSymbolAndLength <0) || (PUSCH_TimeDomainResourceAllocation_startSymbolAndLength>127)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PUSCH_TimeDomainResourceAllocation_startSymbolAndLength choice: 0..127 !\n", - RC.config_file_name, i, PUSCH_TimeDomainResourceAllocation_startSymbolAndLength); - } - - /////////////////////////////////NR PUCCH-ConfigCommon/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).pucch_ResourceCommon[j] = pucch_ResourceCommon; - if ((pucch_ResourceCommon <0) || (pucch_ResourceCommon>15)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for pucch_ResourceCommon choice: 0..15 !\n", - RC.config_file_name, i, pucch_ResourceCommon); - } - - if (strcmp(pucch_GroupHopping , "neither") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).pucch_GroupHopping[j] = NR_PUCCH_ConfigCommon__pucch_GroupHopping_neither; - }else if (strcmp(pucch_GroupHopping , "enable") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).pucch_GroupHopping[j] = NR_PUCCH_ConfigCommon__pucch_GroupHopping_enable; - }else if (strcmp(pucch_GroupHopping , "disable") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).pucch_GroupHopping[j] = NR_PUCCH_ConfigCommon__pucch_GroupHopping_disable; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for pucch_GroupHopping !\n", - RC.config_file_name, i, pucch_GroupHopping); - } - - NRRRC_CONFIGURATION_REQ (msg_p).hoppingId[j] = hoppingId; - if ((hoppingId <0) || (hoppingId>1024)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for hoppingId choice: 0..1024 !\n", - RC.config_file_name, i, hoppingId); - } - - NRRRC_CONFIGURATION_REQ (msg_p).p0_nominal[j] = p0_nominal; - if ((p0_nominal <-202) || (p0_nominal>24)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for p0_nominal choice: -202..24 !\n", - RC.config_file_name, i, p0_nominal); - } - - //////////////////////////////////NR PDSCH-TimeDomainResourceAllocation/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).PDSCH_TimeDomainResourceAllocation_k0[j] = PDSCH_TimeDomainResourceAllocation_k0; - if ((PDSCH_TimeDomainResourceAllocation_k0 <1) || (PDSCH_TimeDomainResourceAllocation_k0>3)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDSCH_TimeDomainResourceAllocation_k0 choice: 0..7 !\n", - RC.config_file_name, i, PDSCH_TimeDomainResourceAllocation_k0); - } - - if (strcmp(PDSCH_TimeDomainResourceAllocation_mappingType , "typeA") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDSCH_TimeDomainResourceAllocation_mappingType[j] = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA; - }else if (strcmp(PDSCH_TimeDomainResourceAllocation_mappingType , "typeB") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDSCH_TimeDomainResourceAllocation_mappingType[j] = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for PDSCH_TimeDomainResourceAllocation_mappingType !\n", - RC.config_file_name, i, PDSCH_TimeDomainResourceAllocation_mappingType); - } - - NRRRC_CONFIGURATION_REQ (msg_p).PDSCH_TimeDomainResourceAllocation_startSymbolAndLength[j] = PDSCH_TimeDomainResourceAllocation_startSymbolAndLength; - if ((PDSCH_TimeDomainResourceAllocation_startSymbolAndLength <0) || (PDSCH_TimeDomainResourceAllocation_startSymbolAndLength>127)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDSCH_TimeDomainResourceAllocation_startSymbolAndLength choice: 0..127 !\n", - RC.config_file_name, i, PDSCH_TimeDomainResourceAllocation_startSymbolAndLength); - } - - //////////////////////////////////NR RateMatchPattern/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).rateMatchPatternId[j] = rateMatchPatternId; - if ((rateMatchPatternId <0) || (rateMatchPatternId>3)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for rateMatchPatternId choice: 0..3 !\n", - RC.config_file_name, i, rateMatchPatternId); - } - - if (strcmp(RateMatchPattern_patternType , "NOTHING") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_patternType[j] = NR_RateMatchPattern__patternType_PR_NOTHING; - }else if (strcmp(RateMatchPattern_patternType , "bitmaps") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_patternType[j] = NR_RateMatchPattern__patternType_PR_bitmaps; - }else if (strcmp(RateMatchPattern_patternType , "controlResourceSet") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_patternType[j] = NR_RateMatchPattern__patternType_PR_controlResourceSet; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for RateMatchPattern_patternType !\n", - RC.config_file_name, i, RateMatchPattern_patternType); - } - - if (strcmp(symbolsInResourceBlock , "NOTHING") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).symbolsInResourceBlock[j] = NR_RateMatchPattern__patternType__bitmaps__symbolsInResourceBlock_PR_NOTHING; - }else if (strcmp(symbolsInResourceBlock , "oneSlot") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).symbolsInResourceBlock[j] = NR_RateMatchPattern__patternType__bitmaps__symbolsInResourceBlock_PR_oneSlot; - }else if (strcmp(symbolsInResourceBlock , "twoSlots") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).symbolsInResourceBlock[j] = NR_RateMatchPattern__patternType__bitmaps__symbolsInResourceBlock_PR_twoSlots; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for symbolsInResourceBlock !\n", - RC.config_file_name, i, symbolsInResourceBlock); - } - - switch(periodicityAndPattern){ - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n2; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n5; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n8; - break; - case 10: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n10; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n20; - break; - case 40: - NRRRC_CONFIGURATION_REQ (msg_p).periodicityAndPattern[j] = NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n40; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for periodicityAndPattern choice: 2,4,5,8,10,20,40 !\n", - RC.config_file_name, i, periodicityAndPattern); - break; - } - - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_controlResourceSet[j] = RateMatchPattern_controlResourceSet; - if ((RateMatchPattern_controlResourceSet <0) || (RateMatchPattern_controlResourceSet>11)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPattern_controlResourceSet choice: 0..3 !\n", - RC.config_file_name, i, RateMatchPattern_controlResourceSet); - } - - if (strcmp(RateMatchPattern_subcarrierSpacing,"kHz15")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_subcarrierSpacing[j] = NR_SubcarrierSpacing_kHz15; - }else if (strcmp(RateMatchPattern_subcarrierSpacing,"kHz30")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_subcarrierSpacing[j] = NR_SubcarrierSpacing_kHz30; - }else if (strcmp(RateMatchPattern_subcarrierSpacing,"kHz60")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_subcarrierSpacing[j] = NR_SubcarrierSpacing_kHz60; - }else if (strcmp(RateMatchPattern_subcarrierSpacing,"kHz120")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_subcarrierSpacing[j] = NR_SubcarrierSpacing_kHz120; - }else if (strcmp(RateMatchPattern_subcarrierSpacing,"kHz240")==0) { - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_subcarrierSpacing[j] = NR_SubcarrierSpacing_kHz240; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for RateMatchPattern_subcarrierSpacing choice: minusinfinity,kHz15,kHz30,kHz60,kHz120,kHz240!\n", - RC.config_file_name, i, RateMatchPattern_subcarrierSpacing); - } - - if (strcmp(RateMatchPattern_mode , "dynamic") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_mode[j] = NR_RateMatchPattern__dummy_dynamic; - }else if (strcmp(RateMatchPattern_mode , "semiStatic") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPattern_mode[j] = NR_RateMatchPattern__dummy_semiStatic; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for RateMatchPattern_mode !\n", - RC.config_file_name, i, RateMatchPattern_mode); - } - - //////////////////////////////////NR PDCCH-ConfigCommon/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).controlResourceSetZero[j] = controlResourceSetZero; - if ((controlResourceSetZero <0) || (controlResourceSetZero>15)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for controlResourceSetZero choice: 0..15 !\n", - RC.config_file_name, i, controlResourceSetZero); - } - - NRRRC_CONFIGURATION_REQ (msg_p).searchSpaceZero[j] = searchSpaceZero; - if ((searchSpaceZero <0) || (searchSpaceZero>15)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for searchSpaceZero choice: 0..15 !\n", - RC.config_file_name, i, searchSpaceZero); - } - - NRRRC_CONFIGURATION_REQ (msg_p).searchSpaceSIB1[j] = searchSpaceSIB1; - if ((searchSpaceSIB1 <0) || (searchSpaceSIB1>39)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for searchSpaceSIB1 choice: 0..39 !\n", - RC.config_file_name, i, searchSpaceSIB1); - } - - NRRRC_CONFIGURATION_REQ (msg_p).searchSpaceOtherSystemInformation[j] = searchSpaceOtherSystemInformation; - if ((searchSpaceOtherSystemInformation <0) || (searchSpaceOtherSystemInformation>39)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for searchSpaceOtherSystemInformation choice: 0..39 !\n", - RC.config_file_name, i, searchSpaceOtherSystemInformation); - } - - NRRRC_CONFIGURATION_REQ (msg_p).pagingSearchSpace[j] = pagingSearchSpace; - if ((pagingSearchSpace <0) || (pagingSearchSpace>39)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for pagingSearchSpace choice: 0..39 !\n", - RC.config_file_name, i, pagingSearchSpace); - } - - NRRRC_CONFIGURATION_REQ (msg_p).ra_SearchSpace[j] = ra_SearchSpace; - if ((ra_SearchSpace <0) || (ra_SearchSpace>39)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for ra_SearchSpace choice: 0..39 !\n", - RC.config_file_name, i, ra_SearchSpace); - } - - //////////////////////////////////NR PDCCH commonControlResourcesSets/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_common_controlResourceSetId[j] = PDCCH_common_controlResourceSetId; - if ((PDCCH_common_controlResourceSetId <0) || (PDCCH_common_controlResourceSetId>11)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_common_controlResourceSetId choice: 0..11 !\n", - RC.config_file_name, i, PDCCH_common_controlResourceSetId); - } - - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_common_ControlResourceSet_duration[j] = PDCCH_common_ControlResourceSet_duration; - if ((PDCCH_common_ControlResourceSet_duration <0) || (PDCCH_common_ControlResourceSet_duration>3)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_common_ControlResourceSet_duration choice: 0..11 !\n", - RC.config_file_name, i, PDCCH_common_ControlResourceSet_duration); - } - - if (strcmp(PDCCH_cce_REG_MappingType , "NOTHING") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_cce_REG_MappingType[j] = NR_ControlResourceSet__cce_REG_MappingType_PR_NOTHING; - }else if (strcmp(PDCCH_cce_REG_MappingType , "interleaved") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_cce_REG_MappingType[j] = NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved; - }else if (strcmp(PDCCH_cce_REG_MappingType , "nonInterleaved") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_cce_REG_MappingType[j] = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for PDCCH_cce_REG_MappingType !\n", - RC.config_file_name, i, PDCCH_cce_REG_MappingType); - } - - switch(PDCCH_reg_BundleSize){ - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_reg_BundleSize[j] = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_reg_BundleSize[j] = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n3; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_reg_BundleSize[j] = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_reg_BundleSize choice: 2,3,6 !\n", - RC.config_file_name, i, PDCCH_reg_BundleSize); - break; - } - - switch(PDCCH_interleaverSize){ - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_interleaverSize[j] = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_interleaverSize[j] = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n3; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_interleaverSize[j] = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_interleaverSize choice: 2,3,6 !\n", - RC.config_file_name, i, PDCCH_interleaverSize); - break; - } - - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_shiftIndex[j] = PDCCH_shiftIndex; - if ((PDCCH_shiftIndex <0) || (PDCCH_shiftIndex>274)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_shiftIndex choice: 0..274 !\n", - RC.config_file_name, i, PDCCH_shiftIndex); - } - - if (strcmp(PDCCH_precoderGranularity , "sameAsREG-bundle") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_precoderGranularity[j] = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - }else if (strcmp(PDCCH_precoderGranularity , "allContiguousRBs") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_precoderGranularity[j] = NR_ControlResourceSet__precoderGranularity_allContiguousRBs; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for PDCCH_precoderGranularity !\n", - RC.config_file_name, i, PDCCH_precoderGranularity); - } - - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_TCI_StateId[j] = PDCCH_TCI_StateId; - if ((PDCCH_TCI_StateId <0) || (PDCCH_TCI_StateId>63)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_TCI_StateId choice: 0..63 !\n", - RC.config_file_name, i, PDCCH_TCI_StateId); - } - - if (strcmp(tci_PresentInDCI , "ENABLE") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).tci_PresentInDCI[j] = TRUE; - } - - NRRRC_CONFIGURATION_REQ (msg_p).PDCCH_DMRS_ScramblingID[j] = PDCCH_DMRS_ScramblingID; - if ((PDCCH_DMRS_ScramblingID <0) || (PDCCH_DMRS_ScramblingID>65535)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for PDCCH_DMRS_ScramblingID choice: 0..65535 !\n", - RC.config_file_name, i, PDCCH_DMRS_ScramblingID); - } - - //////////////////////////////////NR PDCCH commonSearchSpaces/////////////////////////// - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpaceId[j] = SearchSpaceId; - if ((SearchSpaceId <0) || (SearchSpaceId>39)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpaceId choice: 0..39 !\n", - RC.config_file_name, i, SearchSpaceId); - } - - NRRRC_CONFIGURATION_REQ (msg_p).commonSearchSpaces_controlResourceSetId[j] = commonSearchSpaces_controlResourceSetId; - if ((commonSearchSpaces_controlResourceSetId <0) || (commonSearchSpaces_controlResourceSetId>11)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for commonSearchSpaces_controlResourceSetId choice: 0..11 !\n", - RC.config_file_name, i, commonSearchSpaces_controlResourceSetId); - } - - if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl1") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = 0; - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl2") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>1)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..1 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl4") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>3)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..3 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl5") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>4)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..4 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl8") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>7)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..7 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl10") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>9)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..9 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl16") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>15)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..15 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl20") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20; - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_value[j] = SearchSpace_monitoringSlotPeriodicityAndOffset_value; - if ((SearchSpace_monitoringSlotPeriodicityAndOffset_value <0) || (SearchSpace_monitoringSlotPeriodicityAndOffset_value>19)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_monitoringSlotPeriodicityAndOffset_value choice: 0..19 !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_value); - } - - }else if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "UNABLE") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_monitoringSlotPeriodicityAndOffset_choice[j] = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_NOTHING; - - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for SearchSpace_monitoringSlotPeriodicityAndOffset_choice !\n", - RC.config_file_name, i, SearchSpace_monitoringSlotPeriodicityAndOffset_choice); - }// End if (strcmp(SearchSpace_monitoringSlotPeriodicityAndOffset_choice , "sl1") - - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_duration[j] = SearchSpace_duration; - if ((SearchSpace_duration <2) || (SearchSpace_duration>2559)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_duration choice: 2..2559 !\n", - RC.config_file_name, i, SearchSpace_duration); - } - - switch(SearchSpace_nrofCandidates_aggregationLevel1){ - case 0: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - break; - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n5; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n6; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel1[j] = NR_SearchSpace__nrofCandidates__aggregationLevel1_n8; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_nrofCandidates_aggregationLevel1 choice: 0,1,2,3,4,5,6,8 !\n", - RC.config_file_name, i, SearchSpace_nrofCandidates_aggregationLevel1); - break; - } - - switch(SearchSpace_nrofCandidates_aggregationLevel2){ - case 0: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - break; - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n5; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n6; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel2[j] = NR_SearchSpace__nrofCandidates__aggregationLevel2_n8; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_nrofCandidates_aggregationLevel2 choice: 0,1,2,3,4,5,6,8 !\n", - RC.config_file_name, i, SearchSpace_nrofCandidates_aggregationLevel2); - break; - } - - switch(SearchSpace_nrofCandidates_aggregationLevel4){ - case 0: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n0; - break; - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n5; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n6; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel4[j] = NR_SearchSpace__nrofCandidates__aggregationLevel4_n8; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_nrofCandidates_aggregationLevel4 choice: 0,1,2,3,4,5,6,8 !\n", - RC.config_file_name, i, SearchSpace_nrofCandidates_aggregationLevel4); - break; - } - - switch(SearchSpace_nrofCandidates_aggregationLevel8){ - case 0: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - break; - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n5; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n6; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel8[j] = NR_SearchSpace__nrofCandidates__aggregationLevel8_n8; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_nrofCandidates_aggregationLevel8 choice: 0,1,2,3,4,5,6,8 !\n", - RC.config_file_name, i, SearchSpace_nrofCandidates_aggregationLevel8); - break; - } - - switch(SearchSpace_nrofCandidates_aggregationLevel16){ - case 0: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - break; - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n5; - break; - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n6; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_nrofCandidates_aggregationLevel16[j] = NR_SearchSpace__nrofCandidates__aggregationLevel16_n8; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for SearchSpace_nrofCandidates_aggregationLevel16 choice: 0,1,2,3,4,5,6,8 !\n", - RC.config_file_name, i, SearchSpace_nrofCandidates_aggregationLevel16); - break; - } - - if (strcmp(SearchSpace_searchSpaceType , "NOTHING") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_searchSpaceType[j] = NR_SearchSpace__searchSpaceType_PR_NOTHING; - }else if (strcmp(SearchSpace_searchSpaceType , "common") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_searchSpaceType[j] = NR_SearchSpace__searchSpaceType_PR_common; - }else if (strcmp(SearchSpace_searchSpaceType , "ue_Specific") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).SearchSpace_searchSpaceType[j] = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for SearchSpace_searchSpaceType !\n", - RC.config_file_name, i, SearchSpace_searchSpaceType); - } - - switch(Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel1_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel1_n2; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 choice: 1,2 !\n", - RC.config_file_name, i, Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1); - break; - } - - switch(Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel2_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel2_n2; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 choice: 1,2 !\n", - RC.config_file_name, i, Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2); - break; - } - - switch(Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel4_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel4_n2; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 choice: 1,2 !\n", - RC.config_file_name, i, Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4); - break; - } - - switch(Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel8_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel8_n2; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 choice: 1,2 !\n", - RC.config_file_name, i, Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8); - break; - } - - switch(Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel16_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_0__nrofCandidates_SFI__aggregationLevel16_n2; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 choice: 1,2 !\n", - RC.config_file_name, i, Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16); - break; - } - - switch(Common_dci_Format2_3_monitoringPeriodicity){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl2; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl5; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl8; - break; - case 10: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl10; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl16; - break; - case 20: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_monitoringPeriodicity[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy1_sl20; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_3_dummy1 choice: 1,2,4,5,8,10,16,20 !\n", - RC.config_file_name, i, Common_dci_Format2_3_monitoringPeriodicity); - break; - } - - switch(Common_dci_Format2_3_nrofPDCCH_Candidates){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_nrofPDCCH_Candidates[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy2_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).Common_dci_Format2_3_nrofPDCCH_Candidates[j] = NR_SearchSpace__searchSpaceType__common__dci_Format2_3__dummy2_n2; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for Common_dci_Format2_3_nrofPDCCH_Candidates choice: 1,2 !\n", - RC.config_file_name, i, Common_dci_Format2_3_nrofPDCCH_Candidates); - break; - } - - if (strcmp(ue_Specific__dci_Formats , "formats0-0-And-1-0") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).ue_Specific__dci_Formats[j] = NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; - }else if (strcmp(ue_Specific__dci_Formats , "formats0-1-And-1-1") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).ue_Specific__dci_Formats[j] = NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_1_And_1_1; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for ue_Specific__dci_Formats !\n", - RC.config_file_name, i, ue_Specific__dci_Formats); - } - - //////////////////////////////////NR RateMatchPatternLTE-CRS/////////////////////////// - - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierFreqDL[j] = RateMatchPatternLTE_CRS_carrierFreqDL; - if ((RateMatchPatternLTE_CRS_carrierFreqDL <0) || (RateMatchPatternLTE_CRS_carrierFreqDL>16383)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPatternLTE_CRS_carrierFreqDL choice: 0..16383 !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_carrierFreqDL); - } - - - switch(RateMatchPatternLTE_CRS_carrierBandwidthDL){ - case 6: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierBandwidthDL[j] = NR_RateMatchPatternLTE_CRS__carrierBandwidthDL_n6; - break; - case 15: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierBandwidthDL[j] = NR_RateMatchPatternLTE_CRS__carrierBandwidthDL_n15; - break; - case 25: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierBandwidthDL[j] = NR_RateMatchPatternLTE_CRS__carrierBandwidthDL_n25; - break; - case 50: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierBandwidthDL[j] = NR_RateMatchPatternLTE_CRS__carrierBandwidthDL_n50; - break; - case 75: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierBandwidthDL[j] = NR_RateMatchPatternLTE_CRS__carrierBandwidthDL_n75; - break; - case 100: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_carrierBandwidthDL[j] = NR_RateMatchPatternLTE_CRS__carrierBandwidthDL_n100; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPatternLTE_CRS_carrierBandwidthDL choice: 6,15,25,50,75,100 !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_carrierBandwidthDL); - break; - } - - switch(RateMatchPatternLTE_CRS_nrofCRS_Ports){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_nrofCRS_Ports[j] = NR_RateMatchPatternLTE_CRS__nrofCRS_Ports_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_nrofCRS_Ports[j] = NR_RateMatchPatternLTE_CRS__nrofCRS_Ports_n2; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_nrofCRS_Ports[j] = NR_RateMatchPatternLTE_CRS__nrofCRS_Ports_n4; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPatternLTE_CRS_nrofCRS_Ports choice: 1,2,4 !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_nrofCRS_Ports); - break; - } - - switch(RateMatchPatternLTE_CRS_v_Shift){ - case 0: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_v_Shift[j] = NR_RateMatchPatternLTE_CRS__v_Shift_n0; - break; - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_v_Shift[j] = NR_RateMatchPatternLTE_CRS__v_Shift_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_v_Shift[j] = NR_RateMatchPatternLTE_CRS__v_Shift_n2; - break; - case 3: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_v_Shift[j] = NR_RateMatchPatternLTE_CRS__v_Shift_n3; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_v_Shift[j] = NR_RateMatchPatternLTE_CRS__v_Shift_n4; - break; - case 5: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_v_Shift[j] = NR_RateMatchPatternLTE_CRS__v_Shift_n5; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPatternLTE_CRS_v_Shift choice: 0,1,2,3,4,5 !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_v_Shift); - break; - } - - switch(RateMatchPatternLTE_CRS_radioframeAllocationPeriod){ - case 1: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationPeriod[j] = NR_EUTRA_MBSFN_SubframeConfig__radioframeAllocationPeriod_n1; - break; - case 2: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationPeriod[j] = NR_EUTRA_MBSFN_SubframeConfig__radioframeAllocationPeriod_n2; - break; - case 4: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationPeriod[j] = NR_EUTRA_MBSFN_SubframeConfig__radioframeAllocationPeriod_n4; - break; - case 8: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationPeriod[j] = NR_EUTRA_MBSFN_SubframeConfig__radioframeAllocationPeriod_n8; - break; - case 16: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationPeriod[j] = NR_EUTRA_MBSFN_SubframeConfig__radioframeAllocationPeriod_n16; - break; - case 32: - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationPeriod[j] = NR_EUTRA_MBSFN_SubframeConfig__radioframeAllocationPeriod_n32; - break; - default: - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPatternLTE_CRS_radioframeAllocationPeriod choice: 1,2,4,8,16,32 !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_radioframeAllocationPeriod); - break; - } - - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_radioframeAllocationOffset[j] = RateMatchPatternLTE_CRS_radioframeAllocationOffset; - if ((RateMatchPatternLTE_CRS_radioframeAllocationOffset <0) || (RateMatchPatternLTE_CRS_radioframeAllocationOffset>7)){ - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%d\" for RateMatchPatternLTE_CRS_radioframeAllocationOffset choice: 0..7 !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_radioframeAllocationOffset); - } - - if (strcmp(RateMatchPatternLTE_CRS_subframeAllocation_choice , "oneFrame") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_subframeAllocation_choice[j] = NR_EUTRA_MBSFN_SubframeConfig__subframeAllocation1_PR_oneFrame; - }else if (strcmp(RateMatchPatternLTE_CRS_subframeAllocation_choice , "fourFrames") == 0){ - NRRRC_CONFIGURATION_REQ (msg_p).RateMatchPatternLTE_CRS_subframeAllocation_choice[j] = NR_EUTRA_MBSFN_SubframeConfig__subframeAllocation1_PR_fourFrames; - }else { - AssertFatal (0,"Failed to parse gNB configuration file %s, gnb %d unknown value \"%s\" for RateMatchPatternLTE_CRS_subframeAllocation_choice !\n", - RC.config_file_name, i, RateMatchPatternLTE_CRS_subframeAllocation_choice); - } - - - }//End for (j = 0; j < CCsParamList.numelt ;j++) - - }//End if ( CCsParamList.numelt> 0) - - }//End for (k=0; k 0) @@ -2961,12 +977,9 @@ void NRRCConfig(void) { paramlist_def_t L1ParamList = {CONFIG_STRING_L1_LIST,NULL,0}; paramlist_def_t RUParamList = {CONFIG_STRING_RU_LIST,NULL,0}; paramdef_t GNBSParams[] = GNBSPARAMS_DESC; - paramlist_def_t CCsParamList = {GNB_CONFIG_STRING_COMPONENT_CARRIERS,NULL,0}; char aprefix[MAX_OPTNAME_SIZE*2 + 8]; - - /* get global parameters, defined outside any section in the config file */ LOG_I(GNB_APP, "Getting GNBSParams\n"); @@ -2974,28 +987,204 @@ void NRRCConfig(void) { config_get( GNBSParams,sizeof(GNBSParams)/sizeof(paramdef_t),NULL); RC.nb_nr_inst = GNBSParams[GNB_ACTIVE_GNBS_IDX].numelt; - if (RC.nb_nr_inst > 0) { - RC.nb_nr_CC = (int *)malloc((1+RC.nb_nr_inst)*sizeof(int)); - for (int i=0;i 0) { + // Output a list of all gNBs. + config_getlist( &GNBParamList,GNBParams,sizeof(GNBParams)/sizeof(paramdef_t),NULL); + + if (GNBParamList.numelt > 0) { + for (k = 0; k < GNBParamList.numelt; k++) { + if (GNBParamList.paramarray[k][GNB_GNB_ID_IDX].uptr == NULL) { + // Calculate a default eNB ID + if (EPC_MODE_ENABLED) { + uint32_t hash; + hash = s1ap_generate_eNB_id (); + gnb_id = k + (hash & 0xFFFF8); + } else { + gnb_id = k; + } + } else { + gnb_id = *(GNBParamList.paramarray[k][GNB_GNB_ID_IDX].uptr); + } + + // search if in active list + for (j = 0; j < GNBSParams[GNB_ACTIVE_GNBS_IDX].numelt; j++) { + if (strcmp(GNBSParams[GNB_ACTIVE_GNBS_IDX].strlistptr[j], *(GNBParamList.paramarray[k][GNB_GNB_NAME_IDX].strptr)) == 0) { + paramdef_t PLMNParams[] = GNBPLMNPARAMS_DESC; + paramlist_def_t PLMNParamList = {GNB_CONFIG_STRING_PLMN_LIST, NULL, 0}; + /* map parameter checking array instances to parameter definition array instances */ + checkedparam_t config_check_PLMNParams [] = PLMNPARAMS_CHECK; + + for (int I = 0; I < sizeof(PLMNParams) / sizeof(paramdef_t); ++I) + PLMNParams[I].chkPptr = &(config_check_PLMNParams[I]); + + paramdef_t X2Params[] = X2PARAMS_DESC; + paramlist_def_t X2ParamList = {ENB_CONFIG_STRING_TARGET_ENB_X2_IP_ADDRESS,NULL,0}; + paramdef_t SCTPParams[] = GNBSCTPPARAMS_DESC; + paramdef_t NETParams[] = GNBNETPARAMS_DESC; + /* TODO: fix the size - if set lower we have a crash (MAX_OPTNAME_SIZE was 64 when this code was written) */ + /* this is most probably a problem with the config module */ + char aprefix[MAX_OPTNAME_SIZE*80 + 8]; + sprintf(aprefix,"%s.[%i]",GNB_CONFIG_STRING_GNB_LIST,k); + /* Some default/random parameters */ + X2AP_REGISTER_ENB_REQ (msg_p).eNB_id = gnb_id; + + if (strcmp(*(GNBParamList.paramarray[k][GNB_CELL_TYPE_IDX].strptr), "CELL_MACRO_GNB") == 0) { + X2AP_REGISTER_ENB_REQ (msg_p).cell_type = CELL_MACRO_GNB; + }else { + AssertFatal (0, + "Failed to parse eNB configuration file %s, enb %d unknown value \"%s\" for cell_type choice: CELL_MACRO_ENB or CELL_HOME_ENB !\n", + RC.config_file_name, i, *(GNBParamList.paramarray[k][GNB_CELL_TYPE_IDX].strptr)); + } + + X2AP_REGISTER_ENB_REQ (msg_p).eNB_name = strdup(*(GNBParamList.paramarray[k][GNB_GNB_NAME_IDX].strptr)); + X2AP_REGISTER_ENB_REQ (msg_p).tac = *GNBParamList.paramarray[k][GNB_TRACKING_AREA_CODE_IDX].uptr; + config_getlist(&PLMNParamList, PLMNParams, sizeof(PLMNParams)/sizeof(paramdef_t), aprefix); + + if (PLMNParamList.numelt < 1 || PLMNParamList.numelt > 6) + AssertFatal(0, "The number of PLMN IDs must be in [1,6], but is %d\n", + PLMNParamList.numelt); + + if (PLMNParamList.numelt > 1) + LOG_W(X2AP, "X2AP currently handles only one PLMN, ignoring the others!\n"); + + X2AP_REGISTER_ENB_REQ (msg_p).mcc = *PLMNParamList.paramarray[0][GNB_MOBILE_COUNTRY_CODE_IDX].uptr; + X2AP_REGISTER_ENB_REQ (msg_p).mnc = *PLMNParamList.paramarray[0][GNB_MOBILE_NETWORK_CODE_IDX].uptr; + X2AP_REGISTER_ENB_REQ (msg_p).mnc_digit_length = *PLMNParamList.paramarray[0][GNB_MNC_DIGIT_LENGTH].u8ptr; + AssertFatal(X2AP_REGISTER_ENB_REQ(msg_p).mnc_digit_length == 3 + || X2AP_REGISTER_ENB_REQ(msg_p).mnc < 100, + "MNC %d cannot be encoded in two digits as requested (change mnc_digit_length to 3)\n", + X2AP_REGISTER_ENB_REQ(msg_p).mnc); + + X2AP_REGISTER_ENB_REQ (msg_p).num_cc = 1; + J = 0; + X2AP_REGISTER_ENB_REQ (msg_p).eutra_band[J] = 78; //ccparams_nr_x2.nr_band; //78 + X2AP_REGISTER_ENB_REQ (msg_p).downlink_frequency[J] = 3600000000; //ccparams_nr_x2.downlink_frequency; //3600000000 + X2AP_REGISTER_ENB_REQ (msg_p).uplink_frequency_offset[J] = 0; //(unsigned int) ccparams_nr_x2.uplink_frequency_offset; //0 + X2AP_REGISTER_ENB_REQ (msg_p).Nid_cell[J]= 0; //ccparams_nr_x2.Nid_cell; //0 + X2AP_REGISTER_ENB_REQ (msg_p).N_RB_DL[J]= 106; //ccparams_nr_x2.N_RB_DL; //106 + + X2AP_REGISTER_ENB_REQ (msg_p).frame_type[J] = TDD; + + //Temp out + /*X2AP_REGISTER_ENB_REQ (msg_p).fdd_earfcn_DL[J] = to_earfcn_DL(ccparams_lte.eutra_band, ccparams_lte.downlink_frequency, ccparams_lte.N_RB_DL); + X2AP_REGISTER_ENB_REQ (msg_p).fdd_earfcn_UL[J] = to_earfcn_UL(ccparams_lte.eutra_band, ccparams_lte.downlink_frequency + ccparams_lte.uplink_frequency_offset, ccparams_lte.N_RB_DL);*/ + + sprintf(aprefix,"%s.[%i]",GNB_CONFIG_STRING_GNB_LIST,k); + config_getlist( &X2ParamList,X2Params,sizeof(X2Params)/sizeof(paramdef_t),aprefix); + AssertFatal(X2ParamList.numelt <= X2AP_MAX_NB_ENB_IP_ADDRESS, + "value of X2ParamList.numelt %d must be lower than X2AP_MAX_NB_ENB_IP_ADDRESS %d value: reconsider to increase X2AP_MAX_NB_ENB_IP_ADDRESS\n", + X2ParamList.numelt,X2AP_MAX_NB_ENB_IP_ADDRESS); + X2AP_REGISTER_ENB_REQ (msg_p).nb_x2 = 0; + + for (l = 0; l < X2ParamList.numelt; l++) { + X2AP_REGISTER_ENB_REQ (msg_p).nb_x2 += 1; + strcpy(X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv4_address,*(X2ParamList.paramarray[l][ENB_X2_IPV4_ADDRESS_IDX].strptr)); + strcpy(X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv6_address,*(X2ParamList.paramarray[l][ENB_X2_IPV6_ADDRESS_IDX].strptr)); + + if (strcmp(*(X2ParamList.paramarray[l][ENB_X2_IP_ADDRESS_PREFERENCE_IDX].strptr), "ipv4") == 0) { + X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv4 = 1; + X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv6 = 0; + } else if (strcmp(*(X2ParamList.paramarray[l][ENB_X2_IP_ADDRESS_PREFERENCE_IDX].strptr), "ipv6") == 0) { + X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv4 = 0; + X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv6 = 1; + } else if (strcmp(*(X2ParamList.paramarray[l][ENB_X2_IP_ADDRESS_PREFERENCE_IDX].strptr), "no") == 0) { + X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv4 = 1; + X2AP_REGISTER_ENB_REQ (msg_p).target_enb_x2_ip_address[l].ipv6 = 1; + } + } + + // timers + { + int t_reloc_prep = 0; + int tx2_reloc_overall = 0; + paramdef_t p[] = { + { "t_reloc_prep", "t_reloc_prep", 0, iptr:&t_reloc_prep, defintval:0, TYPE_INT, 0 }, + { "tx2_reloc_overall", "tx2_reloc_overall", 0, iptr:&tx2_reloc_overall, defintval:0, TYPE_INT, 0 } + }; + config_get(p, sizeof(p)/sizeof(paramdef_t), aprefix); + + if (t_reloc_prep <= 0 || t_reloc_prep > 10000 || + tx2_reloc_overall <= 0 || tx2_reloc_overall > 20000) { + LOG_E(X2AP, "timers in configuration file have wrong values. We must have [0 < t_reloc_prep <= 10000] and [0 < tx2_reloc_overall <= 20000]\n"); + exit(1); + } + + X2AP_REGISTER_ENB_REQ (msg_p).t_reloc_prep = t_reloc_prep; + X2AP_REGISTER_ENB_REQ (msg_p).tx2_reloc_overall = tx2_reloc_overall; + } + // SCTP SETTING + X2AP_REGISTER_ENB_REQ (msg_p).sctp_out_streams = SCTP_OUT_STREAMS; + X2AP_REGISTER_ENB_REQ (msg_p).sctp_in_streams = SCTP_IN_STREAMS; + + if (EPC_MODE_ENABLED) { + sprintf(aprefix,"%s.[%i].%s",GNB_CONFIG_STRING_GNB_LIST,k,GNB_CONFIG_STRING_SCTP_CONFIG); + config_get( SCTPParams,sizeof(SCTPParams)/sizeof(paramdef_t),aprefix); + X2AP_REGISTER_ENB_REQ (msg_p).sctp_in_streams = (uint16_t)*(SCTPParams[GNB_SCTP_INSTREAMS_IDX].uptr); + X2AP_REGISTER_ENB_REQ (msg_p).sctp_out_streams = (uint16_t)*(SCTPParams[GNB_SCTP_OUTSTREAMS_IDX].uptr); + } + + sprintf(aprefix,"%s.[%i].%s",GNB_CONFIG_STRING_GNB_LIST,k,GNB_CONFIG_STRING_NETWORK_INTERFACES_CONFIG); + // NETWORK_INTERFACES + config_get( NETParams,sizeof(NETParams)/sizeof(paramdef_t),aprefix); + X2AP_REGISTER_ENB_REQ (msg_p).enb_port_for_X2C = (uint32_t)*(NETParams[GNB_PORT_FOR_X2C_IDX].uptr); + + //temp out + if ((NETParams[GNB_IPV4_ADDR_FOR_X2C_IDX].strptr == NULL) || (X2AP_REGISTER_ENB_REQ (msg_p).enb_port_for_X2C == 0)) { + LOG_E(RRC,"Add eNB IPv4 address and/or port for X2C in the CONF file!\n"); + exit(1); + } + + cidr = *(NETParams[ENB_IPV4_ADDR_FOR_X2C_IDX].strptr); + address = strtok(cidr, "/"); + X2AP_REGISTER_ENB_REQ (msg_p).enb_x2_ip_address.ipv6 = 0; + X2AP_REGISTER_ENB_REQ (msg_p).enb_x2_ip_address.ipv4 = 1; + strcpy(X2AP_REGISTER_ENB_REQ (msg_p).enb_x2_ip_address.ipv4_address, address); + } + } + } } } - - // Get num MACRLC instances - config_getlist( &MACRLCParamList,NULL,0, NULL); - RC.nb_macrlc_inst = MACRLCParamList.numelt; - // Get num L1 instances - config_getlist( &L1ParamList,NULL,0, NULL); - RC.nb_nr_L1_inst = L1ParamList.numelt; - - // Get num RU instances - config_getlist( &RUParamList,NULL,0, NULL); - RC.nb_RU = RUParamList.numelt; - - RCconfig_nr_parallel(); - - + return 0; } + + diff --git a/openair2/GNB_APP/gnb_config.h b/openair2/GNB_APP/gnb_config.h index 8320c5ccdc..e2588d9e4d 100644 --- a/openair2/GNB_APP/gnb_config.h +++ b/openair2/GNB_APP/gnb_config.h @@ -103,6 +103,7 @@ extern void NRRCConfig(void); void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc); int RCconfig_NR_S1(MessageDef *msg_p, uint32_t i); +int RCconfig_NR_X2(MessageDef *msg_p, uint32_t i); #endif /* GNB_CONFIG_H_ */ /** @} */ diff --git a/openair2/GNB_APP/gnb_paramdef.h b/openair2/GNB_APP/gnb_paramdef.h index 5b97796f8a..2d9ecb8c8a 100644 --- a/openair2/GNB_APP/gnb_paramdef.h +++ b/openair2/GNB_APP/gnb_paramdef.h @@ -111,6 +111,29 @@ typedef enum { #define GNB_CONFIG_STRING_LOCAL_S_PORTD "local_s_portd" #define GNB_CONFIG_STRING_REMOTE_S_PORTD "remote_s_portd" +typedef struct ccparams_nr_x2 { + char *frame_type; + int32_t tdd_config; + int32_t tdd_config_s; + int32_t nr_band; + long long int downlink_frequency; + int32_t uplink_frequency_offset; + int32_t Nid_cell; + int32_t N_RB_DL; + } ccparams_nr_x2_t; + + +#define CCPARAMS_NR_X2_DESC(ccparams) { \ + {ENB_CONFIG_STRING_FRAME_TYPE, NULL, 0, strptr:&ccparams.frame_type, defstrval:"TDD", TYPE_STRING, 0}, \ + {ENB_CONFIG_STRING_TDD_CONFIG, NULL, 0, iptr:&ccparams.tdd_config, defintval:3, TYPE_UINT, 0}, \ + {ENB_CONFIG_STRING_TDD_CONFIG_S, NULL, 0, iptr:&ccparams.tdd_config_s, defintval:0, TYPE_UINT, 0}, \ + {ENB_CONFIG_STRING_EUTRA_BAND, NULL, 0, iptr:&ccparams.nr_band, defintval:78, TYPE_UINT, 0}, \ + {ENB_CONFIG_STRING_DOWNLINK_FREQUENCY, NULL, 0, i64ptr:(int64_t *)&ccparams.downlink_frequency, defint64val:3600000000, TYPE_UINT64, 0}, \ + {ENB_CONFIG_STRING_UPLINK_FREQUENCY_OFFSET, NULL, 0, iptr:&ccparams.uplink_frequency_offset, defintval:0, TYPE_INT, 0}, \ + {ENB_CONFIG_STRING_NID_CELL, NULL, 0, iptr:&ccparams.Nid_cell, defintval:0, TYPE_UINT, 0}, \ + {ENB_CONFIG_STRING_N_RB_DL, NULL, 0, iptr:&ccparams.N_RB_DL, defintval:106, TYPE_UINT, 0} \ +} + /*-----------------------------------------------------------------------------------------------------------------------------------------*/ /* cell configuration parameters */ /* optname helpstr paramflags XXXptr defXXXval type numelt */ @@ -197,660 +220,7 @@ typedef enum { -/* component carries configuration parameters name */ -#define GNB_CONFIG_STRING_NB_ANT_PORTS "nb_antenna_ports" -#define GNB_CONFIG_STRING_NB_ANT_TX "nb_antennas_tx" -#define GNB_CONFIG_STRING_NB_ANT_RX "nb_antennas_rx" -#define GNB_CONFIG_STRING_TX_GAIN "tx_gain" -#define GNB_CONFIG_STRING_RX_GAIN "rx_gain" - - ///NR - //MIB -#define GNB_CONFIG_STRING_MIB_SUBCARRIERSPACINGCOMMON "MIB_subCarrierSpacingCommon" -#define GNB_CONFIG_STRING_MIB_SSB_SUBCARRIEROFFSET "MIB_ssb_SubcarrierOffset" -#define GNB_CONFIG_STRING_MIB_DMRS_TYPEA_POSITION "MIB_dmrs_TypeA_Position" -#define GNB_CONFIG_STRING_PDCCH_CONFIGSIB1 "pdcch_ConfigSIB1" - - //SIB1 -#define GNB_CONFIG_STRING_SIB1_FREQUENCYOFFSETSSB "SIB1_frequencyOffsetSSB" -#define GNB_CONFIG_STRING_SIB1_SSB_PERIODICITYSERVINGCELL "SIB1_ssb_PeriodicityServingCell" -#define GNB_CONFIG_STRING_SIB1_SS_PBCH_BLOCKPOWER "SIB1_ss_PBCH_BlockPower" - //NR FREQUENCYINFODL -#define GNB_CONFIG_STRING_ABSOLUTEFREQUENCYSSB "absoluteFrequencySSB" -#define GNB_CONFIG_STRING_DL_FREQBANDINDICATORNR "DL_FreqBandIndicatorNR" -#define GNB_CONFIG_STRING_DL_ABSOLUTEFREQUENCYPOINTA "DL_absoluteFrequencyPointA" - - //NR DL SCS-SPECIFICCARRIER -#define GNB_CONFIG_STRING_DL_OFFSETTOCARRIER "DL_offsetToCarrier" -#define GNB_CONFIG_STRING_DL_SCS_SUBCARRIERSPACING "DL_SCS_SubcarrierSpacing" -#define GNB_CONFIG_STRING_DL_CARRIERBANDWIDTH "DL_carrierBandwidth" - - // NR BWP-DOWNLINKCOMMON -#define GNB_CONFIG_STRING_DL_LOCATIONANDBANDWIDTH "DL_locationAndBandwidth" -#define GNB_CONFIG_STRING_DL_BWP_SUBCARRIERSPACING "DL_BWP_SubcarrierSpacing" -#define GNB_CONFIG_STRING_DL_BWP_PREFIX_TYPE "DL_BWP_prefix_type" - - //NR FREQUENCYINFOUL -#define GNB_CONFIG_STRING_UL_FREQBANDINDICATORNR "UL_FreqBandIndicatorNR" -#define GNB_CONFIG_STRING_UL_ABSOLUTEFREQUENCYPOINTA "UL_absoluteFrequencyPointA" -#define GNB_CONFIG_STRING_UL_ADDITIONALSPECTRUMEMISSION "UL_additionalSpectrumEmission" -#define GNB_CONFIG_STRING_UL_P_MAX "UL_p_Max" -#define GNB_CONFIG_STRING_UL_FREQUENCYSHIFT7P5KHZ "UL_frequencyShift7p5khz" - - //NR UL SCS-SPECIFICCARRIER -#define GNB_CONFIG_STRING_UL_OFFSETTOCARRIER "UL_offsetToCarrier" -#define GNB_CONFIG_STRING_UL_SCS_SUBCARRIERSPACING "UL_SCS_SubcarrierSpacing" -#define GNB_CONFIG_STRING_UL_CARRIERBANDWIDTH "UL_carrierBandwidth" - - // NR BWP-UPLINKCOMMON -#define GNB_CONFIG_STRING_UL_LOCATIONANDBANDWIDTH "UL_locationAndBandwidth" -#define GNB_CONFIG_STRING_UL_BWP_SUBCARRIERSPACING "UL_BWP_SubcarrierSpacing" -#define GNB_CONFIG_STRING_UL_BWP_PREFIX_TYPE "UL_BWP_prefix_type" -#define GNB_CONFIG_STRING_UL_TIMEALIGNMENTTIMERCOMMON "UL_timeAlignmentTimerCommon" - -#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_N_TIMINGADVANCEOFFSET "ServingCellConfigCommon_n_TimingAdvanceOffset" -#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_SSB_POSITIONSINBURST_PR "ServingCellConfigCommon_ssb_PositionsInBurst_PR" -#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_SSB_PERIODICITYSERVINGCELL "ServingCellConfigCommon_ssb_periodicityServingCell" -#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_DMRS_TYPEA_POSITION "ServingCellConfigCommon_dmrs_TypeA_Position" -#define GNB_CONFIG_STRING_NIA_SUBCARRIERSPACING "NIA_SubcarrierSpacing" -#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_SS_PBCH_BLOCKPOWER "ServingCellConfigCommon_ss_PBCH_BlockPower" - - - //NR TDD-UL-DL-CONFIGCOMMON -#define GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING "referenceSubcarrierSpacing" -#define GNB_CONFIG_STRING_DL_UL_TRANSMISSIONPERIODICITY "dl_UL_TransmissionPeriodicity" -#define GNB_CONFIG_STRING_NROFDOWNLINKSLOTS "nrofDownlinkSlots" -#define GNB_CONFIG_STRING_NROFDOWNLINKSYMBOLS "nrofDownlinkSymbols" -#define GNB_CONFIG_STRING_NROFUPLINKSLOTS "nrofUplinkSlots" -#define GNB_CONFIG_STRING_NROFUPLINKSYMBOLS "nrofUplinkSymbols" - - //NR RACH-CONFIGCOMMON -#define GNB_CONFIG_STRING_RACH_TOTALNUMBEROFRA_PREAMBLES "rach_totalNumberOfRA_Preambles" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_CHOICE "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEEIGHTH "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEFOURTH "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEHALF "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONE "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_TWO "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_FOUR "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_EIGHT "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight" -#define GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_SIXTEEN "rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen" -#define GNB_CONFIG_STRING_RACH_GROUPBCONFIGURED "rach_groupBconfigured" -#define GNB_CONFIG_STRING_RACH_RA_MSG3SIZEGROUPA "rach_ra_Msg3SizeGroupA" -#define GNB_CONFIG_STRING_RACH_MESSAGEPOWEROFFSETGROUPB "rach_messagePowerOffsetGroupB" -#define GNB_CONFIG_STRING_RACH_NUMBEROFRA_PREAMBLESGROUPA "rach_numberOfRA_PreamblesGroupA" -#define GNB_CONFIG_STRING_RACH_RA_CONTENTIONRESOLUTIONTIMER "rach_ra_ContentionResolutionTimer" -#define GNB_CONFIG_STRING_RSRP_THRESHOLDSSB "rsrp_ThresholdSSB" -#define GNB_CONFIG_STRING_RSRP_THRESHOLDSSB_SUL "rsrp_ThresholdSSB_SUL" -#define GNB_CONFIG_STRING_PRACH_ROOTSEQUENCEINDEX_CHOICE "prach_RootSequenceIndex_choice" -#define GNB_CONFIG_STRING_PRACH_ROOTSEQUENCEINDEX_L839 "prach_RootSequenceIndex_l839" -#define GNB_CONFIG_STRING_PRACH_ROOTSEQUENCEINDEX_L139 "prach_RootSequenceIndex_l139" -#define GNB_CONFIG_STRING_PRACH_MSG1_SUBCARRIERSPACING "prach_msg1_SubcarrierSpacing" -#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" -#define GNB_CONFIG_STRING_MSG3_TRANSFORMPRECODING "msg3_transformPrecoding" - //SSB-PERRACH-OCCASIONANDCB-PREAMBLESPERSSB NOT SURE - - //NR RACH-CONFIGGENERIC -#define GNB_CONFIG_STRING_PRACH_CONFIGURATIONINDEX "prach_ConfigurationIndex" -#define GNB_CONFIG_STRING_PRACH_MSG1_FDM "prach_msg1_FDM" -#define GNB_CONFIG_STRING_PRACH_MSG1_FREQUENCYSTART "prach_msg1_FrequencyStart" -#define GNB_CONFIG_STRING_ZEROCORRELATIONZONECONFIG "zeroCorrelationZoneConfig" -#define GNB_CONFIG_STRING_PREAMBLERECEIVEDTARGETPOWER "preambleReceivedTargetPower" -#define GNB_CONFIG_STRING_PREAMBLETRANSMAX "preambleTransMax" -#define GNB_CONFIG_STRING_POWERRAMPINGSTEP "powerRampingStep" -#define GNB_CONFIG_STRING_RA_RESPONSEWINDOW "ra_ResponseWindow" - - //PUSCH-CONFIGCOMMON -#define GNB_CONFIG_STRING_GROUPHOPPINGENABLEDTRANSFORMPRECODING "groupHoppingEnabledTransformPrecoding" -#define GNB_CONFIG_STRING_MSG3_DELTAPREAMBLE "msg3_DeltaPreamble" -#define GNB_CONFIG_STRING_P0_NOMINALWITHGRANT "p0_NominalWithGrant" - - ///PUSCH-TIMEDOMAINRESOURCEALLOCATION -#define GNB_CONFIG_STRING_PUSCH_TIMEDOMAINRESOURCEALLOCATION_K2 "PUSCH_TimeDomainResourceAllocation_k2" -#define GNB_CONFIG_STRING_PUSCH_TIMEDOMAINRESOURCEALLOCATION_MAPPINGTYPE "PUSCH_TimeDomainResourceAllocation_mappingType" -#define GNB_CONFIG_STRING_PUSCH_TIMEDOMAINRESOURCEALLOCATION_STARTSYMBOLANDLENGTH "PUSCH_TimeDomainResourceAllocation_startSymbolAndLength" - - //PUCCH-CONFIGCOMMON -#define GNB_CONFIG_STRING_PUCCH_RESOURCECOMMON "pucch_ResourceCommon" -#define GNB_CONFIG_STRING_PUCCH_GROUPHOPPING "pucch_GroupHopping" -#define GNB_CONFIG_STRING_HOPPINGID "hoppingId" -#define GNB_CONFIG_STRING_P0_NOMINAL "p0_nominal" - - //PDSCH-CONFIGCOMMON - //PDSCH-TIMEDOMAINRESOURCEALLOCATION -#define GNB_CONFIG_STRING_PDSCH_TIMEDOMAINRESOURCEALLOCATION_K0 "PDSCH_TimeDomainResourceAllocation_k0" -#define GNB_CONFIG_STRING_PDSCH_TIMEDOMAINRESOURCEALLOCATION_MAPPINGTYPE "PDSCH_TimeDomainResourceAllocation_mappingType" -#define GNB_CONFIG_STRING_PDSCH_TIMEDOMAINRESOURCEALLOCATION_STARTSYMBOLANDLENGTH "PDSCH_TimeDomainResourceAllocation_startSymbolAndLength" - //RATEMATCHPATTERN IS USED TO CONFIGURE ONE RATE MATCHING PATTERN FOR PDSCH -#define GNB_CONFIG_STRING_RATEMATCHPATTERNID "rateMatchPatternId" -#define GNB_CONFIG_STRING_RATEMATCHPATTERN_PATTERNTYPE "RateMatchPattern_patternType" -#define GNB_CONFIG_STRING_SYMBOLSINRESOURCEBLOCK "symbolsInResourceBlock" -#define GNB_CONFIG_STRING_PERIODICITYANDPATTERN "periodicityAndPattern" -#define GNB_CONFIG_STRING_RATEMATCHPATTERN_CONTROLRESOURCESET "RateMatchPattern_controlResourceSet" -#define GNB_CONFIG_STRING_RATEMATCHPATTERN_SUBCARRIERSPACING "RateMatchPattern_subcarrierSpacing" -#define GNB_CONFIG_STRING_RATEMATCHPATTERN_MODE "RateMatchPattern_mode" - - //PDCCH-CONFIGCOMMON -#define GNB_CONFIG_STRING_CONTROLRESOURCESETZERO "controlResourceSetZero" -#define GNB_CONFIG_STRING_SEARCHSPACEZERO "searchSpaceZero" -#define GNB_CONFIG_STRING_SEARCHSPACESIB1 "searchSpaceSIB1" -#define GNB_CONFIG_STRING_SEARCHSPACEOTHERSYSTEMINFORMATION "searchSpaceOtherSystemInformation" -#define GNB_CONFIG_STRING_PAGINGSEARCHSPACE "pagingSearchSpace" -#define GNB_CONFIG_STRING_RA_SEARCHSPACE "ra_SearchSpace" - //NR PDCCH-CONFIGCOMMON COMMONCONTROLRESOURCESSETS -#define GNB_CONFIG_STRING_PDCCH_COMMON_CONTROLRESOURCESETID "PDCCH_common_controlResourceSetId" -#define GNB_CONFIG_STRING_PDCCH_COMMON_CONTROLRESOURCESET_DURATION "PDCCH_common_ControlResourceSet_duration" -#define GNB_CONFIG_STRING_PDCCH_CCE_REG_MAPPINGTYPE "PDCCH_cce_REG_MappingType" -#define GNB_CONFIG_STRING_PDCCH_REG_BUNDLESIZE "PDCCH_reg_BundleSize" -#define GNB_CONFIG_STRING_PDCCH_INTERLEAVERSIZE "PDCCH_interleaverSize" -#define GNB_CONFIG_STRING_PDCCH_SHIFTINDEX "PDCCH_shiftIndex" -#define GNB_CONFIG_STRING_PDCCH_PRECODERGRANULARITY "PDCCH_precoderGranularity" -#define GNB_CONFIG_STRING_PDCCH_TCI_STATEID "PDCCH_TCI_StateId" -#define GNB_CONFIG_STRING_TCI_PRESENTINDCI "tci_PresentInDCI" -#define GNB_CONFIG_STRING_PDCCH_DMRS_SCRAMBLINGID "pdcch_DMRS_ScramblingID" - - //NR PDCCH-ConfigCommon commonSearchSpaces -#define GNB_CONFIG_STRING_SEARCHSPACEID "SearchSpaceId" -#define GNB_CONFIG_STRING_COMMONSEARCHSPACES_CONTROLRESOURCESETID "commonSearchSpaces_controlResourceSetId" -#define GNB_CONFIG_STRING_SEARCHSPACE_MONITORINGSLOTPERIODICITYANDOFFSET_CHOICE "SearchSpace_monitoringSlotPeriodicityAndOffset_choice" -#define GNB_CONFIG_STRING_SEARCHSPACE_MONITORINGSLOTPERIODICITYANDOFFSET_VALUE "SearchSpace_monitoringSlotPeriodicityAndOffset_value" -#define GNB_CONFIG_STRING_SEARCHSPACE_DURATION "SearchSpace_duration" -#define GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL1 "SearchSpace_nrofCandidates_aggregationLevel1" -#define GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL2 "SearchSpace_nrofCandidates_aggregationLevel2" -#define GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL4 "SearchSpace_nrofCandidates_aggregationLevel4" -#define GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL8 "SearchSpace_nrofCandidates_aggregationLevel8" -#define GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL16 "SearchSpace_nrofCandidates_aggregationLevel16" -#define GNB_CONFIG_STRING_SEARCHSPACE_SEARCHSPACETYPE "SearchSpace_searchSpaceType" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL1 "Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL2 "Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL4 "Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL8 "Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL16 "Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_3_MONITORINGPERIODICITY "Common_dci_Format2_3_monitoringPeriodicity" -#define GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_3_NROFPDCCH_CANDIDATES "Common_dci_Format2_3_nrofPDCCH_Candidates" -#define GNB_CONFIG_STRING_UE_SPECIFIC__DCI_FORMATS "ue_Specific__dci_Formats" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_CARRIERFREQDL "RateMatchPatternLTE_CRS_carrierFreqDL" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_CARRIERBANDWIDTHDL "RateMatchPatternLTE_CRS_carrierBandwidthDL" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_NROFCRS_PORTS "RateMatchPatternLTE_CRS_nrofCRS_Ports" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_V_SHIFT "RateMatchPatternLTE_CRS_v_Shift" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_RADIOFRAMEALLOCATIONPERIOD "RateMatchPatternLTE_CRS_radioframeAllocationPeriod" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_RADIOFRAMEALLOCATIONOFFSET "RateMatchPatternLTE_CRS_radioframeAllocationOffset" -#define GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_SUBFRAMEALLOCATION_CHOICE "RateMatchPatternLTE_CRS_subframeAllocation_choice" - -/* init for checkedparam_t structure */ - -#define NRCCPARAMS_CHECK { \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ - { .s5= {NULL }} , \ -} - - -/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ -/* component carriers configuration parameters */ -/* optname helpstr paramflags XXXptr defXXXval type numelt checked_param */ -/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ -#define NRCCPARAMS_DESC { \ -{GNB_CONFIG_STRING_FRAME_TYPE, NULL, 0, strptr:&frame_type, defstrval:"TDD", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_DL_PREFIX_TYPE, NULL, 0, strptr:&DL_prefix_type, defstrval:"NORMAL", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_UL_PREFIX_TYPE, NULL, 0, strptr:&UL_prefix_type, defstrval:"NORMAL", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_NR_BAND, NULL, 0, iptr:&nr_band, defintval:78, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DOWNLINK_FREQUENCY, NULL, 0, i64ptr:(int64_t *)&downlink_frequency, defint64val:3600000000, TYPE_UINT64, 0}, \ -{GNB_CONFIG_STRING_UPLINK_FREQUENCY_OFFSET, NULL, 0, iptr:&uplink_frequency_offset, defintval:0, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_NID_CELL, NULL, 0, iptr:&Nid_cell, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_N_RB_DL, NULL, 0, iptr:&N_RB_DL, defintval:25, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_NB_ANT_PORTS, NULL, 0, iptr:&nb_antenna_ports, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_MIB_SUBCARRIERSPACINGCOMMON, NULL, 0, iptr:&MIB_subCarrierSpacingCommon, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_MIB_SSB_SUBCARRIEROFFSET, NULL, 0, iptr:&MIB_ssb_SubcarrierOffset, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_MIB_DMRS_TYPEA_POSITION, NULL, 0, iptr:&MIB_dmrs_TypeA_Position, defintval:2, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_CONFIGSIB1, NULL, 0, iptr:&pdcch_ConfigSIB1, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SIB1_FREQUENCYOFFSETSSB, NULL, 0, strptr:&SIB1_frequencyOffsetSSB, defstrval:"khz5", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_SIB1_SSB_PERIODICITYSERVINGCELL, NULL, 0, iptr:&SIB1_ssb_PeriodicityServingCell, defintval:5, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SIB1_SS_PBCH_BLOCKPOWER, NULL, 0, iptr:&SIB1_ss_PBCH_BlockPower, defintval:-60, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_ABSOLUTEFREQUENCYSSB, NULL, 0, iptr:&absoluteFrequencySSB, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DL_FREQBANDINDICATORNR, NULL, 0, iptr:&DL_FreqBandIndicatorNR, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DL_ABSOLUTEFREQUENCYPOINTA, NULL, 0, iptr:&DL_absoluteFrequencyPointA, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DL_OFFSETTOCARRIER, NULL, 0, iptr:&DL_offsetToCarrier, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DL_SCS_SUBCARRIERSPACING, NULL, 0, strptr:&DL_SCS_SubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_DL_CARRIERBANDWIDTH, NULL, 0, iptr:&DL_carrierBandwidth, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DL_LOCATIONANDBANDWIDTH, NULL, 0, iptr:&DL_locationAndBandwidth, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_DL_BWP_SUBCARRIERSPACING, NULL, 0, strptr:&DL_BWP_SubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_DL_BWP_PREFIX_TYPE, NULL, 0, strptr:&DL_BWP_prefix_type, defstrval:"NORMAL", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_UL_FREQBANDINDICATORNR, NULL, 0, iptr:&UL_FreqBandIndicatorNR, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UL_ABSOLUTEFREQUENCYPOINTA, NULL, 0, iptr:&UL_absoluteFrequencyPointA, defintval:13, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UL_ADDITIONALSPECTRUMEMISSION, NULL, 0, iptr:&UL_additionalSpectrumEmission, defintval:3, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UL_P_MAX, NULL, 0, iptr:&UL_p_Max, defintval:-1, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_UL_FREQUENCYSHIFT7P5KHZ, NULL, 0, strptr:&UL_frequencyShift7p5khz, defstrval:"TRUE", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_UL_OFFSETTOCARRIER, NULL, 0, iptr:&UL_offsetToCarrier, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UL_SCS_SUBCARRIERSPACING, NULL, 0, strptr:&UL_SCS_SubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_UL_CARRIERBANDWIDTH, NULL, 0, iptr:&UL_carrierBandwidth, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UL_LOCATIONANDBANDWIDTH, NULL, 0, iptr:&UL_locationAndBandwidth, defintval:15, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UL_BWP_SUBCARRIERSPACING, NULL, 0, strptr:&UL_BWP_SubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_UL_BWP_PREFIX_TYPE, NULL, 0, strptr:&UL_BWP_prefix_type, defstrval:"NORMAL", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_UL_TIMEALIGNMENTTIMERCOMMON, NULL, 0, strptr:&UL_timeAlignmentTimerCommon, defstrval:"infinity", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_N_TIMINGADVANCEOFFSET, NULL, 0, strptr:&ServingCellConfigCommon_n_TimingAdvanceOffset, defstrval:"n0", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_SSB_POSITIONSINBURST_PR, NULL, 0, i64ptr:(int64_t *)&ServingCellConfigCommon_ssb_PositionsInBurst_PR, defint64val:0, TYPE_UINT64, 0}, \ -{GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_SSB_PERIODICITYSERVINGCELL, NULL, 0, iptr:&ServingCellConfigCommon_ssb_periodicityServingCell, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_DMRS_TYPEA_POSITION, NULL, 0, iptr:&ServingCellConfigCommon_dmrs_TypeA_Position, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_NIA_SUBCARRIERSPACING, NULL, 0, strptr:&NIA_SubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON_SS_PBCH_BLOCKPOWER, NULL, 0, iptr:&ServingCellConfigCommon_ss_PBCH_BlockPower, defintval:-60, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING, NULL, 0, strptr:&referenceSubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_DL_UL_TRANSMISSIONPERIODICITY, NULL, 0, strptr:&dl_UL_TransmissionPeriodicity, defstrval:"ms0p5", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_NROFDOWNLINKSLOTS, NULL, 0, iptr:&nrofDownlinkSlots, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_NROFDOWNLINKSYMBOLS, NULL, 0, iptr:&nrofDownlinkSymbols, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_NROFUPLINKSLOTS, NULL, 0, iptr:&nrofUplinkSlots, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_NROFUPLINKSYMBOLS, NULL, 0, iptr:&nrofUplinkSymbols, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_TOTALNUMBEROFRA_PREAMBLES, NULL, 0, iptr:&rach_totalNumberOfRA_Preambles, defintval:63, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_CHOICE, NULL, 0, strptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice, defstrval:"oneEighth", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEEIGHTH, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth, defintval:4, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEFOURTH, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth, defintval:8, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEHALF, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf, defintval:16, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONE, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one, defintval:24, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_TWO, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two, defintval:32, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_FOUR, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four, defintval:8, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_EIGHT, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight, defintval:4, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_SIXTEEN, NULL, 0, iptr:&rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen, defintval:2, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_GROUPBCONFIGURED, NULL, 0, strptr:&rach_groupBconfigured, defstrval:"ENABLE", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RACH_RA_MSG3SIZEGROUPA, NULL, 0, iptr:&rach_ra_Msg3SizeGroupA, defintval:56, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_MESSAGEPOWEROFFSETGROUPB, NULL, 0, strptr:&rach_messagePowerOffsetGroupB, defstrval:"dB0", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RACH_NUMBEROFRA_PREAMBLESGROUPA, NULL, 0, iptr:&rach_numberOfRA_PreamblesGroupA, defintval:32, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RACH_RA_CONTENTIONRESOLUTIONTIMER, NULL, 0, iptr:&rach_ra_ContentionResolutionTimer, defintval:8, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RSRP_THRESHOLDSSB, NULL, 0, iptr:&rsrp_ThresholdSSB, defintval:64, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RSRP_THRESHOLDSSB_SUL, NULL, 0, iptr:&rsrp_ThresholdSSB_SUL, defintval:64, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PRACH_ROOTSEQUENCEINDEX_CHOICE, NULL, 0, strptr:&prach_RootSequenceIndex_choice, defstrval:"l839", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PRACH_ROOTSEQUENCEINDEX_L839, NULL, 0, iptr:&prach_RootSequenceIndex_l839, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PRACH_ROOTSEQUENCEINDEX_L139, NULL, 0, iptr:&prach_RootSequenceIndex_l139, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PRACH_MSG1_SUBCARRIERSPACING, NULL, 0, strptr:&prach_msg1_SubcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RESTRICTEDSETCONFIG, NULL, 0, strptr:&restrictedSetConfig, defstrval:"unrestrictedSet", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_MSG3_TRANSFORMPRECODING, NULL, 0, strptr:&msg3_transformPrecoding, defstrval:"ENABLE", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PRACH_CONFIGURATIONINDEX, NULL, 0, iptr:&prach_ConfigurationIndex, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PRACH_MSG1_FDM, NULL, 0, strptr:&prach_msg1_FDM, defstrval:"one", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PRACH_MSG1_FREQUENCYSTART, NULL, 0, iptr:&prach_msg1_FrequencyStart, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_ZEROCORRELATIONZONECONFIG, NULL, 0, iptr:&zeroCorrelationZoneConfig, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PREAMBLERECEIVEDTARGETPOWER, NULL, 0, iptr:&preambleReceivedTargetPower, defintval:-150, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_PREAMBLETRANSMAX, NULL, 0, iptr:&preambleTransMax, defintval:6, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_POWERRAMPINGSTEP, NULL, 0, strptr:&powerRampingStep, defstrval:"dB0", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RA_RESPONSEWINDOW, NULL, 0, iptr:&ra_ResponseWindow, defintval:8, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_GROUPHOPPINGENABLEDTRANSFORMPRECODING, NULL, 0, strptr:&groupHoppingEnabledTransformPrecoding, defstrval:"ENABLE", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_MSG3_DELTAPREAMBLE, NULL, 0, iptr:&msg3_DeltaPreamble, defintval:0, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_P0_NOMINALWITHGRANT, NULL, 0, iptr:&p0_NominalWithGrant, defintval:0, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_PUSCH_TIMEDOMAINRESOURCEALLOCATION_K2, NULL, 0, iptr:&PUSCH_TimeDomainResourceAllocation_k2, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PUSCH_TIMEDOMAINRESOURCEALLOCATION_MAPPINGTYPE, NULL, 0, strptr:&PUSCH_TimeDomainResourceAllocation_mappingType, defstrval:"typeA", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PUSCH_TIMEDOMAINRESOURCEALLOCATION_STARTSYMBOLANDLENGTH, NULL, 0, iptr:&PUSCH_TimeDomainResourceAllocation_startSymbolAndLength, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PUCCH_RESOURCECOMMON, NULL, 0, iptr:&pucch_ResourceCommon, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PUCCH_GROUPHOPPING, NULL, 0, strptr:&pucch_GroupHopping, defstrval:"neither", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_HOPPINGID, NULL, 0, iptr:&hoppingId, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_P0_NOMINAL, NULL, 0, iptr:&p0_nominal, defintval:-30, TYPE_INT, 0}, \ -{GNB_CONFIG_STRING_PDSCH_TIMEDOMAINRESOURCEALLOCATION_K0, NULL, 0, iptr:&PDSCH_TimeDomainResourceAllocation_k0, defintval:2, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDSCH_TIMEDOMAINRESOURCEALLOCATION_MAPPINGTYPE, NULL, 0, strptr:&PDSCH_TimeDomainResourceAllocation_mappingType, defstrval:"typeA", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PDSCH_TIMEDOMAINRESOURCEALLOCATION_STARTSYMBOLANDLENGTH, NULL, 0, iptr:&PDSCH_TimeDomainResourceAllocation_startSymbolAndLength, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNID, NULL, 0, iptr:&rateMatchPatternId, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERN_PATTERNTYPE, NULL, 0, strptr:&RateMatchPattern_patternType, defstrval:"bitmaps", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_SYMBOLSINRESOURCEBLOCK, NULL, 0, strptr:&symbolsInResourceBlock, defstrval:"oneSlot", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PERIODICITYANDPATTERN, NULL, 0, iptr:&periodicityAndPattern, defintval:2, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERN_CONTROLRESOURCESET, NULL, 0, iptr:&RateMatchPattern_controlResourceSet, defintval:5, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERN_SUBCARRIERSPACING, NULL, 0, strptr:&RateMatchPattern_subcarrierSpacing, defstrval:"kHz15", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERN_MODE, NULL, 0, strptr:&RateMatchPattern_mode, defstrval:"dynamic", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_CONTROLRESOURCESETZERO, NULL, 0, iptr:&controlResourceSetZero, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACEZERO, NULL, 0, iptr:&searchSpaceZero, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACESIB1, NULL, 0, iptr:&searchSpaceSIB1, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACEOTHERSYSTEMINFORMATION, NULL, 0, iptr:&searchSpaceOtherSystemInformation, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PAGINGSEARCHSPACE, NULL, 0, iptr:&pagingSearchSpace, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RA_SEARCHSPACE, NULL, 0, iptr:&ra_SearchSpace, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_COMMON_CONTROLRESOURCESETID, NULL, 0, iptr:&PDCCH_common_controlResourceSetId, defintval:5, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_COMMON_CONTROLRESOURCESET_DURATION, NULL, 0, iptr:&PDCCH_common_ControlResourceSet_duration, defintval:2, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_CCE_REG_MAPPINGTYPE, NULL, 0, strptr:&PDCCH_cce_REG_MappingType, defstrval:"nonInterleaved", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PDCCH_REG_BUNDLESIZE, NULL, 0, iptr:&PDCCH_reg_BundleSize, defintval:3, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_INTERLEAVERSIZE, NULL, 0, iptr:&PDCCH_interleaverSize, defintval:3, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_SHIFTINDEX, NULL, 0, iptr:&PDCCH_shiftIndex, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_PDCCH_PRECODERGRANULARITY, NULL, 0, strptr:&PDCCH_precoderGranularity, defstrval:"sameAsREG-bundle", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PDCCH_TCI_STATEID, NULL, 0, iptr:&PDCCH_TCI_StateId, defintval:32, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_TCI_PRESENTINDCI, NULL, 0, strptr:&tci_PresentInDCI, defstrval:"ENABLE", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_PDCCH_DMRS_SCRAMBLINGID, NULL, 0, iptr:&PDCCH_DMRS_ScramblingID, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACEID, NULL, 0, iptr:&SearchSpaceId, defintval:10, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMONSEARCHSPACES_CONTROLRESOURCESETID, NULL, 0, iptr:&commonSearchSpaces_controlResourceSetId, defintval:5, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_MONITORINGSLOTPERIODICITYANDOFFSET_CHOICE, NULL, 0, strptr:&SearchSpace_monitoringSlotPeriodicityAndOffset_choice, defstrval:"sl1", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_MONITORINGSLOTPERIODICITYANDOFFSET_VALUE, NULL, 0, iptr:&SearchSpace_monitoringSlotPeriodicityAndOffset_value, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_DURATION, NULL, 0, iptr:&SearchSpace_duration, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL1, NULL, 0, iptr:&SearchSpace_nrofCandidates_aggregationLevel1, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL2, NULL, 0, iptr:&SearchSpace_nrofCandidates_aggregationLevel2, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL4, NULL, 0, iptr:&SearchSpace_nrofCandidates_aggregationLevel4, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL8, NULL, 0, iptr:&SearchSpace_nrofCandidates_aggregationLevel8, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL16, NULL, 0, iptr:&SearchSpace_nrofCandidates_aggregationLevel16, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SEARCHSPACE_SEARCHSPACETYPE, NULL, 0, strptr:&SearchSpace_searchSpaceType, defstrval:"common", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL1, NULL, 0, iptr:&Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL2, NULL, 0, iptr:&Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL4, NULL, 0, iptr:&Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL8, NULL, 0, iptr:&Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL16, NULL, 0, iptr:&Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_3_MONITORINGPERIODICITY, NULL, 0, iptr:&Common_dci_Format2_3_monitoringPeriodicity, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_COMMON_DCI_FORMAT2_3_NROFPDCCH_CANDIDATES, NULL, 0, iptr:&Common_dci_Format2_3_nrofPDCCH_Candidates, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_UE_SPECIFIC__DCI_FORMATS, NULL, 0, strptr:&ue_Specific__dci_Formats, defstrval:"formats0-0-And-1-0", TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_CARRIERFREQDL, NULL, 0, iptr:&RateMatchPatternLTE_CRS_carrierFreqDL, defintval:6, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_CARRIERBANDWIDTHDL, NULL, 0, iptr:&RateMatchPatternLTE_CRS_carrierBandwidthDL, defintval:6, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_NROFCRS_PORTS, NULL, 0, iptr:&RateMatchPatternLTE_CRS_nrofCRS_Ports, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_V_SHIFT, NULL, 0, iptr:&RateMatchPatternLTE_CRS_v_Shift, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_RADIOFRAMEALLOCATIONPERIOD, NULL, 0, iptr:&RateMatchPatternLTE_CRS_radioframeAllocationPeriod, defintval:1, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_RADIOFRAMEALLOCATIONOFFSET, NULL, 0, iptr:&RateMatchPatternLTE_CRS_radioframeAllocationOffset, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_RATEMATCHPATTERNLTE_CRS_SUBFRAMEALLOCATION_CHOICE, NULL, 0, strptr:&RateMatchPatternLTE_CRS_subframeAllocation_choice, defstrval:"oneFrame", TYPE_STRING, 0}, \ -} - - -/* component carries configuration parameters name */ -#define GNB_CONFIG_FRAME_TYPE_IDX 0 -#define GNB_CONFIG_DL_PREFIX_TYPE_IDX 1 -#define GNB_CONFIG_UL_PREFIX_TYPE_IDX 2 -#define GNB_CONFIG_NR_BAND_IDX 3 -#define GNB_CONFIG_DOWNLINK_FREQUENCY_IDX 4 -#define GNB_CONFIG_UPLINK_FREQUENCY_OFFSET_IDX 5 -#define GNB_CONFIG_NID_CELL_IDX 6 -#define GNB_CONFIG_N_RB_DL_IDX 7 -#define GNB_CONFIG_NB_ANT_PORTS_IDX 8 -#define GNB_CONFIG_NB_ANT_TX_IDX 9 -#define GNB_CONFIG_NB_ANT_RX_IDX 10 -#define GNB_CONFIG_TX_GAIN_IDX 11 -#define GNB_CONFIG_RX_GAIN_IDX 12 -#define GNB_CONFIG_MIB_SUBCARRIERSPACINGCOMMON_IDX 13 -#define GNB_CONFIG_MIB_SSB_SUBCARRIEROFFSET_IDX 14 -#define GNB_CONFIG_MIB_DMRS_TYPEA_POSITION_IDX 15 -#define GNB_CONFIG_PDCCH_CONFIGSIB1_IDX 16 -#define GNB_CONFIG_SIB1_FREQUENCYOFFSETSSB_IDX 17 -#define GNB_CONFIG_SIB1_SSB_PERIODICITYSERVINGCELL_IDX 18 -#define GNB_CONFIG_SIB1_SS_PBCH_BLOCKPOWER_IDX 19 -#define GNB_CONFIG_ABSOLUTEFREQUENCYSSB_IDX 20 -#define GNB_CONFIG_DL_FREQBANDINDICATORNR_IDX 22 -#define GNB_CONFIG_DL_ABSOLUTEFREQUENCYPOINTA_IDX 23 -#define GNB_CONFIG_DL_OFFSETTOCARRIER_IDX 24 -#define GNB_CONFIG_DL_SUBCARRIERSPACING_IDX 25 -#define GNB_CONFIG_DL_CARRIERBANDWIDTH_IDX 27 -#define GNB_CONFIG_DL_LOCATIONANDBANDWIDTH_IDX 28 -#define GNB_CONFIG_DL_BWP_SUBCARRIERSPACING_IDX 29 -#define GNB_CONFIG_DL_BWP_PREFIX_TYPE_IDX 30 -#define GNB_CONFIG_UL_FREQBANDINDICATORNR_IDX 31 -#define GNB_CONFIG_UL_ABSOLUTEFREQUENCYPOINTA_IDX 32 -#define GNB_CONFIG_UL_ADDITIONALSPECTRUMEMISSION_IDX 33 -#define GNB_CONFIG_UL_P_MAX_IDX 34 -#define GNB_CONFIG_UL_FREQUENCYSHIFT7P5KHZ_IDX 35 -#define GNB_CONFIG_UL_OFFSETTOCARRIER_IDX 36 -#define GNB_CONFIG_UL_SCS_SUBCARRIERSPACING_IDX 37 -#define GNB_CONFIG_UL_CARRIERBANDWIDTH_IDX 39 -#define GNB_CONFIG_UL_LOCATIONANDBANDWIDTH_IDX 41 -#define GNB_CONFIG_UL_BWP_SUBCARRIERSPACING_IDX 42 -#define GNB_CONFIG_UL_BWP_PREFIX_TYPE_IDX 43 -#define GNB_CONFIG_TIMEALIGNMENTTIMERCOMMON_IDX 44 -#define GNB_CONFIG_SERVINGCELLCONFIGCOMMON_N_TIMINGADVANCEOFFSET_IDX -#define GNB_CONFIG_SERVINGCELLCONFIGCOMMON_SSB_POSITIONSINBURST_PR_IDX 45 -#define GNB_CONFIG_SERVINGCELLCONFIGCOMMON_SSB_PERIODICITYSERVINGCELL_IDX 46 -#define GNB_CONFIG_SERVINGCELLCONFIGCOMMON_DMRS_TYPEA_POSITION_IDX 47 -#define GNB_CONFIG_NIA_SUBCARRIERSPACING_IDX 48 -#define GNB_CONFIG_SERVINGCELLCONFIGCOMMON_SS_PBCH_BLOCKPOWER_IDX 49 -#define GNB_CONFIG_REFERENCESUBCARRIERSPACING_IDX 50 -#define GNB_CONFIG_DL_UL_TRANSMISSIONPERIODICITY_IDX 51 -#define GNB_CONFIG_NROFDOWNLINKSLOTS_IDX 52 -#define GNB_CONFIG_NROFDOWNLINKSYMBOLS_IDX 53 -#define GNB_CONFIG_NROFUPLINKSLOTS_IDX 54 -#define GNB_CONFIG_NROFUPLINKSYMBOLS_IDX 55 -#define GNB_CONFIG_RACH_TOTALNUMBEROFRA_PREAMBLES_IDX 56 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_CHOICE_IDX 57 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEEIGHTH_IDX 58 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEFOURTH_IDX 59 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONEHALF_IDX 60 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_ONE_IDX 61 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_TWO_IDX 62 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_FOUR_IDX 63 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_EIGHT_IDX 64 -#define GNB_CONFIG_RACH_SSB_PERRACH_OCCASIONANDCB_PREAMBLESPERSSB_SIXTEEN_IDX 65 -#define GNB_CONFIG_RACH_GROUPBCONFIGURED_IDX 66 -#define GNB_CONFIG_RACH_RA_MSG3SIZEGROUPA_IDX 67 -#define GNB_CONFIG_RACH_MESSAGEPOWEROFFSETGROUPB_IDX 68 -#define GNB_CONFIG_RACH_NUMBEROFRA_PREAMBLESGROUPA_IDX 69 -#define GNB_CONFIG_RACH_RA_CONTENTIONRESOLUTIONTIMER_IDX 70 -#define GNB_CONFIG_RSRP_THRESHOLDSSB_IDX 71 -#define GNB_CONFIG_RSRP_THRESHOLDSSB_SUL_IDX 72 -#define GNB_CONFIG_PRACH_ROOTSEQUENCEINDEX_CHOICE_IDX 73 -#define GNB_CONFIG_PRACH_ROOTSEQUENCEINDEX_L839_IDX 74 -#define GNB_CONFIG_PRACH_ROOTSEQUENCEINDEX_L139_IDX 75 -#define GNB_CONFIG_PRACH_MSG1_SUBCARRIERSPACING_IDX 76 -#define GNB_CONFIG_RESTRICTEDSETCONFIG_IDX 77 -#define GNB_CONFIG_MSG3_TRANSFORMPRECODING_IDX 78 -#define GNB_CONFIG_PRACH_CONFIGURATIONINDEX_IDX 79 -#define GNB_CONFIG_PRACH_MSG1_FDM_IDX 80 -#define GNB_CONFIG_PRACH_MSG1_FREQUENCYSTART_IDX 81 -#define GNB_CONFIG_ZEROCORRELATIONZONECONFIG_IDX 82 -#define GNB_CONFIG_PREAMBLERECEIVEDTARGETPOWER_IDX 83 -#define GNB_CONFIG_PREAMBLETRANSMAX_IDX 84 -#define GNB_CONFIG_POWERRAMPINGSTEP_IDX 85 -#define GNB_CONFIG_RA_RESPONSEWINDOW_IDX 86 -#define GNB_CONFIG_GROUPHOPPINGENABLEDTRANSFORMPRECODING_IDX 87 -#define GNB_CONFIG_MSG3_DELTAPREAMBLE_IDX 88 -#define GNB_CONFIG_P0_NOMINALWITHGRANT_IDX 89 -#define GNB_CONFIG_PUSCH_TIMEDOMAINRESOURCEALLOCATION_K2_IDX 90 -#define GNB_CONFIG_PUSCH_TIMEDOMAINRESOURCEALLOCATION_MAPPINGTYPE_IDX 91 -#define GNB_CONFIG_PUSCH_TIMEDOMAINRESOURCEALLOCATION_STARTSYMBOLANDLENGTH_IDX 92 -#define GNB_CONFIG_PUCCH_RESOURCECOMMON_IDX 93 -#define GNB_CONFIG_PUCCH_GROUPHOPPING_IDX 94 -#define GNB_CONFIG_HOPPINGID_IDX 95 -#define GNB_CONFIG_P0_NOMINAL_IDX 96 -#define GNB_CONFIG_PDSCH_TIMEDOMAINRESOURCEALLOCATION_K0_IDX 97 -#define GNB_CONFIG_PDSCH_TIMEDOMAINRESOURCEALLOCATION_MAPPINGTYPE_IDX 98 -#define GNB_CONFIG_PDSCH_TIMEDOMAINRESOURCEALLOCATION_STARTSYMBOLANDLENGTH -#define GNB_CONFIG_RATEMATCHPATTERNID_IDX 99 -#define GNB_CONFIG_RATEMATCHPATTERN_PATTERNTYPE_IDX 100 -#define GNB_CONFIG_SYMBOLSINRESOURCEBLOCK_IDX 101 -#define GNB_CONFIG_PERIODICITYANDPATTERN_IDX 102 -#define GNB_CONFIG_RATEMATCHPATTERN_CONTROLRESOURCESET_IDX 103 -#define GNB_CONFIG_RATEMATCHPATTERN_SUBCARRIERSPACING_IDX 104 -#define GNB_CONFIG_RATEMATCHPATTERN_MODE_IDX 105 -#define GNB_CONFIG_CONTROLRESOURCESETZERO_IDX 106 -#define GNB_CONFIG_SEARCHSPACEZERO_IDX 107 -#define GNB_CONFIG_SEARCHSPACESIB1_IDX 108 -#define GNB_CONFIG_SEARCHSPACEOTHERSYSTEMINFORMATION_IDX 109 -#define GNB_CONFIG_PAGINGSEARCHSPACE_IDX 110 -#define GNB_CONFIG_RA_SEARCHSPACE_IDX 111 -#define GNB_CONFIG_PDCCH_COMMON_CONTROLRESOURCESETID_IDX 112 -#define GNB_CONFIG_PDCCH_COMMON_CONTROLRESOURCESET_DURATION_IDX 113 -#define GNB_CONFIG_PDCCH_CCE_REG_MAPPINGTYPE_IDX 114 -#define GNB_CONFIG_PDCCH_REG_BUNDLESIZE_IDX 115 -#define GNB_CONFIG_PDCCH_INTERLEAVERSIZE_IDX 116 -#define GNB_CONFIG_PDCCH_SHIFTINDEX_IDX 117 -#define GNB_CONFIG_PDCCH_PRECODERGRANULARITY_IDX 118 -#define GNB_CONFIG_PDCCH_TCI_STATEID_IDX 119 -#define GNB_CONFIG_TCI_PRESENTINDCI_IDX 120 -#define GNB_CONFIG_PDCCH_DMRS_SCRAMBLINGID_IDX 121 -#define GNB_CONFIG_SEARCHSPACEID_IDX 122 -#define GNB_CONFIG_COMMONSEARCHSPACES_CONTROLRESOURCESETID_IDX 123 -#define GNB_CONFIG_SEARCHSPACE_MONITORINGSLOTPERIODICITYANDOFFSET_CHOICE_IDX 124 -#define GNB_CONFIG_SEARCHSPACE_MONITORINGSLOTPERIODICITYANDOFFSET_VALUE_IDX 125 -#define GNB_CONFIG_SEARCHSPACE_DURATION_IDX 126 -#define GNB_CONFIG_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL1_IDX 127 -#define GNB_CONFIG_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL2_IDX 128 -#define GNB_CONFIG_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL4_IDX 129 -#define GNB_CONFIG_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL8_IDX 130 -#define GNB_CONFIG_SEARCHSPACE_NROFCANDIDATES_AGGREGATIONLEVEL16_IDX 131 -#define GNB_CONFIG_SEARCHSPACE_SEARCHSPACETYPE_IDX 132 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL1_IDX 133 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL2_IDX 134 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL4_IDX 135 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL8_IDX 136 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_0_NROFCANDIDATES_SFI_AGGREGATIONLEVEL16_IDX 137 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_3_MONITORINGPERIODICITY_IDX 138 -#define GNB_CONFIG_COMMON_DCI_FORMAT2_3_NROFPDCCH_CANDIDATES_IDX 139 -#define GNB_CONFIG_UE_SPECIFIC__DCI_FORMATS_IDX 140 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_CARRIERFREQDL_IDX 141 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_CARRIERBANDWIDTHDL_IDX 142 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_NROFCRS_PORTS_IDX 143 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_V_SHIFT_IDX 144 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_RADIOFRAMEALLOCATIONPERIOD_IDX 145 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_RADIOFRAMEALLOCATIONOFFSET_IDX 146 -#define GNB_CONFIG_RATEMATCHPATTERNLTE_CRS_SUBFRAMEALLOCATION_CHOICE_IDX 147 - - -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ -/* SRB1 configuration parameters section name */ -#define GNB_CONFIG_STRING_SRB1 "srb1_parameters" - -/* SRB1 configuration parameters names */ -#define GNB_CONFIG_STRING_SRB1_TIMER_POLL_RETRANSMIT "timer_poll_retransmit" -#define GNB_CONFIG_STRING_SRB1_TIMER_REORDERING "timer_reordering" -#define GNB_CONFIG_STRING_SRB1_TIMER_STATUS_PROHIBIT "timer_status_prohibit" -#define GNB_CONFIG_STRING_SRB1_POLL_PDU "poll_pdu" -#define GNB_CONFIG_STRING_SRB1_POLL_BYTE "poll_byte" -#define GNB_CONFIG_STRING_SRB1_MAX_RETX_THRESHOLD "max_retx_threshold" - -/*-----------------------------------------------------------------------------------------------------------------------------------------------------------*/ -/* SRB1 configuration parameters */ -/* optname helpstr paramflags XXXptr defXXXval type numelt */ -/*-----------------------------------------------------------------------------------------------------------------------------------------------------------*/ -#define GNBSRB1PARAMS_DESC { \ -{GNB_CONFIG_STRING_SRB1_TIMER_POLL_RETRANSMIT, NULL, 0, iptr:&srb1_timer_poll_retransmit, defintval:80, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SRB1_TIMER_REORDERING, NULL, 0, iptr:&srb1_timer_reordering, defintval:35, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SRB1_TIMER_STATUS_PROHIBIT, NULL, 0, iptr:&srb1_timer_status_prohibit, defintval:0, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SRB1_POLL_PDU, NULL, 0, iptr:&srb1_poll_pdu, defintval:4, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SRB1_POLL_BYTE, NULL, 0, iptr:&srb1_poll_byte, defintval:99999, TYPE_UINT, 0}, \ -{GNB_CONFIG_STRING_SRB1_MAX_RETX_THRESHOLD, NULL, 0, iptr:&srb1_max_retx_threshold, defintval:4, TYPE_UINT, 0} \ -} -/*-----------------------------------------------------------------------------------------------------------------------------------------------------------*/ /* MME configuration parameters section name */ #define GNB_CONFIG_STRING_MME_IP_ADDRESS "mme_ip_address" @@ -913,6 +283,8 @@ typedef enum { #define GNB_INTERFACE_NAME_FOR_S1U_IDX 2 #define GNB_IPV4_ADDR_FOR_S1U_IDX 3 #define GNB_PORT_FOR_S1U_IDX 4 +#define GNB_IPV4_ADDR_FOR_X2C_IDX 5 +#define GNB_PORT_FOR_X2C_IDX 6 /* S1 interface configuration parameters names */ #define GNB_CONFIG_STRING_GNB_INTERFACE_NAME_FOR_S1_MME "GNB_INTERFACE_NAME_FOR_S1_MME" @@ -921,6 +293,10 @@ typedef enum { #define GNB_CONFIG_STRING_GNB_IPV4_ADDR_FOR_S1U "GNB_IPV4_ADDRESS_FOR_S1U" #define GNB_CONFIG_STRING_GNB_PORT_FOR_S1U "GNB_PORT_FOR_S1U" +/* X2 interface configuration parameters names */ +#define GNB_CONFIG_STRING_ENB_IPV4_ADDR_FOR_X2C "GNB_IPV4_ADDRESS_FOR_X2C" +#define GNB_CONFIG_STRING_ENB_PORT_FOR_X2C "GNB_PORT_FOR_X2C" + /*--------------------------------------------------------------------------------------------------------------------------------------------------*/ /* S1 interface configuration parameters */ /* optname helpstr paramflags XXXptr defXXXval type numelt */ @@ -930,7 +306,9 @@ typedef enum { {GNB_CONFIG_STRING_GNB_IPV4_ADDRESS_FOR_S1_MME, NULL, 0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0}, \ {GNB_CONFIG_STRING_GNB_INTERFACE_NAME_FOR_S1U, NULL, 0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0}, \ {GNB_CONFIG_STRING_GNB_IPV4_ADDR_FOR_S1U, NULL, 0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0}, \ -{GNB_CONFIG_STRING_GNB_PORT_FOR_S1U, NULL, 0, uptr:NULL, defintval:2152L, TYPE_UINT, 0} \ +{GNB_CONFIG_STRING_GNB_PORT_FOR_S1U, NULL, 0, uptr:NULL, defintval:2152L, TYPE_UINT, 0}, \ +{GNB_CONFIG_STRING_ENB_IPV4_ADDR_FOR_X2C, NULL, 0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0}, \ +{GNB_CONFIG_STRING_ENB_PORT_FOR_X2C, NULL, 0, uptr:NULL, defintval:0L, TYPE_UINT, 0} \ } diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index d240e35a87..7c3b536de2 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -1496,38 +1496,33 @@ schedule_ulsch_rnti(module_id_t module_idP, if (status >= RRC_CONNECTED && UE_sched_ctrl_ptr->cqi_req_timer > 30) { if (UE_sched_ctrl_ptr->cqi_received == 0) { - if (NFAPI_MODE != NFAPI_MONOLITHIC) { - cqi_req = 0; - } else { - cqi_req = 1; - LOG_D(MAC,"Setting CQI_REQ (timer %d)\n",UE_sched_ctrl_ptr->cqi_req_timer); + cqi_req = 1; + LOG_D(MAC, + "Setting CQI_REQ (timer %d)\n", + UE_sched_ctrl_ptr->cqi_req_timer); - /* TDD: to be safe, do not ask CQI in special Subframes:36.213/7.2.3 CQI definition */ - if (cc[CC_id].tdd_Config) { - switch (cc[CC_id].tdd_Config->subframeAssignment) { - case 1: - if(subframeP == 1 || subframeP == 6) { - cqi_req=0; - } + /* TDD: to be safe, do not ask CQI in special + * Subframes:36.213/7.2.3 CQI definition */ + if (cc[CC_id].tdd_Config) { + switch (cc[CC_id].tdd_Config->subframeAssignment) { + case 1: + if (subframeP == 1 || subframeP == 6) + cqi_req = 0; + break; - break; + case 3: + if (subframeP == 1) + cqi_req = 0; + break; - case 3: - if(subframeP == 1) { - cqi_req=0; - } - - break; - - default: - LOG_E(MAC," TDD config not supported\n"); - break; - } + default: + LOG_E(MAC, " TDD config not supported\n"); + break; } + } - if(cqi_req == 1) { - UE_sched_ctrl_ptr->cqi_req_flag |= 1 << sched_subframeP; - } + if (cqi_req == 1) { + UE_sched_ctrl_ptr->cqi_req_flag |= 1 << sched_subframeP; } } else { LOG_D(MAC,"Clearing CQI request timer\n"); diff --git a/openair2/LAYER2/MAC/ue_procedures.c b/openair2/LAYER2/MAC/ue_procedures.c index 8518cba14c..1205851915 100644 --- a/openair2/LAYER2/MAC/ue_procedures.c +++ b/openair2/LAYER2/MAC/ue_procedures.c @@ -2158,7 +2158,7 @@ ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, if (phr_ce_len == sizeof(POWER_HEADROOM_CMD)) { if(NFAPI_MODE==NFAPI_UE_STUB_PNF) { //Substitute with a static value for the MAC layer abstraction (phy_stub mode) - phr_p->PH = 40; + phr_p->PH = 60; } else { phr_p->PH = get_phr_mapping(module_idP, CC_id, eNB_index); } diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 495cbb1eaa..ae23164194 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -20,7 +20,7 @@ */ /*! \file nr_mac_common.c - * \brief Common MAC functions for NR UE and gNB + * \brief Common MAC/PHY functions for NR UE and gNB * \author Florian Kaltenberger and Raymond Knopp * \date 2019 * \version 0.1 @@ -33,43 +33,55 @@ #include "LAYER2/NR_MAC_gNB/mac_proto.h" nr_bandentry_t nr_bandtable[] = { - {1, 1920000, 1980000, 2110000, 2170000, 20, 422000}, - {2, 1850000, 1910000, 1930000, 1990000, 20, 386000}, - {3, 1710000, 1785000, 1805000, 1880000, 20, 361000}, - {5, 824000, 849000, 869000, 894000, 20, 173800}, - {7, 2500000, 2570000, 2620000, 2690000, 20, 524000}, - {8, 880000, 915000, 925000, 960000, 20, 185000}, - {12, 698000, 716000, 728000, 746000, 20, 145800}, - {20, 832000, 862000, 791000, 821000, 20, 158200}, - {25, 1850000, 1915000, 1930000, 1995000, 20, 386000}, - {28, 703000, 758000, 758000, 813000, 20, 151600}, - {34, 2010000, 2025000, 2010000, 2025000, 20, 402000}, - {38, 2570000, 2620000, 2570000, 2630000, 20, 514000}, - {39, 1880000, 1920000, 1880000, 1920000, 20, 376000}, - {40, 2300000, 2400000, 2300000, 2400000, 20, 460000}, - {41, 2496000, 2690000, 2496000, 2690000, 3, 499200}, - {50, 1432000, 1517000, 1432000, 1517000, 20, 286400}, - {51, 1427000, 1432000, 1427000, 1432000, 20, 285400}, - {66, 1710000, 1780000, 2110000, 2200000, 20, 422000}, - {70, 1695000, 1710000, 1995000, 2020000, 20, 399000}, - {71, 663000, 698000, 617000, 652000, 20, 123400}, - {74, 1427000, 1470000, 1475000, 1518000, 20, 295000}, - {75, 000, 000, 1432000, 1517000, 20, 286400}, - {76, 000, 000, 1427000, 1432000, 20, 285400}, - {77, 3300000, 4200000, 3300000, 4200000, 1, 620000}, - {78, 3300000, 3800000, 3300000, 3800000, 1, 620000}, - {79, 4400000, 5000000, 4400000, 5000000, 2, 693334}, - {80, 1710000, 1785000, 000, 000, 20, 342000}, - {81, 860000, 915000, 000, 000, 20, 176000}, - {82, 832000, 862000, 000, 000, 20, 166400}, - {83, 703000, 748000, 000, 000, 20, 140600}, - {84, 1920000, 1980000, 000, 000, 20, 384000}, - {86, 1710000, 1785000, 000, 000, 20, 342000} + {1, 1920000, 1980000, 2110000, 2170000, 20, 422000, 100}, + {2, 1850000, 1910000, 1930000, 1990000, 20, 386000, 100}, + {3, 1710000, 1785000, 1805000, 1880000, 20, 361000, 100}, + {5, 824000, 849000, 869000, 894000, 20, 173800, 100}, + {7, 2500000, 2570000, 2620000, 2690000, 20, 524000, 100}, + {8, 880000, 915000, 925000, 960000, 20, 185000, 100}, + {12, 698000, 716000, 728000, 746000, 20, 145800, 100}, + {20, 832000, 862000, 791000, 821000, 20, 158200, 100}, + {25, 1850000, 1915000, 1930000, 1995000, 20, 386000, 100}, + {28, 703000, 758000, 758000, 813000, 20, 151600, 100}, + {34, 2010000, 2025000, 2010000, 2025000, 20, 402000, 100}, + {38, 2570000, 2620000, 2570000, 2630000, 20, 514000, 100}, + {39, 1880000, 1920000, 1880000, 1920000, 20, 376000, 100}, + {40, 2300000, 2400000, 2300000, 2400000, 20, 460000, 100}, + {41, 2496000, 2690000, 2496000, 2690000, 3, 499200, 15}, + {41, 2496000, 2690000, 2496000, 2690000, 6, 499200, 30}, + {50, 1432000, 1517000, 1432000, 1517000, 20, 286400, 100}, + {51, 1427000, 1432000, 1427000, 1432000, 20, 285400, 100}, + {66, 1710000, 1780000, 2110000, 2200000, 20, 422000, 100}, + {70, 1695000, 1710000, 1995000, 2020000, 20, 399000, 100}, + {71, 663000, 698000, 617000, 652000, 20, 123400, 100}, + {74, 1427000, 1470000, 1475000, 1518000, 20, 295000, 100}, + {75, 000, 000, 1432000, 1517000, 20, 286400, 100}, + {76, 000, 000, 1427000, 1432000, 20, 285400, 100}, + {77, 3300000, 4200000, 3300000, 4200000, 1, 620000, 15}, + {77, 3300000, 4200000, 3300000, 4200000, 2, 620000, 30}, + {78, 3300000, 3800000, 3300000, 3800000, 1, 620000, 15}, + {78, 3300000, 3800000, 3300000, 3800000, 2, 620000, 30}, + {79, 4400000, 5000000, 4400000, 5000000, 1, 693334, 15}, + {79, 4400000, 5000000, 4400000, 5000000, 2, 693334, 30}, + {80, 1710000, 1785000, 000, 000, 20, 342000, 100}, + {81, 860000, 915000, 000, 000, 20, 176000, 100}, + {82, 832000, 862000, 000, 000, 20, 166400, 100}, + {83, 703000, 748000, 000, 000, 20, 140600, 100}, + {84, 1920000, 1980000, 000, 000, 20, 384000, 100}, + {86, 1710000, 1785000, 000, 000, 20, 342000, 100}, + {257,26500000,29500000,26500000,29500000, 1,2054166, 60}, + {257,26500000,29500000,26500000,29500000, 2,2054167, 120}, + {258,24250000,27500000,24250000,27500000, 1,2016667, 60}, + {258,24250000,27500000,24250000,27500000, 2,2016667, 120}, + {260,37000000,40000000,37000000,40000000, 1,2229166, 60}, + {260,37000000,40000000,37000000,40000000, 2,2229167, 120}, + {261,27500000,28350000,27500000,28350000, 1,2070833, 60}, + {261,27500000,28350000,27500000,28350000, 2,2070833, 120} }; #define NR_BANDTABLE_SIZE (sizeof(nr_bandtable)/sizeof(nr_bandentry_t)) -void get_band(uint32_t downlink_frequency, +void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type) @@ -91,40 +103,157 @@ void get_band(uint32_t downlink_frequency, if ( nr_bandtable[ind].dl_min <= dl_freq_khz && nr_bandtable[ind].dl_max >= dl_freq_khz ) { center_frequency_khz = (nr_bandtable[ind].dl_max + nr_bandtable[ind].dl_min)/2; - if (abs(dl_freq_khz - center_frequency_khz) < center_freq_diff_khz){ - *current_band = nr_bandtable[ind].band; - *current_offset = (nr_bandtable[ind].ul_min - nr_bandtable[ind].dl_min)*1000; + *current_offset = (nr_bandtable[ind].ul_min - nr_bandtable[ind].dl_min)*1000; center_freq_diff_khz = abs(dl_freq_khz - center_frequency_khz); - if (*current_offset == 0) - *current_type = TDD; - else - *current_type = FDD; + if (*current_offset == 0) + *current_type = TDD; + else + *current_type = FDD; } } } - LOG_I( PHY, "DL frequency %"PRIu32": band %d, frame_type %d, UL frequency %"PRIu32"\n", + LOG_I( PHY, "DL frequency %"PRIu64": band %d, frame_type %d, UL frequency %"PRIu64"\n", downlink_frequency, *current_band, *current_type, downlink_frequency+*current_offset); AssertFatal(*current_band != 0, - "Can't find EUTRA band for frequency %u\n", downlink_frequency); + "Can't find EUTRA band for frequency %lu\n", downlink_frequency); +} + +uint16_t config_bandwidth(int mu, int nb_rb, int nr_band) +{ + + if (nr_band < 100) { //FR1 + switch(mu) { + case 0 : + if (nb_rb<=25) + return 5; + if (nb_rb<=52) + return 10; + if (nb_rb<=79) + return 15; + if (nb_rb<=106) + return 20; + if (nb_rb<=133) + return 25; + if (nb_rb<=160) + return 30; + if (nb_rb<=216) + return 40; + if (nb_rb<=270) + return 50; + AssertFatal(1==0,"Number of DL resource blocks %d undefined for mu %d and band %d\n", nb_rb, mu, nr_band); + break; + case 1 : + if (nb_rb<=11) + return 5; + if (nb_rb<=24) + return 10; + if (nb_rb<=38) + return 15; + if (nb_rb<=51) + return 20; + if (nb_rb<=65) + return 25; + if (nb_rb<=78) + return 30; + if (nb_rb<=106) + return 40; + if (nb_rb<=133) + return 50; + if (nb_rb<=162) + return 60; + if (nb_rb<=189) + return 70; + if (nb_rb<=217) + return 80; + if (nb_rb<=245) + return 90; + if (nb_rb<=273) + return 100; + AssertFatal(1==0,"Number of DL resource blocks %d undefined for mu %d and band %d\n", nb_rb, mu, nr_band); + break; + case 2 : + if (nb_rb<=11) + return 10; + if (nb_rb<=18) + return 15; + if (nb_rb<=24) + return 20; + if (nb_rb<=31) + return 25; + if (nb_rb<=38) + return 30; + if (nb_rb<=51) + return 40; + if (nb_rb<=65) + return 50; + if (nb_rb<=79) + return 60; + if (nb_rb<=93) + return 70; + if (nb_rb<=107) + return 80; + if (nb_rb<=121) + return 90; + if (nb_rb<=135) + return 100; + AssertFatal(1==0,"Number of DL resource blocks %d undefined for mu %d and band %d\n", nb_rb, mu, nr_band); + break; + default: + AssertFatal(1==0,"Numerology %d undefined for band %d in FR1\n", mu,nr_band); + } + } + else { + switch(mu) { + case 2 : + if (nb_rb<=66) + return 50; + if (nb_rb<=132) + return 100; + if (nb_rb<=264) + return 200; + AssertFatal(1==0,"Number of DL resource blocks %d undefined for mu %d and band %d\n", nb_rb, mu, nr_band); + break; + case 3 : + if (nb_rb<=32) + return 50; + if (nb_rb<=66) + return 100; + if (nb_rb<=132) + return 200; + if (nb_rb<=264) + return 400; + AssertFatal(1==0,"Number of DL resource blocks %d undefined for mu %d and band %d\n", nb_rb, mu, nr_band); + break; + default: + AssertFatal(1==0,"Numerology %d undefined for band %d in FR1\n", mu,nr_band); + } + } + } uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, + uint8_t scs_index, uint32_t bw) { uint64_t dl_CarrierFreq_by_1k = dl_CarrierFreq / 1000; int bw_kHz = bw / 1000; - + int scs_khz = 15< 86\n", nr_bandP); - for (i = 0; i < 30 && nr_bandtable[i].band != nr_bandP; i++); + AssertFatal(nr_bandP <= 261, "nr_band %d > 260\n", nr_bandP); + for (i = 0; i < NR_BANDTABLE_SIZE && nr_bandtable[i].band != nr_bandP; i++); + + // selection of correct Deltaf raster according to SCS + if ( (nr_bandtable[i].deltaf_raster != 100) && (nr_bandtable[i].deltaf_raster != scs_khz)) + i++; AssertFatal(dl_CarrierFreq_by_1k >= nr_bandtable[i].dl_min, "Band %d, bw %u : DL carrier frequency %llu kHz < %llu\n", @@ -135,31 +264,57 @@ uint32_t to_nrarfcn(int nr_bandP, nr_bandP, (long long unsigned int)dl_CarrierFreq,bw, (long long unsigned int)dl_CarrierFreq_by_1k, (long long unsigned int)(nr_bandtable[i].dl_max - bw_kHz)); - int deltaFglobal; + int deltaFglobal = 60; - if (dl_CarrierFreq < 3e9) deltaFglobal = 5; - else deltaFglobal = 15; + if (dl_CarrierFreq < 3e9) deltaFglobal = 15; + if (dl_CarrierFreq < 24.25e9) deltaFglobal = 5; // This is equation before Table 5.4.2.1-1 in 38101-1-f30 // F_REF=F_REF_Offs + deltaF_Global(N_REF-NREF_REF_Offs) - return (((dl_CarrierFreq_by_1k - nr_bandtable[i].dl_min)/deltaFglobal) + - nr_bandtable[i].N_OFFs_DL); + nrarfcn = (((dl_CarrierFreq_by_1k - nr_bandtable[i].dl_min)/deltaFglobal)+nr_bandtable[i].N_OFFs_DL); + + delta_arfcn = nrarfcn - nr_bandtable[i].N_OFFs_DL; + if(delta_arfcn%(nr_bandtable[i].step_size)!=0) + AssertFatal(1==0,"dl_CarrierFreq %lu corresponds to %u which is not on the raster for step size %lu", + dl_CarrierFreq,nrarfcn,nr_bandtable[i].step_size); + + return nrarfcn; } uint64_t from_nrarfcn(int nr_bandP, + uint8_t scs_index, uint32_t dl_nrarfcn) { int i; - int deltaFglobal; + int deltaFglobal = 5; + int scs_khz = 15< 79) deltaFglobal = 5; - else deltaFglobal = 15; + if (dl_nrarfcn > 599999 && dl_nrarfcn < 2016667) + deltaFglobal = 15; + if (dl_nrarfcn > 2016666 && dl_nrarfcn < 3279166) + deltaFglobal = 60; - AssertFatal(nr_bandP < 87, "nr_band %d > 86\n", nr_bandP); - for (i = 0; i < 31 && nr_bandtable[i].band != nr_bandP; i++); - AssertFatal(dl_nrarfcn>=nr_bandtable[i].N_OFFs_DL,"dl_nrarfcn %u < N_OFFs_DL %llu\n",dl_nrarfcn, (long long unsigned int)nr_bandtable[i].N_OFFs_DL); + AssertFatal(nr_bandP <= 261, "nr_band %d > 260\n", nr_bandP); + for (i = 0; i < NR_BANDTABLE_SIZE && nr_bandtable[i].band != nr_bandP; i++); + AssertFatal(dl_nrarfcn>=nr_bandtable[i].N_OFFs_DL,"dl_nrarfcn %u < N_OFFs_DL[%d] %llu\n",dl_nrarfcn, nr_bandtable[i].band,(long long unsigned int)nr_bandtable[i].N_OFFs_DL); + // selection of correct Deltaf raster according to SCS + if ( (nr_bandtable[i].deltaf_raster != 100) && (nr_bandtable[i].deltaf_raster != scs_khz)) + i++; + + delta_arfcn = dl_nrarfcn - nr_bandtable[i].N_OFFs_DL; + if(delta_arfcn%(nr_bandtable[i].step_size)!=0) + AssertFatal(1==0,"dl_nrarfcn %u is not on the raster for step size %lu",dl_nrarfcn,nr_bandtable[i].step_size); + + LOG_I(PHY,"Computing dl_frequency (pointA %llu => %llu (dlmin %llu, nr_bandtable[%d].N_OFFs_DL %llu))\n", + (unsigned long long)dl_nrarfcn, + (unsigned long long)(1000*(nr_bandtable[i].dl_min + (dl_nrarfcn - nr_bandtable[i].N_OFFs_DL) * deltaFglobal)), + (unsigned long long)nr_bandtable[i].dl_min, + i, + (unsigned long long)nr_bandtable[i].N_OFFs_DL); + return 1000*(nr_bandtable[i].dl_min + (dl_nrarfcn - nr_bandtable[i].N_OFFs_DL) * deltaFglobal); } @@ -174,3 +329,420 @@ int32_t get_nr_uldl_offset(int nr_bandP) return (nr_bandtable[i].dl_min - nr_bandtable[i].ul_min); } + + +void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, + int x_overhead) { + + LOG_D(MAC, "TBS calculation\n"); + + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15; + uint16_t N_PRB_oh = x_overhead; + uint8_t N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 + uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; + uint8_t Imcs = pdsch_rel15->mcsIndex[0]; + uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; + LOG_D(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh); + + uint16_t R; + uint32_t TBS=0; + uint8_t table_idx, Qm; + + /*uint8_t mcs_table = config.pdsch_config.mcs_table.value; + uint8_t ss_type = params_rel15.search_space_type; + uint8_t dci_format = params_rel15.dci_format; + get_table_idx(mcs_table, dci_format, rnti_type, ss_type);*/ + table_idx = 0; + R = nr_get_code_rate_dl(Imcs, table_idx); + Qm = nr_get_Qm_dl(Imcs, table_idx); + + TBS = nr_compute_tbs(Qm, + R, + pdsch_rel15->rbSize, + N_sh_symb, + N_PRB_DMRS, + N_PRB_oh, + pdsch_rel15->nrOfLayers)>>3; + + pdsch_rel15->targetCodeRate[0] = R; + pdsch_rel15->qamModOrder[0] = Qm; + pdsch_rel15->TBSize[0] = TBS; + // pdsch_rel15->nb_mod_symbols = N_RE_prime*pdsch_rel15->n_prb*pdsch_rel15->nb_codewords; + pdsch_rel15->mcsTable[0] = table_idx; + + LOG_D(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n", + TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords ); +} + +//Table 5.1.3.1-1 of 38.214 +uint16_t Table_51311[29][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616}, + {4,658},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}}; + +//Table 5.1.3.1-2 of 38.214 +// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point +uint16_t Table_51312[28][2] = {{2,120},{2,193},{2,308},{2,449},{2,602},{4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{6,466},{6,517},{6,567},{6,616},{6,666}, + {6,719},{6,772},{6,822},{6,873},{8,1365},{8,711},{8,754},{8,797},{8,841},{8,885},{8,1833},{8,948}}; + +//Table 5.1.3.1-3 of 38.214 +uint16_t Table_51313[29][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{4,340}, + {4,378},{4,434},{4,490},{4,553},{4,616},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666}, {6,719}, {6,772}}; + +//Table 6.1.4.1-1 of 38.214 TODO fix for tp-pi2BPSK +uint16_t Table_61411[28][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616}, + {4,658},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}}; + +//Table 6.1.4.1-2 of 38.214 TODO fix for tp-pi2BPSK +uint16_t Table_61412[28][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679}, + {4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{4,699},{4,772},{6,567},{6,616},{6,666}, {6,772}}; + + + +uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) { + switch(table_idx) { + case 0: + return (Table_51311[Imcs][0]); + break; + + case 1: + return (Table_51312[Imcs][0]); + break; + + case 2: + return (Table_51313[Imcs][0]); + break; + + default: + AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx); + } +} + +uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx) { + switch(table_idx) { + case 0: + return (Table_51311[Imcs][1]); + break; + + case 1: + return (Table_51312[Imcs][1]); + break; + + case 2: + return (Table_51313[Imcs][1]); + break; + + default: + AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx); + } +} + +uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) { + switch(table_idx) { + case 0: + return (Table_51311[Imcs][0]); + break; + + case 1: + return (Table_51312[Imcs][0]); + break; + + case 2: + return (Table_51313[Imcs][0]); + break; + + case 3: + return (Table_61411[Imcs][0]); + break; + + case 4: + return (Table_61412[Imcs][0]); + break; + + default: + AssertFatal(0, "Invalid MCS table index %d (expected in range [1,2])\n", table_idx); + } +} + +uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) { + switch(table_idx) { + case 0: + return (Table_51311[Imcs][1]); + break; + + case 1: + return (Table_51312[Imcs][1]); + break; + + case 2: + return (Table_51313[Imcs][1]); + break; + + case 3: + return (Table_61411[Imcs][1]); + break; + + case 4: + return (Table_61412[Imcs][1]); + break; + + default: + AssertFatal(0, "Invalid MCS table index %d (expected in range [1,2])\n", table_idx); + } +} + +static inline uint8_t is_codeword_disabled(uint8_t format, uint8_t Imcs, uint8_t rv) { + return ((format==NFAPI_NR_DL_DCI_FORMAT_1_1)&&(Imcs==26)&&(rv==1)); +} + +static inline uint8_t get_table_idx(uint8_t mcs_table, uint8_t dci_format, uint8_t rnti_type, uint8_t ss_type) { + if ((mcs_table == NFAPI_NR_MCS_TABLE_QAM256) && (dci_format == NFAPI_NR_DL_DCI_FORMAT_1_1) && ((rnti_type==NFAPI_NR_RNTI_C)||(rnti_type==NFAPI_NR_RNTI_CS))) + return 2; + else if ((mcs_table == NFAPI_NR_MCS_TABLE_QAM64_LOW_SE) && (rnti_type!=NFAPI_NR_RNTI_new) && (rnti_type==NFAPI_NR_RNTI_C) && (ss_type==NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)) + return 3; + else if (rnti_type==NFAPI_NR_RNTI_new) + return 3; + else if ((mcs_table == NFAPI_NR_MCS_TABLE_QAM256) && (rnti_type==NFAPI_NR_RNTI_CS) && (dci_format == NFAPI_NR_DL_DCI_FORMAT_1_1)) + return 2; // Condition mcs_table not configured in sps_config necessary here but not yet implemented + /*else if((mcs_table == NFAPI_NR_MCS_TABLE_QAM64_LOW_SE) && (rnti_type==NFAPI_NR_RNTI_CS)) + * table_idx = 3; + * Note: the commented block refers to the case where the mcs_table is from sps_config*/ + else + return 1; +} + +int get_num_dmrs(uint16_t dmrs_mask ) { + + int num_dmrs=0; + + for (int i=0;i<16;i++) num_dmrs+=((dmrs_mask>>i)&1); + return(num_dmrs); +} + +uint16_t nr_dci_size(nr_dci_format_t format, + nr_rnti_type_t rnti_type, + uint16_t N_RB) { + + uint16_t size = 0; + + switch(format) { + /*Only sizes for 0_0 and 1_0 are correct at the moment*/ + case NR_UL_DCI_FORMAT_0_0: + /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 + size += 20; + size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated + size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size + // UL/SUL indicator assumed to be 0 + break; + + case NR_UL_DCI_FORMAT_0_1: + /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, SRS request 2 --17 + size += 17; + // Carrier indicator + // UL/SUL indicator + // BWP Indicator + // Freq domain assignment + // Time domain assignment + // VRB to PRB mapping + // Frequency Hopping flag + // 1st DAI + // 2nd DAI + // SRS resource indicator + // Precoding info and number of layers + // Antenna ports + // CSI request + // CBGTI + // PTRS - DMRS association + // beta offset indicator + // DMRS sequence init + break; + + case NR_DL_DCI_FORMAT_1_0: + /// fixed: Format identifier 1, VRB2PRB 1, MCS 5, NDI 1, RV 2, HARQ PID 4, DAI 2, PUCCH TPC 2, PUCCH RInd 3, PDSCH to HARQ TInd 3 Time Domain assgnmt 4 -- 28 + size += 28; + size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment + break; + + case NR_DL_DCI_FORMAT_1_1: + // Carrier indicator + size += 1; // Format identifier + // BWP Indicator + // Freq domain assignment + // Time domain assignment + // VRB to PRB mapping + // PRB bundling size indicator + // Rate matching indicator + // ZP CSI-RS trigger + /// TB1- MCS 5, NDI 1, RV 2 + size += 8; + // TB2 + size += 4 ; // HARQ PID + // DAI + size += 2; // TPC PUCCH + size += 3; // PUCCH resource indicator + size += 3; // PDSCH to HARQ timing indicator + // Antenna ports + // Tx Config Indication + size += 2; // SRS request + // CBGTI + // CBGFI + size += 1; // DMRS sequence init + break; + + case NR_DL_DCI_FORMAT_2_0: + break; + + case NR_DL_DCI_FORMAT_2_1: + break; + + case NR_DL_DCI_FORMAT_2_2: + break; + + case NR_DL_DCI_FORMAT_2_3: + break; + + default: + AssertFatal(1==0, "Invalid NR DCI format %d\n", format); + } + + return size; +} + +int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000}; + +int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) { + + int period,period1,period2=0; + + if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1); + + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 && + scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530) + period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530; + else + period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity]; + + if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) { + if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 && + scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530) + period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530; + else + period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity]; + } + period = period1+period2; + int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing; + int slots=period*(1<tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0); + else return(slot_in_period <= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0); +} + +int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) { + + int period,period1,period2=0; + + if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1); + + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 && + scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530) + period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530; + else + period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity]; + + if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) { + if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 && + scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530) + period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530; + else + period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity]; + } + period = period1+period2; + int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing; + int slots=period*(1<= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0); + else return(slot_in_period >= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0); +} + +int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols) { + + int l0; + if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2) l0=2; + else if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3) l0=3; + else AssertFatal(1==0,"Illegal dmrs_TypeA_Position %d\n",(int)dmrs_TypeA_Position); + if (pdsch_Config == NULL) { // Initial BWP + return(1<dmrs_DownlinkForPDSCH_MappingTypeA && + pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) { + // Relative to start of slot + NR_DMRS_DownlinkConfig_t *dmrs_config = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup; + AssertFatal(NrOfSymbols>1 && NrOfSymbols < 15,"Illegal NrOfSymbols %d\n",NrOfSymbols); + int pos2=0; + if (dmrs_config->maxLength == NULL) { + // this is Table 7.4.1.1.2-3: PDSCH DM-RS positions l for single-symbol DM-RS + if (dmrs_config->dmrs_AdditionalPosition == NULL) pos2=1; + else if (dmrs_config->dmrs_AdditionalPosition && *dmrs_config->dmrs_AdditionalPosition == NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0 ) + return(1<dmrs_AdditionalPosition); + break; + case 8 : + case 9: + return(1<dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) + return(1<dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) + return(1<dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3) + return(1<dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) + return(1<dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3) + return(1<3,"Illegal NrOfSymbols %d for len2 DMRS\n",NrOfSymbols); + if (NrOfSymbols < 10) return(1<dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) return(1<dmrs_DownlinkForPDSCH_MappingTypeB && + pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) { + // Relative to start of PDSCH resource + AssertFatal(1==0,"TypeB DMRS not supported yet\n"); + } + } + AssertFatal(1==0,"Shouldn't get here\n"); + return(-1); +} diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index 7378b58ab6..c983023034 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -35,133 +35,340 @@ #include "NR_MAC-CellGroupConfig.h" +#include "../NR_MAC_gNB/nr_mac_common.h" +#include "SCHED_NR/phy_frame_config_nr.h" + +int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, + int mu, + int nrofDownlinkSlots, int nrofDownlinkSymbols, + int nrofUplinkSlots, int nrofUplinkSymbols) { + + int slot_number = 0; + int nb_periods_per_frame; + int nb_slots_to_set = TDD_CONFIG_NB_FRAMES*(1<tdd_table.tdd_period) { + case 0: + nb_periods_per_frame = 20; // 10ms/0p5ms + break; + + case 1: + nb_periods_per_frame = 16; // 10ms/0p625ms + break; + + case 2: + nb_periods_per_frame = 10; // 10ms/1ms + break; + + case 3: + nb_periods_per_frame = 8; // 10ms/1p25ms + break; + + case 4: + nb_periods_per_frame = 5; // 10ms/2ms + break; + + case 5: + nb_periods_per_frame = 4; // 10ms/2p5ms + break; + + case 6: + nb_periods_per_frame = 2; // 10ms/5ms + break; + + case 7: + nb_periods_per_frame = 1; // 10ms/10ms + break; + + default: + AssertFatal(1==0,"Undefined tdd period %d\n", cfg->tdd_table.tdd_period); + } + + int nb_slots_per_period = ((1<tdd_table.max_tdd_periodicity_list = (fapi_nr_max_tdd_periodicity_t *) malloc(nb_slots_to_set*sizeof(fapi_nr_max_tdd_periodicity_t)); + + for(int memory_alloc =0 ; memory_alloctdd_table.max_tdd_periodicity_list[memory_alloc].max_num_of_symbol_per_slot_list = (fapi_nr_max_num_of_symbol_per_slot_t *) malloc(NR_NUMBER_OF_SYMBOLS_PER_SLOT*sizeof( + fapi_nr_max_num_of_symbol_per_slot_t)); + + while(slot_number != nb_slots_to_set) { + if(nrofDownlinkSlots != 0) { + for (int number_of_symbol = 0; number_of_symbol < nrofDownlinkSlots*NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol%NR_NUMBER_OF_SYMBOLS_PER_SLOT].slot_config= 0; + + if((number_of_symbol+1)%NR_NUMBER_OF_SYMBOLS_PER_SLOT == 0) + slot_number++; + } + } + + if (nrofDownlinkSymbols != 0 || nrofUplinkSymbols != 0) { + for(int number_of_symbol =0; number_of_symbol < nrofDownlinkSymbols; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config= 0; + } + + for(int number_of_symbol = nrofDownlinkSymbols; number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT-nrofUplinkSymbols; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config= 2; + } + + for(int number_of_symbol = NR_NUMBER_OF_SYMBOLS_PER_SLOT-nrofUplinkSymbols; number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config= 1; + } + + slot_number++; + } + + if(nrofUplinkSlots != 0) { + for (int number_of_symbol = 0; number_of_symbol < nrofUplinkSlots*NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) { + cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol%NR_NUMBER_OF_SYMBOLS_PER_SLOT].slot_config= 1; + + if((number_of_symbol+1)%NR_NUMBER_OF_SYMBOLS_PER_SLOT == 0) + slot_number++; + } + } + } + + return (0); +} + + +void config_common_ue(NR_UE_MAC_INST_t *mac, + module_id_t module_id, + int cc_idP) { + + fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; + NR_ServingCellConfigCommon_t *scc = mac->scc; + int i; + + mac->phy_config.Mod_id = module_id; + mac->phy_config.CC_id = cc_idP; + + // carrier config + + LOG_I(MAC,"UE Config Common\n"); + + cfg->carrier_config.dl_bandwidth = config_bandwidth(scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing, + scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth, + *scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]); + + cfg->carrier_config.dl_frequency = from_nrarfcn(*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0], + *scc->ssbSubcarrierSpacing, + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA)/1000; // freq in kHz + + for (i=0; i<5; i++) { + if (i==scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing) { + cfg->carrier_config.dl_grid_size[i] = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + cfg->carrier_config.dl_k0[i] = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier; + } + else { + cfg->carrier_config.dl_grid_size[i] = 0; + cfg->carrier_config.dl_k0[i] = 0; + } + } + + cfg->carrier_config.uplink_bandwidth = config_bandwidth(scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing, + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth, + *scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]); + + int UL_pointA; + if (scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA == NULL) + UL_pointA = scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA; + else + UL_pointA = *scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA; + + cfg->carrier_config.uplink_frequency = from_nrarfcn(*scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0], + *scc->ssbSubcarrierSpacing, + UL_pointA)/1000; // freq in kHz + + + for (i=0; i<5; i++) { + if (i==scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing) { + cfg->carrier_config.ul_grid_size[i] = scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + cfg->carrier_config.ul_k0[i] = scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier; + } + else { + cfg->carrier_config.ul_grid_size[i] = 0; + cfg->carrier_config.ul_k0[i] = 0; + } + } + + + // cell config + + cfg->cell_config.phy_cell_id = *scc->physCellId; + cfg->cell_config.frame_duplex_type = 1; + + + // SSB config + cfg->ssb_config.ss_pbch_power = scc->ss_PBCH_BlockPower; + cfg->ssb_config.scs_common = *scc->ssbSubcarrierSpacing; + + // SSB Table config + int scs_scaling = 1<<(cfg->ssb_config.scs_common); + if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA < 600000) + scs_scaling = scs_scaling*3; + if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA > 2016666) + scs_scaling = scs_scaling>>2; + uint32_t absolute_diff = (*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB - scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA); + cfg->ssb_table.ssb_offset_point_a = absolute_diff/(12*scs_scaling) - 10; + cfg->ssb_table.ssb_period = *scc->ssb_periodicityServingCell; + cfg->ssb_table.ssb_subcarrier_offset = 0; // TODO currently not in RRC? + + switch (scc->ssb_PositionsInBurst->present) { + case 1 : + cfg->ssb_table.ssb_mask_list[0].ssb_mask = scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0]<<24; + cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0; + break; + case 2 : + cfg->ssb_table.ssb_mask_list[0].ssb_mask = scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0]<<24; + cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0; + break; + case 3 : + cfg->ssb_table.ssb_mask_list[0].ssb_mask = 0; + cfg->ssb_table.ssb_mask_list[1].ssb_mask = 0; + for (i=0; i<4; i++) { + cfg->ssb_table.ssb_mask_list[0].ssb_mask += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i+4]<ssb_table.ssb_mask_list[1].ssb_mask += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i]<ssb_PositionsInBurst->present); + } + + // TDD Table Configuration + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 == NULL) + cfg->tdd_table.tdd_period = scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity; + else { + AssertFatal(scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 != NULL, + "scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 is null\n"); + cfg->tdd_table.tdd_period = *scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530; + } + LOG_I(MAC,"Setting TDD configuration period to %d\n",cfg->tdd_table.tdd_period); + if(cfg->cell_config.frame_duplex_type == TDD){ + int return_tdd = set_tdd_config_nr_ue(cfg, + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols + ); + + if (return_tdd !=0) + LOG_E(PHY,"TDD configuration can not be done\n"); + else + LOG_I(PHY,"TDD has been properly configurated\n"); + } + + +} + int nr_rrc_mac_config_req_ue( module_id_t module_id, int cc_idP, uint8_t gNB_index, NR_MIB_t *mibP, - NR_MAC_CellGroupConfig_t *mac_cell_group_configP, - NR_PhysicalCellGroupConfig_t *phy_cell_group_configP, - NR_SpCellConfig_t *spcell_configP ){ + // NR_ServingCellConfigCommon_t *sccP, + // NR_MAC_CellGroupConfig_t *mac_cell_group_configP, + // NR_PhysicalCellGroupConfig_t *phy_cell_group_configP, + NR_SpCellConfig_t *spCell_ConfigP ){ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); -// NR_ServingCellConfig_t *serving_cell_config = spcell_configP->spCellConfigDedicated; -// TODO do something FAPI-like P5 L1/L2 config interface in config_si, config_mib, etc. + // NR_ServingCellConfig_t *serving_cell_config = spcell_configP->spCellConfigDedicated; + // TODO do something FAPI-like P5 L1/L2 config interface in config_si, config_mib, etc. + if(mibP != NULL){ - mac->mib = mibP; // update by every reception - } - - if(mac_cell_group_configP != NULL){ - if(mac_cell_group_configP->drx_Config != NULL ){ - switch(mac_cell_group_configP->drx_Config->present){ - case NR_SetupRelease_DRX_Config_PR_NOTHING: - break; - case NR_SetupRelease_DRX_Config_PR_release: - mac->drx_Config = NULL; - break; - case NR_SetupRelease_DRX_Config_PR_setup: - mac->drx_Config = mac_cell_group_configP->drx_Config->choice.setup; - break; - default: - break; - } - } - - if(mac_cell_group_configP->schedulingRequestConfig != NULL ){ - mac->schedulingRequestConfig = mac_cell_group_configP->schedulingRequestConfig; - } - - if(mac_cell_group_configP->bsr_Config != NULL ){ - mac->bsr_Config = mac_cell_group_configP->bsr_Config; - } - - if(mac_cell_group_configP->tag_Config != NULL ){ - mac->tag_Config = mac_cell_group_configP->tag_Config; - } - - if(mac_cell_group_configP->phr_Config != NULL ){ - switch(mac_cell_group_configP->phr_Config->present){ - case NR_SetupRelease_PHR_Config_PR_NOTHING: - break; - case NR_SetupRelease_PHR_Config_PR_release: - mac->phr_Config = NULL; - break; - case NR_SetupRelease_PHR_Config_PR_setup: - mac->phr_Config = mac_cell_group_configP->phr_Config->choice.setup; - break; - default: - break; - } - - } - - if(phy_cell_group_configP->cs_RNTI != NULL ){ - switch(phy_cell_group_configP->cs_RNTI->present){ - case NR_SetupRelease_RNTI_Value_PR_NOTHING: - break; - case NR_SetupRelease_RNTI_Value_PR_release: - mac->cs_RNTI = NULL; - break; - case NR_SetupRelease_RNTI_Value_PR_setup: - mac->cs_RNTI = &phy_cell_group_configP->cs_RNTI->choice.setup; - break; - default: - break; - } - - } - + mac->mib = mibP; // update by every reception } - if(phy_cell_group_configP != NULL ){ - //config_phy(phy_cell_group_config, NULL); - } - -// TODO check -#if 0 - if(serving_cell_config_configP != NULL ){ - //config_phy(NULL, spcell_config); - mac->servCellIndex = spcell_config->servCellIndex; - } - - - if(serving_cell_config != NULL ){ - if(serving_cell_config->tdd_UL_DL_ConfigurationDedicated != NULL ){ - mac->tdd_UL_DL_ConfigurationDedicated = serving_cell_config->tdd_UL_DL_ConfigurationDedicated; - } - - if(spcell_config->initialDownlinkBWP != NULL ){ - mac->init_DL_BWP = spcell_config->initialDownlinkBWP; - } - - // storage list of DL BWP config. TODO should be modify to maintain(add/release) a list inside MAC instance, this implementation just use for one-shot RRC configuration setting. - if(spcell_config->downlinkBWP_ToAddModList != NULL ){ - mac->BWP_Downlink_list = spcell_config->downlinkBWP_ToAddModList->list; - mac->BWP_Downlink_count = spcell_config->downlinkBWP_ToAddModList->count; - } - - if(spcell_config->bwp_InactivityTimer != NULL ){ - mac->bwp_InactivityTimer = spcell_config->bwp_InactivityTimer; - } - - if(spcell_config->defaultDownlinkBWP_Id != NULL ){ - mac->defaultDownlinkBWP_Id = spcell_config->defaultDownlinkBWP_Id; - } - - if(spcell_config->pdsch_ServingCellConfig != NULL ){ - mac->pdsch_ServingCellConfig = spcell_config->pdsch_ServingCellConfig; - } - - if(spcell_config->csi_MeasConfig != NULL ){ - mac->csi_MeasConfig = spcell_config->csi_MeasConfig; - } - - spcell_config->tag_Id = spcell_config.tag_Id; - } -#endif - //scell config not yet + + if(spCell_ConfigP != NULL ){ + mac->servCellIndex = *spCell_ConfigP->servCellIndex; + if (spCell_ConfigP->reconfigurationWithSync) { + mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon; + config_common_ue(mac,module_id,cc_idP); + mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity; + LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti); + } + mac->scd = spCell_ConfigP->spCellConfigDedicated; + /* + if(mac_cell_group_configP != NULL){ + if(mac_cell_group_configP->drx_Config != NULL ){ + switch(mac_cell_group_configP->drx_Config->present){ + case NR_SetupRelease_DRX_Config_PR_NOTHING: + break; + case NR_SetupRelease_DRX_Config_PR_release: + mac->drx_Config = NULL; + break; + case NR_SetupRelease_DRX_Config_PR_setup: + mac->drx_Config = mac_cell_group_configP->drx_Config->choice.setup; + break; + default: + break; + } + } + + if(mac_cell_group_configP->schedulingRequestConfig != NULL ){ + mac->schedulingRequestConfig = mac_cell_group_configP->schedulingRequestConfig; + } + + if(mac_cell_group_configP->bsr_Config != NULL ){ + mac->bsr_Config = mac_cell_group_configP->bsr_Config; + } + + if(mac_cell_group_configP->tag_Config != NULL ){ + mac->tag_Config = mac_cell_group_configP->tag_Config; + } + + if(mac_cell_group_configP->phr_Config != NULL ){ + switch(mac_cell_group_configP->phr_Config->present){ + case NR_SetupRelease_PHR_Config_PR_NOTHING: + break; + case NR_SetupRelease_PHR_Config_PR_release: + mac->phr_Config = NULL; + break; + case NR_SetupRelease_PHR_Config_PR_setup: + mac->phr_Config = mac_cell_group_configP->phr_Config->choice.setup; + break; + default: + break; + } + } + } + + + if(phy_cell_group_configP != NULL ){ + if(phy_cell_group_configP->cs_RNTI != NULL ){ + switch(phy_cell_group_configP->cs_RNTI->present){ + case NR_SetupRelease_RNTI_Value_PR_NOTHING: + break; + case NR_SetupRelease_RNTI_Value_PR_release: + mac->cs_RNTI = NULL; + break; + case NR_SetupRelease_RNTI_Value_PR_setup: + mac->cs_RNTI = &phy_cell_group_configP->cs_RNTI->choice.setup; + break; + default: + break; + } + } + } + */ + } + return 0; + } diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index b97d4696e7..405ea95eb1 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -50,6 +50,7 @@ #include "NR_ServingCellConfig.h" #include "fapi_nr_ue_interface.h" #include "NR_IF_Module.h" +#include "../NR_MAC_gNB/nr_mac_common.h" #include "PHY/defs_nr_common.h" #include "openair2/LAYER2/NR_MAC_COMMON/nr_mac.h" @@ -129,33 +130,48 @@ typedef struct { } NR_UE_SCHEDULING_INFO; +#define MAX_NUM_BWP 2 + +typedef enum { + RA_IDLE=0, + WAIT_RAR=1, + WAIT_CONTENTION_RESOLUTION=2 +} RA_state_t; /*!\brief Top level UE MAC structure */ typedef struct { - + + NR_ServingCellConfigCommon_t *scc; + NR_ServingCellConfig_t *scd; + int servCellIndex; //// MAC config - NR_DRX_Config_t *drx_Config; - NR_SchedulingRequestConfig_t *schedulingRequestConfig; - NR_BSR_Config_t *bsr_Config; - NR_TAG_Config_t *tag_Config; - NR_PHR_Config_t *phr_Config; - NR_RNTI_Value_t *cs_RNTI; - NR_MIB_t *mib; - + NR_DRX_Config_t *drx_Config; + NR_SchedulingRequestConfig_t *schedulingRequestConfig; + NR_BSR_Config_t *bsr_Config; + NR_TAG_Config_t *tag_Config; + NR_PHR_Config_t *phr_Config; + NR_RNTI_Value_t *cs_RNTI; + NR_MIB_t *mib; + + NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP]; + NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP]; + NR_ControlResourceSet_t *coreset[MAX_NUM_BWP][FAPI_NR_MAX_CORESET_PER_BWP]; + NR_SearchSpace_t *SSpace[MAX_NUM_BWP][FAPI_NR_MAX_CORESET_PER_BWP][FAPI_NR_MAX_SS_PER_CORESET]; + /// Type0-PDCCH seach space fapi_nr_dl_config_dci_dl_pdu_rel15_t type0_pdcch_dci_config; uint32_t type0_pdcch_ss_mux_pattern; SFN_C_TYPE type0_pdcch_ss_sfn_c; uint32_t type0_pdcch_ss_n_c; uint32_t type0_pdcch_consecutive_slots; - - /// Random access parameter + /// state of RA procedure + RA_state_t ra_state; + /// RA-rnti uint16_t ra_rnti; + /// Temporary CRNTI + uint16_t t_crnti; + /// CRNTI uint16_t crnti; - //BWP params - NR_BWP_PARMS initial_bwp_dl; - NR_BWP_PARMS initial_bwp_ul; - //// FAPI-like interface message fapi_nr_tx_request_t tx_request; fapi_nr_ul_config_request_t ul_config_request; @@ -204,7 +220,139 @@ typedef enum frequency_range_e { FR2 } frequency_range_t; +typedef struct { + uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS: + uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213] + uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1: + uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213] + uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits + uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3 + uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND: + uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND: + uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND: + uint8_t short_messages ; // 9 SHORT_MESSAGES: + uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered + // (NOTE 1) If DCI format 0_0 is monitored in common search space + // and if the number of information bits in the DCI format 0_0 prior to padding + // is larger than the payload size of the DCI format 1_0 monitored in common search space + // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 + // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0 + uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + // where I the number of entries in the higher layer parameter pusch-AllocationList + uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] + uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set + uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER: + uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 + uint8_t tb1_mcs ; // 18 TB1_MCS: + uint8_t tb1_ndi ; // 19 TB1_NDI: + uint8_t tb1_rv ; // 20 TB1_RV: + uint8_t tb2_mcs ; // 21 TB2_MCS: + uint8_t tb2_ndi ; // 22 TB2_NDI: + uint8_t tb2_rv ; // 23 TB2_RV: + uint8_t mcs ; // 24 MCS: + uint8_t ndi ; // 25 NDI: + uint8_t rv ; // 26 RV: + uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER: + uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI + // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI + // 0 otherwise + uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK + uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks + uint8_t tb_scaling ; // 31 TB_SCALING: + uint8_t tpc_pusch ; // 32 TPC_PUSCH: + uint8_t tpc_pucch ; // 33 TPC_PUCCH: + uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND: + uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: + uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND: + uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS: + uint8_t antenna_ports ; // 38 ANTENNA_PORTS: + uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits + uint8_t srs_request ; // 40 SRS_REQUEST: + uint8_t tpc_cmd ; // 41 TPC_CMD: + uint8_t csi_request ; // 42 CSI_REQUEST: + uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH + uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator + uint8_t ptrs_dmrs ; // 45 PTRS_DMRS: + uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND: + uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding + // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise + uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH + uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space + // and if the number of information bits in the DCI format 0_0 prior to padding + // is less than the payload size of the DCI format 1_0 monitored in common search space + // zeros shall be appended to the DCI format 0_0 + // until the payload size equals that of the DCI format 1_0 + uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0: + uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX: + uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0: + uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX + uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX + uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI +} nr_dci_pdu_rel15_t; + #define NUM_SLOT_FRAME 10 +#define NBR_NR_FORMATS 8 // The number of formats is 8 (0_0, 0_1, 1_0, 1_1, 2_0, 2_1, 2_2, 2_3) +#define NBR_NR_DCI_FIELDS 56 // The number of different dci fields defined in TS 38.212 subclause 7.3.1 + +#define IDENTIFIER_DCI_FORMATS 0 +#define CARRIER_IND 1 +#define SUL_IND_0_1 2 +#define SLOT_FORMAT_IND 3 +#define PRE_EMPTION_IND 4 +#define BLOCK_NUMBER 5 +#define CLOSE_LOOP_IND 6 +#define BANDWIDTH_PART_IND 7 +#define SHORT_MESSAGE_IND 8 +#define SHORT_MESSAGES 9 +#define FREQ_DOM_RESOURCE_ASSIGNMENT_UL 10 +#define FREQ_DOM_RESOURCE_ASSIGNMENT_DL 11 +#define TIME_DOM_RESOURCE_ASSIGNMENT 12 +#define VRB_TO_PRB_MAPPING 13 +#define PRB_BUNDLING_SIZE_IND 14 +#define RATE_MATCHING_IND 15 +#define ZP_CSI_RS_TRIGGER 16 +#define FREQ_HOPPING_FLAG 17 +#define TB1_MCS 18 +#define TB1_NDI 19 +#define TB1_RV 20 +#define TB2_MCS 21 +#define TB2_NDI 22 +#define TB2_RV 23 +#define MCS 24 +#define NDI 25 +#define RV 26 +#define HARQ_PROCESS_NUMBER 27 +#define DAI_ 28 +#define FIRST_DAI 29 +#define SECOND_DAI 30 +#define TB_SCALING 31 +#define TPC_PUSCH 32 +#define TPC_PUCCH 33 +#define PUCCH_RESOURCE_IND 34 +#define PDSCH_TO_HARQ_FEEDBACK_TIME_IND 35 +#define SRS_RESOURCE_IND 36 +#define PRECOD_NBR_LAYERS 37 +#define ANTENNA_PORTS 38 +#define TCI 39 +#define SRS_REQUEST 40 +#define TPC_CMD 41 +#define CSI_REQUEST 42 +#define CBGTI 43 +#define CBGFI 44 +#define PTRS_DMRS 45 +#define BETA_OFFSET_IND 46 +#define DMRS_SEQ_INI 47 +#define UL_SCH_IND 48 +#define PADDING_NR_DCI 49 +#define SUL_IND_0_0 50 +#define RA_PREAMBLE_INDEX 51 +#define SUL_IND_1_0 52 +#define SS_PBCH_INDEX 53 +#define PRACH_MASK_INDEX 54 +#define RESERVED_NR_DCI 55 + /*@}*/ #endif /*__LAYER2_MAC_DEFS_H__ */ diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 65f9a325fd..36d285e320 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -20,7 +20,7 @@ */ /* \file proto.h - * \brief MAC functions prototypes for eNB and UE + * \brief MAC functions prototypes for gNB and UE * \author R. Knopp, K.H. HSU * \date 2018 * \version 0.1 @@ -35,7 +35,9 @@ #include "mac_defs.h" #include "mac.h" -#include +#include "PHY/defs_nr_UE.h" +#include "RRC/NR_UE/rrc_defs.h" + /**\brief decode mib pdu in NR_UE, from if_module ul_ind with P7 tx_ind message \param module_id module id @@ -47,7 +49,6 @@ \param pdu_length length of pdu \param cell_id cell id */ int8_t nr_ue_decode_mib( - UE_nr_rxtx_proc_t *proc, module_id_t module_id, int cc_id, uint8_t gNB_index, @@ -63,20 +64,18 @@ int8_t nr_ue_decode_mib( \param cc_id component carrier id \param gNB_index gNB index \param mibP pointer to RRC message MIB - \param mac_cell_group_configP pointer to RRC message MAC-related in cell group config - \param phy_cell_group_configP pointer to RRC message PHY-related in cell group config + \param sccP pointer to ServingCellConfigCommon structure, \param spcell_configP pointer to RRC message serving cell config*/ -int nr_rrc_mac_config_req_ue( - module_id_t module_id, - int cc_id, - uint8_t gNB_index, - NR_MIB_t *mibP, - NR_MAC_CellGroupConfig_t *mac_cell_group_configP, - NR_PhysicalCellGroupConfig_t *phy_cell_group_configP, - NR_SpCellConfig_t *spcell_configP ); - +int nr_rrc_mac_config_req_ue( + module_id_t module_id, + int cc_idP, + uint8_t gNB_index, + NR_MIB_t *mibP, + //NR_ServingCellConfigCommon_t *sccP, + NR_SpCellConfig_t *spCell_ConfigP); + /**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/ -int nr_l2_init_ue(void); +NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst); /**\brief fetch MAC instance by module_id, within 0 - (NB_NR_UE_MAC_INST-1) \param module_id index of MAC instance(s)*/ @@ -116,7 +115,8 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe); -int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format); +int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format); +int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci); uint32_t get_ssb_frame(uint32_t test); uint32_t get_ssb_slot(uint32_t ssb_index); @@ -130,38 +130,45 @@ uint32_t mr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t @param module_idP Instance id of UE in machine @param CC_id Component Carrier index @param frameP Current Rx frame -@param ttiP Current Rx tti subframe +@param slotP Current Rx slot @param pdu Pointer to the MAC PDU @param pdu_len Length of the MAC PDU -@param eNB_id Index of eNB that UE is attached to +@param gNB_id Index of gNB that UE is attached to +@param ul_time_alignment of struct handling the timing advance parameters @returns void */ -void nr_ue_send_sdu(module_id_t module_idP,uint8_t CC_id, frame_t frameP, uint8_t ttiP, - uint8_t * pdu, uint16_t pdu_len, uint8_t gNB_index, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); +void nr_ue_send_sdu(module_id_t module_idP, + uint8_t CC_id, + frame_t frameP, + int slotP, + uint8_t * pdu, + uint16_t pdu_len, + uint8_t gNB_index, + NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); -void nr_ue_process_mac_pdu( - module_id_t module_idP, - uint8_t CC_id, - frame_t frameP, - uint8_t *pduP, - uint16_t mac_pdu_len, - uint8_t eNB_index, - NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); +void nr_ue_process_mac_pdu(module_id_t module_idP, + uint8_t CC_id, + frame_t frameP, + uint8_t *pduP, + uint16_t mac_pdu_len, + uint8_t gNB_index, + NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len); -uint8_t nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, - sub_frame_t subframe, uint8_t eNB_index, - uint8_t *ulsch_buffer, uint16_t buflen, uint8_t *access_mode); +void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot); -uint16_t -nr_generate_ulsch_pdu(uint8_t *mac_pdu, - uint8_t *sdus_payload, - uint8_t num_sdus, - uint16_t *sdu_lengths, - uint8_t *sdu_lcids, - uint16_t *crnti, - uint16_t buflen); +void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, + int dci_format, + uint8_t dci_length, + uint16_t rnti, + uint64_t *dci_pdu, + nr_dci_pdu_rel15_t *nr_pdci_info_extracted); + + +int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, + int nrofDownlinkSlots, int nrofDownlinkSymbols, + int nrofUplinkSlots, int nrofUplinkSymbols); #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c index c29f75cd01..61f9ab601e 100644 --- a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c +++ b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c @@ -43,8 +43,7 @@ static NR_UE_MAC_INST_t *nr_ue_mac_inst; -int -nr_l2_init_ue(void) +NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst) { //LOG_I(MAC, "[MAIN] MAC_INIT_GLOBAL_PARAM IN...\n"); @@ -52,17 +51,20 @@ nr_l2_init_ue(void) //init mac here nr_ue_mac_inst = (NR_UE_MAC_INST_t *)malloc(sizeof(NR_UE_MAC_INST_t)*NB_NR_UE_MAC_INST); - - if (IS_SOFTMODEM_NOS1){ + if (rrc_inst) { + nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config->spCellConfig); + + if (IS_SOFTMODEM_NOS1){ if (rlc_module_init(0) != 0) { - LOG_I(RLC, "Problem at RLC initiation \n"); + LOG_I(RLC, "Problem at RLC initiation \n"); } pdcp_layer_init(); nr_ip_over_LTE_DRB_preconfiguration(); + } } + else LOG_I(MAC,"Running without RRC instance\n"); - - return (1); + return (nr_ue_mac_inst); } NR_UE_MAC_INST_t *get_mac_inst(module_id_t module_id){ diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 2df700e031..58b312038a 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -33,8 +33,11 @@ /* MAC related headers */ #include "mac_proto.h" +#include "mac_defs.h" #include "LAYER2/NR_MAC_COMMON/nr_mac.h" #include "mac_extern.h" +#include "common/utils/nr/nr_common.h" + //#include "LAYER2/MAC/mac_vars.h" // TODO Note that mac_vars.h is not NR specific and this should be updated // also, the use of the same should be updated in nr-softmodem and nr-uesoftmodem @@ -60,186 +63,185 @@ //int mbms_rab_id = 2047; //#define ENABLE_MAC_PAYLOAD_DEBUG 1 +#define DEBUG_EXTRACT_DCI 1 extern void mac_rlc_data_ind ( - const module_id_t module_idP, - const rnti_t rntiP, - const eNB_index_t eNB_index, - const frame_t frameP, - const eNB_flag_t enb_flagP, - const MBMS_flag_t MBMS_flagP, - const logical_chan_id_t channel_idP, - char *buffer_pP, - const tb_size_t tb_sizeP, - num_tb_t num_tbP, - crc_t *crcs_pP); + const module_id_t module_idP, + const rnti_t rntiP, + const eNB_index_t eNB_index, + const frame_t frameP, + const eNB_flag_t enb_flagP, + const MBMS_flag_t MBMS_flagP, + const logical_chan_id_t channel_idP, + char *buffer_pP, + const tb_size_t tb_sizeP, + num_tb_t num_tbP, + crc_t *crcs_pP); uint32_t get_ssb_slot(uint32_t ssb_index){ - // this function now only support f <= 3GHz - return ssb_index & 0x3 ; + // this function now only support f <= 3GHz + return ssb_index & 0x3 ; - // return first_symbol(case, freq, ssb_index) / 14 + // return first_symbol(case, freq, ssb_index) / 14 } uint8_t table_9_2_2_1[16][8]={ -{0,12,2, 0, 0,3,0,0}, -{0,12,2, 0, 0,4,8,0}, -{0,12,2, 3, 0,4,8,0}, -{1,10,4, 0, 0,6,0,0}, -{1,10,4, 0, 0,3,6,9}, -{1,10,4, 2, 0,3,6,9}, -{1,10,4, 4, 0,3,6,9}, -{1,4, 10,0, 0,6,0,0}, -{1,4, 10,0, 0,3,6,9}, -{1,4, 10,2, 0,3,6,9}, -{1,4, 10,4, 0,3,6,9}, -{1,0, 14,0, 0,6,0,0}, -{1,0, 14,0, 0,3,6,9}, -{1,0, 14,2, 0,3,6,9}, -{1,0, 14,4, 0,3,6,9}, -{1,0, 14,26,0,3,0,0} + {0,12,2, 0, 0,3,0,0}, + {0,12,2, 0, 0,4,8,0}, + {0,12,2, 3, 0,4,8,0}, + {1,10,4, 0, 0,6,0,0}, + {1,10,4, 0, 0,3,6,9}, + {1,10,4, 2, 0,3,6,9}, + {1,10,4, 4, 0,3,6,9}, + {1,4, 10,0, 0,6,0,0}, + {1,4, 10,0, 0,3,6,9}, + {1,4, 10,2, 0,3,6,9}, + {1,4, 10,4, 0,3,6,9}, + {1,0, 14,0, 0,6,0,0}, + {1,0, 14,0, 0,3,6,9}, + {1,0, 14,2, 0,3,6,9}, + {1,0, 14,4, 0,3,6,9}, + {1,0, 14,26,0,3,0,0} }; int8_t nr_ue_process_dlsch(module_id_t module_id, - int cc_id, - uint8_t gNB_index, - fapi_nr_dci_indication_t *dci_ind, - void *pduP, - uint32_t pdu_len) + int cc_id, + uint8_t gNB_index, + fapi_nr_dci_indication_t *dci_ind, + void *pduP, + uint32_t pdu_len) { - NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; - //fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; - nr_phy_config_t *phy_config = &mac->phy_config; + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; + //fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; + nr_phy_config_t *phy_config = &mac->phy_config; - //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; - // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ. + //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; + // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ. + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; + for (int i=0; i<10; i++) { + if(dci_ind!=NULL){ + if (dci_ind->dci_list[i].dci_format < 2) ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; + } + } + if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) { + // fill in the elements in config request inside P5 message + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0; + for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0; + //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0; + } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; - for (int i=0; i<10; i++) { - if(dci_ind!=NULL){ - if (dci_ind->dci_list[i].dci_format < 2) ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - } + // If we handle PUCCH common + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][0]; /* format 0 1 2 3 4 */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][4]; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][2]; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][1]; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = 0; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = 0; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][3]; /* maxNrofPhysicalResourceBlocks = 275 */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = 0; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = 0; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal; + for (int i=0;iul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0; + // If we handle PUCCH dedicated + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].format; /* format 0 1 2 3 4 */ + switch (ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format){ + case pucch_format1_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.simultaneous_harq_ack_csi; + break; + case pucch_format2_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.simultaneous_harq_ack_csi; + break; + case pucch_format3_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.simultaneous_harq_ack_csi; + break; + case pucch_format4_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.simultaneous_harq_ack_csi; + break; + default: + break; } - if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) { - // fill in the elements in config request inside P5 message - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0; - for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0; - //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0; - } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ - ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; - // If we handle PUCCH common - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][0]; /* format 0 1 2 3 4 */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][4]; /* x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][2]; /* x x x x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][1]; /* x x x x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = 0; /* x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = 0; /* x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][3]; /* maxNrofPhysicalResourceBlocks = 275 */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = 0; /* x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = 0; /* x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal; - for (int i=0;iul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0; - // If we handle PUCCH dedicated - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].format; /* format 0 1 2 3 4 */ - switch (ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format){ - case pucch_format1_nr: - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.inter_slot_frequency_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.additional_dmrs; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.max_code_rate; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.number_of_slots; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.pi2bpsk; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.simultaneous_harq_ack_csi; - break; - case pucch_format2_nr: - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.inter_slot_frequency_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.additional_dmrs; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.max_code_rate; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.number_of_slots; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.pi2bpsk; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.simultaneous_harq_ack_csi; - break; - case pucch_format3_nr: - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.inter_slot_frequency_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.additional_dmrs; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.max_code_rate; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.number_of_slots; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.pi2bpsk; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.simultaneous_harq_ack_csi; - break; - case pucch_format4_nr: - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.inter_slot_frequency_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.additional_dmrs; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.max_code_rate; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.number_of_slots; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.pi2bpsk; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.simultaneous_harq_ack_csi; - break; - default: - break; - } - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].initial_cyclic_shift; /* x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_symbols; /* x x x x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_symbol_index; /* x x x x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].time_domain_occ; /* x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_prbs; /* x x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_prb; /* maxNrofPhysicalResourceBlocks = 275 */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_length; /* x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_index; /* x */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].intra_slot_frequency_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].second_hop_prb; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal; - for (int i=0;iul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */ - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0; - ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].initial_cyclic_shift; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_symbols; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_symbol_index; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].time_domain_occ; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_prbs; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_prb; /* maxNrofPhysicalResourceBlocks = 275 */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_length; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_index; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].intra_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].second_hop_prb; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal; + for (int i=0;iul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0; - } - if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){ - mac->if_module->scheduled_response(&mac->scheduled_response); - } - return 0; + } + if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){ + mac->if_module->scheduled_response(&mac->scheduled_response); + } + return 0; } - -int8_t nr_ue_decode_mib(UE_nr_rxtx_proc_t *proc, - module_id_t module_id, +int8_t nr_ue_decode_mib(module_id_t module_id, int cc_id, uint8_t gNB_index, uint8_t extra_bits, // 8bits 38.212 c7.1.1 @@ -248,490 +250,1061 @@ int8_t nr_ue_decode_mib(UE_nr_rxtx_proc_t *proc, void *pduP, uint16_t cell_id) { - LOG_I(MAC,"[L2][MAC] decode mib\n"); + LOG_I(MAC,"[L2][MAC] decode mib\n"); - NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index, NR_BCCH_BCH, (uint8_t *) pduP, 3 ); // fixed 3 bytes MIB PDU + nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index, NR_BCCH_BCH, (uint8_t *) pduP, 3 ); // fixed 3 bytes MIB PDU - AssertFatal(mac->mib != NULL, "nr_ue_decode_mib() mac->mib == NULL\n"); - //if(mac->mib != NULL){ - uint16_t frame = (mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused); - uint16_t frame_number_4lsb = 0; - for (int i=0; i<4; i++) - frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i); - uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4] - uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5] - - uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset; + AssertFatal(mac->mib != NULL, "nr_ue_decode_mib() mac->mib == NULL\n"); + //if(mac->mib != NULL){ + uint16_t frame = (mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused); + uint16_t frame_number_4lsb = 0; + for (int i=0; i<4; i++) + frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i); + uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4] + uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5] + uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset; - //uint32_t ssb_index = 0; // TODO: ssb_index should obtain from L1 in case Lssb != 64 + //uint32_t ssb_index = 0; // TODO: ssb_index should obtain from L1 in case Lssb != 64 - frame = frame << 4; - frame = frame | frame_number_4lsb; + frame = frame << 4; + frame = frame | frame_number_4lsb; - if(ssb_length == 64){ - ssb_index = ssb_index & (( extra_bits >> 2 ) & 0x1C ); // { extra_bits[5:7], ssb_index[2:0] } - }else{ - if(ssb_subcarrier_offset_msb){ - ssb_subcarrier_offset = ssb_subcarrier_offset | 0x10; - } - } + if(ssb_length == 64){ + ssb_index = ssb_index & (( extra_bits >> 2 ) & 0x1C ); // { extra_bits[5:7], ssb_index[2:0] } + }else{ + if(ssb_subcarrier_offset_msb){ + ssb_subcarrier_offset = ssb_subcarrier_offset | 0x10; + } + } #ifdef DEBUG_MIB - LOG_I(MAC,"system frame number(6 MSB bits): %d\n", mac->mib->systemFrameNumber.buf[0]); - LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame); - LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon); - LOG_I(MAC,"ssb carrier offset(with MSB): %d\n", (int)ssb_subcarrier_offset); - LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position); - LOG_I(MAC,"pdcch config sib1: %d\n", (int)mac->mib->pdcch_ConfigSIB1); - LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred); - LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection); - LOG_I(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit); - LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index); + LOG_I(MAC,"system frame number(6 MSB bits): %d\n", mac->mib->systemFrameNumber.buf[0]); + LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame); + LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon); + LOG_I(MAC,"ssb carrier offset(with MSB): %d\n", (int)ssb_subcarrier_offset); + LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position); + LOG_I(MAC,"pdcch config sib1: %d\n", (int)mac->mib->pdcch_ConfigSIB1); + LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred); + LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection); + LOG_I(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit); + LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index); #endif - subcarrier_spacing_t scs_ssb = scs_30kHz; // default for - //const uint32_t scs_index = 0; - const uint32_t num_slot_per_frame = 20; - subcarrier_spacing_t scs_pdcch; + subcarrier_spacing_t scs_ssb = scs_30kHz; // default for + //const uint32_t scs_index = 0; + const uint32_t num_slot_per_frame = 20; + subcarrier_spacing_t scs_pdcch; - // assume carrier frequency < 6GHz - if(mac->mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60){ - scs_pdcch = scs_15kHz; - }else{ //NR_MIB__subCarrierSpacingCommon_scs30or120 - scs_pdcch = scs_30kHz; - } + // assume carrier frequency < 6GHz + if(mac->mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60){ + scs_pdcch = scs_15kHz; + }else{ //NR_MIB__subCarrierSpacingCommon_scs30or120 + scs_pdcch = scs_30kHz; + } - channel_bandwidth_t min_channel_bw = bw_10MHz; // deafult for testing + channel_bandwidth_t min_channel_bw = bw_10MHz; // deafult for testing - uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13 - frequency_range_t frequency_range = FR1; - uint32_t index_4msb = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero); - uint32_t index_4lsb = (mac->mib->pdcch_ConfigSIB1.searchSpaceZero); - int32_t num_rbs = -1; - int32_t num_symbols = -1; - int32_t rb_offset = -1; - //LOG_I(MAC,"<<<<<<<<mib->pdcch_ConfigSIB1,index_4msb,index_4lsb,scs_ssb,scs_pdcch, (scs_ssb << 5)|scs_pdcch); + uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13 + frequency_range_t frequency_range = FR1; + uint32_t index_4msb = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero); + uint32_t index_4lsb = (mac->mib->pdcch_ConfigSIB1.searchSpaceZero); + int32_t num_rbs = -1; + int32_t num_symbols = -1; + int32_t rb_offset = -1; + //LOG_I(MAC,"<<<<<<<<mib->pdcch_ConfigSIB1,index_4msb,index_4lsb,scs_ssb,scs_pdcch, (scs_ssb << 5)|scs_pdcch); - // type0-pdcch coreset - switch( (scs_ssb << 5)|scs_pdcch ){ - case (scs_15kHz << 5) | scs_15kHz : - AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n"); - mac->type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_1_c2[index_4msb]; - num_symbols = table_38213_13_1_c3[index_4msb]; - rb_offset = table_38213_13_1_c4[index_4msb]; - break; + // type0-pdcch coreset + switch( (scs_ssb << 5)|scs_pdcch ){ + case (scs_15kHz << 5) | scs_15kHz : + AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n"); + mac->type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_1_c2[index_4msb]; + num_symbols = table_38213_13_1_c3[index_4msb]; + rb_offset = table_38213_13_1_c4[index_4msb]; + break; - case (scs_15kHz << 5) | scs_30kHz: - AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n"); - mac->type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_2_c2[index_4msb]; - num_symbols = table_38213_13_2_c3[index_4msb]; - rb_offset = table_38213_13_2_c4[index_4msb]; - break; + case (scs_15kHz << 5) | scs_30kHz: + AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n"); + mac->type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_2_c2[index_4msb]; + num_symbols = table_38213_13_2_c3[index_4msb]; + rb_offset = table_38213_13_2_c4[index_4msb]; + break; - case (scs_30kHz << 5) | scs_15kHz: - if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){ - AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n"); - mac->type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_3_c2[index_4msb]; - num_symbols = table_38213_13_3_c3[index_4msb]; - rb_offset = table_38213_13_3_c4[index_4msb]; - }else if(min_channel_bw & bw_40MHz){ - AssertFatal(index_4msb < 9, "38.213 Table 13-5 4 MSB out of range\n"); - mac->type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_5_c2[index_4msb]; - num_symbols = table_38213_13_5_c3[index_4msb]; - rb_offset = table_38213_13_5_c4[index_4msb]; - }else{ ; } + case (scs_30kHz << 5) | scs_15kHz: + if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){ + AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n"); + mac->type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_3_c2[index_4msb]; + num_symbols = table_38213_13_3_c3[index_4msb]; + rb_offset = table_38213_13_3_c4[index_4msb]; + }else if(min_channel_bw & bw_40MHz){ + AssertFatal(index_4msb < 9, "38.213 Table 13-5 4 MSB out of range\n"); + mac->type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_5_c2[index_4msb]; + num_symbols = table_38213_13_5_c3[index_4msb]; + rb_offset = table_38213_13_5_c4[index_4msb]; + }else{ ; } - break; + break; - case (scs_30kHz << 5) | scs_30kHz: - if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){ - mac->type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_4_c2[index_4msb]; - num_symbols = table_38213_13_4_c3[index_4msb]; - rb_offset = table_38213_13_4_c4[index_4msb]; - LOG_I(MAC,"<<<<<<<<type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_6_c2[index_4msb]; - num_symbols = table_38213_13_6_c3[index_4msb]; - rb_offset = table_38213_13_6_c4[index_4msb]; - }else{ ; } - break; + case (scs_30kHz << 5) | scs_30kHz: + if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){ + mac->type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_4_c2[index_4msb]; + num_symbols = table_38213_13_4_c3[index_4msb]; + rb_offset = table_38213_13_4_c4[index_4msb]; + LOG_I(MAC,"<<<<<<<<type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_6_c2[index_4msb]; + num_symbols = table_38213_13_6_c3[index_4msb]; + rb_offset = table_38213_13_6_c4[index_4msb]; + }else{ ; } + break; - case (scs_120kHz << 5) | scs_60kHz: - AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n"); - if(index_4msb & 0x7){ - mac->type0_pdcch_ss_mux_pattern = 1; - }else if(index_4msb & 0x18){ - mac->type0_pdcch_ss_mux_pattern = 2; - }else{ ; } + case (scs_120kHz << 5) | scs_60kHz: + AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n"); + if(index_4msb & 0x7){ + mac->type0_pdcch_ss_mux_pattern = 1; + }else if(index_4msb & 0x18){ + mac->type0_pdcch_ss_mux_pattern = 2; + }else{ ; } - num_rbs = table_38213_13_7_c2[index_4msb]; - num_symbols = table_38213_13_7_c3[index_4msb]; - if(!is_condition_A && (index_4msb == 8 || index_4msb == 10)){ - rb_offset = table_38213_13_7_c4[index_4msb] - 1; - }else{ - rb_offset = table_38213_13_7_c4[index_4msb]; - } - break; + num_rbs = table_38213_13_7_c2[index_4msb]; + num_symbols = table_38213_13_7_c3[index_4msb]; + if(!is_condition_A && (index_4msb == 8 || index_4msb == 10)){ + rb_offset = table_38213_13_7_c4[index_4msb] - 1; + }else{ + rb_offset = table_38213_13_7_c4[index_4msb]; + } + break; - case (scs_120kHz << 5) | scs_120kHz: - AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n"); - if(index_4msb & 0x3){ - mac->type0_pdcch_ss_mux_pattern = 1; - }else if(index_4msb & 0x0c){ - mac->type0_pdcch_ss_mux_pattern = 3; - } + case (scs_120kHz << 5) | scs_120kHz: + AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n"); + if(index_4msb & 0x3){ + mac->type0_pdcch_ss_mux_pattern = 1; + }else if(index_4msb & 0x0c){ + mac->type0_pdcch_ss_mux_pattern = 3; + } - num_rbs = table_38213_13_8_c2[index_4msb]; - num_symbols = table_38213_13_8_c3[index_4msb]; - if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){ - rb_offset = table_38213_13_8_c4[index_4msb] - 1; - }else{ - rb_offset = table_38213_13_8_c4[index_4msb]; - } - break; + num_rbs = table_38213_13_8_c2[index_4msb]; + num_symbols = table_38213_13_8_c3[index_4msb]; + if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){ + rb_offset = table_38213_13_8_c4[index_4msb] - 1; + }else{ + rb_offset = table_38213_13_8_c4[index_4msb]; + } + break; - case (scs_240kHz << 5) | scs_60kHz: - AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n"); - mac->type0_pdcch_ss_mux_pattern = 1; - num_rbs = table_38213_13_9_c2[index_4msb]; - num_symbols = table_38213_13_9_c3[index_4msb]; - rb_offset = table_38213_13_9_c4[index_4msb]; - break; + case (scs_240kHz << 5) | scs_60kHz: + AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n"); + mac->type0_pdcch_ss_mux_pattern = 1; + num_rbs = table_38213_13_9_c2[index_4msb]; + num_symbols = table_38213_13_9_c3[index_4msb]; + rb_offset = table_38213_13_9_c4[index_4msb]; + break; - case (scs_240kHz << 5) | scs_120kHz: - AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n"); - if(index_4msb & 0x3){ - mac->type0_pdcch_ss_mux_pattern = 1; - }else if(index_4msb & 0x0c){ - mac->type0_pdcch_ss_mux_pattern = 2; - } - num_rbs = table_38213_13_10_c2[index_4msb]; - num_symbols = table_38213_13_10_c3[index_4msb]; - if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){ - rb_offset = table_38213_13_10_c4[index_4msb]-1; - }else{ - rb_offset = table_38213_13_10_c4[index_4msb]; - } + case (scs_240kHz << 5) | scs_120kHz: + AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n"); + if(index_4msb & 0x3){ + mac->type0_pdcch_ss_mux_pattern = 1; + }else if(index_4msb & 0x0c){ + mac->type0_pdcch_ss_mux_pattern = 2; + } + num_rbs = table_38213_13_10_c2[index_4msb]; + num_symbols = table_38213_13_10_c3[index_4msb]; + if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){ + rb_offset = table_38213_13_10_c4[index_4msb]-1; + }else{ + rb_offset = table_38213_13_10_c4[index_4msb]; + } - break; + break; - default: - break; - } + default: + break; + } - AssertFatal(num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined"); - AssertFatal(num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined"); - AssertFatal(rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined"); + AssertFatal(num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined"); + AssertFatal(num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined"); + AssertFatal(rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined"); - //uint32_t cell_id = 0; // obtain from L1 later + //uint32_t cell_id = 0; // obtain from L1 later - //mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset; - //mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1; - uint64_t mask = 0x0; - uint8_t i; - for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs - mask = mask >> 1; - mask = mask | 0x100000000000; - } - //LOG_I(MAC,">>>>>>>>mask %x num_rbs %d rb_offset %d\n", mask, num_rbs, rb_offset); - mac->type0_pdcch_dci_config.coreset.frequency_domain_resource = mask; - mac->type0_pdcch_dci_config.coreset.rb_offset = rb_offset; // additional parameter other than coreset + //mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset; + //mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1; + uint64_t mask = 0x0; + uint8_t i; + for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs + mask = mask >> 1; + mask = mask | 0x100000000000; + } + //LOG_I(MAC,">>>>>>>>mask %x num_rbs %d rb_offset %d\n", mask, num_rbs, rb_offset); + /* + mac->type0_pdcch_dci_config.coreset.frequency_domain_resource = mask; + mac->type0_pdcch_dci_config.coreset.rb_offset = rb_offset; // additional parameter other than coreset - //mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols; - mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED; - mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2 - mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2; // R 38.211 7.3.2.2 - mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_shift_index = cell_id; - mac->type0_pdcch_dci_config.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE; - mac->type0_pdcch_dci_config.coreset.pdcch_dmrs_scrambling_id = cell_id; + //mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols; + mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED; + mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2 + mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2; // R 38.211 7.3.2.2 + mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_shift_index = cell_id; + mac->type0_pdcch_dci_config.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE; + mac->type0_pdcch_dci_config.coreset.pdcch_dmrs_scrambling_id = cell_id; + */ - // type0-pdcch search space - float big_o; - float big_m; - uint32_t temp; - SFN_C_TYPE sfn_c = SFN_C_IMPOSSIBLE; // only valid for mux=1 - uint32_t n_c = UINT_MAX; - uint32_t number_of_search_space_per_slot = UINT_MAX; - uint32_t first_symbol_index = UINT_MAX; - uint32_t search_space_duration; // element of search space - uint32_t coreset_duration; // element of coreset - - // 38.213 table 10.1-1 - /// MUX PATTERN 1 - if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR1){ - big_o = table_38213_13_11_c1[index_4lsb]; - number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb]; - big_m = table_38213_13_11_c3[index_4lsb]; + // type0-pdcch search space + float big_o; + float big_m; + uint32_t temp; + SFN_C_TYPE sfn_c=SFN_C_IMPOSSIBLE; // only valid for mux=1 + uint32_t n_c=UINT_MAX; + uint32_t number_of_search_space_per_slot=UINT_MAX; + uint32_t first_symbol_index=UINT_MAX; + uint32_t search_space_duration; // element of search space + uint32_t coreset_duration; // element of coreset + // 38.213 table 10.1-1 - temp = (uint32_t)(big_o*pow(2, scs_pdcch)) + (uint32_t)(ssb_index*big_m); - n_c = temp / num_slot_per_frame; - if((temp/num_slot_per_frame) & 0x1){ - sfn_c = SFN_C_MOD_2_EQ_1; - }else{ - sfn_c = SFN_C_MOD_2_EQ_0; - } + /// MUX PATTERN 1 + if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR1){ + big_o = table_38213_13_11_c1[index_4lsb]; + number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb]; + big_m = table_38213_13_11_c3[index_4lsb]; - if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 7) && (ssb_index&1)){ - first_symbol_index = num_symbols; - }else{ - first_symbol_index = table_38213_13_11_c4[index_4lsb]; - } - // 38.213 chapter 13: over two consecutive slots - search_space_duration = 2; - } + temp = (uint32_t)(big_o*pow(2, scs_pdcch)) + (uint32_t)(ssb_index*big_m); + n_c = temp / num_slot_per_frame; + if((temp/num_slot_per_frame) & 0x1){ + sfn_c = SFN_C_MOD_2_EQ_1; + }else{ + sfn_c = SFN_C_MOD_2_EQ_0; + } - if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR2){ - big_o = table_38213_13_12_c1[index_4lsb]; - number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb]; - big_m = table_38213_13_12_c3[index_4lsb]; + if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 7) && (ssb_index&1)){ + first_symbol_index = num_symbols; + }else{ + first_symbol_index = table_38213_13_11_c4[index_4lsb]; + } + // 38.213 chapter 13: over two consecutive slots + search_space_duration = 2; + } - if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 10) && (ssb_index&1)){ - first_symbol_index = 7; - }else if((index_4lsb == 6 || index_4lsb == 7 || index_4lsb == 8 || index_4lsb == 11) && (ssb_index&1)){ - first_symbol_index = num_symbols; - }else{ - first_symbol_index = 0; - } - // 38.213 chapter 13: over two consecutive slots - search_space_duration = 2; - } + if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR2){ + big_o = table_38213_13_12_c1[index_4lsb]; + number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb]; + big_m = table_38213_13_12_c3[index_4lsb]; - /// MUX PATTERN 2 - if(mac->type0_pdcch_ss_mux_pattern == 2){ + if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 10) && (ssb_index&1)){ + first_symbol_index = 7; + }else if((index_4lsb == 6 || index_4lsb == 7 || index_4lsb == 8 || index_4lsb == 11) && (ssb_index&1)){ + first_symbol_index = num_symbols; + }else{ + first_symbol_index = 0; + } + // 38.213 chapter 13: over two consecutive slots + search_space_duration = 2; + } + + /// MUX PATTERN 2 + if(mac->type0_pdcch_ss_mux_pattern == 2){ - if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_60kHz)){ - // 38.213 Table 13-13 - AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n"); - // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot - //sfn_c = SFN_C_EQ_SFN_SSB; - n_c = get_ssb_slot(ssb_index); - switch(ssb_index & 0x3){ // ssb_index(i) mod 4 - case 0: - first_symbol_index = 0; - break; - case 1: - first_symbol_index = 1; - break; - case 2: - first_symbol_index = 6; - break; - case 3: - first_symbol_index = 7; - break; - default: break; - } + if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_60kHz)){ + // 38.213 Table 13-13 + AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n"); + // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot + // sfn_c = SFN_C_EQ_SFN_SSB; + n_c = get_ssb_slot(ssb_index); + switch(ssb_index & 0x3){ // ssb_index(i) mod 4 + case 0: + first_symbol_index = 0; + break; + case 1: + first_symbol_index = 1; + break; + case 2: + first_symbol_index = 6; + break; + case 3: + first_symbol_index = 7; + break; + default: break; + } - }else if((scs_ssb == scs_240kHz) && (scs_pdcch == scs_120kHz)){ - // 38.213 Table 13-14 - AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n"); - // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot - //sfn_c = SFN_C_EQ_SFN_SSB; - n_c = get_ssb_slot(ssb_index); - switch(ssb_index & 0x7){ // ssb_index(i) mod 8 - case 0: - first_symbol_index = 0; - break; - case 1: - first_symbol_index = 1; - break; - case 2: - first_symbol_index = 2; - break; - case 3: - first_symbol_index = 3; - break; - case 4: - first_symbol_index = 12; - n_c = get_ssb_slot(ssb_index) - 1; - break; - case 5: - first_symbol_index = 13; - n_c = get_ssb_slot(ssb_index) - 1; - break; - case 6: - first_symbol_index = 0; - break; - case 7: - first_symbol_index = 1; - break; - default: break; - } - }else{ ; } - // 38.213 chapter 13: over one slot - search_space_duration = 1; - } + }else if((scs_ssb == scs_240kHz) && (scs_pdcch == scs_120kHz)){ + // 38.213 Table 13-14 + AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n"); + // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot + // sfn_c = SFN_C_EQ_SFN_SSB; + n_c = get_ssb_slot(ssb_index); + switch(ssb_index & 0x7){ // ssb_index(i) mod 8 + case 0: + first_symbol_index = 0; + break; + case 1: + first_symbol_index = 1; + break; + case 2: + first_symbol_index = 2; + break; + case 3: + first_symbol_index = 3; + break; + case 4: + first_symbol_index = 12; + n_c = get_ssb_slot(ssb_index) - 1; + break; + case 5: + first_symbol_index = 13; + n_c = get_ssb_slot(ssb_index) - 1; + break; + case 6: + first_symbol_index = 0; + break; + case 7: + first_symbol_index = 1; + break; + default: break; + } + }else{ ; } + // 38.213 chapter 13: over one slot + search_space_duration = 1; + } - /// MUX PATTERN 3 - if(mac->type0_pdcch_ss_mux_pattern == 3){ - if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_120kHz)){ - // 38.213 Table 13-15 - AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n"); - // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot - //sfn_c = SFN_C_EQ_SFN_SSB; - n_c = get_ssb_slot(ssb_index); - switch(ssb_index & 0x3){ // ssb_index(i) mod 4 - case 0: - first_symbol_index = 4; - break; - case 1: - first_symbol_index = 8; - break; - case 2: - first_symbol_index = 2; - break; - case 3: - first_symbol_index = 6; - break; - default: break; - } - }else{ ; } - // 38.213 chapter 13: over one slot - search_space_duration = 1; - } + /// MUX PATTERN 3 + if(mac->type0_pdcch_ss_mux_pattern == 3){ + if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_120kHz)){ + // 38.213 Table 13-15 + AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n"); + // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot + // sfn_c = SFN_C_EQ_SFN_SSB; + n_c = get_ssb_slot(ssb_index); + switch(ssb_index & 0x3){ // ssb_index(i) mod 4 + case 0: + first_symbol_index = 4; + break; + case 1: + first_symbol_index = 8; + break; + case 2: + first_symbol_index = 2; + break; + case 3: + first_symbol_index = 6; + break; + default: break; + } + }else{ ; } + // 38.213 chapter 13: over one slot + search_space_duration = 1; + } - AssertFatal(number_of_search_space_per_slot!=UINT_MAX,""); - coreset_duration = num_symbols * number_of_search_space_per_slot; - - mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0]; - mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1]; - mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4 - mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8 - mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16 - mac->type0_pdcch_dci_config.duration = search_space_duration; - mac->type0_pdcch_dci_config.coreset.duration = coreset_duration; // coreset - AssertFatal(first_symbol_index!=UINT_MAX,""); - mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff; - - AssertFatal(sfn_c!=SFN_C_IMPOSSIBLE,""); - AssertFatal(n_c!=UINT_MAX,""); - mac->type0_pdcch_ss_sfn_c = sfn_c; - mac->type0_pdcch_ss_n_c = n_c; + AssertFatal(number_of_search_space_per_slot!=UINT_MAX,""); + coreset_duration = num_symbols * number_of_search_space_per_slot; + /* + mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0]; + mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1]; + mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4 + mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8 + mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16 + mac->type0_pdcch_dci_config.duration = search_space_duration; + mac->type0_pdcch_dci_config.coreset.duration = coreset_duration; // coreset + AssertFatal(first_symbol_index!=UINT_MAX,""); + mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff; + */ + AssertFatal(sfn_c!=SFN_C_IMPOSSIBLE,""); + AssertFatal(n_c!=UINT_MAX,""); + mac->type0_pdcch_ss_sfn_c = sfn_c; + mac->type0_pdcch_ss_n_c = n_c; - // fill in the elements in config request inside P5 message - mac->phy_config.Mod_id = module_id; - mac->phy_config.CC_id = cc_id; + // fill in the elements in config request inside P5 message + mac->phy_config.Mod_id = module_id; + mac->phy_config.CC_id = cc_id; - mac->phy_config.config_req.pbch_config.system_frame_number = frame; // after calculation - mac->phy_config.config_req.pbch_config.subcarrier_spacing_common = mac->mib->subCarrierSpacingCommon; - mac->phy_config.config_req.pbch_config.ssb_subcarrier_offset = ssb_subcarrier_offset; // after calculation - mac->phy_config.config_req.pbch_config.dmrs_type_a_position = mac->mib->dmrs_TypeA_Position; - mac->phy_config.config_req.pbch_config.pdcch_config_sib1 = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero) * 16 + (mac->mib->pdcch_ConfigSIB1.searchSpaceZero); - mac->phy_config.config_req.pbch_config.cell_barred = mac->mib->cellBarred; - mac->phy_config.config_req.pbch_config.intra_frequency_reselection = mac->mib->intraFreqReselection; - mac->phy_config.config_req.pbch_config.half_frame_bit = half_frame_bit; - mac->phy_config.config_req.pbch_config.ssb_index = ssb_index; - mac->phy_config.config_req.config_mask |= FAPI_NR_CONFIG_REQUEST_MASK_PBCH; + mac->dl_config_request.sfn = frame; + mac->dl_config_request.slot = (ssb_index>>1) + ((ssb_index>>4)<<1); // not valid for 240kHz SCS + + //} + return 0; - if(mac->if_module != NULL && mac->if_module->phy_config_request != NULL){ - mac->if_module->phy_config_request(&mac->phy_config); - } - proc->decoded_frame_rx=frame; - //} - return 0; } // TODO: change to UE parameter, scs: 15KHz, slot duration: 1ms uint32_t get_ssb_frame(uint32_t test){ - return test; + return test; } // Performs : // 1. TODO: Call RRC for link status return to PHY // 2. TODO: Perform SR/BSR procedures for scheduling feedback // 3. TODO: Perform PHR procedures -NR_UE_L2_STATE_t nr_ue_scheduler( - const module_id_t module_id, - const uint8_t gNB_index, - const int cc_id, - const frame_t rx_frame, - const slot_t rx_slot, - const int32_t ssb_index, - const frame_t tx_frame, - const slot_t tx_slot ){ +NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, + const uint8_t gNB_index, + const int cc_id, + const frame_t rx_frame, + const slot_t rx_slot, + const int32_t ssb_index, + const frame_t tx_frame, + const slot_t tx_slot ){ - uint32_t search_space_mask = 0; - NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + uint32_t search_space_mask = 0; + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + + fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; - // check type0 from 38.213 13 - if(ssb_index != -1){ - - if(mac->type0_pdcch_ss_mux_pattern == 1){ - // 38.213 chapter 13 - if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration; - } - if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration; - } - } - if(mac->type0_pdcch_ss_mux_pattern == 2){ - // 38.213 Table 13-13, 13-14 - if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration; - } - } - if(mac->type0_pdcch_ss_mux_pattern == 3){ - // 38.213 Table 13-15 - if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration; - } - } - } - - fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; - // Type0 PDCCH search space + // check type0 from 38.213 13 if we have no CellGroupConfig + if ( mac->scd == NULL) { + if( ssb_index != -1){ + + if(mac->type0_pdcch_ss_mux_pattern == 1){ + // 38.213 chapter 13 + if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + if(mac->type0_pdcch_ss_mux_pattern == 2){ + // 38.213 Table 13-13, 13-14 + if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + if(mac->type0_pdcch_ss_mux_pattern == 3){ + // 38.213 Table 13-15 + if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + } // ssb_index != -1 + + // Type0 PDCCH search space if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){ - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1; - - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1; + + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; - /* - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set - + /* + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set + LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n", - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti, - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP); - */ - dl_config->number_pdus = dl_config->number_pdus + 1; + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti, + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP); + */ + dl_config->number_pdus = dl_config->number_pdus + 1; } + } + else { // get PDCCH configuration(s) from SCGConfig + - if(search_space_mask & type0a_pdcch){ - } + - if(search_space_mask & type1_pdcch){ - } - - if(search_space_mask & type2_pdcch){ - } - - if(search_space_mask & type3_pdcch){ - } + // get Coreset and SearchSpace Information from spCellConfigDedicated + + + + /* + if(search_space_mask & type0a_pdcch){ + } + + if(search_space_mask & type1_pdcch){ + } + + if(search_space_mask & type2_pdcch){ + } + + if(search_space_mask & type3_pdcch){ + } + */ + } - mac->scheduled_response.dl_config = dl_config; + mac->scheduled_response.dl_config = dl_config; - return UE_CONNECTION_OK; + return UE_CONNECTION_OK; } +#if 0 +uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue, + uint8_t slot, + int p, + crc_scrambled_t crc_scrambled, + uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], + uint8_t format) { + LOG_DDD("crc_scrambled=%d, n_RB_ULBWP=%d, n_RB_DLBWP=%d\n",crc_scrambled,n_RB_ULBWP,n_RB_DLBWP); + /* + * function nr_dci_format_size calculates and returns the size in bits of a determined format + * it also returns an bi-dimensional array 'dci_fields_sizes' with x rows and y columns, where: + * x is the number of fields defined in TS 38.212 subclause 7.3.1 (Each field is mapped in the order in which it appears in the description in the specification) + * y is the number of formats + * e.g.: dci_fields_sizes[10][0] contains the size in bits of the field FREQ_DOM_RESOURCE_ASSIGNMENT_UL for format 0_0 + */ + // pdsch_config contains the PDSCH-Config IE is used to configure the UE specific PDSCH parameters (TS 38.331) + PDSCH_Config_t pdsch_config = ue->PDSCH_Config; + // pusch_config contains the PUSCH-Config IE is used to configure the UE specific PUSCH parameters (TS 38.331) + PUSCH_Config_t pusch_config = ue->pusch_config; + PUCCH_Config_t pucch_config_dedicated = ue->pucch_config_dedicated_nr[eNB_id]; + crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig = ue->crossCarrierSchedulingConfig; + dmrs_UplinkConfig_t dmrs_UplinkConfig = ue->dmrs_UplinkConfig; + dmrs_DownlinkConfig_t dmrs_DownlinkConfig = ue->dmrs_DownlinkConfig; + csi_MeasConfig_t csi_MeasConfig = ue->csi_MeasConfig; + PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig= ue->PUSCH_ServingCellConfig; + PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig= ue->PDSCH_ServingCellConfig; + NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]; + // 1 CARRIER_IN + // crossCarrierSchedulingConfig from higher layers, variable crossCarrierSchedulingConfig indicates if 'cross carrier scheduling' is enabled or not: + // if No cross carrier scheduling: number of bits for CARRIER_IND is 0 + // if Cross carrier scheduling: number of bits for CARRIER_IND is 3 + // The IE CrossCarrierSchedulingConfig is used to specify the configuration when the cross-carrier scheduling is used in a cell + uint8_t crossCarrierSchedulingConfig_ind = 0; + + if (crossCarrierSchedulingConfig.schedulingCellInfo.other.cif_InSchedulingCell !=0 ) crossCarrierSchedulingConfig_ind=1; + + // 2 SUL_IND_0_1, // 40 SRS_REQUEST, // 50 SUL_IND_0_0 + // UL/SUL indicator (TS 38.331, supplementary uplink is indicated in higher layer parameter ServCellAdd-SUL from IE ServingCellConfig and ServingCellConfigCommon): + // 0 bit for UEs not configured with SUL in the cell or UEs configured with SUL in the cell but only PUCCH carrier in the cell is configured for PUSCH transmission + // 1 bit for UEs configured with SUL in the cell as defined in Table 7.3.1.1.1-1 + // sul_ind indicates whether SUL is configured in cell or not + uint8_t sul_ind=ue->supplementaryUplink.supplementaryUplink; // this value will be 0 or 1 depending on higher layer parameter ServCellAdd-SUL. FIXME!!! + // 7 BANDWIDTH_PART_IND + // number of UL BWPs configured by higher layers + uint8_t n_UL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!! + n_UL_BWP_RRC = ((n_UL_BWP_RRC > 3)?n_UL_BWP_RRC:(n_UL_BWP_RRC+1)); + // number of DL BWPs configured by higher layers + uint8_t n_DL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!! + n_DL_BWP_RRC = ((n_DL_BWP_RRC > 3)?n_DL_BWP_RRC:(n_DL_BWP_RRC+1)); + // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL + // if format0_0, only resource allocation type 1 is allowed + // if format0_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 6.1.2.2.1 + // for PUSCH hopping with resource allocation type 1 + // n_UL_hopping = 1 if the higher layer parameter frequencyHoppingOffsetLists contains two offset values + // n_UL_hopping = 2 if the higher layer parameter frequencyHoppingOffsetLists contains four offset values + uint8_t n_UL_hopping=pusch_config.n_frequencyHoppingOffsetLists; + + if (n_UL_hopping == 2) { + n_UL_hopping = 1; + } else if (n_UL_hopping == 4) { + n_UL_hopping = 2; + } else { + n_UL_hopping = 0; + } + + ul_resourceAllocation_t ul_resource_allocation_type = pusch_config.ul_resourceAllocation; + uint8_t ul_res_alloc_type_0 = 0; + uint8_t ul_res_alloc_type_1 = 0; + + if (ul_resource_allocation_type == ul_resourceAllocationType0) ul_res_alloc_type_0 = 1; + + if (ul_resource_allocation_type == ul_resourceAllocationType1) ul_res_alloc_type_1 = 1; + + if (ul_resource_allocation_type == ul_dynamicSwitch) { + ul_res_alloc_type_0 = 1; + ul_res_alloc_type_1 = 1; + } + + uint8_t n_bits_freq_dom_res_assign_ul=0,n_ul_RGB_tmp; + + if (ul_res_alloc_type_0 == 1) { // implementation of Table 6.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1 + // config1: PUSCH-Config IE contains rbg-Size ENUMERATED {config1 config2} + ul_rgb_Size_t config = pusch_config.ul_rgbSize; + uint8_t nominal_RBG_P = (config==ul_rgb_config1?2:4); + + if (n_RB_ULBWP > 36) nominal_RBG_P = (config==ul_rgb_config1?4:8); + + if (n_RB_ULBWP > 72) nominal_RBG_P = (config==ul_rgb_config1?8:16); + + if (n_RB_ULBWP > 144) nominal_RBG_P = 16; + + n_bits_freq_dom_res_assign_ul = (uint8_t)ceil((n_RB_ULBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0??? + n_ul_RGB_tmp = n_bits_freq_dom_res_assign_ul; + } + + if (ul_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_ul = (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping; + + if ((ul_res_alloc_type_0 == 1) && (ul_res_alloc_type_1 == 1)) + n_bits_freq_dom_res_assign_ul = ((n_bits_freq_dom_res_assign_ul>n_ul_RGB_tmp)?(n_bits_freq_dom_res_assign_ul+1):(n_ul_RGB_tmp+1)); + + // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL + // if format1_0, only resource allocation type 1 is allowed + // if format1_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 5.1.2.2.1 + dl_resourceAllocation_t dl_resource_allocation_type = pdsch_config.dl_resourceAllocation; + uint8_t dl_res_alloc_type_0 = 0; + uint8_t dl_res_alloc_type_1 = 0; + + if (dl_resource_allocation_type == dl_resourceAllocationType0) dl_res_alloc_type_0 = 1; + + if (dl_resource_allocation_type == dl_resourceAllocationType1) dl_res_alloc_type_1 = 1; + + if (dl_resource_allocation_type == dl_dynamicSwitch) { + dl_res_alloc_type_0 = 1; + dl_res_alloc_type_1 = 1; + } + + uint8_t n_bits_freq_dom_res_assign_dl=0,n_dl_RGB_tmp; + + if (dl_res_alloc_type_0 == 1) { // implementation of Table 5.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1 + // config1: PDSCH-Config IE contains rbg-Size ENUMERATED {config1, config2} + dl_rgb_Size_t config = pdsch_config.dl_rgbSize; + uint8_t nominal_RBG_P = (config==dl_rgb_config1?2:4); + + if (n_RB_DLBWP > 36) nominal_RBG_P = (config==dl_rgb_config1?4:8); + + if (n_RB_DLBWP > 72) nominal_RBG_P = (config==dl_rgb_config1?8:16); + + if (n_RB_DLBWP > 144) nominal_RBG_P = 16; + + n_bits_freq_dom_res_assign_dl = (uint8_t)ceil((n_RB_DLBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0??? + n_dl_RGB_tmp = n_bits_freq_dom_res_assign_dl; + } + + if (dl_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_dl = (uint8_t)(ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2))); + + if ((dl_res_alloc_type_0 == 1) && (dl_res_alloc_type_1 == 1)) + n_bits_freq_dom_res_assign_dl = ((n_bits_freq_dom_res_assign_dl>n_dl_RGB_tmp)?(n_bits_freq_dom_res_assign_dl+1):(n_dl_RGB_tmp+1)); + + // 12 TIME_DOM_RESOURCE_ASSIGNMENT + uint8_t pusch_alloc_list = pusch_config.n_push_alloc_list; + uint8_t pdsch_alloc_list = pdsch_config.n_pdsh_alloc_list; + // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] + static_bundleSize_t static_prb_BundlingType = pdsch_config.prbBundleType.staticBundling; + bundleSizeSet1_t dynamic_prb_BundlingType1 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet1; + bundleSizeSet2_t dynamic_prb_BundlingType2 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet2; + uint8_t prb_BundlingType_size=0; + + if ((static_prb_BundlingType==st_n4)||(static_prb_BundlingType==st_wideband)) prb_BundlingType_size=0; + + if ((dynamic_prb_BundlingType1==dy_1_n4)||(dynamic_prb_BundlingType1==dy_1_wideband)||(dynamic_prb_BundlingType1==dy_1_n2_wideband)||(dynamic_prb_BundlingType1==dy_1_n4_wideband)|| + (dynamic_prb_BundlingType2==dy_2_n4)||(dynamic_prb_BundlingType2==dy_2_wideband)) prb_BundlingType_size=1; + + // 15 RATE_MATCHING_IND FIXME!!! + // according to TS 38.212: Rate matching indicator – 0, 1, or 2 bits according to higher layer parameter rateMatchPattern + uint8_t rateMatching_bits = pdsch_config.n_rateMatchPatterns; + // 16 ZP_CSI_RS_TRIGGER FIXME!!! + // 0, 1, or 2 bits as defined in Subclause 5.1.4.2 of [6, TS 38.214]. + // is the number of ZP CSI-RS resource sets in the higher layer parameter zp-CSI-RS-Resource + uint8_t n_zp_bits = pdsch_config.n_zp_CSI_RS_ResourceId; + // 17 FREQ_HOPPING_FLAG + // freqHopping is defined by higher layer parameter frequencyHopping from IE PUSCH-Config. Values are ENUMERATED{mode1, mode2} + frequencyHopping_t f_hopping = pusch_config.frequencyHopping; + uint8_t freqHopping = 0; + + if ((f_hopping==f_hop_mode1)||(f_hopping==f_hop_mode2)) freqHopping = 1; + + // 28 DAI + pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook = pdsch_config.pdsch_HARQ_ACK_Codebook; + uint8_t n_dai = 0; + uint8_t n_serving_cell_dl = 1; // this is hardcoded to 1 as we need to get this value from RRC higher layers parameters. FIXME!!! + + if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl == 1)) n_dai = 2; + + if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl > 1)) n_dai = 4; + + // 29 FIRST_DAI + uint8_t codebook_HARQ_ACK = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI. + + if (pdsch_HARQ_ACK_Codebook == semiStatic) codebook_HARQ_ACK = 1; + + if (pdsch_HARQ_ACK_Codebook == dynamic) codebook_HARQ_ACK = 2; + + // 30 SECOND_DAI + uint8_t n_HARQ_ACK_sub_codebooks = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI. FIXME!!! + // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND + uint8_t pdsch_harq_t_ind = (uint8_t)ceil(log2(pucch_config_dedicated.dl_DataToUL_ACK[0])); + // 36 SRS_RESOURCE_IND + // n_SRS is the number of configured SRS resources in the SRS resource set associated with the higher layer parameter usage of value 'codeBook' or 'nonCodeBook' + // from SRS_ResourceSet_t type we should get the information of the usage parameter (with possible values beamManagement, codebook, nonCodebook, antennaSwitching) + // at frame_parms->srs_nr->p_SRS_ResourceSetList[]->usage + uint8_t n_SRS = ue->srs.number_srs_Resource_Set; + // 37 PRECOD_NBR_LAYERS + // 38 ANTENNA_PORTS + txConfig_t txConfig = pusch_config.txConfig; + transformPrecoder_t transformPrecoder = pusch_config.transformPrecoder; + codebookSubset_t codebookSubset = pusch_config.codebookSubset; + uint8_t maxRank = pusch_config.maxRank; + uint8_t num_antenna_ports = 1; // this is hardcoded. We need to get the real value FIXME!!! + uint8_t precond_nbr_layers_bits = 0; + uint8_t antenna_ports_bits_ul = 0; + + // searching number of bits at tables 7.3.1.1.2-2/3/4/5 from TS 38.212 subclause 7.3.1.1.2 + if (txConfig == txConfig_codebook) { + if (num_antenna_ports == 4) { + if ((transformPrecoder == transformPrecoder_disabled) && ((maxRank == 2)||(maxRank == 3)||(maxRank == 4))) { // Table 7.3.1.1.2-2 + if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=6; + + if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=5; + + if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=4; + } + + if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-3 + if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=5; + + if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=4; + + if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2; + } + } + + if (num_antenna_ports == 2) { + if ((transformPrecoder == transformPrecoder_disabled) && (maxRank == 2)) { // Table 7.3.1.1.2-4 + if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=4; + + if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2; + } + + if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-5 + if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=3; + + if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=1; + } + } + } + + if (txConfig == txConfig_nonCodebook) { + } + + // searching number of bits at tables 7.3.1.1.2-6/7/8/9/10/11/12/13/14/15/16/17/18/19 + if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)) { + if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 2; + + if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4; + + if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 3; + + if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4; + } + + if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type2)) { + if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 4; + + if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 5; + } + + // for format 1_1 number of bits as defined by Tables 7.3.1.2.2-1/2/3/4 + uint8_t antenna_ports_bits_dl = 0; + + if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 4; // Table 7.3.1.2.2-1 + + if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-2 + + if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-3 + + if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 6; // Table 7.3.1.2.2-4 + + // 39 TCI + uint8_t tci_bits=0; + + if (pdcch_vars2->coreset[p].tciPresentInDCI == tciPresentInDCI_enabled) tci_bits=3; + + // 42 CSI_REQUEST + // reportTriggerSize is defined in the CSI-MeasConfig IE (TS 38.331). + // Size of CSI request field in DCI (bits). Corresponds to L1 parameter 'ReportTriggerSize' (see 38.214, section 5.2) + uint8_t reportTriggerSize = csi_MeasConfig.reportTriggerSize; // value from 0..6 + // 43 CBGTI + // for format 0_1 + uint8_t maxCodeBlockGroupsPerTransportBlock = 0; + + if (PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock != 0) + maxCodeBlockGroupsPerTransportBlock = (uint8_t)PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock; + + // for format 1_1, as defined in Subclause 5.1.7 of [6, TS38.214] + uint8_t maxCodeBlockGroupsPerTransportBlock_dl = 0; + + if (PDSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock_dl != 0) + maxCodeBlockGroupsPerTransportBlock_dl = pdsch_config.maxNrofCodeWordsScheduledByDCI; // FIXME!!! + + // 44 CBGFI + uint8_t cbgfi_bit = PDSCH_ServingCellConfig.codeBlockGroupFlushIndicator; + // 45 PTRS_DMRS + // 0 bit if PTRS-UplinkConfig is not configured and transformPrecoder=disabled, or if transformPrecoder=enabled, or if maxRank=1 + // 2 bits otherwise + uint8_t ptrs_dmrs_bits=0; //FIXME!!! + // 46 BETA_OFFSET_IND + // at IE PUSCH-Config, beta_offset indicator – 0 if the higher layer parameter betaOffsets = semiStatic; otherwise 2 bits + // uci-OnPUSCH + // Selection between and configuration of dynamic and semi-static beta-offset. If the field is absent or released, the UE applies the value 'semiStatic' and the BetaOffsets + uint8_t betaOffsets = 0; + + if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_semiStatic); + + if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_dynamic) betaOffsets = 2; + + // 47 DMRS_SEQ_INI + uint8_t dmrs_seq_ini_bits_ul = 0; + uint8_t dmrs_seq_ini_bits_dl = 0; + + //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-UplinkConfig + if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.scramblingID0 != 0) && (dmrs_UplinkConfig.scramblingID1 != 0)) dmrs_seq_ini_bits_ul = 1; + + //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-DownlinkConfig + if ((dmrs_DownlinkConfig.scramblingID0 != 0) && (dmrs_DownlinkConfig.scramblingID0 != 0)) dmrs_seq_ini_bits_dl = 1; + + /* + * For format 2_2 + * + * This format supports power control commands for semi-persistent scheduling. + * As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH) + * + * This format will be implemented in the future FIXME!!! + * + */ + // 5 BLOCK_NUMBER: The parameter tpc-PUSCH or tpc-PUCCH provided by higher layers determines the index to the block number for an UL of a cell + // The following fields are defined for each block: Closed loop indicator and TPC command + // 6 CLOSE_LOOP_IND + // 41 TPC_CMD + uint8_t tpc_cmd_bit_2_2 = 2; + /* + * For format 2_3 + * + * This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control + * either because independent control is desirable or because the device is configured without PUCCH and PUSCH + * + * This format will be implemented in the future FIXME!!! + * + */ + // 40 SRS_REQUEST + // 41 TPC_CMD + uint8_t tpc_cmd_bit_2_3 = 0; + uint8_t dci_field_size_table [NBR_NR_DCI_FIELDS][NBR_NR_FORMATS] = { // This table contains the number of bits for each field (row) contained in each dci format (column). + // The values of the variables indicate field sizes in number of bits + //Format0_0 Format0_1 Format1_0 Format1_1 Formats2_0/1/2/3 + { + 1, 1, (((crc_scrambled == _p_rnti) || (crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti)) ? 0:1), + 1, 0,0,0,0 + }, // 0 IDENTIFIER_DCI_FORMATS: + { + 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3), + 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3), + 0,0,0,0 + }, // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213] + {0, (sul_ind == 0)?0:1, 0, 0, 0,0,0,0}, // 2 SUL_IND_0_1: + {0, 0, 0, 0, 1,0,0,0}, // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213] + {0, 0, 0, 0, 0,1,0,0}, // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits + {0, 0, 0, 0, 0,0,0,0}, // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3 + {0, 0, 0, 0, 0,0,1,0}, // 6 CLOSE_LOOP_IND + { + 0, (uint8_t)ceil(log2(n_UL_BWP_RRC)), + 0, (uint8_t)ceil(log2(n_DL_BWP_RRC)), + 0,0,0,0 + }, // 7 BANDWIDTH_PART_IND: + { + 0, 0, ((crc_scrambled == _p_rnti) ? 2:0), + 0, 0,0,0,0 + }, // 8 SHORT_MESSAGE_IND 2 bits if crc scrambled with P-RNTI + { + 0, 0, ((crc_scrambled == _p_rnti) ? 8:0), + 0, 0,0,0,0 + }, // 9 SHORT_MESSAGES 8 bit8 if crc scrambled with P-RNTI + { + (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping, + n_bits_freq_dom_res_assign_ul, + 0, 0, 0,0,0,0 + }, // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered + // (NOTE 1) If DCI format 0_0 is monitored in common search space + // and if the number of information bits in the DCI format 0_0 prior to padding + // is larger than the payload size of the DCI format 1_0 monitored in common search space + // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 + // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0 + { + 0, 0, (uint8_t)ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2)), + n_bits_freq_dom_res_assign_dl, + 0,0,0,0 + }, // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + { + 4, (uint8_t)log2(pusch_alloc_list), + 4, (uint8_t)log2(pdsch_alloc_list), + 0,0,0,0 + }, // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + // where I the number of entries in the higher layer parameter pusch-AllocationList + { + 0, 0, 1, (((dl_res_alloc_type_0==1) &&(dl_res_alloc_type_1==0))?0:1), + 0,0,0,0 + }, // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + {0, 0, 0, prb_BundlingType_size, 0,0,0,0}, // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] + {0, 0, 0, rateMatching_bits, 0,0,0,0}, // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set + {0, 0, 0, n_zp_bits, 0,0,0,0}, // 16 ZP_CSI_RS_TRIGGER: + { + 1, (((ul_res_alloc_type_0==1) &&(ul_res_alloc_type_1==0))||(freqHopping == 0))?0:1, + 0, 0, 0,0,0,0 + }, // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 + {0, 0, 0, 5, 0,0,0,0}, // 18 TB1_MCS: + {0, 0, 0, 1, 0,0,0,0}, // 19 TB1_NDI: + {0, 0, 0, 2, 0,0,0,0}, // 20 TB1_RV: + {0, 0, 0, 5, 0,0,0,0}, // 21 TB2_MCS: + {0, 0, 0, 1, 0,0,0,0}, // 22 TB2_NDI: + {0, 0, 0, 2, 0,0,0,0}, // 23 TB2_RV: + {5, 5, 5, 0, 0,0,0,0}, // 24 MCS: + {1, 1, (crc_scrambled == _c_rnti)?1:0,0, 0,0,0,0}, // 25 NDI: + { + 2, 2, (((crc_scrambled == _c_rnti) || (crc_scrambled == _si_rnti)) ? 2:0), + 0, 0,0,0,0 + }, // 26 RV: + {4, 4, (crc_scrambled == _c_rnti)?4:0,4, 0,0,0,0}, // 27 HARQ_PROCESS_NUMBER: + {0, 0, (crc_scrambled == _c_rnti)?2:0,n_dai, 0,0,0,0}, // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI + // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI + // 0 otherwise + {0, codebook_HARQ_ACK, 0, 0, 0,0,0,0}, // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK // 2 bits for dynamic HARQ-ACK codebook with single HARQ-ACK codebook + { + 0, (((codebook_HARQ_ACK == 2) &&(n_HARQ_ACK_sub_codebooks==2))?2:0), + 0, 0, 0,0,0,0 + }, // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks // 0 bits otherwise + { + 0, 0, (((crc_scrambled == _p_rnti) || (crc_scrambled == _ra_rnti)) ? 2:0), + 0, 0,0,0,0 + }, // 31 TB_SCALING + {2, 2, 0, 0, 0,0,0,0}, // 32 TPC_PUSCH: + {0, 0, (crc_scrambled == _c_rnti)?2:0,2, 0,0,0,0}, // 33 TPC_PUCCH: + {0, 0, (crc_scrambled == _c_rnti)?3:0,3, 0,0,0,0}, // 34 PUCCH_RESOURCE_IND: + {0, 0, (crc_scrambled == _c_rnti)?3:0,pdsch_harq_t_ind, 0,0,0,0}, // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: + {0, (uint8_t)log2(n_SRS), 0, 0, 0,0,0,0}, // 36 SRS_RESOURCE_IND: + {0, precond_nbr_layers_bits, 0, 0, 0,0,0,0}, // 37 PRECOD_NBR_LAYERS: + {0, antenna_ports_bits_ul, 0, antenna_ports_bits_dl, 0,0,0,0}, // 38 ANTENNA_PORTS: + {0, 0, 0, tci_bits, 0,0,0,0}, // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits + {0, (sul_ind == 0)?2:3, 0, (sul_ind == 0)?2:3, 0,0,0,2}, // 40 SRS_REQUEST: + { + 0, 0, 0, 0, 0,0,tpc_cmd_bit_2_2, + tpc_cmd_bit_2_3 + }, + // 41 TPC_CMD: + {0, reportTriggerSize, 0, 0, 0,0,0,0}, // 42 CSI_REQUEST: + { + 0, maxCodeBlockGroupsPerTransportBlock, + 0, maxCodeBlockGroupsPerTransportBlock_dl, + 0,0,0,0 + }, // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH + {0, 0, 0, cbgfi_bit, 0,0,0,0}, // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator + {0, ptrs_dmrs_bits, 0, 0, 0,0,0,0}, // 45 PTRS_DMRS: + {0, betaOffsets, 0, 0, 0,0,0,0}, // 46 BETA_OFFSET_IND: + {0, dmrs_seq_ini_bits_ul, 0, dmrs_seq_ini_bits_dl, 0,0,0,0}, // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding + // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise + {0, 1, 0, 0, 0,0,0,0}, // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH + {0, 0, 0, 0, 0,0,0,0}, // 49 PADDING_NR_DCI: + // (NOTE 2) If DCI format 0_0 is monitored in common search space + // and if the number of information bits in the DCI format 0_0 prior to padding + // is less than the payload size of the DCI format 1_0 monitored in common search space + // zeros shall be appended to the DCI format 0_0 + // until the payload size equals that of the DCI format 1_0 + {(sul_ind == 0)?0:1, 0, 0, 0, 0,0,0,0}, // 50 SUL_IND_0_0: + {0, 0, 0, 0, 0,0,0,0}, // 51 RA_PREAMBLE_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) + {0, 0, 0, 0, 0,0,0,0}, // 52 SUL_IND_1_0 (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) + {0, 0, 0, 0, 0,0,0,0}, // 53 SS_PBCH_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) + {0, 0, 0, 0, 0,0,0,0}, // 54 PRACH_MASK_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!) + { + 0, 0, ((crc_scrambled == _p_rnti)?6:(((crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti))?16:0)), + 0, 0,0,0,0 + } // 55 RESERVED_NR_DCI + }; + // NOTE 1: adjustments in freq_dom_resource_assignment_UL to be done if necessary + // NOTE 2: adjustments in padding to be done if necessary + uint8_t dci_size [8] = {0,0,0,0,0,0,0,0}; // will contain size for each format + + for (int i=0 ; i position in table is 2) + dci_fields_sizes[j][i] = dci_field_size_table[j][i]; // dci_fields_sizes[j] contains the sizes of each field (j) for a determined format i + //} + } + + LOG_DDD("(nr_dci_format_size) dci_size[%d]=%d for n_RB_ULBWP=%d\n", + i,dci_size[i],n_RB_ULBWP); + } + + LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n"); + +#ifdef NR_PDCCH_DCI_DEBUG + for (int j=0; j dci_size[2])) { + dci_field_size_table[SUL_IND_0_0][0] = 0; + dci_size[0]=dci_size[0]-1; + } + + // if ((format == format0_0) || (format == format1_0)) { + // According to Section 7.3.1.1.1 in TS 38.212 + // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding + // is less than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell, + // zeros shall be appended to the DCI format 0_0 until the payload size equals that of the DCI format 1_0. + if (dci_size[0] < dci_size[2]) { // '0' corresponding to index for format0_0 and '2' corresponding to index of format1_0 + //if (format == format0_0) { + dci_fields_sizes[PADDING_NR_DCI][0] = dci_size[2] - dci_size[0]; + dci_size[0] = dci_size[2]; + LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]); + //} + } + + // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding + // is larger than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell, + // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 is reduced + // such that the size of DCI format 0_0 equals to the size of the DCI format 1_0.. + if (dci_size[0] > dci_size[2]) { + //if (format == format0_0) { + dci_fields_sizes[FREQ_DOM_RESOURCE_ASSIGNMENT_UL][0] -= (dci_size[0] - dci_size[2]); + dci_size[0] = dci_size[2]; + LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]); + //} + } + + /* + * TS 38.212 subclause 7.3.1.1.2 + * For a UE configured with SUL in a cell: + * if PUSCH is configured to be transmitted on both the SUL and the non-SUL of the cell and + * if the number of information bits in format 0_1 for the SUL + * is not equal to the number of information bits in format 0_1 for the non-SUL, + * zeros shall be appended to smaller format 0_1 until the payload size equals that of the larger format 0_1 + * + * Not implemented. FIXME!!! + * + */ + // } + LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n"); + +#ifdef NR_PDCCH_DCI_DEBUG + for (int j=0; j floor (n_RB_DLBWP/2) - // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_DLBWP/2) - l_RB = floor(riv/n_RB_DLBWP) + 1; - start_RB = riv%n_RB_DLBWP; - // if (l_RB - 1) > floor (n_RB_DLBWP/2) we need to recalculate them using the following lines - tmp_RIV = n_RB_DLBWP * (l_RB - 1) + start_RB; - if ((tmp_RIV != riv) || ((start_RB+l_RB)>n_RB_DLBWP)) { // then (l_RB - 1) > floor (n_RB_DLBWP/2) and we need to recalculate l_RB and start_RB - l_RB = n_RB_DLBWP - l_RB + 2; - start_RB = n_RB_DLBWP - start_RB - 1; - } - dlsch_config_pdu->number_rbs = l_RB; - dlsch_config_pdu->start_rb = start_RB; + + /* + * TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0 + */ + /* + * TS 38.214 subclause 5.1.2.2.2 Downlink resource allocation type 1 + */ + dlsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_DLBWP); + dlsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_DLBWP); + } if(ulsch_config_pdu != NULL){ -/* - * TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink) - */ - /* - * TS 38.214 subclause 6.1.2.2.1 Uplink resource allocation type 0 - */ - /* - * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1 - */ - // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV): - // RIV = n_RB_ULBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_ULBWP/2) - // RIV = n_RB_ULBWP * (n_RB_ULBWP - l_RB + 1) + (n_RB_ULBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_ULBWP/2) - // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_ULBWP/2) - l_RB = floor(riv/n_RB_ULBWP) + 1; - start_RB = riv%n_RB_ULBWP; - // if (l_RB - 1) > floor (n_RB_ULBWP/2) we need to recalculate them using the following lines - tmp_RIV = n_RB_ULBWP * (l_RB - 1) + start_RB; - if (tmp_RIV != riv) { // then (l_RB - 1) > floor (n_RB_ULBWP/2) and we need to recalculate l_RB and start_RB - l_RB = n_RB_ULBWP - l_RB + 2; - start_RB = n_RB_ULBWP - start_RB - 1; - } - ulsch_config_pdu->number_rbs = l_RB; - ulsch_config_pdu->start_rb = start_RB; + /* + * TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink) + */ + /* + * TS 38.214 subclause 6.1.2.2.1 Uplink resource allocation type 0 + */ + /* + * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1 + */ + + ulsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_ULBWP); + ulsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_ULBWP); } return 0; } -int8_t nr_ue_process_dci_time_dom_resource_assignment( - fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu, - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu, - uint8_t time_domain_ind, - long dmrs_typeA_pos //0=pos2,1=pos3 -){ +int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, + fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu, + fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu, + uint8_t time_domain_ind + ){ + int dmrs_typeA_pos = mac->scc->dmrs_TypeA_Position; uint8_t k_offset=0; uint8_t sliv_S=0; uint8_t sliv_L=0; uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?12:11}, // row index 1 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5 - {0,(dmrs_typeA_pos == 0)?9:10,(dmrs_typeA_pos == 0)?4:4}, // row index 6 - {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7 - {0,5,7}, // row index 8 - {0,5,2}, // row index 9 - {0,9,2}, // row index 10 - {0,12,2}, // row index 11 - {0,1,13}, // row index 12 - {0,1,6}, // row index 13 - {0,2,4}, // row index 14 - {0,4,7}, // row index 15 - {0,8,4} // row index 16 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?12:11}, // row index 1 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5 + {0,(dmrs_typeA_pos == 0)?9:10,(dmrs_typeA_pos == 0)?4:4}, // row index 6 + {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7 + {0,5,7}, // row index 8 + {0,5,2}, // row index 9 + {0,9,2}, // row index 10 + {0,12,2}, // row index 11 + {0,1,13}, // row index 12 + {0,1,6}, // row index 13 + {0,2,4}, // row index 14 + {0,4,7}, // row index 15 + {0,8,4} // row index 16 }; /*uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?6:5}, // row index 1 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4 - {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5 - {0,(dmrs_typeA_pos == 0)?6:8, (dmrs_typeA_pos == 0)?4:2}, // row index 6 - {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7 - {0,5,6}, // row index 8 - {0,5,2}, // row index 9 - {0,9,2}, // row index 10 - {0,10,2}, // row index 11 - {0,1,11}, // row index 12 - {0,1,6}, // row index 13 - {0,2,4}, // row index 14 - {0,4,6}, // row index 15 - {0,8,4} // row index 16 - };*/ + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?6:5}, // row index 1 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4 + {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5 + {0,(dmrs_typeA_pos == 0)?6:8, (dmrs_typeA_pos == 0)?4:2}, // row index 6 + {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7 + {0,5,6}, // row index 8 + {0,5,2}, // row index 9 + {0,9,2}, // row index 10 + {0,10,2}, // row index 11 + {0,1,11}, // row index 12 + {0,1,6}, // row index 13 + {0,2,4}, // row index 14 + {0,4,6}, // row index 15 + {0,8,4} // row index 16 + };*/ /*uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1 - {0,2,2}, // row index 1 - {0,4,2}, // row index 2 - {0,6,2}, // row index 3 - {0,8,2}, // row index 4 - {0,10,2}, // row index 5 - {1,2,2}, // row index 6 - {1,4,2}, // row index 7 - {0,2,4}, // row index 8 - {0,4,4}, // row index 9 - {0,6,4}, // row index 10 - {0,8,4}, // row index 11 - {0,10,4}, // row index 12 - {0,2,7}, // row index 13 - {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14 - {1,2,4}, // row index 15 - {0,0,0} // row index 16 - };*/ + {0,2,2}, // row index 1 + {0,4,2}, // row index 2 + {0,6,2}, // row index 3 + {0,8,2}, // row index 4 + {0,10,2}, // row index 5 + {1,2,2}, // row index 6 + {1,4,2}, // row index 7 + {0,2,4}, // row index 8 + {0,4,4}, // row index 9 + {0,6,4}, // row index 10 + {0,8,4}, // row index 11 + {0,10,4}, // row index 12 + {0,2,7}, // row index 13 + {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14 + {1,2,4}, // row index 15 + {0,0,0} // row index 16 + };*/ /*uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1 - {0,2,2}, // row index 1 - {0,4,2}, // row index 2 - {0,6,2}, // row index 3 - {0,8,2}, // row index 4 - {0,10,2}, // row index 5 - {0,0,0}, // row index 6 - {0,0,0}, // row index 7 - {0,2,4}, // row index 8 - {0,4,4}, // row index 9 - {0,6,4}, // row index 10 - {0,8,4}, // row index 11 - {0,10,4}, // row index 12 - {0,2,7}, // row index 13 - {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14 - {0,0,6}, // row index 15 - {0,2,6} // row index 16 - };*/ + {0,2,2}, // row index 1 + {0,4,2}, // row index 2 + {0,6,2}, // row index 3 + {0,8,2}, // row index 4 + {0,10,2}, // row index 5 + {0,0,0}, // row index 6 + {0,0,0}, // row index 7 + {0,2,4}, // row index 8 + {0,4,4}, // row index 9 + {0,6,4}, // row index 10 + {0,8,4}, // row index 11 + {0,10,4}, // row index 12 + {0,2,7}, // row index 13 + {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14 + {0,0,6}, // row index 15 + {0,2,6} // row index 16 + };*/ uint8_t mu_pusch = 1; // definition table j Table 6.1.2.1.1-4 uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1; uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1 - {j, 0,14}, // row index 1 - {j, 0,12}, // row index 2 - {j, 0,10}, // row index 3 - {j, 2,10}, // row index 4 - {j, 4,10}, // row index 5 - {j, 4,8}, // row index 6 - {j, 4,6}, // row index 7 - {j+1,0,14}, // row index 8 - {j+1,0,12}, // row index 9 - {j+1,0,10}, // row index 10 - {j+2,0,14}, // row index 11 - {j+2,0,12}, // row index 12 - {j+2,0,10}, // row index 13 - {j, 8,6}, // row index 14 - {j+3,0,14}, // row index 15 - {j+3,0,10} // row index 16 + {j, 0,14}, // row index 1 + {j, 0,12}, // row index 2 + {j, 0,10}, // row index 3 + {j, 2,10}, // row index 4 + {j, 4,10}, // row index 5 + {j, 4,8}, // row index 6 + {j, 4,6}, // row index 7 + {j+1,0,14}, // row index 8 + {j+1,0,12}, // row index 9 + {j+1,0,10}, // row index 10 + {j+2,0,14}, // row index 11 + {j+2,0,12}, // row index 12 + {j+2,0,10}, // row index 13 + {j, 8,6}, // row index 14 + {j+3,0,14}, // row index 15 + {j+3,0,10} // row index 16 }; /*uint8_t table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1 - {j, 0,8}, // row index 1 - {j, 0,12}, // row index 2 - {j, 0,10}, // row index 3 - {j, 2,10}, // row index 4 - {j, 4,4}, // row index 5 - {j, 4,8}, // row index 6 - {j, 4,6}, // row index 7 - {j+1,0,8}, // row index 8 - {j+1,0,12}, // row index 9 - {j+1,0,10}, // row index 10 - {j+2,0,6}, // row index 11 - {j+2,0,12}, // row index 12 - {j+2,0,10}, // row index 13 - {j, 8,4}, // row index 14 - {j+3,0,8}, // row index 15 - {j+3,0,10} // row index 16 - };*/ + {j, 0,8}, // row index 1 + {j, 0,12}, // row index 2 + {j, 0,10}, // row index 3 + {j, 2,10}, // row index 4 + {j, 4,4}, // row index 5 + {j, 4,8}, // row index 6 + {j, 4,6}, // row index 7 + {j+1,0,8}, // row index 8 + {j+1,0,12}, // row index 9 + {j+1,0,10}, // row index 10 + {j+2,0,6}, // row index 11 + {j+2,0,12}, // row index 12 + {j+2,0,10}, // row index 13 + {j, 8,4}, // row index 14 + {j+3,0,8}, // row index 15 + {j+3,0,10} // row index 16 + };*/ -/* - * TS 38.214 subclause 5.1.2.1 Resource allocation in time domain (downlink) - */ + /* + * TS 38.214 subclause 5.1.2.1 Resource allocation in time domain (downlink) + */ if(dlsch_config_pdu != NULL){ + NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = NULL; + if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList) + pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList->choice.setup; + else if (mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList) + pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; + if (pdsch_TimeDomainAllocationList) { + + AssertFatal(pdsch_TimeDomainAllocationList->list.count > time_domain_ind, + "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n", + time_domain_ind,pdsch_TimeDomainAllocationList->list.count); + int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength; + int S,L; + SLIV2SL(startSymbolAndLength,&S,&L); + dlsch_config_pdu->start_symbol=S; + dlsch_config_pdu->number_symbols=L; + dlsch_config_pdu->frame_offset = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0!=NULL ? + *pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0 : + 0; + } + else {// Default configuration from tables k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0]; sliv_S = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][1]; sliv_L = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][2]; @@ -1301,10 +1869,30 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment( dlsch_config_pdu->frame_offset = k_offset; dlsch_config_pdu->number_symbols = sliv_L; dlsch_config_pdu->start_symbol = sliv_S; + } } /* - * TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink) - */ + * TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink) + */ if(ulsch_config_pdu != NULL){ + NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = NULL; + if (mac->ULbwp[0]->bwp_Dedicated->pusch_Config) + pusch_TimeDomainAllocationList = mac->ULbwp[0]->bwp_Dedicated->pusch_Config->choice.setup->pusch_TimeDomainAllocationList->choice.setup; + + if (pusch_TimeDomainAllocationList) { + AssertFatal(pusch_TimeDomainAllocationList->list.count > time_domain_ind, + "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n", + time_domain_ind,pusch_TimeDomainAllocationList->list.count); + int startSymbolAndLength = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength; + int S,L; + SLIV2SL(startSymbolAndLength,&S,&L); + ulsch_config_pdu->start_symbol=S; + ulsch_config_pdu->number_symbols=L; + ulsch_config_pdu->frame_offset = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2!=NULL ? + *pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2 : + mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz60 ? 1 : + mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz120 ? 2 : 3; + } + else { k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0]; sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][1]; sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][2]; @@ -1314,766 +1902,786 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment( ulsch_config_pdu->frame_offset = k_offset; ulsch_config_pdu->number_symbols = sliv_L; ulsch_config_pdu->start_symbol = sliv_S; + } } return 0; } ////////////// +int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci) { -int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + nr_dci_pdu_rel15_t dci_pdu_rel15; - NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; - fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; + LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n", + dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits); + + nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15); + nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format); +} + +int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; + fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; - //const uint16_t n_RB_DLBWP = dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP; //make sure this has been set - const uint16_t n_RB_DLBWP = mac->initial_bwp_dl.N_RB; - const uint16_t n_RB_ULBWP = mac->initial_bwp_ul.N_RB; + //const uint16_t n_RB_DLBWP = dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP; //make sure this has been set + AssertFatal(mac->DLbwp[0]!=NULL,"DLbwp[0] should not be zero here!\n"); + AssertFatal(mac->ULbwp[0]!=NULL,"DLbwp[0] should not be zero here!\n"); - LOG_I(MAC,"nr_ue_process_dci at MAC layer with dci_format=%d (DL BWP %d, UL BWP %d)\n",dci_format,n_RB_DLBWP,n_RB_ULBWP); + const uint16_t n_RB_DLBWP = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + const uint16_t n_RB_ULBWP = NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); - switch(dci_format){ - case format0_0: -/* - * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 32 TPC_PUSCH: - * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space - * 50 SUL_IND_0_0: - */ - ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; - fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; - /* IDENTIFIER_DCI_FORMATS */ - /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); - /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position); - /* FREQ_HOPPING_FLAG */ - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; - /* MCS */ - ulsch_config_pdu_0_0->mcs = dci->mcs; - /* NDI */ - ulsch_config_pdu_0_0->ndi = dci->ndi; - /* RV */ - ulsch_config_pdu_0_0->rv = dci->rv; - /* HARQ_PROCESS_NUMBER */ - ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number; - /* TPC_PUSCH */ - // according to TS 38.213 Table Table 7.1.1-1 - if (dci->tpc_pusch == 0) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4; - } - if (dci->tpc_pusch == 1) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1; - } - if (dci->tpc_pusch == 2) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1; - } - if (dci->tpc_pusch == 3) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4; - } - /* SUL_IND_0_0 */ // To be implemented, FIXME!!! + LOG_D(MAC,"nr_ue_process_dci at MAC layer with dci_format=%d (DL BWP %d, UL BWP %d)\n",dci_format,n_RB_DLBWP,n_RB_ULBWP); - ul_config->number_pdus = ul_config->number_pdus + 1; - break; + NR_PDSCH_Config_t *pdsch_config=mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup; - case format0_1: -/* - * with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 1 CARRIER_IND - * 2 SUL_IND_0_1 - * 7 BANDWIDTH_PART_IND - * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 29 FIRST_DAI - * 30 SECOND_DAI - * 32 TPC_PUSCH: - * 36 SRS_RESOURCE_IND: - * 37 PRECOD_NBR_LAYERS: - * 38 ANTENNA_PORTS: - * 40 SRS_REQUEST: - * 42 CSI_REQUEST: - * 43 CBGTI - * 45 PTRS_DMRS - * 46 BETA_OFFSET_IND - * 47 DMRS_SEQ_INI - * 48 UL_SCH_IND - * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space - */ - ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; - fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; - /* IDENTIFIER_DCI_FORMATS */ - /* CARRIER_IND */ - /* SUL_IND_0_1 */ - /* BANDWIDTH_PART_IND */ - ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind; - /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); - /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position); - /* FREQ_HOPPING_FLAG */ - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; - /* MCS */ - ulsch_config_pdu_0_1->mcs = dci->mcs; - /* NDI */ - ulsch_config_pdu_0_1->ndi = dci->ndi; - /* RV */ - ulsch_config_pdu_0_1->rv = dci->rv; - /* HARQ_PROCESS_NUMBER */ - ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number; - /* FIRST_DAI */ //To be implemented, FIXME!!! - /* SECOND_DAI */ //To be implemented, FIXME!!! - /* TPC_PUSCH */ - // according to TS 38.213 Table Table 7.1.1-1 - if (dci->tpc_pusch == 0) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4; - } - if (dci->tpc_pusch == 1) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1; - } - if (dci->tpc_pusch == 2) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1; - } - if (dci->tpc_pusch == 3) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4; - } - /* SRS_RESOURCE_IND */ - //FIXME!! - /* PRECOD_NBR_LAYERS */ - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_nonCodebook)); - // 0 bits if the higher layer parameter txConfig = nonCodeBook - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_codebook)){ - uint8_t n_antenna_port = 0; //FIXME!!! - if (n_antenna_port == 1); // 1 antenna port and the higher layer parameter txConfig = codebook 0 bits - if (n_antenna_port == 4){ // 4 antenna port and the higher layer parameter txConfig = codebook - // Table 7.3.1.1.2-2: transformPrecoder=disabled and maxRank = 2 or 3 or 4 - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) - && ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2) || - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) || - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){ - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1]; - } - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3]; - } - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5]; - } - } - // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1 - if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) - || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) - && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7]; - } - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9]; - } - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11]; - } - } - } - if (n_antenna_port == 4){ // 2 antenna port and the higher layer parameter txConfig = codebook - // Table 7.3.1.1.2-4: transformPrecoder=disabled and maxRank = 2 - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) - && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){ - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13]; - } - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15]; - } - } - // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1 - if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) - || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) - && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17]; - } - if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19]; - } - } - } - } - /* ANTENNA_PORTS */ - uint8_t rank=0; // We need to initialize rank FIXME!!! - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6 - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports; - } - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7 - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports); - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; - } - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11 - if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports); - } - if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0; - ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1; - } - if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = 0; - ulsch_config_pdu_0_1->dmrs_ports[1] = 1; - ulsch_config_pdu_0_1->dmrs_ports[2] = 2; - } - if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = 0; - ulsch_config_pdu_0_1->dmrs_ports[1] = 1; - ulsch_config_pdu_0_1->dmrs_ports[2] = 2; - ulsch_config_pdu_0_1->dmrs_ports[3] = 3; - } - } - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15 - if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1; - } - if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; - } - if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; - } - if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; - } - } - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19 - if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; - } - if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2]; - } - if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3]; - } - if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = 0; - ulsch_config_pdu_0_1->dmrs_ports[1] = 1; - ulsch_config_pdu_0_1->dmrs_ports[2] = 2; - ulsch_config_pdu_0_1->dmrs_ports[3] = 3; - } - } - if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23 - if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2]; - } - if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3]; - } - if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4]; - } - if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5]; - } - } - /* SRS_REQUEST */ - // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 - /* CSI_REQUEST */ - ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request; - /* CBGTI */ - ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti; - /* PTRS_DMRS */ - if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) || - ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && - (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){ - } else { - ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs; - } - /* BETA_OFFSET_IND */ - // Table 9.3-3 in [5, TS 38.213] - ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind; - /* DMRS_SEQ_INI */ - // FIXME!! - /* UL_SCH_IND */ - // A value of "1" indicates UL-SCH shall be transmitted on the PUSCH and - // a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH + switch(dci_format){ + case NR_UL_DCI_FORMAT_0_0: + /* + * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI + * 0 IDENTIFIER_DCI_FORMATS: + * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 + * 24 MCS: + * 25 NDI: + * 26 RV: + * 27 HARQ_PROCESS_NUMBER: + * 32 TPC_PUSCH: + * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space + * 50 SUL_IND_0_0: + */ + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; + fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; + /* IDENTIFIER_DCI_FORMATS */ + /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ + nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + /* TIME_DOM_RESOURCE_ASSIGNMENT */ + nr_ue_process_dci_time_dom_resource_assignment(mac, + ulsch_config_pdu_0_0,NULL, + dci->time_dom_resource_assignment); - ul_config->number_pdus = ul_config->number_pdus + 1; - break; - - case format1_0: -/* - * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - * 33 TPC_PUCCH: - * 34 PUCCH_RESOURCE_IND: - * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: - * 55 RESERVED_NR_DCI - * with CRC scrambled by P-RNTI - * 8 SHORT_MESSAGE_IND - * 9 SHORT_MESSAGES - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 31 TB_SCALING - * 55 RESERVED_NR_DCI - * with CRC scrambled by SI-RNTI - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 26 RV: - * 55 RESERVED_NR_DCI - * with CRC scrambled by RA-RNTI - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 31 TB_SCALING - * 55 RESERVED_NR_DCI - * with CRC scrambled by TC-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 24 MCS: - * 25 NDI: - * 26 RV: - * 27 HARQ_PROCESS_NUMBER: - * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - * 33 TPC_PUCCH: - */ - dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti; - //fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_pdu_1_0 = dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_0 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; - /* IDENTIFIER_DCI_FORMATS */ - /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ - nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); - /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position); - /* VRB_TO_PRB_MAPPING */ - dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; - /* MCS */ - dlsch_config_pdu_1_0->mcs = dci->mcs; - /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->ndi = dci->ndi; - /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->rv = dci->rv; - /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number; - /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->dai = dci ->dai; - /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */ - // according to TS 38.214 Table 5.1.3.2-3 - if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1; - if (dci->tb_scaling == 1) dlsch_config_pdu_1_0->scaling_factor_S = 0.5; - if (dci->tb_scaling == 2) dlsch_config_pdu_1_0->scaling_factor_S = 0.25; - if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table - /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - // according to TS 38.213 Table 7.2.1-1 - if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1; - if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0; - if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1; - if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3; - /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ - //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! - dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind; - /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ - dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind; - - LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n", - dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti, - dl_config->number_pdus); - LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n", - dci->freq_dom_resource_assignment_DL, - dlsch_config_pdu_1_0->number_rbs, - dlsch_config_pdu_1_0->start_rb); - LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n", - dci->time_dom_resource_assignment, - dlsch_config_pdu_1_0->number_symbols, - dlsch_config_pdu_1_0->start_symbol); - LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n", - dlsch_config_pdu_1_0->vrb_to_prb_mapping, - dlsch_config_pdu_1_0->mcs, - dlsch_config_pdu_1_0->ndi, - dlsch_config_pdu_1_0->rv, - dlsch_config_pdu_1_0->harq_process_nbr, - dlsch_config_pdu_1_0->dai, - dlsch_config_pdu_1_0->scaling_factor_S, - dlsch_config_pdu_1_0->accumulated_delta_PUCCH, - dlsch_config_pdu_1_0->pucch_resource_id, - dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind); - - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP; - - LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type); - - dl_config->number_pdus = dl_config->number_pdus + 1; - break; - - case format1_1: -/* - * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI - * 0 IDENTIFIER_DCI_FORMATS: - * 1 CARRIER_IND: - * 7 BANDWIDTH_PART_IND: - * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: - * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, - * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 - * 14 PRB_BUNDLING_SIZE_IND: - * 15 RATE_MATCHING_IND: - * 16 ZP_CSI_RS_TRIGGER: - * 18 TB1_MCS: - * 19 TB1_NDI: - * 20 TB1_RV: - * 21 TB2_MCS: - * 22 TB2_NDI: - * 23 TB2_RV: - * 27 HARQ_PROCESS_NUMBER: - * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI - * 33 TPC_PUCCH: - * 34 PUCCH_RESOURCE_IND: - * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: - * 38 ANTENNA_PORTS: - * 39 TCI: - * 40 SRS_REQUEST: - * 43 CBGTI: - * 44 CBGFI: - * 47 DMRS_SEQ_INI: - */ - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti; - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_1 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; - /* IDENTIFIER_DCI_FORMATS */ - /* CARRIER_IND */ - /* BANDWIDTH_PART_IND */ - dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind; - /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ - nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); - /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position); - /* VRB_TO_PRB_MAPPING */ - if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0) - dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; - /* PRB_BUNDLING_SIZE_IND */ - dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind; - /* RATE_MATCHING_IND */ - dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind; - /* ZP_CSI_RS_TRIGGER */ - dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger; - /* MCS (for transport block 1)*/ - dlsch_config_pdu_1_1->mcs = dci->tb1_mcs; - /* NDI (for transport block 1)*/ - dlsch_config_pdu_1_1->ndi = dci->tb1_ndi; - /* RV (for transport block 1)*/ - dlsch_config_pdu_1_1->rv = dci->tb1_rv; - /* MCS (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs; - /* NDI (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi; - /* RV (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv; - /* HARQ_PROCESS_NUMBER */ - dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number; - /* DAI */ - dlsch_config_pdu_1_1->dai = dci ->dai; - /* TPC_PUCCH */ - // according to TS 38.213 Table 7.2.1-1 - if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1; - if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0; - if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; - if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; - /* PUCCH_RESOURCE_IND */ - if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! - /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */ - // according to TS 38.213 Table 9.2.3-1 - dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind]; - /* ANTENNA_PORTS */ - uint8_t n_codewords = 1; // FIXME!!! - if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && - (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ - // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1 - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4]; - } - if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && - (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ - // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2 - if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5]; - } - if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6]; - dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7]; - dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9]; - } - } - if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && - (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ - // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1 - if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4]; - } - if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6]; - } - } - if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && - (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ - // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2 - if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5]; - } - if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6]; - dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7]; - dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9]; - } - } - /* TCI */ - if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){ - // 0 bit if higher layer parameter tci-PresentInDCI is not enabled - // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214] - dlsch_config_pdu_1_1->tci_state = dci->tci; - } - /* SRS_REQUEST */ - // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 - /* CBGTI */ - dlsch_config_pdu_1_1->cbgti = dci->cbgti; - /* CBGFI */ - dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi; - /* DMRS_SEQ_INI */ - //FIXME!!! - - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP; - - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type); - - dl_config->number_pdus = dl_config->number_pdus + 1; - - break; - - case format2_0: - break; - - case format2_1: - break; - - case format2_2: - break; - - case format2_3: - break; - - default: - break; + /* FREQ_HOPPING_FLAG */ + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) + ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; + /* MCS */ + ulsch_config_pdu_0_0->mcs = dci->mcs; + /* NDI */ + ulsch_config_pdu_0_0->ndi = dci->ndi; + /* RV */ + ulsch_config_pdu_0_0->rv = dci->rv; + /* HARQ_PROCESS_NUMBER */ + ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number; + /* TPC_PUSCH */ + // according to TS 38.213 Table Table 7.1.1-1 + if (dci->tpc_pusch == 0) { + ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1; + ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4; } - - - if(rnti == SI_RNTI){ - - }else if(rnti == mac->ra_rnti){ - - }else if(rnti == P_RNTI){ - - }else{ // c-rnti - - /// check if this is pdcch order - //dci->random_access_preamble_index; - //dci->ss_pbch_index; - //dci->prach_mask_index; - - /// else normal DL-SCH grant + if (dci->tpc_pusch == 1) { + ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0; + ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1; } - return 0; + if (dci->tpc_pusch == 2) { + ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1; + ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1; + } + if (dci->tpc_pusch == 3) { + ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3; + ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4; + } + /* SUL_IND_0_0 */ // To be implemented, FIXME!!! + + ul_config->number_pdus = ul_config->number_pdus + 1; + break; + + case NR_UL_DCI_FORMAT_0_1: + /* + * with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI + * 0 IDENTIFIER_DCI_FORMATS: + * 1 CARRIER_IND + * 2 SUL_IND_0_1 + * 7 BANDWIDTH_PART_IND + * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 + * 24 MCS: + * 25 NDI: + * 26 RV: + * 27 HARQ_PROCESS_NUMBER: + * 29 FIRST_DAI + * 30 SECOND_DAI + * 32 TPC_PUSCH: + * 36 SRS_RESOURCE_IND: + * 37 PRECOD_NBR_LAYERS: + * 38 ANTENNA_PORTS: + * 40 SRS_REQUEST: + * 42 CSI_REQUEST: + * 43 CBGTI + * 45 PTRS_DMRS + * 46 BETA_OFFSET_IND + * 47 DMRS_SEQ_INI + * 48 UL_SCH_IND + * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space + */ + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; + fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; + /* IDENTIFIER_DCI_FORMATS */ + /* CARRIER_IND */ + /* SUL_IND_0_1 */ + /* BANDWIDTH_PART_IND */ + ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind; + /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ + nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + /* TIME_DOM_RESOURCE_ASSIGNMENT */ + nr_ue_process_dci_time_dom_resource_assignment(mac,ulsch_config_pdu_0_1,NULL, + dci->time_dom_resource_assignment); + /* FREQ_HOPPING_FLAG */ + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) + ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; + /* MCS */ + ulsch_config_pdu_0_1->mcs = dci->mcs; + /* NDI */ + ulsch_config_pdu_0_1->ndi = dci->ndi; + /* RV */ + ulsch_config_pdu_0_1->rv = dci->rv; + /* HARQ_PROCESS_NUMBER */ + ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number; + /* FIRST_DAI */ //To be implemented, FIXME!!! + /* SECOND_DAI */ //To be implemented, FIXME!!! + /* TPC_PUSCH */ + // according to TS 38.213 Table Table 7.1.1-1 + if (dci->tpc_pusch == 0) { + ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1; + ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4; + } + if (dci->tpc_pusch == 1) { + ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0; + ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1; + } + if (dci->tpc_pusch == 2) { + ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1; + ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1; + } + if (dci->tpc_pusch == 3) { + ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3; + ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4; + } + /* SRS_RESOURCE_IND */ + //FIXME!! + /* PRECOD_NBR_LAYERS */ + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_nonCodebook)); + // 0 bits if the higher layer parameter txConfig = nonCodeBook + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_codebook)){ + uint8_t n_antenna_port = 0; //FIXME!!! + if (n_antenna_port == 1); // 1 antenna port and the higher layer parameter txConfig = codebook 0 bits + if (n_antenna_port == 4){ // 4 antenna port and the higher layer parameter txConfig = codebook + // Table 7.3.1.1.2-2: transformPrecoder=disabled and maxRank = 2 or 3 or 4 + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) + && ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2) || + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) || + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){ + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1]; + } + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3]; + } + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5]; + } + } + // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1 + if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) + || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) + && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7]; + } + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9]; + } + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11]; + } + } + } + if (n_antenna_port == 4){ // 2 antenna port and the higher layer parameter txConfig = codebook + // Table 7.3.1.1.2-4: transformPrecoder=disabled and maxRank = 2 + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) + && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){ + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13]; + } + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15]; + } + } + // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1 + if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) + || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) + && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17]; + } + if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19]; + } + } + } + } + /* ANTENNA_PORTS */ + uint8_t rank=0; // We need to initialize rank FIXME!!! + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6 + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports; + } + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7 + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports); + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; + } + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11 + if (rank == 1){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports); + } + if (rank == 2){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0; + ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1; + } + if (rank == 3){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = 0; + ulsch_config_pdu_0_1->dmrs_ports[1] = 1; + ulsch_config_pdu_0_1->dmrs_ports[2] = 2; + } + if (rank == 4){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = 0; + ulsch_config_pdu_0_1->dmrs_ports[1] = 1; + ulsch_config_pdu_0_1->dmrs_ports[2] = 2; + ulsch_config_pdu_0_1->dmrs_ports[3] = 3; + } + } + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15 + if (rank == 1){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1; + } + if (rank == 2){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; + } + if (rank == 3){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3]; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; + } + if (rank == 4){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3]; + ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4]; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; + } + } + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19 + if (rank == 1){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; + } + if (rank == 2){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2]; + } + if (rank == 3){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3]; + } + if (rank == 4){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2; + ulsch_config_pdu_0_1->dmrs_ports[0] = 0; + ulsch_config_pdu_0_1->dmrs_ports[1] = 1; + ulsch_config_pdu_0_1->dmrs_ports[2] = 2; + ulsch_config_pdu_0_1->dmrs_ports[3] = 3; + } + } + if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23 + if (rank == 1){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2]; + } + if (rank == 2){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3]; + } + if (rank == 3){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4]; + } + if (rank == 4){ + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3]; + ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5]; + } + } + /* SRS_REQUEST */ + // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! + ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 + /* CSI_REQUEST */ + ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request; + /* CBGTI */ + ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti; + /* PTRS_DMRS */ + if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) || + ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && + (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){ + } else { + ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs; + } + /* BETA_OFFSET_IND */ + // Table 9.3-3 in [5, TS 38.213] + ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind; + /* DMRS_SEQ_INI */ + // FIXME!! + /* UL_SCH_IND */ + // A value of "1" indicates UL-SCH shall be transmitted on the PUSCH and + // a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH + + ul_config->number_pdus = ul_config->number_pdus + 1; + break; + + case NR_DL_DCI_FORMAT_1_0: + /* + * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI + * 0 IDENTIFIER_DCI_FORMATS: + * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + * 24 MCS: + * 25 NDI: + * 26 RV: + * 27 HARQ_PROCESS_NUMBER: + * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI + * 33 TPC_PUCCH: + * 34 PUCCH_RESOURCE_IND: + * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: + * 55 RESERVED_NR_DCI + * with CRC scrambled by P-RNTI + * 8 SHORT_MESSAGE_IND + * 9 SHORT_MESSAGES + * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + * 24 MCS: + * 31 TB_SCALING + * 55 RESERVED_NR_DCI + * with CRC scrambled by SI-RNTI + * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + * 24 MCS: + * 26 RV: + * 55 RESERVED_NR_DCI + * with CRC scrambled by RA-RNTI + * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + * 24 MCS: + * 31 TB_SCALING + * 55 RESERVED_NR_DCI + * with CRC scrambled by TC-RNTI + * 0 IDENTIFIER_DCI_FORMATS: + * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + * 24 MCS: + * 25 NDI: + * 26 RV: + * 27 HARQ_PROCESS_NUMBER: + * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI + * 33 TPC_PUCCH: + */ + + dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti; + //fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_pdu_1_0 = dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; + fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_0 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; + dlsch_config_pdu_1_0->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + dlsch_config_pdu_1_0->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + dlsch_config_pdu_1_0->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; + /* IDENTIFIER_DCI_FORMATS */ + /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ + nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); + /* TIME_DOM_RESOURCE_ASSIGNMENT */ + nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0, + dci->time_dom_resource_assignment); + + /* dmrs symbol positions*/ + dlsch_config_pdu_1_0->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config, + mac->scc->dmrs_TypeA_Position, + dlsch_config_pdu_1_0->number_symbols); + dlsch_config_pdu_1_0->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2; + /* VRB_TO_PRB_MAPPING */ + dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; + /* MCS */ + dlsch_config_pdu_1_0->mcs = dci->mcs; + /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ + dlsch_config_pdu_1_0->ndi = dci->ndi; + /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ + dlsch_config_pdu_1_0->rv = dci->rv; + /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ + dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number; + /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ + dlsch_config_pdu_1_0->dai = dci ->dai; + /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */ + // according to TS 38.214 Table 5.1.3.2-3 + if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1; + if (dci->tb_scaling == 1) dlsch_config_pdu_1_0->scaling_factor_S = 0.5; + if (dci->tb_scaling == 2) dlsch_config_pdu_1_0->scaling_factor_S = 0.25; + if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table + /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ + // according to TS 38.213 Table 7.2.1-1 + if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1; + if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0; + if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1; + if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3; + /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ + //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! + //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! + //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! + //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! + //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! + //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! + //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! + //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind; + /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ + dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind; + + LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n", + dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti, + dl_config->number_pdus); + LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n", + dci->freq_dom_resource_assignment_DL, + dlsch_config_pdu_1_0->number_rbs, + dlsch_config_pdu_1_0->start_rb); + LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n", + dci->time_dom_resource_assignment, + dlsch_config_pdu_1_0->number_symbols, + dlsch_config_pdu_1_0->start_symbol); + LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n", + dlsch_config_pdu_1_0->vrb_to_prb_mapping, + dlsch_config_pdu_1_0->mcs, + dlsch_config_pdu_1_0->ndi, + dlsch_config_pdu_1_0->rv, + dlsch_config_pdu_1_0->harq_process_nbr, + dlsch_config_pdu_1_0->dai, + dlsch_config_pdu_1_0->scaling_factor_S, + dlsch_config_pdu_1_0->accumulated_delta_PUCCH, + dlsch_config_pdu_1_0->pucch_resource_id, + dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind); + + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + // dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP; + + LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type); + + dl_config->number_pdus = dl_config->number_pdus + 1; + break; + + case NR_DL_DCI_FORMAT_1_1: + /* + * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI + * 0 IDENTIFIER_DCI_FORMATS: + * 1 CARRIER_IND: + * 7 BANDWIDTH_PART_IND: + * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: + * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, + * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 + * 14 PRB_BUNDLING_SIZE_IND: + * 15 RATE_MATCHING_IND: + * 16 ZP_CSI_RS_TRIGGER: + * 18 TB1_MCS: + * 19 TB1_NDI: + * 20 TB1_RV: + * 21 TB2_MCS: + * 22 TB2_NDI: + * 23 TB2_RV: + * 27 HARQ_PROCESS_NUMBER: + * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI + * 33 TPC_PUCCH: + * 34 PUCCH_RESOURCE_IND: + * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: + * 38 ANTENNA_PORTS: + * 39 TCI: + * 40 SRS_REQUEST: + * 43 CBGTI: + * 44 CBGFI: + * 47 DMRS_SEQ_INI: + */ + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti; + fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_1 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; + /* IDENTIFIER_DCI_FORMATS */ + /* CARRIER_IND */ + /* BANDWIDTH_PART_IND */ + // dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind; + /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ + nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); + /* TIME_DOM_RESOURCE_ASSIGNMENT */ + nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1, + dci->time_dom_resource_assignment); + /* VRB_TO_PRB_MAPPING */ + if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0) + dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; + /* PRB_BUNDLING_SIZE_IND */ + dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind; + /* RATE_MATCHING_IND */ + dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind; + /* ZP_CSI_RS_TRIGGER */ + dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger; + /* MCS (for transport block 1)*/ + dlsch_config_pdu_1_1->mcs = dci->tb1_mcs; + /* NDI (for transport block 1)*/ + dlsch_config_pdu_1_1->ndi = dci->tb1_ndi; + /* RV (for transport block 1)*/ + dlsch_config_pdu_1_1->rv = dci->tb1_rv; + /* MCS (for transport block 2)*/ + dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs; + /* NDI (for transport block 2)*/ + dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi; + /* RV (for transport block 2)*/ + dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv; + /* HARQ_PROCESS_NUMBER */ + dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number; + /* DAI */ + dlsch_config_pdu_1_1->dai = dci ->dai; + /* TPC_PUCCH */ + // according to TS 38.213 Table 7.2.1-1 + if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1; + if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0; + if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; + if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; + /* PUCCH_RESOURCE_IND */ + if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! + if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! + if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! + if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! + if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! + if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! + if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! + if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */ + // according to TS 38.213 Table 9.2.3-1 + dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind]; + /* ANTENNA_PORTS */ + uint8_t n_codewords = 1; // FIXME!!! + if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && + (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ + // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1 + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4]; + } + if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && + (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ + // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2 + if (n_codewords == 1) { + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5]; + } + if (n_codewords == 1) { + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6]; + dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7]; + dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9]; + } + } + if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && + (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ + // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1 + if (n_codewords == 1) { + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4]; + } + if (n_codewords == 1) { + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6]; + } + } + if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && + (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ + // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2 + if (n_codewords == 1) { + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5]; + } + if (n_codewords == 1) { + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6]; + dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7]; + dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9]; + } + } + /* TCI */ + if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){ + // 0 bit if higher layer parameter tci-PresentInDCI is not enabled + // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214] + dlsch_config_pdu_1_1->tci_state = dci->tci; + } + /* SRS_REQUEST */ + // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! + dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 + /* CBGTI */ + dlsch_config_pdu_1_1->cbgti = dci->cbgti; + /* CBGFI */ + dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi; + /* DMRS_SEQ_INI */ + //FIXME!!! + + // dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP; + + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type); + + dl_config->number_pdus = dl_config->number_pdus + 1; + + break; + + case NR_DL_DCI_FORMAT_2_0: + break; + + case NR_DL_DCI_FORMAT_2_1: + break; + + case NR_DL_DCI_FORMAT_2_2: + break; + + case NR_DL_DCI_FORMAT_2_3: + break; + + default: + break; + } + + + if(rnti == SI_RNTI){ + + // }else if(rnti == mac->ra_rnti){ + + }else if(rnti == P_RNTI){ + + }else{ // c-rnti + + /// check if this is pdcch order + //dci->random_access_preamble_index; + //dci->ss_pbch_index; + //dci->prach_mask_index; + + /// else normal DL-SCH grant + } + return 0; } int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe){ - return 0; + return 0; } void nr_ue_send_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, - uint8_t ttiP, + int slotP, uint8_t * pdu, uint16_t pdu_len, uint8_t gNB_index, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ - LOG_D(MAC, "Handling PDU frame %d slot %d\n", frameP, ttiP); + LOG_D(MAC, "Handling PDU frame %d slot %d\n", frameP, slotP); uint8_t * pduP = pdu; NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP); - /* - #if UE_TIMING_TRACE - start_meas(&UE_mac_inst[module_idP].rx_dlsch_sdu); - #endif - */ - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SEND_SDU, VCD_FUNCTION_IN); //LOG_D(MAC,"sdu: %x.%x.%x\n",sdu[0],sdu[1],sdu[2]); - if (opt_enabled) { - trace_pdu(DIRECTION_DOWNLINK, pduP, pdu_len, module_idP, WS_C_RNTI, - (int)(UE_mac_inst[module_idP].cs_RNTI), frameP, ttiP, 0, 0); //subframeP - LOG_D(OPT, "[UE %d][DLSCH] Frame %d trace pdu for rnti %p with size %d\n", - module_idP, frameP, UE_mac_inst[module_idP].cs_RNTI, pdu_len); - } - /* #ifdef DEBUG_HEADER_PARSING LOG_D(MAC, "[UE %d] ue_send_sdu : Frame %d gNB_index %d : num_ce %d num_sdu %d\n", @@ -2098,21 +2706,366 @@ void nr_ue_send_sdu(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SEND_SDU, VCD_FUNCTION_OUT); - /* - #if UE_TIMING_TRACE - stop_meas(&UE_mac_inst[module_idP].rx_dlsch_sdu); - #endif - */ } -void nr_ue_process_mac_pdu( - module_id_t module_idP, - uint8_t CC_id, - frame_t frameP, - uint8_t *pduP, - uint16_t mac_pdu_len, - uint8_t gNB_index, - NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ +void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, + int dci_format, + uint8_t dci_size, + uint16_t rnti, + uint64_t *dci_pdu, + nr_dci_pdu_rel15_t *dci_pdu_rel15) { + int rnti_type=-1; + + if (rnti == mac->ra_rnti) rnti_type = NR_RNTI_RA; + else if (rnti == mac->crnti) rnti_type = NR_RNTI_C; + else if (rnti == mac->t_crnti) rnti_type = NR_RNTI_TC; + else if (rnti == 0xFFFE) rnti_type = NR_RNTI_P; + else if (rnti == 0xFFFF) rnti_type = NR_RNTI_SI; + + AssertFatal(rnti_type!=-1,"no identified/handled rnti\n"); + AssertFatal(mac->DLbwp[0] != NULL, "DLbwp[0] shouldn't be null here!\n"); + AssertFatal(mac->ULbwp[0] != NULL, "ULbwp[0] shouldn't be null here!\n"); + int N_RB = (mac->scd != NULL) ? + NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) : + NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); + int N_RB_UL = (mac->scd != NULL) ? + NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) : + NRRIV2BW(mac->scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); + + int pos=0; + int fsize=0; + switch(dci_format) { + + case NR_DL_DCI_FORMAT_1_0: + switch(rnti_type) { + case NR_RNTI_RA: + // Freq domain assignment + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos=fsize; + dci_pdu_rel15->freq_dom_resource_assignment_DL = *dci_pdu>>(dci_size-pos)&((1< %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,N_RB,dci_size-pos,*dci_pdu); +#endif + // Time domain assignment + pos+=4; + dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu >> (dci_size-pos))&0xf; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu); +#endif + // VRB to PRB mapping + + pos++; + dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&0x1; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); +#endif + // MCS + pos+=5; + dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); +#endif + // TB scaling + pos+=2; + dci_pdu_rel15->tb_scaling = (*dci_pdu>>(dci_size-pos))&0x3; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); +#endif + break; + + case NR_RNTI_C: + + // indicating a DL DCI format 1bit + pos++; + dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->identifier_dci_formats,1,N_RB,dci_size-pos,*dci_pdu); +#endif + + // Freq domain assignment (275rb >> fsize = 16) + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos+=fsize; + dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1< %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,dci_size-pos,*dci_pdu); +#endif + + uint16_t is_ra = 1; + for (int i=0; ifreq_dom_resource_assignment_DL>>i)&1)) { + is_ra = 0; + break; + } + if (is_ra) //fsize are all 1 38.212 p86 + { + // ra_preamble_index 6 bits + pos+=6; + dci_pdu_rel15->ra_preamble_index = (*dci_pdu>>(dci_size-pos))&0x3f; + + // UL/SUL indicator 1 bit + pos++; + dci_pdu_rel15->sul_ind_0_1 = (*dci_pdu>>(dci_size-pos))&1; + + // SS/PBCH index 6 bits + pos+=6; + dci_pdu_rel15->ss_pbch_index = (*dci_pdu>>(dci_size-pos))&0x3f; + + // prach_mask_index 4 bits + pos+=4; + dci_pdu_rel15->prach_mask_index = (*dci_pdu>>(dci_size-pos))&0xf; + + } //end if + else { + + // Time domain assignment 4bit + + pos+=4; + dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,4,dci_size-pos,*dci_pdu); +#endif + + // VRB to PRB mapping 1bit + pos++; + dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); +#endif + + // MCS 5bit //bit over 32, so dci_pdu ++ + pos+=5; + dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu); +#endif + + // New data indicator 1bit + pos++; + dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu); +#endif + + // Redundancy version 2bit + pos+=2; + dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu); +#endif + + // HARQ process number 4bit + pos+=4; + dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_process_number,4,dci_size-pos,*dci_pdu); +#endif + + // Downlink assignment index 2bit + pos+=2; + dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); +#endif + + // TPC command for scheduled PUCCH 2bit + pos+=2; + dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc_pucch,2,dci_size-pos,*dci_pdu); +#endif + + // PUCCH resource indicator 3bit + pos+=3; + dci_pdu_rel15->pucch_resource_ind = (*dci_pdu>>(dci_size-pos))&0x7; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_ind,3,dci_size-pos,*dci_pdu); +#endif + + // PDSCH-to-HARQ_feedback timing indicator 3bit + pos+=3; + dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&0x7; +#ifdef DEBUG_EXTRACT_DCI + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_time_ind,3,dci_size-pos,*dci_pdu); +#endif + + } //end else + break; + + case NR_RNTI_P: + /* + // Short Messages Indicator – 2 bits + for (int i=0; i<2; i++) + dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++); + // Short Messages – 8 bits + for (int i=0; i<8; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + + // TB scaling 2 bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++); + */ + + break; + + case NR_RNTI_SI: + /* + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + */ + break; + + case NR_RNTI_TC: + // indicating a DL DCI format 1bit + pos++; + dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos+=fsize; + dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + // VRB to PRB mapping 1 bit + dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1; + // MCS 5bit //bit over 32, so dci_pdu ++ + pos+=5; + dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; + // New data indicator 1bit + dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1; + // Redundancy version 2bit + pos+=2; + dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3; + // HARQ process number 4bit + pos+=4; + dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + // Downlink assignment index – 2 bits + pos+=2; + dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3; + // TPC command for scheduled PUCCH – 2 bits + pos+=2; + dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3; + // PDSCH-to-HARQ_feedback timing indicator – 3 bits + pos+=3; + dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&7; + + break; + } + break; + + case NR_UL_DCI_FORMAT_0_0: + switch(rnti_type) + { + case NR_RNTI_C: + // indicating a DL DCI format 1bit + dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); + pos+=fsize; + dci_pdu_rel15->freq_dom_resource_assignment_UL = (*dci_pdu>>(dci_size-pos))&((1<time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + // Frequency hopping flag – 1 bit + pos++; + dci_pdu_rel15->freq_hopping_flag= (*dci_pdu>>(dci_size-pos))&1; + // MCS 5 bit + pos+=5; + dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f; + // New data indicator 1bit + pos++; + dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1; + // Redundancy version 2bit + pos+=2; + dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3; + // HARQ process number 4bit + pos+=4; + dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + // TPC command for scheduled PUSCH – 2 bits + pos+=2; + dci_pdu_rel15->tpc_pusch = (*dci_pdu>>(dci_size-pos))&3; + // UL/SUL indicator – 1 bit + /* commented for now (RK): need to get this from BWP descriptor + if (cfg->pucch_config.pucch_GroupHopping.value) + dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++); + */ + break; + + case NR_RNTI_TC: + /* + // indicating a DL DCI format 1bit + dci_pdu->= (*dci_pdu>>(dci_size-pos)format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); + for (int i=0; i= ((*dci_pdu>>(dci_size-pos)frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // Frequency hopping flag – 1 bit + dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)frequency_hopping_flag&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)*dci_pdu>>(dci_size-pos)harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)tpc>>(1-i))&1)<<(dci_size-pos++); + */ + // UL/SUL indicator – 1 bit + /* + commented for now (RK): need to get this information from BWP descriptor + if (cfg->pucch_config.pucch_GroupHopping.value) + dci_pdu->= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + */ + break; + + } + break; + } +} + + +void nr_ue_process_mac_pdu(module_id_t module_idP, + uint8_t CC_id, + frame_t frameP, + uint8_t *pduP, + uint16_t mac_pdu_len, + uint8_t gNB_index, + NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ // This function is adapting code from the old // parse_header(...) and ue_send_sdu(...) functions of OAI LTE @@ -2151,9 +3104,9 @@ void nr_ue_process_mac_pdu( // R: Reserved bit, set to zero. while (!done && pdu_len > 0){ - mac_ce_len = 0; - mac_subheader_len = 1; // default to fixed-length subheader = 1-oct - mac_sdu_len = 0; + mac_ce_len = 0x0000; + mac_subheader_len = 0x0001; // default to fixed-length subheader = 1-oct + mac_sdu_len = 0x0000; rx_lcid = ((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID; switch(rx_lcid){ diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 438dd24ecf..c911fbd56a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -41,8 +41,10 @@ #include "NR_ServingCellConfigCommon.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "SCHED_NR/phy_frame_config_nr.h" #include "NR_MIB.h" +#include "nr_mac_common.h" extern RAN_CONTEXT_t RC; //extern int l2_init_gNB(void); @@ -50,170 +52,323 @@ extern void mac_top_init_gNB(void); extern uint8_t nfapi_mode; -void config_nr_mib(int Mod_idP, - int CC_idP, - int p_gNBP, - int subCarrierSpacingCommon, - uint32_t ssb_SubcarrierOffset, - int dmrs_TypeA_Position, - uint32_t pdcch_ConfigSIB1, - int cellBarred, - int intraFreqReselection - ){ - nfapi_nr_config_request_t *cfg = &RC.nrmac[Mod_idP]->config[CC_idP]; +void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigCommon_t *scc) { - cfg->num_tlv=0; - - cfg->rf_config.dl_subcarrierspacing.value = subCarrierSpacingCommon; + nfapi_nr_config_request_scf_t *cfg = &RC.nrmac[Mod_idP]->config[0]; + RC.nrmac[Mod_idP]->common_channels[0].ServingCellConfigCommon = scc; + int i; - cfg->rf_config.dl_subcarrierspacing.tl.tag = NFAPI_NR_RF_CONFIG_DL_SUBCARRIERSPACING_TAG; + // Carrier configuration + + cfg->carrier_config.dl_bandwidth.value = config_bandwidth(scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing, + scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth, + *scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]); + cfg->carrier_config.dl_bandwidth.tl.tag = NFAPI_NR_CONFIG_DL_BANDWIDTH_TAG; //temporary cfg->num_tlv++; - - cfg->rf_config.ul_subcarrierspacing.value = subCarrierSpacingCommon; - cfg->rf_config.ul_subcarrierspacing.tl.tag = NFAPI_NR_RF_CONFIG_UL_SUBCARRIERSPACING_TAG; + LOG_I(PHY,"%s() dl_BandwidthP:%d\n", __FUNCTION__, cfg->carrier_config.dl_bandwidth.value); + + cfg->carrier_config.dl_frequency.value = from_nrarfcn(*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0], + *scc->ssbSubcarrierSpacing, + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA)/1000; // freq in kHz + cfg->carrier_config.dl_frequency.tl.tag = NFAPI_NR_CONFIG_DL_FREQUENCY_TAG; cfg->num_tlv++; - cfg->sch_config.ssb_subcarrier_offset.value = ssb_SubcarrierOffset; - cfg->sch_config.ssb_subcarrier_offset.tl.tag = NFAPI_NR_SCH_CONFIG_SSB_SUBCARRIER_OFFSET_TAG; - cfg->num_tlv++; -} - -void config_common(int Mod_idP, - int CC_idP, - int cellid, - int nr_bandP, - uint64_t ssb_pattern, - uint16_t ssb_periodicity, - uint64_t dl_CarrierFreqP, - uint32_t dl_BandwidthP) -{ - nfapi_nr_config_request_t *cfg = &RC.nrmac[Mod_idP]->config[CC_idP]; - - int mu = 1; - - cfg->sch_config.physical_cell_id.value = cellid; - cfg->sch_config.ssb_scg_position_in_burst.value = ssb_pattern; - cfg->sch_config.ssb_periodicity.value = ssb_periodicity; - - // FDD - cfg->subframe_config.duplex_mode.value = 1; - cfg->subframe_config.duplex_mode.tl.tag = NFAPI_SUBFRAME_CONFIG_DUPLEX_MODE_TAG; - cfg->num_tlv++; - - /// In NR DL and UL will be different band - cfg->nfapi_config.rf_bands.number_rf_bands = 1; - cfg->nfapi_config.rf_bands.rf_band[0] = nr_bandP; - cfg->nfapi_config.rf_bands.tl.tag = NFAPI_PHY_RF_BANDS_TAG; - cfg->num_tlv++; - - cfg->nfapi_config.nrarfcn.value = to_nrarfcn(nr_bandP,dl_CarrierFreqP,dl_BandwidthP*180000*(1+mu)); - cfg->nfapi_config.nrarfcn.tl.tag = NFAPI_NR_NFAPI_NRARFCN_TAG; - cfg->num_tlv++; - - cfg->subframe_config.numerology_index_mu.value = mu; - //cfg->subframe_config.tl.tag = - //cfg->num_tlv++; - - cfg->rf_config.dl_carrier_bandwidth.value = dl_BandwidthP; - cfg->rf_config.dl_carrier_bandwidth.tl.tag = NFAPI_RF_CONFIG_DL_CHANNEL_BANDWIDTH_TAG; //temporary - cfg->num_tlv++; - LOG_I(PHY,"%s() dl_BandwidthP:%d\n", __FUNCTION__, dl_BandwidthP); - - cfg->rf_config.ul_carrier_bandwidth.value = dl_BandwidthP; - cfg->rf_config.ul_carrier_bandwidth.tl.tag = NFAPI_RF_CONFIG_UL_CHANNEL_BANDWIDTH_TAG; //temporary - cfg->num_tlv++; - - //cfg->sch_config.half_frame_index.value = 0; Fix in PHY - //cfg->sch_config.n_ssb_crb.value = 86; Fix in PHY - -} - -/*void config_servingcellconfigcommon(){ - -}*/ - -int rrc_mac_config_req_gNB(module_id_t Mod_idP, - int CC_idP, - int cellid, - int p_gNB, - int nr_bandP, - uint64_t ssb_pattern, - uint16_t ssb_enum_periodicity, - uint64_t dl_CarrierFreqP, - int dl_BandwidthP, - NR_BCCH_BCH_Message_t *mib, - NR_ServingCellConfigCommon_t *servingcellconfigcommon) -{ - uint16_t ssb_periodicity=0; - - switch (ssb_enum_periodicity) { - case 0: - ssb_periodicity = 5; - break; - case 1: - ssb_periodicity = 10; - break; - case 2: - ssb_periodicity = 20; - break; - case 3: - ssb_periodicity = 40; - break; - case 4: - ssb_periodicity = 80; - break; - case 5: - ssb_periodicity = 160; - break; - } - - if( mib != NULL ){ - config_nr_mib(Mod_idP, - CC_idP, - p_gNB, - mib->message.choice.mib->subCarrierSpacingCommon, - mib->message.choice.mib->ssb_SubcarrierOffset, - mib->message.choice.mib->dmrs_TypeA_Position, - mib->message.choice.mib->pdcch_ConfigSIB1.controlResourceSetZero * 16 + mib->message.choice.mib->pdcch_ConfigSIB1.searchSpaceZero, - mib->message.choice.mib->cellBarred, - mib->message.choice.mib->intraFreqReselection - ); - }// END if( mib != NULL ) - - - if( servingcellconfigcommon != NULL ){ - config_common(Mod_idP, - CC_idP, - cellid, - nr_bandP, - ssb_pattern, - ssb_periodicity, - dl_CarrierFreqP, - dl_BandwidthP - ); - }//END if( servingcellconfigcommon != NULL ) - - LOG_E(MAC, "%s() %s:%d RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req:%p\n", __FUNCTION__, __FILE__, __LINE__, RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req); - - // if in nFAPI mode - if ( (nfapi_mode == 1 || nfapi_mode == 2) && (RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req == NULL) ){ - while(RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req == NULL) { - // DJP AssertFatal(RC.nrmac[Mod_idP]->if_inst->PHY_config_req != NULL,"if_inst->phy_config_request is null\n"); - usleep(100 * 1000); - printf("Waiting for PHY_config_req\n"); + for (i=0; i<5; i++) { + if (i==scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing) { + cfg->carrier_config.dl_grid_size[i].value = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + cfg->carrier_config.dl_k0[i].value = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier; + cfg->carrier_config.dl_grid_size[i].tl.tag = NFAPI_NR_CONFIG_DL_GRID_SIZE_TAG; + cfg->carrier_config.dl_k0[i].tl.tag = NFAPI_NR_CONFIG_DL_K0_TAG; + cfg->num_tlv++; + cfg->num_tlv++; + } + else { + cfg->carrier_config.dl_grid_size[i].value = 0; + cfg->carrier_config.dl_k0[i].value = 0; } } - if (servingcellconfigcommon != NULL){ + cfg->carrier_config.uplink_bandwidth.value = config_bandwidth(scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing, + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth, + *scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]); + cfg->carrier_config.uplink_bandwidth.tl.tag = NFAPI_NR_CONFIG_UPLINK_BANDWIDTH_TAG; //temporary + cfg->num_tlv++; + LOG_I(PHY,"%s() dl_BandwidthP:%d\n", __FUNCTION__, cfg->carrier_config.uplink_bandwidth.value); + + int UL_pointA; + if (scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA == NULL) + UL_pointA = scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA; + else + UL_pointA = *scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA; + + cfg->carrier_config.uplink_frequency.value = from_nrarfcn(*scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0], + *scc->ssbSubcarrierSpacing, + UL_pointA)/1000; // freq in kHz + cfg->carrier_config.uplink_frequency.tl.tag = NFAPI_NR_CONFIG_UPLINK_FREQUENCY_TAG; + cfg->num_tlv++; + + for (i=0; i<5; i++) { + if (i==scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing) { + cfg->carrier_config.ul_grid_size[i].value = scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + cfg->carrier_config.ul_k0[i].value = scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier; + cfg->carrier_config.ul_grid_size[i].tl.tag = NFAPI_NR_CONFIG_UL_GRID_SIZE_TAG; + cfg->carrier_config.ul_k0[i].tl.tag = NFAPI_NR_CONFIG_UL_K0_TAG; + cfg->num_tlv++; + cfg->num_tlv++; + } + else { + cfg->carrier_config.ul_grid_size[i].value = 0; + cfg->carrier_config.ul_k0[i].value = 0; + } + } + + + // Cell configuration + cfg->cell_config.phy_cell_id.value = *scc->physCellId; + cfg->cell_config.phy_cell_id.tl.tag = NFAPI_NR_CONFIG_PHY_CELL_ID_TAG; + cfg->num_tlv++; + + cfg->cell_config.frame_duplex_type.value = 1; + cfg->cell_config.frame_duplex_type.tl.tag = NFAPI_NR_CONFIG_FRAME_DUPLEX_TYPE_TAG; + cfg->num_tlv++; + + + // SSB configuration + cfg->ssb_config.ss_pbch_power.value = scc->ss_PBCH_BlockPower; + cfg->ssb_config.ss_pbch_power.tl.tag = NFAPI_NR_CONFIG_SS_PBCH_POWER_TAG; + cfg->num_tlv++; + + cfg->ssb_config.scs_common.value = *scc->ssbSubcarrierSpacing; + cfg->ssb_config.scs_common.tl.tag = NFAPI_NR_CONFIG_SCS_COMMON_TAG; + cfg->num_tlv++; + + // PRACH configuration + + cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present; + cfg->prach_config.prach_sequence_length.tl.tag = NFAPI_NR_CONFIG_PRACH_SEQUENCE_LENGTH_TAG; + cfg->num_tlv++; + + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) + cfg->prach_config.prach_sub_c_spacing.value = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; + else + cfg->prach_config.prach_sub_c_spacing.value = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + cfg->prach_config.prach_sub_c_spacing.tl.tag = NFAPI_NR_CONFIG_PRACH_SUB_C_SPACING_TAG; + cfg->num_tlv++; + + cfg->prach_config.restricted_set_config.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig; + cfg->prach_config.restricted_set_config.tl.tag = NFAPI_NR_CONFIG_RESTRICTED_SET_CONFIG_TAG; + cfg->num_tlv++; + + switch (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM) { + case 0 : + cfg->prach_config.num_prach_fd_occasions.value = 1; + break; + case 1 : + cfg->prach_config.num_prach_fd_occasions.value = 2; + break; + case 2 : + cfg->prach_config.num_prach_fd_occasions.value = 4; + break; + case 3 : + cfg->prach_config.num_prach_fd_occasions.value = 8; + break; + default: + AssertFatal(1==0,"msg1 FDM identifier %ld undefined (0,1,2,3) \n", scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM); + } + cfg->prach_config.num_prach_fd_occasions.tl.tag = NFAPI_NR_CONFIG_NUM_PRACH_FD_OCCASIONS_TAG; + cfg->num_tlv++; + + cfg->prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(cfg->prach_config.num_prach_fd_occasions.value*sizeof(nfapi_nr_num_prach_fd_occasions_t)); + for (i=0; iprach_config.num_prach_fd_occasions.value; i++) { + cfg->prach_config.num_prach_fd_occasions_list[i].num_prach_fd_occasions = i; + if (cfg->prach_config.prach_sequence_length.value) + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139; + else + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l839; + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index.tl.tag = NFAPI_NR_CONFIG_PRACH_ROOT_SEQUENCE_INDEX_TAG; + cfg->num_tlv++; + cfg->prach_config.num_prach_fd_occasions_list[i].k1.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart; + cfg->prach_config.num_prach_fd_occasions_list[i].k1.tl.tag = NFAPI_NR_CONFIG_K1_TAG; + cfg->num_tlv++; + cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig; + cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.tl.tag = NFAPI_NR_CONFIG_PRACH_ZERO_CORR_CONF_TAG; + cfg->num_tlv++; + //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences.value = ??? + } + + cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present; + cfg->prach_config.ssb_per_rach.tl.tag = NFAPI_NR_CONFIG_SSB_PER_RACH_TAG; + cfg->num_tlv++; + + // SSB Table Configuration + int scs_scaling = 1<<(cfg->ssb_config.scs_common.value); + if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA < 600000) + scs_scaling = scs_scaling*3; + if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA > 2016666) + scs_scaling = scs_scaling>>2; + uint32_t absolute_diff = (*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB - scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA); + uint16_t sco = absolute_diff%(12*scs_scaling); + AssertFatal(sco==0,"absoluteFrequencySSB has a subcarrier offset of %d while it should be alligned with CRBs\n",sco); + cfg->ssb_table.ssb_offset_point_a.value = absolute_diff/(12*scs_scaling) - 10; //absoluteFrequencySSB is the central frequency of SSB which is made by 20RBs in total + cfg->ssb_table.ssb_offset_point_a.tl.tag = NFAPI_NR_CONFIG_SSB_OFFSET_POINT_A_TAG; + cfg->num_tlv++; + cfg->ssb_table.ssb_period.value = *scc->ssb_periodicityServingCell; + cfg->ssb_table.ssb_period.tl.tag = NFAPI_NR_CONFIG_SSB_PERIOD_TAG; + cfg->num_tlv++; + + switch (scc->ssb_PositionsInBurst->present) { + case 1 : + cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0]<<24; + cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0; + break; + case 2 : + cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0]<<24; + cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0; + break; + case 3 : + cfg->ssb_table.ssb_mask_list[0].ssb_mask.value = 0; + cfg->ssb_table.ssb_mask_list[1].ssb_mask.value = 0; + for (i=0; i<4; i++) { + cfg->ssb_table.ssb_mask_list[0].ssb_mask.value += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i+4]<ssb_table.ssb_mask_list[1].ssb_mask.value += (scc->ssb_PositionsInBurst->choice.longBitmap.buf[i]<ssb_PositionsInBurst->present); + } + + cfg->ssb_table.ssb_mask_list[0].ssb_mask.tl.tag = NFAPI_NR_CONFIG_SSB_MASK_TAG; + cfg->num_tlv++; + + cfg->carrier_config.num_tx_ant.value = pdsch_AntennaPorts; + AssertFatal(pdsch_AntennaPorts > 0 && pdsch_AntennaPorts < 13, "pdsch_AntennaPorts in 1...12\n"); + cfg->carrier_config.num_tx_ant.tl.tag = NFAPI_NR_CONFIG_NUM_TX_ANT_TAG; + int num_ssb=0; + for (int i=0;i<32;i++) { + num_ssb += (cfg->ssb_table.ssb_mask_list[0].ssb_mask.value>>i)&1; + num_ssb += (cfg->ssb_table.ssb_mask_list[1].ssb_mask.value>>i)&1; + } + + cfg->carrier_config.num_rx_ant.value = cfg->carrier_config.num_tx_ant.value; + cfg->carrier_config.num_rx_ant.tl.tag = NFAPI_NR_CONFIG_NUM_RX_ANT_TAG; + LOG_I(MAC,"Set TX/RX antenna number to %d (num ssb %d: %x,%x)\n",cfg->carrier_config.num_tx_ant.value,num_ssb,cfg->ssb_table.ssb_mask_list[0].ssb_mask.value,cfg->ssb_table.ssb_mask_list[1].ssb_mask.value); + AssertFatal(cfg->carrier_config.num_tx_ant.value > 0,"carrier_config.num_tx_ant.value %d !\n",cfg->carrier_config.num_tx_ant.value ); + cfg->num_tlv++; + cfg->num_tlv++; + + // TDD Table Configuration + //cfg->tdd_table.tdd_period.value = scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity; + cfg->tdd_table.tdd_period.tl.tag = NFAPI_NR_CONFIG_TDD_PERIOD_TAG; + cfg->num_tlv++; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 == NULL) + cfg->tdd_table.tdd_period.value = scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity; + else { + AssertFatal(scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 != NULL, + "scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 is null\n"); + cfg->tdd_table.tdd_period.value = *scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530; + } + LOG_I(MAC,"Setting TDD configuration period to %d\n",cfg->tdd_table.tdd_period.value); + if(cfg->cell_config.frame_duplex_type.value == TDD){ + int return_tdd = set_tdd_config_nr(cfg, + scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots, + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols + ); + + if (return_tdd !=0){ + LOG_E(PHY,"TDD configuration can not be done\n"); + } + else LOG_I(PHY,"TDD has been properly configurated\n"); + } + + +/* + // PDCCH-ConfigCommon + cfg->pdcch_config.controlResourceSetZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero; + cfg->pdcch_config.searchSpaceZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero; + + // PDSCH-ConfigCommon + cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; + cfg->pdsch_config.dmrs_TypeA_Position.value = scc->dmrs_TypeA_Position; + AssertFatal(cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value<=NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS,"illegal TimeDomainAllocation count %d\n",cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value); + for (int i=0;ipdsch_config.num_PDSCHTimeDomainResourceAllocations.value;i++) { + cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_k0[i].value=*scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_mappingType[i].value=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; + cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_startSymbolAndLength[i].value=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + } + + // PUSCH-ConfigCommon + cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value = scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; + cfg->pusch_config.dmrs_TypeA_Position.value = scc->dmrs_TypeA_Position+2; + AssertFatal(cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value<=NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS,"illegal TimeDomainAllocation count %d\n",cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value); + for (int i=0;ipusch_config.num_PUSCHTimeDomainResourceAllocations.value;i++) { + cfg->pusch_config.PUSCHTimeDomainResourceAllocation_k2[i].value=*scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2; + }*/ + + +} + + +int rrc_mac_config_req_gNB(module_id_t Mod_idP, + int ssb_SubcarrierOffset, + int pdsch_AntennaPorts, + NR_ServingCellConfigCommon_t *scc, + int add_ue, + uint32_t rnti, + NR_CellGroupConfig_t *secondaryCellGroup + ){ + + if (scc != NULL ) { + AssertFatal((scc->ssb_PositionsInBurst->present > 0) && (scc->ssb_PositionsInBurst->present < 4), "SSB Bitmap type %d is not valid\n",scc->ssb_PositionsInBurst->present); + + LOG_I(MAC,"Configuring common parameters from NR ServingCellConfig\n"); + + config_common(Mod_idP, + pdsch_AntennaPorts, + scc); + LOG_E(MAC, "%s() %s:%d RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req:%p\n", __FUNCTION__, __FILE__, __LINE__, RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req); + + // if in nFAPI mode + if ( (nfapi_mode == 1 || nfapi_mode == 2) && (RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req == NULL) ){ + while(RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req == NULL) { + // DJP AssertFatal(RC.nrmac[Mod_idP]->if_inst->PHY_config_req != NULL,"if_inst->phy_config_request is null\n"); + usleep(100 * 1000); + printf("Waiting for PHY_config_req\n"); + } + } + + NR_PHY_Config_t phycfg; phycfg.Mod_id = Mod_idP; - phycfg.CC_id = CC_idP; - phycfg.cfg = &RC.nrmac[Mod_idP]->config[CC_idP]; - + phycfg.CC_id = 0; + phycfg.cfg = &RC.nrmac[Mod_idP]->config[0]; + + phycfg.cfg->ssb_table.ssb_subcarrier_offset.value = ssb_SubcarrierOffset; + phycfg.cfg->ssb_table.ssb_subcarrier_offset.tl.tag = NFAPI_NR_CONFIG_SSB_SUBCARRIER_OFFSET_TAG; + phycfg.cfg->num_tlv++; + if (RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req) RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req(&phycfg); - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_OUT); } + + if (secondaryCellGroup) { + + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; + int UE_id; + if (add_ue == 1) { + UE_id = add_new_nr_ue(Mod_idP,rnti); + UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup; + LOG_I(PHY,"Added new UE_id %d/%x with initial secondaryCellGroup\n",UE_id,rnti); + } + else { // secondaryCellGroup has been updated + UE_id = find_nr_UE_id(Mod_idP,rnti); + UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup; + LOG_I(PHY,"Modified UE_id %d/%x with secondaryCellGroup\n",UE_id,rnti); + } + } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_OUT); + return(0); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index d08b8211ee..e5840d9cd1 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -57,11 +57,7 @@ #include "intertask_interface.h" -#include "assertions.h" -#include - -#define ENABLE_MAC_PAYLOAD_DEBUG -#define DEBUG_eNB_SCHEDULER 1 +#include "executables/softmodem-common.h" uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 }; @@ -70,30 +66,33 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB, frame_t frameP, sub_frame_t slotP){ - nfapi_nr_dl_config_request_t *DL_req = &gNB->DL_req[0]; - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; - nfapi_hi_dci0_request_t * HI_DCI0_req = &gNB->HI_DCI0_req[0]; - nfapi_tx_request_t *TX_req = &gNB->TX_req[0]; + nfapi_nr_dl_tti_request_t *DL_req = &gNB->DL_req[0]; + nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; + nfapi_nr_ul_dci_request_t *UL_dci_req = &gNB->UL_dci_req[0]; + nfapi_nr_tx_data_request_t *TX_req = &gNB->TX_req[0]; gNB->pdu_index[CC_idP] = 0; if (nfapi_mode==0 || nfapi_mode == 1) { // monolithic or PNF - DL_req[CC_idP].dl_config_request_body.number_dci = 0; - DL_req[CC_idP].dl_config_request_body.number_pdu = 0; - DL_req[CC_idP].dl_config_request_body.number_pdsch_rnti = 0; - //DL_req[CC_idP].dl_config_request_body.transmission_power_pcfich = 6000; - - HI_DCI0_req[CC_idP].hi_dci0_request_body.sfnsf = slotP + (frameP<<7); - HI_DCI0_req[CC_idP].hi_dci0_request_body.number_of_dci = 0; + DL_req[CC_idP].SFN = frameP; + DL_req[CC_idP].Slot = slotP; + DL_req[CC_idP].dl_tti_request_body.nPDUs = 0; + DL_req[CC_idP].dl_tti_request_body.nGroup = 0; + //DL_req[CC_idP].dl_tti_request_body.transmission_power_pcfich = 6000; + UL_dci_req[CC_idP].SFN = frameP; + UL_dci_req[CC_idP].Slot = slotP; + UL_dci_req[CC_idP].numPdus = 0; + UL_tti_req[CC_idP].SFN = frameP; + UL_tti_req[CC_idP].Slot = slotP; UL_tti_req[CC_idP].n_pdus = 0; UL_tti_req[CC_idP].n_ulsch = 0; UL_tti_req[CC_idP].n_ulcch = 0; UL_tti_req[CC_idP].n_group = 0; - TX_req[CC_idP].tx_request_body.number_of_pdus = 0; + TX_req[CC_idP].Number_of_PDUs = 0; } } @@ -105,7 +104,7 @@ void check_nr_ul_failure(module_id_t module_idP, sub_frame_t slotP) { UE_list_t *UE_list = &RC.nrmac[module_idP]->UE_list; - nfapi_nr_dl_config_request_t *DL_req = &RC.nrmac[module_idP]->DL_req[0]; + nfapi_nr_dl_dci_request_t *DL_req = &RC.nrmac[module_idP]->DL_req[0]; uint16_t rnti = UE_RNTI(module_idP, UE_id); NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels; @@ -118,11 +117,11 @@ void check_nr_ul_failure(module_id_t module_idP, UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 1; // add a format 1A dci for this UE to request an RA procedure (only one UE per subframe) - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_config_request_body.dl_config_pdu_list[DL_req[CC_id].dl_config_request_body.number_pdu]; - memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_config_request_pdu_t)); + nfapi_nr_dl_dci_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_tti_request_body.dl_config_pdu_list[DL_req[CC_id].dl_tti_request_body.number_pdu]; + memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_dci_request_pdu_t)); dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_DCI_REQUEST_DCI_DL_PDU_REL8_TAG; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = get_aggregation(get_bw_index(module_idP, CC_id), UE_list->UE_sched_ctrl[UE_id]. @@ -135,9 +134,9 @@ void check_nr_ul_failure(module_id_t module_idP, "illegal dl_Bandwidth %d\n", (int) cc[CC_id].mib->message.dl_Bandwidth); dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = nr_pdcch_order_table[cc[CC_id].mib->message.dl_Bandwidth]; - DL_req[CC_id].dl_config_request_body.number_dci++; - DL_req[CC_id].dl_config_request_body.number_pdu++; - DL_req[CC_id].dl_config_request_body.tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + DL_req[CC_id].dl_tti_request_body.number_dci++; + DL_req[CC_id].dl_tti_request_body.number_pdu++; + DL_req[CC_id].dl_tti_request_body.tl.tag = NFAPI_DL_TTI_REQUEST_BODY_TAG; LOG_I(MAC, "UE %d rnti %x: sending PDCCH order for RAPROC (failure timer %d), resource_block_coding %d \n", UE_id, rnti, @@ -258,6 +257,19 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram } */ +/* +void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { + + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + + // schedule PRACH for iniital BWP + + if (is_initialBWP_prach_subframe(frameP,subframeP)<0) return; + + // fill FAPI +} +*/ + /* void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { @@ -266,9 +278,7 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - nfapi_ul_config_request_t *ul_req_tmp = &mac->UL_req_tmp[CC_id][slotP]; - nfapi_ul_config_request_t *ul_req = &mac->UL_req[CC_id]; - nfapi_ul_config_request_pdu_t *ul_req_pdu = ul_req->ul_config_request_body.ul_config_pdu_list; + nfapi_ul_config_request_t *ul_req = &mac->UL_tti_req[CC_id]; *ul_req = *ul_req_tmp; @@ -294,23 +304,30 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, sub_frame_t slot_rxP, frame_t frame_txP, sub_frame_t slot_txP){ + + //printf("gNB_dlsch_ulsch_scheduler frameRX %d slotRX %d frameTX %d slotTX %d\n",frame_rxP,slot_rxP,frame_txP,slot_txP); protocol_ctxt_t ctxt; - - int CC_id, i = -1, UE_id = 0; + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame_txP, slot_txP,module_idP); + int CC_id, UE_id = 0; gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - UE_list_t *UE_list = &gNB->UE_list; - rnti_t rnti; + NR_UE_list_t *UE_list = &gNB->UE_list; UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; NR_COMMON_channels_t *cc = gNB->common_channels; start_meas(&RC.nrmac[module_idP]->eNB_scheduler); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); + pdcp_run(&ctxt); + //rrc_rx_tx(&ctxt, CC_id); + RC.nrmac[module_idP]->frame = frame_rxP; RC.nrmac[module_idP]->slot = slot_rxP; + // Check if there are downlink symbols in the slot, + if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) { + memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { //mbsfn_status[CC_id] = 0; @@ -322,55 +339,26 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } // refresh UE list based on UEs dropped by PHY in previous subframe + /* for (i = 0; i < MAX_MOBILES_PER_GNB; i++) { - if (0 /*UE_list->active[i]*/) { + if (UE_list->active[i]) { nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; - - nfapi_nr_coreset_t coreset = RC.nrmac[module_idP]->coreset[CC_id][1]; - nfapi_nr_search_space_t search_space = RC.nrmac[module_idP]->search_space[CC_id][1]; - - if (nr_is_dci_opportunity(search_space, - coreset, - frame_txP, - slot_txP, - *cfg)){ - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, NULL); - } - - rnti = UE_RNTI(module_idP, i); - CC_id = UE_PCCID(module_idP, i); - //int spf = get_spf(cfg); - - if (((frame_txP&127) == 0) && (slot_txP == 0)) { - LOG_I(MAC, - "UE rnti %x : %s, PHR %d dB DL CQI %d PUSCH SNR %d PUCCH SNR %d\n", - rnti, - UE_list->UE_sched_ctrl[i].ul_out_of_sync == - 0 ? "in synch" : "out of sync", - UE_list->UE_template[CC_id][i].phr_info, - UE_list->UE_sched_ctrl[i].dl_cqi[CC_id], - (UE_list->UE_sched_ctrl[i].pusch_snr[CC_id] - 128) / 2, - (UE_list->UE_sched_ctrl[i].pucch1_snr[CC_id] - 128) / 2); - } + + + rnti = 0;//UE_RNTI(module_idP, i); + CC_id = 0;//UE_PCCID(module_idP, i); } //END if (UE_list->active[i]) } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) + */ - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES,NOT_A_RNTI, frame_txP, slot_txP,module_idP); - - pdcp_run(&ctxt); - - //rrc_rx_tx(&ctxt, CC_id); - // This schedules MIB if((slot_txP == 0) && (frame_txP & 7) == 0){ schedule_nr_mib(module_idP, frame_txP, slot_txP); } - // Phytest scheduling - - // TODO once RACH is available, start ta_timer when UE is connected + // TbD once RACH is available, start ta_timer when UE is connected if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; if (ue_sched_ctl->ta_timer == 0) { @@ -384,11 +372,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, gNB->ta_len = 2; } - if (slot_rxP == NR_UPLINK_SLOT){ - nr_schedule_uss_ulsch_phytest(&RC.nrmac[module_idP]->UL_tti_req[0], frame_rxP, slot_rxP); - } - - if (slot_txP == NR_DOWNLINK_SLOT){ + // Phytest scheduling + if (get_softmodem_params()->phy_test && slot_txP==1){ nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); // resetting ta flag gNB->ta_len = 0; @@ -400,6 +385,14 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, allocate_CCEs(module_idP, CC_id, subframeP, 0); */ + } //is_nr_DL_slot + + if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { + if (get_softmodem_params()->phy_test && slot_rxP==8){ + nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); + } + } + stop_meas(&RC.nrmac[module_idP]->eNB_scheduler); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 409ba1d6d2..2a36425fae 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -60,23 +60,20 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc; - nfapi_nr_dl_config_request_t *dl_config_request; - nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu; - nfapi_tx_request_pdu_t *TX_req; + nfapi_nr_dl_tti_request_t *dl_tti_request; + nfapi_nr_dl_tti_request_body_t *dl_req; + nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu; int mib_sdu_length; int CC_id; - uint16_t sfn_sf = frameP << 7 | slotP; - AssertFatal(slotP == 0, "Subframe must be 0\n"); AssertFatal((frameP & 7) == 0, "Frame must be a multiple of 8\n"); for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - dl_config_request = &gNB->DL_req[CC_id]; - dl_req = &dl_config_request->dl_config_request_body; + dl_tti_request = &gNB->DL_req[CC_id]; + dl_req = &dl_tti_request->dl_tti_request_body; cc = &gNB->common_channels[CC_id]; mib_sdu_length = mac_rrc_nr_data_req(module_idP, CC_id, frameP, MIBCH, 1, &cc->MIB_pdu.payload[0]); // not used in this case @@ -85,38 +82,61 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ if (mib_sdu_length > 0) { - LOG_D(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->number_pdu, mib_sdu_length); + LOG_I(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->nPDUs, mib_sdu_length); if ((frameP & 1023) < 80){ - LOG_D(MAC,"[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n",module_idP, frameP, CC_id, mib_sdu_length); + LOG_I(MAC,"[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n",module_idP, frameP, CC_id, mib_sdu_length); } - dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void *) dl_config_pdu, 0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE; - dl_config_pdu->pdu_size =2 + sizeof(nfapi_nr_dl_config_bch_pdu_rel15_t); - dl_config_pdu->bch_pdu_rel15.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG; - dl_config_pdu->bch_pdu_rel15.length = mib_sdu_length; - dl_config_pdu->bch_pdu_rel15.pdu_index = gNB->pdu_index[CC_id]; - dl_config_pdu->bch_pdu_rel15.transmission_power = 6000; - dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; - dl_req->number_pdu++; - dl_config_request->header.message_id = NFAPI_DL_CONFIG_REQUEST; - dl_config_request->sfn_sf = sfn_sf; + dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void *) dl_config_pdu, 0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_config_pdu->PDUType = NFAPI_NR_DL_TTI_SSB_PDU_TYPE; + dl_config_pdu->PDUSize =2 + sizeof(nfapi_nr_dl_tti_ssb_pdu_rel15_t); - LOG_D(MAC, "gNB->DL_req[0].number_pdu %d (%p)\n", dl_req->number_pdu, &dl_req->number_pdu); - // DL request - - TX_req = &gNB->TX_req[CC_id].tx_request_body.tx_pdu_list[gNB->TX_req[CC_id].tx_request_body.number_of_pdus]; - TX_req->pdu_length = 3; - TX_req->pdu_index = gNB->pdu_index[CC_id]++; - TX_req->num_segments = 1; - TX_req->segments[0].segment_length = 3; - TX_req->segments[0].segment_data = cc[CC_id].MIB_pdu.payload; - gNB->TX_req[CC_id].tx_request_body.number_of_pdus++; - gNB->TX_req[CC_id].sfn_sf = sfn_sf; - gNB->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - gNB->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + AssertFatal(cc->ServingCellConfigCommon->physCellId!=NULL,"cc->ServingCellConfigCommon->physCellId is null\n"); + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.PhysCellId = *cc->ServingCellConfigCommon->physCellId; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.BetaPss = 0; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.SsbBlockIndex = 0; + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon!=NULL,"scc->downlinkConfigCommonL is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL!=NULL,"scc->downlinkConfigCommon->frequencyInfoDL is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB!=NULL,"scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.count==1,"Frequency Band list does not have 1 element (%d)\n",cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.count); + AssertFatal(cc->ServingCellConfigCommon->ssbSubcarrierSpacing,"ssbSubcarrierSpacing is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0],"band is null\n"); + long band = *cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]; + uint32_t ssb_offset0 = *cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB - cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA; + int ratio; + switch (*cc->ServingCellConfigCommon->ssbSubcarrierSpacing) { + case NR_SubcarrierSpacing_kHz15: + AssertFatal(band <= 79, "Band %ld is not possible for SSB with 15 kHz SCS\n",band); + if (band<77) // below 3GHz + ratio=3; // NRARFCN step is 5 kHz + else + ratio=1; // NRARFCN step is 15 kHz + break; + case NR_SubcarrierSpacing_kHz30: + AssertFatal(band <= 79, "Band %ld is not possible for SSB with 15 kHz SCS\n",band); + if (band<77) // below 3GHz + ratio=6; // NRARFCN step is 5 kHz + else + ratio=2; // NRARFCN step is 15 kHz + break; + case NR_SubcarrierSpacing_kHz120: + AssertFatal(band >= 257, "Band %ld is not possible for SSB with 120 kHz SCS\n",band); + ratio=2; // NRARFCN step is 15 kHz + break; + case NR_SubcarrierSpacing_kHz240: + AssertFatal(band >= 257, "Band %ld is not possible for SSB with 240 kHz SCS\n",band); + ratio=4; // NRARFCN step is 15 kHz + break; + default: + AssertFatal(1==0,"SCS %ld not allowed for SSB \n", *cc->ServingCellConfigCommon->ssbSubcarrierSpacing); + } + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.SsbSubcarrierOffset = 0; //kSSB + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.ssbOffsetPointA = ssb_offset0/(ratio*12) - 10; // absoluteFrequencySSB is the center of SSB + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag = 1; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload = (*(uint32_t*)cc->MIB_pdu.payload) & ((1<<24)-1); + dl_req->nPDUs++; } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 03795a8c09..1e0fd8d9a2 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -31,15 +31,32 @@ #include "nr_mac_gNB.h" #include "SCHED_NR/sched_nr.h" #include "mac_proto.h" +#include "nr_mac_common.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_dci.h" #include "executables/nr-softmodem.h" #include "LAYER2/NR_MAC_COMMON/nr_mac.h" #include "executables/softmodem-common.h" +#include "common/utils/nr/nr_common.h" +#include "NR_SCS-SpecificCarrier.h" +#include "NR_TDD-UL-DL-ConfigCommon.h" +#include "NR_FrequencyInfoUL.h" +#include "NR_RACH-ConfigGeneric.h" +#include "NR_RACH-ConfigCommon.h" +#include "NR_PUSCH-TimeDomainResourceAllocation.h" +#include "NR_PUSCH-ConfigCommon.h" +#include "NR_PUCCH-ConfigCommon.h" +#include "NR_PDSCH-TimeDomainResourceAllocation.h" +#include "NR_PDSCH-ConfigCommon.h" +#include "NR_RateMatchPattern.h" +#include "NR_RateMatchPatternLTE-CRS.h" +#include "NR_SearchSpace.h" +#include "NR_ControlResourceSet.h" + extern RAN_CONTEXT_t RC; //#define ENABLE_MAC_PAYLOAD_DEBUG 1 -uint8_t mac_pdu[MAX_NR_DLSCH_PAYLOAD_BYTES]; +//uint8_t mac_pdu[MAX_NR_DLSCH_PAYLOAD_BYTES]; /*Scheduling of DLSCH with associated DCI in common search space * current version has only a DCI for type 1 PDCCH for C_RNTI*/ @@ -47,488 +64,776 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { uint8_t CC_id; - gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; - NR_COMMON_channels_t *cc = nr_mac->common_channels; - nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_nr_dl_config_request_pdu_t *dl_config_dci_pdu; - nfapi_nr_dl_config_request_pdu_t *dl_config_dlsch_pdu; - nfapi_tx_request_pdu_t *TX_req; - nfapi_nr_config_request_t *cfg = &nr_mac->config[0]; + gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; + nfapi_nr_dl_tti_request_body_t *dl_req; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; + nfapi_nr_pdu_t *TX_req; + uint16_t rnti = 0x1234; - uint16_t sfn_sf = frameP << 7 | slotP; - int dl_carrier_bandwidth = cfg->rf_config.dl_carrier_bandwidth.value; - // everything here is hard-coded to 30 kHz - int scs = get_dlscs(cfg); - int slots_per_frame = get_spf(cfg); + + // int time_domain_assignment,k0; + + NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon; + + int dlBWP_carrier_bandwidth = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); + + + /* + int scs = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing; + + int slots_per_frame = 10*(1<downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0] >= 257 ? nr_FR2 : nr_FR1; + */ for (CC_id=0; CC_idDL_req[CC_id].dl_config_request_body; - dl_config_dci_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void *)dl_config_dci_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_dci_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; - dl_config_dci_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dci_dl_pdu)); - dl_config_dlsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1]; - memset((void *)dl_config_dlsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_dlsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE; - dl_config_dlsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dlsch_pdu)); - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *dci_dl_pdu_rel15 = &dl_config_dci_pdu->dci_dl_pdu.dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_dci_pdu->dci_dl_pdu.pdcch_params_rel15; - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15; - dlsch_pdu_rel15->start_prb = 0; - dlsch_pdu_rel15->n_prb = 50; - dlsch_pdu_rel15->start_symbol = 2; - dlsch_pdu_rel15->nb_symbols = 8; - dlsch_pdu_rel15->rnti = rnti; - dlsch_pdu_rel15->nb_layers =1; - dlsch_pdu_rel15->nb_codewords = 1; - dlsch_pdu_rel15->mcs_idx = 9; - dlsch_pdu_rel15->ndi = 1; - dlsch_pdu_rel15->redundancy_version = 0; - nr_configure_css_dci_initial(params_rel15, - scs, scs, nr_FR1, 0, 0, 0, - sfn_sf, slotP, - slots_per_frame, - dl_carrier_bandwidth); - params_rel15->first_slot = 0; - dci_dl_pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value); - dci_dl_pdu_rel15->time_domain_assignment = 3; // row index used here instead of SLIV - dci_dl_pdu_rel15->vrb_to_prb_mapping = 1; - dci_dl_pdu_rel15->mcs = 9; - dci_dl_pdu_rel15->tb_scaling = 1; - dci_dl_pdu_rel15->ra_preamble_index = 25; - dci_dl_pdu_rel15->format_indicator = 1; - dci_dl_pdu_rel15->ndi = 1; - dci_dl_pdu_rel15->rv = 0; - dci_dl_pdu_rel15->harq_pid = 0; - dci_dl_pdu_rel15->dai = 2; - dci_dl_pdu_rel15->tpc = 2; - dci_dl_pdu_rel15->pucch_resource_indicator = 7; - dci_dl_pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7; + LOG_D(MAC, "Scheduling common search space DCI type 1 dlBWP BW.firstRB %d.%d\n", + dlBWP_carrier_bandwidth, + NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275)); + + + dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; + dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); + + dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); + + + // nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + + pdsch_pdu_rel15->pduBitmap = 0; + pdsch_pdu_rel15->rnti = rnti; + pdsch_pdu_rel15->pduIndex = 0; + + // BWP + pdsch_pdu_rel15->BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->SubcarrierSpacing = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing; + pdsch_pdu_rel15->CyclicPrefix = 0; + pdsch_pdu_rel15->NrOfCodewords = 1; + int mcsIndex = 9; + pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0); + pdsch_pdu_rel15->qamModOrder[0] = 2; + pdsch_pdu_rel15->mcsIndex[0] = mcsIndex; + pdsch_pdu_rel15->mcsTable[0] = 0; + pdsch_pdu_rel15->rvIndex[0] = 0; + pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; + pdsch_pdu_rel15->nrOfLayers = 1; + pdsch_pdu_rel15->transmissionScheme = 0; + pdsch_pdu_rel15->refPoint = 0; // Point A + + pdsch_pdu_rel15->dmrsConfigType = 0; // Type 1 by default for InitialBWP + pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId; + pdsch_pdu_rel15->SCID = 0; + pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1; + pdsch_pdu_rel15->dmrsPorts = 1; + pdsch_pdu_rel15->resourceAlloc = 1; + pdsch_pdu_rel15->rbStart = 0; + pdsch_pdu_rel15->rbSize = 6; + pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP + // choose shortest PDSCH + int startSymbolAndLength=0; + int StartSymbolIndex=-1,NrOfSymbols=14; + int StartSymbolIndex_tmp,NrOfSymbols_tmp; + + for (int i=0; + idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; + i++) { + startSymbolAndLength = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength,&StartSymbolIndex_tmp,&NrOfSymbols_tmp); + if (NrOfSymbols_tmp < NrOfSymbols) { + NrOfSymbols = NrOfSymbols_tmp; + StartSymbolIndex = StartSymbolIndex_tmp; + // k0 = *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + // time_domain_assignment = i; + } + } + AssertFatal(StartSymbolIndex>=0,"StartSymbolIndex is negative\n"); + pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex; + pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols; + pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, + scc->dmrs_TypeA_Position, + NrOfSymbols); + + /* + AssertFatal(k0==0,"k0 is not zero for Initial DL BWP TimeDomain Alloc\n"); + nr_configure_css_dci_initial(pdcch_pdu_rel15, + scs, + scs, + FR, + 0, + 0, + 0, + sfn_sf, slotP, + slots_per_frame, + dlBWP_carrier_bandwidth); + + + pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->rbStart, + dlBWP_carrier_bandwidth); + pdu_rel15->time_domain_assignment = time_domain_assignment; + + pdu_rel15->vrb_to_prb_mapping = 1; + pdu_rel15->mcs = 9; + pdu_rel15->tb_scaling = 1; + + pdu_rel15->ra_preamble_index = 25; + pdu_rel15->format_indicator = 1; + pdu_rel15->ndi = 1; + pdu_rel15->rv = 0; + pdu_rel15->harq_pid = 0; + pdu_rel15->dai = 2; + pdu_rel15->tpc = 2; + pdu_rel15->pucch_resource_indicator = 7; + pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7; + LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", - dci_dl_pdu_rel15->frequency_domain_assignment, - dci_dl_pdu_rel15->time_domain_assignment, - dci_dl_pdu_rel15->vrb_to_prb_mapping, - dci_dl_pdu_rel15->mcs, - dci_dl_pdu_rel15->tb_scaling, - dci_dl_pdu_rel15->ndi, - dci_dl_pdu_rel15->rv); + pdu_rel15->frequency_domain_assignment, + pdu_rel15->time_domain_assignment, + pdu_rel15->vrb_to_prb_mapping, + pdu_rel15->mcs, + pdu_rel15->tb_scaling, + pdu_rel15->ndi, + pdu_rel15->rv); + params_rel15->rnti = rnti; params_rel15->rnti_type = NFAPI_NR_RNTI_C; params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0; //params_rel15->aggregation_level = 1; - LOG_D(MAC, "DCI type 1 params: rmsi_pdcch_config %d, rnti %d, rnti_type %d, dci_format %d\n \ + LOG_D(MAC, "DCI type 1 params: rnti %x, rnti_type %d, dci_format %d\n \ coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \ ss params : nb_ss_sets_per_slot %d, first symb %d, nb_slots %d, sfn_mod2 %d, first slot %d\n", - 0, - params_rel15->rnti, - params_rel15->rnti_type, - params_rel15->dci_format, - params_rel15->mux_pattern, - params_rel15->n_rb, - params_rel15->n_symb, - params_rel15->rb_offset, - params_rel15->nb_ss_sets_per_slot, - params_rel15->first_symbol, - params_rel15->nb_slots, - params_rel15->sfn_mod2, - params_rel15->first_slot); - nr_get_tbs_dl(&dl_config_dlsch_pdu->dlsch_pdu, dl_config_dci_pdu->dci_dl_pdu, *cfg); + params_rel15->rnti, + params_rel15->rnti_type, + params_rel15->dci_format, + params_rel15->mux_pattern, + params_rel15->n_rb, + params_rel15->n_symb, + params_rel15->rb_offset, + params_rel15->nb_ss_sets_per_slot, + params_rel15->first_symbol, + params_rel15->nb_slots, + params_rel15->sfn_mod2, + params_rel15->first_slot); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, dl_tti_dci_pdu->dci_dl_pdu,0); LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d\n", - dlsch_pdu_rel15->start_prb, - dlsch_pdu_rel15->n_prb, - dlsch_pdu_rel15->start_symbol, - dlsch_pdu_rel15->nb_symbols, - dlsch_pdu_rel15->nb_layers, - dlsch_pdu_rel15->nb_codewords, - dlsch_pdu_rel15->mcs_idx); - dl_req->number_dci++; - dl_req->number_pdsch_rnti++; - dl_req->number_pdu+=2; - TX_req = &nr_mac->TX_req[CC_id].tx_request_body.tx_pdu_list[nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus]; - TX_req->pdu_length = 6; - TX_req->pdu_index = nr_mac->pdu_index[CC_id]++; - TX_req->num_segments = 1; - TX_req->segments[0].segment_length = 8; - TX_req->segments[0].segment_data = &cc[CC_id].RAR_pdu.payload[0]; - nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus++; - nr_mac->TX_req[CC_id].sfn_sf = sfn_sf; - nr_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - nr_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->StartSymbolIndex, + pdsch_pdu_rel15->NrOfSymbols, + pdsch_pdu_rel15->nrOfLayers, + pdsch_pdu_rel15->NrOfCodewords, + pdsch_pdu_rel15->mcsIndex[0]); + */ + + dl_req->nPDUs+=2; + + TX_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; + TX_req->PDU_length = 6; + TX_req->PDU_index = nr_mac->pdu_index[CC_id]++; + TX_req->num_TLV = 1; + TX_req->TLVs[0].length = 8; + memcpy((void*)&TX_req->TLVs[0].value.direct[0],(void*)&cc[CC_id].RAR_pdu.payload[0],TX_req->TLVs[0].length); + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].SFN=frameP; + nr_mac->TX_req[CC_id].Slot=slotP; } } -int configure_fapi_dl_pdu(nfapi_nr_dl_config_request_body_t *dl_req, - nfapi_nr_config_request_t *cfg, - nfapi_nr_coreset_t *coreset, - nfapi_nr_search_space_t *search_space, - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config){ - nfapi_nr_dl_config_request_pdu_t *dl_config_dci_pdu; - nfapi_nr_dl_config_request_pdu_t *dl_config_dlsch_pdu; - uint16_t rnti = 0x1234; - int dl_carrier_bandwidth = cfg->rf_config.dl_carrier_bandwidth.value; - dl_config_dci_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void *)dl_config_dci_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_dci_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; - dl_config_dci_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dci_dl_pdu)); - dl_config_dlsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1]; - memset((void *)dl_config_dlsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_dlsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE; - dl_config_dlsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dlsch_pdu)); - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_dci_pdu->dci_dl_pdu.dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_dci_pdu->dci_dl_pdu.pdcch_params_rel15; - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15; - dlsch_pdu_rel15->start_prb = 0; - dlsch_pdu_rel15->n_prb = 50; - dlsch_pdu_rel15->start_symbol = 2; - dlsch_pdu_rel15->nb_symbols = 9; - dlsch_pdu_rel15->rnti = rnti; - dlsch_pdu_rel15->nb_layers =1; - dlsch_pdu_rel15->nb_codewords = 1; - dlsch_pdu_rel15->mcs_idx = 9; - dlsch_pdu_rel15->ndi = 1; - dlsch_pdu_rel15->redundancy_version = 0; +int configure_fapi_dl_pdu(int Mod_idP, + int *CCEIndex, + nfapi_nr_dl_tti_request_body_t *dl_req, + uint8_t *mcsIndex, + uint16_t *rbSize, + uint16_t *rbStart) { - if (dlsch_config != NULL) { - dlsch_pdu_rel15->start_prb = dlsch_config->start_prb; - dlsch_pdu_rel15->n_prb = dlsch_config->n_prb; - dlsch_pdu_rel15->start_symbol = dlsch_config->start_symbol; - dlsch_pdu_rel15->nb_symbols = dlsch_config->nb_symbols; - dlsch_pdu_rel15->mcs_idx = dlsch_config->mcs_idx; - } - nr_configure_dci_from_pdcch_config(params_rel15, - coreset, - search_space, - *cfg, - dl_carrier_bandwidth); - pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value); - pdu_rel15->time_domain_assignment = 3; // row index used here instead of SLIV; - pdu_rel15->vrb_to_prb_mapping = 1; - pdu_rel15->mcs = dlsch_pdu_rel15->mcs_idx; - pdu_rel15->tb_scaling = 1; - pdu_rel15->ra_preamble_index = 25; - pdu_rel15->format_indicator = 1; - pdu_rel15->ndi = 1; - pdu_rel15->rv = 0; - pdu_rel15->harq_pid = 0; - pdu_rel15->dai = 2; - pdu_rel15->tpc = 2; - pdu_rel15->pucch_resource_indicator = 7; - pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7; - LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", - pdu_rel15->frequency_domain_assignment, - pdu_rel15->time_domain_assignment, - pdu_rel15->vrb_to_prb_mapping, - pdu_rel15->mcs, - pdu_rel15->tb_scaling, - pdu_rel15->ndi, - pdu_rel15->rv); - params_rel15->rnti = rnti; - params_rel15->rnti_type = NFAPI_NR_RNTI_C; - params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0; - //params_rel15->aggregation_level = 1; - LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d, config type %d\n \ - coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \ - ss params : first symb %d, ss type %d\n", - params_rel15->rnti, - params_rel15->rnti_type, - params_rel15->config_type, - params_rel15->dci_format, - params_rel15->mux_pattern, - params_rel15->n_rb, - params_rel15->n_symb, - params_rel15->rb_offset, - params_rel15->first_symbol, - params_rel15->search_space_type); + gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; + NR_COMMON_channels_t *cc = nr_mac->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; + int TBS, bwp_id = 1, UE_id = 0; + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; - nr_get_tbs_dl(&dl_config_dlsch_pdu->dlsch_pdu, dl_config_dci_pdu->dci_dl_pdu, *cfg); - return dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15.transport_block_size/8; + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + + + dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); + + dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + memset((void*)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); + + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + + + pdsch_pdu_rel15->pduBitmap = 0; + pdsch_pdu_rel15->rnti = UE_list->rnti[UE_id]; + pdsch_pdu_rel15->pduIndex = 0; + + // BWP + pdsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; + if (bwp->bwp_Common->genericParameters.cyclicPrefix) pdsch_pdu_rel15->CyclicPrefix = *bwp->bwp_Common->genericParameters.cyclicPrefix; + else pdsch_pdu_rel15->CyclicPrefix=0; + + pdsch_pdu_rel15->NrOfCodewords = 1; + int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9; + pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcs,0); + pdsch_pdu_rel15->qamModOrder[0] = 2; + pdsch_pdu_rel15->mcsIndex[0] = mcs; + pdsch_pdu_rel15->mcsTable[0] = 0; + pdsch_pdu_rel15->rvIndex[0] = 0; + pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; + pdsch_pdu_rel15->nrOfLayers = 1; + pdsch_pdu_rel15->transmissionScheme = 0; + pdsch_pdu_rel15->refPoint = 0; // Point A + + pdsch_pdu_rel15->dmrsConfigType = bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1; + pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId; + pdsch_pdu_rel15->SCID = 0; + pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1; + pdsch_pdu_rel15->dmrsPorts = 1; + pdsch_pdu_rel15->resourceAlloc = 1; + pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0; + pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize; + pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP + // choose shortest PDSCH + int startSymbolAndLength=0; + int time_domain_assignment=2; + int StartSymbolIndex,NrOfSymbols; + + AssertFatal(time_domain_assignmentbwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count,"time_domain_assignment %d>=%d\n",time_domain_assignment,bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count); + startSymbolAndLength = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols); + pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex; + pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols; + + // k0 = *bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(bwp->bwp_Dedicated->pdsch_Config->choice.setup, + scc->dmrs_TypeA_Position, + pdsch_pdu_rel15->NrOfSymbols); + + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + + dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->rbStart, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV; + dci_pdu_rel15[0].vrb_to_prb_mapping = 1; + dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; + dci_pdu_rel15[0].tb_scaling = 1; + + dci_pdu_rel15[0].ra_preamble_index = 25; + dci_pdu_rel15[0].format_indicator = 1; + dci_pdu_rel15[0].ndi = 1; + dci_pdu_rel15[0].rv = 0; + dci_pdu_rel15[0].harq_pid = 0; + dci_pdu_rel15[0].dai = 2; + dci_pdu_rel15[0].tpc = 2; + dci_pdu_rel15[0].pucch_resource_indicator = 7; + dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; + + LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", + dci_pdu_rel15[0].frequency_domain_assignment, + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + dci_pdu_rel15[0].time_domain_assignment, + dci_pdu_rel15[0].vrb_to_prb_mapping, + dci_pdu_rel15[0].mcs, + dci_pdu_rel15[0].tb_scaling, + dci_pdu_rel15[0].ndi, + dci_pdu_rel15[0].rv); + + nr_configure_pdcch(pdcch_pdu_rel15, + 1, // ue-specific + scc, + bwp); + + pdcch_pdu_rel15->numDlDci = 1; + pdcch_pdu_rel15->AggregationLevel[0] = 4; + pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0]; + pdcch_pdu_rel15->CceIndex[0] = CCEIndex[0]; + pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0; + pdcch_pdu_rel15->powerControlOffsetSS[0]=1; + + int dci_formats[2]; + int rnti_types[2]; + + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + rnti_types[0] = NR_RNTI_C; + + pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + + LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ + coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", + pdcch_pdu_rel15->RNTI[0], + rnti_types[0], + dci_formats[0], + (unsigned long long)pdcch_pdu_rel15->FreqDomainResource, + pdcch_pdu_rel15->StartSymbolIndex, + pdcch_pdu_rel15->DurationSymbols); + + int x_Overhead = 0; // should be 0 for initialBWP + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead); + + // Hardcode it for now + TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; + LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + startSymbolAndLength, + pdsch_pdu_rel15->StartSymbolIndex, + pdsch_pdu_rel15->NrOfSymbols, + pdsch_pdu_rel15->nrOfLayers, + pdsch_pdu_rel15->NrOfCodewords, + pdsch_pdu_rel15->mcsIndex[0], + TBS); + + return TBS; //Return TBS in bytes } -void configure_fapi_dl_Tx(nfapi_nr_dl_config_request_body_t *dl_req, - nfapi_tx_request_pdu_t *tx_req, +void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) { + + dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, + pusch_pdu->rb_start, + NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + + dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV; + dci_pdu_rel15->frequency_hopping_flag = 0; + dci_pdu_rel15->mcs = 9; + + dci_pdu_rel15->format_indicator = 0; + dci_pdu_rel15->ndi = 1; + dci_pdu_rel15->rv = 0; + dci_pdu_rel15->harq_pid = 0; + dci_pdu_rel15->tpc = 2; + + LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", + pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], + dci_pdu_rel15->frequency_domain_assignment, + dci_pdu_rel15->time_domain_assignment, + dci_pdu_rel15->frequency_hopping_flag, + dci_pdu_rel15->mcs, + dci_pdu_rel15->tpc, + dci_pdu_rel15->ndi, + dci_pdu_rel15->rv); + + dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; + rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; + pdcch_pdu_rel15->numDlDci++; + +} + + +void configure_fapi_dl_Tx(module_id_t Mod_idP, + frame_t frameP, + sub_frame_t slotP, + nfapi_nr_dl_tti_request_body_t *dl_req, + nfapi_nr_pdu_t *tx_req, int tbs_bytes, int16_t pdu_index){ - nfapi_nr_dl_config_request_pdu_t *dl_config_dlsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu + 1]; - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15; + + int CC_id = 0; + + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS (bytes): %d\n", - dlsch_pdu_rel15->start_prb, - dlsch_pdu_rel15->n_prb, - dlsch_pdu_rel15->start_symbol, - dlsch_pdu_rel15->nb_symbols, - dlsch_pdu_rel15->nb_layers, - dlsch_pdu_rel15->nb_codewords, - dlsch_pdu_rel15->mcs_idx, + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->StartSymbolIndex, + pdsch_pdu_rel15->NrOfSymbols, + pdsch_pdu_rel15->nrOfLayers, + pdsch_pdu_rel15->NrOfCodewords, + pdsch_pdu_rel15->mcsIndex[0], tbs_bytes); - dl_req->number_dci++; - dl_req->number_pdsch_rnti++; - dl_req->number_pdu+=2; + dl_req->nPDUs+=2; - tx_req->pdu_length = tbs_bytes; - tx_req->pdu_index = pdu_index++; - tx_req->num_segments = 1; - //tx_req->segments[0].segment_length = 8; - tx_req->segments[0].segment_length = tbs_bytes + 2; - tx_req->segments[0].segment_data = mac_pdu; + tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; + tx_req->PDU_index = nr_mac->pdu_index[0]++; + tx_req->num_TLV = 1; + tx_req->TLVs[0].length = tbs_bytes +2; + + memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes);; + + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].SFN = frameP; + nr_mac->TX_req[CC_id].Slot = slotP; } void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config) { + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){ - gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; - nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_tx_request_pdu_t *tx_req; - mac_rlc_status_resp_t rlc_status; - nfapi_nr_config_request_t *cfg = &gNB_mac->config[0]; - - unsigned char sdu_lcids[NB_RB_MAX] = {0}; - uint16_t sdu_lengths[NB_RB_MAX] = {0}; + LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n"); int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0; - int CC_id, lcid, offset, i, header_length_last, TBS_bytes; + int lcid, offset, i, header_length_last, TBS_bytes; + int UE_id = 0, CCEIndex = -1, CC_id = 0; - int UE_id = 0; - uint16_t rnti = 0x1234; - uint16_t sfn_sf = frameP << 7 | slotP; + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + //NR_COMMON_channels_t *cc = nr_mac->common_channels; + //NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon; + nfapi_nr_dl_tti_request_body_t *dl_req = &gNB_mac->DL_req[CC_id].dl_tti_request_body; + nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[gNB_mac->TX_req[CC_id].Number_of_PDUs]; + + mac_rlc_status_resp_t rlc_status; + + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + + if (UE_list->num_UEs ==0) return; + + unsigned char sdu_lcids[NB_RB_MAX] = {0}; + uint16_t sdu_lengths[NB_RB_MAX] = {0}; + uint16_t rnti = UE_list->rnti[UE_id]; uint8_t mac_sdus[MAX_NR_DLSCH_PAYLOAD_BYTES]; + + LOG_D(MAC, "Scheduling UE specific search space DCI type 1\n"); - for (CC_id = 0; CC_id < RC.nb_nr_mac_CC[module_idP]; CC_id++) { + ta_len = gNB_mac->ta_len; - LOG_D(MAC, "Scheduling UE specific search space DCI type 1 for UE_id %d CC_id %d frame %d slot %d\n", UE_id, CC_id, frameP, slotP); + CCEIndex = allocate_nr_CCEs(gNB_mac, + 1, // bwp_id + 0, // coreset_id + 4, // aggregation, + 1, // search_space, 0 common, 1 ue-specific + UE_id, + 0); // m - dl_req = &gNB_mac->DL_req[CC_id].dl_config_request_body; - tx_req = &gNB_mac->TX_req[CC_id].tx_request_body.tx_pdu_list[gNB_mac->TX_req[CC_id].tx_request_body.number_of_pdus]; - ta_len = gNB_mac->ta_len; + if (CCEIndex == -1) return; - TBS_bytes = configure_fapi_dl_pdu(dl_req, cfg, &gNB_mac->coreset[CC_id][1], &gNB_mac->search_space[CC_id][1], dlsch_config); + AssertFatal(CCEIndex>0,"CCEIndex is negative\n"); + int CCEIndices[2]; + CCEIndices[0] = CCEIndex; - //The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving - //through the LTE stack - if (IS_SOFTMODEM_NOS1){ + TBS_bytes = configure_fapi_dl_pdu(module_idP, + CCEIndices, + dl_req, + dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL, + dlsch_config!=NULL ? &dlsch_config->rbSize : NULL, + dlsch_config!=NULL ? &dlsch_config->rbStart : NULL); + + //The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving + //through the LTE stack + if (IS_SOFTMODEM_NOS1){ - for (lcid = NB_RB_MAX - 1; lcid >= DTCH; lcid--) { - LOG_D(MAC, "[gNB %d], Frame %d, DTCH%d->DLSCH, Checking RLC status (TBS %d bytes, len %d)\n", - module_idP, frameP, lcid, TBS_bytes, TBS_bytes - ta_len - header_length_total - sdu_length_total - 3); + for (lcid = NB_RB_MAX - 1; lcid >= DTCH; lcid--) { - if (TBS_bytes - ta_len - header_length_total - sdu_length_total - 3 > 0) { - rlc_status = mac_rlc_status_ind(module_idP, - rnti, - module_idP, - frameP, - slotP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - lcid, - TBS_bytes - ta_len - header_length_total - sdu_length_total - 3, - 0, - 0); + // TODO: check if the lcid is active - if (rlc_status.bytes_in_buffer > 0) { - LOG_D(MAC, "[gNB %d][USER-PLANE DEFAULT DRB] Frame %d : DTCH->DLSCH, Requesting %d bytes from RLC (lcid %d total hdr len %d), TBS_bytes: %d \n \n", - module_idP, frameP, TBS_bytes - ta_len - header_length_total - sdu_length_total - 3, - lcid, header_length_total, TBS_bytes); + LOG_D(MAC, "[gNB %d], Frame %d, DTCH%d->DLSCH, Checking RLC status (TBS %d bytes, len %d)\n", + module_idP, frameP, lcid, TBS_bytes, TBS_bytes - ta_len - header_length_total - sdu_length_total - 3); - sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, - rnti, - module_idP, - frameP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - lcid, - TBS_bytes, - (char *)&mac_sdus[sdu_length_total], - 0, - 0); + if (TBS_bytes - ta_len - header_length_total - sdu_length_total - 3 > 0) { + rlc_status = mac_rlc_status_ind(module_idP, + rnti, + module_idP, + frameP, + slotP, + ENB_FLAG_YES, + MBMS_FLAG_NO, + lcid, + TBS_bytes - ta_len - header_length_total - sdu_length_total - 3, + 0, + 0); - LOG_D(MAC, "[gNB %d][USER-PLANE DEFAULT DRB] Got %d bytes for DTCH %d \n", module_idP, sdu_lengths[num_sdus], lcid); + if (rlc_status.bytes_in_buffer > 0) { - sdu_lcids[num_sdus] = lcid; - sdu_length_total += sdu_lengths[num_sdus]; - header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128); - header_length_total += header_length_last; + LOG_D(MAC, "[gNB %d][USER-PLANE DEFAULT DRB] Frame %d : DTCH->DLSCH, Requesting %d bytes from RLC (lcid %d total hdr len %d), TBS_bytes: %d \n \n", + module_idP, frameP, TBS_bytes - ta_len - header_length_total - sdu_length_total - 3, + lcid, header_length_total, TBS_bytes); - num_sdus++; + sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, + rnti, + module_idP, + frameP, + ENB_FLAG_YES, + MBMS_FLAG_NO, + lcid, + TBS_bytes, + (char *)&mac_sdus[sdu_length_total], + 0, + 0); - //ue_sched_ctl->uplane_inactivity_timer = 0; - } - } else { // no TBS_bytes left - break; + LOG_D(MAC, "[gNB %d][USER-PLANE DEFAULT DRB] Got %d bytes for DTCH %d \n", module_idP, sdu_lengths[num_sdus], lcid); + + sdu_lcids[num_sdus] = lcid; + sdu_length_total += sdu_lengths[num_sdus]; + header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128); + header_length_total += header_length_last; + + num_sdus++; + + //ue_sched_ctl->uplane_inactivity_timer = 0; } - } - - } //if (IS_SOFTMODEM_NOS1) - else { - //When the --NOS1 option is not enabled, DLSCH transmissions with random data - //occur every time that the current function is called (dlsch phytest mode) - - // fill dlsch_buffer with random data - for (i = 0; i < TBS_bytes; i++){ - mac_sdus[i] = (unsigned char) rand(); //i&0xFF; - } - - //Sending SDUs with size 1 - //Initialize elements of sdu_lcids and sdu_lengths - sdu_lcids[0] = 0x05; // DRB - sdu_lengths[0] = TBS_bytes - ta_len - 3; - header_length_total += 2 + (sdu_lengths[0] >= 128); - sdu_length_total += sdu_lengths[0]; - num_sdus +=1; - } // else IS_SOFTMODEM_NOS1 - - // there is at least one SDU or TA command - // if (num_sdus > 0 ){ - if (ta_len + sdu_length_total + header_length_total > 0) { - - // Check if there is data from RLC or CE - if (TBS_bytes >= 2 + header_length_total + sdu_length_total + ta_len) { - // we have to consider padding - // padding param currently not in use - //padding = TBS_bytes - header_length_total - sdu_length_total - ta_len - 1; - post_padding = 1; - } else { - //padding = 0; - post_padding = 0; - } - - offset = nr_generate_dlsch_pdu(module_idP, - (unsigned char *) mac_sdus, - (unsigned char *) mac_pdu, - num_sdus, //num_sdus - sdu_lengths, - sdu_lcids, - 255, // no drx - NULL, // contention res id - post_padding); - - // Padding: fill remainder of DLSCH with 0 - if (post_padding > 0){ - for (int j = 0; j < (TBS_bytes - offset); j++) - mac_pdu[offset + j] = 0; - } - - configure_fapi_dl_Tx(dl_req, tx_req, TBS_bytes, gNB_mac->pdu_index[CC_id]); - - gNB_mac->TX_req[CC_id].tx_request_body.number_of_pdus++; - gNB_mac->TX_req[CC_id].sfn_sf = sfn_sf; - gNB_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - gNB_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; - - if(IS_SOFTMODEM_NOS1){ - #if defined(ENABLE_MAC_PAYLOAD_DEBUG) - LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n \n", frameP, slotP, TBS_bytes); - for(int i = 0; i < 10; i++) { // TBS_bytes dlsch_pdu_rel15->transport_block_size/8 6784/8 - LOG_I(MAC, "%x. ", mac_payload[i]); - } - #endif - } else { - #if defined(ENABLE_MAC_PAYLOAD_DEBUG) - if (frameP%100 == 0){ - LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes); - for(int i = 0; i < 10; i++) { - LOG_I(MAC, "%x. ", mac_payload[i]); - } - } - #endif + } else { // no TBS_bytes left + break; } } - else { // There is no data from RLC or MAC header, so don't schedule + + } //if (IS_SOFTMODEM_NOS1) + else { + + //When the --NOS1 option is not enabled, DLSCH transmissions with random data + //occur every time that the current function is called (dlsch phytest mode) + + LOG_D(MAC,"Configuring DL_TX in %d.%d\n", frameP, slotP); + + // fill dlsch_buffer with random data + for (i = 0; i < TBS_bytes; i++){ + //mac_sdus[i] = (unsigned char) rand(); + ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); } - } // CC_id loop + + //Sending SDUs with size 1 + //Initialize elements of sdu_lcids and sdu_lengths + sdu_lcids[0] = 0x05; // DRB + sdu_lengths[0] = TBS_bytes - ta_len - 3; + header_length_total += 2 + (sdu_lengths[0] >= 128); + sdu_length_total += sdu_lengths[0]; + num_sdus +=1; + + #if defined(ENABLE_MAC_PAYLOAD_DEBUG) + if (frameP%100 == 0){ + LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes); + for(int i = 0; i < 10; i++) { + LOG_I(MAC, "%x. ", ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[CC_id][0][0].payload[0])[i]); + } + } + #endif + + } // else IS_SOFTMODEM_NOS1 + + // there is at least one SDU or TA command + // if (num_sdus > 0 ){ + if (ta_len + sdu_length_total + header_length_total > 0) { + + // Check if there is data from RLC or CE + if (TBS_bytes >= 2 + header_length_total + sdu_length_total + ta_len) { + // we have to consider padding + // padding param currently not in use + //padding = TBS_bytes - header_length_total - sdu_length_total - ta_len - 1; + post_padding = 1; + } else { + //padding = 0; + post_padding = 0; + } + + offset = nr_generate_dlsch_pdu(module_idP, + (unsigned char *) mac_sdus, + (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], //(unsigned char *) mac_pdu, + num_sdus, //num_sdus + sdu_lengths, + sdu_lcids, + 255, // no drx + NULL, // contention res id + post_padding); + + // Padding: fill remainder of DLSCH with 0 + if (post_padding > 0){ + for (int j = 0; j < (TBS_bytes - offset); j++) + gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0][offset + j] = 0; // mac_pdu[offset + j] = 0; + } + + configure_fapi_dl_Tx(module_idP, frameP, slotP, dl_req, tx_req, TBS_bytes, gNB_mac->pdu_index[CC_id]); + + if(IS_SOFTMODEM_NOS1){ + #if defined(ENABLE_MAC_PAYLOAD_DEBUG) + LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n \n", frameP, slotP, TBS_bytes); + for(int i = 0; i < 10; i++) { // TBS_bytes dlsch_pdu_rel15->transport_block_size/8 6784/8 + LOG_I(MAC, "%x. ", mac_payload[i]); + } + #endif + } else { + #if defined(ENABLE_MAC_PAYLOAD_DEBUG) + if (frameP%100 == 0){ + LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes); + for(int i = 0; i < 10; i++) { + LOG_I(MAC, "%x. ", ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[CC_id][0][0].payload[0])[i]); //LOG_I(MAC, "%x. ", mac_payload[i]); + } + } + #endif + } + } + else { // There is no data from RLC or MAC header, so don't schedule + } + } -void nr_schedule_uss_ulsch_phytest(nfapi_nr_ul_tti_request_t *UL_tti_req, +void nr_schedule_uss_ulsch_phytest(int Mod_idP, frame_t frameP, sub_frame_t slotP) { - //gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; - //nfapi_nr_ul_tti_request_t *UL_tti_req; - uint16_t rnti = 0x1234; - for (uint8_t CC_id=0; CC_idUL_tti_req[CC_id]; - UL_tti_req->sfn = frameP; - UL_tti_req->slot = slotP; - UL_tti_req->n_pdus = 1; - UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; - UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); - /* - // original configuration - rel15_ul->rnti = 0x1234; - rel15_ul->ulsch_pdu_rel15.start_rb = 30; - rel15_ul->ulsch_pdu_rel15.number_rbs = 50; - rel15_ul->ulsch_pdu_rel15.start_symbol = 2; - rel15_ul->ulsch_pdu_rel15.number_symbols = 12; - rel15_ul->ulsch_pdu_rel15.nb_re_dmrs = 6; - rel15_ul->ulsch_pdu_rel15.length_dmrs = 1; - rel15_ul->ulsch_pdu_rel15.Qm = 2; - rel15_ul->ulsch_pdu_rel15.mcs = 9; - rel15_ul->ulsch_pdu_rel15.rv = 0; - rel15_ul->ulsch_pdu_rel15.n_layers = 1; - */ - pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; - pusch_pdu->rnti = rnti; - pusch_pdu->handle = 0; //not yet used - //BWP related paramters - we don't yet use them as the PHY only uses one default BWP - //pusch_pdu->bwp_size; - //pusch_pdu->bwp_start; - //pusch_pdu->subcarrier_spacing; - //pusch_pdu->cyclic_prefix; - //pusch information always include - //this informantion seems to be redundant. with hthe mcs_index and the modulation table, the mod_order and target_code_rate can be determined. - pusch_pdu->mcs_index = 9; - pusch_pdu->mcs_table = 0; //0: notqam256 [TS38.214, table 5.1.3.1-1] - corresponds to nr_target_code_rate_table1 in PHY - pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; - pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; - pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.; - pusch_pdu->nrOfLayers = 1; - //DMRS - pusch_pdu->ul_dmrs_symb_pos = 1; - pusch_pdu->dmrs_config_type = 0; //dmrs-type 1 (the one with a single DMRS symbol in the beginning) - pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. - pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. - //pusch_pdu->num_dmrs_cdm_grps_no_data; - //pusch_pdu->dmrs_ports; //DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used - //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] - pusch_pdu->resource_alloc = 1; //type 1 - //pusch_pdu->rb_bitmap;// for ressource alloc type 0 - pusch_pdu->rb_start = 0; - pusch_pdu->rb_size = 50; - pusch_pdu->vrb_to_prb_mapping = 0; - pusch_pdu->frequency_hopping = 0; - //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] - pusch_pdu->uplink_frequency_shift_7p5khz = 0; - //Resource Allocation in time domain - pusch_pdu->start_symbol_index = 0; - pusch_pdu->nr_of_symbols = 12; - //Optional Data only included if indicated in pduBitmap - pusch_pdu->pusch_data.rv_index = 0; - pusch_pdu->pusch_data.harq_process_id = 0; - pusch_pdu->pusch_data.new_data_indicator = 0; - pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->mcs_index, - pusch_pdu->target_code_rate, - pusch_pdu->rb_size, - pusch_pdu->nr_of_symbols, - 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI - 0, //nb_rb_oh - pusch_pdu->nrOfLayers = 1); - pusch_pdu->pusch_data.num_cb = 0; //CBG not supported - //pusch_pdu->pusch_data.cb_present_and_position; - //pusch_pdu->pusch_uci; - //pusch_pdu->pusch_ptrs; - //pusch_pdu->dfts_ofdm; - //beamforming - //pusch_pdu->beamforming; //not used for now - } + gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; + NR_COMMON_channels_t *cc = nr_mac->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + + int bwp_id=1; + + int UE_id = 0; + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; + AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id); + + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; + nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[Mod_idP]->UL_dci_req[0]; + + + uint16_t rnti = UE_list->rnti[UE_id]; + nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu; + + UL_tti_req->SFN = frameP; + UL_tti_req->Slot = slotP; + UL_tti_req->n_pdus = 1; + UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); + + LOG_D(MAC, "Scheduling UE specific PUSCH\n"); + //UL_tti_req = &nr_mac->UL_tti_req[CC_id]; + /* + // original configuration + rel15_ul->rnti = 0x1234; + rel15_ul->ulsch_pdu_rel15.start_rb = 30; + rel15_ul->ulsch_pdu_rel15.number_rbs = 50; + rel15_ul->ulsch_pdu_rel15.start_symbol = 2; + rel15_ul->ulsch_pdu_rel15.number_symbols = 12; + rel15_ul->ulsch_pdu_rel15.nb_re_dmrs = 6; + rel15_ul->ulsch_pdu_rel15.length_dmrs = 1; + rel15_ul->ulsch_pdu_rel15.Qm = 2; + rel15_ul->ulsch_pdu_rel15.mcs = 9; + rel15_ul->ulsch_pdu_rel15.rv = 0; + rel15_ul->ulsch_pdu_rel15.n_layers = 1; + */ + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + pusch_pdu->rnti = rnti; + pusch_pdu->handle = 0; //not yet used + + pusch_pdu->bwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pusch_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing; + pusch_pdu->cyclic_prefix = 0; + //pusch information always include + //this informantion seems to be redundant. with hthe mcs_index and the modulation table, the mod_order and target_code_rate can be determined. + pusch_pdu->mcs_index = 9; + pusch_pdu->mcs_table = 0; //0: notqam256 [TS38.214, table 5.1.3.1-1] - corresponds to nr_target_code_rate_table1 in PHY + pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; + pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; + pusch_pdu->transform_precoding = 0; + pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.; + pusch_pdu->nrOfLayers = 1; + //DMRS + pusch_pdu->ul_dmrs_symb_pos = 1<<2; //for now the gnb assumes dmrs in the first symbol of the scheduled pusch resource + pusch_pdu->dmrs_config_type = 0; //dmrs-type 1 (the one with a single DMRS symbol in the beginning) + pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. + pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. + //pusch_pdu->num_dmrs_cdm_grps_no_data; + //pusch_pdu->dmrs_ports; //DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used + //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] + pusch_pdu->resource_alloc = 1; //type 1 + //pusch_pdu->rb_bitmap;// for ressource alloc type 0 + pusch_pdu->rb_start = 0; + pusch_pdu->rb_size = 50; + pusch_pdu->vrb_to_prb_mapping = 0; + pusch_pdu->frequency_hopping = 0; + //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] + pusch_pdu->uplink_frequency_shift_7p5khz = 0; + //Resource Allocation in time domain + pusch_pdu->start_symbol_index = 2; + pusch_pdu->nr_of_symbols = 12; + //Optional Data only included if indicated in pduBitmap + pusch_pdu->pusch_data.rv_index = 0; + pusch_pdu->pusch_data.harq_process_id = 0; + pusch_pdu->pusch_data.new_data_indicator = 0; + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, + pusch_pdu->target_code_rate, + pusch_pdu->rb_size, + pusch_pdu->nr_of_symbols, + 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + 0, //nb_rb_oh + pusch_pdu->nrOfLayers)>>3; + pusch_pdu->pusch_data.num_cb = 0; //CBG not supported + //pusch_pdu->pusch_data.cb_present_and_position; + //pusch_pdu->pusch_uci; + //pusch_pdu->pusch_ptrs; + //pusch_pdu->dfts_ofdm; + //beamforming + //pusch_pdu->beamforming; //not used for now + + + ul_dci_request_pdu = &UL_dci_req->ul_dci_pdu_list[UL_dci_req->numPdus]; + memset((void*)ul_dci_request_pdu,0,sizeof(nfapi_nr_ul_dci_request_pdus_t)); + ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15; + + int dci_formats[2]; + int rnti_types[2]; + + int CCEIndex = allocate_nr_CCEs(nr_mac, + 1, // bwp_id + 0, // coreset_id + 4, // aggregation, + 1, // search_space, 0 common, 1 ue-specific + UE_id, + 0); // m + + dci_formats[0] = NR_UL_DCI_FORMAT_0_0; + rnti_types[0] = NR_RNTI_C; + LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); + nr_configure_pdcch(pdcch_pdu_rel15, + 1, // ue-specific, + scc, + bwp); + + + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + + AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); + pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; + + LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]); + + config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); + + pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index d95819d1e7..9376855882 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -39,6 +39,7 @@ #include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" +#include "common/utils/nr/nr_common.h" #include "UTIL/OPT/opt.h" #include "OCG.h" #include "OCG_extern.h" @@ -53,10 +54,16 @@ #include "intertask_interface.h" #include "T.h" +#include "NR_PDCCH-ConfigCommon.h" +#include "NR_ControlResourceSet.h" +#include "NR_SearchSpace.h" + +#include "nfapi_nr_interface.h" #define ENABLE_MAC_PAYLOAD_DEBUG #define DEBUG_gNB_SCHEDULER 1 + #include "common/ran_context.h" extern RAN_CONTEXT_t RC; @@ -122,29 +129,88 @@ static inline uint8_t get_max_cces(uint8_t scs) { return (nr_max_number_of_cces_per_slot[scs]); } -int is_nr_UL_slot(NR_COMMON_channels_t * ccP, int slot){ +int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, + int bwp_id, + int coreset_id, + int aggregation, + int search_space, // 0 common, 1 ue-specific + int UE_id, + int m + ) { + // uncomment these when we allocate for common search space + // NR_COMMON_channels_t *cc = nr_mac->common_channels; + // NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + + NR_UE_list_t *UE_list = &nr_mac->UE_list; + + NR_BWP_Downlink_t *bwp; + NR_CellGroupConfig_t *secondaryCellGroup; + + NR_ControlResourceSet_t *coreset; + + if (search_space == 1) { + AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id); + secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[coreset_id]; + } + else { + AssertFatal(1==0,"Add code for common search space\n"); + } + + int *cce_list = nr_mac->cce_list[bwp_id][coreset_id]; + + + int n_rb=0; + for (int i=0;i<6;i++) + for (int j=0;j<8;j++) { + n_rb+=((coreset->frequencyDomainResources.buf[i]>>j)&1); + } + n_rb*=6; + + uint16_t N_reg = n_rb * coreset->duration; + uint16_t Y=0, N_cce, M_s_max, n_CI=0; + uint16_t n_RNTI = search_space == 1 ? UE_list->rnti[UE_id]:0; + uint32_t A[3]={39827,39829,39839}; + + N_cce = N_reg / NR_NB_REG_PER_CCE; + + M_s_max = (aggregation==4)?4:(aggregation==8)?2:1; + + if (search_space == 1) { + Y = (A[0]*n_RNTI)%65537; // Candidate 0, antenna port 0 + } + int first_cce = aggregation * (( Y + (m*N_cce)/(aggregation*M_s_max) + n_CI ) % CEILIDIV(N_cce,aggregation)); + + for (int i=0;i>4)&0xf; - uint8_t mu = scs_common; - uint8_t O_scale=0, M_scale=0; // used to decide if the values of O and M need to be divided by 2 + // uint8_t O, M; + // uint8_t ss_idx = rmsi_pdcch_config&0xf; + // uint8_t cset_idx = (rmsi_pdcch_config>>4)&0xf; + // uint8_t mu = scs_common; + // uint8_t O_scale=0, M_scale=0; // used to decide if the values of O and M need to be divided by 2 + AssertFatal(1==0,"todo\n"); + /* /// Coreset params switch(scs_common) { @@ -153,18 +219,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz15: AssertFatal(cset_idx<15,"Coreset index %d reserved for scs kHz15/kHz15\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 6)? 24 : (cset_idx < 12)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_15[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 6)? 24 : (cset_idx < 12)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_15[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; break; case kHz30: AssertFatal(cset_idx<14,"Coreset index %d reserved for scs kHz15/kHz30\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 8)? 24 : 48; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_30[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 8)? 24 : 48; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_30[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; break; default: @@ -179,17 +245,17 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz15: AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 10)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 10)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; break; case kHz30: - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 6)? 24 : 48; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 6)? 24 : 48; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; break; default: @@ -201,18 +267,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz15: AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 3)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 3)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; break; case kHz30: AssertFatal(cset_idx<10,"Coreset index %d reserved for scs kHz30/kHz30\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 4)? 24 : 48; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 4)? 24 : 48; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; break; default: @@ -225,19 +291,19 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz60: AssertFatal(cset_idx<12,"Coreset index %d reserved for scs kHz120/kHz60\n", cset_idx); - pdcch_params->mux_pattern = (cset_idx < 8)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; - pdcch_params->n_rb = (cset_idx < 6)? 48 : (cset_idx < 8)? 96 : (cset_idx < 10)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_120_60[cset_idx]; - pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx]>0)?nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx] : + pdcch_pdu->mux_pattern = (cset_idx < 8)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; + pdcch_pdu->n_rb = (cset_idx < 6)? 48 : (cset_idx < 8)? 96 : (cset_idx < 10)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_120_60[cset_idx]; + pdcch_pdu->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx]>0)?nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx] : (k_ssb == 0)? -41 : -42; break; case kHz120: AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz120/kHz120\n", cset_idx); - pdcch_params->mux_pattern = (cset_idx < 4)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3; - pdcch_params->n_rb = (cset_idx < 2)? 24 : (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; - pdcch_params->n_symb = (cset_idx == 2)? 1 : 2; - pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx] : + pdcch_pdu->mux_pattern = (cset_idx < 4)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3; + pdcch_pdu->n_rb = (cset_idx < 2)? 24 : (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; + pdcch_pdu->n_symb = (cset_idx == 2)? 1 : 2; + pdcch_pdu->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx] : (k_ssb == 0)? -20 : -21; break; @@ -250,18 +316,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz60: AssertFatal(cset_idx<4,"Coreset index %d reserved for scs kHz240/kHz60\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = 96; - pdcch_params->n_symb = (cset_idx < 2)? 1 : 2; - pdcch_params->rb_offset = (cset_idx&1)? 16 : 0; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = 96; + pdcch_pdu->n_symb = (cset_idx < 2)? 1 : 2; + pdcch_pdu->rb_offset = (cset_idx&1)? 16 : 0; break; case kHz120: AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz240/kHz120\n", cset_idx); - pdcch_params->mux_pattern = (cset_idx < 4)? NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; - pdcch_params->n_rb = (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; - pdcch_params->n_symb = ((cset_idx==2)||(cset_idx==3))? 2 : 1; - pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx] : + pdcch_pdu->mux_pattern = (cset_idx < 4)? NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; + pdcch_pdu->n_rb = (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; + pdcch_pdu->n_symb = ((cset_idx==2)||(cset_idx==3))? 2 : 1; + pdcch_pdu->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx] : (k_ssb == 0)? -41 : -42; break; @@ -276,29 +342,29 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p } /// Search space params - switch(pdcch_params->mux_pattern) { + switch(pdcch_pdu->mux_pattern) { case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1: if (freq_range == nr_FR1) { O = nr_ss_param_O_type_0_mux1_FR1[ss_idx]; - pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx]; + pdcch_pdu->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx]; M = nr_ss_param_M_type_0_mux1_FR1[ss_idx]; M_scale = nr_ss_scale_M_mux1_FR1[ss_idx]; - pdcch_params->first_symbol = (ss_idx < 8)? ( (ssb_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8]; + pdcch_pdu->first_symbol = (ss_idx < 8)? ( (ssb_idx&1)? pdcch_pdu->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8]; } else { AssertFatal(ss_idx<14 ,"Invalid search space index for multiplexing type 1 and FR2 %d\n", ss_idx); O = nr_ss_param_O_type_0_mux1_FR2[ss_idx]; O_scale = nr_ss_scale_O_mux1_FR2[ss_idx]; - pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx]; + pdcch_pdu->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx]; M = nr_ss_param_M_type_0_mux1_FR2[ss_idx]; M_scale = nr_ss_scale_M_mux1_FR2[ss_idx]; - pdcch_params->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0; + pdcch_pdu->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0; } - pdcch_params->nb_slots = 2; - pdcch_params->sfn_mod2 = (CEILIDIV( (((O<>O_scale) + ((ssb_idx*M)>>M_scale)), nb_slots_per_frame ) & 1)? 1 : 0; - pdcch_params->first_slot = (((O<>O_scale) + ((ssb_idx*M)>>M_scale)) % nb_slots_per_frame; + pdcch_pdu->nb_slots = 2; + pdcch_pdu->sfn_mod2 = (CEILIDIV( (((O<>O_scale) + ((ssb_idx*M)>>M_scale)), nb_slots_per_frame ) & 1)? 1 : 0; + pdcch_pdu->first_slot = (((O<>O_scale) + ((ssb_idx*M)>>M_scale)) % nb_slots_per_frame; break; @@ -307,14 +373,14 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p "Invalid scs_common/pdcch_scs combination %d/%d for Mux type 2\n", scs_common, pdcch_scs ); AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs); - pdcch_params->nb_slots = 1; + pdcch_pdu->nb_slots = 1; if ((scs_common==kHz120)&&(pdcch_scs==kHz60)) { - pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_60_mux2[ssb_idx&3]; - // Missing in pdcch_params sfn_C and n_C here and in else case + pdcch_pdu->first_symbol = nr_ss_first_symb_idx_scs_120_60_mux2[ssb_idx&3]; + // Missing in pdcch_pdu sfn_C and n_C here and in else case } else { - pdcch_params->first_symbol = ((ssb_idx&7)==4)?12 : ((ssb_idx&7)==4)?13 : nr_ss_first_symb_idx_scs_240_120_set1_mux2[ssb_idx&7]; //??? + pdcch_pdu->first_symbol = ((ssb_idx&7)==4)?12 : ((ssb_idx&7)==4)?13 : nr_ss_first_symb_idx_scs_240_120_set1_mux2[ssb_idx&7]; //??? } break; @@ -324,159 +390,919 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p "Invalid scs_common/pdcch_scs combination %d/%d for Mux type 3\n", scs_common, pdcch_scs ); AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs); - pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_120_mux3[ssb_idx&3]; + pdcch_pdu->first_symbol = nr_ss_first_symb_idx_scs_120_120_mux3[ssb_idx&3]; break; default: - AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_params->mux_pattern); + AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_pdu->mux_pattern); } - pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1; - pdcch_params->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED; - pdcch_params->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE; - pdcch_params->reg_bundle_size = 6; - pdcch_params->interleaver_size = 2; + pdcch_pdu->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1; + pdcch_pdu->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED; + pdcch_pdu->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE; + pdcch_pdu->reg_bundle_size = 6; + pdcch_pdu->interleaver_size = 2; // set initial banwidth part to full bandwidth - pdcch_params->n_RB_BWP = N_RB; + pdcch_pdu->n_RB_BWP = N_RB; + */ } -void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, - nfapi_nr_coreset_t* coreset, - nfapi_nr_search_space_t* search_space, - nfapi_nr_config_request_t cfg, - uint16_t N_RB) { -/// coreset - - //ControlResourceSetId - pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; +void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, + int ss_type, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Downlink_t *bwp){ - //frequencyDomainResources - uint8_t count=0, start=0, start_set=0; - uint64_t bitmap = coreset->frequency_domain_resources; - for (int i=0; i<45; i++) - if ((bitmap>>(44-i))&1) { - count++; - if (!start_set) { + if (bwp) { // This is not the InitialBWP + /// coreset + + //ControlResourceSetId + // pdcch_pdu->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL, + "controlResourceSetToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0, + "controlResourceSetToAddModList is empty\n"); + NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; + + + pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; + pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix; + + pdcch_pdu->DurationSymbols = coreset0->duration; + + //frequencyDomainResources + /* uint8_t count=0, start=0, start_set=0; + // find coreset descriptor + + uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)| + (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)| + (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)| + (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)| + (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)| + (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3); + + for (int i=0; i<45; i++) + if ((bitmap>>(44-i))&1) { + count++; + if (!start_set) { start = i; start_set = 1; + } + } + pdcch_pdu->rb_offset = 6*start; + pdcch_pdu->n_rb = 6*count; + */ + for (int i=0;i<6;i++) + pdcch_pdu->FreqDomainResource[i] = coreset0->frequencyDomainResources.buf[i]; + //duration + + + //cce-REG-MappingType + pdcch_pdu->CceRegMappingType = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? + NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; + if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { + pdcch_pdu->RegBundleSize = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize); + pdcch_pdu->InterleaverSize = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize); + AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n"); + pdcch_pdu->ShiftIndex = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; + } + else { + pdcch_pdu->RegBundleSize = 0; + pdcch_pdu->InterleaverSize = 0; + pdcch_pdu->ShiftIndex = 0; + } + + pdcch_pdu->CoreSetType = 1; + + //precoderGranularity + pdcch_pdu->precoderGranularity = coreset0->precoderGranularity; + + //TCI states + // + /* + //TCI present + if (coreset0->tci_PresentInDCI != NULL) { + AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); + AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); + for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { + + } + */ + + for (int i=0;inumDlDci;i++) { + //pdcch-DMRS-ScramblingID + AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); + pdcch_pdu->ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; + } + + /// SearchSpace + + // first symbol + //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); + int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + NR_SearchSpace_t *ss; + int found=0; + int target_ss = NR_SearchSpace__searchSpaceType_PR_common; + if (ss_type == 1) { + target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + } + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (*ss->controlResourceSetId == coreset0->controlResourceSetId && + ss->searchSpaceType->present == target_ss) { + found=1; + break; } } - pdcch_params->rb_offset = 6*start; - pdcch_params->n_rb = 6*count; - - //duration - pdcch_params->n_symb = coreset->duration; - - //cce-REG-MappingType - pdcch_params->cr_mapping_type = coreset->cce_reg_mapping_type; - if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - pdcch_params->reg_bundle_size = coreset->reg_bundle_size; - pdcch_params->interleaver_size = coreset->interleaver_size; - } - else { - pdcch_params->reg_bundle_size = 0; - pdcch_params->interleaver_size = 0; + AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); + + // for SPS=14 8 MSBs in positions 13 downto 6, + uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | + (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + + for (int i=0; i>(sps-1-i))&1) { + pdcch_pdu->StartSymbolIndex=i; + break; + } } - //shift index - pdcch_params->shift_index = coreset->shift_index; - - //precoderGranularity - pdcch_params->precoder_granularity = coreset->precoder_granularity; - - //TCI states - // PDCCH params does not yet include information about TCI and QCL (needed for DCI 1.1 and 0.1) - - //pdcch-DMRS-ScramblingID - pdcch_params->scrambling_id = coreset->dmrs_scrambling_id; - - -/// SearchSpace - - // first symbol - //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); - int sps = get_symbolsperslot(&cfg); - - for (int i=0; imonitoring_symbols_in_slot>>(sps-1-i))&1) { - pdcch_params->first_symbol=i; - break; - } - - //searchSpaceType - pdcch_params->search_space_type = search_space->search_space_type; - - pdcch_params->n_RB_BWP = N_RB; + else { // this is for InitialBWP + AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n"); + } } -int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, - nfapi_nr_coreset_t coreset, - uint16_t frame, - uint16_t slot, - nfapi_nr_config_request_t cfg) { - AssertFatal(search_space.coreset_id==coreset.coreset_id, "Invalid association of coreset(%d) and search space(%d)\n", - search_space.search_space_id, coreset.coreset_id); - uint8_t is_dci_opportunity=0; - uint16_t Ks=search_space.slot_monitoring_periodicity; - uint16_t Os=search_space.slot_monitoring_offset; - uint8_t Ts=search_space.duration; +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, + int *rnti_types + ) { + + uint16_t N_RB = pdcch_pdu_rel15->BWPSize; + uint8_t fsize=0, pos=0; - if (((frame*get_spf(&cfg) + slot - Os)%Ks)numDlDci;d++) { + + uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; + AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); + + int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; + + /// Payload generation + switch(dci_formats[d]) { + case NR_DL_DCI_FORMAT_1_0: + switch(rnti_types[d]) { + case NR_RNTI_RA: + // Freq domain assignment + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos=fsize; + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); + // Time domain assignment + pos+=4; + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); + LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); + // VRB to PRB mapping + + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos); + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); + // MCS + pos+=5; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); + // TB scaling + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); + LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); + break; + + case NR_RNTI_C: + + // indicating a DL DCI format 1bit + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); + + // Freq domain assignment (275rb >> fsize = 16) + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos+=fsize; + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu); + + uint16_t is_ra = 1; + for (int i=0; ifrequency_domain_assignment>>i)&1)) { + is_ra = 0; + break; + } + if (is_ra) //fsize are all 1 38.212 p86 + { + // ra_preamble_index 6 bits + pos+=6; + *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index&0x3f)<<(dci_size-pos)); + + // UL/SUL indicator 1 bit + pos++; + *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos); + + // SS/PBCH index 6 bits + pos+=6; + *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index&0x3f)<<(dci_size-pos)); + + // prach_mask_index 4 bits + pos+=4; + *dci_pdu |= ((dci_pdu_rel15->prach_mask_index&0xf)<<(dci_size-pos)); + + } //end if + + else { + + // Time domain assignment 4bit + + pos+=4; + *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu); + + // VRB to PRB mapping 1bit + pos++; + *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); + + // MCS 5bit //bit over 32, so dci_pdu ++ + pos+=5; + *dci_pdu |= (dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu); + + // New data indicator 1bit + pos++; + *dci_pdu |= (dci_pdu_rel15->ndi&1)<<(dci_size-pos); + LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu); + + // Redundancy version 2bit + pos+=2; + *dci_pdu |= (dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu); + + // HARQ process number 4bit + pos+=4; + *dci_pdu |= ((dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos)); + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); + + // Downlink assignment index 2bit + pos+=2; + *dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos)); + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); + + // TPC command for scheduled PUCCH 2bit + pos+=2; + *dci_pdu |= ((dci_pdu_rel15->tpc&3)<<(dci_size-pos)); + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); + + // PUCCH resource indicator 3bit + pos+=3; + *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos)); + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); + + // PDSCH-to-HARQ_feedback timing indicator 3bit + pos+=3; + *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos)); + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu); + + } //end else + break; + + case NR_RNTI_P: + + // Short Messages Indicator – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++); + // Short Messages – 8 bits + for (int i=0; i<8; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + + // TB scaling 2 bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++); + + + break; + + case NR_RNTI_SI: + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + + break; + + case NR_RNTI_TC: + // indicating a DL DCI format 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // Downlink assignment index – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUCCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + + + // LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", + // dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]); + + + // PDSCH-to-HARQ_feedback timing indicator – 3 bits + for (int i=0; i<3; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++); + + break; + } + break; + + case NR_UL_DCI_FORMAT_0_0: + switch(rnti_types[d]) + { + case NR_RNTI_C: + // indicating a DL DCI format 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // Frequency hopping flag – 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + + // Padding bits + for(int a = pos;a<32;a++) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); + + // UL/SUL indicator – 1 bit + /* commented for now (RK): need to get this from BWP descriptor + if (cfg->pucch_config.pucch_GroupHopping.value) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + */ + break; + + case NFAPI_NR_RNTI_TC: + + // indicating a DL DCI format 1bit + *dci_pdu |= (dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // Frequency hopping flag – 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + + // Padding bits + for(int a = pos;a<32;a++) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); + + // UL/SUL indicator – 1 bit + /* + commented for now (RK): need to get this information from BWP descriptor + if (cfg->pucch_config.pucch_GroupHopping.value) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + */ + break; + + } + break; + } + } +} + + + /* + int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, + nfapi_nr_coreset_t coreset, + uint16_t frame, + uint16_t slot, + nfapi_nr_config_request_scf_t cfg) { + + AssertFatal(search_space.coreset_id==coreset.coreset_id, "Invalid association of coreset(%d) and search space(%d)\n", + search_space.search_space_id, coreset.coreset_id); + + uint8_t is_dci_opportunity=0; + uint16_t Ks=search_space.slot_monitoring_periodicity; + uint16_t Os=search_space.slot_monitoring_offset; + uint8_t Ts=search_space.duration; + + if (((frame*get_spf(&cfg) + slot - Os)%Ks)rf_config.dl_subcarrierspacing.value); -} - - -int get_ulscs(nfapi_nr_config_request_t *cfg) { - - return(cfg->rf_config.ul_subcarrierspacing.value); -} - -int get_spf(nfapi_nr_config_request_t *cfg) { - - int mu = cfg->rf_config.dl_subcarrierspacing.value; + int mu = cfg->ssb_config.scs_common.value; AssertFatal(mu>=0&&mu<4,"Illegal scs %d\n",mu); return(10 * (1<subframe_config.dl_cyclic_prefix_type.value==NFAPI_CP_EXTENDED)?12:14); +int extract_startSymbol(int startSymbolAndLength) { + int tmp = startSymbolAndLength/14; + int tmp2 = startSymbolAndLength%14; + if (tmp > 0 && tmp < (14-tmp2)) return(tmp2); + else return(13-tmp2); } -int find_nrUE_id(module_id_t mod_idP, rnti_t rntiP) { - +int extract_length(int startSymbolAndLength) { + int tmp = startSymbolAndLength/14; + int tmp2 = startSymbolAndLength%14; + + if (tmp > 0 && tmp < (14-tmp2)) return(tmp); + else return(15-tmp2); +} + +/* + * Dump the UL or DL UE_list into LOG_T(MAC) + */ +void +dump_nr_ue_list(NR_UE_list_t *listP, + int ul_flag) +//------------------------------------------------------------------------------ +{ + if (ul_flag == 0) { + for (int j = listP->head; j >= 0; j = listP->next[j]) { + LOG_T(MAC, "DL list node %d => %d\n", + j, + listP->next[j]); + } + } else { + for (int j = listP->head_ul; j >= 0; j = listP->next_ul[j]) { + LOG_T(MAC, "UL list node %d => %d\n", + j, + listP->next_ul[j]); + } + } + + return; +} + +int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP) +//------------------------------------------------------------------------------ +{ int UE_id; - UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; + NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; for (UE_id = 0; UE_id < MAX_MOBILES_PER_GNB; UE_id++) { if (UE_list->active[UE_id] == TRUE) { - if (UE_list->UE_template[nrUE_PCCID(mod_idP, UE_id)][UE_id].rnti == rntiP) { + if (UE_list->rnti[UE_id] == rntiP) { return UE_id; } } } + return -1; } -int nrUE_PCCID(module_id_t mod_idP, int ue_idP) { - return (RC.nrmac[mod_idP]->UE_list.pCC_id[ue_idP]); +int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ + + int UE_id; + int i; + NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; + LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n", + mod_idP, + rntiP, + UE_list->avail, + UE_list->num_UEs); + dump_nr_ue_list(UE_list, 0); + + for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { + if (UE_list->active[i] == TRUE) + continue; + + UE_id = i; + UE_list->num_UEs++; + UE_list->active[UE_id] = TRUE; + UE_list->rnti[UE_id] = rntiP; + memset((void *) &UE_list->UE_sched_ctrl[UE_id], + 0, + sizeof(NR_UE_sched_ctrl_t)); + LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n", + mod_idP, + UE_id, + rntiP); + dump_nr_ue_list(UE_list, + 0); + return (UE_id); + } + + // printf("MAC: cannot add new UE for rnti %x\n", rntiP); + LOG_E(MAC, "error in add_new_ue(), could not find space in UE_list, Dumping UE list\n"); + dump_nr_ue_list(UE_list, + 0); + return -1; } + +/*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg, + nfapi_nr_coreset_t *coreset, + nfapi_nr_search_space_t *search_space) { + + nfapi_nr_coreset_t *cs; + nfapi_nr_search_space_t *ss; + NR_ServingCellConfigCommon_t *scc=cg->spCellConfig->reconfigurationWithSync->spCellConfigCommon; + AssertFatal(cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", + cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + + NR_BWP_Downlink_t *bwp=cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]; + struct NR_PDCCH_Config__controlResourceSetToAddModList *coreset_list = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList; + AssertFatal(coreset_list->list.count>0, + "cs list has 0 elements\n"); + for (int i=0;ilist.count;i++) { + NR_ControlResourceSet_t *coreset_i=coreset_list->list.array[i]; + cs = coreset + coreset_i->controlResourceSetId; + + cs->coreset_id = coreset_i->controlResourceSetId; + AssertFatal(coreset_i->frequencyDomainResources.size <=8 && coreset_i->frequencyDomainResources.size>0, + "coreset_i->frequencyDomainResources.size=%d\n", + (int)coreset_i->frequencyDomainResources.size); + + for (int f=0;ffrequencyDomainResources.size;f++) + ((uint8_t*)&cs->frequency_domain_resources)[coreset_i->frequencyDomainResources.size-1-f]=coreset_i->frequencyDomainResources.buf[f]; + + cs->frequency_domain_resources>>=coreset_i->frequencyDomainResources.bits_unused; + + cs->duration = coreset_i->duration; + // Need to add information about TCI_StateIDs + + if (coreset_i->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved) + cs->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; + else { + cs->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED; + + if (coreset_i->cce_REG_MappingType.choice.interleaved->reg_BundleSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) + cs->reg_bundle_size = 6; + else cs->reg_bundle_size = 2+coreset_i->cce_REG_MappingType.choice.interleaved->reg_BundleSize; + + if (coreset_i->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) + cs->interleaver_size = 6; + else cs->interleaver_size = 2+coreset_i->cce_REG_MappingType.choice.interleaved->interleaverSize; + + if (coreset_i->cce_REG_MappingType.choice.interleaved->shiftIndex) + cs->shift_index = *coreset_i->cce_REG_MappingType.choice.interleaved->shiftIndex; + else cs->shift_index = 0; + } + + if (coreset_i->precoderGranularity == NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle) + cs->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE; + else cs->precoder_granularity = NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS; + if (coreset_i->tci_PresentInDCI == NULL) cs->tci_present_in_dci = 0; + else cs->tci_present_in_dci = 1; + + if (coreset_i->tci_PresentInDCI == NULL) cs->dmrs_scrambling_id = 0; + else cs->dmrs_scrambling_id = *coreset_i->tci_PresentInDCI; + } + + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + AssertFatal(commonSearchSpaceList->list.count>0, + "common SearchSpace list has 0 elements\n"); + // Common searchspace list + for (int i=0;ilist.count;i++) { + NR_SearchSpace_t *searchSpace_i=commonSearchSpaceList->list.array[i]; + ss=search_space + searchSpace_i->searchSpaceId; + if (searchSpace_i->controlResourceSetId) ss->coreset_id = *searchSpace_i->controlResourceSetId; + switch(searchSpace_i->monitoringSlotPeriodicityAndOffset->present) { + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL1; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL2; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl2; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL4; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl4; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL5; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl5; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL8; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl8; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL10; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl10; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL16; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl16; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL20; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl20; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL40; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl40; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL80; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl80; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL160; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl160; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL320; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl320; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL640; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl640; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL1280; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl1280; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL2560; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl2560; + break; + default: + AssertFatal(1==0,"Shouldn't get here\n"); + break; + } + if (searchSpace_i->duration) ss->duration = *searchSpace_i->duration; + else ss->duration = 1; + + + AssertFatal(searchSpace_i->monitoringSymbolsWithinSlot->size == 2, + "ss_i->monitoringSymbolsWithinSlot = %d != 2\n", + (int)searchSpace_i->monitoringSymbolsWithinSlot->size); + ((uint8_t*)&ss->monitoring_symbols_in_slot)[1] = searchSpace_i->monitoringSymbolsWithinSlot->buf[0]; + ((uint8_t*)&ss->monitoring_symbols_in_slot)[0] = searchSpace_i->monitoringSymbolsWithinSlot->buf[1]; + + AssertFatal(searchSpace_i->nrofCandidates!=NULL,"searchSpace_%d->nrofCandidates is null\n",(int)searchSpace_i->searchSpaceId); + if (searchSpace_i->nrofCandidates->aggregationLevel1 == NR_SearchSpace__nrofCandidates__aggregationLevel1_n8) + ss->number_of_candidates[0] = 8; + else ss->number_of_candidates[0] = searchSpace_i->nrofCandidates->aggregationLevel1; + if (searchSpace_i->nrofCandidates->aggregationLevel2 == NR_SearchSpace__nrofCandidates__aggregationLevel2_n8) + ss->number_of_candidates[1] = 8; + else ss->number_of_candidates[1] = searchSpace_i->nrofCandidates->aggregationLevel2; + if (searchSpace_i->nrofCandidates->aggregationLevel4 == NR_SearchSpace__nrofCandidates__aggregationLevel4_n8) + ss->number_of_candidates[2] = 8; + else ss->number_of_candidates[2] = searchSpace_i->nrofCandidates->aggregationLevel4; + if (searchSpace_i->nrofCandidates->aggregationLevel8 == NR_SearchSpace__nrofCandidates__aggregationLevel8_n8) + ss->number_of_candidates[3] = 8; + else ss->number_of_candidates[3] = searchSpace_i->nrofCandidates->aggregationLevel8; + if (searchSpace_i->nrofCandidates->aggregationLevel16 == NR_SearchSpace__nrofCandidates__aggregationLevel16_n8) + ss->number_of_candidates[4] = 8; + else ss->number_of_candidates[4] = searchSpace_i->nrofCandidates->aggregationLevel16; + + AssertFatal(searchSpace_i->searchSpaceType->present==NR_SearchSpace__searchSpaceType_PR_common, + "searchspace %d is not common\n",(int)searchSpace_i->searchSpaceId); + AssertFatal(searchSpace_i->searchSpaceType->choice.common!=NULL, + "searchspace %d common is null\n",(int)searchSpace_i->searchSpaceId); + ss->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_COMMON; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0) + ss->css_formats_0_0_and_1_0 = 1; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_0) { + ss->css_format_2_0 = 1; + // add aggregation info + } + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_1) + ss->css_format_2_1 = 1; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_2) + ss->css_format_2_2 = 1; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_3) + ss->css_format_2_3 = 1; + } + + struct NR_PDCCH_Config__searchSpacesToAddModList *dedicatedSearchSpaceList = bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList; + AssertFatal(dedicatedSearchSpaceList->list.count>0, + "Dedicated Search Space list has 0 elements\n"); + // Dedicated searchspace list + for (int i=0;ilist.count;i++) { + NR_SearchSpace_t *searchSpace_i=dedicatedSearchSpaceList->list.array[i]; + ss=search_space + searchSpace_i->searchSpaceId; + ss->search_space_id = searchSpace_i->searchSpaceId; + if (searchSpace_i->controlResourceSetId) ss->coreset_id = *searchSpace_i->controlResourceSetId; + switch(searchSpace_i->monitoringSlotPeriodicityAndOffset->present) { + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL1; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL2; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl2; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL4; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl4; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL5; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl5; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL8; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl8; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL10; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl10; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL16; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl16; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL20; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl20; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL40; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl40; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL80; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl80; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL160; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl160; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL320; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl320; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL640; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl640; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL1280; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl1280; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560: + ss->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL2560; + ss->slot_monitoring_offset = searchSpace_i->monitoringSlotPeriodicityAndOffset->choice.sl2560; + break; + default: + AssertFatal(1==0,"Shouldn't get here\n"); + break; + } + if (searchSpace_i->duration) ss->duration = *searchSpace_i->duration; + else ss->duration = 1; + + + AssertFatal(searchSpace_i->monitoringSymbolsWithinSlot->size == 2, + "ss_i->monitoringSymbolsWithinSlot = %d != 2\n", + (int)searchSpace_i->monitoringSymbolsWithinSlot->size); + ((uint8_t*)&ss->monitoring_symbols_in_slot)[1] = searchSpace_i->monitoringSymbolsWithinSlot->buf[0]; + ((uint8_t*)&ss->monitoring_symbols_in_slot)[0] = searchSpace_i->monitoringSymbolsWithinSlot->buf[1]; + + AssertFatal(searchSpace_i->nrofCandidates!=NULL,"searchSpace_%d->nrofCandidates is null\n",(int)searchSpace_i->searchSpaceId); + if (searchSpace_i->nrofCandidates->aggregationLevel1 == NR_SearchSpace__nrofCandidates__aggregationLevel1_n8) + ss->number_of_candidates[0] = 8; + else ss->number_of_candidates[0] = searchSpace_i->nrofCandidates->aggregationLevel1; + if (searchSpace_i->nrofCandidates->aggregationLevel2 == NR_SearchSpace__nrofCandidates__aggregationLevel2_n8) + ss->number_of_candidates[1] = 8; + else ss->number_of_candidates[1] = searchSpace_i->nrofCandidates->aggregationLevel2; + if (searchSpace_i->nrofCandidates->aggregationLevel4 == NR_SearchSpace__nrofCandidates__aggregationLevel4_n8) + ss->number_of_candidates[2] = 8; + else ss->number_of_candidates[2] = searchSpace_i->nrofCandidates->aggregationLevel4; + if (searchSpace_i->nrofCandidates->aggregationLevel8 == NR_SearchSpace__nrofCandidates__aggregationLevel8_n8) + ss->number_of_candidates[3] = 8; + else ss->number_of_candidates[3] = searchSpace_i->nrofCandidates->aggregationLevel8; + if (searchSpace_i->nrofCandidates->aggregationLevel16 == NR_SearchSpace__nrofCandidates__aggregationLevel16_n8) + ss->number_of_candidates[4] = 8; + else ss->number_of_candidates[4] = searchSpace_i->nrofCandidates->aggregationLevel16; + + if (searchSpace_i->searchSpaceType->present==NR_SearchSpace__searchSpaceType_PR_ue_Specific && searchSpace_i->searchSpaceType->choice.ue_Specific!=NULL) { + + ss->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC; + + ss->uss_dci_formats = searchSpace_i->searchSpaceType->choice.ue_Specific-> dci_Formats; + + } else if (searchSpace_i->searchSpaceType->present==NR_SearchSpace__searchSpaceType_PR_common && searchSpace_i->searchSpaceType->choice.common!=NULL) { + ss->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_COMMON; + + if (searchSpace_i->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0) + ss->css_formats_0_0_and_1_0 = 1; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_0) { + ss->css_format_2_0 = 1; + // add aggregation info + } + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_1) + ss->css_format_2_1 = 1; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_2) + ss->css_format_2_2 = 1; + if (searchSpace_i->searchSpaceType->choice.common->dci_Format2_3) + ss->css_format_2_3 = 1; + } + } +} +*/ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 95ae4a8e30..ade5200627 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -222,7 +222,10 @@ void nr_process_mac_pdu( pdu_ptr += ( mac_subheader_len + mac_ce_len + mac_sdu_len ); pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len ); - AssertFatal(pdu_len >= 0, "[MAC] nr_process_mac_pdu, residual mac pdu length < 0!\n"); + if (pdu_len < 0) { + LOG_E(MAC, "%s() residual mac pdu length < 0!\n", __func__); + return; + } } } @@ -241,20 +244,18 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, const uint8_t ul_cqi){ int current_rnti = 0, UE_id = -1, harq_pid = 0; gNB_MAC_INST *gNB_mac = NULL; - UE_list_t *UE_list = NULL; + NR_UE_list_t *UE_list = NULL; UE_sched_ctrl_t *UE_scheduling_control = NULL; current_rnti = rntiP; - UE_id = find_nrUE_id(gnb_mod_idP, current_rnti); + UE_id = find_nr_UE_id(gnb_mod_idP, current_rnti); gNB_mac = RC.nrmac[gnb_mod_idP]; UE_list = &gNB_mac->UE_list; - UE_id = 0; - if (UE_id != -1) { UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); - LOG_D(MAC, "[eNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu round %d from PHY (rnti %x, UE_id %d) ul_cqi %d\n", + LOG_D(MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu round %d from PHY (rnti %x, UE_id %d) ul_cqi %d\n", gnb_mod_idP, harq_pid, CC_idP, diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 744f1a2224..d55a188817 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -40,27 +40,18 @@ void set_cset_offset(uint16_t); void mac_top_init_gNB(void); void config_common(int Mod_idP, - int CC_idP, - int Nid_cell, - int nr_bandP, - uint64_t ssb_pattern, - uint16_t ssb_periodicity, - uint64_t dl_CarrierFreqP, - uint32_t dl_BandwidthP); + int pdsch_AntennaPorts, + NR_ServingCellConfigCommon_t *scc + ); int rrc_mac_config_req_gNB(module_id_t Mod_idP, - int CC_id, - int cellid, - int p_gNB, - int nr_bandP, - uint64_t ssb_pattern, - uint16_t ssb_periodicity, - uint64_t dl_CarrierFreqP, - int dl_BandwidthP, - NR_BCCH_BCH_Message_t *mib, - NR_ServingCellConfigCommon_t *servingcellconfigcommon); - -int is_nr_UL_slot(NR_COMMON_channels_t * ccP, int slotP); + int ssb_SubcarrierOffset, + int pdsch_AntennaPorts, + NR_ServingCellConfigCommon_t *scc, + int nsa_flag, + uint32_t rnti, + NR_CellGroupConfig_t *secondaryCellGroup + ); void clear_nr_nfapi_information(gNB_MAC_INST * gNB, int CC_idP, @@ -89,27 +80,33 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP); -int configure_fapi_dl_pdu(nfapi_nr_dl_config_request_body_t *dl_req, - nfapi_nr_config_request_t *cfg, - nfapi_nr_coreset_t* coreset, - nfapi_nr_search_space_t* search_space, - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config); +int configure_fapi_dl_pdu(int Mod_id, + int *CCEIndeces, + nfapi_nr_dl_tti_request_body_t *dl_req, + uint8_t *mcsIndex, + uint16_t *rbSize, + uint16_t *rbStart); -void configure_fapi_dl_Tx(nfapi_nr_dl_config_request_body_t *dl_req, - nfapi_tx_request_pdu_t *tx_req, +void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types); + +void configure_fapi_dl_Tx(module_id_t Mod_idP, + frame_t frameP, + sub_frame_t slotP, + nfapi_nr_dl_tti_request_body_t *dl_req, + nfapi_nr_pdu_t *tx_req, int tbs_bytes, int16_t pdu_index); void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, - nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config); + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_config); -void nr_schedule_uss_ulsch_phytest(nfapi_nr_ul_tti_request_t *UL_tti_req, +void nr_schedule_uss_ulsch_phytest(int Mod_idP, frame_t frameP, sub_frame_t slotP); -void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, +void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, nr_scs_e scs_common, nr_scs_e pdcch_scs, nr_frequency_range_e freq_range, @@ -120,41 +117,76 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p uint8_t n_ssb, uint16_t nb_slots_per_frame, uint16_t N_RB); - +/* int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, nfapi_nr_coreset_t coreset, uint16_t frame, uint16_t slot, - nfapi_nr_config_request_t cfg); + nfapi_nr_config_request_scf_t cfg); +*/ -void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, - nfapi_nr_coreset_t* coreset, - nfapi_nr_search_space_t* search_space, - nfapi_nr_config_request_t cfg, - uint16_t N_RB); +void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, + int ss_type, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Downlink_t *bwp); + +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, + int *rnti_types); + +int get_spf(nfapi_nr_config_request_scf_t *cfg); + +int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); + +void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); + +void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, + int x_overhead); +/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ +uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); +uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); + +/** \brief Computes Q based on I_MCS PDSCH and table_idx for uplink. Implements MCS Tables from 38.214. */ +uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx); +uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); + +int NRRIV2BW(int locationAndBandwidth,int N_RB); + +int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB); + +void dump_nr_ue_list(NR_UE_list_t *listP, int ul_flag); + +int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP); + +int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); + +int get_num_dmrs(uint16_t dmrs_mask ); + +uint16_t nr_dci_size(nr_dci_format_t format, + nr_rnti_type_t rnti_type, + uint16_t N_RB); + +int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, + int bwp_id, + int coreset_id, + int aggregation, + int search_space, // 0 common, 1 ue-specific + int UE_id, + int m + ); + +int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); +int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); int get_dlscs(nfapi_nr_config_request_t *cfg); int get_ulscs(nfapi_nr_config_request_t *cfg); -int get_spf(nfapi_nr_config_request_t *cfg); - -int to_absslot(nfapi_nr_config_request_t *cfg,int frame,int slot); - int get_symbolsperslot(nfapi_nr_config_request_t *cfg); -void get_band(uint32_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); - -uint64_t from_nrarfcn(int nr_bandP, uint32_t dl_nrarfcn); - -uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint32_t bw); - int32_t get_nr_uldl_offset(int nr_bandP); -int find_nrUE_id(module_id_t mod_idP, rnti_t rntiP); - -int nrUE_PCCID(module_id_t mod_idP, int ue_idP); - void config_nr_mib(int Mod_idP, int CC_idP, int p_gNBP, @@ -183,12 +215,12 @@ void nr_process_mac_pdu( @param ul_cqi Uplink CQI estimate after this pdu (SNR quantized to 8 bits, -64 ... 63.5 dB in .5dB steps) */ void nr_rx_sdu(const module_id_t gnb_mod_idP, - const int CC_idP, - const frame_t frameP, - const sub_frame_t subframeP, - const rnti_t rntiP, - uint8_t * sduP, - const uint16_t sdu_lenP, - const uint16_t timing_advance, const uint8_t ul_cqi); + const int CC_idP, + const frame_t frameP, + const sub_frame_t subframeP, + const rnti_t rntiP, + uint8_t * sduP, + const uint16_t sdu_lenP, + const uint16_t timing_advance, const uint8_t ul_cqi); #endif /*__LAYER2_NR_MAC_PROTO_H__*/ diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c index fcc3581b84..9e8415776b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/main.c +++ b/openair2/LAYER2/NR_MAC_gNB/main.c @@ -44,43 +44,12 @@ extern RAN_CONTEXT_t RC; -void set_cset_offset(uint16_t offset_bits) { - RC.nrmac[0]->coreset[0][1].frequency_domain_resources >>= offset_bits; -} - -void nr_init_coreset(nfapi_nr_coreset_t *coreset) { - - coreset->coreset_id = 1; - coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0 - coreset->duration = 2; - coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; - coreset->reg_bundle_size = 6; - coreset->interleaver_size = 2; - coreset->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE; - coreset->tci_present_in_dci = 0; - coreset->dmrs_scrambling_id = 0; -} - -void nr_init_search_space(nfapi_nr_search_space_t *search_space) -{ - search_space->search_space_id = 1; - search_space->coreset_id = 1; - search_space->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC; - search_space->duration = 5; - search_space->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL10; - search_space->slot_monitoring_offset = 1; - search_space->monitoring_symbols_in_slot = 0x3000; // 14 bits field - search_space->css_formats_0_0_and_1_0 = 1; - search_space->uss_dci_formats = 0; // enum to be defined-- formats 0.0 and 1.0 - for (int i=0; inumber_of_candidates[i] = 4; // TODO -} void mac_top_init_gNB(void) { - module_id_t i,j; + module_id_t i; int list_el; - UE_list_t *UE_list; + NR_UE_list_t *UE_list; gNB_MAC_INST *nrmac; LOG_I(MAC, "[MAIN] Init function start:nb_nr_macrlc_inst=%d\n",RC.nb_nr_macrlc_inst); @@ -88,58 +57,41 @@ void mac_top_init_gNB(void) if (RC.nb_nr_macrlc_inst > 0) { RC.nrmac = (gNB_MAC_INST **) malloc16(RC.nb_nr_macrlc_inst *sizeof(gNB_MAC_INST *)); - + AssertFatal(RC.nrmac != NULL,"can't ALLOCATE %zu Bytes for %d gNB_MAC_INST with size %zu \n", RC.nb_nr_macrlc_inst * sizeof(gNB_MAC_INST *), RC.nb_nr_macrlc_inst, sizeof(gNB_MAC_INST)); for (i = 0; i < RC.nb_nr_macrlc_inst; i++) { - RC.nrmac[i] = (gNB_MAC_INST *) malloc16(sizeof(gNB_MAC_INST)); - AssertFatal(RC.nrmac != NULL,"can't ALLOCATE %zu Bytes for %d gNB_MAC_INST with size %zu \n", - RC.nb_nr_macrlc_inst * sizeof(gNB_MAC_INST *), - RC.nb_nr_macrlc_inst, sizeof(gNB_MAC_INST)); + RC.nrmac[i] = (gNB_MAC_INST *) malloc16(sizeof(gNB_MAC_INST)); + + AssertFatal(RC.nrmac != NULL,"can't ALLOCATE %zu Bytes for %d gNB_MAC_INST with size %zu \n", + RC.nb_nr_macrlc_inst * sizeof(gNB_MAC_INST *), + RC.nb_nr_macrlc_inst, sizeof(gNB_MAC_INST)); + + LOG_D(MAC,"[MAIN] ALLOCATE %zu Bytes for %d gNB_MAC_INST @ %p\n",sizeof(gNB_MAC_INST), RC.nb_nr_macrlc_inst, RC.mac); + + bzero(RC.nrmac[i], sizeof(gNB_MAC_INST)); + + RC.nrmac[i]->Mod_id = i; - LOG_D(MAC,"[MAIN] ALLOCATE %zu Bytes for %d gNB_MAC_INST @ %p\n",sizeof(gNB_MAC_INST), RC.nb_nr_macrlc_inst, RC.mac); - - bzero(RC.nrmac[i], sizeof(gNB_MAC_INST)); - - RC.nrmac[i]->Mod_id = i; - - RC.nrmac[i]->tag = (NR_TAG_t*)malloc(sizeof(NR_TAG_t)); - memset((void*)RC.nrmac[i]->tag,0,sizeof(NR_TAG_t)); - - - for (j = 0; j < MAX_NUM_CCs; j++) { - RC.nrmac[i]->DL_req[j].dl_config_request_body.dl_config_pdu_list = RC.nrmac[i]->dl_config_pdu_list[j]; - - //FK changed UL_req to UL_tti_req, which does not contain a pointer to the pdu_list - //RC.nrmac[i]->UL_req[j].ul_config_request_body.ul_config_pdu_list = RC.nrmac[i]->ul_config_pdu_list[j]; - - //for (int k = 0; k < 10; k++) - // RC.nrmac[i]->UL_req_tmp[j][k].ul_config_request_body.ul_config_pdu_list =RC.nrmac[i]->ul_config_pdu_list_tmp[j][k]; + RC.nrmac[i]->tag = (NR_TAG_t*)malloc(sizeof(NR_TAG_t)); + memset((void*)RC.nrmac[i]->tag,0,sizeof(NR_TAG_t)); - RC.nrmac[i]->HI_DCI0_req[j].hi_dci0_request_body.hi_dci0_pdu_list = RC.nrmac[i]->hi_dci0_pdu_list[j]; - RC.nrmac[i]->TX_req[j].tx_request_body.tx_pdu_list = RC.nrmac[i]->tx_request_pdu[j]; - RC.nrmac[i]->ul_handle = 0; - - // Init PDCCH structures - nr_init_coreset(&RC.nrmac[i]->coreset[j][1]); - nr_init_search_space(&RC.nrmac[i]->search_space[j][1]); - } - + RC.nrmac[i]->ul_handle = 0; }//END for (i = 0; i < RC.nb_nr_macrlc_inst; i++) - AssertFatal(rlc_module_init(1) == 0,"Could not initialize RLC layer\n"); + AssertFatal(rlc_module_init(1) == 0,"Could not initialize RLC layer\n"); - // These should be out of here later - pdcp_layer_init(); + // These should be out of here later + pdcp_layer_init(); - if(IS_SOFTMODEM_NOS1) - nr_ip_over_LTE_DRB_preconfiguration(); + if(IS_SOFTMODEM_NOS1) + nr_ip_over_LTE_DRB_preconfiguration(); - rrc_init_nr_global_param(); + rrc_init_nr_global_param(); }else { RC.nrmac = NULL; @@ -150,25 +102,23 @@ void mac_top_init_gNB(void) nrmac = RC.nrmac[i]; nrmac->if_inst = NR_IF_Module_init(i); - + UE_list = &nrmac->UE_list; UE_list->num_UEs = 0; UE_list->head = -1; UE_list->head_ul = -1; UE_list->avail = 0; - for (list_el = 0; list_el < MAX_MOBILES_PER_ENB - 1; list_el++) { - UE_list->next[list_el] = list_el + 1; + for (list_el = 0; list_el < MAX_MOBILES_PER_GNB - 1; list_el++) { + UE_list->next[list_el] = list_el + 1; UE_list->next_ul[list_el] = list_el + 1; + UE_list->active[list_el] = FALSE; } UE_list->next[list_el] = -1; UE_list->next_ul[list_el] = -1; - /*memset(UE_list->DLSCH_pdu, 0, sizeof(UE_list->DLSCH_pdu)); - memset(UE_list->UE_template, 0, sizeof(UE_list->UE_template)); - memset(UE_list->eNB_UE_stats, 0, sizeof(UE_list->eNB_UE_stats)); - memset(UE_list->UE_sched_ctrl, 0, sizeof(UE_list->UE_sched_ctrl)); - memset(UE_list->active, 0, sizeof(UE_list->active));*/ + UE_list->active[list_el] = FALSE; } + srand48(0); } diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 1f00203dcc..5bc320d5e2 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -47,7 +47,6 @@ #include "NR_ServingCellConfigCommon.h" #include "NR_MeasConfig.h" -#include "nfapi_nr_interface.h" #include "nfapi_nr_interface_scf.h" #include "NR_PHY_INTERFACE/NR_IF_Module.h" @@ -60,44 +59,71 @@ #include "PHY/TOOLS/time_meas.h" #include "targets/ARCH/COMMON/common_lib.h" +#include "nr_mac_common.h" + +#define MAX_NUM_BWP 2 +#define MAX_NUM_CORESET 2 +#define MAX_NUM_CCE 90 #include "NR_TAG.h" /*! \brief gNB common channels */ typedef struct { - int physCellId; - int p_gNB; - int Ncp; - int nr_band; - uint32_t dl_CarrierFreq; - NR_BCCH_BCH_Message_t *mib; - NR_TDD_UL_DL_ConfigCommon_t *tdd_Config; - NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; - long ul_Bandwidth; - /// Outgoing MIB PDU for PHY - MIB_PDU MIB_pdu; - /// Outgoing BCCH pdu for PHY - BCCH_PDU BCCH_pdu; - /// Outgoing BCCH DCI allocation - uint32_t BCCH_alloc_pdu; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing PCCH DCI allocation - uint32_t PCCH_alloc_pdu; - /// Outgoing PCCH pdu for PHY - PCCH_PDU PCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Template for RA computations - RA_t ra[NB_RA_PROC_MAX]; - /// VRB map for common channels - uint8_t vrb_map[100]; - /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; + int physCellId; + int p_gNB; + int Ncp; + int nr_band; + uint64_t dl_CarrierFreq; + NR_BCCH_BCH_Message_t *mib; + NR_ServingCellConfigCommon_t *ServingCellConfigCommon; + NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; + long ul_Bandwidth; + /// Outgoing MIB PDU for PHY + MIB_PDU MIB_pdu; + /// Outgoing BCCH pdu for PHY + BCCH_PDU BCCH_pdu; + /// Outgoing BCCH DCI allocation + uint32_t BCCH_alloc_pdu; + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + /// Outgoing PCCH DCI allocation + uint32_t PCCH_alloc_pdu; + /// Outgoing PCCH pdu for PHY + PCCH_PDU PCCH_pdu; + /// Outgoing RAR pdu for PHY + RAR_PDU RAR_pdu; + /// Template for RA computations + RA_t ra[NB_RA_PROC_MAX]; + /// VRB map for common channels + uint8_t vrb_map[100]; + /// VRB map for common channels and retransmissions by PHICH + uint8_t vrb_map_UL[100]; + /// number of subframe allocation pattern available for MBSFN sync area + uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; +/*! \brief scheduling control information set through an API (not used)*/ +typedef struct { + int dummy; +} NR_UE_sched_ctrl_t; + +/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ +typedef struct { + + DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; + /// scheduling control info + UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; + int next[MAX_MOBILES_PER_GNB]; + int head; + int next_ul[MAX_MOBILES_PER_GNB]; + int head_ul; + int avail; + int num_UEs; + boolean_t active[MAX_MOBILES_PER_GNB]; + rnti_t rnti[MAX_MOBILES_PER_GNB]; + NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; +} NR_UE_list_t; + /*! \brief top level eNB MAC structure */ typedef struct gNB_MAC_INST_s { /// Ethernet parameters for northbound midhaul interface @@ -124,28 +150,17 @@ typedef struct gNB_MAC_INST_s { uint16_t pdu_index[NFAPI_CC_MAX]; /// NFAPI Config Request Structure - nfapi_nr_config_request_t config[NFAPI_CC_MAX]; + nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; /// NFAPI DL Config Request Structure - nfapi_nr_dl_config_request_t DL_req[NFAPI_CC_MAX]; + nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; /// NFAPI UL TTI Request Structure (this is from the new SCF specs) nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; - /// Preallocated DL pdu list - nfapi_nr_dl_config_request_pdu_t dl_config_pdu_list[NFAPI_CC_MAX][MAX_NUM_DL_PDU]; - /// Preallocated HI_DCI0 pdu list - nfapi_hi_dci0_request_pdu_t hi_dci0_pdu_list[NFAPI_CC_MAX][MAX_NUM_HI_DCI0_PDU]; /// NFAPI HI/DCI0 Config Request Structure - nfapi_hi_dci0_request_t HI_DCI0_req[NFAPI_CC_MAX]; - /// Prealocated TX pdu list - nfapi_tx_request_pdu_t tx_request_pdu[NFAPI_CC_MAX][MAX_NUM_TX_REQUEST_PDU]; + nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; /// NFAPI DL PDU structure - nfapi_tx_request_t TX_req[NFAPI_CC_MAX]; - /// NFAPI coreset structure - nfapi_nr_coreset_t coreset[NFAPI_CC_MAX][NFAPI_NR_MAX_NB_CORESETS]; - /// NFAPI search space structure - nfapi_nr_search_space_t search_space[NFAPI_CC_MAX][NFAPI_NR_MAX_NB_SEARCH_SPACES]; + nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; - /// this is an LTE structure and needs to be urgenly updated - UE_list_t UE_list; + NR_UE_list_t UE_list; /// UL handle uint32_t ul_handle; @@ -171,6 +186,72 @@ typedef struct gNB_MAC_INST_s { time_stats_t rx_ulsch_sdu; // include rlc_data_ind /// processing time of eNB PCH scheduler time_stats_t schedule_pch; + /// CCE lists + int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; +typedef struct { + + +uint8_t format_indicator; //1 bit +uint16_t frequency_domain_assignment; //up to 16 bits +uint8_t time_domain_assignment; // 4 bits +uint8_t frequency_hopping_flag; //1 bit + +uint8_t ra_preamble_index; //6 bits +uint8_t ss_pbch_index; //6 bits +uint8_t prach_mask_index; //4 bits + +uint8_t vrb_to_prb_mapping; //0 or 1 bit +uint8_t mcs; //5 bits +uint8_t ndi; //1 bit +uint8_t rv; //2 bits +uint8_t harq_pid; //4 bits +uint8_t dai; //0, 2 or 4 bits +uint8_t dai1; //1 or 2 bits +uint8_t dai2; //0 or 2 bits +uint8_t tpc; //2 bits +uint8_t pucch_resource_indicator; //3 bits +uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + +uint8_t short_messages_indicator; //2 bits +uint8_t short_messages; //8 bits +uint8_t tb_scaling; //2 bits + +uint8_t carrier_indicator; //0 or 3 bits +uint8_t bwp_indicator; //0, 1 or 2 bits +uint8_t prb_bundling_size_indicator; //0 or 1 bits +uint8_t rate_matching_indicator; //0, 1 or 2 bits +uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits +uint8_t transmission_configuration_indication; //0 or 3 bits +uint8_t srs_request; //2 bits +uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits +uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit +uint8_t dmrs_sequence_initialization; //0 or 1 bit + +uint8_t srs_resource_indicator; +uint8_t precoding_information; +uint8_t csi_request; +uint8_t ptrs_dmrs_association; +uint8_t beta_offset_indicator; //0 or 2 bits + +uint8_t slot_format_indicator_count; +uint8_t *slot_format_indicators; + +uint8_t pre_emption_indication_count; +uint16_t *pre_emption_indications; //14 bit + +uint8_t block_number_count; +uint8_t *block_numbers; + +uint8_t ul_sul_indicator; //0 or 1 bit +uint8_t antenna_ports; + +uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits +uint16_t padding; + +} dci_pdu_rel15_t; + + + #endif /*__LAYER2_NR_MAC_GNB_H__ */ diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c index 254d741ae8..b0e6143de1 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c @@ -2299,14 +2299,14 @@ uint64_t pdcp_module_init( uint64_t pdcp_optmask ) { netlink_init_tun("ue",num_if); if (IS_SOFTMODEM_NOS1) nas_config(1, 1, 2, "ue"); - netlink_init_mbms_tun("uem",num_if); + netlink_init_mbms_tun("uem"); nas_config_mbms(1, 2, 2, "uem"); LOG_I(PDCP, "UE pdcp will use tun interface\n"); } else if(ENB_NAS_USE_TUN) { netlink_init_tun("enb",1); nas_config(1, 1, 1, "enb"); if(pdcp_optmask & ENB_NAS_USE_TUN_W_MBMS_BIT){ - netlink_init_mbms_tun("enm",1); + netlink_init_mbms_tun("enm"); nas_config_mbms(1, 2, 1, "enm"); LOG_I(PDCP, "ENB pdcp will use mbms tun interface\n"); } @@ -2318,7 +2318,7 @@ uint64_t pdcp_module_init( uint64_t pdcp_optmask ) { }else{ if(pdcp_optmask & ENB_NAS_USE_TUN_W_MBMS_BIT){ LOG_W(PDCP, "ENB pdcp will use tun interface for MBMS\n"); - netlink_init_mbms_tun("enm",1); + netlink_init_mbms_tun("enm"); nas_config_mbms_s1(1, 2, 1, "enm"); }else LOG_E(PDCP, "ENB pdcp will not use tun interface\n"); diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c index a441ff220e..d203408e55 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c @@ -77,7 +77,7 @@ extern struct iovec nas_iov_rx; extern int nas_sock_fd[MAX_MOBILES_PER_ENB]; -extern int nas_sock_mbms_fd[8]; +extern int nas_sock_mbms_fd; extern int mbms_rab_id; @@ -133,7 +133,7 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { } else if (UE_NAS_USE_TUN) { //ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); if(rb_id == mbms_rab_id){ - ret = write(nas_sock_mbms_fd[0], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); + ret = write(nas_sock_mbms_fd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); } else @@ -299,7 +299,7 @@ int pdcp_fifo_read_input_mbms_sdus_fromtun (const protocol_ctxt_t *const ctxt_p do { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PDCP_MBMS_FIFO_READ, 1 ); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PDCP_MBMS_FIFO_READ_BUFFER, 1 ); - len = read(UE_NAS_USE_TUN?nas_sock_mbms_fd[0]:nas_sock_mbms_fd[0], &nl_rx_buf, NL_MAX_PAYLOAD); + len = read(nas_sock_mbms_fd, &nl_rx_buf, NL_MAX_PAYLOAD); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PDCP_MBMS_FIFO_READ_BUFFER, 0 ); if (len<=0) continue; diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 3ca64f9648..91c75ac67f 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -51,106 +51,100 @@ extern int oai_nfapi_sr_indication(nfapi_sr_indication_t *ind); extern int oai_nfapi_rx_ind(nfapi_rx_indication_t *ind); extern uint8_t nfapi_mode; extern uint16_t sf_ahead; +extern uint16_t sl_ahead; void handle_nr_rach(NR_UL_IND_t *UL_info) { if (UL_info->rach_ind.rach_indication_body.number_of_preambles>0) { AssertFatal(UL_info->rach_ind.rach_indication_body.number_of_preambles==1,"More than 1 preamble not supported\n"); UL_info->rach_ind.rach_indication_body.number_of_preambles=0; LOG_D(MAC,"UL_info[Frame %d, Slot %d] Calling initiate_ra_proc RACH:SFN/SF:%d\n",UL_info->frame,UL_info->slot, NFAPI_SFNSF2DEC(UL_info->rach_ind.sfn_sf)); + /* initiate_ra_proc(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rach_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti,0 - ); + + UL_info->CC_id, + NFAPI_SFNSF2SFN(UL_info->rach_ind.sfn_sf), + NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti +#if (NR_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) || (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) +//#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + ,0 +#endif + + ); + */ } - if (UL_info->rach_ind_br.rach_indication_body.number_of_preambles>0) { - AssertFatal(UL_info->rach_ind_br.rach_indication_body.number_of_preambles<5,"More than 4 preambles not supported\n"); - - for (int i=0; irach_ind_br.rach_indication_body.number_of_preambles; i++) { - AssertFatal(UL_info->rach_ind_br.rach_indication_body.preamble_list[i].preamble_rel13.rach_resource_type>0, - "Got regular PRACH preamble, not BL/CE\n"); - LOG_D(MAC,"Frame %d, Slot %d Calling initiate_ra_proc (CE_level %d)\n",UL_info->frame,UL_info->slot, - UL_info->rach_ind_br.rach_indication_body.preamble_list[i].preamble_rel13.rach_resource_type-1); - initiate_ra_proc(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->rach_ind_br.rach_indication_body.preamble_list[i].preamble_rel8.preamble, - UL_info->rach_ind_br.rach_indication_body.preamble_list[i].preamble_rel8.timing_advance, - UL_info->rach_ind_br.rach_indication_body.preamble_list[i].preamble_rel8.rnti, - UL_info->rach_ind_br.rach_indication_body.preamble_list[i].preamble_rel13.rach_resource_type); - } - - UL_info->rach_ind_br.rach_indication_body.number_of_preambles=0; - } } void handle_nr_sr(NR_UL_IND_t *UL_info) { - if (nfapi_mode == 1) { // PNF - if (UL_info->sr_ind.sr_indication_body.number_of_srs>0) { - oai_nfapi_sr_indication(&UL_info->sr_ind); + + + if (nfapi_mode == 1) // PNF + { + if (UL_info->sr_ind.sr_indication_body.number_of_srs>0) + { + // oai_nfapi_sr_indication(&UL_info->sr_ind); } - } else { - for (int i=0; isr_ind.sr_indication_body.number_of_srs; i++) + } + else + { + + /* + for (int i=0;isr_ind.sr_indication_body.number_of_srs;i++) SR_indication(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi); + UL_info->CC_id, + UL_info->frame, + UL_info->slot, + UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti, + UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi);*/ + + + } UL_info->sr_ind.sr_indication_body.number_of_srs=0; } void handle_nr_cqi(NR_UL_IND_t *UL_info) { - if (nfapi_mode == 1) { - if (UL_info->cqi_ind.number_of_cqis>0) { - LOG_D(PHY,"UL_info->cqi_ind.number_of_cqis:%d\n", UL_info->cqi_ind.number_of_cqis); - nfapi_cqi_indication_t ind; - ind.header.message_id = NFAPI_RX_CQI_INDICATION; - ind.sfn_sf = UL_info->frame<<4 | UL_info->slot; - ind.cqi_indication_body = UL_info->cqi_ind; - oai_nfapi_cqi_indication(&ind); - UL_info->cqi_ind.number_of_cqis=0; - } - } else { - for (int i=0; icqi_ind.number_of_cqis; i++) - cqi_indication(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->cqi_ind.cqi_pdu_list[i].rx_ue_information.rnti, - &UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9, - UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu, - &UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information); + /* + for (int i=0;icqi_ind.number_of_cqis;i++) + cqi_indication(UL_info->module_id, + UL_info->CC_id, + UL_info->frame, + UL_info->slot, + UL_info->cqi_ind.cqi_pdu_list[i].rx_ue_information.rnti, + &UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9, + UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu, + &UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information); + */ UL_info->cqi_ind.number_of_cqis=0; - } + } void handle_nr_harq(NR_UL_IND_t *UL_info) { if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF //LOG_D(PHY, "UL_info->harq_ind.harq_indication_body.number_of_harqs:%d Send to VNF\n", UL_info->harq_ind.harq_indication_body.number_of_harqs); - int retval = oai_nfapi_harq_indication(&UL_info->harq_ind); + /* int retval = oai_nfapi_harq_indication(&UL_info->harq_ind); if (retval!=0) { LOG_E(PHY, "Failed to encode NFAPI HARQ_IND retval:%d\n", retval); } - + */ UL_info->harq_ind.harq_indication_body.number_of_harqs = 0; - } else { - for (int i=0; iharq_ind.harq_indication_body.number_of_harqs; i++) + } + else + { + /* + for (int i=0;iharq_ind.harq_indication_body.number_of_harqs;i++) harq_indication(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf), - &UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]); - + UL_info->CC_id, + NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf), + NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf), + &UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]); + */ UL_info->harq_ind.harq_indication_body.number_of_harqs=0; } } @@ -159,17 +153,18 @@ void handle_nr_ulsch(NR_UL_IND_t *UL_info) { if(nfapi_mode == 1) { if (UL_info->crc_ind.crc_indication_body.number_of_crcs>0) { //LOG_D(PHY,"UL_info->crc_ind.crc_indication_body.number_of_crcs:%d CRC_IND:SFN/SF:%d\n", UL_info->crc_ind.crc_indication_body.number_of_crcs, NFAPI_SFNSF2DEC(UL_info->crc_ind.sfn_sf)); - oai_nfapi_crc_indication(&UL_info->crc_ind); + // oai_nfapi_crc_indication(&UL_info->crc_ind); + UL_info->crc_ind.crc_indication_body.number_of_crcs = 0; } if (UL_info->rx_ind.rx_indication_body.number_of_pdus>0) { //LOG_D(PHY,"UL_info->rx_ind.number_of_pdus:%d RX_IND:SFN/SF:%d\n", UL_info->rx_ind.rx_indication_body.number_of_pdus, NFAPI_SFNSF2DEC(UL_info->rx_ind.sfn_sf)); - oai_nfapi_rx_ind(&UL_info->rx_ind); + // oai_nfapi_rx_ind(&UL_info->rx_ind); UL_info->rx_ind.rx_indication_body.number_of_pdus = 0; } } else { - // printf("UL_info->rx_ind.rx_indication_body.number_of_pdus %d UL_info->crc_ind.crc_indication_body.number_of_crcs %d\n", UL_info->rx_ind.rx_indication_body.number_of_pdus, UL_info->crc_ind.crc_indication_body.number_of_crcs); + if (UL_info->rx_ind.rx_indication_body.number_of_pdus>0 && UL_info->crc_ind.crc_indication_body.number_of_crcs>0) { for (int i=0; irx_ind.rx_indication_body.number_of_pdus; i++) { for (int j=0; jcrc_ind.crc_indication_body.number_of_crcs; j++) { @@ -182,27 +177,28 @@ void handle_nr_ulsch(NR_UL_IND_t *UL_info) { LOG_D(PHY, "UL_info->crc_ind.crc_indication_body.crc_pdu_list[%d].crc_indication_rel8.crc_flag:%d\n", j, UL_info->crc_ind.crc_indication_body.crc_pdu_list[j].crc_indication_rel8.crc_flag); if (UL_info->crc_ind.crc_indication_body.crc_pdu_list[j].crc_indication_rel8.crc_flag == 1) { // CRC error indication - LOG_I(MAC,"Frame %d, Slot %d Calling rx_sdu (CRC error) \n",UL_info->frame,UL_info->slot); + LOG_D(MAC,"Frame %d, Slot %d Calling rx_sdu (CRC error) \n",UL_info->frame,UL_info->slot); + nr_rx_sdu(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rx_ind.sfn_sf), //UL_info->frame, - NFAPI_SFNSF2SF(UL_info->rx_ind.sfn_sf), //UL_info->slot, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti, - (uint8_t *)NULL, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.ul_cqi); + UL_info->CC_id, + NFAPI_SFNSF2SFN(UL_info->rx_ind.sfn_sf), //UL_info->frame, + NFAPI_SFNSF2SF(UL_info->rx_ind.sfn_sf), //UL_info->slot, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti, + (uint8_t *)NULL, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.ul_cqi); } else { - LOG_D(MAC,"Frame %d, Slot %d Calling rx_sdu (CRC ok), received length: %d \n",UL_info->frame,UL_info->slot, UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length); + LOG_D(MAC,"Frame %d, Slot %d Calling rx_sdu (CRC ok) \n",UL_info->frame,UL_info->slot); nr_rx_sdu(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rx_ind.sfn_sf), //UL_info->frame, - NFAPI_SFNSF2SF(UL_info->rx_ind.sfn_sf), //UL_info->slot, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].data, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.ul_cqi); + UL_info->CC_id, + NFAPI_SFNSF2SFN(UL_info->rx_ind.sfn_sf), //UL_info->frame, + NFAPI_SFNSF2SF(UL_info->rx_ind.sfn_sf), //UL_info->slot, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].data, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance, + UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.ul_cqi); } //printf("rx_indication_rel8.timing_advance %d\n", UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance); break; @@ -259,35 +255,37 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { handle_nr_cqi(UL_info); handle_nr_harq(UL_info); // clear HI prior to handling ULSCH - mac->HI_DCI0_req[CC_id].hi_dci0_request_body.number_of_hi = 0; + mac->UL_dci_req[CC_id].numPdus = 0; handle_nr_ulsch(UL_info); if (nfapi_mode != 1) { if (ifi->CC_mask == ((1<frame+((UL_info->slot>(9-sf_ahead))?1:0)) % 1024, - (UL_info->slot+sf_ahead)%10); + (UL_info->frame+((UL_info->slot>(9-sl_ahead))?1:0)) % 1024, + (UL_info->slot+sl_ahead)%10); */ - nfapi_nr_config_request_t *cfg = &mac->config[CC_id]; + nfapi_nr_config_request_scf_t *cfg = &mac->config[CC_id]; int spf = get_spf(cfg); gNB_dlsch_ulsch_scheduler(module_id, UL_info->frame, UL_info->slot, - (UL_info->frame+((UL_info->slot>(spf-1-sf_ahead))?1:0)) % 1024, - (UL_info->slot+sf_ahead)%spf); + (UL_info->frame+((UL_info->slot>(spf-1-sl_ahead))?1:0)) % 1024, + (UL_info->slot+sl_ahead)%spf); ifi->CC_mask = 0; sched_info->module_id = module_id; sched_info->CC_id = CC_id; - sched_info->frame = (UL_info->frame + ((UL_info->slot>(spf-1-sf_ahead)) ? 1 : 0)) % 1024; - sched_info->slot = (UL_info->slot+sf_ahead)%spf; + sched_info->frame = (UL_info->frame + ((UL_info->slot>(spf-1-sl_ahead)) ? 1 : 0)) % 1024; + sched_info->slot = (UL_info->slot+sl_ahead)%spf; sched_info->DL_req = &mac->DL_req[CC_id]; - sched_info->HI_DCI0_req = &mac->HI_DCI0_req[CC_id]; + sched_info->UL_dci_req = &mac->UL_dci_req[CC_id]; - if ((mac->common_channels[CC_id].tdd_Config==NULL) || - (is_nr_UL_slot(&mac->common_channels[CC_id],(sched_info->slot+sf_ahead)%spf)>0)) + if ((mac->common_channels[CC_id].ServingCellConfigCommon->tdd_UL_DL_ConfigurationCommon==NULL) || + (is_nr_UL_slot(mac->common_channels[CC_id].ServingCellConfigCommon,UL_info->slot)>0)) { + //printf("NR_UL_indication: this is an UL slot. UL_info: frame %d, slot %d. UL_tti_req: frame %d, slot %d\n",UL_info->frame,UL_info->slot,mac->UL_tti_req[CC_id].SFN,mac->UL_tti_req[CC_id].Slot); sched_info->UL_tti_req = &mac->UL_tti_req[CC_id]; + } else sched_info->UL_tti_req = NULL; @@ -304,18 +302,24 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { ifi->NR_Schedule_response(sched_info); } - LOG_D(PHY,"NR_Schedule_response: SFN_SF:%d%d dl_pdus:%d\n",sched_info->frame,sched_info->slot,sched_info->DL_req->dl_config_request_body.number_pdu); + LOG_D(PHY,"NR_Schedule_response: SFN_SF:%d%d dl_pdus:%d\n", + sched_info->frame, + sched_info->slot, + sched_info->DL_req->dl_tti_request_body.nPDUs); } } } NR_IF_Module_t *NR_IF_Module_init(int Mod_id) { AssertFatal(Mod_id %d\n",Mod_id,MAX_IF_MODULES); - LOG_D(PHY,"Installing callbacks for IF_Module - UL_indication\n"); + LOG_I(PHY,"Installing callbacks for IF_Module - UL_indication\n"); if (if_inst[Mod_id]==NULL) { - if_inst[Mod_id] = (NR_IF_Module_t *)malloc(sizeof(NR_IF_Module_t)); - memset((void *)if_inst[Mod_id],0,sizeof(NR_IF_Module_t)); + if_inst[Mod_id] = (NR_IF_Module_t*)malloc(sizeof(NR_IF_Module_t)); + memset((void*)if_inst[Mod_id],0,sizeof(NR_IF_Module_t)); + + LOG_I(MAC,"Allocating shared L1/L2 interface structure for instance %d @ %p\n",Mod_id,if_inst[Mod_id]); + if_inst[Mod_id]->CC_mask=0; if_inst[Mod_id]->NR_UL_indication = NR_UL_indication; AssertFatal(pthread_mutex_init(&if_inst[Mod_id]->if_mutex,NULL)==0, diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h index 898197cc30..14355781d0 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h @@ -100,19 +100,19 @@ typedef struct { /// slot slot_t slot; /// nFAPI DL Config Request - nfapi_nr_dl_config_request_t *DL_req; + nfapi_nr_dl_tti_request_t *DL_req; /// nFAPI UL Config Request nfapi_nr_ul_tti_request_t *UL_tti_req; - /// nFAPI HI_DCI Request - nfapi_hi_dci0_request_t *HI_DCI0_req; + /// nFAPI UL_DCI Request + nfapi_nr_ul_dci_request_t *UL_dci_req; /// Pointers to DL SDUs - nfapi_tx_request_t *TX_req; + nfapi_nr_tx_data_request_t *TX_req; } NR_Sched_Rsp_t; typedef struct { uint8_t Mod_id; int CC_id; - nfapi_nr_config_request_t *cfg; + nfapi_nr_config_request_scf_t *cfg; } NR_PHY_Config_t; typedef struct NR_IF_Module_s { diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 494baefc29..64a814bcdb 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -45,17 +45,16 @@ static nr_ue_if_module_t *nr_ue_if_module_inst[MAX_IF_MODULES]; // L2 Abstraction Layer -int handle_bcch_bch(UE_nr_rxtx_proc_t *proc, module_id_t module_id, int cc_id, unsigned int gNB_index, uint8_t *pduP, unsigned int additional_bits, uint32_t ssb_index, uint32_t ssb_length, uint16_t cell_id){ +int handle_bcch_bch(module_id_t module_id, int cc_id, unsigned int gNB_index, uint8_t *pduP, unsigned int additional_bits, uint32_t ssb_index, uint32_t ssb_length, uint16_t cell_id){ - return nr_ue_decode_mib( proc, - module_id, - cc_id, - gNB_index, - additional_bits, - ssb_length, // Lssb = 64 is not support - ssb_index, - pduP, - cell_id); + return nr_ue_decode_mib(module_id, + cc_id, + gNB_index, + additional_bits, + ssb_length, // Lssb = 64 is not support + ssb_index, + pduP, + cell_id); } @@ -65,22 +64,23 @@ int handle_bcch_dlsch(module_id_t module_id, int cc_id, unsigned int gNB_index, return 0; } // L2 Abstraction Layer -int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){ +int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_indication_pdu_t *dci){ //printf("handle_dci: rnti %x,dci_type %d\n",rnti,dci_type); - return nr_ue_process_dci(module_id, cc_id, gNB_index, dci, rnti, dci_type); + return nr_ue_process_dci_indication_pdu(module_id, cc_id, gNB_index, dci); } // L2 Abstraction Layer int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len, frame_t frame, int slot, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ + LOG_D(MAC, "handle_dlsch at MAC layer \n"); //if (IS_SOFTMODEM_NOS1 || IS_SOFTMODEM_RFSIM) // sdu should be processed even when is S1 mode because data and timing advance updates are transmitted by the UE - nr_ue_send_sdu(module_id, cc_id, frame, slot, - pduP, - pdu_len, - gNB_index, - ul_time_alignment); + nr_ue_send_sdu(module_id, cc_id, frame, slot, + pduP, + pdu_len, + gNB_index, + ul_time_alignment); return 0; /* @@ -157,15 +157,12 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); for(i=0; idci_ind->number_of_dcis; ++i){ LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis); - fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci; + // fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci; - ret_mask |= (handle_dci( - dl_info->module_id, - dl_info->cc_id, - dl_info->gNB_index, - dci, - (dl_info->dci_ind->dci_list+i)->rnti, - (dl_info->dci_ind->dci_list+i)->dci_format)) << FAPI_NR_DCI_IND; + ret_mask |= (handle_dci(dl_info->module_id, + dl_info->cc_id, + dl_info->gNB_index, + dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND); AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" ); nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response); @@ -211,28 +208,22 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ }*/ //(dl_info->dci_list+i)->rnti - - - - } } if(dl_info->rx_ind != NULL){ - LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); for(i=0; irx_ind->number_pdus; ++i){ switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ case FAPI_NR_RX_PDU_TYPE_MIB: - ret_mask |= (handle_bcch_bch( dl_info->proc, - dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB; - LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - /*ret_mask |= (handle_bcch_bch( dl_info->proc, - dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + /*ret_mask |= (handle_bcch_bch( dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->rx_ind->rx_indication_body[i].mib_pdu.pdu, dl_info->rx_ind->rx_indication_body[i].mib_pdu.additional_bits, dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_index, @@ -249,9 +240,9 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ // ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH; ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot,ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH; + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot, ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH; - LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); /* // dl_config structure just stores what was received - not really needed @@ -310,49 +301,11 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) { fapi_nr_dl_config_request_t *dl_config=&dcireq->dl_config_req; NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0); - - // Type0 PDCCH search space - dl_config->number_pdus = 1; - dl_config->dl_config_list[0].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.rnti = 0x1234; // to be set - - uint64_t mask = 0x0; - uint16_t num_rbs=24; - uint16_t rb_offset=0; - uint16_t cell_id=0; - uint16_t num_symbols=2; - for(int i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs - mask = mask >> 1; - mask = mask | 0x100000000000; - } - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.frequency_domain_resource = mask; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset - - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id; - - uint32_t number_of_search_space_per_slot=1; - uint32_t first_symbol_index=0; - uint32_t search_space_duration=0; // element of search space - uint32_t coreset_duration; // element of coreset - - coreset_duration = num_symbols * number_of_search_space_per_slot; - - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[0] = table_38213_10_1_1_c2[0]; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[1] = table_38213_10_1_1_c2[1]; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16 - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.duration = search_space_duration; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff; - dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.N_RB_BWP = UE_mac->initial_bwp_dl.N_RB; - - + dl_config->sfn=UE_mac->dl_config_request.sfn; + dl_config->slot=UE_mac->dl_config_request.slot; + dl_config->number_pdus=0; + + ue_dci_configuration(UE_mac,dl_config,dcireq->frame,dcireq->slot); return 0; } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h index e46ae2103f..0784e71584 100755 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h @@ -106,8 +106,6 @@ typedef struct { int CC_id; /// frame frame_t frame; - /// subframe - sub_frame_t subframe; /// slot int slot; @@ -215,7 +213,7 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq); \param ssb_index SSB index within 0 - (L_ssb-1) corresponding to 38.331 ch.13 parameter i \param ssb_length corresponding to L1 parameter L_ssb \param cell_id cell id */ -int handle_bcch_bch(UE_nr_rxtx_proc_t *proc, module_id_t module_id, int cc_id, unsigned int gNB_index, uint8_t *pduP, unsigned int additional_bits, uint32_t ssb_index, uint32_t ssb_length, uint16_t cell_id); +int handle_bcch_bch(module_id_t module_id, int cc_id, unsigned int gNB_index, uint8_t *pduP, unsigned int additional_bits, uint32_t ssb_index, uint32_t ssb_length, uint16_t cell_id); // TODO check /**\brief handle BCCH-DL-SCH message from dl_indication @@ -223,7 +221,7 @@ int handle_bcch_bch(UE_nr_rxtx_proc_t *proc, module_id_t module_id, int cc_id, u \param pduP pointer to pdu*/ int handle_bcch_dlsch(module_id_t module_id, int cc_id, unsigned int gNB_index, uint32_t sibs_mask, uint8_t *pduP, uint32_t pdu_len); -int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type); +int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_indication_pdu_t *dci); #endif diff --git a/openair2/PHY_INTERFACE/phy_stub_UE.c b/openair2/PHY_INTERFACE/phy_stub_UE.c index 14974c2e15..bf2bbf7429 100644 --- a/openair2/PHY_INTERFACE/phy_stub_UE.c +++ b/openair2/PHY_INTERFACE/phy_stub_UE.c @@ -1,14 +1,29 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ -//#include "openair1/PHY/defs.h" -//#include "openair2/PHY_INTERFACE/IF_Module.h" -//#include "openair1/PHY/extern.h" #include "openair2/LAYER2/MAC/mac_extern.h" #include "openair2/LAYER2/MAC/mac.h" #include "openair2/LAYER2/MAC/mac_proto.h" -//#include "openair2/LAYER2/MAC/vars.h" #include "openair1/SCHED_UE/sched_UE.h" #include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_interface.h" -//#include "common/ran_context.h" #include "openair2/PHY_INTERFACE/phy_stub_UE.h" #include "openair2/ENB_APP/L1_paramdef.h" #include "openair2/ENB_APP/enb_paramdef.h" @@ -16,14 +31,12 @@ #include "common/config/config_load_configmodule.h" #include "common/config/config_userapi.h" -//#define DEADLINE_SCHEDULER 1 - - -extern int oai_nfapi_crc_indication(nfapi_crc_indication_t *crc_ind); -extern int oai_nfapi_rx_ind(nfapi_rx_indication_t *ind); extern int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind); -void configure_nfapi_pnf(char *vnf_ip_addr, int vnf_p5_port, char *pnf_ip_addr, int pnf_p7_port, int vnf_p7_port); - +void configure_nfapi_pnf(char *vnf_ip_addr, + int vnf_p5_port, + char *pnf_ip_addr, + int pnf_p7_port, + int vnf_p7_port); UL_IND_t *UL_INFO = NULL; nfapi_tx_request_pdu_t* tx_request_pdu_list = NULL; @@ -31,8 +44,6 @@ nfapi_dl_config_request_t* dl_config_req = NULL; nfapi_ul_config_request_t* ul_config_req = NULL; nfapi_hi_dci0_request_t* hi_dci0_req = NULL; -//extern uint8_t nfapi_pnf; -//UL_IND_t *UL_INFO; extern nfapi_tx_request_pdu_t* tx_request_pdu[1023][10][10]; //extern int timer_subframe; //extern int timer_frame; @@ -42,1010 +53,1057 @@ extern uint16_t sf_ahead; void Msg1_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id); void Msg3_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id); +void fill_rx_indication_UE_MAC(module_id_t Mod_id, + int frame, + int subframe, + UL_IND_t *UL_INFO, + uint8_t *ulsch_buffer, + uint16_t buflen, + uint16_t rnti, + int index) { + nfapi_rx_indication_pdu_t *pdu; + int timing_advance_update; + pthread_mutex_lock(&fill_ul_mutex.rx_mutex); -void fill_rx_indication_UE_MAC(module_id_t Mod_id,int frame,int subframe, UL_IND_t* UL_INFO, uint8_t *ulsch_buffer, uint16_t buflen, uint16_t rnti, int index) -{ - nfapi_rx_indication_pdu_t *pdu; + UL_INFO->rx_ind.sfn_sf = frame << 4 | subframe; + UL_INFO->rx_ind.rx_indication_body.tl.tag = NFAPI_RX_INDICATION_BODY_TAG; + UL_INFO->rx_ind.vendor_extension = ul_config_req->vendor_extension; - int timing_advance_update; + pdu = &UL_INFO->rx_ind.rx_indication_body + .rx_pdu_list[UL_INFO->rx_ind.rx_indication_body.number_of_pdus]; + // pdu = &UL_INFO->rx_ind.rx_indication_body.rx_pdu_list[index]; + // pdu->rx_ue_information.handle = eNB->ulsch[UE_id]->handle; + pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; + pdu->rx_ue_information.rnti = rnti; + pdu->rx_indication_rel8.tl.tag = NFAPI_RX_INDICATION_REL8_TAG; + pdu->rx_indication_rel8.length = buflen; + pdu->rx_indication_rel8.offset = 1; + pdu->rx_indication_rel9.tl.tag = NFAPI_RX_INDICATION_REL9_TAG; + pdu->rx_indication_rel9.timing_advance_r9 = 0; - // pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); - // change for mutiple UE's simulation. - pthread_mutex_lock(&fill_ul_mutex.rx_mutex); + // ulsch_buffer is necessary to keep its value. + pdu->data = malloc(buflen); + memcpy(pdu->data, ulsch_buffer, buflen); + // estimate timing advance for MAC + timing_advance_update = 0; // Don't know what to put here + pdu->rx_indication_rel8.timing_advance = timing_advance_update; + int SNRtimes10 = 640; - UL_INFO->rx_ind.sfn_sf = frame<<4| subframe; - UL_INFO->rx_ind.rx_indication_body.tl.tag = NFAPI_RX_INDICATION_BODY_TAG; - UL_INFO->rx_ind.vendor_extension = ul_config_req->vendor_extension; - - - pdu = &UL_INFO->rx_ind.rx_indication_body.rx_pdu_list[UL_INFO->rx_ind.rx_indication_body.number_of_pdus]; - //pdu = &UL_INFO->rx_ind.rx_indication_body.rx_pdu_list[index]; - - // pdu->rx_ue_information.handle = eNB->ulsch[UE_id]->handle; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = rnti; - pdu->rx_indication_rel8.tl.tag = NFAPI_RX_INDICATION_REL8_TAG; - //pdu->rx_indication_rel8.length = eNB->ulsch[UE_id]->harq_processes[harq_pid]->TBS>>3; - pdu->rx_indication_rel8.length = buflen; - pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation - - // ulsch_buffer is necessary to keep its value. - //pdu->data = ulsch_buffer; - pdu->data = malloc(buflen); - memcpy(pdu->data,ulsch_buffer,buflen); - // estimate timing advance for MAC - //sync_pos = lte_est_timing_advance_pusch(eNB,UE_id); - timing_advance_update = 0; // Don't know what to put here - pdu->rx_indication_rel8.timing_advance = timing_advance_update; - - int SNRtimes10 = 640; - - if (SNRtimes10 < -640) pdu->rx_indication_rel8.ul_cqi=0; - else if (SNRtimes10 > 635) pdu->rx_indication_rel8.ul_cqi=255; - else pdu->rx_indication_rel8.ul_cqi=(640+SNRtimes10)/5; - - - UL_INFO->rx_ind.rx_indication_body.number_of_pdus++; - UL_INFO->rx_ind.sfn_sf = frame<<4 | subframe; - // pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); - // change for mutiple UE's simulation. - pthread_mutex_unlock(&fill_ul_mutex.rx_mutex); - + if (SNRtimes10 < -640) + pdu->rx_indication_rel8.ul_cqi = 0; + else if (SNRtimes10 > 635) + pdu->rx_indication_rel8.ul_cqi = 255; + else + pdu->rx_indication_rel8.ul_cqi = (640 + SNRtimes10) / 5; + UL_INFO->rx_ind.rx_indication_body.number_of_pdus++; + UL_INFO->rx_ind.sfn_sf = frame << 4 | subframe; + pthread_mutex_unlock(&fill_ul_mutex.rx_mutex); } -void fill_sr_indication_UE_MAC(int Mod_id,int frame,int subframe, UL_IND_t *UL_INFO, uint16_t rnti) { - - - // change for mutiple UE's simulation. - //pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); +void fill_sr_indication_UE_MAC(int Mod_id, + int frame, + int subframe, + UL_IND_t *UL_INFO, + uint16_t rnti) { pthread_mutex_lock(&fill_ul_mutex.sr_mutex); - nfapi_sr_indication_t *sr_ind = &UL_INFO->sr_ind; - nfapi_sr_indication_body_t *sr_ind_body = &sr_ind->sr_indication_body; - nfapi_sr_indication_pdu_t *pdu = &sr_ind_body->sr_pdu_list[sr_ind_body->number_of_srs]; - UL_INFO->sr_ind.vendor_extension = ul_config_req->vendor_extension; + nfapi_sr_indication_t *sr_ind = &UL_INFO->sr_ind; + nfapi_sr_indication_body_t *sr_ind_body = &sr_ind->sr_indication_body; + nfapi_sr_indication_pdu_t *pdu = &sr_ind_body->sr_pdu_list[sr_ind_body->number_of_srs]; + UL_INFO->sr_ind.vendor_extension = ul_config_req->vendor_extension; - //nfapi_sr_indication_pdu_t *pdu = &UL_INFO->sr_ind.sr_indication_body.sr_pdu_list[UL_INFO->rx_ind.rx_indication_body.number_of_pdus]; - - sr_ind->sfn_sf = frame<<4|subframe; + sr_ind->sfn_sf = frame << 4 | subframe; sr_ind->header.message_id = NFAPI_RX_SR_INDICATION; sr_ind_body->tl.tag = NFAPI_SR_INDICATION_BODY_TAG; - pdu->instance_length = 0; // don't know what to do with this + pdu->instance_length = 0; // don't know what to do with this // pdu->rx_ue_information.handle = handle; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = rnti; //UE_mac_inst[Mod_id].crnti - - - // dependency from PHY not sure how to substitute this. Should we hardcode it? - //int SNRtimes10 = dB_fixed_times10(stat) - 200;//(10*eNB->measurements.n0_power_dB[0]); - int SNRtimes10 = 640; + pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; + pdu->rx_ue_information.rnti = rnti; // UE_mac_inst[Mod_id].crnti pdu->ul_cqi_information.tl.tag = NFAPI_UL_CQI_INFORMATION_TAG; - - - if (SNRtimes10 < -640) pdu->ul_cqi_information.ul_cqi=0; - else if (SNRtimes10 > 635) pdu->ul_cqi_information.ul_cqi=255; - else pdu->ul_cqi_information.ul_cqi=(640+SNRtimes10)/5; pdu->ul_cqi_information.channel = 0; - //UL_INFO->rx_ind.rx_indication_body.number_of_pdus++; + int SNRtimes10 = 640; + if (SNRtimes10 < -640) + pdu->ul_cqi_information.ul_cqi = 0; + else if (SNRtimes10 > 635) + pdu->ul_cqi_information.ul_cqi = 255; + else + pdu->ul_cqi_information.ul_cqi = (640 + SNRtimes10) / 5; + + // UL_INFO->rx_ind.rx_indication_body.number_of_pdus++; sr_ind_body->number_of_srs++; - // change for mutiple UE's simulation. - // pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); pthread_mutex_unlock(&fill_ul_mutex.sr_mutex); } - -void fill_crc_indication_UE_MAC(int Mod_id,int frame,int subframe, UL_IND_t *UL_INFO, uint8_t crc_flag, int index, uint16_t rnti) { - - // change for mutiple UE's simulation. - //pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); +void fill_crc_indication_UE_MAC(int Mod_id, + int frame, + int subframe, + UL_IND_t *UL_INFO, + uint8_t crc_flag, + int index, + uint16_t rnti) { pthread_mutex_lock(&fill_ul_mutex.crc_mutex); - // REMEMBER HAVE EXCHANGED THE FOLLOWING TWO LINES HERE! - nfapi_crc_indication_pdu_t *pdu = &UL_INFO->crc_ind.crc_indication_body.crc_pdu_list[UL_INFO->crc_ind.crc_indication_body.number_of_crcs]; + nfapi_crc_indication_pdu_t *pdu = + &UL_INFO->crc_ind.crc_indication_body + .crc_pdu_list[UL_INFO->crc_ind.crc_indication_body.number_of_crcs]; - UL_INFO->crc_ind.sfn_sf = frame<<4| subframe; - UL_INFO->crc_ind.vendor_extension = ul_config_req->vendor_extension; - UL_INFO->crc_ind.header.message_id = NFAPI_CRC_INDICATION; + UL_INFO->crc_ind.sfn_sf = frame << 4 | subframe; + UL_INFO->crc_ind.vendor_extension = ul_config_req->vendor_extension; + UL_INFO->crc_ind.header.message_id = NFAPI_CRC_INDICATION; UL_INFO->crc_ind.crc_indication_body.tl.tag = NFAPI_CRC_INDICATION_BODY_TAG; - pdu->instance_length = 0; // don't know what to do with this - // pdu->rx_ue_information.handle = handle; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; + pdu->instance_length = 0; + pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - //pdu->rx_ue_information.rnti = UE_mac_inst[Mod_id].crnti; - pdu->rx_ue_information.rnti = rnti; - pdu->crc_indication_rel8.tl.tag = NFAPI_CRC_INDICATION_REL8_TAG; - pdu->crc_indication_rel8.crc_flag = crc_flag; + pdu->rx_ue_information.rnti = rnti; + pdu->crc_indication_rel8.tl.tag = NFAPI_CRC_INDICATION_REL8_TAG; + pdu->crc_indication_rel8.crc_flag = crc_flag; UL_INFO->crc_ind.crc_indication_body.number_of_crcs++; - LOG_D(PHY, "%s() rnti:%04x pdus:%d\n", __FUNCTION__, pdu->rx_ue_information.rnti, UL_INFO->crc_ind.crc_indication_body.number_of_crcs); + LOG_D(PHY, + "%s() rnti:%04x pdus:%d\n", + __FUNCTION__, + pdu->rx_ue_information.rnti, + UL_INFO->crc_ind.crc_indication_body.number_of_crcs); - // change for mutiple UE's simulation. - // pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); pthread_mutex_unlock(&fill_ul_mutex.crc_mutex); } -void fill_rach_indication_UE_MAC(int Mod_id,int frame,int subframe, UL_IND_t *UL_INFO, uint8_t ra_PreambleIndex, uint16_t ra_RNTI) { +void fill_rach_indication_UE_MAC(int Mod_id, + int frame, + int subframe, + UL_IND_t *UL_INFO, + uint8_t ra_PreambleIndex, + uint16_t ra_RNTI) { + LOG_D(MAC, "fill_rach_indication_UE_MAC 1 \n"); - LOG_D(MAC, "fill_rach_indication_UE_MAC 1 \n"); + pthread_mutex_lock(&fill_ul_mutex.rach_mutex); - // change for mutiple UE's simulation. - // pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); - pthread_mutex_lock(&fill_ul_mutex.rach_mutex); + UL_INFO->rach_ind.rach_indication_body.number_of_preambles = 1; - // memory allocation and free memory of UL_INFO are done in UE_phy_stub_single_thread_rxn_txnp4. - // UL_INFO = (UL_IND_t*)malloc(sizeof(UL_IND_t)); + UL_INFO->rach_ind.header.message_id = NFAPI_RACH_INDICATION; + UL_INFO->rach_ind.sfn_sf = frame << 4 | subframe; + UL_INFO->rach_ind.vendor_extension = NULL; - UL_INFO->rach_ind.rach_indication_body.number_of_preambles = 1; + UL_INFO->rach_ind.rach_indication_body.tl.tag = NFAPI_RACH_INDICATION_BODY_TAG; - //eNB->UL_INFO.rach_ind.preamble_list = &eNB->preamble_list[0]; - UL_INFO->rach_ind.header.message_id = NFAPI_RACH_INDICATION; - UL_INFO->rach_ind.sfn_sf = frame<<4 | subframe; - UL_INFO->rach_ind.vendor_extension = NULL; + const int np = UL_INFO->rach_ind.rach_indication_body.number_of_preambles; + UL_INFO->rach_ind.rach_indication_body.preamble_list = + calloc(np, sizeof(nfapi_preamble_pdu_t)); + UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.tl.tag = + NFAPI_PREAMBLE_REL8_TAG; + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel8.timing_advance = 0; // Not sure about that - UL_INFO->rach_ind.rach_indication_body.tl.tag = NFAPI_RACH_INDICATION_BODY_TAG; + // The two following should get extracted from the call to + // get_prach_resources(). + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel8.preamble = ra_PreambleIndex; + UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti = + ra_RNTI; + // UL_INFO->rach_ind.rach_indication_body.number_of_preambles++; + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel13.rach_resource_type = 0; + UL_INFO->rach_ind.rach_indication_body.preamble_list[0].instance_length = 0; - UL_INFO->rach_ind.rach_indication_body.preamble_list = (nfapi_preamble_pdu_t*)malloc(UL_INFO->rach_ind.rach_indication_body.number_of_preambles*sizeof(nfapi_preamble_pdu_t)); - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.tl.tag = NFAPI_PREAMBLE_REL8_TAG; - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance = 0; // Not sure about that + LOG_I(PHY, + "UE Filling NFAPI indication for RACH : TA %d, Preamble %d, rnti %x, " + "rach_resource_type %d\n", + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel8.timing_advance, + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel8.preamble, + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel8.rnti, + UL_INFO->rach_ind.rach_indication_body.preamble_list[0] + .preamble_rel13.rach_resource_type); - //The two following should get extracted from the call to get_prach_resources(). - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble = ra_PreambleIndex; - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti = ra_RNTI; - //UL_INFO->rach_ind.rach_indication_body.number_of_preambles++; - - - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel13.rach_resource_type = 0; - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].instance_length = 0; - - - LOG_E(PHY,"\n\n\n\nDJP - this needs to be sent to VNF **********************************************\n\n\n\n"); - LOG_E(PHY,"UE Filling NFAPI indication for RACH : TA %d, Preamble %d, rnti %x, rach_resource_type %d\n", - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti, - UL_INFO->rach_ind.rach_indication_body.preamble_list[0].preamble_rel13.rach_resource_type); - - // This function is currently defined only in the nfapi-RU-RAU-split so we should call it when we merge - // with that branch. - oai_nfapi_rach_ind(&UL_INFO->rach_ind); - free(UL_INFO->rach_ind.rach_indication_body.preamble_list); - - // memory allocation and free memory of UL_INFO are done in UE_phy_stub_single_thread_rxn_txnp4. - //free(UL_INFO); - - //} - // change for mutiple UE's simulation. - // pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); - pthread_mutex_unlock(&fill_ul_mutex.rach_mutex); + // This function is currently defined only in the nfapi-RU-RAU-split so we + // should call it when we merge with that branch. + oai_nfapi_rach_ind(&UL_INFO->rach_ind); + free(UL_INFO->rach_ind.rach_indication_body.preamble_list); + pthread_mutex_unlock(&fill_ul_mutex.rach_mutex); } -void fill_ulsch_cqi_indication_UE_MAC(int Mod_id, uint16_t frame,uint8_t subframe, UL_IND_t *UL_INFO, uint16_t rnti) { +void fill_ulsch_cqi_indication_UE_MAC(int Mod_id, + uint16_t frame, + uint8_t subframe, + UL_IND_t *UL_INFO, + uint16_t rnti) { + pthread_mutex_lock(&fill_ul_mutex.cqi_mutex); + nfapi_cqi_indication_pdu_t *pdu = + &UL_INFO->cqi_ind.cqi_indication_body + .cqi_pdu_list[UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis]; + nfapi_cqi_indication_raw_pdu_t *raw_pdu = + &UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list + [UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis]; - // change for mutiple UE's simulation. - //pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); - pthread_mutex_lock(&fill_ul_mutex.cqi_mutex); - nfapi_cqi_indication_pdu_t *pdu = &UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list[UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis]; - nfapi_cqi_indication_raw_pdu_t *raw_pdu = &UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list[UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis]; + UL_INFO->cqi_ind.sfn_sf = frame << 4 | subframe; + // because of nfapi_vnf.c:733, set message id to 0, not + // NFAPI_RX_CQI_INDICATION; + UL_INFO->cqi_ind.header.message_id = 0; + UL_INFO->cqi_ind.cqi_indication_body.tl.tag = NFAPI_CQI_INDICATION_BODY_TAG; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = rnti; - // Since we assume that CRC flag is always 0 (ACK) I guess that data_offset should always be 0. - pdu->cqi_indication_rel9.data_offset = 0; + pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; + pdu->rx_ue_information.rnti = rnti; + // Since we assume that CRC flag is always 0 (ACK) I guess that data_offset + // should always be 0. + pdu->cqi_indication_rel8.data_offset = 0; - // by default set O to rank 1 value - //pdu->cqi_indication_rel9.length = (ulsch_harq->Or1>>3) + ((ulsch_harq->Or1&7) > 0 ? 1 : 0); - // Not useful field for our case - pdu->cqi_indication_rel9.tl.tag = NFAPI_CQI_INDICATION_REL9_TAG; - pdu->cqi_indication_rel9.length = 0; - pdu->cqi_indication_rel9.ri[0] = 0; + pdu->cqi_indication_rel8.tl.tag = NFAPI_CQI_INDICATION_REL8_TAG; + pdu->cqi_indication_rel8.length = 1; + pdu->cqi_indication_rel8.ri = 0; - - pdu->cqi_indication_rel9.timing_advance = 0; - pdu->cqi_indication_rel9.number_of_cc_reported = 1; + pdu->cqi_indication_rel8.timing_advance = 0; + // pdu->cqi_indication_rel8.number_of_cc_reported = 1; + pdu->ul_cqi_information.tl.tag = NFAPI_UL_CQI_INFORMATION_TAG; pdu->ul_cqi_information.channel = 1; // PUSCH - // Not sure how to substitute this. This should be the actual CQI value? So can - // we hardcode it to a specific value? - //memcpy((void*)raw_pdu->pdu,ulsch_harq->o,pdu->cqi_indication_rel9.length); - raw_pdu->pdu[0] = 7; - - + // eNB_scheduler_primitives.c:4839: the upper four bits seem to be the CQI + const int cqi = 15; + raw_pdu->pdu[0] = cqi << 4; UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis++; - // change for mutiple UE's simulation. - //pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); pthread_mutex_unlock(&fill_ul_mutex.cqi_mutex); } -void fill_ulsch_harq_indication_UE_MAC(int Mod_id, int frame,int subframe, UL_IND_t *UL_INFO, nfapi_ul_config_ulsch_harq_information *harq_information, uint16_t rnti) -{ - - // change for mutiple UE's simulation. - //pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); +void fill_ulsch_harq_indication_UE_MAC( + int Mod_id, + int frame, + int subframe, + UL_IND_t *UL_INFO, + nfapi_ul_config_ulsch_harq_information *harq_information, + uint16_t rnti) { pthread_mutex_lock(&fill_ul_mutex.harq_mutex); - nfapi_harq_indication_pdu_t *pdu = &UL_INFO->harq_ind.harq_indication_body.harq_pdu_list[UL_INFO->harq_ind.harq_indication_body.number_of_harqs]; - int i; + nfapi_harq_indication_pdu_t *pdu = + &UL_INFO->harq_ind.harq_indication_body.harq_pdu_list + [UL_INFO->harq_ind.harq_indication_body.number_of_harqs]; UL_INFO->harq_ind.header.message_id = NFAPI_HARQ_INDICATION; - UL_INFO->harq_ind.sfn_sf = frame<<4|subframe; - UL_INFO->harq_ind.vendor_extension = ul_config_req->vendor_extension; + UL_INFO->harq_ind.sfn_sf = frame << 4 | subframe; + UL_INFO->harq_ind.vendor_extension = ul_config_req->vendor_extension; - UL_INFO->harq_ind.harq_indication_body.tl.tag = NFAPI_HARQ_INDICATION_BODY_TAG; + UL_INFO->harq_ind.harq_indication_body.tl.tag = + NFAPI_HARQ_INDICATION_BODY_TAG; - pdu->instance_length = 0; // don't know what to do with this + pdu->instance_length = 0; // don't know what to do with this // pdu->rx_ue_information.handle = handle; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = rnti; + pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; + pdu->rx_ue_information.rnti = rnti; // For now we consider only FDD - //if (eNB->frame_parms.frame_type == FDD) { - pdu->harq_indication_fdd_rel13.tl.tag = NFAPI_HARQ_INDICATION_FDD_REL13_TAG; - pdu->harq_indication_fdd_rel13.mode = 0; - pdu->harq_indication_fdd_rel13.number_of_ack_nack = harq_information->harq_information_rel10.harq_size; + // if (eNB->frame_parms.frame_type == FDD) { + pdu->harq_indication_fdd_rel13.tl.tag = NFAPI_HARQ_INDICATION_FDD_REL13_TAG; + pdu->harq_indication_fdd_rel13.mode = 0; + pdu->harq_indication_fdd_rel13.number_of_ack_nack = + harq_information->harq_information_rel10.harq_size; - // Could this be wrong? Is the number_of_ack_nack field equivalent to O_ACK? - //pdu->harq_indication_fdd_rel13.number_of_ack_nack = ulsch_harq->O_ACK; + // Could this be wrong? Is the number_of_ack_nack field equivalent to O_ACK? + // pdu->harq_indication_fdd_rel13.number_of_ack_nack = ulsch_harq->O_ACK; - for (i=0;iharq_information_rel10.harq_size;i++) { - - pdu->harq_indication_fdd_rel13.harq_tb_n[i] = 1; // Assuming always an ACK (No NACK or DTX) - - } + for (int i = 0; i < harq_information->harq_information_rel10.harq_size; i++) { + pdu->harq_indication_fdd_rel13.harq_tb_n[i] = 1; // Assume always ACK (No NACK or DTX) + } UL_INFO->harq_ind.harq_indication_body.number_of_harqs++; - // change for mutiple UE's simulation. - //pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); - pthread_mutex_unlock(&fill_ul_mutex.harq_mutex);} - + pthread_mutex_unlock(&fill_ul_mutex.harq_mutex); +} void fill_uci_harq_indication_UE_MAC(int Mod_id, int frame, int subframe, UL_IND_t *UL_INFO, nfapi_ul_config_harq_information *harq_information, - uint16_t rnti - /*uint8_t tdd_mapping_mode, - uint16_t tdd_multiplexing_mask*/) { - - - // change for mutiple UE's simulation. - //pthread_mutex_lock(&UE_mac_inst[Mod_id].UL_INFO_mutex); + uint16_t rnti) { pthread_mutex_lock(&fill_ul_mutex.harq_mutex); - nfapi_harq_indication_t *ind = &UL_INFO->harq_ind; + nfapi_harq_indication_t *ind = &UL_INFO->harq_ind; nfapi_harq_indication_body_t *body = &ind->harq_indication_body; - nfapi_harq_indication_pdu_t *pdu = &body->harq_pdu_list[UL_INFO->harq_ind.harq_indication_body.number_of_harqs]; + nfapi_harq_indication_pdu_t *pdu = + &body->harq_pdu_list[UL_INFO->harq_ind.harq_indication_body + .number_of_harqs]; - UL_INFO->harq_ind.vendor_extension = ul_config_req->vendor_extension; + UL_INFO->harq_ind.vendor_extension = ul_config_req->vendor_extension; - ind->sfn_sf = frame<<4|subframe; + ind->sfn_sf = frame << 4 | subframe; ind->header.message_id = NFAPI_HARQ_INDICATION; body->tl.tag = NFAPI_HARQ_INDICATION_BODY_TAG; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; + pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->instance_length = 0; // don't know what to do with this - // pdu->rx_ue_information.handle = handle; - pdu->rx_ue_information.rnti = rnti; + pdu->instance_length = 0; // don't know what to do with this + pdu->rx_ue_information.rnti = rnti; pdu->ul_cqi_information.tl.tag = NFAPI_UL_CQI_INFORMATION_TAG; int SNRtimes10 = 640; - - if (SNRtimes10 < -640) pdu->ul_cqi_information.ul_cqi=0; - else if (SNRtimes10 > 635) pdu->ul_cqi_information.ul_cqi=255; - else pdu->ul_cqi_information.ul_cqi=(640+SNRtimes10)/5; + if (SNRtimes10 < -640) + pdu->ul_cqi_information.ul_cqi = 0; + else if (SNRtimes10 > 635) + pdu->ul_cqi_information.ul_cqi = 255; + else + pdu->ul_cqi_information.ul_cqi = (640 + SNRtimes10) / 5; pdu->ul_cqi_information.channel = 0; - if(harq_information->harq_information_rel9_fdd.tl.tag == NFAPI_UL_CONFIG_REQUEST_HARQ_INFORMATION_REL9_FDD_TAG){ - if ((harq_information->harq_information_rel9_fdd.ack_nack_mode == 0) && - (harq_information->harq_information_rel9_fdd.harq_size == 1)) { - - pdu->harq_indication_fdd_rel13.tl.tag = NFAPI_HARQ_INDICATION_FDD_REL13_TAG; + if (harq_information->harq_information_rel9_fdd.tl.tag + == NFAPI_UL_CONFIG_REQUEST_HARQ_INFORMATION_REL9_FDD_TAG) { + if ((harq_information->harq_information_rel9_fdd.ack_nack_mode == 0) + && (harq_information->harq_information_rel9_fdd.harq_size == 1)) { + pdu->harq_indication_fdd_rel13.tl.tag = + NFAPI_HARQ_INDICATION_FDD_REL13_TAG; pdu->harq_indication_fdd_rel13.mode = 0; pdu->harq_indication_fdd_rel13.number_of_ack_nack = 1; - //AssertFatal(harq_ack[0] == 1 || harq_ack[0] == 2 || harq_ack[0] == 4, "harq_ack[0] is %d, should be 1,2 or 4\n",harq_ack[0]); - pdu->harq_indication_fdd_rel13.harq_tb_n[0] = 1; // Assuming always an ACK (No NACK or DTX) + // AssertFatal(harq_ack[0] == 1 || harq_ack[0] == 2 || harq_ack[0] == 4, + // "harq_ack[0] is %d, should be 1,2 or 4\n",harq_ack[0]); + pdu->harq_indication_fdd_rel13.harq_tb_n[0] = + 1; // Assuming always an ACK (No NACK or DTX) - - } - else if ((harq_information->harq_information_rel9_fdd.ack_nack_mode == 0) && - (harq_information->harq_information_rel9_fdd.harq_size == 2)) { - pdu->harq_indication_fdd_rel13.tl.tag = NFAPI_HARQ_INDICATION_FDD_REL13_TAG; + } else if ((harq_information->harq_information_rel9_fdd.ack_nack_mode == 0) + && (harq_information->harq_information_rel9_fdd.harq_size + == 2)) { + pdu->harq_indication_fdd_rel13.tl.tag = + NFAPI_HARQ_INDICATION_FDD_REL13_TAG; pdu->harq_indication_fdd_rel13.mode = 0; pdu->harq_indication_fdd_rel13.number_of_ack_nack = 2; - pdu->harq_indication_fdd_rel13.harq_tb_n[0] = 1; // Assuming always an ACK (No NACK or DTX) - pdu->harq_indication_fdd_rel13.harq_tb_n[1] = 1; // Assuming always an ACK (No NACK or DTX) - + pdu->harq_indication_fdd_rel13.harq_tb_n[0] = + 1; // Assuming always an ACK (No NACK or DTX) + pdu->harq_indication_fdd_rel13.harq_tb_n[1] = + 1; // Assuming always an ACK (No NACK or DTX) } - }else if(harq_information->harq_information_rel10_tdd.tl.tag == NFAPI_UL_CONFIG_REQUEST_HARQ_INFORMATION_REL10_TDD_TAG ){ - if ((harq_information->harq_information_rel10_tdd.ack_nack_mode == 0) && - (harq_information->harq_information_rel10_tdd.harq_size == 1)) { - pdu->harq_indication_tdd_rel13.tl.tag = NFAPI_HARQ_INDICATION_TDD_REL13_TAG; - pdu->harq_indication_tdd_rel13.mode = 0; - pdu->harq_indication_tdd_rel13.number_of_ack_nack = 1; - pdu->harq_indication_tdd_rel13.harq_data[0].bundling.value_0 = 1; - - } else if ((harq_information->harq_information_rel10_tdd.ack_nack_mode == 1) && - (harq_information->harq_information_rel10_tdd.harq_size == 2)) { - pdu->harq_indication_tdd_rel13.tl.tag = NFAPI_HARQ_INDICATION_TDD_REL13_TAG; - pdu->harq_indication_tdd_rel13.mode = 0; - pdu->harq_indication_tdd_rel13.number_of_ack_nack = 1; - pdu->harq_indication_tdd_rel13.harq_data[0].bundling.value_0 = 1; - pdu->harq_indication_tdd_rel13.harq_data[1].bundling.value_0 = 1; - - } - } else AssertFatal(1==0,"only format 1a/b for now, received \n"); + } else if (harq_information->harq_information_rel10_tdd.tl.tag + == NFAPI_UL_CONFIG_REQUEST_HARQ_INFORMATION_REL10_TDD_TAG) { + if ((harq_information->harq_information_rel10_tdd.ack_nack_mode == 0) + && (harq_information->harq_information_rel10_tdd.harq_size == 1)) { + pdu->harq_indication_tdd_rel13.tl.tag = + NFAPI_HARQ_INDICATION_TDD_REL13_TAG; + pdu->harq_indication_tdd_rel13.mode = 0; + pdu->harq_indication_tdd_rel13.number_of_ack_nack = 1; + pdu->harq_indication_tdd_rel13.harq_data[0].bundling.value_0 = 1; + } else if ((harq_information->harq_information_rel10_tdd.ack_nack_mode == 1) + && (harq_information->harq_information_rel10_tdd.harq_size + == 2)) { + pdu->harq_indication_tdd_rel13.tl.tag = + NFAPI_HARQ_INDICATION_TDD_REL13_TAG; + pdu->harq_indication_tdd_rel13.mode = 0; + pdu->harq_indication_tdd_rel13.number_of_ack_nack = 1; + pdu->harq_indication_tdd_rel13.harq_data[0].bundling.value_0 = 1; + pdu->harq_indication_tdd_rel13.harq_data[1].bundling.value_0 = 1; + } + } else + AssertFatal(1 == 0, "only format 1a/b for now, received \n"); UL_INFO->harq_ind.harq_indication_body.number_of_harqs++; - LOG_D(PHY,"Incremented eNB->UL_INFO.harq_ind.number_of_harqs:%d\n", UL_INFO->harq_ind.harq_indication_body.number_of_harqs); - // change for mutiple UE's simulation. - //pthread_mutex_unlock(&UE_mac_inst[Mod_id].UL_INFO_mutex); + LOG_D(PHY, + "Incremented eNB->UL_INFO.harq_ind.number_of_harqs:%d\n", + UL_INFO->harq_ind.harq_indication_body.number_of_harqs); pthread_mutex_unlock(&fill_ul_mutex.harq_mutex); - } - void handle_nfapi_ul_pdu_UE_MAC(module_id_t Mod_id, - nfapi_ul_config_request_pdu_t *ul_config_pdu, - uint16_t frame,uint8_t subframe,uint8_t srs_present, int index) -{ - + nfapi_ul_config_request_pdu_t *ul_config_pdu, + uint16_t frame, + uint8_t subframe, + uint8_t srs_present, + int index) { if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_ULSCH_PDU_TYPE) { - LOG_D(PHY,"Applying UL config for UE, rnti %x for frame %d, subframe %d\n", - (ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8).rnti,frame,subframe); - uint8_t ulsch_buffer[5477] __attribute__ ((aligned(32))); + LOG_D(PHY, + "Applying UL config for UE, rnti %x for frame %d, subframe %d\n", + (ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8).rnti, + frame, + subframe); + uint8_t ulsch_buffer[5477] __attribute__((aligned(32))); uint16_t buflen = ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.size; uint16_t rnti = ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.rnti; - uint8_t access_mode=SCHEDULED_ACCESS; - if(buflen>0){ - if(UE_mac_inst[Mod_id].first_ULSCH_Tx == 1){ // Msg3 case - LOG_D(MAC, "handle_nfapi_ul_pdu_UE_MAC 2.2, Mod_id:%d, SFN/SF: %d/%d \n", Mod_id, frame, subframe); - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, UE_mac_inst[Mod_id].RA_prach_resources.Msg3,buflen, rnti, index); - Msg3_transmitted(Mod_id, 0, frame, 0); - // Modification - UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; - UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + uint8_t access_mode = SCHEDULED_ACCESS; + if (buflen > 0) { + if (UE_mac_inst[Mod_id].first_ULSCH_Tx == 1) { // Msg3 case + LOG_D(MAC, + "handle_nfapi_ul_pdu_UE_MAC 2.2, Mod_id:%d, SFN/SF: %d/%d \n", + Mod_id, + frame, + subframe); + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + UE_mac_inst[Mod_id].RA_prach_resources.Msg3, + buflen, + rnti, + index); + Msg3_transmitted(Mod_id, 0, frame, 0); + // Modification + UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; + UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - // This should be done after the reception of the respective hi_dci0 - //UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - } - else { - ue_get_sdu( Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_buffer,buflen, rnti, index); - } + // This should be done after the reception of the respective hi_dci0 + // UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + } else { + ue_get_sdu(Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + ulsch_buffer, + buflen, + rnti, + index); + } } } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE) { + // AssertFatal((UE_id = + // find_ulsch(ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE))>=0, + // "No available UE ULSCH for rnti + // %x\n",ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti); + uint8_t ulsch_buffer[5477] __attribute__((aligned(32))); + uint16_t buflen = + ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.size; + nfapi_ul_config_ulsch_harq_information *ulsch_harq_information = + &ul_config_pdu->ulsch_harq_pdu.harq_information; + uint16_t rnti = ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti; + uint8_t access_mode = SCHEDULED_ACCESS; + if (buflen > 0) { + if (UE_mac_inst[Mod_id].first_ULSCH_Tx == 1) { // Msg3 case + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + UE_mac_inst[Mod_id].RA_prach_resources.Msg3, + buflen, + rnti, + index); + Msg3_transmitted(Mod_id, 0, frame, 0); + // UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + // Modification + UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; + UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + } else { + ue_get_sdu(Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + ulsch_buffer, + buflen, + rnti, + index); + } + } + if (ulsch_harq_information != NULL) + fill_ulsch_harq_indication_UE_MAC( + Mod_id, frame, subframe, UL_INFO, ulsch_harq_information, rnti); - //AssertFatal((UE_id = find_ulsch(ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE))>=0, - // "No available UE ULSCH for rnti %x\n",ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti); - uint8_t ulsch_buffer[5477] __attribute__ ((aligned(32))); - uint16_t buflen = ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.size; - nfapi_ul_config_ulsch_harq_information *ulsch_harq_information = &ul_config_pdu->ulsch_harq_pdu.harq_information; - uint16_t rnti = ul_config_pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti; - uint8_t access_mode=SCHEDULED_ACCESS; - if(buflen>0){ - if(UE_mac_inst[Mod_id].first_ULSCH_Tx == 1){ // Msg3 case - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, UE_mac_inst[Mod_id].RA_prach_resources.Msg3,buflen, rnti, index); - Msg3_transmitted(Mod_id, 0, frame, 0); - //UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - // Modification - UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; - UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - } - else { - ue_get_sdu( Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_buffer,buflen, rnti, index); - } + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_RI_PDU_TYPE) { + uint8_t ulsch_buffer[5477] __attribute__((aligned(32))); + uint16_t buflen = ul_config_pdu->ulsch_cqi_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.size; - } - if(ulsch_harq_information!=NULL) - fill_ulsch_harq_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_harq_information, rnti); + uint16_t rnti = ul_config_pdu->ulsch_cqi_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti; + uint8_t access_mode = SCHEDULED_ACCESS; + if (buflen > 0) { + if (UE_mac_inst[Mod_id].first_ULSCH_Tx == 1) { // Msg3 case + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + UE_mac_inst[Mod_id].RA_prach_resources.Msg3, + buflen, + rnti, + index); + Msg3_transmitted(Mod_id, 0, frame, 0); + // UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + // Modification + UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; + UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + } else { + ue_get_sdu(Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + ulsch_buffer, + buflen, + rnti, + index); + } + } + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE) { + uint8_t ulsch_buffer[5477] __attribute__((aligned(32))); + uint16_t buflen = ul_config_pdu->ulsch_cqi_harq_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.size; + nfapi_ul_config_ulsch_harq_information *ulsch_harq_information = + &ul_config_pdu->ulsch_cqi_harq_ri_pdu.harq_information; + uint16_t rnti = ul_config_pdu->ulsch_cqi_harq_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti; + uint8_t access_mode = SCHEDULED_ACCESS; + if (buflen > 0) { + if (UE_mac_inst[Mod_id].first_ULSCH_Tx == 1) { // Msg3 case + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + UE_mac_inst[Mod_id].RA_prach_resources.Msg3, + buflen, + rnti, + index); + Msg3_transmitted(Mod_id, 0, frame, 0); + // UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + // Modification + UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; + UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + } else { + ue_get_sdu(Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); + fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); + fill_rx_indication_UE_MAC(Mod_id, + frame, + subframe, + UL_INFO, + ulsch_buffer, + buflen, + rnti, + index); + } + } + + if (ulsch_harq_information != NULL) + fill_ulsch_harq_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_harq_information, rnti); + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE) { + uint16_t rnti = ul_config_pdu->uci_harq_pdu.ue_information.ue_information_rel8.rnti; + + nfapi_ul_config_harq_information *ulsch_harq_information = &ul_config_pdu->uci_harq_pdu.harq_information; + if (ulsch_harq_information != NULL) + fill_uci_harq_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_harq_information, rnti); + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_PDU_TYPE) { + AssertFatal(1 == 0, "NFAPI_UL_CONFIG_UCI_CQI_PDU_TYPE not handled yet\n"); + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_HARQ_PDU_TYPE) { + AssertFatal(1 == 0, + "NFAPI_UL_CONFIG_UCI_CQI_HARQ_PDU_TYPE not handled yet\n"); + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_SR_PDU_TYPE) { + AssertFatal(1 == 0, + "NFAPI_UL_CONFIG_UCI_CQI_SR_PDU_TYPE not handled yet\n"); + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_SR_PDU_TYPE) { + uint16_t rnti = + ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti; + + if (ue_get_SR(Mod_id, 0, frame, 0, rnti, subframe)) + fill_sr_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, rnti); + + } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_SR_HARQ_PDU_TYPE) { + // AssertFatal((UE_id = + // find_uci(rel8->rnti,proc->frame_tx,proc->subframe_tx,eNB,SEARCH_EXIST_OR_FREE))>=0, + // "No available UE UCI for rnti + // %x\n",ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti); + + uint16_t rnti = + ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti; + + // We fill the sr_indication only if ue_get_sr() would normally instruct PHY + // to send a SR. + if (ue_get_SR(Mod_id, 0, frame, 0, rnti, subframe)) + fill_sr_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, rnti); + + nfapi_ul_config_harq_information *ulsch_harq_information = + &ul_config_pdu->uci_sr_harq_pdu.harq_information; + if (ulsch_harq_information != NULL) + fill_uci_harq_indication_UE_MAC( + Mod_id, frame, subframe, UL_INFO, ulsch_harq_information, rnti); } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_RI_PDU_TYPE) { - uint8_t ulsch_buffer[5477] __attribute__ ((aligned(32))); - uint16_t buflen = ul_config_pdu->ulsch_cqi_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.size; - - uint16_t rnti = ul_config_pdu->ulsch_cqi_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti; - uint8_t access_mode=SCHEDULED_ACCESS; - if(buflen>0){ - if(UE_mac_inst[Mod_id].first_ULSCH_Tx == 1){ // Msg3 case - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, UE_mac_inst[Mod_id].RA_prach_resources.Msg3,buflen, rnti, index); - Msg3_transmitted(Mod_id, 0, frame, 0); - //UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - // Modification - UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; - UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - } - else { - ue_get_sdu( Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_buffer,buflen, rnti, index); - } - } - fill_ulsch_cqi_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, rnti); - - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE) { - - uint8_t ulsch_buffer[5477] __attribute__ ((aligned(32))); - uint16_t buflen = ul_config_pdu->ulsch_cqi_harq_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.size; - nfapi_ul_config_ulsch_harq_information *ulsch_harq_information = &ul_config_pdu->ulsch_cqi_harq_ri_pdu.harq_information; - - uint16_t rnti = ul_config_pdu->ulsch_cqi_harq_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti; - uint8_t access_mode=SCHEDULED_ACCESS; - if(buflen>0){ - if(UE_mac_inst[Mod_id].first_ULSCH_Tx == 1){ // Msg3 case - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, UE_mac_inst[Mod_id].RA_prach_resources.Msg3,buflen, rnti, index); - Msg3_transmitted(Mod_id, 0, frame, 0); - //UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - // Modification - UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; - UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - } - else { - ue_get_sdu( Mod_id, 0, frame, subframe, 0, ulsch_buffer, buflen, &access_mode); - fill_crc_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, 0, index, rnti); - fill_rx_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_buffer,buflen, rnti, index); - } - } - - if(ulsch_harq_information!=NULL) - fill_ulsch_harq_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, ulsch_harq_information, rnti); - fill_ulsch_cqi_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, rnti); - - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE) { - - uint16_t rnti = ul_config_pdu->uci_harq_pdu.ue_information.ue_information_rel8.rnti; - - nfapi_ul_config_harq_information *ulsch_harq_information = &ul_config_pdu->uci_harq_pdu.harq_information; - if(ulsch_harq_information != NULL) - fill_uci_harq_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO,ulsch_harq_information, rnti); - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_PDU_TYPE) { - AssertFatal(1==0,"NFAPI_UL_CONFIG_UCI_CQI_PDU_TYPE not handled yet\n"); - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_HARQ_PDU_TYPE) { - AssertFatal(1==0,"NFAPI_UL_CONFIG_UCI_CQI_HARQ_PDU_TYPE not handled yet\n"); - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_SR_PDU_TYPE) { - AssertFatal(1==0,"NFAPI_UL_CONFIG_UCI_CQI_SR_PDU_TYPE not handled yet\n"); - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_SR_PDU_TYPE) { - - uint16_t rnti = ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti; - - if (ue_get_SR(Mod_id ,0,frame, 0, rnti, subframe)) - fill_sr_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO, rnti); - - } - else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_SR_HARQ_PDU_TYPE) { - //AssertFatal((UE_id = find_uci(rel8->rnti,proc->frame_tx,proc->subframe_tx,eNB,SEARCH_EXIST_OR_FREE))>=0, - // "No available UE UCI for rnti %x\n",ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti); - - uint16_t rnti = ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti; - - // We fill the sr_indication only if ue_get_sr() would normally instruct PHY to send a SR. - if (ue_get_SR(Mod_id ,0,frame, 0, rnti, subframe)) - fill_sr_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO,rnti); - - nfapi_ul_config_harq_information *ulsch_harq_information = &ul_config_pdu->uci_sr_harq_pdu.harq_information; - if (ulsch_harq_information != NULL) - fill_uci_harq_indication_UE_MAC(Mod_id, frame, subframe, UL_INFO,ulsch_harq_information, rnti); - - } - } - - - - - -int ul_config_req_UE_MAC(nfapi_ul_config_request_t* req, int timer_frame, int timer_subframe, module_id_t Mod_id) -{ - //if (req!=NULL){ // && req->ul_config_request_body.ul_config_pdu_list !=NULL){ - LOG_D(PHY,"[PNF] UL_CONFIG_REQ %s() sfn_sf:%d pdu:%d rach_prach_frequency_resources:%d srs_present:%u\n", - __FUNCTION__, - NFAPI_SFNSF2DEC(req->sfn_sf), - req->ul_config_request_body.number_of_pdus, - req->ul_config_request_body.rach_prach_frequency_resources, - req->ul_config_request_body.srs_present - ); +int ul_config_req_UE_MAC(nfapi_ul_config_request_t *req, + int timer_frame, + int timer_subframe, + module_id_t Mod_id) { + LOG_D(PHY, + "[PNF] UL_CONFIG_REQ %s() sfn_sf:%d pdu:%d " + "rach_prach_frequency_resources:%d srs_present:%u\n", + __FUNCTION__, + NFAPI_SFNSF2DEC(req->sfn_sf), + req->ul_config_request_body.number_of_pdus, + req->ul_config_request_body.rach_prach_frequency_resources, + req->ul_config_request_body.srs_present); int sfn = NFAPI_SFNSF2SFN(req->sfn_sf); int sf = NFAPI_SFNSF2SF(req->sfn_sf); + LOG_D(MAC, + "ul_config_req_UE_MAC() TOTAL NUMBER OF UL_CONFIG PDUs: %d, SFN/SF: " + "%d/%d \n", + req->ul_config_request_body.number_of_pdus, + timer_frame, + timer_subframe); - LOG_D(MAC, "ul_config_req_UE_MAC() TOTAL NUMBER OF UL_CONFIG PDUs: %d, SFN/SF: %d/%d \n", req->ul_config_request_body.number_of_pdus, timer_frame, timer_subframe); - - - - for (int i=0;iul_config_request_body.number_of_pdus;i++) - { - - if ( - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].ulsch_pdu.ulsch_pdu_rel8.rnti == UE_mac_inst[Mod_id].crnti) || - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti == UE_mac_inst[Mod_id].crnti) || - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_RI_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].ulsch_cqi_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti == UE_mac_inst[Mod_id].crnti) || - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].ulsch_cqi_harq_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti == UE_mac_inst[Mod_id].crnti) || - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].uci_cqi_harq_pdu.ue_information.ue_information_rel8.rnti == UE_mac_inst[Mod_id].crnti) || - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_UCI_SR_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].uci_sr_pdu.ue_information.ue_information_rel8.rnti == UE_mac_inst[Mod_id].crnti) || - (req->ul_config_request_body.ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_UCI_SR_HARQ_PDU_TYPE && req->ul_config_request_body.ul_config_pdu_list[i].uci_cqi_sr_harq_pdu.ue_information.ue_information_rel8.rnti == UE_mac_inst[Mod_id].crnti) - ) - { - - handle_nfapi_ul_pdu_UE_MAC(Mod_id,&req->ul_config_request_body.ul_config_pdu_list[i],sfn,sf,req->ul_config_request_body.srs_present, i); - - } - else - { - //NFAPI_TRACE(NFAPI_TRACE_ERROR, "%s() PDU:%i UNKNOWN type :%d\n", __FUNCTION__, i, ul_config_pdu_list[i].pdu_type); + const rnti_t rnti = UE_mac_inst[Mod_id].crnti; + for (int i = 0; i < req->ul_config_request_body.number_of_pdus; i++) { + nfapi_ul_config_request_pdu_t* pdu = &req->ul_config_request_body.ul_config_pdu_list[i]; + const int pdu_type = pdu->pdu_type; + if ( (pdu_type == NFAPI_UL_CONFIG_ULSCH_PDU_TYPE + && pdu->ulsch_pdu.ulsch_pdu_rel8.rnti == rnti) + || (pdu_type == NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE + && pdu->ulsch_harq_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti == rnti) + || (pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_RI_PDU_TYPE + && pdu->ulsch_cqi_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti == rnti) + || (pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE + && pdu->ulsch_cqi_harq_ri_pdu.ulsch_pdu.ulsch_pdu_rel8.rnti == rnti) + || (pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE + && pdu->uci_cqi_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) + || (pdu_type == NFAPI_UL_CONFIG_UCI_SR_PDU_TYPE + && pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti == rnti) + || (pdu_type == NFAPI_UL_CONFIG_UCI_SR_HARQ_PDU_TYPE + && pdu->uci_cqi_sr_harq_pdu.ue_information.ue_information_rel8.rnti == rnti)) { + handle_nfapi_ul_pdu_UE_MAC( + Mod_id, pdu, sfn, sf, req->ul_config_request_body.srs_present, i); + } else { + // NFAPI_TRACE(NFAPI_TRACE_ERROR, "%s() PDU:%i UNKNOWN type :%d\n", + // __FUNCTION__, i, ul_config_pdu_list[i].pdu_type); } } -// } - return 0; } +int tx_req_UE_MAC(nfapi_tx_request_t *req) { + LOG_D(PHY, + "%s() SFN/SF:%d/%d PDUs:%d\n", + __FUNCTION__, + NFAPI_SFNSF2SFN(req->sfn_sf), + NFAPI_SFNSF2SF(req->sfn_sf), + req->tx_request_body.number_of_pdus); - -int tx_req_UE_MAC(nfapi_tx_request_t* req) -{ - - LOG_D(PHY,"%s() SFN/SF:%d/%d PDUs:%d\n", __FUNCTION__, NFAPI_SFNSF2SFN(req->sfn_sf), NFAPI_SFNSF2SF(req->sfn_sf), req->tx_request_body.number_of_pdus); - - - for (int i=0; itx_request_body.number_of_pdus; i++) - { - LOG_D(PHY,"%s() SFN/SF:%d/%d number_of_pdus:%d [PDU:%d] pdu_length:%d pdu_index:%d num_segments:%d\n", + for (int i = 0; i < req->tx_request_body.number_of_pdus; i++) { + LOG_D(PHY, + "%s() SFN/SF:%d/%d number_of_pdus:%d [PDU:%d] pdu_length:%d " + "pdu_index:%d num_segments:%d\n", __FUNCTION__, - NFAPI_SFNSF2SFN(req->sfn_sf), NFAPI_SFNSF2SF(req->sfn_sf), + NFAPI_SFNSF2SFN(req->sfn_sf), + NFAPI_SFNSF2SF(req->sfn_sf), req->tx_request_body.number_of_pdus, i, req->tx_request_body.tx_pdu_list[i].pdu_length, req->tx_request_body.tx_pdu_list[i].pdu_index, - req->tx_request_body.tx_pdu_list[i].num_segments - ); - - } + req->tx_request_body.tx_pdu_list[i].num_segments); + } return 0; } - -int dl_config_req_UE_MAC(nfapi_dl_config_request_t* req, module_id_t Mod_id) //, nfapi_tx_request_pdu_t* tx_request_pdu_list) -{ - //if (req!=NULL && tx_request_pdu_list!=NULL){ +int dl_config_req_UE_MAC(nfapi_dl_config_request_t* req, module_id_t Mod_id) { int sfn = NFAPI_SFNSF2SFN(req->sfn_sf); int sf = NFAPI_SFNSF2SF(req->sfn_sf); - //Mod_id = 0; // Currently static (only for one UE) but this should change. - /*struct PHY_VARS_eNB_s *eNB = RC.eNB[0][0]; - L1_rxtx_proc_t *proc = &eNB->proc.L1_proc;*/ nfapi_dl_config_request_pdu_t* dl_config_pdu_list = req->dl_config_request_body.dl_config_pdu_list; - nfapi_dl_config_request_pdu_t *dl_config_pdu_tmp; - //NFAPI_TRACE(NFAPI_TRACE_INFO, "%s() TX:%d/%d RX:%d/%d sfn_sf:%d DCI:%d PDU:%d\n", __FUNCTION__, proc->frame_tx, proc->subframe_tx, proc->frame_rx, proc->subframe_rx, NFAPI_SFNSF2DEC(req->sfn_sf), req->dl_config_request_body.number_dci, req->dl_config_request_body.number_pdu); - - - - //LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SF:%d%d dl_pdu:%d tx_req:%d hi_dci0:%d ul_cfg:%d num_pdcch_symbols:%d\n", - // frame,subframe,number_dl_pdu,TX_req->tx_request_body.number_of_pdus,number_hi_dci0_pdu,number_ul_pdu, eNB->pdcch_vars[subframe&1].num_pdcch_symbols); - - for (int i=0;idl_config_request_body.number_pdu;i++) - { - //NFAPI_TRACE(NFAPI_TRACE_INFO, "%s() sfn/sf:%d PDU[%d] size:%d\n", __FUNCTION__, NFAPI_SFNSF2DEC(req->sfn_sf), i, dl_config_pdu_list[i].pdu_size); - //LOG_E(MAC, "dl_config_req_UE_MAC 2 Received real ones: sfn/sf:%d.%d PDU[%d] size:%d\n", sfn, sf, i, dl_config_pdu_list[i].pdu_size); - - if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE) - { - if (dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti_type == 1) { - // C-RNTI (Normal DLSCH case) - dl_config_pdu_tmp = &dl_config_pdu_list[i+1]; - if (dl_config_pdu_tmp->pdu_type == NFAPI_DL_CONFIG_DLSCH_PDU_TYPE && UE_mac_inst[Mod_id].crnti == dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti){ - - /*nfapi_tx_request_pdu_t *ptr = tx_request_pdu_list; - ptr += dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index*(sizeof(nfapi_tx_request_pdu_t)); - nfapi_tx_request_pdu_t temp; - memset(&temp, 0, sizeof(nfapi_tx_request_pdu_t)); - //if (!memcmp(&temp, ptr, sizeof(temp)) ... - if( *(char*)ptr != 0){ - //if(tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data!= NULL && tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_length >0){ - */ - - // to avoid unexpected error , add check pdu_index is more than 0. - if((dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index >= 0) &&(dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index <= tx_req_num_elems -1)){ - //if(tx_request_pdu_list + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index!= NULL){ - - LOG_E(MAC, "dl_config_req_UE_MAC 2 Received data: sfn/sf:%d PDU[%d] size:%d, TX_PDU index: %d, tx_req_num_elems: %d \n", NFAPI_SFNSF2DEC(req->sfn_sf), i, dl_config_pdu_list[i].pdu_size, dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index, tx_req_num_elems); - - ue_send_sdu(Mod_id, 0, sfn, sf, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_length, - 0); - i++; - } - else{ - LOG_E(MAC,"dl_config_req_UE_MAC 2: Problem with receiving data: sfn/sf:%d PDU[%d] size:%d, TX_PDU index: %d\n", NFAPI_SFNSF2DEC(req->sfn_sf), i, dl_config_pdu_list[i].pdu_size, dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index); - i++; - } - } - else { - LOG_E(MAC,"[UE %d] Frame %d, subframe %d : DLSCH PDU from NFAPI not for this UE \n",Mod_id, sfn,sf); - i++; - } - } - else if (dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti_type == 2) { - dl_config_pdu_tmp = &dl_config_pdu_list[i+1]; - if(dl_config_pdu_tmp->pdu_type == NFAPI_DL_CONFIG_DLSCH_PDU_TYPE && dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti == 0xFFFF && UE_mac_inst[Mod_id].UE_mode[0] != NOT_SYNCHED){ //&& UE_mac_inst[Mod_id].UE_mode[0] != NOT_SYNCHED - - if(dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index <= tx_req_num_elems -1){ - //if(tx_request_pdu_list + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index!= NULL){ - ue_decode_si(Mod_id, 0, sfn, 0, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_length); - i++; - } - else{ - LOG_E(MAC,"dl_config_req_UE_MAC 3: Problem with receiving SI: sfn/sf:%d PDU[%d] size:%d, TX_PDU index: %d\n", NFAPI_SFNSF2DEC(req->sfn_sf), i, dl_config_pdu_list[i].pdu_size, dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index); - i++; - } - } - else if(dl_config_pdu_tmp->pdu_type == NFAPI_DL_CONFIG_DLSCH_PDU_TYPE && dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti == 0xFFFE){ - // P_RNTI case - //pdu = Tx_req->tx_request_body.tx_pdu_list[dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data; - - if (dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index <= tx_req_num_elems -1){ - //if(tx_request_pdu_list + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index!= NULL){ - ue_decode_p(Mod_id, 0, sfn, 0, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_length); - i++; - } - else{ - LOG_E(MAC,"dl_config_req_UE_MAC: Problem with receiving Paging: sfn/sf:%d PDU[%d] size:%d, TX_PDU index: %d\n", NFAPI_SFNSF2DEC(req->sfn_sf), i, dl_config_pdu_list[i].pdu_size, dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index); - i++; - } - } - else if(dl_config_pdu_tmp->pdu_type == NFAPI_DL_CONFIG_DLSCH_PDU_TYPE) { - // RA-RNTI case - LOG_E(MAC,"dl_config_req_UE_MAC 4 Received RAR? \n"); - // RNTI parameter not actually used. Provided only to comply with existing function definition. - // Not sure about parameters to fill the preamble index. - //rnti_t c_rnti = UE_mac_inst[Mod_id].crnti; - rnti_t ra_rnti = UE_mac_inst[Mod_id].RA_prach_resources.ra_RNTI; - if ((UE_mac_inst[Mod_id].UE_mode[0] != PUSCH) && - (UE_mac_inst[Mod_id].RA_prach_resources.Msg3!=NULL) && (ra_rnti== dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti) && - //(tx_request_pdu_list + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index!= NULL)) { - (dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index <= tx_req_num_elems -1)) { - LOG_E(MAC,"dl_config_req_UE_MAC 5 Received RAR, PreambleIndex: %d \n", UE_mac_inst[Mod_id].RA_prach_resources.ra_PreambleIndex); - ue_process_rar(Mod_id, 0, sfn, - ra_rnti, //RA-RNTI - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data, - &dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti, //t-crnti - UE_mac_inst[Mod_id].RA_prach_resources.ra_PreambleIndex, - tx_request_pdu_list[dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index].segments[0].segment_data); - UE_mac_inst[Mod_id].UE_mode[0] = RA_RESPONSE; - UE_mac_inst[Mod_id].first_ULSCH_Tx = 1; //Expecting an UL_CONFIG_ULSCH_PDU to enable Msg3 Txon (first ULSCH Txon for the UE) - } - i++; - } - else { - LOG_E(MAC,"[UE %d] Frame %d, subframe %d : Cannot extract DLSCH PDU from NFAPI 2\n",Mod_id, sfn, sf); - i++; - } - - } - } - else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE) - { - // BCH case - // Last parameter is 1 if first time synchronization and zero otherwise. Not sure which value to put - // for our case. - //LOG_E(MAC,"dl_config_req_UE_MAC 4 Received MIB: sfn/sf: %d.%d \n", sfn, sf); - if(UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED){ - dl_phy_sync_success(Mod_id,sfn,0, 1); - LOG_E(MAC,"dl_config_req_UE_MAC 5 Received MIB: UE_mode: %d, sfn/sf: %d.%d\n", UE_mac_inst[Mod_id].UE_mode[0], sfn, sf); - UE_mac_inst[Mod_id].UE_mode[0]=PRACH; - } - else - dl_phy_sync_success(Mod_id,sfn,0, 0); - - } - - else - { - //NFAPI_TRACE(NFAPI_TRACE_ERROR, "%s() UNKNOWN:%d\n", __FUNCTION__, dl_config_pdu_list[i].pdu_type); - } - } - - return 0; - -} - - -int hi_dci0_req_UE_MAC(nfapi_hi_dci0_request_t* req, module_id_t Mod_id) -{ - if (req!=NULL && req->hi_dci0_request_body.hi_dci0_pdu_list!=NULL){ - LOG_D(PHY,"[UE-PHY_STUB] hi dci0 request sfn_sf:%d number_of_dci:%d number_of_hi:%d\n", NFAPI_SFNSF2DEC(req->sfn_sf), req->hi_dci0_request_body.number_of_dci, req->hi_dci0_request_body.number_of_hi); - - - - for (int i=0; ihi_dci0_request_body.number_of_dci + req->hi_dci0_request_body.number_of_hi; i++) - { - LOG_D(PHY,"[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d]\n", NFAPI_SFNSF2DEC(req->sfn_sf), i); - - if (req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type == NFAPI_HI_DCI0_DCI_PDU_TYPE) - { - LOG_D(PHY,"[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - NFAPI_HI_DCI0_DCI_PDU_TYPE not used \n", NFAPI_SFNSF2DEC(req->sfn_sf), i); - - } - else if (req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type == NFAPI_HI_DCI0_HI_PDU_TYPE) - { - //LOG_I(MAC,"[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - NFAPI_HI_DCI0_HI_PDU_TYPE\n", NFAPI_SFNSF2DEC(req->sfn_sf), i); - - nfapi_hi_dci0_request_pdu_t *hi_dci0_req_pdu = &req->hi_dci0_request_body.hi_dci0_pdu_list[i]; - - // This is meaningful only after ACKnowledging the first ULSCH Txon (i.e. Msg3) - if(hi_dci0_req_pdu->hi_pdu.hi_pdu_rel8.hi_value == 1 && UE_mac_inst[Mod_id].first_ULSCH_Tx == 1){ - //LOG_I(MAC,"[UE-PHY_STUB] HI_DCI0_REQ 2 sfn_sf:%d PDU[%d] - NFAPI_HI_DCI0_HI_PDU_TYPE\n", NFAPI_SFNSF2DEC(req->sfn_sf), i); - //UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; - //UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + for (int i = 0; i < req->dl_config_request_body.number_pdu; i++) { + if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE) { + const rnti_t rnti = dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti; + const int rnti_type = dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti_type; + /* We assume the DCI DL PDU is followed by the DLSCH (the standard is + * more free), so advance by one more and directly process the + * following DLSCH PDU */ + i++; + AssertFatal(i < req->dl_config_request_body.number_pdu, + "Need PDU following DCI at index %d, but not found\n", + i); + nfapi_dl_config_request_pdu_t *dl_config_pdu_tmp = &dl_config_pdu_list[i]; + if (dl_config_pdu_tmp->pdu_type != NFAPI_DL_CONFIG_DLSCH_PDU_TYPE) { + LOG_E(MAC, "expected DLSCH PDU at index %d\n", i); + continue; } + if (rnti != dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti) { + LOG_I(MAC, + "%s(): sfn/sf %d DLSCH PDU RNTI %x does not match DCI RNTI %x\n", + __func__, + NFAPI_SFNSF2DEC(req->sfn_sf), + rnti, + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti); + continue; + } + const int pdu_index = dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index; + if (pdu_index < 0 && pdu_index >= tx_req_num_elems) { + LOG_E(MAC, + "dl_config_req_UE_MAC 2: Problem with receiving data: " + "sfn/sf:%d PDU[%d] size:%d, TX_PDU index: %d\n", + NFAPI_SFNSF2DEC(req->sfn_sf), + i, + dl_config_pdu_list[i].pdu_size, + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index); + continue; + } + if (rnti_type == 1) { + // C-RNTI (Normal DLSCH case) + if (UE_mac_inst[Mod_id].crnti != rnti) { + LOG_D(MAC, + "sfn/sf %d/%d DCI not for UE %d/RNTI %x but for RNTI %x, " + "skipping\n", + sfn, sf, Mod_id, UE_mac_inst[Mod_id].crnti, rnti); + continue; + } - } - else - { - LOG_E(PHY,"[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - unknown pdu type:%d\n", NFAPI_SFNSF2DEC(req->sfn_sf), i, req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type); + LOG_D(MAC, + "%s() Received data: sfn/sf:%d PDU[%d] " + "size:%d, TX_PDU index: %d, tx_req_num_elems: %d \n", + __func__, + NFAPI_SFNSF2DEC(req->sfn_sf), + i, + dl_config_pdu_list[i].pdu_size, + dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index, + tx_req_num_elems); + ue_send_sdu(Mod_id, 0, sfn, sf, + tx_request_pdu_list[pdu_index].segments[0].segment_data, + tx_request_pdu_list[pdu_index].segments[0].segment_length, + 0); + } else if (rnti_type == 2) { + if (rnti == 0xFFFF) { /* SI-RNTI */ + if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED) { + /* this check is in the code before refactoring, but I don't know + * why. Leave it in here for the moment */ + continue; + } + + ue_decode_si(Mod_id, 0, sfn, 0, + tx_request_pdu_list[pdu_index].segments[0].segment_data, + tx_request_pdu_list[pdu_index].segments[0].segment_length); + } else if (rnti == 0xFFFE) { /* PI-RNTI */ + LOG_I(MAC, "%s() Received paging message: sfn/sf:%d PDU[%d]\n", + __func__, NFAPI_SFNSF2DEC(req->sfn_sf), i); + ue_decode_p(Mod_id, 0, sfn, 0, + tx_request_pdu_list[pdu_index].segments[0].segment_data, + tx_request_pdu_list[pdu_index].segments[0].segment_length); + } else if (rnti == 0x0002) { /* RA-RNTI */ + LOG_E(MAC, "%s(): Received RAR?\n", __func__); + // RNTI parameter not actually used. Provided only to comply with + // existing function definition. Not sure about parameters to fill + // the preamble index. + const rnti_t ra_rnti = UE_mac_inst[Mod_id].RA_prach_resources.ra_RNTI; + DevAssert(ra_rnti == 0x0002); + if (UE_mac_inst[Mod_id].UE_mode[0] != PUSCH + && UE_mac_inst[Mod_id].RA_prach_resources.Msg3 != NULL + && ra_rnti == dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti) { + LOG_E(MAC, + "dl_config_req_UE_MAC 5 Received RAR, PreambleIndex: %d \n", + UE_mac_inst[Mod_id].RA_prach_resources.ra_PreambleIndex); + ue_process_rar(Mod_id, 0, sfn, + ra_rnti, //RA-RNTI + tx_request_pdu_list[pdu_index].segments[0].segment_data, + &dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti, //t-crnti + UE_mac_inst[Mod_id].RA_prach_resources.ra_PreambleIndex, + tx_request_pdu_list[pdu_index].segments[0].segment_data); + UE_mac_inst[Mod_id].UE_mode[0] = RA_RESPONSE; + // Expecting an UL_CONFIG_ULSCH_PDU to enable Msg3 Txon (first + // ULSCH Txon for the UE) + UE_mac_inst[Mod_id].first_ULSCH_Tx = 1; + } + } else { + LOG_W(MAC, "can not handle special RNTI %x\n", rnti); + } + } + } else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE) { + // BCH case: Last parameter is 1 if first time synchronization and zero + // otherwise. Not sure which value to put for our case. + if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED){ + dl_phy_sync_success(Mod_id, sfn, 0, 1); + LOG_E(MAC, + "%s(): Received MIB: UE_mode: %d, sfn/sf: %d.%d\n", + __func__, + UE_mac_inst[Mod_id].UE_mode[0], + sfn, + sf); + UE_mac_inst[Mod_id].UE_mode[0] = PRACH; + } else { + dl_phy_sync_success(Mod_id, sfn, 0, 0); + } } } + return 0; +} +int hi_dci0_req_UE_MAC(nfapi_hi_dci0_request_t *req, module_id_t Mod_id) { + if (req != NULL && req->hi_dci0_request_body.hi_dci0_pdu_list != NULL) { + LOG_D(PHY, + "[UE-PHY_STUB] hi dci0 request sfn_sf:%d number_of_dci:%d " + "number_of_hi:%d\n", + NFAPI_SFNSF2DEC(req->sfn_sf), + req->hi_dci0_request_body.number_of_dci, + req->hi_dci0_request_body.number_of_hi); + + for (int i = 0; i < req->hi_dci0_request_body.number_of_dci + + req->hi_dci0_request_body.number_of_hi; + i++) { + LOG_D(PHY, + "[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d]\n", + NFAPI_SFNSF2DEC(req->sfn_sf), + i); + + if (req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type + == NFAPI_HI_DCI0_DCI_PDU_TYPE) { + LOG_D(PHY, + "[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - " + "NFAPI_HI_DCI0_DCI_PDU_TYPE\n", + NFAPI_SFNSF2DEC(req->sfn_sf), + i); + const nfapi_hi_dci0_dci_pdu_rel8_t *dci = + &req->hi_dci0_request_body.hi_dci0_pdu_list[i].dci_pdu.dci_pdu_rel8; + if (dci->rnti != UE_mac_inst[Mod_id].crnti) + continue; + const int sfn = NFAPI_SFNSF2SFN(req->sfn_sf); + const int sf = NFAPI_SFNSF2SF(req->sfn_sf); + if (dci->cqi_csi_request) + fill_ulsch_cqi_indication_UE_MAC(Mod_id, sfn, sf, UL_INFO, dci->rnti); + } else if (req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type + == NFAPI_HI_DCI0_HI_PDU_TYPE) { + nfapi_hi_dci0_request_pdu_t *hi_dci0_req_pdu = + &req->hi_dci0_request_body.hi_dci0_pdu_list[i]; + + // This is meaningful only after ACKnowledging the first ULSCH Txon + // (i.e. Msg3) + if (hi_dci0_req_pdu->hi_pdu.hi_pdu_rel8.hi_value == 1 + && UE_mac_inst[Mod_id].first_ULSCH_Tx == 1) { + // LOG_I(MAC,"[UE-PHY_STUB] HI_DCI0_REQ 2 sfn_sf:%d PDU[%d] - + // NFAPI_HI_DCI0_HI_PDU_TYPE\n", NFAPI_SFNSF2DEC(req->sfn_sf), i); + // UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; + // UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; + } + + } else { + LOG_E(PHY, + "[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - unknown pdu " + "type:%d\n", + NFAPI_SFNSF2DEC(req->sfn_sf), + i, + req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type); + } + } } - return 0; } +// The following set of memcpy functions should be getting called as callback +// functions from pnf_p7_subframe_ind. +int memcpy_dl_config_req(nfapi_pnf_p7_config_t *pnf_p7, + nfapi_dl_config_request_t *req) { + dl_config_req = (nfapi_dl_config_request_t *)malloc(sizeof(nfapi_dl_config_request_t)); + // UE_mac_inst[Mod_id].dl_config_req->header = req->header; + dl_config_req->sfn_sf = req->sfn_sf; + dl_config_req->vendor_extension = req->vendor_extension; + dl_config_req->dl_config_request_body.number_dci = req->dl_config_request_body.number_dci; + dl_config_req->dl_config_request_body.number_pdcch_ofdm_symbols = req->dl_config_request_body.number_pdcch_ofdm_symbols; + dl_config_req->dl_config_request_body.number_pdsch_rnti = req->dl_config_request_body.number_pdsch_rnti; + dl_config_req->dl_config_request_body.number_pdu = req->dl_config_request_body.number_pdu; -// The following set of memcpy functions should be getting called as callback functions from -// pnf_p7_subframe_ind. -int memcpy_dl_config_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_dl_config_request_t* req) -{ + dl_config_req->dl_config_request_body.tl.tag = req->dl_config_request_body.tl.tag; + dl_config_req->dl_config_request_body.tl.length = req->dl_config_request_body.tl.length; - //for (Mod_id=0; Mod_idheader = req->header; - dl_config_req->sfn_sf = req->sfn_sf; - - dl_config_req->vendor_extension = req->vendor_extension; - - dl_config_req->dl_config_request_body.number_dci = req->dl_config_request_body.number_dci; - dl_config_req->dl_config_request_body.number_pdcch_ofdm_symbols = req->dl_config_request_body.number_pdcch_ofdm_symbols; - dl_config_req->dl_config_request_body.number_pdsch_rnti = req->dl_config_request_body.number_pdsch_rnti; - dl_config_req->dl_config_request_body.number_pdu = req->dl_config_request_body.number_pdu; - - dl_config_req->dl_config_request_body.tl.tag = req->dl_config_request_body.tl.tag; - dl_config_req->dl_config_request_body.tl.length = req->dl_config_request_body.tl.length; - - dl_config_req->dl_config_request_body.dl_config_pdu_list = (nfapi_dl_config_request_pdu_t*) calloc(req->dl_config_request_body.number_pdu, sizeof(nfapi_dl_config_request_pdu_t)); - for(int i=0; idl_config_request_body.number_pdu; i++) { - dl_config_req->dl_config_request_body.dl_config_pdu_list[i] = req->dl_config_request_body.dl_config_pdu_list[i]; - } - - //} - - return 0; + dl_config_req->dl_config_request_body.dl_config_pdu_list = + calloc(req->dl_config_request_body.number_pdu, + sizeof(nfapi_dl_config_request_pdu_t)); + for (int i = 0; i < dl_config_req->dl_config_request_body.number_pdu; i++) { + dl_config_req->dl_config_request_body.dl_config_pdu_list[i] = + req->dl_config_request_body.dl_config_pdu_list[i]; + } + return 0; } -int memcpy_ul_config_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_ul_config_request_t* req) -{ +int memcpy_ul_config_req(nfapi_pnf_p7_config_t *pnf_p7, + nfapi_ul_config_request_t *req) { + ul_config_req = malloc(sizeof(nfapi_ul_config_request_t)); - //for (Mod_id=0; Mod_idsfn_sf = req->sfn_sf; + ul_config_req->vendor_extension = req->vendor_extension; - ul_config_req = (nfapi_ul_config_request_t*)malloc(sizeof(nfapi_ul_config_request_t)); + ul_config_req->ul_config_request_body.number_of_pdus = req->ul_config_request_body.number_of_pdus; + ul_config_req->ul_config_request_body.rach_prach_frequency_resources = req->ul_config_request_body.rach_prach_frequency_resources; + ul_config_req->ul_config_request_body.srs_present = req->ul_config_request_body.srs_present; - ul_config_req->sfn_sf = req->sfn_sf; - ul_config_req->vendor_extension = req->vendor_extension; + ul_config_req->ul_config_request_body.tl.tag = req->ul_config_request_body.tl.tag; + ul_config_req->ul_config_request_body.tl.length = req->ul_config_request_body.tl.length; + ul_config_req->ul_config_request_body.ul_config_pdu_list = + calloc(req->ul_config_request_body.number_of_pdus, + sizeof(nfapi_ul_config_request_pdu_t)); + for (int i = 0; i < ul_config_req->ul_config_request_body.number_of_pdus; i++) { + ul_config_req->ul_config_request_body.ul_config_pdu_list[i] = + req->ul_config_request_body.ul_config_pdu_list[i]; + } - ul_config_req->ul_config_request_body.number_of_pdus = req->ul_config_request_body.number_of_pdus; - ul_config_req->ul_config_request_body.rach_prach_frequency_resources = req->ul_config_request_body.rach_prach_frequency_resources; - ul_config_req->ul_config_request_body.srs_present = req->ul_config_request_body.srs_present; - - ul_config_req->ul_config_request_body.tl.tag = req->ul_config_request_body.tl.tag; - ul_config_req->ul_config_request_body.tl.length = req->ul_config_request_body.tl.length; - - //LOG_D(MAC, "memcpy_ul_config_req 1 #ofULPDUs: %d \n", UE_mac_inst[Mod_id].ul_config_req->ul_config_request_body.number_of_pdus); //req->ul_config_request_body.number_of_pdus); - ul_config_req->ul_config_request_body.ul_config_pdu_list = (nfapi_ul_config_request_pdu_t*) malloc(req->ul_config_request_body.number_of_pdus*sizeof(nfapi_ul_config_request_pdu_t)); - for(int i=0; iul_config_request_body.number_of_pdus; i++) { - ul_config_req->ul_config_request_body.ul_config_pdu_list[i] = req->ul_config_request_body.ul_config_pdu_list[i]; - } - //} - - return 0; + return 0; } +int memcpy_tx_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_tx_request_t *req) { + tx_req_num_elems = req->tx_request_body.number_of_pdus; + tx_request_pdu_list = calloc(tx_req_num_elems, sizeof(nfapi_tx_request_pdu_t)); + for (int i = 0; i < tx_req_num_elems; i++) { + tx_request_pdu_list[i].num_segments = req->tx_request_body.tx_pdu_list[i].num_segments; + tx_request_pdu_list[i].pdu_index = req->tx_request_body.tx_pdu_list[i].pdu_index; + tx_request_pdu_list[i].pdu_length = req->tx_request_body.tx_pdu_list[i].pdu_length; + for (int j = 0; j < req->tx_request_body.tx_pdu_list[i].num_segments; j++) { + tx_request_pdu_list[i].segments[j].segment_length = req->tx_request_body.tx_pdu_list[i].segments[j].segment_length; + if (tx_request_pdu_list[i].segments[j].segment_length > 0) { + tx_request_pdu_list[i].segments[j].segment_data = calloc( + tx_request_pdu_list[i].segments[j].segment_length, sizeof(uint8_t)); + memcpy(tx_request_pdu_list[i].segments[j].segment_data, + req->tx_request_body.tx_pdu_list[i].segments[j].segment_data, + tx_request_pdu_list[i].segments[j].segment_length); + } + } + } - - -int memcpy_tx_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_tx_request_t* req) -{ - - tx_req_num_elems = req->tx_request_body.number_of_pdus; - tx_request_pdu_list = (nfapi_tx_request_pdu_t*) calloc(tx_req_num_elems, sizeof(nfapi_tx_request_pdu_t)); - for (int i=0; itx_request_body.tx_pdu_list[i].num_segments; - tx_request_pdu_list[i].pdu_index = req->tx_request_body.tx_pdu_list[i].pdu_index; - tx_request_pdu_list[i].pdu_length = req->tx_request_body.tx_pdu_list[i].pdu_length; - for (int j=0; jtx_request_body.tx_pdu_list[i].num_segments; j++){ - //*tx_request_pdu_list[i].segments[j].segment_data = *req->tx_request_body.tx_pdu_list[i].segments[j].segment_data; - tx_request_pdu_list[i].segments[j].segment_length = req->tx_request_body.tx_pdu_list[i].segments[j].segment_length; - if(tx_request_pdu_list[i].segments[j].segment_length > 0){ - tx_request_pdu_list[i].segments[j].segment_data = (uint8_t*)malloc(tx_request_pdu_list[i].segments[j].segment_length*sizeof (uint8_t)); - memcpy(tx_request_pdu_list[i].segments[j].segment_data, req->tx_request_body.tx_pdu_list[i].segments[j].segment_data, tx_request_pdu_list[i].segments[j].segment_length); - } - } - - } - - return 0; + return 0; } -int memcpy_hi_dci0_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_hi_dci0_request_t* req) -{ +int memcpy_hi_dci0_req(nfapi_pnf_p7_config_t *pnf_p7, + nfapi_hi_dci0_request_t *req) { + hi_dci0_req = (nfapi_hi_dci0_request_t *)malloc(sizeof(nfapi_hi_dci0_request_t)); - //if(req!=0){ + hi_dci0_req->sfn_sf = req->sfn_sf; + hi_dci0_req->vendor_extension = req->vendor_extension; - //for (Mod_id=0; Mod_idhi_dci0_request_body.number_of_dci = req->hi_dci0_request_body.number_of_dci; + hi_dci0_req->hi_dci0_request_body.number_of_hi = req->hi_dci0_request_body.number_of_hi; + hi_dci0_req->hi_dci0_request_body.sfnsf = req->hi_dci0_request_body.sfnsf; - hi_dci0_req->sfn_sf = req->sfn_sf; - hi_dci0_req->vendor_extension = req->vendor_extension; + // UE_mac_inst[Mod_id].hi_dci0_req->hi_dci0_request_body.tl = + // req->hi_dci0_request_body.tl; + hi_dci0_req->hi_dci0_request_body.tl.tag = req->hi_dci0_request_body.tl.tag; + hi_dci0_req->hi_dci0_request_body.tl.length = req->hi_dci0_request_body.tl.length; - hi_dci0_req->hi_dci0_request_body.number_of_dci = req->hi_dci0_request_body.number_of_dci; - hi_dci0_req->hi_dci0_request_body.number_of_hi = req->hi_dci0_request_body.number_of_hi; - hi_dci0_req->hi_dci0_request_body.sfnsf = req->hi_dci0_request_body.sfnsf; + int total_pdus = hi_dci0_req->hi_dci0_request_body.number_of_dci + + hi_dci0_req->hi_dci0_request_body.number_of_hi; - //UE_mac_inst[Mod_id].hi_dci0_req->hi_dci0_request_body.tl = req->hi_dci0_request_body.tl; - hi_dci0_req->hi_dci0_request_body.tl.tag = req->hi_dci0_request_body.tl.tag; - hi_dci0_req->hi_dci0_request_body.tl.length = req->hi_dci0_request_body.tl.length; + hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list = + calloc(total_pdus, sizeof(nfapi_hi_dci0_request_pdu_t)); - int total_pdus = hi_dci0_req->hi_dci0_request_body.number_of_dci + hi_dci0_req->hi_dci0_request_body.number_of_hi; - - hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list = (nfapi_hi_dci0_request_pdu_t*) malloc(total_pdus*sizeof(nfapi_hi_dci0_request_pdu_t)); - - for(int i=0; ihi_dci0_request_body.hi_dci0_pdu_list[i] = req->hi_dci0_request_body.hi_dci0_pdu_list[i]; - //LOG_I(MAC, "Original hi_dci0 req. type:%d, Copy type: %d \n",req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type, UE_mac_inst[Mod_id].hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type); - } - - //} - return 0; + for (int i = 0; i < total_pdus; i++) { + hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list[i] = req->hi_dci0_request_body.hi_dci0_pdu_list[i]; + // LOG_I(MAC, "Original hi_dci0 req. type:%d, Copy type: %d + // \n",req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type, + // UE_mac_inst[Mod_id].hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type); + } + return 0; } - - void UE_config_stub_pnf(void) { - int j; + int j; paramdef_t L1_Params[] = L1PARAMS_DESC; - paramlist_def_t L1_ParamList = {CONFIG_STRING_L1_LIST,NULL,0}; + paramlist_def_t L1_ParamList = {CONFIG_STRING_L1_LIST, NULL, 0}; - config_getlist( &L1_ParamList,L1_Params,sizeof(L1_Params)/sizeof(paramdef_t), NULL); + config_getlist(&L1_ParamList, L1_Params, sizeof(L1_Params) / sizeof(paramdef_t), NULL); if (L1_ParamList.numelt > 0) { - for (j=0; jnonCriticalExtension = &r8_a0; + r8_a0.nonCriticalExtension = &r11_80; + r11_80.nonCriticalExtension = &r13_10; + r13_10.nonCriticalExtension = &r14_30; + r14_30.nonCriticalExtension = &r15_10; + + /* TODO: no hardcoded values here */ + + OCTET_STRING_t req_freq; + //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78 + //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x08, 0x18 }; // bands 7 & nr260 + + //unsigned char req_freq_buf[13] = { 0x00, 0xc0, 0x18, 0x01, 0x01, 0x30, 0x4b, 0x04, 0x0e, 0x08, 0x24, 0x04, 0xd0 }; + unsigned char req_freq_buf[21] = { +0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a + }; + + req_freq.buf = req_freq_buf; + req_freq.size = 5; + req_freq.size = 21; + + r15_10.requestedFreqBandsNR_MRDC_r15 = &req_freq; + + if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + xer_fprint(stdout, &asn_DEF_LTE_DL_DCCH_Message, (void *)&dl_dcch_msg); + } + + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_DL_DCCH_Message, + NULL, + (void *)&dl_dcch_msg, + buffer, + 100); + + if(enc_rval.encoded == -1) { + LOG_I(RRC, "[eNB AssertFatal]ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + return -1; + } + + LOG_D(RRC,"[eNB %d] NR UECapabilityRequest for UE %x Encoded %zd bits (%zd bytes)\n", + ctxt_pP->module_id, + ctxt_pP->rnti, + enc_rval.encoded, + (enc_rval.encoded+7)/8); + + if (enc_rval.encoded==-1) { + LOG_E(RRC,"[eNB %d] ASN1 : NR UECapabilityRequest encoding failed for UE %x\n", + ctxt_pP->module_id, + ctxt_pP->rnti); + return(-1); + } + + return((enc_rval.encoded+7)/8); +} + uint16_t do_RRCConnectionReconfiguration_BR(const protocol_ctxt_t *const ctxt_pP, uint8_t *buffer, diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.h b/openair2/RRC/LTE/MESSAGES/asn1_msg.h index ccd5e1c537..dda2340610 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.h +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.h @@ -358,6 +358,13 @@ do_UECapabilityEnquiry( const uint8_t Transaction_id ); +uint8_t +do_NR_UECapabilityEnquiry( + const protocol_ctxt_t *const ctxt_pP, + uint8_t *const buffer, + const uint8_t Transaction_id +); + uint8_t do_SecurityModeCommand( const protocol_ctxt_t *const ctxt_pP, uint8_t *const buffer, diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index ad51927caa..f050733a13 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -92,6 +92,7 @@ #define PC5_DISCOVERY_PAYLOAD_SIZE 29 +#define DEBUG_SCG_CONFIG 1 typedef enum { UE_STATE_OFF_NETWORK, @@ -264,7 +265,8 @@ typedef enum UE_STATE_e { RRC_SI_RECEIVED, RRC_CONNECTED, RRC_RECONFIGURED, - RRC_HO_EXECUTION + RRC_HO_EXECUTION, + RRC_NR_NSA, } UE_STATE_t; typedef enum HO_STATE_e { @@ -644,6 +646,8 @@ typedef struct eNB_RRC_UE_s { uint32_t ue_rrc_inactivity_timer; uint8_t e_rab_release_command_flag; int8_t reestablishment_xid; + int does_nr; + int nr_capabilities_requested; } eNB_RRC_UE_t; typedef uid_t ue_uid_t; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index a91e6fcd00..1d25bf180a 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -113,6 +113,8 @@ extern uint32_t to_earfcn_DL(int eutra_bandP, uint32_t dl_CarrierFreq, uint32_t extern int rrc_eNB_process_security(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, security_capabilities_t *security_capabilities_pP); extern void process_eNB_security_key (const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, uint8_t *security_key_pP); extern int derive_keNB_star(const uint8_t *kenb_32, const uint16_t pci, const uint32_t earfcn_dl, const bool is_rel8_only, uint8_t *kenb_star); +extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, OCTET_STRING_t *scg_RB_config); +extern struct rrc_eNB_ue_context_s * get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); pthread_mutex_t rrc_release_freelist; RRC_release_list_t rrc_release_info; @@ -1277,6 +1279,52 @@ rrc_eNB_generate_UECapabilityEnquiry( PDCP_TRANSMISSION_MODE_CONTROL); } +//----------------------------------------------------------------------------- +void +rrc_eNB_generate_NR_UECapabilityEnquiry( + const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP +) +//----------------------------------------------------------------------------- +{ + uint8_t buffer[100]; + uint8_t size; + T(T_ENB_RRC_UE_CAPABILITY_ENQUIRY, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), + T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); + size = do_NR_UECapabilityEnquiry( + ctxt_pP, + buffer, + rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); + LOG_I(RRC, + PROTOCOL_RRC_CTXT_UE_FMT" Logical Channel DL-DCCH, Generate NR UECapabilityEnquiry (bytes %d)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + size); + LOG_D(RRC, + PROTOCOL_RRC_CTXT_UE_FMT" --- PDCP_DATA_REQ/%d Bytes (NR UECapabilityEnquiry MUI %d) --->[PDCP][RB %02d]\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + size, + rrc_eNB_mui, + DCCH); + MSC_LOG_TX_MESSAGE( + MSC_RRC_ENB, + MSC_RRC_UE, + buffer, + size, + MSC_AS_TIME_FMT" rrcNRUECapabilityEnquiry UE %x MUI %d size %u", + MSC_AS_TIME_ARGS(ctxt_pP), + ue_context_pP->ue_context.rnti, + rrc_eNB_mui, + size); + rrc_data_req( + ctxt_pP, + DCCH, + rrc_eNB_mui++, + SDU_CONFIRM_NO, + size, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); +} + //----------------------------------------------------------------------------- void rrc_eNB_generate_RRCConnectionReject( @@ -2808,11 +2856,14 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t LTE_MAC_MainConfig_t *mac_MainConfig = NULL; LTE_MeasObjectToAddModList_t *MeasObj_list = NULL; LTE_MeasObjectToAddMod_t *MeasObj = NULL; + LTE_MeasObjectToAddMod_t *MeasObj2 = NULL; LTE_ReportConfigToAddModList_t *ReportConfig_list = NULL; LTE_ReportConfigToAddMod_t *ReportConfig_per, *ReportConfig_A1, *ReportConfig_A2, *ReportConfig_A3, *ReportConfig_A4, *ReportConfig_A5; + LTE_ReportConfigToAddMod_t *ReportConfig_NR = NULL; LTE_MeasIdToAddModList_t *MeasId_list = NULL; LTE_MeasIdToAddMod_t *MeasId0, *MeasId1, *MeasId2, *MeasId3, *MeasId4, *MeasId5; + LTE_MeasIdToAddMod_t *MeasId6; long *sr_ProhibitTimer_r9 = NULL; long *logicalchannelgroup = NULL; long *logicalchannelgroup_drb = NULL; @@ -3094,6 +3145,16 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t MeasId5->measObjectId = 1; MeasId5->reportConfigId = 6; ASN_SEQUENCE_ADD(&MeasId_list->list, MeasId5); + + if (ue_context_pP->ue_context.does_nr) { + MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t)); + if (MeasId6 == NULL) exit(1); + MeasId6->measId = 7; + MeasId6->measObjectId = 2; + MeasId6->reportConfigId = 7; + ASN_SEQUENCE_ADD(&MeasId_list->list, MeasId6); + } + // LTE_RRCConnectionReconfiguration->criticalExtensions.choice.c1.choice.rrcConnectionReconfiguration_r8.measConfig->measIdToAddModList = MeasId_list; // Add one EUTRA Measurement Object MeasObj_list = CALLOC(1, sizeof(*MeasObj_list)); @@ -3143,6 +3204,27 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ASN_SEQUENCE_ADD(&MeasObj_list->list, MeasObj); // LTE_RRCConnectionReconfiguration->criticalExtensions.choice.c1.choice.rrcConnectionReconfiguration_r8.measConfig->measObjectToAddModList = MeasObj_list; + if (ue_context_pP->ue_context.does_nr) { + MeasObj2 = calloc(1, sizeof(LTE_MeasObjectToAddMod_t)); + if (MeasObj2 == NULL) exit(1); + MeasObj2->measObjectId = 2; + MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; + MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; + MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; + MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.subcarrierSpacingSSB_r15 = LTE_RS_ConfigSSB_NR_r15__subcarrierSpacingSSB_r15_kHz30; + MeasObj2->measObject.choice.measObjectNR_r15.quantityConfigSet_r15 = 1; + MeasObj2->measObject.choice.measObjectNR_r15.ext1 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1__bandNR_r15)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->present = LTE_MeasObjectNR_r15__ext1__bandNR_r15_PR_setup; + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->choice.setup = 78; + + ASN_SEQUENCE_ADD(&MeasObj_list->list, MeasObj2); + } + if (!ue_context_pP->ue_context.measurement_info->events) { ue_context_pP->ue_context.measurement_info->events = CALLOC(1,sizeof(*(ue_context_pP->ue_context.measurement_info->events))); } @@ -3155,6 +3237,9 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_A3 = CALLOC(1, sizeof(*ReportConfig_A3)); ReportConfig_A4 = CALLOC(1, sizeof(*ReportConfig_A4)); ReportConfig_A5 = CALLOC(1, sizeof(*ReportConfig_A5)); + if (ue_context_pP->ue_context.does_nr) { + ReportConfig_NR = CALLOC(1, sizeof(*ReportConfig_NR)); + } ReportConfig_per->reportConfigId = 1; ReportConfig_per->reportConfig.present = LTE_ReportConfigToAddMod__reportConfig_PR_reportConfigEUTRA; ReportConfig_per->reportConfig.choice.reportConfigEUTRA.triggerType.present = @@ -3260,6 +3345,30 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_A5->reportConfig.choice.reportConfigEUTRA.reportInterval = LTE_ReportInterval_ms120; ReportConfig_A5->reportConfig.choice.reportConfigEUTRA.reportAmount = LTE_ReportConfigEUTRA__reportAmount_infinity; ASN_SEQUENCE_ADD(&ReportConfig_list->list, ReportConfig_A5); + + if (ue_context_pP->ue_context.does_nr) { + ReportConfig_NR->reportConfigId = 7; + ReportConfig_NR->reportConfig.present = LTE_ReportConfigToAddMod__reportConfig_PR_reportConfigInterRAT; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.maxReportCells = 4; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrp = TRUE; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrq = TRUE; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_sinr = TRUE; + ASN_SEQUENCE_ADD(&ReportConfig_list->list, ReportConfig_NR); + } + // LTE_RRCConnectionReconfiguration->criticalExtensions.choice.c1.choice.rrcConnectionReconfiguration_r8.measConfig->reportConfigToAddModList = ReportConfig_list; /* A3 event update */ @@ -4230,6 +4339,10 @@ rrc_eNB_process_MeasurementReport( ctxt_pP->subframe); break; + case 7: + LOG_D(RRC, "NR event frame %d subframe %d\n", ctxt_pP->frame, ctxt_pP->subframe); + break; + default: LOG_D(RRC,"Other event report frame %d and subframe %d \n", ctxt_pP->frame, ctxt_pP->subframe); break; @@ -4243,6 +4356,22 @@ rrc_eNB_process_MeasurementReport( ue_context_pP->ue_context.measResults->measResultPCell.rsrqResult/2 - 20); } + /* TODO: improve NR triggering */ + if (measResults2->measId == 7) { + if (ue_context_pP->ue_context.Status != RRC_NR_NSA) { + MessageDef *msg; + ue_context_pP->ue_context.Status = RRC_NR_NSA; + + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + LOG_I(RRC, + "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", + ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; + } + } + if (measResults2->measResultNeighCells == NULL) return; @@ -6298,6 +6427,16 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( free(DRB_Release_configList2); ue_context_pP->ue_context.DRB_Release_configList2[xid] = NULL; } + + /* let's request NR capabilities if the UE supports NR + * maybe not the right place/time to request + */ + if (ue_context_pP->ue_context.does_nr && + !ue_context_pP->ue_context.nr_capabilities_requested) { + ue_context_pP->ue_context.nr_capabilities_requested = 1; + rrc_eNB_generate_NR_UECapabilityEnquiry(ctxt_pP, ue_context_pP); + } + } //----------------------------------------------------------------------------- @@ -7116,6 +7255,48 @@ rrc_eNB_decode_ccch( return rval; } +//----------------------------------------------------------------------------- +static int +is_en_dc_supported( + LTE_UE_EUTRA_Capability_t *c +) +//----------------------------------------------------------------------------- +{ + /* to be refined - check that the eNB is connected to a gNB, check that + * the bands supported by the UE include the band of the gNB + */ +#define NCE nonCriticalExtension + return c != NULL + && c->NCE != NULL + && c->NCE->NCE != NULL + && c->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL + && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; +#undef NCE +} + //----------------------------------------------------------------------------- int rrc_eNB_decode_dcch( @@ -7645,6 +7826,22 @@ rrc_eNB_decode_dcch( LOG_I(RRC, "got UE capabilities for UE %x\n", ctxt_pP->rnti); + int eutra_index = -1; + + for (i = 0; i < ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.count; i++) { + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == LTE_RAT_Type_eutra) { + if (eutra_index != -1) { + LOG_E(RRC, "fatal: more than 1 eutra capability\n"); + exit(1); + } + eutra_index = i; + } + } + + /* do nothing if no EUTRA capabilities (TODO: may be NR capabilities, to be processed somehow) */ + if (eutra_index == -1) + break; + if (ue_context_p->ue_context.UE_Capability) { LOG_I(RRC, "freeing old UE capabilities for UE %x\n", ctxt_pP->rnti); ASN_STRUCT_FREE(asn_DEF_LTE_UE_EUTRA_Capability, @@ -7655,15 +7852,10 @@ rrc_eNB_decode_dcch( dec_rval = uper_decode(NULL, &asn_DEF_LTE_UE_EUTRA_Capability, (void **)&ue_context_p->ue_context.UE_Capability, - ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions. - choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list. - array[0]->ueCapabilityRAT_Container.buf, - ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions. - choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list. - array[0]->ueCapabilityRAT_Container.size, 0, 0); - ue_context_p->ue_context.UE_Capability_size = ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions. - choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list. - array[0]->ueCapabilityRAT_Container.size; + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size, + 0, 0); + ue_context_p->ue_context.UE_Capability_size = ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { xer_fprint(stdout, &asn_DEF_LTE_UE_EUTRA_Capability, ue_context_p->ue_context.UE_Capability); @@ -7678,6 +7870,9 @@ rrc_eNB_decode_dcch( ue_context_p->ue_context.UE_Capability = 0; } + if (dec_rval.code == RC_OK) + ue_context_p->ue_context.does_nr = is_en_dc_supported(ue_context_p->ue_context.UE_Capability); + if (EPC_MODE_ENABLED) { rrc_eNB_send_S1AP_UE_CAPABILITIES_IND(ctxt_pP, ue_context_p, @@ -8241,6 +8436,100 @@ void rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_RX_TX, VCD_FUNCTION_OUT); } +void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, x2ap_ENDC_sgnb_addition_req_ACK_t *m) { + + + NR_CG_Config_t *CG_Config = NULL; + + { + int i; + printf("%d: ", m->rrc_buffer_size); + for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); + printf("\n"); + + } + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_CG_Config, + (void **)&CG_Config, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); + return; + } + xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); + // recreate enough of X2 EN-DC Container + + AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, + "CG_Config not present\n"); + + OCTET_STRING_t *scg_CellGroupConfig = NULL; + OCTET_STRING_t *nr1_conf = NULL; + + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig){ + scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; +#ifdef DEBUG_SCG_CONFIG + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; + int i; + LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); + printf("\n"); + + } +#endif + + } + else{ + LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); + return; + } + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config){ + nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; +#ifdef DEBUG_SCG_CONFIG + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; + int i; + LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); + printf("\n"); + + } +#endif + } + else{ + LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); + return; + } + + protocol_ctxt_t ctxt; + rrc_eNB_ue_context_t *ue_context; + unsigned char buffer[8192]; + int size; + + ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); + + PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, + 0, + ENB_FLAG_YES, + m->rnti, + 0, 0); + + size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); + + rrc_data_req(&ctxt, + DCCH, + rrc_eNB_mui++, + SDU_CONFIRM_NO, + size, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); +} + + //----------------------------------------------------------------------------- void *rrc_enb_process_itti_msg(void *notUsed) { MessageDef *msg_p; @@ -8519,6 +8808,12 @@ void *rrc_enb_process_itti_msg(void *notUsed) { break; } + case X2AP_ENDC_SGNB_ADDITION_REQ_ACK: { + rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); + break; + } + + /* Messages from eNB app */ case RRC_CONFIGURATION_REQ: LOG_I(RRC, "[eNB %d] Received %s : %p\n", instance, msg_name_p, &RRC_CONFIGURATION_REQ(msg_p)); @@ -8597,11 +8892,17 @@ rrc_enb_task( //----------------------------------------------------------------------------- { rrc_enb_init(); + itti_mark_task_ready(TASK_RRC_ENB); LOG_I(RRC,"Entering main loop of RRC message task\n"); while (1) { (void) rrc_enb_process_itti_msg(NULL); +{ + //extern volatile int go_nr; + void rrc_go_nr(void); + //if (go_nr) rrc_go_nr(); +} } } diff --git a/openair2/RRC/LTE/rrc_proto.h b/openair2/RRC/LTE/rrc_proto.h index d5009de270..8f6baabcbf 100644 --- a/openair2/RRC/LTE/rrc_proto.h +++ b/openair2/RRC/LTE/rrc_proto.h @@ -584,6 +584,12 @@ rrc_eNB_generate_UECapabilityEnquiry( rrc_eNB_ue_context_t *const ue_context_pP ); +void +rrc_eNB_generate_NR_UECapabilityEnquiry( + const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP +); + void rrc_eNB_generate_SecurityModeCommand( const protocol_ctxt_t *const ctxt_pP, diff --git a/openair2/RRC/NR/L2_nr_interface.c b/openair2/RRC/NR/L2_nr_interface.c index 2a9448218a..1e8e45ef4d 100644 --- a/openair2/RRC/NR/L2_nr_interface.c +++ b/openair2/RRC/NR/L2_nr_interface.c @@ -64,7 +64,7 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, NR_BCCH_BCH_Message_t *mib; rrc = RC.nrrrc[Mod_idP]; - carrier = &rrc->carrier[0]; + carrier = &rrc->carrier; mib = &carrier->mib; if( (Srb_id & RAB_OFFSET ) == MIBCH) { diff --git a/openair2/RRC/NR/MESSAGES/asn1_msg.c b/openair2/RRC/NR/MESSAGES/asn1_msg.c index b321aa3e4f..a4092c11fa 100644 --- a/openair2/RRC/NR/MESSAGES/asn1_msg.c +++ b/openair2/RRC/NR/MESSAGES/asn1_msg.c @@ -129,16 +129,6 @@ extern unsigned char NB_gNB_INST; extern RAN_CONTEXT_t RC; -uint16_t two_tier_hexagonal_nr_cellIds[7] = {0,1,2,4,5,7,8}; -uint16_t two_tier_hexagonal_adjacent_nr_cellIds[7][6] = {{1,2,4,5,7,8}, // CellId 0 - {11,18,2,0,8,15}, // CellId 1 - {18,13,3,4,0,1}, // CellId 2 - {2,3,14,6,5,0}, // CellId 4 - {0,4,6,16,9,7}, // CellId 5 - {8,0,5,9,17,12}, // CellId 7 - {15,1,0,7,12,10} -};// CellId 8 - /* * This is a helper function for xer_sprint, which directs all incoming data * into the provided string. @@ -180,34 +170,16 @@ int xer_nr_sprint (char *string, size_t string_size, asn_TYPE_descriptor_t *td, return er.encoded; } -uint16_t get_adjacent_cell_id_NR(uint8_t Mod_id,uint8_t index) { - return(two_tier_hexagonal_adjacent_nr_cellIds[Mod_id][index]); -} -/* This only works for the hexagonal topology...need a more general function for other topologies */ - -uint8_t get_adjacent_cell_mod_id_NR(uint16_t phyCellId) { - uint8_t i; - - for(i=0; i<7; i++) { - if(two_tier_hexagonal_nr_cellIds[i] == phyCellId) { - return i; - } - } - - LOG_E(RRC,"\nCannot get adjacent cell mod id! Fatal error!\n"); - return 0xFF; //error! -} - //------------------------------------------------------------------------------ -uint8_t do_MIB_NR(rrc_gNB_carrier_data_t *carrier, - uint32_t frame, - uint32_t ssb_SubcarrierOffset, - uint32_t pdcch_ConfigSIB1, - uint32_t subCarrierSpacingCommon, - uint32_t dmrs_TypeA_Position) { +uint8_t do_MIB_NR(gNB_RRC_INST *rrc,uint32_t frame) { + asn_enc_rval_t enc_rval; + rrc_gNB_carrier_data_t *carrier = &rrc->carrier; + NR_BCCH_BCH_Message_t *mib = &carrier->mib; + NR_ServingCellConfigCommon_t *scc = carrier->servingcellconfigcommon; + memset(mib,0,sizeof(NR_BCCH_BCH_Message_t)); mib->message.present = NR_BCCH_BCH_MessageType_PR_mib; mib->message.choice.mib = CALLOC(1,sizeof(struct NR_MIB)); @@ -226,44 +198,47 @@ uint8_t do_MIB_NR(rrc_gNB_carrier_data_t *carrier, mib->message.choice.mib->spare.buf = (uint8_t *)spare; mib->message.choice.mib->spare.size = 1; mib->message.choice.mib->spare.bits_unused = 7; // This makes a spare of 1 bits - mib->message.choice.mib->ssb_SubcarrierOffset = ssb_SubcarrierOffset; - mib->message.choice.mib->pdcch_ConfigSIB1.controlResourceSetZero = (pdcch_ConfigSIB1 / 16); - mib->message.choice.mib->pdcch_ConfigSIB1.searchSpaceZero = (pdcch_ConfigSIB1 % 16); - switch (subCarrierSpacingCommon) { - case 15: - mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs15or60; - break; - - case 30: - mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs30or120; - break; - - case 60: - mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs15or60; - break; - - case 120: - mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs30or120; - break; - - default: - AssertFatal(1==0, "Unknown subCarrierSpacingCommon %u\n", subCarrierSpacingCommon); + mib->message.choice.mib->ssb_SubcarrierOffset = (carrier->ssb_SubcarrierOffset)&15; + mib->message.choice.mib->pdcch_ConfigSIB1.controlResourceSetZero = *scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero; + mib->message.choice.mib->pdcch_ConfigSIB1.searchSpaceZero = *scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero; + AssertFatal(scc->ssbSubcarrierSpacing != NULL, "scc->ssbSubcarrierSpacing is null\n"); + switch (*scc->ssbSubcarrierSpacing) { + case NR_SubcarrierSpacing_kHz15: + mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs15or60; + break; + + case NR_SubcarrierSpacing_kHz30: + mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs30or120; + break; + + case NR_SubcarrierSpacing_kHz60: + mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs15or60; + break; + + case NR_SubcarrierSpacing_kHz120: + mib->message.choice.mib->subCarrierSpacingCommon = NR_MIB__subCarrierSpacingCommon_scs30or120; + break; + + case NR_SubcarrierSpacing_kHz240: + AssertFatal(1==0,"Unknown subCarrierSpacingCommon %d\n",(int)*scc->ssbSubcarrierSpacing); + break; + + default: + AssertFatal(1==0,"Unknown subCarrierSpacingCommon %d\n",(int)*scc->ssbSubcarrierSpacing); } - mib->message.choice.mib->subCarrierSpacingCommon = 1; - - switch (dmrs_TypeA_Position) { - case 2: - mib->message.choice.mib->dmrs_TypeA_Position = NR_MIB__dmrs_TypeA_Position_pos2; - break; - - case 3: - mib->message.choice.mib->dmrs_TypeA_Position = NR_MIB__dmrs_TypeA_Position_pos3; - break; - - default: - AssertFatal(1==0, "Unknown dmrs_TypeA_Position %u\n", dmrs_TypeA_Position); + switch (scc->dmrs_TypeA_Position) { + case NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2: + mib->message.choice.mib->dmrs_TypeA_Position = NR_MIB__dmrs_TypeA_Position_pos2; + break; + + case NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3: + mib->message.choice.mib->dmrs_TypeA_Position = NR_MIB__dmrs_TypeA_Position_pos3; + break; + + default: + AssertFatal(1==0,"Unknown dmrs_TypeA_Position %d\n",(int)scc->dmrs_TypeA_Position); } // assign_enum @@ -286,7 +261,6 @@ uint8_t do_MIB_NR(rrc_gNB_carrier_data_t *carrier, return((enc_rval.encoded+7)/8); } - uint8_t do_SIB1_NR(rrc_gNB_carrier_data_t *carrier, gNB_RrcConfigurationReq *configuration ) { @@ -382,519 +356,6 @@ uint8_t do_SIB1_NR(rrc_gNB_carrier_data_t *carrier, } -void do_SERVINGCELLCONFIGCOMMON(uint8_t Mod_id, - int CC_id, - gNB_RrcConfigurationReq *configuration, - int initial_flag - ) { - NR_ServingCellConfigCommon_t **servingcellconfigcommon = &RC.nrrrc[Mod_id]->carrier[CC_id].servingcellconfigcommon; - NR_FreqBandIndicatorNR_t *dl_frequencyBandList; - NR_SCS_SpecificCarrier_t *dl_scs_SpecificCarrierList; - NR_TCI_StateId_t *TCI_StateId; - NR_ControlResourceSet_t *bwp_dl_controlresourceset; - NR_SearchSpace_t *bwp_dl_searchspace; - NR_PDSCH_TimeDomainResourceAllocation_t *bwp_dl_timedomainresourceallocation; - NR_FreqBandIndicatorNR_t *ul_frequencyBandList; - NR_SCS_SpecificCarrier_t *ul_scs_SpecificCarrierList; - NR_PUSCH_TimeDomainResourceAllocation_t *pusch_configcommontimedomainresourceallocation; - NR_RateMatchPattern_t *ratematchpattern; - NR_RateMatchPatternId_t *ratematchpatternid; - dl_frequencyBandList = CALLOC(1,sizeof(NR_FreqBandIndicatorNR_t)); - ul_frequencyBandList = CALLOC(1,sizeof(NR_FreqBandIndicatorNR_t)); - dl_scs_SpecificCarrierList = CALLOC(1,sizeof(NR_SCS_SpecificCarrier_t)); - ul_scs_SpecificCarrierList = CALLOC(1,sizeof(NR_SCS_SpecificCarrier_t)); - TCI_StateId = CALLOC(1,sizeof(NR_TCI_StateId_t)); - bwp_dl_searchspace = CALLOC(1,sizeof(NR_SearchSpace_t)); - bwp_dl_timedomainresourceallocation = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t)); - pusch_configcommontimedomainresourceallocation = CALLOC(1,sizeof(NR_PUSCH_TimeDomainResourceAllocation_t)); - ratematchpattern = CALLOC(1,sizeof(NR_RateMatchPattern_t)); - ratematchpatternid = CALLOC(1,sizeof(NR_RateMatchPatternId_t)); - - if(initial_flag == 1) { - (*servingcellconfigcommon) = CALLOC(1,sizeof(NR_ServingCellConfigCommon_t)); - (*servingcellconfigcommon)->physCellId = CALLOC(1,sizeof(NR_PhysCellId_t)); - (*servingcellconfigcommon)->downlinkConfigCommon = CALLOC(1,sizeof(struct NR_DownlinkConfigCommon)); - (*servingcellconfigcommon)->downlinkConfigCommon->frequencyInfoDL = CALLOC(1,sizeof(struct NR_FrequencyInfoDL)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP = CALLOC(1,sizeof(struct NR_BWP_DownlinkCommon)); - (*servingcellconfigcommon)->uplinkConfigCommon = CALLOC(1,sizeof(struct NR_UplinkConfigCommon)); - (*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL = CALLOC(1,sizeof(struct NR_FrequencyInfoUL)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP = CALLOC(1,sizeof(struct NR_BWP_UplinkCommon)); - //(*servingcellconfigcommon)->supplementaryUplinkConfig = CALLOC(1,sizeof(struct NR_UplinkConfigCommon)); - (*servingcellconfigcommon)->ssb_PositionsInBurst = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__ssb_PositionsInBurst)); - (*servingcellconfigcommon)->ssb_periodicityServingCell = CALLOC(1,sizeof(long)); - //(*servingcellconfigcommon)->lte_CRS_ToMatchAround = CALLOC(1,sizeof(struct NR_SetupRelease_RateMatchPatternLTE_CRS)); - (*servingcellconfigcommon)->rateMatchPatternToAddModList = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToAddModList)); - (*servingcellconfigcommon)->rateMatchPatternToReleaseList = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToReleaseList)); - (*servingcellconfigcommon)->ssbSubcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t)); - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon = CALLOC(1,sizeof(struct NR_TDD_UL_DL_ConfigCommon)); - (*servingcellconfigcommon)->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB = CALLOC(1,sizeof(NR_ARFCN_ValueNR_t)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->genericParameters.cyclicPrefix = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon = CALLOC(1,sizeof(struct NR_SetupRelease_PDCCH_ConfigCommon)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PDCCH_ConfigCommon)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = CALLOC(1,sizeof(NR_ControlResourceSet_t)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList = CALLOC(1, - sizeof(struct NR_PDCCH_ConfigCommon__commonSearchSpaceList)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1 = CALLOC(1,sizeof(NR_SearchSpaceId_t)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation = CALLOC(1,sizeof(NR_SearchSpaceId_t)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->pagingSearchSpace = CALLOC(1,sizeof(NR_SearchSpaceId_t)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->ra_SearchSpace = CALLOC(1,sizeof(NR_SearchSpaceId_t)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon = CALLOC(1,sizeof(struct NR_SetupRelease_PDSCH_ConfigCommon)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PDSCH_ConfigCommon)); - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = CALLOC(1, - sizeof(struct NR_PDSCH_TimeDomainResourceAllocationList)); - (*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->frequencyBandList = CALLOC(1,sizeof(NR_MultiFrequencyBandListNR_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA = CALLOC(1,sizeof(NR_ARFCN_ValueNR_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->additionalSpectrumEmission = CALLOC(1,sizeof(NR_AdditionalSpectrumEmission_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->p_Max = CALLOC(1,sizeof(NR_P_Max_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->frequencyShift7p5khz = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->genericParameters.cyclicPrefix = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon = CALLOC(1,sizeof(NR_SetupRelease_RACH_ConfigCommon_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_RACH_ConfigCommon)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB = CALLOC(1, - sizeof(struct NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->groupBconfigured = CALLOC(1, - sizeof(struct NR_RACH_ConfigCommon__groupBconfigured)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB = CALLOC(1,sizeof(NR_RSRP_Range_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB_SUL = CALLOC(1,sizeof(NR_RSRP_Range_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon = CALLOC(1,sizeof(NR_SetupRelease_PUSCH_ConfigCommon_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PUSCH_ConfigCommon)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->groupHoppingEnabledTransformPrecoding = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList = CALLOC(1,sizeof(NR_PUSCH_TimeDomainResourceAllocationList_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->msg3_DeltaPreamble = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon = CALLOC(1,sizeof(struct NR_SetupRelease_PUCCH_ConfigCommon)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup = CALLOC(1,sizeof(struct NR_PUCCH_ConfigCommon)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon = CALLOC(1,sizeof(BIT_STRING_t)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId = CALLOC(1,sizeof(long)); - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.shortBitmap.buf = MALLOC(1); - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.mediumBitmap.buf = MALLOC(1); - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf = MALLOC(8); - bwp_dl_controlresourceset =(*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; - bwp_dl_controlresourceset->cce_REG_MappingType.choice.interleaved = CALLOC(1,sizeof(struct NR_ControlResourceSet__cce_REG_MappingType__interleaved)); - bwp_dl_controlresourceset->frequencyDomainResources.buf = MALLOC(6); - bwp_dl_controlresourceset->cce_REG_MappingType.choice.interleaved->shiftIndex = CALLOC(1,sizeof(long)); - bwp_dl_controlresourceset->tci_StatesPDCCH_ToAddList = CALLOC(1,sizeof(struct NR_ControlResourceSet__tci_StatesPDCCH_ToAddList)); - bwp_dl_controlresourceset->tci_PresentInDCI = CALLOC(1,sizeof(long)); - bwp_dl_controlresourceset->pdcch_DMRS_ScramblingID = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->controlResourceSetId = CALLOC(1,sizeof(NR_ControlResourceSetId_t)); - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset = CALLOC(1,sizeof(struct NR_SearchSpace__monitoringSlotPeriodicityAndOffset)); - bwp_dl_searchspace->duration = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->monitoringSymbolsWithinSlot = CALLOC(1,sizeof(BIT_STRING_t)); - bwp_dl_searchspace->monitoringSymbolsWithinSlot->buf = MALLOC(2); - bwp_dl_searchspace->nrofCandidates = CALLOC(1,sizeof(struct NR_SearchSpace__nrofCandidates)); - bwp_dl_searchspace->searchSpaceType = CALLOC(1,sizeof(struct NR_SearchSpace__searchSpaceType)); - bwp_dl_timedomainresourceallocation->k0 = CALLOC(1,sizeof(long)); - pusch_configcommontimedomainresourceallocation = CALLOC(1,sizeof(NR_PUSCH_TimeDomainResourceAllocation_t)); - pusch_configcommontimedomainresourceallocation->k2 = CALLOC(1,sizeof(long)); - ratematchpattern->patternType.choice.bitmaps = CALLOC(1,sizeof(struct NR_RateMatchPattern__patternType__bitmaps)); - ratematchpattern->patternType.choice.bitmaps->resourceBlocks.buf = MALLOC(35); - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.oneSlot.buf = MALLOC(2); - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.buf = MALLOC(4); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern = CALLOC(1,sizeof(struct NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern)); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n2.buf = MALLOC(1); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n4.buf = MALLOC(1); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n5.buf = MALLOC(1); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n8.buf = MALLOC(1); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n10.buf = MALLOC(2); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.buf = MALLOC(3); - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf = MALLOC(5); - ratematchpattern->subcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t)); - } else { - bwp_dl_controlresourceset =(*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; - } - - //------------------------------------Start Fill ServingCellConfigCommon------------------------------------// - //physCellId - *((*servingcellconfigcommon)->physCellId) = configuration->Nid_cell[CC_id]; - //NR_DownlinkConfigCommon - *((*servingcellconfigcommon)->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB) = configuration->absoluteFrequencySSB[CC_id]; - *(dl_frequencyBandList) = configuration->DL_FreqBandIndicatorNR[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list,&dl_frequencyBandList); - (*servingcellconfigcommon)->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA = configuration->DL_absoluteFrequencyPointA[CC_id]; - dl_scs_SpecificCarrierList->offsetToCarrier = configuration->DL_offsetToCarrier[CC_id]; - dl_scs_SpecificCarrierList->subcarrierSpacing = configuration->DL_SCS_SubcarrierSpacing[CC_id]; - dl_scs_SpecificCarrierList->carrierBandwidth = configuration->DL_carrierBandwidth[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list,&dl_scs_SpecificCarrierList); - //initialDownlinkBWP - //initialDownlinkBWP ----- genericParameters - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth = configuration->DL_locationAndBandwidth[CC_id]; - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing = configuration->DL_BWP_SubcarrierSpacing[CC_id]; - - if(configuration->DL_BWP_prefix_type[CC_id]) { - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->genericParameters.cyclicPrefix = NR_BWP__cyclicPrefix_extended; - } - - //initialDownlinkBWP ----- pdcch_ConfigCommon - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; - //Fill initialDownlinkBWP -> pdcch_ConfigCommon -> ControlResourceSet list // - *((*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero) = configuration->controlResourceSetZero[CC_id]; - *((*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero) = configuration->searchSpaceZero[CC_id]; - bwp_dl_controlresourceset->controlResourceSetId = configuration->PDCCH_common_controlResourceSetId[CC_id]; - //BIT STRING (SIZE (45)) - bwp_dl_controlresourceset->frequencyDomainResources.size = 6; - bwp_dl_controlresourceset->frequencyDomainResources.bits_unused = 3; - bwp_dl_controlresourceset->frequencyDomainResources.buf[0] = 0x1f; - bwp_dl_controlresourceset->frequencyDomainResources.buf[1] = 0xff; - bwp_dl_controlresourceset->frequencyDomainResources.buf[2] = 0xff; - bwp_dl_controlresourceset->frequencyDomainResources.buf[3] = 0xff; - bwp_dl_controlresourceset->frequencyDomainResources.buf[4] = 0xff; - bwp_dl_controlresourceset->frequencyDomainResources.buf[5] = 0xff; - bwp_dl_controlresourceset->duration = configuration->PDCCH_common_ControlResourceSet_duration[CC_id]; - bwp_dl_controlresourceset->cce_REG_MappingType.present = configuration->PDCCH_cce_REG_MappingType[CC_id]; - - if(bwp_dl_controlresourceset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved ) { - bwp_dl_controlresourceset->cce_REG_MappingType.choice.interleaved->reg_BundleSize = configuration->PDCCH_reg_BundleSize[CC_id]; - bwp_dl_controlresourceset->cce_REG_MappingType.choice.interleaved->interleaverSize = configuration->PDCCH_interleaverSize[CC_id]; - *(bwp_dl_controlresourceset->cce_REG_MappingType.choice.interleaved->shiftIndex) = configuration->PDCCH_shiftIndex[CC_id]; - } else if(bwp_dl_controlresourceset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved) { - bwp_dl_controlresourceset->cce_REG_MappingType.choice.nonInterleaved = 0; - } - - bwp_dl_controlresourceset->precoderGranularity = configuration->PDCCH_precoderGranularity[CC_id]; - *(TCI_StateId) = configuration->PDCCH_TCI_StateId[CC_id]; - ASN_SEQUENCE_ADD(&bwp_dl_controlresourceset->tci_StatesPDCCH_ToAddList->list,&TCI_StateId); - - if(configuration->tci_PresentInDCI[CC_id]) { - bwp_dl_controlresourceset->tci_PresentInDCI = NR_ControlResourceSet__tci_PresentInDCI_enabled; - } - - *(bwp_dl_controlresourceset->pdcch_DMRS_ScramblingID) = configuration->PDCCH_DMRS_ScramblingID[CC_id];; - //Fill downlinkConfigCommon -> initialDownlinkBWP -> pdcch_ConfigCommon -> SearchSpace list // - bwp_dl_searchspace->searchSpaceId = configuration->SearchSpaceId[CC_id]; - *(bwp_dl_searchspace->controlResourceSetId) = configuration->commonSearchSpaces_controlResourceSetId[CC_id]; - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_choice[CC_id]; - - if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl1 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl2 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl4 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl5 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl8 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl10 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl16 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl20 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl40 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl80 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl160 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl320 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl640 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl1280 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } else if(bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->present == NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560) { - bwp_dl_searchspace->monitoringSlotPeriodicityAndOffset->choice.sl2560 = configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id]; - } - - *(bwp_dl_searchspace->duration) = configuration->SearchSpace_duration[CC_id]; - bwp_dl_searchspace->monitoringSymbolsWithinSlot->size = 2; - bwp_dl_searchspace->monitoringSymbolsWithinSlot->bits_unused = 2; - bwp_dl_searchspace->monitoringSymbolsWithinSlot->buf[0] = 0x3f; - bwp_dl_searchspace->monitoringSymbolsWithinSlot->buf[1] = 0xff; - bwp_dl_searchspace->nrofCandidates->aggregationLevel1 = configuration->SearchSpace_nrofCandidates_aggregationLevel1[CC_id]; - bwp_dl_searchspace->nrofCandidates->aggregationLevel2 = configuration->SearchSpace_nrofCandidates_aggregationLevel2[CC_id]; - bwp_dl_searchspace->nrofCandidates->aggregationLevel4 = configuration->SearchSpace_nrofCandidates_aggregationLevel4[CC_id]; - bwp_dl_searchspace->nrofCandidates->aggregationLevel8 = configuration->SearchSpace_nrofCandidates_aggregationLevel8[CC_id]; - bwp_dl_searchspace->nrofCandidates->aggregationLevel16 = configuration->SearchSpace_nrofCandidates_aggregationLevel16[CC_id]; - bwp_dl_searchspace->searchSpaceType->present = configuration->SearchSpace_searchSpaceType[CC_id]; - - if(bwp_dl_searchspace->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_common) { - bwp_dl_searchspace->searchSpaceType->choice.common = CALLOC(1,sizeof(struct NR_SearchSpace__searchSpaceType__common)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0 = CALLOC(1,sizeof(struct NR_SearchSpace__searchSpaceType__common__dci_Format2_0)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel1 = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel2 = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel4 = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel8 = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel16 = CALLOC(1,sizeof(long)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_3 = CALLOC(1,sizeof(struct NR_SearchSpace__searchSpaceType__common__dci_Format2_3)); - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_3->dummy1 = CALLOC(1,sizeof(long)); - *(bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel1) = configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1[CC_id]; - *(bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel2) = configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2[CC_id]; - *(bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel4) = configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4[CC_id]; - *(bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel8) = configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8[CC_id]; - *(bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_0->nrofCandidates_SFI.aggregationLevel16) = configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16[CC_id]; - *(bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_3->dummy1) = configuration->Common_dci_Format2_3_monitoringPeriodicity[CC_id]; - bwp_dl_searchspace->searchSpaceType->choice.common->dci_Format2_3->dummy2 = configuration->Common_dci_Format2_3_nrofPDCCH_Candidates[CC_id]; - } else if (bwp_dl_searchspace->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) { - bwp_dl_searchspace->searchSpaceType->choice.ue_Specific = CALLOC(1,sizeof(struct NR_SearchSpace__searchSpaceType__ue_Specific)); - bwp_dl_searchspace->searchSpaceType->choice.ue_Specific->dci_Formats = configuration->ue_Specific__dci_Formats[CC_id]; - } - - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,&bwp_dl_searchspace); - *((*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1) = configuration->searchSpaceSIB1[CC_id]; - *((*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation) = configuration->searchSpaceOtherSystemInformation[CC_id]; - *((*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->pagingSearchSpace) = configuration->pagingSearchSpace[CC_id]; - *((*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->ra_SearchSpace) = configuration->ra_SearchSpace[CC_id]; - //initialDownlinkBWP ----- pdsch_ConfigCommon - (*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; - *(bwp_dl_timedomainresourceallocation->k0) = configuration->PDSCH_TimeDomainResourceAllocation_k0[CC_id]; - bwp_dl_timedomainresourceallocation->mappingType = configuration->PDSCH_TimeDomainResourceAllocation_mappingType[CC_id]; - bwp_dl_timedomainresourceallocation->startSymbolAndLength = configuration->PDSCH_TimeDomainResourceAllocation_startSymbolAndLength[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,&bwp_dl_timedomainresourceallocation); - //uplinkConfigCommon - //uplinkConfigCommon frequencyInfoUL // - *(ul_frequencyBandList) = configuration->UL_FreqBandIndicatorNR[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list,&ul_frequencyBandList); - *((*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA) = configuration->UL_absoluteFrequencyPointA[CC_id]; - ul_scs_SpecificCarrierList->offsetToCarrier = configuration->UL_offsetToCarrier[CC_id]; - ul_scs_SpecificCarrierList->subcarrierSpacing = configuration->UL_SCS_SubcarrierSpacing[CC_id]; - ul_scs_SpecificCarrierList->carrierBandwidth = configuration->UL_carrierBandwidth[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list,&ul_scs_SpecificCarrierList); - *((*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->additionalSpectrumEmission) = configuration->UL_additionalSpectrumEmission[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->p_Max) = configuration->UL_p_Max[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->frequencyInfoUL->frequencyShift7p5khz) = configuration->UL_frequencyShift7p5khz[CC_id]; - //uplinkConfigCommon initialUplinkBWP // - //Fill initialUplinkBWP -> BWP-UplinkCommon -> genericParameters// - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth = configuration->UL_locationAndBandwidth[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing = configuration->UL_BWP_SubcarrierSpacing[CC_id]; - - if(configuration->UL_BWP_prefix_type[CC_id]) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->genericParameters.cyclicPrefix = NR_BWP__cyclicPrefix_extended; - } - - //Fill initialUplinkBWP -> BWP-UplinkCommon -> rach_ConfigCommon// - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->present = NR_SetupRelease_RACH_ConfigCommon_PR_setup; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles) = configuration->rach_totalNumberOfRA_Preambles[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[CC_id]; - - if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_oneEighth) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.oneEighth = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_oneFourth) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.oneFourth = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_oneHalf) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.oneHalf = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_one) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.one = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_two) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.two = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_four) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.four = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_eight) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.eight = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight[CC_id]; - } else if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present == - NR_RACH_ConfigCommon__ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR_sixteen) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->choice.sixteen = - configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen[CC_id]; - } - - if(configuration->rach_groupBconfigured[CC_id]) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->groupBconfigured->ra_Msg3SizeGroupA = configuration->rach_ra_Msg3SizeGroupA[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->groupBconfigured->messagePowerOffsetGroupB = configuration->rach_messagePowerOffsetGroupB[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->groupBconfigured->numberOfRA_PreamblesGroupA = - configuration->rach_numberOfRA_PreamblesGroupA[CC_id]; - } - - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ra_ContentionResolutionTimer = configuration->rach_ra_ContentionResolutionTimer[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB) = configuration->rsrp_ThresholdSSB[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB_SUL) = configuration->rsrp_ThresholdSSB_SUL[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present = configuration->prach_RootSequenceIndex_choice[CC_id]; - - if((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present == NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l839) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l839 = configuration->prach_RootSequenceIndex_l839[CC_id]; - } else if ((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present == - NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139 = configuration->prach_RootSequenceIndex_l139[CC_id]; - } - - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) = configuration->prach_msg1_SubcarrierSpacing[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig = configuration->restrictedSetConfig[CC_id]; - - if(configuration->msg3_transformPrecoding[CC_id]) { - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder) = NR_RACH_ConfigCommon__msg3_transformPrecoder_enabled; - } - - //Fill initialUplinkBWP -> BWP-UplinkCommon -> rach_ConfigCommon -> rach_ConfigGeneric// - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex = configuration->prach_ConfigurationIndex[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM = configuration->prach_msg1_FDM[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart = configuration->prach_msg1_FrequencyStart[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig = configuration->zeroCorrelationZoneConfig[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower = - configuration->preambleReceivedTargetPower[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleTransMax = configuration->preambleTransMax[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.powerRampingStep = configuration->powerRampingStep[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow = configuration->ra_ResponseWindow[CC_id]; - //Fill initialUplinkBWP -> BWP-UplinkCommon -> pusch_ConfigCommon// - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->present = NR_SetupRelease_PUSCH_ConfigCommon_PR_setup; - - if(configuration->groupHoppingEnabledTransformPrecoding[CC_id]) { - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->groupHoppingEnabledTransformPrecoding = - NR_PUSCH_ConfigCommon__groupHoppingEnabledTransformPrecoding_enabled; - } - - *(pusch_configcommontimedomainresourceallocation->k2) = configuration->PUSCH_TimeDomainResourceAllocation_k2[CC_id]; - pusch_configcommontimedomainresourceallocation->mappingType = configuration->PUSCH_TimeDomainResourceAllocation_mappingType[CC_id]; - pusch_configcommontimedomainresourceallocation->startSymbolAndLength = configuration->PUSCH_TimeDomainResourceAllocation_startSymbolAndLength[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list, - &pusch_configcommontimedomainresourceallocation); - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->msg3_DeltaPreamble) = configuration->msg3_DeltaPreamble[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant) = configuration->p0_NominalWithGrant[CC_id]; - //Fill initialUplinkBWP -> BWP-UplinkCommon -> pucch_ConfigCommon// - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->present = NR_SetupRelease_PUCCH_ConfigCommon_PR_setup; - (*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_GroupHopping = configuration->pucch_GroupHopping[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal) = configuration->p0_nominal[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon) = configuration->pucch_ResourceCommon[CC_id]; - *((*servingcellconfigcommon)->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId) = configuration->hoppingId[CC_id]; - (*servingcellconfigcommon)->uplinkConfigCommon->dummy = configuration->UL_timeAlignmentTimerCommon[CC_id]; - (*servingcellconfigcommon)->n_TimingAdvanceOffset = CALLOC(1,sizeof(long)); - *((*servingcellconfigcommon)->n_TimingAdvanceOffset)=configuration->ServingCellConfigCommon_n_TimingAdvanceOffset[CC_id]; - //ssb_PositionsInBurst - (*servingcellconfigcommon)->ssb_PositionsInBurst->present = configuration->ServingCellConfigCommon_ssb_PositionsInBurst_PR[CC_id]; - uint64_t t_freq; - - if(configuration->nr_band[CC_id] == 41 || (configuration->nr_band[CC_id] > 76 && configuration->nr_band[CC_id] < 80)) - t_freq = 2400000000; - else - t_freq = 3000000000; - - if(configuration->downlink_frequency[CC_id]ssb_PositionsInBurst->choice.shortBitmap.size = 1; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.shortBitmap.bits_unused = 4; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.shortBitmap.buf[0] = configuration->ServingCellConfigCommon_ssb_PositionsInBurst_PR[CC_id]; - } else if(configuration->downlink_frequency[CC_id]<6000000000) { - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.mediumBitmap.size = 1; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.mediumBitmap.bits_unused = 0; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = configuration->ServingCellConfigCommon_ssb_PositionsInBurst_PR[CC_id]; - } else { - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.size = 8; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.bits_unused = 0; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[0] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[1] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[2] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[3] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[4] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[5] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[6] = 0xff; - (*servingcellconfigcommon)->ssb_PositionsInBurst->choice.longBitmap.buf[7] = 0xff; - } - - //ssb_periodicityServingCell - *(*servingcellconfigcommon)->ssb_periodicityServingCell = configuration->ServingCellConfigCommon_ssb_periodicityServingCell[CC_id]; - //dmrs_TypeA_Position - (*servingcellconfigcommon)->dmrs_TypeA_Position = configuration->ServingCellConfigCommon_dmrs_TypeA_Position[CC_id]; - //lte_CRS_ToMatchAround - //rateMatchPatternToAddModList - ratematchpattern->rateMatchPatternId = configuration->rateMatchPatternId[CC_id]; - ratematchpattern->patternType.present = configuration->RateMatchPattern_patternType[CC_id]; - - if(ratematchpattern->patternType.present == NR_RateMatchPattern__patternType_PR_bitmaps) { - ratematchpattern->patternType.choice.bitmaps->resourceBlocks.size = 35; - ratematchpattern->patternType.choice.bitmaps->resourceBlocks.bits_unused = 5; - ratematchpattern->patternType.choice.bitmaps->resourceBlocks.buf[0] = 0x07; - - for (int i =1; i<=34; i++ ) { - ratematchpattern->patternType.choice.bitmaps->resourceBlocks.buf[i] =0xff; - } - - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.present = configuration->symbolsInResourceBlock[CC_id]; - - if(ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.present == NR_RateMatchPattern__patternType__bitmaps__symbolsInResourceBlock_PR_oneSlot) { - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.oneSlot.size=2; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.oneSlot.bits_unused=2; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.oneSlot.buf[0]=0x3f; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.oneSlot.buf[1]=0xff; - } else if(ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.present == NR_RateMatchPattern__patternType__bitmaps__symbolsInResourceBlock_PR_twoSlots) { - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.size=4; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.bits_unused=4; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.buf[0]=0x0f; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.buf[1]=0xff; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.buf[2]=0xff; - ratematchpattern->patternType.choice.bitmaps->symbolsInResourceBlock.choice.twoSlots.buf[3]=0xff; - } - - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present = configuration->periodicityAndPattern[CC_id]; - - if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n2) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n2.size = 1; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n2.bits_unused = 6; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n2.buf[0] =0x03; - } else if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n4) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n4.size = 1; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n4.bits_unused = 4; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n4.buf[0] = 0x0f; - } else if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n5) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n5.size = 1; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n5.bits_unused = 3; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n5.buf[0] = 0x1f; - } else if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n8) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n8.size = 1; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n8.bits_unused = 0; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n8.buf[0] = 0xff; - } else if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n10) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n10.size = 2; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n10.bits_unused = 6; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n10.buf[0] = 0x03; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n10.buf[1] = 0xff; - } else if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n20) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.size = 3; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.bits_unused = 4; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.buf[0] = 0x0f; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.buf[1] = 0xff; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n20.buf[2] = 0xff; - } else if(ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->present == NR_RateMatchPattern__patternType__bitmaps__periodicityAndPattern_PR_n40) { - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.size = 5; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.bits_unused = 0; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf[0] = 0xff; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf[1] = 0xff; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf[2] = 0xff; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf[3] = 0xff; - ratematchpattern->patternType.choice.bitmaps->periodicityAndPattern->choice.n40.buf[4] = 0xff; - } - } else if(ratematchpattern->patternType.present == NR_RateMatchPattern__patternType_PR_controlResourceSet) { - ratematchpattern->patternType.choice.controlResourceSet = configuration->RateMatchPattern_controlResourceSet[CC_id]; - } - - *(ratematchpattern->subcarrierSpacing) = configuration->RateMatchPattern_subcarrierSpacing[CC_id]; - ratematchpattern->dummy = configuration->RateMatchPattern_mode[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->rateMatchPatternToAddModList->list,&ratematchpattern); - //rateMatchPatternToReleaseList - *(ratematchpatternid) = configuration->rateMatchPatternId[CC_id]; - ASN_SEQUENCE_ADD(&(*servingcellconfigcommon)->rateMatchPatternToReleaseList->list,&ratematchpatternid); - //subcarrierSpacing - *(*servingcellconfigcommon)->ssbSubcarrierSpacing = configuration->NIA_SubcarrierSpacing[CC_id]; - //tdd_UL_DL_ConfigurationCommon - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing = configuration->referenceSubcarrierSpacing[CC_id]; - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity = configuration->dl_UL_TransmissionPeriodicity[CC_id]; - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots = configuration->nrofDownlinkSlots[CC_id]; - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols = configuration->nrofDownlinkSymbols[CC_id]; - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots = configuration->nrofUplinkSlots[CC_id]; - (*servingcellconfigcommon)->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols = configuration->nrofUplinkSymbols[CC_id]; - //ss_PBCH_BlockPower - (*servingcellconfigcommon)->ss_PBCH_BlockPower = configuration->ServingCellConfigCommon_ss_PBCH_BlockPower[CC_id]; -} - - void do_RLC_BEARER(uint8_t Mod_id, int CC_id, struct NR_CellGroupConfig__rlc_BearerToAddModList *rlc_BearerToAddModList, @@ -1106,28 +567,14 @@ void do_PHYSICALCELLGROUP(uint8_t Mod_id, } -void do_SpCellConfig(uint8_t Mod_id, - int CC_id, - NR_SpCellConfig_t *spconfig) { - //spconfig->servCellIndex = CALLOC(1,sizeof(NR_ServCellIndex_t)); - //*(spconfig->servCellIndex)= + +void do_SpCellConfig(gNB_RRC_INST *rrc, + struct NR_SpCellConfig *spconfig){ gNB_RrcConfigurationReq *common_configuration; common_configuration = CALLOC(1,sizeof(gNB_RrcConfigurationReq)); //Fill servingcellconfigcommon config value - rrc_config_servingcellconfigcommon(Mod_id, - CC_id, - common_configuration - ); //Fill common config to structure - do_SERVINGCELLCONFIGCOMMON(Mod_id, - CC_id, - common_configuration, - 0 - ); + // rrc->configuration = common_configuration; spconfig->reconfigurationWithSync = CALLOC(1,sizeof(struct NR_ReconfigurationWithSync)); - /* - memcpy( spconfig->reconfigurationWithSync, - RC.nrrrc[Mod_id]->carrier[0].servingcellconfigcommon, - sizeof(struct NR_ServingCellConfigCommon)); - */ } + diff --git a/openair2/RRC/NR/MESSAGES/asn1_msg.h b/openair2/RRC/NR/MESSAGES/asn1_msg.h index 69ce650b23..3f647cb887 100644 --- a/openair2/RRC/NR/MESSAGES/asn1_msg.h +++ b/openair2/RRC/NR/MESSAGES/asn1_msg.h @@ -53,24 +53,9 @@ */ int xer_sprint_NR(char *string, size_t string_size, struct asn_TYPE_descriptor_s *td, void *sptr); -uint16_t get_adjacent_cell_id_NR(uint8_t Mod_id,uint8_t index); +uint8_t do_MIB_NR(gNB_RRC_INST *rrc, + uint32_t frame); -uint8_t get_adjacent_cell_mod_id_NR(uint16_t phyCellId); - -/** -\brief Generate configuration for SIB1 (eNB). -@param carrier pointer to Carrier information -@param N_RB_DL Number of downlink PRBs -@param phich_Resource PHICH resoure parameter -@param phich_duration PHICH duration parameter -@param frame radio frame number -@return size of encoded bit stream in bytes*/ -uint8_t do_MIB_NR(rrc_gNB_carrier_data_t *carrier, - uint32_t frame, - uint32_t ssb_SubcarrierOffset, - uint32_t pdcch_ConfigSIB1, - uint32_t subCarrierSpacingCommon, - uint32_t dmrs_TypeA_Position); /** \brief Generate configuration for SIB1 (gNB). @param carrier pointer to Carrier information @@ -80,16 +65,10 @@ uint8_t do_SIB1_NR(rrc_gNB_carrier_data_t *carrier, gNB_RrcConfigurationReq *configuration ); -void do_SERVINGCELLCONFIGCOMMON(uint8_t Mod_id, - int CC_id, - gNB_RrcConfigurationReq *configuration, - int initial_flag); - void do_RLC_BEARER(uint8_t Mod_id, - int CC_id, - struct NR_CellGroupConfig__rlc_BearerToAddModList *rlc_BearerToAddModList, - rlc_bearer_config_t *rlc_config); - + int CC_id, + struct NR_CellGroupConfig__rlc_BearerToAddModList *rlc_BearerToAddModList, + rlc_bearer_config_t *rlc_config); void do_MAC_CELLGROUP(uint8_t Mod_id, int CC_id, NR_MAC_CellGroupConfig_t *mac_CellGroupConfig, @@ -100,6 +79,6 @@ void do_PHYSICALCELLGROUP(uint8_t Mod_id, NR_PhysicalCellGroupConfig_t *physicalCellGroupConfig, physicalcellgroup_t *physicalcellgroup_config); -void do_SpCellConfig(uint8_t Mod_id, - int CC_id, - NR_SpCellConfig_t *spconfig); + +void do_SpCellConfig(gNB_RRC_INST *rrc, + struct NR_SpCellConfig *spconfig); diff --git a/openair2/RRC/NR/nr_rrc_config.c b/openair2/RRC/NR/nr_rrc_config.c index e09b1e6055..dedd4cf839 100644 --- a/openair2/RRC/NR/nr_rrc_config.c +++ b/openair2/RRC/NR/nr_rrc_config.c @@ -30,142 +30,6 @@ #include "nr_rrc_config.h" -void rrc_config_servingcellconfigcommon(uint8_t Mod_id, - int CC_id, - gNB_RrcConfigurationReq *common_configuration - ){ - - common_configuration->MIB_subCarrierSpacingCommon[CC_id] = 0; - common_configuration->MIB_ssb_SubcarrierOffset[CC_id] = 0; - common_configuration->MIB_dmrs_TypeA_Position[CC_id] = 0; - common_configuration->pdcch_ConfigSIB1[CC_id] = 0; - common_configuration->absoluteFrequencySSB[CC_id] = 0; - common_configuration->DL_FreqBandIndicatorNR[CC_id] = 0; - common_configuration->DL_absoluteFrequencyPointA[CC_id] = 0; - common_configuration->DL_offsetToCarrier[CC_id] = 0; - common_configuration->DL_SCS_SubcarrierSpacing[CC_id] = 0; - common_configuration->DL_carrierBandwidth[CC_id] = 0; - common_configuration->DL_locationAndBandwidth[CC_id] = 0; - common_configuration->DL_BWP_SubcarrierSpacing[CC_id] = 0; - common_configuration->DL_BWP_prefix_type[CC_id] = 0; - common_configuration->UL_FreqBandIndicatorNR[CC_id] = 0; - common_configuration->UL_absoluteFrequencyPointA[CC_id] = 0; - common_configuration->UL_additionalSpectrumEmission[CC_id] = 0; - common_configuration->UL_p_Max[CC_id] = 0; - common_configuration->UL_frequencyShift7p5khz[CC_id] = 0; - common_configuration->UL_offsetToCarrier[CC_id] = 0; - common_configuration->UL_SCS_SubcarrierSpacing[CC_id] = 0; - common_configuration->UL_carrierBandwidth[CC_id] = 0; - common_configuration->UL_locationAndBandwidth[CC_id] = 0; - common_configuration->UL_BWP_SubcarrierSpacing[CC_id] = 0; - common_configuration->UL_BWP_prefix_type[CC_id] = 0; - common_configuration->UL_timeAlignmentTimerCommon[CC_id] = 0; - common_configuration->ServingCellConfigCommon_ssb_PositionsInBurst_PR[CC_id] = 0; - common_configuration->ServingCellConfigCommon_ssb_periodicityServingCell[CC_id] = 0; - common_configuration->ServingCellConfigCommon_dmrs_TypeA_Position[CC_id] = 0; - common_configuration->NIA_SubcarrierSpacing[CC_id] = 0; - common_configuration->ServingCellConfigCommon_ss_PBCH_BlockPower[CC_id] = 0; - common_configuration->referenceSubcarrierSpacing[CC_id] = 0; - common_configuration->dl_UL_TransmissionPeriodicity[CC_id] = 0; - common_configuration->nrofDownlinkSlots[CC_id] = 0; - common_configuration->nrofDownlinkSymbols[CC_id] = 0; - common_configuration->nrofUplinkSlots[CC_id] = 0; - common_configuration->nrofUplinkSymbols[CC_id] = 0; - common_configuration->rach_totalNumberOfRA_Preambles[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight[CC_id] = 0; - common_configuration->rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen[CC_id] = 0; - common_configuration->rach_groupBconfigured[CC_id] = 0; - common_configuration->rach_ra_Msg3SizeGroupA[CC_id] = 0; - common_configuration->rach_messagePowerOffsetGroupB[CC_id] = 0; - common_configuration->rach_numberOfRA_PreamblesGroupA[CC_id] = 0; - common_configuration->rach_ra_ContentionResolutionTimer[CC_id] = 0; - common_configuration->rsrp_ThresholdSSB[CC_id] = 0; - common_configuration->rsrp_ThresholdSSB_SUL[CC_id] = 0; - common_configuration->prach_RootSequenceIndex_choice[CC_id] = 0; - common_configuration->prach_RootSequenceIndex_l839[CC_id] = 0; - common_configuration->prach_RootSequenceIndex_l139[CC_id] = 0; - common_configuration->prach_msg1_SubcarrierSpacing[CC_id] = 0; - common_configuration->restrictedSetConfig[CC_id] = 0; - common_configuration->msg3_transformPrecoding[CC_id] = 0; - common_configuration->prach_ConfigurationIndex[CC_id] = 0; - common_configuration->prach_msg1_FDM[CC_id] = 0; - common_configuration->prach_msg1_FrequencyStart[CC_id] = 0; - common_configuration->zeroCorrelationZoneConfig[CC_id] = 0; - common_configuration->preambleReceivedTargetPower[CC_id] = 0; - common_configuration->preambleTransMax[CC_id] = 0; - common_configuration->powerRampingStep[CC_id] = 0; - common_configuration->ra_ResponseWindow[CC_id] = 0; - common_configuration->groupHoppingEnabledTransformPrecoding[CC_id] = 0; - common_configuration->msg3_DeltaPreamble[CC_id] = 0; - common_configuration->p0_NominalWithGrant[CC_id] = 0; - common_configuration->PUSCH_TimeDomainResourceAllocation_k2[CC_id] = 0; - common_configuration->PUSCH_TimeDomainResourceAllocation_mappingType[CC_id] = 0; - common_configuration->PUSCH_TimeDomainResourceAllocation_startSymbolAndLength[CC_id] = 0; - common_configuration->pucch_ResourceCommon[CC_id] = 0; - common_configuration->pucch_GroupHopping[CC_id] = 0; - common_configuration->hoppingId[CC_id] = 0; - common_configuration->p0_nominal[CC_id] = 0; - common_configuration->PDSCH_TimeDomainResourceAllocation_k0[CC_id] = 0; - common_configuration->PDSCH_TimeDomainResourceAllocation_mappingType[CC_id] = 0; - common_configuration->PDSCH_TimeDomainResourceAllocation_startSymbolAndLength[CC_id] = 0; - common_configuration->rateMatchPatternId[CC_id] = 0; - common_configuration->RateMatchPattern_patternType[CC_id] = 0; - common_configuration->symbolsInResourceBlock[CC_id] = 0; - common_configuration->periodicityAndPattern[CC_id] = 0; - common_configuration->RateMatchPattern_controlResourceSet[CC_id] = 0; - common_configuration->RateMatchPattern_subcarrierSpacing[CC_id] = 0; - common_configuration->RateMatchPattern_mode[CC_id] = 0; - common_configuration->controlResourceSetZero[CC_id] = 0; - common_configuration->searchSpaceZero[CC_id] = 0; - common_configuration->searchSpaceSIB1[CC_id] = 0; - common_configuration->searchSpaceOtherSystemInformation[CC_id] = 0; - common_configuration->pagingSearchSpace[CC_id] = 0; - common_configuration->ra_SearchSpace[CC_id] = 0; - common_configuration->PDCCH_common_controlResourceSetId[CC_id] = 0; - common_configuration->PDCCH_common_ControlResourceSet_duration[CC_id] = 0; - common_configuration->PDCCH_cce_REG_MappingType[CC_id] = 0; - common_configuration->PDCCH_reg_BundleSize[CC_id] = 0; - common_configuration->PDCCH_interleaverSize[CC_id] = 0; - common_configuration->PDCCH_shiftIndex[CC_id] = 0; - common_configuration->PDCCH_precoderGranularity[CC_id] = 0; - common_configuration->PDCCH_TCI_StateId[CC_id] = 0; - common_configuration->tci_PresentInDCI[CC_id] = 0; - common_configuration->PDCCH_DMRS_ScramblingID[CC_id] = 0; - common_configuration->SearchSpaceId[CC_id] = 0; - common_configuration->commonSearchSpaces_controlResourceSetId[CC_id] = 0; - common_configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_choice[CC_id] = 0; - common_configuration->SearchSpace_monitoringSlotPeriodicityAndOffset_value[CC_id] = 0; - common_configuration->SearchSpace_duration[CC_id] = 0; - common_configuration->SearchSpace_nrofCandidates_aggregationLevel1[CC_id] = 0; - common_configuration->SearchSpace_nrofCandidates_aggregationLevel2[CC_id] = 0; - common_configuration->SearchSpace_nrofCandidates_aggregationLevel4[CC_id] = 0; - common_configuration->SearchSpace_nrofCandidates_aggregationLevel8[CC_id] = 0; - common_configuration->SearchSpace_nrofCandidates_aggregationLevel16[CC_id] = 0; - common_configuration->SearchSpace_searchSpaceType[CC_id] = 0; - common_configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1[CC_id] = 0; - common_configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2[CC_id] = 0; - common_configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4[CC_id] = 0; - common_configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8[CC_id] = 0; - common_configuration->Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16[CC_id] = 0; - common_configuration->Common_dci_Format2_3_monitoringPeriodicity[CC_id] = 0; - common_configuration->Common_dci_Format2_3_nrofPDCCH_Candidates[CC_id] = 0; - common_configuration->ue_Specific__dci_Formats[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_carrierFreqDL[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_carrierBandwidthDL[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_nrofCRS_Ports[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_v_Shift[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_radioframeAllocationPeriod[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_radioframeAllocationOffset[CC_id] = 0; - common_configuration->RateMatchPatternLTE_CRS_subframeAllocation_choice[CC_id] = 0; -} - void rrc_config_rlc_bearer(uint8_t Mod_id, int CC_id, rlc_bearer_config_t *rlc_config diff --git a/openair2/RRC/NR/nr_rrc_defs.h b/openair2/RRC/NR/nr_rrc_defs.h index 6b4a9864c7..02b4154c41 100644 --- a/openair2/RRC/NR/nr_rrc_defs.h +++ b/openair2/RRC/NR/nr_rrc_defs.h @@ -46,16 +46,10 @@ //#include "COMMON/mac_rrc_primitives.h" #include "NR_SIB1.h" -//#include "SystemInformation.h" -//#include "RRCConnectionReconfiguration.h" #include "NR_RRCReconfigurationComplete.h" #include "NR_RRCReconfiguration.h" -//#include "RRCConnectionReconfigurationComplete.h" -//#include "RRCConnectionSetup.h" -//#include "RRCConnectionSetupComplete.h" -//#include "RRCConnectionRequest.h" -//#include "RRCConnectionReestablishmentRequest.h" #include "NR_RRCReestablishmentRequest.h" +#include "NR_BCCH-BCH-Message.h" #include "NR_BCCH-DL-SCH-Message.h" #include "NR_BCCH-BCH-Message.h" #include "NR_PLMN-IdentityInfo.h" @@ -66,6 +60,7 @@ //#include "AS-Config.h" //#include "AS-Context.h" #include "NR_UE-NR-Capability.h" +#include "NR_UE-MRDC-Capability.h" #include "NR_MeasResults.h" #include "NR_CellGroupConfig.h" #include "NR_ServingCellConfigCommon.h" @@ -86,12 +81,12 @@ /*I will change the name of the structure for compile purposes--> hope not to undo this process*/ typedef unsigned int uid_nr_t; -#define NR_UID_LINEAR_ALLOCATOR_BITMAP_SIZE (((NUMBER_OF_NR_UE_MAX/8)/sizeof(unsigned int)) + 1) +#define NR_UID_LINEAR_ALLOCATOR_BITMAP_SIZE (((MAX_MOBILES_PER_GNB/8)/sizeof(unsigned int)) + 1) -/*typedef struct nr_uid_linear_allocator_s { +typedef struct nr_uid_linear_allocator_s { unsigned int bitmap[NR_UID_LINEAR_ALLOCATOR_BITMAP_SIZE]; -} nr_uid_allocator_t;*/ - +} nr_uid_allocator_t; + #define PROTOCOL_NR_RRC_CTXT_UE_FMT PROTOCOL_CTXT_FMT #define PROTOCOL_NR_RRC_CTXT_UE_ARGS(CTXT_Pp) PROTOCOL_CTXT_ARGS(CTXT_Pp) @@ -121,7 +116,6 @@ typedef enum UE_STATE_NR_e { } NR_UE_STATE_t; -//#define NUMBER_OF_NR_UE_MAX MAX_MOBILES_PER_RG #define RRM_FREE(p) if ( (p) != NULL) { free(p) ; p=NULL ; } #define RRM_MALLOC(t,n) (t *) malloc16( sizeof(t) * n ) #define RRM_CALLOC(t,n) (t *) malloc16( sizeof(t) * n) @@ -271,7 +265,14 @@ typedef struct gNB_RRC_UE_s { HANDOVER_INFO *handover_info; NR_MeasResults_t *measResults; - NR_UE_NR_Capability_t *UE_Capability; + + NR_UE_NR_Capability_t* UE_Capability_nr; + NR_UE_MRDC_Capability_t* UE_Capability_MRDC; + + NR_CellGroupConfig_t *secondaryCellGroup; + NR_RRCReconfiguration_t *reconfig; + NR_RadioBearerConfig_t *rb_config; + ImsiMobileIdentity_t imsi; #if defined(ENABLE_SECURITY) @@ -374,24 +375,15 @@ typedef struct { uint8_t *ServingCellConfigCommon; uint8_t sizeof_servingcellconfigcommon; - //implicit parameters needed - int physCellId; - int Ncp; //cyclic prefix for DL - int Ncp_UL; //cyclic prefix for UL - int p_gNB; //number of tx antenna port - int p_rx_gNB; //number of receiving antenna ports - uint64_t dl_CarrierFreq; //detected by the UE - uint64_t ul_CarrierFreq; //detected by the UE - - //are the only static one (memory has been already allocated) NR_BCCH_BCH_Message_t mib; + int ssb_SubcarrierOffset; + int pdsch_AntennaPorts; NR_BCCH_DL_SCH_Message_t *siblock1; - NR_ServingCellConfigCommon_t *servingcellconfigcommon; - - + NR_CellGroupConfig_t *secondaryCellGroup[MAX_NR_RRC_UE_CONTEXTS]; NR_SRB_INFO SI; NR_SRB_INFO Srb0; + int initial_csi_index[MAX_NR_RRC_UE_CONTEXTS]; } rrc_gNB_carrier_data_t; //--------------------------------------------------- @@ -401,19 +393,15 @@ typedef struct { //---NR---(completely change)--------------------- typedef struct gNB_RRC_INST_s { + int module_id; eth_params_t eth_params_s; - rrc_gNB_carrier_data_t carrier[MAX_NUM_CCs]; - uid_allocator_t uid_allocator; // for rrc_ue_head + rrc_gNB_carrier_data_t carrier; + nr_uid_allocator_t uid_allocator; // for rrc_ue_head RB_HEAD(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s) rrc_ue_head; // ue_context tree key search by rnti - - uint8_t Nb_ue; - + int Nb_ue; hash_table_t *initial_id2_s1ap_ids; // key is content is rrc_ue_s1ap_ids_t hash_table_t *s1ap_id2_s1ap_ids ; // key is content is rrc_ue_s1ap_ids_t - //RRC configuration - gNB_RrcConfigurationReq configuration;//rrc_messages_types.h - // other PLMN parameters /// Mobile country code int mcc; diff --git a/openair2/RRC/NR/nr_rrc_proto.h b/openair2/RRC/NR/nr_rrc_proto.h index ce90ee46fb..5770b80595 100644 --- a/openair2/RRC/NR/nr_rrc_proto.h +++ b/openair2/RRC/NR/nr_rrc_proto.h @@ -33,6 +33,12 @@ #include "RRC/NR/nr_rrc_defs.h" #include "flexran_agent_extern.h" +#include "NR_RRCReconfiguration.h" +#include "NR_UE-NR-Capability.h" +#include "NR_UE-CapabilityRAT-ContainerList.h" +#include "LTE_UE-CapabilityRAT-ContainerList.h" +#include "NR_CG-Config.h" +#include "NR_CG-ConfigInfo.h" int rrc_init_nr_global_param(void); @@ -57,6 +63,35 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( rrc_gNB_ue_context_t *const ue_context_pP ); +struct rrc_gNB_ue_context_s *rrc_gNB_allocate_new_UE_context(gNB_RRC_INST *rrc_instance_pP); + +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList); + +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p); + +void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, + NR_CellGroupConfig_t *secondaryCellGroup, + int scg_id, + int servCellIndex, + int n_physical_antenna_ports, + int initial_csi_index); + +void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon, + NR_RRCReconfiguration_IEs_t *reconfig, + NR_CellGroupConfig_t *secondaryCellGroup, + int n_physical_antenna_ports, + int initial_csi_index); + +void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig); + +int generate_CG_Config(gNB_RRC_INST *rrc, + NR_CG_Config_t *cg_Config, + NR_RRCReconfiguration_t *reconfig, + NR_RadioBearerConfig_t *rbconfig); + +int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo); + + /**\brief RRC eNB task. \param void *args_p Pointer on arguments to start the task. */ diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index 586fcd3492..fba6610554 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -49,6 +49,8 @@ #include "NR_DL-DCCH-Message.h" #include "NR_CellGroupConfig.h" #include "NR_MeasResults.h" +#include "LTE_UECapabilityInformation.h" +#include "LTE_UL-DCCH-Message.h" #include "rlc.h" #include "rrc_eNB_UE_context.h" @@ -74,31 +76,17 @@ #include "pdcp.h" #include "gtpv1u_eNB_task.h" + #include "intertask_interface.h" - - -#if ENABLE_RAL - #include "rrc_eNB_ral.h" -#endif - #include "SIMULATION/TOOLS/sim.h" // for taus +#include "executables/softmodem-common.h" + //#define XER_PRINT extern RAN_CONTEXT_t RC; -#ifdef PHY_EMUL - extern EMULATION_VARS *Emul_vars; -#endif -//extern eNB_MAC_INST *eNB_mac_inst; -//extern UE_MAC_INST *UE_mac_inst; -#ifdef BIGPHYSAREA - extern void *bigphys_malloc(int); -#endif - -extern uint16_t two_tier_hexagonal_cellIds[7]; - mui_t rrc_gNB_mui = 0; ///---------------------------------------------------------------------------------------------------------------/// @@ -107,12 +95,11 @@ mui_t rrc_gNB_mui = 0; void openair_nr_rrc_on(const protocol_ctxt_t *const ctxt_pP) { LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" gNB:OPENAIR NR RRC IN....\n",PROTOCOL_NR_RRC_CTXT_ARGS(ctxt_pP)); - for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].SI, BCCH, 1); - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].SI.Active = 1; - rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].Srb0, CCCH, 1); - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].Srb0.Active = 1; - } + rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.SI, BCCH, 1); + RC.nrrrc[ctxt_pP->module_id]->carrier.SI.Active = 1; + rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0, CCCH, 1); + RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0.Active = 1; + } ///---------------------------------------------------------------------------------------------------------------/// @@ -185,108 +172,181 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ue_context_pP->ue_context.primaryCC_id, physicalCellGroupConfig, physicalcellgroup_config); - do_SpCellConfig(ctxt_pP->module_id, - ue_context_pP->ue_context.primaryCC_id, + + do_SpCellConfig(RC.nrrrc[ctxt_pP->module_id], spCellConfig); } ///---------------------------------------------------------------------------------------------------------------/// ///---------------------------------------------------------------------------------------------------------------/// -static void init_NR_SI(const protocol_ctxt_t *const ctxt_pP, - const int CC_id, - gNB_RrcConfigurationReq *configuration +static void init_NR_SI(gNB_RRC_INST *rrc) { + - ) { - //int i; LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__); - // copy basic parameters - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].physCellId = configuration->Nid_cell[CC_id]; - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].p_gNB = configuration->nb_antenna_ports[CC_id]; - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].Ncp = configuration->DL_prefix_type[CC_id]; - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].Ncp_UL = configuration->UL_prefix_type[CC_id]; - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].dl_CarrierFreq = configuration->downlink_frequency[CC_id]; - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].ul_CarrierFreq = configuration->downlink_frequency[CC_id]+ configuration->uplink_frequency_offset[CC_id]; - ///MIB - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_MIB = 0; - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].MIB = (uint8_t *) malloc16(4); - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_MIB = do_MIB_NR(&RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id],0, - configuration->MIB_ssb_SubcarrierOffset[CC_id], - configuration->pdcch_ConfigSIB1[CC_id], - configuration->MIB_subCarrierSpacingCommon[CC_id], - configuration->MIB_dmrs_TypeA_Position[CC_id] - ); - do_SERVINGCELLCONFIGCOMMON(ctxt_pP->module_id, - CC_id, - configuration, - 1 - ); + + + + rrc->carrier.MIB = (uint8_t*) malloc16(4); + rrc->carrier.sizeof_MIB = do_MIB_NR(rrc,0); + + LOG_I(NR_RRC,"Done init_NR_SI\n"); - rrc_mac_config_req_gNB(ctxt_pP->module_id, - CC_id, - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].physCellId, - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].p_gNB, - configuration->nr_band[CC_id], - configuration->ServingCellConfigCommon_ssb_PositionsInBurst_PR[CC_id], - configuration->ServingCellConfigCommon_ssb_periodicityServingCell[CC_id], - RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].dl_CarrierFreq, - configuration->N_RB_DL[CC_id], - (NR_BCCH_BCH_Message_t *)&RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].mib, - (NR_ServingCellConfigCommon_t *)&RC.nrrrc[ctxt_pP->module_id]->carrier[CC_id].servingcellconfigcommon - ); + + + rrc_mac_config_req_gNB(rrc->module_id, + rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.pdsch_AntennaPorts, + (NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon, + 0, + 0, + (NR_CellGroupConfig_t *)NULL + ); + + + if (get_softmodem_params()->phy_test > 0) { + // This is for phytest only, emulate first X2 message if uecap.raw file is present + FILE *fd; + + fd = fopen("uecap.raw","r"); + if (fd != NULL) { + char buffer[4096]; + int msg_len=fread(buffer,1,4096,fd); + LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); + LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message; + + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_LTE_UL_DCCH_Message, + (void **)<E_UL_DCCH_Message, + (uint8_t *)buffer, + msg_len); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + return; + } + fclose(fd); + xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); + // recreate enough of X2 EN-DC Container + AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, + "ueCapabilityInformation not present\n"); + NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); + CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); + CG_ConfigInfo->criticalExtensions.choice.c1->present = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); + NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; + cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, + (const char *)buffer, + (enc_rval.encoded+7)>>3); + parse_CG_ConfigInfo(rrc,CG_ConfigInfo); + } + else { + struct rrc_gNB_ue_context_s *ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); + + LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); + rrc_add_nsa_user(rrc,ue_context_p); + } + } } char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigurationReq *configuration) { protocol_ctxt_t ctxt; - int CC_id; + + gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gnb_mod_idP, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,gnb_mod_idP); + LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Init...\n", PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); #if OCP_FRAMEWORK - while ( RC.nrrrc[gnb_mod_idP] == NULL ) { + while (rrc == NULL ) { LOG_E(NR_RRC, "RC.nrrrc not yet initialized, waiting 1 second\n"); sleep(1); } - -#endif - AssertFatal(RC.nrrrc[gnb_mod_idP] != NULL, "RC.nrrrc not initialized!"); +#endif + AssertFatal(rrc != NULL, "RC.nrrrc not initialized!"); AssertFatal(NUMBER_OF_UE_MAX < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow"); AssertFatal(configuration!=NULL,"configuration input is null\n"); + rrc->module_id = gnb_mod_idP; + rrc->Nb_ue = 0; + + rrc->carrier.Srb0.Active = 0; - RC.nrrrc[ctxt.module_id]->Nb_ue = 0; - - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - RC.nrrrc[ctxt.module_id]->carrier[CC_id].Srb0.Active = 0; - } - - uid_linear_allocator_init(&RC.nrrrc[ctxt.module_id]->uid_allocator); - RB_INIT(&RC.nrrrc[ctxt.module_id]->rrc_ue_head); - RC.nrrrc[ctxt.module_id]->initial_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); - RC.nrrrc[ctxt.module_id]->s1ap_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); - memcpy(&RC.nrrrc[ctxt.module_id]->configuration,configuration,sizeof(gNB_RrcConfigurationReq)); + nr_uid_linear_allocator_init(&rrc->uid_allocator); + RB_INIT(&rrc->rrc_ue_head); + rrc->initial_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); + rrc->s1ap_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); + rrc->carrier.servingcellconfigcommon = configuration->scc; + rrc->carrier.ssb_SubcarrierOffset = configuration->ssb_SubcarrierOffset; + rrc->carrier.pdsch_AntennaPorts = configuration->pdsch_AntennaPorts; /// System Information INIT LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Checking release \n",PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - init_NR_SI(&ctxt, - CC_id, - configuration - ); - }//END for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) - + init_NR_SI(rrc); rrc_init_nr_global_param(); openair_nr_rrc_on(&ctxt); return 0; }//END openair_rrc_gNB_configuration -///---------------------------------------------------------------------------------------------------------------/// -///---------------------------------------------------------------------------------------------------------------/// +void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) { + LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; + + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_LTE_UL_DCCH_Message, + (void **)<E_UL_DCCH_Message, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); + +/* asn_dec_rval_t dec_rval = uper_decode( NULL, + &asn_DEF_LTE_UL_DCCH_Message, + (void **)<E_UL_DCCH_Message, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size, 0, 0);//m->rrc_buffer_size); +*/ + gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + return; + } + xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); + // recreate enough of X2 EN-DC Container + AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, + "ueCapabilityInformation not present\n"); + NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); + CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); + CG_ConfigInfo->criticalExtensions.choice.c1->present = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); + NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; + cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, + (const char *)m->rrc_buffer, + (enc_rval.encoded+7)>>3); + parse_CG_ConfigInfo(rrc,CG_ConfigInfo); + +} + +///---------------------------------------------------------------------------------------------------------------/// +///---------------------------------------------------------------------------------------------------------------/// void *rrc_gnb_task(void *args_p) { MessageDef *msg_p; const char *msg_name_p; @@ -380,6 +440,17 @@ void *rrc_gnb_task(void *args_p) { openair_rrc_gNB_configuration(GNB_INSTANCE_TO_MODULE_ID(instance), &NRRRC_CONFIGURATION_REQ(msg_p)); break; + /* Messages from X2AP */ + case X2AP_ENDC_SGNB_ADDITION_REQ: + LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); + rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); + break; + + case X2AP_ENDC_SGNB_RECONF_COMPLETE: + LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); + break; + + default: LOG_E(NR_RRC, "[gNB %d] Received unexpected message %s\n", instance, msg_name_p); break; diff --git a/openair2/RRC/NR_UE/main_ue.c b/openair2/RRC/NR_UE/main_ue.c index 6929040034..07409c6026 100644 --- a/openair2/RRC/NR_UE/main_ue.c +++ b/openair2/RRC/NR_UE/main_ue.c @@ -34,11 +34,8 @@ #include "rrc_proto.h" #include "common/utils/LOG/log.h" -int nr_l3_init_ue(void){ - LOG_I(RRC, "[MAIN] NR UE MAC initialization...\n"); - - openair_rrc_top_init_ue_nr(); - - return 0; +NR_UE_RRC_INST_t* nr_l3_init_ue(char* rrc_config_path){ + //LOG_I(RRC, "[MAIN] NR UE MAC initialization...\n"); + return openair_rrc_top_init_ue_nr(rrc_config_path); } diff --git a/openair2/RRC/NR_UE/rrc_UE.c b/openair2/RRC/NR_UE/rrc_UE.c index 7db6be499e..87e899845e 100755 --- a/openair2/RRC/NR_UE/rrc_UE.c +++ b/openair2/RRC/NR_UE/rrc_UE.c @@ -44,7 +44,7 @@ #include "rrc_vars.h" #include "mac_proto.h" - +#include "executables/softmodem-common.h" // from LTE-RRC DL-DCCH RRCConnectionReconfiguration nr-secondary-cell-group-config (encoded) @@ -80,11 +80,19 @@ int8_t nr_rrc_ue_decode_secondary_cellgroup_config( SEQUENCE_free(&asn_DEF_NR_CellGroupConfig, (void *)cell_group_config, 0); } - //nr_rrc_mac_config_req_ue( module_id_t module_id, int CC_id, uint8_t gNB_index, NR_MIB_t *mibP, NR_MAC_CellGroupConfig_t *mac_cell_group_configP, NR_PhysicalCellGroupConfig_t *phy_cell_group_configP, NR_SpCellConfig_t *spcell_configP ); + //nr_rrc_mac_config_req_ue( 0,0,0,NULL, cell_group_config->mac_CellGroupConfig, cell_group_config->physicalCellGroupConfig, cell_group_config->spCellConfig ); return 0; } +int8_t nr_rrc_ue_process_RadioBearerConfig(NR_RadioBearerConfig_t *RadioBearerConfig){ + + + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)RadioBearerConfig); + // Configure PDCP + + return 0; +} // from LTE-RRC DL-DCCH RRCConnectionReconfiguration nr-secondary-cell-group-config (decoded) // RRCReconfiguration @@ -96,7 +104,7 @@ int8_t nr_rrc_ue_process_rrcReconfiguration(NR_RRCReconfiguration_t *rrcReconfig if(NR_UE_rrc_inst->radio_bearer_config == NULL){ NR_UE_rrc_inst->radio_bearer_config = rrcReconfiguration->criticalExtensions.choice.rrcReconfiguration->radioBearerConfig; }else{ - nr_rrc_ue_process_radio_bearer_config(rrcReconfiguration->criticalExtensions.choice.rrcReconfiguration->radioBearerConfig); + nr_rrc_ue_process_RadioBearerConfig(rrcReconfiguration->criticalExtensions.choice.rrcReconfiguration->radioBearerConfig); } } @@ -108,14 +116,17 @@ int8_t nr_rrc_ue_process_rrcReconfiguration(NR_RRCReconfiguration_t *rrcReconfig (uint8_t *)rrcReconfiguration->criticalExtensions.choice.rrcReconfiguration->secondaryCellGroup->buf, rrcReconfiguration->criticalExtensions.choice.rrcReconfiguration->secondaryCellGroup->size, 0, 0); + xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)cellGroupConfig); + if(NR_UE_rrc_inst->cell_group_config == NULL){ // first time receive the configuration, just use the memory allocated from uper_decoder. TODO this is not good implementation, need to maintain RRC_INST own structure every time. NR_UE_rrc_inst->cell_group_config = cellGroupConfig; nr_rrc_ue_process_scg_config(cellGroupConfig); }else{ // after first time, update it and free the memory after. + SEQUENCE_free(&asn_DEF_NR_CellGroupConfig, (void *)NR_UE_rrc_inst->cell_group_config, 0); + NR_UE_rrc_inst->cell_group_config = cellGroupConfig; nr_rrc_ue_process_scg_config(cellGroupConfig); - SEQUENCE_free(&asn_DEF_NR_CellGroupConfig, (void *)cellGroupConfig, 0); } } @@ -148,6 +159,8 @@ int8_t nr_rrc_ue_process_rrcReconfiguration(NR_RRCReconfiguration_t *rrcReconfig return 0; } + + int8_t nr_rrc_ue_process_meas_config(NR_MeasConfig_t *meas_config){ return 0; @@ -156,8 +169,7 @@ int8_t nr_rrc_ue_process_meas_config(NR_MeasConfig_t *meas_config){ int8_t nr_rrc_ue_process_scg_config(NR_CellGroupConfig_t *cell_group_config){ int i; if(NR_UE_rrc_inst->cell_group_config==NULL){ - // initial list - + // initial list if(cell_group_config->spCellConfig != NULL){ if(cell_group_config->spCellConfig->spCellConfigDedicated != NULL){ if(cell_group_config->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList != NULL){ @@ -167,8 +179,6 @@ int8_t nr_rrc_ue_process_scg_config(NR_CellGroupConfig_t *cell_group_config){ } } } - - }else{ // maintain list if(cell_group_config->spCellConfig != NULL){ @@ -197,13 +207,57 @@ int8_t nr_rrc_ue_process_scg_config(NR_CellGroupConfig_t *cell_group_config){ return 0; } -int8_t nr_rrc_ue_process_radio_bearer_config(NR_RadioBearerConfig_t *radio_bearer_config){ - return 0; + + + +void process_nsa_message(NR_UE_RRC_INST_t *rrc, nsa_message_t nsa_message_type, void *message,int msg_len) { + + switch (nsa_message_type) { + case nr_SecondaryCellGroupConfig_r15: + { + NR_RRCReconfiguration_t *RRCReconfiguration=NULL; + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_RRCReconfiguration, + (void **)&RRCReconfiguration, + (uint8_t *)message, + msg_len); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC,"NR_RRCReconfiguration decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_RRCReconfiguration, RRCReconfiguration, 1 ); + return; + } + nr_rrc_ue_process_rrcReconfiguration(RRCReconfiguration); + } + break; + case nr_RadioBearerConfigX_r15: + { + NR_RadioBearerConfig_t *RadioBearerConfig=NULL; + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_RadioBearerConfig, + (void **)&RadioBearerConfig, + (uint8_t *)message, + msg_len); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC,"NR_RadioBearerConfig decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_RadioBearerConfig, RadioBearerConfig, 1 ); + return; + } + nr_rrc_ue_process_RadioBearerConfig(RadioBearerConfig); + } + break; + default: + AssertFatal(1==0,"Unknown message %d\n",nsa_message_type); + break; + } + } - -int8_t openair_rrc_top_init_ue_nr(void){ +NR_UE_RRC_INST_t* openair_rrc_top_init_ue_nr(char* rrc_config_path){ if(NB_NR_UE_INST > 0){ NR_UE_rrc_inst = (NR_UE_RRC_INST_t *)malloc(NB_NR_UE_INST * sizeof(NR_UE_RRC_INST_t)); @@ -264,11 +318,44 @@ int8_t openair_rrc_top_init_ue_nr(void){ RRC_LIST_INIT(NR_UE_rrc_inst->CSI_SSB_ResourceSet_list, NR_maxNrofCSI_SSB_ResourceSets); RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ResourceConfig_list, NR_maxNrofCSI_ResourceConfigurations); RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ReportConfig_list, NR_maxNrofCSI_ReportConfigurations); + + if (get_softmodem_params()->phy_test==1) { + // read in files for RRCReconfiguration and RBconfig + FILE *fd; + char filename[1024]; + if (rrc_config_path) + sprintf(filename,"%s/reconfig.raw",rrc_config_path); + else + sprintf(filename,"reconfig.raw"); + fd = fopen(filename,"r"); + char buffer[1024]; + AssertFatal(fd, + "cannot read file %s: errno %d, %s\n", + filename, + errno, + strerror(errno)); + int msg_len=fread(buffer,1,1024,fd); + fclose(fd); + process_nsa_message(NR_UE_rrc_inst, nr_SecondaryCellGroupConfig_r15, buffer,msg_len); + if (rrc_config_path) + sprintf(filename,"%s/rbconfig.raw",rrc_config_path); + else + sprintf(filename,"rbconfig.raw"); + fd = fopen(filename,"r"); + AssertFatal(fd, + "cannot read file %s: errno %d, %s\n", + filename, + errno, + strerror(errno)); + msg_len=fread(buffer,1,1024,fd); + fclose(fd); + process_nsa_message(NR_UE_rrc_inst, nr_RadioBearerConfigX_r15, buffer,msg_len); + } }else{ NR_UE_rrc_inst = NULL; } - return 0; + return NR_UE_rrc_inst; } @@ -339,7 +426,7 @@ int8_t nr_rrc_ue_decode_NR_BCCH_BCH_Message( // (void *)&bcch_message->message.choice.mib, // sizeof(NR_MIB_t) ); - nr_rrc_mac_config_req_ue( 0, 0, 0, mib, NULL, NULL, NULL); + nr_rrc_mac_config_req_ue( 0, 0, 0, mib, NULL); } return 0; diff --git a/openair2/RRC/NR_UE/rrc_defs.h b/openair2/RRC/NR_UE/rrc_defs.h index e2b22ef243..cb1207757d 100644 --- a/openair2/RRC/NR_UE/rrc_defs.h +++ b/openair2/RRC/NR_UE/rrc_defs.h @@ -58,12 +58,17 @@ typedef uint32_t channel_t; +typedef enum { + nr_SecondaryCellGroupConfig_r15=0, + nr_RadioBearerConfigX_r15=1 +} nsa_message_t; + typedef struct NR_UE_RRC_INST_s { NR_MeasConfig_t *meas_config; NR_CellGroupConfig_t *cell_group_config; NR_RadioBearerConfig_t *radio_bearer_config; - + NR_MIB_t *mib; // lists diff --git a/openair2/RRC/NR_UE/rrc_proto.h b/openair2/RRC/NR_UE/rrc_proto.h index 111a9d2dd1..6e0d0a10de 100644 --- a/openair2/RRC/NR_UE/rrc_proto.h +++ b/openair2/RRC/NR_UE/rrc_proto.h @@ -43,14 +43,14 @@ // main_rrc.c // /**\brief Layer 3 initialization*/ -int nr_l3_init_ue(void); +NR_UE_RRC_INST_t* nr_l3_init_ue(char*); // // UE_rrc.c // /**\brief Initial the top level RRC structure instance*/ -int8_t openair_rrc_top_init_ue_nr(void); +NR_UE_RRC_INST_t* openair_rrc_top_init_ue_nr(char*); diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c index b7ccb07461..b297c96e56 100644 --- a/openair2/X2AP/x2ap_eNB.c +++ b/openair2/X2AP/x2ap_eNB.c @@ -101,7 +101,6 @@ void x2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_enb_data_p; DevAssert(sctp_new_association_resp != NULL); - printf("x2ap_eNB_handle_sctp_association_resp at 1\n"); dump_trees(); instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); @@ -129,7 +128,6 @@ void x2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa x2ap_enb_data_p = x2ap_get_eNB(instance_p, -1, sctp_new_association_resp->ulp_cnx_id); DevAssert(x2ap_enb_data_p != NULL); - printf("x2ap_eNB_handle_sctp_association_resp at 2\n"); dump_trees(); if (sctp_new_association_resp->sctp_state != SCTP_STATE_ESTABLISHED) { @@ -142,17 +140,17 @@ void x2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa return; } - printf("x2ap_eNB_handle_sctp_association_resp at 3\n"); dump_trees(); /* Update parameters */ x2ap_enb_data_p->assoc_id = sctp_new_association_resp->assoc_id; x2ap_enb_data_p->in_streams = sctp_new_association_resp->in_streams; x2ap_enb_data_p->out_streams = sctp_new_association_resp->out_streams; - printf("x2ap_eNB_handle_sctp_association_resp at 4\n"); dump_trees(); /* Prepare new x2 Setup Request */ - x2ap_eNB_generate_x2_setup_request(instance_p, x2ap_enb_data_p); - //x2ap_eNB_generate_ENDC_x2_setup_request(instance_p, x2ap_enb_data_p); + if(instance_p->cell_type == CELL_MACRO_GNB) + x2ap_gNB_generate_ENDC_x2_setup_request(instance_p, x2ap_enb_data_p); + else + x2ap_eNB_generate_x2_setup_request(instance_p, x2ap_enb_data_p); } static @@ -448,6 +446,78 @@ void x2ap_eNB_handle_handover_req_ack(instance_t instance, x2ap_eNB_generate_x2_handover_request_ack(instance_p, target, x2ap_handover_req_ack); } +static +void x2ap_eNB_handle_sgNB_add_req(instance_t instance, + x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req) +{ + x2ap_id_manager *id_manager; + x2ap_eNB_instance_t *instance_p; + x2ap_eNB_data_t *x2ap_eNB_data; + int ue_id; + + /* TODO: remove hardcoded value */ + x2ap_eNB_data = x2ap_is_eNB_id_in_list(3584); + DevAssert(x2ap_eNB_data != NULL); + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + + /* allocate x2ap ID */ + id_manager = &instance_p->id_manager; + ue_id = x2ap_allocate_new_id(id_manager); + if (ue_id == -1) { + X2AP_ERROR("could not allocate a new X2AP UE ID\n"); + /* TODO: cancel NSA: send (to be defined) message to RRC */ + exit(1); + } + /* id_source is ue_id, id_target is unknown yet */ + x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req->rnti, ue_id, -1); + x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_NSA_PREPARE); + + x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_eNB_data, ue_id); +} + +static +void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, + x2ap_ENDC_sgnb_addition_req_ACK_t *x2ap_ENDC_sgnb_addition_req_ACK) +{ + /* TODO: remove this hack (the goal is to find the correct + * eNodeB structure for the other end) - we need a proper way for RRC + * and X2AP to identify eNodeBs + * RRC knows about mod_id and X2AP knows about eNB_id (eNB_ID in + * the configuration file) + * as far as I understand.. CROUX + */ + + + x2ap_eNB_instance_t *instance_p; + x2ap_eNB_data_t *target; + /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; + int ue_id; + int id_source; + int id_target;*/ + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + + /*target = x2ap_get_eNB(NULL, source_assoc_id, 0); + DevAssert(target != NULL);*/ + + // rnti is a new information, save it + + /*ue_id = x2ap_handover_req_ack->x2_id_target; + id_source = x2ap_id_get_id_source(&instance_p->id_manager, ue_id); + id_target = ue_id; + x2ap_set_ids(&instance_p->id_manager, ue_id, x2ap_handover_req_ack->rnti, id_source, id_target);*/ + + + //target = x2ap_get_eNB(NULL, 17, 0); + target = x2ap_is_eNB_id_in_list (3585); //Currently hardcoded. Need to extract it differently + DevAssert(target != NULL); + x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, x2ap_ENDC_sgnb_addition_req_ACK, 0); +} + + static void x2ap_eNB_ue_context_release(instance_t instance, x2ap_ue_context_release_t *x2ap_ue_context_release) @@ -513,6 +583,17 @@ void *x2ap_task(void *arg) { &X2AP_UE_CONTEXT_RELEASE(received_msg)); break; + case X2AP_ENDC_SGNB_ADDITION_REQ: + x2ap_eNB_handle_sgNB_add_req(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &X2AP_ENDC_SGNB_ADDITION_REQ(received_msg)); + break; + + case X2AP_ENDC_SGNB_ADDITION_REQ_ACK: + x2ap_gNB_trigger_sgNB_add_req_ack(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(received_msg)); + LOG_I(X2AP, "Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK \n"); + break; + case SCTP_INIT_MSG_MULTI_CNF: x2ap_eNB_handle_sctp_init_msg_multi_cnf(ITTI_MESSAGE_GET_INSTANCE(received_msg), &received_msg->ittiMsg.sctp_init_msg_multi_cnf); @@ -556,7 +637,6 @@ int is_x2ap_enabled(void) static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER; if (pthread_mutex_lock(&mutex)) goto mutex_error; - if (config_loaded) { if (pthread_mutex_unlock(&mutex)) goto mutex_error; return enabled; @@ -569,13 +649,20 @@ int is_x2ap_enabled(void) /* TODO: do it per module - we check only first eNB */ config_get(p, sizeof(p)/sizeof(paramdef_t), "eNBs.[0]"); - if (enable_x2 != NULL && strcmp(enable_x2, "yes") == 0) - enabled = 1; + if (enable_x2 != NULL && strcmp(enable_x2, "yes") == 0){ + enabled = 1; + } + + /*Consider also the case of enabling X2AP for a gNB by parsing a gNB configuration file*/ + + config_get(p, sizeof(p)/sizeof(paramdef_t), "gNBs.[0]"); + if (enable_x2 != NULL && strcmp(enable_x2, "yes") == 0){ + enabled = 1; + } config_loaded = 1; if (pthread_mutex_unlock(&mutex)) goto mutex_error; - return enabled; mutex_error: diff --git a/openair2/X2AP/x2ap_eNB_decoder.c b/openair2/X2AP/x2ap_eNB_decoder.c index 7b178fb109..93b82c2765 100644 --- a/openair2/X2AP/x2ap_eNB_decoder.c +++ b/openair2/X2AP/x2ap_eNB_decoder.c @@ -60,8 +60,14 @@ static int x2ap_eNB_decode_initiating_message(X2AP_X2AP_PDU_t *pdu) break; case X2AP_ProcedureCode_id_endcX2Setup: - X2AP_INFO("X2AP_ProcedureCode_id_endcX2Setup message!\n"); - break; + X2AP_INFO("X2AP_ProcedureCode_id_endcX2Setup message!\n"); + break; + case X2AP_ProcedureCode_id_sgNBAdditionPreparation: + X2AP_INFO("X2AP_ProcedureCode_id_sgNBAdditionPreparation message!\n"); + break; + case X2AP_ProcedureCode_id_sgNBReconfigurationCompletion: + X2AP_INFO("X2AP_ProcedureCode_id_sgNBReconfigurationCompletion message!\n"); + break; default: X2AP_ERROR("Unknown procedure ID (%d) for initiating message\n", @@ -93,6 +99,10 @@ static int x2ap_eNB_decode_successful_outcome(X2AP_X2AP_PDU_t *pdu) X2AP_INFO("x2ap_eNB_decode_successfuloutcome_message!\n"); break; + case X2AP_ProcedureCode_id_sgNBAdditionPreparation: + X2AP_INFO("x2ap_eNB_decode_successfuloutcome_message!\n"); + break; + default: X2AP_ERROR("Unknown procedure ID (%d) for successfull outcome message\n", (int)pdu->choice.successfulOutcome.procedureCode); @@ -134,9 +144,9 @@ int x2ap_eNB_decode_pdu(X2AP_X2AP_PDU_t *pdu, const uint8_t *const buffer, uint3 length, 0, 0); - if (asn1_xer_print) { + //if (asn1_xer_print) { xer_fprint(stdout, &asn_DEF_X2AP_X2AP_PDU, pdu); - } + //} if (dec_ret.code != RC_OK) { X2AP_ERROR("Failed to decode pdu\n"); diff --git a/openair2/X2AP/x2ap_eNB_encoder.c b/openair2/X2AP/x2ap_eNB_encoder.c index 8b1c030d35..392206e4d7 100644 --- a/openair2/X2AP/x2ap_eNB_encoder.c +++ b/openair2/X2AP/x2ap_eNB_encoder.c @@ -44,9 +44,9 @@ int x2ap_eNB_encode_pdu(X2AP_X2AP_PDU_t *pdu, uint8_t **buffer, uint32_t *len) DevAssert(buffer != NULL); DevAssert(len != NULL); - if (asn1_xer_print) { + //if (asn1_xer_print) { xer_fprint(stdout, &asn_DEF_X2AP_X2AP_PDU, (void *)pdu); - } + //} encoded = aper_encode_to_new_buffer(&asn_DEF_X2AP_X2AP_PDU, 0, pdu, (void **)buffer); diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index e43db6aa8a..47a3475063 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -39,6 +39,7 @@ #include "x2ap_ids.h" #include "x2ap_eNB_itti_messaging.h" +#include "X2AP_SupportedSULFreqBandItem.h" #include "msc.h" #include "assertions.h" @@ -1097,7 +1098,6 @@ int x2ap_eNB_generate_senb_addition_request (x2ap_eNB_instance_t *instance_p, x2 return ret; } -//Panos: int x2ap_eNB_generate_senb_addition_request_ack (x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, x2ap_senb_addition_req_ack_t *x2ap_addition_req_ack) { @@ -1118,8 +1118,6 @@ int x2ap_eNB_generate_senb_addition_request_ack (x2ap_eNB_instance_t *instance_p DevAssert(instance_p != NULL); DevAssert(x2ap_eNB_data_p != NULL); - //Panos: The fact that we have separate IDs here is because the ID for a specific UE might be different - //between the 2 eNBs? //ue_id = x2ap_addition_req_ack->x2_id_target; //Panos: change name to master_x2... //id_source = x2ap_id_get_id_source(&instance_p->id_manager, ue_id); //id_target = ue_id; @@ -1128,7 +1126,6 @@ int x2ap_eNB_generate_senb_addition_request_ack (x2ap_eNB_instance_t *instance_p memset(&pdu, 0, sizeof(pdu)); pdu.present = X2AP_X2AP_PDU_PR_successfulOutcome; pdu.choice.successfulOutcome.procedureCode = X2AP_ProcedureCode_id_seNBAdditionPreparation; - //Panos: What does the criticality indicate here? pdu.choice.successfulOutcome.criticality = X2AP_Criticality_reject; pdu.choice.successfulOutcome.value.present = X2AP_SuccessfulOutcome__value_PR_SeNBAdditionRequestAcknowledge; out = &pdu.choice.successfulOutcome.value.choice.SeNBAdditionRequestAcknowledge; @@ -1144,7 +1141,6 @@ int x2ap_eNB_generate_senb_addition_request_ack (x2ap_eNB_instance_t *instance_p /* mandatory */ ie = (X2AP_SeNBAdditionRequestAcknowledge_IEs_t *)calloc(1, sizeof(X2AP_SeNBAdditionRequestAcknowledge_IEs_t)); ie->id = X2AP_ProtocolIE_ID_id_SeNB_UE_X2AP_ID; - //Panos: Why for the X2_HANDOVER_REQ_ACK here the criticality is ignore whereas in the specs it is reject? ie->criticality = X2AP_Criticality_reject; ie->value.present = X2AP_SeNBAdditionRequestAcknowledge_IEs__value_PR_UE_X2AP_ID_1; ie->value.choice.UE_X2AP_ID_1 = 0; @@ -1230,17 +1226,17 @@ int x2ap_eNB_generate_senb_addition_request_ack (x2ap_eNB_instance_t *instance_p return ret; } -/*setup request message from an eNB to a gNB*/ -int x2ap_eNB_generate_ENDC_x2_setup_request( +/*setup request message from a gNB to an eNB*/ +int x2ap_gNB_generate_ENDC_x2_setup_request( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p) { - printf("In x2ap_eNB_generate_ENDC_x2_setup_request \n"); X2AP_X2AP_PDU_t pdu; X2AP_ENDCX2SetupRequest_t *out; X2AP_ENDCX2SetupRequest_IEs_t *ie; - X2AP_ENB_ENDCX2SetupReqIEs_t *ie_ENB_ENDC; + X2AP_En_gNB_ENDCX2SetupReqIEs_t *ie_GNB_ENDC; X2AP_PLMN_Identity_t *plmn; - ServedEUTRAcellsENDCX2ManagementList__Member *servedCellMember; + ServedNRcellsENDCX2ManagementList__Member *servedCellMember; + X2AP_SupportedSULFreqBandItem_t *SULFreqBandItem; uint8_t *buffer; uint32_t len; @@ -1262,24 +1258,166 @@ int x2ap_eNB_generate_ENDC_x2_setup_request( ie = (X2AP_ENDCX2SetupRequest_IEs_t *)calloc(1, sizeof(X2AP_ENDCX2SetupRequest_IEs_t)); ie->id = X2AP_ProtocolIE_ID_id_InitiatingNodeType_EndcX2Setup; ie->value.present = X2AP_ENDCX2SetupRequest_IEs__value_PR_InitiatingNodeType_EndcX2Setup; - ie->value.choice.InitiatingNodeType_EndcX2Setup.present = X2AP_InitiatingNodeType_EndcX2Setup_PR_init_eNB; + ie->value.choice.InitiatingNodeType_EndcX2Setup.present = X2AP_InitiatingNodeType_EndcX2Setup_PR_init_en_gNB; - ie_ENB_ENDC = (X2AP_ENB_ENDCX2SetupReqIEs_t *)calloc(1, sizeof(X2AP_ENB_ENDCX2SetupReqIEs_t)); + ie_GNB_ENDC = (X2AP_En_gNB_ENDCX2SetupReqIEs_t *)calloc(1, sizeof(X2AP_En_gNB_ENDCX2SetupReqIEs_t)); + ie_GNB_ENDC->id = X2AP_ProtocolIE_ID_id_Globalen_gNB_ID; + ie_GNB_ENDC->criticality = X2AP_Criticality_reject; + ie_GNB_ENDC->value.present = X2AP_En_gNB_ENDCX2SetupReqAckIEs__value_PR_GlobalGNB_ID; + ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.present = X2AP_GNB_ID_PR_gNB_ID; + INT32_TO_OCTET_STRING(instance_p->eNB_id, + &ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID); + +X2AP_INFO("%d -> %02x%02x%02x\n", instance_p->eNB_id, + ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID.buf[0], + ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID.buf[1], + ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID.buf[2]); + +MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, + &ie_GNB_ENDC->value.choice.GlobalGNB_ID.pLMN_Identity); + + ASN_SEQUENCE_ADD(&ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_en_gNB.list, ie_GNB_ENDC); + + ie_GNB_ENDC = (X2AP_En_gNB_ENDCX2SetupReqIEs_t *)calloc(1, sizeof(X2AP_En_gNB_ENDCX2SetupReqIEs_t)); + ie_GNB_ENDC->id = X2AP_ProtocolIE_ID_id_ServedNRcellsENDCX2ManagementList; + ie_GNB_ENDC->criticality = X2AP_Criticality_reject; + ie_GNB_ENDC->value.present = X2AP_En_gNB_ENDCX2SetupReqIEs__value_PR_ServedNRcellsENDCX2ManagementList; + + { + for (int i = 0; inum_cc; i++){ + servedCellMember = (ServedNRcellsENDCX2ManagementList__Member *)calloc(1,sizeof(ServedNRcellsENDCX2ManagementList__Member)); + { + servedCellMember->servedNRCellInfo.nrpCI = instance_p->Nid_cell[i]; + + MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, + &servedCellMember->servedNRCellInfo.nrCellID.pLMN_Identity); + NR_CELL_ID_TO_BIT_STRING(instance_p->eNB_id, + &servedCellMember->servedNRCellInfo.nrCellID.nRcellIdentifier); + servedCellMember->servedNRCellInfo.fiveGS_TAC = calloc(1, sizeof(X2AP_FiveGS_TAC_t)); + if (servedCellMember->servedNRCellInfo.fiveGS_TAC == NULL) + exit(1); + NR_FIVEGS_TAC_ID_TO_BIT_STRING(instance_p->tac, servedCellMember->servedNRCellInfo.fiveGS_TAC); + + X2AP_INFO("TAC: %d -> %02x%02x%02x\n", instance_p->tac, + servedCellMember->servedNRCellInfo.fiveGS_TAC->buf[0], + servedCellMember->servedNRCellInfo.fiveGS_TAC->buf[1], + servedCellMember->servedNRCellInfo.fiveGS_TAC->buf[2]); + + plmn = (X2AP_PLMN_Identity_t *)calloc(1,sizeof(X2AP_PLMN_Identity_t)); + { + MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, plmn); + ASN_SEQUENCE_ADD(&servedCellMember->servedNRCellInfo.broadcastPLMNs.list, plmn); + } + + if (instance_p->frame_type[i] == TDD) { + X2AP_FreqBandNrItem_t *freq_band; + servedCellMember->servedNRCellInfo.nrModeInfo.present = X2AP_ServedNRCell_Information__nrModeInfo_PR_tdd; + servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nRFreqInfo.nRARFCN = 0; //instance_p->tdd_nRARFCN[i]; + /* addition of Frequency Band List */ + freq_band = calloc(1, sizeof(X2AP_FreqBandNrItem_t)); + if (freq_band == NULL) + exit(1); + freq_band->freqBandIndicatorNr = 1; /* TODO: put correct value */ + + SULFreqBandItem = calloc(1, sizeof(X2AP_SupportedSULFreqBandItem_t)); + SULFreqBandItem->freqBandIndicatorNr=80; /* TODO: put correct value */ + ASN_SEQUENCE_ADD(&freq_band->supportedSULBandList.list, SULFreqBandItem); + + ASN_SEQUENCE_ADD(&servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nRFreqInfo.freqBandListNr, freq_band); + switch (instance_p->N_RB_DL[i]) { + case 50: + //This is not correct. Just to be able to test X2 only using an eNB instead of gNB + servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb51; + break; + case 93 : + servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb93; + break; + case 106: + servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb106; + break; + case 121: + servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb121; + break; + /*More cases to be added */ + default: + AssertFatal(0,"Failed: Check value for N_RB_DL/N_RB_UL"); + break; + } + } + else { + AssertFatal(0,"ENDC_X2Setuprequest not supported for FDD!"); + } + /*Don't know where to extract the value of measurementTimingConfiguration from. Set it to 0 for now */ + INT8_TO_OCTET_STRING(0, &servedCellMember->servedNRCellInfo.measurementTimingConfiguration); + } + ASN_SEQUENCE_ADD(&ie_GNB_ENDC->value.choice.ServedNRcellsENDCX2ManagementList.list, servedCellMember); + } + } + ASN_SEQUENCE_ADD(&ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_en_gNB.list, ie_GNB_ENDC); + + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + X2AP_ERROR("Failed to encode ENDC X2 setup request\n"); + return -1; + } + + MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); + + x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); + + return ret; +} + +int x2ap_eNB_generate_ENDC_x2_setup_response( + x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p) +{ + X2AP_X2AP_PDU_t pdu; + X2AP_ENDCX2SetupResponse_t *out; + X2AP_ENDCX2SetupResponse_IEs_t *ie; + X2AP_ENB_ENDCX2SetupReqAckIEs_t *ie_ENB_ENDC; + X2AP_PLMN_Identity_t *plmn; + ServedEUTRAcellsENDCX2ManagementList__Member *servedCellMember; + + uint8_t *buffer; + uint32_t len; + int ret = 0; + + DevAssert(instance_p != NULL); + DevAssert(x2ap_eNB_data_p != NULL); + + x2ap_eNB_data_p->state = X2AP_ENB_STATE_WAITING; + + /* Prepare the X2AP message to encode */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = X2AP_X2AP_PDU_PR_successfulOutcome; + pdu.choice.successfulOutcome.procedureCode = X2AP_ProcedureCode_id_endcX2Setup; + pdu.choice.successfulOutcome.criticality = X2AP_Criticality_reject; + pdu.choice.successfulOutcome.value.present = X2AP_SuccessfulOutcome__value_PR_ENDCX2SetupResponse; + out = &pdu.choice.successfulOutcome.value.choice.ENDCX2SetupResponse; + + ie = (X2AP_ENDCX2SetupResponse_IEs_t *)calloc(1, sizeof(X2AP_ENDCX2SetupResponse_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_RespondingNodeType_EndcX2Setup; + ie->value.present = X2AP_ENDCX2SetupResponse_IEs__value_PR_RespondingNodeType_EndcX2Setup; + ie->value.choice.RespondingNodeType_EndcX2Setup.present = X2AP_RespondingNodeType_EndcX2Setup_PR_respond_eNB; + + ie_ENB_ENDC = (X2AP_ENB_ENDCX2SetupReqAckIEs_t *)calloc(1, sizeof(X2AP_ENB_ENDCX2SetupReqAckIEs_t)); ie_ENB_ENDC->id = X2AP_ProtocolIE_ID_id_GlobalENB_ID; ie_ENB_ENDC->criticality = X2AP_Criticality_reject; - ie_ENB_ENDC->value.present = X2AP_ENB_ENDCX2SetupReqIEs__value_PR_GlobalENB_ID; + ie_ENB_ENDC->value.present = X2AP_ENB_ENDCX2SetupReqAckIEs__value_PR_GlobalENB_ID; ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.present = X2AP_ENB_ID_PR_macro_eNB_ID; MACRO_ENB_ID_TO_BIT_STRING(instance_p->eNB_id, &ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID); MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, &ie_ENB_ENDC->value.choice.GlobalENB_ID.pLMN_Identity); - ASN_SEQUENCE_ADD(&ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_eNB.list, ie_ENB_ENDC); + ASN_SEQUENCE_ADD(&ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_eNB.list, ie_ENB_ENDC); - ie_ENB_ENDC = (X2AP_ENB_ENDCX2SetupReqIEs_t *)calloc(1, sizeof(X2AP_ENB_ENDCX2SetupReqIEs_t)); + ie_ENB_ENDC = (X2AP_ENB_ENDCX2SetupReqAckIEs_t *)calloc(1, sizeof(X2AP_ENB_ENDCX2SetupReqAckIEs_t)); ie_ENB_ENDC->id = X2AP_ProtocolIE_ID_id_ServedEUTRAcellsENDCX2ManagementList; ie_ENB_ENDC->criticality = X2AP_Criticality_reject; - ie_ENB_ENDC->value.present = X2AP_ENB_ENDCX2SetupReqIEs__value_PR_ServedEUTRAcellsENDCX2ManagementList; + ie_ENB_ENDC->value.present = X2AP_ENB_ENDCX2SetupReqAckIEs__value_PR_ServedEUTRAcellsENDCX2ManagementList; { for (int i = 0; inum_cc; i++){ @@ -1299,11 +1437,11 @@ int x2ap_eNB_generate_ENDC_x2_setup_request( ASN_SEQUENCE_ADD(&servedCellMember->servedEUTRACellInfo.broadcastPLMNs.list, plmn); } - if (instance_p->frame_type[i] == FDD) { - servedCellMember->servedEUTRACellInfo.eUTRA_Mode_Info.present = X2AP_EUTRA_Mode_Info_PR_fDD; + if (instance_p->frame_type[i] == FDD) { + servedCellMember->servedEUTRACellInfo.eUTRA_Mode_Info.present = X2AP_EUTRA_Mode_Info_PR_fDD; servedCellMember->servedEUTRACellInfo.eUTRA_Mode_Info.choice.fDD.dL_EARFCN = instance_p->fdd_earfcn_DL[i]; servedCellMember->servedEUTRACellInfo.eUTRA_Mode_Info.choice.fDD.uL_EARFCN = instance_p->fdd_earfcn_UL[i]; - switch (instance_p->N_RB_DL[i]) { + switch (instance_p->N_RB_DL[i]) { case 6: servedCellMember->servedEUTRACellInfo.eUTRA_Mode_Info.choice.fDD.uL_Transmission_Bandwidth = X2AP_Transmission_Bandwidth_bw6; servedCellMember->servedEUTRACellInfo.eUTRA_Mode_Info.choice.fDD.dL_Transmission_Bandwidth = X2AP_Transmission_Bandwidth_bw6; @@ -1334,177 +1472,13 @@ int x2ap_eNB_generate_ENDC_x2_setup_request( } } else { - AssertFatal(0,"X2Setuprequest not supported for TDD!"); + AssertFatal(0,"X2Setupresponse not supported for TDD!"); } } ASN_SEQUENCE_ADD(&ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list, servedCellMember); } } - ASN_SEQUENCE_ADD(&ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_eNB.list, ie_ENB_ENDC); - - - ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); - - if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { - X2AP_ERROR("Failed to encode ENDC X2 setup request\n"); - return -1; - } - - MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); - - x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); - - return ret; -} - - -/*setup request message from an eNB to a gNB*/ -int x2ap_gNB_generate_ENDC_x2_setup_response( - x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p) -{ - X2AP_INFO("In x2ap_gNB_generate_ENDC_x2_setup_response ()!\n"); - X2AP_X2AP_PDU_t pdu; - X2AP_ENDCX2SetupResponse_t *out; - X2AP_ENDCX2SetupResponse_IEs_t *ie; - X2AP_En_gNB_ENDCX2SetupReqAckIEs_t *ie_GNB_ENDC; - X2AP_PLMN_Identity_t *plmn; - ServedNRcellsENDCX2ManagementList__Member *servedCellMember; - - uint8_t *buffer; - uint32_t len; - int ret = 0; - - DevAssert(instance_p != NULL); - DevAssert(x2ap_eNB_data_p != NULL); - - x2ap_eNB_data_p->state = X2AP_ENB_STATE_WAITING; - - /* Prepare the X2AP message to encode */ - memset(&pdu, 0, sizeof(pdu)); - pdu.present = X2AP_X2AP_PDU_PR_successfulOutcome; - pdu.choice.successfulOutcome.procedureCode = X2AP_ProcedureCode_id_endcX2Setup; - pdu.choice.successfulOutcome.criticality = X2AP_Criticality_reject; - pdu.choice.successfulOutcome.value.present = X2AP_SuccessfulOutcome__value_PR_ENDCX2SetupResponse; - out = &pdu.choice.successfulOutcome.value.choice.ENDCX2SetupResponse; - - ie = (X2AP_ENDCX2SetupResponse_IEs_t *)calloc(1, sizeof(X2AP_ENDCX2SetupResponse_IEs_t)); - ie->id = X2AP_ProtocolIE_ID_id_RespondingNodeType_EndcX2Setup; - ie->value.present = X2AP_ENDCX2SetupResponse_IEs__value_PR_RespondingNodeType_EndcX2Setup; - ie->value.choice.RespondingNodeType_EndcX2Setup.present = X2AP_RespondingNodeType_EndcX2Setup_PR_respond_en_gNB; - - ie_GNB_ENDC = (X2AP_En_gNB_ENDCX2SetupReqAckIEs_t *)calloc(1, sizeof(X2AP_En_gNB_ENDCX2SetupReqAckIEs_t)); - ie_GNB_ENDC->id = X2AP_ProtocolIE_ID_id_Globalen_gNB_ID; - ie_GNB_ENDC->criticality = X2AP_Criticality_reject; - ie_GNB_ENDC->value.present = X2AP_En_gNB_ENDCX2SetupReqAckIEs__value_PR_GlobalGNB_ID; - ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.present = X2AP_GNB_ID_PR_gNB_ID; - - INT32_TO_OCTET_STRING(instance_p->eNB_id, - &ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID); - - X2AP_INFO("%d -> %02x%02x%02x\n", instance_p->eNB_id, - ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID.buf[0], - ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID.buf[1], - ie_GNB_ENDC->value.choice.GlobalGNB_ID.gNB_ID.choice.gNB_ID.buf[2]); - - MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, - &ie_GNB_ENDC->value.choice.GlobalGNB_ID.pLMN_Identity); - - ASN_SEQUENCE_ADD(&ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_en_gNB.list, ie_GNB_ENDC); - - ie_GNB_ENDC = (X2AP_En_gNB_ENDCX2SetupReqAckIEs_t *)calloc(1, sizeof(X2AP_En_gNB_ENDCX2SetupReqAckIEs_t)); - ie_GNB_ENDC->id = X2AP_ProtocolIE_ID_id_ServedNRcellsENDCX2ManagementList; - ie_GNB_ENDC->criticality = X2AP_Criticality_reject; - ie_GNB_ENDC->value.present = X2AP_En_gNB_ENDCX2SetupReqAckIEs__value_PR_ServedNRcellsENDCX2ManagementList; - - { - for (int i = 0; inum_cc; i++){ - servedCellMember = (ServedNRcellsENDCX2ManagementList__Member *)calloc(1,sizeof(ServedNRcellsENDCX2ManagementList__Member)); - { - servedCellMember->servedNRCellInfo.nrpCI = instance_p->Nid_cell[i]; - - MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, - &servedCellMember->servedNRCellInfo.nrCellID.pLMN_Identity); - NR_CELL_ID_TO_BIT_STRING(instance_p->eNB_id, - &servedCellMember->servedNRCellInfo.nrCellID.nRcellIdentifier); - servedCellMember->servedNRCellInfo.fiveGS_TAC = calloc(1, sizeof(X2AP_FiveGS_TAC_t)); - if (servedCellMember->servedNRCellInfo.fiveGS_TAC == NULL) - exit(1); - NR_FIVEGS_TAC_ID_TO_BIT_STRING(instance_p->tac, servedCellMember->servedNRCellInfo.fiveGS_TAC); - - X2AP_INFO("TAC: %d -> %02x%02x%02x\n", instance_p->tac, - servedCellMember->servedNRCellInfo.fiveGS_TAC->buf[0], - servedCellMember->servedNRCellInfo.fiveGS_TAC->buf[1], - servedCellMember->servedNRCellInfo.fiveGS_TAC->buf[2]); - - plmn = (X2AP_PLMN_Identity_t *)calloc(1,sizeof(X2AP_PLMN_Identity_t)); - { - MCC_MNC_TO_PLMNID(instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length, plmn); - ASN_SEQUENCE_ADD(&servedCellMember->servedNRCellInfo.broadcastPLMNs.list, plmn); - } - - if (instance_p->frame_type[i] == TDD) { // Panos: Remember to change that to TDD - X2AP_FreqBandNrItem_t *freq_band; - servedCellMember->servedNRCellInfo.nrModeInfo.present = X2AP_ServedNRCell_Information__nrModeInfo_PR_tdd; - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nRFreqInfo.nRARFCN = 0; //instance_p->tdd_nRARFCN[i]; - - /* addition of Frequency Band List */ - freq_band = calloc(1, sizeof(X2AP_FreqBandNrItem_t)); - if (freq_band == NULL) - exit(1); - freq_band->freqBandIndicatorNr = 1; /* TODO: put correct value */ - ASN_SEQUENCE_ADD(&servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nRFreqInfo.freqBandListNr, freq_band); - - switch (instance_p->N_RB_DL[i]) { - case 50: - //This is not correct. Just to be able to test X2 only using an eNB instead of gNB - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb51; - break; - case 93 : - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb93; - break; - case 106: - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb106; - break; - case 121: - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRNRB = X2AP_NRNRB_nrb121; - break; - - /*More cases to be added */ - - default: - AssertFatal(0,"Failed: Check value for N_RB_DL/N_RB_UL"); - break; - } - - instance_p->nr_SCS[i] = 30; // Hardcoded for now. Normally this should originate from the gNB config file - switch (instance_p->nr_SCS[i]) { - case 15: - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRSCS = X2AP_NRSCS_scs15; - break; - case 30: - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRSCS = X2AP_NRSCS_scs30; - break; - case 60: - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRSCS = X2AP_NRSCS_scs60; - break; - case 120: - servedCellMember->servedNRCellInfo.nrModeInfo.choice.tdd.nR_TxBW.nRSCS = X2AP_NRSCS_scs120; - break; - default: - AssertFatal(0,"Failed: Check value for nr_SCS"); - break; - } - } - else { - AssertFatal(0,"nr_X2Setupresponse not supported for FDD!"); - } - /*Don't know where to extract the value of measurementTimingConfiguration from. Set it to 0 for now */ - INT8_TO_OCTET_STRING(0, &servedCellMember->servedNRCellInfo.measurementTimingConfiguration); - } - ASN_SEQUENCE_ADD(&ie_GNB_ENDC->value.choice.ServedNRcellsENDCX2ManagementList.list, servedCellMember); - } - } - ASN_SEQUENCE_ADD(&ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_en_gNB.list, ie_GNB_ENDC); + ASN_SEQUENCE_ADD(&ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_eNB.list, ie_ENB_ENDC); ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); @@ -1521,3 +1495,360 @@ int x2ap_gNB_generate_ENDC_x2_setup_response( return ret; } +int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( + x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) +{ + X2AP_X2AP_PDU_t pdu; + X2AP_SgNBAdditionRequest_t *out; + X2AP_SgNBAdditionRequest_IEs_t *ie; + X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs_t *e_RABS_ToBeAdded_SgNBAddReq_ItemIEs; + X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item_t *e_RABS_ToBeAdded_SgNBAddReq_Item; + + uint8_t *buffer; + uint32_t len; + int ret = 0; + + // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted + // with values coming from RRC. + uint16_t nRencryptionAlgorithms = 0; + uint16_t nRintegrityProtectionAlgorithms = 0; + uint8_t SgNBSecurityKey[32] = { 0 }; + int uEaggregateMaximumBitRateDownlink = 100000000; + int uEaggregateMaximumBitRateUplink = 100000000; + int e_rabs_tobeadded = 1; + int e_RAB_ID = 1; + int drb_ID = 2; + long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; + long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; + long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; + long qCI = 1; + X2AP_Pre_emptionCapability_t pre_emptionCapability = X2AP_Pre_emptionCapability_shall_not_trigger_pre_emption; + X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability = X2AP_Pre_emptionVulnerability_not_pre_emptable; + priority_level_t priority_level = PRIORITY_LEVEL_NO_PRIORITY; + e_rab_tobe_added_t e_MCG_rabs_tobeadded; + e_MCG_rabs_tobeadded.gtp_teid = 0; + e_MCG_rabs_tobeadded.eNB_addr.length = 24; + uint8_t buf[20] = { 0 }; + memcpy(e_MCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); + + FILE *fd; + fd = fopen("../../../executables/uecap.raw","r"); + if (fd != NULL) { + OCTET_STRING_t CG_Config_Info; + CG_Config_Info.size = 4096; + CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t)); + int msg_len=fread(CG_Config_Info.buf,1,CG_Config_Info.size,fd); + CG_Config_Info.size = msg_len; + + /*char buffer[4096]; + int msg_len=fread(buffer,1,4096,fd);*/ + LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); + + + /*OCTET_STRING_t CG_Config_Info; + CG_Config_Info.size = 4096; + CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t));*/ + + + DevAssert(instance_p != NULL); + DevAssert(x2ap_eNB_data_p != NULL); + + x2ap_eNB_data_p->state = X2AP_ENB_STATE_WAITING; + + + + /* Prepare the X2AP message to encode */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = X2AP_X2AP_PDU_PR_initiatingMessage; + pdu.choice.initiatingMessage.procedureCode = X2AP_ProcedureCode_id_sgNBAdditionPreparation; + pdu.choice.initiatingMessage.criticality = X2AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = X2AP_InitiatingMessage__value_PR_SgNBAdditionRequest; + out = &pdu.choice.initiatingMessage.value.choice.SgNBAdditionRequest; + + ie = (X2AP_SgNBAdditionRequest_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequest_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID; //Not sure about that + ie->criticality= X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_UE_X2AP_ID; + ie->value.choice.UE_X2AP_ID = x2ap_id_get_id_source(&instance_p->id_manager, ue_id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequest_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequest_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_NRUESecurityCapabilities; + INT16_TO_BIT_STRING(nRencryptionAlgorithms, &ie->value.choice.NRUESecurityCapabilities.nRencryptionAlgorithms); + INT16_TO_BIT_STRING(nRintegrityProtectionAlgorithms, &ie->value.choice.NRUESecurityCapabilities.nRintegrityProtectionAlgorithms); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequest_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequest_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_SgNBSecurityKey; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_SgNBSecurityKey; + KENB_STAR_TO_BIT_STRING(SgNBSecurityKey, &ie->value.choice.SgNBSecurityKey); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequest_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequest_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_SgNBUEAggregateMaximumBitRate; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_UEAggregateMaximumBitRate; + ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateDownlink.buf = (uint8_t *)calloc(4, sizeof(uint8_t)); + INT32_TO_BUFFER(uEaggregateMaximumBitRateDownlink, ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateDownlink.buf); + ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateDownlink.size = 4; + + ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateUplink.buf = (uint8_t *)calloc(4, sizeof(uint8_t)); + INT32_TO_BUFFER(uEaggregateMaximumBitRateUplink, ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateUplink.buf); + ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateUplink.size = 4; + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequest_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequest_IEs_t)); + //Not sure if id should be X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_List or X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_SgNBAddReqList + ie->id = X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_SgNBAddReqList; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_E_RABs_ToBeAdded_SgNBAddReqList; + + for (int i=0;iid = X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_SgNBAddReq_Item; + e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->criticality = X2AP_Criticality_ignore; + e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs__value_PR_E_RABs_ToBeAdded_SgNBAddReq_Item; + e_RABS_ToBeAdded_SgNBAddReq_Item = &e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_ToBeAdded_SgNBAddReq_Item; + { + e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = drb_ID; + e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID; + e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB; + e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; + e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; + if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.qCI = qCI; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability = pre_emptionCapability; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority. pre_emptionVulnerability = pre_emptionVulnerability; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel = priority_level; + + //Continue from filling the UL_GTPtunnelEndpointInformation inspired from how it is done for the HO case + INT32_TO_OCTET_STRING(e_MCG_rabs_tobeadded.gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID); + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = e_MCG_rabs_tobeadded.eNB_addr.length/8; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_MCG_rabs_tobeadded.eNB_addr.length%8; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf = + calloc(1, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); + + memcpy (e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf, + e_MCG_rabs_tobeadded.eNB_addr.buffer, + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); + } + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABs_ToBeAdded_SgNBAddReqList.list, e_RABS_ToBeAdded_SgNBAddReq_ItemIEs); + } + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequest_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequest_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_MeNBtoSgNBContainer; + ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *)calloc(CG_Config_Info.size, sizeof(uint8_t)); + memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, CG_Config_Info.buf, CG_Config_Info.size); + ie->value.choice.MeNBtoSgNBContainer.size = CG_Config_Info.size; //4096; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n"); + return -1; + } + + MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); + + x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); + fclose(fd); + } + else { + LOG_I(RRC, "uecap.raw file could not be opened... \n"); + return -1; + } + + return ret; + +} + + +int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, + x2ap_ENDC_sgnb_addition_req_ACK_t *x2ap_sgnb_addition_req_ACK, int ue_id) +{ + + X2AP_X2AP_PDU_t pdu; + X2AP_SgNBAdditionRequestAcknowledge_t *out; + X2AP_SgNBAdditionRequestAcknowledge_IEs_t *ie; + X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs_t *e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs; + X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item_t *e_RABS_AdmittedToBeAdded_SgNBAddReq_Item; + + uint8_t *buffer; + uint32_t len; + int ret = 0; + int MeNB_UE_X2AP_id = ue_id; + int SgNB_UE_X2AP_id = 0; + + // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted + // with values coming from RRC. + uint16_t nRencryptionAlgorithms = 0; + uint16_t nRintegrityProtectionAlgorithms = 0; + uint8_t SgNBSecurityKey[32] = { 0 }; + int uEaggregateMaximumBitRateDownlink = 100000000; + int uEaggregateMaximumBitRateUplink = 100000000; + int e_rabs_admitted_tobeadded = 1; + int e_RAB_ID = 1; + long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; + long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; + long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; + e_rab_setup_t e_SCG_rabs_tobeadded; + e_SCG_rabs_tobeadded.gtp_teid = 0; + e_SCG_rabs_tobeadded.eNB_addr.length = 24; + uint8_t buf[20] = { 0 }; + memcpy(e_SCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); + + DevAssert(instance_p != NULL); + DevAssert(x2ap_eNB_data_p != NULL); + + x2ap_eNB_data_p->state = X2AP_ENB_STATE_WAITING; + + // Prepare the X2AP message to encode + memset(&pdu, 0, sizeof(pdu)); + pdu.present = X2AP_X2AP_PDU_PR_successfulOutcome; + pdu.choice.successfulOutcome.procedureCode = X2AP_ProcedureCode_id_sgNBAdditionPreparation; + pdu.choice.successfulOutcome.criticality = X2AP_Criticality_reject; + pdu.choice.successfulOutcome.value.present = X2AP_SuccessfulOutcome__value_PR_SgNBAdditionRequestAcknowledge; + out = &pdu.choice.successfulOutcome.value.choice.SgNBAdditionRequestAcknowledge; + + // MeNB_UE_X2AP_id + ie = (X2AP_SgNBAdditionRequestAcknowledge_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequestAcknowledge_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID; + ie->criticality= X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequestAcknowledge_IEs__value_PR_UE_X2AP_ID; + ie->value.choice.UE_X2AP_ID = MeNB_UE_X2AP_id; //x2ap_id_get_id_source(&instance_p->id_manager, ue_id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + // SgNB_UE_X2AP_id + ie = (X2AP_SgNBAdditionRequestAcknowledge_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequestAcknowledge_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_SgNB_UE_X2AP_ID; + ie->criticality= X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequestAcknowledge_IEs__value_PR_SgNB_UE_X2AP_ID; + ie->value.choice.UE_X2AP_ID = SgNB_UE_X2AP_id; //x2ap_id_get_id_source(&instance_p->id_manager, ue_id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequestAcknowledge_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequestAcknowledge_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList; + ie->criticality = X2AP_Criticality_ignore; + ie->value.present = X2AP_SgNBAdditionRequestAcknowledge_IEs__value_PR_E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList; + + for (int i=0;iid = X2AP_ProtocolIE_ID_id_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; + e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->criticality = X2AP_Criticality_ignore; + e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs__value_PR_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item = &e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; + { + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; + if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item__resource_configuration_PR_sgNBPDCPpresent; + + INT32_TO_OCTET_STRING(e_SCG_rabs_tobeadded.gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID); + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = e_SCG_rabs_tobeadded.eNB_addr.length/8; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_SCG_rabs_tobeadded.eNB_addr.length%8; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf = + calloc(1, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); + + memcpy (e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf, + e_SCG_rabs_tobeadded.eNB_addr.buffer, + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); + } + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList.list, e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs); + } + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBAdditionRequestAcknowledge_IEs_t *)calloc(1, sizeof(X2AP_SgNBAdditionRequestAcknowledge_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_SgNBtoMeNBContainer; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBAdditionRequestAcknowledge_IEs__value_PR_SgNBtoMeNBContainer; + ie->value.choice.SgNBtoMeNBContainer.buf = (uint8_t *)calloc(x2ap_sgnb_addition_req_ACK->rrc_buffer_size, sizeof(uint8_t)); + memcpy(ie->value.choice.SgNBtoMeNBContainer.buf, x2ap_sgnb_addition_req_ACK->rrc_buffer, x2ap_sgnb_addition_req_ACK->rrc_buffer_size); + ie->value.choice.SgNBtoMeNBContainer.size = x2ap_sgnb_addition_req_ACK->rrc_buffer_size; //4096; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n"); + return -1; + } + + MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); + + x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); + + return ret; + +} + + +int x2ap_eNB_generate_ENDC_x2_SgNB_reconfiguration_complete( + x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id, int SgNB_ue_id) +{ + X2AP_X2AP_PDU_t pdu; + X2AP_SgNBReconfigurationComplete_t *out; + X2AP_SgNBReconfigurationComplete_IEs_t *ie; + + uint8_t *buffer; + uint32_t len; + int ret = 0; + + DevAssert(instance_p != NULL); + DevAssert(x2ap_eNB_data_p != NULL); + + x2ap_eNB_data_p->state = X2AP_ENB_STATE_WAITING; + + + /* Prepare the X2AP message to encode */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = X2AP_X2AP_PDU_PR_initiatingMessage; + pdu.choice.initiatingMessage.procedureCode = X2AP_ProcedureCode_id_sgNBReconfigurationCompletion; + pdu.choice.initiatingMessage.criticality = X2AP_Criticality_ignore; + pdu.choice.initiatingMessage.value.present = X2AP_InitiatingMessage__value_PR_SgNBReconfigurationComplete; + out = &pdu.choice.initiatingMessage.value.choice.SgNBReconfigurationComplete; + + ie = (X2AP_SgNBReconfigurationComplete_IEs_t *)calloc(1, sizeof(X2AP_SgNBReconfigurationComplete_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID; + ie->criticality= X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBReconfigurationComplete_IEs__value_PR_UE_X2AP_ID; + ie->value.choice.UE_X2AP_ID = ue_id; //x2ap_id_get_id_source(&instance_p->id_manager, ue_id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBReconfigurationComplete_IEs_t *)calloc(1, sizeof(X2AP_SgNBReconfigurationComplete_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_SgNB_UE_X2AP_ID; + ie->criticality = X2AP_Criticality_reject; + ie->value.present = X2AP_SgNBReconfigurationComplete_IEs__value_PR_SgNB_UE_X2AP_ID; + ie->value.choice.SgNB_UE_X2AP_ID = SgNB_ue_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (X2AP_SgNBReconfigurationComplete_IEs_t *)calloc(1, sizeof(X2AP_SgNBReconfigurationComplete_IEs_t)); + ie->id = X2AP_ProtocolIE_ID_id_ResponseInformationSgNBReconfComp; + ie->criticality = X2AP_Criticality_ignore; + ie->value.present = X2AP_SgNBReconfigurationComplete_IEs__value_PR_ResponseInformationSgNBReconfComp; + ie->value.choice.ResponseInformationSgNBReconfComp.present = X2AP_ResponseInformationSgNBReconfComp_PR_success_SgNBReconfComp; + // meNBtoSgNBContainer should contain the RRCReconfigurationComplete message from the UE but in the specs 36.423(9.1.4.4) its presence is not mandatory + ie->value.choice.ResponseInformationSgNBReconfComp.choice.success_SgNBReconfComp.meNBtoSgNBContainer = NULL; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n"); + return -1; + } + + x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); + + return ret; + +} diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.h b/openair2/X2AP/x2ap_eNB_generate_messages.h index 6b0cd9c2da..114ed84a68 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.h +++ b/openair2/X2AP/x2ap_eNB_generate_messages.h @@ -66,8 +66,15 @@ int x2ap_eNB_generate_senb_addition_request (x2ap_eNB_instance_t *instance_p, x2 int x2ap_eNB_generate_senb_addition_request_ack (x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, x2ap_senb_addition_req_ack_t *x2ap_addition_req_ack); -int x2ap_eNB_generate_ENDC_x2_setup_request(x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p); +int x2ap_gNB_generate_ENDC_x2_setup_request(x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p); -int x2ap_gNB_generate_ENDC_x2_setup_response( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p); +int x2ap_eNB_generate_ENDC_x2_setup_response( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p); + +int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id); + +int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, x2ap_ENDC_sgnb_addition_req_ACK_t *x2ap_sgnb_addition_req_ACK, int ue_id); + +int x2ap_eNB_generate_ENDC_x2_SgNB_reconfiguration_complete( + x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id, int SgNB_ue_id); #endif /* X2AP_ENB_GENERATE_MESSAGES_H_ */ diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index bde7bd59d9..b7a9b70596 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -103,7 +103,7 @@ int x2ap_eNB_handle_senb_addition_request_reject (instance_t instance, uint32_t stream, X2AP_X2AP_PDU_t *pdu); -int x2ap_gNB_handle_ENDC_x2_setup_request(instance_t instance, +int x2ap_eNB_handle_ENDC_x2_setup_request(instance_t instance, uint32_t assoc_id, uint32_t stream, X2AP_X2AP_PDU_t *pdu); @@ -114,8 +114,26 @@ x2ap_gNB_handle_ENDC_x2_setup_response(instance_t instance, uint32_t stream, X2AP_X2AP_PDU_t *pdu); +static +int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu); -/* Handlers matrix. Only eNB related procedure present here */ +static +int x2ap_eNB_handle_ENDC_sGNB_addition_response (instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu); + +static +int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu); + + +/* Handlers matrix. Only eNB related procedure present here. Placement of callback functions according to X2AP_ProcedureCode.h */ x2ap_message_decoded_callback x2ap_messages_callback[][3] = { { x2ap_eNB_handle_handover_preparation, x2ap_eNB_handle_handover_response, 0 }, /* handoverPreparation */ { x2ap_eNB_handle_handover_cancel, 0, 0 }, /* handoverCancel */ @@ -144,6 +162,8 @@ x2ap_message_decoded_callback x2ap_messages_callback[][3] = { { 0, 0, 0 }, /* seNBinitiatedSeNBRelease */ { 0, 0, 0 }, /* seNBCounterCheck */ { 0, 0, 0 }, /* retrieveUEContext */ + { x2ap_gNB_handle_ENDC_sGNB_addition_request, x2ap_eNB_handle_ENDC_sGNB_addition_response, 0 }, /*X2AP_ProcedureCode_id_sgNBAdditionPreparation*/ + { x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete, 0, 0 }, /*X2AP_ProcedureCode_id_sgNBReconfigurationCompletion*/ { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, @@ -151,9 +171,7 @@ x2ap_message_decoded_callback x2ap_messages_callback[][3] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, - { 0, 0, 0 }, - { 0, 0, 0 }, - { x2ap_gNB_handle_ENDC_x2_setup_request, x2ap_gNB_handle_ENDC_x2_setup_response, 0 }, + { x2ap_eNB_handle_ENDC_x2_setup_request, x2ap_gNB_handle_ENDC_x2_setup_response, 0 }, /*X2AP_ProcedureCode_id_endcX2Setup*/ { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 } @@ -1324,7 +1342,7 @@ int x2ap_eNB_handle_senb_addition_request_reject (instance_t instance, } int -x2ap_gNB_handle_ENDC_x2_setup_request(instance_t instance, +x2ap_eNB_handle_ENDC_x2_setup_request(instance_t instance, uint32_t assoc_id, uint32_t stream, X2AP_X2AP_PDU_t *pdu) @@ -1332,12 +1350,12 @@ x2ap_gNB_handle_ENDC_x2_setup_request(instance_t instance, X2AP_ENDCX2SetupRequest_t *x2_ENDC_SetupRequest; X2AP_ENDCX2SetupRequest_IEs_t *ie; - X2AP_ENB_ENDCX2SetupReqIEs_t *ie_ENB_ENDC; - ServedEUTRAcellsENDCX2ManagementList__Member *servedCellMember; + X2AP_En_gNB_ENDCX2SetupReqIEs_t *ie_GNB_ENDC; + ServedNRcellsENDCX2ManagementList__Member *servedCellMember; x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; - uint32_t eNB_id = 0; + uint32_t gNB_id = 0; x2ap_eNB_data = NULL; DevAssert (pdu != NULL); @@ -1372,156 +1390,11 @@ x2ap_gNB_handle_ENDC_x2_setup_request(instance_t instance, X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); return -1; } else { - if (ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_eNB.list.count > 0) { - //Panos: Here the container parameter in X2AP_FIND_PROTOCOLIE_BY_ID should be the x2_ENDC_SetupRequest - //message or the ie to which there are more nested information elements? - for (int i=0; ivalue.choice.InitiatingNodeType_EndcX2Setup.choice.init_eNB.list.count;i++) { + if (ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_en_gNB.list.count > 0) { - ie_ENB_ENDC = (X2AP_ENB_ENDCX2SetupReqIEs_t*) ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_eNB.list.array[i]; - if (ie_ENB_ENDC == NULL ) { - X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); - return -1; - } + for (int i=0; ivalue.choice.InitiatingNodeType_EndcX2Setup.choice.init_en_gNB.list.count;i++) { - else if (ie_ENB_ENDC->id == X2AP_ProtocolIE_ID_id_GlobalENB_ID) { - if (ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.present == X2AP_ENB_ID_PR_home_eNB_ID) { - // Home eNB ID = 28 bits - uint8_t *eNB_id_buf = ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.home_eNB_ID.buf; - if (ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID.size != 28) { - //TODO: handle case were size != 28 -> notify ? reject ? - } - eNB_id = (eNB_id_buf[0] << 20) + (eNB_id_buf[1] << 12) + (eNB_id_buf[2] << 4) + ((eNB_id_buf[3] & 0xf0) >> 4); - X2AP_DEBUG("Home eNB id: %07x\n", eNB_id); - } else { - // Macro eNB = 20 bits - uint8_t *eNB_id_buf = ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID.buf; - if (ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID.size != 20) { - //TODO: handle case were size != 20 -> notify ? reject ? - } - eNB_id = (eNB_id_buf[0] << 12) + (eNB_id_buf[1] << 4) + ((eNB_id_buf[2] & 0xf0) >> 4); - X2AP_DEBUG("macro eNB id: %05x\n", eNB_id); - } - X2AP_DEBUG("Adding eNB to the list of associated eNBs\n"); - if ((x2ap_eNB_data = x2ap_is_eNB_id_in_list (eNB_id)) == NULL) { - /* - * eNB has not been found in list of associated eNB, - * * * * Add it to the tail of list and initialize data - */ - if ((x2ap_eNB_data = x2ap_is_eNB_assoc_id_in_list (assoc_id)) == NULL) { - /* - * ?? - */ - return -1; - } else { - x2ap_eNB_data->state = X2AP_ENB_STATE_RESETTING; - x2ap_eNB_data->eNB_id = eNB_id; - } - } else { - x2ap_eNB_data->state = X2AP_ENB_STATE_RESETTING; - - /* - * eNB has been found in list, consider the x2 setup request as a reset connection, - * * * * reseting any previous UE state if sctp association is != than the previous one - */ - if (x2ap_eNB_data->assoc_id != assoc_id) { - /* - * ??: Send an overload cause... - */ - X2AP_ERROR("Rejecting x2 setup request as eNB id %d is already associated to an active sctp association" "Previous known: %d, new one: %d\n", eNB_id, x2ap_eNB_data->assoc_id, assoc_id); - - // Panos: Here we should be calling an ENDC specific setup_failure function instead - x2ap_eNB_generate_x2_setup_failure (instance, - assoc_id, - X2AP_Cause_PR_protocol, - X2AP_CauseProtocol_unspecified, - -1); - return -1; - } - /* - * * TODO: call the reset procedure - */ - } - } - else if (ie_ENB_ENDC->id == X2AP_ProtocolIE_ID_id_ServedEUTRAcellsENDCX2ManagementList){ - if (ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list.count > 0) { - x2ap_eNB_data->num_cc = ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list.count; - for (int i=0; ivalue.choice.ServedEUTRAcellsENDCX2ManagementList.list.count;i++) { - servedCellMember = (ServedEUTRAcellsENDCX2ManagementList__Member *)ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list.array[i]; - x2ap_eNB_data->Nid_cell[i] = servedCellMember->servedEUTRACellInfo.pCI; - } - } - } - } - } - else { - X2AP_ERROR("%s %d: init_eNB list is empty \n",__FILE__,__LINE__); - return -1; - } - } - - instance_p = x2ap_eNB_get_instance(instance); - DevAssert(instance_p != NULL); - - // Panos: Here we should be calling an ENDC specific setup response function - return x2ap_gNB_generate_ENDC_x2_setup_response(instance_p, x2ap_eNB_data); - //return x2ap_eNB_generate_x2_setup_response(instance_p, x2ap_eNB_data); -} - -int -x2ap_gNB_handle_ENDC_x2_setup_response(instance_t instance, - uint32_t assoc_id, - uint32_t stream, - X2AP_X2AP_PDU_t *pdu) -{ - - X2AP_ENDCX2SetupResponse_t *x2_ENDC_SetupResponse; - X2AP_ENDCX2SetupResponse_IEs_t *ie; - X2AP_En_gNB_ENDCX2SetupReqAckIEs_t *ie_GNB_ENDC; - ServedNRcellsENDCX2ManagementList__Member *servedCellMember; - - x2ap_eNB_instance_t *instance_p; - x2ap_eNB_data_t *x2ap_eNB_data; - uint32_t gNB_id = 0; - - x2ap_eNB_data = NULL; - DevAssert (pdu != NULL); - x2_ENDC_SetupResponse = &pdu->choice.successfulOutcome.value.choice.ENDCX2SetupResponse; - - /* - * We received a new valid X2 Setup Request on a stream != 0. - * * * * This should not happen -> reject eNB x2 setup request. - */ - - if (stream != 0) { - X2AP_ERROR("Received new x2 setup request on stream != 0\n"); - /* - * Send a x2 setup failure with protocol cause unspecified - */ - // Panos: Here we should be calling an ENDC specific setup_failure function instead - return x2ap_eNB_generate_x2_setup_failure (instance, - assoc_id, - X2AP_Cause_PR_protocol, - X2AP_CauseProtocol_unspecified, - -1); - } - - X2AP_DEBUG("Received a new X2 setup request\n"); - - X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_ENDCX2SetupResponse_IEs_t, ie, x2_ENDC_SetupResponse, - X2AP_ProtocolIE_ID_id_RespondingNodeType_EndcX2Setup, true); - - - - if (ie == NULL ) { - X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); - return -1; - } else { - if (ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_en_gNB.list.count > 0) { - //Panos: Here the container parameter in X2AP_FIND_PROTOCOLIE_BY_ID should be the x2_ENDC_SetupRequest - //message or the ie to which there are more nested information elements? - for (int i=0; ivalue.choice.RespondingNodeType_EndcX2Setup.choice.respond_en_gNB.list.count;i++) { - - ie_GNB_ENDC = (X2AP_En_gNB_ENDCX2SetupReqAckIEs_t*) ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_en_gNB.list.array[i]; + ie_GNB_ENDC = (X2AP_En_gNB_ENDCX2SetupReqIEs_t*) ie->value.choice.InitiatingNodeType_EndcX2Setup.choice.init_eNB.list.array[i]; if (ie_GNB_ENDC == NULL ) { X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); return -1; @@ -1606,6 +1479,146 @@ x2ap_gNB_handle_ENDC_x2_setup_response(instance_t instance, } } + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + + return x2ap_eNB_generate_ENDC_x2_setup_response(instance_p, x2ap_eNB_data); +} + +int +x2ap_gNB_handle_ENDC_x2_setup_response(instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu) +{ + + X2AP_ENDCX2SetupResponse_t *x2_ENDC_SetupResponse; + X2AP_ENDCX2SetupResponse_IEs_t *ie; + X2AP_ENB_ENDCX2SetupReqAckIEs_t *ie_ENB_ENDC; + ServedEUTRAcellsENDCX2ManagementList__Member *servedCellMember; + + x2ap_eNB_instance_t *instance_p; + x2ap_eNB_data_t *x2ap_eNB_data; + uint32_t eNB_id = 0; + + x2ap_eNB_data = NULL; + DevAssert (pdu != NULL); + x2_ENDC_SetupResponse = &pdu->choice.successfulOutcome.value.choice.ENDCX2SetupResponse; + + /* + * We received a new valid X2 Setup Request on a stream != 0. + * * * * This should not happen -> reject eNB x2 setup request. + */ + + if (stream != 0) { + X2AP_ERROR("Received new x2 setup request on stream != 0\n"); + /* + * Send a x2 setup failure with protocol cause unspecified + */ + // Here we should be calling an ENDC specific setup_failure function instead + return x2ap_eNB_generate_x2_setup_failure (instance, + assoc_id, + X2AP_Cause_PR_protocol, + X2AP_CauseProtocol_unspecified, + -1); + } + + X2AP_DEBUG("Received a new X2 setup request\n"); + + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_ENDCX2SetupResponse_IEs_t, ie, x2_ENDC_SetupResponse, + X2AP_ProtocolIE_ID_id_RespondingNodeType_EndcX2Setup, true); + + + + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } else { + if (ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_eNB.list.count > 0) { + for (int i=0; ivalue.choice.RespondingNodeType_EndcX2Setup.choice.respond_eNB.list.count;i++) { + + ie_ENB_ENDC = (X2AP_ENB_ENDCX2SetupReqAckIEs_t*) ie->value.choice.RespondingNodeType_EndcX2Setup.choice.respond_eNB.list.array[i]; + if (ie_ENB_ENDC == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + else if (ie_ENB_ENDC->id == X2AP_ProtocolIE_ID_id_GlobalENB_ID) { + if (ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.present == X2AP_ENB_ID_PR_home_eNB_ID) { + // Home eNB ID = 28 bits + uint8_t *eNB_id_buf = ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.home_eNB_ID.buf; + if (ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID.size != 28) { + //TODO: handle case were size != 28 -> notify ? reject ? + } + eNB_id = (eNB_id_buf[0] << 20) + (eNB_id_buf[1] << 12) + (eNB_id_buf[2] << 4) + ((eNB_id_buf[3] & 0xf0) >> 4); + X2AP_DEBUG("Home eNB id: %07x\n", eNB_id); + } else { + // Macro eNB = 20 bits + uint8_t *eNB_id_buf = ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID.buf; + if (ie_ENB_ENDC->value.choice.GlobalENB_ID.eNB_ID.choice.macro_eNB_ID.size != 20) { + //TODO: handle case were size != 20 -> notify ? reject ? + } + eNB_id = (eNB_id_buf[0] << 12) + (eNB_id_buf[1] << 4) + ((eNB_id_buf[2] & 0xf0) >> 4); + X2AP_DEBUG("macro eNB id: %05x\n", eNB_id); + } + X2AP_DEBUG("Adding eNB to the list of associated eNBs\n"); + if ((x2ap_eNB_data = x2ap_is_eNB_id_in_list (eNB_id)) == NULL) { + /* + * eNB has not been found in list of associated eNB, + * * * * Add it to the tail of list and initialize data + */ + if ((x2ap_eNB_data = x2ap_is_eNB_assoc_id_in_list (assoc_id)) == NULL) { + /* + * ?? + */ + return -1; + } else { + x2ap_eNB_data->state = X2AP_ENB_STATE_RESETTING; + x2ap_eNB_data->eNB_id = eNB_id; + } + } else { + x2ap_eNB_data->state = X2AP_ENB_STATE_RESETTING; + + /* + * eNB has been found in list, consider the x2 setup request as a reset connection, + * * * * reseting any previous UE state if sctp association is != than the previous one + */ + if (x2ap_eNB_data->assoc_id != assoc_id) { + /* + * ??: Send an overload cause... + */ + X2AP_ERROR("Rejecting x2 setup request as eNB id %d is already associated to an active sctp association" "Previous known: %d, new one: %d\n", eNB_id, x2ap_eNB_data->assoc_id, assoc_id); + + // Here we should be calling an ENDC specific setup_failure function instead + x2ap_eNB_generate_x2_setup_failure (instance, + assoc_id, + X2AP_Cause_PR_protocol, + X2AP_CauseProtocol_unspecified, + -1); + return -1; + } + /* + * * TODO: call the reset procedure + */ + } + } + else if (ie_ENB_ENDC->id == X2AP_ProtocolIE_ID_id_ServedEUTRAcellsENDCX2ManagementList){ + if (ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list.count > 0) { + x2ap_eNB_data->num_cc = ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list.count; + for (int i=0; ivalue.choice.ServedEUTRAcellsENDCX2ManagementList.list.count;i++) { + servedCellMember = (ServedEUTRAcellsENDCX2ManagementList__Member *)ie_ENB_ENDC->value.choice.ServedEUTRAcellsENDCX2ManagementList.list.array[i]; + x2ap_eNB_data->Nid_cell[i] = servedCellMember->servedEUTRACellInfo.pCI; + } + } + } + } + } + else { + X2AP_ERROR("%s %d: init_eNB list is empty \n",__FILE__,__LINE__); + return -1; + } + } + /* Optionaly set the target eNB name */ /* The association is now ready as source and target eNBs know parameters of each other. @@ -1622,4 +1635,379 @@ x2ap_gNB_handle_ENDC_x2_setup_response(instance_t instance, return 0; } +static +int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu) +{ + + + X2AP_SgNBAdditionRequest_t *x2SgNBAdditionRequest; + X2AP_SgNBAdditionRequest_IEs_t *ie; + + X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs_t *e_RABS_ToBeAdded_SgNBAddReq_ItemIEs; + X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item_t *e_RABS_ToBeAdded_SgNBAddReq_Item; + + x2ap_eNB_instance_t *instance_p; + x2ap_eNB_data_t *x2ap_eNB_data; + MessageDef *msg; + int ue_id; + + DevAssert (pdu != NULL); + x2SgNBAdditionRequest = &pdu->choice.initiatingMessage.value.choice.SgNBAdditionRequest; + + /*if (stream == 0) { + X2AP_ERROR ("Received new x2 SgNB Addition request on stream == 0\n"); + // TODO: send a x2 failure response + return 0; + }*/ + + X2AP_DEBUG ("Received a new X2 SgNB Addition request\n"); + + x2ap_eNB_data = x2ap_get_eNB(NULL, assoc_id, 0); + DevAssert(x2ap_eNB_data != NULL); + + X2AP_INFO("X2AP Association id: %d \n",assoc_id); + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + + //Allocate an ITTI X2AP_SGNB_ADDITION_REQ message instead + msg = itti_alloc_new_message(TASK_X2AP, X2AP_ENDC_SGNB_ADDITION_REQ); + + /* X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, + X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID, true); + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + + // allocate a new X2AP UE ID + ue_id = x2ap_allocate_new_id(&instance_p->id_manager); + if (ue_id == -1) { + X2AP_ERROR("could not allocate a new X2AP UE ID\n"); + // TODO: cancel handover: send HO preparation failure to source eNB + exit(1); + } + // rnti is unknown yet, must not be set to -1, 0 is fine + x2ap_set_ids(&instance_p->id_manager, ue_id, 0, ie->value.choice.UE_X2AP_ID, ue_id); + x2ap_id_set_state(&instance_p->id_manager, ue_id, X2ID_STATE_TARGET); + + X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ue_id; + + + /* X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, + X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities, true); + + X2AP_ENDC_SGNB_ADDITION_REQ(msg).security_capabilities.encryption_algorithms = + BIT_STRING_to_uint16(&ie->value.choice.NRUESecurityCapabilities.nRencryptionAlgorithms); + + X2AP_ENDC_SGNB_ADDITION_REQ(msg).security_capabilities.integrity_algorithms = + BIT_STRING_to_uint16(&ie->value.choice.NRUESecurityCapabilities.nRintegrityProtectionAlgorithms); + + /* X2AP_ProtocolIE_ID_id_SgNBSecurityKey */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, + X2AP_ProtocolIE_ID_id_SgNBSecurityKey, true); + + if ((ie->value.choice.SgNBSecurityKey.buf) && + (ie->value.choice.SgNBSecurityKey.size == 32)) { + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).kgnb, ie->value.choice.SgNBSecurityKey.buf, 32); + } else { + X2AP_WARN ("Size of eNB key star does not match the expected value\n"); + } + + + /* X2AP_ProtocolIE_ID_id_SgNBUEAggregateMaximumBitRate */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, + X2AP_ProtocolIE_ID_id_SgNBUEAggregateMaximumBitRate, true); + + //X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_ambr.br_dl =ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateDownlink; + //X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_ambr.br_ul = ie->value.choice.UEAggregateMaximumBitRate.uEaggregateMaximumBitRateUplink; + + /* X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_SgNBAddReqList */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, + X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_SgNBAddReqList, true); + + + if (ie->value.choice.E_RABs_ToBeAdded_SgNBAddReqList.list.count > 0) { + + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = ie->value.choice.E_RABs_ToBeAdded_SgNBAddReqList.list.count; + + for (int i=0;ivalue.choice.E_RABs_ToBeAdded_SgNBAddReqList.list.count;i++) { + e_RABS_ToBeAdded_SgNBAddReq_ItemIEs = (X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs_t *) ie->value.choice.E_RABs_ToBeAdded_SgNBAddReqList.list.array[i]; + e_RABS_ToBeAdded_SgNBAddReq_Item = &e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_ToBeAdded_SgNBAddReq_Item; + + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].e_rab_id = e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID ; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].drb_ID = e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID; + if(e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.qci = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.qCI; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.pre_emp_vulnerability = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionVulnerability; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.priority_level = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel; + + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.buffer, + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf, + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); + + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.length = + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; + + OCTET_STRING_TO_INT32(&e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid); + } + + } + + } + else { + X2AP_ERROR ("Can't decode the e_RABs_ToBeSetup_List \n"); + } + + /* X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, + X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer, true); + + X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; + + if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s + { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } + + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; + + itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); + + return 0; +} + + +static +int x2ap_eNB_handle_ENDC_sGNB_addition_response (instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu) +{ + + X2AP_SgNBAdditionRequestAcknowledge_t *x2SgNBAdditionRequest_ack; + X2AP_SgNBAdditionRequestAcknowledge_IEs_t *ie; + + X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs_t *e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs; + X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item_t *e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item; + + x2ap_eNB_instance_t *instance_p; + x2ap_eNB_data_t *x2ap_eNB_data; + MessageDef *msg; + int ue_id; + int id_source; + int id_target; + int rnti; + + DevAssert (pdu != NULL); + x2SgNBAdditionRequest_ack = &pdu->choice.successfulOutcome.value.choice.SgNBAdditionRequestAcknowledge; + + /*if (stream == 0) { + X2AP_ERROR ("Received new x2 SgNB Addition request on stream == 0\n"); + // TODO: send a x2 failure response + return 0; + }*/ + + X2AP_DEBUG ("Received a new X2 SgNB Addition request\n"); + + x2ap_eNB_data = x2ap_get_eNB(NULL, assoc_id, 0); + DevAssert(x2ap_eNB_data != NULL); + + X2AP_INFO("X2AP Association id: %d \n",assoc_id); + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + + //Allocate an ITTI X2AP_SGNB_ADDITION_REQ message instead + msg = itti_alloc_new_message(TASK_X2AP, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); + + /* X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequestAcknowledge_IEs_t, ie, x2SgNBAdditionRequest_ack, + X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID, true); + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + id_source = ie->value.choice.UE_X2AP_ID; + + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).MeNB_ue_x2_id = ie->value.choice.UE_X2AP_ID; + + + /* X2AP_ProtocolIE_ID_id_SgNB_UE_X2AP_ID */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequestAcknowledge_IEs_t, ie, x2SgNBAdditionRequest_ack, + X2AP_ProtocolIE_ID_id_SgNB_UE_X2AP_ID, true); + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + id_target = ie->value.choice.SgNB_UE_X2AP_ID; + + ue_id = id_source; + + if (ue_id != x2ap_find_id_from_id_source(&instance_p->id_manager, id_source)) { + X2AP_WARN("incorrect/unknown X2AP IDs for UE (old ID %d new ID %d), ignoring sGNB addition response\n", + id_source, id_target); + itti_free(ITTI_MSG_ORIGIN_ID(msg), msg); + return 0; + } + + rnti = x2ap_id_get_rnti(&instance_p->id_manager, ue_id); + + /* id_target is a new information, store it */ + x2ap_set_ids(&instance_p->id_manager, ue_id, rnti, id_source, id_target); + + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rnti = rnti; + + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).SgNB_ue_x2_id = ie->value.choice.SgNB_UE_X2AP_ID; + + /* X2AP_ProtocolIE_ID_id_E_RABs_ToBeAdded_SgNBAddReqList */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequestAcknowledge_IEs_t, ie, x2SgNBAdditionRequest_ack, + X2AP_ProtocolIE_ID_id_E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList, true); + + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + + if (ie->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList.list.count > 0) { + + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = ie->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList.list.count; + + for (int i=0;ivalue.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList.list.count;i++) { + + e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs = (X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs_t *) ie->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAckList.list.array[i]; + e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item = &e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; + + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->e_RAB_ID ; + if(e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->en_DC_ResourceConfiguration.pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ + + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.buffer, + e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf, + e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.length = + e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; + + OCTET_STRING_TO_INT32(&e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); + } + + } + + } + else { + X2AP_ERROR ("Can't decode the e_RABs_ToBeSetup_List \n"); + } + + /* X2AP_ProtocolIE_ID_id_SgNBtoMeNBContainer */ + + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequestAcknowledge_IEs_t, ie, x2SgNBAdditionRequest_ack, + X2AP_ProtocolIE_ID_id_SgNBtoMeNBContainer, true); + + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + //X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; + + if (ie->value.choice.SgNBtoMeNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s + { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } + + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, ie->value.choice.SgNBtoMeNBContainer.buf, ie->value.choice.SgNBtoMeNBContainer.size); + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = ie->value.choice.SgNBtoMeNBContainer.size; + + itti_send_msg_to_task(TASK_RRC_ENB, instance_p->instance, msg); + + return 0; +} + +static +int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance, + uint32_t assoc_id, + uint32_t stream, + X2AP_X2AP_PDU_t *pdu) { + + X2AP_SgNBReconfigurationComplete_t *x2SgNBReconfigurationComplete; + X2AP_SgNBReconfigurationComplete_IEs_t *ie; + + x2ap_eNB_instance_t *instance_p; + x2ap_eNB_data_t *x2ap_eNB_data; + MessageDef *msg; + int ue_id; + + DevAssert (pdu != NULL); + x2SgNBReconfigurationComplete = &pdu->choice.initiatingMessage.value.choice.SgNBReconfigurationComplete; + + /*if (stream == 0) { + X2AP_ERROR ("Received new x2 SgNB Addition request on stream == 0\n"); + // TODO: send a x2 failure response + return 0; + }*/ + + X2AP_DEBUG ("Received X2 SgNB Reconfiguration complete message\n"); + + x2ap_eNB_data = x2ap_get_eNB(NULL, assoc_id, 0); + DevAssert(x2ap_eNB_data != NULL); + + X2AP_INFO("X2AP Association id: %d \n",assoc_id); + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + + //Allocate an ITTI X2AP_SGNB_ADDITION_REQ message instead + msg = itti_alloc_new_message(TASK_X2AP, X2AP_ENDC_SGNB_RECONF_COMPLETE); + + /* X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBReconfigurationComplete_IEs_t, ie, x2SgNBReconfigurationComplete, + X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID, true); + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + X2AP_ENDC_SGNB_RECONF_COMPLETE(msg).MeNB_ue_x2_id = ie->value.choice.UE_X2AP_ID; + + + /* X2AP_ProtocolIE_ID_id_SgNB_UE_X2AP_ID */ + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBReconfigurationComplete_IEs_t, ie, x2SgNBReconfigurationComplete, + X2AP_ProtocolIE_ID_id_SgNB_UE_X2AP_ID, true); + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + X2AP_ENDC_SGNB_RECONF_COMPLETE(msg).SgNB_ue_x2_id = ie->value.choice.SgNB_UE_X2AP_ID; + + + X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBReconfigurationComplete_IEs_t, ie, x2SgNBReconfigurationComplete, + X2AP_ProtocolIE_ID_id_ResponseInformationSgNBReconfComp, true); + if (ie == NULL ) { + X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); + return -1; + } + + if(ie->value.choice.ResponseInformationSgNBReconfComp.present == X2AP_ResponseInformationSgNBReconfComp_PR_success_SgNBReconfComp){ + X2AP_ENDC_SGNB_RECONF_COMPLETE(msg).reconf_response = X2AP_RECONF_RESPONSE_SUCCESS; + } + else { + X2AP_ENDC_SGNB_RECONF_COMPLETE(msg).reconf_response = X2AP_RECONF_RESPONSE_REJECT; + } + + itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); + + + return 0; +} + + diff --git a/openair2/X2AP/x2ap_ids.h b/openair2/X2AP/x2ap_ids.h index 3d2799e8c4..f2670f3612 100644 --- a/openair2/X2AP/x2ap_ids.h +++ b/openair2/X2AP/x2ap_ids.h @@ -37,7 +37,8 @@ typedef enum { X2ID_STATE_SOURCE_PREPARE, X2ID_STATE_SOURCE_OVERALL, - X2ID_STATE_TARGET + X2ID_STATE_TARGET, + X2ID_STATE_NSA_PREPARE, } x2id_state_t; typedef struct { diff --git a/openair3/NAS/COMMON/UTIL/nas_log.h b/openair3/NAS/COMMON/UTIL/nas_log.h index b41e34c51b..d1531fa6db 100644 --- a/openair3/NAS/COMMON/UTIL/nas_log.h +++ b/openair3/NAS/COMMON/UTIL/nas_log.h @@ -95,14 +95,15 @@ typedef enum { /****************** E X P O R T E D F U N C T I O N S ******************/ /****************************************************************************/ +#define __FILENAME__ (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) #ifdef LOG_E # define LOG_TRACE(s, x, args...) \ do { \ switch (s) { \ - case ERROR: LOG_E(NAS, " %s:%d " x "\n", __FILE__, __LINE__, ##args); break; \ - case WARNING: LOG_W(NAS, " %s:%d " x "\n", __FILE__, __LINE__, ##args); break; \ - case INFO: LOG_I(NAS, " %s:%d " x "\n", __FILE__, __LINE__, ##args); break; \ - default: LOG_D(NAS, " %s:%d " x "\n", __FILE__, __LINE__, ##args); break; \ + case ERROR: LOG_E(NAS, " %s:%d " x "\n", __FILENAME__, __LINE__, ##args); break; \ + case WARNING: LOG_W(NAS, " %s:%d " x "\n", __FILENAME__, __LINE__, ##args); break; \ + case INFO: LOG_I(NAS, " %s:%d " x "\n", __FILENAME__, __LINE__, ##args); break; \ + default: LOG_D(NAS, " %s:%d " x "\n", __FILENAME__, __LINE__, ##args); break; \ } \ } while (0) diff --git a/openair3/NAS/UE/EMM/SecurityModeControl.c b/openair3/NAS/UE/EMM/SecurityModeControl.c index 7bdd21572e..67bfaf784e 100644 --- a/openair3/NAS/UE/EMM/SecurityModeControl.c +++ b/openair3/NAS/UE/EMM/SecurityModeControl.c @@ -286,7 +286,7 @@ int emm_proc_security_mode_command(nas_user_t *user, int native_ksi, int ksi, user->emm_data->security->selected_algorithms.encryption = seea; user->emm_data->security->selected_algorithms.integrity = seia; #if defined(NAS_BUILT_IN_UE) - nas_itti_kenb_refresh_req(security_data->kenb.value); + nas_itti_kenb_refresh_req(security_data->kenb.value, user->ueid); #endif } diff --git a/openair3/NAS/UE/nas_itti_messaging.c b/openair3/NAS/UE/nas_itti_messaging.c index 55566700d7..885ebbdd81 100644 --- a/openair3/NAS/UE/nas_itti_messaging.c +++ b/openair3/NAS/UE/nas_itti_messaging.c @@ -100,7 +100,7 @@ int nas_itti_protected_msg(const char *buffer, const nas_message_t *msg, const i extern unsigned char NB_eNB_INST; -int nas_itti_kenb_refresh_req(const Byte_t kenb[32]) { +int nas_itti_kenb_refresh_req(const Byte_t kenb[32], int user_id) { MessageDef *message_p; message_p = itti_alloc_new_message(TASK_NAS_UE, NAS_KENB_REFRESH_REQ); memcpy(NAS_KENB_REFRESH_REQ(message_p).kenb, kenb, sizeof(NAS_KENB_REFRESH_REQ(message_p).kenb)); @@ -125,7 +125,7 @@ int nas_itti_kenb_refresh_req(const Byte_t kenb[32]) { kenb[20], kenb[21], kenb[22], kenb[23], kenb[24], kenb[25], kenb[26], kenb[27], kenb[28], kenb[29], kenb[30], kenb[31]); - return itti_send_msg_to_task(TASK_RRC_UE, NB_eNB_INST + 0 /* TODO to be virtualized */, message_p); + return itti_send_msg_to_task(TASK_RRC_UE, NB_eNB_INST + user_id, message_p); } int nas_itti_cell_info_req(const plmn_t plmnID, const Byte_t rat, int user_id) { diff --git a/openair3/NAS/UE/nas_itti_messaging.h b/openair3/NAS/UE/nas_itti_messaging.h index d958317e5a..967bbb3059 100644 --- a/openair3/NAS/UE/nas_itti_messaging.h +++ b/openair3/NAS/UE/nas_itti_messaging.h @@ -48,7 +48,7 @@ int nas_itti_protected_msg( # if defined(NAS_BUILT_IN_UE) -int nas_itti_kenb_refresh_req(const Byte_t kenb[32]); +int nas_itti_kenb_refresh_req(const Byte_t kenb[32], int user_id); int nas_itti_cell_info_req(const plmn_t plmnID, const Byte_t rat, int user_id); diff --git a/openair3/UTILS/conversions.h b/openair3/UTILS/conversions.h index e39a841d96..d28c9acccb 100644 --- a/openair3/UTILS/conversions.h +++ b/openair3/UTILS/conversions.h @@ -116,8 +116,14 @@ do { \ #define INT16_TO_OCTET_STRING(x, aSN) \ do { \ (aSN)->buf = calloc(2, sizeof(uint8_t)); \ - (aSN)->size = 2; \ - INT16_TO_BUFFER(x, (aSN)->buf); \ + INT16_TO_BUFFER(x, ((aSN)->buf)); \ + (aSN)->size = 2; \ +} while(0) + +#define INT16_TO_BIT_STRING(x, aSN) \ +do { \ + INT16_TO_OCTET_STRING(x, aSN); \ + (aSN)->bits_unused = 0; \ } while(0) #define INT8_TO_OCTET_STRING(x, aSN) \ diff --git a/targets/ARCH/COMMON/common_lib.c b/targets/ARCH/COMMON/common_lib.c index 757ad6f75d..3066f0906f 100644 --- a/targets/ARCH/COMMON/common_lib.c +++ b/targets/ARCH/COMMON/common_lib.c @@ -37,6 +37,7 @@ #include #include "common_lib.h" +#include "assertions.h" #include "common/utils/load_module_shlib.h" #include "common/utils/LOG/log.h" #include "targets/RT/USER/lte-softmodem.h" @@ -91,38 +92,44 @@ int load_lib(openair0_device *device, { loader_shlibfunc_t shlib_fdesc[1]; int ret=0; - char *libname; + char *deflibname=OAI_RF_LIBNAME; openair0_cfg->recplay_mode = read_recplayconfig(&(openair0_cfg->recplay_conf),&(device->recplay_state)); if ( openair0_cfg->recplay_mode == RECPLAY_REPLAYMODE ) { - libname=OAI_IQPLAYER_LIBNAME; + deflibname=OAI_IQPLAYER_LIBNAME; shlib_fdesc[0].fname="device_init"; set_softmodem_optmask(SOFTMODEM_RECPLAY_BIT); // softmodem has to know we use the iqplayer to workaround randomized algorithms } else if ( IS_SOFTMODEM_BASICSIM ) { - libname=OAI_BASICSIM_LIBNAME; + deflibname=OAI_BASICSIM_LIBNAME; shlib_fdesc[0].fname="device_init"; } else if (IS_SOFTMODEM_RFSIM && flag == RAU_LOCAL_RADIO_HEAD) { - libname=OAI_RFSIM_LIBNAME; + deflibname=OAI_RFSIM_LIBNAME; shlib_fdesc[0].fname="device_init"; } else if (flag == RAU_LOCAL_RADIO_HEAD) { if (IS_SOFTMODEM_RFSIM) - libname="rfsimulator"; + deflibname="rfsimulator"; else - libname=OAI_RF_LIBNAME; + deflibname=OAI_RF_LIBNAME; shlib_fdesc[0].fname="device_init"; } else { - libname=OAI_TP_LIBNAME; + deflibname=OAI_TP_LIBNAME; shlib_fdesc[0].fname="transport_init"; } - ret=load_module_shlib(libname,shlib_fdesc,1,NULL); + + char *devname=NULL; + paramdef_t device_params[]=DEVICE_PARAMS_DESC ; + int numparams = sizeof(device_params)/sizeof(paramdef_t); + int devname_pidx = config_paramidx_fromname(device_params,numparams, CONFIG_DEVICEOPT_NAME); + device_params[devname_pidx].defstrval=deflibname; + + config_get(device_params,numparams,DEVICE_SECTION); + + ret=load_module_shlib(devname,shlib_fdesc,1,NULL); + AssertFatal( (ret >= 0), + "Library %s couldn't be loaded\n",devname); - if (ret < 0) { - LOG_E(HW,"Library %s couldn't be loaded\n",libname); - } else { - ret=((devfunc_t)shlib_fdesc[0].fptr)(device,openair0_cfg,cfg); - } - return ret; + return ((devfunc_t)shlib_fdesc[0].fptr)(device,openair0_cfg,cfg); } diff --git a/targets/ARCH/COMMON/common_lib.h b/targets/ARCH/COMMON/common_lib.h index 7e51bdc81a..ecadb68c0c 100644 --- a/targets/ARCH/COMMON/common_lib.h +++ b/targets/ARCH/COMMON/common_lib.h @@ -448,6 +448,24 @@ typedef struct { extern "C" { #endif + + +#define DEVICE_SECTION "device" +#define CONFIG_HLP_DEVICE "Identifies the oai device (the interface to RF) to use, the shared lib \"lib_.so\" will be loaded" + +#define CONFIG_DEVICEOPT_NAME "name" + +/* inclusion for device configuration */ +/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* config parameters for oai device */ +/* optname helpstr paramflags XXXptr defXXXval type numelt */ +/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#define DEVICE_PARAMS_DESC {\ + { CONFIG_DEVICEOPT_NAME, CONFIG_HLP_DEVICE, 0, strptr:&devname, defstrval:NULL, TYPE_STRING, 0}\ +} + + + /*! \brief get device name from device type */ char *get_devname(int devtype); /*! \brief Initialize openair RF target. It returns 0 if OK */ diff --git a/targets/ARCH/COMMON/record_player.h b/targets/ARCH/COMMON/record_player.h index 903dda006b..500acdd709 100644 --- a/targets/ARCH/COMMON/record_player.h +++ b/targets/ARCH/COMMON/record_player.h @@ -37,19 +37,6 @@ extern "C" { #endif -#define CONFIG_OPT_RECPLAY "enable_recplay" - -#define CONFIG_HLP_RECPLAY "Allow record player" -#define USRP_SECTION "device.usrp" -/* inclusion for device configuration */ -/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ -/* command line parameters for USRP record/playback */ -/* optname helpstr paramflags XXXptr defXXXval type numelt */ -/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ -#define DEVICE_PARAMS_DESC { \ - {CONFIG_OPT_RECPLAY, CONFIG_HLP_RECPLAY, PARAMFLAG_BOOL, uptr:&enable_recplay, defuintval:0, TYPE_UINT, 0} \ - } - /* inclusions for record player */ #define RECPLAY_DISABLED 0 @@ -114,7 +101,7 @@ typedef struct { {CONFIG_OPT_SF_LOOPS, CONFIG_HLP_SF_LOOPS, 0, uptr:&((*recplay_conf)->u_sf_loops), defintval:DEF_SF_NB_LOOP, TYPE_UINT, 0}, \ {CONFIG_OPT_SF_RDELAY, CONFIG_HLP_SF_RDELAY, 0, uptr:&((*recplay_conf)->u_sf_read_delay), defintval:DEF_SF_DELAY_READ, TYPE_UINT, 0}, \ {CONFIG_OPT_SF_WDELAY, CONFIG_HLP_SF_WDELAY, 0, uptr:&((*recplay_conf)->u_sf_write_delay), defintval:DEF_SF_DELAY_WRITE, TYPE_UINT, 0}, \ - }/*! \brief USRP Configuration and state */ + }/*! \brief Record Player Configuration and state */ typedef struct { char u_sf_filename[1024]; // subframes file path unsigned int u_sf_max ; // max number of recorded subframes diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp index 5135be0cd4..f37c8cf5cf 100644 --- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp +++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp @@ -270,14 +270,17 @@ static int trx_usrp_start(openair0_device *device) { // setup GPIO for TDD, GPIO(4) = ATR_RX //set data direction register (DDR) to output - s->usrp->set_gpio_attr("FP0", "DDR", 0x7f, 0x7f); - //set control register to ATR - s->usrp->set_gpio_attr("FP0", "CTRL", 0x7f,0x7f); + s->usrp->set_gpio_attr("FP0", "DDR", 0xfff, 0xfff); + //set lower 7 bits to be controlled automatically by ATR (the rest 5 bits are controlled manually) + s->usrp->set_gpio_attr("FP0", "CTRL", 0x7f,0xfff); //set pins 4 (RX_TX_Switch) and 6 (Shutdown PA) to 1 when the radio is only receiving (ATR_RX) s->usrp->set_gpio_attr("FP0", "ATR_RX", (1<<4)|(1<<6), 0x7f); // set pin 5 (Shutdown LNA) to 1 when the radio is transmitting and receiveing (ATR_XX) // (we use full duplex here, because our RX is on all the time - this might need to change later) s->usrp->set_gpio_attr("FP0", "ATR_XX", (1<<5), 0x7f); + // set the output pins to 0 + s->usrp->set_gpio_attr("FP0", "OUT", 7<<7, 0xf80); + // init recv and send streaming uhd::stream_cmd_t cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS); LOG_I(HW,"Time in secs now: %llu \n", s->usrp->get_time_now().to_ticks(s->sample_rate)); @@ -326,10 +329,19 @@ static void trx_usrp_end(openair0_device *device) { @param antenna_id index of the antenna if the device has multiple antennas @param flags flags must be set to TRUE if timestamp parameter needs to be applied */ -static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, void **buff, int nsamps, int cc, int flags) { +static int trx_usrp_write(openair0_device *device, + openair0_timestamp timestamp, + void **buff, + int nsamps, + int cc, + int flags) { int ret=0; usrp_state_t *s = (usrp_state_t *)device->priv; int nsamps2; // aligned to upper 32 or 16 byte boundary + + int flags_lsb = flags&0xff; + int flags_msb = (flags>>8)&0xff; + #if defined(__x86_64) || defined(__i386__) #ifdef __AVX2__ nsamps2 = (nsamps+7)>>3; @@ -363,40 +375,51 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, boolean_t first_packet_state=false,last_packet_state=false; - if (flags == 2) { // start of burst + if (flags_lsb == 2) { // start of burst // s->tx_md.start_of_burst = true; // s->tx_md.end_of_burst = false; first_packet_state = true; last_packet_state = false; - } else if (flags == 3) { // end of burst + } else if (flags_lsb == 3) { // end of burst //s->tx_md.start_of_burst = false; //s->tx_md.end_of_burst = true; first_packet_state = false; last_packet_state = true; - } else if (flags == 4) { // start and end - // s->tx_md.start_of_burst = true; - // s->tx_md.end_of_burst = true; + } else if (flags_lsb == 4) { // start and end + // s->tx_md.start_of_burst = true; + // s->tx_md.end_of_burst = true; first_packet_state = true; last_packet_state = true; - } else if (flags==1) { // middle of burst - // s->tx_md.start_of_burst = false; - // s->tx_md.end_of_burst = false; + } else if (flags_lsb==1) { // middle of burst + // s->tx_md.start_of_burst = false; + // s->tx_md.end_of_burst = false; first_packet_state = false; last_packet_state = false; - } else if (flags==10) { // fail safe mode - // s->tx_md.has_time_spec = false; - // s->tx_md.start_of_burst = false; - // s->tx_md.end_of_burst = true; - first_packet_state = false; - last_packet_state = true; + } + else if (flags_lsb==10) { // fail safe mode + // s->tx_md.has_time_spec = false; + // s->tx_md.start_of_burst = false; + // s->tx_md.end_of_burst = true; + first_packet_state = false; + last_packet_state = true; } + s->tx_md.has_time_spec = true; s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet_state; s->tx_md.end_of_burst = last_packet_state; s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate); s->tx_count++; + // bit 3 enables gpio (for backward compatibility) + if (flags_msb&8) { + // push GPIO bits 7-9 from flags_msb + int gpio789=(flags_msb&7)<<7; + s->usrp->set_command_time(s->tx_md.time_spec); + s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380); + s->usrp->clear_command_time(); + } + if (cc>1) { std::vector buff_ptrs; @@ -404,7 +427,11 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, buff_ptrs.push_back(&(((int16_t *)buff_tx[i])[0])); ret = (int)s->tx_stream->send(buff_ptrs, nsamps, s->tx_md); - } else ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md); + } + else { + ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md); + } + if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps); return ret; @@ -1116,4 +1143,4 @@ extern "C" { return 0; } /*@}*/ -}/* extern c */ \ No newline at end of file +}/* extern c */ diff --git a/targets/ARCH/iqplayer/iqplayer_lib.c b/targets/ARCH/iqplayer/iqplayer_lib.c index beb05de3fd..c4133d1b11 100644 --- a/targets/ARCH/iqplayer/iqplayer_lib.c +++ b/targets/ARCH/iqplayer/iqplayer_lib.c @@ -25,6 +25,7 @@ */ #define _LARGEFILE_SOURCE #define _FILE_OFFSET_BITS 64 +#define NB_ANTENNAS_RX 2 #include #include #include @@ -45,7 +46,9 @@ static void parse_iqfile_header(openair0_device *device, iqfile_header_t *iq_fh) { - AssertFatal((memcmp(iq_fh->oaiid,OAIIQFILE_ID,sizeof(OAIIQFILE_ID)) == 0),"iqfile doesn't seem to be compatible with oai (invalid id in header)\n"); + AssertFatal((memcmp(iq_fh->oaiid,OAIIQFILE_ID,sizeof(OAIIQFILE_ID)) == 0), + "iqfile doesn't seem to be compatible with oai (invalid id %.4s in header)\n", + iq_fh->oaiid); device->type = iq_fh->devtype; device->openair0_cfg[0].tx_sample_advance=iq_fh->tx_sample_advance; device->openair0_cfg[0].tx_bw = device->openair0_cfg[0].rx_bw = iq_fh->bw; @@ -138,6 +141,13 @@ static int iqplayer_loadfile(openair0_device *device, openair0_config_t *openair return 0; } +/*! \brief start the oai iq player + * \param device, the hardware used + */ +static int trx_iqplayer_start(openair0_device *device){ + return 0; +} + /*! \brief Terminate operation of the oai iq player * \param device, the hardware used */ @@ -287,7 +297,7 @@ static int trx_iqplayer_read(openair0_device *device, openair0_timestamp *ptimes int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { device->openair0_cfg = openair0_cfg; - device->trx_start_func = NULL; + device->trx_start_func = trx_iqplayer_start; device->trx_get_stats_func = NULL; device->trx_reset_stats_func = NULL; device->trx_end_func = trx_iqplayer_end; diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index 906314a67c..54dfd3b888 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -478,9 +478,9 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi } if ( b->headerMode==false ) { - LOG_D(HW,"UEsock: %d Set b->lastReceivedTS %ld\n", fd, b->lastReceivedTS); if ( ! b->trashingPacket ) { b->lastReceivedTS=b->th.timestamp+b->th.size-byteToSample(b->remainToTransfer,b->th.nbAnt); + LOG_D(HW,"UEsock: %d Set b->lastReceivedTS %ld\n", fd, b->lastReceivedTS); } if ( b->remainToTransfer==0) { diff --git a/targets/COMMON/openairinterface5g_limits.h b/targets/COMMON/openairinterface5g_limits.h index 42752b44e0..aa99eee048 100644 --- a/targets/COMMON/openairinterface5g_limits.h +++ b/targets/COMMON/openairinterface5g_limits.h @@ -21,21 +21,18 @@ # define NUMBER_OF_CONNECTED_gNB_MAX 1 # else # define NUMBER_OF_UE_MAX 256 -# define NUMBER_OF_NR_UE_MAX 16 # define NUMBER_OF_UCI_VARS_MAX 256 # define NUMBER_OF_CONNECTED_eNB_MAX 1 # define NUMBER_OF_CONNECTED_gNB_MAX 3 # endif # else # define NUMBER_OF_UE_MAX 256 -# define NUMBER_OF_NR_UE_MAX 256 # define NUMBER_OF_UCI_VARS_MAX 256 # define NUMBER_OF_CONNECTED_eNB_MAX 1 # define NUMBER_OF_CONNECTED_gNB_MAX 1 # endif # else # define NUMBER_OF_UE_MAX 1 -# define NUMBER_OF_NR_UE_MAX 1 # define NUMBER_OF_UCI_VARS_MAX 56 # define NUMBER_OF_CONNECTED_eNB_MAX 1 # define NUMBER_OF_CONNECTED_gNB_MAX 1 @@ -53,20 +50,17 @@ and the other are using MAX_MOBILES_PER_ENB in for-loop. */ # ifndef UESIM_EXPANSION # define NUMBER_OF_UE_MAX 16 -# define NUMBER_OF_NR_UE_MAX 20 # define NUMBER_OF_UCI_VARS_MAX 56 # define NUMBER_OF_CONNECTED_eNB_MAX 3 # define NUMBER_OF_CONNECTED_gNB_MAX 3 # else # define NUMBER_OF_UE_MAX 256 -# define NUMBER_OF_NR_UE_MAX 20 # define NUMBER_OF_UCI_VARS_MAX 256 # define NUMBER_OF_CONNECTED_eNB_MAX 1 # define NUMBER_OF_CONNECTED_gNB_MAX 3 # endif # else # define NUMBER_OF_UE_MAX 256 -# define NUMBER_OF_NR_UE_MAX 256 # define NUMBER_OF_UCI_VARS_MAX 256 # define NUMBER_OF_CONNECTED_eNB_MAX 1 # define NUMBER_OF_CONNECTED_gNB_MAX 1 @@ -76,7 +70,6 @@ and the other are using MAX_MOBILES_PER_ENB in for-loop. # undef NUMBER_OF_gNB_MAX # undef NUMBER_OF_UE_MAX -# undef NUMBER_OF_NR_UE_MAX # undef NUMBER_OF_RU_MAX # undef NUMBER_OF_NR_RU_MAX @@ -85,7 +78,6 @@ and the other are using MAX_MOBILES_PER_ENB in for-loop. # define NUMBER_OF_gNB_MAX 3 # define NUMBER_OF_UE_MAX 3 -# define NUMBER_OF_NR_UE_MAX 3 # define NUMBER_OF_RU_MAX 3 # define NUMBER_OF_NR_RU_MAX 3 @@ -95,7 +87,6 @@ and the other are using MAX_MOBILES_PER_ENB in for-loop. # undef NUMBER_OF_gNB_MAX # undef NUMBER_OF_UE_MAX -# undef NUMBER_OF_NR_UE_MAX # undef NUMBER_OF_CONNECTED_eNB_MAX # undef NUMBER_OF_CONNECTED_gNB_MAX @@ -107,7 +98,6 @@ and the other are using MAX_MOBILES_PER_ENB in for-loop. # define NUMBER_OF_gNB_MAX 2 # define NUMBER_OF_UE_MAX 120 -# define NUMBER_OF_NR_UE_MAX 120 # define NUMBER_OF_RU_MAX 16 # define NUMBER_OF_NR_RU_MAX 16 diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index b98adf5a95..904a455600 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -21,183 +21,166 @@ gNBs = ////////// Physical parameters: - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = -120000000; - Nid_cell = 0; - N_RB_DL = 106; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x01; - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; + #spCellConfigCommon - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; + physCellId = 0; - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641032; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } # ------- SCTP definitions SCTP : @@ -246,17 +229,16 @@ L1s = ( RUs = ( { local_rf = "yes" - nb_tx = 1; - nb_rx = 1; - att_tx = 0; + nb_tx = 1 + nb_rx = 1 + att_tx = 0 att_rx = 0; bands = [7]; max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - - sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2,clock_source=external,time_source=external"; - + sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2"; + #clock_src = "external"; } ); @@ -269,16 +251,6 @@ THREAD_STRUCT = ( } ); -NETWORK_CONTROLLER : -{ - FLEXRAN_ENABLED = "no"; - FLEXRAN_INTERFACE_NAME = "lo"; - FLEXRAN_IPV4_ADDRESS = "127.0.0.1"; - FLEXRAN_PORT = 2210; - FLEXRAN_CACHE = "/mnt/oai_agent_cache"; - FLEXRAN_AWAIT_RECONF = "no"; -}; - log_config : { global_log_level ="info"; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf index 420188b80e..06aa4f6f9f 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf @@ -21,183 +21,166 @@ gNBs = ////////// Physical parameters: - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = 0; - Nid_cell = 0; - N_RB_DL = 106; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x01;##### - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; + #spCellConfigCommon - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; + physCellId = 0; - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 633032; + dl_frequencyBand = 78; + # this is 3480 MHz + dl_absoluteFrequencyPointA = 632000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13475; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 255; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } # ------- SCTP definitions SCTP : @@ -246,7 +229,7 @@ L1s = ( RUs = ( { local_rf = "yes" - nb_tx = 1 + nb_tx = 1 nb_rx = 1 att_tx = 0 att_rx = 0; @@ -254,8 +237,7 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "type=x300"; - + sdr_addrs = "type=x300"; } ); @@ -268,16 +250,6 @@ THREAD_STRUCT = ( } ); -NETWORK_CONTROLLER : -{ - FLEXRAN_ENABLED = "no"; - FLEXRAN_INTERFACE_NAME = "lo"; - FLEXRAN_IPV4_ADDRESS = "127.0.0.1"; - FLEXRAN_PORT = 2210; - FLEXRAN_CACHE = "/mnt/oai_agent_cache"; - FLEXRAN_AWAIT_RECONF = "no"; -}; - log_config : { global_log_level ="info"; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf index 06c52e1aff..b82c455ef4 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf @@ -21,183 +21,166 @@ gNBs = ////////// Physical parameters: - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = -120000000; - Nid_cell = 0; - N_RB_DL = 217; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x01; - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; + #spCellConfigCommon - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; + physCellId = 0; - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 642364; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 217; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 217; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 1; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } # ------- SCTP definitions SCTP : @@ -215,15 +198,29 @@ gNBs = preference = "ipv4"; } ); + + ///X2 + enable_x2 = "no"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.12.108"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); NETWORK_INTERFACES : { GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; - GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.188/24"; GNB_INTERFACE_NAME_FOR_S1U = "eth0"; - GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.188/24"; GNB_PORT_FOR_S1U = 2152; # Spec 2152 + + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.12.188/23"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 }; } ); @@ -268,13 +265,21 @@ THREAD_STRUCT = ( } ); - log_config : +#rfsimulator : +#{ +# serveraddr = "server"; +# serverport = "4043"; +# options = ("chanmod"); +# modelname = "AWGN"; +#}; + +log_config : { global_log_level ="info"; global_log_verbosity ="medium"; hw_log_level ="info"; hw_log_verbosity ="medium"; - phy_log_level ="info"; + phy_log_level ="debug"; phy_log_verbosity ="medium"; mac_log_level ="info"; mac_log_verbosity ="high"; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf index 691224b883..4cbec5b86e 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf @@ -21,183 +21,166 @@ gNBs = ////////// Physical parameters: - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = -120000000; - Nid_cell = 0; - N_RB_DL = 217; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x0ff; - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; + #spCellConfigCommon - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; + physCellId = 0; - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 642016; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 217; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 217; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 255; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } # ------- SCTP definitions SCTP : @@ -246,7 +229,7 @@ L1s = ( RUs = ( { local_rf = "yes" - nb_tx = 8 + nb_tx = 1 nb_rx = 1 att_tx = 0 att_rx = 0; @@ -255,29 +238,18 @@ RUs = ( max_rxgain = 114; eNB_instances = [0]; sdr_addrs = "type=x300"; - } ); THREAD_STRUCT = ( { #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" - parallel_config = "PARALLEL_SINGLE_THREAD"; + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" worker_config = "WORKER_ENABLE"; } ); -NETWORK_CONTROLLER : -{ - FLEXRAN_ENABLED = "no"; - FLEXRAN_INTERFACE_NAME = "lo"; - FLEXRAN_IPV4_ADDRESS = "127.0.0.1"; - FLEXRAN_PORT = 2210; - FLEXRAN_CACHE = "/mnt/oai_agent_cache"; - FLEXRAN_AWAIT_RECONF = "no"; -}; - log_config : { global_log_level ="info"; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf index ce8af8f5b8..f5e2298a99 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf @@ -21,183 +21,166 @@ gNBs = ////////// Physical parameters: - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = -120000000; - Nid_cell = 0; - N_RB_DL = 273; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x01; - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; + #spCellConfigCommon - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; + physCellId = 0; - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 642016; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 273; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=2,L=3 + initialDLBWPstartSymbolAndLength_0 = 40; - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 273; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 13559; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#0 = 839, 1 = 139 + prach_RootSequenceIndex_PR = 1; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 255; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } # ------- SCTP definitions SCTP : @@ -254,7 +237,8 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2,mgmt_addr=192.168.10.2,clock_source=external,time_source=external"; + sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2"; + clock_src = "external"; } ); diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.beamw.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.beamw.usrpn300.conf deleted file mode 100644 index a9d251efa2..0000000000 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.beamw.usrpn300.conf +++ /dev/null @@ -1,291 +0,0 @@ -Active_gNBs = ( "gNB-Eurecom-5GNRBox"); -# Asn1_verbosity, choice in: none, info, annoying -Asn1_verbosity = "none"; - -gNBs = -( - { - ////////// Identification parameters: - gNB_ID = 0xe00; - - cell_type = "CELL_MACRO_GNB"; - - gNB_name = "gNB-Eurecom-5GNRBox"; - - // Tracking area code, 0x0000 and 0xfffe are reserved values - tracking_area_code = 1; - - plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); - - tr_s_preference = "local_mac" - - ////////// Physical parameters: - - component_carriers = ( - { - node_function = "3GPP_gNODEB"; - node_timing = "synch_to_ext_device"; - node_synch_ref = 0; - frame_type = "TDD"; - DL_prefix_type = "NORMAL"; - UL_prefix_type = "NORMAL"; - eutra_band = 78; - downlink_frequency = 3510000000L; - uplink_frequency_offset = -120000000; - Nid_cell = 0; - N_RB_DL = 217; - nb_antenna_ports = 1; - nb_antennas_tx = 1; - nb_antennas_rx = 1; - tx_gain = 90; - rx_gain = 125; - MIB_subCarrierSpacingCommon = 30; - MIB_ssb_SubcarrierOffset = 0; - MIB_dmrs_TypeA_Position = 2; - pdcch_ConfigSIB1 = 0; - SIB1_frequencyOffsetSSB = "khz5"; - SIB1_ssb_PeriodicityServingCell = 5; - SIB1_ss_PBCH_BlockPower = -60; - absoluteFrequencySSB = 0; - DL_FreqBandIndicatorNR = 15; - DL_absoluteFrequencyPointA = 15; - DL_offsetToCarrier = 15; - DL_SCS_SubcarrierSpacing = "kHz30"; - DL_SCS_SpecificCarrier_k0 = 0; - DL_carrierBandwidth = 15; - DL_locationAndBandwidth = 15; - DL_BWP_SubcarrierSpacing = "kHz30"; - DL_BWP_prefix_type = "NORMAL"; - UL_FreqBandIndicatorNR = 15; - UL_absoluteFrequencyPointA = 13; - UL_additionalSpectrumEmission = 3; - UL_p_Max = -1; - UL_frequencyShift7p5khz = "TRUE"; - UL_offsetToCarrier = 10; - UL_SCS_SubcarrierSpacing = "kHz30"; - UL_SCS_SpecificCarrier_k0 = 0; - UL_carrierBandwidth = 15; - UL_locationAndBandwidth = 15; - UL_BWP_SubcarrierSpacing = "kHz30"; - UL_BWP_prefix_type = "NORMAL"; - UL_timeAlignmentTimerCommon = "infinity"; - ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" - ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x03; - ServingCellConfigCommon_ssb_periodicityServingCell = 10; - ServingCellConfigCommon_dmrs_TypeA_Position = 2; - NIA_SubcarrierSpacing = "kHz15"; - ServingCellConfigCommon_ss_PBCH_BlockPower = -60; - referenceSubcarrierSpacing = "kHz15"; - dl_UL_TransmissionPeriodicity = "ms0p5"; - nrofDownlinkSlots = 10; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 10; - nrofUplinkSymbols = 10; - rach_totalNumberOfRA_Preambles = 63; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; - rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; - rach_groupBconfigured = "ENABLE"; - rach_ra_Msg3SizeGroupA = 56; - rach_messagePowerOffsetGroupB = "dB0"; - rach_numberOfRA_PreamblesGroupA = 32; - rach_ra_ContentionResolutionTimer = 8; - rsrp_ThresholdSSB = 64; - rsrp_ThresholdSSB_SUL = 64; - prach_RootSequenceIndex_choice = "l839"; - prach_RootSequenceIndex_l839 = 0; - prach_RootSequenceIndex_l139 = 0; - prach_msg1_SubcarrierSpacing = "kHz30"; - restrictedSetConfig = "unrestrictedSet"; - msg3_transformPrecoding = "ENABLE"; - prach_ConfigurationIndex = 10; - prach_msg1_FDM = "one"; - prach_msg1_FrequencyStart = 10; - zeroCorrelationZoneConfig = 10; - preambleReceivedTargetPower = -150; - preambleTransMax = 6; - powerRampingStep = "dB0"; - ra_ResponseWindow = 8; - groupHoppingEnabledTransformPrecoding = "ENABLE"; - msg3_DeltaPreamble = 0; - p0_NominalWithGrant = 0; - PUSCH_TimeDomainResourceAllocation_k2 = 0; - PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - pucch_ResourceCommon = 0; - pucch_GroupHopping = "neither"; - hoppingId = 0; - p0_nominal = -30; - PDSCH_TimeDomainResourceAllocation_k0 = 2; - PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; - PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; - rateMatchPatternId = 0; - RateMatchPattern_patternType = "bitmaps"; - symbolsInResourceBlock = "oneSlot"; - periodicityAndPattern = 2; - RateMatchPattern_controlResourceSet = 5; - RateMatchPattern_subcarrierSpacing = "kHz30"; - RateMatchPattern_mode = "dynamic"; - controlResourceSetZero = 0; - searchSpaceZero = 0; - searchSpaceSIB1 = 10; - searchSpaceOtherSystemInformation = 10; - pagingSearchSpace = 10; - ra_SearchSpace = 10; - PDCCH_common_controlResourceSetId = 5; - PDCCH_common_ControlResourceSet_duration = 2; - PDCCH_cce_REG_MappingType = "nonInterleaved"; - PDCCH_reg_BundleSize = 3; - PDCCH_interleaverSize = 3; - PDCCH_shiftIndex = 10; - PDCCH_precoderGranularity = "sameAsREG-bundle"; - PDCCH_TCI_StateId = 32; - tci_PresentInDCI = "ENABLE"; - PDCCH_DMRS_ScramblingID = 0; - SearchSpaceId = 10; - commonSearchSpaces_controlResourceSetId = 5; - SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; - SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; - SearchSpace_duration = 2; - SearchSpace_nrofCandidates_aggregationLevel1 = 0; - SearchSpace_nrofCandidates_aggregationLevel2 = 0; - SearchSpace_nrofCandidates_aggregationLevel4 = 0; - SearchSpace_nrofCandidates_aggregationLevel8 = 0; - SearchSpace_nrofCandidates_aggregationLevel16 = 0; - SearchSpace_searchSpaceType = "common"; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; - Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; - Common_dci_Format2_3_monitoringPeriodicity = 1; - Common_dci_Format2_3_nrofPDCCH_Candidates = 1; - ue_Specific__dci_Formats = "formats0-0-And-1-0"; - RateMatchPatternLTE_CRS_carrierFreqDL = 6; - RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; - RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; - RateMatchPatternLTE_CRS_v_Shift = 0; - RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; - RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; - RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; - } - ); - - - srb1_parameters : - { - # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] - timer_poll_retransmit = 80; - - # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] - timer_reordering = 35; - - # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] - timer_status_prohibit = 0; - - # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] - poll_pdu = 4; - - # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] - poll_byte = 99999; - - # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] - max_retx_threshold = 4; - } - - # ------- SCTP definitions - SCTP : - { - # Number of streams to use in input/output - SCTP_INSTREAMS = 2; - SCTP_OUTSTREAMS = 2; - }; - - - ////////// MME parameters: - mme_ip_address = ( { ipv4 = "192.168.12.26"; - ipv6 = "192:168:30::17"; - active = "yes"; - preference = "ipv4"; - } - ); - - NETWORK_INTERFACES : - { - - GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; - GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; - GNB_INTERFACE_NAME_FOR_S1U = "eth0"; - GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; - GNB_PORT_FOR_S1U = 2152; # Spec 2152 - }; - } -); - -MACRLCs = ( - { - num_cc = 1; - tr_s_preference = "local_L1"; - tr_n_preference = "local_RRC"; - } -); - -L1s = ( - { - num_cc = 1; - tr_n_preference = "local_mac"; - } -); - -RUs = ( - { - local_rf = "yes" - nb_tx = 2 - nb_rx = 1 - att_tx = 0 - att_rx = 0; - bands = [7]; - max_pdschReferenceSignalPower = -27; - max_rxgain = 114; - eNB_instances = [0]; - sdr_addrs = "addr=192.168.10.2"; - # beamforming weights for static beams each of them is a int32 composed by two int16 representing imaginary and real part of the weight - # weights are input in an array, starting with the weights associated to first logical beam for all nb_tx , than the weights for 2nd logical beam and so on - # the list size is (nb_tx) X (number of logical beams) - bf_weights = [0x00007fff, 0x00000000, 0x00000000, 0x00007fff]; - } -); - -THREAD_STRUCT = ( - { - #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" - parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; - #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" - worker_config = "WORKER_ENABLE"; - } -); - - log_config : - { - global_log_level ="info"; - global_log_verbosity ="medium"; - hw_log_level ="info"; - hw_log_verbosity ="medium"; - phy_log_level ="info"; - phy_log_verbosity ="medium"; - mac_log_level ="info"; - mac_log_verbosity ="high"; - rlc_log_level ="info"; - rlc_log_verbosity ="medium"; - pdcp_log_level ="info"; - pdcp_log_verbosity ="medium"; - rrc_log_level ="info"; - rrc_log_verbosity ="medium"; - }; - diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index f88d98536d..e6364cad23 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -2194,7 +2194,9 @@ int start_rf(RU_t *ru) { } int stop_rf(RU_t *ru) { - ru->rfdevice.trx_end_func(&ru->rfdevice); + if(ru->rfdevice.trx_end_func != NULL) { + ru->rfdevice.trx_end_func(&ru->rfdevice); + } return 0; } @@ -2342,11 +2344,15 @@ void init_RU_proc(RU_t *ru) { init_frame_parms(ru->frame_parms,1); ru->frame_parms->nb_antennas_rx = ru->nb_rx; phy_init_RU(ru); - openair0_device_load(&ru->rfdevice,&ru->openair0_cfg); + ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg); + if (ret < 0) { + LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n"); + exit(1); + } if (setup_RU_buffers(ru)!=0) { - printf("Exiting, cannot initialize RU Buffers\n"); - exit(-1); + LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n"); + exit(1); } } diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c index c08ab2a77b..0b365ea938 100644 --- a/targets/RT/USER/lte-softmodem.c +++ b/targets/RT/USER/lte-softmodem.c @@ -113,7 +113,7 @@ uint16_t runtime_phy_tx[29][6]; // SISO [MCS 0-28][RBs 0-5 : 6, 15, 25, 50, 75, volatile int oai_exit = 0; -uint32_t downlink_frequency[MAX_NUM_CCs][4]; +uint64_t downlink_frequency[MAX_NUM_CCs][4]; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; int UE_scan = 1; diff --git a/targets/RT/USER/lte-softmodem.h b/targets/RT/USER/lte-softmodem.h index 7b896b2817..5e1bf36160 100644 --- a/targets/RT/USER/lte-softmodem.h +++ b/targets/RT/USER/lte-softmodem.h @@ -141,7 +141,7 @@ extern pthread_cond_t sync_cond; extern pthread_mutex_t sync_mutex; extern int sync_var; -extern uint32_t downlink_frequency[MAX_NUM_CCs][4]; +extern uint64_t downlink_frequency[MAX_NUM_CCs][4]; extern int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; extern int rx_input_level_dBm; diff --git a/targets/RT/USER/lte-ue.c b/targets/RT/USER/lte-ue.c index 5a8afc2358..75ed018434 100644 --- a/targets/RT/USER/lte-ue.c +++ b/targets/RT/USER/lte-ue.c @@ -88,7 +88,7 @@ extern void oai_subframe_ind(uint16_t sfn, uint16_t sf); extern void multicast_link_start(void (*rx_handlerP) (unsigned int, char *), unsigned char _multicast_group, char *multicast_ifname); extern int oai_nfapi_crc_indication(nfapi_crc_indication_t *crc_ind); -extern int oai_nfapi_crc_indication(nfapi_crc_indication_t *crc_ind); +extern int oai_nfapi_cqi_indication(nfapi_cqi_indication_t *cqi_ind); extern int oai_nfapi_harq_indication(nfapi_harq_indication_t *harq_ind); extern int oai_nfapi_sr_indication(nfapi_sr_indication_t *ind); extern int oai_nfapi_rx_ind(nfapi_rx_indication_t *ind); @@ -992,6 +992,19 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) phy_stub_ticking->num_single_thread[ue_thread_id] = -1; UE = rtd->UE; + UL_INFO = (UL_IND_t *)malloc(sizeof(UL_IND_t)); + UL_INFO->rx_ind.rx_indication_body.rx_pdu_list = calloc(NB_UE_INST, sizeof(nfapi_rx_indication_pdu_t)); + UL_INFO->rx_ind.rx_indication_body.number_of_pdus = 0; + UL_INFO->crc_ind.crc_indication_body.crc_pdu_list = calloc(NB_UE_INST, sizeof(nfapi_crc_indication_pdu_t)); + UL_INFO->crc_ind.crc_indication_body.number_of_crcs = 0; + UL_INFO->harq_ind.harq_indication_body.harq_pdu_list = calloc(NB_UE_INST, sizeof(nfapi_harq_indication_pdu_t)); + UL_INFO->harq_ind.harq_indication_body.number_of_harqs = 0; + UL_INFO->sr_ind.sr_indication_body.sr_pdu_list = calloc(NB_UE_INST, sizeof(nfapi_sr_indication_pdu_t)); + UL_INFO->sr_ind.sr_indication_body.number_of_srs = 0; + UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list = calloc(NB_UE_INST, sizeof(nfapi_cqi_indication_pdu_t)); + UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list = calloc(NB_UE_INST, sizeof(nfapi_cqi_indication_raw_pdu_t)); + UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis = 0; + if(ue_thread_id == 0) { phy_stub_ticking->ticking_var = -1; proc->subframe_rx=proc->sub_frame_start; @@ -1064,20 +1077,6 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) initRefTimes(t3); pickTime(current); updateTimes(proc->gotIQs, &t2, 10000, "Delay to wake up UE_Thread_Rx (case 2)");*/ - // Not sure whether we should put the memory allocation here and not sure how much memory - //we should allocate for each subframe cycle. - UL_INFO = (UL_IND_t *)malloc(sizeof(UL_IND_t)); - UL_INFO->rx_ind.rx_indication_body.rx_pdu_list = (nfapi_rx_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_rx_indication_pdu_t)); - UL_INFO->rx_ind.rx_indication_body.number_of_pdus = 0; - UL_INFO->crc_ind.crc_indication_body.crc_pdu_list = (nfapi_crc_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_crc_indication_pdu_t)); - UL_INFO->crc_ind.crc_indication_body.number_of_crcs = 0; - UL_INFO->harq_ind.harq_indication_body.harq_pdu_list = (nfapi_harq_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_harq_indication_pdu_t)); - UL_INFO->harq_ind.harq_indication_body.number_of_harqs = 0; - UL_INFO->sr_ind.sr_indication_body.sr_pdu_list = (nfapi_sr_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_sr_indication_pdu_t)); - UL_INFO->sr_ind.sr_indication_body.number_of_srs = 0; - UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list = (nfapi_cqi_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_cqi_indication_pdu_t)); - UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list = (nfapi_cqi_indication_raw_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_cqi_indication_raw_pdu_t)); - UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis = 0; if (pthread_mutex_lock(&phy_stub_ticking->mutex_single_thread) != 0) { LOG_E( MAC, "[SCHED][UE] error locking mutex for ue_thread_id %d (mutex_single_thread)\n",ue_thread_id); @@ -1253,6 +1252,11 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) UL_INFO->rx_ind.rx_indication_body.number_of_pdus = 0; } + if (UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis > 0) { + oai_nfapi_cqi_indication(&UL_INFO->cqi_ind); + UL_INFO->cqi_ind.cqi_indication_body.number_of_cqis = 0; + } + if(UL_INFO->harq_ind.harq_indication_body.number_of_harqs>0) { //LOG_D(MAC, "ul_config_req_UE_MAC 2.4, SFN/SF of PNF counter:%d.%d, number_of_harqs: %d \n", timer_frame, timer_subframe, UL_INFO->harq_ind.harq_indication_body.number_of_harqs); oai_nfapi_harq_indication(&UL_INFO->harq_ind); @@ -1267,30 +1271,6 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) UL_INFO->sr_ind.sr_indication_body.number_of_srs = 0; } - // Free UL_INFO messages - //if(UL_INFO->crc_ind.crc_indication_body.crc_pdu_list != NULL){ - free(UL_INFO->crc_ind.crc_indication_body.crc_pdu_list); - UL_INFO->crc_ind.crc_indication_body.crc_pdu_list = NULL; - //} - //if(UL_INFO->rx_ind.rx_indication_body.rx_pdu_list != NULL){ - free(UL_INFO->rx_ind.rx_indication_body.rx_pdu_list); - UL_INFO->rx_ind.rx_indication_body.rx_pdu_list = NULL; - //} - //if(UL_INFO->harq_ind.harq_indication_body.harq_pdu_list !=NULL){ - free(UL_INFO->harq_ind.harq_indication_body.harq_pdu_list); - UL_INFO->harq_ind.harq_indication_body.harq_pdu_list = NULL; - //} - //if(UL_INFO->sr_ind.sr_indication_body.sr_pdu_list!=NULL){ - free(UL_INFO->sr_ind.sr_indication_body.sr_pdu_list); - UL_INFO->sr_ind.sr_indication_body.sr_pdu_list = NULL; - //} - free(UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list); - UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list = NULL; - free(UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list); - UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list = NULL; - free(UL_INFO); - UL_INFO = NULL; - // De-allocate memory of nfapi requests copies before next subframe round if(dl_config_req!=NULL) { if(dl_config_req->vendor_extension!=NULL) { @@ -1308,6 +1288,13 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) } if(tx_request_pdu_list!=NULL) { + for (int i = 0; i < tx_req_num_elems; i++) { + for (int j = 0; j < tx_request_pdu_list[i].num_segments; j++) { + free(tx_request_pdu_list[i].segments[j].segment_data); + tx_request_pdu_list[i].segments[j].segment_data = NULL; + } + } + tx_req_num_elems = 0; free(tx_request_pdu_list); tx_request_pdu_list = NULL; } @@ -1334,6 +1321,22 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) } } + // Free UL_INFO messages + free(UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list); + UL_INFO->cqi_ind.cqi_indication_body.cqi_raw_pdu_list = NULL; + free(UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list); + UL_INFO->cqi_ind.cqi_indication_body.cqi_pdu_list = NULL; + free(UL_INFO->sr_ind.sr_indication_body.sr_pdu_list); + UL_INFO->sr_ind.sr_indication_body.sr_pdu_list = NULL; + free(UL_INFO->harq_ind.harq_indication_body.harq_pdu_list); + UL_INFO->harq_ind.harq_indication_body.harq_pdu_list = NULL; + free(UL_INFO->crc_ind.crc_indication_body.crc_pdu_list); + UL_INFO->crc_ind.crc_indication_body.crc_pdu_list = NULL; + free(UL_INFO->rx_ind.rx_indication_body.rx_pdu_list); + UL_INFO->rx_ind.rx_indication_body.rx_pdu_list = NULL; + free(UL_INFO); + UL_INFO = NULL; + // thread finished free(arg); return &UE_thread_rxtx_retval; diff --git a/targets/RT/USER/lte-uesoftmodem.c b/targets/RT/USER/lte-uesoftmodem.c index d0014b5e8a..25371260bf 100644 --- a/targets/RT/USER/lte-uesoftmodem.c +++ b/targets/RT/USER/lte-uesoftmodem.c @@ -120,7 +120,7 @@ clock_source_t clock_source = internal,time_source=internal; unsigned int mmapped_dma=0; -uint32_t downlink_frequency[MAX_NUM_CCs][4]; +uint64_t downlink_frequency[MAX_NUM_CCs][4]; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; From a1024058965a64123f21ce394afe97798d3d85b3 Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Wed, 13 May 2020 22:31:30 +0800 Subject: [PATCH 08/70] LDPC cuda support BG1 all length --- openair1/PHY/CODING/TESTBENCH/ldpctest.c | 10 -------- .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu | 23 +++++++++++++------ .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h | 11 +++++++++ .../CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h | 11 +++++++++ 4 files changed, 38 insertions(+), 17 deletions(-) diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index 732cc75d6c..d47d6e7755 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -20,16 +20,6 @@ */ // add GPU mode (-G 1) - /*! \file PHY/CODING/TESTBENCH/ldpctest.c - * \brief Merge remote-tracking branch 'origin/develop' into NCTU_OpinConnect_LDPC - * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN - * \email tyhsu@cs.nctu.edu.tw - * \date 13-05-2020 - * \version - * \note - * \warning - */ - #include #include #include diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu index e48cee7fb9..68ca2f450f 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu @@ -1,3 +1,13 @@ + /*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu + * \brief LDPC cuda support BG1 all length + * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ + #include #include #include @@ -143,8 +153,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, for(int i = 0; i < s; i++){ // v0: Best performance so far. 0.75f is the value of alpha. sq = 1 - 2 * ((Q_sign >> i) & 0x01); -// R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); - R_temp = sign * sq * (i != idx_min ? rmin1 : rmin2); + R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); // write results to global memory h_element_t = dev_h_compact1[i*row+iBlkRow]; int addr_temp = offsetR + h_element_t.y * row * Zc; @@ -214,8 +223,8 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, // The 2nd recursion for(int i = 0; i < s; i ++){ sq = 1 - 2 * ((Q_sign >> i) & 0x01); -// R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); - R_temp = sign * sq * (i != idx_min ? rmin1 : rmin2); + R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); + // write results to global memory h_element_t = dev_h_compact1[i*row+iBlkRow]; @@ -251,7 +260,7 @@ ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int { h_element_t = dev_h_compact2[i*col+iBlkCol]; - shift_t = h_element_t.value; + shift_t = h_element_t.value%Zc; iBlkRow = h_element_t.x; sf = iSubCol - shift_t; @@ -472,7 +481,7 @@ start_meas(time_decoder); // Define CUDA kernel dimension - int blockSizeX = (Zc + 32 - 1)/ 32 * 32; // round block size to multiples of 32 + int blockSizeX = Zc; dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks dim3 dimBlockKernel1(blockSizeX, 1, 1); @@ -513,7 +522,7 @@ start_meas(time_decoder); (dev_llr, dev_dt, dev_const_llr, BG, row, col, Zc); } - int pack = block_length/128; + int pack = (block_length/128)+1; dim3 pack_block(pack, MC, 1); pack_decoded_bit<<>>(dev_llr, dev_tmp, col, Zc); diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h index 5602ccecdd..e74f42b3d3 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h @@ -4,6 +4,17 @@ #include "nrLDPC_types.h" #include "nrLDPC_init_mem.h" +/*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h + * \brief LDPC cuda support BG1 all length + * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ + + /*** \brief LDPC decoder \param p_decParams LDPC decoder parameters diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h index de17d8be07..9c64c262b9 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h @@ -19,6 +19,17 @@ * contact@openairinterface.org */ + /*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h + * \brief LDPC cuda support BG1 all length + * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN + * \email tyhsu@cs.nctu.edu.tw + * \date 13-05-2020 + * \version + * \note + * \warning + */ + + /*!\file nrLDPC_defs.h * \brief Defines all constants and buffers for the LDPC decoder * \author Sebastian Wagner (TCL Communications) Email: From 03d354efcea67f186c107d7e18a56b9c45753b87 Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Mon, 1 Jun 2020 19:27:44 +0800 Subject: [PATCH 09/70] merge to develop --- NOTICE.md | 2 +- ci-scripts/.gitignore | 2 + ci-scripts/Jenkinsfile-inria-r2lab | 47 +- ci-scripts/checkCodingFormattingRules.sh | 65 + .../enb.band17.tm1.mbms.25PRB.usrpb210.conf | 2 +- ci-scripts/cppcheck_suppressions.list | 5 + ci-scripts/main.py | 3737 ++----- ci-scripts/reportBuildLocally.sh | 71 + ci-scripts/runTestOnVM.sh | 176 +- .../enb_usrp210_band13_test_10mhz_tm1.xml | 2 +- .../enb_usrp210_band40_test_05mhz_tm2.xml | 2 +- ...st_05mhz_tm1_rrc_inactivity_no_flexran.xml | 4 +- ...est_05mhz_tm1_rrc_inactivity_w_flexran.xml | 4 +- .../enb_ue_usrp210_band7_test_05mhz_tm1.xml | 2 +- ...b_ue_usrp210_band7_test_05mhz_tm1_nos1.xml | 2 +- .../enb_usrp210_band7_test_05mhz_tm1.xml | 2 +- ...enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml | 4 +- cmake_targets/CMakeLists.txt | 127 +- cmake_targets/autotests/test_case_list.xml | 46 +- cmake_targets/build_oai | 9 +- cmake_targets/nas_sim_tools/CMakeLists.txt | 1 + cmake_targets/phy_simulators/CMakeLists.txt | 30 +- cmake_targets/tools/build_helper | 13 +- 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openair2/LAYER2/PROTO_AGENT/proto_agent.h | 49 +- .../LAYER2/PROTO_AGENT/proto_agent_async.c | 49 +- .../LAYER2/PROTO_AGENT/proto_agent_async.h | 48 +- .../LAYER2/PROTO_AGENT/proto_agent_common.c | 48 +- .../LAYER2/PROTO_AGENT/proto_agent_common.h | 48 +- .../LAYER2/PROTO_AGENT/proto_agent_defs.h | 48 +- .../LAYER2/PROTO_AGENT/proto_agent_handler.c | 48 +- .../LAYER2/PROTO_AGENT/proto_agent_net_comm.c | 48 +- .../LAYER2/PROTO_AGENT/proto_agent_net_comm.h | 48 +- openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c | 26 +- openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.h | 12 +- openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.c | 3 - openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.h | 4 +- openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.c | 15 +- openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.h | 16 +- openair2/LAYER2/RLC/rlc.h | 11 +- openair2/LAYER2/RLC/rlc_mac.c | 14 +- openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c | 10 +- openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h | 4 - openair2/LAYER2/openair2_proc.c | 104 +- openair2/M2AP/m2ap_MCE_handler.h | 6 +- .../M2AP/m2ap_MCE_management_procedures.h | 6 +- openair2/M2AP/m2ap_eNB_generate_messages.h | 6 +- .../M2AP/m2ap_eNB_management_procedures.h | 6 +- openair2/MCE_APP/mce_app.c | 4 +- openair2/NETWORK_DRIVER/LITE/proto_extern.h | 4 +- openair2/NETWORK_DRIVER/MESH/proto_extern.h | 4 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 137 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.h | 23 +- openair2/PHY_INTERFACE/IF_Module.c | 4 +- openair2/PHY_INTERFACE/IF_Module.h | 75 +- openair2/PHY_INTERFACE/phy_stub_UE.c | 343 +- openair2/PHY_INTERFACE/phy_stub_UE.h | 26 +- openair2/RRC/LTE/rrc_eNB.c | 305 +- openair2/RRC/LTE/rrc_eNB_UE_context.h | 2 + openair2/RRC/LTE/utils.c | 14 +- openair2/RRC/NR/MESSAGES/asn1_msg.c | 4 +- openair2/RRC/NR/nr_rrc_extern.h | 10 +- openair2/RRC/NR/rrc_gNB.c | 8 +- openair2/RRC/NR/rrc_gNB_UE_context.h | 6 +- openair2/RRC/NR/rrc_gNB_nsa.c | 6 +- openair2/UTIL/MEM/mem_block.c | 668 -- openair2/UTIL/MEM/mem_block.h | 108 - openair2/UTIL/MEM/mem_mngt.c | 489 - openair2/UTIL/MEM/mem_mngt_proto_extern.h | 21 - openair2/UTIL/MEM/mem_pool.h | 38 - openair2/UTIL/OCG/OCG_if.h | 4 +- openair2/UTIL/OPT/mac_pcap.h | 5 +- openair2/UTIL/OPT/opt.h | 4 - openair2/UTIL/OPT/packet-mac-lte.h | 4 + openair2/UTIL/OPT/probe.c | 12 +- openair2/UTIL/OSA/osa_defs.h | 6 +- openair2/UTIL/OTG/traffic_config.h | 5 + openair2/X2AP/x2ap_eNB_generate_messages.c | 10 +- openair2/X2AP/x2ap_eNB_handler.c | 5 +- .../X2AP/x2ap_eNB_management_procedures.h | 6 +- openair3/M3AP/m3ap_MCE_generate_messages.h | 25 +- openair3/M3AP/m3ap_MCE_handler.h | 10 +- .../M3AP/m3ap_MCE_management_procedures.h | 6 +- openair3/M3AP/m3ap_MME_generate_messages.h | 8 +- .../M3AP/m3ap_MME_management_procedures.h | 6 +- openair3/MME_APP/enb_paramdef_mme.h | 4 + openair3/MME_APP/mme_config.h | 7 +- openair3/NAS/COMMON/API/NETWORK/as_message.h | 578 - openair3/NAS/COMMON/UTIL/socket.c | 2 +- openair3/NAS/COMMON/UTIL/socket.h | 6 +- openair3/NAS/COMMON/commonDef.h | 333 - openair3/NAS/COMMON/networkDef.h | 271 - openair3/NAS/TEST/USER/user_parser.h | 6 +- openair3/NAS/TOOLS/conf_network.c | 4 +- openair3/NAS/TOOLS/conf_parser.c | 2 +- openair3/TEST/oaisim_mme_test_s1c_s1ap.h | 5 + openair3/TEST/oaisim_mme_test_s1c_scenario.h | 5 + openair3/UTILS/mme_config.h | 8 +- openair3/UTILS/queue.h | 592 - openair3/UTILS/tree.h | 678 -- targets/ARCH/COMMON/common_lib.h | 42 +- targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h | 9 +- targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 274 +- targets/ARCH/rfsimulator/README.md | 33 +- targets/ARCH/rfsimulator/apply_channelmod.c | 23 +- targets/ARCH/rfsimulator/simulator.c | 52 +- targets/ARCH/rfsimulator/stored_node.c | 23 +- targets/COMMON/create_tasks.c | 5 +- targets/COMMON/create_tasks_mbms.h | 32 - .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 4 +- .../CONF/gnb.band78.tm1.273PRB.usrpn300.conf | 2 +- targets/RT/USER/gNB_usrp.gtkw | 22 +- targets/RT/USER/lte-enb.c | 14 +- targets/RT/USER/lte-ru.c | 32 +- targets/RT/USER/lte-softmodem.c | 77 +- targets/RT/USER/lte-softmodem.h | 4 +- targets/RT/USER/lte-ue.c | 149 +- targets/RT/USER/lte-uesoftmodem.c | 19 +- targets/RT/USER/rfsim.c | 4 +- 338 files changed, 11521 insertions(+), 28975 deletions(-) delete mode 100644 common/utils/itti_analyzer/common/queue.h delete mode 100644 openair1/PHY/TOOLS/lte_dfts.c delete mode 100644 openair2/LAYER2/MAC/defs.h delete mode 100644 openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h delete mode 100644 openair2/UTIL/MEM/mem_block.c delete mode 100644 openair2/UTIL/MEM/mem_mngt.c delete mode 100644 openair2/UTIL/MEM/mem_mngt_proto_extern.h delete mode 100644 openair2/UTIL/MEM/mem_pool.h delete mode 100644 openair3/NAS/COMMON/API/NETWORK/as_message.h delete mode 100644 openair3/NAS/COMMON/commonDef.h delete mode 100644 openair3/NAS/COMMON/networkDef.h delete mode 100644 openair3/UTILS/queue.h delete mode 100644 openair3/UTILS/tree.h delete mode 100644 targets/COMMON/create_tasks_mbms.h diff --git a/NOTICE.md b/NOTICE.md index 65c6105660..96b5d4c552 100644 --- a/NOTICE.md +++ b/NOTICE.md @@ -4,7 +4,7 @@ For more details of the license, refer to [LICENSE](LICENSE) file in the same di However, the source code also contains third party software that is acknowledged here for reference. -## Credits for LFDS user space source code located in folder openair2/UTILS/LFDS/liblfds6.1.1/ ## +## Credits for LFDS user space source code located in folder openair2/UTILS/LFDS/ ## See on [liblfds website](https://liblfds.org/) the license section. diff --git a/ci-scripts/.gitignore b/ci-scripts/.gitignore index d77a672c0c..dc5e7c7476 100644 --- a/ci-scripts/.gitignore +++ b/ci-scripts/.gitignore @@ -5,3 +5,5 @@ iperf_*.* phones_list.txt modules_list.txt test_results*.html +pMain* +__pycache__ diff --git a/ci-scripts/Jenkinsfile-inria-r2lab b/ci-scripts/Jenkinsfile-inria-r2lab index 3c4dddae8b..ada52277f4 100644 --- a/ci-scripts/Jenkinsfile-inria-r2lab +++ b/ci-scripts/Jenkinsfile-inria-r2lab @@ -62,6 +62,7 @@ def r2labUE0IpAddr = r2labBaseIpAddr + r2labUE0Idx def r2labENB1Idx = '16' def r2labENB1 = 'fit' + r2labENB1Idx def r2labENB1IpAddr = r2labBaseIpAddr + r2labENB1Idx +def r2labDoAllOff = true pipeline { agent { @@ -136,19 +137,49 @@ pipeline { sh "python3 /home/eurecom/inria-scripts/booking-lease.py --book-lease --from ${BOOK_TIMESTAMP}T${r2labStartTime} --duration ${r2labDuration} --slice inria_oaici ${r2labuser} ${r2labpassword}" sh "python3 /home/eurecom/inria-scripts/booking-lease.py --get-leases ${r2labuser} ${r2labpassword} | grep -v nightly" } + + // Adding a tempo after booking leases + sh "sleep 10" + LEASE_STATUS = sh returnStdout: true, script: "ssh -t inria_oaici@faraday.inria.fr 'rleases --check'" + LEASE_STATUS = LEASE_STATUS.trim() + if (LEASE_STATUS ==~ /.*Access currently denied to inria_oaici.*/) { + r2labDoAllOff = false + currentBuild.result = 'ABORTED' + error('Stopping early because R2LAB not available') + } } } } stage ("Load Images") { steps { script { + sh "ssh -t inria_oaici@faraday.inria.fr 'all-off'" + sh "sleep 10" + echo '\u2705 \u001B[32mLoad Image for Python Executor\u001B[0m' - sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labPythonExeIdx} > /dev/null 2>&1'" - sh "ssh -t inria_oaici@faraday.inria.fr 'rwait --silent ${r2labPythonExeIdx}'" + try { + sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labPythonExeIdx} > /dev/null 2>&1'" + } catch (Exception e) { + echo "Why is it wrong?" + } + try { + //sh "ssh -t inria_oaici@faraday.inria.fr 'rwait --silent ${r2labPythonExeIdx}'" + sh "ssh -t inria_oaici@faraday.inria.fr 'rwait ${r2labPythonExeIdx}'" + } catch (Exception e) { + echo "Why is it wrong?" + } echo '\u2705 \u001B[32mLoad Image for two (2) eNBs\u001B[0m' - sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labENB0Idx},${r2labENB1Idx} > /dev/null 2>&1'" - sh "ssh -t inria_oaici@faraday.inria.fr 'rwait --silent ${r2labENB0Idx},${r2labENB1Idx}'" + try { + sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labENB0Idx},${r2labENB1Idx} > /dev/null 2>&1'" + } catch (Exception e) { + echo "Why is it wrong?" + } + try { + sh "ssh -t inria_oaici@faraday.inria.fr 'rwait --silent ${r2labENB0Idx},${r2labENB1Idx}'" + } catch (Exception e) { + echo "Why is it wrong?" + } sh "ssh -t inria_oaici@faraday.inria.fr 'uon ${r2labENB0Idx},${r2labENB1Idx}'" sh "sleep 5" sh "ssh -t inria_oaici@faraday.inria.fr 'uon ${r2labENB0Idx},${r2labENB1Idx}'" @@ -415,9 +446,11 @@ pipeline { post { always { script { - echo '\u2705 \u001B[32mShutdown every node\u001B[0m' - sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"' - sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"' + if (r2labDoAllOff) { + echo '\u2705 \u001B[32mShutdown every node\u001B[0m' + sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"' + sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"' + } } } } diff --git a/ci-scripts/checkCodingFormattingRules.sh b/ci-scripts/checkCodingFormattingRules.sh index 6ac43ca19f..fb159d4da0 100755 --- a/ci-scripts/checkCodingFormattingRules.sh +++ b/ci-scripts/checkCodingFormattingRules.sh @@ -62,6 +62,30 @@ then NB_FILES_TO_FORMAT=`astyle --dry-run --options=ci-scripts/astyle-options.txt --recursive *.c *.h | grep -c Formatted ` echo "Nb Files that do NOT follow OAI rules: $NB_FILES_TO_FORMAT" echo $NB_FILES_TO_FORMAT > ./oai_rules_result.txt + + # Testing Circular Dependencies protection + awk '/#[ \t]*ifndef/ { gsub("^.*ifndef *",""); if (names[$1]!="") print "files with same {define ", FILENAME, names[$1]; names[$1]=FILENAME } /#[ \t]*define/ { gsub("^.*define *",""); if(names[$1]!=FILENAME) print "error in declaration", FILENAME, $1, names[$1]; nextfile }' `find openair* common targets executables -name *.h |grep -v LFDS` > header-files-w-incorrect-define.txt + + # Testing if explicit GNU GPL license banner + egrep -irl --exclude-dir=.git --include=*.cpp --include=*.c --include=*.h "General Public License" . > files-w-gnu-gpl-license-banner.txt + + # Looking at exotic/suspect banner + LIST_OF_FILES_W_BANNER=`egrep -irl --exclude-dir=.git --include=*.cpp --include=*.c --include=*.h "Copyright|copyleft" .` + if [ -f ./files-w-suspect-banner.txt ]; then rm -f ./files-w-suspect-banner.txt; fi + for FILE in $LIST_OF_FILES_W_BANNER + do + IS_NFAPI=`echo $FILE | egrep -c "nfapi/open-nFAPI|nfapi/oai_integration/vendor_ext"` + IS_OAI_LICENCE_PRESENT=`egrep -c "OAI Public License" $FILE` + IS_BSD_LICENCE_PRESENT=`egrep -c "the terms of the BSD Licence" $FILE` + IS_EXCEPTION=`echo $FILE | egrep -c "common/utils/collection/tree.h|common/utils/collection/queue.h|common/utils/itti_analyzer/common/queue.h|openair3/UTILS/tree.h|openair3/UTILS/queue.h"` + if [ $IS_OAI_LICENCE_PRESENT -eq 0 ] && [ $IS_BSD_LICENCE_PRESENT -eq 0 ] + then + if [ $IS_NFAPI -eq 0 ] && [ $IS_EXCEPTION -eq 0 ] + then + echo $FILE >> ./files-w-suspect-banner.txt + fi + fi + done exit 0 fi @@ -131,8 +155,25 @@ if [ -f oai_rules_result_list.txt ] then rm -f oai_rules_result_list.txt fi +if [ -f header-files-w-incorrect-define.txt ] +then + rm -f header-files-w-incorrect-define.txt +fi +if [ -f files-w-gnu-gpl-license-banner.txt ] +then + rm -f files-w-gnu-gpl-license-banner.txt +fi +if [ -f files-w-suspect-banner.txt ] +then + rm -f files-w-suspect-banner.txt +fi +awk '/#[ \t]*ifndef/ { gsub("^.*ifndef *",""); if (names[$1]!="") print "files with same {define ", FILENAME, names[$1]; names[$1]=FILENAME } /#[ \t]*define/ { gsub("^.*define *",""); if(names[$1]!=FILENAME) print "error in declaration", FILENAME, $1, names[$1]; nextfile }' `find openair* common targets executables -name *.h |grep -v LFDS` > header-files-w-incorrect-define-tmp.txt + for FULLFILE in $MODIFIED_FILES do + # sometimes, we remove files + if [ ! -f $FULLFILE ]; then continue; fi + filename=$(basename -- "$FULLFILE") EXT="${filename##*.}" if [ $EXT = "c" ] || [ $EXT = "h" ] || [ $EXT = "cpp" ] || [ $EXT = "hpp" ] @@ -144,8 +185,32 @@ do echo $FULLFILE echo $FULLFILE >> ./oai_rules_result_list.txt fi + # Testing if explicit GNU GPL license banner + egrep -i "General Public License" $FULLFILE >> files-w-gnu-gpl-license-banner.txt + # Looking at exotic/suspect banner + IS_BANNER=`egrep -i -c "Copyright|copyleft" $FULLFILE` + if [ $IS_BANNER -ne 0 ] + then + IS_NFAPI=`echo $FULLFILE | egrep -c "nfapi/open-nFAPI|nfapi/oai_integration/vendor_ext"` + IS_OAI_LICENCE_PRESENT=`egrep -c "OAI Public License" $FULLFILE` + IS_BSD_LICENCE_PRESENT=`egrep -c "the terms of the BSD Licence" $FULLFILE` + IS_EXCEPTION=`echo $FILE | egrep -c "common/utils/collection/tree.h|common/utils/collection/queue.h|common/utils/itti_analyzer/common/queue.h|openair3/UTILS/tree.h|openair3/UTILS/queue.h"` + if [ $IS_OAI_LICENCE_PRESENT -eq 0 ] && [ $IS_BSD_LICENCE_PRESENT -eq 0 ] + then + if [ $IS_NFAPI -eq 0 ] && [ $IS_EXCEPTION -eq 0 ] + then + echo $FILE >> ./files-w-suspect-banner.txt + fi + fi + fi + fi + # Testing Circular Dependencies protection + if [ $EXT = "h" ] || [ $EXT = "hpp" ] + then + grep $FULLFILE header-files-w-incorrect-define-tmp.txt >> header-files-w-incorrect-define.txt fi done +rm -f header-files-w-incorrect-define-tmp.txt echo "" echo " ----------------------------------------------------------" echo "Nb Files that do NOT follow OAI rules: $NB_TO_FORMAT" diff --git a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf index fbb8c5d6f8..de58950df4 100644 --- a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf +++ b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf @@ -288,7 +288,7 @@ MCEs = ( mnc_length = 2; } service_id=0; - lcid=8; #this must be properly defined lcid:8+service:0 -> rab_id:8 + lcid=5; #this must be properly defined lcid:8+service:0 -> rab_id:5 } ); } diff --git a/ci-scripts/cppcheck_suppressions.list b/ci-scripts/cppcheck_suppressions.list index 4536f57315..cad2aab88b 100644 --- a/ci-scripts/cppcheck_suppressions.list +++ b/ci-scripts/cppcheck_suppressions.list @@ -76,6 +76,11 @@ nullPointer:common/utils/T/local_tracer.c:243 // first iteration of the loop nullPointer:common/utils/T/tracer/multi.c:264 nullPointer:common/utils/T/tracer/multi.c:265 +//----------------------------------------------------------------------------- +// this file is used for testing the RLC V2 implementation, this error is +// not a problem, the programmer has to know what she does when writing +// the tests +arrayIndexOutOfBounds:openair2/LAYER2/rlc_v2/tests/test.c:401 // //***************************************************************************** // diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 21d51105f8..e9313051fc 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -1,4 +1,4 @@ -#/* + # * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more # * contributor license agreements. See the NOTICE file distributed with # * this work for additional information regarding copyright ownership. @@ -28,47 +28,7 @@ # pexpect #--------------------------------------------------------------------- -#----------------------------------------------------------- -# Version -#----------------------------------------------------------- -Version = '0.1' - -#----------------------------------------------------------- -# Constants -#----------------------------------------------------------- -ALL_PROCESSES_OK = 0 -ENB_PROCESS_FAILED = -1 -ENB_PROCESS_OK = +1 -ENB_PROCESS_SEG_FAULT = -11 -ENB_PROCESS_ASSERTION = -12 -ENB_PROCESS_REALTIME_ISSUE = -13 -ENB_PROCESS_NOLOGFILE_TO_ANALYZE = -14 -ENB_PROCESS_SLAVE_RRU_NOT_SYNCED = -15 -HSS_PROCESS_FAILED = -2 -HSS_PROCESS_OK = +2 -MME_PROCESS_FAILED = -3 -MME_PROCESS_OK = +3 -SPGW_PROCESS_FAILED = -4 -SPGW_PROCESS_OK = +4 -UE_IP_ADDRESS_ISSUE = -5 -OAI_UE_PROCESS_NOLOGFILE_TO_ANALYZE = -20 -OAI_UE_PROCESS_COULD_NOT_SYNC = -21 -OAI_UE_PROCESS_ASSERTION = -22 -OAI_UE_PROCESS_FAILED = -23 -OAI_UE_PROCESS_NO_TUNNEL_INTERFACE = -24 -OAI_UE_PROCESS_SEG_FAULT = -25 -OAI_UE_PROCESS_OK = +6 - -UE_STATUS_DETACHED = 0 -UE_STATUS_DETACHING = 1 -UE_STATUS_ATTACHING = 2 -UE_STATUS_ATTACHED = 3 - -X2_HO_REQ_STATE__IDLE = 0 -X2_HO_REQ_STATE__TARGET_RECEIVES_REQ = 1 -X2_HO_REQ_STATE__TARGET_RRC_RECFG_COMPLETE = 2 -X2_HO_REQ_STATE__TARGET_SENDS_SWITCH_REQ = 3 -X2_HO_REQ_STATE__SOURCE_RECEIVES_REQ_ACK = 10 +import constants as CONST #----------------------------------------------------------- # Import @@ -89,55 +49,27 @@ logging.basicConfig( format="[%(asctime)s] %(name)s:%(levelname)s: %(message)s" ) + #----------------------------------------------------------- # Class Declaration #----------------------------------------------------------- -class SSHConnection(): +class OaiCiTest(): + def __init__(self): - self.prematureExit = False self.ranRepository = '' self.ranBranch = '' - self.ranAllowMerge = False self.ranCommitID = '' + self.ranAllowMerge = False self.ranTargetBranch = '' - self.eNBIPAddress = '' - self.eNBUserName = '' - self.eNBPassword = '' - self.eNBSourceCodePath = '' - self.EPCIPAddress = '' - self.EPCUserName = '' - self.EPCPassword = '' - self.eNB1IPAddress = '' - self.eNB1UserName = '' - self.eNB1Password = '' - self.eNB1SourceCodePath = '' - self.eNB2IPAddress = '' - self.eNB2UserName = '' - self.eNB2Password = '' - self.eNB2SourceCodePath = '' - self.EPCSourceCodePath = '' - self.EPCType = '' - self.EPC_PcapFileName = '' + + self.FailReportCnt = 0 self.ADBIPAddress = '' self.ADBUserName = '' self.ADBPassword = '' self.ADBCentralized = True self.testCase_id = '' self.testXMLfiles = [] - self.nbTestXMLfiles = 0 self.desc = '' - self.Build_eNB_args = '' - self.backgroundBuild = False - self.backgroundBuildTestId = ['', '', ''] - self.Build_eNB_forced_workspace_cleanup = False - self.Initialize_eNB_args = '' - self.air_interface = 'lte' - self.eNB_instance = '' - self.eNB_serverId = '' - self.eNBLogFiles = ['', '', ''] - self.eNBOptions = ['', '', ''] - self.eNBmbmsEnables = [False, False, False] - self.eNBstatuses = [-1, -1, -1] self.ping_args = '' self.ping_packetloss_threshold = '' self.iperf_args = '' @@ -154,30 +86,13 @@ class SSHConnection(): self.UEDevicesRebootCmd = [] self.CatMDevices = [] self.UEIPAddresses = [] - self.htmlFile = '' - self.htmlHeaderCreated = False - self.htmlFooterCreated = False - self.htmlUEConnected = -1 - self.htmleNBFailureMsg = '' - self.htmlUEFailureMsg = '' - self.picocom_closure = False self.idle_sleep_time = 0 self.x2_ho_options = 'network' self.x2NbENBs = 0 self.x2ENBBsIds = [] self.x2ENBConnectedUEs = [] - self.htmlTabRefs = [] - self.htmlTabNames = [] - self.htmlTabIcons = [] self.repeatCounts = [] self.finalStatus = False - self.OsVersion = '' - self.KernelVersion = '' - self.UhdVersion = '' - self.UsrpBoard = '' - self.CpuNb = '' - self.CpuModel = '' - self.CpuMHz = '' self.UEIPAddress = '' self.UEUserName = '' self.UEPassword = '' @@ -187,819 +102,192 @@ class SSHConnection(): self.Build_OAI_UE_args = '' self.Initialize_OAI_UE_args = '' self.clean_repository = True - self.flexranCtrlInstalled = False - self.flexranCtrlStarted = False self.expectedNbOfConnectedUEs = 0 - self.startTime = 0 - - def open(self, ipaddress, username, password): - count = 0 - connect_status = False - while count < 4: - self.ssh = pexpect.spawn('ssh', [username + '@' + ipaddress], timeout = 5) - self.sshresponse = self.ssh.expect(['Are you sure you want to continue connecting (yes/no)?', 'password:', 'Last login', pexpect.EOF, pexpect.TIMEOUT]) - if self.sshresponse == 0: - self.ssh.sendline('yes') - self.ssh.expect('password:') - self.ssh.sendline(password) - self.sshresponse = self.ssh.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if self.sshresponse == 0: - count = 10 - connect_status = True - else: - logging.debug('self.sshresponse = ' + str(self.sshresponse)) - elif self.sshresponse == 1: - self.ssh.sendline(password) - self.sshresponse = self.ssh.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if self.sshresponse == 0: - count = 10 - connect_status = True - else: - logging.debug('self.sshresponse = ' + str(self.sshresponse)) - elif self.sshresponse == 2: - # Checking if we are really on the remote client defined by its IP address - self.command('stdbuf -o0 ifconfig | egrep --color=never "inet addr:|inet "', '\$', 5) - result = re.search(str(ipaddress), str(self.ssh.before)) - if result is None: - self.close() - else: - count = 10 - connect_status = True - else: - # debug output - logging.debug(str(self.ssh.before)) - logging.debug('self.sshresponse = ' + str(self.sshresponse)) - # adding a tempo when failure - if not connect_status: - time.sleep(1) - count += 1 - if connect_status: - pass - else: - sys.exit('SSH Connection Failed') - - def command(self, commandline, expectedline, timeout): - logging.debug(commandline) - self.ssh.timeout = timeout - self.ssh.sendline(commandline) - self.sshresponse = self.ssh.expect([expectedline, pexpect.EOF, pexpect.TIMEOUT]) - if self.sshresponse == 0: - return 0 - elif self.sshresponse == 1: - logging.debug('\u001B[1;37;41m Unexpected EOF \u001B[0m') - logging.debug('Expected Line : ' + expectedline) - logging.debug(str(self.ssh.before)) - sys.exit(self.sshresponse) - elif self.sshresponse == 2: - logging.debug('\u001B[1;37;41m Unexpected TIMEOUT \u001B[0m') - logging.debug('Expected Line : ' + expectedline) - result = re.search('ping |iperf |picocom', str(commandline)) - if result is None: - logging.debug(str(self.ssh.before)) - sys.exit(self.sshresponse) - else: - return -1 - else: - logging.debug('\u001B[1;37;41m Unexpected Others \u001B[0m') - logging.debug('Expected Line : ' + expectedline) - sys.exit(self.sshresponse) - - def close(self): - self.ssh.timeout = 5 - self.ssh.sendline('exit') - self.sshresponse = self.ssh.expect([pexpect.EOF, pexpect.TIMEOUT]) - if self.sshresponse == 0: - pass - elif self.sshresponse == 1: - if not self.picocom_closure: - logging.debug('\u001B[1;37;41m Unexpected TIMEOUT during closing\u001B[0m') - else: - logging.debug('\u001B[1;37;41m Unexpected Others during closing\u001B[0m') - - def copyin(self, ipaddress, username, password, source, destination): - count = 0 - copy_status = False - logging.debug('scp '+ username + '@' + ipaddress + ':' + source + ' ' + destination) - while count < 10: - scp_spawn = pexpect.spawn('scp '+ username + '@' + ipaddress + ':' + source + ' ' + destination, timeout = 100) - scp_response = scp_spawn.expect(['Are you sure you want to continue connecting (yes/no)?', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if scp_response == 0: - scp_spawn.sendline('yes') - scp_spawn.expect('password:') - scp_spawn.sendline(password) - scp_response = scp_spawn.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if scp_response == 0: - count = 10 - copy_status = True - else: - logging.debug('1 - scp_response = ' + str(scp_response)) - elif scp_response == 1: - scp_spawn.sendline(password) - scp_response = scp_spawn.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if scp_response == 0 or scp_response == 3: - count = 10 - copy_status = True - else: - logging.debug('2 - scp_response = ' + str(scp_response)) - elif scp_response == 2: - count = 10 - copy_status = True - else: - logging.debug('3 - scp_response = ' + str(scp_response)) - # adding a tempo when failure - if not copy_status: - time.sleep(1) - count += 1 - if copy_status: - return 0 - else: - return -1 - - def copyout(self, ipaddress, username, password, source, destination): - count = 0 - copy_status = False - logging.debug('scp ' + source + ' ' + username + '@' + ipaddress + ':' + destination) - while count < 4: - scp_spawn = pexpect.spawn('scp ' + source + ' ' + username + '@' + ipaddress + ':' + destination, timeout = 100) - scp_response = scp_spawn.expect(['Are you sure you want to continue connecting (yes/no)?', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if scp_response == 0: - scp_spawn.sendline('yes') - scp_spawn.expect('password:') - scp_spawn.sendline(password) - scp_response = scp_spawn.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if scp_response == 0: - count = 10 - copy_status = True - else: - logging.debug('1 - scp_response = ' + str(scp_response)) - elif scp_response == 1: - scp_spawn.sendline(password) - scp_response = scp_spawn.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT]) - if scp_response == 0 or scp_response == 3: - count = 10 - copy_status = True - else: - logging.debug('2 - scp_response = ' + str(scp_response)) - elif scp_response == 2: - count = 10 - copy_status = True - else: - logging.debug('3 - scp_response = ' + str(scp_response)) - # adding a tempo when failure - if not copy_status: - time.sleep(1) - count += 1 - if copy_status: - pass - else: - sys.exit('SCP failed') - - def BuildeNB(self): - if self.ranRepository == '' or self.ranBranch == '' or self.ranCommitID == '': - Usage() - sys.exit('Insufficient Parameter') - if self.eNB_serverId == '0': - lIpAddr = self.eNBIPAddress - lUserName = self.eNBUserName - lPassWord = self.eNBPassword - lSourcePath = self.eNBSourceCodePath - elif self.eNB_serverId == '1': - lIpAddr = self.eNB1IPAddress - lUserName = self.eNB1UserName - lPassWord = self.eNB1Password - lSourcePath = self.eNB1SourceCodePath - elif self.eNB_serverId == '2': - lIpAddr = self.eNB2IPAddress - lUserName = self.eNB2UserName - lPassWord = self.eNB2Password - lSourcePath = self.eNB2SourceCodePath - if lIpAddr == '' or lUserName == '' or lPassWord == '' or lSourcePath == '': - Usage() - sys.exit('Insufficient Parameter') - self.open(lIpAddr, lUserName, lPassWord) - result = re.search('--gNB', self.Build_eNB_args) - if result is not None: - self.air_interface = 'nr' - else: - self.air_interface = 'lte' - if self.Build_eNB_forced_workspace_cleanup: - self.command('echo ' + lPassWord + ' | sudo -S rm -Rf ' + lSourcePath, '\$', 15) - result = re.search('([a-zA-Z0-9\:\-\.\/])+\.git', self.ranRepository) - if result is not None: - full_ran_repo_name = self.ranRepository - else: - full_ran_repo_name = self.ranRepository + '.git' - self.command('mkdir -p ' + lSourcePath, '\$', 5) - self.command('cd ' + lSourcePath, '\$', 5) - self.command('if [ ! -e .git ]; then stdbuf -o0 git clone ' + full_ran_repo_name + ' .; else stdbuf -o0 git fetch --prune; fi', '\$', 600) - # Raphael: here add a check if git clone or git fetch went smoothly - self.command('git config user.email "jenkins@openairinterface.org"', '\$', 5) - self.command('git config user.name "OAI Jenkins"', '\$', 5) - # Checking the BUILD INFO file - if not self.backgroundBuild: - self.command('ls *.txt', '\$', 5) - result = re.search('LAST_BUILD_INFO', str(self.ssh.before)) - if result is not None: - mismatch = False - self.command('grep SRC_COMMIT LAST_BUILD_INFO.txt', '\$', 2) - result = re.search(self.ranCommitID, str(self.ssh.before)) - if result is None: - mismatch = True - self.command('grep MERGED_W_TGT_BRANCH LAST_BUILD_INFO.txt', '\$', 2) - if (self.ranAllowMerge): - result = re.search('YES', str(self.ssh.before)) - if result is None: - mismatch = True - self.command('grep TGT_BRANCH LAST_BUILD_INFO.txt', '\$', 2) - if self.ranTargetBranch == '': - result = re.search('develop', str(self.ssh.before)) - else: - result = re.search(self.ranTargetBranch, str(self.ssh.before)) - if result is None: - mismatch = True - else: - result = re.search('NO', str(self.ssh.before)) - if result is None: - mismatch = True - if not mismatch: - self.close() - self.CreateHtmlTestRow(self.Build_eNB_args, 'OK', ALL_PROCESSES_OK) - return - - self.command('echo ' + lPassWord + ' | sudo -S git clean -x -d -ff', '\$', 30) - # if the commit ID is provided use it to point to it - if self.ranCommitID != '': - self.command('git checkout -f ' + self.ranCommitID, '\$', 5) - # if the branch is not develop, then it is a merge request and we need to do - # the potential merge. Note that merge conflicts should already been checked earlier - if (self.ranAllowMerge): - if self.ranTargetBranch == '': - if (self.ranBranch != 'develop') and (self.ranBranch != 'origin/develop'): - self.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5) - else: - logging.debug('Merging with the target branch: ' + self.ranTargetBranch) - self.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5) - self.command('source oaienv', '\$', 5) - self.command('cd cmake_targets', '\$', 5) - self.command('mkdir -p log', '\$', 5) - self.command('chmod 777 log', '\$', 5) - # no need to remove in log (git clean did the trick) - if self.backgroundBuild: - self.command('echo "./build_oai ' + self.Build_eNB_args + '" > ./my-lte-softmodem-build.sh', '\$', 5) - self.command('chmod 775 ./my-lte-softmodem-build.sh', '\$', 5) - self.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=build_enb_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ./my-lte-softmodem-build.sh', '\$', 5) - self.close() - self.CreateHtmlTestRow(self.Build_eNB_args, 'OK', ALL_PROCESSES_OK) - self.backgroundBuildTestId[int(self.eNB_instance)] = self.testCase_id - return - self.command('stdbuf -o0 ./build_oai ' + self.Build_eNB_args + ' 2>&1 | stdbuf -o0 tee compile_oai_enb.log', 'Bypassing the Tests|build have failed', 1500) - self.checkBuildeNB(lIpAddr, lUserName, lPassWord, lSourcePath, self.testCase_id) - - def WaitBuildeNBisFinished(self): - if self.eNB_serverId == '0': - lIpAddr = self.eNBIPAddress - lUserName = self.eNBUserName - lPassWord = self.eNBPassword - lSourcePath = self.eNBSourceCodePath - elif self.eNB_serverId == '1': - lIpAddr = self.eNB1IPAddress - lUserName = self.eNB1UserName - lPassWord = self.eNB1Password - lSourcePath = self.eNB1SourceCodePath - elif self.eNB_serverId == '2': - lIpAddr = self.eNB2IPAddress - lUserName = self.eNB2UserName - lPassWord = self.eNB2Password - lSourcePath = self.eNB2SourceCodePath - if lIpAddr == '' or lUserName == '' or lPassWord == '' or lSourcePath == '': - Usage() - sys.exit('Insufficient Parameter') - self.open(lIpAddr, lUserName, lPassWord) - count = 40 - buildOAIprocess = True - while (count > 0) and buildOAIprocess: - self.command('ps aux | grep --color=never build_ | grep -v grep', '\$', 3) - result = re.search('build_oai', str(self.ssh.before)) - if result is None: - buildOAIprocess = False - else: - count -= 1 - time.sleep(30) - self.checkBuildeNB(lIpAddr, lUserName, lPassWord, lSourcePath, self.backgroundBuildTestId[int(self.eNB_instance)]) - - def checkBuildeNB(self, lIpAddr, lUserName, lPassWord, lSourcePath, testcaseId): - self.command('cd ' + lSourcePath + '/cmake_targets', '\$', 3) - self.command('ls ran_build/build', '\$', 3) - self.command('ls ran_build/build', '\$', 3) - if self.air_interface == 'nr': - nodeB_prefix = 'g' - else: - nodeB_prefix = 'e' - buildStatus = True - result = re.search(self.air_interface + '-softmodem', str(self.ssh.before)) - if result is None: - buildStatus = False - else: - # Generating a BUILD INFO file - self.command('echo "SRC_BRANCH: ' + self.ranBranch + '" > ../LAST_BUILD_INFO.txt', '\$', 2) - self.command('echo "SRC_COMMIT: ' + self.ranCommitID + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) - if (self.ranAllowMerge): - self.command('echo "MERGED_W_TGT_BRANCH: YES" >> ../LAST_BUILD_INFO.txt', '\$', 2) - if self.ranTargetBranch == '': - self.command('echo "TGT_BRANCH: develop" >> ../LAST_BUILD_INFO.txt', '\$', 2) - else: - self.command('echo "TGT_BRANCH: ' + self.ranTargetBranch + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) - else: - self.command('echo "MERGED_W_TGT_BRANCH: NO" >> ../LAST_BUILD_INFO.txt', '\$', 2) - self.command('mkdir -p build_log_' + testcaseId, '\$', 5) - self.command('mv log/* ' + 'build_log_' + testcaseId, '\$', 5) - self.command('mv compile_oai_enb.log ' + 'build_log_' + testcaseId, '\$', 5) - if self.eNB_serverId != '0': - self.command('cd cmake_targets', '\$', 5) - self.command('if [ -e tmp_build' + testcaseId + '.zip ]; then rm -f tmp_build' + testcaseId + '.zip; fi', '\$', 5) - self.command('zip -r -qq tmp_build' + testcaseId + '.zip build_log_' + testcaseId, '\$', 5) - self.close() - if (os.path.isfile('./tmp_build' + testcaseId + '.zip')): - os.remove('./tmp_build' + testcaseId + '.zip') - self.copyin(lIpAddr, lUserName, lPassWord, lSourcePath + '/cmake_targets/tmp_build' + testcaseId + '.zip', '.') - if (os.path.isfile('./tmp_build' + testcaseId + '.zip')): - self.copyout(self.eNBIPAddress, self.eNBUserName, self.eNBPassword, './tmp_build' + testcaseId + '.zip', self.eNBSourceCodePath + '/cmake_targets/.') - os.remove('./tmp_build' + testcaseId + '.zip') - self.open(self.eNBIPAddress, self.eNBUserName, self.eNBPassword) - self.command('cd ' + self.eNBSourceCodePath + '/cmake_targets', '\$', 5) - self.command('unzip -qq -DD tmp_build' + testcaseId + '.zip', '\$', 5) - self.command('rm -f tmp_build' + testcaseId + '.zip', '\$', 5) - self.close() - else: - self.close() - - if buildStatus: - logging.info('\u001B[1m Building OAI ' + nodeB_prefix + 'NB Pass\u001B[0m') - self.CreateHtmlTestRow(self.Build_eNB_args, 'OK', ALL_PROCESSES_OK) - else: - logging.error('\u001B[1m Building OAI ' + nodeB_prefix + 'NB Failed\u001B[0m') - self.CreateHtmlTestRow(self.Build_eNB_args, 'KO', ALL_PROCESSES_OK) - self.CreateHtmlTabFooter(False) - sys.exit(1) def BuildOAIUE(self): if self.UEIPAddress == '' or self.ranRepository == '' or self.ranBranch == '' or self.UEUserName == '' or self.UEPassword == '' or self.UESourceCodePath == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) result = re.search('--nrUE', self.Build_OAI_UE_args) if result is not None: - self.air_interface = 'nr' + RAN.Setair_interface('nr') ue_prefix = 'NR ' else: - self.air_interface = 'lte' + RAN.Setair_interface('lte') ue_prefix = '' result = re.search('([a-zA-Z0-9\:\-\.\/])+\.git', self.ranRepository) if result is not None: full_ran_repo_name = self.ranRepository else: full_ran_repo_name = self.ranRepository + '.git' - self.command('mkdir -p ' + self.UESourceCodePath, '\$', 5) - self.command('cd ' + self.UESourceCodePath, '\$', 5) - self.command('if [ ! -e .git ]; then stdbuf -o0 git clone ' + full_ran_repo_name + ' .; else stdbuf -o0 git fetch --prune; fi', '\$', 600) + SSH.command('mkdir -p ' + self.UESourceCodePath, '\$', 5) + SSH.command('cd ' + self.UESourceCodePath, '\$', 5) + SSH.command('if [ ! -e .git ]; then stdbuf -o0 git clone ' + full_ran_repo_name + ' .; else stdbuf -o0 git fetch --prune; fi', '\$', 600) # here add a check if git clone or git fetch went smoothly - self.command('git config user.email "jenkins@openairinterface.org"', '\$', 5) - self.command('git config user.name "OAI Jenkins"', '\$', 5) + SSH.command('git config user.email "jenkins@openairinterface.org"', '\$', 5) + SSH.command('git config user.name "OAI Jenkins"', '\$', 5) if self.clean_repository: - self.command('ls *.txt', '\$', 5) - result = re.search('LAST_BUILD_INFO', str(self.ssh.before)) + SSH.command('ls *.txt', '\$', 5) + result = re.search('LAST_BUILD_INFO', SSH.getBefore()) if result is not None: mismatch = False - self.command('grep SRC_COMMIT LAST_BUILD_INFO.txt', '\$', 2) - result = re.search(self.ranCommitID, str(self.ssh.before)) + SSH.command('grep SRC_COMMIT LAST_BUILD_INFO.txt', '\$', 2) + result = re.search(self.ranCommitID, SSH.getBefore()) if result is None: mismatch = True - self.command('grep MERGED_W_TGT_BRANCH LAST_BUILD_INFO.txt', '\$', 2) - if (self.ranAllowMerge): - result = re.search('YES', str(self.ssh.before)) + SSH.command('grep MERGED_W_TGT_BRANCH LAST_BUILD_INFO.txt', '\$', 2) + if self.ranAllowMerge: + result = re.search('YES', SSH.getBefore()) if result is None: mismatch = True - self.command('grep TGT_BRANCH LAST_BUILD_INFO.txt', '\$', 2) + SSH.command('grep TGT_BRANCH LAST_BUILD_INFO.txt', '\$', 2) if self.ranTargetBranch == '': - result = re.search('develop', str(self.ssh.before)) + result = re.search('develop', SSH.getBefore()) else: - result = re.search(self.ranTargetBranch, str(self.ssh.before)) + result = re.search(self.ranTargetBranch, SSH.getBefore()) if result is None: mismatch = True else: - result = re.search('NO', str(self.ssh.before)) + result = re.search('NO', SSH.getBefore()) if result is None: mismatch = True if not mismatch: - self.close() - self.CreateHtmlTestRow(self.Build_eNB_args, 'OK', ALL_PROCESSES_OK) + SSH.close() + HTML.CreateHtmlTestRow(RAN.GetBuild_eNB_args(), 'OK', CONST.ALL_PROCESSES_OK) return - self.command('echo ' + self.UEPassword + ' | sudo -S git clean -x -d -ff', '\$', 30) + SSH.command('echo ' + self.UEPassword + ' | sudo -S git clean -x -d -ff', '\$', 30) # if the commit ID is provided use it to point to it if self.ranCommitID != '': - self.command('git checkout -f ' + self.ranCommitID, '\$', 5) + SSH.command('git checkout -f ' + self.ranCommitID, '\$', 5) # if the branch is not develop, then it is a merge request and we need to do # the potential merge. Note that merge conflicts should already been checked earlier - if (self.ranAllowMerge): + if self.ranAllowMerge: if self.ranTargetBranch == '': if (self.ranBranch != 'develop') and (self.ranBranch != 'origin/develop'): - self.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5) + SSH.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5) else: logging.debug('Merging with the target branch: ' + self.ranTargetBranch) - self.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5) - self.command('source oaienv', '\$', 5) - self.command('cd cmake_targets', '\$', 5) - self.command('mkdir -p log', '\$', 5) - self.command('chmod 777 log', '\$', 5) + SSH.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5) + SSH.command('source oaienv', '\$', 5) + SSH.command('cd cmake_targets', '\$', 5) + SSH.command('mkdir -p log', '\$', 5) + SSH.command('chmod 777 log', '\$', 5) # no need to remove in log (git clean did the trick) - self.command('stdbuf -o0 ./build_oai ' + self.Build_OAI_UE_args + ' 2>&1 | stdbuf -o0 tee compile_oai_ue.log', 'Bypassing the Tests|build have failed', 600) - self.command('ls ran_build/build', '\$', 3) - self.command('ls ran_build/build', '\$', 3) + SSH.command('stdbuf -o0 ./build_oai ' + self.Build_OAI_UE_args + ' 2>&1 | stdbuf -o0 tee compile_oai_ue.log', 'Bypassing the Tests|build have failed', 900) + SSH.command('ls ran_build/build', '\$', 3) + SSH.command('ls ran_build/build', '\$', 3) buildStatus = True - result = re.search(self.air_interface + '-uesoftmodem', str(self.ssh.before)) + result = re.search(RAN.Getair_interface() + '-uesoftmodem', SSH.getBefore()) if result is None: buildStatus = False - self.command('mkdir -p build_log_' + self.testCase_id, '\$', 5) - self.command('mv log/* ' + 'build_log_' + self.testCase_id, '\$', 5) - self.command('mv compile_oai_ue.log ' + 'build_log_' + self.testCase_id, '\$', 5) + SSH.command('mkdir -p build_log_' + self.testCase_id, '\$', 5) + SSH.command('mv log/* ' + 'build_log_' + self.testCase_id, '\$', 5) + SSH.command('mv compile_oai_ue.log ' + 'build_log_' + self.testCase_id, '\$', 5) if buildStatus: # Generating a BUILD INFO file - self.command('echo "SRC_BRANCH: ' + self.ranBranch + '" > ../LAST_BUILD_INFO.txt', '\$', 2) - self.command('echo "SRC_COMMIT: ' + self.ranCommitID + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) - if (self.ranAllowMerge): - self.command('echo "MERGED_W_TGT_BRANCH: YES" >> ../LAST_BUILD_INFO.txt', '\$', 2) + SSH.command('echo "SRC_BRANCH: ' + self.ranBranch + '" > ../LAST_BUILD_INFO.txt', '\$', 2) + SSH.command('echo "SRC_COMMIT: ' + self.ranCommitID + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) + if self.ranAllowMerge: + SSH.command('echo "MERGED_W_TGT_BRANCH: YES" >> ../LAST_BUILD_INFO.txt', '\$', 2) if self.ranTargetBranch == '': - self.command('echo "TGT_BRANCH: develop" >> ../LAST_BUILD_INFO.txt', '\$', 2) + SSH.command('echo "TGT_BRANCH: develop" >> ../LAST_BUILD_INFO.txt', '\$', 2) else: - self.command('echo "TGT_BRANCH: ' + self.ranTargetBranch + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) + SSH.command('echo "TGT_BRANCH: ' + self.ranTargetBranch + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) else: - self.command('echo "MERGED_W_TGT_BRANCH: NO" >> ../LAST_BUILD_INFO.txt', '\$', 2) - self.close() - self.CreateHtmlTestRow(self.Build_OAI_UE_args, 'OK', ALL_PROCESSES_OK, 'OAI UE') + SSH.command('echo "MERGED_W_TGT_BRANCH: NO" >> ../LAST_BUILD_INFO.txt', '\$', 2) + SSH.close() + HTML.CreateHtmlTestRow(self.Build_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK, 'OAI UE') else: - self.close() + SSH.close() logging.error('\u001B[1m Building OAI UE Failed\u001B[0m') - self.CreateHtmlTestRow(self.Build_OAI_UE_args, 'KO', ALL_PROCESSES_OK, 'OAI UE') - self.CreateHtmlTabFooter(False) + HTML.CreateHtmlTestRow(self.Build_OAI_UE_args, 'KO', CONST.ALL_PROCESSES_OK, 'OAI UE') + HTML.CreateHtmlTabFooter(False) sys.exit(1) - - def InitializeHSS(self): - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '' or self.EPCSourceCodePath == '' or self.EPCType == '': - Usage() - sys.exit('Insufficient Parameter') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - logging.debug('Using the OAI EPC Release 14 Cassandra-based HSS') - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - logging.debug('\u001B[1m Launching tshark on all interfaces \u001B[0m') - EPC_PcapFileName = 'epc_' + self.testCase_id + '.pcap' - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f ' + EPC_PcapFileName, '\$', 5) - self.command('echo $USER; nohup sudo tshark -f "tcp port not 22 and port not 53" -i any -w ' + self.EPCSourceCodePath + '/scripts/' + EPC_PcapFileName + ' > /tmp/tshark.log 2>&1 &', self.EPCUserName, 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S mkdir -p logs', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f hss_' + self.testCase_id + '.log logs/hss*.*', '\$', 5) - self.command('echo "oai_hss -j /usr/local/etc/oai/hss_rel14.json" > ./my-hss.sh', '\$', 5) - self.command('chmod 755 ./my-hss.sh', '\$', 5) - self.command('sudo daemon --unsafe --name=hss_daemon --chdir=' + self.EPCSourceCodePath + '/scripts -o ' + self.EPCSourceCodePath + '/scripts/hss_' + self.testCase_id + '.log ./my-hss.sh', '\$', 5) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - logging.debug('Using the OAI EPC HSS') - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('source oaienv', '\$', 5) - self.command('cd scripts', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S ./run_hss 2>&1 | stdbuf -o0 awk \'{ print strftime("[%Y/%m/%d %H:%M:%S] ",systime()) $0 }\' | stdbuf -o0 tee -a hss_' + self.testCase_id + '.log &', 'Core state: 2 -> 3', 35) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - logging.debug('Using the ltebox simulated HSS') - self.command('if [ -d ' + self.EPCSourceCodePath + '/scripts ]; then echo ' + self.eNBPassword + ' | sudo -S rm -Rf ' + self.EPCSourceCodePath + '/scripts ; fi', '\$', 5) - self.command('mkdir -p ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('cd /opt/hss_sim0609', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f hss.log daemon.log', '\$', 5) - # based on Robert's feedback, new method to run simulated HSS - self.command('sudo su -c "cd /opt/hss_sim0609 && screen -dm -S simulated_hss ./starthss_real"', '\$', 5) - else: - logging.error('This option should not occur!') - self.close() - self.CreateHtmlTestRow(self.EPCType, 'OK', ALL_PROCESSES_OK) - - def InitializeMME(self): - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '' or self.EPCSourceCodePath == '' or self.EPCType == '': - Usage() - sys.exit('Insufficient Parameter') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - logging.debug('Using the OAI EPC Release 14 MME') - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f mme_' + self.testCase_id + '.log', '\$', 5) - self.command('echo "./run_mme --config-file /usr/local/etc/oai/mme.conf --set-virt-if" > ./my-mme.sh', '\$', 5) - self.command('chmod 755 ./my-mme.sh', '\$', 5) - self.command('sudo daemon --unsafe --name=mme_daemon --chdir=' + self.EPCSourceCodePath + '/scripts -o ' + self.EPCSourceCodePath + '/scripts/mme_' + self.testCase_id + '.log ./my-mme.sh', '\$', 5) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('source oaienv', '\$', 5) - self.command('cd scripts', '\$', 5) - self.command('stdbuf -o0 hostname', '\$', 5) - result = re.search('hostname\\\\r\\\\n(?P[a-zA-Z0-9\-\_]+)\\\\r\\\\n', str(self.ssh.before)) - if result is None: - logging.debug('\u001B[1;37;41m Hostname Not Found! \u001B[0m') - sys.exit(1) - host_name = result.group('host_name') - self.command('echo ' + self.EPCPassword + ' | sudo -S ./run_mme 2>&1 | stdbuf -o0 tee -a mme_' + self.testCase_id + '.log &', 'MME app initialization complete', 100) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cd /opt/ltebox/tools', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S ./start_mme', '\$', 5) - else: - logging.error('This option should not occur!') - self.close() - self.CreateHtmlTestRow(self.EPCType, 'OK', ALL_PROCESSES_OK) - - def InitializeSPGW(self): - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '' or self.EPCSourceCodePath == '' or self.EPCType == '': - Usage() - sys.exit('Insufficient Parameter') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - logging.debug('Using the OAI EPC Release 14 SPGW-CUPS') - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f spgwc_' + self.testCase_id + '.log spgwu_' + self.testCase_id + '.log', '\$', 5) - self.command('echo "spgwc -c /usr/local/etc/oai/spgw_c.conf" > ./my-spgwc.sh', '\$', 5) - self.command('chmod 755 ./my-spgwc.sh', '\$', 5) - self.command('sudo daemon --unsafe --name=spgwc_daemon --chdir=' + self.EPCSourceCodePath + '/scripts -o ' + self.EPCSourceCodePath + '/scripts/spgwc_' + self.testCase_id + '.log ./my-spgwc.sh', '\$', 5) - time.sleep(5) - self.command('echo "spgwu -c /usr/local/etc/oai/spgw_u.conf" > ./my-spgwu.sh', '\$', 5) - self.command('chmod 755 ./my-spgwu.sh', '\$', 5) - self.command('sudo daemon --unsafe --name=spgwu_daemon --chdir=' + self.EPCSourceCodePath + '/scripts -o ' + self.EPCSourceCodePath + '/scripts/spgwu_' + self.testCase_id + '.log ./my-spgwu.sh', '\$', 5) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('source oaienv', '\$', 5) - self.command('cd scripts', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S ./run_spgw 2>&1 | stdbuf -o0 tee -a spgw_' + self.testCase_id + '.log &', 'Initializing SPGW-APP task interface: DONE', 30) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cd /opt/ltebox/tools', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S ./start_xGw', '\$', 5) - else: - logging.error('This option should not occur!') - self.close() - self.CreateHtmlTestRow(self.EPCType, 'OK', ALL_PROCESSES_OK) - + def CheckFlexranCtrlInstallation(self): - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '': + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': return - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('ls -ls /opt/flexran_rtc/*/rt_controller', '\$', 5) - result = re.search('/opt/flexran_rtc/build/rt_controller', str(self.ssh.before)) + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('ls -ls /opt/flexran_rtc/*/rt_controller', '\$', 5) + result = re.search('/opt/flexran_rtc/build/rt_controller', SSH.getBefore()) if result is not None: - self.flexranCtrlInstalled = True + RAN.SetflexranCtrlInstalled(True) logging.debug('Flexran Controller is installed') - self.close() + SSH.close() def InitializeFlexranCtrl(self): - if self.flexranCtrlInstalled == False: + if RAN.GetflexranCtrlInstalled() == False: return - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd /opt/flexran_rtc', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f log/*.log', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S echo "build/rt_controller -c log_config/basic_log" > ./my-flexran-ctl.sh', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S chmod 755 ./my-flexran-ctl.sh', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S daemon --unsafe --name=flexran_rtc_daemon --chdir=/opt/flexran_rtc -o /opt/flexran_rtc/log/flexranctl_' + self.testCase_id + '.log ././my-flexran-ctl.sh', '\$', 5) - self.command('ps -aux | grep --color=never rt_controller', '\$', 5) - result = re.search('rt_controller -c ', str(self.ssh.before)) + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd /opt/flexran_rtc', '\$', 5) + SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S rm -f log/*.log', '\$', 5) + SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S echo "build/rt_controller -c log_config/basic_log" > ./my-flexran-ctl.sh', '\$', 5) + SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S chmod 755 ./my-flexran-ctl.sh', '\$', 5) + SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S daemon --unsafe --name=flexran_rtc_daemon --chdir=/opt/flexran_rtc -o /opt/flexran_rtc/log/flexranctl_' + self.testCase_id + '.log ././my-flexran-ctl.sh', '\$', 5) + SSH.command('ps -aux | grep --color=never rt_controller', '\$', 5) + result = re.search('rt_controller -c ', SSH.getBefore()) if result is not None: logging.debug('\u001B[1m Initialize FlexRan Controller Completed\u001B[0m') - self.flexranCtrlStarted = True - self.close() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - - def InitializeeNB(self): - if self.eNB_serverId == '0': - lIpAddr = self.eNBIPAddress - lUserName = self.eNBUserName - lPassWord = self.eNBPassword - lSourcePath = self.eNBSourceCodePath - elif self.eNB_serverId == '1': - lIpAddr = self.eNB1IPAddress - lUserName = self.eNB1UserName - lPassWord = self.eNB1Password - lSourcePath = self.eNB1SourceCodePath - elif self.eNB_serverId == '2': - lIpAddr = self.eNB2IPAddress - lUserName = self.eNB2UserName - lPassWord = self.eNB2Password - lSourcePath = self.eNB2SourceCodePath - if lIpAddr == '' or lUserName == '' or lPassWord == '' or lSourcePath == '': - Usage() - sys.exit('Insufficient Parameter') - check_eNB = False - check_OAI_UE = False - pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) - if (pStatus < 0): - self.CreateHtmlTestRow(self.Initialize_eNB_args, 'KO', pStatus) - self.CreateHtmlTabFooter(False) - sys.exit(1) - # If tracer options is on, running tshark on EPC side and capture traffic b/ EPC and eNB - result = re.search('T_stdout', str(self.Initialize_eNB_args)) - if result is not None: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('ip addr show | awk -f /tmp/active_net_interfaces.awk | egrep -v "lo|tun"', '\$', 5) - result = re.search('interfaceToUse=(?P[a-zA-Z0-9\-\_]+)done', str(self.ssh.before)) - if result is not None: - eth_interface = result.group('eth_interface') - logging.debug('\u001B[1m Launching tshark on interface ' + eth_interface + '\u001B[0m') - self.EPC_PcapFileName = 'enb_' + self.testCase_id + '_s1log.pcap' - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f /tmp/' + self.EPC_PcapFileName, '\$', 5) - self.command('echo $USER; nohup sudo tshark -f "host ' + lIpAddr +'" -i ' + eth_interface + ' -w /tmp/' + self.EPC_PcapFileName + ' > /tmp/tshark.log 2>&1 &', self.EPCUserName, 5) - self.close() - self.open(lIpAddr, lUserName, lPassWord) - self.command('cd ' + lSourcePath, '\$', 5) - # Initialize_eNB_args usually start with -O and followed by the location in repository - full_config_file = self.Initialize_eNB_args.replace('-O ','') - extra_options = '' - extIdx = full_config_file.find('.conf') - if (extIdx > 0): - extra_options = full_config_file[extIdx + 5:] - # if tracer options is on, compiling and running T Tracer - result = re.search('T_stdout', str(extra_options)) - if result is not None: - logging.debug('\u001B[1m Compiling and launching T Tracer\u001B[0m') - self.command('cd common/utils/T/tracer', '\$', 5) - self.command('make', '\$', 10) - self.command('echo $USER; nohup ./record -d ../T_messages.txt -o ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '_record.raw -ON -off VCD -off HEAVY -off LEGACY_GROUP_TRACE -off LEGACY_GROUP_DEBUG > ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '_record.log 2>&1 &', lUserName, 5) - self.command('cd ' + lSourcePath, '\$', 5) - full_config_file = full_config_file[:extIdx + 5] - config_path, config_file = os.path.split(full_config_file) - else: - sys.exit('Insufficient Parameter') - ci_full_config_file = config_path + '/ci-' + config_file - rruCheck = False - result = re.search('^rru|^rcc|^du.band', str(config_file)) - if result is not None: - rruCheck = True - # do not reset board twice in IF4.5 case - result = re.search('^rru|^enb|^du.band', str(config_file)) - if result is not None: - self.command('echo ' + lPassWord + ' | sudo -S uhd_find_devices', '\$', 60) - result = re.search('type: b200', str(self.ssh.before)) - if result is not None: - logging.debug('Found a B2xx device --> resetting it') - self.command('echo ' + lPassWord + ' | sudo -S b2xx_fx3_utils --reset-device', '\$', 10) - # Reloading FGPA bin firmware - self.command('echo ' + lPassWord + ' | sudo -S uhd_find_devices', '\$', 60) - # Make a copy and adapt to EPC / eNB IP addresses - self.command('cp ' + full_config_file + ' ' + ci_full_config_file, '\$', 5) - self.command('sed -i -e \'s/CI_MME_IP_ADDR/' + self.EPCIPAddress + '/\' ' + ci_full_config_file, '\$', 2); - self.command('sed -i -e \'s/CI_ENB_IP_ADDR/' + lIpAddr + '/\' ' + ci_full_config_file, '\$', 2); - self.command('sed -i -e \'s/CI_RCC_IP_ADDR/' + self.eNBIPAddress + '/\' ' + ci_full_config_file, '\$', 2); - self.command('sed -i -e \'s/CI_RRU1_IP_ADDR/' + self.eNB1IPAddress + '/\' ' + ci_full_config_file, '\$', 2); - self.command('sed -i -e \'s/CI_RRU2_IP_ADDR/' + self.eNB2IPAddress + '/\' ' + ci_full_config_file, '\$', 2); - if self.flexranCtrlInstalled and self.flexranCtrlStarted: - self.command('sed -i -e \'s/FLEXRAN_ENABLED.*;/FLEXRAN_ENABLED = "yes";/\' ' + ci_full_config_file, '\$', 2); - else: - self.command('sed -i -e \'s/FLEXRAN_ENABLED.*;/FLEXRAN_ENABLED = "no";/\' ' + ci_full_config_file, '\$', 2); - self.eNBmbmsEnables[int(self.eNB_instance)] = False - self.command('grep enable_enb_m2 ' + ci_full_config_file, '\$', 2); - result = re.search('yes', str(self.ssh.before)) - if result is not None: - self.eNBmbmsEnables[int(self.eNB_instance)] = True - logging.debug('\u001B[1m MBMS is enabled on this eNB\u001B[0m') - result = re.search('noS1', str(self.Initialize_eNB_args)) - eNBinNoS1 = False - if result is not None: - eNBinNoS1 = True - logging.debug('\u001B[1m eNB is in noS1 configuration \u001B[0m') - # Launch eNB with the modified config file - self.command('source oaienv', '\$', 5) - self.command('cd cmake_targets', '\$', 5) - self.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) - self.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) - self.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) - self.command('hostnamectl','\$', 5) - result = re.search('CentOS Linux 7', str(self.ssh.before)) - if result is not None: - self.command('echo $USER; nohup sudo ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh > ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log 2>&1 &', lUserName, 10) - else: - self.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=enb' + str(self.eNB_instance) + '_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) - self.eNBLogFiles[int(self.eNB_instance)] = 'enb_' + self.testCase_id + '.log' - if extra_options != '': - self.eNBOptions[int(self.eNB_instance)] = extra_options - time.sleep(6) - doLoop = True - loopCounter = 20 - enbDidSync = False - while (doLoop): - loopCounter = loopCounter - 1 - if (loopCounter == 0): - # In case of T tracer recording, we may need to kill it - result = re.search('T_stdout', str(self.Initialize_eNB_args)) - if result is not None: - self.command('killall --signal SIGKILL record', '\$', 5) - self.close() - doLoop = False - logging.error('\u001B[1;37;41m eNB logging system did not show got sync! \u001B[0m') - self.CreateHtmlTestRow('-O ' + config_file + extra_options, 'KO', ALL_PROCESSES_OK) - # In case of T tracer recording, we need to kill tshark on EPC side - result = re.search('T_stdout', str(self.Initialize_eNB_args)) - if result is not None: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - logging.debug('\u001B[1m Stopping tshark \u001B[0m') - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL tshark', '\$', 5) - if self.EPC_PcapFileName != '': - time.sleep(0.5) - self.command('echo ' + self.EPCPassword + ' | sudo -S chmod 666 /tmp/' + self.EPC_PcapFileName, '\$', 5) - self.close() - time.sleep(1) - if self.EPC_PcapFileName != '': - copyin_res = self.copyin(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, '/tmp/' + self.EPC_PcapFileName, '.') - if (copyin_res == 0): - self.copyout(lIpAddr, lUserName, lPassWord, self.EPC_PcapFileName, lSourcePath + '/cmake_targets/.') - self.prematureExit = True - return - else: - self.command('stdbuf -o0 cat enb_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync|Starting"', '\$', 4) - if rruCheck: - result = re.search('wait RUs', str(self.ssh.before)) - else: - result = re.search('got sync|Starting F1AP at CU', str(self.ssh.before)) - if result is None: - time.sleep(6) - else: - doLoop = False - enbDidSync = True - time.sleep(10) - - if enbDidSync and eNBinNoS1: - self.command('ifconfig oaitun_enb1', '\$', 4) - self.command('ifconfig oaitun_enb1', '\$', 4) - result = re.search('inet addr:1|inet 1', str(self.ssh.before)) - if result is not None: - logging.debug('\u001B[1m oaitun_enb1 interface is mounted and configured\u001B[0m') - else: - logging.error('\u001B[1m oaitun_enb1 interface is either NOT mounted or NOT configured\u001B[0m') - if self.eNBmbmsEnables[int(self.eNB_instance)]: - self.command('ifconfig oaitun_enm1', '\$', 4) - result = re.search('inet addr', str(self.ssh.before)) - if result is not None: - logging.debug('\u001B[1m oaitun_enm1 interface is mounted and configured\u001B[0m') - else: - logging.error('\u001B[1m oaitun_enm1 interface is either NOT mounted or NOT configured\u001B[0m') - if enbDidSync: - self.eNBstatuses[int(self.eNB_instance)] = int(self.eNB_serverId) - - self.close() - self.CreateHtmlTestRow('-O ' + config_file + extra_options, 'OK', ALL_PROCESSES_OK) - logging.debug('\u001B[1m Initialize eNB Completed\u001B[0m') - + RAN.SetflexranCtrlStarted(True) + SSH.close() + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) + def InitializeUE_common(self, device_id, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if not self.ADBCentralized: # Reboot UE - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesRebootCmd[idx], '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesRebootCmd[idx], '\$', 60) # Wait #time.sleep(60) # Put in LTE-Mode only - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode 11"\'', '\$', 60) - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode1 11"\'', '\$', 60) - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode2 11"\'', '\$', 60) - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode3 11"\'', '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode 11"\'', '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode1 11"\'', '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode2 11"\'', '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "settings put global preferred_network_mode3 11"\'', '\$', 60) # enable data service - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data enable"\'', '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data enable"\'', '\$', 60) # we need to do radio on/off cycle to make sure of above changes # airplane mode off // radio on - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOnCmd[idx], '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOnCmd[idx], '\$', 60) #time.sleep(10) # airplane mode on // radio off - #self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) + #SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) # normal procedure without reboot # enable data service - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data enable"\'', '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data enable"\'', '\$', 60) # airplane mode on // radio off - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) - self.close() + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) + SSH.close() return # enable data service - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "svc data enable"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "svc data enable"', '\$', 60) # The following commands are deprecated since we no longer work on Android 7+ - # self.command('stdbuf -o0 adb -s ' + device_id + ' shell settings put global airplane_mode_on 1', '\$', 10) - # self.command('stdbuf -o0 adb -s ' + device_id + ' shell am broadcast -a android.intent.action.AIRPLANE_MODE --ez state true', '\$', 60) + # SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell settings put global airplane_mode_on 1', '\$', 10) + # SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell am broadcast -a android.intent.action.AIRPLANE_MODE --ez state true', '\$', 60) # a dedicated script has to be installed inside the UE # airplane mode on means call /data/local/tmp/off if device_id == '84B7N16418004022': - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) else: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) #airplane mode off means call /data/local/tmp/on logging.debug('\u001B[1mUE (' + device_id + ') Initialize Completed\u001B[0m') - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def InitializeUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') multi_jobs = [] i = 0 @@ -1011,62 +299,62 @@ class SSHConnection(): i += 1 for job in multi_jobs: job.join() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def InitializeOAIUE(self): if self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '' or self.UESourceCodePath == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - if self.air_interface == 'lte': + if RAN.Getair_interface() == 'lte': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) if result is None: check_eNB = True check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', pStatus) - self.CreateHtmlTabFooter(False) + HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', pStatus) + HTML.CreateHtmlTabFooter(False) sys.exit(1) UE_prefix = '' else: UE_prefix = 'NR ' - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) # b2xx_fx3_utils reset procedure - self.command('echo ' + self.UEPassword + ' | sudo -S uhd_find_devices', '\$', 60) - result = re.search('type: b200', str(self.ssh.before)) + SSH.command('echo ' + self.UEPassword + ' | sudo -S uhd_find_devices', '\$', 60) + result = re.search('type: b200', SSH.getBefore()) if result is not None: logging.debug('Found a B2xx device --> resetting it') - self.command('echo ' + self.UEPassword + ' | sudo -S b2xx_fx3_utils --reset-device', '\$', 10) + SSH.command('echo ' + self.UEPassword + ' | sudo -S b2xx_fx3_utils --reset-device', '\$', 10) # Reloading FGPA bin firmware - self.command('echo ' + self.UEPassword + ' | sudo -S uhd_find_devices', '\$', 60) - result = re.search('type: n3xx', str(self.ssh.before)) + SSH.command('echo ' + self.UEPassword + ' | sudo -S uhd_find_devices', '\$', 60) + result = re.search('type: n3xx', str(SSH.getBefore())) if result is not None: logging.debug('Found a N3xx device --> resetting it') - self.command('cd ' + self.UESourceCodePath, '\$', 5) + SSH.command('cd ' + self.UESourceCodePath, '\$', 5) # Initialize_OAI_UE_args usually start with -C and followed by the location in repository # in case of NR-UE, we may have rrc_config_path (Temporary?) modifiedUeOptions = str(self.Initialize_OAI_UE_args) - if self.air_interface == 'nr': + if RAN.Getair_interface() == 'nr': result = re.search('--rrc_config_path ', modifiedUeOptions) if result is not None: modifiedUeOptions = modifiedUeOptions.replace('rrc_config_path ', 'rrc_config_path ' + self.UESourceCodePath + '/') - self.command('source oaienv', '\$', 5) - self.command('cd cmake_targets/ran_build/build', '\$', 5) - if self.air_interface == 'lte': + SSH.command('source oaienv', '\$', 5) + SSH.command('cd cmake_targets/ran_build/build', '\$', 5) + if RAN.Getair_interface() == 'lte': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) # We may have to regenerate the .u* files if result is None: - self.command('ls /tmp/*.sed', '\$', 5) - result = re.search('adapt_usim_parameters', str(self.ssh.before)) + SSH.command('ls /tmp/*.sed', '\$', 5) + result = re.search('adapt_usim_parameters', SSH.getBefore()) if result is not None: - self.command('sed -f /tmp/adapt_usim_parameters.sed ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) + SSH.command('sed -f /tmp/adapt_usim_parameters.sed ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) else: - self.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) - self.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5) - self.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) - self.command('echo "ulimit -c unlimited && ./'+ self.air_interface +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) - self.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) - self.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) + SSH.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) + SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + SSH.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) self.UELogFile = 'ue_' + self.testCase_id + '.log' # We are now looping several times to hope we really sync w/ an eNB @@ -1075,13 +363,13 @@ class SSHConnection(): gotSyncStatus = True fullSyncStatus = True while (doOutterLoop): - self.command('cd ' + self.UESourceCodePath + '/cmake_targets/ran_build/build', '\$', 5) - self.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) + SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets/ran_build/build', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) #use nohup instead of daemon - #self.command('echo ' + self.UEPassword + ' | sudo -S -E daemon --inherit --unsafe --name=ue' + str(self.UE_instance) + '_daemon --chdir=' + self.UESourceCodePath + '/cmake_targets/ran_build/build -o ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) - self.command('echo $USER; nohup sudo ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh' + ' > ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ' + ' 2>&1 &', self.UEUserName, 5) + #SSH.command('echo ' + self.UEPassword + ' | sudo -S -E daemon --inherit --unsafe --name=ue' + str(self.UE_instance) + '_daemon --chdir=' + self.UESourceCodePath + '/cmake_targets/ran_build/build -o ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + SSH.command('echo $USER; nohup sudo ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh' + ' > ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ' + ' 2>&1 &', self.UEUserName, 5) time.sleep(6) - self.command('cd ../..', '\$', 5) + SSH.command('cd ../..', '\$', 5) doLoop = True loopCounter = 10 gotSyncStatus = True @@ -1094,11 +382,11 @@ class SSHConnection(): gotSyncStatus = False doLoop = False continue - self.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4) - if self.air_interface == 'nr': - result = re.search('Starting sync detection', str(self.ssh.before)) + SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4) + if RAN.Getair_interface() == 'nr': + result = re.search('Starting sync detection', SSH.getBefore()) else: - result = re.search('got sync', str(self.ssh.before)) + result = re.search('got sync', SSH.getBefore()) if result is None: time.sleep(10) else: @@ -1106,33 +394,60 @@ class SSHConnection(): logging.debug('Found "got sync" message!') if gotSyncStatus == False: # we certainly need to stop the lte-uesoftmodem process if it is still running! - self.command('ps -aux | grep --text --color=never softmodem | grep -v grep', '\$', 4) - result = re.search('-uesoftmodem', str(self.ssh.before)) + SSH.command('ps -aux | grep --text --color=never softmodem | grep -v grep', '\$', 4) + result = re.search('-uesoftmodem', SSH.getBefore()) if result is not None: - self.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT -r *-uesoftmodem', '\$', 4) + SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT -r *-uesoftmodem', '\$', 4) time.sleep(3) outterLoopCounter = outterLoopCounter - 1 if (outterLoopCounter == 0): doOutterLoop = False continue - if self.air_interface == 'nr': - fullSyncStatus = True - doOutterLoop = False + # We are now checking if sync w/ eNB DOES NOT OCCUR + # Usually during the cell synchronization stage, the UE returns with No cell synchronization message + # That is the case for LTE + # In NR case, it's a positive message that will show if synchronization occurs + doLoop = True + if RAN.Getair_interface() == 'nr': + loopCounter = 10 else: # We are now checking if sync w/ eNB DOES NOT OCCUR # Usually during the cell synchronization stage, the UE returns with No cell synchronization message - doLoop = True loopCounter = 10 - while (doLoop): - loopCounter = loopCounter - 1 - if (loopCounter == 0): + while (doLoop): + loopCounter = loopCounter - 1 + if (loopCounter == 0): + if RAN.Getair_interface() == 'nr': + # Here we do have great chances that UE did NOT cell-sync w/ gNB + doLoop = False + fullSyncStatus = False + logging.debug('Never seen the NR-Sync message (Measured Carrier Frequency) --> try again') + time.sleep(6) + # Stopping the NR-UE + SSH.command('ps -aux | grep --text --color=never softmodem | grep -v grep', '\$', 4) + result = re.search('nr-uesoftmodem', SSH.getBefore()) + if result is not None: + SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT nr-uesoftmodem', '\$', 4) + time.sleep(6) + else: # Here we do have a great chance that the UE did cell-sync w/ eNB doLoop = False doOutterLoop = False fullSyncStatus = True continue - self.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4) - result = re.search('No cell synchronization found', str(self.ssh.before)) + SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync|Frequency"', '\$', 4) + if RAN.Getair_interface() == 'nr': + # Positive messaging --> + result = re.search('Measured Carrier Frequency', SSH.getBefore()) + if result is not None: + doLoop = False + doOutterLoop = False + fullSyncStatus = True + else: + time.sleep(6) + else: + # Negative messaging --> + result = re.search('No cell synchronization found', SSH.getBefore()) if result is None: time.sleep(6) else: @@ -1140,31 +455,40 @@ class SSHConnection(): fullSyncStatus = False logging.debug('Found: "No cell synchronization" message! --> try again') time.sleep(6) - self.command('ps -aux | grep --text --color=never softmodem | grep -v grep', '\$', 4) - result = re.search('lte-uesoftmodem', str(self.ssh.before)) + SSH.command('ps -aux | grep --text --color=never softmodem | grep -v grep', '\$', 4) + result = re.search('lte-uesoftmodem', SSH.getBefore()) if result is not None: - self.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT lte-uesoftmodem', '\$', 4) - outterLoopCounter = outterLoopCounter - 1 - if (outterLoopCounter == 0): - doOutterLoop = False + SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT lte-uesoftmodem', '\$', 4) + outterLoopCounter = outterLoopCounter - 1 + if (outterLoopCounter == 0): + doOutterLoop = False - if fullSyncStatus and gotSyncStatus and self.air_interface == 'lte': - result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) - if result is None: - self.command('ifconfig oaitun_ue1', '\$', 4) - self.command('ifconfig oaitun_ue1', '\$', 4) + if fullSyncStatus and gotSyncStatus: + doInterfaceCheck = False + if RAN.Getair_interface() == 'lte': + result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) + if result is None: + doInterfaceCheck = True + # For the moment, only in explicit noS1 without kernel module (ie w/ tunnel interface) + if RAN.Getair_interface() == 'nr': + result = re.search('--noS1 --nokrnmod 1', str(self.Initialize_OAI_UE_args)) + if result is not None: + doInterfaceCheck = True + if doInterfaceCheck: + SSH.command('ifconfig oaitun_ue1', '\$', 4) + SSH.command('ifconfig oaitun_ue1', '\$', 4) # ifconfig output is different between ubuntu 16 and ubuntu 18 - result = re.search('inet addr:1|inet 1', str(self.ssh.before)) + result = re.search('inet addr:1|inet 1', SSH.getBefore()) if result is not None: logging.debug('\u001B[1m oaitun_ue1 interface is mounted and configured\u001B[0m') tunnelInterfaceStatus = True else: - logging.debug(str(self.ssh.before)) + logging.debug(SSH.getBefore()) logging.error('\u001B[1m oaitun_ue1 interface is either NOT mounted or NOT configured\u001B[0m') tunnelInterfaceStatus = False - if self.eNBmbmsEnables[0]: - self.command('ifconfig oaitun_uem1', '\$', 4) - result = re.search('inet addr', str(self.ssh.before)) + if RAN.GeteNBmbmsEnable(0): + SSH.command('ifconfig oaitun_uem1', '\$', 4) + result = re.search('inet addr', SSH.getBefore()) if result is not None: logging.debug('\u001B[1m oaitun_uem1 interface is mounted and configured\u001B[0m') tunnelInterfaceStatus = tunnelInterfaceStatus and True @@ -1176,116 +500,116 @@ class SSHConnection(): else: tunnelInterfaceStatus = True - self.close() + SSH.close() if fullSyncStatus and gotSyncStatus and tunnelInterfaceStatus: - self.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'OK', ALL_PROCESSES_OK, 'OAI UE') + HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK, 'OAI UE') logging.debug('\u001B[1m Initialize OAI UE Completed\u001B[0m') if (self.ADBIPAddress != 'none'): self.UEDevices = [] self.UEDevices.append('OAI-UE') self.UEDevicesStatus = [] - self.UEDevicesStatus.append(UE_STATUS_DETACHED) + self.UEDevicesStatus.append(CONST.UE_STATUS_DETACHED) else: - if self.air_interface == 'lte': - if self.eNBmbmsEnables[0]: - self.htmlUEFailureMsg = 'oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured' + if RAN.Getair_interface() == 'lte': + if RAN.GeteNBmbmsEnable(0): + HTML.SethtmlUEFailureMsg('oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured') else: - self.htmlUEFailureMsg = 'oaitun_ue1 interface is either NOT mounted or NOT configured' - self.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE') + HTML.SethtmlUEFailureMsg('oaitun_ue1 interface is either NOT mounted or NOT configured') + HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE') else: - self.htmlUEFailureMsg = 'nr-uesoftmodem did NOT synced' - self.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE') + HTML.SethtmlUEFailureMsg('nr-uesoftmodem did NOT synced') + HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE') logging.error('\033[91mInitialize OAI UE Failed! \033[0m') self.AutoTerminateUEandeNB() def checkDevTTYisUnlocked(self): - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) count = 0 while count < 5: - self.command('echo ' + self.ADBPassword + ' | sudo -S lsof | grep ttyUSB0', '\$', 10) - result = re.search('picocom', str(self.ssh.before)) + SSH.command('echo ' + self.ADBPassword + ' | sudo -S lsof | grep ttyUSB0', '\$', 10) + result = re.search('picocom', SSH.getBefore()) if result is None: count = 10 else: time.sleep(5) count = count + 1 - self.close() + SSH.close() def InitializeCatM(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.picocom_closure = True - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.enablePicocomClosure() + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # dummy call to start a sudo session. The picocom command does NOT handle well the `sudo -S` - self.command('echo ' + self.ADBPassword + ' | sudo -S ls', '\$', 10) - self.command('sudo picocom --baud 921600 --flow n --databits 8 /dev/ttyUSB0', 'Terminal ready', 10) + SSH.command('echo ' + self.ADBPassword + ' | sudo -S ls', '\$', 10) + SSH.command('sudo picocom --baud 921600 --flow n --databits 8 /dev/ttyUSB0', 'Terminal ready', 10) time.sleep(1) # Calling twice AT to clear all buffers - self.command('AT', 'OK|ERROR', 5) - self.command('AT', 'OK', 5) + SSH.command('AT', 'OK|ERROR', 5) + SSH.command('AT', 'OK', 5) # Doing a power cycle - self.command('AT^RESET', 'SIMSTORE,READY', 15) - self.command('AT', 'OK|ERROR', 5) - self.command('AT', 'OK', 5) - self.command('ATE1', 'OK', 5) + SSH.command('AT^RESET', 'SIMSTORE,READY', 15) + SSH.command('AT', 'OK|ERROR', 5) + SSH.command('AT', 'OK', 5) + SSH.command('ATE1', 'OK', 5) # Disabling the Radio - self.command('AT+CFUN=0', 'OK', 5) + SSH.command('AT+CFUN=0', 'OK', 5) logging.debug('\u001B[1m Cellular Functionality disabled\u001B[0m') # Checking if auto-attach is enabled - self.command('AT^AUTOATT?', 'OK', 5) - result = re.search('AUTOATT: (?P[0-9\-]+)', str(self.ssh.before)) + SSH.command('AT^AUTOATT?', 'OK', 5) + result = re.search('AUTOATT: (?P[0-9\-]+)', SSH.getBefore()) if result is not None: if result.group('state') is not None: autoAttachState = int(result.group('state')) if autoAttachState is not None: if autoAttachState == 0: - self.command('AT^AUTOATT=1', 'OK', 5) + SSH.command('AT^AUTOATT=1', 'OK', 5) logging.debug('\u001B[1m Auto-Attach enabled\u001B[0m') else: logging.debug('\u001B[1;37;41m Could not check Auto-Attach! \u001B[0m') # Force closure of picocom but device might still be locked - self.close() - self.picocom_closure = False - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + SSH.close() + SSH.disablePicocomClosure() + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) self.checkDevTTYisUnlocked() def TerminateCatM(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.picocom_closure = True - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.enablePicocomClosure() + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # dummy call to start a sudo session. The picocom command does NOT handle well the `sudo -S` - self.command('echo ' + self.ADBPassword + ' | sudo -S ls', '\$', 10) - self.command('sudo picocom --baud 921600 --flow n --databits 8 /dev/ttyUSB0', 'Terminal ready', 10) + SSH.command('echo ' + self.ADBPassword + ' | sudo -S ls', '\$', 10) + SSH.command('sudo picocom --baud 921600 --flow n --databits 8 /dev/ttyUSB0', 'Terminal ready', 10) time.sleep(1) # Calling twice AT to clear all buffers - self.command('AT', 'OK|ERROR', 5) - self.command('AT', 'OK', 5) + SSH.command('AT', 'OK|ERROR', 5) + SSH.command('AT', 'OK', 5) # Disabling the Radio - self.command('AT+CFUN=0', 'OK', 5) + SSH.command('AT+CFUN=0', 'OK', 5) logging.debug('\u001B[1m Cellular Functionality disabled\u001B[0m') - self.close() - self.picocom_closure = False - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + SSH.close() + SSH.disablePicocomClosure() + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) self.checkDevTTYisUnlocked() def AttachCatM(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.picocom_closure = True - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.enablePicocomClosure() + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # dummy call to start a sudo session. The picocom command does NOT handle well the `sudo -S` - self.command('echo ' + self.ADBPassword + ' | sudo -S ls', '\$', 10) - self.command('sudo picocom --baud 921600 --flow n --databits 8 /dev/ttyUSB0', 'Terminal ready', 10) + SSH.command('echo ' + self.ADBPassword + ' | sudo -S ls', '\$', 10) + SSH.command('sudo picocom --baud 921600 --flow n --databits 8 /dev/ttyUSB0', 'Terminal ready', 10) time.sleep(1) # Calling twice AT to clear all buffers - self.command('AT', 'OK|ERROR', 5) - self.command('AT', 'OK', 5) + SSH.command('AT', 'OK|ERROR', 5) + SSH.command('AT', 'OK', 5) # Enabling the Radio - self.command('AT+CFUN=1', 'SIMSTORE,READY', 5) + SSH.command('AT+CFUN=1', 'SIMSTORE,READY', 5) logging.debug('\u001B[1m Cellular Functionality enabled\u001B[0m') time.sleep(4) # We should check if we register @@ -1293,15 +617,15 @@ class SSHConnection(): attach_cnt = 0 attach_status = False while count < 5: - self.command('AT+CEREG?', 'OK', 5) - result = re.search('CEREG: 2,(?P[0-9\-]+),', str(self.ssh.before)) + SSH.command('AT+CEREG?', 'OK', 5) + result = re.search('CEREG: 2,(?P[0-9\-]+),', SSH.getBefore()) if result is not None: mDataConnectionState = int(result.group('state')) if mDataConnectionState is not None: if mDataConnectionState == 1: count = 10 attach_status = True - result = re.search('CEREG: 2,1,"(?P[0-9A-Z]+)","(?P[0-9A-Z]+)"', str(self.ssh.before)) + result = re.search('CEREG: 2,1,"(?P[0-9A-Z]+)","(?P[0-9A-Z]+)"', SSH.getBefore()) if result is not None: networky = result.group('networky') networkz = result.group('networkz') @@ -1312,21 +636,21 @@ class SSHConnection(): logging.debug('+CEREG: 2,' + str(mDataConnectionState)) attach_cnt = attach_cnt + 1 else: - logging.debug(str(self.ssh.before)) + logging.debug(SSH.getBefore()) attach_cnt = attach_cnt + 1 count = count + 1 time.sleep(1) if attach_status: - self.command('AT+CESQ', 'OK', 5) - result = re.search('CESQ: 99,99,255,255,(?P[0-9]+),(?P[0-9]+)', str(self.ssh.before)) + SSH.command('AT+CESQ', 'OK', 5) + result = re.search('CESQ: 99,99,255,255,(?P[0-9]+),(?P[0-9]+)', SSH.getBefore()) if result is not None: nRSRQ = int(result.group('rsrq')) nRSRP = int(result.group('rsrp')) if (nRSRQ is not None) and (nRSRP is not None): logging.debug(' RSRQ = ' + str(-20+(nRSRQ/2)) + ' dB') logging.debug(' RSRP = ' + str(-140+nRSRP) + ' dBm') - self.close() - self.picocom_closure = False + SSH.close() + SSH.disablePicocomClosure() html_queue = SimpleQueue() self.checkDevTTYisUnlocked() if attach_status: @@ -1337,74 +661,74 @@ class SSHConnection(): else: html_cell += '' html_queue.put(html_cell) - self.CreateHtmlTestRowQueue('N/A', 'OK', 1, html_queue) + HTML.CreateHtmlTestRowQueue('N/A', 'OK', 1, html_queue) else: logging.error('\u001B[1m CAT-M module Attachment Failed\u001B[0m') html_cell = '
CAT-M module Attachment Failed
' html_queue.put(html_cell) - self.CreateHtmlTestRowQueue('N/A', 'KO', 1, html_queue) + HTML.CreateHtmlTestRowQueue('N/A', 'KO', 1, html_queue) self.AutoTerminateUEandeNB() def PingCatM(self): - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '' or self.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) self.AutoTerminateUEandeNB() return try: statusQueue = SimpleQueue() lock = Lock() - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('cd scripts', '\$', 5) - if re.match('OAI', self.EPCType, re.IGNORECASE): + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.command('cd scripts', '\$', 5) + if re.match('OAI', EPC.GetType(), re.IGNORECASE): logging.debug('Using the OAI EPC HSS: not implemented yet') - self.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) - self.CreateHtmlTabFooter(False) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) + HTML.CreateHtmlTabFooter(False) sys.exit(1) else: - self.command('egrep --color=never "Allocated ipv4 addr" /opt/ltebox/var/log/xGwLog.0', '\$', 5) - result = re.search('Allocated ipv4 addr: (?P[0-9\.]+) from Pool', str(self.ssh.before)) + SSH.command('egrep --color=never "Allocated ipv4 addr" /opt/ltebox/var/log/xGwLog.0', '\$', 5) + result = re.search('Allocated ipv4 addr: (?P[0-9\.]+) from Pool', SSH.getBefore()) if result is not None: moduleIPAddr = result.group('ipaddr') else: - self.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) self.AutoTerminateUEandeNB() return ping_time = re.findall("-c (\d+)",str(self.ping_args)) device_id = 'catm' - ping_status = self.command('stdbuf -o0 ping ' + self.ping_args + ' ' + str(moduleIPAddr) + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '_' + device_id + '.log', '\$', int(ping_time[0])*1.5) + ping_status = SSH.command('stdbuf -o0 ping ' + self.ping_args + ' ' + str(moduleIPAddr) + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '_' + device_id + '.log', '\$', int(ping_time[0])*1.5) # TIMEOUT CASE if ping_status < 0: message = 'Ping with UE (' + str(moduleIPAddr) + ') crashed due to TIMEOUT!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, moduleIPAddr, device_id, statusQueue, message) return - result = re.search(', (?P[0-9\.]+)% packet loss, time [0-9\.]+ms', str(self.ssh.before)) + result = re.search(', (?P[0-9\.]+)% packet loss, time [0-9\.]+ms', SSH.getBefore()) if result is None: message = 'Packet Loss Not Found!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, moduleIPAddr, device_id, statusQueue, message) return packetloss = result.group('packetloss') if float(packetloss) == 100: message = 'Packet Loss is 100%' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, moduleIPAddr, device_id, statusQueue, message) return - result = re.search('rtt min\/avg\/max\/mdev = (?P[0-9\.]+)\/(?P[0-9\.]+)\/(?P[0-9\.]+)\/[0-9\.]+ ms', str(self.ssh.before)) + result = re.search('rtt min\/avg\/max\/mdev = (?P[0-9\.]+)\/(?P[0-9\.]+)\/(?P[0-9\.]+)\/[0-9\.]+ ms', SSH.getBefore()) if result is None: message = 'Ping RTT_Min RTT_Avg RTT_Max Not Found!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, moduleIPAddr, device_id, statusQueue, message) return rtt_min = result.group('rtt_min') @@ -1431,37 +755,37 @@ class SSHConnection(): qMsg += '\nPacket Loss is not 0%' logging.debug('\u001B[1;30;43m Packet Loss is not 0% \u001B[0m') lock.release() - self.close() + SSH.close() html_cell = '
CAT-M module\nIP Address  : ' + moduleIPAddr + '\n' + qMsg + '
' statusQueue.put(html_cell) if (packetLossOK): - self.CreateHtmlTestRowQueue(self.ping_args, 'OK', 1, statusQueue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'OK', 1, statusQueue) else: - self.CreateHtmlTestRowQueue(self.ping_args, 'KO', 1, statusQueue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'KO', 1, statusQueue) self.AutoTerminateUEandeNB() except: os.kill(os.getppid(),signal.SIGUSR1) def AttachUE_common(self, device_id, statusQueue, lock, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: if device_id == '84B7N16418004022': - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/on"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/on"', '\$', 60) else: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/on', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/on', '\$', 60) else: # airplane mode off // radio on - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOnCmd[idx], '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOnCmd[idx], '\$', 60) time.sleep(2) max_count = 45 count = max_count while count > 0: if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "dumpsys telephony.registry" | grep -m 1 mDataConnectionState', '\$', 15) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "dumpsys telephony.registry" | grep -m 1 mDataConnectionState', '\$', 15) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "dumpsys telephony.registry"\' | grep -m 1 mDataConnectionState', '\$', 60) - result = re.search('mDataConnectionState.*=(?P[0-9\-]+)', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "dumpsys telephony.registry"\' | grep -m 1 mDataConnectionState', '\$', 60) + result = re.search('mDataConnectionState.*=(?P[0-9\-]+)', SSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m mDataConnectionState Not Found! \u001B[0m') lock.acquire() @@ -1484,19 +808,19 @@ class SSHConnection(): logging.debug('\u001B[1;30;43m Retry UE (' + device_id + ') Flight Mode Off \u001B[0m') if self.ADBCentralized: if device_id == '84B7N16418004022': - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) else: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) time.sleep(0.5) if self.ADBCentralized: if device_id == '84B7N16418004022': - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/on"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/on"', '\$', 60) else: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/on', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/on', '\$', 60) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOnCmd[idx], '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOnCmd[idx], '\$', 60) time.sleep(0.5) logging.debug('\u001B[1mWait UE (' + device_id + ') a second until mDataConnectionState=2 (' + str(max_count-count) + ' times)\u001B[0m') time.sleep(1) @@ -1507,19 +831,19 @@ class SSHConnection(): statusQueue.put(device_id) statusQueue.put('Attach Failed') lock.release() - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def AttachUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow('N/A', 'KO', pStatus) + HTML.CreateHtmlTestRow('N/A', 'KO', pStatus) self.AutoTerminateUEandeNB() return multi_jobs = [] @@ -1528,7 +852,7 @@ class SSHConnection(): nb_ue_to_connect = 0 for device_id in self.UEDevices: if (self.nbMaxUEtoAttach == -1) or (nb_ue_to_connect < self.nbMaxUEtoAttach): - self.UEDevicesStatus[nb_ue_to_connect] = UE_STATUS_ATTACHING + self.UEDevicesStatus[nb_ue_to_connect] = CONST.UE_STATUS_ATTACHING p = Process(target = self.AttachUE_common, args = (device_id, status_queue, lock,nb_ue_to_connect,)) p.daemon = True p.start() @@ -1538,7 +862,7 @@ class SSHConnection(): job.join() if (status_queue.empty()): - self.CreateHtmlTestRow('N/A', 'KO', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'KO', CONST.ALL_PROCESSES_OK) self.AutoTerminateUEandeNB() return else: @@ -1558,48 +882,48 @@ class SSHConnection(): if (attach_status): cnt = 0 while cnt < len(self.UEDevices): - if self.UEDevicesStatus[cnt] == UE_STATUS_ATTACHING: - self.UEDevicesStatus[cnt] = UE_STATUS_ATTACHED + if self.UEDevicesStatus[cnt] == CONST.UE_STATUS_ATTACHING: + self.UEDevicesStatus[cnt] = CONST.UE_STATUS_ATTACHED cnt += 1 - self.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) - result = re.search('T_stdout', str(self.Initialize_eNB_args)) + HTML.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) + result = re.search('T_stdout', str(RAN.GetInitialize_eNB_args())) if result is not None: logging.debug('Waiting 5 seconds to fill up record file') time.sleep(5) else: - self.CreateHtmlTestRowQueue('N/A', 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue('N/A', 'KO', len(self.UEDevices), html_queue) self.AutoTerminateUEandeNB() def DetachUE_common(self, device_id, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: if device_id == '84B7N16418004022': - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) else: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) logging.debug('\u001B[1mUE (' + device_id + ') Detach Completed\u001B[0m') - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def DetachUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow('N/A', 'KO', pStatus) + HTML.CreateHtmlTestRow('N/A', 'KO', pStatus) self.AutoTerminateUEandeNB() return multi_jobs = [] cnt = 0 for device_id in self.UEDevices: - self.UEDevicesStatus[cnt] = UE_STATUS_DETACHING + self.UEDevicesStatus[cnt] = CONST.UE_STATUS_DETACHING p = Process(target = self.DetachUE_common, args = (device_id,cnt,)) p.daemon = True p.start() @@ -1607,37 +931,37 @@ class SSHConnection(): cnt += 1 for job in multi_jobs: job.join() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - result = re.search('T_stdout', str(self.Initialize_eNB_args)) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) + result = re.search('T_stdout', str(RAN.GetInitialize_eNB_args())) if result is not None: logging.debug('Waiting 5 seconds to fill up record file') time.sleep(5) cnt = 0 while cnt < len(self.UEDevices): - self.UEDevicesStatus[cnt] = UE_STATUS_DETACHED + self.UEDevicesStatus[cnt] = CONST.UE_STATUS_DETACHED cnt += 1 def RebootUE_common(self, device_id): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) previousmDataConnectionStates = [] # Save mDataConnectionState - self.command('stdbuf -o0 adb -s ' + device_id + ' shell dumpsys telephony.registry | grep mDataConnectionState', '\$', 15) - self.command('stdbuf -o0 adb -s ' + device_id + ' shell dumpsys telephony.registry | grep mDataConnectionState', '\$', 15) - result = re.search('mDataConnectionState.*=(?P[0-9\-]+)', str(self.ssh.before)) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell dumpsys telephony.registry | grep mDataConnectionState', '\$', 15) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell dumpsys telephony.registry | grep mDataConnectionState', '\$', 15) + result = re.search('mDataConnectionState.*=(?P[0-9\-]+)', SSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m mDataConnectionState Not Found! \u001B[0m') sys.exit(1) previousmDataConnectionStates.append(int(result.group('state'))) # Reboot UE - self.command('stdbuf -o0 adb -s ' + device_id + ' shell reboot', '\$', 10) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell reboot', '\$', 10) time.sleep(60) previousmDataConnectionState = previousmDataConnectionStates.pop(0) count = 180 while count > 0: count = count - 1 - self.command('stdbuf -o0 adb -s ' + device_id + ' shell dumpsys telephony.registry | grep mDataConnectionState', '\$', 15) - result = re.search('mDataConnectionState.*=(?P[0-9\-]+)', str(self.ssh.before)) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell dumpsys telephony.registry | grep mDataConnectionState', '\$', 15) + result = re.search('mDataConnectionState.*=(?P[0-9\-]+)', SSH.getBefore()) if result is None: mDataConnectionState = None else: @@ -1652,20 +976,20 @@ class SSHConnection(): if count == 0: logging.debug('\u001B[1;37;41m UE (' + device_id + ') Reboot Failed \u001B[0m') sys.exit(1) - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def RebootUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow('N/A', 'KO', pStatus) - self.CreateHtmlTabFooter(False) + HTML.CreateHtmlTestRow('N/A', 'KO', pStatus) + HTML.CreateHtmlTabFooter(False) sys.exit(1) multi_jobs = [] for device_id in self.UEDevices: @@ -1675,24 +999,24 @@ class SSHConnection(): multi_jobs.append(p) for job in multi_jobs: job.join() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def DataDisableUE_common(self, device_id, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # disable data service if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "svc data disable"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "svc data disable"', '\$', 60) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data disable"\'', '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data disable"\'', '\$', 60) logging.debug('\u001B[1mUE (' + device_id + ') Disabled Data Service\u001B[0m') - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def DataDisableUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') multi_jobs = [] i = 0 @@ -1704,24 +1028,24 @@ class SSHConnection(): i += 1 for job in multi_jobs: job.join() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def DataEnableUE_common(self, device_id, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # enable data service if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "svc data enable"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "svc data enable"', '\$', 60) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data enable"\'', '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "svc data enable"\'', '\$', 60) logging.debug('\u001B[1mUE (' + device_id + ') Enabled Data Service\u001B[0m') - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def DataEnableUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') multi_jobs = [] i = 0 @@ -1733,25 +1057,26 @@ class SSHConnection(): i += 1 for job in multi_jobs: job.join() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def GetAllUEDevices(self, terminate_ue_flag): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: - self.command('adb devices', '\$', 15) - self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",str(self.ssh.before)) - self.close() + SSH.command('adb devices', '\$', 15) + #self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore()) + self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore()) + SSH.close() else: if (os.path.isfile('./phones_list.txt')): os.remove('./phones_list.txt') - self.command('ls /etc/*/phones*.txt', '\$', 5) - result = re.search('/etc/ci/phones_list.txt', str(self.ssh.before)) - self.close() + SSH.command('ls /etc/*/phones*.txt', '\$', 5) + result = re.search('/etc/ci/phones_list.txt', SSH.getBefore()) + SSH.close() if (result is not None) and (len(self.UEDevices) == 0): - self.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, '/etc/ci/phones_list.txt', '.') + SSH.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, '/etc/ci/phones_list.txt', '.') if (os.path.isfile('./phones_list.txt')): phone_list_file = open('./phones_list.txt', 'r') for line in phone_list_file.readlines(): @@ -1768,46 +1093,47 @@ class SSHConnection(): self.UEDevicesRebootCmd.append(comma_split[5]) phone_list_file.close() - if terminate_ue_flag == False: + if terminate_ue_flag == True: if len(self.UEDevices) == 0: logging.debug('\u001B[1;37;41m UE Not Found! \u001B[0m') sys.exit(1) if len(self.UEDevicesStatus) == 0: cnt = 0 while cnt < len(self.UEDevices): - self.UEDevicesStatus.append(UE_STATUS_DETACHED) + self.UEDevicesStatus.append(CONST.UE_STATUS_DETACHED) cnt += 1 def GetAllCatMDevices(self, terminate_ue_flag): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: - self.command('lsusb | egrep "Future Technology Devices International, Ltd FT2232C" | sed -e "s#:.*##" -e "s# #_#g"', '\$', 15) - self.CatMDevices = re.findall("\\\\r\\\\n([A-Za-z0-9_]+)",str(self.ssh.before)) + SSH.command('lsusb | egrep "Future Technology Devices International, Ltd FT2232C" | sed -e "s#:.*##" -e "s# #_#g"', '\$', 15) + #self.CatMDevices = re.findall("\\\\r\\\\n([A-Za-z0-9_]+)",SSH.getBefore()) + self.CatMDevices = re.findall("\\\\r\\\\n([A-Za-z0-9_]+)",SSH.getBefore()) else: if (os.path.isfile('./modules_list.txt')): os.remove('./modules_list.txt') - self.command('ls /etc/*/modules*.txt', '\$', 5) - result = re.search('/etc/ci/modules_list.txt', str(self.ssh.before)) - self.close() + SSH.command('ls /etc/*/modules*.txt', '\$', 5) + result = re.search('/etc/ci/modules_list.txt', SSH.getBefore()) + SSH.close() if result is not None: logging.debug('Found a module list file on ADB server') - if terminate_ue_flag == False: + if terminate_ue_flag == True: if len(self.CatMDevices) == 0: logging.debug('\u001B[1;37;41m CAT-M UE Not Found! \u001B[0m') sys.exit(1) - self.close() + SSH.close() def CheckUEStatus_common(self, lock, device_id, statusQueue, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "dumpsys telephony.registry"', '\$', 15) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "dumpsys telephony.registry"', '\$', 15) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "dumpsys telephony.registry"\'', '\$', 60) - result = re.search('mServiceState=(?P[0-9]+)', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "dumpsys telephony.registry"\'', '\$', 60) + result = re.search('mServiceState=(?P[0-9]+)', SSH.getBefore()) serviceState = 'Service State: UNKNOWN' if result is not None: lServiceState = int(result.group('serviceState')) @@ -1819,7 +1145,7 @@ class SSHConnection(): serviceState = 'Service State: IN_SERVICE' if lServiceState == 2: serviceState = 'Service State: EMERGENCY_ONLY' - result = re.search('mDataConnectionState=(?P[0-9]+)', str(self.ssh.before)) + result = re.search('mDataConnectionState=(?P[0-9]+)', SSH.getBefore()) dataConnectionState = 'Data State: UNKNOWN' if result is not None: lDataConnectionState = int(result.group('dataConnectionState')) @@ -1831,7 +1157,7 @@ class SSHConnection(): dataConnectionState = 'Data State: CONNECTED' if lDataConnectionState == 3: dataConnectionState = 'Data State: SUSPENDED' - result = re.search('mDataConnectionReason=(?P[0-9a-zA-Z_]+)', str(self.ssh.before)) + result = re.search('mDataConnectionReason=(?P[0-9a-zA-Z_]+)', SSH.getBefore()) dataConnectionReason = 'Data Reason: UNKNOWN' if result is not None: dataConnectionReason = 'Data Reason: ' + result.group('dataConnectionReason') @@ -1845,20 +1171,20 @@ class SSHConnection(): qMsg = serviceState + '\n' + dataConnectionState + '\n' + dataConnectionReason statusQueue.put(qMsg) lock.release() - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def CheckStatusUE(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow('N/A', 'KO', pStatus) - self.CreateHtmlTabFooter(False) + HTML.CreateHtmlTestRow('N/A', 'KO', pStatus) + HTML.CreateHtmlTabFooter(False) sys.exit(1) multi_jobs = [] lock = Lock() @@ -1872,12 +1198,12 @@ class SSHConnection(): i += 1 for job in multi_jobs: job.join() - if self.flexranCtrlInstalled and self.flexranCtrlStarted: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd /opt/flexran_rtc', '\$', 5) - self.command('curl http://localhost:9999/stats | jq \'.\' > log/check_status_' + self.testCase_id + '.log 2>&1', '\$', 5) - self.command('cat log/check_status_' + self.testCase_id + '.log | jq \'.eNB_config[0].UE\' | grep -c rnti | sed -e "s#^#Nb Connected UE = #"', '\$', 5) - result = re.search('Nb Connected UE = (?P[0-9]+)', str(self.ssh.before)) + if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd /opt/flexran_rtc', '\$', 5) + SSH.command('curl http://localhost:9999/stats | jq \'.\' > log/check_status_' + self.testCase_id + '.log 2>&1', '\$', 5) + SSH.command('cat log/check_status_' + self.testCase_id + '.log | jq \'.eNB_config[0].UE\' | grep -c rnti | sed -e "s#^#Nb Connected UE = #"', '\$', 5) + result = re.search('Nb Connected UE = (?P[0-9]+)', SSH.getBefore()) passStatus = True if result is not None: nb_ues = int(result.group('nb_ues')) @@ -1888,13 +1214,13 @@ class SSHConnection(): passStatus = False else: htmlOptions = 'N/A' - self.close() + SSH.close() else: passStatus = True htmlOptions = 'N/A' if (status_queue.empty()): - self.CreateHtmlTestRow(htmlOptions, 'KO', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow(htmlOptions, 'KO', CONST.ALL_PROCESSES_OK) self.AutoTerminateUEandeNB() else: check_status = True @@ -1908,24 +1234,24 @@ class SSHConnection(): html_cell = '
UE (' + device_id + ')\n' + message + '
' html_queue.put(html_cell) if check_status and passStatus: - self.CreateHtmlTestRowQueue(htmlOptions, 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(htmlOptions, 'OK', len(self.UEDevices), html_queue) else: - self.CreateHtmlTestRowQueue(htmlOptions, 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(htmlOptions, 'KO', len(self.UEDevices), html_queue) self.AutoTerminateUEandeNB() def GetAllUEIPAddresses(self): if self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') ue_ip_status = 0 self.UEIPAddresses = [] if (len(self.UEDevices) == 1) and (self.UEDevices[0] == 'OAI-UE'): if self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '' or self.UESourceCodePath == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('ifconfig oaitun_ue1', '\$', 4) - result = re.search('inet addr:(?P[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+)|inet (?P[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+)', str(self.ssh.before)) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('ifconfig oaitun_ue1', '\$', 4) + result = re.search('inet addr:(?P[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+)|inet (?P[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+)', SSH.getBefore()) if result is not None: if result.group('ueipaddress') is not None: UE_IPAddress = result.group('ueipaddress') @@ -1936,21 +1262,21 @@ class SSHConnection(): else: logging.debug('\u001B[1;37;41m UE IP Address Not Found! \u001B[0m') ue_ip_status -= 1 - self.close() + SSH.close() return ue_ip_status - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) idx = 0 for device_id in self.UEDevices: - if self.UEDevicesStatus[idx] != UE_STATUS_ATTACHED: + if self.UEDevicesStatus[idx] != CONST.UE_STATUS_ATTACHED: idx += 1 continue count = 0 while count < 4: if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "ip addr show | grep rmnet"', '\$', 15) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "ip addr show | grep rmnet"', '\$', 15) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ip addr show | grep rmnet"\'', '\$', 60) - result = re.search('inet (?P[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+)\/[0-9]+[0-9a-zA-Z\.\s]+', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ip addr show | grep rmnet"\'', '\$', 60) + result = re.search('inet (?P[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+)\/[0-9]+[0-9a-zA-Z\.\s]+', SSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m UE IP Address Not Found! \u001B[0m') time.sleep(1) @@ -1969,7 +1295,7 @@ class SSHConnection(): continue self.UEIPAddresses.append(UE_IPAddress) idx += 1 - self.close() + SSH.close() return ue_ip_status def ping_iperf_wrong_exit(self, lock, UE_IPAddress, device_id, statusQueue, message): @@ -1985,50 +1311,50 @@ class SSHConnection(): # Launch ping on the EPC side (true for ltebox and old open-air-cn) # But for OAI-Rel14-CUPS, we launch from python executor launchFromEpc = True - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): + if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE): launchFromEpc = False ping_time = re.findall("-c (\d+)",str(self.ping_args)) if launchFromEpc: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('cd scripts', '\$', 5) - ping_status = self.command('stdbuf -o0 ping ' + self.ping_args + ' ' + UE_IPAddress + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '_' + device_id + '.log', '\$', int(ping_time[0])*1.5) + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.command('cd scripts', '\$', 5) + ping_status = SSH.command('stdbuf -o0 ping ' + self.ping_args + ' ' + UE_IPAddress + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '_' + device_id + '.log', '\$', int(ping_time[0])*1.5) else: cmd = 'ping ' + self.ping_args + ' ' + UE_IPAddress + ' 2>&1 > ping_' + self.testCase_id + '_' + device_id + '.log' message = cmd + '\n' logging.debug(cmd) ret = subprocess.run(cmd, shell=True) ping_status = ret.returncode - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'ping_' + self.testCase_id + '_' + device_id + '.log', self.EPCSourceCodePath + '/scripts') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cat ' + self.EPCSourceCodePath + '/scripts/ping_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'ping_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cat ' + EPC.GetSourceCodePath() + '/scripts/ping_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) # TIMEOUT CASE if ping_status < 0: message = 'Ping with UE (' + str(UE_IPAddress) + ') crashed due to TIMEOUT!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return - result = re.search(', (?P[0-9\.]+)% packet loss, time [0-9\.]+ms', str(self.ssh.before)) + result = re.search(', (?P[0-9\.]+)% packet loss, time [0-9\.]+ms', SSH.getBefore()) if result is None: message = 'Packet Loss Not Found!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return packetloss = result.group('packetloss') if float(packetloss) == 100: message = 'Packet Loss is 100%' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return - result = re.search('rtt min\/avg\/max\/mdev = (?P[0-9\.]+)\/(?P[0-9\.]+)\/(?P[0-9\.]+)\/[0-9\.]+ ms', str(self.ssh.before)) + result = re.search('rtt min\/avg\/max\/mdev = (?P[0-9\.]+)\/(?P[0-9\.]+)\/(?P[0-9\.]+)\/[0-9\.]+ ms', SSH.getBefore()) if result is None: message = 'Ping RTT_Min RTT_Avg RTT_Max Not Found!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return rtt_min = result.group('rtt_min') @@ -2062,7 +1388,7 @@ class SSHConnection(): statusQueue.put(UE_IPAddress) statusQueue.put(qMsg) lock.release() - self.close() + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) @@ -2070,41 +1396,41 @@ class SSHConnection(): html_queue = SimpleQueue() html_cell = '
OAI UE ping result\n' + qMsg + '
' html_queue.put(html_cell) - self.CreateHtmlTestRowQueue(self.ping_args, 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'KO', len(self.UEDevices), html_queue) def PingNoS1(self): check_eNB = True check_OAI_UE = True pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) self.AutoTerminateUEandeNB() return ping_from_eNB = re.search('oaitun_enb1', str(self.ping_args)) if ping_from_eNB is not None: - if self.eNBIPAddress == '' or self.eNBUserName == '' or self.eNBPassword == '': - Usage() + if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') else: if self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '': - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') try: if ping_from_eNB is not None: - self.open(self.eNBIPAddress, self.eNBUserName, self.eNBPassword) - self.command('cd ' + self.eNBSourceCodePath + '/cmake_targets/', '\$', 5) + SSH.open(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword()) + SSH.command('cd ' + RAN.GeteNBSourceCodePath() + '/cmake_targets/', '\$', 5) else: - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('cd ' + self.UESourceCodePath + '/cmake_targets/', '\$', 5) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets/', '\$', 5) ping_time = re.findall("-c (\d+)",str(self.ping_args)) - ping_status = self.command('stdbuf -o0 ping ' + self.ping_args + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '.log', '\$', int(ping_time[0])*1.5) + ping_status = SSH.command('stdbuf -o0 ping ' + self.ping_args + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '.log', '\$', int(ping_time[0])*1.5) # TIMEOUT CASE if ping_status < 0: message = 'Ping with OAI UE crashed due to TIMEOUT!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') self.PingNoS1_wrong_exit(message) return - result = re.search(', (?P[0-9\.]+)% packet loss, time [0-9\.]+ms', str(self.ssh.before)) + result = re.search(', (?P[0-9\.]+)% packet loss, time [0-9\.]+ms', SSH.getBefore()) if result is None: message = 'Packet Loss Not Found!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') @@ -2116,7 +1442,7 @@ class SSHConnection(): logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') self.PingNoS1_wrong_exit(message) return - result = re.search('rtt min\/avg\/max\/mdev = (?P[0-9\.]+)\/(?P[0-9\.]+)\/(?P[0-9\.]+)\/[0-9\.]+ ms', str(self.ssh.before)) + result = re.search('rtt min\/avg\/max\/mdev = (?P[0-9\.]+)\/(?P[0-9\.]+)\/(?P[0-9\.]+)\/[0-9\.]+ ms', SSH.getBefore()) if result is None: message = 'Ping RTT_Min RTT_Avg RTT_Max Not Found!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') @@ -2144,33 +1470,33 @@ class SSHConnection(): elif float(packetloss) > 0: qMsg += '\nPacket Loss is not 0%' logging.debug('\u001B[1;30;43m Packet Loss is not 0% \u001B[0m') - self.close() + SSH.close() html_queue = SimpleQueue() ip_addr = 'TBD' html_cell = '
OAI UE ping result\n' + qMsg + '
' html_queue.put(html_cell) if packetLossOK: - self.CreateHtmlTestRowQueue(self.ping_args, 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'OK', len(self.UEDevices), html_queue) else: - self.CreateHtmlTestRowQueue(self.ping_args, 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'KO', len(self.UEDevices), html_queue) # copying on the EPC server for logCollection if ping_from_eNB is not None: - copyin_res = self.copyin(self.eNBIPAddress, self.eNBUserName, self.eNBPassword, self.eNBSourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') + copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') else: - copyin_res = self.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') + copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') if (copyin_res == 0): - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'ping_' + self.testCase_id + '.log', self.EPCSourceCodePath + '/scripts') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'ping_' + self.testCase_id + '.log', EPC.GetSourceCodePath() + '/scripts') except: os.kill(os.getppid(),signal.SIGUSR1) def Ping(self): - result = re.search('noS1', str(self.Initialize_eNB_args)) + result = re.search('noS1', str(RAN.GetInitialize_eNB_args())) if result is not None: self.PingNoS1() return - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '' or self.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True if (len(self.UEDevices) == 1) and (self.UEDevices[0] == 'OAI-UE'): @@ -2179,12 +1505,12 @@ class SSHConnection(): check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) self.AutoTerminateUEandeNB() return ueIpStatus = self.GetAllUEIPAddresses() if (ueIpStatus < 0): - self.CreateHtmlTestRow(self.ping_args, 'KO', UE_IP_ADDRESS_ISSUE) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', CONST.UE_IP_ADDRESS_ISSUE) self.AutoTerminateUEandeNB() return multi_jobs = [] @@ -2202,7 +1528,7 @@ class SSHConnection(): job.join() if (status_queue.empty()): - self.CreateHtmlTestRow(self.ping_args, 'KO', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow(self.ping_args, 'KO', CONST.ALL_PROCESSES_OK) self.AutoTerminateUEandeNB() else: ping_status = True @@ -2217,9 +1543,9 @@ class SSHConnection(): html_cell = '
UE (' + device_id + ')\nIP Address  : ' + ip_addr + '\n' + message + '
' html_queue.put(html_cell) if (ping_status): - self.CreateHtmlTestRowQueue(self.ping_args, 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'OK', len(self.UEDevices), html_queue) else: - self.CreateHtmlTestRowQueue(self.ping_args, 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.ping_args, 'KO', len(self.UEDevices), html_queue) self.AutoTerminateUEandeNB() def Iperf_ComputeTime(self): @@ -2255,8 +1581,8 @@ class SSHConnection(): return result def Iperf_analyzeV2TCPOutput(self, lock, UE_IPAddress, device_id, statusQueue, iperf_real_options): - self.command('awk -f /tmp/tcp_iperf_stats.awk /tmp/CI-eNB/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) - result = re.search('Avg Bitrate : (?P[0-9\.]+ Mbits\/sec) Max Bitrate : (?P[0-9\.]+ Mbits\/sec) Min Bitrate : (?P[0-9\.]+ Mbits\/sec)', str(self.ssh.before)) + SSH.command('awk -f /tmp/tcp_iperf_stats.awk /tmp/CI-eNB/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + result = re.search('Avg Bitrate : (?P[0-9\.]+ Mbits\/sec) Max Bitrate : (?P[0-9\.]+ Mbits\/sec) Min Bitrate : (?P[0-9\.]+ Mbits\/sec)', SSH.getBefore()) if result is not None: avgbitrate = result.group('average') maxbitrate = result.group('maximum') @@ -2285,9 +1611,9 @@ class SSHConnection(): if result is None: return self.Iperf_analyzeV2TCPOutput(lock, UE_IPAddress, device_id, statusQueue, iperf_real_options) - result = re.search('Server Report:', str(self.ssh.before)) + result = re.search('Server Report:', SSH.getBefore()) if result is None: - result = re.search('read failed: Connection refused', str(self.ssh.before)) + result = re.search('read failed: Connection refused', SSH.getBefore()) if result is not None: logging.debug('\u001B[1;37;41m Could not connect to iperf server! \u001B[0m') else: @@ -2311,7 +1637,7 @@ class SSHConnection(): req_bandwidth = '%.1f Gbits/sec' % req_bw req_bw = req_bw * 1000000000 - result = re.search('Server Report:\\\\r\\\\n(?:|\[ *\d+\].*) (?P[0-9\.]+ [KMG]bits\/sec) +(?P[0-9\.]+ ms) +(\d+\/..\d+) +(\((?P[0-9\.]+)%\))', str(self.ssh.before)) + result = re.search('Server Report:\\\\r\\\\n(?:|\[ *\d+\].*) (?P[0-9\.]+ [KMG]bits\/sec) +(?P[0-9\.]+ ms) +(\d+\/..\d+) +(\((?P[0-9\.]+)%\))', SSH.getBefore()) if result is not None: bitrate = result.group('bitrate') packetloss = result.group('packetloss') @@ -2462,9 +1788,9 @@ class SSHConnection(): def Iperf_analyzeV3Output(self, lock, UE_IPAddress, device_id, statusQueue): - result = re.search('(?P[0-9\.]+ [KMG]bits\/sec) +(?:|[0-9\.]+ ms +\d+\/\d+ \((?P[0-9\.]+)%\)) +(?:|receiver)\\\\r\\\\n(?:|\[ *\d+\] Sent \d+ datagrams)\\\\r\\\\niperf Done\.', str(self.ssh.before)) + result = re.search('(?P[0-9\.]+ [KMG]bits\/sec) +(?:|[0-9\.]+ ms +\d+\/\d+ \((?P[0-9\.]+)%\)) +(?:|receiver)\\\\r\\\\n(?:|\[ *\d+\] Sent \d+ datagrams)\\\\r\\\\niperf Done\.', SSH.getBefore()) if result is None: - result = re.search('(?Piperf: error - [a-zA-Z0-9 :]+)', str(self.ssh.before)) + result = re.search('(?Piperf: error - [a-zA-Z0-9 :]+)', SSH.getBefore()) lock.acquire() statusQueue.put(-1) statusQueue.put(device_id) @@ -2513,7 +1839,7 @@ class SSHConnection(): # Launch iperf server on EPC side (true for ltebox and old open-air-cn0 # But for OAI-Rel14-CUPS, we launch from python executor and we are using its IP address as iperf client address launchFromEpc = True - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): + if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE): launchFromEpc = False cmd = 'hostname -I' ret = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, encoding='utf-8') @@ -2521,14 +1847,14 @@ class SSHConnection(): EPC_Iperf_UE_IPAddress = ret.stdout.strip() port = 5001 + idx if launchFromEpc: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) + SSH.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) if udpIperf: - self.command('echo $USER; nohup iperf -u -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.EPCUserName, 5) + SSH.command('echo $USER; nohup iperf -u -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.GetUserName(), 5) else: - self.command('echo $USER; nohup iperf -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.EPCUserName, 5) - self.close() + SSH.command('echo $USER; nohup iperf -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.GetUserName(), 5) + SSH.close() else: if self.ueIperfVersion == self.dummyIperfVersion: prefix = '' @@ -2546,11 +1872,11 @@ class SSHConnection(): # Launch iperf client on UE if (device_id == 'OAI-UE'): - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) else: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) iperf_time = self.Iperf_ComputeTime() time.sleep(0.5) @@ -2561,50 +1887,50 @@ class SSHConnection(): modified_options = modified_options.replace('-R','') time.sleep(0.5) - self.command('rm -f iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.command('rm -f iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) if (device_id == 'OAI-UE'): - iperf_status = self.command('iperf -c ' + EPC_Iperf_UE_IPAddress + ' ' + modified_options + ' -p ' + str(port) + ' -B ' + UE_IPAddress + ' 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) + iperf_status = SSH.command('iperf -c ' + EPC_Iperf_UE_IPAddress + ' ' + modified_options + ' -p ' + str(port) + ' -B ' + UE_IPAddress + ' 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) else: if self.ADBCentralized: - iperf_status = self.command('stdbuf -o0 adb -s ' + device_id + ' shell "/data/local/tmp/iperf -c ' + EPC_Iperf_UE_IPAddress + ' ' + modified_options + ' -p ' + str(port) + '" 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) + iperf_status = SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "/data/local/tmp/iperf -c ' + EPC_Iperf_UE_IPAddress + ' ' + modified_options + ' -p ' + str(port) + '" 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) else: - iperf_status = self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "/data/local/tmp/iperf -c ' + EPC_Iperf_UE_IPAddress + ' ' + modified_options + ' -p ' + str(port) + '"\' 2>&1 > iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) - self.command('fromdos -o iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) - self.command('cat iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + iperf_status = SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "/data/local/tmp/iperf -c ' + EPC_Iperf_UE_IPAddress + ' ' + modified_options + ' -p ' + str(port) + '"\' 2>&1 > iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) + SSH.command('fromdos -o iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.command('cat iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) # TIMEOUT Case if iperf_status < 0: - self.close() + SSH.close() message = 'iperf on UE (' + str(UE_IPAddress) + ') crashed due to TIMEOUT !' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return clientStatus = self.Iperf_analyzeV2Output(lock, UE_IPAddress, device_id, statusQueue, modified_options) - self.close() + SSH.close() # Kill iperf server on EPC side if launchFromEpc: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('killall --signal SIGKILL iperf', self.EPCUserName, 5) - self.close() + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('killall --signal SIGKILL iperf', EPC.GetUserName(), 5) + SSH.close() else: cmd = 'killall --signal SIGKILL iperf' logging.debug(cmd) subprocess.run(cmd, shell=True) time.sleep(1) - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', self.EPCSourceCodePath + '/scripts') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') # in case of failure, retrieve server log if (clientStatus == -1) or (clientStatus == -2): if launchFromEpc: time.sleep(1) if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')): os.remove('iperf_server_' + self.testCase_id + '_' + device_id + '.log') - self.copyin(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, self.EPCSourceCodePath + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyin(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath() + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') self.Iperf_analyzeV2Server(lock, UE_IPAddress, device_id, statusQueue, modified_options) # in case of OAI-UE if (device_id == 'OAI-UE'): - self.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_' + self.testCase_id + '_' + device_id + '.log', '.') - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_' + self.testCase_id + '_' + device_id + '.log', self.EPCSourceCodePath + '/scripts') + SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') def Iperf_common(self, lock, UE_IPAddress, device_id, idx, ue_num, statusQueue): try: @@ -2616,48 +1942,48 @@ class SSHConnection(): self.ueIperfVersion = '2.0.5' if (device_id != 'OAI-UE'): - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # if by chance ADB server and EPC are on the same remote host, at least log collection will take care of it - self.command('if [ ! -d ' + self.EPCSourceCodePath + '/scripts ]; then mkdir -p ' + self.EPCSourceCodePath + '/scripts ; fi', '\$', 5) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) + SSH.command('if [ ! -d ' + EPC.GetSourceCodePath() + '/scripts ]; then mkdir -p ' + EPC.GetSourceCodePath() + '/scripts ; fi', '\$', 5) + SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) # Checking if iperf / iperf3 are installed if self.ADBCentralized: - self.command('adb -s ' + device_id + ' shell "ls /data/local/tmp"', '\$', 5) + SSH.command('adb -s ' + device_id + ' shell "ls /data/local/tmp"', '\$', 5) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ls /data/local/tmp"\'', '\$', 60) - result = re.search('iperf3', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ls /data/local/tmp"\'', '\$', 60) + result = re.search('iperf3', SSH.getBefore()) if result is None: - result = re.search('iperf', str(self.ssh.before)) + result = re.search('iperf', SSH.getBefore()) if result is None: message = 'Neither iperf nor iperf3 installed on UE!' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') - self.close() + SSH.close() self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return else: if self.ADBCentralized: - self.command('adb -s ' + device_id + ' shell "/data/local/tmp/iperf --version"', '\$', 5) + SSH.command('adb -s ' + device_id + ' shell "/data/local/tmp/iperf --version"', '\$', 5) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "/data/local/tmp/iperf --version"\'', '\$', 60) - result = re.search('iperf version 2.0.5', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "/data/local/tmp/iperf --version"\'', '\$', 60) + result = re.search('iperf version 2.0.5', SSH.getBefore()) if result is not None: self.ueIperfVersion = '2.0.5' - result = re.search('iperf version 2.0.10', str(self.ssh.before)) + result = re.search('iperf version 2.0.10', SSH.getBefore()) if result is not None: self.ueIperfVersion = '2.0.10' else: useIperf3 = True - self.close() + SSH.close() else: - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('iperf --version', '\$', 5) - result = re.search('iperf version 2.0.5', str(self.ssh.before)) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('iperf --version', '\$', 5) + result = re.search('iperf version 2.0.5', SSH.getBefore()) if result is not None: self.ueIperfVersion = '2.0.5' - result = re.search('iperf version 2.0.10', str(self.ssh.before)) + result = re.search('iperf version 2.0.10', SSH.getBefore()) if result is not None: self.ueIperfVersion = '2.0.10' - self.close() + SSH.close() # in case of iperf, UL has its own function if (not useIperf3): result = re.search('-R', str(self.iperf_args)) @@ -2667,44 +1993,44 @@ class SSHConnection(): # Launch the IPERF server on the UE side for DL if (device_id == 'OAI-UE'): - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) - self.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) + SSH.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) result = re.search('-u', str(self.iperf_args)) if result is None: - self.command('echo $USER; nohup iperf -B ' + UE_IPAddress + ' -s -i 1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.UEUserName, 5) + SSH.command('echo $USER; nohup iperf -B ' + UE_IPAddress + ' -s -i 1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.UEUserName, 5) udpIperf = False else: - self.command('echo $USER; nohup iperf -B ' + UE_IPAddress + ' -u -s -i 1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.UEUserName, 5) + SSH.command('echo $USER; nohup iperf -B ' + UE_IPAddress + ' -u -s -i 1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.UEUserName, 5) else: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) if self.ADBCentralized: if (useIperf3): - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/iperf3 -s &', '\$', 5) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/iperf3 -s &', '\$', 5) else: - self.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) result = re.search('-u', str(self.iperf_args)) if result is None: - self.command('echo $USER; nohup adb -s ' + device_id + ' shell "/data/local/tmp/iperf -s -i 1" > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.ADBUserName, 5) + SSH.command('echo $USER; nohup adb -s ' + device_id + ' shell "/data/local/tmp/iperf -s -i 1" > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.ADBUserName, 5) udpIperf = False else: - self.command('echo $USER; nohup adb -s ' + device_id + ' shell "/data/local/tmp/iperf -u -s -i 1" > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.ADBUserName, 5) + SSH.command('echo $USER; nohup adb -s ' + device_id + ' shell "/data/local/tmp/iperf -u -s -i 1" > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.ADBUserName, 5) else: - self.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) - self.command('echo $USER; nohup ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "/data/local/tmp/iperf -u -s -i 1" \' 2>&1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.ADBUserName, 60) + SSH.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.command('echo $USER; nohup ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "/data/local/tmp/iperf -u -s -i 1" \' 2>&1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.ADBUserName, 60) time.sleep(0.5) - self.close() + SSH.close() # Launch the IPERF client on the EPC side for DL (true for ltebox and old open-air-cn # But for OAI-Rel14-CUPS, we launch from python executor launchFromEpc = True - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): + if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE): launchFromEpc = False if launchFromEpc: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) iperf_time = self.Iperf_ComputeTime() time.sleep(0.5) @@ -2715,18 +2041,18 @@ class SSHConnection(): time.sleep(0.5) if launchFromEpc: - self.command('rm -f iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.command('rm -f iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) else: if (os.path.isfile('iperf_' + self.testCase_id + '_' + device_id + '.log')): os.remove('iperf_' + self.testCase_id + '_' + device_id + '.log') if (useIperf3): - self.command('stdbuf -o0 iperf3 -c ' + UE_IPAddress + ' ' + modified_options + ' 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) + SSH.command('stdbuf -o0 iperf3 -c ' + UE_IPAddress + ' ' + modified_options + ' 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) clientStatus = 0 self.Iperf_analyzeV3Output(lock, UE_IPAddress, device_id, statusQueue) else: if launchFromEpc: - iperf_status = self.command('stdbuf -o0 iperf -c ' + UE_IPAddress + ' ' + modified_options + ' 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) + iperf_status = SSH.command('stdbuf -o0 iperf -c ' + UE_IPAddress + ' ' + modified_options + ' 2>&1 | stdbuf -o0 tee iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', int(iperf_time)*5.0) else: if self.ueIperfVersion == self.dummyIperfVersion: prefix = '' @@ -2739,46 +2065,46 @@ class SSHConnection(): logging.debug(cmd) ret = subprocess.run(cmd, shell=True) iperf_status = ret.returncode - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_' + self.testCase_id + '_' + device_id + '.log', self.EPCSourceCodePath + '/scripts') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cat ' + self.EPCSourceCodePath + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cat ' + EPC.GetSourceCodePath() + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) if iperf_status < 0: if launchFromEpc: - self.close() + SSH.close() message = 'iperf on UE (' + str(UE_IPAddress) + ') crashed due to TIMEOUT !' logging.debug('\u001B[1;37;41m ' + message + ' \u001B[0m') self.ping_iperf_wrong_exit(lock, UE_IPAddress, device_id, statusQueue, message) return clientStatus = self.Iperf_analyzeV2Output(lock, UE_IPAddress, device_id, statusQueue, modified_options) - self.close() + SSH.close() # Kill the IPERF server that runs in background if (device_id == 'OAI-UE'): - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('killall iperf', '\$', 5) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('killall iperf', '\$', 5) else: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell ps | grep --color=never iperf | grep -v grep', '\$', 5) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell ps | grep --color=never iperf | grep -v grep', '\$', 5) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ps" | grep --color=never iperf | grep -v grep\'', '\$', 60) - result = re.search('shell +(?P\d+)', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ps" | grep --color=never iperf | grep -v grep\'', '\$', 60) + result = re.search('shell +(?P\d+)', SSH.getBefore()) if result is not None: pid_iperf = result.group('pid') if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell kill -KILL ' + pid_iperf, '\$', 5) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell kill -KILL ' + pid_iperf, '\$', 5) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "kill -KILL ' + pid_iperf + '"\'', '\$', 60) - self.close() + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "kill -KILL ' + pid_iperf + '"\'', '\$', 60) + SSH.close() # if the client report is absent, try to analyze the server log file if (clientStatus == -1): time.sleep(1) if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')): os.remove('iperf_server_' + self.testCase_id + '_' + device_id + '.log') if (device_id == 'OAI-UE'): - self.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') else: - self.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, self.EPCSourceCodePath + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, EPC.GetSourceCodePath() + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') # fromdos has to be called on the python executor not on ADB server cmd = 'fromdos -o iperf_server_' + self.testCase_id + '_' + device_id + '.log' subprocess.run(cmd, shell=True) @@ -2788,29 +2114,29 @@ class SSHConnection(): if (device_id == 'OAI-UE'): if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')): if not launchFromEpc: - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', self.EPCSourceCodePath + '/scripts') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') else: - self.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', self.EPCSourceCodePath + '/scripts') + SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') except: os.kill(os.getppid(),signal.SIGUSR1) def IperfNoS1(self): - if self.eNBIPAddress == '' or self.eNBUserName == '' or self.eNBPassword == '' or self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '': - Usage() + if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True check_OAI_UE = True pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow(self.iperf_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.iperf_args, 'KO', pStatus) self.AutoTerminateUEandeNB() return server_on_enb = re.search('-R', str(self.iperf_args)) if server_on_enb is not None: - iServerIPAddr = self.eNBIPAddress - iServerUser = self.eNBUserName - iServerPasswd = self.eNBPassword + iServerIPAddr = RAN.GeteNBIPAddress() + iServerUser = RAN.GeteNBUserName() + iServerPasswd = RAN.GeteNBPassword() iClientIPAddr = self.UEIPAddress iClientUser = self.UEUserName iClientPasswd = self.UEPassword @@ -2818,29 +2144,29 @@ class SSHConnection(): iServerIPAddr = self.UEIPAddress iServerUser = self.UEUserName iServerPasswd = self.UEPassword - iClientIPAddr = self.eNBIPAddress - iClientUser = self.eNBUserName - iClientPasswd = self.eNBPassword + iClientIPAddr = RAN.GeteNBIPAddress() + iClientUser = RAN.GeteNBUserName() + iClientPasswd = RAN.GeteNBPassword() if self.iperf_options != 'sink': # Starting the iperf server - self.open(iServerIPAddr, iServerUser, iServerPasswd) + SSH.open(iServerIPAddr, iServerUser, iServerPasswd) # args SHALL be "-c client -u any" # -c 10.0.1.2 -u -b 1M -t 30 -i 1 -fm -B 10.0.1.1 # -B 10.0.1.1 -u -s -i 1 -fm server_options = re.sub('-u.*$', '-u -s -i 1 -fm', str(self.iperf_args)) server_options = server_options.replace('-c','-B') - self.command('rm -f /tmp/tmp_iperf_server_' + self.testCase_id + '.log', '\$', 5) - self.command('echo $USER; nohup iperf ' + server_options + ' > /tmp/tmp_iperf_server_' + self.testCase_id + '.log 2>&1 &', iServerUser, 5) + SSH.command('rm -f /tmp/tmp_iperf_server_' + self.testCase_id + '.log', '\$', 5) + SSH.command('echo $USER; nohup iperf ' + server_options + ' > /tmp/tmp_iperf_server_' + self.testCase_id + '.log 2>&1 &', iServerUser, 5) time.sleep(0.5) - self.close() + SSH.close() # Starting the iperf client modified_options = self.Iperf_ComputeModifiedBW(0, 1) modified_options = modified_options.replace('-R','') iperf_time = self.Iperf_ComputeTime() - self.open(iClientIPAddr, iClientUser, iClientPasswd) - self.command('rm -f /tmp/tmp_iperf_' + self.testCase_id + '.log', '\$', 5) - iperf_status = self.command('stdbuf -o0 iperf ' + modified_options + ' 2>&1 | stdbuf -o0 tee /tmp/tmp_iperf_' + self.testCase_id + '.log', '\$', int(iperf_time)*5.0) + SSH.open(iClientIPAddr, iClientUser, iClientPasswd) + SSH.command('rm -f /tmp/tmp_iperf_' + self.testCase_id + '.log', '\$', 5) + iperf_status = SSH.command('stdbuf -o0 iperf ' + modified_options + ' 2>&1 | stdbuf -o0 tee /tmp/tmp_iperf_' + self.testCase_id + '.log', '\$', int(iperf_time)*5.0) status_queue = SimpleQueue() lock = Lock() if iperf_status < 0: @@ -2856,28 +2182,29 @@ class SSHConnection(): status_queue.put('Sink Test : no check') else: clientStatus = self.Iperf_analyzeV2Output(lock, '10.0.1.2', 'OAI-UE', status_queue, modified_options) - self.close() + SSH.close() # Stopping the iperf server if self.iperf_options != 'sink': - self.open(iServerIPAddr, iServerUser, iServerPasswd) - self.command('killall --signal SIGKILL iperf', '\$', 5) + SSH.open(iServerIPAddr, iServerUser, iServerPasswd) + SSH.command('killall --signal SIGKILL iperf', '\$', 5) time.sleep(0.5) - self.close() + SSH.close() + if (clientStatus == -1): if (os.path.isfile('iperf_server_' + self.testCase_id + '.log')): os.remove('iperf_server_' + self.testCase_id + '.log') - self.copyin(iServerIPAddr, iServerUser, iServerPasswd, '/tmp/tmp_iperf_server_' + self.testCase_id + '.log', 'iperf_server_' + self.testCase_id + '_OAI-UE.log') + SSH.copyin(iServerIPAddr, iServerUser, iServerPasswd, '/tmp/tmp_iperf_server_' + self.testCase_id + '.log', 'iperf_server_' + self.testCase_id + '_OAI-UE.log') self.Iperf_analyzeV2Server(lock, '10.0.1.2', 'OAI-UE', status_queue, modified_options) # copying on the EPC server for logCollection if (clientStatus == -1): - copyin_res = self.copyin(iServerIPAddr, iServerUser, iServerPasswd, '/tmp/tmp_iperf_server_' + self.testCase_id + '.log', 'iperf_server_' + self.testCase_id + '_OAI-UE.log') + copyin_res = SSH.copyin(iServerIPAddr, iServerUser, iServerPasswd, '/tmp/tmp_iperf_server_' + self.testCase_id + '.log', 'iperf_server_' + self.testCase_id + '_OAI-UE.log') if (copyin_res == 0): - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_server_' + self.testCase_id + '_OAI-UE.log', self.EPCSourceCodePath + '/scripts') - copyin_res = self.copyin(iClientIPAddr, iClientUser, iClientPasswd, '/tmp/tmp_iperf_' + self.testCase_id + '.log', 'iperf_' + self.testCase_id + '_OAI-UE.log') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_OAI-UE.log', EPC.GetSourceCodePath() + '/scripts') + copyin_res = SSH.copyin(iClientIPAddr, iClientUser, iClientPasswd, '/tmp/tmp_iperf_' + self.testCase_id + '.log', 'iperf_' + self.testCase_id + '_OAI-UE.log') if (copyin_res == 0): - self.copyout(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, 'iperf_' + self.testCase_id + '_OAI-UE.log', self.EPCSourceCodePath + '/scripts') + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_OAI-UE.log', EPC.GetSourceCodePath() + '/scripts') iperf_noperf = False if status_queue.empty(): iperf_status = False @@ -2896,20 +2223,20 @@ class SSHConnection(): html_cell = '
UE (' + device_id + ')\nIP Address  : ' + ip_addr + '\n' + message + '
' html_queue.put(html_cell) if (iperf_noperf and iperf_status): - self.CreateHtmlTestRowQueue(self.iperf_args, 'PERF NOT MET', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.iperf_args, 'PERF NOT MET', len(self.UEDevices), html_queue) elif (iperf_status): - self.CreateHtmlTestRowQueue(self.iperf_args, 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.iperf_args, 'OK', len(self.UEDevices), html_queue) else: - self.CreateHtmlTestRowQueue(self.iperf_args, 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.iperf_args, 'KO', len(self.UEDevices), html_queue) self.AutoTerminateUEandeNB() def Iperf(self): - result = re.search('noS1', str(self.Initialize_eNB_args)) + result = re.search('noS1', str(RAN.GetInitialize_eNB_args())) if result is not None: self.IperfNoS1() return - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '' or self.EPCSourceCodePath == '' or self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True if (len(self.UEDevices) == 1) and (self.UEDevices[0] == 'OAI-UE'): @@ -2918,12 +2245,13 @@ class SSHConnection(): check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - self.CreateHtmlTestRow(self.iperf_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.iperf_args, 'KO', pStatus) self.AutoTerminateUEandeNB() return ueIpStatus = self.GetAllUEIPAddresses() if (ueIpStatus < 0): - self.CreateHtmlTestRow(self.iperf_args, 'KO', UE_IP_ADDRESS_ISSUE) + logging.debug('going here') + HTML.CreateHtmlTestRow(self.iperf_args, 'KO', CONST.UE_IP_ADDRESS_ISSUE) self.AutoTerminateUEandeNB() return @@ -2945,7 +2273,7 @@ class SSHConnection(): status_queue = SimpleQueue() for UE_IPAddress in self.UEIPAddresses: device_id = self.UEDevices[i] - p = Process(target = SSH.Iperf_common, args = (lock,UE_IPAddress,device_id,i,ue_num,status_queue,)) + p = Process(target = self.Iperf_common, args = (lock,UE_IPAddress,device_id,i,ue_num,status_queue,)) p.daemon = True p.start() multi_jobs.append(p) @@ -2954,7 +2282,7 @@ class SSHConnection(): job.join() if (status_queue.empty()): - self.CreateHtmlTestRow(self.iperf_args, 'KO', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow(self.iperf_args, 'KO', CONST.ALL_PROCESSES_OK) self.AutoTerminateUEandeNB() else: iperf_status = True @@ -2972,11 +2300,11 @@ class SSHConnection(): html_cell = '
UE (' + device_id + ')\nIP Address  : ' + ip_addr + '\n' + message + '
' html_queue.put(html_cell) if (iperf_noperf and iperf_status): - self.CreateHtmlTestRowQueue(self.iperf_args, 'PERF NOT MET', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.iperf_args, 'PERF NOT MET', len(self.UEDevices), html_queue) elif (iperf_status): - self.CreateHtmlTestRowQueue(self.iperf_args, 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.iperf_args, 'OK', len(self.UEDevices), html_queue) else: - self.CreateHtmlTestRowQueue(self.iperf_args, 'KO', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue(self.iperf_args, 'KO', len(self.UEDevices), html_queue) self.AutoTerminateUEandeNB() def CheckProcessExist(self, check_eNB, check_OAI_UE): @@ -2984,17 +2312,17 @@ class SSHConnection(): status_queue = SimpleQueue() # in noS1 config, no need to check status from EPC # in gNB also currently no need to check - result = re.search('noS1|band78', str(self.Initialize_eNB_args)) + result = re.search('noS1|band78', str(RAN.GetInitialize_eNB_args())) if result is None: - p = Process(target = SSH.CheckHSSProcess, args = (status_queue,)) + p = Process(target = EPC.CheckHSSProcess, args = (status_queue,)) p.daemon = True p.start() multi_jobs.append(p) - p = Process(target = SSH.CheckMMEProcess, args = (status_queue,)) + p = Process(target = EPC.CheckMMEProcess, args = (status_queue,)) p.daemon = True p.start() multi_jobs.append(p) - p = Process(target = SSH.CheckSPGWProcess, args = (status_queue,)) + p = Process(target = EPC.CheckSPGWProcess, args = (status_queue,)) p.daemon = True p.start() multi_jobs.append(p) @@ -3002,12 +2330,12 @@ class SSHConnection(): if (check_eNB == False) and (check_OAI_UE == False): return 0 if check_eNB: - p = Process(target = SSH.CheckeNBProcess, args = (status_queue,)) + p = Process(target = RAN.CheckeNBProcess, args = (status_queue,)) p.daemon = True p.start() multi_jobs.append(p) if check_OAI_UE: - p = Process(target = SSH.CheckOAIUEProcess, args = (status_queue,)) + p = Process(target = self.CheckOAIUEProcess, args = (status_queue,)) p.daemon = True p.start() multi_jobs.append(p) @@ -3022,15 +2350,15 @@ class SSHConnection(): status = status_queue.get() if (status < 0): result = status - if result == ENB_PROCESS_FAILED: - fileCheck = re.search('enb_', str(self.eNBLogFiles[0])) + if result == CONST.ENB_PROCESS_FAILED: + fileCheck = re.search('enb_', str(RAN.GeteNBLogFile(0))) if fileCheck is not None: - self.copyin(self.eNBIPAddress, self.eNBUserName, self.eNBPassword, self.eNBSourceCodePath + '/cmake_targets/' + self.eNBLogFiles[0], '.') - logStatus = self.AnalyzeLogFile_eNB(self.eNBLogFiles[0]) + SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/' + RAN.GeteNBLogFile(0), '.') + logStatus = RAN.AnalyzeLogFile_eNB(RAN.GeteNBLogFile[0]) if logStatus < 0: result = logStatus - self.eNBLogFiles[0] = '' - if self.flexranCtrlInstalled and self.flexranCtrlStarted: + RAN.SeteNBLogFile('', 0) + if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): self.TerminateFlexranCtrl() return result @@ -3038,7 +2366,7 @@ class SSHConnection(): multi_jobs = [] status_queue = SimpleQueue() if initialize_OAI_UE_flag == False: - p = Process(target = SSH.CheckOAIUEProcess, args = (status_queue,)) + p = Process(target = self.CheckOAIUEProcess, args = (status_queue,)) p.daemon = True p.start() multi_jobs.append(p) @@ -3053,10 +2381,10 @@ class SSHConnection(): status = status_queue.get() if (status < 0): result = status - if result == OAI_UE_PROCESS_FAILED: + if result == CONST.OAI_UE_PROCESS_FAILED: fileCheck = re.search('ue_', str(self.UELogFile)) if fileCheck is not None: - self.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/' + self.UELogFile, '.') + SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/' + self.UELogFile, '.') logStatus = self.AnalyzeLogFile_UE(self.UELogFile) if logStatus < 0: result = logStatus @@ -3064,379 +2392,18 @@ class SSHConnection(): def CheckOAIUEProcess(self, status_queue): try: - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + '-uesoftmodem | grep -v grep', '\$', 5) - result = re.search(self.air_interface + '-uesoftmodem', str(self.ssh.before)) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + RAN.Getair_interface() + '-uesoftmodem | grep -v grep', '\$', 5) + result = re.search(RAN.Getair_interface() + '-uesoftmodem', SSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m OAI UE Process Not Found! \u001B[0m') - status_queue.put(OAI_UE_PROCESS_FAILED) + status_queue.put(CONST.OAI_UE_PROCESS_FAILED) else: - status_queue.put(OAI_UE_PROCESS_OK) - self.close() + status_queue.put(CONST.OAI_UE_PROCESS_OK) + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) - def CheckeNBProcess(self, status_queue): - try: - # At least the instance 0 SHALL be on! - if self.eNBstatuses[0] == 0: - lIpAddr = self.eNBIPAddress - lUserName = self.eNBUserName - lPassWord = self.eNBPassword - elif self.eNBstatuses[0] == 1: - lIpAddr = self.eNB1IPAddress - lUserName = self.eNB1UserName - lPassWord = self.eNB1Password - elif self.eNBstatuses[0] == 2: - lIpAddr = self.eNB2IPAddress - lUserName = self.eNB2UserName - lPassWord = self.eNB2Password - else: - lIpAddr = self.eNBIPAddress - lUserName = self.eNBUserName - lPassWord = self.eNBPassword - self.open(lIpAddr, lUserName, lPassWord) - self.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + '-softmodem | grep -v grep', '\$', 5) - result = re.search(self.air_interface + '-softmodem', str(self.ssh.before)) - if result is None: - logging.debug('\u001B[1;37;41m eNB Process Not Found! \u001B[0m') - status_queue.put(ENB_PROCESS_FAILED) - else: - status_queue.put(ENB_PROCESS_OK) - self.close() - except: - os.kill(os.getppid(),signal.SIGUSR1) - - def CheckHSSProcess(self, status_queue): - try: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('stdbuf -o0 ps -aux | grep --color=never hss | grep -v grep', '\$', 5) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - result = re.search('oai_hss -j', str(self.ssh.before)) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - result = re.search('\/bin\/bash .\/run_', str(self.ssh.before)) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - result = re.search('hss_sim s6as diam_hss', str(self.ssh.before)) - else: - logging.error('This should not happen!') - if result is None: - logging.debug('\u001B[1;37;41m HSS Process Not Found! \u001B[0m') - status_queue.put(HSS_PROCESS_FAILED) - else: - status_queue.put(HSS_PROCESS_OK) - self.close() - except: - os.kill(os.getppid(),signal.SIGUSR1) - - def CheckMMEProcess(self, status_queue): - try: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('stdbuf -o0 ps -aux | grep --color=never mme | grep -v grep', '\$', 5) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - result = re.search('mme -c', str(self.ssh.before)) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - result = re.search('\/bin\/bash .\/run_', str(self.ssh.before)) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - result = re.search('mme', str(self.ssh.before)) - else: - logging.error('This should not happen!') - if result is None: - logging.debug('\u001B[1;37;41m MME Process Not Found! \u001B[0m') - status_queue.put(MME_PROCESS_FAILED) - else: - status_queue.put(MME_PROCESS_OK) - self.close() - except: - os.kill(os.getppid(),signal.SIGUSR1) - - def CheckSPGWProcess(self, status_queue): - try: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('stdbuf -o0 ps -aux | grep --color=never spgw | grep -v grep', '\$', 5) - result = re.search('spgwu -c ', str(self.ssh.before)) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - self.command('stdbuf -o0 ps -aux | grep --color=never spgw | grep -v grep', '\$', 5) - result = re.search('\/bin\/bash .\/run_', str(self.ssh.before)) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('stdbuf -o0 ps -aux | grep --color=never xGw | grep -v grep', '\$', 5) - result = re.search('xGw', str(self.ssh.before)) - else: - logging.error('This should not happen!') - if result is None: - logging.debug('\u001B[1;37;41m SPGW Process Not Found! \u001B[0m') - status_queue.put(SPGW_PROCESS_FAILED) - else: - status_queue.put(SPGW_PROCESS_OK) - self.close() - except: - os.kill(os.getppid(),signal.SIGUSR1) - - def AnalyzeLogFile_eNB(self, eNBlogFile): - if (not os.path.isfile('./' + eNBlogFile)): - return -1 - enb_log_file = open('./' + eNBlogFile, 'r') - exitSignalReceived = False - foundAssertion = False - msgAssertion = '' - msgLine = 0 - foundSegFault = False - foundRealTimeIssue = False - rrcSetupComplete = 0 - rrcReleaseRequest = 0 - rrcReconfigRequest = 0 - rrcReconfigComplete = 0 - rrcReestablishRequest = 0 - rrcReestablishComplete = 0 - rrcReestablishReject = 0 - rlcDiscardBuffer = 0 - rachCanceledProcedure = 0 - uciStatMsgCount = 0 - pdcpFailure = 0 - ulschFailure = 0 - ulschOK = 0 - cdrxActivationMessageCount = 0 - dropNotEnoughRBs = 0 - mbmsRequestMsg = 0 - self.htmleNBFailureMsg = '' - isRRU = False - isSlave = False - slaveReceivesFrameResyncCmd = False - X2HO_state = X2_HO_REQ_STATE__IDLE - X2HO_inNbProcedures = 0 - X2HO_outNbProcedures = 0 - for line in enb_log_file.readlines(): - if X2HO_state == X2_HO_REQ_STATE__IDLE: - result = re.search('target eNB Receives X2 HO Req X2AP_HANDOVER_REQ', str(line)) - if result is not None: - X2HO_state = X2_HO_REQ_STATE__TARGET_RECEIVES_REQ - result = re.search('source eNB receives the X2 HO ACK X2AP_HANDOVER_REQ_ACK', str(line)) - if result is not None: - X2HO_state = X2_HO_REQ_STATE__SOURCE_RECEIVES_REQ_ACK - if X2HO_state == X2_HO_REQ_STATE__TARGET_RECEIVES_REQ: - result = re.search('Received LTE_RRCConnectionReconfigurationComplete from UE', str(line)) - if result is not None: - X2HO_state = X2_HO_REQ_STATE__TARGET_RRC_RECFG_COMPLETE - if X2HO_state == X2_HO_REQ_STATE__TARGET_RRC_RECFG_COMPLETE: - result = re.search('issue rrc_eNB_send_PATH_SWITCH_REQ', str(line)) - if result is not None: - X2HO_state = X2_HO_REQ_STATE__TARGET_SENDS_SWITCH_REQ - if X2HO_state == X2_HO_REQ_STATE__TARGET_SENDS_SWITCH_REQ: - result = re.search('received path switch ack S1AP_PATH_SWITCH_REQ_ACK', str(line)) - if result is not None: - X2HO_state = X2_HO_REQ_STATE__IDLE - X2HO_inNbProcedures += 1 - if X2HO_state == X2_HO_REQ_STATE__SOURCE_RECEIVES_REQ_ACK: - result = re.search('source eNB receives the X2 UE CONTEXT RELEASE X2AP_UE_CONTEXT_RELEASE', str(line)) - if result is not None: - X2HO_state = X2_HO_REQ_STATE__IDLE - X2HO_outNbProcedures += 1 - - if self.eNBOptions[int(self.eNB_instance)] != '': - res1 = re.search('max_rxgain (?P[0-9]+)', self.eNBOptions[int(self.eNB_instance)]) - res2 = re.search('max_rxgain (?P[0-9]+)', str(line)) - if res1 is not None and res2 is not None: - requested_option = int(res1.group('requested_option')) - applied_option = int(res2.group('applied_option')) - if requested_option == applied_option: - self.htmleNBFailureMsg += ' Command line option(s) correctly applied ' + self.eNBOptions[int(self.eNB_instance)] + '\n\n' - else: - self.htmleNBFailureMsg += ' Command line option(s) NOT applied ' + self.eNBOptions[int(self.eNB_instance)] + '\n\n' - result = re.search('Exiting OAI softmodem', str(line)) - if result is not None: - exitSignalReceived = True - result = re.search('[Ss]egmentation [Ff]ault', str(line)) - if result is not None and not exitSignalReceived: - foundSegFault = True - result = re.search('[Cc]ore [dD]ump', str(line)) - if result is not None and not exitSignalReceived: - foundSegFault = True - result = re.search('./ran_build/build/lte-softmodem', str(line)) - if result is not None and not exitSignalReceived: - foundSegFault = True - result = re.search('[Aa]ssertion', str(line)) - if result is not None and not exitSignalReceived: - foundAssertion = True - result = re.search('LLL', str(line)) - if result is not None and not exitSignalReceived: - foundRealTimeIssue = True - if foundAssertion and (msgLine < 3): - msgLine += 1 - msgAssertion += str(line) - result = re.search('Setting function for RU', str(line)) - if result is not None: - isRRU = True - if isRRU: - result = re.search('RU 0 is_slave=yes', str(line)) - if result is not None: - isSlave = True - if isSlave: - result = re.search('Received RRU_frame_resynch command', str(line)) - if result is not None: - slaveReceivesFrameResyncCmd = True - result = re.search('LTE_RRCConnectionSetupComplete from UE', str(line)) - if result is not None: - rrcSetupComplete += 1 - result = re.search('Generate LTE_RRCConnectionRelease|Generate RRCConnectionRelease', str(line)) - if result is not None: - rrcReleaseRequest += 1 - result = re.search('Generate LTE_RRCConnectionReconfiguration', str(line)) - if result is not None: - rrcReconfigRequest += 1 - result = re.search('LTE_RRCConnectionReconfigurationComplete from UE rnti', str(line)) - if result is not None: - rrcReconfigComplete += 1 - result = re.search('LTE_RRCConnectionReestablishmentRequest', str(line)) - if result is not None: - rrcReestablishRequest += 1 - result = re.search('LTE_RRCConnectionReestablishmentComplete', str(line)) - if result is not None: - rrcReestablishComplete += 1 - result = re.search('LTE_RRCConnectionReestablishmentReject', str(line)) - if result is not None: - rrcReestablishReject += 1 - result = re.search('CDRX configuration activated after RRC Connection', str(line)) - if result is not None: - cdrxActivationMessageCount += 1 - result = re.search('uci->stat', str(line)) - if result is not None: - uciStatMsgCount += 1 - result = re.search('PDCP.*Out of Resources.*reason', str(line)) - if result is not None: - pdcpFailure += 1 - result = re.search('ULSCH in error in round', str(line)) - if result is not None: - ulschFailure += 1 - if self.air_interface == 'nr': - result = re.search('ULSCH received ok', str(line)) - if result is not None: - ulschOK += 1 - result = re.search('BAD all_segments_received', str(line)) - if result is not None: - rlcDiscardBuffer += 1 - result = re.search('Canceled RA procedure for UE rnti', str(line)) - if result is not None: - rachCanceledProcedure += 1 - result = re.search('dropping, not enough RBs', str(line)) - if result is not None: - dropNotEnoughRBs += 1 - if self.eNBmbmsEnables[int(self.eNB_instance)]: - result = re.search('MBMS USER-PLANE.*Requesting.*bytes from RLC', str(line)) - if result is not None: - mbmsRequestMsg += 1 - enb_log_file.close() - logging.debug(' File analysis completed') - self.htmleNBFailureMsg = '' - if self.air_interface == 'lte': - nodeB_prefix = 'e' - else: - nodeB_prefix = 'g' - if uciStatMsgCount > 0: - statMsg = nodeB_prefix + 'NB showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)' - logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmleNBFailureMsg += statMsg + '\n' - if pdcpFailure > 0: - statMsg = nodeB_prefix + 'NB showed ' + str(pdcpFailure) + ' "PDCP Out of Resources" message(s)' - logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmleNBFailureMsg += statMsg + '\n' - if ulschFailure > 0: - statMsg = nodeB_prefix + 'NB showed ' + str(ulschFailure) + ' "ULSCH in error in round" message(s)' - logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmleNBFailureMsg += statMsg + '\n' - if self.air_interface == 'nr': - if ulschOK > 0: - statMsg = nodeB_prefix + 'NB showed ' + str(ulschOK) + ' "ULSCH received ok" message(s)' - logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmleNBFailureMsg += statMsg + '\n' - if dropNotEnoughRBs > 0: - statMsg = 'eNB showed ' + str(dropNotEnoughRBs) + ' "dropping, not enough RBs" message(s)' - logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmleNBFailureMsg += statMsg + '\n' - if rrcSetupComplete > 0: - rrcMsg = nodeB_prefix + 'NB completed ' + str(rrcSetupComplete) + ' RRC Connection Setup(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - rrcMsg = ' -- ' + str(rrcSetupComplete) + ' were completed' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if rrcReleaseRequest > 0: - rrcMsg = nodeB_prefix + 'NB requested ' + str(rrcReleaseRequest) + ' RRC Connection Release(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if rrcReconfigRequest > 0 or rrcReconfigComplete > 0: - rrcMsg = nodeB_prefix + 'NB requested ' + str(rrcReconfigRequest) + ' RRC Connection Reconfiguration(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - rrcMsg = ' -- ' + str(rrcReconfigComplete) + ' were completed' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if rrcReestablishRequest > 0 or rrcReestablishComplete > 0 or rrcReestablishReject > 0: - rrcMsg = nodeB_prefix + 'NB requested ' + str(rrcReestablishRequest) + ' RRC Connection Reestablishment(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - rrcMsg = ' -- ' + str(rrcReestablishComplete) + ' were completed' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - rrcMsg = ' -- ' + str(rrcReestablishReject) + ' were rejected' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if self.eNBmbmsEnables[int(self.eNB_instance)]: - if mbmsRequestMsg > 0: - rrcMsg = 'eNB requested ' + str(mbmsRequestMsg) + ' times the RLC for MBMS USER-PLANE' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if X2HO_inNbProcedures > 0: - rrcMsg = 'eNB completed ' + str(X2HO_inNbProcedures) + ' X2 Handover Connection procedure(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if X2HO_outNbProcedures > 0: - rrcMsg = 'eNB completed ' + str(X2HO_outNbProcedures) + ' X2 Handover Release procedure(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if self.eNBOptions[int(self.eNB_instance)] != '': - res1 = re.search('drx_Config_present prSetup', self.eNBOptions[int(self.eNB_instance)]) - if res1 is not None: - if cdrxActivationMessageCount > 0: - rrcMsg = 'eNB activated the CDRX Configuration for ' + str(cdrxActivationMessageCount) + ' time(s)' - logging.debug('\u001B[1;30;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - else: - rrcMsg = 'eNB did NOT ACTIVATE the CDRX Configuration' - logging.debug('\u001B[1;37;43m ' + rrcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rrcMsg + '\n' - if rachCanceledProcedure > 0: - rachMsg = nodeB_prefix + 'NB cancelled ' + str(rachCanceledProcedure) + ' RA procedure(s)' - logging.debug('\u001B[1;30;43m ' + rachMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rachMsg + '\n' - if isRRU: - if isSlave: - if slaveReceivesFrameResyncCmd: - rruMsg = 'Slave RRU received the RRU_frame_resynch command from RAU' - logging.debug('\u001B[1;30;43m ' + rruMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rruMsg + '\n' - else: - rruMsg = 'Slave RRU DID NOT receive the RRU_frame_resynch command from RAU' - logging.debug('\u001B[1;37;41m ' + rruMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rruMsg + '\n' - self.prematureExit = True - return ENB_PROCESS_SLAVE_RRU_NOT_SYNCED - if foundSegFault: - logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB ended with a Segmentation Fault! \u001B[0m') - return ENB_PROCESS_SEG_FAULT - if foundAssertion: - logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB ended with an assertion! \u001B[0m') - self.htmleNBFailureMsg += msgAssertion - return ENB_PROCESS_ASSERTION - if foundRealTimeIssue: - logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB faced real time issues! \u001B[0m') - self.htmleNBFailureMsg += nodeB_prefix + 'NB faced real time issues!\n' - #return ENB_PROCESS_REALTIME_ISSUE - if rlcDiscardBuffer > 0: - rlcMsg = nodeB_prefix + 'NB RLC discarded ' + str(rlcDiscardBuffer) + ' buffer(s)' - logging.debug('\u001B[1;37;41m ' + rlcMsg + ' \u001B[0m') - self.htmleNBFailureMsg += rlcMsg + '\n' - return ENB_PROCESS_REALTIME_ISSUE - return 0 def AnalyzeLogFile_UE(self, UElogFile): if (not os.path.isfile('./' + UElogFile)): @@ -3464,7 +2431,7 @@ class SSHConnection(): nrFoundDCI = 0 nrCRCOK = 0 mbms_messages = 0 - self.htmlUEFailureMsg = '' + HTML.SethtmlUEFailureMsg('') for line in ue_log_file.readlines(): result = re.search('nr_synchro_time', str(line)) if result is not None: @@ -3525,7 +2492,7 @@ class SSHConnection(): result = re.search('No cell synchronization found, abandoning', str(line)) if result is not None: no_cell_sync_found = True - if self.eNBmbmsEnables[0]: + if RAN.GeteNBmbmsEnable(0): result = re.search('TRIED TO PUSH MBMS DATA', str(line)) if result is not None: mbms_messages += 1 @@ -3533,22 +2500,22 @@ class SSHConnection(): if result is not None and (not mib_found): try: mibMsg = "MIB Information: " + result.group(1) + ', ' + result.group(2) - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " nidcell = " + result.group('nidcell') - self.htmlUEFailureMsg += mibMsg + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg) logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " n_rb_dl = " + result.group('n_rb_dl') - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " phich_duration = " + result.group('phich_duration') - self.htmlUEFailureMsg += mibMsg + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg) logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " phich_resource = " + result.group('phich_resource') - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " tx_ant = " + result.group('tx_ant') - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') mib_found = True except Exception as e: @@ -3557,7 +2524,7 @@ class SSHConnection(): if result is not None and (not frequency_found): try: mibMsg = "Measured Carrier Frequency = " + result.group('measured_carrier_frequency') + ' Hz' - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') frequency_found = True except Exception as e: @@ -3566,7 +2533,7 @@ class SSHConnection(): if result is not None and (not plmn_found): try: mibMsg = 'PLMN MCC = ' + result.group('mcc') + ' MNC = ' + result.group('mnc') - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') plmn_found = True except Exception as e: @@ -3575,7 +2542,7 @@ class SSHConnection(): if result is not None: try: mibMsg = "The operator is: " + result.group('operator') - self.htmlUEFailureMsg += mibMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') logging.debug('\033[94m' + mibMsg + '\033[0m') except Exception as e: logging.error('\033[91m' + "Operator name not found" + '\033[0m') @@ -3583,7 +2550,7 @@ class SSHConnection(): if result is not None: try: mibMsg = "SIB5 InterFreqCarrierFreq element " + result.group(1) + '/' + result.group(2) - self.htmlUEFailureMsg += mibMsg + ' -> ' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + ' -> ') logging.debug('\033[94m' + mibMsg + '\033[0m') except Exception as e: logging.error('\033[91m' + "SIB5 InterFreqCarrierFreq element not found" + '\033[0m') @@ -3593,7 +2560,7 @@ class SSHConnection(): freq = result.group('carrier_frequency') new_freq = re.sub('/[0-9]+','',freq) float_freq = float(new_freq) / 1000000 - self.htmlUEFailureMsg += 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz' + HTMLSethtmlUEFailureMsg(HTMLGethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz') logging.debug('\033[94m' + " DL Carrier Frequency is: " + freq + '\033[0m') except Exception as e: logging.error('\033[91m' + " DL Carrier Frequency not found" + '\033[0m') @@ -3601,7 +2568,7 @@ class SSHConnection(): if result is not None: try: prb = result.group('allowed_bandwidth') - self.htmlUEFailureMsg += ' -- PRB: ' + prb + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + ' -- PRB: ' + prb + '\n') logging.debug('\033[94m' + " AllowedMeasBandwidth: " + prb + '\033[0m') except Exception as e: logging.error('\033[91m' + " AllowedMeasBandwidth not found" + '\033[0m') @@ -3609,339 +2576,167 @@ class SSHConnection(): if rrcConnectionRecfgComplete > 0: statMsg = 'UE connected to eNB (' + str(rrcConnectionRecfgComplete) + ' RRCConnectionReconfigurationComplete message(s) generated)' logging.debug('\033[94m' + statMsg + '\033[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if nrUEFlag: if nrDecodeMib > 0: statMsg = 'UE showed ' + str(nrDecodeMib) + ' MIB decode message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if nrFoundDCI > 0: statMsg = 'UE showed ' + str(nrFoundDCI) + ' DCI found message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if nrCRCOK > 0: statMsg = 'UE showed ' + str(nrCRCOK) + ' PDSCH decoding message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if not frequency_found: statMsg = 'NR-UE could NOT synch!' logging.error('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if uciStatMsgCount > 0: statMsg = 'UE showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if pdcpDataReqFailedCount > 0: statMsg = 'UE showed ' + str(pdcpDataReqFailedCount) + ' "PDCP data request failed" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if badDciCount > 0: statMsg = 'UE showed ' + str(badDciCount) + ' "bad DCI 1(A)" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if f1aRetransmissionCount > 0: statMsg = 'UE showed ' + str(f1aRetransmissionCount) + ' "Format1A Retransmission but TBS are different" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if fatalErrorCount > 0: statMsg = 'UE showed ' + str(fatalErrorCount) + ' "FATAL ERROR:" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if macBsrTimerExpiredCount > 0: statMsg = 'UE showed ' + str(fatalErrorCount) + ' "MAC BSR Triggered ReTxBSR Timer expiry" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' - if self.eNBmbmsEnables[0]: + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + if RAN.GeteNBmbmsEnable(0): if mbms_messages > 0: statMsg = 'UE showed ' + str(mbms_messages) + ' "TRIED TO PUSH MBMS DATA" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') else: statMsg = 'UE did NOT SHOW "TRIED TO PUSH MBMS DATA" message(s)' logging.debug('\u001B[1;30;41m ' + statMsg + ' \u001B[0m') - self.htmlUEFailureMsg += statMsg + '\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if foundSegFault: logging.debug('\u001B[1;37;41m UE ended with a Segmentation Fault! \u001B[0m') if not nrUEFlag: - return OAI_UE_PROCESS_SEG_FAULT + return CONST.OAI_UE_PROCESS_SEG_FAULT else: if not frequency_found: - return OAI_UE_PROCESS_SEG_FAULT + return CONST.OAI_UE_PROCESS_SEG_FAULT if foundAssertion: logging.debug('\u001B[1;30;43m UE showed an assertion! \u001B[0m') - self.htmlUEFailureMsg += 'UE showed an assertion!\n' + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE showed an assertion!\n') if not nrUEFlag: if not mib_found or not frequency_found: - return OAI_UE_PROCESS_ASSERTION + return CONST.OAI_UE_PROCESS_ASSERTION else: if not frequency_found: - return OAI_UE_PROCESS_ASSERTION + return CONST.OAI_UE_PROCESS_ASSERTION if foundRealTimeIssue: logging.debug('\u001B[1;37;41m UE faced real time issues! \u001B[0m') - self.htmlUEFailureMsg += 'UE faced real time issues!\n' - #return ENB_PROCESS_REALTIME_ISSUE + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE faced real time issues!\n') + #return CONST.ENB_PROCESS_REALTIME_ISSUE if nrUEFlag: if not frequency_found: - return OAI_UE_PROCESS_COULD_NOT_SYNC + return CONST.OAI_UE_PROCESS_COULD_NOT_SYNC else: if no_cell_sync_found and not mib_found: logging.debug('\u001B[1;37;41m UE could not synchronize ! \u001B[0m') - self.htmlUEFailureMsg += 'UE could not synchronize!\n' - return OAI_UE_PROCESS_COULD_NOT_SYNC + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE could not synchronize!\n') + return CONST.OAI_UE_PROCESS_COULD_NOT_SYNC return 0 - def TerminateeNB(self): - if self.eNB_serverId == '0': - lIpAddr = self.eNBIPAddress - lUserName = self.eNBUserName - lPassWord = self.eNBPassword - lSourcePath = self.eNBSourceCodePath - elif self.eNB_serverId == '1': - lIpAddr = self.eNB1IPAddress - lUserName = self.eNB1UserName - lPassWord = self.eNB1Password - lSourcePath = self.eNB1SourceCodePath - elif self.eNB_serverId == '2': - lIpAddr = self.eNB2IPAddress - lUserName = self.eNB2UserName - lPassWord = self.eNB2Password - lSourcePath = self.eNB2SourceCodePath - if lIpAddr == '' or lUserName == '' or lPassWord == '' or lSourcePath == '': - Usage() - sys.exit('Insufficient Parameter') - self.open(lIpAddr, lUserName, lPassWord) - self.command('cd ' + lSourcePath + '/cmake_targets', '\$', 5) - if self.air_interface == 'lte': - nodeB_prefix = 'e' - else: - nodeB_prefix = 'g' - self.command('stdbuf -o0 ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) - result = re.search('-softmodem', str(self.ssh.before)) - if result is not None: - self.command('echo ' + lPassWord + ' | sudo -S daemon --name=enb' + str(self.eNB_instance) + '_daemon --stop', '\$', 5) - self.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem || true', '\$', 5) - time.sleep(10) - self.command('stdbuf -o0 ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) - result = re.search('-softmodem', str(self.ssh.before)) - if result is not None: - self.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem || true', '\$', 5) - time.sleep(5) - self.command('rm -f my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) - self.close() - # If tracer options is on, stopping tshark on EPC side - result = re.search('T_stdout', str(self.Initialize_eNB_args)) - if result is not None: - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - logging.debug('\u001B[1m Stopping tshark \u001B[0m') - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL tshark', '\$', 5) - time.sleep(1) - if self.EPC_PcapFileName != '': - self.command('echo ' + self.EPCPassword + ' | sudo -S chmod 666 /tmp/' + self.EPC_PcapFileName, '\$', 5) - self.copyin(self.EPCIPAddress, self.EPCUserName, self.EPCPassword, '/tmp/' + self.EPC_PcapFileName, '.') - self.copyout(lIpAddr, lUserName, lPassWord, self.EPC_PcapFileName, lSourcePath + '/cmake_targets/.') - self.close() - logging.debug('\u001B[1m Replaying RAW record file\u001B[0m') - self.open(lIpAddr, lUserName, lPassWord) - self.command('cd ' + lSourcePath + '/common/utils/T/tracer/', '\$', 5) - enbLogFile = self.eNBLogFiles[int(self.eNB_instance)] - raw_record_file = enbLogFile.replace('.log', '_record.raw') - replay_log_file = enbLogFile.replace('.log', '_replay.log') - extracted_txt_file = enbLogFile.replace('.log', '_extracted_messages.txt') - extracted_log_file = enbLogFile.replace('.log', '_extracted_messages.log') - self.command('./extract_config -i ' + lSourcePath + '/cmake_targets/' + raw_record_file + ' > ' + lSourcePath + '/cmake_targets/' + extracted_txt_file, '\$', 5) - self.command('echo $USER; nohup ./replay -i ' + lSourcePath + '/cmake_targets/' + raw_record_file + ' > ' + lSourcePath + '/cmake_targets/' + replay_log_file + ' 2>&1 &', lUserName, 5) - self.command('./textlog -d ' + lSourcePath + '/cmake_targets/' + extracted_txt_file + ' -no-gui -ON -full > ' + lSourcePath + '/cmake_targets/' + extracted_log_file, '\$', 5) - self.close() - self.copyin(lIpAddr, lUserName, lPassWord, lSourcePath + '/cmake_targets/' + extracted_log_file, '.') - logging.debug('\u001B[1m Analyzing eNB replay logfile \u001B[0m') - logStatus = self.AnalyzeLogFile_eNB(extracted_log_file) - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - self.eNBLogFiles[int(self.eNB_instance)] = '' - else: - analyzeFile = False - if self.eNBLogFiles[int(self.eNB_instance)] != '': - analyzeFile = True - fileToAnalyze = self.eNBLogFiles[int(self.eNB_instance)] - self.eNBLogFiles[int(self.eNB_instance)] = '' - if analyzeFile: - copyin_res = self.copyin(lIpAddr, lUserName, lPassWord, lSourcePath + '/cmake_targets/' + fileToAnalyze, '.') - if (copyin_res == -1): - logging.debug('\u001B[1;37;41m Could not copy ' + nodeB_prefix + 'NB logfile to analyze it! \u001B[0m') - self.htmleNBFailureMsg = 'Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!' - self.CreateHtmlTestRow('N/A', 'KO', ENB_PROCESS_NOLOGFILE_TO_ANALYZE) - self.eNBmbmsEnables[int(self.eNB_instance)] = False - return - if self.eNB_serverId != '0': - self.copyout(self.eNBIPAddress, self.eNBUserName, self.eNBPassword, './' + fileToAnalyze, self.eNBSourceCodePath + '/cmake_targets/') - logging.debug('\u001B[1m Analyzing ' + nodeB_prefix + 'NB logfile \u001B[0m ' + fileToAnalyze) - logStatus = self.AnalyzeLogFile_eNB(fileToAnalyze) - if (logStatus < 0): - self.CreateHtmlTestRow('N/A', 'KO', logStatus) - self.preamtureExit = True - self.eNBmbmsEnables[int(self.eNB_instance)] = False - return - else: - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - else: - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - self.eNBmbmsEnables[int(self.eNB_instance)] = False - self.eNBstatuses[int(self.eNB_instance)] = -1 - - def TerminateHSS(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGINT oai_hss || true', '\$', 5) - time.sleep(2) - self.command('stdbuf -o0 ps -aux | grep hss | grep -v grep', '\$', 5) - result = re.search('oai_hss -j', str(self.ssh.before)) - if result is not None: - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL oai_hss || true', '\$', 5) - self.command('rm -f ' + self.EPCSourceCodePath + '/scripts/my-hss.sh', '\$', 5) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGINT run_hss oai_hss || true', '\$', 5) - time.sleep(2) - self.command('stdbuf -o0 ps -aux | grep hss | grep -v grep', '\$', 5) - result = re.search('\/bin\/bash .\/run_', str(self.ssh.before)) - if result is not None: - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL run_hss oai_hss || true', '\$', 5) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('cd scripts', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S daemon --name=simulated_hss --stop', '\$', 5) - time.sleep(1) - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL hss_sim', '\$', 5) - else: - logging.error('This should not happen!') - self.close() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - - def TerminateMME(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI', self.EPCType, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGINT run_mme mme || true', '\$', 5) - time.sleep(2) - self.command('stdbuf -o0 ps -aux | grep mme | grep -v grep', '\$', 5) - result = re.search('mme -c', str(self.ssh.before)) - if result is not None: - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL run_mme mme || true', '\$', 5) - self.command('rm -f ' + self.EPCSourceCodePath + '/scripts/my-mme.sh', '\$', 5) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cd /opt/ltebox/tools', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S ./stop_mme', '\$', 5) - else: - logging.error('This should not happen!') - self.close() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) - - def TerminateSPGW(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGINT spgwc spgwu || true', '\$', 5) - time.sleep(2) - self.command('stdbuf -o0 ps -aux | grep spgw | grep -v grep', '\$', 5) - result = re.search('spgwc -c |spgwu -c ', str(self.ssh.before)) - if result is not None: - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL spgwc spgwu || true', '\$', 5) - self.command('rm -f ' + self.EPCSourceCodePath + '/scripts/my-spgw*.sh', '\$', 5) - self.command('stdbuf -o0 ps -aux | grep tshark | grep -v grep', '\$', 5) - result = re.search('-w ', str(self.ssh.before)) - if result is not None: - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGINT tshark || true', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S chmod 666 ' + self.EPCSourceCodePath + '/scripts/*.pcap', '\$', 5) - elif re.match('OAI', self.EPCType, re.IGNORECASE): - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGINT run_spgw spgw || true', '\$', 5) - time.sleep(2) - self.command('stdbuf -o0 ps -aux | grep spgw | grep -v grep', '\$', 5) - result = re.search('\/bin\/bash .\/run_', str(self.ssh.before)) - if result is not None: - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL run_spgw spgw || true', '\$', 5) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cd /opt/ltebox/tools', '\$', 5) - self.command('echo ' + self.EPCPassword + ' | sudo -S ./stop_xGw', '\$', 5) - else: - logging.error('This should not happen!') - self.close() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) def TerminateFlexranCtrl(self): - if self.flexranCtrlInstalled == False or self.flexranCtrlStarted == False: + if RAN.GetflexranCtrlInstalled() == False or RAN.GetflexranCtrlStarted() == False: return - if self.EPCIPAddress == '' or self.EPCUserName == '' or self.EPCPassword == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('echo ' + self.EPCPassword + ' | sudo -S daemon --name=flexran_rtc_daemon --stop', '\$', 5) + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S daemon --name=flexran_rtc_daemon --stop', '\$', 5) time.sleep(1) - self.command('echo ' + self.EPCPassword + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5) + SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5) time.sleep(1) - self.close() - self.flexranCtrlStarted = False - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + SSH.close() + RAN.SetflexranCtrlStarted(False) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def TerminateUE_common(self, device_id, idx): try: - self.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) + SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # back in airplane mode on (ie radio off) if self.ADBCentralized: if device_id == '84B7N16418004022': - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "su - root -c /data/local/tmp/off"', '\$', 60) else: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/off', '\$', 60) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' ' + self.UEDevicesOffCmd[idx], '\$', 60) logging.debug('\u001B[1mUE (' + device_id + ') Detach Completed\u001B[0m') if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "ps | grep --color=never iperf | grep -v grep"', '\$', 5) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "ps | grep --color=never iperf | grep -v grep"', '\$', 5) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ps | grep --color=never iperf | grep -v grep"\'', '\$', 60) - result = re.search('shell +(?P\d+)', str(self.ssh.before)) + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "ps | grep --color=never iperf | grep -v grep"\'', '\$', 60) + result = re.search('shell +(?P\d+)', SSH.getBefore()) if result is not None: pid_iperf = result.group('pid') if self.ADBCentralized: - self.command('stdbuf -o0 adb -s ' + device_id + ' shell "kill -KILL ' + pid_iperf + '"', '\$', 5) + SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell "kill -KILL ' + pid_iperf + '"', '\$', 5) else: - self.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "kill -KILL ' + pid_iperf + '"\'', '\$', 60) - self.close() + SSH.command('ssh ' + self.UEDevicesRemoteUser[idx] + '@' + self.UEDevicesRemoteServer[idx] + ' \'adb -s ' + device_id + ' shell "kill -KILL ' + pid_iperf + '"\'', '\$', 60) + SSH.close() except: os.kill(os.getppid(),signal.SIGUSR1) def TerminateUE(self): - terminate_ue_flag = True + terminate_ue_flag = False self.GetAllUEDevices(terminate_ue_flag) multi_jobs = [] i = 0 for device_id in self.UEDevices: - p = Process(target= SSH.TerminateUE_common, args = (device_id,i,)) + p = Process(target= self.TerminateUE_common, args = (device_id,i,)) p.daemon = True p.start() multi_jobs.append(p) i += 1 for job in multi_jobs: job.join() - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def TerminateOAIUE(self): - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) - self.command('ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) - result = re.search('-uesoftmodem', str(self.ssh.before)) + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) + SSH.command('ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) + result = re.search('-uesoftmodem', SSH.getBefore()) if result is not None: - self.command('echo ' + self.UEPassword + ' | sudo -S killall --signal SIGINT -r .*-uesoftmodem || true', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal SIGINT -r .*-uesoftmodem || true', '\$', 5) time.sleep(10) - self.command('ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) - result = re.search('-uesoftmodem', str(self.ssh.before)) + SSH.command('ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) + result = re.search('-uesoftmodem', SSH.getBefore()) if result is not None: - self.command('echo ' + self.UEPassword + ' | sudo -S killall --signal SIGKILL -r .*-uesoftmodem || true', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal SIGKILL -r .*-uesoftmodem || true', '\$', 5) time.sleep(5) - self.command('rm -f my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) - self.close() + SSH.command('rm -f my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + SSH.close() result = re.search('ue_', str(self.UELogFile)) if result is not None: - copyin_res = self.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/' + self.UELogFile, '.') + copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/' + self.UELogFile, '.') if (copyin_res == -1): logging.debug('\u001B[1;37;41m Could not copy UE logfile to analyze it! \u001B[0m') - self.htmlUEFailureMsg = 'Could not copy UE logfile to analyze it!' - self.CreateHtmlTestRow('N/A', 'KO', OAI_UE_PROCESS_NOLOGFILE_TO_ANALYZE, 'UE') + HTML.SethtmlUEFailureMsg('Could not copy UE logfile to analyze it!') + HTML.CreateHtmlTestRow('N/A', 'KO', CONST.OAI_UE_PROCESS_NOLOGFILE_TO_ANALYZE, 'UE') self.UELogFile = '' return logging.debug('\u001B[1m Analyzing UE logfile \u001B[0m') @@ -3953,56 +2748,64 @@ class SSHConnection(): ueAction = 'Connection' if (logStatus < 0): logging.debug('\u001B[1m' + ueAction + ' Failed \u001B[0m') - self.htmlUEFailureMsg = '' + ueAction + ' Failed\n' + self.htmlUEFailureMsg - self.CreateHtmlTestRow('N/A', 'KO', logStatus, 'UE') - if self.air_interface == 'lte': + HTML.SethtmlUEFailureMsg('' + ueAction + ' Failed\n' + HTML.GethtmlUEFailureMsg()) + HTML.CreateHtmlTestRow('N/A', 'KO', logStatus, 'UE') + if RAN.Getair_interface() == 'lte': # In case of sniffing on commercial eNBs we have random results # Not an error then - if (logStatus != OAI_UE_PROCESS_COULD_NOT_SYNC) or (ueAction != 'Sniffing'): + if (logStatus != CONST.OAI_UE_PROCESS_COULD_NOT_SYNC) or (ueAction != 'Sniffing'): self.Initialize_OAI_UE_args = '' self.AutoTerminateUEandeNB() else: - if (logStatus == OAI_UE_PROCESS_COULD_NOT_SYNC): + if (logStatus == CONST.OAI_UE_PROCESS_COULD_NOT_SYNC): self.Initialize_OAI_UE_args = '' self.AutoTerminateUEandeNB() else: logging.debug('\u001B[1m' + ueAction + ' Completed \u001B[0m') - self.htmlUEFailureMsg = '' + ueAction + ' Completed\n' + self.htmlUEFailureMsg - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.SethtmlUEFailureMsg('' + ueAction + ' Completed\n' + HTML.GethtmlUEFailureMsg()) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) self.UELogFile = '' else: - self.CreateHtmlTestRow('N/A', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def AutoTerminateUEandeNB(self): if (self.ADBIPAddress != 'none'): self.testCase_id = 'AUTO-KILL-UE' + HTML.SettestCase_id(self.testCase_id) self.desc = 'Automatic Termination of UE' + HTML.Setdesc('Automatic Termination of UE') self.ShowTestID() self.TerminateUE() if (self.Initialize_OAI_UE_args != ''): - self.testCase_id = 'AUTO-KILL-UE' - self.desc = 'Automatic Termination of UE' + self.testCase_id = 'AUTO-KILL-OAI-UE' + HTML.SettestCase_id(self.testCase_id) + self.desc = 'Automatic Termination of OAI-UE' + HTML.Setdesc('Automatic Termination of OAI-UE') self.ShowTestID() self.TerminateOAIUE() - if (self.Initialize_eNB_args != ''): + if (RAN.GetInitialize_eNB_args() != ''): self.testCase_id = 'AUTO-KILL-eNB' + HTML.SettestCase_id(self.testCase_id) self.desc = 'Automatic Termination of eNB' + HTML.Setdesc('Automatic Termination of eNB') self.ShowTestID() - self.eNB_instance = '0' - self.TerminateeNB() - if self.flexranCtrlInstalled and self.flexranCtrlStarted: + RAN.SeteNB_instance('0') + RAN.TerminateeNB() + if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): self.testCase_id = 'AUTO-KILL-flexran-ctl' + HTML.SettestCase_id(self.testCase_id) self.desc = 'Automatic Termination of FlexRan CTL' + HTML.Setdesc('Automatic Termination of FlexRan CTL') self.ShowTestID() self.TerminateFlexranCtrl() - self.prematureExit = True + RAN.SetprematureExit(True) def IdleSleep(self): time.sleep(self.idle_sleep_time) - self.CreateHtmlTestRow(str(self.idle_sleep_time) + ' sec', 'OK', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow(str(self.idle_sleep_time) + ' sec', 'OK', CONST.ALL_PROCESSES_OK) def X2_Status(self, idx, fileName): - cmd = "curl --silent http://" + self.EPCIPAddress + ":9999/stats | jq '.' > " + fileName + cmd = "curl --silent http://" + EPC.GetIPAddress() + ":9999/stats | jq '.' > " + fileName message = cmd + '\n' logging.debug(cmd) subprocess.run(cmd, shell=True) @@ -4051,7 +2854,7 @@ class SSHConnection(): logging.debug(msg) fullMessage += msg + '\n' if self.x2_ho_options == 'network': - if self.flexranCtrlInstalled and self.flexranCtrlStarted: + if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): self.x2ENBBsIds = [] self.x2ENBConnectedUEs = [] self.x2ENBBsIds.append([]) @@ -4066,7 +2869,7 @@ class SSHConnection(): eNB_cnt = self.x2NbENBs cnt = 0 while cnt < eNB_cnt: - cmd = "curl -XPOST http://" + self.EPCIPAddress + ":9999/rrc/x2_ho_net_control/enb/" + str(self.x2ENBBsIds[0][cnt]) + "/1" + cmd = "curl -XPOST http://" + EPC.GetIPAddress() + ":9999/rrc/x2_ho_net_control/enb/" + str(self.x2ENBBsIds[0][cnt]) + "/1" logging.debug(cmd) fullMessage += cmd + '\n' subprocess.run(cmd, shell=True) @@ -4080,7 +2883,7 @@ class SSHConnection(): while cnt < eNB_cnt: ueIdx = 0 while ueIdx < len(self.x2ENBConnectedUEs[0][cnt]): - cmd = "curl -XPOST http://" + self.EPCIPAddress + ":9999/rrc/ho/senb/" + str(self.x2ENBBsIds[0][cnt]) + "/ue/" + str(self.x2ENBConnectedUEs[0][cnt][ueIdx]) + "/tenb/" + str(self.x2ENBBsIds[0][eNB_cnt - cnt - 1]) + cmd = "curl -XPOST http://" + EPC.GetIPAddress() + ":9999/rrc/ho/senb/" + str(self.x2ENBBsIds[0][cnt]) + "/ue/" + str(self.x2ENBConnectedUEs[0][cnt][ueIdx]) + "/tenb/" + str(self.x2ENBBsIds[0][eNB_cnt - cnt - 1]) logging.debug(cmd) fullMessage += cmd + '\n' subprocess.run(cmd, shell=True) @@ -4101,22 +2904,22 @@ class SSHConnection(): logging.debug(msg) fullMessage += msg + '' html_queue.put(fullMessage) - self.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) else: msg = "X2 Handover FAILED" logging.error(msg) fullMessage += msg + '' html_queue.put(fullMessage) - self.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) + HTML.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) else: - self.CreateHtmlTestRow('Cannot perform requested X2 Handover', 'KO', ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow('Cannot perform requested X2 Handover', 'KO', CONST.ALL_PROCESSES_OK) def LogCollectBuild(self): - if (self.eNBIPAddress != '' and self.eNBUserName != '' and self.eNBPassword != ''): - IPAddress = self.eNBIPAddress - UserName = self.eNBUserName - Password = self.eNBPassword - SourceCodePath = self.eNBSourceCodePath + if (RAN.GeteNBIPAddress() != '' and RAN.GeteNBUserName() != '' and RAN.GeteNBPassword() != ''): + IPAddress = RAN.GeteNBIPAddress() + UserName = RAN.GeteNBUserName() + Password = RAN.GeteNBPassword() + SourceCodePath = RAN.GeteNBSourceCodePath() elif (self.UEIPAddress != '' and self.UEUserName != '' and self.UEPassword != ''): IPAddress = self.UEIPAddress UserName = self.UEUserName @@ -4124,109 +2927,55 @@ class SSHConnection(): SourceCodePath = self.UESourceCodePath else: sys.exit('Insufficient Parameter') - self.open(IPAddress, UserName, Password) - self.command('cd ' + SourceCodePath, '\$', 5) - self.command('cd cmake_targets', '\$', 5) - self.command('rm -f build.log.zip', '\$', 5) - self.command('zip build.log.zip build_log_*/*', '\$', 60) - self.close() - - def LogCollecteNB(self): - self.open(self.eNBIPAddress, self.eNBUserName, self.eNBPassword) - self.command('cd ' + self.eNBSourceCodePath, '\$', 5) - self.command('cd cmake_targets', '\$', 5) - self.command('echo ' + self.eNBPassword + ' | sudo -S rm -f enb.log.zip', '\$', 5) - self.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 60) - self.command('echo ' + self.eNBPassword + ' | sudo -S rm enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 5) - self.close() - + SSH.open(IPAddress, UserName, Password) + SSH.command('cd ' + SourceCodePath, '\$', 5) + SSH.command('cd cmake_targets', '\$', 5) + SSH.command('rm -f build.log.zip', '\$', 5) + SSH.command('zip build.log.zip build_log_*/*', '\$', 60) + SSH.close() def LogCollectPing(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('cd scripts', '\$', 5) - self.command('rm -f ping.log.zip', '\$', 5) - self.command('zip ping.log.zip ping*.log', '\$', 60) - self.command('rm ping*.log', '\$', 5) - self.close() + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.command('cd scripts', '\$', 5) + SSH.command('rm -f ping.log.zip', '\$', 5) + SSH.command('zip ping.log.zip ping*.log', '\$', 60) + SSH.command('rm ping*.log', '\$', 5) + SSH.close() def LogCollectIperf(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath, '\$', 5) - self.command('cd scripts', '\$', 5) - self.command('rm -f iperf.log.zip', '\$', 5) - self.command('zip iperf.log.zip iperf*.log', '\$', 60) - self.command('rm iperf*.log', '\$', 5) - self.close() - - def LogCollectHSS(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('rm -f hss.log.zip', '\$', 5) - if re.match('OAI', self.EPCType, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('zip hss.log.zip hss*.log', '\$', 60) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm hss*.log', '\$', 5) - if re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('zip hss.log.zip logs/hss*.* *.pcap', '\$', 60) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm -f logs/hss*.* *.pcap', '\$', 5) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cp /opt/hss_sim0609/hss.log .', '\$', 60) - self.command('zip hss.log.zip hss.log', '\$', 60) - else: - logging.error('This option should not occur!') - self.close() - - def LogCollectMME(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('rm -f mme.log.zip', '\$', 5) - if re.match('OAI', self.EPCType, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('zip mme.log.zip mme*.log', '\$', 60) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm mme*.log', '\$', 5) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cp /opt/ltebox/var/log/*Log.0 .', '\$', 5) - self.command('zip mme.log.zip mmeLog.0 s1apcLog.0 s1apsLog.0 s11cLog.0 libLog.0 s1apCodecLog.0', '\$', 60) - else: - logging.error('This option should not occur!') - self.close() - - def LogCollectSPGW(self): - self.open(self.EPCIPAddress, self.EPCUserName, self.EPCPassword) - self.command('cd ' + self.EPCSourceCodePath + '/scripts', '\$', 5) - self.command('rm -f spgw.log.zip', '\$', 5) - if re.match('OAI', self.EPCType, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.EPCType, re.IGNORECASE): - self.command('zip spgw.log.zip spgw*.log', '\$', 60) - self.command('echo ' + self.EPCPassword + ' | sudo -S rm spgw*.log', '\$', 5) - elif re.match('ltebox', self.EPCType, re.IGNORECASE): - self.command('cp /opt/ltebox/var/log/xGwLog.0 .', '\$', 5) - self.command('zip spgw.log.zip xGwLog.0', '\$', 60) - else: - logging.error('This option should not occur!') - self.close() - + SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.command('cd scripts', '\$', 5) + SSH.command('rm -f iperf.log.zip', '\$', 5) + SSH.command('zip iperf.log.zip iperf*.log', '\$', 60) + SSH.command('rm iperf*.log', '\$', 5) + SSH.close() + def LogCollectOAIUE(self): - self.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - self.command('cd ' + self.UESourceCodePath, '\$', 5) - self.command('cd cmake_targets', '\$', 5) - self.command('echo ' + self.UEPassword + ' | sudo -S rm -f ue.log.zip', '\$', 5) - self.command('echo ' + self.UEPassword + ' | sudo -S zip ue.log.zip ue*.log core* ue_*record.raw ue_*.pcap ue_*txt', '\$', 60) - self.command('echo ' + self.UEPassword + ' | sudo -S rm ue*.log core* ue_*record.raw ue_*.pcap ue_*txt', '\$', 5) - self.close() + SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) + SSH.command('cd ' + self.UESourceCodePath, '\$', 5) + SSH.command('cd cmake_targets', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -f ue.log.zip', '\$', 5) + SSH.command('echo ' + self.UEPassword + ' | sudo -S zip ue.log.zip ue*.log core* ue_*record.raw ue_*.pcap ue_*txt', '\$', 60) + SSH.command('echo ' + self.UEPassword + ' | sudo -S rm ue*.log core* ue_*record.raw ue_*.pcap ue_*txt', '\$', 5) + SSH.close() def RetrieveSystemVersion(self, machine): - if self.eNBIPAddress == 'none' or self.UEIPAddress == 'none': - self.OsVersion = 'Ubuntu 16.04.5 LTS' - self.KernelVersion = '4.15.0-45-generic' - self.UhdVersion = '3.13.0.1-0' - self.UsrpBoard = 'B210' - self.CpuNb = '4' - self.CpuModel = 'Intel(R) Core(TM) i5-6200U' - self.CpuMHz = '2399.996 MHz' + if RAN.GeteNBIPAddress() == 'none' or self.UEIPAddress == 'none': + HTML.SetOsVersion('Ubuntu 16.04.5 LTS', 0) + HTML.SetKernelVersion('4.15.0-45-generic', 0) + HTML.SetUhdVersion('3.13.0.1-0', 0) + HTML.SetUsrpBoard('B210', 0) + HTML.SetCpuNb('4', 0) + HTML.SetCpuModel('Intel(R) Core(TM) i5-6200U', 0) + HTML.SetCpuMHz('2399.996 MHz', 0) return 0 if machine == 'eNB': - if self.eNBIPAddress != '' and self.eNBUserName != '' and self.eNBPassword != '': - IPAddress = self.eNBIPAddress - UserName = self.eNBUserName - Password = self.eNBPassword + if RAN.GeteNBIPAddress() != '' and RAN.GeteNBUserName() != '' and RAN.GeteNBPassword() != '': + IPAddress = RAN.GeteNBIPAddress() + UserName = RAN.GeteNBUserName() + Password = RAN.GeteNBPassword() + idx = 0 else: return -1 if machine == 'UE': @@ -4234,386 +2983,73 @@ class SSHConnection(): IPAddress = self.UEIPAddress UserName = self.UEUserName Password = self.UEPassword + idx = 1 else: return -1 - self.open(IPAddress, UserName, Password) - self.command('lsb_release -a', '\$', 5) - result = re.search('Description:\\\\t(?P[a-zA-Z0-9\-\_\.\ ]+)', str(self.ssh.before)) + SSH.open(IPAddress, UserName, Password) + SSH.command('lsb_release -a', '\$', 5) + result = re.search('Description:\\\\t(?P[a-zA-Z0-9\-\_\.\ ]+)', SSH.getBefore()) if result is not None: - self.OsVersion = result.group('os_type') - logging.debug('OS is: ' + self.OsVersion) + OsVersion = result.group('os_type') + logging.debug('OS is: ' + OsVersion) + HTML.SetOsVersion(OsVersion, idx) else: - self.command('hostnamectl', '\$', 5) - result = re.search('Operating System: (?P[a-zA-Z0-9\-\_\.\ ]+)', str(self.ssh.before)) + SSH.command('hostnamectl', '\$', 5) + result = re.search('Operating System: (?P[a-zA-Z0-9\-\_\.\ ]+)', SSH.getBefore()) if result is not None: - self.OsVersion = result.group('os_type') - if self.OsVersion == 'CentOS Linux 7 ': - self.command('cat /etc/redhat-release', '\$', 5) - result = re.search('CentOS Linux release (?P[0-9\.]+)', str(self.ssh.before)) + OsVersion = result.group('os_type') + if OsVersion == 'CentOS Linux 7 ': + SSH.command('cat /etc/redhat-release', '\$', 5) + result = re.search('CentOS Linux release (?P[0-9\.]+)', SSH.getBefore()) if result is not None: - self.OsVersion = self.OsVersion.replace('7 ', result.group('os_version')) - logging.debug('OS is: ' + self.OsVersion) - self.command('uname -r', '\$', 5) - result = re.search('uname -r\\\\r\\\\n(?P[a-zA-Z0-9\-\_\.]+)', str(self.ssh.before)) + OsVersion = OsVersion.replace('7 ', result.group('os_version')) + logging.debug('OS is: ' + OsVersion) + HTML.SetOsVersion(OsVersion, idx) + SSH.command('uname -r', '\$', 5) + result = re.search('uname -r\\\\r\\\\n(?P[a-zA-Z0-9\-\_\.]+)', SSH.getBefore()) if result is not None: - self.KernelVersion = result.group('kernel_version') - logging.debug('Kernel Version is: ' + self.KernelVersion) - self.command('dpkg --list | egrep --color=never libuhd003', '\$', 5) - result = re.search('libuhd003:amd64 *(?P[0-9\.]+)', str(self.ssh.before)) + KernelVersion = result.group('kernel_version') + logging.debug('Kernel Version is: ' + KernelVersion) + HTML.SetKernelVersion(KernelVersion, idx) + SSH.command('dpkg --list | egrep --color=never libuhd003', '\$', 5) + result = re.search('libuhd003:amd64 *(?P[0-9\.]+)', SSH.getBefore()) if result is not None: - self.UhdVersion = result.group('uhd_version') - logging.debug('UHD Version is: ' + self.UhdVersion) + UhdVersion = result.group('uhd_version') + logging.debug('UHD Version is: ' + UhdVersion) + HTML.SetUhdVersion(UhdVersion, idx) else: - self.command('uhd_config_info --version', '\$', 5) - result = re.search('UHD (?P[a-zA-Z0-9\.\-]+)', str(self.ssh.before)) + SSH.command('uhd_config_info --version', '\$', 5) + result = re.search('UHD (?P[a-zA-Z0-9\.\-]+)', SSH.getBefore()) if result is not None: - self.UhdVersion = result.group('uhd_version') - logging.debug('UHD Version is: ' + self.UhdVersion) - self.command('echo ' + Password + ' | sudo -S uhd_find_devices', '\$', 60) - usrp_boards = re.findall('product: ([0-9A-Za-z]+)\\\\r\\\\n', str(self.ssh.before)) + UhdVersion = result.group('uhd_version') + logging.debug('UHD Version is: ' + UhdVersion) + HTML.SetUhdVersion(UhdVersion, idx) + SSH.command('echo ' + Password + ' | sudo -S uhd_find_devices', '\$', 60) + usrp_boards = re.findall('product: ([0-9A-Za-z]+)\\\\r\\\\n', SSH.getBefore()) count = 0 for board in usrp_boards: if count == 0: - self.UsrpBoard = board + UsrpBoard = board else: - self.UsrpBoard += ',' + board + UsrpBoard += ',' + board count += 1 if count > 0: - logging.debug('USRP Board(s) : ' + self.UsrpBoard) - self.command('lscpu', '\$', 5) - result = re.search('CPU\(s\): *(?P[0-9]+).*Model name: *(?P[a-zA-Z0-9\-\_\.\ \(\)]+).*CPU MHz: *(?P[0-9\.]+)', str(self.ssh.before)) + logging.debug('USRP Board(s) : ' + UsrpBoard) + HTML.SetUsrpBoard(UsrpBoard, idx) + SSH.command('lscpu', '\$', 5) + result = re.search('CPU\(s\): *(?P[0-9]+).*Model name: *(?P[a-zA-Z0-9\-\_\.\ \(\)]+).*CPU MHz: *(?P[0-9\.]+)', SSH.getBefore()) if result is not None: - self.CpuNb = result.group('nb_cpus') - logging.debug('nb_cpus: ' + self.CpuNb) - self.CpuModel = result.group('model') - logging.debug('model: ' + self.CpuModel) - self.CpuMHz = result.group('cpu_mhz') + ' MHz' - logging.debug('cpu_mhz: ' + self.CpuMHz) - self.close() - -#----------------------------------------------------------- -# HTML Reporting.... -#----------------------------------------------------------- - def CreateHtmlHeader(self): - if (not self.htmlHeaderCreated): - logging.debug('\u001B[1m----------------------------------------\u001B[0m') - logging.debug('\u001B[1m Creating HTML header \u001B[0m') - logging.debug('\u001B[1m----------------------------------------\u001B[0m') - self.htmlFile = open('test_results.html', 'w') - self.htmlFile.write('\n') - self.htmlFile.write('\n') - self.htmlFile.write('\n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' Test Results for TEMPLATE_JOB_NAME job build #TEMPLATE_BUILD_ID\n') - self.htmlFile.write('\n') - self.htmlFile.write('
\n') - self.htmlFile.write('
\n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write('
\n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' Job Summary -- Job: TEMPLATE_JOB_NAME -- Build-ID: TEMPLATE_BUILD_ID\n') - self.htmlFile.write('
\n') - self.htmlFile.write('
\n') - self.htmlFile.write('
TEMPLATE_STAGE_NAME
\n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if (self.ranAllowMerge): - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if (self.ranAllowMerge): - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if (self.ranAllowMerge): - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if self.ranAllowMerge != '': - commit_message = subprocess.check_output("git log -n1 --pretty=format:\"%s\" " + self.ranCommitID, shell=True, universal_newlines=True) - commit_message = commit_message.strip() - self.htmlFile.write(' \n') - if (self.ranAllowMerge): - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if (self.ranAllowMerge): - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if (self.ranTargetBranch == ''): - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write('
Build Start Time (UTC) TEMPLATE_BUILD_TIME
GIT Repository ' + self.ranRepository + '
Job Trigger Merge-RequestPush to Branch
Source Branch Branch' + self.ranBranch + '
Source Commit ID Commit ID ' + self.ranCommitID + '
Source Commit Message Commit Message ' + commit_message + '
Target Branch develop' + self.ranTargetBranch + '
\n') - - if (self.ADBIPAddress != 'none'): - terminate_ue_flag = True - self.GetAllUEDevices(terminate_ue_flag) - self.GetAllCatMDevices(terminate_ue_flag) - self.htmlUEConnected = len(self.UEDevices) - self.htmlFile.write('

' + str(len(self.UEDevices)) + ' UE(s) is(are) connected to ADB bench server

\n') - self.htmlFile.write('

' + str(len(self.CatMDevices)) + ' CAT-M UE(s) is(are) connected to bench server

\n') - else: - self.UEDevices.append('OAI-UE') - self.htmlUEConnected = len(self.UEDevices) - self.htmlFile.write('

' + str(len(self.UEDevices)) + ' OAI UE(s) is(are) connected to CI bench

\n') - self.htmlFile.write('
\n') - self.htmlFile.write(' \n') - self.htmlFile.write('
\n') - self.htmlFile.close() - - def CreateHtmlTabHeader(self): - if (not self.htmlHeaderCreated): - if (not os.path.isfile('test_results.html')): - self.CreateHtmlHeader() - self.htmlFile = open('test_results.html', 'a') - if (self.nbTestXMLfiles == 1): - self.htmlFile.write('
\n') - self.htmlFile.write('

Test Summary for ' + self.testXMLfiles[0] + '

\n') - else: - self.htmlFile.write('
\n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if (self.htmlUEConnected == -1): - terminate_ue_flag = True - if (self.ADBIPAddress != 'none'): - self.GetAllUEDevices(terminate_ue_flag) - self.GetAllCatMDevices(terminate_ue_flag) - else: - self.UEDevices.append('OAI-UE') - self.htmlUEConnected = len(self.UEDevices) - - i = 0 - while (i < self.htmlUEConnected): - self.htmlFile.write(' \n') - i += 1 - self.htmlFile.write(' \n') - self.htmlHeaderCreated = True - - def CreateHtmlTabFooter(self, passStatus): - if ((not self.htmlFooterCreated) and (self.htmlHeaderCreated)): - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if passStatus: - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write('
Relative Time (ms)Test IdTest DescTest OptionsTest StatusUE' + str(i) + ' Status
Final Tab StatusPASS FAIL
\n') - self.htmlFile.write('
\n') - self.htmlFile.close() - time.sleep(1) - if passStatus: - cmd = "sed -i -e 's/__STATE_" + self.htmlTabNames[0] + "__//' test_results.html" - subprocess.run(cmd, shell=True) - else: - cmd = "sed -i -e 's/__STATE_" + self.htmlTabNames[0] + "__/<\/span>/' test_results.html" - subprocess.run(cmd, shell=True) - self.htmlFooterCreated = False - - def CreateHtmlFooter(self, passStatus): - if (os.path.isfile('test_results.html')): - logging.debug('\u001B[1m----------------------------------------\u001B[0m') - logging.debug('\u001B[1m Creating HTML footer \u001B[0m') - logging.debug('\u001B[1m----------------------------------------\u001B[0m') - - self.htmlFile = open('test_results.html', 'a') - self.htmlFile.write('
\n') - self.htmlFile.write('

\n') - self.htmlFile.write(' \n') - - machines = [ 'eNB', 'UE' ] - for machine in machines: - res = self.RetrieveSystemVersion(machine) - if res == -1: - continue - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - if passStatus: - self.htmlFile.write(' \n') - else: - self.htmlFile.write(' \n') - self.htmlFile.write(' \n') - self.htmlFile.write('
' + str(machine) + ' Server Characteristics
OS Version' + self.OsVersion + 'Kernel Version' + self.KernelVersion + 'UHD Version' + self.UhdVersion + 'USRP Board' + self.UsrpBoard + '
Nb CPUs' + self.CpuNb + 'CPU Model Name' + self.CpuModel + 'CPU Frequency' + self.CpuMHz + '
Final StatusPASS FAIL
\n') - self.htmlFile.write('

\n') - self.htmlFile.write('
End of Test Report -- Copyright 2018 OpenAirInterface. All Rights Reserved.
\n') - self.htmlFile.write('
\n') - self.htmlFile.write('\n') - self.htmlFile.close() - - def CreateHtmlTestRow(self, options, status, processesStatus, machine='eNB'): - if ((not self.htmlFooterCreated) and (self.htmlHeaderCreated)): - currentTime = int(round(time.time() * 1000)) - self.startTime - self.htmlFile.write(' \n') - self.htmlFile.write(' ' + format(currentTime / 1000, '.1f') + '\n') - self.htmlFile.write(' ' + self.testCase_id + '\n') - self.htmlFile.write(' ' + self.desc + '\n') - self.htmlFile.write(' ' + str(options) + '\n') - if (str(status) == 'OK'): - self.htmlFile.write(' ' + str(status) + '\n') - elif (str(status) == 'KO'): - if (processesStatus == 0): - self.htmlFile.write(' ' + str(status) + '\n') - elif (processesStatus == ENB_PROCESS_FAILED): - self.htmlFile.write(' KO - eNB process not found\n') - elif (processesStatus == OAI_UE_PROCESS_FAILED): - self.htmlFile.write(' KO - OAI UE process not found\n') - elif (processesStatus == ENB_PROCESS_SEG_FAULT) or (processesStatus == OAI_UE_PROCESS_SEG_FAULT): - self.htmlFile.write(' KO - ' + machine + ' process ended in Segmentation Fault\n') - elif (processesStatus == ENB_PROCESS_ASSERTION) or (processesStatus == OAI_UE_PROCESS_ASSERTION): - self.htmlFile.write(' KO - ' + machine + ' process ended in Assertion\n') - elif (processesStatus == ENB_PROCESS_REALTIME_ISSUE): - self.htmlFile.write(' KO - ' + machine + ' process faced Real Time issue(s)\n') - elif (processesStatus == ENB_PROCESS_NOLOGFILE_TO_ANALYZE) or (processesStatus == OAI_UE_PROCESS_NOLOGFILE_TO_ANALYZE): - self.htmlFile.write(' OK?\n') - elif (processesStatus == ENB_PROCESS_SLAVE_RRU_NOT_SYNCED): - self.htmlFile.write(' KO - ' + machine + ' Slave RRU could not synch\n') - elif (processesStatus == OAI_UE_PROCESS_COULD_NOT_SYNC): - self.htmlFile.write(' KO - UE could not sync\n') - elif (processesStatus == HSS_PROCESS_FAILED): - self.htmlFile.write(' KO - HSS process not found\n') - elif (processesStatus == MME_PROCESS_FAILED): - self.htmlFile.write(' KO - MME process not found\n') - elif (processesStatus == SPGW_PROCESS_FAILED): - self.htmlFile.write(' KO - SPGW process not found\n') - elif (processesStatus == UE_IP_ADDRESS_ISSUE): - self.htmlFile.write(' KO - Could not retrieve UE IP address\n') - else: - self.htmlFile.write(' ' + str(status) + '\n') - else: - self.htmlFile.write(' ' + str(status) + '\n') - if (len(str(self.htmleNBFailureMsg)) > 2): - cellBgColor = 'white' - result = re.search('ended with|faced real time issues', self.htmleNBFailureMsg) - if result is not None: - cellBgColor = 'red' - else: - result = re.search('showed|Reestablishment|Could not copy eNB logfile', self.htmleNBFailureMsg) - if result is not None: - cellBgColor = 'orange' - self.htmlFile.write(' 
' + self.htmleNBFailureMsg + '
\n') - self.htmleNBFailureMsg = '' - elif (len(str(self.htmlUEFailureMsg)) > 2): - cellBgColor = 'white' - result = re.search('ended with|faced real time issues', self.htmlUEFailureMsg) - if result is not None: - cellBgColor = 'red' - else: - result = re.search('showed|Could not copy UE logfile|oaitun_ue1 interface is either NOT mounted or NOT configured', self.htmlUEFailureMsg) - if result is not None: - cellBgColor = 'orange' - self.htmlFile.write(' 
' + self.htmlUEFailureMsg + '
\n') - self.htmlUEFailureMsg = '' - else: - i = 0 - while (i < self.htmlUEConnected): - self.htmlFile.write(' -\n') - i += 1 - self.htmlFile.write(' \n') - - def CreateHtmlTestRowQueue(self, options, status, ue_status, ue_queue): - if ((not self.htmlFooterCreated) and (self.htmlHeaderCreated)): - currentTime = int(round(time.time() * 1000)) - self.startTime - addOrangeBK = False - self.htmlFile.write(' \n') - self.htmlFile.write(' ' + format(currentTime / 1000, '.1f') + '\n') - self.htmlFile.write(' ' + self.testCase_id + '\n') - self.htmlFile.write(' ' + self.desc + '\n') - self.htmlFile.write(' ' + str(options) + '\n') - if (str(status) == 'OK'): - self.htmlFile.write(' ' + str(status) + '\n') - elif (str(status) == 'KO'): - self.htmlFile.write(' ' + str(status) + '\n') - else: - addOrangeBK = True - self.htmlFile.write(' ' + str(status) + '\n') - i = 0 - while (i < self.htmlUEConnected): - if (i < ue_status): - if (not ue_queue.empty()): - if (addOrangeBK): - self.htmlFile.write(' ' + str(ue_queue.get()).replace('white', 'orange') + '\n') - else: - self.htmlFile.write(' ' + str(ue_queue.get()) + '\n') - else: - self.htmlFile.write(' -\n') - else: - self.htmlFile.write(' -\n') - i += 1 - self.htmlFile.write(' \n') + CpuNb = result.group('nb_cpus') + logging.debug('nb_cpus: ' + CpuNb) + HTML.SetCpuNb(CpuNb, idx) + CpuModel = result.group('model') + logging.debug('model: ' + CpuModel) + HTML.SetCpuModel(CpuModel, idx) + CpuMHz = result.group('cpu_mhz') + ' MHz' + logging.debug('cpu_mhz: ' + CpuMHz) + HTML.SetCpuMHz(CpuMHz, idx) + SSH.close() #----------------------------------------------------------- # ShowTestID() @@ -4624,50 +3060,6 @@ class SSHConnection(): logging.debug('\u001B[1m' + self.desc + '\u001B[0m') logging.debug('\u001B[1m----------------------------------------\u001B[0m') -#----------------------------------------------------------- -# Usage() -#----------------------------------------------------------- -def Usage(): - print('----------------------------------------------------------------------------------------------------------------------') - print('main.py Ver:' + Version) - print('----------------------------------------------------------------------------------------------------------------------') - print('Usage: python main.py [options]') - print(' --help Show this help.') - print(' --mode=[Mode]') - print(' TesteNB') - print(' InitiateHtml, FinalizeHtml') - print(' TerminateeNB, TerminateUE, TerminateHSS, TerminateMME, TerminateSPGW') - print(' LogCollectBuild, LogCollecteNB, LogCollectHSS, LogCollectMME, LogCollectSPGW, LogCollectPing, LogCollectIperf') - print('---------------------------------------------------------------------------------------------------- Git Options --') - print(' --ranRepository=[OAI RAN Repository URL]') - print(' --ranBranch=[OAI RAN Repository Branch]') - print(' --ranCommitID=[OAI RAN Repository Commit SHA-1]') - print(' --ranAllowMerge=[Allow Merge Request (with target branch) (true or false)]') - print(' --ranTargetBranch=[Target Branch in case of a Merge Request]') - print('--------------------------------------------------------------------------------------------- eNB Server Options --') - print(' --eNBIPAddress=[eNB\'s IP Address]') - print(' --eNBUserName=[eNB\'s Login User Name]') - print(' --eNBPassword=[eNB\'s Login Password]') - print(' --eNBSourceCodePath=[eNB\'s Source Code Path]') - print('------------------------------------------------------------------------------------------ OAI UE Server Options --') - print(' --UEIPAddress=[UE\'s IP Address]') - print(' --UEUserName=[UE\'s Login User Name]') - print(' --UEPassword=[UE\'s Login Password]') - print(' --UESourceCodePath=[UE\'s Source Code Path]') - print('--------------------------------------------------------------------------------------------- EPC Server Options --') - print(' --EPCIPAddress=[EPC\'s IP Address]') - print(' --EPCUserName=[EPC\'s Login User Name]') - print(' --EPCPassword=[EPC\'s Login Password]') - print(' --EPCSourceCodePath=[EPC\'s Source Code Path]') - print(' --EPCType=[EPC\'s Type: OAI or ltebox or OAI-Rel14-CUPS]') - print('--------------------------------------------------------------------------------------------- ABD Server Options --') - print(' --ADBIPAddress=[ADB\'s IP Address]') - print(' --ADBUserName=[ADB\'s Login User Name]') - print(' --ADBPassword=[ADB\'s Login Password]') - print('----------------------------------------------------------------------------------------------------------------------') - print(' --XMLTestFile=[XML Test File to be run]') - print('----------------------------------------------------------------------------------------------------------------------') - def CheckClassValidity(action,id): if action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': logging.debug('ERROR: test-case ' + id + ' has wrong class ' + action) @@ -4676,143 +3068,145 @@ def CheckClassValidity(action,id): def GetParametersFromXML(action): if action == 'Build_eNB': - SSH.Build_eNB_args = test.findtext('Build_eNB_args') + RAN.SetBuild_eNB_args(test.findtext('Build_eNB_args')) forced_workspace_cleanup = test.findtext('forced_workspace_cleanup') if (forced_workspace_cleanup is None): - SSH.Build_eNB_forced_workspace_cleanup = False + RAN.SetBuild_eNB_forced_workspace_cleanup(False) else: if re.match('true', forced_workspace_cleanup, re.IGNORECASE): - SSH.Build_eNB_forced_workspace_cleanup = True + RAN.SetBuild_eNB_forced_workspace_cleanup(True) else: - SSH.Build_eNB_forced_workspace_cleanup = False - SSH.eNB_instance = test.findtext('eNB_instance') - if (SSH.eNB_instance is None): - SSH.eNB_instance = '0' - SSH.eNB_serverId = test.findtext('eNB_serverId') - if (SSH.eNB_serverId is None): - SSH.eNB_serverId = '0' + RAN.SetBuild_eNB_forced_workspace_cleanup(False) + RAN.SeteNB_instance(test.findtext('eNB_instance')) + if (RAN.GeteNB_instance() is None): + RAN.SeteNB_instance('0') + RAN.SeteNB_serverId(test.findtext('eNB_serverId')) + if (RAN.GeteNB_serverId() is None): + RAN.SeteNB_serverId('0') xmlBgBuildField = test.findtext('backgroundBuild') if (xmlBgBuildField is None): - SSH.backgroundBuild = False + RAN.SetbackgroundBuild(False) else: if re.match('true', xmlBgBuildField, re.IGNORECASE): - SSH.backgroundBuild = True + RAN.SetbackgroundBuild(True) else: - SSH.backgroundBuild = False + RAN.SetbackgroundBuild(False) if action == 'WaitEndBuild_eNB': - SSH.Build_eNB_args = test.findtext('Build_eNB_args') - SSH.eNB_instance = test.findtext('eNB_instance') - if (SSH.eNB_instance is None): - SSH.eNB_instance = '0' - SSH.eNB_serverId = test.findtext('eNB_serverId') - if (SSH.eNB_serverId is None): - SSH.eNB_serverId = '0' + RAN.SetBuild_eNB_args(test.findtext('Build_eNB_args')) + RAN.SeteNB_instance(test.findtext('eNB_instance')) + if (RAN.GeteNB_instance() is None): + RAN.SeteNB_instance('0') + RAN.SeteNB_serverId(test.findtext('eNB_serverId')) + if (RAN.GeteNB_serverId() is None): + RAN.SeteNB_serverId('0') if action == 'Initialize_eNB': - SSH.Initialize_eNB_args = test.findtext('Initialize_eNB_args') - SSH.eNB_instance = test.findtext('eNB_instance') - if (SSH.eNB_instance is None): - SSH.eNB_instance = '0' - SSH.eNB_serverId = test.findtext('eNB_serverId') - if (SSH.eNB_serverId is None): - SSH.eNB_serverId = '0' - SSH.air_interface = test.findtext('air_interface') - if (SSH.air_interface is None): - SSH.air_interface = 'lte' + RAN.SetInitialize_eNB_args(test.findtext('Initialize_eNB_args')) + RAN.SeteNB_instance(test.findtext('eNB_instance')) + if (RAN.GeteNB_instance() is None): + RAN.SeteNB_instance('0') + RAN.SeteNB_serverId(test.findtext('eNB_serverId')) + if (RAN.GeteNB_serverId() is None): + RAN.SeteNB_serverId('0') + CiTestObj.air_interface = test.findtext('air_interface') + if (CiTestObj.air_interface is None): + CiTestObj.air_interface = 'lte' else: - SSH.air_interface = SSH.air_interface.lower() + CiTestObj.air_interface = CiTestObj.air_interface.lower() + RAN.Setair_interface(CiTestObj.air_interface) if action == 'Terminate_eNB': - SSH.eNB_instance = test.findtext('eNB_instance') - if (SSH.eNB_instance is None): - SSH.eNB_instance = '0' - SSH.eNB_serverId = test.findtext('eNB_serverId') - if (SSH.eNB_serverId is None): - SSH.eNB_serverId = '0' - SSH.air_interface = test.findtext('air_interface') - if (SSH.air_interface is None): - SSH.air_interface = 'lte' + RAN.SeteNB_instance(test.findtext('eNB_instance')) + if (RAN.GeteNB_instance() is None): + RAN.SeteNB_instance('0') + RAN.SeteNB_serverId(test.findtext('eNB_serverId')) + if (RAN.GeteNB_serverId() is None): + RAN.SeteNB_serverId('0') + CiTestObj.air_interface = test.findtext('air_interface') + if (CiTestObj.air_interface is None): + CiTestObj.air_interface = 'lte' else: - SSH.air_interface = SSH.air_interface.lower() + CiTestObj.air_interface = CiTestObj.air_interface.lower() + RAN.Setair_interface(CiTestObj.air_interface) if action == 'Attach_UE': nbMaxUEtoAttach = test.findtext('nbMaxUEtoAttach') if (nbMaxUEtoAttach is None): - SSH.nbMaxUEtoAttach = -1 + CiTestObj.nbMaxUEtoAttach = -1 else: - SSH.nbMaxUEtoAttach = int(nbMaxUEtoAttach) + CiTestObj.nbMaxUEtoAttach = int(nbMaxUEtoAttach) if action == 'CheckStatusUE': expectedNBUE = test.findtext('expectedNbOfConnectedUEs') if (expectedNBUE is None): - SSH.expectedNbOfConnectedUEs = -1 + CiTestObj.expectedNbOfConnectedUEs = -1 else: - SSH.expectedNbOfConnectedUEs = int(expectedNBUE) + CiTestObj.expectedNbOfConnectedUEs = int(expectedNBUE) if action == 'Build_OAI_UE': - SSH.Build_OAI_UE_args = test.findtext('Build_OAI_UE_args') - SSH.clean_repository = test.findtext('clean_repository') - if (SSH.clean_repository == 'false'): - SSH.clean_repository = False + CiTestObj.Build_OAI_UE_args = test.findtext('Build_OAI_UE_args') + CiTestObj.clean_repository = test.findtext('clean_repository') + if (CiTestObj.clean_repository == 'false'): + CiTestObj.clean_repository = False else: - SSH.clean_repository = True + CiTestObj.clean_repository = True if action == 'Initialize_OAI_UE': - SSH.Initialize_OAI_UE_args = test.findtext('Initialize_OAI_UE_args') - SSH.UE_instance = test.findtext('UE_instance') - if (SSH.UE_instance is None): - SSH.UE_instance = '0' - SSH.air_interface = test.findtext('air_interface') - if (SSH.air_interface is None): - SSH.air_interface = 'lte' + CiTestObj.Initialize_OAI_UE_args = test.findtext('Initialize_OAI_UE_args') + CiTestObj.UE_instance = test.findtext('UE_instance') + if (CiTestObj.UE_instance is None): + CiTestObj.UE_instance = '0' + CiTestObj.air_interface = test.findtext('air_interface') + if (CiTestObj.air_interface is None): + CiTestObj.air_interface = 'lte' else: - SSH.air_interface = SSH.air_interface.lower() + CiTestObj.air_interface = CiTestObj.air_interface.lower() if action == 'Terminate_OAI_UE': - SSH.eNB_instance = test.findtext('UE_instance') - if (SSH.UE_instance is None): - SSH.UE_instance = '0' + RAN.SeteNB_instance(test.findtext('UE_instance')) + if (CiTestObj.UE_instance is None): + CiTestObj.UE_instance = '0' if action == 'Ping' or action == 'Ping_CatM_module': - SSH.ping_args = test.findtext('ping_args') - SSH.ping_packetloss_threshold = test.findtext('ping_packetloss_threshold') + CiTestObj.ping_args = test.findtext('ping_args') + CiTestObj.ping_packetloss_threshold = test.findtext('ping_packetloss_threshold') if action == 'Iperf': - SSH.iperf_args = test.findtext('iperf_args') - SSH.iperf_packetloss_threshold = test.findtext('iperf_packetloss_threshold') - SSH.iperf_profile = test.findtext('iperf_profile') - if (SSH.iperf_profile is None): - SSH.iperf_profile = 'balanced' + CiTestObj.iperf_args = test.findtext('iperf_args') + CiTestObj.iperf_packetloss_threshold = test.findtext('iperf_packetloss_threshold') + CiTestObj.iperf_profile = test.findtext('iperf_profile') + if (CiTestObj.iperf_profile is None): + CiTestObj.iperf_profile = 'balanced' else: - if SSH.iperf_profile != 'balanced' and SSH.iperf_profile != 'unbalanced' and SSH.iperf_profile != 'single-ue': - logging.debug('ERROR: test-case has wrong profile ' + SSH.iperf_profile) - SSH.iperf_profile = 'balanced' - SSH.iperf_options = test.findtext('iperf_options') - if (SSH.iperf_options is None): - SSH.iperf_options = 'check' + if CiTestObj.iperf_profile != 'balanced' and CiTestObj.iperf_profile != 'unbalanced' and CiTestObj.iperf_profile != 'single-ue': + logging.debug('ERROR: test-case has wrong profile ' + CiTestObj.iperf_profile) + CiTestObj.iperf_profile = 'balanced' + CiTestObj.iperf_options = test.findtext('iperf_options') + if (CiTestObj.iperf_options is None): + CiTestObj.iperf_options = 'check' else: - if SSH.iperf_options != 'check' and SSH.iperf_options != 'sink': - logging.debug('ERROR: test-case has wrong option ' + SSH.iperf_options) - SSH.iperf_options = 'check' + if CiTestObj.iperf_options != 'check' and CiTestObj.iperf_options != 'sink': + logging.debug('ERROR: test-case has wrong option ' + CiTestObj.iperf_options) + CiTestObj.iperf_options = 'check' if action == 'IdleSleep': string_field = test.findtext('idle_sleep_time_in_sec') if (string_field is None): - SSH.idle_sleep_time = 5 + CiTestObj.idle_sleep_time = 5 else: - SSH.idle_sleep_time = int(string_field) + CiTestObj.idle_sleep_time = int(string_field) if action == 'Perform_X2_Handover': string_field = test.findtext('x2_ho_options') if (string_field is None): - SSH.x2_ho_options = 'network' + CiTestObj.x2_ho_options = 'network' else: if string_field != 'network': logging.error('ERROR: test-case has wrong option ' + string_field) - SSH.x2_ho_options = 'network' + CiTestObj.x2_ho_options = 'network' else: - SSH.x2_ho_options = string_field + CiTestObj.x2_ho_options = string_field #check if given test is in list @@ -4831,7 +3225,23 @@ def receive_signal(signum, frame): # Parameter Check #----------------------------------------------------------- mode = '' -SSH = SSHConnection() +CiTestObj = OaiCiTest() + +import sshconnection +import epc +import helpreadme as HELP +import ran +import html +import constants + +SSH = sshconnection.SSHConnection() +EPC = epc.EPCManagement() +RAN = ran.RANManagement() +HTML = html.HTMLManagement() + +EPC.SetHtmlObj(HTML) +RAN.SetHtmlObj(HTML) +RAN.SetEpcObj(EPC) argvs = sys.argv argc = len(argvs) @@ -4839,8 +3249,9 @@ cwd = os.getcwd() while len(argvs) > 1: myArgv = argvs.pop(1) # 0th is this file's name + if re.match('^\-\-help$', myArgv, re.IGNORECASE): - Usage() + HELP.GenericHelp(CONST.Version) sys.exit(0) elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE) @@ -4850,7 +3261,9 @@ while len(argvs) > 1: matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE) else: matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) - SSH.ranRepository = matchReg.group(1) + CiTestObj.ranRepository = matchReg.group(1) + RAN.SetranRepository(matchReg.group(1)) + HTML.SetranRepository(matchReg.group(1)) elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) @@ -4858,259 +3271,289 @@ while len(argvs) > 1: matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) doMerge = matchReg.group(1) if ((doMerge == 'true') or (doMerge == 'True')): - SSH.ranAllowMerge = True + CiTestObj.ranAllowMerge = True + RAN.SetranAllowMerge(True) + HTML.SetranAllowMerge(True) elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE) else: matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) - SSH.ranBranch = matchReg.group(1) + CiTestObj.ranBranch = matchReg.group(1) + RAN.SetranBranch(matchReg.group(1)) + HTML.SetranBranch(matchReg.group(1)) elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) else: matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) - SSH.ranCommitID = matchReg.group(1) + CiTestObj.ranCommitID = matchReg.group(1) + RAN.SetranCommitID(matchReg.group(1)) + HTML.SetranCommitID(matchReg.group(1)) elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) else: matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) - SSH.ranTargetBranch = matchReg.group(1) + CiTestObj.ranTargetBranch = matchReg.group(1) + RAN.SetranTargetBranch(matchReg.group(1)) + HTML.SetranTargetBranch(matchReg.group(1)) elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) - SSH.eNBIPAddress = matchReg.group(1) + RAN.SeteNBIPAddress(matchReg.group(1)) elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB1IPAddress = matchReg.group(1) + RAN.SeteNB1IPAddress(matchReg.group(1)) elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB2IPAddress = matchReg.group(1) + RAN.SeteNB2IPAddress(matchReg.group(1)) elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) - SSH.eNBUserName = matchReg.group(1) + RAN.SeteNBUserName(matchReg.group(1)) elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB1UserName = matchReg.group(1) + RAN.SeteNB1UserName(matchReg.group(1)) elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB2UserName = matchReg.group(1) + RAN.SeteNB2UserName(matchReg.group(1)) elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) - SSH.eNBPassword = matchReg.group(1) + RAN.SeteNBPassword(matchReg.group(1)) elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB1Password = matchReg.group(1) + RAN.SeteNB1Password(matchReg.group(1)) elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB2Password = matchReg.group(1) + RAN.SeteNB2Password(matchReg.group(1)) elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) - SSH.eNBSourceCodePath = matchReg.group(1) + RAN.SeteNBSourceCodePath(matchReg.group(1)) elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB1SourceCodePath = matchReg.group(1) + RAN.SeteNB1SourceCodePath(matchReg.group(1)) elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE) - SSH.eNB2SourceCodePath = matchReg.group(1) + RAN.SeteNB2SourceCodePath(matchReg.group(1)) elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) - SSH.EPCIPAddress = matchReg.group(1) - elif re.match('^\-\-EPCBranch=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCBranch=(.+)$', myArgv, re.IGNORECASE) - SSH.EPCBranch = matchReg.group(1) + EPC.SetIPAddress(matchReg.group(1)) elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE) - SSH.EPCUserName = matchReg.group(1) + EPC.SetUserName(matchReg.group(1)) elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE) - SSH.EPCPassword = matchReg.group(1) + EPC.SetPassword(matchReg.group(1)) elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE) - SSH.EPCSourceCodePath = matchReg.group(1) + EPC.SetSourceCodePath(matchReg.group(1)) elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE) - if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE): - SSH.EPCType = matchReg.group(1) + if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE): + EPC.SetType(matchReg.group(1)) else: - sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS)') + sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)') + elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE) + EPC.SetContainerPrefix(matchReg.group(1)) elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE) - SSH.ADBIPAddress = matchReg.group(1) + CiTestObj.ADBIPAddress = matchReg.group(1) elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE) - SSH.ADBUserName = matchReg.group(1) + CiTestObj.ADBUserName = matchReg.group(1) elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE) if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE): if re.match('distributed', matchReg.group(1), re.IGNORECASE): - SSH.ADBCentralized = False + CiTestObj.ADBCentralized = False else: - SSH.ADBCentralized = True + CiTestObj.ADBCentralized = True else: sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)') elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE) - SSH.ADBPassword = matchReg.group(1) + CiTestObj.ADBPassword = matchReg.group(1) elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) - SSH.testXMLfiles.append(matchReg.group(1)) - SSH.nbTestXMLfiles += 1 + CiTestObj.testXMLfiles.append(matchReg.group(1)) + HTML.SettestXMLfiles(matchReg.group(1)) + HTML.SetnbTestXMLfiles(HTML.GetnbTestXMLfiles()+1) elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) - SSH.UEIPAddress = matchReg.group(1) + CiTestObj.UEIPAddress = matchReg.group(1) elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE) - SSH.UEUserName = matchReg.group(1) + CiTestObj.UEUserName = matchReg.group(1) elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE) - SSH.UEPassword = matchReg.group(1) + CiTestObj.UEPassword = matchReg.group(1) elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE) - SSH.UESourceCodePath = matchReg.group(1) + CiTestObj.UESourceCodePath = matchReg.group(1) elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE) finalStatus = matchReg.group(1) if ((finalStatus == 'true') or (finalStatus == 'True')): - SSH.finalStatus = True + CiTestObj.finalStatus = True else: - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Invalid Parameter: ' + myArgv) if re.match('^TerminateeNB$', mode, re.IGNORECASE): - if SSH.eNBIPAddress == '' or SSH.eNBUserName == '' or SSH.eNBPassword == '': - Usage() + if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.eNB_serverId = '0' - SSH.eNB_instance = '0' - SSH.eNBSourceCodePath = '/tmp/' - SSH.TerminateeNB() + RAN.SeteNB_serverId('0') + RAN.SeteNB_instance('0') + RAN.SeteNBSourceCodePath('/tmp/') + RAN.TerminateeNB() elif re.match('^TerminateUE$', mode, re.IGNORECASE): - if (SSH.ADBIPAddress == '' or SSH.ADBUserName == '' or SSH.ADBPassword == ''): - Usage() + if (CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == ''): + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') signal.signal(signal.SIGUSR1, receive_signal) - SSH.TerminateUE() + CiTestObj.TerminateUE() elif re.match('^TerminateOAIUE$', mode, re.IGNORECASE): - if SSH.UEIPAddress == '' or SSH.UEUserName == '' or SSH.UEPassword == '': - Usage() + if CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') signal.signal(signal.SIGUSR1, receive_signal) - SSH.TerminateOAIUE() + CiTestObj.TerminateOAIUE() elif re.match('^TerminateHSS$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.TerminateHSS() + EPC.TerminateHSS() elif re.match('^TerminateMME$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.TerminateMME() + EPC.TerminateMME() elif re.match('^TerminateSPGW$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.TerminateSPGW() + EPC.TerminateSPGW() elif re.match('^LogCollectBuild$', mode, re.IGNORECASE): - if (SSH.eNBIPAddress == '' or SSH.eNBUserName == '' or SSH.eNBPassword == '' or SSH.eNBSourceCodePath == '') and (SSH.UEIPAddress == '' or SSH.UEUserName == '' or SSH.UEPassword == '' or SSH.UESourceCodePath == ''): - Usage() + if (RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '') and (CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == ''): + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectBuild() + CiTestObj.LogCollectBuild() elif re.match('^LogCollecteNB$', mode, re.IGNORECASE): - if SSH.eNBIPAddress == '' or SSH.eNBUserName == '' or SSH.eNBPassword == '' or SSH.eNBSourceCodePath == '': - Usage() + if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollecteNB() + RAN.LogCollecteNB() elif re.match('^LogCollectHSS$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectHSS() + EPC.LogCollectHSS() elif re.match('^LogCollectMME$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectMME() + EPC.LogCollectMME() elif re.match('^LogCollectSPGW$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectSPGW() + EPC.LogCollectSPGW() elif re.match('^LogCollectPing$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectPing() + CiTestObj.LogCollectPing() elif re.match('^LogCollectIperf$', mode, re.IGNORECASE): - if SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCSourceCodePath == '': - Usage() + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectIperf() + CiTestObj.LogCollectIperf() elif re.match('^LogCollectOAIUE$', mode, re.IGNORECASE): - if SSH.UEIPAddress == '' or SSH.UEUserName == '' or SSH.UEPassword == '' or SSH.UESourceCodePath == '': - Usage() + if CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == '': + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.LogCollectOAIUE() + CiTestObj.LogCollectOAIUE() elif re.match('^InitiateHtml$', mode, re.IGNORECASE): - if (SSH.ADBIPAddress == '' or SSH.ADBUserName == '' or SSH.ADBPassword == ''): - Usage() + if (CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == ''): + HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') count = 0 foundCount = 0 - while (count < SSH.nbTestXMLfiles): - xml_test_file = cwd + "/" + SSH.testXMLfiles[count] + while (count < HTML.GetnbTestXMLfiles()): + #xml_test_file = cwd + "/" + CiTestObj.testXMLfiles[count] + xml_test_file = sys.path[0] + "/" + CiTestObj.testXMLfiles[count] if (os.path.isfile(xml_test_file)): try: xmlTree = ET.parse(xml_test_file) except: print("Error while parsing file: " + xml_test_file) xmlRoot = xmlTree.getroot() - SSH.htmlTabRefs.append(xmlRoot.findtext('htmlTabRef',default='test-tab-' + str(count))) - SSH.htmlTabNames.append(xmlRoot.findtext('htmlTabName',default='Test-' + str(count))) - SSH.htmlTabIcons.append(xmlRoot.findtext('htmlTabIcon',default='info-sign')) + HTML.SethtmlTabRefs(xmlRoot.findtext('htmlTabRef',default='test-tab-' + str(count))) + HTML.SethtmlTabNames(xmlRoot.findtext('htmlTabName',default='test-tab-' + str(count))) + HTML.SethtmlTabIcons(xmlRoot.findtext('htmlTabIcon',default='info-sign')) foundCount += 1 count += 1 - if foundCount != SSH.nbTestXMLfiles: - SSH.nbTestXMLfiles = foundCount - SSH.CreateHtmlHeader() + if foundCount != HTML.GetnbTestXMLfiles(): + HTML.SetnbTestXMLfiles(foundcount) + + if (CiTestObj.ADBIPAddress != 'none'): + terminate_ue_flag = False + CiTestObj.GetAllUEDevices(terminate_ue_flag) + CiTestObj.GetAllCatMDevices(terminate_ue_flag) + HTML.SethtmlUEConnected(len(CiTestObj.UEDevices) + len(CiTestObj.CatMDevices)) + HTML.SethtmlNb_Smartphones(len(CiTestObj.UEDevices)) + HTML.SethtmlNb_CATM_Modules(len(CiTestObj.CatMDevices)) + HTML.CreateHtmlHeader(CiTestObj.ADBIPAddress) elif re.match('^FinalizeHtml$', mode, re.IGNORECASE): - SSH.CreateHtmlFooter(SSH.finalStatus) + logging.debug('\u001B[1m----------------------------------------\u001B[0m') + logging.debug('\u001B[1m Creating HTML footer \u001B[0m') + logging.debug('\u001B[1m----------------------------------------\u001B[0m') + + CiTestObj.RetrieveSystemVersion('eNB') + CiTestObj.RetrieveSystemVersion('UE') + HTML.CreateHtmlFooter(CiTestObj.finalStatus) elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re.IGNORECASE): if re.match('^TesteNB$', mode, re.IGNORECASE): - if SSH.eNBIPAddress == '' or SSH.ranRepository == '' or SSH.ranBranch == '' or SSH.eNBUserName == '' or SSH.eNBPassword == '' or SSH.eNBSourceCodePath == '' or SSH.EPCIPAddress == '' or SSH.EPCUserName == '' or SSH.EPCPassword == '' or SSH.EPCType == '' or SSH.EPCSourceCodePath == '' or SSH.ADBIPAddress == '' or SSH.ADBUserName == '' or SSH.ADBPassword == '': - Usage() + if RAN.GeteNBIPAddress() == '' or RAN.GetranRepository() == '' or RAN.GetranBranch() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '' or EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '' or CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == '': + HELP.GenericHelp(CONST.Version) + if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or EPC.GetType() == '': + HELP.EPCSrvHelp(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath(), EPC.GetType()) + if RAN.GetranRepository() == '': + HELP.GitSrvHelp(RAN.GetranRepository(), RAN.GetranBranch(), RAN.GetranCommitID(), RAN.GetranAllowMerge(), RAN.GetranTargetBranch()) + if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '': + HELP.eNBSrvHelp(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath()) sys.exit('Insufficient Parameter') - if (SSH.EPCIPAddress != '') and (SSH.EPCIPAddress != 'none'): - SSH.copyout(SSH.EPCIPAddress, SSH.EPCUserName, SSH.EPCPassword, cwd + "/tcp_iperf_stats.awk", "/tmp") - SSH.copyout(SSH.EPCIPAddress, SSH.EPCUserName, SSH.EPCPassword, cwd + "/active_net_interfaces.awk", "/tmp") + if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'): + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), cwd + "/tcp_iperf_stats.awk", "/tmp") + SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), cwd + "/active_net_interfaces.awk", "/tmp") else: - if SSH.UEIPAddress == '' or SSH.ranRepository == '' or SSH.ranBranch == '' or SSH.UEUserName == '' or SSH.UEPassword == '' or SSH.UESourceCodePath == '': - Usage() + if CiTestObj.UEIPAddress == '' or CiTestObj.ranRepository == '' or CiTestObj.ranBranch == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == '': + HELP.GenericHelp(CONST.Version) sys.exit('UE: Insufficient Parameter') #read test_case_list.xml file # if no parameters for XML file, use default value - if (SSH.nbTestXMLfiles != 1): + if (HTML.GetnbTestXMLfiles() != 1): xml_test_file = cwd + "/test_case_list.xml" else: - xml_test_file = cwd + "/" + SSH.testXMLfiles[0] + xml_test_file = cwd + "/" + CiTestObj.testXMLfiles[0] xmlTree = ET.parse(xml_test_file) xmlRoot = xmlTree.getroot() exclusion_tests=xmlRoot.findtext('TestCaseExclusionList',default='') requested_tests=xmlRoot.findtext('TestCaseRequestedList',default='') - if (SSH.nbTestXMLfiles == 1): - SSH.htmlTabRefs.append(xmlRoot.findtext('htmlTabRef',default='test-tab-0')) - SSH.htmlTabNames.append(xmlRoot.findtext('htmlTabName',default='Test-0')) + if (HTML.GetnbTestXMLfiles() == 1): + HTML.SethtmlTabRefs(xmlRoot.findtext('htmlTabRef',default='test-tab-0')) + HTML.SethtmlTabNames(xmlRoot.findtext('htmlTabName',default='Test-0')) repeatCount = xmlRoot.findtext('repeatCount',default='1') - SSH.repeatCounts.append(int(repeatCount)) + CiTestObj.repeatCounts.append(int(repeatCount)) all_tests=xmlRoot.findall('testCase') exclusion_tests=exclusion_tests.split() @@ -5136,8 +3579,9 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re else: logging.debug('ERROR: requested test is invalidly formatted: ' + test) sys.exit(1) - if (SSH.EPCIPAddress != '') and (SSH.EPCIPAddress != 'none'): - SSH.CheckFlexranCtrlInstallation() + if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'): + CiTestObj.CheckFlexranCtrlInstallation() + EPC.SetMmeIPAddress() #get the list of tests to be done todo_tests=[] @@ -5150,108 +3594,125 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re signal.signal(signal.SIGUSR1, receive_signal) - SSH.CreateHtmlTabHeader() + if (CiTestObj.ADBIPAddress != 'none'): + terminate_ue_flag = False + CiTestObj.GetAllUEDevices(terminate_ue_flag) + CiTestObj.GetAllCatMDevices(terminate_ue_flag) + else: + CiTestObj.UEDevices.append('OAI-UE') + HTML.SethtmlUEConnected(len(CiTestObj.UEDevices) + len(CiTestObj.CatMDevices)) + HTML.CreateHtmlTabHeader() - cnt = 0 - SSH.prematureExit = True - SSH.startTime = int(round(time.time() * 1000)) - while cnt < SSH.repeatCounts[0] and SSH.prematureExit: - SSH.prematureExit = False + CiTestObj.FailReportCnt = 0 + RAN.SetprematureExit(True) + HTML.SetstartTime(int(round(time.time() * 1000))) + while CiTestObj.FailReportCnt < CiTestObj.repeatCounts[0] and RAN.GetprematureExit(): + RAN.SetprematureExit(False) + # At every iteratin of the retry loop, a separator will be added + # pass CiTestObj.FailReportCnt as parameter of HTML.CreateHtmlRetrySeparator + HTML.CreateHtmlRetrySeparator(CiTestObj.FailReportCnt) for test_case_id in todo_tests: - if SSH.prematureExit: + if RAN.GetprematureExit(): break for test in all_tests: - if SSH.prematureExit: + if RAN.GetprematureExit(): break id = test.get('id') if test_case_id != id: continue - SSH.testCase_id = id - SSH.desc = test.findtext('desc') + CiTestObj.testCase_id = id + HTML.SettestCase_id(CiTestObj.testCase_id) + EPC.SetTestCase_id(CiTestObj.testCase_id) + CiTestObj.desc = test.findtext('desc') + HTML.Setdesc(CiTestObj.desc) action = test.findtext('class') if (CheckClassValidity(action, id) == False): continue - SSH.ShowTestID() + CiTestObj.ShowTestID() GetParametersFromXML(action) if action == 'Initialize_UE' or action == 'Attach_UE' or action == 'Detach_UE' or action == 'Ping' or action == 'Iperf' or action == 'Reboot_UE' or action == 'DataDisable_UE' or action == 'DataEnable_UE' or action == 'CheckStatusUE': - if (SSH.ADBIPAddress != 'none'): + if (CiTestObj.ADBIPAddress != 'none'): terminate_ue_flag = False - SSH.GetAllUEDevices(terminate_ue_flag) + CiTestObj.GetAllUEDevices(terminate_ue_flag) if action == 'Build_eNB': - SSH.BuildeNB() + RAN.BuildeNB() elif action == 'WaitEndBuild_eNB': - SSH.WaitBuildeNBisFinished() + RAN.WaitBuildeNBisFinished() elif action == 'Initialize_eNB': - SSH.InitializeeNB() + check_eNB = False + check_OAI_UE = False + RAN.SetpStatus(CiTestObj.CheckProcessExist(check_eNB, check_OAI_UE)) + + RAN.InitializeeNB() elif action == 'Terminate_eNB': - SSH.TerminateeNB() + RAN.TerminateeNB() elif action == 'Initialize_UE': - SSH.InitializeUE() + CiTestObj.InitializeUE() elif action == 'Terminate_UE': - SSH.TerminateUE() + CiTestObj.TerminateUE() elif action == 'Attach_UE': - SSH.AttachUE() + CiTestObj.AttachUE() elif action == 'Detach_UE': - SSH.DetachUE() + CiTestObj.DetachUE() elif action == 'DataDisable_UE': - SSH.DataDisableUE() + CiTestObj.DataDisableUE() elif action == 'DataEnable_UE': - SSH.DataEnableUE() + CiTestObj.DataEnableUE() elif action == 'CheckStatusUE': - SSH.CheckStatusUE() + CiTestObj.CheckStatusUE() elif action == 'Build_OAI_UE': - SSH.BuildOAIUE() + CiTestObj.BuildOAIUE() elif action == 'Initialize_OAI_UE': - SSH.InitializeOAIUE() + CiTestObj.InitializeOAIUE() elif action == 'Terminate_OAI_UE': - SSH.TerminateOAIUE() + CiTestObj.TerminateOAIUE() elif action == 'Initialize_CatM_module': - SSH.InitializeCatM() + CiTestObj.InitializeCatM() elif action == 'Terminate_CatM_module': - SSH.TerminateCatM() + CiTestObj.TerminateCatM() elif action == 'Attach_CatM_module': - SSH.AttachCatM() + CiTestObj.AttachCatM() elif action == 'Detach_CatM_module': - SSH.TerminateCatM() + CiTestObj.TerminateCatM() elif action == 'Ping_CatM_module': - SSH.PingCatM() + CiTestObj.PingCatM() elif action == 'Ping': - SSH.Ping() + CiTestObj.Ping() elif action == 'Iperf': - SSH.Iperf() + CiTestObj.Iperf() elif action == 'Reboot_UE': - SSH.RebootUE() + CiTestObj.RebootUE() elif action == 'Initialize_HSS': - SSH.InitializeHSS() + EPC.InitializeHSS() elif action == 'Terminate_HSS': - SSH.TerminateHSS() + EPC.TerminateHSS() elif action == 'Initialize_MME': - SSH.InitializeMME() + EPC.InitializeMME() elif action == 'Terminate_MME': - SSH.TerminateMME() + EPC.TerminateMME() elif action == 'Initialize_SPGW': - SSH.InitializeSPGW() + EPC.InitializeSPGW() elif action == 'Terminate_SPGW': - SSH.TerminateSPGW() + EPC.TerminateSPGW() elif action == 'Initialize_FlexranCtrl': - SSH.InitializeFlexranCtrl() + CiTestObj.InitializeFlexranCtrl() elif action == 'Terminate_FlexranCtrl': - SSH.TerminateFlexranCtrl() + CiTestObj.TerminateFlexranCtrl() elif action == 'IdleSleep': - SSH.IdleSleep() + CiTestObj.IdleSleep() elif action == 'Perform_X2_Handover': - SSH.Perform_X2_Handover() + CiTestObj.Perform_X2_Handover() else: sys.exit('Invalid action') - cnt += 1 - if cnt == SSH.repeatCounts[0] and SSH.prematureExit: - logging.debug('Testsuite failed ' + str(cnt) + ' time(s)') - SSH.CreateHtmlTabFooter(False) + CiTestObj.FailReportCnt += 1 + if CiTestObj.FailReportCnt == CiTestObj.repeatCounts[0] and RAN.GetprematureExit(): + logging.debug('Testsuite failed ' + str(CiTestObj.FailReportCnt) + ' time(s)') + HTML.CreateHtmlTabFooter(False) sys.exit('Failed Scenario') else: - logging.info('Testsuite passed after ' + str(cnt) + ' time(s)') - SSH.CreateHtmlTabFooter(True) + logging.info('Testsuite passed after ' + str(CiTestObj.FailReportCnt) + ' time(s)') + HTML.CreateHtmlTabFooter(True) else: - Usage() + HELP.GenericHelp(CONST.Version) sys.exit('Invalid mode') sys.exit(0) diff --git a/ci-scripts/reportBuildLocally.sh b/ci-scripts/reportBuildLocally.sh index 54372ac6ba..0a75ff25b7 100755 --- a/ci-scripts/reportBuildLocally.sh +++ b/ci-scripts/reportBuildLocally.sh @@ -492,6 +492,77 @@ function report_build { awk '{print " "$1""}' ./oai_rules_result_list.txt >> ./build_results.html echo " " >> ./build_results.html echo "
" >> ./build_results.html + echo "
" >> ./build_results.html + fi + if [ -f ./header-files-w-incorrect-define.txt ] + then + NB_FILES_IN_ERROR=`wc -l ./header-files-w-incorrect-define.txt | sed -e "s@ .*@@"` + if [ $NB_FILES_IN_ERROR -eq 0 ] + then + echo "
" >> ./build_results.html + if [ $MR_TRIG -eq 1 ]; then echo " No Issue for CIRCULAR DEPENDENCY PROTECTION in modified files" >> ./build_results.html; fi + if [ $PU_TRIG -eq 1 ]; then echo " No Issue for CIRCULAR DEPENDENCY PROTECTION in the whole repository" >> ./build_results.html; fi + echo "
" >> ./build_results.html + else + echo "
" >> ./build_results.html + if [ $MR_TRIG -eq 1 ]; then echo " ${NB_FILES_IN_ERROR} modified files MAY NOT HAVE CIRCULAR DEPENDENCY PROTECTION" >> ./build_results.html; fi + if [ $PU_TRIG -eq 1 ]; then echo " ${NB_FILES_IN_ERROR} files in repository MAY NOT HAVE CIRCULAR DEPENDENCY PROTECTION in the whole repository" >> ./build_results.html; fi + echo "
" >> ./build_results.html + echo " " >> ./build_results.html + echo "
" >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + awk '{if($0 ~/error in/){print " "};if($0 ~/files with same/){print " "}}' ./header-files-w-incorrect-define.txt >> ./build_results.html + echo "
Potential IssueImpacted FileIncorrect Macro
error in declaration"$4""$5"
files with same #define"$5""$6"
" >> ./build_results.html + echo "
" >> ./build_results.html + echo "
" >> ./build_results.html + fi + fi + if [ -f ./files-w-gnu-gpl-license-banner.txt ] + then + NB_FILES_IN_ERROR=`wc -l ./files-w-gnu-gpl-license-banner.txt | sed -e "s@ .*@@"` + if [ $NB_FILES_IN_ERROR -ne 0 ] + then + echo "
" >> ./build_results.html + if [ $MR_TRIG -eq 1 ]; then echo " ${NB_FILES_IN_ERROR} modified files HAVE a GNU GPL license banner" >> ./build_results.html; fi + if [ $PU_TRIG -eq 1 ]; then echo " ${NB_FILES_IN_ERROR} files in repository HAVE a GNU GPL license banner" >> ./build_results.html; fi + echo "
" >> ./build_results.html + echo " " >> ./build_results.html + echo "
" >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + awk '{print " "}' ./files-w-gnu-gpl-license-banner.txt >> ./build_results.html + echo "
Filename
"$1"
" >> ./build_results.html + echo "
" >> ./build_results.html + echo "
" >> ./build_results.html + fi + fi + if [ -f ./files-w-suspect-banner.txt ] + then + NB_FILES_IN_ERROR=`wc -l ./files-w-suspect-banner.txt | sed -e "s@ .*@@"` + if [ $NB_FILES_IN_ERROR -ne 0 ] + then + echo "
" >> ./build_results.html + if [ $MR_TRIG -eq 1 ]; then echo " ${NB_FILES_IN_ERROR} modified files HAVE a suspect license banner" >> ./build_results.html; fi + if [ $PU_TRIG -eq 1 ]; then echo " ${NB_FILES_IN_ERROR} files in repository HAVE a suspect license banner" >> ./build_results.html; fi + echo "
" >> ./build_results.html + echo " " >> ./build_results.html + echo "
" >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + echo " " >> ./build_results.html + awk '{print " "}' ././files-w-suspect-banner.txt >> ./build_results.html + echo "
Filename
"$1"
" >> ./build_results.html + echo "
" >> ./build_results.html + echo "
" >> ./build_results.html + fi fi fi diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index 502c1a5d47..64af11c8ba 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -342,34 +342,8 @@ function check_iperf { local FILE_COMPLETE=`egrep -c "Server Report" ${LOC_BASE_LOG}_client.txt` if [ $FILE_COMPLETE -eq 0 ] then - # This part will become obsolete once we have UL - if [[ $LOC_IS_RF_SIM -eq 1 ]] && [[ $LOC_IS_NR -eq 1 ]] - then - echo "no UL integration right now --> normal to have no server report" - if [ -f ${LOC_BASE_LOG}_server.txt ] - then - local EFFECTIVE_BANDWIDTH=`tail -n1 ${LOC_BASE_LOG}_server.txt | sed -e "s#^.*MBytes *##" -e "s#^.*KBytes *##" -e "s#sec.*#sec#"` - if [[ $2 =~ .*K.* ]] - then - local BW_PREFIX="K" - else - local BW_PREFIX="M" - fi - if [[ $EFFECTIVE_BANDWIDTH =~ .*${LOC_REQ_BW}.*${BW_PREFIX}bits.* ]] || [[ $EFFECTIVE_BANDWIDTH =~ .*${LOC_REQ_BW_MINUS_ONE}.*${BW_PREFIX}bits.* ]] - then - echo "got requested DL bandwidth: $EFFECTIVE_BANDWIDTH" - else - echo "got LESS than requested DL bandwidth: $EFFECTIVE_BANDWIDTH" - IPERF_STATUS=-1 - fi - else - IPERF_STATUS=-1 - echo "Server File Report not found" - fi - else - IPERF_STATUS=-1 - echo "File Report not found" - fi + IPERF_STATUS=-1 + echo "File Report not found" else if [ `egrep -c "Mbits/sec" ${LOC_BASE_LOG}_client.txt` -ne 0 ] then @@ -2044,81 +2018,117 @@ function run_test_on_vm { if [[ "$RUN_OPTIONS" == "complex" ]] && [[ $VM_NAME =~ .*-rf-sim.* ]] then - NR_STATUS=0 - PING_STATUS=0 - IPERF_STATUS=0 - CN_CONFIG="noS1" CONF_FILE=gnb.band78.tm1.106PRB.usrpn300.conf S1_NOS1_CFG=0 PRB=106 FREQUENCY=3510 + local try_cnt="0" + NR_STATUS=0 + ######### start of loop + while [ $try_cnt -lt 5 ] + do + SYNC_STATUS=0 + PING_STATUS=0 + IPERF_STATUS=0 - echo "############################################################" - echo "${CN_CONFIG} : Starting the gNB" - echo "############################################################" - CURRENT_GNB_LOG_FILE=tdd_${PRB}prb_${CN_CONFIG}_gnb.log - start_rf_sim_gnb $GNB_VM_CMDS "$GNB_VM_IP_ADDR" $CURRENT_GNB_LOG_FILE $PRB $CONF_FILE $S1_NOS1_CFG + echo "############################################################" + echo "${CN_CONFIG} : Starting the gNB" + echo "############################################################" + CURRENT_GNB_LOG_FILE=tdd_${PRB}prb_${CN_CONFIG}_gnb.log + start_rf_sim_gnb $GNB_VM_CMDS "$GNB_VM_IP_ADDR" $CURRENT_GNB_LOG_FILE $PRB $CONF_FILE $S1_NOS1_CFG - echo "############################################################" - echo "${CN_CONFIG} : Starting the NR-UE" - echo "############################################################" - CURRENT_NR_UE_LOG_FILE=tdd_${PRB}prb_${CN_CONFIG}_ue.log - start_rf_sim_nr_ue $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $GNB_VM_IP_ADDR $CURRENT_NR_UE_LOG_FILE $PRB $FREQUENCY $S1_NOS1_CFG - if [ $NR_UE_SYNC -eq 0 ] - then - echo "Problem w/ gNB and NR-UE not syncing" + echo "############################################################" + echo "${CN_CONFIG} : Starting the NR-UE" + echo "############################################################" + CURRENT_NR_UE_LOG_FILE=tdd_${PRB}prb_${CN_CONFIG}_ue.log + start_rf_sim_nr_ue $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $GNB_VM_IP_ADDR $CURRENT_NR_UE_LOG_FILE $PRB $FREQUENCY $S1_NOS1_CFG + if [ $NR_UE_SYNC -eq 0 ] + then + echo "Problem w/ gNB and NR-UE not syncing" + terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 + terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 + SYNC_STATUS=-1 + try_cnt=$[$try_cnt+1] + continue + fi + + echo "############################################################" + echo "${CN_CONFIG} : Pinging the gNB from NR-UE" + echo "############################################################" + get_enb_noS1_ip_addr $GNB_VM_CMDS $GNB_VM_IP_ADDR + PING_LOG_FILE=tdd_${PRB}prb_${CN_CONFIG}_ping_gnb_from_nrue.log + ping_epc_ip_addr $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $ENB_IP_ADDR $PING_LOG_FILE 1 0 + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC + check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + + echo "############################################################" + echo "${CN_CONFIG} : Pinging the NR-UE from gNB" + echo "############################################################" + get_ue_ip_addr $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 1 + PING_LOG_FILE=tdd_${PRB}prb_${CN_CONFIG}_ping_from_gnb_nrue.log + ping_enb_ip_addr $GNB_VM_CMDS $GNB_VM_IP_ADDR $UE_IP_ADDR $PING_LOG_FILE 0 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/$PING_LOG_FILE $ARCHIVES_LOC + check_ping_result $ARCHIVES_LOC/$PING_LOG_FILE 20 + + echo "############################################################" + echo "${CN_CONFIG} : iperf DL -- NR-UE is server and gNB is client" + echo "############################################################" + THROUGHPUT="30K" + CURR_IPERF_LOG_BASE=tdd_${PRB}prb_${CN_CONFIG}_iperf_dl + get_enb_noS1_ip_addr $GNB_VM_CMDS $GNB_VM_IP_ADDR + get_ue_ip_addr $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 1 + generic_iperf $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $UE_IP_ADDR $GNB_VM_CMDS $GNB_VM_IP_ADDR $ENB_IP_ADDR $THROUGHPUT $CURR_IPERF_LOG_BASE 1 0 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_client.txt $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_server.txt $ARCHIVES_LOC + check_iperf $ARCHIVES_LOC/$CURR_IPERF_LOG_BASE $THROUGHPUT + if [ $IPERF_STATUS -ne 0 ] + then + echo "DL test not OK" + terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 + terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 + try_cnt=$[$try_cnt+1] + continue + fi + + echo "############################################################" + echo "${CN_CONFIG} : iperf UL -- gNB is server and NR-UE is client" + echo "############################################################" + THROUGHPUT="30K" + CURR_IPERF_LOG_BASE=tdd_${PRB}prb_${CN_CONFIG}_iperf_ul + get_enb_noS1_ip_addr $GNB_VM_CMDS $GNB_VM_IP_ADDR + get_ue_ip_addr $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 1 + generic_iperf $GNB_VM_CMDS $GNB_VM_IP_ADDR $ENB_IP_ADDR $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $UE_IP_ADDR $THROUGHPUT $CURR_IPERF_LOG_BASE 1 0 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_server.txt $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_client.txt $ARCHIVES_LOC + check_iperf $ARCHIVES_LOC/$CURR_IPERF_LOG_BASE $THROUGHPUT + + echo "############################################################" + echo "${CN_CONFIG} : Terminate gNB/NR-UE simulators" + echo "############################################################" terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC - echo "5G-NR RFSIM seems to FAIL" - echo "5G-NR: TEST_KO" >> $ARCHIVES_LOC/test_final_status.log - STATUS=-1 - return - fi - - echo "############################################################" - echo "${CN_CONFIG} : iperf DL -- NR-UE is server and gNB is client" - echo "############################################################" - THROUGHPUT="30K" - CURR_IPERF_LOG_BASE=tdd_${PRB}prb_${CN_CONFIG}_iperf_dl - get_enb_noS1_ip_addr $GNB_VM_CMDS $GNB_VM_IP_ADDR - get_ue_ip_addr $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 1 - generic_iperf $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $UE_IP_ADDR $GNB_VM_CMDS $GNB_VM_IP_ADDR $ENB_IP_ADDR $THROUGHPUT $CURR_IPERF_LOG_BASE 1 0 - scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_client.txt $ARCHIVES_LOC - scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_server.txt $ARCHIVES_LOC - check_iperf $ARCHIVES_LOC/$CURR_IPERF_LOG_BASE $THROUGHPUT - - echo "############################################################" - echo "${CN_CONFIG} : iperf UL -- gNB is server and NR-UE is client" - echo "############################################################" - THROUGHPUT="30K" - CURR_IPERF_LOG_BASE=tdd_${PRB}prb_${CN_CONFIG}_iperf_ul - get_enb_noS1_ip_addr $GNB_VM_CMDS $GNB_VM_IP_ADDR - get_ue_ip_addr $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 1 - generic_iperf $GNB_VM_CMDS $GNB_VM_IP_ADDR $ENB_IP_ADDR $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR $UE_IP_ADDR $THROUGHPUT $CURR_IPERF_LOG_BASE 1 0 - scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_server.txt $ARCHIVES_LOC - scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/${CURR_IPERF_LOG_BASE}_client.txt $ARCHIVES_LOC - check_iperf $ARCHIVES_LOC/$CURR_IPERF_LOG_BASE $THROUGHPUT - - echo "############################################################" - echo "${CN_CONFIG} : Terminate gNB/NR-UE simulators" - echo "############################################################" - terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 - terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 - scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC - scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC - + if [ $IPERF_STATUS -ne 0 ] + then + echo "UL test not OK" + try_cnt=$[$try_cnt+1] + else + try_cnt=$[$try_cnt+10] + fi + done ######### end of loop full_l2_sim_destroy + echo "############################################################" echo "Checking run status" echo "############################################################" + if [ $SYNC_STATUS -ne 0 ]; then NR_STATUS=-1; fi if [ $PING_STATUS -ne 0 ]; then NR_STATUS=-1; fi if [ $IPERF_STATUS -ne 0 ]; then NR_STATUS=-1; fi if [ $NR_STATUS -eq 0 ] diff --git a/ci-scripts/xml_files/enb_usrp210_band13_test_10mhz_tm1.xml b/ci-scripts/xml_files/enb_usrp210_band13_test_10mhz_tm1.xml index 680f09c435..611492b0bc 100644 --- a/ci-scripts/xml_files/enb_usrp210_band13_test_10mhz_tm1.xml +++ b/ci-scripts/xml_files/enb_usrp210_band13_test_10mhz_tm1.xml @@ -24,7 +24,7 @@ test-lte-m-10-tm1 Test-LTE-M-10MHz-TM1 tasks - 2 + 1 030201 040102 diff --git a/ci-scripts/xml_files/enb_usrp210_band40_test_05mhz_tm2.xml b/ci-scripts/xml_files/enb_usrp210_band40_test_05mhz_tm2.xml index 2a035396c5..09aa0b04a2 100644 --- a/ci-scripts/xml_files/enb_usrp210_band40_test_05mhz_tm2.xml +++ b/ci-scripts/xml_files/enb_usrp210_band40_test_05mhz_tm2.xml @@ -25,7 +25,7 @@ test-05-tm2 Test-05MHz-TM2 tasks - 3 + 2 030201 040101 diff --git a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml index a28a81d970..41e746bc85 100644 --- a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml +++ b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml @@ -33,8 +33,8 @@ IdleSleep - Waiting for 35 seconds - 35 + Waiting for 55 seconds + 55 diff --git a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml index 07cd8fbb30..6ee9247ef3 100644 --- a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml +++ b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml @@ -36,8 +36,8 @@ IdleSleep - Waiting for 45 seconds - 45 + Waiting for 55 seconds + 55 diff --git a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml index 0196bf1ab6..ae348b6b25 100644 --- a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml +++ b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml @@ -46,7 +46,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz) - -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT + -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 diff --git a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml index c2835d0461..b77c6273e6 100644 --- a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml +++ b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml @@ -52,7 +52,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz) - -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT + -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 diff --git a/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml index 964550d872..df41385f83 100644 --- a/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml +++ b/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml @@ -93,7 +93,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz) - -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT + -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 diff --git a/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml b/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml index 22f8b63266..852f48c370 100644 --- a/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml +++ b/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml @@ -64,7 +64,7 @@ Initialize_eNB Initialize eNB #0 (FDD/Band7/5MHz) - -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 123456 + -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 123456 0 0 @@ -72,7 +72,7 @@ Initialize_eNB Initialize eNB #1 (FDD/Band7/5MHz) - -O ci-scripts/conf_files/enb.band7.tm1.25PRB.slave.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 98765 + -O ci-scripts/conf_files/enb.band7.tm1.25PRB.slave.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 98765 1 1 diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 72c7d319db..bb8f9024f9 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -20,9 +20,15 @@ # */ # Author: laurent THOMAS, Lionel GAUTHIER - +###################### FOR CUDA############################# +# author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN: +# Add for PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu +# email tyhsu@cs.nctu.edu.tw +###################### FOR CUDA############################# cmake_minimum_required (VERSION 3.0) + + ############################################## # Base CUDA setting ############################################## @@ -33,7 +39,7 @@ message ("cuda library ${CUDA_LIBRARY_DIRS}") add_definitions("-L/usr/local/cuda/lib64") SET(CUDA_NVCC_FLAGS - "${CUDA_NVCC_FLAGS};-arch=sm_60") + "${CUDA_NVCC_FLAGS};-arch=sm_75;") # Disable warnings for CUDA SET(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS};-lpthread;-w;-O3;--default-stream;per-thread;-I/usr/local/cuda/inc;-L/usr/local/cuda/lib -lcutil;-rdc=true;-lcudadevrt") @@ -186,14 +192,14 @@ endif() # set(CMAKE_C_FLAGS - "${CMAKE_C_FLAGS} ${C_FLAGS_PROCESSOR} -std=gnu99 -Wall -Wstrict-prototypes -fno-strict-aliasing -rdynamic -funroll-loops -Wno-packed-bitfield-compat -fPIC") + "${CMAKE_C_FLAGS} ${C_FLAGS_PROCESSOR} -pipe -std=gnu99 -Wall -Wstrict-prototypes -fno-strict-aliasing -rdynamic -funroll-loops -Wno-packed-bitfield-compat -fPIC") # add autotools definitions that were maybe used! -set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'") +# set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'") set(CMAKE_C_FLAGS - "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER}" + "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP " ) set(CMAKE_CXX_FLAGS - "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11" #-D${MKVER} + "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 " ) add_definitions("-DASN_DISABLE_OER_SUPPORT") @@ -746,7 +752,6 @@ Message("CPU_Affinity flag is ${CPU_AFFINITY}") ############################################################## add_boolean_option(NO_RRM True "DO WE HAVE A RADIO RESSOURCE MANAGER: NO") -add_boolean_option(RRC_DEFAULT_RAB_IS_AM False "set the RLC mode to AM for the default bearer") add_boolean_option(OAI_NW_DRIVER_TYPE_ETHERNET False "????") add_boolean_option(DEADLINE_SCHEDULER True "Use the Linux scheduler SCHED_DEADLINE: kernel >= 3.14") @@ -847,7 +852,7 @@ add_boolean_option(TRACE_RLC_UM_TX_STATUS False "TRACE for RLC UM, TO BE CHANGE ########################## # RRC LAYER OPTIONS ########################## -add_boolean_option(RRC_DEFAULT_RAB_IS_AM False "Otherwise it is UM, configure params are actually set in rrc_eNB.c:rrc_eNB_generate_defaultRRCConnectionReconfiguration(...)") +add_boolean_option(RRC_DEFAULT_RAB_IS_AM True "set the RLC mode to AM for the default bearer, otherwise it is UM.") ########################## @@ -903,6 +908,7 @@ include_directories("${OPENAIR2_DIR}/LAYER2/PDCP_v10.1.0") include_directories("${OPENAIR2_DIR}/RRC/LTE/MESSAGES") include_directories("${OPENAIR2_DIR}/RRC/LTE") include_directories("${OPENAIR_DIR}/common/utils") +include_directories("${OPENAIR_DIR}/common/utils/collection") include_directories("${OPENAIR_DIR}/common/utils/ocp_itti") include_directories("${OPENAIR3_DIR}/NAS/COMMON") include_directories("${OPENAIR3_DIR}/NAS/COMMON/API/NETWORK") @@ -1323,7 +1329,6 @@ set(PHY_TURBOIF set(PHY_LDPC_ORIG_SRC ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c - ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_encoder/ldpc_encoder.c ) @@ -1350,6 +1355,9 @@ add_library(ldpc MODULE ${PHY_LDPC_OPTIM8SEGMULTI_SRC} ) add_library(coding MODULE ${PHY_TURBOSRC} ) +add_library(dfts MODULE ${OPENAIR1_DIR}/PHY/TOOLS/oai_dfts.c ) + + set(PHY_SRC_COMMON ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/lte_mcs.c @@ -1390,7 +1398,7 @@ set(PHY_SRC_COMMON ${OPENAIR1_DIR}/PHY/INIT/lte_parms.c ${OPENAIR1_DIR}/PHY/INIT/lte_param_init.c ${OPENAIR1_DIR}/PHY/TOOLS/cadd_vv.c - ${OPENAIR1_DIR}/PHY/TOOLS/lte_dfts.c + ${OPENAIR1_DIR}/PHY/TOOLS/dfts_load.c ${OPENAIR1_DIR}/PHY/TOOLS/log2_approx.c ${OPENAIR1_DIR}/PHY/TOOLS/cmult_sv.c ${OPENAIR1_DIR}/PHY/TOOLS/cmult_vv.c @@ -1515,6 +1523,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold.c + ${OPENAIR1_DIR}/PHY/NR_REFSIG/scrambling_luts.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c @@ -1536,6 +1545,7 @@ set(PHY_SRC_UE ${PHY_SMALLBLOCKSRC} ${PHY_NR_CODINGIF} ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/pucch_rx.c + ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_uci_tools_common.c ) set(PHY_NR_UE_SRC ${OPENAIR1_DIR}/PHY/INIT/nr_parms.c @@ -1559,6 +1569,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/dci_nr.c ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/dci_tools_nr.c ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/pucch_nr.c + ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_uci_tools_common.c ${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/ul_ref_seq_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -1605,7 +1616,9 @@ endif () add_library(PHY_COMMON ${PHY_SRC_COMMON}) add_dependencies(PHY_COMMON rrc_flag) +add_dependencies(PHY_COMMON dfts) add_library(PHY ${PHY_SRC}) + add_dependencies(PHY rrc_flag) add_library(PHY_UE ${PHY_SRC_UE}) add_dependencies(PHY_UE rrc_flag) @@ -1656,7 +1669,7 @@ set(NR_RRC_DIR ${OPENAIR2_DIR}/RRC/NR) set(NR_UE_RRC_DIR ${OPENAIR2_DIR}/RRC/NR_UE) set(PDCP_DIR ${OPENAIR2_DIR}/LAYER2/PDCP_v10.1.0) -set(LTE_RLC_SRC +set(RLC_V1 ${RLC_AM_DIR}/rlc_am.c ${RLC_AM_DIR}/rlc_am_init.c ${RLC_AM_DIR}/rlc_am_timer_poll_retransmit.c @@ -1686,6 +1699,17 @@ set(LTE_RLC_SRC ${RLC_DIR}/rlc_mpls.c ) +set(RLC_V2 + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_oai_api.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/asn1_utils.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_ue_manager.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_entity.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_entity_am.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_entity_um.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_pdu.c + ${OPENAIR2_DIR}/LAYER2/rlc_v2/rlc_sdu.c + ) + set(NR_RLC_SRC ${OPENAIR2_DIR}/LAYER2/nr_rlc/asn1_utils.c ${OPENAIR2_DIR}/LAYER2/nr_rlc/nr_rlc_entity.c @@ -1720,7 +1744,7 @@ set(L2_SRC ) set(L2_LTE_SRC - ${LTE_RLC_SRC} + ${RLC_V2} ) set(L2_NR_SRC @@ -1757,7 +1781,7 @@ set(LTE_NR_L2_SRC_UE ${PDCP_DIR}/pdcp_util.c ${PDCP_DIR}/pdcp_security.c ${PDCP_DIR}/pdcp_netlink.c - ${LTE_RLC_SRC} + ${RLC_V2} ) set(NR_L2_SRC_UE @@ -2441,9 +2465,9 @@ endif (${T_TRACER}) #This rule and the following deal with it. add_custom_command ( OUTPUT ${OPENAIR_DIR}/common/utils/T/T_IDs.h - COMMAND $(MAKE) clean - COMMAND $(MAKE) - COMMAND $(MAKE) check_vcd + COMMAND make clean + COMMAND make + COMMAND make check_vcd WORKING_DIRECTORY ${OPENAIR_DIR}/common/utils/T DEPENDS ${OPENAIR_DIR}/common/utils/T/T_messages.txt ${OPENAIR_DIR}/common/utils/LOG/vcd_signal_dumper.c @@ -2497,6 +2521,7 @@ add_executable(lte-softmodem ${OPENAIR_TARGETS}/RT/USER/lte-ru.c ${OPENAIR_TARGETS}/RT/USER/ru_control.c ${OPENAIR_TARGETS}/RT/USER/lte-softmodem.c + ${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c ${OPENAIR_DIR}/executables/softmodem-common.c ${OPENAIR2_DIR}/ENB_APP/NB_IoT_interface.c ${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c @@ -2532,6 +2557,43 @@ target_link_libraries (lte-softmodem pthread m ${CONFIG_LIB} rt crypt ${CRYPTO_L target_link_libraries (lte-softmodem ${LIB_LMS_LIBRARIES}) target_link_libraries (lte-softmodem ${T_LIB}) + +add_executable(ocp-enb + ${OPENAIR_DIR}/executables/main-ocp.c + ${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c + ${OPENAIR_DIR}/executables/softmodem-common.c + ${OPENAIR_DIR}/executables/main-fs6.c + ${OPENAIR_DIR}/executables/transport_split.c + ${OPENAIR2_DIR}/ENB_APP/NB_IoT_interface.c + ${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c + ${OPENAIR_TARGETS}/COMMON/create_tasks.c + ${OPENAIR_TARGETS}/COMMON/create_tasks_mbms.c + ${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c + ${OPENAIR_TARGETS}/ARCH/COMMON/record_player.c + ${OPENAIR2_DIR}/RRC/NAS/nas_config.c + ${OPENAIR2_DIR}/RRC/NAS/rb_config.c + ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c + ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/multicast_link.c + ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/socket.c + ${OPENAIR3_DIR}/NAS/UE/nas_ue_task.c + ${OPENAIR_DIR}/common/utils/utils.c + ${OPENAIR_DIR}/common/utils/system.c + ${GTPU_need_ITTI} + ${XFORMSINTERFACE_SOURCE} + ${T_SOURCE} + ${CONFIG_SOURCES} + ${SHLIB_LOADER_SOURCES} + ) +add_dependencies(ocp-enb rrc_flag s1ap_flag x2_flag oai_iqplayer) + +target_link_libraries (ocp-enb + -Wl,--start-group + RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB SCHED_RU_LIB + PHY_COMMON PHY PHY_RU LFDS L2 L2_LTE NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB LFDS7 + ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} ${FSPT_MSG_LIB} ${PROTO_AGENT_LIB} + -Wl,--end-group z dl) +target_link_libraries (ocp-enb ${LIBXML2_LIBRARIES} pthread m ${CONFIG_LIBRARIES} rt crypt ${CRYPTO_LIBRARIES} ${OPENSSL_LIBRARIES} ${NETTLE_LIBRARIES} sctp ${PROTOBUF_LIB} ${CMAKE_DL_LIBS} ${LIBYAML_LIBRARIES} ${LIB_LMS_LIBRARIES} ${T_LIB}) + add_executable(cu_test ${OPENAIR2_DIR}/LAYER2/PROTO_AGENT/cu_test.c ${OPENAIR2_DIR}/LAYER2/PROTO_AGENT/proto_agent_handler.c @@ -2763,46 +2825,38 @@ target_link_libraries(smallblocktest m pthread ${ATLAS_LIBRARIES} dl ) -<<<<<<< HEAD ################################################### # For CUDA library ################################################### CUDA_ADD_LIBRARY(LDPC_CU ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu ) - +CUDA_ADD_CUFFT_TO_TARGET(LDPC_CU) cuda_add_executable(ldpctest -======= -add_executable(ldpctest - ${PHY_NR_CODINGIF} ->>>>>>> origin/develop ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) -<<<<<<< HEAD target_link_libraries(ldpctest -ldl -Wl,--start-group LDPC_CU UTIL SIMU PHY_NR CONFIG_LIB -Wl,--end-group -======= + m pthread ${ATLAS_LIBRARIES} dl + ) + +# add_executable(ldpctest + # ${PHY_NR_CODINGIF} + # ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c + # ${T_SOURCE} + # ${SHLIB_LOADER_SOURCES} + # ) add_dependencies( ldpctest ldpc_orig ldpc_optim ldpc_optim8seg ldpc ) target_link_libraries(ldpctest -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group ->>>>>>> origin/develop m pthread ${ATLAS_LIBRARIES} dl ) -#add_executable(ldpctest -# ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c -# ${T_SOURCE} -# ${SHLIB_LOADER_SOURCES} -# ) -#target_link_libraries(ldpctest -# -Wl,--start-group UTIL SIMU PHY_NR CONFIG_LIB -Wl,--end-group -# m pthread ${ATLAS_LIBRARIES} dl -# ) add_executable(nr_dlschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c @@ -2900,6 +2954,7 @@ foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim pr add_executable(${myExe} ${OPENAIR1_DIR}/SIMULATION/LTE_PHY/${myExe}.c + ${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c ${OPENAIR_DIR}/common/utils/backtrace.c ${OPENAIR_DIR}/common/utils/system.c ${XFORMS_SOURCE} @@ -2990,7 +3045,7 @@ if (${T_TRACER}) PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_COMMON PHY_NR_UE PHY_RU PHY_MEX L2 L2_LTE L2_NR L2_UE NR_L2_UE MAC_NR_COMMON MAC_NR MAC_UE_NR CN_UTILS GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU SIMU_ETH OPENAIR0_LIB - ldpc_orig ldpc_optim ldpc_optim8seg ldpc) + ldpc_orig ldpc_optim ldpc_optim8seg ldpc PROTO_AGENT) if (TARGET ${i}) add_dependencies(${i} generate_T) endif() @@ -3033,7 +3088,7 @@ function(make_driver name dir) endforeach() CONFIGURE_FILE(${OPENAIR_CMAKE}/tools/Kbuild.cmake ${OPENAIR_BIN_DIR}/${name}/Kbuild) add_custom_command(OUTPUT ${name}.ko - COMMAND $(MAKE) -C ${module_build_path} M=${OPENAIR_BIN_DIR}/${name} + COMMAND make -C ${module_build_path} M=${OPENAIR_BIN_DIR}/${name} WORKING_DIRECTORY ${OPENAIR_BIN_DIR}/${name} COMMENT "building ${module}.ko" VERBATIM diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index b3954db1fd..882670727b 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1104,9 +1104,8 @@ -n100 -R217 -a80 -s5 -n100 -R217 -a110 -s5 -b100 -n100 -e27 -s30 - -n100 -e16 -s10 - - nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 + -n100 -e16 -s10 + nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 PDSCH test OK segmentation fault|assertion|exiting|fatal 3 @@ -1177,21 +1176,38 @@ execution - nr_pucchsim Test cases. (Test1: Format 0 ACK miss 106 PRB), - (Test2: Format 1 ACK miss 106 PRB), - (Test3: Format 1 ACK miss 273 PRB), - (Test4: Format 1 NACKtoACK 106 PRB) + nr_pucchsim Test cases. (Test1: Format 0 1-bit ACK miss 106 PRB), + (Test2: Format 0 2-bit ACK miss 106 PRB), + (Test3: Format 0 2-bit ACK miss, 1-bit SR 106 PRB), + (Test4: Format 2 3-bit 106 PRB), + (Test5: Format 2 4-bit 106 PRB), + (Test6: Format 2 5-bit 106 PRB), + (Test7: Format 2 6-bit 106 PRB), + (Test8: Format 2 7-bit 106 PRB), + (Test9: Format 2 8-bit 106 PRB), + (Test10: Format 2 9-bit 106 PRB), + (Test11: Format 2 10-bit 106 PRB), + (Test12: Format 2 11-bit 106 PRB) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash $OPENAIR_DIR/targets/bin/nr_pucchsim.Rel15 - -R 106 -i 1 -P 0 -b 1 -s3 -n100 - -R 106 -i 14 -P 1 -b 1 -s-6 -n100 - -R 273 -i 14 -P 1 -b 1 -s-6 -n100 - -R 106 -i 14 -P 1 -b 1 -s-6 -T 0.001 -n1000 - nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 + -R 106 -i 1 -P 0 -b 1 -s-2 -n1000 + -R 106 -i 1 -P 0 -b 2 -s-2 -n1000 + -R 106 -i 1 -P 0 -b 2 -s-2 -c -n1000 + -R 106 -i 1 -P 2 -b 3 -s0 -n1000 + -R 106 -i 1 -P 2 -b 4 -s0 -n1000 + -R 106 -i 1 -P 2 -b 5 -s1 -n1000 + -R 106 -i 1 -P 2 -b 6 -s2 -n1000 + -R 106 -i 1 -P 2 -b 7 -s3 -n1000 + -R 106 -i 1 -P 2 -b 8 -s4 -n1000 + -R 106 -i 1 -P 2 -b 9 -s5 -n1000 + -R 106 -i 1 -P 2 -b 10 -s6 -n1000 + -R 106 -i 1 -P 2 -b 11 -s6 -n1000 + + nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 PUCCH test OK segmentation fault|assertion|exiting|fatal 3 @@ -1248,11 +1264,11 @@ $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash $OPENAIR_DIR/targets/bin/nr_ulsim.Rel15 - -n100 -m9 -r106 -s0 + -n100 -m9 -r106 -s5 -n100 -m16 -s10 -n100 -m28 -s20 - -n100 -m9 -R217 -r217 -s0 - -n100 -m9 -R273 -r273 -s0 + -n100 -m9 -R217 -r217 -s5 + -n100 -m9 -R273 -r273 -s5 nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5 PUSCH test OK segmentation fault|assertion|exiting|fatal diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 78769ed8d4..9a5d5f370c 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -408,6 +408,10 @@ function main() { SKIP_SHARED_LIB_FLAG="True" echo_info "Skipping build of shared libraries, rfsimulator, basicsimulator and transport protocol libraries" shift;; + --ninja) + CMAKE_CMD="$CMAKE_CMD -GNinja" + MAKE_CMD=ninja + shift;; -h | --help) print_help exit 1;; @@ -697,12 +701,7 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim -<<<<<<< HEAD -#simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim" -simlist="ldpctest" -======= simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" ->>>>>>> origin/develop for f in $simlist ; do compilations \ phy_simulators $f \ diff --git a/cmake_targets/nas_sim_tools/CMakeLists.txt b/cmake_targets/nas_sim_tools/CMakeLists.txt index c1a0bb419b..308c71be4c 100644 --- a/cmake_targets/nas_sim_tools/CMakeLists.txt +++ b/cmake_targets/nas_sim_tools/CMakeLists.txt @@ -14,6 +14,7 @@ set(CMAKE_C_FLAGS set(OPENAIR_DIR $ENV{OPENAIR_DIR}) set(OPENAIR3_DIR $ENV{OPENAIR_DIR}/openair3) +include_directories (${OPENAIR_DIR}/openair2/COMMON) set(CONF2UEDATA_LIB_SRC ${OPENAIR_DIR}/openair3/NAS/TOOLS/conf_emm.c diff --git a/cmake_targets/phy_simulators/CMakeLists.txt b/cmake_targets/phy_simulators/CMakeLists.txt index b43f7dd389..5f2d34883e 100644 --- a/cmake_targets/phy_simulators/CMakeLists.txt +++ b/cmake_targets/phy_simulators/CMakeLists.txt @@ -1,13 +1,19 @@ cmake_minimum_required(VERSION 2.8) -set(PACKAGE_NAME "unitary_tests_simulators") -set(PHYSIM True) -set(RF_BOARD None) -set(XFORMS True) -set(ENABLE_ITTI True) -set(DEBUG_PHY False) -set(MU_RECIEVER False) -set(NAS_UE False) -set(MESSAGE_CHART_GENERATOR False) -set(RRC_ASN1_VERSION "Rel15") -set(T_TRACER True) -include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt) \ No newline at end of file +set ( CMAKE_BUILD_TYPE ) +set ( CFLAGS_PROCESSOR_USER "" ) +set ( UE_EXPANSION False ) +set ( PRE_SCD_THREAD False ) +set ( UESIM_EXPANSION False ) +set ( ENABLE_VCD_FIFO False ) +set ( RF_BOARD "OAI_USRP") +set ( TRANSP_PRO "None") +set ( PACKAGE_NAME "") +set ( DEADLINE_SCHEDULER "False" ) +set ( CPU_AFFINITY "False" ) +set ( T_TRACER True ) +set ( UE_AUTOTEST_TRACE False ) +set ( UE_DEBUG_TRACE False ) +set ( UE_TIMING_TRACE False ) +set ( USRP_REC_PLAY False ) +set ( SKIP_SHARED_LIB_FLAG False ) +include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt) diff --git a/cmake_targets/tools/build_helper b/cmake_targets/tools/build_helper index 818b1fd79c..20bc5dc2b9 100755 --- a/cmake_targets/tools/build_helper +++ b/cmake_targets/tools/build_helper @@ -183,11 +183,15 @@ compilations() { else COV_SCAN_PREFIX="" fi + if [ "$MAKE_CMD" != "" ]; then + $MAKE_CMD $2 + else if [ "$VERBOSE_COMPILE" == "1" ]; then $COV_SCAN_PREFIX make -j`nproc` $2 VERBOSE=$VERBOSE_COMPILE else $COV_SCAN_PREFIX make -j`nproc` $2 fi + fi } > $dlog/$2.$REL.txt 2>&1 set -e @@ -217,7 +221,7 @@ install_protobuf_from_source(){ #tar -xzvf protobuf-2.6.1.tar.gz --owner $USER --group $USER --no-same-owner #cd protobuf-2.6.1/ rm -rf /tmp/protobuf-cpp-3.3.0.tar.gz* /tmp/protobuf-3.3.0 - wget https://github.com/google/protobuf/releases/download/v3.3.0/protobuf-cpp-3.3.0.tar.gz + wget --tries=3 --retry-connrefused https://github.com/google/protobuf/releases/download/v3.3.0/protobuf-cpp-3.3.0.tar.gz tar -xzvf protobuf-cpp-3.3.0.tar.gz --owner $USER --group $(groups | cut -d" " -f1) --no-same-owner cd protobuf-3.3.0/ ./configure @@ -353,8 +357,8 @@ install_bladerf_driver_from_source(){ $SUDO ldconfig echo "Downloading FPGA and firmware images" cd /tmp/bladeRF - wget https://www.nuand.com/fx3/bladeRF_fw_latest.img - wget https://www.nuand.com/fpga/hostedx40-latest.rbf + wget --tries=3 --retry-connrefused https://www.nuand.com/fx3/bladeRF_fw_latest.img + wget --tries=3 --retry-connrefused https://www.nuand.com/fpga/hostedx40-latest.rbf sudo mkdir -p /usr/share/Nuand/bladeRF sudo mv bladeRF_fw_latest.img /usr/share/Nuand/bladeRF/bladeRF_fw.img sudo mv hostedx40-latest.rbf /usr/share/Nuand/bladeRF/hostedx40.rbf @@ -567,7 +571,7 @@ check_install_additional_tools (){ echo_info "Installing Netinterfaces package. The logfile for installation is in $log_netiface" ( $SUDO rm -fr /tmp/netifaces-0.10.4.tar.gz /tmp/netifaces - wget -P /tmp https://pypi.python.org/packages/18/fa/dd13d4910aea339c0bb87d2b3838d8fd923c11869b1f6e741dbd0ff3bc00/netifaces-0.10.4.tar.gz + wget --tries=3 --retry-connrefused -P /tmp https://pypi.python.org/packages/18/fa/dd13d4910aea339c0bb87d2b3838d8fd923c11869b1f6e741dbd0ff3bc00/netifaces-0.10.4.tar.gz tar -xzvf /tmp/netifaces-0.10.4.tar.gz -C /tmp cd /tmp/netifaces-0.10.4 $SUDO python setup.py install @@ -619,6 +623,7 @@ check_install_oai_software() { build-essential \ cmake \ cmake-curses-gui \ + ninja-build \ doxygen \ doxygen-gui \ texlive-latex-base \ diff --git a/common/utils/LOG/vcd_signal_dumper.c b/common/utils/LOG/vcd_signal_dumper.c index 0043eb3238..79db7f1c0e 100644 --- a/common/utils/LOG/vcd_signal_dumper.c +++ b/common/utils/LOG/vcd_signal_dumper.c @@ -248,7 +248,8 @@ const char* eurecomVariablesNames[] = { "slot_number_TX1_gNB", "slot_number_RX0_gNB", "slot_number_RX1_gNB", - "ru_tx_ofdm_mask" + "ru_tx_ofdm_mask", + "usrp_send_return" }; const char* eurecomFunctionsNames[] = { @@ -282,6 +283,8 @@ const char* eurecomFunctionsNames[] = { "lock_mutex_ru", "lock_mutex_ru1", "lock_mutex_ru2", + /* uhd signals */ + "trx_write_thread", /* simulation signals */ "do_DL_sig", "do_UL_sig", diff --git a/common/utils/LOG/vcd_signal_dumper.h b/common/utils/LOG/vcd_signal_dumper.h index 20588bb828..88655977bb 100644 --- a/common/utils/LOG/vcd_signal_dumper.h +++ b/common/utils/LOG/vcd_signal_dumper.h @@ -226,6 +226,7 @@ typedef enum { VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX0_GNB, VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX1_GNB, VCD_SIGNAL_DUMPER_VARIABLES_RU_TX_OFDM_MASK, + VCD_SIGNAL_DUMPER_VARIABLES_USRP_SEND_RETURN, VCD_SIGNAL_DUMPER_VARIABLES_END @@ -262,6 +263,8 @@ typedef enum { VCD_SIGNAL_DUMPER_FUNCTIONS_LOCK_MUTEX_RU, VCD_SIGNAL_DUMPER_FUNCTIONS_LOCK_MUTEX_RU1, VCD_SIGNAL_DUMPER_FUNCTIONS_LOCK_MUTEX_RU2, + /* uhd signals */ + VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD, /* SIMULATION signals */ VCD_SIGNAL_DUMPER_FUNCTIONS_SIM_DO_DL_SIGNAL, VCD_SIGNAL_DUMPER_FUNCTIONS_SIM_DO_UL_SIGNAL, diff --git a/common/utils/T/T_defs.h b/common/utils/T/T_defs.h index 4cb4bf2bba..2221dbbcac 100644 --- a/common/utils/T/T_defs.h +++ b/common/utils/T/T_defs.h @@ -73,10 +73,10 @@ typedef struct { } T_cache_t; /* number of VCD functions (to be kept up to date! see in T_messages.txt) */ -#define VCD_NUM_FUNCTIONS (248) +#define VCD_NUM_FUNCTIONS (249) /* number of VCD variables (to be kept up to date! see in T_messages.txt) */ -#define VCD_NUM_VARIABLES (186) +#define VCD_NUM_VARIABLES (187) /* first VCD function (to be kept up to date! see in T_messages.txt) */ #define VCD_FIRST_FUNCTION ((uintptr_t)T_VCD_FUNCTION_RT_SLEEP) diff --git a/common/utils/T/T_messages.txt b/common/utils/T/T_messages.txt index f8b746669c..3838518834 100644 --- a/common/utils/T/T_messages.txt +++ b/common/utils/T/T_messages.txt @@ -2138,6 +2138,11 @@ ID = VCD_VARIABLE_RU_TX_OFDM_MASK GROUP = ALL:VCD:ENB:VCD_VARIABLE FORMAT = ulong,value VCD_NAME = ru_tx_ofdm_mask +ID = VCD_VARIABLE_USRP_SEND_RETURN + DESC = VCD variable USRP_SEND_RETURN + GROUP = ALL:VCD:ENB:VCD_VARIABLE + FORMAT = ulong,value + VCD_NAME = usrp_send_return #functions @@ -2286,6 +2291,11 @@ ID = VCD_FUNCTION_LOCK_MUTEX_RU2 GROUP = ALL:VCD:UE:VCD_FUNCTION FORMAT = int,value VCD_NAME = lock_mutex_ru2 +ID = VCD_FUNCTION_TRX_WRITE_THREAD + DESC = VCD function TRX_WRITE_THREAD + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = trx_write_thread ID = VCD_FUNCTION_SIM_DO_DL_SIGNAL DESC = VCD function SIM_DO_DL_SIGNAL GROUP = ALL:VCD:ENB:VCD_FUNCTION diff --git a/common/utils/T/tracer/config.h b/common/utils/T/tracer/config.h index 07290c71a3..765b126133 100644 --- a/common/utils/T/tracer/config.h +++ b/common/utils/T/tracer/config.h @@ -1,5 +1,5 @@ -#ifndef _CONFIG_H_ -#define _CONFIG_H_ +#ifndef __COMMON_UTILS_T_TRACER_CONFIG__H__ +#define __COMMON_UTILS_T_TRACER_CONFIG__H__ void clear_remote_config(void); void append_received_config_chunk(char *buf, int length); @@ -7,4 +7,4 @@ void load_config_file(char *filename); void verify_config(void); void get_local_config(char **txt, int *len); -#endif /* _CONFIG_H_ */ +#endif /* __COMMON_UTILS_T_TRACER_CONFIG__H__ */ diff --git a/common/utils/T/tracer/hacks/time_meas.c b/common/utils/T/tracer/hacks/time_meas.c index 6bd2950301..408189cd80 100644 --- a/common/utils/T/tracer/hacks/time_meas.c +++ b/common/utils/T/tracer/hacks/time_meas.c @@ -13,7 +13,8 @@ void usage(void) "options:\n" " -d this option is mandatory\n" " -ip connect to given IP address (default %s)\n" -" -p connect to given port (default %d)\n", +" -p connect to given port (default %d)\n" +" -e event to trace (default VCD_FUNCTION_ENB_DLSCH_ULSCH_SCHEDULER)\n", DEFAULT_REMOTE_IP, DEFAULT_REMOTE_PORT ); @@ -47,6 +48,7 @@ int main(int n, char **v) int ev_fun; int start_valid = 0; struct timespec start_time, stop_time, delta_time; + char *name = "VCD_FUNCTION_ENB_DLSCH_ULSCH_SCHEDULER"; for (i = 1; i < n; i++) { if (!strcmp(v[i], "-h") || !strcmp(v[i], "--help")) usage(); @@ -55,6 +57,7 @@ int main(int n, char **v) if (!strcmp(v[i], "-ip")) { if (i > n-2) usage(); ip = v[++i]; continue; } if (!strcmp(v[i], "-p")) { if (i > n-2) usage(); port = atoi(v[++i]); continue; } + if (!strcmp(v[i], "-e")) { if (i > n-2) usage(); name = v[++i]; continue; } usage(); } @@ -71,10 +74,9 @@ int main(int n, char **v) is_on = calloc(number_of_events, sizeof(int)); if (is_on == NULL) abort(); - on_off(database, "VCD_FUNCTION_ENB_DLSCH_ULSCH_SCHEDULER", is_on, 1); + on_off(database, name, is_on, 1); - ev_fun = event_id_from_name(database, - "VCD_FUNCTION_ENB_DLSCH_ULSCH_SCHEDULER"); + ev_fun = event_id_from_name(database, name); socket = connect_to(ip, port); diff --git a/common/utils/T/tracer/hacks/timeplot.c b/common/utils/T/tracer/hacks/timeplot.c index 79905d16f9..a1ddb2a1c9 100644 --- a/common/utils/T/tracer/hacks/timeplot.c +++ b/common/utils/T/tracer/hacks/timeplot.c @@ -28,6 +28,7 @@ int bins[50]; #define N 1000 int data[N]; +long start = 100; void plot(void) { @@ -45,7 +46,8 @@ void plot(void) if (data[i] < vmin) vmin = data[i]; if (data[i] > vmax) vmax = data[i]; vavg += data[i]; - int ms2 = data[i]/binsize_ns; + int ms2 = (data[i] - start * 1000)/binsize_ns; + if (ms2 < 0) ms2 = 0; if (ms2 > 49) ms2 = 49; bins[ms2]++; if (bins[ms2] > max) max = bins[ms2]; @@ -55,7 +57,7 @@ void plot(void) GOTO(1,1); for (i = 0; i < 50; i++) { - double binend = (i+1) * binsize_ns / 1000.; + double binend = (i+1) * binsize_ns / 1000. + start; int k; int width = bins[i] * 70 / max; /* force at least width of 1 if some point is there */ @@ -68,11 +70,23 @@ void plot(void) printf("min %d ns max %d ns avg %ld ns\n", vmin, vmax, vavg); } +void up(int x) +{ + start += 5; +} + +void down(int x) +{ + start -= 5; +} + int main(void) { int i; int pos = 0; signal(SIGINT, sig); + signal(SIGUSR1, up); + signal(SIGUSR2, down); RESET(); HIDE_CURSOR(); while (!feof(stdin)) { diff --git a/common/utils/T/tracer/packet-mac-lte.h b/common/utils/T/tracer/packet-mac-lte.h index 1bc6df632b..54e6d1a09b 100644 --- a/common/utils/T/tracer/packet-mac-lte.h +++ b/common/utils/T/tracer/packet-mac-lte.h @@ -33,6 +33,9 @@ * SUCH DAMAGE */ +#ifndef __COMMON_UTILS_T_TRACER_PACKET_MAC_LTE__H__ +#define __COMMON_UTILS_T_TRACER_PACKET_MAC_LTE__H__ + //#include "ws_symbol_export.h" /* radioType */ @@ -139,3 +142,4 @@ continues until the end of the frame) */ #define MAC_LTE_PAYLOAD_TAG 0x01 +#endif diff --git a/common/utils/assertions.h b/common/utils/assertions.h index 97f1866274..48d8df401c 100644 --- a/common/utils/assertions.h +++ b/common/utils/assertions.h @@ -19,6 +19,9 @@ * contact@openairinterface.org */ +#ifndef __COMMON_UTILS_ASSERTIONS__H__ +#define __COMMON_UTILS_ASSERTIONS__H__ + #include #include #include @@ -30,9 +33,6 @@ # include "backtrace.h" #endif -#ifndef ASSERTIONS_H_ -#define ASSERTIONS_H_ - void output_log_mem(void); #define _Assert_Exit_ \ fprintf(stderr, "\nExiting execution\n"); \ @@ -83,4 +83,4 @@ do { \ } \ } while(0) -#endif /* ASSERTIONS_H_ */ +#endif /* __COMMON_UTILS_ASSERTIONS__H__ */ diff --git a/common/utils/itti_analyzer/common/queue.h b/common/utils/itti_analyzer/common/queue.h deleted file mode 100644 index 294d485110..0000000000 --- a/common/utils/itti_analyzer/common/queue.h +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright (c) 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)queue.h 8.5 (Berkeley) 8/20/94 - */ - -#ifndef _SYS_QUEUE_H_ -#define _SYS_QUEUE_H_ - -/* - * This file defines five types of data structures: singly-linked lists, - * lists, simple queues, tail queues, and circular queues. - * - * A singly-linked list is headed by a single forward pointer. The - * elements are singly linked for minimum space and pointer manipulation - * overhead at the expense of O(n) removal for arbitrary elements. New - * elements can be added to the list after an existing element or at the - * head of the list. Elements being removed from the head of the list - * should use the explicit macro for this purpose for optimum - * efficiency. A singly-linked list may only be traversed in the forward - * direction. Singly-linked lists are ideal for applications with large - * datasets and few or no removals or for implementing a LIFO queue. - * - * A list is headed by a single forward pointer (or an array of forward - * pointers for a hash table header). The elements are doubly linked - * so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before - * or after an existing element or at the head of the list. A list - * may only be traversed in the forward direction. - * - * A simple queue is headed by a pair of pointers, one the head of the - * list and the other to the tail of the list. The elements are singly - * linked to save space, so elements can only be removed from the - * head of the list. New elements can be added to the list after - * an existing element, at the head of the list, or at the end of the - * list. A simple queue may only be traversed in the forward direction. - * - * A tail queue is headed by a pair of pointers, one to the head of the - * list and the other to the tail of the list. The elements are doubly - * linked so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before or - * after an existing element, at the head of the list, or at the end of - * the list. A tail queue may be traversed in either direction. - * - * A circle queue is headed by a pair of pointers, one to the head of the - * list and the other to the tail of the list. The elements are doubly - * linked so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before or after - * an existing element, at the head of the list, or at the end of the list. - * A circle queue may be traversed in either direction, but has a more - * complex end of list detection. - * - * For details on the use of these macros, see the queue(3) manual page. - * SLIST LIST STAILQ TAILQ CIRCLEQ - * _HEAD + + + + + - * _HEAD_INITIALIZER + + + + + - * _ENTRY + + + + + - * _INIT + + + + + - * _EMPTY + + + + + - * _FIRST + + + + + - * _NEXT + + + + + - * _PREV - - - + + - * _LAST - - + + + - * _FOREACH + + + + + - * _FOREACH_REVERSE - - - + + - * _INSERT_HEAD + + + + + - * _INSERT_BEFORE - + - + + - * _INSERT_AFTER + + + + + - * _INSERT_TAIL - - + + + - * _REMOVE_HEAD + - + - - - * _REMOVE + + + + + - */ - -/* - * List definitions. - */ -#define LIST_HEAD(name, type) \ -struct name { \ - struct type *lh_first; /* first element */ \ -} - -#define LIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define LIST_ENTRY(type) \ -struct { \ - struct type *le_next; /* next element */ \ - struct type **le_prev; /* address of previous next element */ \ -} - -/* - * List functions. - */ -#define LIST_INIT(head) do { \ - (head)->lh_first = NULL; \ -} while (/*CONSTCOND*/0) - -#define LIST_INSERT_AFTER(listelm, elm, field) do { \ - if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ - (listelm)->field.le_next->field.le_prev = \ - &(elm)->field.le_next; \ - (listelm)->field.le_next = (elm); \ - (elm)->field.le_prev = &(listelm)->field.le_next; \ -} while (/*CONSTCOND*/0) - -#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ - (elm)->field.le_prev = (listelm)->field.le_prev; \ - (elm)->field.le_next = (listelm); \ - *(listelm)->field.le_prev = (elm); \ - (listelm)->field.le_prev = &(elm)->field.le_next; \ -} while (/*CONSTCOND*/0) - -#define LIST_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.le_next = (head)->lh_first) != NULL) \ - (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ - (head)->lh_first = (elm); \ - (elm)->field.le_prev = &(head)->lh_first; \ -} while (/*CONSTCOND*/0) - -#define LIST_REMOVE(elm, field) do { \ - if ((elm)->field.le_next != NULL) \ - (elm)->field.le_next->field.le_prev = \ - (elm)->field.le_prev; \ - *(elm)->field.le_prev = (elm)->field.le_next; \ -} while (/*CONSTCOND*/0) - -#define LIST_FOREACH(var, head, field) \ - for ((var) = ((head)->lh_first); \ - (var); \ - (var) = ((var)->field.le_next)) - -/* - * List access methods. - */ -#define LIST_EMPTY(head) ((head)->lh_first == NULL) -#define LIST_FIRST(head) ((head)->lh_first) -#define LIST_NEXT(elm, field) ((elm)->field.le_next) - - -/* - * Singly-linked List definitions. - */ -#define SLIST_HEAD(name, type) \ -struct name { \ - struct type *slh_first; /* first element */ \ -} - -#define SLIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define SLIST_ENTRY(type) \ -struct { \ - struct type *sle_next; /* next element */ \ -} - -/* - * Singly-linked List functions. - */ -#define SLIST_INIT(head) do { \ - (head)->slh_first = NULL; \ -} while (/*CONSTCOND*/0) - -#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ - (elm)->field.sle_next = (slistelm)->field.sle_next; \ - (slistelm)->field.sle_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define SLIST_INSERT_HEAD(head, elm, field) do { \ - (elm)->field.sle_next = (head)->slh_first; \ - (head)->slh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define SLIST_REMOVE_HEAD(head, field) do { \ - (head)->slh_first = (head)->slh_first->field.sle_next; \ -} while (/*CONSTCOND*/0) - -#define SLIST_REMOVE(head, elm, type, field) do { \ - if ((head)->slh_first == (elm)) { \ - SLIST_REMOVE_HEAD((head), field); \ - } \ - else { \ - struct type *curelm = (head)->slh_first; \ - while(curelm->field.sle_next != (elm)) \ - curelm = curelm->field.sle_next; \ - curelm->field.sle_next = \ - curelm->field.sle_next->field.sle_next; \ - } \ -} while (/*CONSTCOND*/0) - -#define SLIST_FOREACH(var, head, field) \ - for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next) - -/* - * Singly-linked List access methods. - */ -#define SLIST_EMPTY(head) ((head)->slh_first == NULL) -#define SLIST_FIRST(head) ((head)->slh_first) -#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) - - -/* - * Singly-linked Tail queue declarations. - */ -#define STAILQ_HEAD(name, type) \ -struct name { \ - struct type *stqh_first; /* first element */ \ - struct type **stqh_last; /* addr of last next element */ \ -} - -#define STAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).stqh_first } - -#define STAILQ_ENTRY(type) \ -struct { \ - struct type *stqe_next; /* next element */ \ -} - -/* - * Singly-linked Tail queue functions. - */ -#define STAILQ_INIT(head) do { \ - (head)->stqh_first = NULL; \ - (head)->stqh_last = &(head)->stqh_first; \ -} while (/*CONSTCOND*/0) - -#define STAILQ_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ - (head)->stqh_last = &(elm)->field.stqe_next; \ - (head)->stqh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define STAILQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.stqe_next = NULL; \ - *(head)->stqh_last = (elm); \ - (head)->stqh_last = &(elm)->field.stqe_next; \ -} while (/*CONSTCOND*/0) - -#define STAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ - if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\ - (head)->stqh_last = &(elm)->field.stqe_next; \ - (listelm)->field.stqe_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define STAILQ_REMOVE_HEAD(head, field) do { \ - if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \ - (head)->stqh_last = &(head)->stqh_first; \ -} while (/*CONSTCOND*/0) - -#define STAILQ_REMOVE(head, elm, type, field) do { \ - if ((head)->stqh_first == (elm)) { \ - STAILQ_REMOVE_HEAD((head), field); \ - } else { \ - struct type *curelm = (head)->stqh_first; \ - while (curelm->field.stqe_next != (elm)) \ - curelm = curelm->field.stqe_next; \ - if ((curelm->field.stqe_next = \ - curelm->field.stqe_next->field.stqe_next) == NULL) \ - (head)->stqh_last = &(curelm)->field.stqe_next; \ - } \ -} while (/*CONSTCOND*/0) - -#define STAILQ_FOREACH(var, head, field) \ - for ((var) = ((head)->stqh_first); \ - (var); \ - (var) = ((var)->field.stqe_next)) - -#define STAILQ_CONCAT(head1, head2) do { \ - if (!STAILQ_EMPTY((head2))) { \ - *(head1)->stqh_last = (head2)->stqh_first; \ - (head1)->stqh_last = (head2)->stqh_last; \ - STAILQ_INIT((head2)); \ - } \ -} while (/*CONSTCOND*/0) - -/* - * Singly-linked Tail queue access methods. - */ -#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) -#define STAILQ_FIRST(head) ((head)->stqh_first) -#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) - - -/* - * Simple queue definitions. - */ -#define SIMPLEQ_HEAD(name, type) \ -struct name { \ - struct type *sqh_first; /* first element */ \ - struct type **sqh_last; /* addr of last next element */ \ -} - -#define SIMPLEQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).sqh_first } - -#define SIMPLEQ_ENTRY(type) \ -struct { \ - struct type *sqe_next; /* next element */ \ -} - -/* - * Simple queue functions. - */ -#define SIMPLEQ_INIT(head) do { \ - (head)->sqh_first = NULL; \ - (head)->sqh_last = &(head)->sqh_first; \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ - (head)->sqh_last = &(elm)->field.sqe_next; \ - (head)->sqh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.sqe_next = NULL; \ - *(head)->sqh_last = (elm); \ - (head)->sqh_last = &(elm)->field.sqe_next; \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ - if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ - (head)->sqh_last = &(elm)->field.sqe_next; \ - (listelm)->field.sqe_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_REMOVE_HEAD(head, field) do { \ - if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ - (head)->sqh_last = &(head)->sqh_first; \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_REMOVE(head, elm, type, field) do { \ - if ((head)->sqh_first == (elm)) { \ - SIMPLEQ_REMOVE_HEAD((head), field); \ - } else { \ - struct type *curelm = (head)->sqh_first; \ - while (curelm->field.sqe_next != (elm)) \ - curelm = curelm->field.sqe_next; \ - if ((curelm->field.sqe_next = \ - curelm->field.sqe_next->field.sqe_next) == NULL) \ - (head)->sqh_last = &(curelm)->field.sqe_next; \ - } \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_FOREACH(var, head, field) \ - for ((var) = ((head)->sqh_first); \ - (var); \ - (var) = ((var)->field.sqe_next)) - -/* - * Simple queue access methods. - */ -#define SIMPLEQ_EMPTY(head) ((head)->sqh_first == NULL) -#define SIMPLEQ_FIRST(head) ((head)->sqh_first) -#define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) - - -/* - * Tail queue definitions. - */ -#define _TAILQ_HEAD(name, type, qual) \ -struct name { \ - qual type *tqh_first; /* first element */ \ - qual type *qual *tqh_last; /* addr of last next element */ \ -} -#define TAILQ_HEAD(name, type) _TAILQ_HEAD(name, struct type,) - -#define TAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).tqh_first } - -#define _TAILQ_ENTRY(type, qual) \ -struct { \ - qual type *tqe_next; /* next element */ \ - qual type *qual *tqe_prev; /* address of previous next element */\ -} -#define TAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,) - -/* - * Tail queue functions. - */ -#define TAILQ_INIT(head) do { \ - (head)->tqh_first = NULL; \ - (head)->tqh_last = &(head)->tqh_first; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ - (head)->tqh_first->field.tqe_prev = \ - &(elm)->field.tqe_next; \ - else \ - (head)->tqh_last = &(elm)->field.tqe_next; \ - (head)->tqh_first = (elm); \ - (elm)->field.tqe_prev = &(head)->tqh_first; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.tqe_next = NULL; \ - (elm)->field.tqe_prev = (head)->tqh_last; \ - *(head)->tqh_last = (elm); \ - (head)->tqh_last = &(elm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ - if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ - (elm)->field.tqe_next->field.tqe_prev = \ - &(elm)->field.tqe_next; \ - else \ - (head)->tqh_last = &(elm)->field.tqe_next; \ - (listelm)->field.tqe_next = (elm); \ - (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ - (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ - (elm)->field.tqe_next = (listelm); \ - *(listelm)->field.tqe_prev = (elm); \ - (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_REMOVE(head, elm, field) do { \ - if (((elm)->field.tqe_next) != NULL) \ - (elm)->field.tqe_next->field.tqe_prev = \ - (elm)->field.tqe_prev; \ - else \ - (head)->tqh_last = (elm)->field.tqe_prev; \ - *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_FOREACH(var, head, field) \ - for ((var) = ((head)->tqh_first); \ - (var); \ - (var) = ((var)->field.tqe_next)) - -#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ - for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); \ - (var); \ - (var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last))) - -#define TAILQ_CONCAT(head1, head2, field) do { \ - if (!TAILQ_EMPTY(head2)) { \ - *(head1)->tqh_last = (head2)->tqh_first; \ - (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ - (head1)->tqh_last = (head2)->tqh_last; \ - TAILQ_INIT((head2)); \ - } \ -} while (/*CONSTCOND*/0) - -/* - * Tail queue access methods. - */ -#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) -#define TAILQ_FIRST(head) ((head)->tqh_first) -#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) - -#define TAILQ_LAST(head, headname) \ - (*(((struct headname *)((head)->tqh_last))->tqh_last)) -#define TAILQ_PREV(elm, headname, field) \ - (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) - - -/* - * Circular queue definitions. - */ -#define CIRCLEQ_HEAD(name, type) \ -struct name { \ - struct type *cqh_first; /* first element */ \ - struct type *cqh_last; /* last element */ \ -} - -#define CIRCLEQ_HEAD_INITIALIZER(head) \ - { (void *)&head, (void *)&head } - -#define CIRCLEQ_ENTRY(type) \ -struct { \ - struct type *cqe_next; /* next element */ \ - struct type *cqe_prev; /* previous element */ \ -} - -/* - * Circular queue functions. - */ -#define CIRCLEQ_INIT(head) do { \ - (head)->cqh_first = (void *)(head); \ - (head)->cqh_last = (void *)(head); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ - (elm)->field.cqe_next = (listelm)->field.cqe_next; \ - (elm)->field.cqe_prev = (listelm); \ - if ((listelm)->field.cqe_next == (void *)(head)) \ - (head)->cqh_last = (elm); \ - else \ - (listelm)->field.cqe_next->field.cqe_prev = (elm); \ - (listelm)->field.cqe_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ - (elm)->field.cqe_next = (listelm); \ - (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ - if ((listelm)->field.cqe_prev == (void *)(head)) \ - (head)->cqh_first = (elm); \ - else \ - (listelm)->field.cqe_prev->field.cqe_next = (elm); \ - (listelm)->field.cqe_prev = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ - (elm)->field.cqe_next = (head)->cqh_first; \ - (elm)->field.cqe_prev = (void *)(head); \ - if ((head)->cqh_last == (void *)(head)) \ - (head)->cqh_last = (elm); \ - else \ - (head)->cqh_first->field.cqe_prev = (elm); \ - (head)->cqh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.cqe_next = (void *)(head); \ - (elm)->field.cqe_prev = (head)->cqh_last; \ - if ((head)->cqh_first == (void *)(head)) \ - (head)->cqh_first = (elm); \ - else \ - (head)->cqh_last->field.cqe_next = (elm); \ - (head)->cqh_last = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_REMOVE(head, elm, field) do { \ - if ((elm)->field.cqe_next == (void *)(head)) \ - (head)->cqh_last = (elm)->field.cqe_prev; \ - else \ - (elm)->field.cqe_next->field.cqe_prev = \ - (elm)->field.cqe_prev; \ - if ((elm)->field.cqe_prev == (void *)(head)) \ - (head)->cqh_first = (elm)->field.cqe_next; \ - else \ - (elm)->field.cqe_prev->field.cqe_next = \ - (elm)->field.cqe_next; \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_FOREACH(var, head, field) \ - for ((var) = ((head)->cqh_first); \ - (var) != (const void *)(head); \ - (var) = ((var)->field.cqe_next)) - -#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \ - for ((var) = ((head)->cqh_last); \ - (var) != (const void *)(head); \ - (var) = ((var)->field.cqe_prev)) - -/* - * Circular queue access methods. - */ -#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) -#define CIRCLEQ_FIRST(head) ((head)->cqh_first) -#define CIRCLEQ_LAST(head) ((head)->cqh_last) -#define CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) -#define CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) - -#define CIRCLEQ_LOOP_NEXT(head, elm, field) \ - (((elm)->field.cqe_next == (void *)(head)) \ - ? ((head)->cqh_first) \ - : (elm->field.cqe_next)) -#define CIRCLEQ_LOOP_PREV(head, elm, field) \ - (((elm)->field.cqe_prev == (void *)(head)) \ - ? ((head)->cqh_last) \ - : (elm->field.cqe_prev)) - -#endif /* sys/queue.h */ diff --git a/common/utils/nr/nr_common.h b/common/utils/nr/nr_common.h index 979cf86343..5601c0fcbf 100644 --- a/common/utils/nr/nr_common.h +++ b/common/utils/nr/nr_common.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __COMMON_UTILS_NR_NR_COMMON__H__ +#define __COMMON_UTILS_NR_NR_COMMON__H__ + #include #include "assertions.h" @@ -63,3 +66,5 @@ void SLIV2SL(int SLIV,int *S,int *L); #define max(a,b) cmax(a,b) #define min(a,b) cmin(a,b) #endif + +#endif diff --git a/common/utils/ocp_itti/intertask_interface.cpp b/common/utils/ocp_itti/intertask_interface.cpp index 89e19074bf..3d4d356dcf 100644 --- a/common/utils/ocp_itti/intertask_interface.cpp +++ b/common/utils/ocp_itti/intertask_interface.cpp @@ -1,12 +1,32 @@ /* - Author: Laurent THOMAS, Open Cells - copyleft: OpenAirInterface Software Alliance and it's licence +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + #include #include #include +extern "C" { #include #include @@ -35,7 +55,6 @@ typedef struct task_list_s { int timer_expired(int fd); task_list_t tasks[TASK_MAX]; -extern "C" { void *pool_buffer_init (void) { return 0; } @@ -86,6 +105,9 @@ extern "C" { temp->ittiMsgHeader.messageId = message_id; temp->ittiMsgHeader.originTaskId = origin_task_id; temp->ittiMsgHeader.ittiMsgSize = size; + temp->ittiMsgHeader.destinationTaskId=TASK_UNKNOWN; + temp->ittiMsgHeader.instance=0; + temp->ittiMsgHeader.lte_time={0}; return temp; //return itti_alloc_new_message_sized(origin_task_id, message_id, messages_info[message_id].size); } diff --git a/common/utils/ocp_itti/intertask_interface.h b/common/utils/ocp_itti/intertask_interface.h index 52c733752d..0cd25ee231 100644 --- a/common/utils/ocp_itti/intertask_interface.h +++ b/common/utils/ocp_itti/intertask_interface.h @@ -1,7 +1,26 @@ /* - Author: Laurent THOMAS, Open Cells - Copyleft: OpenAirInterface software alliance and it's license +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + #ifndef INTERTASK_INTERFACE_H_ #define INTERTASK_INTERFACE_H_ #include @@ -275,7 +294,7 @@ typedef struct { //TASK_DEF(TASK_RRC_ENB, TASK_PRIORITY_MED, 200, NULL, NULL) //TASK_DEF(TASK_GTPV1_U, TASK_PRIORITY_MED, 1000,NULL, NULL) //TASK_DEF(TASK_UDP, TASK_PRIORITY_MED, 1000, NULL, NULL) - +void * rrc_enb_process_msg(void*); #define FOREACH_TASK(TASK_DEF) \ TASK_DEF(TASK_UNKNOWN, TASK_PRIORITY_MED, 50, NULL, NULL) \ TASK_DEF(TASK_TIMER, TASK_PRIORITY_MED, 10, NULL, NULL) \ diff --git a/common/utils/system.c b/common/utils/system.c index 3a8fe7be3d..1bd5c7d39b 100644 --- a/common/utils/system.c +++ b/common/utils/system.c @@ -243,6 +243,8 @@ void configure_linux(void) { // Set CPU frequency to it's maximum if ( 0 != system("for d in /sys/devices/system/cpu/cpu[0-9]*; do cat $d/cpufreq/cpuinfo_max_freq > $d/cpufreq/scaling_min_freq; done")) - LOG_W(HW,"Can't set cpu frequency\n"); - + LOG_E(HW,"Can't set cpu frequency\n"); + + mlockall(MCL_CURRENT | MCL_FUTURE); + } diff --git a/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h b/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h index 89ced509a4..7a45b351f3 100644 --- a/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h +++ b/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h @@ -32,6 +32,8 @@ * \warning */ +#ifndef __TELNETSRV_CPUMEASUR_DEF__H__ +#define __TELNETSRV_CPUMEASUR_DEF__H__ #define CPU_PHYENB_MEASURE \ { \ @@ -97,3 +99,5 @@ {"pdcp_ip", &(pdcpvars->pdcp_ip),0},\ {"ip_pdcp", &(pdcpvars->ip_pdcp),0},\ } + +#endif diff --git a/common/utils/telnetsrv/telnetsrv_enb_measurements.c b/common/utils/telnetsrv/telnetsrv_enb_measurements.c index 9c5c5b675b..8830173e6d 100644 --- a/common/utils/telnetsrv/telnetsrv_enb_measurements.c +++ b/common/utils/telnetsrv/telnetsrv_enb_measurements.c @@ -110,13 +110,13 @@ void measurcmd_display_pdcpcpu(telnet_printfunc_t prnt) { void measurcmd_display_macstats_ue(telnet_printfunc_t prnt) { - UE_list_t *UE_list = &(RC.mac[eNB_id]->UE_list); + UE_info_t *UE_info = &(RC.mac[eNB_id]->UE_info); - for (int UE_id=UE_list->head; UE_id>=0; UE_id=UE_list->next[UE_id]) { - for (int i=0; inumactiveCCs[UE_id]; i++) { - int CC_id = UE_list->ordered_CCids[i][UE_id]; + for (int UE_id=UE_info->list.head; UE_id>=0; UE_id=UE_info->list.next[UE_id]) { + for (int i=0; inumactiveCCs[UE_id]; i++) { + int CC_id = UE_info->ordered_CCids[i][UE_id]; prnt("%s UE %i Id %i CCid %i %s\n",HDR,i,UE_id,CC_id,HDR); - eNB_UE_STATS *macuestatptr = &(UE_list->eNB_UE_stats[CC_id][UE_id]); + eNB_UE_STATS *macuestatptr = &(UE_info->eNB_UE_stats[CC_id][UE_id]); telnet_ltemeasurdef_t statsptr[]=LTEMAC_UEMEASURE; measurcmd_display_measures(prnt, statsptr, sizeof(statsptr)/sizeof(telnet_ltemeasurdef_t)); } @@ -155,7 +155,7 @@ void measurcmd_display_one_rlcstat(telnet_printfunc_t prnt, int UE_id, telnet_lt void measurcmd_display_rlcstats(telnet_printfunc_t prnt) { protocol_ctxt_t ctxt; - UE_list_t *UE_list = &(RC.mac[eNB_id]->UE_list); + UE_info_t *UE_info = &(RC.mac[eNB_id]->UE_info); telnet_ltemeasurdef_t statsptr[]=LTE_RLCMEASURE; int num_rlcmeasure = sizeof(statsptr)/sizeof(telnet_ltemeasurdef_t ); unsigned int *rlcstats = malloc(num_rlcmeasure*sizeof(unsigned int)); @@ -165,9 +165,9 @@ void measurcmd_display_rlcstats(telnet_printfunc_t prnt) { statsptr[i].vptr = rlcstats + i; } - for (int UE_id=UE_list->head; UE_id>=0; UE_id=UE_list->next[UE_id]) { + for (int UE_id=UE_info->list.head; UE_id>=0; UE_id=UE_info->list.next[UE_id]) { #define NB_eNB_INST 1 - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt,eNB_id, ENB_FLAG_YES,UE_list->eNB_UE_stats[0][UE_id].crnti, + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt,eNB_id, ENB_FLAG_YES,UE_info->eNB_UE_stats[0][UE_id].crnti, eNB->frame,eNB->subframe,eNB_id); measurcmd_display_one_rlcstat(prnt, UE_id, statsptr, num_rlcmeasure, rlcstats, "DCCH", &ctxt, SRB_FLAG_YES, DCCH); measurcmd_display_one_rlcstat(prnt, UE_id, statsptr, num_rlcmeasure, rlcstats, "DTCH", &ctxt, SRB_FLAG_NO, DTCH-2); diff --git a/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h b/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h index 160111f15e..c1aab51e23 100644 --- a/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h +++ b/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h @@ -32,6 +32,8 @@ * \warning */ +#ifndef __TELNETSRV_LTEMEASUR_DEF__H__ +#define __TELNETSRV_LTEMEASUR_DEF__H__ #define LTEMAC_MEASURE \ { \ @@ -125,3 +127,5 @@ {"timer_poll_retrans_tout", NULL, TELNET_VARTYPE_UINT, 0},\ {"timer_status_prohibit_tout", NULL, TELNET_VARTYPE_UINT, 0},\ } + +#endif diff --git a/common/utils/telnetsrv/telnetsrv_measurements.h b/common/utils/telnetsrv/telnetsrv_measurements.h index 80276bc2d0..08136df0fd 100644 --- a/common/utils/telnetsrv/telnetsrv_measurements.h +++ b/common/utils/telnetsrv/telnetsrv_measurements.h @@ -31,6 +31,10 @@ * \note * \warning */ + +#ifndef __TELNETSRV_MEASUREMENTS__H__ +#define __TELNETSRV_MEASUREMENTS__H__ + #include #include "telnetsrv.h" #include "openair1/PHY/defs_eNB.h" @@ -97,3 +101,4 @@ extern uint64_t measurcmd_getstatvalue(telnet_ltemeasurdef_t *measur,telnet_prin extern void measurcmd_display_measures(telnet_printfunc_t prnt, telnet_ltemeasurdef_t *statsptr, int stats_size); #endif /* TELNETSRV_MEASURCMD_MAIN */ +#endif diff --git a/common/utils/telnetsrv/telnetsrv_phycmd.h b/common/utils/telnetsrv/telnetsrv_phycmd.h index e35b2a53ab..0d574027fb 100644 --- a/common/utils/telnetsrv/telnetsrv_phycmd.h +++ b/common/utils/telnetsrv/telnetsrv_phycmd.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __TELNETSRV_PHYCMD__H__ +#define __TELNETSRV_PHYCMD__H__ + #ifdef TELNETSRV_PHYCMD_MAIN #include "common/utils/LOG/log.h" @@ -61,3 +64,4 @@ extern void add_phy_cmds(void); /*-------------------------------------------------------------------------------------*/ +#endif diff --git a/common/utils/telnetsrv/telnetsrv_proccmd.h b/common/utils/telnetsrv/telnetsrv_proccmd.h index 1a0a8d25dc..f130606b6c 100644 --- a/common/utils/telnetsrv/telnetsrv_proccmd.h +++ b/common/utils/telnetsrv/telnetsrv_proccmd.h @@ -30,6 +30,10 @@ * \note * \warning */ + +#ifndef __TELNETSRV_PROCCMD__H__ +#define __TELNETSRV_PROCCMD__H__ + #include #include "telnetsrv.h" @@ -79,3 +83,4 @@ telnetshell_cmddef_t proc_cmdarray[] = { extern void add_proccmd_cmds(void); #endif /* TELNETSRV_PROCCMD_MAIN */ +#endif diff --git a/common/utils/threadPool/measurement_display.c b/common/utils/threadPool/measurement_display.c index 8f6e2c239a..0f5a3e0f69 100644 --- a/common/utils/threadPool/measurement_display.c +++ b/common/utils/threadPool/measurement_display.c @@ -1,7 +1,26 @@ /* - Author: Laurent THOMAS, Open Cells - copyleft: OpenAirInterface Software Alliance and it's licence +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + #include #include "thread-pool.h" diff --git a/common/utils/threadPool/thread-pool.c b/common/utils/threadPool/thread-pool.c index dd3d16d717..cbb2dbe3d9 100644 --- a/common/utils/threadPool/thread-pool.c +++ b/common/utils/threadPool/thread-pool.c @@ -1,8 +1,27 @@ /* - Author: Laurent THOMAS, Open Cells - copyleft: OpenAirInterface Software Alliance and it's licence +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + #define _GNU_SOURCE #include #include diff --git a/common/utils/threadPool/thread-pool.h b/common/utils/threadPool/thread-pool.h index 9a2681a828..0ed8715811 100644 --- a/common/utils/threadPool/thread-pool.h +++ b/common/utils/threadPool/thread-pool.h @@ -1,8 +1,27 @@ /* - Author: Laurent THOMAS, Open Cells - copyleft: OpenAirInterface Software Alliance and it's licence +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + #ifndef THREAD_POOL_H #define THREAD_POOL_H #include @@ -217,11 +236,11 @@ static inline void pushTpool(tpool_t *t, notifiedFIFO_elt_t *msg) { static inline notifiedFIFO_elt_t *pullTpool(notifiedFIFO_t *responseFifo, tpool_t *t) { notifiedFIFO_elt_t *msg= pullNotifiedFIFO(responseFifo); - + AssertFatal(t->traceFd, "Thread pool used while not initialized"); if (t->measurePerf) msg->returnTime=rdtsc(); - if (t->traceFd >= 0) + if (t->traceFd > 0) if(write(t->traceFd, msg, sizeof(*msg))); return msg; @@ -229,7 +248,7 @@ static inline notifiedFIFO_elt_t *pullTpool(notifiedFIFO_t *responseFifo, tpool_ static inline notifiedFIFO_elt_t *tryPullTpool(notifiedFIFO_t *responseFifo, tpool_t *t) { notifiedFIFO_elt_t *msg= pollNotifiedFIFO(responseFifo); - + AssertFatal(t->traceFd, "Thread pool used while not initialized"); if (msg == NULL) return NULL; diff --git a/doc/L2NFAPI.md b/doc/L2NFAPI.md index 4dcaaef3bc..137e4847e4 100644 --- a/doc/L2NFAPI.md +++ b/doc/L2NFAPI.md @@ -14,19 +14,24 @@ This simulator allows to test L2 and above Layers using the nFAPI interface. +The UE executable is able to "simulate" multiple UEs in order to stimulate the scheduler in the eNB. + **This simulator is available starting the `v1.0.0` release on the `master` branch.** -Currently the only validated deployment by CI and developers is *with S1 interface and eNB / UEs are on the same machine*. - -Others deployments will be supported later after bug fixes and validation in the CI process. - -1. [With S1 -- eNB and UE on same machine](L2NFAPI_S1.md) - - +Currently the Continuous Integration process is validating this simulator the following way: +* the LTE modem executable is run on one host (in our CI deployment it is a **Xenial Virtual Machine**) +* the UE(s) modem executable is run on another host (in our CI deployment it is also a **Xenial Virtual Machine**) +* We are testing: + * in S1 mode (ie we are connected to a 3rd-party EPC) + * in noS1 mode (no need for an EPC) +Normally it should be fine to run both executables on the same host using the `loopback` interface to communicate. **But we are not guaranting it** +1. [With S1 -- eNB and UE on 2 hosts](L2NFAPI_S1.md) +2. [No S1 -- eNB and UE on 2 hosts](L2NFAPI_NOS1.md) +---- [oai wiki home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home) diff --git a/doc/L2NFAPI_S1.md b/doc/L2NFAPI_S1.md index b9156e9379..9fd6d51818 100644 --- a/doc/L2NFAPI_S1.md +++ b/doc/L2NFAPI_S1.md @@ -7,7 +7,7 @@ - L2 nFAPI Simulator (with S1 / same machine deployment) + L2 nFAPI Simulator (with S1 / 2-host deployment) @@ -21,25 +21,24 @@ 5. [Setup of the Configuration files](#5-setup-of-the-configuration-files) 1. [The eNB Configuration file](#51-the-enb-configuration-file) 2. [The UE Configuration file](#52-the-ue-configuration-file) -6. [Bring Up a second loopback interface](#6-bring-up-a-second-loopback-interface) -7. [Build the eNB](#7-build-the-enb) -8. [Build the UE](#8-build-the-ue) -9. [Initialize the NAS UE Layer](#9-initialize-the-nas-ue-layer) -10. [Start the eNB](#10-start-the-enb) -11. [Start the UE](#11-start-the-ue) -12. [Test with ping](#12-test-with-ping) -13. [Limitations](#13-limitations) +6. [Build OAI UE and eNodeB](#6-build-oai-ue-and-enodeb) +7. [Start EPC](#7-start-epc) +8. [Start the eNB](#8-start-the-enb) +9. [Start the UE](#9-start-the-ue) +10. [Test with ping](#10-test-with-ping) +11. [Limitations](#11-limitations) # 1. Environment # -2 servers are used in this deployment. You can use Virtual Machines instead of each server; like it is done in the CI process. +3 servers are used in this deployment. You can use Virtual Machines instead of each server; like it is done in the CI process. * Machine A contains the EPC. -* Machine B contains the OAI eNB and the OAI UE(s) +* Machine B contains the OAI eNB executable (`lte-softmodem`) +* Machine C contains the OAI UE(s) executable (`lte-uesoftmodem`) Example of L2 nFAPI Simulator testing environment: - + Note that the IP addresses are indicative and need to be adapted to your environment. @@ -47,26 +46,35 @@ Note that the IP addresses are indicative and need to be adapted to your environ Create the environment for the EPC and register all **USIM** information into the **HSS** database. -If you are using OAI-EPC ([see on GitHub](https://github.com/OPENAIRINTERFACE/openair-cn)), build **HSS/MME/SPGW** and create config files. +If you are using OAI-EPC ([see on GitHub](https://github.com/OPENAIRINTERFACE/openair-epc-fed)), build **HSS/MME/SPGW** and create config files. # 3. Retrieve the OAI eNB-UE source code # -The eNB and the UE executables will compiled into 2 separate folders on the same machine `B`. +At the time of writing, the tag used in the `develop` branch to do this documentation was `2020.w16`. + +The tutorial should be valid for the `master` branch tags such as `v1.2.0` or `v1.2.1`. But you may face issues that could be fixed in newer `develop` tags. + +Please try to use the same commit ID on both eNB/UE hosts. ```bash $ ssh sudousername@machineB -$ git clone https://gitlab.eurecom.fr/oai/openairinterface5g/ enb_folder -$ cd enb_folder -$ git checkout -f v1.0.0 -$ cd .. -$ cp -Rf enb_folder ue_folder +git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git enb_folder +cd enb_folder +git checkout develop +``` + +```bash +$ ssh sudousername@machineC +git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git ue_folder +cd ue_folder +git checkout develop ``` # 4. Setup of the USIM information in UE folder # ```bash -$ ssh sudousername@machineB -$ cd ue_folder +$ ssh sudousername@machineC +cd ue_folder # Edit openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf with your preferred editor ``` @@ -126,19 +134,19 @@ You can repeat the operation for as many users you want to test with. ```bash $ ssh sudousername@machineB -$ cd enb_folder +cd enb_folder # Edit ci-scripts/conf_files/rcc.band7.tm1.nfapi.conf with your preferred editor ``` -First verify the nFAPI interface setup on the 2nd loopback interface. +First verify the nFAPI interface setup on the physical ethernet interface of machineB and put the proper IP addresses for both hosts. ``` MACRLCs = ( { num_cc = 1; - local_s_if_name = "lo:"; // <-- HERE - remote_s_address = "127.0.0.1"; // <-- HERE - local_s_address = "127.0.0.2"; // <-- HERE + local_s_if_name = "ens3"; // <-- HERE + remote_s_address = "192.168.122.169"; // <-- HERE + local_s_address = "192.168.122.31"; // <-- HERE local_s_portc = 50001; remote_s_portc = 50000; local_s_portd = 50011; @@ -171,7 +179,7 @@ Last, the S1 interface shall be properly set. ``` ////////// MME parameters: - mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR"; // replace with 192.168.10.20 + mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR"; // replace with 192.168.122.195 ipv6 = "192:168:30::17"; active = "yes"; preference = "ipv4"; @@ -181,11 +189,11 @@ Last, the S1 interface shall be properly set. NETWORK_INTERFACES : { ENB_INTERFACE_NAME_FOR_S1_MME = "ens3"; // replace with the proper interface name - ENB_IPV4_ADDRESS_FOR_S1_MME = "CI_ENB_IP_ADDR"; // replace with 192.168.10.10 + ENB_IPV4_ADDRESS_FOR_S1_MME = "CI_ENB_IP_ADDR"; // replace with 192.168.122.31 ENB_INTERFACE_NAME_FOR_S1U = "ens3"; // replace with the proper interface name - ENB_IPV4_ADDRESS_FOR_S1U = "CI_ENB_IP_ADDR"; // replace with 192.168.10.10 + ENB_IPV4_ADDRESS_FOR_S1U = "CI_ENB_IP_ADDR"; // replace with 192.168.122.31 ENB_PORT_FOR_S1U = 2152; # Spec 2152 - ENB_IPV4_ADDRESS_FOR_X2C = "CI_ENB_IP_ADDR"; // replace with 192.168.10.10 + ENB_IPV4_ADDRESS_FOR_X2C = "CI_ENB_IP_ADDR"; // replace with 192.168.122.31 ENB_PORT_FOR_X2C = 36422; # Spec 36422 }; @@ -195,7 +203,7 @@ Last, the S1 interface shall be properly set. ```bash $ ssh sudousername@machineB -$ cd ue_folder +cd ue_folder # Edit ci-scripts/conf_files/ue.nfapi.conf with your preferred editor ``` @@ -206,9 +214,9 @@ L1s = ( { num_cc = 1; tr_n_preference = "nfapi"; - local_n_if_name = "lo"; // <- HERE - remote_n_address = "127.0.0.2"; // <- HERE - local_n_address = "127.0.0.1"; // <- HERE + local_n_if_name = "ens3"; // <- HERE + remote_n_address = "192.168.122.31"; // <- HERE + local_n_address = "192.168.122.169"; // <- HERE local_n_portc = 50000; remote_n_portc = 50001; local_n_portd = 50010; @@ -217,20 +225,11 @@ L1s = ( ); ``` -# 6. Bring Up a second loopback interface # +# 6. Build OAI UE and eNodeB # -A second loopback interface is used to connect the eNB and the UEs. +See [Build documentation](./BUILD.md). -```bash -$ ssh sudousername@machineB -$ sudo ifconfig lo: 127.0.0.2 netmask 255.0.0.0 up -``` - -# 7. [Build OAI UE and eNodeB](BUILD.md) # - - - -# 8. Initialize the NAS UE Layer # +# 7. Start EPC # Start the EPC on machine `A`. @@ -239,61 +238,89 @@ $ ssh sudousername@machineA # Start the EPC ``` -# 9. Start the eNB # +# 8. Start the eNB # In the first terminal (the one you used to build the eNB): ```bash $ ssh sudousername@machineB -$ cd enb_folder/cmake_targets -$ sudo -E ./ran_build/build/lte-softmodem -O ../ci-scripts/conf_files/rcc.band7.tm1.nfapi.conf > enb.log 2>&1 +cd enb_folder/cmake_targets +sudo -E ./ran_build/build/lte-softmodem -O ../ci-scripts/conf_files/rcc.band7.tm1.nfapi.conf > enb.log 2>&1 ``` If you don't use redirection, you can test but many logs are printed on the console and this may affect performance of the L2-nFAPI simulator. We do recommend the redirection in steady mode once your setup is correct. -# 10. Start the UE # +# 9. Start the UE # In the second terminal (the one you used to build the UE): ```bash -$ ssh sudousername@machineB -$ cd ue_folder/cmake_targets -# Test 64 UEs, 64 threads in FDD mode -$ sudo -E ./ran_build/build/lte-uesoftmodem -O ../ci-scripts/conf_files/ue.nfapi.conf --L2-emul 3 --num-ues 64 --nums-ue-thread 64 > ue.log 2>&1 -# Test 64 UEs, 64 threads in TDD mode -$ sudo -E ./ran_build/build/lte-uesoftmodem -O ../ci-scripts/conf_files/ue.nfapi.conf --L2-emul 3 --num-ues 64 --nums-ue-thread 64 -T 1 > ue.log 2>&1 +$ ssh sudousername@machineC +cd ue_folder/cmake_targets +# Test 64 UEs, 1 thread in FDD mode +sudo -E ./ran_build/build/lte-uesoftmodem -O ../ci-scripts/conf_files/ue.nfapi.conf --L2-emul 3 --num-ues 64 --nums_ue_thread 1 --nokrnmod 1 > ue.log 2>&1 +# Test 64 UEs, 1 thread in TDD mode +sudo -E ./ran_build/build/lte-uesoftmodem -O ../ci-scripts/conf_files/ue.nfapi.conf --L2-emul 3 --num-ues 64 --nums_ue_thread 1 --nokrnmod 1 -T 1 > ue.log 2>&1 # The "-T 1" option means TDD config ``` - The number of UEs can set by using `--num-ues` option and the maximum UE number is 255 (with the `--mu*` options, otherwise 16). -- The umber of threads can set with the `--nums-ue-thread`. This number **SHALL NOT** be greater than the number of UEs. +- The number of threads can set with the `--nums-ue-thread`. This number **SHALL NOT** be greater than the number of UEs. + * At the time of writing, it seems to be enough to run on a single thread. +- The `--nokrnmod 1` option makes use of the preferred and supported tunnel interface. - How many UE that can be tested depends on hardware (server , PC, etc) performance in your environment. -# 11. Test with ping # +For example, running with 4 UEs: -In a third terminal, after around 10 seconds, the UE(s) shall be connected to the eNB: +```bash +$ ssh sudousername@machineC +cd ue_folder/cmake_targets +sudo -E ./ran_build/build/lte-uesoftmodem -O ../ci-scripts/conf_files/ue.nfapi.conf --L2-emul 3 --num-ues 64 --nums_ue_thread 1 --nokrnmod 1 > ue.log 2>&1 +sleep 10 +ifconfig +ens3 Link encap:Ethernet HWaddr XX:XX:XX:XX:XX:XX + inet addr:192.168.122.169 Bcast:192.168.122.255 Mask:255.255.255.0 +.... +oaitun_ue1 Link encap:UNSPEC HWaddr 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 + inet addr:192.172.0.2 P-t-P:192.172.0.2 Mask:255.255.255.0 +.... +oaitun_ue2 Link encap:UNSPEC HWaddr 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 + inet addr:192.172.0.3 P-t-P:192.172.0.3 Mask:255.255.255.0 +.... +oaitun_ue3 Link encap:UNSPEC HWaddr 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 + inet addr:192.172.0.4 P-t-P:192.172.0.4 Mask:255.255.255.0 +.... +oaitun_ue4 Link encap:UNSPEC HWaddr 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 + inet addr:192.172.0.5 P-t-P:192.172.0.5 Mask:255.255.255.0 +.... +oaitun_uem1 Link encap:UNSPEC HWaddr 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 + inet addr:10.0.2.2 P-t-P:10.0.2.2 Mask:255.255.255.0 +.... +.... +``` + +Having the 4 oaitun_ue tunnel interfaces up and with an allocated address means the connection with EPC went alright. + +# 10. Test with ping # + +In a third terminal, after around 10 seconds, the UE(s) shall be connected to the eNB: Check with ifconfig ```bash $ ssh sudousername@machineA -# Ping UE0 IP address based on the EPC pool used: in this example: -$ ping -c 20 192.168.200.2 # Ping UE1 IP address based on the EPC pool used: in this example: -$ ping -c 20 192.168.200.4 +$ ping -c 20 192.172.0.2 +# Ping UE4 IP address based on the EPC pool used: in this example: +$ ping -c 20 192.172.0.5 ``` -# 12. Limitations # - -Testing on the CI process is currently limited at time of writing. Improvements will be made soon. - - - - - +iperf operations can also be performed. +# 11. Limitations # +---- [oai wiki home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home) diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index e03700e4f5..aa16c771ae 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -62,9 +62,7 @@ #include "PHY/phy_extern.h" -#include "LAYER2/MAC/mac.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" -#include "LAYER2/MAC/mac_proto.h" #include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface.h" #include "common/utils/LOG/log_extern.h" @@ -161,7 +159,7 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t oai_subframe_ind(frame_rx, slot_rx); stop_meas(&nfapi_meas); - if (gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus|| + /*if (gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus|| gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs || gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs || gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles || @@ -175,7 +173,7 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t gNB->UL_INFO.cqi_ind.number_of_cqis, frame_rx, slot_rx, frame_tx, slot_tx); - } + }*/ } // **************************************** @@ -187,8 +185,8 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t wakeup_prach_gNB(gNB,NULL,proc->frame_rx,proc->slot_rx); } */ - // Call the scheduler + pthread_mutex_lock(&gNB->UL_INFO_mutex); gNB->UL_INFO.frame = frame_rx; gNB->UL_INFO.slot = slot_rx; @@ -326,7 +324,7 @@ static void *gNB_L1_thread( void *param ) { gNB_L1_rxtx_proc_t *L1_proc = &gNB_proc->L1_proc; //PHY_VARS_gNB *gNB = RC.gNB[0][proc->CC_id]; char thread_name[100]; - + // set default return value // set default return value gNB_thread_rxtx_status = 0; @@ -423,7 +421,7 @@ int wakeup_txfh(PHY_VARS_gNB *gNB,gNB_L1_rxtx_proc_t *proc,int frame_tx,int slot int waitret = 0, ret = 0, time_ns = 1000*1000; struct timespec now, abstime; - + // note this should depend on the numerology used by the TX L1 thread, set here for 500us slot time // note this should depend on the numerology used by the TX L1 thread, set here for 500us slot time VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GAIN_CONTROL,1); time_ns = time_ns/gNB->frame_parms.slots_per_subframe; @@ -445,27 +443,27 @@ int wakeup_txfh(PHY_VARS_gNB *gNB,gNB_L1_rxtx_proc_t *proc,int frame_tx,int slot VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GAIN_CONTROL,0); if (waitret == ETIMEDOUT) { - LOG_W(PHY,"Dropping TX slot (%d.%d) because FH is blocked more than 1 slot times (500us)\n",frame_tx,slot_tx); + LOG_W(PHY,"Dropping TX slot (%d.%d) because FH is blocked more than 1 slot times (500us)\n",frame_tx,slot_tx); - AssertFatal((ret=pthread_mutex_lock(&gNB->proc.mutex_RU_tx))==0,"mutex_lock returns %d\n",ret); - gNB->proc.RU_mask_tx = 0; - AssertFatal((ret=pthread_mutex_unlock(&gNB->proc.mutex_RU_tx))==0,"mutex_unlock returns %d\n",ret); - AssertFatal((ret=pthread_mutex_lock(&proc->mutex_RUs_tx))==0,"mutex_lock returns %d\n",ret); - proc->instance_cnt_RUs = 0; - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_UE,proc->instance_cnt_RUs); - AssertFatal((ret=pthread_mutex_unlock(&proc->mutex_RUs_tx))==0,"mutex_unlock returns %d\n",ret); + AssertFatal((ret=pthread_mutex_lock(&gNB->proc.mutex_RU_tx))==0,"mutex_lock returns %d\n",ret); + gNB->proc.RU_mask_tx = 0; + AssertFatal((ret=pthread_mutex_unlock(&gNB->proc.mutex_RU_tx))==0,"mutex_unlock returns %d\n",ret); + AssertFatal((ret=pthread_mutex_lock(&proc->mutex_RUs_tx))==0,"mutex_lock returns %d\n",ret); + proc->instance_cnt_RUs = 0; + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_UE,proc->instance_cnt_RUs); + AssertFatal((ret=pthread_mutex_unlock(&proc->mutex_RUs_tx))==0,"mutex_unlock returns %d\n",ret); - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE,1); - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE,0); + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE,1); + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE,0); + + return(-1); + } - return(-1); - } - for(int i=0; inum_RU; i++) { ru = gNB->RU_list[i]; ru_proc = &ru->proc; - + if (ru_proc->instance_cnt_gNBs == 0) { VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST_UE, 1); @@ -486,10 +484,10 @@ int wakeup_txfh(PHY_VARS_gNB *gNB,gNB_L1_rxtx_proc_t *proc,int frame_tx,int slot VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_UE, ru_proc->instance_cnt_gNBs); - LOG_D(PHY,"Signaling tx_thread_fh for %d.%d\n",frame_tx,slot_tx); + LOG_D(PHY,"Signaling tx_thread_fh for %d.%d\n",frame_tx,slot_tx); // the thread can now be woken up AssertFatal(pthread_cond_signal(&ru_proc->cond_gNBs) == 0, - "[gNB] ERROR pthread_cond_signal for gNB TXnp4 thread\n"); + "[gNB] ERROR pthread_cond_signal for gNB TXnp4 thread\n"); AssertFatal((ret=pthread_mutex_unlock(&ru_proc->mutex_gNBs))==0,"mutex_unlock returned %d\n",ret); } @@ -507,7 +505,7 @@ int wakeup_tx(PHY_VARS_gNB *gNB,int frame_rx,int slot_rx,int frame_tx,int slot_t AssertFatal((ret = pthread_mutex_lock(&L1_proc_tx->mutex))==0,"mutex_lock returns %d\n",ret); - while(L1_proc_tx->instance_cnt == 0){ + while(L1_proc_tx->instance_cnt == 0) { pthread_cond_wait(&L1_proc_tx->cond,&L1_proc_tx->mutex); } @@ -523,7 +521,7 @@ int wakeup_tx(PHY_VARS_gNB *gNB,int frame_rx,int slot_rx,int frame_tx,int slot_t VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_UE,1); VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_UE,0); - + // the thread can now be woken up // the thread can now be woken up AssertFatal(pthread_cond_signal(&L1_proc_tx->cond) == 0, "ERROR pthread_cond_signal for gNB L1 thread\n"); @@ -543,11 +541,11 @@ int wakeup_rxtx(PHY_VARS_gNB *gNB,RU_t *ru) { int time_ns = 50000; AssertFatal((ret=pthread_mutex_lock(&proc->mutex_RU))==0,"mutex_lock returns %d\n",ret); - for (i=0;inum_RU;i++) { + for (i=0; inum_RU; i++) { if (ru == gNB->RU_list[i]) { if ((proc->RU_mask&(1< 0) - LOG_E(PHY,"gNB %d frame %d, subframe %d : previous information from RU %d (num_RU %d,mask %x) has not been served yet!\n", - gNB->Mod_id,proc->frame_rx,proc->slot_rx,ru->idx,gNB->num_RU,proc->RU_mask); + LOG_E(PHY,"gNB %d frame %d, subframe %d : previous information from RU %d (num_RU %d,mask %x) has not been served yet!\n", + gNB->Mod_id,proc->frame_rx,proc->slot_rx,ru->idx,gNB->num_RU,proc->RU_mask); proc->RU_mask |= (1<mutex, &abstime)) == 0,"mutex_lock returns %d\n", ret); if (L1_proc->instance_cnt == 0) { // L1_thread is busy so abort the subframe - AssertFatal((ret=pthread_mutex_unlock( &L1_proc->mutex))==0,"muex_unlock return %d\n",ret); - LOG_W(PHY,"L1_thread isn't ready in %d.%d, aborting RX processing\n",ru_proc->frame_rx,ru_proc->tti_rx); - return(-1); + AssertFatal((ret=pthread_mutex_unlock( &L1_proc->mutex))==0,"muex_unlock return %d\n",ret); + LOG_W(PHY,"L1_thread isn't ready in %d.%d, aborting RX processing\n",ru_proc->frame_rx,ru_proc->tti_rx); + return(-1); } - + ++L1_proc->instance_cnt; - - // We have just received and processed the common part of a subframe, say n. - // TS_rx is the last received timestamp (start of 1st slot), TS_tx is the desired + // We have just received and processed the common part of a subframe, say n. + // TS_rx is the last received timestamp (start of 1st slot), TS_tx is the desired // transmitted timestamp of the next TX slot (first). + // The last (TS_rx mod samples_per_frame) was n*samples_per_tti, // we want to generate subframe (n+sf_ahead), so TS_tx = TX_rx+sf_ahead*samples_per_tti, // and proc->slot_tx = proc->slot_rx+sf_ahead @@ -603,7 +601,7 @@ int wakeup_rxtx(PHY_VARS_gNB *gNB,RU_t *ru) { exit_fun( "ERROR pthread_cond_signal" ); return(-1); } - + return(0); } /* @@ -707,9 +705,9 @@ static void* gNB_thread_prach( void* param ) { extern void init_td_thread(PHY_VARS_gNB *); extern void init_te_thread(PHY_VARS_gNB *); -static void* process_stats_thread(void* param) { +static void *process_stats_thread(void *param) { - PHY_VARS_gNB *gNB = (PHY_VARS_gNB*)param; + PHY_VARS_gNB *gNB = (PHY_VARS_gNB *)param; reset_meas(&gNB->dlsch_encoding_stats); reset_meas(&gNB->dlsch_scrambling_stats); @@ -736,9 +734,7 @@ void init_gNB_proc(int inst) { gNB_L1_rxtx_proc_t *L1_proc,*L1_proc_tx; // LOG_I(PHY,"%s(inst:%d) RC.nb_nr_CC[inst]:%d \n",__FUNCTION__,inst,RC.nb_nr_CC[inst]); gNB = RC.gNB[inst]; -#ifndef OCP_FRAMEWORK LOG_I(PHY,"Initializing gNB processes instance:%d CC_id %d \n",inst,CC_id); -#endif proc = &gNB->proc; L1_proc = &proc->L1_proc; @@ -952,9 +948,7 @@ void init_gNB(int single_thread_flag,int wait_for_sync) { NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL);*/ LOG_I(PHY,"Initializing gNB %d single_thread_flag:%d\n",inst,gNB->single_thread_flag); -#ifndef OCP_FRAMEWORK LOG_I(PHY,"Initializing gNB %d\n",inst); -#endif LOG_I(PHY,"Registering with MAC interface module (before %p)\n",gNB->if_inst); AssertFatal((gNB->if_inst = NR_IF_Module_init(inst))!=NULL,"Cannot register interface"); @@ -963,12 +957,12 @@ void init_gNB(int single_thread_flag,int wait_for_sync) { gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); LOG_I(PHY,"Setting indication lists\n"); - gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = gNB->rx_pdu_list; - gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = gNB->crc_pdu_list; - gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list; + gNB->UL_INFO.rx_ind.pdu_list = gNB->rx_pdu_list; + gNB->UL_INFO.crc_ind.crc_list = gNB->crc_pdu_list; + /*gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list; gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = gNB->harq_pdu_list; gNB->UL_INFO.cqi_ind.cqi_pdu_list = gNB->cqi_pdu_list; - gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list; + gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list;*/ gNB->prach_energy_counter = 0; } diff --git a/executables/nr-ru.c b/executables/nr-ru.c index fe10988462..3ea026f6e6 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -1,41 +1,24 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Campus SophiaTech, 450 Route des Chappes, CS 50193 - 06904 Biot Sophia Antipolis cedex, FRANCE - -*******************************************************************************/ - -/*! \file lte-enb.c - * \brief Top-level threads for eNodeB - * \author R. Knopp, F. Kaltenberger, Navid Nikaein - * \date 2012 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr, navid.nikaein@eurecom.fr - * \note - * \warning +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org */ + #define _GNU_SOURCE #include #include @@ -72,9 +55,7 @@ #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" -#include "LAYER2/MAC/mac.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" -#include "LAYER2/MAC/mac_proto.h" #include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface.h" @@ -93,7 +74,7 @@ unsigned short config_frames[4] = {2,9,11,13}; static int DEFBANDS[] = {7}; static int DEFENBS[] = {0}; static int DEFBFW[] = {0x00007fff}; - + //static int DEFNRBANDS[] = {7}; //static int DEFGNBS[] = {0}; @@ -713,7 +694,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { } -void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { +void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { RU_proc_t *proc = &ru->proc; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; @@ -792,7 +773,7 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %d\n",ru->idx, (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0 ); - AssertFatal(txs == siglen+sf_extension,"TX : Timeout (sent %u/%d)\n", txs, siglen); + //AssertFatal(txs == 0,"trx write function error %d\n", txs); } } @@ -884,7 +865,7 @@ void *ru_thread_prach( void *param ) { 0,0 ); } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_RU_PRACH_RX, 0 );*/ + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_RU_PRACH_RX, 0 );*/ if (release_thread(&proc->mutex_prach,&proc->instance_cnt_prach,"ru_prach_thread") < 0) break; } @@ -1111,16 +1092,16 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) { } } else if(N_RB == 106) { if (fp->threequarter_fs) { - cfg->sample_rate=46.08e6; - cfg->samples_per_frame = 460800; - cfg->tx_bw = 40e6; - cfg->rx_bw = 40e6; + cfg->sample_rate=46.08e6; + cfg->samples_per_frame = 460800; + cfg->tx_bw = 40e6; + cfg->rx_bw = 40e6; } else { - cfg->sample_rate=61.44e6; - cfg->samples_per_frame = 614400; - cfg->tx_bw = 40e6; - cfg->rx_bw = 40e6; + cfg->sample_rate=61.44e6; + cfg->samples_per_frame = 614400; + cfg->tx_bw = 40e6; + cfg->rx_bw = 40e6; } } else { AssertFatal(0==1,"N_RB %d not yet supported for numerology %d\n",N_RB,mu); @@ -1242,7 +1223,7 @@ void *ru_stats_thread(void *param) { if (ru->feprx) print_meas(&ru->ofdm_demod_stats,"feprx",NULL,NULL); - if (ru->feptx_ofdm){ + if (ru->feptx_ofdm) { print_meas(&ru->precoding_stats,"feptx_prec",NULL,NULL); print_meas(&ru->txdataF_copy_stats,"txdataF_copy",NULL,NULL); print_meas(&ru->ofdm_mod_stats,"feptx_ofdm",NULL,NULL); @@ -1251,7 +1232,7 @@ void *ru_stats_thread(void *param) { if (ru->fh_north_asynch_in) print_meas(&ru->rx_fhaul,"rx_fhaul",NULL,NULL); - print_meas(&ru->tx_fhaul,"tx_fhaul",NULL,NULL); + print_meas(&ru->tx_fhaul,"tx_fhaul",NULL,NULL); if (ru->fh_north_out) { print_meas(&ru->compression,"compression",NULL,NULL); print_meas(&ru->transport,"transport",NULL,NULL); @@ -1382,7 +1363,7 @@ void *ru_thread_tx( void *param ) { L1_proc->instance_cnt_RUs = 0; VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_UE,L1_proc->instance_cnt_RUs); AssertFatal(pthread_cond_signal(&L1_proc->cond_RUs) == 0, - "ERROR pthread_cond_signal for gNB_L1_thread\n"); + "ERROR pthread_cond_signal for gNB_L1_thread\n"); } //else AssertFatal(1==0,"gNB TX thread is not ready\n"); ret = pthread_mutex_unlock(&L1_proc->mutex_RUs_tx); AssertFatal(ret == 0,"mutex_unlock returns %d\n",ret); @@ -1482,6 +1463,16 @@ void *ru_thread( void *param ) { // if this is a slave RRU, try to synchronize on the DL frequency if ((ru->is_slave) && (ru->if_south == LOCAL_RF)) do_ru_synch(ru); + + // start trx write thread + if (ru->start_write_thread){ + if(ru->start_write_thread(ru) != 0){ + LOG_E(HW,"Could not start tx write thread\n"); + } + else{ + LOG_I(PHY,"tx write thread ready\n"); + } + } } pthread_mutex_lock(&proc->mutex_FH1); @@ -1691,14 +1682,15 @@ int stop_rf(RU_t *ru) { return 0; } +int start_write_thread(RU_t *ru) { + return(ru->rfdevice.trx_write_init(&ru->rfdevice)); +} void init_RU_proc(RU_t *ru) { int i=0; RU_proc_t *proc; char name[100]; -#ifndef OCP_FRAMEWORK LOG_I(PHY,"Initializing RU proc %d (%s,%s),\n",ru->idx,NB_functions[ru->function],NB_timing[ru->if_timing]); -#endif proc = &ru->proc; memset((void *)proc,0,sizeof(RU_proc_t)); proc->ru = ru; @@ -2086,6 +2078,7 @@ void set_function_spec_param(RU_t *ru) { ru->fh_south_out = tx_rf; // local synchronous RF TX ru->start_rf = start_rf; // need to start the local RF interface ru->stop_rf = stop_rf; + ru->start_write_thread = start_write_thread; // starting RF TX in different thread printf("configuring ru_id %u (start_rf %p)\n", ru->idx, start_rf); /* if (ru->function == gNodeB_3GPP) { // configure RF parameters only for 3GPP eNodeB, we need to get them from RAU otherwise @@ -2111,6 +2104,7 @@ void set_function_spec_param(RU_t *ru) { ru->fh_south_asynch_in = NULL; // no asynchronous UL ru->start_rf = NULL; // no local RF ru->stop_rf = NULL; + ru->start_write_thread = NULL; ru->nr_start_if = nr_start_if; // need to start if interface for IF5 ru->ifdevice.host_type = RAU_HOST; ru->ifdevice.eth_params = &ru->eth_params; @@ -2137,6 +2131,7 @@ void set_function_spec_param(RU_t *ru) { ru->fh_north_asynch_in = NULL; ru->start_rf = NULL; // no local RF ru->stop_rf = NULL; + ru->start_write_thread = NULL; ru->nr_start_if = nr_start_if; // need to start if interface for IF4p5 ru->ifdevice.host_type = RAU_HOST; ru->ifdevice.eth_params = &ru->eth_params; @@ -2166,7 +2161,6 @@ void init_NR_RU(char *rf_config_file) PHY_VARS_gNB *gNB0= (PHY_VARS_gNB *)NULL; NR_DL_FRAME_PARMS *fp = (NR_DL_FRAME_PARMS *)NULL; int i; - int CC_id; // create status mask RC.ru_mask = 0; pthread_mutex_init(&RC.ru_mutex,NULL); @@ -2295,9 +2289,27 @@ void RCconfig_RU(void) } } else { - RC.ru[j]->openair0_cfg.clock_source = unset; + RC.ru[j]->openair0_cfg.clock_source = unset; } + if (config_isparamset(RUParamList.paramarray[j], RU_SDR_TME_SRC)) { + if (strcmp(*(RUParamList.paramarray[j][RU_SDR_TME_SRC].strptr), "internal") == 0) { + RC.ru[j]->openair0_cfg.time_source = internal; + LOG_D(PHY, "RU time source set as internal\n"); + } else if (strcmp(*(RUParamList.paramarray[j][RU_SDR_TME_SRC].strptr), "external") == 0) { + RC.ru[j]->openair0_cfg.time_source = external; + LOG_D(PHY, "RU time source set as external\n"); + } else if (strcmp(*(RUParamList.paramarray[j][RU_SDR_TME_SRC].strptr), "gpsdo") == 0) { + RC.ru[j]->openair0_cfg.time_source = gpsdo; + LOG_D(PHY, "RU time source set as gpsdo\n"); + } else { + LOG_E(PHY, "Erroneous RU time source in the provided configuration file: '%s'\n", *(RUParamList.paramarray[j][RU_SDR_CLK_SRC].strptr)); + } + } + else { + RC.ru[j]->openair0_cfg.time_source = unset; + } + if (strcmp(*(RUParamList.paramarray[j][RU_LOCAL_RF_IDX].strptr), "yes") == 0) { if ( !(config_isparamset(RUParamList.paramarray[j],RU_LOCAL_IF_NAME_IDX)) ) { RC.ru[j]->if_south = LOCAL_RF; diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 04c515e556..f473d0161b 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -49,8 +49,6 @@ #include "PHY/phy_vars.h" #include "SCHED/sched_common_vars.h" #include "LAYER2/MAC/mac_vars.h" -#include "LAYER2/MAC/mac.h" -#include "LAYER2/MAC/mac_proto.h" #include "RRC/LTE/rrc_vars.h" #include "PHY_INTERFACE/phy_interface_vars.h" #include "gnb_config.h" @@ -108,7 +106,7 @@ static int wait_for_sync = 0; unsigned int mmapped_dma=0; int single_thread_flag=1; -static int8_t threequarter_fs=0; +int8_t threequarter_fs=0; uint64_t downlink_frequency[MAX_NUM_CCs][4]; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; @@ -171,6 +169,10 @@ uint32_t target_ul_mcs = 20; uint32_t timing_advance = 0; uint64_t num_missed_slots=0; // counter for the number of missed slots +int split73=0; +void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_t *data, int dataLen, int r_offset) { + AssertFatal(false, "Must not be called in this context\n"); +} extern void reset_opp_meas(void); extern void print_opp_meas(void); @@ -706,7 +708,6 @@ int stop_L1L2(module_id_t gnb_id) { */ int restart_L1L2(module_id_t gnb_id) { RU_t *ru = RC.ru[gnb_id]; - int cc_id; MessageDef *msg_p = NULL; LOG_W(GNB_APP, "restarting nr-softmodem\n"); /* block threads */ @@ -721,13 +722,9 @@ int restart_L1L2(module_id_t gnb_id) { memcpy(&ru->nr_frame_parms, &RC.gNB[gnb_id]->frame_parms, sizeof(NR_DL_FRAME_PARMS)); set_function_spec_param(RC.ru[gnb_id]); LOG_I(GNB_APP, "attempting to create ITTI tasks\n"); - - if (itti_create_task (TASK_RRC_ENB, rrc_enb_task, NULL) < 0) { - LOG_E(RRC, "Create task for RRC eNB failed\n"); - return -1; - } else { - LOG_I(RRC, "Re-created task for RRC gNB successfully\n"); - } + // No more rrc thread, as many race conditions are hidden behind + rrc_enb_init(); + itti_mark_task_ready(TASK_RRC_ENB); if (itti_create_task (TASK_L2L1, l2l1_task, NULL) < 0) { LOG_E(PDCP, "Create task for L2L1 failed\n"); @@ -770,23 +767,23 @@ static void wait_nfapi_init(char *thread_name) { void init_pdcp(void) { //if (!NODE_IS_DU(RC.rrc[0]->node_type)) { - pdcp_layer_init(); - uint32_t pdcp_initmask = (IS_SOFTMODEM_NOS1) ? - (PDCP_USE_NETLINK_BIT | LINK_ENB_PDCP_TO_IP_DRIVER_BIT) : LINK_ENB_PDCP_TO_GTPV1U_BIT; + pdcp_layer_init(); + uint32_t pdcp_initmask = (IS_SOFTMODEM_NOS1) ? + (PDCP_USE_NETLINK_BIT | LINK_ENB_PDCP_TO_IP_DRIVER_BIT) : LINK_ENB_PDCP_TO_GTPV1U_BIT; - if (IS_SOFTMODEM_NOS1){ - printf("IS_SOFTMODEM_NOS1 option enabled \n"); - pdcp_initmask = pdcp_initmask | ENB_NAS_USE_TUN_BIT | SOFTMODEM_NOKRNMOD_BIT ; - } + if (IS_SOFTMODEM_NOS1) { + printf("IS_SOFTMODEM_NOS1 option enabled \n"); + pdcp_initmask = pdcp_initmask | ENB_NAS_USE_TUN_BIT | SOFTMODEM_NOKRNMOD_BIT ; + } - pdcp_module_init(pdcp_initmask); + pdcp_module_init(pdcp_initmask); - /*if (NODE_IS_CU(RC.rrc[0]->node_type)) { - pdcp_set_rlc_data_req_func((send_rlc_data_req_func_t)proto_agent_send_rlc_data_req); - } else {*/ - pdcp_set_rlc_data_req_func((send_rlc_data_req_func_t) rlc_data_req); - pdcp_set_pdcp_data_ind_func((pdcp_data_ind_func_t) pdcp_data_ind); - //} + /*if (NODE_IS_CU(RC.rrc[0]->node_type)) { + pdcp_set_rlc_data_req_func((send_rlc_data_req_func_t)proto_agent_send_rlc_data_req); + } else {*/ + pdcp_set_rlc_data_req_func((send_rlc_data_req_func_t) rlc_data_req); + pdcp_set_pdcp_data_ind_func((pdcp_data_ind_func_t) pdcp_data_ind); + //} /*} else { pdcp_set_pdcp_data_ind_func((pdcp_data_ind_func_t) proto_agent_send_pdcp_data_ind); }*/ @@ -840,7 +837,7 @@ int main( int argc, char **argv ) MSC_INIT(MSC_E_UTRAN, THREAD_MAX+TASK_MAX); -init_opt(); + init_opt(); #ifdef PDCP_USE_NETLINK @@ -857,7 +854,7 @@ if(!IS_SOFTMODEM_NOS1) LOG_I(HW, "Version: %s\n", PACKAGE_VERSION); if(IS_SOFTMODEM_NOS1) - init_pdcp(); + init_pdcp(); if (RC.nb_nr_inst > 0) { // don't create if node doesn't connect to RRC/S1/GTP @@ -987,27 +984,27 @@ if(!IS_SOFTMODEM_NOS1) printf("oai_exit=%d\n",oai_exit); // stop threads -/*#ifdef XFORMS + /*#ifdef XFORMS - printf("waiting for XFORMS thread\n"); + printf("waiting for XFORMS thread\n"); - if (do_forms==1) { - pthread_join(forms_thread,&status); - fl_hide_form(form_stats->stats_form); - fl_free_form(form_stats->stats_form); + if (do_forms==1) { + pthread_join(forms_thread,&status); + fl_hide_form(form_stats->stats_form); + fl_free_form(form_stats->stats_form); - fl_hide_form(form_stats_l2->stats_form); - fl_free_form(form_stats_l2->stats_form); + fl_hide_form(form_stats_l2->stats_form); + fl_free_form(form_stats_l2->stats_form); - for(UE_id=0; UE_idphy_scope_gNB); - fl_free_form(form_enb[CC_id][UE_id]->phy_scope_gNB); - } - } - } + for(UE_id=0; UE_idphy_scope_gNB); + fl_free_form(form_enb[CC_id][UE_id]->phy_scope_gNB); + } + } + } -#endif*/ + #endif*/ printf("stopping MODEM threads\n"); // cleanup stop_gNB(NB_gNB_INST); diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 131710ee02..dbee6f1e6f 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -357,10 +357,11 @@ static void UE_synch(void *arg) { } void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { - uint32_t nb_rb, start_rb; - uint8_t nb_symb_sch, start_symbol, mcs, precod_nbr_layers, harq_pid, rvidx; - uint16_t n_rnti; + uint32_t rb_size, rb_start; + uint16_t rnti, l_prime_mask, n_rb0, n_rb1, pdu_bit_map; + uint8_t nr_of_symbols, start_symbol_index, mcs_index, mcs_table, nrOfLayers, harq_process_id, rv_index, dmrs_config_type; + uint8_t ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, ptrs_time_density, ptrs_freq_density; nr_dcireq_t dcireq; nr_scheduled_response_t scheduled_response; @@ -381,30 +382,53 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { scheduled_response.frame = proc->frame_rx; scheduled_response.slot = proc->nr_tti_rx; //--------------------------Temporary configuration-----------------------------// - n_rnti = 0x1234; - nb_rb = 50; - start_rb = 0; - nb_symb_sch = 12; - start_symbol = 2; - precod_nbr_layers = 1; - mcs = 9; - harq_pid = 0; - rvidx = 0; + rnti = 0x1234; + rb_size = 50; + rb_start = 0; + nr_of_symbols = 12; + start_symbol_index = 2; + nrOfLayers = 1; + mcs_index = 9; + mcs_table = 0; + harq_process_id = 0; + rv_index = 0; + l_prime_mask = get_l_prime(nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); + dmrs_config_type = 0; + ptrs_mcs1 = 2; + ptrs_mcs2 = 4; + ptrs_mcs3 = 10; + n_rb0 = 25; + n_rb1 = 75; + pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, mcs_index, mcs_table); + ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, rb_size); //------------------------------------------------------------------------------// scheduled_response.ul_config->slot = 8; scheduled_response.ul_config->number_pdus = 1; scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.rnti = n_rnti; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = nb_rb; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = start_rb; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = nb_symb_sch; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = start_symbol; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.mcs = mcs; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.rv = rvidx; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers; - scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rnti = rnti; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_size = rb_size; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_start = rb_start; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nr_of_symbols = nr_of_symbols; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_process_id; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t)); + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + + if (1 << ptrs_time_density >= nr_of_symbols) { + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + } nr_ue_scheduled_response(&scheduled_response); @@ -471,7 +495,6 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { } } - // no UL for now /* if (UE->mac_enabled==1) { @@ -521,7 +544,7 @@ void UE_processing(void *arg) { // then timing advance is processed and set to be applied in the next UL transmission */ if (UE->mac_enabled == 1) { - if (frame_tx == ul_time_alignment->ta_frame && slot_tx == ul_time_alignment->ta_slot){ + if (frame_tx == ul_time_alignment->ta_frame && slot_tx == ul_time_alignment->ta_slot) { LOG_D(PHY,"Applying timing advance -- frame %d -- slot %d\n", frame_tx, slot_tx); //if (nfapi_mode!=3){ @@ -591,7 +614,6 @@ void readFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp, bool toTrash) void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode); - void *dummy_tx[UE->frame_parms.nb_antennas_tx]; *timestamp += UE->frame_parms.get_samples_per_slot(1,&UE->frame_parms); for ( int size=UE->rx_offset ; size > 0 ; size -= UE->frame_parms.samples_per_subframe ) { @@ -753,7 +775,7 @@ void *UE_thread(void *arg) { #ifdef OAI_ADRV9371_ZC706 /*uint32_t total_gain_dB_prev = 0; if (total_gain_dB_prev != UE->rx_total_gain_dB) { - total_gain_dB_prev = UE->rx_total_gain_dB; + total_gain_dB_prev = UE->rx_total_gain_dB; openair0_cfg[0].rx_gain[0] = UE->rx_total_gain_dB; UE->rfdevice.trx_set_gains_func(&UE->rfdevice,&openair0_cfg[0]); }*/ @@ -837,7 +859,7 @@ void *UE_thread(void *arg) { if ( decoded_frame_rx != curMsg->proc.frame_rx && ((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx ) - LOG_D(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n", + LOG_E(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n", decoded_frame_rx, curMsg->proc.frame_rx ); nbSlotProcessing++; diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 53e407923f..9b2b704833 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -47,7 +47,6 @@ #include "PHY/NR_REFSIG/nr_mod_table.h" #include "LAYER2/MAC/mac_vars.h" -#include "LAYER2/MAC/mac_proto.h" #include "RRC/LTE/rrc_vars.h" #include "PHY_INTERFACE/phy_interface_vars.h" #include "openair1/SIMULATION/TOOLS/sim.h" @@ -127,7 +126,6 @@ volatile int start_eNB = 0; volatile int start_UE = 0; volatile int oai_exit = 0; -static clock_source_t clock_source = unset; int single_thread_flag=1; static double snr_dB=20; @@ -215,7 +213,7 @@ int emulate_rf = 0; tpool_t *Tpool; #ifdef UE_DLSCH_PARALLELISATION -tpool_t *Tpool_dl; + tpool_t *Tpool_dl; #endif @@ -311,8 +309,8 @@ static void *scope_thread(void *arg) { while (!oai_exit) { phy_scope_nrUE(form_nrue[0], - PHY_vars_UE_g[0][0], - 0,0,1); + PHY_vars_UE_g[0][0], + 0,0,1); usleep(100*1000); } @@ -383,9 +381,9 @@ static void get_options(void) { int tddflag=0, nonbiotflag, vcdflag=0; char *loopfile=NULL; int dumpframe=0; - //uint32_t noS1; //uint32_t nokrnmod; + //uint32_t nokrnmod; paramdef_t cmdline_params[] =CMDLINE_PARAMS_DESC_UE ; config_process_cmdline( cmdline_params,sizeof(cmdline_params)/sizeof(paramdef_t),NULL); @@ -529,12 +527,12 @@ void init_openair0(void) { else { openair0_cfg[card].sample_rate=122.88e6; openair0_cfg[card].samples_per_frame = 1228800; - } + } } else { LOG_E(PHY,"Unsupported numerology!\n"); exit(-1); } - }else if(frame_parms[0]->N_RB_DL == 273) { + } else if(frame_parms[0]->N_RB_DL == 273) { if (numerology==1) { if (frame_parms[0]->threequarter_fs) { AssertFatal(0 == 1,"three quarter sampling not supported for N_RB 273\n"); @@ -542,12 +540,12 @@ void init_openair0(void) { else { openair0_cfg[card].sample_rate=122.88e6; openair0_cfg[card].samples_per_frame = 1228800; - } + } } else { LOG_E(PHY,"Unsupported numerology!\n"); exit(-1); } - }else if(frame_parms[0]->N_RB_DL == 106) { + } else if(frame_parms[0]->N_RB_DL == 106) { if (numerology==0) { if (frame_parms[0]->threequarter_fs) { openair0_cfg[card].sample_rate=23.04e6; @@ -556,15 +554,15 @@ void init_openair0(void) { openair0_cfg[card].sample_rate=30.72e6; openair0_cfg[card].samples_per_frame = 307200; } - } else if (numerology==1) { + } else if (numerology==1) { if (frame_parms[0]->threequarter_fs) { - openair0_cfg[card].sample_rate=46.08e6; - openair0_cfg[card].samples_per_frame = 460800; + openair0_cfg[card].sample_rate=46.08e6; + openair0_cfg[card].samples_per_frame = 460800; } else { - openair0_cfg[card].sample_rate=61.44e6; - openair0_cfg[card].samples_per_frame = 614400; - } + openair0_cfg[card].sample_rate=61.44e6; + openair0_cfg[card].samples_per_frame = 614400; + } } else if (numerology==2) { openair0_cfg[card].sample_rate=122.88e6; openair0_cfg[card].samples_per_frame = 1228800; @@ -597,7 +595,8 @@ void init_openair0(void) { PHY_vars_UE_g[0][0]->frame_parms.nb_antennas_rx); openair0_cfg[card].Mod_id = 0; openair0_cfg[card].num_rb_dl=frame_parms[0]->N_RB_DL; - openair0_cfg[card].clock_source = clock_source; + openair0_cfg[card].clock_source = get_softmodem_params()->clock_source; + openair0_cfg[card].time_source = get_softmodem_params()->timing_source; openair0_cfg[card].tx_num_channels=min(2,PHY_vars_UE_g[0][0]->frame_parms.nb_antennas_tx); openair0_cfg[card].rx_num_channels=min(2,PHY_vars_UE_g[0][0]->frame_parms.nb_antennas_rx); @@ -639,7 +638,7 @@ void init_pdcp(void) { pdcp_initmask = pdcp_initmask | UE_NAS_USE_TUN_BIT; /*if (rlc_module_init() != 0) { - LOG_I(RLC, "Problem at RLC initiation \n"); + LOG_I(RLC, "Problem at RLC initiation \n"); } pdcp_layer_init(); nr_ip_over_LTE_DRB_preconfiguration();*/ @@ -649,6 +648,11 @@ void init_pdcp(void) { LOG_I(PDCP, "Before getting out from init_pdcp() \n"); } +// Stupid function addition because UE itti messages queues definition is common with eNB +void *rrc_enb_process_msg(void *notUsed) { + return NULL; +} + int main( int argc, char **argv ) { //uint8_t beta_ACK=0,beta_RI=0,beta_CQI=2; @@ -676,12 +680,12 @@ int main( int argc, char **argv ) { set_taus_seed (0); tpool_t pool; Tpool = &pool; - char params[]="-1,-1"; + char params[]="-1,-1"; initTpool(params, Tpool, false); #ifdef UE_DLSCH_PARALLELISATION tpool_t pool_dl; Tpool_dl = &pool_dl; - char params_dl[]="-1,-1,-1,-1, -1,-1,-1,-1,-1,-1,-1,-1,-1,-1"; + char params_dl[]="-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1"; initTpool(params_dl, Tpool_dl, false); #endif cpuf=get_cpu_freq_GHz(); diff --git a/executables/nr-uesoftmodem.h b/executables/nr-uesoftmodem.h index 7fad43e897..ba293324e3 100644 --- a/executables/nr-uesoftmodem.h +++ b/executables/nr-uesoftmodem.h @@ -59,7 +59,6 @@ /* optname helpstr paramflags XXXptr defXXXval type numelt */ /*----------------------------------------------------------------------------------------------------------------------------------------------------*/ #define CMDLINE_PARAMS_DESC_UE { \ - {"clock-source", CONFIG_HLP_EXCCLK, 0, iptr:&clock_source, defintval:0, TYPE_INT, 0}, \ {"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \ {"nr-dlsch-demod-shift", CONFIG_HLP_DLSHIFT, 0, iptr:(int32_t *)&nr_dlsch_demod_shift, defintval:0, TYPE_INT, 0}, \ {"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \ diff --git a/executables/softmodem-common.c b/executables/softmodem-common.c index f714fa2bd4..04a58413b5 100644 --- a/executables/softmodem-common.c +++ b/executables/softmodem-common.c @@ -81,8 +81,8 @@ char *get_softmodem_function(uint64_t *sofmodemfunc_mask_ptr) { } void get_common_options(uint32_t execmask) { - uint32_t online_log_messages; - uint32_t glog_level ; + uint32_t online_log_messages=0; + uint32_t glog_level=0 ; uint32_t start_telnetsrv = 0; uint32_t noS1 = 0, nokrnmod = 0, nonbiot = 0; uint32_t rfsim = 0, basicsim = 0, do_forms = 0; @@ -145,27 +145,27 @@ void get_common_options(uint32_t execmask) { if(worker_config != NULL) set_worker_conf(worker_config); } void softmodem_printresources(int sig, telnet_printfunc_t pf) { - struct rusage usage; - struct timespec stop; + struct rusage usage; + struct timespec stop; - clock_gettime(CLOCK_BOOTTIME, &stop); + clock_gettime(CLOCK_BOOTTIME, &stop); - uint64_t elapse = (stop.tv_sec - start.tv_sec) ; // in seconds + uint64_t elapse = (stop.tv_sec - start.tv_sec) ; // in seconds - int st = getrusage(RUSAGE_SELF,&usage); - if (!st) { - pf("\nRun time: %lluh %llus\n",(unsigned long long)elapse/3600,(unsigned long long)(elapse - (elapse/3600))); - pf("\tTime executing user inst.: %lds %ldus\n",(long)usage.ru_utime.tv_sec,(long)usage.ru_utime.tv_usec); - pf("\tTime executing system inst.: %lds %ldus\n",(long)usage.ru_stime.tv_sec,(long)usage.ru_stime.tv_usec); - pf("\tMax. Phy. memory usage: %ldkB\n",(long)usage.ru_maxrss); - pf("\tPage fault number (no io): %ld\n",(long)usage.ru_minflt); - pf("\tPage fault number (requiring io): %ld\n",(long)usage.ru_majflt); - pf("\tNumber of file system read: %ld\n",(long)usage.ru_inblock); - pf("\tNumber of filesystem write: %ld\n",(long)usage.ru_oublock); - pf("\tNumber of context switch (process origin, io...): %ld\n",(long)usage.ru_nvcsw); - pf("\tNumber of context switch (os origin, priority...): %ld\n",(long)usage.ru_nivcsw); - } + int st = getrusage(RUSAGE_SELF,&usage); + if (!st) { + pf("\nRun time: %lluh %llus\n",(unsigned long long)elapse/3600,(unsigned long long)(elapse - (elapse/3600))); + pf("\tTime executing user inst.: %lds %ldus\n",(long)usage.ru_utime.tv_sec,(long)usage.ru_utime.tv_usec); + pf("\tTime executing system inst.: %lds %ldus\n",(long)usage.ru_stime.tv_sec,(long)usage.ru_stime.tv_usec); + pf("\tMax. Phy. memory usage: %ldkB\n",(long)usage.ru_maxrss); + pf("\tPage fault number (no io): %ld\n",(long)usage.ru_minflt); + pf("\tPage fault number (requiring io): %ld\n",(long)usage.ru_majflt); + pf("\tNumber of file system read: %ld\n",(long)usage.ru_inblock); + pf("\tNumber of filesystem write: %ld\n",(long)usage.ru_oublock); + pf("\tNumber of context switch (process origin, io...): %ld\n",(long)usage.ru_nvcsw); + pf("\tNumber of context switch (os origin, priority...): %ld\n",(long)usage.ru_nivcsw); + } } void signal_handler(int sig) { @@ -180,9 +180,9 @@ void signal_handler(int sig) { backtrace_symbols_fd(array, size, 2); exit(-1); } else { - if(sig==SIGINT ||sig==SOFTMODEM_RTSIGNAL) - softmodem_printresources(sig,(telnet_printfunc_t)printf); - if (sig != SOFTMODEM_RTSIGNAL) { + if(sig==SIGINT ||sig==SOFTMODEM_RTSIGNAL) + softmodem_printresources(sig,(telnet_printfunc_t)printf); + if (sig != SOFTMODEM_RTSIGNAL) { printf("Linux signal %s...\n",strsignal(sig)); exit_function(__FILE__, __FUNCTION__, __LINE__,"softmodem starting exit procedure\n"); } @@ -192,7 +192,7 @@ void signal_handler(int sig) { void set_softmodem_sighandler(void) { - struct sigaction act,oldact; + struct sigaction act,oldact; clock_gettime(CLOCK_BOOTTIME, &start); memset(&act,0,sizeof(act)); act.sa_handler=signal_handler; @@ -201,6 +201,6 @@ void set_softmodem_sighandler(void) { signal(SIGSEGV, signal_handler); signal(SIGINT, signal_handler); signal(SIGTERM, signal_handler); - signal(SIGABRT, signal_handler); + signal(SIGABRT, signal_handler); } diff --git a/executables/softmodem-common.h b/executables/softmodem-common.h index cfed951469..0ac7b6449e 100644 --- a/executables/softmodem-common.h +++ b/executables/softmodem-common.h @@ -38,6 +38,11 @@ extern "C" #endif /* help strings definition for command line options, used in CMDLINE_XXX_DESC macros and printed when -h option is used */ #define CONFIG_HLP_RFCFGF "Configuration file for front-end (e.g. LMS7002M)\n" +#define CONFIG_HLP_SPLIT73 "Split 7.3 (below rate matching) option: ::" +#define CONFIG_HLP_TPOOL "Thread pool configuration: \n\ + default no pool (runs in calling thread),\n\ + list of cores, comma separated (negative value is no core affinity)\n\ + example: -1,3 launches two working threads one floating, the second set on core 3" #define CONFIG_HLP_ULMAXE "set the eNodeB max ULSCH erros\n" #define CONFIG_HLP_CALUER "set UE RX calibration\n" #define CONFIG_HLP_CALUERM "" @@ -53,6 +58,7 @@ extern "C" #define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n" #define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0" #define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n" +#define CONFIG_HLP_TME "tells hardware to use a time reference (0:internal, 1:external, 2:gpsdo)\n" #define CONFIG_HLP_USIM "use XOR autentication algo in case of test usim mode\n" #define CONFIG_HLP_NOSNGLT "Disables single-thread mode in lte-softmodem\n" #define CONFIG_HLP_DLF "Set the downlink frequency for all component carriers\n" @@ -88,6 +94,8 @@ extern "C" /* optname helpstr paramflags XXXptr defXXXval type numelt */ /*-----------------------------------------------------------------------------------------------------------------------------------------------------*/ #define RF_CONFIG_FILE softmodem_params.rf_config_file +#define SPLIT73 softmodem_params.split73 +#define TP_CONFIG softmodem_params.threadPoolConfig #define PHY_TEST softmodem_params.phy_test #define WAIT_FOR_SYNC softmodem_params.wait_for_sync #define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag @@ -103,9 +111,12 @@ extern "C" #define CMDLINE_PARAMS_DESC { \ {"rf-config-file", CONFIG_HLP_RFCFGF, 0, strptr:(char **)&RF_CONFIG_FILE, defstrval:NULL, TYPE_STRING, sizeof(RF_CONFIG_FILE)},\ + {"split73", CONFIG_HLP_SPLIT73, 0, strptr:(char **)&SPLIT73, defstrval:NULL, TYPE_STRING, sizeof(SPLIT73)},\ + {"thread-pool", CONFIG_HLP_TPOOL, 0, strptr:(char **)&TP_CONFIG, defstrval:"n", TYPE_STRING, sizeof(TP_CONFIG)}, \ {"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \ {"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \ - {"clock", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \ + {"clock-source", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \ + {"time-source", CONFIG_HLP_TME, 0, uptr:&TIMING_SOURCE, defintval:0, TYPE_UINT, 0}, \ {"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&WAIT_FOR_SYNC, defintval:0, TYPE_INT, 0}, \ {"single-thread-enable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&SINGLE_THREAD_FLAG, defintval:0, TYPE_INT, 0}, \ {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:0, TYPE_UINT64, 0}, \ @@ -191,6 +202,8 @@ typedef struct { uint64_t optmask; //THREAD_STRUCT thread_struct; char rf_config_file[1024]; + char split73[1024]; + char threadPoolConfig[1024]; int phy_test; uint8_t usim_test; int emulate_rf; diff --git a/nfapi/oai_integration/nfapi.c b/nfapi/oai_integration/nfapi.c index 4fc35fd951..86d1ae3127 100644 --- a/nfapi/oai_integration/nfapi.c +++ b/nfapi/oai_integration/nfapi.c @@ -29,7 +29,7 @@ typedef struct { nfapi_mode_t nfapi_mode; } nfapi_params_t; -static nfapi_params_t nfapi_params; +static nfapi_params_t nfapi_params = {0}; void set_thread_priority(int priority) { //printf("%s(priority:%d)\n", __FUNCTION__, priority); diff --git a/nfapi/oai_integration/nfapi_pnf.c b/nfapi/oai_integration/nfapi_pnf.c index f07fb1ad23..59857659c1 100644 --- a/nfapi/oai_integration/nfapi_pnf.c +++ b/nfapi/oai_integration/nfapi_pnf.c @@ -49,7 +49,6 @@ extern RAN_CONTEXT_t RC; #include "fapi_stub.h" //#include "fapi_l1.h" #include "common/utils/LOG/log.h" -#include "openair2/LAYER2/MAC/mac_proto.h" #include "PHY/INIT/phy_init.h" #include "PHY/LTE_TRANSPORT/transport_proto.h" @@ -692,13 +691,14 @@ void pnf_phy_deallocate_p7_vendor_ext(nfapi_p7_message_header_t *header) { free(header); } -int pnf_phy_hi_dci0_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_hi_dci0_request_t *req) { +int pnf_phy_hi_dci0_req(L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7, nfapi_hi_dci0_request_t *req) { if (req->hi_dci0_request_body.number_of_dci == 0 && req->hi_dci0_request_body.number_of_hi == 0) LOG_D(PHY,"[PNF] HI_DCI0_REQUEST SFN/SF:%05d dci:%d hi:%d\n", NFAPI_SFNSF2DEC(req->sfn_sf), req->hi_dci0_request_body.number_of_dci, req->hi_dci0_request_body.number_of_hi); //phy_info* phy = (phy_info*)(pnf_p7->user_data); struct PHY_VARS_eNB_s *eNB = RC.eNB[0][0]; - L1_rxtx_proc_t *proc = &eNB->proc.L1_proc; + if (proc ==NULL) + proc = &eNB->proc.L1_proc; for (int i=0; ihi_dci0_request_body.number_of_dci + req->hi_dci0_request_body.number_of_hi; i++) { //LOG_D(PHY,"[PNF] HI_DCI0_REQ sfn_sf:%d PDU[%d]\n", NFAPI_SFNSF2DEC(req->sfn_sf), i); @@ -719,7 +719,7 @@ int pnf_phy_hi_dci0_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_hi_dci0_request_t * return 0; } -int pnf_phy_dl_config_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request_t *req) { +int pnf_phy_dl_config_req(L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request_t *req) { if (RC.ru == 0) { return -1; } @@ -740,7 +740,8 @@ int pnf_phy_dl_config_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request int sfn = NFAPI_SFNSF2SFN(req->sfn_sf); int sf = NFAPI_SFNSF2SF(req->sfn_sf); struct PHY_VARS_eNB_s *eNB = RC.eNB[0][0]; - L1_rxtx_proc_t *proc = &eNB->proc.L1_proc; + if (proc==NULL) + proc = &eNB->proc.L1_proc; nfapi_dl_config_request_pdu_t *dl_config_pdu_list = req->dl_config_request_body.dl_config_pdu_list; LTE_eNB_PDCCH *pdcch_vars = &eNB->pdcch_vars[sf&1]; pdcch_vars->num_pdcch_symbols = req->dl_config_request_body.number_pdcch_ofdm_symbols; @@ -797,7 +798,7 @@ int pnf_phy_dl_config_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request uint8_t *dlsch_sdu = tx_pdus[UE_id][harq_pid]; memcpy(dlsch_sdu, tx_pdu->segments[0].segment_data, tx_pdu->segments[0].segment_length); //NFAPI_TRACE(NFAPI_TRACE_INFO, "%s() DLSCH:pdu_index:%d handle_nfapi_dlsch_pdu(eNB, proc_rxtx, dlsch_pdu, transport_blocks:%d sdu:%p) eNB->pdcch_vars[proc->subframe_tx & 1].num_pdcch_symbols:%d\n", __FUNCTION__, rel8_pdu->pdu_index, rel8_pdu->transport_blocks, dlsch_sdu, eNB->pdcch_vars[proc->subframe_tx & 1].num_pdcch_symbols); - handle_nfapi_dlsch_pdu( eNB, sfn,sf, &eNB->proc.L1_proc, &dl_config_pdu_list[i], rel8_pdu->transport_blocks-1, dlsch_sdu); + handle_nfapi_dlsch_pdu( eNB, sfn,sf, proc, &dl_config_pdu_list[i], rel8_pdu->transport_blocks-1, dlsch_sdu); } else { NFAPI_TRACE(NFAPI_TRACE_ERROR, "%s() DLSCH NULL TX PDU SFN/SF:%d PDU_INDEX:%d\n", __FUNCTION__, NFAPI_SFNSF2DEC(req->sfn_sf), rel8_pdu->pdu_index); } @@ -837,7 +838,7 @@ int pnf_phy_tx_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_tx_request_t *req) { return 0; } -int pnf_phy_ul_config_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_ul_config_request_t *req) { +int pnf_phy_ul_config_req(L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7, nfapi_ul_config_request_t *req) { if (0)LOG_D(PHY,"[PNF] UL_CONFIG_REQ %s() sfn_sf:%d pdu:%d rach_prach_frequency_resources:%d srs_present:%u\n", __FUNCTION__, NFAPI_SFNSF2DEC(req->sfn_sf), @@ -866,7 +867,8 @@ int pnf_phy_ul_config_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_ul_config_request uint16_t curr_sfn = NFAPI_SFNSF2SFN(req->sfn_sf); uint16_t curr_sf = NFAPI_SFNSF2SF(req->sfn_sf); struct PHY_VARS_eNB_s *eNB = RC.eNB[0][0]; - L1_rxtx_proc_t *proc = &eNB->proc.L1_proc; + if (proc==NULL) + proc = &eNB->proc.L1_proc; nfapi_ul_config_request_pdu_t *ul_config_pdu_list = req->ul_config_request_body.ul_config_pdu_list; for (int i=0; iul_config_request_body.number_of_pdus; i++) { diff --git a/nfapi/oai_integration/nfapi_pnf.h b/nfapi/oai_integration/nfapi_pnf.h index e213d785f1..2c8201737c 100644 --- a/nfapi/oai_integration/nfapi_pnf.h +++ b/nfapi/oai_integration/nfapi_pnf.h @@ -23,5 +23,5 @@ #define NFAPI_PNF_H__ int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind); void configure_nfapi_pnf(char *vnf_ip_addr, int vnf_p5_port, char *pnf_ip_addr, int pnf_p7_port, int vnf_p7_port); - +void oai_subframe_ind(uint16_t sfn, uint16_t sf); #endif diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 576144e1df..2c3809f5d4 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -22,6 +22,8 @@ #include "fapi_nr_ue_constants.h" #include "PHY/impl_defs_nr.h" +#define NFAPI_UE_MAX_NUM_CB 8 + /* typedef unsigned int uint32_t; typedef unsigned short uint16_t; @@ -256,40 +258,124 @@ typedef struct { } fapi_nr_ul_config_pucch_pdu; - typedef enum {pusch_freq_hopping_disabled = 0 , pusch_freq_hopping_enabled = 1}pusch_freq_hopping_t; - typedef struct{ - uint8_t aperiodicSRS_ResourceTrigger; - } fapi_nr_ul_srs_config_t; - typedef struct { - uint8_t bandwidth_part_ind; - uint16_t number_rbs; - uint16_t start_rb; - uint8_t frame_offset; - uint16_t number_symbols; - uint16_t start_symbol; - pusch_freq_hopping_t pusch_freq_hopping; - uint8_t mcs; - uint8_t ndi; - uint8_t rv; - uint8_t harq_process_nbr; - int8_t accumulated_delta_PUSCH; - int8_t absolute_delta_PUSCH; - uint8_t n_layers; - uint8_t tpmi; - uint8_t n_dmrs_cdm_groups; - uint8_t dmrs_ports[4]; - uint8_t n_front_load_symb; - fapi_nr_ul_srs_config_t srs_config; - uint8_t csi_reportTriggerSize; - uint8_t maxCodeBlockGroupsPerTransportBlock; - uint8_t ptrs_dmrs_association_port; - uint8_t beta_offset_ind; - } fapi_nr_ul_config_pusch_pdu_rel15_t; +typedef struct +{ + uint8_t rv_index; + uint8_t harq_process_id; + uint8_t new_data_indicator; + uint32_t tb_size; + uint16_t num_cb; + uint8_t cb_present_and_position[(NFAPI_UE_MAX_NUM_CB+7) / 8]; -typedef struct { +} nfapi_nr_ue_pusch_data_t; + +typedef struct +{ + uint16_t harq_ack_bit_length; + uint16_t csi_part1_bit_length; + uint16_t csi_part2_bit_length; + uint8_t alpha_scaling; + uint8_t beta_offset_harq_ack; + uint8_t beta_offset_csi1; + uint8_t beta_offset_csi2; + +} nfapi_nr_ue_pusch_uci_t; + +typedef struct +{ + uint16_t ptrs_port_index;//PT-RS antenna ports [TS38.214, sec6.2.3.1 and 38.212, section 7.3.1.1.2] Bitmap occupying the 12 LSBs with: bit 0: antenna port 0 bit 11: antenna port 11 and for each bit 0: PTRS port not used 1: PTRS port used + uint8_t ptrs_dmrs_port;//DMRS port corresponding to PTRS. + uint8_t ptrs_re_offset;//PT-RS resource element offset value taken from 0~11 +} nfapi_nr_ue_ptrs_ports_t; + +typedef struct +{ + uint8_t num_ptrs_ports; + nfapi_nr_ue_ptrs_ports_t* ptrs_ports_list; + uint8_t ptrs_time_density; + uint8_t ptrs_freq_density; + uint8_t ul_ptrs_power; + +}nfapi_nr_ue_pusch_ptrs_t; + +typedef struct +{ + uint8_t low_papr_group_number;//Group number for Low PAPR sequence generation. + uint16_t low_papr_sequence_number;//[TS38.211, sec 5.2.2] For DFT-S-OFDM. + uint8_t ul_ptrs_sample_density;//Number of PTRS groups [But I suppose this sentence is misplaced, so as the next one. --Chenyu] + uint8_t ul_ptrs_time_density_transform_precoding;//Number of samples per PTRS group + +} nfapi_nr_ue_dfts_ofdm_t; + +typedef struct +{ + uint16_t beam_idx;//Index of the digital beam weight vector pre-stored at cell configuration. The vector maps this input port to output TXRUs. Value: 0->65535 + +}nfapi_nr_ue_dig_bf_interface_t; + +typedef struct +{ + nfapi_nr_ue_dig_bf_interface_t* dig_bf_interface_list; + +} nfapi_nr_ue_ul_beamforming_number_of_prgs_t; + +typedef struct +{ + uint16_t num_prgs; + uint16_t prg_size; + //watchout: dig_bf_interface here, in table 3-43 it's dig_bf_interfaces + uint8_t dig_bf_interface; + nfapi_nr_ue_ul_beamforming_number_of_prgs_t* prgs_list;// + +} nfapi_nr_ue_ul_beamforming_t; + +typedef struct +{ + uint16_t pdu_bit_map;//Bitmap indicating presence of optional PDUs (see above) uint16_t rnti; - fapi_nr_ul_config_pusch_pdu_rel15_t ulsch_pdu_rel15; -} fapi_nr_ul_config_pusch_pdu; + uint32_t handle;//An opaque handling returned in the RxData.indication and/or UCI.indication message + //BWP + uint16_t bwp_size; + uint16_t bwp_start; + uint8_t subcarrier_spacing; + uint8_t cyclic_prefix; + //pusch information always include + uint16_t target_code_rate; + uint8_t qam_mod_order; + uint8_t mcs_index; + uint8_t mcs_table; + uint8_t transform_precoding; + uint16_t data_scrambling_id; + uint8_t nrOfLayers; + //DMRS + uint16_t ul_dmrs_symb_pos; + uint8_t dmrs_config_type; + uint16_t ul_dmrs_scrambling_id; + uint8_t scid; + uint8_t num_dmrs_cdm_grps_no_data; + uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used + //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] + uint8_t resource_alloc; + uint8_t rb_bitmap[36];// + uint16_t rb_start; + uint16_t rb_size; + uint8_t vrb_to_prb_mapping; + uint8_t frequency_hopping; + uint16_t tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] + uint8_t uplink_frequency_shift_7p5khz; + //Resource Allocation in time domain + uint8_t start_symbol_index; + uint8_t nr_of_symbols; + //Optional Data only included if indicated in pduBitmap + nfapi_nr_ue_pusch_data_t pusch_data; + nfapi_nr_ue_pusch_uci_t pusch_uci; + nfapi_nr_ue_pusch_ptrs_t pusch_ptrs; + nfapi_nr_ue_dfts_ofdm_t dfts_ofdm; + //beamforming + nfapi_nr_ue_ul_beamforming_t beamforming; + //OAI specific + int8_t absolute_delta_PUSCH; +} nfapi_nr_ue_pusch_pdu_t; typedef struct { @@ -300,7 +386,7 @@ typedef struct { union { fapi_nr_ul_config_prach_pdu prach_config_pdu; fapi_nr_ul_config_pucch_pdu pucch_config_pdu; - fapi_nr_ul_config_pusch_pdu ulsch_config_pdu; + nfapi_nr_ue_pusch_pdu_t pusch_config_pdu; fapi_nr_ul_config_srs_pdu srs_config_pdu; }; } fapi_nr_ul_config_request_pdu_t; @@ -341,7 +427,6 @@ typedef struct { uint8_t SubcarrierSpacing; uint16_t number_rbs; uint16_t start_rb; - uint8_t frame_offset; uint16_t number_symbols; uint16_t start_symbol; uint16_t dlDmrsSymbPos; diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h index 5fe1c53a54..650bda4f78 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h @@ -10,6 +10,7 @@ #define _NFAPI_NR_INTERFACE_H_ #include "nfapi_interface.h" +#include #define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5 #define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64 diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index f69c928ed2..54b592202d 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -19,6 +19,7 @@ #define NFAPI_MAX_NUM_UL_UE_PER_GROUP 6 #define NFAPI_MAX_NUM_UL_PDU 8 +#define NFAPI_MAX_NUM_UCI_INDICATION 8 #define NFAPI_MAX_NUM_GROUPS 8 #define NFAPI_MAX_NUM_CB 8 @@ -1393,7 +1394,7 @@ typedef struct uint16_t timing_advance;//Timing advance 𝑇𝐴 measured for the UE [TS 38.213, Section 4.2] NTA_new = NTA_old + (TA − 31) ⋅ 16 ⋅ 64⁄2μ Value: 0 → 63 0xffff should be set if this field is invalid uint16_t rssi; //variable ! fixme - uint32_t pdu; //MAC PDU + uint8_t *pdu; //MAC PDU } nfapi_nr_rx_data_pdu_t; @@ -1519,8 +1520,8 @@ typedef struct uint8_t ul_cqi; uint16_t timing_advance; uint16_t rssi; - nfapi_nr_sr_pdu_0_1_t sr;//67 - nfapi_nr_harq_pdu_0_1_t harq;//68 + nfapi_nr_sr_pdu_0_1_t *sr;//67 + nfapi_nr_harq_pdu_0_1_t *harq;//68 }nfapi_nr_uci_pucch_pdu_format_0_1_t; @@ -1542,28 +1543,22 @@ typedef struct }nfapi_nr_uci_pucch_pdu_format_2_3_4_t; -//for SR, HARQ and CSI Part 1/ 2 PDUs +typedef enum { + NFAPI_NR_UCI_PDCCH_PDU_TYPE = 0, + NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE = 1, + NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE = 2, +} nfapi_nr_uci_pdu_type_e; typedef struct { - nfapi_nr_uci_pusch_pdu_t* pusch_pdu; - nfapi_nr_uci_pucch_pdu_format_0_1_t* pucch_pdu_format_0_1; - nfapi_nr_uci_pucch_pdu_format_2_3_4_t* pucch_pdu_format_2_3_4; - nfapi_nr_sr_pdu_0_1_t* sr_pdu_0_1; - nfapi_nr_sr_pdu_2_3_4_t* sr_pdu_2_3_4; - nfapi_nr_harq_pdu_0_1_t* harq_pdu_0_1; - nfapi_nr_harq_pdu_2_3_4_t* harq_pdu_2_3_4; - nfapi_nr_csi_part1_pdu_t* csi_part1_pdu; - nfapi_nr_csi_part2_pdu_t* csi_part2_pdu; - -} nfapi_nr_uci_pdu_information_t; - -typedef struct -{ - uint16_t pdu_type; + uint16_t pdu_type; // 0 for PDU on PUSCH, 1 for PUCCH format 0 or 1, 2 for PUCCH format 2 to 4 uint16_t pdu_size; - nfapi_nr_uci_pdu_information_t uci_pdu; - + union + { + nfapi_nr_uci_pusch_pdu_t pusch_pdu; + nfapi_nr_uci_pucch_pdu_format_0_1_t pucch_pdu_format_0_1; + nfapi_nr_uci_pucch_pdu_format_2_3_4_t pucch_pdu_format_2_3_4; + }; } nfapi_nr_uci_t; typedef struct @@ -1571,7 +1566,7 @@ typedef struct uint16_t sfn; uint16_t slot; uint16_t num_ucis; - nfapi_nr_uci_t* uci_list; + nfapi_nr_uci_t uci_list[NFAPI_MAX_NUM_UCI_INDICATION]; } nfapi_nr_uci_indication_t; diff --git a/nfapi/open-nFAPI/pnf/public_inc/nfapi_pnf_interface.h b/nfapi/open-nFAPI/pnf/public_inc/nfapi_pnf_interface.h index 8d17416a41..d169177d6b 100644 --- a/nfapi/open-nFAPI/pnf/public_inc/nfapi_pnf_interface.h +++ b/nfapi/open-nFAPI/pnf/public_inc/nfapi_pnf_interface.h @@ -24,6 +24,7 @@ extern "C" { #include "nfapi_interface.h" #include "debug.h" +#include #include @@ -619,21 +620,21 @@ typedef struct nfapi_pnf_p7_config * \param req A pointer to the dl config request message structure * \return not currently used */ - int (*dl_config_req)(nfapi_pnf_p7_config_t* config, nfapi_dl_config_request_t* req); + int (*dl_config_req)(L1_rxtx_proc_t *proc,nfapi_pnf_p7_config_t* config, nfapi_dl_config_request_t* req); /*! A callback for the UL_CONFIG.request * \param config A poiner to the PNF P7 config * \param req A pointer to the ul config request message structure * \return not currently used */ - int (*ul_config_req)(nfapi_pnf_p7_config_t* config, nfapi_ul_config_request_t* req); + int (*ul_config_req)(L1_rxtx_proc_t *proc,nfapi_pnf_p7_config_t* config, nfapi_ul_config_request_t* req); /*! A callback for the HI_DCI0.request * \param config A poiner to the PNF P7 config * \param req A pointer to the hi dci0 request message structure * \return not currently used */ - int (*hi_dci0_req)(nfapi_pnf_p7_config_t* config, nfapi_hi_dci0_request_t* req); + int (*hi_dci0_req)(L1_rxtx_proc_t *proc,nfapi_pnf_p7_config_t* config, nfapi_hi_dci0_request_t* req); /*! A callback for the TX_REQ.request * \param config A poiner to the PNF P7 config diff --git a/nfapi/open-nFAPI/pnf/src/pnf_interface.c b/nfapi/open-nFAPI/pnf/src/pnf_interface.c index 7310fc0c66..dda0d0fdc6 100644 --- a/nfapi/open-nFAPI/pnf/src/pnf_interface.c +++ b/nfapi/open-nFAPI/pnf/src/pnf_interface.c @@ -39,7 +39,7 @@ nfapi_pnf_config_t* nfapi_pnf_config_create() _this->_public.codec_config.allocate = &malloc; _this->_public.codec_config.deallocate = &free; - return &(_this->_public); + return (nfapi_pnf_config_t* )_this; } void nfapi_pnf_config_destory(nfapi_pnf_config_t* config) diff --git a/nfapi/open-nFAPI/pnf/src/pnf_p7.c b/nfapi/open-nFAPI/pnf/src/pnf_p7.c index 9446730375..5ba912e059 100644 --- a/nfapi/open-nFAPI/pnf/src/pnf_p7.c +++ b/nfapi/open-nFAPI/pnf/src/pnf_p7.c @@ -576,20 +576,20 @@ void send_dummy_subframe(pnf_p7_t* pnf_p7, uint16_t sfn_sf) { pnf_p7->_public.dummy_subframe.dl_config_req->sfn_sf = sfn_sf; //NFAPI_TRACE(NFAPI_TRACE_INFO, "Dummy dl_config_req - enter\n"); - (pnf_p7->_public.dl_config_req)(&(pnf_p7->_public), pnf_p7->_public.dummy_subframe.dl_config_req); + (pnf_p7->_public.dl_config_req)(NULL, &(pnf_p7->_public), pnf_p7->_public.dummy_subframe.dl_config_req); //NFAPI_TRACE(NFAPI_TRACE_INFO, "Dummy dl_config_req - exit\n"); } if(pnf_p7->_public.ul_config_req && pnf_p7->_public.dummy_subframe.ul_config_req) { pnf_p7->_public.dummy_subframe.ul_config_req->sfn_sf = sfn_sf; NFAPI_TRACE(NFAPI_TRACE_INFO, "Dummy ul_config_req - enter\n"); - (pnf_p7->_public.ul_config_req)(&pnf_p7->_public, pnf_p7->_public.dummy_subframe.ul_config_req); + (pnf_p7->_public.ul_config_req)(NULL, &pnf_p7->_public, pnf_p7->_public.dummy_subframe.ul_config_req); } if(pnf_p7->_public.hi_dci0_req && pnf_p7->_public.dummy_subframe.hi_dci0_req) { pnf_p7->_public.dummy_subframe.hi_dci0_req->sfn_sf = sfn_sf; NFAPI_TRACE(NFAPI_TRACE_INFO, "Dummy hi_dci0 - enter\n"); - (pnf_p7->_public.hi_dci0_req)(&pnf_p7->_public, pnf_p7->_public.dummy_subframe.hi_dci0_req); + (pnf_p7->_public.hi_dci0_req)(NULL, &pnf_p7->_public, pnf_p7->_public.dummy_subframe.hi_dci0_req); } if(pnf_p7->_public.lbt_dl_config_req && pnf_p7->_public.dummy_subframe.lbt_dl_config_req) { @@ -699,7 +699,7 @@ int pnf_p7_subframe_ind(pnf_p7_t* pnf_p7, uint16_t phy_id, uint16_t sfn_sf) if(tx_subframe_buffer->dl_config_req != 0) { if(pnf_p7->_public.dl_config_req) - (pnf_p7->_public.dl_config_req)(&(pnf_p7->_public), tx_subframe_buffer->dl_config_req); + (pnf_p7->_public.dl_config_req)(NULL, &(pnf_p7->_public), tx_subframe_buffer->dl_config_req); //deallocate_nfapi_dl_config_request(subframe_buffer->dl_config_req, pnf_p7); } @@ -709,14 +709,14 @@ int pnf_p7_subframe_ind(pnf_p7_t* pnf_p7, uint16_t phy_id, uint16_t sfn_sf) if(pnf_p7->_public.dl_config_req && pnf_p7->_public.dummy_subframe.dl_config_req) { pnf_p7->_public.dummy_subframe.dl_config_req->sfn_sf = sfn_sf_tx; - (pnf_p7->_public.dl_config_req)(&(pnf_p7->_public), pnf_p7->_public.dummy_subframe.dl_config_req); + (pnf_p7->_public.dl_config_req)(NULL, &(pnf_p7->_public), pnf_p7->_public.dummy_subframe.dl_config_req); } } if(tx_subframe_buffer->hi_dci0_req != 0) { if(pnf_p7->_public.hi_dci0_req) - (pnf_p7->_public.hi_dci0_req)(&(pnf_p7->_public), tx_subframe_buffer->hi_dci0_req); + (pnf_p7->_public.hi_dci0_req)(NULL, &(pnf_p7->_public), tx_subframe_buffer->hi_dci0_req); //deallocate_nfapi_hi_dci0_request(subframe_buffer->hi_dci0_req, pnf_p7); } @@ -726,7 +726,7 @@ int pnf_p7_subframe_ind(pnf_p7_t* pnf_p7, uint16_t phy_id, uint16_t sfn_sf) if(pnf_p7->_public.hi_dci0_req && pnf_p7->_public.dummy_subframe.hi_dci0_req) { pnf_p7->_public.dummy_subframe.hi_dci0_req->sfn_sf = sfn_sf_tx; - (pnf_p7->_public.hi_dci0_req)(&(pnf_p7->_public), pnf_p7->_public.dummy_subframe.hi_dci0_req); + (pnf_p7->_public.hi_dci0_req)(NULL, &(pnf_p7->_public), pnf_p7->_public.dummy_subframe.hi_dci0_req); } } @@ -777,7 +777,7 @@ int pnf_p7_subframe_ind(pnf_p7_t* pnf_p7, uint16_t phy_id, uint16_t sfn_sf) if(subframe_buffer->ul_config_req != 0) { if(pnf_p7->_public.ul_config_req) - (pnf_p7->_public.ul_config_req)(&(pnf_p7->_public), subframe_buffer->ul_config_req); + (pnf_p7->_public.ul_config_req)(NULL, &(pnf_p7->_public), subframe_buffer->ul_config_req); //deallocate_nfapi_ul_config_request(subframe_buffer->ul_config_req, pnf_p7); } @@ -787,7 +787,7 @@ int pnf_p7_subframe_ind(pnf_p7_t* pnf_p7, uint16_t phy_id, uint16_t sfn_sf) if(pnf_p7->_public.ul_config_req && pnf_p7->_public.dummy_subframe.ul_config_req) { pnf_p7->_public.dummy_subframe.ul_config_req->sfn_sf = sfn_sf; - (pnf_p7->_public.ul_config_req)(&(pnf_p7->_public), pnf_p7->_public.dummy_subframe.ul_config_req); + (pnf_p7->_public.ul_config_req)(NULL, &(pnf_p7->_public), pnf_p7->_public.dummy_subframe.ul_config_req); } } diff --git a/nfapi/open-nFAPI/vnf/src/vnf_interface.c b/nfapi/open-nFAPI/vnf/src/vnf_interface.c index 0aba0a29f5..59d7f3eb4f 100644 --- a/nfapi/open-nFAPI/vnf/src/vnf_interface.c +++ b/nfapi/open-nFAPI/vnf/src/vnf_interface.c @@ -55,7 +55,7 @@ nfapi_vnf_config_t* nfapi_vnf_config_create() _this->_public.codec_config.deallocate = &free; - return &(_this->_public); + return (nfapi_vnf_config_t* )_this; } void nfapi_vnf_config_destory(nfapi_vnf_config_t* config) diff --git a/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c b/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c index 35bd5e4c1b..a0efeeb5f4 100644 --- a/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c +++ b/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c @@ -47,7 +47,7 @@ nfapi_vnf_p7_config_t* nfapi_vnf_p7_config_create() _this->_public.codec_config.deallocate = &free; - return &(_this->_public); + return (nfapi_vnf_p7_config_t*)_this; } void nfapi_vnf_p7_config_destory(nfapi_vnf_p7_config_t* config) diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index d47d6e7755..b3c9f3117c 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -18,7 +18,6 @@ * For more information about the OpenAirInterface (OAI) Software Alliance: * contact@openairinterface.org */ -// add GPU mode (-G 1) #include #include @@ -26,12 +25,11 @@ #include #include "assertions.h" #include "SIMULATION/TOOLS/sim.h" -#include "PHY/CODING/nrLDPC_encoder/defs.h" -#include "PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h" +#include "PHY/CODING/nrLDPC_extern.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" - -#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h" - +// extern "C" { +#include "openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h" +// } #define MAX_NUM_DLSCH_SEGMENTS 16 #define MAX_BLOCK_LENGTH 8448 @@ -88,6 +86,7 @@ typedef struct { RAN_CONTEXT_t RC; PHY_VARS_UE ***PHY_vars_UE_g; uint16_t NB_UE_INST = 1; +nrLDPC_encoderfunc_t encoder_orig; short lift_size[51]= {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}; @@ -118,7 +117,6 @@ int test_ldpc(short No_iteration, double sigma; sigma = 1.0/sqrt(2*SNR); - opp_enabled=1; cpu_freq_GHz = get_cpu_freq_GHz(); //short test_input[block_length]; @@ -290,16 +288,19 @@ int test_ldpc(short No_iteration, no_punctured_columns=(int)((nrows-2)*Zc+block_length-block_length*(1/((float)nom_rate/(float)denom_rate)))/Zc; // printf("puncture:%d\n",no_punctured_columns); removed_bit=(nrows-no_punctured_columns-2) * Zc+block_length-(int)(block_length/((float)nom_rate/(float)denom_rate)); + encoder_implemparams_t impp=INIT0_LDPCIMPLEMPARAMS; + + impp.gen_code=1; if (ntrials==0) - ldpc_encoder_orig(test_input[0],channel_input[0], Zc, BG, block_length, BG, 1); - + encoder_orig(test_input,channel_input, Zc, BG, block_length, BG, &impp); + impp.gen_code=0; for (trial=0; trial < ntrials; trial++) { segment_bler = 0; //// encoder start_meas(&time); for(j=0;j 1280, 2401 -> 2560 - short run_cuda = 0; + short No_iteration=5; int n_segments=1; //double rate=0.333; + short run_cuda = 0; + int nom_rate=1; int denom_rate=3; double SNR0=-2.0,SNR,SNR_lin; @@ -540,9 +540,9 @@ int main(int argc, char *argv[]) time_stats_t time_optim[10], time_decoder[10]; n_iter_stats_t dec_iter[3]; - short BG=0,Zc,Kb; + short BG=0,Zc,Kb=0; - while ((c = getopt (argc, argv, "q:r:s:S:l:n:d:i:t:u:h:G:")) != -1) + while ((c = getopt (argc, argv, "q:r:s:S:l:G:n:d:i:t:u:h")) != -1) switch (c) { case 'q': @@ -552,10 +552,7 @@ int main(int argc, char *argv[]) case 'r': nom_rate = atoi(optarg); break; - case 'G': - run_cuda = atoi(optarg); - break; - + case 'd': denom_rate = atoi(optarg); break; @@ -563,6 +560,10 @@ int main(int argc, char *argv[]) case 'l': block_length = atoi(optarg); break; + + case 'G': + run_cuda = atoi(optarg); + break; case 'n': n_trials = atoi(optarg); @@ -587,7 +588,6 @@ int main(int argc, char *argv[]) case 'u': test_uncoded = atoi(optarg); break; - case 'h': default: @@ -599,6 +599,7 @@ int main(int argc, char *argv[]) printf("-r Nominator rate, (1, 2, 22), Default: 1\n"); printf("-d Denominator rate, (3, 5, 25), Default: 1\n"); printf("-l Block length (l > 3840 -> BG1, rest BG2 ), Default: 8448\n"); + printf("-G give 1 to run cuda for LDPC, Default: 0\n"); printf("-n Number of simulation trials, Default: 1\n"); //printf("-M MCS2 for TB 2\n"); printf("-s SNR per information bit (EbNo) in dB, Default: -2\n"); @@ -606,7 +607,6 @@ int main(int argc, char *argv[]) printf("-t SNR simulation step, Default: 0.1\n"); printf("-i Max decoder iterations, Default: 5\n"); printf("-u Set SNR per coded bit, Default: 0\n"); - printf("-G set 1 to run cuda for ldpc \n"); exit(1); break; } @@ -616,10 +616,10 @@ int main(int argc, char *argv[]) printf("block length %d: \n", block_length); printf("n_trials %d: \n", n_trials); printf("SNR0 %f: \n", SNR0); - - + load_nrLDPClib(); + load_nrLDPClib_ref("_orig", &encoder_orig); //for (block_length=8;block_length<=MAX_BLOCK_LENGTH;block_length+=8) diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c index dbf671fdfb..785b588b9f 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c @@ -1,4 +1,4 @@ -/* +/* * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. @@ -18,7 +18,7 @@ * For more information about the OpenAirInterface (OAI) Software Alliance: * contact@openairinterface.org */ - + /*!\file nrLDPC_decoder.c * \brief Defines the LDPC decoder * \author Sebastian Wagner (TCL Communications) Email: diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h index 10b45ac0e7..b76750459d 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h +++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h @@ -135,25 +135,25 @@ static inline void nrLDPC_llr2llrProcBuf(t_nrLDPC_lut* p_lut, int8_t* llr, t_nrL */ static inline void nrLDPC_llr2CnProcBuf_BG1(t_nrLDPC_lut* p_lut, int8_t* llr, t_nrLDPC_procBuf* p_procBuf, uint16_t Z) { - const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0]; - const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1]; - const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2]; - const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3]; - const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4]; - const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5]; - const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6]; - const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7]; - const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8]; + const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0]; + const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1]; + const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2]; + const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3]; + const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4]; + const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5]; + const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6]; + const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7]; + const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8]; - const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->posBnInCnProcBuf[0]; - const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->posBnInCnProcBuf[1]; - const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->posBnInCnProcBuf[2]; - const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->posBnInCnProcBuf[3]; - const uint8_t (*lut_posBnInCnProcBuf_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->posBnInCnProcBuf[4]; - const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->posBnInCnProcBuf[5]; - const uint8_t (*lut_posBnInCnProcBuf_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->posBnInCnProcBuf[6]; - const uint8_t (*lut_posBnInCnProcBuf_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->posBnInCnProcBuf[7]; - const uint8_t (*lut_posBnInCnProcBuf_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->posBnInCnProcBuf[8]; + const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->posBnInCnProcBuf[0]; + const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->posBnInCnProcBuf[1]; + const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->posBnInCnProcBuf[2]; + const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->posBnInCnProcBuf[3]; + const uint8_t (*lut_posBnInCnProcBuf_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->posBnInCnProcBuf[4]; + const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->posBnInCnProcBuf[5]; + const uint8_t (*lut_posBnInCnProcBuf_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->posBnInCnProcBuf[6]; + const uint8_t (*lut_posBnInCnProcBuf_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->posBnInCnProcBuf[7]; + const uint8_t (*lut_posBnInCnProcBuf_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->posBnInCnProcBuf[8]; const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups; const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups; @@ -344,19 +344,19 @@ static inline void nrLDPC_llr2CnProcBuf_BG1(t_nrLDPC_lut* p_lut, int8_t* llr, t_ */ static inline void nrLDPC_llr2CnProcBuf_BG2(t_nrLDPC_lut* p_lut, int8_t* llr, t_nrLDPC_procBuf* p_procBuf, uint16_t Z) { - const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0]; - const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1]; - const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2]; - const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3]; - const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4]; - const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5]; + const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0]; + const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1]; + const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2]; + const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3]; + const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4]; + const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5]; - const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->posBnInCnProcBuf[0]; - const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->posBnInCnProcBuf[1]; - const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->posBnInCnProcBuf[2]; - const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->posBnInCnProcBuf[3]; - const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->posBnInCnProcBuf[4]; - const uint8_t (*lut_posBnInCnProcBuf_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->posBnInCnProcBuf[5]; + const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->posBnInCnProcBuf[0]; + const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->posBnInCnProcBuf[1]; + const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->posBnInCnProcBuf[2]; + const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->posBnInCnProcBuf[3]; + const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->posBnInCnProcBuf[4]; + const uint8_t (*lut_posBnInCnProcBuf_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->posBnInCnProcBuf[5]; const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups; const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups; @@ -483,26 +483,26 @@ static inline void nrLDPC_cn2bnProcBuf_BG2(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups; const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups; - const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0]; - const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1]; - const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2]; - const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3]; - const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4]; - const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5]; + const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0]; + const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1]; + const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2]; + const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3]; + const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4]; + const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5]; - const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; - const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; - const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; - const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; - const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; - const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; + const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; + const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; + const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; + const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; + const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; + const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; - const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0]; - const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; - const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; - const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; - const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; - const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; + const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0]; + const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; + const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; + const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; + const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; + const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; int8_t* cnProcBufRes = p_procBuf->cnProcBufRes; int8_t* bnProcBuf = p_procBuf->bnProcBuf; @@ -626,34 +626,34 @@ static inline void nrLDPC_cn2bnProcBuf_BG1(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups; const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups; - const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0]; - const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1]; - const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2]; - const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3]; - const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4]; - const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5]; - const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6]; - const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7]; - const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8]; + const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0]; + const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1]; + const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2]; + const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3]; + const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4]; + const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5]; + const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6]; + const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7]; + const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8]; - const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; - const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; - const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; - const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; - const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; - const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; - const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6]; - const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7]; - const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8]; + const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; + const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; + const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; + const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; + const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; + const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; + const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6]; + const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7]; + const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8]; - const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; - const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; - const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; - const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; - const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; - const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6]; - const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7]; - const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8]; + const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; + const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; + const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; + const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; + const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; + const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6]; + const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7]; + const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8]; int8_t* cnProcBufRes = p_procBuf->cnProcBufRes; int8_t* bnProcBuf = p_procBuf->bnProcBuf; @@ -824,26 +824,26 @@ static inline void nrLDPC_bn2cnProcBuf_BG2(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups; const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups; - const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0]; - const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1]; - const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2]; - const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3]; - const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4]; - const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5]; + const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0]; + const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1]; + const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2]; + const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3]; + const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4]; + const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5]; - const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; - const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; - const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; - const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; - const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; - const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; + const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; + const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; + const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; + const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; + const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; + const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; - const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0]; - const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; - const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; - const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; - const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; - const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; + const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0]; + const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; + const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; + const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; + const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; + const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; int8_t* cnProcBuf = p_procBuf->cnProcBuf; int8_t* bnProcBufRes = p_procBuf->bnProcBufRes; @@ -966,34 +966,34 @@ static inline void nrLDPC_bn2cnProcBuf_BG1(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups; const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups; - const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0]; - const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1]; - const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2]; - const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3]; - const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4]; - const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5]; - const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6]; - const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7]; - const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8]; + const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0]; + const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1]; + const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2]; + const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3]; + const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4]; + const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5]; + const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6]; + const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7]; + const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8]; - const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; - const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; - const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; - const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; - const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; - const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; - const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6]; - const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7]; - const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8]; + const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0]; + const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1]; + const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2]; + const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3]; + const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4]; + const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5]; + const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6]; + const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7]; + const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8]; - const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; - const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; - const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; - const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; - const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; - const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6]; - const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7]; - const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8]; + const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1]; + const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2]; + const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3]; + const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4]; + const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5]; + const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6]; + const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7]; + const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8]; int8_t* cnProcBuf = p_procBuf->cnProcBuf; int8_t* bnProcBufRes = p_procBuf->bnProcBufRes; diff --git a/openair1/PHY/INIT/lte_init_ru.c b/openair1/PHY/INIT/lte_init_ru.c index 207bf249f5..dddd6b1bd5 100644 --- a/openair1/PHY/INIT/lte_init_ru.c +++ b/openair1/PHY/INIT/lte_init_ru.c @@ -38,7 +38,7 @@ int phy_init_RU(RU_t *ru) { LTE_DL_FRAME_PARMS *fp = ru->frame_parms; RU_CALIBRATION *calibration = &ru->calibration; int i,j,p,re; - init_dfts(); + //load_dftslib(); LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d\n",ru_if_types[ru->if_south],ru->nb_tx); if (ru->is_slave == 1) { @@ -76,7 +76,7 @@ int phy_init_RU(RU_t *ru) { } if (ru->function != NGFI_RRU_IF5) { // we need to do RX/TX RU processing - init_dfts(); + load_dftslib(); init_7_5KHz(); LOG_I(PHY,"nb_tx %d\n",ru->nb_tx); ru->common.rxdata_7_5kHz = (int32_t **)malloc16(ru->nb_rx*sizeof(int32_t *) ); diff --git a/openair1/PHY/INIT/lte_init_ue.c b/openair1/PHY/INIT/lte_init_ue.c index 1a6f0081e1..082db61da9 100644 --- a/openair1/PHY/INIT/lte_init_ue.c +++ b/openair1/PHY/INIT/lte_init_ue.c @@ -625,7 +625,7 @@ int init_lte_ue_signal(PHY_VARS_UE *ue, int th_id; LOG_D(PHY,"Initializing UE vars (abstraction %"PRIu8") for eNB TXant %"PRIu8", UE RXant %"PRIu8"\n",abstraction_flag,fp->nb_antennas_tx,fp->nb_antennas_rx); crcTableInit(); - init_dfts(); + load_dftslib(); init_frame_parms(&ue->frame_parms,1); lte_sync_time_init(&ue->frame_parms); init_lte_top(&ue->frame_parms); diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 1c0d5a6aca..813d419429 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -96,7 +96,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, while(gNB->configured == 0) usleep(10000); - init_dfts(); + load_dftslib(); /* LOG_I(PHY,"[gNB %"PRIu8"] Initializing DL_FRAME_PARMS : N_RB_DL %"PRIu8", PHICH Resource %d, PHICH Duration %d nb_antennas_tx:%u nb_antennas_rx:%u PRACH[rootSequenceIndex:%u prach_Config_enabled:%u configIndex:%u highSpeed:%u zeroCorrelationZoneConfig:%u freqOffset:%u]\n", gNB->Mod_id, @@ -112,7 +112,8 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, );*/ LOG_D(PHY,"[MSC_NEW][FRAME 00000][PHY_gNB][MOD %02"PRIu8"][]\n", gNB->Mod_id); crcTableInit(); - init_dfts(); + init_scrambling_luts(); + init_pucch2_luts(); load_nrLDPClib(); // PBCH DMRS gold sequences generation nr_init_pbch_dmrs(gNB); diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index 4ed5be2119..5a60d15e2b 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -657,8 +657,8 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, abstraction_flag = 0; fp->nb_antennas_tx = 1; fp->nb_antennas_rx=1; - dmrs_UplinkConfig_t *dmrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig; - ptrs_UplinkConfig_t *ptrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig; + // dmrs_UplinkConfig_t *dmrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig; + // ptrs_UplinkConfig_t *ptrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig; printf("Initializing UE vars (abstraction %"PRIu8") for eNB TXant %"PRIu8", UE RXant %"PRIu8"\n",abstraction_flag,fp->nb_antennas_tx,fp->nb_antennas_rx); //LOG_D(PHY,"[MSC_NEW][FRAME 00000][PHY_UE][MOD %02u][]\n", ue->Mod_id+NB_eNB_INST); phy_init_nr_top(ue); @@ -710,9 +710,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, } //------------- config DMRS parameters--------------// - dmrs_Uplink_Config->pusch_dmrs_type = pusch_dmrs_type1; - dmrs_Uplink_Config->pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0; - dmrs_Uplink_Config->pusch_maxLength = pusch_len1; + // dmrs_Uplink_Config->pusch_dmrs_type = pusch_dmrs_type1; + // dmrs_Uplink_Config->pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0; + // dmrs_Uplink_Config->pusch_maxLength = pusch_len1; //-------------------------------------------------// ue->dmrs_DownlinkConfig.pdsch_dmrs_type = pdsch_dmrs_type1; ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition = pdsch_dmrs_pos0; @@ -745,15 +745,13 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, /////////////////////////PUSCH PTRS init///////////////////////// /////////// - ue->ptrs_configured = 0; // flag to be toggled by RCC - //------------- config PTRS parameters--------------// - ptrs_Uplink_Config->timeDensity.ptrs_mcs1 = 0; // setting MCS values to 0 indicate abscence of time_density field in the configuration - ptrs_Uplink_Config->timeDensity.ptrs_mcs2 = 0; - ptrs_Uplink_Config->timeDensity.ptrs_mcs3 = 0; - ptrs_Uplink_Config->frequencyDensity.n_rb0 = 0; // setting N_RB values to 0 indicate abscence of frequency_density field in the configuration - ptrs_Uplink_Config->frequencyDensity.n_rb1 = 0; - ptrs_Uplink_Config->resourceElementOffset = 0; + // ptrs_Uplink_Config->timeDensity.ptrs_mcs1 = 2; // setting MCS values to 0 indicate abscence of time_density field in the configuration + // ptrs_Uplink_Config->timeDensity.ptrs_mcs2 = 4; + // ptrs_Uplink_Config->timeDensity.ptrs_mcs3 = 10; + // ptrs_Uplink_Config->frequencyDensity.n_rb0 = 25; // setting N_RB values to 0 indicate abscence of frequency_density field in the configuration + // ptrs_Uplink_Config->frequencyDensity.n_rb1 = 75; + // ptrs_Uplink_Config->resourceElementOffset = 0; //-------------------------------------------------// /////////// @@ -988,7 +986,7 @@ void init_nr_ue_transport(PHY_VARS_NR_UE *ue, void phy_init_nr_top(PHY_VARS_NR_UE *ue) { NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms; crcTableInit(); - init_dfts(); + load_dftslib(); init_context_synchro_nr(frame_parms); generate_ul_reference_signal_sequences(SHRT_MAX); // Polar encoder init for PBCH diff --git a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c index 04fe19ecbc..aaa138fcd9 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c @@ -56,22 +56,22 @@ int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms, // do ifft of channel estimate switch(frame_parms->N_RB_DL) { case 6: - dft128((int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], + dft(DFT_128,(int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa], 1); break; case 25: - dft512((int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], + dft(DFT_512,(int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa], 1); break; case 50: - dft1024((int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], + dft(DFT_1024,(int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa], 1); break; case 100: - dft2048((int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], + dft(DFT_2048,(int16_t*) <e_eNB_srs->srs_ch_estimates[aa][0], (int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa], 1); break; diff --git a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_ue.c b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_ue.c index 7414c3a69d..23f261149a 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_ue.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_ue.c @@ -23,7 +23,6 @@ #include "PHY/defs_UE.h" #include "PHY/LTE_ESTIMATION/lte_estimation.h" #include "PHY/impl_defs_top.h" -#include "openair2/LAYER2/MAC/mac_proto.h" #include "common/utils/LOG/vcd_signal_dumper.h" diff --git a/openair1/PHY/LTE_ESTIMATION/lte_dl_bf_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_dl_bf_channel_estimation.c index 43c0350efb..2331e253d5 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_dl_bf_channel_estimation.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_dl_bf_channel_estimation.c @@ -43,7 +43,7 @@ int lte_dl_bf_channel_estimation(PHY_VARS_UE *phy_vars_ue, uint8_t pilot0,pilot1,pilot2,pilot3; short ch[2], *pil, *rxF, *dl_bf_ch, *dl_bf_ch_prev; - short *fl, *fm, *fr, *fl_dc, *fm_dc, *fr_dc, *f1, *f2l, *f2r; + short *fl=NULL, *fm=NULL, *fr=NULL, *fl_dc=NULL, *fm_dc=NULL, *fr_dc=NULL, *f1, *f2l=NULL, *f2r=NULL; unsigned int *rballoc; int **rxdataF; @@ -58,10 +58,10 @@ int lte_dl_bf_channel_estimation(PHY_VARS_UE *phy_vars_ue, dlsch0_harq = dlsch_ue[0]->harq_processes[harq_pid]; if (((frame_parms->Ncp == NORMAL) && (symbol>=7)) || - ((frame_parms->Ncp == EXTENDED) && (symbol>=6))) - rballoc = dlsch0_harq->rb_alloc_odd; + ((frame_parms->Ncp == EXTENDED) && (symbol>=6))) + rballoc = dlsch0_harq->rb_alloc_odd; else - rballoc = dlsch0_harq->rb_alloc_even; + rballoc = dlsch0_harq->rb_alloc_even; rxdataF = phy_vars_ue->common_vars.common_vars_rx_data_per_thread[phy_vars_ue->current_thread_id[Ns>>1]].rxdataF; @@ -69,56 +69,56 @@ int lte_dl_bf_channel_estimation(PHY_VARS_UE *phy_vars_ue, beamforming_mode = phy_vars_ue->transmission_mode[eNB_id]>6 ? phy_vars_ue->transmission_mode[eNB_id] : 0; if (phy_vars_ue->high_speed_flag == 0) // use second channel estimate position for temporary storage - ch_offset = frame_parms->ofdm_symbol_size; + ch_offset = frame_parms->ofdm_symbol_size; else - ch_offset = frame_parms->ofdm_symbol_size*symbol; + ch_offset = frame_parms->ofdm_symbol_size*symbol; + - uespec_nushift = frame_parms->Nid_cell%3; subframe = Ns>>1; - - //generate ue specific pilots - lprime = symbol/3-1; - lte_dl_ue_spec_rx(phy_vars_ue,uespec_pilot,Ns,5,lprime,0,dlsch0_harq->nb_rb); - //LOG_M("uespec_pilot_rx.m","uespec_pilot",uespec_pilot,300,1,1); - if (frame_parms->Ncp==0){ - if (symbol==3 || symbol==6 || symbol==9 || symbol==12) - uespec_pilots = 1; - } else{ - if (symbol==4 || symbol==7 || symbol==10) - uespec_pilots = 1; - } - - if ((frame_parms->Ncp==0 && (symbol==6 ||symbol ==12)) || (frame_parms->Ncp==1 && symbol==7)) - uespec_poffset = 2; + //generate ue specific pilots + lprime = symbol/3-1; + lte_dl_ue_spec_rx(phy_vars_ue,uespec_pilot,Ns,5,lprime,0,dlsch0_harq->nb_rb); + //LOG_M("uespec_pilot_rx.m","uespec_pilot",uespec_pilot,300,1,1); - if (phy_vars_ue->frame_parms.Ncp == 0) { // normal prefix - pilot0 = 3; - pilot1 = 6; - pilot2 = 9; - pilot3 = 12; - } else { // extended prefix - pilot0 = 4; - pilot1 = 7; - pilot2 = 10; - } + if (frame_parms->Ncp==0){ + if (symbol==3 || symbol==6 || symbol==9 || symbol==12) + uespec_pilots = 1; + } else{ + if (symbol==4 || symbol==7 || symbol==10) + uespec_pilots = 1; + } - //define the filter - pil_offset = (uespec_nushift+uespec_poffset)%3; - // printf("symbol=%d,pil_offset=%d\n",symbol,pil_offset); - switch (pil_offset) { - case 0: - fl = filt16_l0; - fm = filt16_m0; - fr = filt16_r0; - fl_dc = filt16_l0; - fm_dc = filt16_m0; - fr_dc = filt16_r0; - f1 = filt16_1; - f2l = filt16_2l0; - f2r = filt16_2r0; + if ((frame_parms->Ncp==0 && (symbol==6 ||symbol ==12)) || (frame_parms->Ncp==1 && symbol==7)) + uespec_poffset = 2; + + if (phy_vars_ue->frame_parms.Ncp == 0) { // normal prefix + pilot0 = 3; + pilot1 = 6; + pilot2 = 9; + pilot3 = 12; + } else { // extended prefix + pilot0 = 4; + pilot1 = 7; + pilot2 = 10; + } + + //define the filter + pil_offset = (uespec_nushift+uespec_poffset)%3; + // printf("symbol=%d,pil_offset=%d\n",symbol,pil_offset); + switch (pil_offset) { + case 0: + fl = filt16_l0; + fm = filt16_m0; + fr = filt16_r0; + fl_dc = filt16_l0; + fm_dc = filt16_m0; + fr_dc = filt16_r0; + f1 = filt16_1; + f2l = filt16_2l0; + f2r = filt16_2r0; break; case 1: diff --git a/openair1/PHY/LTE_ESTIMATION/lte_dl_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_dl_channel_estimation.c index e50af7cdd8..d221348b44 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_dl_channel_estimation.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_dl_channel_estimation.c @@ -657,35 +657,35 @@ int lte_dl_channel_estimation(PHY_VARS_UE *ue, } } - void (*idft)(int16_t *,int16_t *, int); + idft_size_idx_t idftsizeidx; switch (ue->frame_parms.ofdm_symbol_size) { case 128: - idft = idft128; - break; - - case 256: - idft = idft256; - break; - - case 512: - idft = idft512; - break; - - case 1024: - idft = idft1024; - break; - - case 1536: - idft = idft1536; - break; - - case 2048: - idft = idft2048; - break; - - default: - idft = idft512; + idftsizeidx = IDFT_128; + break; + + case 256: + idftsizeidx = IDFT_256; + break; + + case 512: + idftsizeidx = IDFT_512; + break; + + case 1024: + idftsizeidx = IDFT_1024; + break; + + case 1536: + idftsizeidx = IDFT_1536; + break; + + case 2048: + idftsizeidx = IDFT_2048; + break; + + default: + idftsizeidx = IDFT_512; break; } @@ -695,7 +695,7 @@ int lte_dl_channel_estimation(PHY_VARS_UE *ue, for (p=0; pframe_parms.nb_antenna_ports_eNB; p++) { if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx]) { //LOG_I(PHY,"Channel Impulse Computation Slot %d ThreadId %d Symbol %d \n", Ns, ue->current_thread_id[Ns>>1], l); - idft((int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx][8], + idft(idftsizeidx,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx][8], (int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates_time[eNB_offset][(p<<1)+aarx],1); } } diff --git a/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c index 6f917ee49c..333a6f0866 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c @@ -724,31 +724,31 @@ int lte_dl_mbsfn_channel_estimation(PHY_VARS_UE *ue, if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa]) { switch (ue->frame_parms.N_RB_DL) { case 6: - idft128((int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], + idft(IDFT_128,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], (int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa], 1); break; case 25: - idft512((int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], + idft(IDFT_512,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], (int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa], 1); break; case 50: - idft1024((int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], + idft(IDFT_1024,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], (int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa], 1); break; case 75: - idft1536((int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], + idft(IDFT_1536,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], (int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa], 1); break; case 100: - idft2048((int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], + idft(IDFT_2048,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8], (int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa], 1); break; diff --git a/openair1/PHY/LTE_ESTIMATION/lte_sync_time.c b/openair1/PHY/LTE_ESTIMATION/lte_sync_time.c index 0c98bdc5a5..0d765a18b3 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_sync_time.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_sync_time.c @@ -141,28 +141,28 @@ int lte_sync_time_init(LTE_DL_FRAME_PARMS *frame_parms ) // LTE_UE_COMMON *com switch (frame_parms->N_RB_DL) { case 6: - idft128((short*)syncF_tmp, /// complex input + idft(IDFT_128,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 25: - idft512((short*)syncF_tmp, /// complex input + idft(IDFT_512,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 50: - idft1024((short*)syncF_tmp, /// complex input + idft(IDFT_1024,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 75: - idft1536((short*)syncF_tmp, /// complex input + idft(IDFT_1536,(short*)syncF_tmp, /// complex input (short*)sync_tmp, 1); /// complex output break; case 100: - idft2048((short*)syncF_tmp, /// complex input + idft(IDFT_2048,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; @@ -189,28 +189,28 @@ int lte_sync_time_init(LTE_DL_FRAME_PARMS *frame_parms ) // LTE_UE_COMMON *com switch (frame_parms->N_RB_DL) { case 6: - idft128((short*)syncF_tmp, /// complex input + idft(IDFT_128,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 25: - idft512((short*)syncF_tmp, /// complex input + idft(IDFT_512,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 50: - idft1024((short*)syncF_tmp, /// complex input + idft(IDFT_1024,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 75: - idft1536((short*)syncF_tmp, /// complex input + idft(IDFT_1536,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 100: - idft2048((short*)syncF_tmp, /// complex input + idft(IDFT_2048,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; @@ -237,28 +237,28 @@ int lte_sync_time_init(LTE_DL_FRAME_PARMS *frame_parms ) // LTE_UE_COMMON *com switch (frame_parms->N_RB_DL) { case 6: - idft128((short*)syncF_tmp, /// complex input + idft(IDFT_128,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 25: - idft512((short*)syncF_tmp, /// complex input + idft(IDFT_512,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 50: - idft1024((short*)syncF_tmp, /// complex input + idft(IDFT_1024,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 75: - idft1536((short*)syncF_tmp, /// complex input + idft(IDFT_1536,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; case 100: - idft2048((short*)syncF_tmp, /// complex input + idft(IDFT_2048,(short*)syncF_tmp, /// complex input (short*)sync_tmp, /// complex output 1); break; @@ -492,28 +492,28 @@ int ru_sync_time_init(RU_t *ru) // LTE_UE_COMMON *common_vars switch (ru->frame_parms->N_RB_DL) { case 6: - idft128((int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), + idft(IDFT_128,(int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), ru->dmrssync, /// complex output 1); break; case 25: - idft512((int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), + idft(IDFT_512,(int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), ru->dmrssync, /// complex output 1); break; case 50: - idft1024((int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), + idft(IDFT_1024,(int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), ru->dmrssync, /// complex output 1); break; case 75: - idft1536((int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), + idft(IDFT_1536,(int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), ru->dmrssync, 1); /// complex output break; case 100: - idft2048((int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), + idft(IDFT_2048,(int16_t*)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]), ru->dmrssync, /// complex output 1); break; diff --git a/openair1/PHY/LTE_ESTIMATION/lte_sync_timefreq.c b/openair1/PHY/LTE_ESTIMATION/lte_sync_timefreq.c index de48a855df..524b200e1a 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_sync_timefreq.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_sync_timefreq.c @@ -80,7 +80,7 @@ void lte_sync_timefreq(PHY_VARS_UE *ue,int band,unsigned int DL_freq) while (1) { //compute frequency-domain representation of 6144-sample chunk - dft6144((int16_t *)rxp, + dft(DFT_6144,(int16_t *)rxp, sp,1); @@ -267,7 +267,7 @@ void lte_sync_timefreq(PHY_VARS_UE *ue,int band,unsigned int DL_freq) } // ifft, accumulate energy over two half-frames - idft256((int16_t*)autocorr0,(int16_t*)tmp_t,1); + idft(IDFT_256,(int16_t*)autocorr0,(int16_t*)tmp_t,1); /* if (i==12288) { sprintf(fname,"corr256F_%d.m",abs(f)); @@ -285,12 +285,12 @@ void lte_sync_timefreq(PHY_VARS_UE *ue,int band,unsigned int DL_freq) for (re=0; re<(256/4); re++) autocorr0_t[re] = _mm_add_epi32(autocorr0_t[re],_mm_madd_epi16(tmp_t[re],tmp_t[re])); - idft256((int16_t*)autocorr1,(int16_t*)tmp_t,1); + idft(IDFT_256,(int16_t*)autocorr1,(int16_t*)tmp_t,1); for (re=0; re<(256/4); re++) autocorr1_t[re] = _mm_add_epi32(autocorr1_t[re],_mm_madd_epi16(tmp_t[re],tmp_t[re])); - idft256((int16_t*)autocorr2,(int16_t*)tmp_t,1); + idft(IDFT_256,(int16_t*)autocorr2,(int16_t*)tmp_t,1); for (re=0; re<(256/4); re++) autocorr2_t[re] = _mm_add_epi32(autocorr2_t[re],_mm_madd_epi16(tmp_t[re],tmp_t[re])); diff --git a/openair1/PHY/LTE_ESTIMATION/lte_ue_measurements.c b/openair1/PHY/LTE_ESTIMATION/lte_ue_measurements.c index 2e4f3e6036..880c056578 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_ue_measurements.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_ue_measurements.c @@ -1029,7 +1029,7 @@ void lte_ue_measurements(PHY_VARS_UE *ue, int N_RB_DL = frame_parms->N_RB_DL; - int rank_tm3_tm4; + int rank_tm3_tm4=-1; ue->measurements.nb_antennas_rx = frame_parms->nb_antennas_rx; diff --git a/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c index cb001f9dc4..7caaf07406 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c @@ -50,8 +50,11 @@ int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB, int32_t **ul_ch_estimates_time = (eNB!=NULL) ? pusch_vars->drs_ch_estimates_time : calibration->drs_ch_estimates_time; AssertFatal(ul_ch_estimates_time != NULL, "ul_ch_estimates_time is null\n"); int32_t **rxdataF_ext = (eNB!=NULL) ? pusch_vars->rxdataF_ext : calibration->rxdataF_ext; - int subframe = (eNB!=NULL) ? proc->subframe_rx : ru->proc.tti_rx; - uint8_t harq_pid; + + int subframe = proc->subframe_rx; + + uint8_t harq_pid; + int16_t delta_phase = 0; int16_t *ru1 = ru_90; int16_t *ru2 = ru_90; @@ -246,25 +249,25 @@ int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB, switch(frame_parms->N_RB_DL) { case 6: - idft128((int16_t *) temp_in_ifft_0, + idft(IDFT_128,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; case 25: - idft512((int16_t *) temp_in_ifft_0, + idft(IDFT_512,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; case 50: - idft1024((int16_t *) temp_in_ifft_0, + idft(IDFT_1024,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; case 100: - idft2048((int16_t *) temp_in_ifft_0, + idft(IDFT_2048,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; @@ -575,25 +578,25 @@ int32_t lte_ul_channel_estimation_RRU(LTE_DL_FRAME_PARMS *frame_parms, switch(frame_parms->N_RB_DL) { case 6: - idft128((int16_t *) temp_in_ifft_0, + idft(IDFT_128,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; case 25: - idft512((int16_t *) temp_in_ifft_0, + idft(IDFT_512,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; case 50: - idft1024((int16_t *) temp_in_ifft_0, + idft(IDFT_1024,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; case 100: - idft2048((int16_t *) temp_in_ifft_0, + idft(IDFT_2048,(int16_t *) temp_in_ifft_0, (int16_t *) ul_ch_estimates_time[aa], 1); break; diff --git a/openair1/PHY/LTE_REFSIG/mod_table.h b/openair1/PHY/LTE_REFSIG/mod_table.h index 7bdc1f518f..29ae9f4495 100644 --- a/openair1/PHY/LTE_REFSIG/mod_table.h +++ b/openair1/PHY/LTE_REFSIG/mod_table.h @@ -19,9 +19,14 @@ * contact@openairinterface.org */ +#ifndef __PHY_LTE_REFSIG_MOD_TABLE__H__ +#define __PHY_LTE_REFSIG_MOD_TABLE__H__ + #define MOD_TABLE_SIZE_SHORT 304 #define MOD_TABLE_QPSK_OFFSET 1 #define MOD_TABLE_16QAM_OFFSET 5 #define MOD_TABLE_64QAM_OFFSET 21 #define MOD_TABLE_PSS_OFFSET 85 short mod_table[MOD_TABLE_SIZE_SHORT] = {0,0,768,768,768,-768,-768,768,-768,-768,343,343,343,1030,1030,343,1030,1030,343,-343,343,-1030,1030,-343,1030,-1030,-343,343,-343,1030,-1030,343,-1030,1030,-343,-343,-343,-1030,-1030,-343,-1030,-1030,503,503,503,168,168,503,168,168,503,838,503,1173,168,838,168,1173,838,503,838,168,1173,503,1173,168,838,838,838,1173,1173,838,1173,1173,503,-503,503,-168,168,-503,168,-168,503,-838,503,-1173,168,-838,168,-1173,838,-503,838,-168,1173,-503,1173,-168,838,-838,838,-1173,1173,-838,1173,-1173,-503,503,-503,168,-168,503,-168,168,-503,838,-503,1173,-168,838,-168,1173,-838,503,-838,168,-1173,503,-1173,168,-838,838,-838,1173,-1173,838,-1173,1173,-503,-503,-503,-168,-168,-503,-168,-168,-503,-838,-503,-1173,-168,-838,-168,-1173,-838,-503,-838,-168,-1173,-503,-1173,-168,-838,-838,-838,-1173,-1173,-838,-1173,-1173,1086,0,1081,-108,1065,-215,1038,-320,1001,-422,954,-519,897,-612,832,-698,758,-777,677,-849,589,-912,495,-966,397,-1011,294,-1046,189,-1070,81,-1083,-27,-1086,-135,-1078,-242,-1059,-346,-1030,-447,-990,-543,-941,-634,-882,-719,-814,-796,-739,-866,-656,-927,-566,-979,-471,-1021,-371,-1053,-268,-1074,-162,-1085,-54,-1085,54,-1074,162,-1053,268,-1021,371,-979,471,-927,566,-866,656,-796,739,-719,814,-634,882,-543,941,-447,990,-346,1030,-242,1059,-135,1078,-27,1086,81,1083,189,1070,294,1045,397,1011,495,966,589,912,677,849,758,777,832,698,897,612,954,519,1001,422,1038,320,1065,215,1081,108,16384,0,8192,0,4096,0,2048,0}; + +#endif diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c index 6595158f1a..15eb5206a1 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c @@ -20,15 +20,15 @@ */ /*! \file PHY/LTE_TRANSPORT/dlsch_coding.c -* \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03 -* \author R. Knopp -* \date 2011 -* \version 0.1 -* \company Eurecom -* \email: knopp@eurecom.fr -* \note -* \warning -*/ + * \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03 + * \author R. Knopp + * \date 2011 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr + * \note + * \warning + */ #include "PHY/defs_eNB.h" #include "PHY/phy_extern.h" @@ -42,22 +42,23 @@ #include "common/utils/LOG/log.h" #include "targets/RT/USER/lte-softmodem.h" #include -#include "executables/thread-common.h" +#include "targets/RT/USER/rt_wrapper.h" +#include //#define DEBUG_DLSCH_CODING //#define DEBUG_DLSCH_FREE 1 /* -#define is_not_pilot(pilots,first_pilot,re) (pilots==0) || \ + #define is_not_pilot(pilots,first_pilot,re) (pilots==0) || \ ((pilots==1)&&(first_pilot==1)&&(((re>2)&&(re<6))||((re>8)&&(re<12)))) || \ ((pilots==1)&&(first_pilot==0)&&(((re<3))||((re>5)&&(re<9)))) \ */ #define is_not_pilot(pilots,first_pilot,re) (1) /*extern void thread_top_init(char *thread_name, - int affinity, - uint64_t runtime, - uint64_t deadline, - uint64_t period);*/ + int affinity, + uint64_t runtime, + uint64_t deadline, + uint64_t period);*/ extern volatile int oai_exit; @@ -83,11 +84,6 @@ void free_eNB_dlsch(LTE_eNB_DLSCH_t *dlsch) { free16(dlsch->harq_processes[i]->c[r],((r==0)?8:0) + 3+768); dlsch->harq_processes[i]->c[r] = NULL; } - - if (dlsch->harq_processes[i]->d[r]) { - free16(dlsch->harq_processes[i]->d[r],(96+12+3+(3*6144))); - dlsch->harq_processes[i]->d[r] = NULL; - } } free16(dlsch->harq_processes[i],sizeof(LTE_DL_eNB_HARQ_t)); @@ -108,26 +104,26 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo, LTE_DL_FRAME_PARMS *frame_parms) { LTE_eNB_DLSCH_t *dlsch; - unsigned char exit_flag = 0,i,j,r,aa,layer; + unsigned char exit_flag = 0,i,r,aa,layer; int re; unsigned char bw_scaling =1; switch (N_RB_DL) { - case 6: - bw_scaling =16; - break; + case 6: + bw_scaling =16; + break; - case 25: - bw_scaling =4; - break; + case 25: + bw_scaling =4; + break; - case 50: - bw_scaling =2; - break; + case 50: + bw_scaling =2; + break; - default: - bw_scaling =1; - break; + default: + bw_scaling =1; + break; } dlsch = (LTE_eNB_DLSCH_t *)malloc16(sizeof(LTE_eNB_DLSCH_t)); @@ -153,11 +149,11 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo, // NOTE: THIS HAS TO BE REVISED FOR RU, commenting to remove memory leak !!!!! /* - dlsch->calib_dl_ch_estimates = (int32_t**)malloc16(frame_parms->nb_antennas_tx*sizeof(int32_t*)); - for (aa=0; aanb_antennas_tx; aa++) { - dlsch->calib_dl_ch_estimates[aa] = (int32_t *)malloc16(OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES*sizeof(int32_t)); + dlsch->calib_dl_ch_estimates = (int32_t**)malloc16(frame_parms->nb_antennas_tx*sizeof(int32_t*)); + for (aa=0; aanb_antennas_tx; aa++) { + dlsch->calib_dl_ch_estimates[aa] = (int32_t *)malloc16(OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES*sizeof(int32_t)); - }*/ + }*/ for (i=0; i<20; i++) dlsch->harq_ids[i/10][i%10] = Mdlharq; @@ -183,7 +179,6 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo, for (r=0; rharq_processes[i]->c[r] = (uint8_t *)malloc16(((r==0)?8:0) + 3+ 768); - dlsch->harq_processes[i]->d[r] = (uint8_t *)malloc16((96+12+3+(3*6144))); if (dlsch->harq_processes[i]->c[r]) { bzero(dlsch->harq_processes[i]->c[r],((r==0)?8:0) + 3+ 768); @@ -191,13 +186,6 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo, printf("Can't get c\n"); exit_flag=2; } - - if (dlsch->harq_processes[i]->d[r]) { - bzero(dlsch->harq_processes[i]->d[r],(96+12+3+(3*6144))); - } else { - printf("Can't get d\n"); - exit_flag=2; - } } } } else { @@ -209,13 +197,6 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo, if (exit_flag==0) { for (i=0; iharq_processes[i]->round=0; - - for (j=0; j<96; j++) - for (r=0; rharq_processes[%d]->d[%d] %p\n",i,r,dlsch->harq_processes[i]->d[r]); - if (dlsch->harq_processes[i]->d[r]) - dlsch->harq_processes[i]->d[r][j] = LTE_NULL; - } } return(dlsch); @@ -231,7 +212,7 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo, void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch) { unsigned char Mdlharq; - unsigned char i,j,r; + unsigned char i; if (dlsch) { Mdlharq = dlsch->Mdlharq; @@ -255,307 +236,17 @@ void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch) { dlsch->harq_processes[i]->status = 0; dlsch->harq_processes[i]->round = 0; - for (j=0; j<96; j++) - for (r=0; rharq_processes[i]->d[r]) - dlsch->harq_processes[i]->d[r][j] = LTE_NULL; } } } } - -int dlsch_encoding_2threads0(te_params *tep) { - LTE_eNB_DLSCH_t *dlsch = tep->dlsch; - unsigned int G = tep->G; - unsigned char harq_pid = tep->harq_pid; - unsigned int total_worker = tep->total_worker; - unsigned int current_worker = tep->current_worker; - unsigned short nb_rb = dlsch->harq_processes[harq_pid]->nb_rb; - unsigned int Kr=0,Kr_bytes,r,r_offset=0; - // unsigned short m=dlsch->harq_processes[harq_pid]->mcs; - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING_W, VCD_FUNCTION_IN); - - if (dlsch->harq_processes[harq_pid]->round == 0) { // this is a new packet - for (r=(dlsch->harq_processes[harq_pid]->C/(total_worker+1))*current_worker; r<(dlsch->harq_processes[harq_pid]->C/(total_worker+1))*(current_worker+1); r++) { - if (rharq_processes[harq_pid]->Cminus) - Kr = dlsch->harq_processes[harq_pid]->Kminus; - else - Kr = dlsch->harq_processes[harq_pid]->Kplus; - - Kr_bytes = Kr>>3; - encoder(dlsch->harq_processes[harq_pid]->c[r], - Kr>>3, - &dlsch->harq_processes[harq_pid]->d[r][96], - (r==0) ? dlsch->harq_processes[harq_pid]->F : 0 - ); - dlsch->harq_processes[harq_pid]->RTC[r] = - sub_block_interleaving_turbo(4+(Kr_bytes*8), - &dlsch->harq_processes[harq_pid]->d[r][96], - dlsch->harq_processes[harq_pid]->w[r]); - } - } - - // Fill in the "e"-sequence from 36-212, V8.6 2009-03, p. 16-17 (for each "e") and concatenate the - // outputs for each code segment, see Section 5.1.5 p.20 - - for (r=0,r_offset=0; r<(dlsch->harq_processes[harq_pid]->C/(total_worker+1))*(current_worker+1); r++) { - if(r<(dlsch->harq_processes[harq_pid]->C/(total_worker+1))*(current_worker)) { - int Nl=dlsch->harq_processes[harq_pid]->Nl; - int Qm=dlsch->harq_processes[harq_pid]->Qm; - int C = dlsch->harq_processes[harq_pid]->C; - int Gp = G/Nl/Qm; - int GpmodC = Gp%C; - - if (r < (C-(GpmodC))) - r_offset += Nl*Qm * (Gp/C); - else - r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C)); - } else { - r_offset += lte_rate_matching_turbo(dlsch->harq_processes[harq_pid]->RTC[r], - G, //G - dlsch->harq_processes[harq_pid]->w[r], - dlsch->harq_processes[harq_pid]->e+r_offset, - dlsch->harq_processes[harq_pid]->C, // C - dlsch->Nsoft, // Nsoft, - dlsch->Mdlharq, - dlsch->Kmimo, - dlsch->harq_processes[harq_pid]->rvidx, - dlsch->harq_processes[harq_pid]->Qm, - dlsch->harq_processes[harq_pid]->Nl, - r, - nb_rb); - // m); // r - } - } - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING_W, VCD_FUNCTION_OUT); - return(0); -} - - void *te_thread(void *param) { - te_params *tep = (te_params *)param; - - //wait_sync("te_thread"); - - while (!oai_exit) { - if (wait_on_condition(&tep->mutex_te,&tep->cond_te,&tep->instance_cnt_te,"te thread")<0) break; - - if(oai_exit) break; - - dlsch_encoding_2threads0(tep); - - if (release_thread(&tep->mutex_te,&tep->instance_cnt_te,"te thread")<0) break; - - if (pthread_cond_signal(&tep->cond_te) != 0) { - printf("[eNB] ERROR pthread_cond_signal for te thread exit\n"); - exit_fun( "ERROR pthread_cond_signal" ); - return(NULL); - } - - /*if(opp_enabled == 1 && te_wakeup_stats0->p_time>50*3000){ - print_meas_now(te_wakeup_stats0,"coding_wakeup",stderr); - printf("te_thread0 delay for waking up in frame_rx: %d subframe_rx: %d \n",proc->frame_rx,proc->subframe_rx); - }*/ - } - return(NULL); } - -int dlsch_encoding_2threads(PHY_VARS_eNB *eNB, - unsigned char *a, - uint8_t num_pdcch_symbols, - LTE_eNB_DLSCH_t *dlsch, - int frame, - uint8_t subframe, - time_stats_t *rm_stats, - time_stats_t *te_stats, - time_stats_t *te_wait_stats, - time_stats_t *te_main_stats, - time_stats_t *te_wakeup_stats0, - time_stats_t *te_wakeup_stats1, - time_stats_t *i_stats, - int worker_num) { - //start_meas(&eNB->dlsch_turbo_encoding_preperation_stats); - LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms; - L1_proc_t *proc = &eNB->proc; - unsigned int G; - unsigned int crc=1; - unsigned char harq_pid = dlsch->harq_ids[frame%2][subframe]; - if((harq_pid < 0) || (harq_pid >= dlsch->Mdlharq)) { - LOG_E(PHY,"dlsch_encoding_2threads illegal harq_pid %d %s:%d\n", harq_pid, __FILE__, __LINE__); - return(-1); - } - - unsigned short nb_rb = dlsch->harq_processes[harq_pid]->nb_rb; - unsigned int A; - unsigned char mod_order; - unsigned int Kr=0,Kr_bytes,r,r_offset=0; - // unsigned short m=dlsch->harq_processes[harq_pid]->mcs; - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); - A = dlsch->harq_processes[harq_pid]->TBS; //6228 - mod_order = dlsch->harq_processes[harq_pid]->Qm; - G = get_G(frame_parms,nb_rb,dlsch->harq_processes[harq_pid]->rb_alloc,mod_order,dlsch->harq_processes[harq_pid]->Nl,num_pdcch_symbols,frame,subframe, - dlsch->harq_processes[harq_pid]->mimo_mode==TM7?7:0); - - if (dlsch->harq_processes[harq_pid]->round == 0) { // this is a new packet - start_meas(&eNB->dlsch_turbo_encoding_preperation_stats); - // Add 24-bit crc (polynomial A) to payload - crc = crc24a(a, - A)>>8; - stop_meas(&eNB->dlsch_turbo_encoding_preperation_stats); - a[A>>3] = ((uint8_t *)&crc)[2]; - a[1+(A>>3)] = ((uint8_t *)&crc)[1]; - a[2+(A>>3)] = ((uint8_t *)&crc)[0]; - dlsch->harq_processes[harq_pid]->B = A+24; - memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+4); - //stop_meas(&eNB->dlsch_turbo_encoding_preperation_stats); - start_meas(&eNB->dlsch_turbo_encoding_segmentation_stats); - - if (lte_segmentation(dlsch->harq_processes[harq_pid]->b, - dlsch->harq_processes[harq_pid]->c, - dlsch->harq_processes[harq_pid]->B, - &dlsch->harq_processes[harq_pid]->C, - &dlsch->harq_processes[harq_pid]->Cplus, - &dlsch->harq_processes[harq_pid]->Cminus, - &dlsch->harq_processes[harq_pid]->Kplus, - &dlsch->harq_processes[harq_pid]->Kminus, - &dlsch->harq_processes[harq_pid]->F)<0) - return(-1); - - stop_meas(&eNB->dlsch_turbo_encoding_segmentation_stats); - start_meas(&eNB->dlsch_turbo_encoding_signal_stats); - - for(int i=0; itep[i].eNB = eNB; - proc->tep[i].dlsch = dlsch; - proc->tep[i].G = G; - proc->tep[i].harq_pid = harq_pid; - proc->tep[i].total_worker = worker_num; - proc->tep[i].current_worker = i; - pthread_mutex_lock( &proc->tep[i].mutex_te ); - - if (proc->tep[i].instance_cnt_te==0) { - printf("[eNB] TE thread busy\n"); - exit_fun("TE thread busy"); - pthread_mutex_unlock( &proc->tep[i].mutex_te ); - return(-1); - } - - ++proc->tep[i].instance_cnt_te; - - // wakeup worker to do segments - if (pthread_cond_signal(&proc->tep[i].cond_te) != 0) { - printf("[eNB] ERROR pthread_cond_signal for te thread %d exit\n",i); - exit_fun( "ERROR pthread_cond_signal" ); - return (-1); - } - - pthread_mutex_unlock( &proc->tep[i].mutex_te ); - } - - stop_meas(&eNB->dlsch_turbo_encoding_signal_stats); - start_meas(te_main_stats); - - for (r=(dlsch->harq_processes[harq_pid]->C/(worker_num+1))*worker_num; rharq_processes[harq_pid]->C; r++) { - if (rharq_processes[harq_pid]->Cminus) - Kr = dlsch->harq_processes[harq_pid]->Kminus; - else - Kr = dlsch->harq_processes[harq_pid]->Kplus; - - Kr_bytes = Kr>>3; - start_meas(te_stats); - encoder(dlsch->harq_processes[harq_pid]->c[r], - Kr>>3, - &dlsch->harq_processes[harq_pid]->d[r][96], - (r==0) ? dlsch->harq_processes[harq_pid]->F : 0 - ); - stop_meas(te_stats); - start_meas(i_stats); - dlsch->harq_processes[harq_pid]->RTC[r] = - sub_block_interleaving_turbo(4+(Kr_bytes*8), - &dlsch->harq_processes[harq_pid]->d[r][96], - dlsch->harq_processes[harq_pid]->w[r]); - stop_meas(i_stats); - } - } else { - for(int i=0; itep[i].eNB = eNB; - proc->tep[i].dlsch = dlsch; - proc->tep[i].G = G; - proc->tep[i].total_worker = worker_num; - proc->tep[i].current_worker = i; - - if (pthread_cond_signal(&proc->tep[i].cond_te) != 0) { - printf("[eNB] ERROR pthread_cond_signal for te thread exit\n"); - exit_fun( "ERROR pthread_cond_signal" ); - return (-1); - } - } - } - - // Fill in the "e"-sequence from 36-212, V8.6 2009-03, p. 16-17 (for each "e") and concatenate the - // outputs for each code segment, see Section 5.1.5 p.20 - for (r=0,r_offset=0; rharq_processes[harq_pid]->C; r++) { - // get information for E for the segments that are handled by the worker thread - if (r<(dlsch->harq_processes[harq_pid]->C/(worker_num+1))*worker_num) { - int Nl=dlsch->harq_processes[harq_pid]->Nl; - int Qm=dlsch->harq_processes[harq_pid]->Qm; - int C = dlsch->harq_processes[harq_pid]->C; - int Gp = G/Nl/Qm; - int GpmodC = Gp%C; - - if (r < (C-(GpmodC))) - r_offset += Nl*Qm * (Gp/C); - else - r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C)); - } else { - start_meas(rm_stats); - r_offset += lte_rate_matching_turbo(dlsch->harq_processes[harq_pid]->RTC[r], - G, //G - dlsch->harq_processes[harq_pid]->w[r], - dlsch->harq_processes[harq_pid]->e+r_offset, - dlsch->harq_processes[harq_pid]->C, // C - dlsch->Nsoft, // Nsoft, - dlsch->Mdlharq, - dlsch->Kmimo, - dlsch->harq_processes[harq_pid]->rvidx, - dlsch->harq_processes[harq_pid]->Qm, - dlsch->harq_processes[harq_pid]->Nl, - r, - nb_rb); - // m); // r - stop_meas(rm_stats); - } - } - - stop_meas(te_main_stats); - start_meas(te_wait_stats); - - if(worker_num == 1) { - wait_on_busy_condition(&proc->tep[0].mutex_te,&proc->tep[0].cond_te,&proc->tep[0].instance_cnt_te,"te thread 0"); - } else if(worker_num == 2) { - wait_on_busy_condition(&proc->tep[0].mutex_te,&proc->tep[0].cond_te,&proc->tep[0].instance_cnt_te,"te thread 0"); - wait_on_busy_condition(&proc->tep[1].mutex_te,&proc->tep[1].cond_te,&proc->tep[1].instance_cnt_te,"te thread 1"); - } else { - wait_on_busy_condition(&proc->tep[0].mutex_te,&proc->tep[0].cond_te,&proc->tep[0].instance_cnt_te,"te thread 0"); - wait_on_busy_condition(&proc->tep[1].mutex_te,&proc->tep[1].cond_te,&proc->tep[1].instance_cnt_te,"te thread 1"); - wait_on_busy_condition(&proc->tep[2].mutex_te,&proc->tep[2].cond_te,&proc->tep[2].instance_cnt_te,"te thread 2"); - } - - stop_meas(te_wait_stats); - /*if(opp_enabled == 1 && te_wait_stats->p_time>100*3000){ - print_meas_now(te_wait_stats,"coding_wait",stderr); - printf("coding delay in wait on codition in frame_rx: %d \n",proc->frame_rx); - }*/ - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); - return(0); -} - - int dlsch_encoding_all(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, unsigned char *a, uint8_t num_pdcch_symbols, LTE_eNB_DLSCH_t *dlsch, @@ -568,108 +259,72 @@ int dlsch_encoding_all(PHY_VARS_eNB *eNB, time_stats_t *te_wakeup_stats0, time_stats_t *te_wakeup_stats1, time_stats_t *i_stats) { - int encoding_return = 0; - unsigned int L,C,B; uint8_t harq_pid = dlsch->harq_ids[frame%2][subframe]; if(harq_pid >= dlsch->Mdlharq) { LOG_E(PHY,"dlsch_encoding_all illegal harq_pid %d\n", harq_pid); return(-1); } - B = dlsch->harq_processes[harq_pid]->B; + + LOG_D(PHY,"B %d, harq_pid %d\n", + dlsch->harq_processes[harq_pid]->B, + dlsch->harq_ids[frame%2][subframe]); - LOG_D(PHY,"B %d, harq_pid %d\n",B,dlsch->harq_ids[frame%2][subframe]); + return dlsch_encoding(eNB, + proc, + a, + num_pdcch_symbols, + dlsch, + frame, + subframe, + rm_stats, + te_stats, + i_stats); - if(B<=6144) { - L=0; - C=1; - } else { - L=24; - C = B/(6144-L); - - if((6144-L)*C < B) { - C = C+1; - } - } - - if(get_thread_worker_conf() == WORKER_ENABLE) { - if(C >= 8) { //one main three worker - encoding_return = - dlsch_encoding_2threads(eNB, - a, - num_pdcch_symbols, - dlsch, - frame, - subframe, - rm_stats, - te_stats, - te_wait_stats, - te_main_stats, - te_wakeup_stats0, - te_wakeup_stats1, - i_stats, - 3); - } else if(C >= 6) { //one main two worker - encoding_return = - dlsch_encoding_2threads(eNB, - a, - num_pdcch_symbols, - dlsch, - frame, - subframe, - rm_stats, - te_stats, - te_wait_stats, - te_main_stats, - te_wakeup_stats0, - te_wakeup_stats1, - i_stats, - 2); - } else if(C >= 4) { //one main one worker - encoding_return = - dlsch_encoding_2threads(eNB, - a, - num_pdcch_symbols, - dlsch, - frame, - subframe, - rm_stats, - te_stats, - te_wait_stats, - te_main_stats, - te_wakeup_stats0, - te_wakeup_stats1, - i_stats, - 1); - } else { - encoding_return = - dlsch_encoding(eNB, - a, - num_pdcch_symbols, - dlsch, - frame, - subframe, - rm_stats, - te_stats, - i_stats); - } - } else { - encoding_return = - dlsch_encoding(eNB, - a, - num_pdcch_symbols, - dlsch, - frame, - subframe, - rm_stats, - te_stats, - i_stats); - } - - return encoding_return; } +static void TPencode(void * arg) { + turboEncode_t * rdata=(turboEncode_t *) arg; + unsigned char harq_pid = rdata->harq_pid; + LTE_DL_eNB_HARQ_t *hadlsch=rdata->dlsch->harq_processes[harq_pid]; + + if ( rdata-> round == 0) { + uint8_t tmp[96+12+3+3*6144]; + memset(tmp,LTE_NULL, TURBO_SIMD_SOFTBITS); + start_meas(rdata->te_stats); + encoder(rdata->input, + rdata->Kr_bytes, + tmp+96,//&dlsch->harq_processes[harq_pid]->d[r][96], + rdata->filler); + stop_meas(rdata->te_stats); + start_meas(rdata->i_stats); + hadlsch->RTC[rdata->r] = + sub_block_interleaving_turbo(4+(rdata->Kr_bytes*8), + tmp+96, + hadlsch->w[rdata->r]); + stop_meas(rdata->i_stats); + } + + // Fill in the "e"-sequence from 36-212, V8.6 2009-03, p. 16-17 (for each "e") and concatenate the + // outputs for each code segment, see Section 5.1.5 p.20 + start_meas(rdata->rm_stats); + lte_rate_matching_turbo(hadlsch->RTC[rdata->r], + rdata->G, //G + hadlsch->w[rdata->r], + hadlsch->eDL+rdata->r_offset, + hadlsch->C, // C + rdata->dlsch->Nsoft, // Nsoft, + rdata->dlsch->Mdlharq, + rdata->dlsch->Kmimo, + hadlsch->rvidx, + hadlsch->Qm, + hadlsch->Nl, + rdata->r, + hadlsch->nb_rb); + stop_meas(rdata->rm_stats); +} int dlsch_encoding(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, unsigned char *a, uint8_t num_pdcch_symbols, LTE_eNB_DLSCH_t *dlsch, @@ -678,8 +333,6 @@ int dlsch_encoding(PHY_VARS_eNB *eNB, time_stats_t *rm_stats, time_stats_t *te_stats, time_stats_t *i_stats) { - unsigned int G; - unsigned int crc=1; LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms; unsigned char harq_pid = dlsch->harq_ids[frame%2][subframe]; if((harq_pid < 0) || (harq_pid >= dlsch->Mdlharq)) { @@ -687,135 +340,88 @@ int dlsch_encoding(PHY_VARS_eNB *eNB, return(-1); } - unsigned short nb_rb = dlsch->harq_processes[harq_pid]->nb_rb; - unsigned int A; - unsigned char mod_order; - unsigned int Kr=0,Kr_bytes,r,r_offset=0; - // unsigned short m=dlsch->harq_processes[harq_pid]->mcs; + LTE_DL_eNB_HARQ_t *hadlsch=dlsch->harq_processes[harq_pid]; uint8_t beamforming_mode=0; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); - A = dlsch->harq_processes[harq_pid]->TBS; //6228 - // printf("Encoder: A: %d\n",A); - mod_order = dlsch->harq_processes[harq_pid]->Qm; - if(dlsch->harq_processes[harq_pid]->mimo_mode == TM7) + if(hadlsch->mimo_mode == TM7) beamforming_mode = 7; - else if(dlsch->harq_processes[harq_pid]->mimo_mode == TM8) + else if(hadlsch->mimo_mode == TM8) beamforming_mode = 8; - else if(dlsch->harq_processes[harq_pid]->mimo_mode == TM9_10) + else if(hadlsch->mimo_mode == TM9_10) beamforming_mode = 9; - G = get_G(frame_parms,nb_rb,dlsch->harq_processes[harq_pid]->rb_alloc,mod_order,dlsch->harq_processes[harq_pid]->Nl,num_pdcch_symbols,frame,subframe,beamforming_mode); + unsigned int G = get_G(frame_parms,hadlsch->nb_rb, + hadlsch->rb_alloc, + hadlsch->Qm, // mod order + hadlsch->Nl, + num_pdcch_symbols, + frame,subframe,beamforming_mode); - // if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet - if (dlsch->harq_processes[harq_pid]->round == 0) { // this is a new packet -#ifdef DEBUG_DLSCH_CODING - printf("encoding thinks this is a new packet for harq_pid %d (%p), A %u \n",harq_pid,dlsch,A); -#endif - /* - int i; - printf("dlsch (tx): \n"); - for (i=0;i<(A>>3);i++) - printf("%02x.",a[i]); - printf("\n"); - */ + proc->nbEncode=0; + + // if (hadlsch->Ndi == 1) { // this is a new packet + if (hadlsch->round == 0) { // this is a new packet // Add 24-bit crc (polynomial A) to payload - crc = crc24a(a, + unsigned int A=hadlsch->TBS; //6228; + unsigned int crc = crc24a(a, A)>>8; a[A>>3] = ((uint8_t *)&crc)[2]; a[1+(A>>3)] = ((uint8_t *)&crc)[1]; a[2+(A>>3)] = ((uint8_t *)&crc)[0]; // printf("CRC %x (A %d)\n",crc,A); - dlsch->harq_processes[harq_pid]->B = A+24; - // dlsch->harq_processes[harq_pid]->b = a; - memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+4); - - if (lte_segmentation(dlsch->harq_processes[harq_pid]->b, - dlsch->harq_processes[harq_pid]->c, - dlsch->harq_processes[harq_pid]->B, - &dlsch->harq_processes[harq_pid]->C, - &dlsch->harq_processes[harq_pid]->Cplus, - &dlsch->harq_processes[harq_pid]->Cminus, - &dlsch->harq_processes[harq_pid]->Kplus, - &dlsch->harq_processes[harq_pid]->Kminus, - &dlsch->harq_processes[harq_pid]->F)<0) + hadlsch->B = A+24; + // hadlsch->b = a; + memcpy(hadlsch->b,a,(A/8)+4); + + if (lte_segmentation(hadlsch->b, + hadlsch->c, + hadlsch->B, + &hadlsch->C, + &hadlsch->Cplus, + &hadlsch->Cminus, + &hadlsch->Kplus, + &hadlsch->Kminus, + &hadlsch->F)<0) return(-1); - - for (r=0; rharq_processes[harq_pid]->C; r++) { - if (rharq_processes[harq_pid]->Cminus) - Kr = dlsch->harq_processes[harq_pid]->Kminus; - else - Kr = dlsch->harq_processes[harq_pid]->Kplus; - - Kr_bytes = Kr>>3; -#ifdef DEBUG_DLSCH_CODING - printf("Generating Code Segment %u (%u bits)\n",r,Kr); - // generate codewords - printf("bits_per_codeword (Kr)= %u, A %u\n",Kr,A); - printf("N_RB = %d\n",nb_rb); - printf("Ncp %d\n",frame_parms->Ncp); - printf("mod_order %d\n",mod_order); -#endif - start_meas(te_stats); - encoder(dlsch->harq_processes[harq_pid]->c[r], - Kr>>3, - &dlsch->harq_processes[harq_pid]->d[r][96], - (r==0) ? dlsch->harq_processes[harq_pid]->F : 0 - ); - stop_meas(te_stats); -#ifdef DEBUG_DLSCH_CODING - - if (r==0) - LOG_M("enc_output0.m","enc0",&dlsch->harq_processes[harq_pid]->d[r][96],(3*8*Kr_bytes)+12,1,4); - -#endif - start_meas(i_stats); - dlsch->harq_processes[harq_pid]->RTC[r] = - sub_block_interleaving_turbo(4+(Kr_bytes*8), - &dlsch->harq_processes[harq_pid]->d[r][96], - dlsch->harq_processes[harq_pid]->w[r]); - stop_meas(i_stats); + } + + for (int r=0, r_offset=0; rC; r++) { + + union turboReqUnion id= {.s={dlsch->rnti,frame,subframe,r,0}}; + notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboEncode_t), id.p, proc->respEncode, TPencode); + turboEncode_t * rdata=(turboEncode_t *) NotifiedFifoData(req); + rdata->input=hadlsch->c[r]; + rdata->Kr_bytes= ( rCminus ? hadlsch->Kminus : hadlsch->Kplus) >>3; + rdata->filler=(r==0) ? hadlsch->F : 0; + rdata->r=r; + rdata->harq_pid=harq_pid; + rdata->dlsch=dlsch; + rdata->rm_stats=rm_stats; + rdata->te_stats=te_stats; + rdata->i_stats=i_stats; + rdata->round=hadlsch->round; + rdata->r_offset=r_offset; + rdata->G=G; + + if ( proc->threadPool->activated ) { + pushTpool(proc->threadPool,req); + proc->nbEncode++; + } else { + TPencode(rdata); + delNotifiedFIFO_elt(req); } + + int Qm=hadlsch->Qm; + int C=hadlsch->C; + int Nl=hadlsch->Nl; + int Gp = G/Nl/Qm; + int GpmodC = Gp%C; + if (r < (C-(GpmodC))) + r_offset += Nl*Qm * (Gp/C); + else + r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C)); } - // Fill in the "e"-sequence from 36-212, V8.6 2009-03, p. 16-17 (for each "e") and concatenate the - // outputs for each code segment, see Section 5.1.5 p.20 - - for (r=0; rharq_processes[harq_pid]->C; r++) { -#ifdef DEBUG_DLSCH_CODING - printf("Rate Matching, Code segment %u (coded bits (G) %u,unpunctured/repeated bits per code segment %u,mod_order %d, nb_rb %d)...\n", - r, - G, - Kr*3, - mod_order,nb_rb); -#endif - start_meas(rm_stats); -#ifdef DEBUG_DLSCH_CODING - printf("rvidx in encoding = %d\n", dlsch->harq_processes[harq_pid]->rvidx); -#endif - r_offset += lte_rate_matching_turbo(dlsch->harq_processes[harq_pid]->RTC[r], - G, //G - dlsch->harq_processes[harq_pid]->w[r], - dlsch->harq_processes[harq_pid]->e+r_offset, - dlsch->harq_processes[harq_pid]->C, // C - dlsch->Nsoft, // Nsoft, - dlsch->Mdlharq, - dlsch->Kmimo, - dlsch->harq_processes[harq_pid]->rvidx, - dlsch->harq_processes[harq_pid]->Qm, - dlsch->harq_processes[harq_pid]->Nl, - r, - nb_rb); - // m); // r - stop_meas(rm_stats); -#ifdef DEBUG_DLSCH_CODING - - if (r==dlsch->harq_processes[harq_pid]->C-1) - LOG_M("enc_output.m","enc",dlsch->harq_processes[harq_pid]->e,r_offset,1,4); - -#endif - } - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); return(0); } diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c index 04a49d062a..475c8bd521 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c @@ -158,7 +158,7 @@ int allocate_REs_in_RB_no_pilots_QPSK_siso(PHY_VARS_eNB* phy_vars_eNB, { LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->frame_parms; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint32_t qpsk_table_offset_re = 0; uint32_t qpsk_table_offset_im = 0; @@ -248,7 +248,7 @@ int allocate_REs_in_RB_pilots_QPSK_siso(PHY_VARS_eNB* phy_vars_eNB, LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->frame_parms; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint32_t qpsk_table_offset_re = 0; uint32_t qpsk_table_offset_im = 0; @@ -343,7 +343,7 @@ int allocate_REs_in_RB_no_pilots_16QAM_siso(PHY_VARS_eNB* phy_vars_eNB, { LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->frame_parms; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint32_t qam16_table_offset_re = 0; uint32_t qam16_table_offset_im = 0; @@ -439,7 +439,7 @@ int allocate_REs_in_RB_pilots_16QAM_siso(PHY_VARS_eNB* phy_vars_eNB, LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->frame_parms; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint32_t qam16_table_offset_re = 0; uint32_t qam16_table_offset_im = 0; @@ -542,7 +542,7 @@ int allocate_REs_in_RB_no_pilots_64QAM_siso(PHY_VARS_eNB* phy_vars_eNB, LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->frame_parms; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint32_t qam64_table_offset_re = 0; uint32_t qam64_table_offset_im = 0; @@ -699,7 +699,7 @@ int allocate_REs_in_RB_pilots_64QAM_siso(PHY_VARS_eNB* phy_vars_eNB, LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->frame_parms; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint32_t qam64_table_offset_re = 0; uint32_t qam64_table_offset_im = 0; @@ -866,12 +866,12 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB, if ((dlsch0_harq != NULL) && (dlsch1_harq != NULL)) { //this is for TM3, TM4 - x0 = dlsch0_harq->e; + x0 = dlsch0_harq->eDL; mimo_mode = dlsch0_harq->mimo_mode; first_layer0 = dlsch0_harq->first_layer; Nlayers0 = dlsch0_harq->Nlayers; mod_order0 = dlsch0_harq->Qm; - x1 = dlsch1_harq->e; + x1 = dlsch1_harq->eDL; // Fill these in later for TM8-10 // Nlayers1 = dlsch1_harq->Nlayers; // first_layer1 = dlsch1_harq->first_layer; @@ -879,7 +879,7 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB, } else if ((dlsch0_harq != NULL) && (dlsch1_harq == NULL)){ //This is for SIS0 TM1, TM6, etc - x0 = dlsch0_harq->e; + x0 = dlsch0_harq->eDL; mimo_mode = dlsch0_harq->mimo_mode; first_layer0 = dlsch0_harq->first_layer; Nlayers0 = dlsch0_harq->Nlayers; @@ -887,7 +887,7 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB, } else if ((dlsch0_harq == NULL) && (dlsch1_harq != NULL)){ // This is for TM4 retransmission - x0 = dlsch1_harq->e; + x0 = dlsch1_harq->eDL; mimo_mode = dlsch1_harq->mimo_mode; first_layer0 = dlsch1_harq->first_layer; Nlayers0 = dlsch1_harq->Nlayers; @@ -2692,7 +2692,7 @@ int dlsch_modulation_SIC(int32_t **sic_buffer, LTE_DL_eNB_HARQ_t *dlsch0_harq = dlsch0->harq_processes[harq_pid]; uint32_t i,jj,re_allocated=0; uint8_t mod_order0 = dlsch0_harq->Qm; - uint8_t *x0 = dlsch0_harq->e; + uint8_t *x0 = dlsch0_harq->eDL; uint8_t qam64_table_offset_re = 0; uint8_t qam64_table_offset_im = 0; uint8_t qam16_table_offset_re = 0; @@ -2883,7 +2883,7 @@ int mch_modulation(int32_t **txdataF, &jj, re_offset, symbol_offset, - dlsch->harq_processes[0]->e, + dlsch->harq_processes[0]->eDL, l, mod_order, amp, diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_scrambling.c b/openair1/PHY/LTE_TRANSPORT/dlsch_scrambling.c index 2e8ddde848..d48164e07d 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_scrambling.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_scrambling.c @@ -52,7 +52,7 @@ void dlsch_scrambling(LTE_DL_FRAME_PARMS *frame_parms, int n; // uint8_t reset; uint32_t x1, x2, s=0; - uint8_t *dlsch_e=dlsch->harq_processes[harq_pid]->e; + uint8_t *dlsch_e=dlsch->harq_processes[harq_pid]->eDL; uint8_t *e=dlsch_e; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_SCRAMBLING, VCD_FUNCTION_IN); // Rule for accumulation of subframes for BL/CE UEs diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h b/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h index 9673ba15b5..5a08b7a402 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h @@ -19,6 +19,9 @@ * contact@openairinterface.org */ +#ifndef __DLSCH_TBS_FULL__H__ +#define __DLSCH_TBS_FULL__H__ + #define TBStable_rowCnt 27 /** \brief "Transport block size table" @@ -54,3 +57,4 @@ unsigned int TBStable[TBStable_rowCnt][110] = {{16,32,56,88,120,152,176,208,224, }; unsigned int TBStable1C[32] = {40, 56, 72, 120, 136, 144, 176, 208, 224, 256, 280, 296, 328, 336, 392, 488, 552, 600, 632, 696, 776, 840, 904, 1000, 1064, 1128, 1224, 1288, 1384, 1480, 1608, 1736}; +#endif diff --git a/openair1/PHY/LTE_TRANSPORT/if5_tools.h b/openair1/PHY/LTE_TRANSPORT/if5_tools.h index 0f24f7bece..6c75b20bd9 100644 --- a/openair1/PHY/LTE_TRANSPORT/if5_tools.h +++ b/openair1/PHY/LTE_TRANSPORT/if5_tools.h @@ -61,7 +61,8 @@ typedef struct IF5_mobipass_header IF5_mobipass_header_t; void send_IF5(RU_t *, openair0_timestamp, int, uint8_t*, uint16_t); -void recv_IF5(RU_t *, openair0_timestamp*, int, uint16_t); +void recv_IF5(RU_t *ru, openair0_timestamp *proc_timestamp, int subframe, uint16_t packet_type); + void malloc_IF5_buffer(RU_t *ru); diff --git a/openair1/PHY/LTE_TRANSPORT/lte_mcs.c b/openair1/PHY/LTE_TRANSPORT/lte_mcs.c index c13876f29a..6144b978bf 100644 --- a/openair1/PHY/LTE_TRANSPORT/lte_mcs.c +++ b/openair1/PHY/LTE_TRANSPORT/lte_mcs.c @@ -94,6 +94,35 @@ unsigned char I_TBS2I_MCS(unsigned char I_TBS) { return I_MCS; } +uint16_t find_nb_rb_DL(uint8_t mcs, uint32_t bytes, uint16_t nb_rb_max, uint16_t rb_gran) { + if (bytes == 0 || mcs > 28 || nb_rb_max == 0) + return 0; + const uint32_t bits = bytes << 3; + const unsigned char I_TBS = get_I_TBS(mcs); + + uint32_t TBS = TBStable[I_TBS][nb_rb_max - 1]; + if (bits >= TBS) // is nb_rb_max too small? + return nb_rb_max; + + TBS = TBStable[I_TBS][rb_gran - 1]; + if (bits <= TBS) // is rb_gran RB enough? + return rb_gran; + + nb_rb_max += nb_rb_max % rb_gran; // round up to full RBG + uint16_t hi = nb_rb_max/rb_gran - 1; + uint16_t lo = 0; + uint16_t p = (hi + lo) / 2; + for (; lo + 1 != hi; p = (hi + lo) / 2) { + const uint16_t rbi = (p + 1) * rb_gran - 1; // convert "RBG" -> RB + TBS = TBStable[I_TBS][rbi]; + if (bits <= TBS) // need less RBs + hi = p; + else // need more RBs + lo = p; + } + return (hi + 1) * rb_gran; +} + uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb) { uint32_t TBS; diff --git a/openair1/PHY/LTE_TRANSPORT/phich.c b/openair1/PHY/LTE_TRANSPORT/phich.c index ab2fe2d743..6d8b58818b 100644 --- a/openair1/PHY/LTE_TRANSPORT/phich.c +++ b/openair1/PHY/LTE_TRANSPORT/phich.c @@ -714,7 +714,7 @@ void generate_phich_top(PHY_VARS_eNB *eNB, int32_t **txdataF = eNB->common_vars.txdataF; uint8_t Ngroup_PHICH,ngroup_PHICH,nseq_PHICH; uint8_t NSF_PHICH = 4; - uint8_t pusch_subframe; + uint8_t pusch_subframe=-1; uint8_t i; int subframe = proc->subframe_tx; phich_config_t *phich; diff --git a/openair1/PHY/LTE_TRANSPORT/pmch.c b/openair1/PHY/LTE_TRANSPORT/pmch.c index f48ee629a1..90e2836b1e 100644 --- a/openair1/PHY/LTE_TRANSPORT/pmch.c +++ b/openair1/PHY/LTE_TRANSPORT/pmch.c @@ -105,6 +105,7 @@ void generate_mch(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc,uint8_t *a) AssertFatal(eNB->dlsch_MCH->harq_processes[0]->pdu != NULL, "attempt to encode a NULL harq PDU\n"); AssertFatal(dlsch_encoding(eNB, + proc, // a, eNB->dlsch_MCH->harq_processes[0]->pdu, 1, diff --git a/openair1/PHY/LTE_TRANSPORT/prach.c b/openair1/PHY/LTE_TRANSPORT/prach.c index 3471f98af7..24faf584d3 100644 --- a/openair1/PHY/LTE_TRANSPORT/prach.c +++ b/openair1/PHY/LTE_TRANSPORT/prach.c @@ -38,9 +38,13 @@ #include "SCHED/sched_eNB.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "prach_extern.h" +#include +#include void rx_prach0(PHY_VARS_eNB *eNB, RU_t *ru, + int frame_prach, + int subframe, uint16_t *max_preamble, uint16_t *max_preamble_energy, uint16_t *max_preamble_delay, @@ -51,17 +55,14 @@ void rx_prach0(PHY_VARS_eNB *eNB, uint8_t ce_level ) { int i; - LTE_DL_FRAME_PARMS *fp=NULL; lte_frame_type_t frame_type; uint16_t rootSequenceIndex; uint8_t prach_ConfigIndex; uint8_t Ncs_config; uint8_t restricted_set; uint8_t n_ra_prb; - int subframe; int16_t *prachF=NULL; int16_t **rxsigF=NULL; - int nb_rx=0; int16_t *prach2; uint8_t preamble_index; uint16_t NCS,NCS2; @@ -89,6 +90,8 @@ void rx_prach0(PHY_VARS_eNB *eNB, int32_t **prach_ifftp=(int32_t **)NULL; int prach_ifft_cnt=0; + LTE_DL_FRAME_PARMS *fp; + int nb_rx; if(eNB) { fp = &(eNB->frame_parms); nb_rx = fp->nb_antennas_rx; @@ -96,7 +99,7 @@ void rx_prach0(PHY_VARS_eNB *eNB, fp = (ru->frame_parms); nb_rx = ru->nb_rx; } - + AssertFatal(fp!=NULL,"rx_prach called without valid RU or eNB descriptor\n"); frame_type = fp->frame_type; @@ -133,14 +136,13 @@ void rx_prach0(PHY_VARS_eNB *eNB, if (eNB) { if (br_flag == 1) { prach_ifftp = eNB->prach_vars_br.prach_ifft[ce_level]; - subframe = eNB->proc.subframe_prach_br; prachF = eNB->prach_vars_br.prachF; rxsigF = eNB->prach_vars_br.rxsigF[ce_level]; if (LOG_DEBUGFLAG(PRACH)) { - if (((eNB->proc.frame_prach)&1023) < 20) LOG_I(PHY, + if (((frame_prach)&1023) < 20) LOG_I(PHY, "PRACH (eNB) : running rx_prach (br_flag %d, ce_level %d) for frame %d subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d, rootSequenceIndex %d, repetition number %d,numRepetitionsPrePreambleAttempt %d\n", - br_flag,ce_level,eNB->proc.frame_prach,subframe, + br_flag,ce_level,frame_prach,subframe, fp->prach_emtc_config_common.prach_ConfigInfo.prach_FreqOffset[ce_level], prach_ConfigIndex,rootSequenceIndex, eNB->prach_vars_br.repetition_number[ce_level], @@ -148,30 +150,27 @@ void rx_prach0(PHY_VARS_eNB *eNB, } } else { prach_ifftp = eNB->prach_vars.prach_ifft[0]; - subframe = eNB->proc.subframe_prach; prachF = eNB->prach_vars.prachF; rxsigF = eNB->prach_vars.rxsigF[0]; if (LOG_DEBUGFLAG(PRACH)) { - if (((eNB->proc.frame_prach)&1023) < 20) LOG_I(PHY,"PRACH (eNB) : running rx_prach for subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d , rootSequenceIndex %d\n", subframe, + if (((frame_prach)&1023) < 20) LOG_I(PHY,"PRACH (eNB) : running rx_prach for subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d , rootSequenceIndex %d\n", subframe, fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset,prach_ConfigIndex,rootSequenceIndex); } } } else { if (br_flag == 1) { - subframe = ru->proc.subframe_prach_br; rxsigF = ru->prach_rxsigF_br[ce_level]; if (LOG_DEBUGFLAG(PRACH)) { - if (((ru->proc.frame_prach)&1023) < 20) LOG_I(PHY,"PRACH (RU) : running rx_prach (br_flag %d, ce_level %d) for frame %d subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d\n", - br_flag,ce_level,ru->proc.frame_prach,subframe,fp->prach_emtc_config_common.prach_ConfigInfo.prach_FreqOffset[ce_level],prach_ConfigIndex); + if (((frame_prach)&1023) < 20) LOG_I(PHY,"PRACH (RU) : running rx_prach (br_flag %d, ce_level %d) for frame %d subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d\n", + br_flag,ce_level,frame_prach,subframe,fp->prach_emtc_config_common.prach_ConfigInfo.prach_FreqOffset[ce_level],prach_ConfigIndex); } } else { - subframe = ru->proc.subframe_prach; rxsigF = ru->prach_rxsigF; if (LOG_DEBUGFLAG(PRACH)) { - if (((ru->proc.frame_prach)&1023) < 20) LOG_I(PHY,"PRACH (RU) : running rx_prach for subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d\n", + if (((frame_prach)&1023) < 20) LOG_I(PHY,"PRACH (RU) : running rx_prach for subframe %d, prach_FreqOffset %d, prach_ConfigIndex %d\n", subframe,fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset,prach_ConfigIndex); } } @@ -202,7 +201,7 @@ void rx_prach0(PHY_VARS_eNB *eNB, if (prach[0]!= NULL) LOG_M("prach_rx","prach_rx",prach[0],fp->samples_per_tti,1,1); LOG_I(PHY,"RU %d, br_flag %d ce_level %d frame %d subframe %d per_tti:%d prach:%p (energy %d) TA:%d %s rxdata:%p index:%d\n", - ru->idx,br_flag,ce_level,ru->proc.frame_prach,subframe,fp->samples_per_tti, + ru->idx,br_flag,ce_level,frame_prach,subframe,fp->samples_per_tti, prach[aa],dbEn0,ru->N_TA_offset,buffer,ru->common.rxdata[aa], (subframe*fp->samples_per_tti)-ru->N_TA_offset); } @@ -298,24 +297,24 @@ void rx_prach0(PHY_VARS_eNB *eNB, switch (fp->N_RB_UL) { case 6: if (prach_fmt == 4) { - dft256(prach2,rxsigF[aa],1); + dft(DFT_256,prach2,rxsigF[aa],1); } else { - dft1536(prach2,rxsigF[aa],1); + dft(DFT_1536,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft1536(prach2+3072,rxsigF[aa]+3072,1); + dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1); } break; case 15: if (prach_fmt == 4) { - dft256(prach2,rxsigF[aa],1); + dft(DFT_256,prach2,rxsigF[aa],1); } else { - dft3072(prach2,rxsigF[aa],1); + dft(DFT_3072,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft3072(prach2+6144,rxsigF[aa]+6144,1); + dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1); } break; @@ -323,13 +322,13 @@ void rx_prach0(PHY_VARS_eNB *eNB, case 25: default: if (prach_fmt == 4) { - dft1024(prach2,rxsigF[aa],1); + dft(DFT_1024,prach2,rxsigF[aa],1); fft_size = 1024; } else { - dft6144(prach2,rxsigF[aa],1); + dft(DFT_6144,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft6144(prach2+12288,rxsigF[aa]+12288,1); + dft(DFT_6144,prach2+12288,rxsigF[aa]+12288,1); fft_size = 6144; } @@ -338,24 +337,24 @@ void rx_prach0(PHY_VARS_eNB *eNB, case 50: if (prach_fmt == 4) { - dft2048(prach2,rxsigF[aa],1); + dft(DFT_2048,prach2,rxsigF[aa],1); } else { - dft12288(prach2,rxsigF[aa],1); + dft(DFT_12288,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft12288(prach2+24576,rxsigF[aa]+24576,1); + dft(DFT_12288,prach2+24576,rxsigF[aa]+24576,1); } break; case 75: if (prach_fmt == 4) { - dft3072(prach2,rxsigF[aa],1); + dft(DFT_3072,prach2,rxsigF[aa],1); } else { - dft18432(prach2,rxsigF[aa],1); + dft(DFT_18432,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft18432(prach2+36864,rxsigF[aa]+36864,1); + dft(DFT_18432,prach2+36864,rxsigF[aa]+36864,1); } break; @@ -363,21 +362,21 @@ void rx_prach0(PHY_VARS_eNB *eNB, case 100: if (fp->threequarter_fs==0) { if (prach_fmt == 4) { - dft4096(prach2,rxsigF[aa],1); + dft(DFT_4096,prach2,rxsigF[aa],1); } else { - dft24576(prach2,rxsigF[aa],1); + dft(DFT_24576,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft24576(prach2+49152,rxsigF[aa]+49152,1); + dft(DFT_24576,prach2+49152,rxsigF[aa]+49152,1); } } else { if (prach_fmt == 4) { - dft3072(prach2,rxsigF[aa],1); + dft(DFT_3072,prach2,rxsigF[aa],1); } else { - dft18432(prach2,rxsigF[aa],1); + dft(DFT_18432,prach2,rxsigF[aa],1); if (prach_fmt>1) - dft18432(prach2+36864,rxsigF[aa]+36864,1); + dft(DFT_18432,prach2+36864,rxsigF[aa]+36864,1); } } @@ -407,16 +406,16 @@ void rx_prach0(PHY_VARS_eNB *eNB, if ((eNB==NULL) && ru->function == NGFI_RRU_IF4p5) { /// **** send_IF4 of rxsigF to RAU **** /// if (br_flag == 1) - send_IF4p5(ru, ru->proc.frame_prach, ru->proc.subframe_prach, IF4p5_PRACH+1+ce_level); + send_IF4p5(ru, frame_prach, subframe, IF4p5_PRACH+1+ce_level); else - send_IF4p5(ru, ru->proc.frame_prach, ru->proc.subframe_prach, IF4p5_PRACH); + send_IF4p5(ru, frame_prach, subframe, IF4p5_PRACH); return; } else if (eNB!=NULL) { if ( LOG_DEBUGFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t *)&rxsigF[0][0],840)); - if ((en > 60)&&(br_flag==1)) LOG_I(PHY,"PRACH (br_flag %d,ce_level %d, n_ra_prb %d, k %d): Frame %d, Subframe %d => %d dB\n",br_flag,ce_level,n_ra_prb,k,eNB->proc.frame_rx,eNB->proc.subframe_rx,en); + if ((en > 60)&&(br_flag==1)) LOG_I(PHY,"PRACH (br_flag %d,ce_level %d, n_ra_prb %d, k %d): Frame %d, Subframe %d => %d dB\n",br_flag,ce_level,n_ra_prb,k,frame_prach,subframe,en); } } @@ -457,7 +456,7 @@ void rx_prach0(PHY_VARS_eNB *eNB, if (LOG_DEBUGFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t *)&rxsigF[0][0],840)); - if (en>60) LOG_I(PHY,"frame %d, subframe %d : Trying preamble %d (br_flag %d)\n",ru->proc.frame_prach,subframe,preamble_index,br_flag); + if (en>60) LOG_I(PHY,"frame %d, subframe %d : Trying preamble %d (br_flag %d)\n",frame_prach,subframe,preamble_index,br_flag); } if (restricted_set == 0) { @@ -543,7 +542,7 @@ void rx_prach0(PHY_VARS_eNB *eNB, int en = dB_fixed(signal_energy((int32_t *)&rxsigF[0][0],840)); if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d: offset %d, preamble shift %d (br_flag %d, en %d)\n", - ru->proc.frame_prach,subframe,preamble_index,preamble_offset,preamble_shift,br_flag,en); + frame_prach,subframe,preamble_index,preamble_offset,preamble_shift,br_flag,en); } log2_ifft_size = 10; @@ -589,13 +588,13 @@ void rx_prach0(PHY_VARS_eNB *eNB, // Now do IFFT of size 1024 (N_ZC=839) or 256 (N_ZC=139) if (N_ZC == 839) { log2_ifft_size = 10; - idft1024(prachF,prach_ifft_tmp,1); + idft(IDFT_1024,prachF,prach_ifft_tmp,1); // compute energy and accumulate over receive antennas and repetitions for BR for (i=0; i<2048; i++) prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[i<<1] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>9; } else { - idft256(prachF,prach_ifft_tmp,1); + idft(IDFT_256,prachF,prach_ifft_tmp,1); log2_ifft_size = 8; // compute energy and accumulate over receive antennas and repetitions for BR @@ -618,7 +617,7 @@ void rx_prach0(PHY_VARS_eNB *eNB, if (LOG_DEBUGFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t *)&rxsigF[0][0],840)); - if (en>60) LOG_I(PHY,"frame %d, subframe %d: Checking for peak in time-domain (br_flag %d, en %d)\n",ru->proc.frame_prach,subframe,br_flag,en); + if (en>60) LOG_I(PHY,"frame %d, subframe %d: Checking for peak in time-domain (br_flag %d, en %d)\n",frame_prach,subframe,br_flag,en); } preamble_shift2 = ((preamble_shift==0) ? 0 : ((preamble_shift<60) && (br_flag==1)) LOG_D(PHY,"frame %d, subframe %d : max_preamble_energy %d, max_preamble_delay %d, max_preamble %d (br_flag %d,ce_level %d, levdB %d, lev %d)\n", - ru->proc.frame_prach,subframe, + frame_prach,subframe, *max_preamble_energy,*max_preamble_delay, *max_preamble,br_flag,ce_level,levdB,lev); } @@ -694,8 +693,16 @@ void rx_prach(PHY_VARS_eNB *eNB, int i; int prach_mask=0; + int subframe; + if (eNB) + subframe= br_flag?eNB->proc.subframe_prach_br:eNB->proc.subframe_prach; + else + subframe= br_flag?ru->proc.subframe_prach_br:ru->proc.subframe_prach; + + int frame_prach=eNB?eNB->proc.frame_prach: ru->proc.frame_prach; + if (br_flag == 0) { - rx_prach0(eNB,ru,max_preamble,max_preamble_energy,max_preamble_delay,avg_preamble_energy,Nf,tdd_mapindex,0,0); + rx_prach0(eNB,ru,frame_prach,subframe,max_preamble,max_preamble_energy,max_preamble_delay,avg_preamble_energy,Nf,tdd_mapindex,0,0); } else { // This is procedure for eMTC, basically handling the repetitions prach_mask = is_prach_subframe(&eNB->frame_parms,eNB->proc.frame_prach_br,eNB->proc.subframe_prach_br); @@ -709,7 +716,7 @@ void rx_prach(PHY_VARS_eNB *eNB, // increment repetition number eNB->prach_vars_br.repetition_number[i]++; // do basic PRACH reception - rx_prach0(eNB,ru,max_preamble,max_preamble_energy,max_preamble_delay,avg_preamble_energy,Nf,tdd_mapindex,1,i); + rx_prach0(eNB,ru,frame_prach,subframe,max_preamble,max_preamble_energy,max_preamble_delay,avg_preamble_energy,Nf,tdd_mapindex,1,i); // if last repetition, clear counter if (eNB->prach_vars_br.repetition_number[i] == eNB->frame_parms.prach_emtc_config_common.prach_ConfigInfo.prach_numRepetitionPerPreambleAttempt[i]) { diff --git a/openair1/PHY/LTE_TRANSPORT/prach_extern.h b/openair1/PHY/LTE_TRANSPORT/prach_extern.h index 2f8a83e24f..47fbd93ad7 100644 --- a/openair1/PHY/LTE_TRANSPORT/prach_extern.h +++ b/openair1/PHY/LTE_TRANSPORT/prach_extern.h @@ -29,6 +29,10 @@ * \note * \warning */ + +#ifndef __PHY_LTE_TRANSPORT_PRACH_EXTERN__H__ +#define __PHY_LTE_TRANSPORT_PRACH_EXTERN__H__ + #include "PHY/sse_intrin.h" #include "PHY/defs_eNB.h" #include "PHY/phy_extern.h" @@ -91,3 +95,4 @@ void compute_prach_seq(uint16_t rootSequenceIndex, lte_frame_type_t frame_type, uint32_t X_u[64][839]); +#endif diff --git a/openair1/PHY/LTE_TRANSPORT/pucch.c b/openair1/PHY/LTE_TRANSPORT/pucch.c index e142d2f29f..8637e80137 100644 --- a/openair1/PHY/LTE_TRANSPORT/pucch.c +++ b/openair1/PHY/LTE_TRANSPORT/pucch.c @@ -180,7 +180,7 @@ uint16_t pucchfmt3_ChannelEstimation( int16_t SubCarrierDeMapData[NB_ANTENNAS_RX uint16_t n3_pucch_array[NUMBER_OF_UE_MAX], uint8_t ncs_cell[20][7] ) { uint32_t aa, symNo, k, slotNo, sym, i, j; - int16_t np, np_n, ip_ind; + int16_t np, np_n, ip_ind=-1; //int16_t npucch_sf; int16_t calctmp[2]; int16_t BsCshData[NB_ANTENNAS_RX][D_NSYM1SF][D_NSC1RB][2]; diff --git a/openair1/PHY/LTE_TRANSPORT/pucch_extern.h b/openair1/PHY/LTE_TRANSPORT/pucch_extern.h index 899b904306..b151374888 100644 --- a/openair1/PHY/LTE_TRANSPORT/pucch_extern.h +++ b/openair1/PHY/LTE_TRANSPORT/pucch_extern.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __PHY_LTE_TRANSPORT_PUCCH_EXTERN__H__ +#define __PHY_LTE_TRANSPORT_PUCCH_EXTERN__H__ + #include /* PUCCH format3 >> */ @@ -76,3 +79,5 @@ extern uint8_t Np4_TBL[4]; // alpha_TBL extern int16_t alphaTBL_re[12]; extern int16_t alphaTBL_im[12]; + +#endif diff --git a/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h b/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h index 1d7aa598af..e4f5d9a17f 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h @@ -60,6 +60,8 @@ unsigned char get_I_TBS_UL(unsigned char I_MCS); @return Transport block size */ uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb); +uint16_t find_nb_rb_DL(uint8_t mcs, uint32_t bytes, uint16_t nb_rb_max, uint16_t rb_gran); + /** \brief Compute Q (modulation order) based on uplink I_MCS. Implements table 7.1.7.1-1 from 36.213. @param I_MCS @param nb_rb diff --git a/openair1/PHY/LTE_TRANSPORT/transport_eNB.h b/openair1/PHY/LTE_TRANSPORT/transport_eNB.h index 7b9004ba80..5e446db5fd 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_eNB.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_eNB.h @@ -100,7 +100,7 @@ typedef struct { /// start symbold of pdsch uint8_t pdsch_start; /// Concatenated "e"-sequences (for definition see 36-212 V8.6 2009-03, p.17-18) - uint8_t e[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32))); + uint8_t eDL[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32))); /// Turbo-code outputs (36-212 V8.6 2009-03, p.12 uint8_t *d[MAX_NUM_DLSCH_SEGMENTS];//[(96+3+(3*6144))]; /// Sub-block interleaver outputs (36-212 V8.6 2009-03, p.16-17) @@ -261,12 +261,13 @@ typedef struct { /// coded RI bits int16_t q_RI[MAX_RI_PAYLOAD]; /// Concatenated "e"-sequences (for definition see 36-212 V8.6 2009-03, p.17-18) - int16_t e[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32))); + int16_t eUL[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32))); /// Temporary h sequence to flag PUSCH_x/PUSCH_y symbols which are not scrambled uint8_t h[MAX_NUM_CHANNEL_BITS]; /// Pointer to the payload - uint8_t *b; + uint8_t *decodedBytes; /// Pointers to transport block segments + //TBD uint8_t *c[MAX_NUM_ULSCH_SEGMENTS]; /// RTC values for each segment (for definition see 36-212 V8.6 2009-03, p.15) uint32_t RTC[MAX_NUM_ULSCH_SEGMENTS]; @@ -282,8 +283,12 @@ typedef struct { uint8_t rvidx; /// soft bits for each received segment ("w"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) int16_t w[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; + int16_t pusch_rep_buffer[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; /// soft bits for each received segment ("d"-sequence)(for definition see 36-212 V8.6 2009-03, p.15) + //TBD int16_t *d[MAX_NUM_ULSCH_SEGMENTS]; + uint32_t processedSegments; + uint32_t processedBadSegment; /// Number of code segments (for definition see 36-212 V8.6 2009-03, p.9) uint32_t C; /// Number of "small" code segments (for definition see 36-212 V8.6 2009-03, p.10) diff --git a/openair1/PHY/LTE_TRANSPORT/transport_extern.h b/openair1/PHY/LTE_TRANSPORT/transport_extern.h index 357d31ca10..8b33449cca 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_extern.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_extern.h @@ -22,7 +22,7 @@ extern unsigned int dlsch_tbs25[27][25],TBStable[27][110],TBStable1C[32]; extern unsigned short lte_cqi_eff1024[16]; extern char lte_cqi_snr_dB[15]; -extern short conjugate[8],conjugate2[8]; +extern const short conjugate[8],conjugate2[8]; extern short minus_one[8]; extern short minus_one[8]; extern short *ul_ref_sigs[30][2][34]; diff --git a/openair1/PHY/LTE_TRANSPORT/transport_proto.h b/openair1/PHY/LTE_TRANSPORT/transport_proto.h index f034039e7e..3988923bb9 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_proto.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_proto.h @@ -73,18 +73,19 @@ void free_eNB_ulsch(LTE_eNB_ULSCH_t *ulsch); LTE_eNB_ULSCH_t *new_eNB_ulsch(uint8_t max_turbo_iterations,uint8_t N_RB_UL, uint8_t abstraction_flag); int dlsch_encoding_all(PHY_VARS_eNB *eNB, - unsigned char *a, - uint8_t num_pdcch_symbols, - LTE_eNB_DLSCH_t *dlsch, - int frame, - uint8_t subframe, - time_stats_t *rm_stats, - time_stats_t *te_stats, - time_stats_t *te_wait_stats, - time_stats_t *te_main_stats, - time_stats_t *te_wakeup_stats0, - time_stats_t *te_wakeup_stats1, - time_stats_t *i_stats); + L1_rxtx_proc_t *proc, + unsigned char *a, + uint8_t num_pdcch_symbols, + LTE_eNB_DLSCH_t *dlsch, + int frame, + uint8_t subframe, + time_stats_t *rm_stats, + time_stats_t *te_stats, + time_stats_t *te_wait_stats, + time_stats_t *te_main_stats, + time_stats_t *te_wakeup_stats0, + time_stats_t *te_wakeup_stats1, + time_stats_t *i_stats); /** \fn dlsch_encoding(PHY_VARS_eNB *eNB, uint8_t *input_buffer, @@ -112,6 +113,7 @@ int dlsch_encoding_all(PHY_VARS_eNB *eNB, @returns status */ int32_t dlsch_encoding(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, uint8_t *a, uint8_t num_pdcch_symbols, LTE_eNB_DLSCH_t *dlsch, @@ -467,9 +469,12 @@ void rx_ulsch(PHY_VARS_eNB *eNB, int ulsch_decoding_data_all(PHY_VARS_eNB *eNB, - int UE_id, - int harq_pid, - int llr8_flag); + + L1_rxtx_proc_t *proc, + int UE_id, + int harq_pid, + int llr8_flag); + /*! \brief Decoding of PUSCH/ACK/RI/ACK from 36-212. @@ -511,6 +516,7 @@ int ulsch_decoding_data_2thread(PHY_VARS_eNB *eNB, @returns 0 on success */ int ulsch_decoding_data(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, int UE_id, int harq_pid, int llr8_flag); diff --git a/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c b/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c index 39556902fc..92fe777201 100644 --- a/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c +++ b/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c @@ -41,22 +41,22 @@ #include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface.h" #include "transport_proto.h" -#include "common/utils/LOG/vcd_signal_dumper.h" - +#include extern WORKER_CONF_t get_thread_worker_conf(void); extern volatile int oai_exit; + void free_eNB_ulsch(LTE_eNB_ULSCH_t *ulsch) { int i,r; if (ulsch) { for (i=0; i<8; i++) { if (ulsch->harq_processes[i]) { - if (ulsch->harq_processes[i]->b) { - free16(ulsch->harq_processes[i]->b,MAX_ULSCH_PAYLOAD_BYTES); - ulsch->harq_processes[i]->b = NULL; + if (ulsch->harq_processes[i]->decodedBytes) { + free16(ulsch->harq_processes[i]->decodedBytes,MAX_ULSCH_PAYLOAD_BYTES); + ulsch->harq_processes[i]->decodedBytes = NULL; } for (r=0; rharq_processes[i]) { memset(ulsch->harq_processes[i],0,sizeof(LTE_UL_eNB_HARQ_t)); - ulsch->harq_processes[i]->b = (uint8_t *)malloc16(MAX_ULSCH_PAYLOAD_BYTES/bw_scaling); + ulsch->harq_processes[i]->decodedBytes = (uint8_t *)malloc16(MAX_ULSCH_PAYLOAD_BYTES/bw_scaling); - if (ulsch->harq_processes[i]->b) - memset(ulsch->harq_processes[i]->b,0,MAX_ULSCH_PAYLOAD_BYTES/bw_scaling); + if (ulsch->harq_processes[i]->decodedBytes) + memset(ulsch->harq_processes[i]->decodedBytes,0,MAX_ULSCH_PAYLOAD_BYTES/bw_scaling); else exit_flag=3; @@ -210,388 +210,26 @@ uint8_t extract_cqi_crc(uint8_t *cqi,uint8_t CQI_LENGTH) { return(crc); } - - - -int ulsch_decoding_data_2thread0(td_params *tdp) { - PHY_VARS_eNB *eNB = tdp->eNB; - int UE_id = tdp->UE_id; - int harq_pid = tdp->harq_pid; - int llr8_flag = tdp->llr8_flag; - unsigned int r,r_offset=0,Kr,Kr_bytes; - uint8_t crc_type; - int offset = 0; - int ret = 1; - int16_t dummy_w[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; - LTE_eNB_ULSCH_t *ulsch = eNB->ulsch[UE_id]; - LTE_UL_eNB_HARQ_t *ulsch_harq = ulsch->harq_processes[harq_pid]; - int Q_m = ulsch_harq->Qm; - int G = ulsch_harq->G; - uint32_t E=0; - uint32_t Gp,GpmodC,Nl=1; - uint32_t C = ulsch_harq->C; - decoder_if_t *tc; - - if (llr8_flag == 0) - tc = decoder16; - else - tc = decoder8; - - // go through first half of segments to get r_offset - for (r=0; r<(ulsch_harq->C/2); r++) { - // Get Turbo interleaver parameters - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - // This is stolen from rate-matching algorithm to get the value of E - Gp = G/Nl/Q_m; - GpmodC = Gp%C; - - if (r < (C-(GpmodC))) - E = Nl*Q_m * (Gp/C); - else - E = Nl*Q_m * ((GpmodC==0?0:1) + (Gp/C)); - - r_offset += E; - - if (r==0) { - offset = Kr_bytes - (ulsch_harq->F>>3) - ((ulsch_harq->C>1)?3:0); - } else { - offset += (Kr_bytes- ((ulsch_harq->C>1)?3:0)); - } - } - - // go through second half of segments - for (; r<(ulsch_harq->C); r++) { - // printf("before subblock deinterleaving c[%d] = %p\n",r,ulsch_harq->c[r]); - // Get Turbo interleaver parameters - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - memset(&dummy_w[r][0],0,3*(6144+64)*sizeof(short)); - ulsch_harq->RTC[r] = generate_dummy_w(4+(Kr_bytes*8), - (uint8_t *)&dummy_w[r][0], +void processULSegment(void * arg) { + turboDecode_t* rdata=(turboDecode_t*) arg; + PHY_VARS_eNB *eNB=rdata->eNB; + LTE_UL_eNB_HARQ_t *ulsch_harq=rdata->ulsch_harq; + int r=rdata->segment_r; + int G=ulsch_harq->G; + int Kr_bytes=rdata->Kr>>3; + int16_t dummy_w[3*(6144+64)]; + + memset(&dummy_w[0],0,3*(6144+64)*sizeof(short)); + ulsch_harq->RTC[r] = generate_dummy_w(4+(Kr_bytes*8), + (uint8_t *)&dummy_w[0], (r==0) ? ulsch_harq->F : 0); -#ifdef DEBUG_ULSCH_DECODING - printf("Rate Matching Segment %u (coded bits (G) %d,unpunctured/repeated bits %u, Q_m %d, nb_rb %d, Nl %d)...\n", - r, G, - Kr*3, - Q_m, - nb_rb, - ulsch_harq->Nl); -#endif - - if (lte_rate_matching_turbo_rx(ulsch_harq->RTC[r], - G, - ulsch_harq->w[r], - (uint8_t *) &dummy_w[r][0], - ulsch_harq->e+r_offset, - ulsch_harq->C, - NSOFT, - 0, //Uplink - 1, - ulsch_harq->rvidx, - (ulsch_harq->round==0)?1:0, // clear - ulsch_harq->Qm, - 1, - r, - &E)==-1) { - LOG_E(PHY,"ulsch_decoding.c: Problem in rate matching\n"); - return(-1); - } - - r_offset += E; - sub_block_deinterleaving_turbo(4+Kr, - &ulsch_harq->d[r][96], - ulsch_harq->w[r]); - - if (ulsch_harq->C == 1) - crc_type = CRC24_A; - else - crc_type = CRC24_B; - - ret = tc(&ulsch_harq->d[r][96], - NULL, - ulsch_harq->c[r], - NULL, - Kr, - ulsch->max_turbo_iterations,//MAX_TURBO_ITERATIONS, - crc_type, - (r==0) ? ulsch_harq->F : 0, - &eNB->ulsch_tc_init_stats, - &eNB->ulsch_tc_alpha_stats, - &eNB->ulsch_tc_beta_stats, - &eNB->ulsch_tc_gamma_stats, - &eNB->ulsch_tc_ext_stats, - &eNB->ulsch_tc_intl1_stats, - &eNB->ulsch_tc_intl2_stats); - - // Reassembly of Transport block here - - if (ret != (1+ulsch->max_turbo_iterations)) { - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - memcpy(ulsch_harq->b+offset, - ulsch_harq->c[r], - Kr_bytes - ((ulsch_harq->C>1)?3:0)); - offset += (Kr_bytes- ((ulsch_harq->C>1)?3:0)); - } else { - break; - } - } - - return(ret); -} - - -void *td_thread(void *param) { - PHY_VARS_eNB *eNB = ((td_params *)param)->eNB; - L1_proc_t *proc = &eNB->proc; - pthread_setname_np( pthread_self(),"td processing"); - LOG_I(PHY,"thread td created id=%ld\n", syscall(__NR_gettid)); - //wait_sync("td_thread"); - - while (!oai_exit) { - if (wait_on_condition(&proc->mutex_td,&proc->cond_td,&proc->instance_cnt_td,"td thread")<0) break; - - if(oai_exit) break; - - ((td_params *)param)->ret = ulsch_decoding_data_2thread0((td_params *)param); - - if (release_thread(&proc->mutex_td,&proc->instance_cnt_td,"td thread")<0) break; - - if (pthread_cond_signal(&proc->cond_td) != 0) { - printf("[eNB] ERROR pthread_cond_signal for td thread exit\n"); - exit_fun( "ERROR pthread_cond_signal" ); - return(NULL); - } - } - - return(NULL); -} - -int ulsch_decoding_data_2thread(PHY_VARS_eNB *eNB,int UE_id,int harq_pid,int llr8_flag) { - L1_proc_t *proc = &eNB->proc; - unsigned int r,r_offset=0,Kr,Kr_bytes; - uint8_t crc_type; - int offset = 0; - int ret = 1; - int16_t dummy_w[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; - LTE_eNB_ULSCH_t *ulsch = eNB->ulsch[UE_id]; - LTE_UL_eNB_HARQ_t *ulsch_harq = ulsch->harq_processes[harq_pid]; - int G = ulsch_harq->G; + start_meas(&eNB->ulsch_deinterleaving_stats); unsigned int E; - int Cby2; - decoder_if_t *tc; - struct timespec wait; - wait.tv_sec=0; - wait.tv_nsec=5000000L; - - if (llr8_flag == 0) - tc = decoder16; - else - tc = decoder8; - - if (ulsch_harq->C>1) { // wakeup worker if more than 1 segment - if (pthread_mutex_timedlock(&proc->mutex_td,&wait) != 0) { - printf("[eNB] ERROR pthread_mutex_lock for TD thread (IC %d)\n", proc->instance_cnt_td); - exit_fun( "error locking mutex_fep" ); - return -1; - } - - if (proc->instance_cnt_td==0) { - printf("[eNB] TD thread busy\n"); - exit_fun("TD thread busy"); - pthread_mutex_unlock( &proc->mutex_td ); - return -1; - } - - ++proc->instance_cnt_td; - proc->tdp.eNB = eNB; - proc->tdp.UE_id = UE_id; - proc->tdp.harq_pid = harq_pid; - proc->tdp.llr8_flag = llr8_flag; - - // wakeup worker to do second half segments - if (pthread_cond_signal(&proc->cond_td) != 0) { - printf("[eNB] ERROR pthread_cond_signal for td thread exit\n"); - exit_fun( "ERROR pthread_cond_signal" ); - return (1+ulsch->max_turbo_iterations); - } - - pthread_mutex_unlock( &proc->mutex_td ); - Cby2 = ulsch_harq->C/2; - } else { - Cby2 = 1; - } - - // go through first half of segments in main thread - for (r=0; rc[r]); - // Get Turbo interleaver parameters - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - memset(&dummy_w[r][0],0,3*(6144+64)*sizeof(short)); - ulsch_harq->RTC[r] = generate_dummy_w(4+(Kr_bytes*8), - (uint8_t *)&dummy_w[r][0], - (r==0) ? ulsch_harq->F : 0); -#ifdef DEBUG_ULSCH_DECODING - printf("Rate Matching Segment %u (coded bits (G) %d,unpunctured/repeated bits %u, Q_m %d, nb_rb %d, Nl %d)...\n", - r, G, - Kr*3, - Q_m, - nb_rb, - ulsch_harq->Nl); -#endif - start_meas(&eNB->ulsch_rate_unmatching_stats); - - if (lte_rate_matching_turbo_rx(ulsch_harq->RTC[r], + if (lte_rate_matching_turbo_rx(ulsch_harq->RTC[r], G, ulsch_harq->w[r], - (uint8_t *) &dummy_w[r][0], - ulsch_harq->e+r_offset, - ulsch_harq->C, - NSOFT, - 0, //Uplink - 1, - ulsch_harq->rvidx, - (ulsch_harq->round==0)?1:0, // clear - ulsch_harq->Qm, - 1, - r, - &E)==-1) { - LOG_E(PHY,"ulsch_decoding.c: Problem in rate matching\n"); - return(-1); - } - - stop_meas(&eNB->ulsch_rate_unmatching_stats); - r_offset += E; - start_meas(&eNB->ulsch_deinterleaving_stats); - sub_block_deinterleaving_turbo(4+Kr, - &ulsch_harq->d[r][96], - ulsch_harq->w[r]); - stop_meas(&eNB->ulsch_deinterleaving_stats); - - if (ulsch_harq->C == 1) - crc_type = CRC24_A; - else - crc_type = CRC24_B; - - start_meas(&eNB->ulsch_turbo_decoding_stats); - ret = tc(&ulsch_harq->d[r][96], - NULL, - ulsch_harq->c[r], - NULL, - Kr, - ulsch->max_turbo_iterations,//MAX_TURBO_ITERATIONS, - crc_type, - (r==0) ? ulsch_harq->F : 0, - &eNB->ulsch_tc_init_stats, - &eNB->ulsch_tc_alpha_stats, - &eNB->ulsch_tc_beta_stats, - &eNB->ulsch_tc_gamma_stats, - &eNB->ulsch_tc_ext_stats, - &eNB->ulsch_tc_intl1_stats, - &eNB->ulsch_tc_intl2_stats); - - // Reassembly of Transport block here - - if (ret != (1+ulsch->max_turbo_iterations)) { - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - - if (r==0) { - memcpy(ulsch_harq->b, - &ulsch_harq->c[0][(ulsch_harq->F>>3)], - Kr_bytes - (ulsch_harq->F>>3) - ((ulsch_harq->C>1)?3:0)); - offset = Kr_bytes - (ulsch_harq->F>>3) - ((ulsch_harq->C>1)?3:0); - } else { - memcpy(ulsch_harq->b+offset, - ulsch_harq->c[r], - Kr_bytes - ((ulsch_harq->C>1)?3:0)); - offset += (Kr_bytes- ((ulsch_harq->C>1)?3:0)); - } - } else { - break; - } - - stop_meas(&eNB->ulsch_turbo_decoding_stats); - //printf("/////////////////////////////////////////**************************loop for %d time in ulsch_decoding main\n",r); - } - - // wait for worker to finish - wait_on_busy_condition(&proc->mutex_td,&proc->cond_td,&proc->instance_cnt_td,"td thread"); - return( (ret>proc->tdp.ret) ? ret : proc->tdp.ret ); -} - -int ulsch_decoding_data(PHY_VARS_eNB *eNB,int UE_id,int harq_pid,int llr8_flag) { - unsigned int r,r_offset=0,Kr,Kr_bytes; - uint8_t crc_type; - int offset = 0; - int ret = 1; - int16_t dummy_w[MAX_NUM_ULSCH_SEGMENTS][3*(6144+64)]; - LTE_eNB_ULSCH_t *ulsch = eNB->ulsch[UE_id]; - LTE_UL_eNB_HARQ_t *ulsch_harq = ulsch->harq_processes[harq_pid]; - int G = ulsch_harq->G; - unsigned int E; - decoder_if_t *tc; - static int32_t pusch_rep_buffer[3*(6144+64)]; - int max_Ncb; - - if (llr8_flag == 0) - tc = *decoder16; - else - tc = *decoder8; - - if(ulsch_harq->repetition_number == 1) { - memset(pusch_rep_buffer,0,(sizeof(int32_t)*3*(6144+64))) ; // reset the buffer every new repetitions - } - - for (r=0; rC; r++) { - // printf("before subblock deinterleaving c[%d] = %p\n",r,ulsch_harq->c[r]); - // Get Turbo interleaver parameters - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - memset(&dummy_w[r][0],0,3*(6144+64)*sizeof(short)); - ulsch_harq->RTC[r] = generate_dummy_w(4+(Kr_bytes*8), - (uint8_t *)&dummy_w[r][0], - (r==0) ? ulsch_harq->F : 0); -#ifdef DEBUG_ULSCH_DECODING - printf("Rate Matching Segment %u (coded bits (G) %d,unpunctured/repeated bits %u, Q_m %d, Nl %d)...\n", - r, G, - Kr*3, - ulsch_harq->Qm, - ulsch_harq->Nl); -#endif - start_meas(&eNB->ulsch_rate_unmatching_stats); - - if (lte_rate_matching_turbo_rx(ulsch_harq->RTC[r], - G, - ulsch_harq->w[r], - (uint8_t *) &dummy_w[r][0], - ulsch_harq->e+r_offset, + (uint8_t *) &dummy_w[0], + ulsch_harq->eUL+rdata->r_offset, ulsch_harq->C, NSOFT, 0, //Uplink @@ -603,97 +241,132 @@ int ulsch_decoding_data(PHY_VARS_eNB *eNB,int UE_id,int harq_pid,int llr8_flag) r, &E)==-1) { LOG_E(PHY,"ulsch_decoding.c: Problem in rate matching\n"); - return(-1); + return; + } + stop_meas(&eNB->ulsch_rate_unmatching_stats); + int max_Ncb = 3*ulsch_harq->RTC[r]*32 ; + + if(ulsch_harq->repetition_number == 1) { + memset(ulsch_harq->pusch_rep_buffer[r],0,(sizeof(int32_t)*3*(6144+64))) ; // reset the buffer every new repetitions + } + if(ulsch_harq->total_number_of_repetitions > 1) { + if (ulsch_harq->rvidx==1) { + LOG_E(PHY,"Adding HARQ data for segment: %d\n", r); + // Store the result of HARQ combining in the last emtc repetitions of sequence 0,2,3,1 + for (int nn=0; nnpusch_rep_buffer[r][nn] += ulsch_harq->w[r][nn] ; } - stop_meas(&eNB->ulsch_rate_unmatching_stats); - max_Ncb = 3*ulsch_harq->RTC[r]*32 ; - - if(ulsch_harq->total_number_of_repetitions > 1) { - if (ulsch_harq->rvidx==1) { - // Store the result of HARQ combining in the last emtc repetitions of sequence 0,2,3,1 - for (int nn=0; nnw[r][nn] ; - } - } - - if (ulsch_harq->repetition_number == ulsch_harq->total_number_of_repetitions) { - for (int nn=0; nnw[r][nn] = pusch_rep_buffer[nn] ; - } - } - } - - r_offset += E; - start_meas(&eNB->ulsch_deinterleaving_stats); - sub_block_deinterleaving_turbo(4+Kr, - &ulsch_harq->d[r][96], - ulsch_harq->w[r]); - stop_meas(&eNB->ulsch_deinterleaving_stats); - - if (ulsch_harq->C == 1) - crc_type = CRC24_A; - else - crc_type = CRC24_B; - - start_meas(&eNB->ulsch_turbo_decoding_stats); - ret = tc(&ulsch_harq->d[r][96], - NULL, - ulsch_harq->c[r], - NULL, - Kr, - ulsch->max_turbo_iterations,//MAX_TURBO_ITERATIONS, - crc_type, - (r==0) ? ulsch_harq->F : 0, - &eNB->ulsch_tc_init_stats, - &eNB->ulsch_tc_alpha_stats, - &eNB->ulsch_tc_beta_stats, - &eNB->ulsch_tc_gamma_stats, - &eNB->ulsch_tc_ext_stats, - &eNB->ulsch_tc_intl1_stats, - &eNB->ulsch_tc_intl2_stats); - stop_meas(&eNB->ulsch_turbo_decoding_stats); - - // Reassembly of Transport block here - - if (ret != (1+ulsch->max_turbo_iterations)) { - if (rCminus) - Kr = ulsch_harq->Kminus; - else - Kr = ulsch_harq->Kplus; - - Kr_bytes = Kr>>3; - - if (r==0) { - memcpy(ulsch_harq->b, - &ulsch_harq->c[0][(ulsch_harq->F>>3)], - Kr_bytes - (ulsch_harq->F>>3) - ((ulsch_harq->C>1)?3:0)); - offset = Kr_bytes - (ulsch_harq->F>>3) - ((ulsch_harq->C>1)?3:0); - } else { - memcpy(ulsch_harq->b+offset, - ulsch_harq->c[r], - Kr_bytes - ((ulsch_harq->C>1)?3:0)); - offset += (Kr_bytes- ((ulsch_harq->C>1)?3:0)); - } - } else { - break; + if (ulsch_harq->repetition_number == ulsch_harq->total_number_of_repetitions) { + LOG_E(PHY,"Will use HARQ data sum up for segment: %d\n", r); + for (int nn=0; nnw[r][nn] = ulsch_harq->pusch_rep_buffer[r][nn] ; } } + int16_t soft_bits[3*8*6144+12+96] __attribute__((aligned(32))); + sub_block_deinterleaving_turbo(4+rdata->Kr, + soft_bits+96, + ulsch_harq->w[r]); + stop_meas(&eNB->ulsch_deinterleaving_stats); + rdata->decodeIterations = rdata->function( soft_bits+96, + NULL, + rdata->decoded_bytes, + NULL, + rdata->Kr, + rdata->maxIterations, + rdata->nbSegments == 1 ? CRC24_A: CRC24_B, + rdata->Fbits, + &eNB->ulsch_tc_init_stats, + &eNB->ulsch_tc_alpha_stats, + &eNB->ulsch_tc_beta_stats, + &eNB->ulsch_tc_gamma_stats, + &eNB->ulsch_tc_ext_stats, + &eNB->ulsch_tc_intl1_stats, + &eNB->ulsch_tc_intl2_stats); + stop_meas(&eNB->ulsch_turbo_decoding_stats); + +} +void *td_thread(void *param) { + + return(NULL); +} + +int ulsch_decoding_data(PHY_VARS_eNB *eNB, L1_rxtx_proc_t *proc, + int UE_id,int harq_pid,int llr8_flag) { + unsigned int r_offset=0; + int offset = 0; + LTE_eNB_ULSCH_t *ulsch = eNB->ulsch[UE_id]; + LTE_UL_eNB_HARQ_t *ulsch_harq = ulsch->harq_processes[harq_pid]; + int G = ulsch_harq->G; + unsigned int E; + int ret=0; + + decoder_if_t * td=llr8_flag == 0 ? + *decoder16 : *decoder8; + ulsch_harq->processedSegments=0; + + for (int r=0; rC; r++) { + // printf("before subblock deinterleaving c[%d] = %p\n",r,ulsch_harq->c[r]); + // Get Turbo interleaver parameters + unsigned int Kr= rCminus ? + ulsch_harq->Kminus :ulsch_harq->Kplus; + unsigned int Kr_bytes = Kr>>3; + +#ifdef DEBUG_ULSCH_DECODING + printf("Rate Matching Segment %d (coded bits (G) %d,unpunctured/repeated bits %u, Q_m %d, Nl %d, r_offset %u)...\n", + r, G, + Kr*3, + ulsch_harq->Qm, + ulsch_harq->Nl, r_offset); +#endif + int Gp=G/ulsch_harq->Qm; + int GpmodC = Gp%ulsch_harq->C; + + if (r < (ulsch_harq->C-(GpmodC))) + E = ulsch_harq->Qm * (Gp/ulsch_harq->C); + else + E = ulsch_harq->Qm * ((GpmodC==0?0:1) + (Gp/ulsch_harq->C)); + + if ( split73 == SPLIT73_DU ) { + sendFs6Ul(eNB, UE_id, harq_pid, r, ulsch_harq->eUL+r_offset, E*sizeof(int16_t), r_offset); + r_offset += E; + continue; + } + + union turboReqUnion id= {.s={ulsch->rnti,proc->frame_rx,proc->subframe_rx,0,0}}; + notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboDecode_t), id.p, proc->respDecode, processULSegment); + turboDecode_t * rdata=(turboDecode_t *) NotifiedFifoData(req); + + rdata->eNB=eNB; + rdata->frame=proc->frame_rx; + rdata->subframe=proc->subframe_rx; + rdata->UEid=UE_id; + rdata->harq_pid=harq_pid; + rdata->Kr=Kr; + rdata->maxIterations=eNB->ulsch[UE_id]->max_turbo_iterations; + rdata->ulsch_harq=ulsch_harq; + rdata->eNB=eNB; + rdata->nbSegments=ulsch_harq->C; + rdata->segment_r=r; + rdata->Fbits=(r==0) ? ulsch_harq->F : 0; + rdata->r_offset=r_offset; + rdata->offset=offset; + rdata->function=td; + int Fbytes=(r==0) ? rdata->Fbits>>3 : 0; + int sz=Kr_bytes - Fbytes - ((ulsch_harq->C>1)?3:0); + pushTpool(proc->threadPool,req); + proc->nbDecode++; + LOG_D(PHY,"Added a block to decode, in pipe: %d\n",proc->nbDecode); + r_offset+=E; + offset+=sz; + } return(ret); } -int ulsch_decoding_data_all(PHY_VARS_eNB *eNB,int UE_id,int harq_pid,int llr8_flag) { - int ret = 0; - /*if(get_thread_worker_conf() == WORKER_ENABLE) - { - ret = ulsch_decoding_data_2thread(eNB,UE_id,harq_pid,llr8_flag); - } - else*/ - { - ret = ulsch_decoding_data(eNB,UE_id,harq_pid,llr8_flag); - } - return ret; +int ulsch_decoding_data_all(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, + int UE_id,int harq_pid,int llr8_flag) { + return ulsch_decoding_data(eNB,proc,UE_id,harq_pid,llr8_flag); } static inline unsigned int lte_gold_unscram(unsigned int *x1, unsigned int *x2, unsigned char reset) __attribute__((always_inline)); @@ -767,7 +440,6 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, else harq_pid = subframe2harq_pid(frame_parms,proc->frame_rx,subframe); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING0+harq_pid,1); // x1 is set in lte_gold_generic x2 = ((uint32_t)ulsch->rnti<<14) + ((uint32_t)subframe<<9) + frame_parms->Nid_cell; //this is c_init in 36.211 Sec 6.3.1 ulsch_harq = ulsch->harq_processes[harq_pid]; @@ -779,8 +451,9 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, A = ulsch_harq->TBS; Q_m = ulsch_harq->Qm; G = nb_rb * (12 * Q_m) * ulsch_harq->Nsymb_pusch; + LOG_D(PHY, "PUSCH nb_rb %d Q_m %d ulsch_harq->Nsymb_pusch %d\n",nb_rb, Q_m, ulsch_harq->Nsymb_pusch); //#ifdef DEBUG_ULSCH_DECODING - LOG_D(PHY,"[PUSCH %d] Frame %d, Subframe %d: ulsch_decoding (Nid_cell %d, rnti %x, x2 %x): A %d, round %d, RV %d, O_r1 %d, O_RI %d, O_ACK %d, G %d, Q_m %d Nsymb_pusch %d nb_rb %d\n", + LOG_D(PHY,"[PUSCH harq %d] Frame %d, Subframe %d: ulsch_decoding (Nid_cell %d, rnti %x, x2 %x): TBS %d, round %d, RV %d, O_r1 %d, O_RI %d, O_ACK %d, G %d, Q_m %d Nsymb_pusch %d nb_rb %d\n", harq_pid, proc->frame_rx,subframe, frame_parms->Nid_cell,ulsch->rnti,x2, @@ -822,7 +495,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, } AssertFatal(sumKr>0, - "[eNB] ulsch_decoding.c: FATAL sumKr is 0! (Nid_cell %d, rnti %x, x2 %x): harq_pid %d round %d, RV %d, O_RI %d, O_ACK %d, G %d, subframe %d\n", + "[eNB] ulsch_decoding.c: FATAL sumKr is 0! (Nid_cell %d, rnti %x, x2 %x): harq_pid %d round %d, RV %d, O_RI %d, O_ACK %d, G %u, subframe %d\n", frame_parms->Nid_cell,ulsch->rnti,x2, harq_pid, ulsch_harq->round, @@ -833,6 +506,12 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, subframe); // Compute Q_ri Qprime = ulsch_harq->O_RI*ulsch_harq->Msc_initial*ulsch_harq->Nsymb_initial * ulsch->beta_offset_ri_times8; + LOG_D(PHY, "Qprime %d, O_RI %d, Msc %d, Nym %d beta %d\n", + Qprime, + ulsch_harq->O_RI, + ulsch_harq->Msc_initial, + ulsch_harq->Nsymb_initial, + ulsch->beta_offset_ri_times8); if (Qprime > 0 ) { if ((Qprime % (8*sumKr)) > 0) @@ -893,7 +572,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, G = G - Q_RI - Q_CQI; ulsch_harq->G = G; AssertFatal((int)G > 0, - "FATAL: ulsch_decoding.c G < 0 (%d) : Q_RI %d, Q_CQI %d\n",G,Q_RI,Q_CQI); + "FATAL: ulsch_decoding.c G < 0 (%u) : Q_RI %u, Q_CQI %u\n",G,Q_RI,Q_CQI); H = G + Q_CQI; Hprime = H/Q_m; // Demultiplexing/Deinterleaving of PUSCH/ACK/RI/CQI @@ -1209,8 +888,8 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, j2+=2; } - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; } break; @@ -1222,10 +901,10 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, j2+=4; } - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; } break; @@ -1237,12 +916,12 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, j2+=6; } - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; - ulsch_harq->e[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; + ulsch_harq->eUL[iprime++] = y[j2++]; } break; @@ -1280,7 +959,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB, */ int16_t *yp,*ep; - for (iprime=0,yp=&y[j2],ep=&ulsch_harq->e[0]; + for (iprime=0,yp=&y[j2],ep=&ulsch_harq->eUL[0]; iprimeO_ACK,ulsch_harq->o_ACK[0],ulsch_harq->o_ACK[1],ulsch_harq->o_ACK[2],ulsch_harq->o_ACK[3]); // Do ULSCH Decoding for data portion - ret = ulsch_decoding_data_all(eNB,UE_id,harq_pid,llr8_flag); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING0+harq_pid,0); + ret = ulsch_decoding_data_all(eNB,proc, UE_id,harq_pid,llr8_flag); return(ret); } diff --git a/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c b/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c index 1b0d7feaf5..f357e385f0 100644 --- a/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c +++ b/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c @@ -154,9 +154,9 @@ void lte_idft(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *z, uint16_t Msc_PUSCH) { switch (Msc_PUSCH) { case 12: - dft12((int16_t *)idft_in0,(int16_t *)idft_out0); - dft12((int16_t *)idft_in1,(int16_t *)idft_out1); - dft12((int16_t *)idft_in2,(int16_t *)idft_out2); + dft(DFT_12,(int16_t *)idft_in0,(int16_t *)idft_out0,0); + dft(DFT_12,(int16_t *)idft_in1,(int16_t *)idft_out1,0); + dft(DFT_12,(int16_t *)idft_in2,(int16_t *)idft_out2,0); #if defined(__x86_64__)||defined(__i386__) norm128 = _mm_set1_epi16(9459); #elif defined(__arm__) @@ -178,201 +178,201 @@ void lte_idft(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *z, uint16_t Msc_PUSCH) { break; case 24: - dft24(idft_in0,idft_out0,1); - dft24(idft_in1,idft_out1,1); - dft24(idft_in2,idft_out2,1); + dft(DFT_24,idft_in0,idft_out0,1); + dft(DFT_24,idft_in1,idft_out1,1); + dft(DFT_24,idft_in2,idft_out2,1); break; case 36: - dft36(idft_in0,idft_out0,1); - dft36(idft_in1,idft_out1,1); - dft36(idft_in2,idft_out2,1); + dft(DFT_36,idft_in0,idft_out0,1); + dft(DFT_36,idft_in1,idft_out1,1); + dft(DFT_36,idft_in2,idft_out2,1); break; case 48: - dft48(idft_in0,idft_out0,1); - dft48(idft_in1,idft_out1,1); - dft48(idft_in2,idft_out2,1); + dft(DFT_48,idft_in0,idft_out0,1); + dft(DFT_48,idft_in1,idft_out1,1); + dft(DFT_48,idft_in2,idft_out2,1); break; case 60: - dft60(idft_in0,idft_out0,1); - dft60(idft_in1,idft_out1,1); - dft60(idft_in2,idft_out2,1); + dft(DFT_60,idft_in0,idft_out0,1); + dft(DFT_60,idft_in1,idft_out1,1); + dft(DFT_60,idft_in2,idft_out2,1); break; case 72: - dft72(idft_in0,idft_out0,1); - dft72(idft_in1,idft_out1,1); - dft72(idft_in2,idft_out2,1); + dft(DFT_72,idft_in0,idft_out0,1); + dft(DFT_72,idft_in1,idft_out1,1); + dft(DFT_72,idft_in2,idft_out2,1); break; case 96: - dft96(idft_in0,idft_out0,1); - dft96(idft_in1,idft_out1,1); - dft96(idft_in2,idft_out2,1); + dft(DFT_96,idft_in0,idft_out0,1); + dft(DFT_96,idft_in1,idft_out1,1); + dft(DFT_96,idft_in2,idft_out2,1); break; case 108: - dft108(idft_in0,idft_out0,1); - dft108(idft_in1,idft_out1,1); - dft108(idft_in2,idft_out2,1); + dft(DFT_108,idft_in0,idft_out0,1); + dft(DFT_108,idft_in1,idft_out1,1); + dft(DFT_108,idft_in2,idft_out2,1); break; case 120: - dft120(idft_in0,idft_out0,1); - dft120(idft_in1,idft_out1,1); - dft120(idft_in2,idft_out2,1); + dft(DFT_120,idft_in0,idft_out0,1); + dft(DFT_120,idft_in1,idft_out1,1); + dft(DFT_120,idft_in2,idft_out2,1); break; case 144: - dft144(idft_in0,idft_out0,1); - dft144(idft_in1,idft_out1,1); - dft144(idft_in2,idft_out2,1); + dft(DFT_144,idft_in0,idft_out0,1); + dft(DFT_144,idft_in1,idft_out1,1); + dft(DFT_144,idft_in2,idft_out2,1); break; case 180: - dft180(idft_in0,idft_out0,1); - dft180(idft_in1,idft_out1,1); - dft180(idft_in2,idft_out2,1); + dft(DFT_180,idft_in0,idft_out0,1); + dft(DFT_180,idft_in1,idft_out1,1); + dft(DFT_180,idft_in2,idft_out2,1); break; case 192: - dft192(idft_in0,idft_out0,1); - dft192(idft_in1,idft_out1,1); - dft192(idft_in2,idft_out2,1); + dft(DFT_192,idft_in0,idft_out0,1); + dft(DFT_192,idft_in1,idft_out1,1); + dft(DFT_192,idft_in2,idft_out2,1); break; case 216: - dft216(idft_in0,idft_out0,1); - dft216(idft_in1,idft_out1,1); - dft216(idft_in2,idft_out2,1); + dft(DFT_216,idft_in0,idft_out0,1); + dft(DFT_216,idft_in1,idft_out1,1); + dft(DFT_216,idft_in2,idft_out2,1); break; case 240: - dft240(idft_in0,idft_out0,1); - dft240(idft_in1,idft_out1,1); - dft240(idft_in2,idft_out2,1); + dft(DFT_240,idft_in0,idft_out0,1); + dft(DFT_240,idft_in1,idft_out1,1); + dft(DFT_240,idft_in2,idft_out2,1); break; case 288: - dft288(idft_in0,idft_out0,1); - dft288(idft_in1,idft_out1,1); - dft288(idft_in2,idft_out2,1); + dft(DFT_288,idft_in0,idft_out0,1); + dft(DFT_288,idft_in1,idft_out1,1); + dft(DFT_288,idft_in2,idft_out2,1); break; case 300: - dft300(idft_in0,idft_out0,1); - dft300(idft_in1,idft_out1,1); - dft300(idft_in2,idft_out2,1); + dft(DFT_300,idft_in0,idft_out0,1); + dft(DFT_300,idft_in1,idft_out1,1); + dft(DFT_300,idft_in2,idft_out2,1); break; case 324: - dft324((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft324((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft324((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_324,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_324,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_324,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 360: - dft360((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft360((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft360((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_360,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_360,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_360,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 384: - dft384((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft384((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft384((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_384,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_384,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_384,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 432: - dft432((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft432((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft432((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_432,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_432,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_432,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 480: - dft480((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft480((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft480((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_480,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_480,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_480,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 540: - dft540((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft540((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft540((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_540,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_540,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_540,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 576: - dft576((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft576((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft576((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_576,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_576,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_576,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 600: - dft600((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft600((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft600((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_600,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_600,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_600,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 648: - dft648((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft648((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft648((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_648,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_648,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_648,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 720: - dft720((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft720((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft720((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_720,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_720,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_720,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 768: - dft768((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft768((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft768((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_768,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_768,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_768,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 864: - dft864((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft864((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft864((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_864,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_864,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_864,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 900: - dft900((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft900((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft900((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_900,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_900,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_900,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 960: - dft960((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft960((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft960((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_960,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_960,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_960,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 972: - dft972((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft972((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft972((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_972,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_972,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_972,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 1080: - dft1080((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft1080((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft1080((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_1080,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_1080,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_1080,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 1152: - dft1152((int16_t *)idft_in0,(int16_t *)idft_out0,1); - dft1152((int16_t *)idft_in1,(int16_t *)idft_out1,1); - dft1152((int16_t *)idft_in2,(int16_t *)idft_out2,1); + dft(DFT_1152,(int16_t *)idft_in0,(int16_t *)idft_out0,1); + dft(DFT_1152,(int16_t *)idft_in1,(int16_t *)idft_out1,1); + dft(DFT_1152,(int16_t *)idft_in2,(int16_t *)idft_out2,1); break; case 1200: - dft1200(idft_in0,idft_out0,1); - dft1200(idft_in1,idft_out1,1); - dft1200(idft_in2,idft_out2,1); + dft(DFT_1200,idft_in0,idft_out0,1); + dft(DFT_1200,idft_in1,idft_out1,1); + dft(DFT_1200,idft_in2,idft_out2,1); break; default: @@ -780,7 +780,6 @@ void ulsch_channel_compensation(int32_t **rxdataF_ext, #endif for (rb=0; rbharq_processes[harq_pid]->RTC[r], G, //G dlsch->harq_processes[harq_pid]->w[r], - dlsch->harq_processes[harq_pid]->e+r_offset, + dlsch->harq_processes[harq_pid]->eDL+r_offset, dlsch->harq_processes[harq_pid]->C, // C dlsch->Nsoft, // Nsoft, dlsch->Mdlharq, diff --git a/openair1/PHY/LTE_UE_TRANSPORT/initial_sync.c b/openair1/PHY/LTE_UE_TRANSPORT/initial_sync.c index afa46de820..ba904629a1 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/initial_sync.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/initial_sync.c @@ -38,7 +38,6 @@ #include "PHY/MODULATION/modulation_UE.h" #include "PHY/LTE_ESTIMATION/lte_estimation.h" #include "PHY/LTE_REFSIG/lte_refsig.h" -#include "openair2/LAYER2/MAC/mac_proto.h" #include "common_lib.h" #include "PHY/INIT/phy_init.h" diff --git a/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c b/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c index 49fa484c26..e4083863f0 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c @@ -65,7 +65,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 uint16_t *prach_root_sequence_map; uint16_t preamble_offset,preamble_shift; uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar; - uint16_t d_start,numshift; + uint16_t d_start=-1,numshift; uint8_t prach_fmt = get_prach_fmt(prach_ConfigIndex,frame_type); //uint8_t Nsp=2; //uint8_t f_ra,t1_ra; @@ -338,11 +338,11 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 switch (ue->frame_parms.N_RB_UL) { case 6: if (prach_fmt == 4) { - idft256(prachF,prach2,1); + idft(IDFT_256,prachF,prach2,1); memmove( prach, prach+512, Ncp<<2 ); prach_len = 256+Ncp; } else { - idft1536(prachF,prach2,1); + idft(IDFT_1536,prachF,prach2,1); memmove( prach, prach+3072, Ncp<<2 ); prach_len = 1536+Ncp; @@ -356,12 +356,12 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 case 15: if (prach_fmt == 4) { - idft512(prachF,prach2,1); + idft(IDFT_512,prachF,prach2,1); //TODO: account for repeated format in dft output memmove( prach, prach+1024, Ncp<<2 ); prach_len = 512+Ncp; } else { - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); memmove( prach, prach+6144, Ncp<<2 ); prach_len = 3072+Ncp; @@ -376,11 +376,11 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 case 25: default: if (prach_fmt == 4) { - idft1024(prachF,prach2,1); + idft(IDFT_1024,prachF,prach2,1); memmove( prach, prach+2048, Ncp<<2 ); prach_len = 1024+Ncp; } else { - idft6144(prachF,prach2,1); + idft(IDFT_6144,prachF,prach2,1); /*for (i=0;i<6144*2;i++) prach2[i]<<=1;*/ memmove( prach, prach+12288, Ncp<<2 ); @@ -396,11 +396,11 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 case 50: if (prach_fmt == 4) { - idft2048(prachF,prach2,1); + idft(IDFT_2048,prachF,prach2,1); memmove( prach, prach+4096, Ncp<<2 ); prach_len = 2048+Ncp; } else { - idft12288(prachF,prach2,1); + idft(IDFT_12288,prachF,prach2,1); memmove( prach, prach+24576, Ncp<<2 ); prach_len = 12288+Ncp; @@ -414,12 +414,12 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 case 75: if (prach_fmt == 4) { - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); //TODO: account for repeated format in dft output memmove( prach, prach+6144, Ncp<<2 ); prach_len = 3072+Ncp; } else { - idft18432(prachF,prach2,1); + idft(IDFT_18432,prachF,prach2,1); memmove( prach, prach+36864, Ncp<<2 ); prach_len = 18432+Ncp; @@ -434,11 +434,11 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 case 100: if (ue->frame_parms.threequarter_fs == 0) { if (prach_fmt == 4) { - idft4096(prachF,prach2,1); + idft(IDFT_4096,prachF,prach2,1); memmove( prach, prach+8192, Ncp<<2 ); prach_len = 4096+Ncp; } else { - idft24576(prachF,prach2,1); + idft(IDFT_24576,prachF,prach2,1); memmove( prach, prach+49152, Ncp<<2 ); prach_len = 24576+Ncp; @@ -449,12 +449,12 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 } } else { if (prach_fmt == 4) { - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); //TODO: account for repeated format in dft output memmove( prach, prach+6144, Ncp<<2 ); prach_len = 3072+Ncp; } else { - idft18432(prachF,prach2,1); + idft(IDFT_18432,prachF,prach2,1); memmove( prach, prach+36864, Ncp<<2 ); prach_len = 18432+Ncp; printf("Generated prach for 100 PRB, 3/4 sampling\n"); diff --git a/openair1/PHY/LTE_UE_TRANSPORT/sldch.c b/openair1/PHY/LTE_UE_TRANSPORT/sldch.c index 9c9d36c974..8769d5f81b 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/sldch.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/sldch.c @@ -29,8 +29,6 @@ * \note * \warning */ -#ifndef __LTE_TRANSPORT_SLSS__C__ -#define __LTE_TRANSPORT_SLSS__C__ #include "PHY/defs_UE.h" extern int multicast_link_write_sock(int groupP, char *dataP, uint32_t sizeP); @@ -63,4 +61,3 @@ void generate_sldch(PHY_VARS_UE *ue,SLDCH_t *sldch,int frame_tx,int subframe_tx) } -#endif diff --git a/openair1/PHY/LTE_UE_TRANSPORT/slsch.c b/openair1/PHY/LTE_UE_TRANSPORT/slsch.c index e51e33626d..e4e94a232d 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/slsch.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/slsch.c @@ -29,8 +29,6 @@ * \note * \warning */ -#ifndef __LTE_TRANSPORT_SLSS__C__ -#define __LTE_TRANSPORT_SLSS__C__ #include "PHY/defs_UE.h" extern int @@ -66,5 +64,3 @@ void generate_slsch(PHY_VARS_UE *ue,SLSCH_t *slsch,int frame_tx,int subframe_tx) } } - -#endif diff --git a/openair1/PHY/LTE_UE_TRANSPORT/slss.c b/openair1/PHY/LTE_UE_TRANSPORT/slss.c index 18bc5a28de..3cd1c1acb0 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/slss.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/slss.c @@ -29,8 +29,6 @@ * \note * \warning */ -#ifndef __LTE_TRANSPORT_SLSS__C__ -#define __LTE_TRANSPORT_SLSS__C__ #include "PHY/defs_UE.h" @@ -39,5 +37,3 @@ void generate_slss(PHY_VARS_UE *ue,SLSS_t *slss,int frame_tx,int subframe_tx) { AssertFatal(1==0,"Should get here yet for UE %d\n",ue->Mod_id); } - -#endif diff --git a/openair1/PHY/LTE_UE_TRANSPORT/ulsch_coding.c b/openair1/PHY/LTE_UE_TRANSPORT/ulsch_coding.c index cc1f762e70..de1c3891da 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/ulsch_coding.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/ulsch_coding.c @@ -446,6 +446,13 @@ uint32_t ulsch_encoding(uint8_t *a, Qprime = (ulsch->O + L) * ulsch->harq_processes[harq_pid]->Msc_initial*ulsch->harq_processes[harq_pid]->Nsymb_initial * ulsch->beta_offset_cqi_times8; else Qprime = 0; + LOG_D(PHY,"Qprime %d, O_RI %d + %d, Msc %d, Nym %d beta %d\n", + Qprime, + ulsch->O, L, + ulsch->harq_processes[harq_pid]->Msc_initial, + ulsch->harq_processes[harq_pid]->Nsymb_initial, + ulsch->beta_offset_cqi_times8); + if (Qprime > 0) { if ((Qprime % (8*sumKr)) > 0) @@ -455,7 +462,7 @@ uint32_t ulsch_encoding(uint8_t *a, } G = ulsch->harq_processes[harq_pid]->nb_rb * (12 * Q_m) * (ulsch->Nsymb_pusch); - + LOG_D(PHY,"G: rb %d * ( 12 * Qm %d ) * nsymb %d, Qprime %d, O_RI %d\n", ulsch->harq_processes[harq_pid]->nb_rb, Q_m, ulsch->Nsymb_pusch, Qprime, ulsch->O_RI); if (Qprime > (G - ulsch->O_RI)) Qprime = G - ulsch->O_RI; @@ -465,6 +472,7 @@ uint32_t ulsch_encoding(uint8_t *a, G = G - Q_RI - Q_CQI; + LOG_D(PHY,"new G: %d, Q_RI %d Q_CQI %d\n", G , Q_RI , Q_CQI); ulsch->harq_processes[harq_pid]->G = G; /* diff --git a/openair1/PHY/LTE_UE_TRANSPORT/ulsch_modulation.c b/openair1/PHY/LTE_UE_TRANSPORT/ulsch_modulation.c index a9878b4eae..b08fe30248 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/ulsch_modulation.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/ulsch_modulation.c @@ -104,9 +104,9 @@ void dft_lte(int32_t *z,int32_t *d, int32_t Msc_PUSCH, uint8_t Nsymb) switch (Msc_PUSCH) { case 12: - dft12((int16_t *)dft_in0,(int16_t *)dft_out0); - dft12((int16_t *)dft_in1,(int16_t *)dft_out1); - dft12((int16_t *)dft_in2,(int16_t *)dft_out2); + dft(DFT_12,(int16_t *)dft_in0,(int16_t *)dft_out0,0); + dft(DFT_12,(int16_t *)dft_in1,(int16_t *)dft_out1,0); + dft(DFT_12,(int16_t *)dft_in2,(int16_t *)dft_out2,0); /* dft12f(&((__m128i *)dft_in0)[0],&((__m128i *)dft_in0)[1],&((__m128i *)dft_in0)[2],&((__m128i *)dft_in0)[3],&((__m128i *)dft_in0)[4],&((__m128i *)dft_in0)[5],&((__m128i *)dft_in0)[6],&((__m128i *)dft_in0)[7],&((__m128i *)dft_in0)[8],&((__m128i *)dft_in0)[9],&((__m128i *)dft_in0)[10],&((__m128i *)dft_in0)[11], @@ -138,201 +138,201 @@ void dft_lte(int32_t *z,int32_t *d, int32_t Msc_PUSCH, uint8_t Nsymb) break; case 24: - dft24((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft24((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft24((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_24,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_24,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_24,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 36: - dft36((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft36((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft36((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_36,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_36,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_36,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 48: - dft48((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft48((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft48((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_48,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_48,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_48,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 60: - dft60((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft60((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft60((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_60,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_60,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_60,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 72: - dft72((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft72((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft72((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_72,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_72,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_72,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 96: - dft96((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft96((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft96((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_96,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_96,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_96,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 108: - dft108((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft108((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft108((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_108,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_108,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_108,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 120: - dft120((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft120((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft120((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_120,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_120,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_120,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 144: - dft144((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft144((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft144((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_144,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_144,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_144,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 180: - dft180((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft180((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft180((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_180,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_180,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_180,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 192: - dft192((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft192((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft192((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_192,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_192,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_192,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 216: - dft216((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft216((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft216((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_216,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_216,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_216,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 240: - dft240((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft240((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft240((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_240,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_240,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_240,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 288: - dft288((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft288((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft288((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_288,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_288,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_288,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 300: - dft300((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft300((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft300((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_300,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_300,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_300,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 324: - dft324((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft324((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft324((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_324,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_324,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_324,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 360: - dft360((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft360((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft360((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_360,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_360,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_360,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 384: - dft384((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft384((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft384((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_384,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_384,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_384,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 432: - dft432((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft432((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft432((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_432,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_432,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_432,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 480: - dft480((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft480((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft480((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_480,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_480,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_480,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 540: - dft540((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft540((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft540((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_540,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_540,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_540,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 576: - dft576((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft576((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft576((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_576,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_576,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_576,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 600: - dft600((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft600((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft600((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_600,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_600,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_600,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 648: - dft648((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft648((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft648((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_648,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_648,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_648,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 720: - dft720((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft720((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft720((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_720,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_720,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_720,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 768: - dft768((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft768((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft768((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_768,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_768,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_768,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 864: - dft864((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft864((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft864((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_864,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_864,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_864,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 900: - dft900((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft900((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft900((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_900,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_900,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_900,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 960: - dft960((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft960((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft960((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_960,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_960,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_960,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 972: - dft972((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft972((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft972((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_972,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_972,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_972,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 1080: - dft1080((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft1080((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft1080((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_1080,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_1080,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_1080,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 1152: - dft1152((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft1152((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft1152((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_1152,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_1152,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_1152,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; case 1200: - dft1200((int16_t*)dft_in0,(int16_t*)dft_out0,1); - dft1200((int16_t*)dft_in1,(int16_t*)dft_out1,1); - dft1200((int16_t*)dft_in2,(int16_t*)dft_out2,1); + dft(DFT_1200,(int16_t*)dft_in0,(int16_t*)dft_out0,1); + dft(DFT_1200,(int16_t*)dft_in1,(int16_t*)dft_out1,1); + dft(DFT_1200,(int16_t*)dft_in2,(int16_t*)dft_out2,1); break; } diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index 5c8fce3c38..b27b692e66 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -242,7 +242,7 @@ void nr_dft(int32_t *z, int32_t *d, uint32_t Msc_PUSCH) switch (Msc_PUSCH) { case 12: - dft12((int16_t *)dft_in0, (int16_t *)dft_out0); + dft(DFT_12,(int16_t *)dft_in0, (int16_t *)dft_out0,0); #if defined(__x86_64__) || defined(__i386__) norm128 = _mm_set1_epi16(9459); @@ -260,135 +260,135 @@ void nr_dft(int32_t *z, int32_t *d, uint32_t Msc_PUSCH) break; case 24: - dft24((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_24,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 36: - dft36((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_36,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 48: - dft48((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_48,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 60: - dft60((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_60,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 72: - dft72((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_72,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 96: - dft96((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_96,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 108: - dft108((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_108,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 120: - dft120((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_120,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 144: - dft144((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_144,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 180: - dft180((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_180,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 192: - dft192((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_192,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 216: - dft216((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_216,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 240: - dft240((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_240,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 288: - dft288((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_288,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 300: - dft300((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_300,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 324: - dft324((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_324,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 360: - dft360((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_360,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 384: - dft384((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_384,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 432: - dft432((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_432,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 480: - dft480((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_480,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 540: - dft540((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_540,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 576: - dft576((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_576,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 600: - dft600((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_600,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 648: - dft648((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_648,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 720: - dft720((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_720,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 768: - dft768((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_768,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 864: - dft864((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_864,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 900: - dft900((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_900,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 960: - dft960((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_960,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 972: - dft972((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_960,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 1080: - dft1080((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_1080,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 1152: - dft1152((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_1152,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; case 1200: - dft1200((int16_t*)dft_in0, (int16_t*)dft_out0, 1); + dft(DFT_1200,(int16_t*)dft_in0, (int16_t*)dft_out0, 1); break; } diff --git a/openair1/PHY/MODULATION/ofdm_mod.c b/openair1/PHY/MODULATION/ofdm_mod.c index cbeeca1327..855e649cc5 100644 --- a/openair1/PHY/MODULATION/ofdm_mod.c +++ b/openair1/PHY/MODULATION/ofdm_mod.c @@ -95,41 +95,41 @@ void PHY_ofdm_mod(int *input, /// pointer to complex input volatile int *output_ptr=(int*)0; int *temp_ptr=(int*)0; - void (*idft)(int16_t *,int16_t *, int); + idft_size_idx_t idftsize; switch (fftsize) { case 128: - idft = idft128; + idftsize = IDFT_128; break; case 256: - idft = idft256; + idftsize = IDFT_256; break; case 512: - idft = idft512; + idftsize = IDFT_512; break; case 1024: - idft = idft1024; + idftsize = IDFT_1024; break; case 1536: - idft = idft1536; + idftsize = IDFT_1536; break; case 2048: - idft = idft2048; + idftsize = IDFT_2048; break; case 3072: - idft = idft3072; + idftsize = IDFT_3072; break; case 4096: - idft = idft4096; + idftsize = IDFT_4096; break; default: - idft = idft512; + idftsize = IDFT_512; break; } @@ -148,12 +148,12 @@ void PHY_ofdm_mod(int *input, /// pointer to complex input #ifndef __AVX2__ // handle 128-bit alignment for 128-bit SIMD (SSE4,NEON,AltiVEC) - idft((int16_t *)&input[i*fftsize], + idft(idftsize,(int16_t *)&input[i*fftsize], (fftsize==128) ? (int16_t *)temp : (int16_t *)&output[(i*fftsize) + ((1+i)*nb_prefix_samples)], 1); #else // on AVX2 need 256-bit alignment - idft((int16_t *)&input[i*fftsize], + idft(idftsize,(int16_t *)&input[i*fftsize], (int16_t *)temp, 1); diff --git a/openair1/PHY/MODULATION/slot_fep.c b/openair1/PHY/MODULATION/slot_fep.c index 163ebac65f..8f41735f10 100644 --- a/openair1/PHY/MODULATION/slot_fep.c +++ b/openair1/PHY/MODULATION/slot_fep.c @@ -49,36 +49,36 @@ int slot_fep(PHY_VARS_UE *ue, unsigned char harq_pid = dlsch_ue[0]->current_harq_pid; LTE_DL_UE_HARQ_t *dlsch0_harq = dlsch_ue[0]->harq_processes[harq_pid]; int uespec_pilot[9][1200];*/ - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsizeidx; int tmp_dft_in[2048] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft128; - break; - - case 256: - dft = dft256; - break; - - case 512: - dft = dft512; - break; - - case 1024: - dft = dft1024; - break; - - case 1536: - dft = dft1536; - break; - - case 2048: - dft = dft2048; + dftsizeidx = DFT_128; + break; + + case 256: + dftsizeidx = DFT_256; + break; + + case 512: + dftsizeidx = DFT_512; + break; + + case 1024: + dftsizeidx = DFT_1024; + break; + + case 1536: + dftsizeidx = DFT_1536; + break; + + case 2048: + dftsizeidx = DFT_2048; break; default: - dft = dft512; + dftsizeidx = DFT_512; break; } @@ -118,13 +118,13 @@ int slot_fep(PHY_VARS_UE *ue, memcpy((void *)tmp_dft_in, (void *)&common_vars->rxdata[aa][rx_offset % frame_length_samples], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsizeidx,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly #if UE_TIMING_TRACE start_meas(&ue->rx_dft_stats); #endif - dft((int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); #if UE_TIMING_TRACE stop_meas(&ue->rx_dft_stats); @@ -153,10 +153,10 @@ int slot_fep(PHY_VARS_UE *ue, memcpy((void *)tmp_dft_in, (void *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsizeidx,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly - dft((int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } @@ -247,36 +247,36 @@ int front_end_fft(PHY_VARS_UE *ue, unsigned char harq_pid = dlsch_ue[0]->current_harq_pid; LTE_DL_UE_HARQ_t *dlsch0_harq = dlsch_ue[0]->harq_processes[harq_pid]; int uespec_pilot[9][1200];*/ - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsizeidx; int tmp_dft_in[2048] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft128; - break; - - case 256: - dft = dft256; - break; - - case 512: - dft = dft512; - break; - - case 1024: - dft = dft1024; - break; - - case 1536: - dft = dft1536; - break; - - case 2048: - dft = dft2048; - break; - - default: - dft = dft512; + dftsizeidx = DFT_128; + break; + + case 256: + dftsizeidx = DFT_256; + break; + + case 512: + dftsizeidx = DFT_512; + break; + + case 1024: + dftsizeidx = DFT_1024; + break; + + case 1536: + dftsizeidx = DFT_1536; + break; + + case 2048: + dftsizeidx = DFT_2048; + break; + + default: + dftsizeidx = DFT_512; break; } @@ -319,11 +319,11 @@ int front_end_fft(PHY_VARS_UE *ue, memcpy((void *)tmp_dft_in, (void *)&common_vars->rxdata[aa][rx_offset % frame_length_samples], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsizeidx,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[threadId].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly start_meas(&ue->rx_dft_stats); - dft((int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[threadId].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); stop_meas(&ue->rx_dft_stats); } @@ -349,10 +349,10 @@ int front_end_fft(PHY_VARS_UE *ue, memcpy((void *)tmp_dft_in, (void *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsizeidx,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[threadId].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly - dft((int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[threadId].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } diff --git a/openair1/PHY/MODULATION/slot_fep_mbsfn.c b/openair1/PHY/MODULATION/slot_fep_mbsfn.c index 38d78119e3..6036745029 100644 --- a/openair1/PHY/MODULATION/slot_fep_mbsfn.c +++ b/openair1/PHY/MODULATION/slot_fep_mbsfn.c @@ -42,35 +42,35 @@ int slot_fep_mbsfn(PHY_VARS_UE *ue, unsigned int subframe_offset; // int i; unsigned int frame_length_samples = frame_parms->samples_per_tti * 10; - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsizeidx; switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft128; - break; - - case 256: - dft = dft256; - break; - - case 512: - dft = dft512; - break; - - case 1024: - dft = dft1024; - break; - - case 1536: - dft = dft1536; - break; - - case 2048: - dft = dft2048; - break; - - default: - dft = dft512; + dftsizeidx = DFT_128; + break; + + case 256: + dftsizeidx = DFT_256; + break; + + case 512: + dftsizeidx = DFT_512; + break; + + case 1024: + dftsizeidx = DFT_1024; + break; + + case 1536: + dftsizeidx = DFT_1536; + break; + + case 2048: + dftsizeidx = DFT_2048; + break; + + default: + dftsizeidx = DFT_512; break; } @@ -110,7 +110,7 @@ int slot_fep_mbsfn(PHY_VARS_UE *ue, #if UE_TIMING_TRACE start_meas(&ue->rx_dft_stats); #endif - dft((int16_t *)&common_vars->rxdata[aa][(sample_offset + + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(sample_offset + nb_prefix_samples0 + subframe_offset - SOFFSET) % frame_length_samples], @@ -131,7 +131,7 @@ int slot_fep_mbsfn(PHY_VARS_UE *ue, #if UE_TIMING_TRACE start_meas(&ue->rx_dft_stats); #endif - dft((int16_t *)&common_vars->rxdata[aa][(sample_offset + + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(sample_offset + (frame_parms->ofdm_symbol_size+nb_prefix_samples0+nb_prefix_samples) + (frame_parms->ofdm_symbol_size+nb_prefix_samples)*(l-1) + subframe_offset- @@ -208,43 +208,43 @@ int slot_fep_mbsfn_khz_1dot25(PHY_VARS_UE *ue, int ofdm_symbol_size; unsigned int subframe_offset; unsigned int frame_length_samples = frame_parms->samples_per_tti * 10; - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsizeidx; AssertFatal(frame_parms->frame_type == FDD, "Frame is TDD!\n"); switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft1536; + dftsizeidx = DFT_1536; ofdm_symbol_size=1536; nb_prefix_samples=384; break; case 256: AssertFatal(1==0,"FeMBMS dft3072 not implemented\n"); - dft = dft3072; + dftsizeidx = DFT_3072; ofdm_symbol_size=3072; nb_prefix_samples=768; break; case 512: - dft = dft6144; + dftsizeidx = DFT_6144; nb_prefix_samples=1536; ofdm_symbol_size=6144; break; case 1024: - dft = dft12288; + dftsizeidx = DFT_12288; nb_prefix_samples=3072; ofdm_symbol_size=12288; break; case 1536: - dft = dft18432; + dftsizeidx = DFT_18432; nb_prefix_samples=4608; ofdm_symbol_size=18432; break; case 2048: - dft = dft24576; + dftsizeidx = DFT_24576; nb_prefix_samples=6144; ofdm_symbol_size=24576; break; @@ -265,7 +265,7 @@ int slot_fep_mbsfn_khz_1dot25(PHY_VARS_UE *ue, #if UE_TIMING_TRACE start_meas(&ue->rx_dft_stats); #endif - dft((int16_t *)&common_vars->rxdata[aa][(sample_offset + + dft(dftsizeidx,(int16_t *)&common_vars->rxdata[aa][(sample_offset + nb_prefix_samples + subframe_offset - SOFFSET) % frame_length_samples], diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index f2e5d24bad..7fe8437c4e 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -25,6 +25,7 @@ #include "nr_modulation.h" #include "PHY/LTE_ESTIMATION/lte_estimation.h" #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" +#include //#define DEBUG_FEP @@ -62,44 +63,44 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, unsigned int rx_offset; - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsize; int tmp_dft_in[8192] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft128; + dftsize = DFT_128; break; case 256: - dft = dft256; + dftsize = DFT_256; break; case 512: - dft = dft512; + dftsize = DFT_512; break; case 1024: - dft = dft1024; + dftsize = DFT_1024; break; case 1536: - dft = dft1536; + dftsize = DFT_1536; break; case 2048: - dft = dft2048; + dftsize = DFT_2048; break; case 3072: - dft = dft3072; + dftsize = DFT_3072; break; case 4096: - dft = dft4096; + dftsize = DFT_4096; break; case 8192: - dft = dft8192; + dftsize = DFT_8192; break; default: @@ -155,14 +156,14 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, memcpy((void *)tmp_dft_in, (void *) &common_vars->rxdata[aa][rx_offset % frame_length_samples], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsize,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly #if UE_TIMING_TRACE start_meas(&ue->rx_dft_stats); #endif - dft((int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); #if UE_TIMING_TRACE stop_meas(&ue->rx_dft_stats); @@ -183,11 +184,11 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, memcpy((void *)tmp_dft_in, (void *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsize,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly - dft((int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } #if UE_TIMING_TRACE @@ -237,44 +238,44 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, unsigned int rx_offset; - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsize; int tmp_dft_in[8192] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft128; + dftsize = DFT_128; break; case 256: - dft = dft256; + dftsize = DFT_256; break; case 512: - dft = dft512; + dftsize = DFT_512; break; case 1024: - dft = dft1024; + dftsize = DFT_1024; break; case 1536: - dft = dft1536; + dftsize = DFT_1536; break; case 2048: - dft = dft2048; + dftsize = DFT_2048; break; case 3072: - dft = dft3072; + dftsize = DFT_3072; break; case 4096: - dft = dft4096; + dftsize = DFT_4096; break; case 8192: - dft = dft8192; + dftsize = DFT_8192; break; default: @@ -330,14 +331,15 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, memcpy((void *)tmp_dft_in, (void *) &common_vars->rxdata[aa][rx_offset], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsize,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly #if UE_TIMING_TRACE start_meas(&ue->rx_dft_stats); #endif - dft((int16_t *) &common_vars->rxdata[aa][rx_offset], + + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); #if UE_TIMING_TRACE stop_meas(&ue->rx_dft_stats); @@ -358,11 +360,10 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, memcpy((void *)tmp_dft_in, (void *) &common_vars->rxdata[aa][rx_offset], frame_parms->ofdm_symbol_size*sizeof(int)); - dft((int16_t *)tmp_dft_in, + dft(dftsize,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly - - dft((int16_t *) &common_vars->rxdata[aa][rx_offset], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } #if UE_TIMING_TRACE @@ -400,43 +401,43 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, unsigned int nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples); unsigned int nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples0); - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsize; switch (frame_parms->ofdm_symbol_size) { case 128: - dft = dft128; + dftsize = DFT_128; break; case 256: - dft = dft256; + dftsize = DFT_256; break; case 512: - dft = dft512; + dftsize = DFT_512; break; case 1024: - dft = dft1024; + dftsize = DFT_1024; break; case 1536: - dft = dft1536; + dftsize = DFT_1536; break; case 2048: - dft = dft2048; + dftsize = DFT_2048; break; case 4096: - dft = dft4096; + dftsize = DFT_4096; break; case 8192: - dft = dft8192; + dftsize = DFT_8192; break; default: - dft = dft512; + dftsize = DFT_512; break; } @@ -448,7 +449,7 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, else rxdata_offset = slot_offset + nb_prefix_samples0 + (symbol * (frame_parms->ofdm_symbol_size + nb_prefix_samples)) - SOFFSET; - dft((int16_t *)&rxdata[rxdata_offset], + dft(dftsize,(int16_t *)&rxdata[rxdata_offset], (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); return(0); diff --git a/openair1/PHY/MODULATION/slot_fep_ul.c b/openair1/PHY/MODULATION/slot_fep_ul.c index 3ac8537c69..746f8dbc0e 100644 --- a/openair1/PHY/MODULATION/slot_fep_ul.c +++ b/openair1/PHY/MODULATION/slot_fep_ul.c @@ -44,7 +44,7 @@ int slot_fep_ul(RU_t *ru, unsigned int slot_offset; - void (*dft)(int16_t *,int16_t *, int); + dft_size_idx_t dftsize; int tmp_dft_in[2048] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs unsigned int frame_length_samples = fp->samples_per_tti * 10; @@ -52,31 +52,31 @@ int slot_fep_ul(RU_t *ru, switch (fp->ofdm_symbol_size) { case 128: - dft = dft128; + dftsize = DFT_128; break; case 256: - dft = dft256; + dftsize = DFT_256; break; case 512: - dft = dft512; + dftsize = DFT_512; break; case 1024: - dft = dft1024; + dftsize = DFT_1024; break; case 1536: - dft = dft1536; + dftsize = DFT_1536; break; case 2048: - dft = dft2048; + dftsize = DFT_2048; break; default: - dft = dft512; + dftsize = DFT_512; break; } @@ -109,7 +109,7 @@ int slot_fep_ul(RU_t *ru, LOG_D(PHY,"slot_fep: symbol 0 %d dB\n", dB_fixed(signal_energy(&common->rxdata_7_5kHz[aa][rx_offset],fp->ofdm_symbol_size))); #endif - dft( (int16_t *)&common->rxdata_7_5kHz[aa][rx_offset], + dft( dftsize,(int16_t *)&common->rxdata_7_5kHz[aa][rx_offset], (int16_t *)&common->rxdataF[aa][fp->ofdm_symbol_size*symbol], 1 ); @@ -121,13 +121,13 @@ int slot_fep_ul(RU_t *ru, memcpy((void *)&tmp_dft_in, (void *)&common->rxdata_7_5kHz[aa][(rx_offset % frame_length_samples)], fp->ofdm_symbol_size*sizeof(int)); - dft( (short *) tmp_dft_in, + dft( dftsize,(short *) tmp_dft_in, (short*) &common->rxdataF[aa][fp->ofdm_symbol_size*symbol], 1 ); } else{ - dft( (short *)&common->rxdata_7_5kHz[aa][rx_offset], + dft( dftsize,(short *)&common->rxdata_7_5kHz[aa][rx_offset], (short*)&common->rxdataF[aa][fp->ofdm_symbol_size*symbol], 1 ); diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index 0d7732599f..f94a82c111 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -430,55 +430,55 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, switch (gNB->frame_parms.ofdm_symbol_size) { case 128: - idft128((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_128,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 256: - idft256((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_256,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 512: - idft512((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_512,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 1024: - idft1024((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_1024,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 1536: - idft1536((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_1536,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 2048: - idft2048((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_2048,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 4096: - idft4096((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_4096,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; case 8192: - idft8192((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_8192,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; default: - idft512((int16_t*) &ul_ch_estimates[aarx][symbol_offset], + idft(IDFT_512,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], 1); break; diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c index ed37a79d0f..8718fc8610 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.c +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c @@ -35,143 +35,6 @@ /***********************************************************************/ -// TS 38.211 Table 6.4.1.1.3-3: PUSCH DMRS positions l' within a slot for single-symbol DMRS and intra-slot frequency hopping disabled. -// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B. -// When l' = l0, it is represented by 1 -// E.g. when symbol duration is 12 in colomn 7, value 1057 ('10000100001') which means l' = l0, 5, 10. - -int32_t table_6_4_1_1_3_3_pusch_dmrs_positions_l [12][8] = { // Duration in symbols -{-1, -1, -1, -1, 1, 1, 1, 1}, //<4 // (DMRS l' position) -{1, 1, 1, 1, 1, 1, 1, 1}, //4 // (DMRS l' position) -{1, 1, 1, 1, 1, 5, 5, 5}, //5 // (DMRS l' position) -{1, 1, 1, 1, 1, 5, 5, 5}, //6 // (DMRS l' position) -{1, 1, 1, 1, 1, 5, 5, 5}, //7 // (DMRS l' position) -{1, 129, 129, 129, 1, 65, 73, 73}, //8 // (DMRS l' position) -{1, 129, 129, 129, 1, 65, 73, 73}, //9 // (DMRS l' position) -{1, 513, 577, 577, 1, 257, 273, 585}, //10 // (DMRS l' position) -{1, 513, 577, 577, 1, 257, 273, 585}, //11 // (DMRS l' position) -{1, 513, 577, 2337, 1, 1025, 1057, 585}, //12 // (DMRS l' position) -{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //13 // (DMRS l' position) -{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //14 // (DMRS l' position) -}; - - -// TS 38.211 Table 6.4.1.1.3-4: PUSCH DMRS positions l' within a slot for double-symbol DMRS and intra-slot frequency hopping disabled. -// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B. -// When l' = l0, it is represented by 1 - -int32_t table_6_4_1_1_3_4_pusch_dmrs_positions_l [12][8] = { // Duration in symbols -{-1, -1, -1, -1, -1, -1, -1, -1}, //<4 // (DMRS l' position) -{1, 1, -1, -1, -1, -1, -1, -1}, //4 // (DMRS l' position) -{1, 1, -1, -1, 1, 1, -1, -1}, //5 // (DMRS l' position) -{1, 1, -1, -1, 1, 1, -1, -1}, //6 // (DMRS l' position) -{1, 1, -1, -1, 1, 1, -1, -1}, //7 // (DMRS l' position) -{1, 1, -1, -1, 1, 33, -1, -1}, //8 // (DMRS l' position) -{1, 1, -1, -1, 1, 33, -1, -1}, //9 // (DMRS l' position) -{1, 257, -1, -1, 1, 129, -1, -1}, //10 // (DMRS l' position) -{1, 257, -1, -1, 1, 129, -1, -1}, //11 // (DMRS l' position) -{1, 257, -1, -1, 1, 513, -1, -1}, //12 // (DMRS l' position) -{1, 1025, -1, -1, 1, 513, -1, -1}, //13 // (DMRS l' position) -{1, 1025, -1, -1, 1, 513, -1, -1}, //14 // (DMRS l' position) -}; - -int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength) { - - uint8_t row, colomn; - int32_t l_prime; - - colomn = additional_pos; - - if (mapping_type == typeB) - colomn += 4; - - if (duration_in_symbols < 4) - row = 0; - else - row = duration_in_symbols - 3; - - if (pusch_maxLength == pusch_len1) - l_prime = table_6_4_1_1_3_3_pusch_dmrs_positions_l[row][colomn]; - else - l_prime = table_6_4_1_1_3_4_pusch_dmrs_positions_l[row][colomn]; - - AssertFatal(l_prime>0,"invalid l_prime < 0\n"); - - return l_prime; -} - -/******************************************************************* -* -* NAME : is_dmrs_symbol -* -* PARAMETERS : l ofdm symbol index within slot -* k subcarrier index -* start_sc first subcarrier index -* k_prime index alternating 0 and 1 -* n index starting 0,1,... -* delta see Table 6.4.1.1.3 -* duration_in_symbols number of scheduled PUSCH ofdm symbols -* dmrs_UplinkConfig DMRS uplink configuration -* mapping_type PUSCH mapping type (A or B) -* ofdm_symbol_size IFFT size -* -* RETURN : 0 if symbol(k,l) is data, or 1 if symbol(k,l) is dmrs -* -* DESCRIPTION : 3GPP TS 38.211 6.4.1.1 Demodulation reference signal for PUSCH -* -*********************************************************************/ - -uint8_t is_dmrs_symbol(uint8_t l, - uint16_t k, - uint16_t start_sc, - uint8_t k_prime, - uint16_t n, - uint8_t delta, - uint8_t duration_in_symbols, - uint8_t dmrs_type, - uint16_t ofdm_symbol_size) { - - uint8_t is_dmrs_freq, is_dmrs_time, l0; - int32_t l_prime_mask; - pusch_dmrs_AdditionalPosition_t additional_pos = pusch_dmrs_pos0; - pusch_maxLength_t pusch_maxLength = pusch_len1; - uint8_t mapping_type = typeB; - - is_dmrs_freq = 0; - is_dmrs_time = 0; - - - l0 = get_l0_ul(mapping_type, 2); - l_prime_mask = get_l_prime(duration_in_symbols, mapping_type, additional_pos, pusch_maxLength); - - if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%ofdm_symbol_size)) - is_dmrs_freq = 1; - - - if (l_prime_mask == 1){ - - if (l == l0) - is_dmrs_time = 1; - - } else if ( (l==l0) || (((l_prime_mask>>l)&1) == 1 && l!=0) ) - is_dmrs_time = 1; - - if (pusch_maxLength == pusch_len2){ - - if (((l_prime_mask>>(l-1))&1) == 1 && l!=0 && l!=1) - is_dmrs_time = 1; - - if (l-1 == l0) - is_dmrs_time = 1; - - } - - if (is_dmrs_time && is_dmrs_freq) - return 1; - else - return 0; - -} /******************************************************************* * @@ -364,25 +227,6 @@ void lte_gold_new(LTE_DL_FRAME_PARMS *frame_parms, uint32_t lte_gold_table[20][2 #endif } -/******************************************************************* -* -* NAME : get_l0_ul -* -* PARAMETERS : mapping_type : PUSCH mapping type -* dmrs_typeA_position : higher layer parameter -* -* RETURN : demodulation reference signal for PUSCH -* -* DESCRIPTION : see TS 38.211 V15.4.0 Demodulation reference signals for PUSCH -* -*********************************************************************/ - -uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position) { - - return ((mapping_type==typeA)?dmrs_typeA_position:0); - -} - /******************************************************************* * * NAME : get_dmrs_freq_idx_ul diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.h b/openair1/PHY/NR_REFSIG/dmrs_nr.h index f1dfffff8b..6badf71745 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.h +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.h @@ -54,21 +54,8 @@ int pseudo_random_sequence(int M_PN, uint32_t *c, uint32_t cinit); void lte_gold_new(LTE_DL_FRAME_PARMS *frame_parms, uint32_t lte_gold_table[20][2][14], uint16_t Nid_cell); void generate_dmrs_pbch(uint32_t dmrs_pbch_bitmap[DMRS_PBCH_I_SSB][DMRS_PBCH_N_HF][DMRS_BITMAP_SIZE], uint16_t Nid_cell); -uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position); uint16_t get_dmrs_freq_idx_ul(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t dmrs_type); -int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength); - -uint8_t is_dmrs_symbol(uint8_t l, - uint16_t k, - uint16_t start_sc, - uint8_t k_prime, - uint16_t n, - uint8_t delta, - uint8_t duration_in_symbols, - uint8_t dmrs_type, - uint16_t ofdm_symbol_size); - #undef EXTERN #endif /* DMRS_NR_H */ diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index a998429699..c34dadb663 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -1,3 +1,27 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +#ifndef __PHY_NR_REFSIG_NR_MOD_TABLE__H__ +#define __PHY_NR_REFSIG_NR_MOD_TABLE__H__ + #define NR_MOD_TABLE_SIZE_SHORT 686 #define NR_MOD_TABLE_BPSK_OFFSET 1 #define NR_MOD_TABLE_QPSK_OFFSET 3 @@ -5,3 +29,5 @@ #define NR_MOD_TABLE_QAM64_OFFSET 23 #define NR_MOD_TABLE_QAM256_OFFSET 87 short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,16384,-16384,-16384,16384,-16384,-16384,7327,7327,7327,21981,21981,7327,21981,21981,7327,-7327,7327,-21981,21981,-7327,21981,-21981,-7327,7327,-7327,21981,-21981,7327,-21981,21981,-7327,-7327,-7327,-21981,-21981,-7327,-21981,-21981,10726,10726,10726,3576,3576,10726,3576,3576,10726,17876,10726,25027,3576,17876,3576,25027,17876,10726,17876,3576,25027,10726,25027,3576,17876,17876,17876,25027,25027,17876,25027,25027,10726,-10726,10726,-3576,3576,-10726,3576,-3576,10726,-17876,10726,-25027,3576,-17876,3576,-25027,17876,-10726,17876,-3576,25027,-10726,25027,-3576,17876,-17876,17876,-25027,25027,-17876,25027,-25027,-10726,10726,-10726,3576,-3576,10726,-3576,3576,-10726,17876,-10726,25027,-3576,17876,-3576,25027,-17876,10726,-17876,3576,-25027,10726,-25027,3576,-17876,17876,-17876,25027,-25027,17876,-25027,25027,-10726,-10726,-10726,-3576,-3576,-10726,-3576,-3576,-10726,-17876,-10726,-25027,-3576,-17876,-3576,-25027,-17876,-10726,-17876,-3576,-25027,-10726,-25027,-3576,-17876,-17876,-17876,-25027,-25027,-17876,-25027,-25027,8886,8886,8886,12439,12439,8886,12439,12439,8886,5332,8886,1778,12439,5332,12439,1778,5332,8886,5332,12439,1778,8886,1778,12439,5332,5332,5332,1778,1778,5332,1778,1778,8886,19547,8886,15993,12439,19547,12439,15993,8886,23101,8886,26655,12439,23101,12439,26655,5332,19547,5332,15993,1778,19547,1778,15993,5332,23101,5332,26655,1778,23101,1778,26655,19547,8886,19547,12439,15993,8886,15993,12439,19547,5332,19547,1778,15993,5332,15993,1778,23101,8886,23101,12439,26655,8886,26655,12439,23101,5332,23101,1778,26655,5332,26655,1778,19547,19547,19547,15993,15993,19547,15993,15993,19547,23101,19547,26655,15993,23101,15993,26655,23101,19547,23101,15993,26655,19547,26655,15993,23101,23101,23101,26655,26655,23101,26655,26655,8886,-8886,8886,-12439,12439,-8886,12439,-12439,8886,-5332,8886,-1778,12439,-5332,12439,-1778,5332,-8886,5332,-12439,1778,-8886,1778,-12439,5332,-5332,5332,-1778,1778,-5332,1778,-1778,8886,-19547,8886,-15993,12439,-19547,12439,-15993,8886,-23101,8886,-26655,12439,-23101,12439,-26655,5332,-19547,5332,-15993,1778,-19547,1778,-15993,5332,-23101,5332,-26655,1778,-23101,1778,-26655,19547,-8886,19547,-12439,15993,-8886,15993,-12439,19547,-5332,19547,-1778,15993,-5332,15993,-1778,23101,-8886,23101,-12439,26655,-8886,26655,-12439,23101,-5332,23101,-1778,26655,-5332,26655,-1778,19547,-19547,19547,-15993,15993,-19547,15993,-15993,19547,-23101,19547,-26655,15993,-23101,15993,-26655,23101,-19547,23101,-15993,26655,-19547,26655,-15993,23101,-23101,23101,-26655,26655,-23101,26655,-26655,-8886,8886,-8886,12439,-12439,8886,-12439,12439,-8886,5332,-8886,1778,-12439,5332,-12439,1778,-5332,8886,-5332,12439,-1778,8886,-1778,12439,-5332,5332,-5332,1778,-1778,5332,-1778,1778,-8886,19547,-8886,15993,-12439,19547,-12439,15993,-8886,23101,-8886,26655,-12439,23101,-12439,26655,-5332,19547,-5332,15993,-1778,19547,-1778,15993,-5332,23101,-5332,26655,-1778,23101,-1778,26655,-19547,8886,-19547,12439,-15993,8886,-15993,12439,-19547,5332,-19547,1778,-15993,5332,-15993,1778,-23101,8886,-23101,12439,-26655,8886,-26655,12439,-23101,5332,-23101,1778,-26655,5332,-26655,1778,-19547,19547,-19547,15993,-15993,19547,-15993,15993,-19547,23101,-19547,26655,-15993,23101,-15993,26655,-23101,19547,-23101,15993,-26655,19547,-26655,15993,-23101,23101,-23101,26655,-26655,23101,-26655,26655,-8886,-8886,-8886,-12439,-12439,-8886,-12439,-12439,-8886,-5332,-8886,-1778,-12439,-5332,-12439,-1778,-5332,-8886,-5332,-12439,-1778,-8886,-1778,-12439,-5332,-5332,-5332,-1778,-1778,-5332,-1778,-1778,-8886,-19547,-8886,-15993,-12439,-19547,-12439,-15993,-8886,-23101,-8886,-26655,-12439,-23101,-12439,-26655,-5332,-19547,-5332,-15993,-1778,-19547,-1778,-15993,-5332,-23101,-5332,-26655,-1778,-23101,-1778,-26655,-19547,-8886,-19547,-12439,-15993,-8886,-15993,-12439,-19547,-5332,-19547,-1778,-15993,-5332,-15993,-1778,-23101,-8886,-23101,-12439,-26655,-8886,-26655,-12439,-23101,-5332,-23101,-1778,-26655,-5332,-26655,-1778,-19547,-19547,-19547,-15993,-15993,-19547,-15993,-15993,-19547,-23101,-19547,-26655,-15993,-23101,-15993,-26655,-23101,-19547,-23101,-15993,-26655,-19547,-26655,-15993,-23101,-23101,-23101,-26655,-26655,-23101,-26655,-26655}; + +#endif diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h index 5af0e88099..d18f6405d7 100644 --- a/openair1/PHY/NR_REFSIG/nr_refsig.h +++ b/openair1/PHY/NR_REFSIG/nr_refsig.h @@ -26,7 +26,7 @@ #include "PHY/defs_gNB.h" #include "PHY/LTE_REFSIG/lte_refsig.h" - +#include "PHY/sse_intrin.h" /*!\brief This function generates the NR Gold sequence (38-211, Sec 5.2.1) for the PBCH DMRS. @param PHY_VARS_gNB* gNB structure provides configuration, frame parameters and the pointers to the 32 bits sequence storage tables @@ -49,4 +49,10 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned char lp, unsigned short nb_pusch_rb, uint8_t dmrs_type); + +void init_scrambling_luts(void); + +extern __m64 byte2m64_re[256]; +extern __m64 byte2m64_im[256]; + #endif diff --git a/openair1/PHY/NR_REFSIG/pss_nr.h b/openair1/PHY/NR_REFSIG/pss_nr.h index a2e66d4e11..19b9736bcb 100644 --- a/openair1/PHY/NR_REFSIG/pss_nr.h +++ b/openair1/PHY/NR_REFSIG/pss_nr.h @@ -127,8 +127,8 @@ time_stats_t generic_time[TIME_LAST]; /************** FUNCTION ******************************************/ -void *get_idft(int ofdm_symbol_size); -void *get_dft(int ofdm_symbol_size); +idft_size_idx_t get_idft(int ofdm_symbol_size); +dft_size_idx_t get_dft(int ofdm_symbol_size); void init_context_synchro_nr(NR_DL_FRAME_PARMS *frame_parms_ue); void free_context_synchro_nr(void); void init_context_pss_nr(NR_DL_FRAME_PARMS *frame_parms_ue); diff --git a/openair1/PHY/NR_REFSIG/ptrs_nr.c b/openair1/PHY/NR_REFSIG/ptrs_nr.c index 12f76b950f..785252126a 100644 --- a/openair1/PHY/NR_REFSIG/ptrs_nr.c +++ b/openair1/PHY/NR_REFSIG/ptrs_nr.c @@ -38,18 +38,18 @@ /***********************************************************************/ - //#define max(a,b) (((a) > (b)) ? (a) : (b)) +//#define max(a,b) (((a) > (b)) ? (a) : (b)) // TS 38.211 Table 6.4.1.2.2.1-1: The parameter kRE_ref. // The first 4 colomns are DM-RS Configuration type 1 and the last 4 colomns are DM-RS Configuration type 2. int16_t table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref [6][8] = { -{ 0, 2, 6, 8, 0, 1, 6, 7}, -{ 2, 4, 8, 10, 1, 6, 7, 0}, -{ 1, 3, 7, 9, 2, 3, 8, 9}, -{ 3, 5, 9, 11, 3, 8, 9, 2}, -{-1, -1, -1, -1, 4, 5, 10, 11}, -{-1, -1, -1, -1, 5, 10, 11, 4}, + { 0, 2, 6, 8, 0, 1, 6, 7}, + { 2, 4, 8, 10, 1, 6, 7, 0}, + { 1, 3, 7, 9, 2, 3, 8, 9}, + { 3, 5, 9, 11, 3, 8, 9, 2}, + {-1, -1, -1, -1, 4, 5, 10, 11}, + {-1, -1, -1, -1, 5, 10, 11, 4}, }; @@ -68,55 +68,20 @@ int16_t table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref [6][8] = { *********************************************************************/ int16_t get_kRE_ref(uint8_t dmrs_antenna_port, uint8_t pusch_dmrs_type, uint8_t resourceElementOffset) { - uint8_t colomn; int16_t k_RE_ref; - colomn = resourceElementOffset; if (pusch_dmrs_type == 2) colomn += 4; k_RE_ref = table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref[dmrs_antenna_port][colomn]; - AssertFatal(k_RE_ref>=0,"invalid k_RE_ref < 0. Check PTRS Configuration\n"); - return k_RE_ref; } -/******************************************************************* -* -* NAME : get_K_ptrs -* -* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration -* N_RB number of RBs scheduled for PUSCH -* -* RETURN : the parameter K_ptrs -* -* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-2 -* -*********************************************************************/ -uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){ - - uint16_t nrb0, nrb1; - - nrb0 = ptrs_UplinkConfig->frequencyDensity.n_rb0; - nrb1 = ptrs_UplinkConfig->frequencyDensity.n_rb1; - - if (nrb0 == 0 || nrb0 == 0) - return 2; - - if (N_RB < nrb0){ - LOG_I(PHY,"PUSH PT-RS is not present.\n"); - return 0; - } - else if (N_RB >= nrb0 && N_RB < nrb1) - return 2; - else - return 4; -} /******************************************************************* * @@ -126,7 +91,7 @@ uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){ * duration_in_symbols number of scheduled PUSCH ofdm symbols * start_symbol first ofdm symbol of PUSCH within slot * L_ptrs the parameter L_ptrs -* ofdm_symbol_size FFT size +* ul_dmrs_symb_pos bitmap of the time domain positions of the DMRS symbols in the scheduled PUSCH * * RETURN : sets the bit map of PTRS ofdm symbol indicies * @@ -137,54 +102,31 @@ uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){ void set_ptrs_symb_idx(uint16_t *ptrs_symbols, uint8_t duration_in_symbols, uint8_t start_symbol, - uint8_t dmrs_type, uint8_t L_ptrs, - uint8_t pusch_maxLength, - uint16_t ofdm_symbol_size) { + uint16_t ul_dmrs_symb_pos) { - uint8_t i, last_symbol, is_dmrs_symbol1, is_dmrs_symbol2; - int16_t l_ref; - - *ptrs_symbols = 0; - i = 0; - is_dmrs_symbol1 = 0; - is_dmrs_symbol2 = 0; - l_ref = start_symbol; - last_symbol = start_symbol + duration_in_symbols - 1; + uint8_t i = 0, last_symbol, is_dmrs_symbol, l_ref; + int8_t l_counter; + l_ref = start_symbol; + last_symbol = start_symbol + duration_in_symbols - 1; while ( (l_ref + i*L_ptrs) <= last_symbol) { - is_dmrs_symbol1 = is_dmrs_symbol(max((l_ref + (i-1)*L_ptrs + 1), l_ref), - 0, - 0, - 0, - 0, - 0, - duration_in_symbols, - dmrs_type, - ofdm_symbol_size); + is_dmrs_symbol = 0; - is_dmrs_symbol2 = is_dmrs_symbol(l_ref + i*L_ptrs, - 0, - 0, - 0, - 0, - 0, - duration_in_symbols, - dmrs_type, - ofdm_symbol_size); + for(l_counter = l_ref + i*L_ptrs; l_counter >= max(l_ref + (i-1)*L_ptrs + 1, l_ref); l_counter--) { - if ( is_dmrs_symbol1 + is_dmrs_symbol2 > 0 ) { + if((ul_dmrs_symb_pos >> l_counter) & 0x01) { + is_dmrs_symbol = 1; + break; + } - if (pusch_maxLength == 2) - l_ref = l_ref + i*L_ptrs + 1; - else - l_ref = l_ref + i*L_ptrs; - - i = 1; - - continue; + } + if (is_dmrs_symbol) { + l_ref = l_counter; + i = 1; + continue; } *ptrs_symbols = *ptrs_symbols | (1<<(l_ref + i*L_ptrs)); @@ -192,53 +134,19 @@ void set_ptrs_symb_idx(uint16_t *ptrs_symbols, } } -/******************************************************************* -* -* NAME : get_L_ptrs -* -* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration -* I_mcs MCS index used for PUSCH -* -* RETURN : the parameter L_ptrs -* -* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-1 -* -*********************************************************************/ - -uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs) { - - uint8_t mcs1, mcs2, mcs3; - - mcs1 = ptrs_UplinkConfig->timeDensity.ptrs_mcs1; - mcs2 = ptrs_UplinkConfig->timeDensity.ptrs_mcs2; - mcs3 = ptrs_UplinkConfig->timeDensity.ptrs_mcs3; - - if (mcs1 == 0 || mcs2 == 0 || mcs3 == 0) - return 1; - - if (I_mcs < mcs1){ - LOG_I(PHY,"PUSH PT-RS is not present.\n"); - return 0; - } - else if (I_mcs >= mcs1 && I_mcs < mcs2) - return 4; - else if (I_mcs >= mcs2 && I_mcs < mcs3) - return 2; - else - return 1; -} - /******************************************************************* * * NAME : is_ptrs_subcarrier * * PARAMETERS : k subcarrier index -* K_ptrs the parameter K_ptrs * n_rnti UE CRNTI +* dmrs_antenna_port DMRS antenna port +* K_ptrs the parameter K_ptrs +* pusch_dmrs_type the DMRS configuration type used for PUSCH * N_RB number of RBs scheduled for PUSCH * k_RE_ref the parameter k_RE_ref * start_sc first subcarrier index -* ofdm_symbol_size FFT size +* ofdm_symbol_size number of samples in an OFDM symbol * * RETURN : 1 if subcarrier k is PTRS, or 0 otherwise * @@ -246,107 +154,48 @@ uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs) { * *********************************************************************/ -uint8_t is_ptrs_subcarrier(uint16_t k, uint8_t K_ptrs, uint16_t n_rnti, uint16_t N_RB, int16_t k_RE_ref, uint16_t start_sc, uint16_t ofdm_symbol_size) { +uint8_t is_ptrs_subcarrier(uint16_t k, + uint16_t n_rnti, + uint8_t dmrs_antenna_port, + uint8_t pusch_dmrs_type, + uint8_t K_ptrs, + uint16_t N_RB, + uint8_t k_RE_ref, + uint16_t start_sc, + uint16_t ofdm_symbol_size) +{ + // int16_t k_RE_ref = get_kRE_ref(dmrs_antenna_port, pusch_dmrs_type, resourceElementOffset); + uint16_t k_RB_ref; - uint16_t k_RB_ref, i, sc; - - i = 0; - sc = 0; - k_RB_ref = 0; - - if (N_RB % K_ptrs == 0) - k_RB_ref = n_rnti % K_ptrs; - else - k_RB_ref = n_rnti % (N_RB % K_ptrs); - - while (k > sc){ - - sc = (start_sc + k_RE_ref + (i*K_ptrs + k_RB_ref)*NR_NB_SC_PER_RB)%ofdm_symbol_size; - i++; - - } - - if (k == sc) - return 1; - else - return 0; - -} - -/******************************************************************* -* -* NAME : is_ptrs_symbol -* -* PARAMETERS : l ofdm symbol index within slot -* k subcarrier index -* n_rnti UE CRNTI -* N_RB number of RBs scheduled for PUSCH -* duration_in_symbols number of scheduled PUSCH ofdm symbols -* dmrs_antenna_port DMRS antenna port -* K_ptrs the parameter K_ptrs -* ptrs_symbols bit mask of ptrs -* start_sc first subcarrier index -* ofdm_symbol_size FFT size -* pusch_dmrs_type PUSCH DMRS type (1 or 2) -* ptrs_UplinkConfig PTRS uplink configuration -* -* RETURN : 0 if symbol(k,l) is data, or 1 if symbol(k,l) is ptrs -* -* DESCRIPTION : 3GPP TS 38.211 6.4.1.2 Phase-tracking reference signal for PUSCH -* -*********************************************************************/ - -uint8_t is_ptrs_symbol(uint8_t l, - uint16_t k, - uint16_t n_rnti, - uint16_t N_RB, - uint8_t duration_in_symbols, - uint8_t dmrs_antenna_port, - uint8_t K_ptrs, - uint16_t ptrs_symbols, - uint16_t start_sc, - uint16_t ofdm_symbol_size, - pusch_dmrs_type_t pusch_dmrs_type, - uint8_t resourceElementOffset) { - - uint8_t is_ptrs_freq, is_ptrs_time; - int16_t k_RE_ref; - - is_ptrs_freq = 0; - is_ptrs_time = 0; - - k_RE_ref = get_kRE_ref(dmrs_antenna_port, pusch_dmrs_type, resourceElementOffset); - - is_ptrs_freq = is_ptrs_subcarrier(k, K_ptrs, n_rnti, N_RB, k_RE_ref, start_sc, ofdm_symbol_size); - - if (is_ptrs_freq == 0) - return 0; - - if (((ptrs_symbols>>l)&1) == 1) - is_ptrs_time = 1; - - if (is_ptrs_time && is_ptrs_freq) - return 1; + if (N_RB % K_ptrs == 0) + k_RB_ref = n_rnti % K_ptrs; else - return 0; + k_RB_ref = n_rnti % (N_RB % K_ptrs); + if (k < start_sc) + k += ofdm_symbol_size; + + if ((k - k_RE_ref - k_RB_ref*NR_NB_SC_PER_RB - start_sc) % (K_ptrs*NR_NB_SC_PER_RB) == 0) + return 1; + + return 0; } /* int main(int argc, char const *argv[]) { - dmrs_UplinkConfig_t dmrs_Uplink_Config; - ptrs_UplinkConfig_t ptrs_Uplink_Config; - uint8_t resourceElementOffset; - uint8_t dmrs_antenna_port; - uint8_t L_ptrs, K_ptrs; - int16_t k_RE_ref; - uint16_t N_RB, ptrs_symbols, ofdm_symbol_size, k; - uint8_t duration_in_symbols, I_mcs; - uint8_t start_symbol, l; - uint8_t ptrs_symbol_flag; - uint16_t n_rnti; + dmrs_UplinkConfig_t dmrs_Uplink_Config; + ptrs_UplinkConfig_t ptrs_Uplink_Config; + uint8_t resourceElementOffset; + uint8_t dmrs_antenna_port; + uint8_t L_ptrs, K_ptrs; + int16_t k_RE_ref; + uint16_t N_RB, ptrs_symbols, ofdm_symbol_size, k; + uint8_t duration_in_symbols, I_mcs; + uint8_t start_symbol, l; + uint8_t ptrs_symbol_flag; + uint16_t n_rnti; dmrs_Uplink_Config.pusch_dmrs_type = pusch_dmrs_type1; dmrs_Uplink_Config.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos1; @@ -362,13 +211,13 @@ int main(int argc, char const *argv[]) n_rnti = 0x1234; resourceElementOffset = 0; ptrs_symbols = 0; - dmrs_antenna_port = 0; - N_RB = 50; - duration_in_symbols = 14; - ofdm_symbol_size = 2048; - I_mcs = 9; - start_symbol = 0; - ptrs_symbol_flag = 0; + dmrs_antenna_port = 0; + N_RB = 50; + duration_in_symbols = 14; + ofdm_symbol_size = 2048; + I_mcs = 9; + start_symbol = 0; + ptrs_symbol_flag = 0; k_RE_ref = get_kRE_ref(dmrs_antenna_port, dmrs_Uplink_Config.pusch_dmrs_type, resourceElementOffset); @@ -418,6 +267,6 @@ int main(int argc, char const *argv[]) printf("\n"); - return 0; + return 0; } */ diff --git a/openair1/PHY/NR_REFSIG/ptrs_nr.h b/openair1/PHY/NR_REFSIG/ptrs_nr.h index 291ff4a555..e8a4e61232 100644 --- a/openair1/PHY/NR_REFSIG/ptrs_nr.h +++ b/openair1/PHY/NR_REFSIG/ptrs_nr.h @@ -49,32 +49,36 @@ int16_t get_kRE_ref(uint8_t dmrs_antenna_port, uint8_t pusch_dmrs_type, uint8_t resourceElementOffset); -uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB); - void set_ptrs_symb_idx(uint16_t *ptrs_symbols, uint8_t duration_in_symbols, uint8_t start_symbol, - uint8_t dmrs_type, uint8_t L_ptrs, - uint8_t pusch_maxLength, - uint16_t ofdm_symbol_size); + uint16_t ul_dmrs_symb_pos); -uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs); +uint8_t is_ptrs_subcarrier(uint16_t k, + uint16_t n_rnti, + uint8_t dmrs_antenna_port, + uint8_t pusch_dmrs_type, + uint8_t K_ptrs, + uint16_t N_RB, + uint8_t k_RE_ref, + uint16_t start_sc, + uint16_t ofdm_symbol_size); -uint8_t is_ptrs_subcarrier(uint16_t k, uint8_t K_ptrs, uint16_t n_rnti, uint16_t N_RB, int16_t k_RE_ref, uint16_t start_sc, uint16_t ofdm_symbol_size); +/******************************************************************* +* +* NAME : is_ptrs_symbol +* +* PARAMETERS : l ofdm symbol index within slot +* ptrs_symbols bit mask of ptrs +* +* RETURN : 1 if symbol is ptrs, or 0 otherwise +* +* DESCRIPTION : 3GPP TS 38.211 6.4.1.2 Phase-tracking reference signal for PUSCH +* +*********************************************************************/ -uint8_t is_ptrs_symbol(uint8_t l, - uint16_t k, - uint16_t n_rnti, - uint16_t N_RB, - uint8_t duration_in_symbols, - uint8_t dmrs_antenna_port, - uint8_t K_ptrs, - uint16_t ptrs_symbols, - uint16_t start_sc, - uint16_t ofdm_symbol_size, - pusch_dmrs_type_t pusch_dmrs_type, - uint8_t resourceElementOffset); +static inline uint8_t is_ptrs_symbol(uint8_t l, uint16_t ptrs_symbols) { return ((ptrs_symbols >> l) & 1); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index ccec73d40e..c7b14571b7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -137,7 +137,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { int N_reg = n_rb * pdcch_pdu_rel15->DurationSymbols; - int C; + int C=-1; for (int d=0;dnumDlDci;d++) { int L = pdcch_pdu_rel15->AggregationLevel[d]; @@ -210,7 +210,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, for (int i=0;inumDlDci;i++) { - uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE); @@ -248,7 +248,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB, for (int i=0;inumDlDci;i++) { - uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; // if there's no DL DCI then generate CCE list if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 856a7863f4..f120864184 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -64,7 +64,6 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) a_segments = a_segments/273; } - uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment #ifdef DEBUG_DLSCH_FREE @@ -82,7 +81,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) #endif if (dlsch->harq_processes[i]->b) { - free16(dlsch->harq_processes[i]->b,dlsch_bytes); + free16(dlsch->harq_processes[i]->b,a_segments*1056); dlsch->harq_processes[i]->b = NULL; #ifdef DEBUG_DLSCH_FREE LOG_D(PHY,"Freeing dlsch process %d b (%p)\n",i,dlsch->harq_processes[i]->b); diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 5710499e1a..5c4d048a77 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -175,39 +175,39 @@ void rx_nr_prach_ru(RU_t *ru, //50 MHz @ 61.44 Ms/s prach2 = prach[aa] + (Ncp<<2); if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - dft49152(prach2,rxsigF[aa],1); + dft(DFT_49152,prach2,rxsigF[aa],1); if (prach_fmt == 1 || prach_fmt == 2) { - dft49152(prach2+98304,rxsigF[aa]+98304,1); + dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1); reps++; } if (prach_fmt == 2) { - dft49152(prach2+(98304*2),rxsigF[aa]+(98304*2),1); - dft49152(prach2+(98304*3),rxsigF[aa]+(98304*3),1); + dft(DFT_49152,prach2+(98304*2),rxsigF[aa]+(98304*2),1); + dft(DFT_49152,prach2+(98304*3),rxsigF[aa]+(98304*3),1); reps+=2; } if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft12288(prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); + for (int i=0;i<4;i++) dft(DFT_12288,prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); reps=4; } if (prach_fmt >3) { - dft2048(prach2,rxsigF[aa],1); + dft(DFT_2048,prach2,rxsigF[aa],1); if (prach_fmt != 0xc0) { - dft2048(prach2+4096,rxsigF[aa]+4096,1); + dft(DFT_2048,prach2+4096,rxsigF[aa]+4096,1); reps++; } } if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft2048(prach2+4096*2,rxsigF[aa]+4096*2,1); - dft2048(prach2+4096*3,rxsigF[aa]+4096*3,1); + dft(DFT_2048,prach2+4096*2,rxsigF[aa]+4096*2,1); + dft(DFT_2048,prach2+4096*3,rxsigF[aa]+4096*3,1); reps+=2; } if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); - dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); + dft(DFT_2048,prach2+4096*4,rxsigF[aa]+4096*4,1); + dft(DFT_2048,prach2+4096*5,rxsigF[aa]+4096*5,1); reps+=2; } if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft2048(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + for (int i=6;i<11;i++) dft(DFT_2048,prach2+(3072*i),rxsigF[aa]+(3072*i),1); reps+=6; } } else { @@ -215,41 +215,41 @@ void rx_nr_prach_ru(RU_t *ru, prach2 = prach[aa] + (3*Ncp); AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dft36864(prach2,rxsigF[aa],1); + dft(DFT_36864,prach2,rxsigF[aa],1); reps++; } if (prach_fmt == 1 || prach_fmt == 2) { - dft36864(prach2+73728,rxsigF[aa]+73728,1); + dft(DFT_36864,prach2+73728,rxsigF[aa]+73728,1); reps++; } if (prach_fmt == 2) { - dft36864(prach2+(98304*2),rxsigF[aa]+(98304*2),1); - dft36864(prach2+(98304*3),rxsigF[aa]+(98304*3),1); + dft(DFT_36864,prach2+(98304*2),rxsigF[aa]+(98304*2),1); + dft(DFT_36864,prach2+(98304*3),rxsigF[aa]+(98304*3),1); reps+=2; } if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft9216(prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); + for (int i=0;i<4;i++) dft(DFT_9216,prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); reps=4; } if (prach_fmt >3) { - dft1536(prach2,rxsigF[aa],1); + dft(DFT_1536,prach2,rxsigF[aa],1); if (prach_fmt != 0xc0) { - dft1536(prach2+3072,rxsigF[aa]+3072,1); + dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1); reps++; } } if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); - dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); + dft(DFT_1536,prach2+3072*2,rxsigF[aa]+3072*2,1); + dft(DFT_1536,prach2+3072*3,rxsigF[aa]+3072*3,1); reps+=2; } if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); - dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); + dft(DFT_1536,prach2+3072*4,rxsigF[aa]+3072*4,1); + dft(DFT_1536,prach2+3072*5,rxsigF[aa]+3072*5,1); reps+=2; } if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + for (int i=6;i<11;i++) dft(DFT_1536,prach2+(3072*i),rxsigF[aa]+(3072*i),1); reps+=6; } } @@ -260,41 +260,41 @@ void rx_nr_prach_ru(RU_t *ru, dftlen=98304; //80,90,100 MHz @ 61.44 Ms/s if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - dft98304(prach2,rxsigF[aa],1); + dft(DFT_98304,prach2,rxsigF[aa],1); if (prach_fmt == 1 || prach_fmt == 2) { - dft98304(prach2+196608,rxsigF[aa]+196608,1); + dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1); reps++; } if (prach_fmt == 1 || prach_fmt == 2) { - dft98304(prach2+196608,rxsigF[aa]+196608,1); - dft98304(prach2+(196608*2),rxsigF[aa]+(196608*2),1); + dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1); + dft(DFT_98304,prach2+(196608*2),rxsigF[aa]+(196608*2),1); reps+=2; } if (prach_fmt == 3) { - dft24576(prach2+(2*49152),rxsigF[aa]+(2*49152),1); + dft(DFT_24576,prach2+(2*49152),rxsigF[aa]+(2*49152),1); reps=4; dftlen=24576; } if (prach_fmt >3) { dftlen=4096; - dft4096(prach2,rxsigF[aa],1); + dft(DFT_4096,prach2,rxsigF[aa],1); if (prach_fmt != 0xc0) { - dft4096(prach2+8192,rxsigF[aa]+8192,1); + dft(DFT_4096,prach2+8192,rxsigF[aa]+8192,1); reps++; } } if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft4096(prach2+8192*2,rxsigF[aa]+8192*2,1); - dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); + dft(DFT_4096,prach2+8192*2,rxsigF[aa]+8192*2,1); + dft(DFT_4096,prach2+8192*3,rxsigF[aa]+8192*3,1); reps+=2; } if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); - dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); + dft(DFT_4096,prach2+8192*4,rxsigF[aa]+8192*4,1); + dft(DFT_4096,prach2+8192*5,rxsigF[aa]+8192*5,1); reps+=2; } if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); + for (int i=6;i<11;i++) dft(DFT_4096,prach2+(8192*i),rxsigF[aa]+(8192*i),1); reps+=6; } } else { @@ -303,39 +303,39 @@ void rx_nr_prach_ru(RU_t *ru, // 80 MHz @ 46.08 Ms/s dftlen=73728; if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dft73728(prach2,rxsigF[aa],1); + dft(DFT_73728,prach2,rxsigF[aa],1); reps++; } if (prach_fmt == 1 || prach_fmt == 2) { - dft73728(prach2+(2*73728),rxsigF[aa]+(2*73728),1); + dft(DFT_73728,prach2+(2*73728),rxsigF[aa]+(2*73728),1); reps++; } if (prach_fmt == 3) { - dft73728(prach2+(4*73728),rxsigF[aa]+(4*73728),1); + dft(DFT_73728,prach2+(4*73728),rxsigF[aa]+(4*73728),1); reps=4; dftlen=18432; } if (prach_fmt >3) { dftlen=3072; - dft3072(prach2,rxsigF[aa],1); + dft(DFT_3072,prach2,rxsigF[aa],1); if (prach_fmt != 0xc0) { - dft3072(prach2+6144,rxsigF[aa]+6144,1); + dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1); reps++; } } if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft3072(prach2+6144*2,rxsigF[aa]+6144*2,1); - dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); + dft(DFT_3072,prach2+6144*2,rxsigF[aa]+6144*2,1); + dft(DFT_3072,prach2+6144*3,rxsigF[aa]+6144*3,1); reps+=2; } if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); - dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); + dft(DFT_3072,prach2+6144*4,rxsigF[aa]+6144*4,1); + dft(DFT_3072,prach2+6144*5,rxsigF[aa]+6144*5,1); reps+=2; } if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); + for (int i=6;i<11;i++) dft(DFT_3072,prach2+(6144*i),rxsigF[aa]+(6144*i),1); reps+=6; } } @@ -366,6 +366,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, uint16_t *max_preamble_delay ) { + AssertFatal(gNB!=NULL,"Can only be called from gNB\n"); int i; @@ -405,7 +406,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, nr_frequency_range_e freq_range; - AssertFatal(gNB!=NULL,"Can only be called from gNB\n"); fp = &gNB->frame_parms; nb_rx = fp->nb_antennas_rx; @@ -420,8 +420,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,freq_range); uint16_t N_ZC = (prach_fmt <4)?839:139; - AssertFatal(gNB!=NULL,"gNB is null\n"); - prach_ifft = gNB->prach_vars.prach_ifft; prachF = gNB->prach_vars.prachF; if (LOG_DEBUGFLAG(PRACH)){ @@ -456,8 +454,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, AssertFatal(NCS!=99,"NCS has not been set\n"); - if (gNB) start_meas(&gNB->rx_prach); - + start_meas(&gNB->rx_prach); prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; @@ -590,12 +587,12 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // Now do IFFT of size 1024 (N_ZC=839) or 256 (N_ZC=139) if (N_ZC == 839) { log2_ifft_size = 10; - idft1024(prachF,prach_ifft_tmp,1); + idft(IDFT_1024,prachF,prach_ifft_tmp,1); // compute energy and accumulate over receive antennas for (i=0;i<2048;i++) prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[i<<1] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; } else { - idft256(prachF,prach_ifft_tmp,1); + idft(IDFT_256,prachF,prach_ifft_tmp,1); log2_ifft_size = 8; // compute energy and accumulate over receive antennas and repetitions for BR for (i=0;i<256;i++) diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h index be73875058..98e5930c4c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport.h @@ -123,4 +123,32 @@ void rx_nr_prach_ru(RU_t *ru, int frame, int subframe); +void compute_nr_prach_seq(uint16_t rootSequenceIndex, + uint8_t prach_ConfigIndex, + uint8_t zeroCorrelationZoneConfig, + uint8_t highSpeedFlag, + lte_frame_type_t frame_type, + nr_frequency_range_e fr, + uint32_t X_u[64][839]); + +void nr_decode_pucch1(int32_t **rxdataF, + pucch_GroupHopping_t pucch_GroupHopping, + uint32_t n_id, // hoppingID higher layer parameter + uint64_t *payload, + NR_DL_FRAME_PARMS *frame_parms, + int16_t amp, + int nr_tti_tx, + uint8_t m0, + uint8_t nrofSymbols, + uint8_t startingSymbolIndex, + uint16_t startingPRB, + uint16_t startingPRB_intraSlotHopping, + uint8_t timeDomainOCC, + uint8_t nr_bit); + +void nr_decode_pucch0(PHY_VARS_gNB *gNB, + int slot, + nfapi_nr_uci_pucch_pdu_format_0_1_t* uci_pdu, + nfapi_nr_pucch_pdu_t* pucch_pdu); + #endif /*__NR_TRANSPORT__H__*/ diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h index 762346048f..ab5b0c38ac 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h @@ -41,7 +41,19 @@ #define NR_PUSCH_y 3 // UCI placeholder bit +void nr_group_sequence_hopping(pucch_GroupHopping_t PUCCH_GroupHopping, + uint32_t n_id, + uint8_t n_hop, + int nr_tti_tx, + uint8_t *u, + uint8_t *v); +double nr_cyclic_shift_hopping(uint32_t n_id, + uint8_t m0, + uint8_t mcs, + uint8_t lnormal, + uint8_t lprime, + int nr_tti_tx); /** \brief Computes available bits G. */ @@ -49,4 +61,5 @@ uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch, uint8_t nb_re_dmrs, uint uint32_t nr_get_E(uint32_t G, uint8_t C, uint8_t Qm, uint8_t Nl, uint8_t r); +void init_pucch2_luts(void); #endif diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h index dd37455e26..fe61733f49 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h @@ -29,8 +29,8 @@ * \note * \warning */ -#ifndef __NR_TRANSPORT_PROTO_UE__H__ -#define __NR_TRANSPORT_PROTO_UE__H__ +#ifndef __NR_TRANSPORT_PROTO_COMMON_H__ +#define __NR_TRANSPORT_PROTO_COMMON_H__ #include "PHY/defs_nr_UE.h" #include "SCHED_NR_UE/defs.h" //#include "PHY/LTE_TRANSPORT/transport_common_proto.h" @@ -43,29 +43,6 @@ * @{ */ -/** \fn free_ue_dlsch(NR_UE_DLSCH_t *dlsch) - \brief This function frees memory allocated for a particular DLSCH at UE - @param dlsch Pointer to DLSCH to be removed -*/ -void free_nr_ue_dlsch(NR_UE_DLSCH_t *dlsch); - -/** \fn new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag) - \brief This function allocates structures for a particular DLSCH at UE - @returns Pointer to DLSCH to be removed - @param Kmimo Kmimo factor from 36-212/36-213 - @param Mdlharq Maximum number of HARQ rounds (36-212/36-213) - @param Nsoft Soft-LLR buffer size from UE-Category - @params N_RB_DL total number of resource blocks (determine the operating BW) - @param abstraction_flag Flag to indicate abstracted interface -*/ -NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag); - - -void free_nr_ue_ulsch(NR_UE_ULSCH_t *ulsch); - - -NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); - void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue, @@ -1051,25 +1028,6 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint8_t is_crnti, uint8_t llr8_flag); -int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, - NR_DL_FRAME_PARMS* frame_parms, - uint8_t harq_pid); - -/*! \brief Perform PUSCH scrambling. TS 38.211 V15.4.0 subclause 6.3.1.1 - @param[in] in Pointer to input bits - @param[in] size of input bits - @param[in] Nid cell id - @param[in] n_RNTI CRNTI - @param[out] out the scrambled bits -*/ - -void nr_pusch_codeword_scrambling(uint8_t *in, - uint16_t size, - uint32_t Nid, - uint32_t n_RNTI, - uint32_t* out); - - uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, UE_nr_rxtx_proc_t *proc, int eNB_id, @@ -1128,17 +1086,6 @@ int32_t nr_rx_pdsch(PHY_VARS_NR_UE *phy_vars_ue, uint8_t i_mod, uint8_t harq_pid); -int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, - uint32_t frame, - uint8_t nr_tti_rx, - uint8_t eNB_id, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag, - uint8_t is_secondary_ue, - int nb_coreset_active, - uint16_t symbol_mon, - NR_SEARCHSPACE_TYPE_t searchSpaceType); - /*! \brief Extract PSS and SSS resource elements @param phy_vars_ue Pointer to UE variables @param[out] pss_ext contain the PSS signals after the extraction @@ -1471,18 +1418,6 @@ void init_transport_channels(uint8_t); void generate_RIV_tables(void); -/*! - \brief This function performs the initial cell search procedure - PSS detection, SSS detection and PBCH detection. At the - end, the basic frame parameters are known (Frame configuration - TDD/FDD and cyclic prefix length, - N_RB_DL, PHICH_CONFIG and Nid_cell) and the UE can begin decoding PDCCH and DLSCH SI to retrieve the rest. Once these - parameters are know, the routine calls some basic initialization routines (cell-specific reference signals, etc.) - @param phy_vars_ue Pointer to UE variables - @param mode current running mode -*/ -int nr_initial_sync(UE_nr_rxtx_proc_t *proc, - PHY_VARS_NR_UE *phy_vars_ue, runmode_t mode); - - /*! \brief Encoding of PUSCH/ACK/RI/ACK from 36-212. @param a Pointer to ulsch SDU @@ -1724,10 +1659,6 @@ uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms, uint8_t n_ra_prboffset, uint8_t tdd_mapindex, uint16_t Nf); -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, - int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common); - - uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset); int nr_rx_pdsch(PHY_VARS_NR_UE *ue, diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index e8a961360f..6c6ff4fd05 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -70,13 +70,12 @@ void free_gNB_ulsch(NR_gNB_ULSCH_t **ulschptr,uint8_t N_RB_UL) a_segments = a_segments/273; } - uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment for (i=0; iharq_processes[i]) { if (ulsch->harq_processes[i]->b) { - free16(ulsch->harq_processes[i]->b,ulsch_bytes); + free16(ulsch->harq_processes[i]->b,a_segments*1056); ulsch->harq_processes[i]->b = NULL; } for (r=0; rC; r++) { E = nr_get_E(G, harq_process->C, Qm, n_layers, r); -#if gNB_TIMING_TRACE - start_meas(ulsch_deinterleaving_stats); -#endif + + start_meas(&phy_vars_gNB->ulsch_deinterleaving_stats); //////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////// nr_deinterleaving_ldpc /////////////////////////////////// @@ -476,13 +474,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, //for (int i =0; i<16; i++) // printf("rx output deinterleaving w[%d]= %d r_offset %d\n", i,harq_process->w[r][i], r_offset); -#if gNB_TIMING_TRACE - stop_meas(ulsch_deinterleaving_stats); -#endif + stop_meas(&phy_vars_gNB->ulsch_deinterleaving_stats); -#if gNB_TIMING_TRACE - start_meas(ulsch_rate_unmatching_stats); -#endif #ifdef DEBUG_ULSCH_DECODING LOG_D(PHY,"HARQ_PID %d Rate Matching Segment %d (coded bits %d,unpunctured/repeated bits %d, TBS %d, mod_order %d, nb_rb %d, Nl %d, rv %d, round %d)...\n", @@ -504,6 +497,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ///////////////////////// harq_process->e =====> harq_process->d ///////////////////////// + start_meas(&phy_vars_gNB->ulsch_rate_unmatching_stats); + Tbslbrm = nr_compute_tbslbrm(0,nb_rb,n_layers,harq_process->C); if (nr_rate_matching_ldpc_rx(Ilbrm, @@ -518,15 +513,13 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, E, harq_process->F, Kr-harq_process->F-2*(p_decParams->Z))==-1) { -#if gNB_TIMING_TRACE - stop_meas(ulsch_rate_unmatching_stats); -#endif + + stop_meas(&phy_vars_gNB->ulsch_rate_unmatching_stats); + LOG_E(PHY,"ulsch_decoding.c: Problem in rate_matching\n"); return (ulsch->max_ldpc_iterations + 1); } else { -#if gNB_TIMING_TRACE - stop_meas(ulsch_rate_unmatching_stats); -#endif + stop_meas(&phy_vars_gNB->ulsch_rate_unmatching_stats); } r_offset += E; @@ -564,9 +557,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, if (err_flag == 0) { -#if gNB_TIMING_TRACE - start_meas(ulsch_turbo_decoding_stats); -#endif + start_meas(&phy_vars_gNB->ulsch_ldpc_decoding_stats); //LOG_E(PHY,"AbsSubframe %d.%d Start LDPC segment %d/%d A %d ",frame%1024,nr_tti_rx,r,harq_process->C-1, A); @@ -636,9 +627,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, //write_output("dec_output.m","dec0",harq_process->c[0],Kr_bytes,1,4); #endif -#if gNB_TIMING_TRACE - stop_meas(ulsch_turbo_decoding_stats); -#endif + stop_meas(&phy_vars_gNB->ulsch_ldpc_decoding_stats); } if ((err_flag == 0) && (ret >= (ulsch->max_ldpc_iterations + 1))) { diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index bce8ddcc29..363b67960d 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -44,7 +44,7 @@ void nr_idft(uint32_t *z, uint32_t Msc_PUSCH) switch (Msc_PUSCH) { case 12: - dft12((int16_t *)idft_in0, (int16_t *)idft_out0); + dft(DFT_12,(int16_t *)idft_in0, (int16_t *)idft_out0,0); #if defined(__x86_64__)||defined(__i386__) norm128 = _mm_set1_epi16(9459); @@ -63,135 +63,135 @@ void nr_idft(uint32_t *z, uint32_t Msc_PUSCH) break; case 24: - dft24(idft_in0, idft_out0, 1); + dft(DFT_24,idft_in0, idft_out0, 1); break; case 36: - dft36(idft_in0, idft_out0, 1); + dft(DFT_36,idft_in0, idft_out0, 1); break; case 48: - dft48(idft_in0, idft_out0, 1); + dft(DFT_48,idft_in0, idft_out0, 1); break; case 60: - dft60(idft_in0, idft_out0, 1); + dft(DFT_60,idft_in0, idft_out0, 1); break; case 72: - dft72(idft_in0, idft_out0, 1); + dft(DFT_72,idft_in0, idft_out0, 1); break; case 96: - dft96(idft_in0, idft_out0, 1); + dft(DFT_96,idft_in0, idft_out0, 1); break; case 108: - dft108(idft_in0, idft_out0, 1); + dft(DFT_108,idft_in0, idft_out0, 1); break; case 120: - dft120(idft_in0, idft_out0, 1); + dft(DFT_120,idft_in0, idft_out0, 1); break; case 144: - dft144(idft_in0, idft_out0, 1); + dft(DFT_144,idft_in0, idft_out0, 1); break; case 180: - dft180(idft_in0, idft_out0, 1); + dft(DFT_180,idft_in0, idft_out0, 1); break; case 192: - dft192(idft_in0, idft_out0, 1); + dft(DFT_192,idft_in0, idft_out0, 1); break; case 216: - dft216(idft_in0, idft_out0, 1); + dft(DFT_216,idft_in0, idft_out0, 1); break; case 240: - dft240(idft_in0, idft_out0, 1); + dft(DFT_240,idft_in0, idft_out0, 1); break; case 288: - dft288(idft_in0, idft_out0, 1); + dft(DFT_288,idft_in0, idft_out0, 1); break; case 300: - dft300(idft_in0, idft_out0, 1); + dft(DFT_300,idft_in0, idft_out0, 1); break; case 324: - dft324((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_324,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 360: - dft360((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_360,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 384: - dft384((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_384,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 432: - dft432((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_432,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 480: - dft480((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_480,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 540: - dft540((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_540,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 576: - dft576((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_576,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 600: - dft600((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_600,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 648: - dft648((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_648,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 720: - dft720((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_720,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 768: - dft768((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_768,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 864: - dft864((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_864,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 900: - dft900((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_900,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 960: - dft960((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_960,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 972: - dft972((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_972,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 1080: - dft1080((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_1080,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 1152: - dft1152((int16_t*)idft_in0, (int16_t*)idft_out0, 1); + dft(DFT_1152,(int16_t*)idft_in0, (int16_t*)idft_out0, 1); break; case 1200: - dft1200(idft_in0, idft_out0, 1); + dft(DFT_1200,idft_in0, idft_out0, 1); break; default: @@ -284,19 +284,17 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, else is_dmrs_re = 0; - if ( ((pusch_pdu->pdu_bit_map)>>2)& 0x01 ) { - is_ptrs_symbol_flag = is_ptrs_symbol(symbol, - (start_re + re)%frame_parms->ofdm_symbol_size, - n_rnti, - pusch_pdu->rb_size, - pusch_pdu->nr_of_symbols, - aarx, - K_ptrs, - pusch_vars->ptrs_symbols, - start_re, - frame_parms->ofdm_symbol_size, - pusch_pdu->dmrs_config_type, - pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset); + if (pusch_pdu->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { + if(is_ptrs_symbol(symbol, pusch_vars->ptrs_symbols)) + is_ptrs_symbol_flag = is_ptrs_subcarrier((start_re + re) % frame_parms->ofdm_symbol_size, + n_rnti, + aarx, + pusch_pdu->dmrs_config_type, + K_ptrs, + pusch_pdu->rb_size, + pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset, + start_re, + frame_parms->ofdm_symbol_size); if (is_ptrs_symbol_flag == 1) num_ptrs_symbols++; @@ -304,7 +302,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, } #ifdef DEBUG_RB_EXT - printf("re = %d, is_dmrs_symbol_flag = %d, symbol = %d\n", re, is_dmrs_symbol_flag, symbol); + printf("re = %d, is_ptrs_symbol_flag = %d, symbol = %d\n", re, is_ptrs_symbol_flag, symbol); #endif if ( is_dmrs_re == 0 && is_ptrs_symbol_flag == 0) { @@ -315,8 +313,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, ul_ch0_ptrs_ext[ul_ch0_ptrs_ext_index] = ul_ch0_ptrs[ul_ch0_ptrs_index]; #ifdef DEBUG_RB_EXT - printf("rxF_ext[%d] = %d\n", rxF_ext_index, rxF_ext[rxF_ext_index]); - printf("rxF_ext[%d] = %d\n", rxF_ext_index+1, rxF_ext[rxF_ext_index+1]); + printf("rxF_ext[%d] = %d, %d\n", rxF_ext_index, rxF_ext[rxF_ext_index], rxF_ext[rxF_ext_index+1]); #endif ul_ch0_ext_index++; @@ -1026,7 +1023,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, unsigned char harq_pid) { - uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag, ptrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol + uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol uint32_t nb_re_pusch, bwp_start_subcarrier; uint8_t L_ptrs = 0; // PTRS parameter int avgs; @@ -1035,7 +1032,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; dmrs_symbol_flag = 0; - ptrs_symbol_flag = 0; first_symbol_flag = 0; gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0; @@ -1046,16 +1042,14 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, gNB->pusch_vars[UE_id]->ptrs_symbols = 0; first_symbol_flag = 1; - if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu + if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { // if there is ptrs pdu L_ptrs = 1<<(rel15_ul->pusch_ptrs.ptrs_time_density); set_ptrs_symb_idx(&gNB->pusch_vars[UE_id]->ptrs_symbols, rel15_ul->nr_of_symbols, rel15_ul->start_symbol_index, - rel15_ul->dmrs_config_type, L_ptrs, - 1, // only dmrs of length 1 is currently supported - frame_parms->ofdm_symbol_size); + rel15_ul->ul_dmrs_symb_pos); } } @@ -1070,30 +1064,16 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; } - if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu - ptrs_symbol_flag = is_ptrs_symbol(symbol, - 0, - rel15_ul->rnti, - rel15_ul->rb_size, - rel15_ul->nr_of_symbols, - 0, - (rel15_ul->pusch_ptrs.ptrs_freq_density)?4:2, - gNB->pusch_vars[UE_id]->ptrs_symbols, - 0, - frame_parms->ofdm_symbol_size, - rel15_ul->dmrs_config_type, - rel15_ul->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset); - } - - if (ptrs_symbol_flag == 1){ - gNB->pusch_vars[UE_id]->ptrs_symbol_index = symbol; + if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { // if there is ptrs pdu + if(is_ptrs_symbol(symbol, gNB->pusch_vars[UE_id]->ptrs_symbols)) + gNB->pusch_vars[UE_id]->ptrs_symbol_index = symbol; } //---------------------------------------------------------- //--------------------- Channel estimation --------------------- //---------------------------------------------------------- - + start_meas(&gNB->ulsch_channel_estimation_stats); if (dmrs_symbol_flag == 1) nr_pusch_channel_estimation(gNB, nr_tti_rx, @@ -1101,17 +1081,19 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, symbol, bwp_start_subcarrier, rel15_ul); - + stop_meas(&gNB->ulsch_channel_estimation_stats); //---------------------------------------------------------- //--------------------- RBs extraction --------------------- //---------------------------------------------------------- + start_meas(&gNB->ulsch_rbs_extraction_stats); nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, gNB->pusch_vars[UE_id], symbol, dmrs_symbol_flag, rel15_ul, frame_parms); + stop_meas(&gNB->ulsch_rbs_extraction_stats); nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, frame_parms, @@ -1140,6 +1122,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, } + start_meas(&gNB->ulsch_channel_compensation_stats); nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, gNB->pusch_vars[UE_id]->ul_ch_mag0, @@ -1152,6 +1135,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, rel15_ul->qam_mod_order, rel15_ul->rb_size, gNB->pusch_vars[UE_id]->log2_maxh); + stop_meas(&gNB->ulsch_channel_compensation_stats); #ifdef NR_SC_FDMA nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); @@ -1160,7 +1144,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, //---------------------------------------------------------- //-------------------- LLRs computation -------------------- //---------------------------------------------------------- - + start_meas(&gNB->ulsch_llr_stats); nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], gNB->pusch_vars[UE_id]->ul_ch_mag0, gNB->pusch_vars[UE_id]->ul_ch_magb0, @@ -1169,6 +1153,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, nb_re_pusch, symbol, rel15_ul->qam_mod_order); + stop_meas(&gNB->ulsch_llr_stats); gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch - gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol; diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index b74b078dfd..6dfbffc46e 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -1,3 +1,34 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/NR_TRANSPORT/pucch_rx.c +* \brief Top-level routines for decoding the PUCCH physical channel +* \author A. Mico Pereperez, Padarthi Naga Prasanth, Francesco Mani, Raymond Knopp +* \date 2020 +* \version 0.2 +* \company Eurecom +* \email: +* \note +* \warning +*/ #include #include #include @@ -8,38 +39,113 @@ #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_common.h" -#include "PHY/defs_nr_UE.h" +#include "PHY/defs_gNB.h" +#include "PHY/sse_intrin.h" #include "PHY/NR_UE_TRANSPORT/pucch_nr.h" -#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" - +#include +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_REFSIG/nr_refsig.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "T.h" +//#define DEBUG_NR_PUCCH_RX 1 + +int get_pucch0_cs_lut_index(PHY_VARS_gNB *gNB,nfapi_nr_pucch_pdu_t* pucch_pdu) { + + int i=0; + +#ifdef DEBUG_NR_PUCCH_RX + printf("getting index for LUT with %d entries, Nid %d\n",gNB->pucch0_lut.nb_id, pucch_pdu->hopping_id); +#endif + + for (i=0;ipucch0_lut.nb_id;i++) { + if (gNB->pucch0_lut.Nid[i] == pucch_pdu->hopping_id) break; + } +#ifdef DEBUG_NR_PUCCH_RX + printf("found index %d\n",i); +#endif + if (ipucch0_lut.nb_id) return(i); + +#ifdef DEBUG_NR_PUCCH_RX + printf("Initializing PUCCH0 LUT index %i with Nid %d\n",i, pucch_pdu->hopping_id); +#endif + // initialize + gNB->pucch0_lut.Nid[gNB->pucch0_lut.nb_id]=pucch_pdu->hopping_id; + for (int slot=0;slot<10<subcarrier_spacing;slot++) + for (int symbol=0;symbol<14;symbol++) + gNB->pucch0_lut.lut[gNB->pucch0_lut.nb_id][slot][symbol] = (int)floor(nr_cyclic_shift_hopping(pucch_pdu->hopping_id,0,0,symbol,0,slot)/0.5235987756); + gNB->pucch0_lut.nb_id++; + return(gNB->pucch0_lut.nb_id-1); +} + + + +int16_t idft12_re[12][12] = { + {23170,23170,23170,23170,23170,23170,23170,23170,23170,23170,23170,23170}, + {23170,20066,11585,0,-11585,-20066,-23170,-20066,-11585,0,11585,20066}, + {23170,11585,-11585,-23170,-11585,11585,23170,11585,-11585,-23170,-11585,11585}, + {23170,0,-23170,0,23170,0,-23170,0,23170,0,-23170,0}, + {23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585}, + {23170,-20066,11585,0,-11585,20066,-23170,20066,-11585,0,11585,-20066}, + {23170,-23170,23170,-23170,23170,-23170,23170,-23170,23170,-23170,23170,-23170}, + {23170,-20066,11585,0,-11585,20066,-23170,20066,-11585,0,11585,-20066}, + {23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585}, + {23170,0,-23170,0,23170,0,-23170,0,23170,0,-23170,0}, + {23170,11585,-11585,-23170,-11585,11585,23170,11585,-11585,-23170,-11585,11585}, + {23170,20066,11585,0,-11585,-20066,-23170,-20066,-11585,0,11585,20066} +}; + +int16_t idft12_im[12][12] = { + {0,0,0,0,0,0,0,0,0,0,0,0}, + {0,11585,20066,23170,20066,11585,0,-11585,-20066,-23170,-20066,-11585}, + {0,20066,20066,0,-20066,-20066,0,20066,20066,0,-20066,-20066}, + {0,23170,0,-23170,0,23170,0,-23170,0,23170,0,-23170}, + {0,20066,-20066,0,20066,-20066,0,20066,-20066,0,20066,-20066}, + {0,11585,-20066,23170,-20066,11585,0,-11585,20066,-23170,20066,-11585}, + {0,0,0,0,0,0,0,0,0,0,0,0}, + {0,-11585,20066,-23170,20066,-11585,0,11585,-20066,23170,-20066,11585}, + {0,-20066,20066,0,-20066,20066,0,-20066,20066,0,-20066,20066}, + {0,-23170,0,23170,0,-23170,0,23170,0,-23170,0,23170}, + {0,-20066,-20066,0,20066,20066,0,-20066,-20066,0,20066,20066}, + {0,-11585,-20066,-23170,-20066,-11585,0,11585,20066,23170,20066,11585} +}; + + +void nr_decode_pucch0(PHY_VARS_gNB *gNB, + int slot, + nfapi_nr_uci_pucch_pdu_format_0_1_t* uci_pdu, + nfapi_nr_pucch_pdu_t* pucch_pdu) { + + + int32_t **rxdataF = gNB->common_vars.rxdataF; + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; -void nr_decode_pucch0( int32_t **rxdataF, - pucch_GroupHopping_t pucch_GroupHopping, - uint32_t n_id, // hoppingID higher layer parameter - uint64_t *payload, - NR_DL_FRAME_PARMS *frame_parms, - int16_t amp, - int nr_tti_tx, - uint8_t m0, // should come from resource set - uint8_t nrofSymbols, // should come from resource set - uint8_t startingSymbolIndex, // should come from resource set - uint16_t startingPRB, // should come from resource set - uint8_t nr_bit) { // is number of UCI bits to be decoded int nr_sequences; const uint8_t *mcs; - if(nr_bit==1){ + + pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1); + + AssertFatal(pucch_pdu->bit_len_harq > 0 || pucch_pdu->sr_flag > 0, + "Either bit_len_harq (%d) or sr_flag (%d) must be > 0\n", + pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); + + if(pucch_pdu->bit_len_harq==0){ mcs=table1_mcs; - nr_sequences=4; + nr_sequences=1; + } + else if(pucch_pdu->bit_len_harq==1){ + mcs=table1_mcs; + nr_sequences=4>>(1-pucch_pdu->sr_flag); } else{ mcs=table2_mcs; - nr_sequences=8; + nr_sequences=8>>(1-pucch_pdu->sr_flag); } + + int cs_ind = get_pucch0_cs_lut_index(gNB,pucch_pdu); /* * Implement TS 38.211 Subclause 6.3.2.3.1 Sequence generation * @@ -53,8 +159,6 @@ void nr_decode_pucch0( int32_t **rxdataF, //uint8_t lnormal; // lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213] //uint8_t lprime; - // mcs is provided by TC 38.213 subclauses 9.2.3, 9.2.4, 9.2.5 FIXME! - //uint8_t mcs; /* * in TS 38.213 Subclause 9.2.1 it is said that: @@ -73,76 +177,76 @@ void nr_decode_pucch0( int32_t **rxdataF, // if frequency hopping is enabled by the higher-layer parameter PUCCH-frequency-hopping // n_hop = 0 for first hop // n_hop = 1 for second hop - uint8_t n_hop = 0; - //uint8_t PUCCH_Frequency_Hopping; // from higher layers FIXME!! + uint8_t n_hop = 0; // Frequnecy hopping not implemented FIXME!! // x_n contains the sequence r_u_v_alpha_delta(n) - int16_t x_n_re[nr_sequences][24],x_n_im[nr_sequences][24]; + int n,i,l; + nr_group_sequence_hopping(pucch_GroupHopping,pucch_pdu->hopping_id,n_hop,slot,&u,&v); // calculating u and v value + + uint32_t re_offset=0; + uint8_t l2; + +#ifdef OLD_IMPL + int16_t x_n_re[nr_sequences][24],x_n_im[nr_sequences][24]; + for(i=0;inr_of_symbols; l++){ + alpha = nr_cyclic_shift_hopping(pucch_pdu->hopping_id,pucch_pdu->initial_cyclic_shift,mcs[i],l,pucch_pdu->start_symbol_index,slot); +#ifdef DEBUG_NR_PUCCH_RX + printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d/%d,mcs %d)\n",u,v,alpha,l,l+pucch_pdu->start_symbol_index,mcs[i]); + printf("lut output %d\n",gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index]); +#endif + alpha=0.0; for (n=0; n<12; n++){ - x_n_re[i][(12*l)+n] = (int16_t)((int32_t)(amp)*(int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15) - - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))>>15); // Re part of base sequence shifted by alpha - x_n_im[i][(12*l)+n] =(int16_t)((int32_t)(amp)* (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) - + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))>>15); // Im part of base sequence shifted by alpha - #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d)\n", - u,v,alpha,l,n,x_n_re[(12*l)+n],x_n_im[(12*l)+n]); - #endif + x_n_re[i][(12*l)+n] = (int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15) + - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))); // Re part of base sequence shifted by alpha + x_n_im[i][(12*l)+n] =(int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) + + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))); // Im part of base sequence shifted by alpha +#ifdef DEBUG_NR_PUCCH_RX + printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d) %d,%d\n", + u,v,alpha,l,n,x_n_re[i][(12*l)+n],x_n_im[i][(12*l)+n], + (int32_t)(round(32767*cos(alpha*n))), + (int32_t)(round(32767*sin(alpha*n)))); +#endif } } } - int16_t r_re[24],r_im[24]; /* - * Implementing TS 38.211 Subclause 6.3.2.3.2 Mapping to physical resources FIXME! + * Implementing TS 38.211 Subclause 6.3.2.3.2 Mapping to physical resources */ - uint32_t re_offset=0; - for (l=0; lN_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is lower band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; - } - if ((startingPRB >= (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is upper band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1))); - } - if ((startingPRB < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is lower band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; - } - if ((startingPRB > (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is upper band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1))) + 6; - } - if ((startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB contains DC - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; - } + + int16_t r_re[24],r_im[24]; + + for (l=0; lnr_of_symbols; l++) { + + l2 = l+pucch_pdu->start_symbol_index; + re_offset = (12*pucch_pdu->prb_start) + (12*pucch_pdu->bwp_start) + frame_parms->first_carrier_offset; + if (re_offset>= frame_parms->ofdm_symbol_size) + re_offset-=frame_parms->ofdm_symbol_size; + for (n=0; n<12; n++){ - if ((n==6) && (startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { - // if number RBs in bandwidth is odd and current PRB contains DC, we need to recalculate the offset when n=6 (for second half PRB) - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size); - } - r_re[(12*l)+n]=((int16_t *)&rxdataF[0][re_offset])[0]; - r_im[(12*l)+n]=((int16_t *)&rxdataF[0][re_offset])[1]; + + r_re[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0]; + r_im[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]; #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch0] mapping to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", - amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,re_offset, - l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]); + printf("\t [nr_generate_pucch0] mapping to RE \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size)+re_offset, + l,n,((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0], + ((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]); #endif re_offset++; + if (re_offset>= frame_parms->ofdm_symbol_size) + re_offset-=frame_parms->ofdm_symbol_size; } - } + } double corr[nr_sequences],corr_re[nr_sequences],corr_im[nr_sequences]; memset(corr,0,nr_sequences*sizeof(double)); memset(corr_re,0,nr_sequences*sizeof(double)); memset(corr_im,0,nr_sequences*sizeof(double)); for(i=0;inr_of_symbols;l++){ for(n=0;n<12;n++){ corr_re[i]+= (double)(r_re[12*l+n])/32767*(double)(x_n_re[i][12*l+n])/32767+(double)(r_im[12*l+n])/32767*(double)(x_n_im[i][12*l+n])/32767; corr_im[i]+= (double)(r_re[12*l+n])/32767*(double)(x_n_im[i][12*l+n])/32767-(double)(r_im[12*l+n])/32767*(double)(x_n_re[i][12*l+n])/32767; @@ -151,14 +255,122 @@ void nr_decode_pucch0( int32_t **rxdataF, corr[i]=corr_re[i]*corr_re[i]+corr_im[i]*corr_im[i]; } float max_corr=corr[0]; - int index=0; + uint8_t index=0; for(i=1;imax_corr){ index= i; max_corr=corr[i]; } } - *payload=(uint64_t)index; // payload bits 00..b3b2b0, b0 is the SR bit and b3b2 are HARQ bits +#else + + const int16_t *x_re = table_5_2_2_2_2_Re[u],*x_im = table_5_2_2_2_2_Im[u]; + int16_t xr[24] __attribute__((aligned(32))); + int16_t xrt[24] __attribute__((aligned(32))); + int32_t xrtmag=0; + int maxpos=0; + int n2=0; + uint8_t index=0; + memset((void*)xr,0,24*sizeof(int16_t)); + + for (l=0; lnr_of_symbols; l++) { + + l2 = l+pucch_pdu->start_symbol_index; + re_offset = (12*pucch_pdu->prb_start) + frame_parms->first_carrier_offset; + if (re_offset>= frame_parms->ofdm_symbol_size) + re_offset-=frame_parms->ofdm_symbol_size; + + AssertFatal(re_offset+12 < frame_parms->ofdm_symbol_size,"pucch straddles DC carrier, handle this!\n"); + + int16_t *r=(int16_t*)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size+re_offset)]; + for (n=0;n<12;n++,n2+=2) { + xr[n2] =(int16_t)(((int32_t)x_re[n]*r[n2]+(int32_t)x_im[n]*r[n2+1])>>15); + xr[n2+1]=(int16_t)(((int32_t)x_re[n]*r[n2+1]-(int32_t)x_im[n]*r[n2])>>15); +#ifdef DEBUG_NR_PUCCH_RX + printf("x (%d,%d), r (%d,%d), xr (%d,%d)\n", + x_re[n],x_im[n],r[n2],r[n2+1],xr[n2],xr[n2+1]); +#endif + } + } + int32_t corr_re,corr_im,temp; + int seq_index; + + for(i=0;inr_of_symbols;l++) { + + seq_index = (pucch_pdu->initial_cyclic_shift+ + mcs[i]+ + gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index])%12; + for (n=0;n<12;n++,n2+=2) { + corr_re+=(xr[n2]*idft12_re[seq_index][n]+xr[n2+1]*idft12_im[seq_index][n])>>15; + corr_im+=(xr[n2]*idft12_im[seq_index][n]-xr[n2+1]*idft12_re[seq_index][n])>>15; + } + } + +#ifdef DEBUG_NR_PUCCH_RX + printf("PUCCH IDFT[%d/%d] = (%d,%d)=>%f\n",mcs[i],seq_index,corr_re,corr_im,10*log10(corr_re*corr_re + corr_im*corr_im)); +#endif + if ((temp=corr_re*corr_re + corr_im*corr_im)>xrtmag) { + xrtmag=temp; + maxpos=i; + } + } + + uint8_t xrtmag_dB = dB_fixed(xrtmag); + +#ifdef DEBUG_NR_PUCCH_RX + printf("PUCCH 0 : maxpos %d\n",maxpos); +#endif + + index=maxpos; +#endif + // first bit of bitmap for sr presence and second bit for acknack presence + uci_pdu->pdu_bit_map = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1); + uci_pdu->pucch_format = 0; // format 0 + uci_pdu->ul_cqi = 0xff; // currently not valid + uci_pdu->timing_advance = 0xffff; // currently not valid + uci_pdu->rssi = 0xffff; // currently not valid + + if (pucch_pdu->bit_len_harq==0) { + uci_pdu->harq = NULL; + uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr)); + if (xrtmag_dB>(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres)) { + uci_pdu->sr->sr_indication = 1; + uci_pdu->sr->sr_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); + } else { + uci_pdu->sr->sr_indication = 0; + uci_pdu->sr->sr_confidence_level = (gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres)-xrtmag_dB; + } + } + else if (pucch_pdu->bit_len_harq==1) { + uci_pdu->harq = calloc(1,sizeof(*uci_pdu->harq)); + uci_pdu->harq->num_harq = 1; + uci_pdu->harq->harq_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); + uci_pdu->harq->harq_list = (nfapi_nr_harq_t*)malloc(1); + uci_pdu->harq->harq_list[0].harq_value = index&0x01; + if (pucch_pdu->sr_flag == 1) { + uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr)); + uci_pdu->sr->sr_indication = (index>1) ? 1 : 0; + uci_pdu->sr->sr_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); + } + } + else { + uci_pdu->harq = calloc(1,sizeof(*uci_pdu->harq)); + uci_pdu->harq->num_harq = 2; + uci_pdu->harq->harq_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); + uci_pdu->harq->harq_list = (nfapi_nr_harq_t*)malloc(2); + + uci_pdu->harq->harq_list[0].harq_value = index&0x01; + uci_pdu->harq->harq_list[1].harq_value = (index>>1)&0x01; + + if (pucch_pdu->sr_flag == 1) { + uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr)); + uci_pdu->sr->sr_indication = (index>3) ? 1 : 0; + uci_pdu->sr->sr_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); + } + } } @@ -180,7 +392,7 @@ void nr_decode_pucch1( int32_t **rxdataF, uint8_t timeDomainOCC, uint8_t nr_bit) { #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch1] start function at slot(nr_tti_tx)=%d payload=%d m0=%d nrofSymbols=%d startingSymbolIndex=%d startingPRB=%d startingPRB_intraSlotHopping=%d timeDomainOCC=%d nr_bit=%d\n", + printf("\t [nr_generate_pucch1] start function at slot(nr_tti_tx)=%d payload=%lp m0=%d nrofSymbols=%d startingSymbolIndex=%d startingPRB=%d startingPRB_intraSlotHopping=%d timeDomainOCC=%d nr_bit=%d\n", nr_tti_tx,payload,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,timeDomainOCC,nr_bit); #endif /* @@ -190,7 +402,7 @@ void nr_decode_pucch1( int32_t **rxdataF, // complex-valued symbol d_re, d_im containing complex-valued symbol d(0): int16_t d_re=0, d_im=0,d1_re=0,d1_im=0; #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch1] sequence modulation: payload=%x \tde_re=%d \tde_im=%d\n",payload,d_re,d_im); + printf("\t [nr_generate_pucch1] sequence modulation: payload=%lp \tde_re=%d \tde_im=%d\n",payload,d_re,d_im); #endif /* * Defining cyclic shift hopping TS 38.211 Subclause 6.3.2.2.2 @@ -274,7 +486,6 @@ void nr_decode_pucch1( int32_t **rxdataF, re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; } - //txptr = &txdataF[0][re_offset]; for (int n=0; n<12; n++) { if ((n==6) && (startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB contains DC, we need to recalculate the offset when n=6 (for second half PRB) @@ -285,9 +496,9 @@ void nr_decode_pucch1( int32_t **rxdataF, z_re_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[0]; z_im_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[1]; #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch1] mapping PUCCH to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_pucch[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + printf("\t [nr_generate_pucch1] mapping PUCCH to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_pucch[%d]=txptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n", amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+n,re_offset, - l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]); + l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]); #endif } @@ -296,9 +507,9 @@ void nr_decode_pucch1( int32_t **rxdataF, z_dmrs_im_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[1]; // printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch1] mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + printf("\t [nr_generate_pucch1] mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n", amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+n,re_offset, - l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]); + l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]); #endif // printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); } @@ -409,7 +620,7 @@ void nr_decode_pucch1( int32_t **rxdataF, mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n], table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n], - z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif // multiplying with conjugate of low papr sequence z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) @@ -443,7 +654,7 @@ void nr_decode_pucch1( int32_t **rxdataF, mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n], table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n], - z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif //finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) @@ -494,7 +705,7 @@ void nr_decode_pucch1( int32_t **rxdataF, mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n], table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n], - z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); @@ -522,7 +733,7 @@ void nr_decode_pucch1( int32_t **rxdataF, mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n], table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n], - z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif //finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) @@ -641,3 +852,496 @@ void nr_decode_pucch1( int32_t **rxdataF, } } +__m256i pucch2_3bit[8*2]; +__m256i pucch2_4bit[16*2]; +__m256i pucch2_5bit[32*2]; +__m256i pucch2_6bit[64*2]; +__m256i pucch2_7bit[128*2]; +__m256i pucch2_8bit[256*2]; +__m256i pucch2_9bit[512*2]; +__m256i pucch2_10bit[1024*2]; +__m256i pucch2_11bit[2048*2]; + +__m256i *pucch2_lut[9]={pucch2_3bit, + pucch2_4bit, + pucch2_5bit, + pucch2_6bit, + pucch2_7bit, + pucch2_8bit, + pucch2_9bit, + pucch2_10bit, + pucch2_11bit}; + +void init_pucch2_luts() { + + uint32_t out; + int8_t bit; + + for (int b=3;b<12;b++) { + for (uint16_t i=0;i<(1< 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,0); + bit = (out&0x2) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,0); + bit = (out&0x4) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,1); + bit = (out&0x8) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,1); + bit = (out&0x10) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,2); + bit = (out&0x20) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,2); + bit = (out&0x40) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,3); + bit = (out&0x80) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,3); + bit = (out&0x100) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,4); + bit = (out&0x200) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,4); + bit = (out&0x400) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,5); + bit = (out&0x800) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,5); + bit = (out&0x1000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,6); + bit = (out&0x2000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,6); + bit = (out&0x4000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,7); + bit = (out&0x8000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,7); + bit = (out&0x10000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,8); + bit = (out&0x20000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,8); + bit = (out&0x40000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,9); + bit = (out&0x80000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,9); + bit = (out&0x100000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,10); + bit = (out&0x200000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,10); + bit = (out&0x400000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,11); + bit = (out&0x800000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,11); + bit = (out&0x1000000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,12); + bit = (out&0x2000000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,12); + bit = (out&0x4000000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,13); + bit = (out&0x8000000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,13); + bit = (out&0x10000000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,14); + bit = (out&0x20000000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,14); + bit = (out&0x40000000) > 0 ? -1 : 1; + *lut_i = _mm256_insert_epi16(*lut_i,bit,15); + bit = (out&0x80000000) > 0 ? -1 : 1; + *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,15); + } + } +} + + +void nr_decode_pucch2(PHY_VARS_gNB *gNB, + int slot, + nfapi_nr_uci_pucch_pdu_format_2_3_4_t* uci_pdu, + nfapi_nr_pucch_pdu_t* pucch_pdu) { + + int32_t **rxdataF = gNB->common_vars.rxdataF; + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; + pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1); + + AssertFatal(pucch_pdu->nr_of_symbols==1 || pucch_pdu->nr_of_symbols==2, + "Illegal number of symbols for PUCCH 2 %d\n",pucch_pdu->nr_of_symbols); + + + //extract pucch and dmrs first + + int l2=-1; + int re_offset = (12*pucch_pdu->prb_start) + (12*pucch_pdu->bwp_start) + frame_parms->first_carrier_offset; + if (re_offset>= frame_parms->ofdm_symbol_size) + re_offset-=frame_parms->ofdm_symbol_size; + + AssertFatal(pucch_pdu->prb_size*pucch_pdu->nr_of_symbols > 1,"number of PRB*SYMB (%d,%d)< 2", + pucch_pdu->prb_size,pucch_pdu->nr_of_symbols); + + int Prx = gNB->gNB_config.carrier_config.num_rx_ant.value; + int Prx2 = (Prx==1)?2:Prx; + // use 2 for Nb antennas in case of single antenna to allow the following allocations + int16_t r_re_ext[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t r_im_ext[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t r_re_ext2[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t r_im_ext2[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t rd_re_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t rd_im_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + + int16_t *rp[Prx2]; + __m64 dmrs_re,dmrs_im; + + for (int aa=0;aaofdm_symbol_size)+re_offset]); + +#ifdef DEBUG_NR_PUCCH_RX + printf("Decoding pucch2 for %d symbols, %d PRB\n",pucch_pdu->nr_of_symbols,pucch_pdu->prb_size); +#endif + + int nc_group_size=1; // 2 PRB + int ngroup = pucch_pdu->prb_size/nc_group_size/2; + int32_t corr32_re[ngroup][Prx2],corr32_im[ngroup][Prx2]; + for (int aa=0;aanr_of_symbols == 1) { + AssertFatal((pucch_pdu->prb_size&1) == 0,"prb_size %d is not a multiple of 2\n",pucch_pdu->prb_size); + // 24 PRBs contains 48x16-bit, so 6x8x16-bit + for (int prb=0;prbprb_size;prb+=2) { + for (int aa=0;aa (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext[aa][i],rd_im_ext[aa]); +#endif + } // aa + } // prb + + + // first compute DMRS component + uint32_t x1, x2, s=0; + x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause +#ifdef DEBUG_NR_PUCCH_RX + printf("slot %d, start_symbol_index %d, dmrs_scrambling_id %d\n", + slot,pucch_pdu->start_symbol_index,pucch_pdu->dmrs_scrambling_id); +#endif + s = lte_gold_generic(&x1, &x2, 1); + + + for (int group=0;group>=5; + corr32_im[group][aa]>>=5; +#ifdef DEBUG_NR_PUCCH_RX + printf("Group %d: corr32 (%d,%d)\n",group,corr32_re[group][aa],corr32_im[group][aa]); +#endif + } //aa + + if ((group&3) == 3) s = lte_gold_generic(&x1, &x2, 0); + } // group + } + else { // 2 symbol case + AssertFatal(1==0, "Fill in 2 symbol PUCCH2 case\n"); + } + + uint32_t x1, x2, s=0; + // unscrambling + x2 = ((pucch_pdu->rnti)<<15)+pucch_pdu->data_scrambling_id; + s = lte_gold_generic(&x1, &x2, 1); +#ifdef DEBUG_NR_PUCCH_RX + printf("x2 %x, s %x\n",x2,s); +#endif + __m64 c_re0,c_im0,c_re1,c_im1,c_re2,c_im2,c_re3,c_im3; + re_offset=0; + for (int prb=0;prbprb_size;prb+=2,re_offset+=16) { + c_re0 = byte2m64_re[((uint8_t*)&s)[0]]; + c_im0 = byte2m64_im[((uint8_t*)&s)[0]]; + c_re1 = byte2m64_re[((uint8_t*)&s)[1]]; + c_im1 = byte2m64_im[((uint8_t*)&s)[1]]; + c_re2 = byte2m64_re[((uint8_t*)&s)[2]]; + c_im2 = byte2m64_im[((uint8_t*)&s)[2]]; + c_re3 = byte2m64_re[((uint8_t*)&s)[3]]; + c_im3 = byte2m64_im[((uint8_t*)&s)[3]]; + + for (int aa=0;aabit_len_csi_part1 + pucch_pdu->bit_len_csi_part2 == 0,"no csi for now\n"); + AssertFatal((pucch_pdu->bit_len_harq+pucch_pdu->sr_flag > 2 ) && (pucch_pdu->bit_len_harq+pucch_pdu->sr_flag < 12),"illegal length (%d,%d)\n",pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); + int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag; + __m256i *rp_re[Prx2]; + __m256i *rp2_re[Prx2]; + __m256i *rp_im[Prx2]; + __m256i *rp2_im[Prx2]; + for (int aa=0;aa>1], + ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[1+(i>>1)]); + } + printf("\n"); +#endif + // do complex correlation + for (int aa=0;aa corr) { + corr = corr_tmp; + cw_ML=cw; + } + } + uint8_t corr_dB = dB_fixed64((uint64_t)corr); + LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB); + uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; + + + int harq_bytes=pucch_pdu->bit_len_harq>>3; + if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; + uci_pdu->harq.harq_payload = (uint8_t*)malloc(harq_bytes); + uci_pdu->harq.harq_crc = 2; + for (int i=0;iharq.harq_payload[i] = cw_ML & 255; + cw_ML>>=8; + } + + if (pucch_pdu->sr_flag == 1) { + uci_pdu->sr.sr_bit_len = 1; + uci_pdu->sr.sr_payload = malloc(1); + uci_pdu->sr.sr_payload[0] = cw_ML; + } +} + diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c index cc22e5f7d7..7f5872e885 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c @@ -23,7 +23,6 @@ #include "PHY/defs_nr_UE.h" #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" #include "PHY/impl_defs_top.h" -//#include "openair2/LAYER2/MAC/mac_proto.h" #include "common/utils/LOG/vcd_signal_dumper.h" diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c index be5c754beb..71a5771f5b 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c @@ -405,39 +405,39 @@ int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue, } - void (*idft)(int16_t *,int16_t *, int); + idft_size_idx_t idftsizeidx; switch (ue->frame_parms.ofdm_symbol_size) { case 128: - idft = idft128; + idftsizeidx = IDFT_128; break; case 256: - idft = idft256; + idftsizeidx = IDFT_256; break; case 512: - idft = idft512; + idftsizeidx = IDFT_512; break; case 1024: - idft = idft1024; + idftsizeidx = IDFT_1024; break; case 1536: - idft = idft1536; + idftsizeidx = IDFT_1536; break; case 2048: - idft = idft2048; + idftsizeidx = IDFT_2048; break; case 3072: - idft = idft3072; + idftsizeidx = IDFT_3072; break; case 4096: - idft = idft4096; + idftsizeidx = IDFT_4096; break; default: @@ -453,7 +453,8 @@ int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue, if (ue->pbch_vars[eNB_offset]->dl_ch_estimates[(p<<1)+aarx]) { LOG_D(PHY,"Channel Impulse Computation Slot %d ThreadId %d Symbol %d ch_offset %d\n", Ns, ue->current_thread_id[Ns], symbol, ch_offset); - idft((int16_t*) &ue->pbch_vars[eNB_offset]->dl_ch_estimates[(p<<1)+aarx][ch_offset], + idft(idftsizeidx, + (int16_t*) &ue->pbch_vars[eNB_offset]->dl_ch_estimates[(p<<1)+aarx][ch_offset], (int16_t*) ue->pbch_vars[eNB_offset]->dl_ch_estimates_time[(p<<1)+aarx],1); } } @@ -617,7 +618,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PDCCH - printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); #endif multadd_real_vector_complex_scalar(fr, diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h index 95b6cfd2e2..5f1321dd32 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h @@ -29,6 +29,10 @@ * \note * \warning */ + +#ifndef __PHY_NR_UE_TRANSPORT_DCI_NR__H__ +#define __PHY_NR_UE_TRANSPORT_DCI_NR__H__ + #ifndef USER_MODE #include "PHY/types.h" #else @@ -118,4 +122,5 @@ typedef struct NR_DCI_INFO_EXTRACTED NR_DCI_INFO_EXTRACTED_t; #endif +#endif diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index 00167507ce..e5cbc4e07a 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -69,12 +69,11 @@ void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr,uint8_t N_RB_DL) a_segments = a_segments/273; } - uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment for (i=0; iMdlharq; i++) { if (dlsch->harq_processes[i]) { if (dlsch->harq_processes[i]->b) { - free16(dlsch->harq_processes[i]->b,dlsch_bytes); + free16(dlsch->harq_processes[i]->b,a_segments*1056); dlsch->harq_processes[i]->b = NULL; } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index f407119024..013b5ca4a6 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -38,8 +38,10 @@ #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" +#include #include "T.h" +#include @@ -88,7 +90,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t *prach_root_sequence_map; uint16_t preamble_offset,preamble_shift; uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar; - uint16_t d_start,numshift; + uint16_t d_start=-1,numshift; uint16_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); //uint8_t Nsp=2; @@ -398,7 +400,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // This is after cyclic prefix (Ncp<<1 samples for 30.72 Ms/s, Ncp<<2 samples for 61.44 Ms/s prach2 = prach+(Ncp<<1); if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft49152(prachF,prach2,1); + idft(IDFT_49152,prachF,prach2,1); // here we have |empty | Prach49152| memmove(prach,prach+(49152<<1),(Ncp<<3)); // here we have |Prefix | Prach49152| @@ -406,7 +408,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, dftlen=49152; } else if (prach_fmt == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft49152(prachF,prach2,1); + idft(IDFT_49152,prachF,prach2,1); memmove(prach2+(49152<<1),prach2,(49152<<2)); // here we have |empty | Prach49152 | Prach49152| memmove(prach,prach+(49152<<2),(Ncp<<3)); @@ -415,7 +417,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, dftlen=49152; } else if (prach_fmt == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft49152(prachF,prach2,1); + idft(IDFT_49152,prachF,prach2,1); memmove(prach2+(49152<<1),prach2,(49152<<2)); // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 memmove(prach2+(49152<<2),prach2,(49152<<3)); @@ -426,7 +428,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, dftlen=49152; } else if (prach_fmt == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s - idft12288(prachF,prach2,1); + idft(IDFT_12288,prachF,prach2,1); memmove(prach2+(12288<<1),prach2,(12288<<2)); // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 memmove(prach2+(12288<<2),prach2,(12288<<3)); @@ -438,7 +440,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); + idft(IDFT_2048,prachF,prach2,1); dftlen=2048; // here we have |empty | Prach2048 | if (prach_fmt != 0xc0) { @@ -450,7 +452,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x2048 - idft2048(prachF,prach2,1); + idft(IDFT_2048,prachF,prach2,1); dftlen=2048; // here we have |empty | Prach2048 | memmove(prach2+(2048<<1),prach2,(2048<<2)); @@ -463,7 +465,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x2048 prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); + idft(IDFT_2048,prachF,prach2,1); dftlen=2048; // here we have |empty | Prach2048 | memmove(prach2+(2048<<1),prach2,(2048<<2)); @@ -477,7 +479,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (2048*6)+Ncp; } else if (prach_fmt == 0xb4) { // 12x2048 - idft2048(prachF,prach2,1); + idft(IDFT_2048,prachF,prach2,1); dftlen=2048; // here we have |empty | Prach2048 | memmove(prach2+(2048<<1),prach2,(2048<<2)); @@ -498,7 +500,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, Ncp = (Ncp*3)/2; prach2 = prach+(Ncp<<1); if (prach_fmt == 0) { - idft36864(prachF,prach2,1); + idft(IDFT_36864,prachF,prach2,1); dftlen=36864; // here we have |empty | Prach73728| memmove(prach,prach+(36864<<1),(Ncp<<2)); @@ -506,7 +508,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (36864*1)+Ncp; } else if (prach_fmt == 1) { - idft36864(prachF,prach2,1); + idft(IDFT_36864,prachF,prach2,1); dftlen=36864; memmove(prach2+(36864<<1),prach2,(36864<<2)); // here we have |empty | Prach73728 | Prach73728| @@ -515,7 +517,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (36864*2)+Ncp; } if (prach_fmt == 2) { - idft36864(prachF,prach2,1); + idft(IDFT_36864,prachF,prach2,1); dftlen=36864; memmove(prach2+(36864<<1),prach2,(36864<<2)); // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 @@ -526,7 +528,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (36864*4)+Ncp; } else if (prach_fmt == 3) { - idft9216(prachF,prach2,1); + idft(IDFT_9216,prachF,prach2,1); dftlen=36864; memmove(prach2+(9216<<1),prach2,(9216<<2)); // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216 @@ -537,7 +539,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (9216*4)+Ncp; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - idft1536(prachF,prach2,1); + idft(IDFT_1536,prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | if (prach_fmt != 0xc0) @@ -547,7 +549,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (1536*2)+Ncp; } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536 - idft1536(prachF,prach2,1); + idft(IDFT_1536,prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | memmove(prach2+(1536<<1),prach2,(1536<<2)); @@ -559,7 +561,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (1536*4)+Ncp; } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x1536 - idft1536(prachF,prach2,1); + idft(IDFT_1536,prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | memmove(prach2+(1536<<1),prach2,(1536<<2)); @@ -573,7 +575,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (1536*6)+Ncp; } else if (prach_fmt == 0xb4) { // 12x1536 - idft1536(prachF,prach2,1); + idft(IDFT_1536,prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | memmove(prach2+(1536<<1),prach2,(1536<<2)); @@ -595,7 +597,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, Ncp<<=2; prach2 = prach+(Ncp<<1); if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s - idft98304(prachF,prach2,1); + idft(IDFT_98304,prachF,prach2,1); dftlen=98304; // here we have |empty | Prach98304| memmove(prach,prach+(98304<<1),(Ncp<<2)); @@ -603,7 +605,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (98304*1)+Ncp; } else if (prach_fmt == 1) { - idft98304(prachF,prach2,1); + idft(IDFT_98304,prachF,prach2,1); dftlen=98304; memmove(prach2+(98304<<1),prach2,(98304<<2)); // here we have |empty | Prach98304 | Prach98304| @@ -612,7 +614,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (98304*2)+Ncp; } else if (prach_fmt == 2) { - idft98304(prachF,prach2,1); + idft(IDFT_98304,prachF,prach2,1); dftlen=98304; memmove(prach2+(98304<<1),prach2,(98304<<2)); // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304 @@ -623,7 +625,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (98304*4)+Ncp; } else if (prach_fmt == 3) { // 4x6144, Ncp 3168 - idft24576(prachF,prach2,1); + idft(IDFT_24576,prachF,prach2,1); dftlen=24576; memmove(prach2+(24576<<1),prach2,(24576<<2)); // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576 @@ -634,7 +636,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (24576*4)+(Ncp<<1); } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - idft4096(prachF,prach2,1); + idft(IDFT_4096,prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | if (prach_fmt != 0xc0) { @@ -647,7 +649,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x4096 - idft4096(prachF,prach2,1); + idft(IDFT_4096,prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | memmove(prach2+(4096<<1),prach2,(4096<<2)); @@ -659,7 +661,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (4096*4)+Ncp; } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x4096 - idft4096(prachF,prach2,1); + idft(IDFT_4096,prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | memmove(prach2+(4096<<1),prach2,(4096<<2)); @@ -673,7 +675,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (4096*6)+Ncp; } else if (prach_fmt == 0xb4) { // 12x4096 - idft4096(prachF,prach2,1); + idft(IDFT_4096,prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | memmove(prach2+(4096<<1),prach2,(4096<<2)); @@ -693,7 +695,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, Ncp = (Ncp*3); prach2 = prach+(Ncp<<1); if (prach_fmt == 0) { - idft73728(prachF,prach2,1); + idft(IDFT_73728,prachF,prach2,1); dftlen=73728; // here we have |empty | Prach73728| memmove(prach,prach+(73728<<1),(Ncp<<4)); @@ -701,7 +703,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (73728*1)+Ncp; } else if (prach_fmt == 1) { - idft73728(prachF,prach2,1); + idft(IDFT_73728,prachF,prach2,1); dftlen=73728; memmove(prach2+(73728<<1),prach2,(73728<<2)); // here we have |empty | Prach73728 | Prach73728| @@ -710,7 +712,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (73728*2)+Ncp; } if (prach_fmt == 2) { - idft73728(prachF,prach2,1); + idft(IDFT_73728,prachF,prach2,1); dftlen=73728; memmove(prach2+(73728<<1),prach2,(73728<<2)); // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 @@ -721,7 +723,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (73728*4)+Ncp; } else if (prach_fmt == 3) { - idft18432(prachF,prach2,1); + idft(IDFT_18432,prachF,prach2,1); dftlen=18432; memmove(prach2+(18432<<1),prach2,(18432<<2)); // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 @@ -732,7 +734,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (18432*4)+Ncp; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | if (prach_fmt != 0xc0) { @@ -744,7 +746,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x3072 - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | memmove(prach2+(3072<<1),prach2,(3072<<2)); @@ -758,7 +760,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (3072*6)+Ncp; } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x3072 - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | memmove(prach2+(3072<<1),prach2,(3072<<2)); @@ -770,7 +772,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, prach_len = (3072*4)+Ncp; } else if (prach_fmt == 0xb4) { // 12x3072 - idft3072(prachF,prach2,1); + idft(IDFT_3072,prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | memmove(prach2+(3072<<1),prach2,(3072<<2)); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index 35fe8bc899..4aae9ef7b4 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -1053,7 +1053,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, NR_DL_FRAME_PARMS* frame_parms, - uint8_t harq_pid); + uint8_t harq_pid, + unsigned int G); /*! \brief Perform PUSCH scrambling. TS 38.211 V15.4.0 subclause 6.3.1.1 @param[in] in, Pointer to input bits diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h index fb560f229d..bb92508934 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h @@ -43,7 +43,7 @@ #endif #include "LAYER2/NR_MAC_gNB/mac_proto.h" - +#include "openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h" //#include "../LTE_TRANSPORT/transport_common.h" // structures below implement 36-211 and 36-212 @@ -86,40 +86,26 @@ typedef struct { #endif typedef struct { + /// NDAPI struct for UE + nfapi_nr_ue_pusch_pdu_t pusch_pdu; /// Indicator of first transmission uint8_t first_tx; - /// Last Ndi received for this process on DCI (used for C-RNTI only) - uint8_t DCINdi; /// HARQ tx status harq_result_t tx_status; - /// Flag indicating that this ULSCH has a new packet (start of new round) - // uint8_t Ndi; /// Status Flag indicating for this ULSCH (idle,active,disabled) SCH_status_t status; /// Subframe scheduling indicator (i.e. Transmission opportunity indicator) uint8_t subframe_scheduling_flag; /// Subframe cba scheduling indicator (i.e. Transmission opportunity indicator) uint8_t subframe_cba_scheduling_flag; - /// First Allocated RB - uint16_t first_rb; - /// Current Number of RBs - uint16_t nb_rb; - /// number of layers - uint8_t Nl; /// Last TPC command uint8_t TPC; - /// Transport block size - uint32_t TBS; /// The payload + CRC size in bits, "B" from 36-212 uint32_t B; /// Length of ACK information (bits) uint8_t O_ACK; /// Index of current HARQ round for this ULSCH uint8_t round; - /// MCS format of this ULSCH - uint8_t mcs; - /// Redundancy-version of the current sub-frame - uint8_t rvidx; /// pointer to pdu from MAC interface (TS 36.212 V15.4.0, Sec 5.1 p. 8) unsigned char *a; /// Pointer to the payload + CRC @@ -152,19 +138,11 @@ typedef struct { uint32_t G; // Number of modulated symbols carrying data uint32_t num_of_mod_symbols; - // This is "L" in TS 38.214 V15.4.0 subclause 6.1.2.1 - uint8_t number_of_symbols; - // This is "S" in TS 38.214 V15.4.0 subclause 6.1.2.1 - uint8_t start_symbol; // decode phich uint8_t decode_phich; } NR_UL_UE_HARQ_t; typedef struct { - /// number of DMRS resource elements - uint8_t nb_re_dmrs; - /// DMRS length - uint8_t length_dmrs; /// SRS active flag uint8_t srs_active; //#if defined(UPGRADE_RAT_NR) @@ -226,8 +204,6 @@ typedef struct { uint8_t power_offset; // for cooperative communication uint8_t cooperation_flag; - /// RNTI attributed to this ULSCH - uint16_t rnti; /// RNTI type uint8_t rnti_type; /// Cell ID diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c index 55bac90520..7299b085bb 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c @@ -60,17 +60,16 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulschptr,unsigned char N_RB_UL) a_segments = a_segments/273; } - uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment for (i=0; iharq_processes[i]) { if (ulsch->harq_processes[i]->a) { - free16(ulsch->harq_processes[i]->a,ulsch_bytes); + free16(ulsch->harq_processes[i]->a,a_segments*1056); ulsch->harq_processes[i]->a = NULL; } if (ulsch->harq_processes[i]->b) { - free16(ulsch->harq_processes[i]->b,ulsch_bytes); + free16(ulsch->harq_processes[i]->b,a_segments*1056); ulsch->harq_processes[i]->b = NULL; } if (ulsch->harq_processes[i]->e) { @@ -217,12 +216,13 @@ NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL, int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, NR_DL_FRAME_PARMS* frame_parms, - uint8_t harq_pid) + uint8_t harq_pid, + unsigned int G) { /////////////////////////parameters and variables declaration///////////////////////// /////////// - unsigned int G,crc; + unsigned int crc; NR_UL_UE_HARQ_t *harq_process; uint16_t nb_rb ; uint8_t nb_symb_sch ; @@ -235,8 +235,6 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, uint32_t E,Kb; uint8_t Ilbrm; uint32_t Tbslbrm; - uint8_t nb_re_dmrs; - uint16_t length_dmrs; uint16_t R; float Coderate; @@ -249,20 +247,17 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, crc = 1; harq_process = ulsch->harq_processes[harq_pid]; - nb_rb = harq_process->nb_rb; - nb_symb_sch = harq_process->number_of_symbols; - A = harq_process->TBS; + nb_rb = harq_process->pusch_pdu.rb_size; + A = harq_process->pusch_pdu.pusch_data.tb_size; pz = &Z; - mod_order = nr_get_Qm_ul(harq_process->mcs,0); - R = nr_get_code_rate_ul(harq_process->mcs, 0); + mod_order = nr_get_Qm_ul(harq_process->pusch_pdu.mcs_index, harq_process->pusch_pdu.mcs_table); + R = nr_get_code_rate_ul(harq_process->pusch_pdu.mcs_index, harq_process->pusch_pdu.mcs_table); Kr=0; r_offset=0; BG = 1; F=0; Ilbrm = 0; Tbslbrm = 950984; //max tbs - nb_re_dmrs = ulsch->nb_re_dmrs; - length_dmrs = ulsch->length_dmrs; Coderate = 0.0; /////////// @@ -271,10 +266,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); - LOG_D(PHY,"ulsch coding nb_rb %d nb_symb_sch %d nb_re_dmrs %d, length_dmrs %d, harq_process->Nl = %d\n", nb_rb,nb_symb_sch, nb_re_dmrs,length_dmrs, harq_process->Nl); - - - G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs,mod_order,harq_process->Nl); + LOG_D(PHY,"ulsch coding nb_rb %d, Nl = %d\n", nb_rb, harq_process->pusch_pdu.nrOfLayers); LOG_D(PHY,"ulsch coding A %d G %d mod_order %d\n", A,G, mod_order); // if (harq_process->Ndi == 1) { // this is a new packet @@ -356,11 +348,6 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, Kr_bytes = Kr>>3; #endif -/////////// -///////////////////////////////////////////////////////////////////////////////////// - -opp_enabled=0; - ///////////////////////// c---->| LDCP coding |---->d ///////////////////////// /////////// @@ -386,6 +373,12 @@ opp_enabled=0; //for (int i=0;i<68*384;i++) // printf("channel_input[%d]=%d\n",i,channel_input[i]); + int temp_opp = 0; + + if (opp_enabled) { + opp_enabled = 0; + temp_opp = 1; + } /*printf("output %d %d %d %d %d \n", harq_process->d[0][0], harq_process->d[0][1], harq_process->d[r][2],harq_process->d[0][3], harq_process->d[0][4]); @@ -402,10 +395,12 @@ opp_enabled=0; //stop_meas(te_stats); //printf("end ldpc encoder -- output\n"); #ifdef DEBUG_DLSCH_CODING - write_output("ulsch_enc_input0.m","enc_in0",&harq_process->c[0][0],Kr_bytes,1,4); - write_output("ulsch_enc_output0.m","enc0",&harq_process->d[0][0],(3*8*Kr_bytes)+12,1,4); + write_output("ulsch_enc_input0.m","enc_in0",&harq_process->c[0][0],Kr_bytes,1,4); + write_output("ulsch_enc_output0.m","enc0",&harq_process->d[0][0],(3*8*Kr_bytes)+12,1,4); #endif + if (temp_opp) opp_enabled = 1; + /////////// /////////////////////////////////////////////////////////////////////////////// @@ -431,15 +426,15 @@ opp_enabled=0; //start_meas(rm_stats); #ifdef DEBUG_DLSCH_CODING - printf("rvidx in encoding = %d\n", harq_process->rvidx); + printf("rvidx in encoding = %d\n", harq_process->pusch_pdu.pusch_data.rv_index); #endif ///////////////////////// d---->| Rate matching bit selection |---->e ///////////////////////// /////////// - E = nr_get_E(G, harq_process->C, mod_order, harq_process->Nl, r); + E = nr_get_E(G, harq_process->C, mod_order, harq_process->pusch_pdu.nrOfLayers, r); - Tbslbrm = nr_compute_tbslbrm(0,nb_rb,harq_process->Nl,harq_process->C); + Tbslbrm = nr_compute_tbslbrm(0,nb_rb,harq_process->pusch_pdu.nrOfLayers,harq_process->C); nr_rate_matching_ldpc(Ilbrm, Tbslbrm, @@ -450,7 +445,7 @@ opp_enabled=0; harq_process->C, F, Kr-F-2*(*pz), - harq_process->rvidx, + harq_process->pusch_pdu.pusch_data.rv_index, E); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index f1d4a304f9..69b3421ace 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -98,7 +98,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t thread_id, int gNB_id) { - uint32_t available_bits; + uint32_t available_bits, TBS; uint8_t mod_order, cwd_index, num_of_codewords, l; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; uint32_t ***pusch_dmrs; @@ -106,67 +106,66 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, int32_t **txdataF; uint16_t start_sc, start_rb; int8_t Wf[2], Wt[2], l_prime[2], delta; - uint16_t n_dmrs, code_rate, number_dmrs_symbols, k; - uint8_t dmrs_type; + uint16_t rnti, n_dmrs, code_rate, number_dmrs_symbols, nb_rb, k; + uint8_t dmrs_type, nb_dmrs_re_per_rb, number_of_symbols, mcs, Nl; int ap, start_symbol, Nid_cell, i; int sample_offsetF, N_RE_prime, N_PRB_oh; - uint16_t n_rnti; + uint16_t n_rnti, ul_dmrs_symb_pos; uint8_t data_existing =0; uint8_t L_ptrs, K_ptrs; // PTRS parameters uint16_t beta_ptrs; // PTRS parameter related to power control NR_UE_ULSCH_t *ulsch_ue; - NR_UL_UE_HARQ_t *harq_process_ul_ue; + NR_UL_UE_HARQ_t *harq_process_ul_ue=NULL; NR_DL_FRAME_PARMS *frame_parms = &UE->frame_parms; NR_UE_PUSCH *pusch_ue = UE->pusch_vars[thread_id][gNB_id]; uint8_t ulsch_input_buffer[MAX_ULSCH_PAYLOAD_BYTES]; - ptrs_UplinkConfig_t *ptrs_Uplink_Config = &UE->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig; + // ptrs_UplinkConfig_t *ptrs_Uplink_Config = &UE->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig; num_of_codewords = 1; // tmp assumption - n_rnti = 0x1234; Nid_cell = 0; N_PRB_oh = 0; // higher layer (RRC) parameter xOverhead in PUSCH-ServingCellConfig number_dmrs_symbols = 0; - uint8_t mapping_type = UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; for (cwd_index = 0;cwd_index < num_of_codewords; cwd_index++) { ulsch_ue = UE->ulsch[thread_id][gNB_id][cwd_index]; harq_process_ul_ue = ulsch_ue->harq_processes[harq_pid]; - start_symbol = harq_process_ul_ue->start_symbol; + start_symbol = harq_process_ul_ue->pusch_pdu.start_symbol_index; + ul_dmrs_symb_pos = harq_process_ul_ue->pusch_pdu.ul_dmrs_symb_pos; + number_of_symbols = harq_process_ul_ue->pusch_pdu.nr_of_symbols; + dmrs_type = harq_process_ul_ue->pusch_pdu.dmrs_config_type; - for (i = start_symbol; i < start_symbol + harq_process_ul_ue->number_of_symbols; i++) - number_dmrs_symbols += is_dmrs_symbol((mapping_type)?i-start_symbol:i, - 0, - 0, - 0, - 0, - 0, - harq_process_ul_ue->number_of_symbols, - UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, - frame_parms->ofdm_symbol_size); + for (i = start_symbol; i < start_symbol + number_of_symbols; i++) { - ulsch_ue->length_dmrs = number_dmrs_symbols; // pusch.MaxLenght is redundant here as number_dmrs_symbols - // contains all dmrs symbols even for double symbol dmrs - ulsch_ue->rnti = n_rnti; + if((ul_dmrs_symb_pos >> i) & 0x01) + number_dmrs_symbols += 1; + + } + + rnti = harq_process_ul_ue->pusch_pdu.rnti; ulsch_ue->Nid_cell = Nid_cell; - ulsch_ue->nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4); + nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4); - N_RE_prime = NR_NB_SC_PER_RB*harq_process_ul_ue->number_of_symbols - ulsch_ue->nb_re_dmrs*number_dmrs_symbols - N_PRB_oh; + N_RE_prime = NR_NB_SC_PER_RB*number_of_symbols - nb_dmrs_re_per_rb*number_dmrs_symbols - N_PRB_oh; - harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*harq_process_ul_ue->nb_rb*num_of_codewords; + nb_rb = harq_process_ul_ue->pusch_pdu.rb_size; - mod_order = nr_get_Qm_ul(harq_process_ul_ue->mcs, 0); - code_rate = nr_get_code_rate_ul(harq_process_ul_ue->mcs, 0); + harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*num_of_codewords; - harq_process_ul_ue->TBS = nr_compute_tbs(mod_order, + mcs = harq_process_ul_ue->pusch_pdu.mcs_index; + Nl = harq_process_ul_ue->pusch_pdu.nrOfLayers; + mod_order = nr_get_Qm_ul(mcs, 0); + code_rate = nr_get_code_rate_ul(mcs, 0); + + harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = nr_compute_tbs(mod_order, code_rate, - harq_process_ul_ue->nb_rb, - harq_process_ul_ue->number_of_symbols, - ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs, + nb_rb, + number_of_symbols, + nb_dmrs_re_per_rb*number_dmrs_symbols, 0, - harq_process_ul_ue->Nl); + harq_process_ul_ue->pusch_pdu.nrOfLayers); uint8_t access_mode = SCHEDULED_ACCESS; @@ -174,19 +173,20 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, // to be removed later when MAC is ready if (harq_process_ul_ue != NULL){ + TBS = harq_process_ul_ue->pusch_pdu.pusch_data.tb_size; data_existing = 0; if (IS_SOFTMODEM_NOS1){ - data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame, - slot, 0, ulsch_input_buffer, harq_process_ul_ue->TBS/8, &access_mode); + data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame, + slot, 0, ulsch_input_buffer, TBS/8, &access_mode); //IP traffic to be transmitted - if(data_existing){ - //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char)); - memcpy(harq_process_ul_ue->a, ulsch_input_buffer, harq_process_ul_ue->TBS/8); + if(data_existing){ + //harq_process_ul_ue->a = (unsigned char*)calloc(TBS/8, sizeof(unsigned char)); + memcpy(harq_process_ul_ue->a, ulsch_input_buffer, TBS/8); #ifdef DEBUG_MAC_PDU - LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", harq_process_ul_ue->TBS/8); - for (i = 0; i < harq_process_ul_ue->TBS / 8; i++) { + LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", TBS/8); + for (i = 0; i < TBS / 8; i++) { printf("0x%02x",harq_process_ul_ue->a[i]); } printf("\n"); @@ -203,7 +203,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, for (i = 0; ia[i] = 0; - for (i = payload_offset; i < harq_process_ul_ue->TBS / 8; i++) { + for (i = payload_offset; i < TBS / 8; i++) { harq_process_ul_ue->a[i] = (unsigned char) rand(); //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); } @@ -218,8 +218,10 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////ULSCH coding///////////////////////// /////////// + unsigned int G = nr_get_G(nb_rb, number_of_symbols, + nb_dmrs_re_per_rb, number_dmrs_symbols, mod_order, Nl); - nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid); + nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid, G); /////////// //////////////////////////////////////////////////////////////////// @@ -227,21 +229,14 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////ULSCH scrambling///////////////////////// /////////// - mod_order = nr_get_Qm_ul(harq_process_ul_ue->mcs, 0); - - available_bits = nr_get_G(harq_process_ul_ue->nb_rb, - harq_process_ul_ue->number_of_symbols, - ulsch_ue->nb_re_dmrs, - ulsch_ue->length_dmrs, - mod_order, - 1); + available_bits = G; memset(scrambled_output[cwd_index], 0, ((available_bits>>5)+1)*sizeof(uint32_t)); nr_pusch_codeword_scrambling(ulsch_ue->g, available_bits, ulsch_ue->Nid_cell, - ulsch_ue->rnti, + rnti, scrambled_output[cwd_index]); // assume one codeword for the moment @@ -269,9 +264,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////DMRS Modulation///////////////////////// /////////// pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; - n_dmrs = (harq_process_ul_ue->nb_rb*ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs); + n_dmrs = (nb_rb*nb_dmrs_re_per_rb*number_dmrs_symbols); int16_t mod_dmrs[n_dmrs<<1]; - dmrs_type = UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type; /////////// //////////////////////////////////////////////////////////////////////// @@ -279,26 +273,23 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////PTRS parameters' initialization///////////////////////// /////////// - int16_t mod_ptrs[(harq_process_ul_ue->nb_rb/2)*(NR_SYMBOLS_PER_SLOT-1)*2]; // assume maximum number of PTRS per pusch allocation + int16_t mod_ptrs[(nb_rb/2)*(NR_SYMBOLS_PER_SLOT-1)*2]; // assume maximum number of PTRS per pusch allocation K_ptrs = 0; // just to avoid a warning - if (UE->ptrs_configured == 1) { + if (harq_process_ul_ue->pusch_pdu.pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { - K_ptrs = get_K_ptrs(ptrs_Uplink_Config, harq_process_ul_ue->nb_rb); - - L_ptrs = get_L_ptrs(ptrs_Uplink_Config, harq_process_ul_ue->mcs); + K_ptrs = (harq_process_ul_ue->pusch_pdu.pusch_ptrs.ptrs_freq_density)?4:2; + L_ptrs = 1<pusch_pdu.pusch_ptrs.ptrs_time_density; beta_ptrs = 1; // temp value until power control is implemented ulsch_ue->ptrs_symbols = 0; set_ptrs_symb_idx(&ulsch_ue->ptrs_symbols, - harq_process_ul_ue->number_of_symbols, + number_of_symbols, start_symbol, - dmrs_type, L_ptrs, - ulsch_ue->length_dmrs, - frame_parms->ofdm_symbol_size); + ul_dmrs_symb_pos); } /////////// @@ -310,7 +301,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, tx_layers = (int16_t **)pusch_ue->txdataF_layers; nr_ue_layer_mapping(UE->ulsch[thread_id][gNB_id], - harq_process_ul_ue->Nl, + Nl, available_bits/mod_order, tx_layers); @@ -327,24 +318,19 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint32_t nb_re_pusch, nb_re_dmrs_per_rb; uint32_t y_offset = 0; - for (l = start_symbol; l < start_symbol + harq_process_ul_ue->number_of_symbols; l++) { + for (l = start_symbol; l < start_symbol + number_of_symbols; l++) { - is_dmrs = is_dmrs_symbol((mapping_type)?l-start_symbol:l, - 0, - 0, - 0, - 0, - 0, - harq_process_ul_ue->number_of_symbols, - dmrs_type, - frame_parms->ofdm_symbol_size); + if((ul_dmrs_symb_pos >> l) & 0x01) + is_dmrs = 1; + else + is_dmrs = 0; if (is_dmrs == 1) - nb_re_dmrs_per_rb = ulsch_ue->nb_re_dmrs; + nb_re_dmrs_per_rb = nb_dmrs_re_per_rb; else nb_re_dmrs_per_rb = 0; - nb_re_pusch = harq_process_ul_ue->nb_rb * (NR_NB_SC_PER_RB - nb_re_dmrs_per_rb); + nb_re_pusch = nb_rb * (NR_NB_SC_PER_RB - nb_re_dmrs_per_rb); nr_dft(&ulsch_ue->y[y_offset], &((int32_t*)tx_layers[0])[y_offset], nb_re_pusch); @@ -364,13 +350,13 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, txdataF = UE->common_vars.txdataF; - start_rb = harq_process_ul_ue->first_rb; + start_rb = harq_process_ul_ue->pusch_pdu.rb_start; start_sc = frame_parms->first_carrier_offset + start_rb*NR_NB_SC_PER_RB; if (start_sc >= frame_parms->ofdm_symbol_size) start_sc -= frame_parms->ofdm_symbol_size; - for (ap=0; apNl; ap++) { + for (ap=0; ap< Nl; ap++) { // DMRS params for this ap get_Wt(Wt, ap, dmrs_type); @@ -380,46 +366,38 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t k_prime=0; uint8_t is_dmrs, is_ptrs; - uint8_t l_ref; uint16_t m=0, n=0, dmrs_idx=0, ptrs_idx = 0; - for (l=start_symbol; lnumber_of_symbols; l++) { + for (l=start_symbol; lnb_rb*NR_NB_SC_PER_RB; i++) { + for (i=0; i< nb_rb*NR_NB_SC_PER_RB; i++) { sample_offsetF = l*frame_parms->ofdm_symbol_size + k; is_dmrs = 0; is_ptrs = 0; - is_dmrs = is_dmrs_symbol(l_ref, - k, - start_sc, - k_prime, - n, - delta, - harq_process_ul_ue->number_of_symbols, - dmrs_type, - frame_parms->ofdm_symbol_size); + if((ul_dmrs_symb_pos >> l) & 0x01) { + if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%frame_parms->ofdm_symbol_size)) + is_dmrs = 1; + } - if (UE->ptrs_configured == 1){ - is_ptrs = is_ptrs_symbol(l, - k, - ulsch_ue->rnti, - harq_process_ul_ue->nb_rb, - harq_process_ul_ue->number_of_symbols, - ap, - K_ptrs, - ulsch_ue->ptrs_symbols, - start_sc, - frame_parms->ofdm_symbol_size, - UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, - ptrs_Uplink_Config->resourceElementOffset); + if (harq_process_ul_ue->pusch_pdu.pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS){ + + if(is_ptrs_symbol(l, ulsch_ue->ptrs_symbols)) + is_ptrs = is_ptrs_subcarrier(k, + rnti, + ap, + dmrs_type, + K_ptrs, + nb_rb, + harq_process_ul_ue->pusch_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset, + start_sc, + frame_parms->ofdm_symbol_size); } if (is_dmrs == 1) { @@ -446,7 +424,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, } else if (is_ptrs == 1) { if (k == start_sc){ - nr_modulation(pusch_dmrs[l][0], harq_process_ul_ue->nb_rb/2, DMRS_MOD_ORDER, mod_ptrs); + nr_modulation(pusch_dmrs[l][0], nb_rb, DMRS_MOD_ORDER, mod_ptrs); } ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = (beta_ptrs*AMP*mod_ptrs[ptrs_idx<<1]) >> 15; @@ -494,7 +472,7 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, int32_t **txdata; int32_t **txdataF; int timing_advance; - uint8_t Nl = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->Nl; // cw 0 + uint8_t Nl = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->pusch_pdu.nrOfLayers; // cw 0 /////////////////////////IFFT/////////////////////// /////////// diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c index e8eceb77a6..baf34ade92 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c @@ -52,7 +52,7 @@ * * PARAMETERS : size of ofdm symbol * -* RETURN : function idft +* RETURN : index pointing to the dft func in the dft library * * DESCRIPTION : get idft function depending of ofdm size * @@ -60,45 +60,45 @@ //#define DBG_PSS_NR -void *get_idft(int ofdm_symbol_size) +idft_size_idx_t get_idft(int ofdm_symbol_size) { - void (*idft)(int16_t *,int16_t *, int); - + + switch (ofdm_symbol_size) { case 128: - idft = idft128; + return IDFT_128; break; case 256: - idft = idft256; + return IDFT_256; break; case 512: - idft = idft512; + return IDFT_512; break; case 1024: - idft = idft1024; + return IDFT_1024; break; case 1536: - idft = idft1536; + return IDFT_1536; break; case 2048: - idft = idft2048; + return IDFT_2048; break; case 3072: - idft = idft3072; + return IDFT_3072; break; case 4096: - idft = idft4096; + return IDFT_4096; break; case 8192: - idft = idft8192; + return IDFT_8192; break; default: @@ -106,7 +106,7 @@ void *get_idft(int ofdm_symbol_size) assert(0); break; } - return idft; + return IDFT_SIZE_IDXTABLESIZE; // never reached and will trigger assertion in idft function } /******************************************************************* @@ -121,41 +121,41 @@ void *get_idft(int ofdm_symbol_size) * *********************************************************************/ -void *get_dft(int ofdm_symbol_size) +dft_size_idx_t get_dft(int ofdm_symbol_size) { - void (*dft)(int16_t *,int16_t *, int); + switch (ofdm_symbol_size) { case 128: - dft = dft128; + return DFT_128; break; case 256: - dft = dft256; + return DFT_256; break; case 512: - dft = dft512; + return DFT_512; break; case 1024: - dft = dft1024; + return DFT_1024; break; case 1536: - dft = dft1536; + return DFT_1536; break; case 2048: - dft = dft2048; + return DFT_2048; break; case 4096: - dft = dft4096; + return DFT_4096; break; case 8192: - dft = dft8192; + return DFT_8192; break; default: @@ -163,7 +163,7 @@ void *get_dft(int ofdm_symbol_size) assert(0); break; } - return dft; + return DFT_SIZE_IDXTABLESIZE; // never reached and will trigger assertion in idft function; } /******************************************************************* @@ -191,7 +191,7 @@ void generate_pss_nr(NR_DL_FRAME_PARMS *fp,int N_ID_2) unsigned int size = length * IQ_SIZE; /* i & q */ int16_t *primary_synchro = primary_synchro_nr[N_ID_2]; /* pss in complex with alternatively i then q */ int16_t *primary_synchro2 = primary_synchro_nr2[N_ID_2]; /* pss in complex with alternatively i then q */ - void (*idft)(int16_t *,int16_t *, int); + #define INITIAL_PSS_NR (7) const int x_initial[INITIAL_PSS_NR] = {0, 1, 1 , 0, 1, 1, 1}; @@ -282,9 +282,10 @@ void generate_pss_nr(NR_DL_FRAME_PARMS *fp,int N_ID_2) /* IFFT will give temporal signal of Pss */ - idft = get_idft(length); - - idft(synchroF_tmp, /* complex input */ + + + idft((int16_t)get_idft(length), + synchroF_tmp, /* complex input */ synchro_tmp, /* complex output */ 1); /* scaling factor */ @@ -312,6 +313,7 @@ void generate_pss_nr(NR_DL_FRAME_PARMS *fp,int N_ID_2) #endif + #if 0 /* it allows checking that process of idft on a signal and then dft gives same signal with limited errors */ @@ -323,10 +325,11 @@ void generate_pss_nr(NR_DL_FRAME_PARMS *fp,int N_ID_2) bzero(synchroF_tmp, size); - void (*dft)(int16_t *,int16_t *, int) = get_dft(length); + /* get pss in the time domain by applying an inverse FFT */ - dft(synchro_tmp, /* complex input */ + dft((int16_t)get_dft(length), + synchro_tmp, /* complex input */ synchroF_tmp, /* complex output */ 1); /* scaling factor */ diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index 351c4ea22a..c8f7268d04 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -37,157 +37,20 @@ //#include "LAYER2/MAC/extern.h" #include "PHY/NR_UE_TRANSPORT/pucch_nr.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" - +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "T.h" +//#define NR_UNIT_TEST 1 #ifdef NR_UNIT_TEST #define DEBUG_PUCCH_TX #define DEBUG_NR_PUCCH_TX #endif + //#define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2) -void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping, - uint32_t n_id, - uint8_t n_hop, - int nr_tti_tx, - uint8_t *u, - uint8_t *v) { - /* - * Implements TS 38.211 subclause 6.3.2.2.1 Group and sequence hopping - * The following variables are set by higher layers: - * - PUCCH_GroupHopping: - * - n_id: higher-layer parameter hoppingId - * - n_hop: frequency hopping index - * if intra-slot frequency hopping is disabled by the higher-layer parameter PUCCH-frequency-hopping - * n_hop=0 - * if frequency hopping is enabled by the higher-layer parameter PUCCH-frequency-hopping - * n_hop=0 for the first hop - * n_hop=1 for the second hop - */ - // depending on the value of the PUCCH_GroupHopping, we will obtain different values for u,v - //pucch_GroupHopping_t PUCCH_GroupHopping = ue->pucch_config_common_nr->pucch_GroupHopping; // from higher layers FIXME!!! - // n_id defined as per TS 38.211 subclause 6.3.2.2.1 (is given by the higher-layer parameter hoppingId) - // it is hoppingId from PUCCH-ConfigCommon: - // Cell-Specific scrambling ID for group hoppping and sequence hopping if enabled - // Corresponds to L1 parameter 'HoppingID' (see 38.211, section 6.3.2.2) BIT STRING (SIZE (10)) - //uint16_t n_id = ue->pucch_config_common_nr->hoppingId; // from higher layers FIXME!!! -#ifdef DEBUG_NR_PUCCH_TX - // initialization to be removed - PUCCH_GroupHopping=neither; - n_id=10; - printf("\t\t [nr_group_sequence_hopping] initialization PUCCH_GroupHopping=%u, n_id=%u -> variable initializations TO BE REMOVED\n",PUCCH_GroupHopping,n_id); -#endif - uint8_t f_ss=0,f_gh=0; - *u=0; - *v=0; - uint32_t c_init = 0; - uint32_t x1,s; // TS 38.211 Subclause 5.2.1 - int l = 32, minShift = ((2*nr_tti_tx+n_hop)<<3); - int tmpShift =0; -#ifdef DEBUG_NR_PUCCH_TX - printf("\t\t [nr_group_sequence_hopping] calculating u,v -> "); -#endif - - if (PUCCH_GroupHopping == neither) { // PUCCH_GroupHopping 'neither' - f_ss = n_id%30; - } - - if (PUCCH_GroupHopping == enable) { // PUCCH_GroupHopping 'enabled' - c_init = floor(n_id/30); // we initialize c_init to calculate u,v according to 6.3.2.2.1 of 38.211 - s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1 - for (int m=0; m<8; m++) { - while(minShift >= l) { - s = lte_gold_generic(&x1, &c_init, 0); - l = l+32; - } - - tmpShift = (minShift&((1<<5)-1)); //minShift%32; - f_gh = f_gh + ((1<>tmpShift)&1))); - minShift ++; - } - - f_gh = f_gh%30; - f_ss = n_id%30; - /* for (int m=0; m<8; m++){ - f_gh = f_gh + ((1<>(8*(2*nr_tti_tx+n_hop)+m))&1))); // Not sure we have to use nr_tti_tx FIXME!!! - } - f_gh = f_gh%30; - f_ss = n_id%30;*/ - } - - if (PUCCH_GroupHopping == disable) { // PUCCH_GroupHopping 'disabled' - c_init = (1<<5)*floor(n_id/30)+(n_id%30); // we initialize c_init to calculate u,v - s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1 - f_ss = n_id%30; - l = 32, minShift = (2*nr_tti_tx+n_hop); - - while(minShift >= l) { - s = lte_gold_generic(&x1, &c_init, 0); - l = l+32; - } - - tmpShift = (minShift&((1<<5)-1)); //minShift%32; - *v = (uint8_t)((s>>tmpShift)&1); - // *v = (uint8_t)((s>>(2*nr_tti_tx+n_hop))&1); // Not sure we have to use nr_tti_tx FIXME!!! - } - - *u = (f_gh+f_ss)%30; -#ifdef DEBUG_NR_PUCCH_TX - printf("%d,%d\n",*u,*v); -#endif -} - -double nr_cyclic_shift_hopping(uint32_t n_id, - uint8_t m0, - uint8_t mcs, - uint8_t lnormal, - uint8_t lprime, - int nr_tti_tx) { - /* - * Implements TS 38.211 subclause 6.3.2.2.2 Cyclic shift hopping - * - n_id: higher-layer parameter hoppingId - * - m0: provided by higher layer parameter PUCCH-F0-F1-initial-cyclic-shift of PUCCH-F0-resource-config - * - mcs: mcs=0 except for PUCCH format 0 when it depends on information to be transmitted according to TS 38.213 subclause 9.2 - * - lnormal: lnormal is the OFDM symbol number in the PUCCH transmission where l=0 corresponds to the first OFDM symbol of the PUCCH transmission - * - lprime: lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213] - */ - // alpha_init initialized to 2*PI/12=0.5235987756 - double alpha = 0.5235987756; - uint32_t c_init = n_id; // we initialize c_init again to calculate n_cs -#ifdef DEBUG_NR_PUCCH_TX - // initialization to be remo.ved - c_init=10; - printf("\t\t [nr_cyclic_shift_hopping] initialization c_init=%u -> variable initialization TO BE REMOVED\n",c_init); -#endif - uint32_t x1,s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1 - uint8_t n_cs=0; - int l = 32, minShift = (14*8*nr_tti_tx )+ 8*(lnormal+lprime); - int tmpShift =0; -#ifdef DEBUG_NR_PUCCH_TX - printf("\t\t [nr_cyclic_shift_hopping] calculating alpha (cyclic shift) using c_init=%u -> \n",c_init); -#endif - - for (int m=0; m<8; m++) { - while(minShift >= l) { - s = lte_gold_generic(&x1, &c_init, 0); - l = l+32; - } - - tmpShift = (minShift&((1<<5)-1)); //minShift%32; - minShift ++; - n_cs = n_cs+((1<>tmpShift)&1))); - // calculating n_cs (Not sure we have to use nr_tti_tx FIXME!!!) - // n_cs = n_cs+((1<>((14*8*nr_tti_tx) + 8*(lnormal+lprime) + m))&1))); - } - - alpha = (alpha * (double)((m0+mcs+n_cs)%12)); -#ifdef DEBUG_NR_PUCCH_TX - printf("n_cs=%d -> %lf\n",n_cs,alpha); -#endif - return(alpha); -} void nr_generate_pucch0(PHY_VARS_NR_UE *ue, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, @@ -271,46 +134,31 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, */ //int32_t *txptr; uint32_t re_offset=0; + uint8_t l2; for (int l=0; lN_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is lower band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; - } - - if ((startingPRB >= (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is upper band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1))); - } - - if ((startingPRB < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is lower band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; - } - - if ((startingPRB > (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is upper band - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1))) + 6; - } - - if ((startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB contains DC - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset; - } + l2=l+startingSymbolIndex; + re_offset = (12*startingPRB) + frame_parms->first_carrier_offset; + if (re_offset>= frame_parms->ofdm_symbol_size) + re_offset-=frame_parms->ofdm_symbol_size; //txptr = &txdataF[0][re_offset]; for (int n=0; n<12; n++) { - if ((n==6) && (startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { - // if number RBs in bandwidth is odd and current PRB contains DC, we need to recalculate the offset when n=6 (for second half PRB) - re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size); - } - ((int16_t *)&txdataF[0][re_offset])[0] = (int16_t)(((int32_t)(amp) * x_n_re[(12*l)+n])>>15); - ((int16_t *)&txdataF[0][re_offset])[1] = (int16_t)(((int32_t)(amp) * x_n_im[(12*l)+n])>>15); + ((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[0] = (int16_t)(((int32_t)(amp) * x_n_re[(12*l)+n])>>15); + ((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[1] = (int16_t)(((int32_t)(amp) * x_n_im[(12*l)+n])>>15); //((int16_t *)txptr[0][re_offset])[0] = (int16_t)((int32_t)amp * x_n_re[(12*l)+n])>>15; //((int16_t *)txptr[0][re_offset])[1] = (int16_t)((int32_t)amp * x_n_im[(12*l)+n])>>15; //txptr[re_offset] = (x_n_re[(12*l)+n]<<16) + x_n_im[(12*l)+n]; #ifdef DEBUG_NR_PUCCH_TX printf("\t [nr_generate_pucch0] mapping to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n", - amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,re_offset, - l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]); + amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size) + re_offset, + l2,n,((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[0], + ((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[1]); #endif re_offset++; + if (re_offset>= frame_parms->ofdm_symbol_size) + re_offset-=frame_parms->ofdm_symbol_size; } } } @@ -1059,7 +907,9 @@ void nr_uci_encoding(uint64_t payload, if (A<=11) { // procedure in subclause 6.3.1.2.2 (UCI encoded by channel coding of small block lengths -> subclause 6.3.1.3.2) // CRC bits are not attached, and coding small block lengths (subclause 5.3.3) + b[0] = encodeSmallBlock((uint16_t*)&payload,A); } else if (A>=12) { + AssertFatal(1==0,"Polar encoding not supported yet for UCI\n"); // procedure in subclause 6.3.1.2.1 (UCI encoded by Polar code -> subclause 6.3.1.3.1) /*if ((A>=360 && E>=1088)||(A>=1013)) { I_seg = 1; @@ -1078,10 +928,13 @@ void nr_uci_encoding(uint64_t payload, // code block segmentation and CRC attachment is performed according to subclause 5.2.1 // polar coding subclause 5.3.1 } + } //#if 0 void nr_generate_pucch2(PHY_VARS_NR_UE *ue, uint16_t crnti, + uint32_t dmrs_scrambling_id, + uint32_t data_scrambling_id, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, @@ -1115,14 +968,14 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, */ uint8_t *btilde = malloc(sizeof(int8_t)*M_bit); // rnti is given by the C-RNTI - uint16_t rnti=crnti, n_id=0; + uint16_t rnti=crnti; #ifdef DEBUG_NR_PUCCH_TX printf("\t [nr_generate_pucch2] rnti = %d ,\n",rnti); #endif /* * Implementing TS 38.211 Subclause 6.3.2.5.1 scrambling format 2 */ - nr_pucch2_3_4_scrambling(M_bit,rnti,n_id,b,btilde); + nr_pucch2_3_4_scrambling(M_bit,rnti,data_scrambling_id,b,btilde); /* * Implementing TS 38.211 Subclause 6.3.2.5.2 modulation format 2 * btilde shall be modulated as described in subclause 5.1 using QPSK @@ -1170,10 +1023,10 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, int m=0; for (int l=0; lN_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is lower band diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h index e8cd147526..a2446dccf9 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h @@ -20,7 +20,7 @@ */ /*! \file PHY/NR_UE_TRANSPORT/pucch_nr.c -* \brief Top-level routines for generating and decoding the PUCCH physical channel +* \brief Top-level routines for generating the PUCCH physical channel * \author A. Mico Pereperez * \date 2018 * \version 0.1 @@ -29,6 +29,9 @@ * \note * \warning */ +#ifndef __PUCCH_NR__H__ +#define __PUCCH_NR__H__ + //#include "PHY/defs.h" #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_common.h" @@ -42,46 +45,7 @@ #include "T.h" #define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2) -void nr_decode_pucch1( int32_t **rxdataF, - pucch_GroupHopping_t pucch_GroupHopping, - uint32_t n_id, // hoppingID higher layer parameter - uint64_t *payload, - NR_DL_FRAME_PARMS *frame_parms, - int16_t amp, - int nr_tti_tx, - uint8_t m0, - uint8_t nrofSymbols, - uint8_t startingSymbolIndex, - uint16_t startingPRB, - uint16_t startingPRB_intraSlotHopping, - uint8_t timeDomainOCC, - uint8_t nr_bit); -void nr_decode_pucch0( int32_t **rxdataF, - pucch_GroupHopping_t PUCCH_GroupHopping, - uint32_t n_id, //PHY_VARS_gNB *gNB, generally rxdataf is in gNB->common_vars - uint64_t *payload, - NR_DL_FRAME_PARMS *frame_parms, - int16_t amp, - int nr_tti_tx, - uint8_t m0, // should come from resource set - uint8_t nrofSymbols, // should come from resource set - uint8_t startingSymbolIndex, // should come from resource set - uint16_t startingPRB, // should come from resource set - uint8_t nr_bit); - -void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping, - uint32_t n_id, - uint8_t n_hop, - int nr_tti_tx, - uint8_t *u, - uint8_t *v); -double nr_cyclic_shift_hopping(uint32_t n_id, - uint8_t m0, - uint8_t mcs, - uint8_t lnormal, - uint8_t lprime, - int nr_tti_tx); void nr_generate_pucch0(PHY_VARS_NR_UE *ue, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, @@ -109,6 +73,8 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue, uint8_t nr_bit); void nr_generate_pucch2(PHY_VARS_NR_UE *ue, uint16_t crnti, + uint32_t dmrs_scrambling_id, + uint32_t data_scrambling_id, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, @@ -139,8 +105,8 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, uint8_t occ_index_format4); // tables for mcs values for different payloads - static const uint8_t table1_mcs[]={0,3,6,9}; - static const uint8_t table2_mcs[]={0,1,3,4,6,7,9,10}; + static const uint8_t table1_mcs[]={0,6,3,9}; + static const uint8_t table2_mcs[]={0,3,9,6,1,4,10,7}; /* * The following tables implement TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (rows->u {0,1,..,29} / columns->n {0,1,...,M_ZC-1) @@ -454,3 +420,4 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, 73, 79, 83, 89, 97, 101,103,107,109,113, 127,131,137,139,149,151,157,163,167,173, 179,181,191,193,197,199}; +#endif diff --git a/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c index 44d500b0b7..e3f1f13a8d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/sss_nr.c @@ -182,7 +182,7 @@ void insert_sss_nr(int16_t *sss_time, } /* get sss in the frequency domain by applying an inverse FFT */ - idft2048(synchroF_tmp, /* complex input */ + idft(IDFT_2048,synchroF_tmp, /* complex input */ synchro_tmp, /* complex output */ 1); /* scaling factor */ diff --git a/openair1/PHY/TOOLS/lte_dfts.c b/openair1/PHY/TOOLS/lte_dfts.c deleted file mode 100644 index 2de8653ab3..0000000000 --- a/openair1/PHY/TOOLS/lte_dfts.c +++ /dev/null @@ -1,9688 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -#include -#include -#include - -#include -#include -#include -#include - -#ifndef M_PI -#define M_PI 3.14159265358979323846 -#endif - -#ifndef MR_MAIN -#include "PHY/defs_common.h" -#include "PHY/impl_defs_top.h" -#include "tools_defs.h" -#else -#include "time_meas.h" -#include "LOG/log.h" -#define debug_msg -#define ONE_OVER_SQRT2_Q15 23170 - -int oai_exit=0; -#endif - -#define ONE_OVER_SQRT3_Q15 18919 - -#include "../sse_intrin.h" - -#include "assertions.h" - -#define print_shorts(s,x) printf("%s %d,%d,%d,%d,%d,%d,%d,%d\n",s,(x)[0],(x)[1],(x)[2],(x)[3],(x)[4],(x)[5],(x)[6],(x)[7]) -#define print_shorts256(s,x) printf("%s %d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n",s,(x)[0],(x)[1],(x)[2],(x)[3],(x)[4],(x)[5],(x)[6],(x)[7],(x)[8],(x)[9],(x)[10],(x)[11],(x)[12],(x)[13],(x)[14],(x)[15]) - -#define print_ints(s,x) printf("%s %d %d %d %d\n",s,(x)[0],(x)[1],(x)[2],(x)[3]) - - -const static int16_t conjugatedft[32] __attribute__((aligned(32))) = {-1,1,-1,1,-1,1,-1,1,-1,1,-1,1,-1,1,-1,1,-1,1}; - - -const static int16_t reflip[32] __attribute__((aligned(32))) = {1,-1,1,-1,1,-1,1,-1,1,-1,1,-1,1,-1,1,-1}; - - - -#if defined(__x86_64__) || defined(__i386__) -static inline void cmac(__m128i a,__m128i b, __m128i *re32, __m128i *im32) __attribute__((always_inline)); -static inline void cmac(__m128i a,__m128i b, __m128i *re32, __m128i *im32) -{ - - __m128i cmac_tmp,cmac_tmp_re32,cmac_tmp_im32; - - cmac_tmp = _mm_sign_epi16(b,*(__m128i*)reflip); - cmac_tmp_re32 = _mm_madd_epi16(a,cmac_tmp); - - - // cmac_tmp = _mm_shufflelo_epi16(b,_MM_SHUFFLE(2,3,0,1)); - // cmac_tmp = _mm_shufflehi_epi16(cmac_tmp,_MM_SHUFFLE(2,3,0,1)); - cmac_tmp = _mm_shuffle_epi8(b,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - cmac_tmp_im32 = _mm_madd_epi16(cmac_tmp,a); - - *re32 = _mm_add_epi32(*re32,cmac_tmp_re32); - *im32 = _mm_add_epi32(*im32,cmac_tmp_im32); -} - -static inline void cmacc(__m128i a,__m128i b, __m128i *re32, __m128i *im32) __attribute__((always_inline)); -static inline void cmacc(__m128i a,__m128i b, __m128i *re32, __m128i *im32) -{ - - __m128i cmac_tmp,cmac_tmp_re32,cmac_tmp_im32; - - - cmac_tmp_re32 = _mm_madd_epi16(a,b); - - - cmac_tmp = _mm_sign_epi16(b,*(__m128i*)reflip); - // cmac_tmp = _mm_shufflelo_epi16(b,_MM_SHUFFLE(2,3,0,1)); - // cmac_tmp = _mm_shufflehi_epi16(cmac_tmp,_MM_SHUFFLE(2,3,0,1)); - cmac_tmp = _mm_shuffle_epi8(cmac_tmp,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - cmac_tmp_im32 = _mm_madd_epi16(cmac_tmp,a); - - *re32 = _mm_add_epi32(*re32,cmac_tmp_re32); - *im32 = _mm_add_epi32(*im32,cmac_tmp_im32); -} - -#ifdef __AVX2__ -static inline void cmac_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) __attribute__((always_inline)); -static inline void cmac_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) -{ - - __m256i cmac_tmp,cmac_tmp_re32,cmac_tmp_im32; - __m256i imshuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,19,18,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - cmac_tmp = _mm256_sign_epi16(b,*(__m256i*)reflip); - cmac_tmp_re32 = _mm256_madd_epi16(a,cmac_tmp); - - cmac_tmp = _mm256_shuffle_epi8(b,imshuffle); - cmac_tmp_im32 = _mm256_madd_epi16(cmac_tmp,a); - - *re32 = _mm256_add_epi32(*re32,cmac_tmp_re32); - *im32 = _mm256_add_epi32(*im32,cmac_tmp_im32); -} - -static inline void cmacc_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) __attribute__((always_inline)); -static inline void cmacc_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) -{ - - __m256i cmac_tmp,cmac_tmp_re32,cmac_tmp_im32; - __m256i imshuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,19,18,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - cmac_tmp_re32 = _mm256_madd_epi16(a,b); - - - cmac_tmp = _mm256_sign_epi16(b,*(__m256i*)reflip); - cmac_tmp = _mm256_shuffle_epi8(b,imshuffle); - cmac_tmp_im32 = _mm256_madd_epi16(cmac_tmp,a); - - *re32 = _mm256_add_epi32(*re32,cmac_tmp_re32); - *im32 = _mm256_add_epi32(*im32,cmac_tmp_im32); -} - -#endif - -static inline void cmult(__m128i a,__m128i b, __m128i *re32, __m128i *im32) __attribute__((always_inline)); - -static inline void cmult(__m128i a,__m128i b, __m128i *re32, __m128i *im32) -{ - - register __m128i mmtmpb; - - mmtmpb = _mm_sign_epi16(b,*(__m128i*)reflip); - *re32 = _mm_madd_epi16(a,mmtmpb); - // mmtmpb = _mm_shufflelo_epi16(b,_MM_SHUFFLE(2,3,0,1)); - // mmtmpb = _mm_shufflehi_epi16(mmtmpb,_MM_SHUFFLE(2,3,0,1)); - mmtmpb = _mm_shuffle_epi8(b,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - *im32 = _mm_madd_epi16(a,mmtmpb); - -} - -#ifdef __AVX2__ -static inline void cmult_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) __attribute__((always_inline)); - -static inline void cmult_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) -{ - - register __m256i mmtmpb; - __m256i const perm_mask = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - mmtmpb = _mm256_sign_epi16(b,*(__m256i*)reflip); - *re32 = _mm256_madd_epi16(a,mmtmpb); - mmtmpb = _mm256_shuffle_epi8(b,perm_mask); - *im32 = _mm256_madd_epi16(a,mmtmpb); - -} - -#endif - -static inline void cmultc(__m128i a,__m128i b, __m128i *re32, __m128i *im32) __attribute__((always_inline)); - -static inline void cmultc(__m128i a,__m128i b, __m128i *re32, __m128i *im32) -{ - - register __m128i mmtmpb; - - *re32 = _mm_madd_epi16(a,b); - mmtmpb = _mm_sign_epi16(b,*(__m128i*)reflip); - mmtmpb = _mm_shuffle_epi8(mmtmpb,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - *im32 = _mm_madd_epi16(a,mmtmpb); - -} - -#ifdef __AVX2__ -static inline void cmultc_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) __attribute__((always_inline)); - -static inline void cmultc_256(__m256i a,__m256i b, __m256i *re32, __m256i *im32) -{ - - register __m256i mmtmpb; - __m256i const perm_mask = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - *re32 = _mm256_madd_epi16(a,b); - mmtmpb = _mm256_sign_epi16(b,*(__m256i*)reflip); - mmtmpb = _mm256_shuffle_epi8(mmtmpb,perm_mask); - *im32 = _mm256_madd_epi16(a,mmtmpb); - -} - -#endif - -static inline __m128i cpack(__m128i xre,__m128i xim) __attribute__((always_inline)); - -static inline __m128i cpack(__m128i xre,__m128i xim) -{ - - register __m128i cpack_tmp1,cpack_tmp2; - - cpack_tmp1 = _mm_unpacklo_epi32(xre,xim); - cpack_tmp2 = _mm_unpackhi_epi32(xre,xim); - return(_mm_packs_epi32(_mm_srai_epi32(cpack_tmp1,15),_mm_srai_epi32(cpack_tmp2,15))); - -} - -#ifdef __AVX2__ -static inline __m256i cpack_256(__m256i xre,__m256i xim) __attribute__((always_inline)); - -static inline __m256i cpack_256(__m256i xre,__m256i xim) -{ - - register __m256i cpack_tmp1,cpack_tmp2; - - cpack_tmp1 = _mm256_unpacklo_epi32(xre,xim); - cpack_tmp2 = _mm256_unpackhi_epi32(xre,xim); - return(_mm256_packs_epi32(_mm256_srai_epi32(cpack_tmp1,15),_mm256_srai_epi32(cpack_tmp2,15))); - -} - -#endif - -static inline void packed_cmult(__m128i a,__m128i b, __m128i *c) __attribute__((always_inline)); - -static inline void packed_cmult(__m128i a,__m128i b, __m128i *c) -{ - - __m128i cre,cim; - cmult(a,b,&cre,&cim); - *c = cpack(cre,cim); - -} - -#ifdef __AVX2__ -static inline void packed_cmult_256(__m256i a,__m256i b, __m256i *c) __attribute__((always_inline)); - -static inline void packed_cmult_256(__m256i a,__m256i b, __m256i *c) -{ - - __m256i cre,cim; - cmult_256(a,b,&cre,&cim); - *c = cpack_256(cre,cim); - -} -#endif - -static inline void packed_cmultc(__m128i a,__m128i b, __m128i *c) __attribute__((always_inline)); - -static inline void packed_cmultc(__m128i a,__m128i b, __m128i *c) -{ - - __m128i cre,cim; - - cmultc(a,b,&cre,&cim); - *c = cpack(cre,cim); - -} - -#ifdef __AVX2__ -static inline void packed_cmultc_256(__m256i a,__m256i b, __m256i *c) __attribute__((always_inline)); - -static inline void packed_cmultc_256(__m256i a,__m256i b, __m256i *c) -{ - - __m256i cre,cim; - - cmultc_256(a,b,&cre,&cim); - *c = cpack_256(cre,cim); - -} -#endif - -static inline __m128i packed_cmult2(__m128i a,__m128i b,__m128i b2) __attribute__((always_inline)); - -static inline __m128i packed_cmult2(__m128i a,__m128i b,__m128i b2) -{ - - - register __m128i cre,cim; - - cre = _mm_madd_epi16(a,b); - cim = _mm_madd_epi16(a,b2); - - return(cpack(cre,cim)); - -} - -#ifdef __AVX2__ -static inline __m256i packed_cmult2_256(__m256i a,__m256i b,__m256i b2) __attribute__((always_inline)); - -static inline __m256i packed_cmult2_256(__m256i a,__m256i b,__m256i b2) -{ - - - register __m256i cre,cim; - - cre = _mm256_madd_epi16(a,b); - cim = _mm256_madd_epi16(a,b2); - - return(cpack_256(cre,cim)); - -} -#endif - -#elif defined (__arm__) -static inline void cmac(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) __attribute__((always_inline)); -static inline void cmac(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) -{ - - - int32x4_t ab_re0,ab_re1,ab_im0,ab_im1; - int16x8_t bflip = vrev32q_s16(b); - int16x8_t bconj = vmulq_s16(b,*(int16x8_t *)reflip); - - ab_re0 = vmull_s16(((int16x4_t*)&a)[0],((int16x4_t*)&bconj)[0]); - ab_re1 = vmull_s16(((int16x4_t*)&a)[1],((int16x4_t*)&bconj)[1]); - ab_im0 = vmull_s16(((int16x4_t*)&a)[0],((int16x4_t*)&bflip)[0]); - ab_im1 = vmull_s16(((int16x4_t*)&a)[1],((int16x4_t*)&bflip)[1]); - *re32 = vqaddq_s32(*re32,vcombine_s32(vpadd_s32(((int32x2_t*)&ab_re0)[0],((int32x2_t*)&ab_re0)[1]), - vpadd_s32(((int32x2_t*)&ab_re1)[0],((int32x2_t*)&ab_re1)[1]))); - *im32 = vqaddq_s32(*im32,vcombine_s32(vpadd_s32(((int32x2_t*)&ab_im0)[0],((int32x2_t*)&ab_im0)[1]), - vpadd_s32(((int32x2_t*)&ab_im1)[0],((int32x2_t*)&ab_im1)[1]))); -} - -static inline void cmacc(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) __attribute__((always_inline)); -static inline void cmacc(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) -{ - int32x4_t ab_re0,ab_re1,ab_im0,ab_im1; - int16x8_t bconj = vmulq_s16(b,*(int16x8_t *)reflip); - int16x8_t bflip = vrev32q_s16(bconj); - - ab_re0 = vmull_s16(((int16x4_t*)&a)[0],((int16x4_t*)&b)[0]); - ab_re1 = vmull_s16(((int16x4_t*)&a)[1],((int16x4_t*)&b)[1]); - ab_im0 = vmull_s16(((int16x4_t*)&a)[0],((int16x4_t*)&bflip)[0]); - ab_im1 = vmull_s16(((int16x4_t*)&a)[1],((int16x4_t*)&bflip)[1]); - *re32 = vqaddq_s32(*re32,vcombine_s32(vpadd_s32(((int32x2_t*)&ab_re0)[0],((int32x2_t*)&ab_re0)[1]), - vpadd_s32(((int32x2_t*)&ab_re1)[0],((int32x2_t*)&ab_re1)[1]))); - *im32 = vqaddq_s32(*im32,vcombine_s32(vpadd_s32(((int32x2_t*)&ab_im0)[0],((int32x2_t*)&ab_im0)[1]), - vpadd_s32(((int32x2_t*)&ab_im1)[0],((int32x2_t*)&ab_im1)[1]))); - -} - -static inline void cmult(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) __attribute__((always_inline)); -static inline void cmult(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) -{ - int32x4_t ab_re0,ab_re1,ab_im0,ab_im1; - int16x8_t bflip = vrev32q_s16(b); - int16x8_t bconj = vmulq_s16(b,*(int16x8_t *)reflip); - int16x4_t al,ah,bcl,bch,bfl,bfh; - int32x2_t abr0l,abr0h,abr1l,abr1h,abi0l,abi0h,abi1l,abi1h; - - al = vget_low_s16(a); ah = vget_high_s16(a); - bcl = vget_low_s16(bconj); bch = vget_high_s16(bconj); - bfl = vget_low_s16(bflip); bfh = vget_high_s16(bflip); - - ab_re0 = vmull_s16(al,bcl); - ab_re1 = vmull_s16(ah,bch); - ab_im0 = vmull_s16(al,bfl); - ab_im1 = vmull_s16(ah,bfh); - abr0l = vget_low_s32(ab_re0); abr0h = vget_high_s32(ab_re0); - abr1l = vget_low_s32(ab_re1); abr1h = vget_high_s32(ab_re1); - abi0l = vget_low_s32(ab_im0); abi0h = vget_high_s32(ab_im0); - abi1l = vget_low_s32(ab_im1); abi1h = vget_high_s32(ab_im1); - - *re32 = vcombine_s32(vpadd_s32(abr0l,abr0h), - vpadd_s32(abr1l,abr1h)); - *im32 = vcombine_s32(vpadd_s32(abi0l,abi0h), - vpadd_s32(abi1l,abi1h)); -} - -static inline void cmultc(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) __attribute__((always_inline)); - -static inline void cmultc(int16x8_t a,int16x8_t b, int32x4_t *re32, int32x4_t *im32) -{ - int32x4_t ab_re0,ab_re1,ab_im0,ab_im1; - int16x8_t bconj = vmulq_s16(b,*(int16x8_t *)reflip); - int16x8_t bflip = vrev32q_s16(bconj); - int16x4_t al,ah,bl,bh,bfl,bfh; - int32x2_t abr0l,abr0h,abr1l,abr1h,abi0l,abi0h,abi1l,abi1h; - al = vget_low_s16(a); ah = vget_high_s16(a); - bl = vget_low_s16(b); bh = vget_high_s16(b); - bfl = vget_low_s16(bflip); bfh = vget_high_s16(bflip); - - ab_re0 = vmull_s16(al,bl); - ab_re1 = vmull_s16(ah,bh); - ab_im0 = vmull_s16(al,bfl); - ab_im1 = vmull_s16(ah,bfh); - - abr0l = vget_low_s32(ab_re0); abr0h = vget_high_s32(ab_re0); - abr1l = vget_low_s32(ab_re1); abr1h = vget_high_s32(ab_re1); - abi0l = vget_low_s32(ab_im0); abi0h = vget_high_s32(ab_im0); - abi1l = vget_low_s32(ab_im1); abi1h = vget_high_s32(ab_im1); - - *re32 = vcombine_s32(vpadd_s32(abr0l,abr0h), - vpadd_s32(abr1l,abr1h)); - *im32 = vcombine_s32(vpadd_s32(abi0l,abi0h), - vpadd_s32(abi1l,abi1h)); - -} - - -static inline int16x8_t cpack(int32x4_t xre,int32x4_t xim) __attribute__((always_inline)); - -static inline int16x8_t cpack(int32x4_t xre,int32x4_t xim) -{ - int32x4x2_t xtmp; - - xtmp = vzipq_s32(xre,xim); - return(vcombine_s16(vqshrn_n_s32(xtmp.val[0],15),vqshrn_n_s32(xtmp.val[1],15))); - -} - - -static inline void packed_cmult(int16x8_t a,int16x8_t b, int16x8_t *c) __attribute__((always_inline)); - -static inline void packed_cmult(int16x8_t a,int16x8_t b, int16x8_t *c) -{ - - int32x4_t cre,cim; - cmult(a,b,&cre,&cim); - *c = cpack(cre,cim); - -} - - -static inline void packed_cmultc(int16x8_t a,int16x8_t b, int16x8_t *c) __attribute__((always_inline)); - -static inline void packed_cmultc(int16x8_t a,int16x8_t b, int16x8_t *c) -{ - - int32x4_t cre,cim; - - cmultc(a,b,&cre,&cim); - *c = cpack(cre,cim); - -} - -static inline int16x8_t packed_cmult2(int16x8_t a,int16x8_t b, int16x8_t b2) __attribute__((always_inline)); - -static inline int16x8_t packed_cmult2(int16x8_t a,int16x8_t b, int16x8_t b2) -{ - - - - int32x4_t ab_re0,ab_re1,ab_im0,ab_im1,cre,cim; - - ab_re0 = vmull_s16(((int16x4_t*)&a)[0],((int16x4_t*)&b)[0]); - ab_re1 = vmull_s16(((int16x4_t*)&a)[1],((int16x4_t*)&b)[1]); - ab_im0 = vmull_s16(((int16x4_t*)&a)[0],((int16x4_t*)&b2)[0]); - ab_im1 = vmull_s16(((int16x4_t*)&a)[1],((int16x4_t*)&b2)[1]); - cre = vcombine_s32(vpadd_s32(((int32x2_t*)&ab_re0)[0],((int32x2_t*)&ab_re0)[1]), - vpadd_s32(((int32x2_t*)&ab_re1)[0],((int32x2_t*)&ab_re1)[1])); - cim = vcombine_s32(vpadd_s32(((int32x2_t*)&ab_im0)[0],((int32x2_t*)&ab_im0)[1]), - vpadd_s32(((int32x2_t*)&ab_im1)[0],((int32x2_t*)&ab_im1)[1])); - return(cpack(cre,cim)); - -} - -#endif - -const static int16_t W0s[16]__attribute__((aligned(32))) = {32767,0,32767,0,32767,0,32767,0,32767,0,32767,0,32767,0,32767,0}; - -const static int16_t W13s[16]__attribute__((aligned(32))) = {-16384,-28378,-16384,-28378,-16384,-28378,-16384,-28378,-16384,-28378,-16384,-28378,-16384,-28378,-16384,-28378}; -const static int16_t W23s[16]__attribute__((aligned(32))) = {-16384,28378,-16384,28378,-16384,28378,-16384,28378,-16384,28378,-16384,28378,-16384,28378,-16384,28378}; - -const static int16_t W15s[16]__attribute__((aligned(32))) = {10126,-31163,10126,-31163,10126,-31163,10126,-31163,10126,-31163,10126,-31163,10126,-31163,10126,-31163}; -const static int16_t W25s[16]__attribute__((aligned(32))) = {-26509,-19260,-26509,-19260,-26509,-19260,-26509,-19260,-26509,-19260,-26509,-19260,-26509,-19260,-26509,-19260}; -const static int16_t W35s[16]__attribute__((aligned(32))) = {-26510,19260,-26510,19260,-26510,19260,-26510,19260,-26510,19260,-26510,19260,-26510,19260,-26510,19260}; -const static int16_t W45s[16]__attribute__((aligned(32))) = {10126,31163,10126,31163,10126,31163,10126,31163,10126,31163,10126,31163,10126,31163,10126,31163}; - -#if defined(__x86_64__) || defined(__i386__) -const __m128i *W0 = (__m128i *)W0s; -const __m128i *W13 = (__m128i *)W13s; -const __m128i *W23 = (__m128i *)W23s; -const __m128i *W15 = (__m128i *)W15s; -const __m128i *W25 = (__m128i *)W25s; -const __m128i *W35 = (__m128i *)W35s; -const __m128i *W45 = (__m128i *)W45s; - -#ifdef __AVX2__ -const __m256i *W0_256 = (__m256i *)W0s; -const __m256i *W13_256 = (__m256i *)W13s; -const __m256i *W23_256 = (__m256i *)W23s; -const __m256i *W15_256 = (__m256i *)W15s; -const __m256i *W25_256 = (__m256i *)W25s; -const __m256i *W35_256 = (__m256i *)W35s; -const __m256i *W45_256 = (__m256i *)W45s; -#endif - -#elif defined(__arm__) -int16x8_t *W0 = (int16x8_t *)W0s; -int16x8_t *W13 = (int16x8_t *)W13s; -int16x8_t *W23 = (int16x8_t *)W23s; -int16x8_t *W15 = (int16x8_t *)W15s; -int16x8_t *W25 = (int16x8_t *)W25s; -int16x8_t *W35 = (int16x8_t *)W35s; -int16x8_t *W45 = (int16x8_t *)W45s; -#endif -const static int16_t dft_norm_table[16] = {9459, //12 - 6689,//24 - 5461,//36 - 4729,//482 - 4230,//60 - 23170,//72 - 3344,//96 - 3153,//108 - 2991,//120 - 18918,//sqrt(3),//144 - 18918,//sqrt(3),//180 - 16384,//2, //192 - 18918,//sqrt(3), // 216 - 16384,//2, //240 - 18918,//sqrt(3), // 288 - 14654 -}; //sqrt(5) //300 - - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly2(__m128i *x0, __m128i *x1,__m128i *y0, __m128i *y1,__m128i *tw)__attribute__((always_inline)); - -static inline void bfly2(__m128i *x0, __m128i *x1,__m128i *y0, __m128i *y1,__m128i *tw) -{ - - __m128i x0r_2,x0i_2,x1r_2,x1i_2,dy0r,dy1r,dy0i,dy1i; - __m128i bfly2_tmp1,bfly2_tmp2; - - cmult(*(x0),*(W0),&x0r_2,&x0i_2); - cmult(*(x1),*(tw),&x1r_2,&x1i_2); - - dy0r = _mm_srai_epi32(_mm_add_epi32(x0r_2,x1r_2),15); - dy1r = _mm_srai_epi32(_mm_sub_epi32(x0r_2,x1r_2),15); - dy0i = _mm_srai_epi32(_mm_add_epi32(x0i_2,x1i_2),15); - // printf("y0i %d\n",((int16_t *)y0i)[0]); - dy1i = _mm_srai_epi32(_mm_sub_epi32(x0i_2,x1i_2),15); - - bfly2_tmp1 = _mm_unpacklo_epi32(dy0r,dy0i); - bfly2_tmp2 = _mm_unpackhi_epi32(dy0r,dy0i); - *y0 = _mm_packs_epi32(bfly2_tmp1,bfly2_tmp2); - - bfly2_tmp1 = _mm_unpacklo_epi32(dy1r,dy1i); - bfly2_tmp2 = _mm_unpackhi_epi32(dy1r,dy1i); - *y1 = _mm_packs_epi32(bfly2_tmp1,bfly2_tmp2); -} - -#ifdef __AVX2__ - -static inline void bfly2_256(__m256i *x0, __m256i *x1,__m256i *y0, __m256i *y1,__m256i *tw)__attribute__((always_inline)); - -static inline void bfly2_256(__m256i *x0, __m256i *x1,__m256i *y0, __m256i *y1,__m256i *tw) -{ - - __m256i x0r_2,x0i_2,x1r_2,x1i_2,dy0r,dy1r,dy0i,dy1i; - __m256i bfly2_tmp1,bfly2_tmp2; - - cmult_256(*(x0),*(W0_256),&x0r_2,&x0i_2); - cmult_256(*(x1),*(tw),&x1r_2,&x1i_2); - - dy0r = _mm256_srai_epi32(_mm256_add_epi32(x0r_2,x1r_2),15); - dy1r = _mm256_srai_epi32(_mm256_sub_epi32(x0r_2,x1r_2),15); - dy0i = _mm256_srai_epi32(_mm256_add_epi32(x0i_2,x1i_2),15); - // printf("y0i %d\n",((int16_t *)y0i)[0]); - dy1i = _mm256_srai_epi32(_mm256_sub_epi32(x0i_2,x1i_2),15); - - bfly2_tmp1 = _mm256_unpacklo_epi32(dy0r,dy0i); - bfly2_tmp2 = _mm256_unpackhi_epi32(dy0r,dy0i); - *y0 = _mm256_packs_epi32(bfly2_tmp1,bfly2_tmp2); - - bfly2_tmp1 = _mm256_unpacklo_epi32(dy1r,dy1i); - bfly2_tmp2 = _mm256_unpackhi_epi32(dy1r,dy1i); - *y1 = _mm256_packs_epi32(bfly2_tmp1,bfly2_tmp2); -} - -#endif - -#elif defined(__arm__) - -static inline void bfly2(int16x8_t *x0, int16x8_t *x1,int16x8_t *y0, int16x8_t *y1,int16x8_t *tw)__attribute__((always_inline)); - -static inline void bfly2(int16x8_t *x0, int16x8_t *x1,int16x8_t *y0, int16x8_t *y1,int16x8_t *tw) -{ - - int32x4_t x0r_2,x0i_2,x1r_2,x1i_2,dy0r,dy1r,dy0i,dy1i; - - cmult(*(x0),*(W0),&x0r_2,&x0i_2); - cmult(*(x1),*(tw),&x1r_2,&x1i_2); - - dy0r = vqaddq_s32(x0r_2,x1r_2); - dy1r = vqsubq_s32(x0r_2,x1r_2); - dy0i = vqaddq_s32(x0i_2,x1i_2); - dy1i = vqsubq_s32(x0i_2,x1i_2); - - *y0 = cpack(dy0r,dy0i); - *y1 = cpack(dy1r,dy1i); -} - - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly2_tw1(__m128i *x0, __m128i *x1, __m128i *y0, __m128i *y1)__attribute__((always_inline)); - -static inline void bfly2_tw1(__m128i *x0, __m128i *x1, __m128i *y0, __m128i *y1) -{ - - *y0 = _mm_adds_epi16(*x0,*x1); - *y1 = _mm_subs_epi16(*x0,*x1); - -} - -#elif defined(__arm__) - -static inline void bfly2_tw1(int16x8_t *x0, int16x8_t *x1, int16x8_t *y0, int16x8_t *y1)__attribute__((always_inline)); - -static inline void bfly2_tw1(int16x8_t *x0, int16x8_t *x1, int16x8_t *y0, int16x8_t *y1) -{ - - *y0 = vqaddq_s16(*x0,*x1); - *y1 = vqsubq_s16(*x0,*x1); - -} -#endif - -#if defined(__x86_64__) || defined(__i386__) - - - -static inline void bfly2_16(__m128i *x0, __m128i *x1, __m128i *y0, __m128i *y1, __m128i *tw, __m128i *twb)__attribute__((always_inline)); - -static inline void bfly2_16(__m128i *x0, __m128i *x1, __m128i *y0, __m128i *y1, __m128i *tw, __m128i *twb) -{ - - // register __m128i x1t; - __m128i x1t; - - x1t = packed_cmult2(*(x1),*(tw),*(twb)); - /* - print_shorts("x0",(int16_t*)x0); - print_shorts("x1",(int16_t*)x1); - print_shorts("tw",(int16_t*)tw); - print_shorts("twb",(int16_t*)twb); - print_shorts("x1t",(int16_t*)&x1t);*/ - *y0 = _mm_adds_epi16(*x0,x1t); - *y1 = _mm_subs_epi16(*x0,x1t); - /* print_shorts("y0",(int16_t*)y0); - print_shorts("y1",(int16_t*)y1);*/ -} - -#ifdef __AVX2__ - -static inline void bfly2_16_256(__m256i *x0, __m256i *x1, __m256i *y0, __m256i *y1, __m256i *tw, __m256i *twb)__attribute__((always_inline)); - -static inline void bfly2_16_256(__m256i *x0, __m256i *x1, __m256i *y0, __m256i *y1, __m256i *tw, __m256i *twb) -{ - - // register __m256i x1t; - __m256i x1t; - - x1t = packed_cmult2_256(*(x1),*(tw),*(twb)); - /* - print_shorts256("x0",(int16_t*)x0); - print_shorts256("x1",(int16_t*)x1); - print_shorts256("tw",(int16_t*)tw); - print_shorts256("twb",(int16_t*)twb); - print_shorts256("x1t",(int16_t*)&x1t);*/ - *y0 = _mm256_adds_epi16(*x0,x1t); - *y1 = _mm256_subs_epi16(*x0,x1t); - - /*print_shorts256("y0",(int16_t*)y0); - print_shorts256("y1",(int16_t*)y1);*/ -} -#endif - - -#elif defined(__arm__) - -static inline void bfly2_16(int16x8_t *x0, int16x8_t *x1, int16x8_t *y0, int16x8_t *y1, int16x8_t *tw, int16x8_t *twb)__attribute__((always_inline)); - -static inline void bfly2_16(int16x8_t *x0, int16x8_t *x1, int16x8_t *y0, int16x8_t *y1, int16x8_t *tw, int16x8_t *twb) -{ - - *y0 = vqaddq_s16(*x0,*x1); - *y1 = vqsubq_s16(*x0,*x1); - -} -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void ibfly2(__m128i *x0, __m128i *x1,__m128i *y0, __m128i *y1,__m128i *tw)__attribute__((always_inline)); - -static inline void ibfly2(__m128i *x0, __m128i *x1,__m128i *y0, __m128i *y1,__m128i *tw) -{ - - __m128i x0r_2,x0i_2,x1r_2,x1i_2,dy0r,dy1r,dy0i,dy1i; - __m128i bfly2_tmp1,bfly2_tmp2; - - cmultc(*(x0),*(W0),&x0r_2,&x0i_2); - cmultc(*(x1),*(tw),&x1r_2,&x1i_2); - - dy0r = _mm_srai_epi32(_mm_add_epi32(x0r_2,x1r_2),15); - dy1r = _mm_srai_epi32(_mm_sub_epi32(x0r_2,x1r_2),15); - dy0i = _mm_srai_epi32(_mm_add_epi32(x0i_2,x1i_2),15); - // printf("y0i %d\n",((int16_t *)y0i)[0]); - dy1i = _mm_srai_epi32(_mm_sub_epi32(x0i_2,x1i_2),15); - - bfly2_tmp1 = _mm_unpacklo_epi32(dy0r,dy0i); - bfly2_tmp2 = _mm_unpackhi_epi32(dy0r,dy0i); - *y0 = _mm_packs_epi32(bfly2_tmp1,bfly2_tmp2); - - bfly2_tmp1 = _mm_unpacklo_epi32(dy1r,dy1i); - bfly2_tmp2 = _mm_unpackhi_epi32(dy1r,dy1i); - *y1 = _mm_packs_epi32(bfly2_tmp1,bfly2_tmp2); -} - -#ifdef __AVX2__ -static inline void ibfly2_256(__m256i *x0, __m256i *x1,__m256i *y0, __m256i *y1,__m256i *tw)__attribute__((always_inline)); - -static inline void ibfly2_256(__m256i *x0, __m256i *x1,__m256i *y0, __m256i *y1,__m256i *tw) -{ - - __m256i x0r_2,x0i_2,x1r_2,x1i_2,dy0r,dy1r,dy0i,dy1i; - __m256i bfly2_tmp1,bfly2_tmp2; - - cmultc_256(*(x0),*(W0_256),&x0r_2,&x0i_2); - cmultc_256(*(x1),*(tw),&x1r_2,&x1i_2); - - dy0r = _mm256_srai_epi32(_mm256_add_epi32(x0r_2,x1r_2),15); - dy1r = _mm256_srai_epi32(_mm256_sub_epi32(x0r_2,x1r_2),15); - dy0i = _mm256_srai_epi32(_mm256_add_epi32(x0i_2,x1i_2),15); - // printf("y0i %d\n",((int16_t *)y0i)[0]); - dy1i = _mm256_srai_epi32(_mm256_sub_epi32(x0i_2,x1i_2),15); - - bfly2_tmp1 = _mm256_unpacklo_epi32(dy0r,dy0i); - bfly2_tmp2 = _mm256_unpackhi_epi32(dy0r,dy0i); - *y0 = _mm256_packs_epi32(bfly2_tmp1,bfly2_tmp2); - - bfly2_tmp1 = _mm256_unpacklo_epi32(dy1r,dy1i); - bfly2_tmp2 = _mm256_unpackhi_epi32(dy1r,dy1i); - *y1 = _mm256_packs_epi32(bfly2_tmp1,bfly2_tmp2); -} -#endif - -#elif defined(__arm__) -static inline void ibfly2(int16x8_t *x0, int16x8_t *x1,int16x8_t *y0, int16x8_t *y1,int16x8_t *tw) -{ - - int32x4_t x0r_2,x0i_2,x1r_2,x1i_2,dy0r,dy1r,dy0i,dy1i; - - cmultc(*(x0),*(W0),&x0r_2,&x0i_2); - cmultc(*(x1),*(tw),&x1r_2,&x1i_2); - - dy0r = vqaddq_s32(x0r_2,x1r_2); - dy1r = vqsubq_s32(x0r_2,x1r_2); - dy0i = vqaddq_s32(x0i_2,x1i_2); - dy1i = vqsubq_s32(x0i_2,x1i_2); - - *y0 = cpack(dy0r,dy0i); - *y1 = cpack(dy1r,dy1i); - -} - -#endif - - - - -// This is the radix-3 butterfly (fft) - -#if defined(__x86_64__) || defined(__i386__) - -static inline void bfly3(__m128i *x0,__m128i *x1,__m128i *x2, - __m128i *y0,__m128i *y1,__m128i *y2, - __m128i *tw1,__m128i *tw2) __attribute__((always_inline)); - -static inline void bfly3(__m128i *x0,__m128i *x1,__m128i *x2, - __m128i *y0,__m128i *y1,__m128i *y2, - __m128i *tw1,__m128i *tw2) -{ - - __m128i tmpre,tmpim,x1_2,x2_2; - - packed_cmult(*(x1),*(tw1),&x1_2); - packed_cmult(*(x2),*(tw2),&x2_2); - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(x1_2,x2_2)); - cmult(x1_2,*(W13),&tmpre,&tmpim); - cmac(x2_2,*(W23),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = _mm_adds_epi16(*(x0),*(y1)); - cmult(x1_2,*(W23),&tmpre,&tmpim); - cmac(x2_2,*(W13),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = _mm_adds_epi16(*(x0),*(y2)); -} - -#ifdef __AVX2__ - -static inline void bfly3_256(__m256i *x0,__m256i *x1,__m256i *x2, - __m256i *y0,__m256i *y1,__m256i *y2, - __m256i *tw1,__m256i *tw2) __attribute__((always_inline)); - -static inline void bfly3_256(__m256i *x0,__m256i *x1,__m256i *x2, - __m256i *y0,__m256i *y1,__m256i *y2, - __m256i *tw1,__m256i *tw2) -{ - - __m256i tmpre,tmpim,x1_2,x2_2; - - packed_cmult_256(*(x1),*(tw1),&x1_2); - packed_cmult_256(*(x2),*(tw2),&x2_2); - *(y0) = _mm256_adds_epi16(*(x0),_mm256_adds_epi16(x1_2,x2_2)); - cmult_256(x1_2,*(W13_256),&tmpre,&tmpim); - cmac_256(x2_2,*(W23_256),&tmpre,&tmpim); - *(y1) = cpack_256(tmpre,tmpim); - *(y1) = _mm256_adds_epi16(*(x0),*(y1)); - cmult_256(x1_2,*(W23_256),&tmpre,&tmpim); - cmac_256(x2_2,*(W13_256),&tmpre,&tmpim); - *(y2) = cpack_256(tmpre,tmpim); - *(y2) = _mm256_adds_epi16(*(x0),*(y2)); -} -#endif - -#elif defined(__arm__) -static inline void bfly3(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2, - int16x8_t *tw1,int16x8_t *tw2) __attribute__((always_inline)); - -static inline void bfly3(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2, - int16x8_t *tw1,int16x8_t *tw2) -{ - - int32x4_t tmpre,tmpim; - int16x8_t x1_2,x2_2; - - packed_cmult(*(x1),*(tw1),&x1_2); - packed_cmult(*(x2),*(tw2),&x2_2); - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(x1_2,x2_2)); - cmult(x1_2,*(W13),&tmpre,&tmpim); - cmac(x2_2,*(W23),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = vqaddq_s16(*(x0),*(y1)); - cmult(x1_2,*(W23),&tmpre,&tmpim); - cmac(x2_2,*(W13),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = vqaddq_s16(*(x0),*(y2)); -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void ibfly3(__m128i *x0,__m128i *x1,__m128i *x2, - __m128i *y0,__m128i *y1,__m128i *y2, - __m128i *tw1,__m128i *tw2) __attribute__((always_inline)); - -static inline void ibfly3(__m128i *x0,__m128i *x1,__m128i *x2, - __m128i *y0,__m128i *y1,__m128i *y2, - __m128i *tw1,__m128i *tw2) -{ - - __m128i tmpre,tmpim,x1_2,x2_2; - - packed_cmultc(*(x1),*(tw1),&x1_2); - packed_cmultc(*(x2),*(tw2),&x2_2); - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(x1_2,x2_2)); - cmultc(x1_2,*(W13),&tmpre,&tmpim); - cmacc(x2_2,*(W23),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = _mm_adds_epi16(*(x0),*(y1)); - cmultc(x1_2,*(W23),&tmpre,&tmpim); - cmacc(x2_2,*(W13),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = _mm_adds_epi16(*(x0),*(y2)); -} - -#ifdef __AVX2__ - -static inline void ibfly3_256(__m256i *x0,__m256i *x1,__m256i *x2, - __m256i *y0,__m256i *y1,__m256i *y2, - __m256i *tw1,__m256i *tw2) __attribute__((always_inline)); - -static inline void ibfly3_256(__m256i *x0,__m256i *x1,__m256i *x2, - __m256i *y0,__m256i *y1,__m256i *y2, - __m256i *tw1,__m256i *tw2) -{ - - __m256i tmpre,tmpim,x1_2,x2_2; - - packed_cmultc_256(*(x1),*(tw1),&x1_2); - packed_cmultc_256(*(x2),*(tw2),&x2_2); - *(y0) = _mm256_adds_epi16(*(x0),_mm256_adds_epi16(x1_2,x2_2)); - cmultc_256(x1_2,*(W13_256),&tmpre,&tmpim); - cmacc_256(x2_2,*(W23_256),&tmpre,&tmpim); - *(y1) = cpack_256(tmpre,tmpim); - *(y1) = _mm256_adds_epi16(*(x0),*(y1)); - cmultc_256(x1_2,*(W23_256),&tmpre,&tmpim); - cmacc_256(x2_2,*(W13_256),&tmpre,&tmpim); - *(y2) = cpack_256(tmpre,tmpim); - *(y2) = _mm256_adds_epi16(*(x0),*(y2)); -} -#endif - -#elif defined(__arm__) -static inline void ibfly3(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2, - int16x8_t *tw1,int16x8_t *tw2) __attribute__((always_inline)); - -static inline void ibfly3(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2, - int16x8_t *tw1,int16x8_t *tw2) -{ - - int32x4_t tmpre,tmpim; - int16x8_t x1_2,x2_2; - - packed_cmultc(*(x1),*(tw1),&x1_2); - packed_cmultc(*(x2),*(tw2),&x2_2); - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(x1_2,x2_2)); - cmultc(x1_2,*(W13),&tmpre,&tmpim); - cmacc(x2_2,*(W23),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = vqaddq_s16(*(x0),*(y1)); - cmultc(x1_2,*(W23),&tmpre,&tmpim); - cmacc(x2_2,*(W13),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = vqaddq_s16(*(x0),*(y2)); -} -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly3_tw1(__m128i *x0,__m128i *x1,__m128i *x2, - __m128i *y0,__m128i *y1,__m128i *y2) __attribute__((always_inline)); - -static inline void bfly3_tw1(__m128i *x0,__m128i *x1,__m128i *x2, - __m128i *y0,__m128i *y1,__m128i *y2) -{ - - __m128i tmpre,tmpim; - - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(*(x1),*(x2))); - cmult(*(x1),*(W13),&tmpre,&tmpim); - cmac(*(x2),*(W23),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = _mm_adds_epi16(*(x0),*(y1)); - cmult(*(x1),*(W23),&tmpre,&tmpim); - cmac(*(x2),*(W13),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = _mm_adds_epi16(*(x0),*(y2)); -} - -#ifdef __AVX2__ - -static inline void bfly3_tw1_256(__m256i *x0,__m256i *x1,__m256i *x2, - __m256i *y0,__m256i *y1,__m256i *y2) __attribute__((always_inline)); - -static inline void bfly3_tw1_256(__m256i *x0,__m256i *x1,__m256i *x2, - __m256i *y0,__m256i *y1,__m256i *y2) -{ - - __m256i tmpre,tmpim; - - *(y0) = _mm256_adds_epi16(*(x0),_mm256_adds_epi16(*(x1),*(x2))); - cmult_256(*(x1),*(W13_256),&tmpre,&tmpim); - cmac_256(*(x2),*(W23_256),&tmpre,&tmpim); - *(y1) = cpack_256(tmpre,tmpim); - *(y1) = _mm256_adds_epi16(*(x0),*(y1)); - cmult_256(*(x1),*(W23_256),&tmpre,&tmpim); - cmac_256(*(x2),*(W13_256),&tmpre,&tmpim); - *(y2) = cpack_256(tmpre,tmpim); - *(y2) = _mm256_adds_epi16(*(x0),*(y2)); -} -#endif - -#elif defined(__arm__) -static inline void bfly3_tw1(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2) __attribute__((always_inline)); - -static inline void bfly3_tw1(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2) -{ - - int32x4_t tmpre,tmpim; - - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(*(x1),*(x2))); - cmult(*(x1),*(W13),&tmpre,&tmpim); - cmac(*(x2),*(W23),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = vqaddq_s16(*(x0),*(y1)); - cmult(*(x1),*(W23),&tmpre,&tmpim); - cmac(*(x2),*(W13),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = vqaddq_s16(*(x0),*(y2)); - -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly4(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3)__attribute__((always_inline)); - -static inline void bfly4(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3) -{ - - __m128i x1r_2,x1i_2,x2r_2,x2i_2,x3r_2,x3i_2,dy0r,dy0i,dy1r,dy1i,dy2r,dy2i,dy3r,dy3i; - - // cmult(*(x0),*(W0),&x0r_2,&x0i_2); - cmult(*(x1),*(tw1),&x1r_2,&x1i_2); - cmult(*(x2),*(tw2),&x2r_2,&x2i_2); - cmult(*(x3),*(tw3),&x3r_2,&x3i_2); - // dy0r = _mm_add_epi32(x0r_2,_mm_add_epi32(x1r_2,_mm_add_epi32(x2r_2,x3r_2))); - // dy0i = _mm_add_epi32(x0i_2,_mm_add_epi32(x1i_2,_mm_add_epi32(x2i_2,x3i_2))); - // *(y0) = cpack(dy0r,dy0i); - dy0r = _mm_add_epi32(x1r_2,_mm_add_epi32(x2r_2,x3r_2)); - dy0i = _mm_add_epi32(x1i_2,_mm_add_epi32(x2i_2,x3i_2)); - *(y0) = _mm_add_epi16(*(x0),cpack(dy0r,dy0i)); - // dy1r = _mm_add_epi32(x0r_2,_mm_sub_epi32(x1i_2,_mm_add_epi32(x2r_2,x3i_2))); - // dy1i = _mm_sub_epi32(x0i_2,_mm_add_epi32(x1r_2,_mm_sub_epi32(x2i_2,x3r_2))); - // *(y1) = cpack(dy1r,dy1i); - dy1r = _mm_sub_epi32(x1i_2,_mm_add_epi32(x2r_2,x3i_2)); - dy1i = _mm_sub_epi32(_mm_sub_epi32(x3r_2,x2i_2),x1r_2); - *(y1) = _mm_add_epi16(*(x0),cpack(dy1r,dy1i)); - // dy2r = _mm_sub_epi32(x0r_2,_mm_sub_epi32(x1r_2,_mm_sub_epi32(x2r_2,x3r_2))); - // dy2i = _mm_sub_epi32(x0i_2,_mm_sub_epi32(x1i_2,_mm_sub_epi32(x2i_2,x3i_2))); - // *(y2) = cpack(dy2r,dy2i); - dy2r = _mm_sub_epi32(_mm_sub_epi32(x2r_2,x3r_2),x1r_2); - dy2i = _mm_sub_epi32(_mm_sub_epi32(x2i_2,x3i_2),x1i_2); - *(y2) = _mm_add_epi16(*(x0),cpack(dy2r,dy2i)); - // dy3r = _mm_sub_epi32(x0r_2,_mm_add_epi32(x1i_2,_mm_sub_epi32(x2r_2,x3i_2))); - // dy3i = _mm_add_epi32(x0i_2,_mm_sub_epi32(x1r_2,_mm_add_epi32(x2i_2,x3r_2))); - // *(y3) = cpack(dy3r,dy3i); - dy3r = _mm_sub_epi32(_mm_sub_epi32(x3i_2,x2r_2),x1i_2); - dy3i = _mm_sub_epi32(x1r_2,_mm_add_epi32(x2i_2,x3r_2)); - *(y3) = _mm_add_epi16(*(x0),cpack(dy3r,dy3i)); -} - -#ifdef __AVX2__ -static inline void bfly4_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3)__attribute__((always_inline)); - -static inline void bfly4_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3) -{ - - __m256i x1r_2,x1i_2,x2r_2,x2i_2,x3r_2,x3i_2,dy0r,dy0i,dy1r,dy1i,dy2r,dy2i,dy3r,dy3i; - - // cmult(*(x0),*(W0),&x0r_2,&x0i_2); - cmult_256(*(x1),*(tw1),&x1r_2,&x1i_2); - cmult_256(*(x2),*(tw2),&x2r_2,&x2i_2); - cmult_256(*(x3),*(tw3),&x3r_2,&x3i_2); - // dy0r = _mm_add_epi32(x0r_2,_mm_add_epi32(x1r_2,_mm_add_epi32(x2r_2,x3r_2))); - // dy0i = _mm_add_epi32(x0i_2,_mm_add_epi32(x1i_2,_mm_add_epi32(x2i_2,x3i_2))); - // *(y0) = cpack(dy0r,dy0i); - dy0r = _mm256_add_epi32(x1r_2,_mm256_add_epi32(x2r_2,x3r_2)); - dy0i = _mm256_add_epi32(x1i_2,_mm256_add_epi32(x2i_2,x3i_2)); - *(y0) = _mm256_add_epi16(*(x0),cpack_256(dy0r,dy0i)); - // dy1r = _mm_add_epi32(x0r_2,_mm_sub_epi32(x1i_2,_mm_add_epi32(x2r_2,x3i_2))); - // dy1i = _mm_sub_epi32(x0i_2,_mm_add_epi32(x1r_2,_mm_sub_epi32(x2i_2,x3r_2))); - // *(y1) = cpack(dy1r,dy1i); - dy1r = _mm256_sub_epi32(x1i_2,_mm256_add_epi32(x2r_2,x3i_2)); - dy1i = _mm256_sub_epi32(_mm256_sub_epi32(x3r_2,x2i_2),x1r_2); - *(y1) = _mm256_add_epi16(*(x0),cpack_256(dy1r,dy1i)); - // dy2r = _mm_sub_epi32(x0r_2,_mm_sub_epi32(x1r_2,_mm_sub_epi32(x2r_2,x3r_2))); - // dy2i = _mm_sub_epi32(x0i_2,_mm_sub_epi32(x1i_2,_mm_sub_epi32(x2i_2,x3i_2))); - // *(y2) = cpack(dy2r,dy2i); - dy2r = _mm256_sub_epi32(_mm256_sub_epi32(x2r_2,x3r_2),x1r_2); - dy2i = _mm256_sub_epi32(_mm256_sub_epi32(x2i_2,x3i_2),x1i_2); - *(y2) = _mm256_add_epi16(*(x0),cpack_256(dy2r,dy2i)); - // dy3r = _mm_sub_epi32(x0r_2,_mm_add_epi32(x1i_2,_mm_sub_epi32(x2r_2,x3i_2))); - // dy3i = _mm_add_epi32(x0i_2,_mm_sub_epi32(x1r_2,_mm_add_epi32(x2i_2,x3r_2))); - // *(y3) = cpack(dy3r,dy3i); - dy3r = _mm256_sub_epi32(_mm256_sub_epi32(x3i_2,x2r_2),x1i_2); - dy3i = _mm256_sub_epi32(x1r_2,_mm256_add_epi32(x2i_2,x3r_2)); - *(y3) = _mm256_add_epi16(*(x0),cpack_256(dy3r,dy3i)); -} -#endif -#elif defined(__arm__) -static inline void bfly4(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3)__attribute__((always_inline)); - -static inline void bfly4(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3) -{ - - int32x4_t x1r_2,x1i_2,x2r_2,x2i_2,x3r_2,x3i_2,dy0r,dy0i,dy1r,dy1i,dy2r,dy2i,dy3r,dy3i; - - // cmult(*(x0),*(W0),&x0r_2,&x0i_2); - cmult(*(x1),*(tw1),&x1r_2,&x1i_2); - cmult(*(x2),*(tw2),&x2r_2,&x2i_2); - cmult(*(x3),*(tw3),&x3r_2,&x3i_2); - // dy0r = _mm_add_epi32(x0r_2,_mm_add_epi32(x1r_2,_mm_add_epi32(x2r_2,x3r_2))); - // dy0i = _mm_add_epi32(x0i_2,_mm_add_epi32(x1i_2,_mm_add_epi32(x2i_2,x3i_2))); - // *(y0) = cpack(dy0r,dy0i); - dy0r = vqaddq_s32(x1r_2,vqaddq_s32(x2r_2,x3r_2)); - dy0i = vqaddq_s32(x1i_2,vqaddq_s32(x2i_2,x3i_2)); - *(y0) = vqaddq_s16(*(x0),cpack(dy0r,dy0i)); - // dy1r = _mm_add_epi32(x0r_2,_mm_sub_epi32(x1i_2,_mm_add_epi32(x2r_2,x3i_2))); - // dy1i = _mm_sub_epi32(x0i_2,_mm_add_epi32(x1r_2,_mm_sub_epi32(x2i_2,x3r_2))); - // *(y1) = cpack(dy1r,dy1i); - dy1r = vqsubq_s32(x1i_2,vqaddq_s32(x2r_2,x3i_2)); - dy1i = vqsubq_s32(vqsubq_s32(x3r_2,x2i_2),x1r_2); - *(y1) = vqaddq_s16(*(x0),cpack(dy1r,dy1i)); - // dy2r = _mm_sub_epi32(x0r_2,_mm_sub_epi32(x1r_2,_mm_sub_epi32(x2r_2,x3r_2))); - // dy2i = _mm_sub_epi32(x0i_2,_mm_sub_epi32(x1i_2,_mm_sub_epi32(x2i_2,x3i_2))); - // *(y2) = cpack(dy2r,dy2i); - dy2r = vqsubq_s32(vqsubq_s32(x2r_2,x3r_2),x1r_2); - dy2i = vqsubq_s32(vqsubq_s32(x2i_2,x3i_2),x1i_2); - *(y2) = vqaddq_s16(*(x0),cpack(dy2r,dy2i)); - // dy3r = _mm_sub_epi32(x0r_2,_mm_add_epi32(x1i_2,_mm_sub_epi32(x2r_2,x3i_2))); - // dy3i = _mm_add_epi32(x0i_2,_mm_sub_epi32(x1r_2,_mm_add_epi32(x2i_2,x3r_2))); - // *(y3) = cpack(dy3r,dy3i); - dy3r = vqsubq_s32(vqsubq_s32(x3i_2,x2r_2),x1i_2); - dy3i = vqsubq_s32(x1r_2,vqaddq_s32(x2i_2,x3r_2)); - *(y3) = vqaddq_s16(*(x0),cpack(dy3r,dy3i)); -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void ibfly4(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3)__attribute__((always_inline)); - -static inline void ibfly4(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3) -{ - - __m128i x1r_2,x1i_2,x2r_2,x2i_2,x3r_2,x3i_2,dy0r,dy0i,dy1r,dy1i,dy2r,dy2i,dy3r,dy3i; - - - cmultc(*(x1),*(tw1),&x1r_2,&x1i_2); - cmultc(*(x2),*(tw2),&x2r_2,&x2i_2); - cmultc(*(x3),*(tw3),&x3r_2,&x3i_2); - - dy0r = _mm_add_epi32(x1r_2,_mm_add_epi32(x2r_2,x3r_2)); - dy0i = _mm_add_epi32(x1i_2,_mm_add_epi32(x2i_2,x3i_2)); - *(y0) = _mm_add_epi16(*(x0),cpack(dy0r,dy0i)); - dy3r = _mm_sub_epi32(x1i_2,_mm_add_epi32(x2r_2,x3i_2)); - dy3i = _mm_sub_epi32(_mm_sub_epi32(x3r_2,x2i_2),x1r_2); - *(y3) = _mm_add_epi16(*(x0),cpack(dy3r,dy3i)); - dy2r = _mm_sub_epi32(_mm_sub_epi32(x2r_2,x3r_2),x1r_2); - dy2i = _mm_sub_epi32(_mm_sub_epi32(x2i_2,x3i_2),x1i_2); - *(y2) = _mm_add_epi16(*(x0),cpack(dy2r,dy2i)); - dy1r = _mm_sub_epi32(_mm_sub_epi32(x3i_2,x2r_2),x1i_2); - dy1i = _mm_sub_epi32(x1r_2,_mm_add_epi32(x2i_2,x3r_2)); - *(y1) = _mm_add_epi16(*(x0),cpack(dy1r,dy1i)); -} - -#ifdef __AVX2__ - -static inline void ibfly4_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3)__attribute__((always_inline)); - -static inline void ibfly4_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3) -{ - - __m256i x1r_2,x1i_2,x2r_2,x2i_2,x3r_2,x3i_2,dy0r,dy0i,dy1r,dy1i,dy2r,dy2i,dy3r,dy3i; - - - cmultc_256(*(x1),*(tw1),&x1r_2,&x1i_2); - cmultc_256(*(x2),*(tw2),&x2r_2,&x2i_2); - cmultc_256(*(x3),*(tw3),&x3r_2,&x3i_2); - - dy0r = _mm256_add_epi32(x1r_2,_mm256_add_epi32(x2r_2,x3r_2)); - dy0i = _mm256_add_epi32(x1i_2,_mm256_add_epi32(x2i_2,x3i_2)); - *(y0) = _mm256_add_epi16(*(x0),cpack_256(dy0r,dy0i)); - dy3r = _mm256_sub_epi32(x1i_2,_mm256_add_epi32(x2r_2,x3i_2)); - dy3i = _mm256_sub_epi32(_mm256_sub_epi32(x3r_2,x2i_2),x1r_2); - *(y3) = _mm256_add_epi16(*(x0),cpack_256(dy3r,dy3i)); - dy2r = _mm256_sub_epi32(_mm256_sub_epi32(x2r_2,x3r_2),x1r_2); - dy2i = _mm256_sub_epi32(_mm256_sub_epi32(x2i_2,x3i_2),x1i_2); - *(y2) = _mm256_add_epi16(*(x0),cpack_256(dy2r,dy2i)); - dy1r = _mm256_sub_epi32(_mm256_sub_epi32(x3i_2,x2r_2),x1i_2); - dy1i = _mm256_sub_epi32(x1r_2,_mm256_add_epi32(x2i_2,x3r_2)); - *(y1) = _mm256_add_epi16(*(x0),cpack_256(dy1r,dy1i)); -} - -#endif -#elif defined(__arm__) - -static inline void ibfly4(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3)__attribute__((always_inline)); - -static inline void ibfly4(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3) -{ - - int32x4_t x1r_2,x1i_2,x2r_2,x2i_2,x3r_2,x3i_2,dy0r,dy0i,dy1r,dy1i,dy2r,dy2i,dy3r,dy3i; - - - cmultc(*(x1),*(tw1),&x1r_2,&x1i_2); - cmultc(*(x2),*(tw2),&x2r_2,&x2i_2); - cmultc(*(x3),*(tw3),&x3r_2,&x3i_2); - - dy0r = vqaddq_s32(x1r_2,vqaddq_s32(x2r_2,x3r_2)); - dy0i = vqaddq_s32(x1i_2,vqaddq_s32(x2i_2,x3i_2)); - *(y0) = vqaddq_s16(*(x0),cpack(dy0r,dy0i)); - dy3r = vqsubq_s32(x1i_2,vqaddq_s32(x2r_2,x3i_2)); - dy3i = vqsubq_s32(vqsubq_s32(x3r_2,x2i_2),x1r_2); - *(y3) = vqaddq_s16(*(x0),cpack(dy3r,dy3i)); - dy2r = vqsubq_s32(vqsubq_s32(x2r_2,x3r_2),x1r_2); - dy2i = vqsubq_s32(vqsubq_s32(x2i_2,x3i_2),x1i_2); - *(y2) = vqaddq_s16(*(x0),cpack(dy2r,dy2i)); - dy1r = vqsubq_s32(vqsubq_s32(x3i_2,x2r_2),x1i_2); - dy1i = vqsubq_s32(x1r_2,vqaddq_s32(x2i_2,x3r_2)); - *(y1) = vqaddq_s16(*(x0),cpack(dy1r,dy1i)); -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) - -static inline void bfly4_tw1(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3)__attribute__((always_inline)); - -static inline void bfly4_tw1(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3) -{ - register __m128i x1_flip,x3_flip,x02t,x13t; - register __m128i complex_shuffle = _mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - x02t = _mm_adds_epi16(*(x0),*(x2)); - x13t = _mm_adds_epi16(*(x1),*(x3)); - *(y0) = _mm_adds_epi16(x02t,x13t); - *(y2) = _mm_subs_epi16(x02t,x13t); - x1_flip = _mm_sign_epi16(*(x1),*(__m128i*)conjugatedft); - x1_flip = _mm_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm_sign_epi16(*(x3),*(__m128i*)conjugatedft); - x3_flip = _mm_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm_subs_epi16(*(x0),*(x2)); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - *(y1) = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y3) = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - /* - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(*(x1),_mm_adds_epi16(*(x2),*(x3)))); - x1_flip = _mm_sign_epi16(*(x1),*(__m128i*)conjugatedft); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(*(x3),*(__m128i*)conjugatedft); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - *(y1) = _mm_adds_epi16(*(x0),_mm_subs_epi16(x1_flip,_mm_adds_epi16(*(x2),x3_flip))); - *(y2) = _mm_subs_epi16(*(x0),_mm_subs_epi16(*(x1),_mm_subs_epi16(*(x2),*(x3)))); - *(y3) = _mm_subs_epi16(*(x0),_mm_adds_epi16(x1_flip,_mm_subs_epi16(*(x2),x3_flip))); - */ -} - -#ifdef __AVX2__ - -static inline void bfly4_tw1_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3)__attribute__((always_inline)); - -static inline void bfly4_tw1_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3) -{ - register __m256i x1_flip,x3_flip,x02t,x13t; - register __m256i complex_shuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - x02t = _mm256_adds_epi16(*(x0),*(x2)); - x13t = _mm256_adds_epi16(*(x1),*(x3)); - *(y0) = _mm256_adds_epi16(x02t,x13t); - *(y2) = _mm256_subs_epi16(x02t,x13t); - x1_flip = _mm256_sign_epi16(*(x1),*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(*(x3),*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(*(x0),*(x2)); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - *(y1) = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y3) = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f -} -#endif - -#elif defined(__arm__) - -static inline void bfly4_tw1(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3)__attribute__((always_inline)); - -static inline void bfly4_tw1(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3) -{ - - register int16x8_t x1_flip,x3_flip; - - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(*(x1),vqaddq_s16(*(x2),*(x3)))); - x1_flip = vrev32q_s16(vmulq_s16(*(x1),*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(*(x3),*(int16x8_t*)conjugatedft)); - *(y1) = vqaddq_s16(*(x0),vqsubq_s16(x1_flip,vqaddq_s16(*(x2),x3_flip))); - *(y2) = vqsubq_s16(*(x0),vqsubq_s16(*(x1),vqsubq_s16(*(x2),*(x3)))); - *(y3) = vqsubq_s16(*(x0),vqaddq_s16(x1_flip,vqsubq_s16(*(x2),x3_flip))); -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) - -static inline void ibfly4_tw1(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3)__attribute__((always_inline)); - -static inline void ibfly4_tw1(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3) -{ - - register __m128i x1_flip,x3_flip; - - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(*(x1),_mm_adds_epi16(*(x2),*(x3)))); - - x1_flip = _mm_sign_epi16(*(x1),*(__m128i*)conjugatedft); - // x1_flip = _mm_shufflelo_epi16(x1_flip,_MM_SHUFFLE(2,3,0,1)); - // x1_flip = _mm_shufflehi_epi16(x1_flip,_MM_SHUFFLE(2,3,0,1)); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(*(x3),*(__m128i*)conjugatedft); - // x3_flip = _mm_shufflelo_epi16(x3_flip,_MM_SHUFFLE(2,3,0,1)); - // x3_flip = _mm_shufflehi_epi16(x3_flip,_MM_SHUFFLE(2,3,0,1)); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - *(y1) = _mm_subs_epi16(*(x0),_mm_adds_epi16(x1_flip,_mm_subs_epi16(*(x2),x3_flip))); - *(y2) = _mm_subs_epi16(*(x0),_mm_subs_epi16(*(x1),_mm_subs_epi16(*(x2),*(x3)))); - *(y3) = _mm_adds_epi16(*(x0),_mm_subs_epi16(x1_flip,_mm_adds_epi16(*(x2),x3_flip))); -} - - -#elif defined(__arm__) -static inline void ibfly4_tw1(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3)__attribute__((always_inline)); - -static inline void ibfly4_tw1(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3) -{ - - register int16x8_t x1_flip,x3_flip; - - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(*(x1),vqaddq_s16(*(x2),*(x3)))); - x1_flip = vrev32q_s16(vmulq_s16(*(x1),*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(*(x3),*(int16x8_t*)conjugatedft)); - *(y1) = vqsubq_s16(*(x0),vqaddq_s16(x1_flip,vqsubq_s16(*(x2),x3_flip))); - *(y2) = vqsubq_s16(*(x0),vqsubq_s16(*(x1),vqsubq_s16(*(x2),*(x3)))); - *(y3) = vqaddq_s16(*(x0),vqsubq_s16(x1_flip,vqaddq_s16(*(x2),x3_flip))); -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly4_16(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3, - __m128i *tw1b,__m128i *tw2b,__m128i *tw3b)__attribute__((always_inline)); - -static inline void bfly4_16(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3, - __m128i *tw1b,__m128i *tw2b,__m128i *tw3b) -{ - - register __m128i x1t,x2t,x3t,x02t,x13t; - register __m128i x1_flip,x3_flip; - - x1t = packed_cmult2(*(x1),*(tw1),*(tw1b)); - x2t = packed_cmult2(*(x2),*(tw2),*(tw2b)); - x3t = packed_cmult2(*(x3),*(tw3),*(tw3b)); - - - // bfly4_tw1(x0,&x1t,&x2t,&x3t,y0,y1,y2,y3); - x02t = _mm_adds_epi16(*(x0),x2t); - x13t = _mm_adds_epi16(x1t,x3t); - /* - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(x1t,_mm_adds_epi16(x2t,x3t))); - *(y2) = _mm_subs_epi16(*(x0),_mm_subs_epi16(x1t,_mm_subs_epi16(x2t,x3t))); - */ - *(y0) = _mm_adds_epi16(x02t,x13t); - *(y2) = _mm_subs_epi16(x02t,x13t); - - x1_flip = _mm_sign_epi16(x1t,*(__m128i*)conjugatedft); - // x1_flip = _mm_shufflelo_epi16(x1_flip,_MM_SHUFFLE(2,3,0,1)); - // x1_flip = _mm_shufflehi_epi16(x1_flip,_MM_SHUFFLE(2,3,0,1)); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(x3t,*(__m128i*)conjugatedft); - // x3_flip = _mm_shufflelo_epi16(x3_flip,_MM_SHUFFLE(2,3,0,1)); - // x3_flip = _mm_shufflehi_epi16(x3_flip,_MM_SHUFFLE(2,3,0,1)); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x02t = _mm_subs_epi16(*(x0),x2t); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - /* - *(y1) = _mm_adds_epi16(*(x0),_mm_subs_epi16(x1_flip,_mm_adds_epi16(x2t,x3_flip))); // x0 + x1f - x2 - x3f - *(y3) = _mm_subs_epi16(*(x0),_mm_adds_epi16(x1_flip,_mm_subs_epi16(x2t,x3_flip))); // x0 - x1f - x2 + x3f - */ - *(y1) = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y3) = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - -} - -#ifdef __AVX2__ -static inline void bfly4_16_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3, - __m256i *tw1b,__m256i *tw2b,__m256i *tw3b)__attribute__((always_inline)); - -static inline void bfly4_16_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3, - __m256i *tw1b,__m256i *tw2b,__m256i *tw3b) -{ - - register __m256i x1t,x2t,x3t,x02t,x13t; - register __m256i x1_flip,x3_flip; - register __m256i complex_shuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - // each input xi is assumed to be to consecutive vectors xi0 xi1 on which to perform the 8 butterflies - // [xi00 xi01 xi02 xi03 xi10 xi20 xi30 xi40] - // each output yi is the same - - x1t = packed_cmult2_256(*(x1),*(tw1),*(tw1b)); - x2t = packed_cmult2_256(*(x2),*(tw2),*(tw2b)); - x3t = packed_cmult2_256(*(x3),*(tw3),*(tw3b)); - - x02t = _mm256_adds_epi16(*(x0),x2t); - x13t = _mm256_adds_epi16(x1t,x3t); - *(y0) = _mm256_adds_epi16(x02t,x13t); - *(y2) = _mm256_subs_epi16(x02t,x13t); - - x1_flip = _mm256_sign_epi16(x1t,*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(x3t,*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(*(x0),x2t); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - *(y1) = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y3) = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - -} - -#endif - -#elif defined(__arm__) - -static inline void bfly4_16(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3, - int16x8_t *tw1b,int16x8_t *tw2b,int16x8_t *tw3b)__attribute__((always_inline)); - -static inline void bfly4_16(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3, - int16x8_t *tw1b,int16x8_t *tw2b,int16x8_t *tw3b) -{ - - register int16x8_t x1t,x2t,x3t,x02t,x13t; - register int16x8_t x1_flip,x3_flip; - - x1t = packed_cmult2(*(x1),*(tw1),*(tw1b)); - x2t = packed_cmult2(*(x2),*(tw2),*(tw2b)); - x3t = packed_cmult2(*(x3),*(tw3),*(tw3b)); - - - - x02t = vqaddq_s16(*(x0),x2t); - x13t = vqaddq_s16(x1t,x3t); - *(y0) = vqaddq_s16(x02t,x13t); - *(y2) = vqsubq_s16(x02t,x13t); - x1_flip = vrev32q_s16(vmulq_s16(x1t,*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(x3t,*(int16x8_t*)conjugatedft)); - x02t = vqsubq_s16(*(x0),x2t); - x13t = vqsubq_s16(x1_flip,x3_flip); - *(y1) = vqaddq_s16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y3) = vqsubq_s16(x02t,x13t); // x0 - x1f - x2 + x3f -} -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void ibfly4_16(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3, - __m128i *tw1b,__m128i *tw2b,__m128i *tw3b)__attribute__((always_inline)); - -static inline void ibfly4_16(__m128i *x0,__m128i *x1,__m128i *x2,__m128i *x3, - __m128i *y0,__m128i *y1,__m128i *y2,__m128i *y3, - __m128i *tw1,__m128i *tw2,__m128i *tw3, - __m128i *tw1b,__m128i *tw2b,__m128i *tw3b) -{ - - register __m128i x1t,x2t,x3t,x02t,x13t; - register __m128i x1_flip,x3_flip; - - x1t = packed_cmult2(*(x1),*(tw1),*(tw1b)); - x2t = packed_cmult2(*(x2),*(tw2),*(tw2b)); - x3t = packed_cmult2(*(x3),*(tw3),*(tw3b)); - - - // bfly4_tw1(x0,&x1t,&x2t,&x3t,y0,y1,y2,y3); - x02t = _mm_adds_epi16(*(x0),x2t); - x13t = _mm_adds_epi16(x1t,x3t); - /* - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(x1t,_mm_adds_epi16(x2t,x3t))); - *(y2) = _mm_subs_epi16(*(x0),_mm_subs_epi16(x1t,_mm_subs_epi16(x2t,x3t))); - */ - *(y0) = _mm_adds_epi16(x02t,x13t); - *(y2) = _mm_subs_epi16(x02t,x13t); - - x1_flip = _mm_sign_epi16(x1t,*(__m128i*)conjugatedft); - // x1_flip = _mm_shufflelo_epi16(x1_flip,_MM_SHUFFLE(2,3,0,1)); - // x1_flip = _mm_shufflehi_epi16(x1_flip,_MM_SHUFFLE(2,3,0,1)); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(x3t,*(__m128i*)conjugatedft); - // x3_flip = _mm_shufflelo_epi16(x3_flip,_MM_SHUFFLE(2,3,0,1)); - // x3_flip = _mm_shufflehi_epi16(x3_flip,_MM_SHUFFLE(2,3,0,1)); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x02t = _mm_subs_epi16(*(x0),x2t); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - /* - *(y1) = _mm_adds_epi16(*(x0),_mm_subs_epi16(x1_flip,_mm_adds_epi16(x2t,x3_flip))); // x0 + x1f - x2 - x3f - *(y3) = _mm_subs_epi16(*(x0),_mm_adds_epi16(x1_flip,_mm_subs_epi16(x2t,x3_flip))); // x0 - x1f - x2 + x3f - */ - *(y3) = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y1) = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - -} - -#ifdef __AVX2__ -static inline void ibfly4_16_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3, - __m256i *tw1b,__m256i *tw2b,__m256i *tw3b)__attribute__((always_inline)); - -static inline void ibfly4_16_256(__m256i *x0,__m256i *x1,__m256i *x2,__m256i *x3, - __m256i *y0,__m256i *y1,__m256i *y2,__m256i *y3, - __m256i *tw1,__m256i *tw2,__m256i *tw3, - __m256i *tw1b,__m256i *tw2b,__m256i *tw3b) -{ - - register __m256i x1t,x2t,x3t,x02t,x13t; - register __m256i x1_flip,x3_flip; - register __m256i complex_shuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - // each input xi is assumed to be to consecutive vectors xi0 xi1 on which to perform the 8 butterflies - // [xi00 xi01 xi02 xi03 xi10 xi20 xi30 xi40] - // each output yi is the same - - x1t = packed_cmult2_256(*(x1),*(tw1),*(tw1b)); - x2t = packed_cmult2_256(*(x2),*(tw2),*(tw2b)); - x3t = packed_cmult2_256(*(x3),*(tw3),*(tw3b)); - - x02t = _mm256_adds_epi16(*(x0),x2t); - x13t = _mm256_adds_epi16(x1t,x3t); - *(y0) = _mm256_adds_epi16(x02t,x13t); - *(y2) = _mm256_subs_epi16(x02t,x13t); - - x1_flip = _mm256_sign_epi16(x1t,*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(x3t,*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(*(x0),x2t); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - *(y3) = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - *(y1) = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - -} -#endif - -#elif defined(__arm__) -static inline void ibfly4_16(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3, - int16x8_t *tw1b,int16x8_t *tw2b,int16x8_t *tw3b)__attribute__((always_inline)); - -static inline void ibfly4_16(int16x8_t *x0,int16x8_t *x1,int16x8_t *x2,int16x8_t *x3, - int16x8_t *y0,int16x8_t *y1,int16x8_t *y2,int16x8_t *y3, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3, - int16x8_t *tw1b,int16x8_t *tw2b,int16x8_t *tw3b) -{ - - register int16x8_t x1t,x2t,x3t,x02t,x13t; - register int16x8_t x1_flip,x3_flip; - - x1t = packed_cmult2(*(x1),*(tw1),*(tw1b)); - x2t = packed_cmult2(*(x2),*(tw2),*(tw2b)); - x3t = packed_cmult2(*(x3),*(tw3),*(tw3b)); - - x02t = vqaddq_s16(*(x0),x2t); - x13t = vqaddq_s16(x1t,x3t); - *(y0) = vqaddq_s16(x02t,x13t); - *(y2) = vqsubq_s16(x02t,x13t); - x1_flip = vrev32q_s16(vmulq_s16(x1t,*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(x3t,*(int16x8_t*)conjugatedft)); - x02t = vqsubq_s16(*(x0),x2t); - x13t = vqsubq_s16(x1_flip,x3_flip); - *(y3) = vqaddq_s16(x02t,x13t); // x0 - x1f - x2 + x3f - *(y1) = vqsubq_s16(x02t,x13t); // x0 + x1f - x2 - x3f -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly5(__m128i *x0, __m128i *x1, __m128i *x2, __m128i *x3,__m128i *x4, - __m128i *y0, __m128i *y1, __m128i *y2, __m128i *y3,__m128i *y4, - __m128i *tw1,__m128i *tw2,__m128i *tw3,__m128i *tw4)__attribute__((always_inline)); - -static inline void bfly5(__m128i *x0, __m128i *x1, __m128i *x2, __m128i *x3,__m128i *x4, - __m128i *y0, __m128i *y1, __m128i *y2, __m128i *y3,__m128i *y4, - __m128i *tw1,__m128i *tw2,__m128i *tw3,__m128i *tw4) -{ - - - - __m128i x1_2,x2_2,x3_2,x4_2,tmpre,tmpim; - - packed_cmult(*(x1),*(tw1),&x1_2); - packed_cmult(*(x2),*(tw2),&x2_2); - packed_cmult(*(x3),*(tw3),&x3_2); - packed_cmult(*(x4),*(tw4),&x4_2); - - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(x1_2,_mm_adds_epi16(x2_2,_mm_adds_epi16(x3_2,x4_2)))); - cmult(x1_2,*(W15),&tmpre,&tmpim); - cmac(x2_2,*(W25),&tmpre,&tmpim); - cmac(x3_2,*(W35),&tmpre,&tmpim); - cmac(x4_2,*(W45),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = _mm_adds_epi16(*(x0),*(y1)); - - cmult(x1_2,*(W25),&tmpre,&tmpim); - cmac(x2_2,*(W45),&tmpre,&tmpim); - cmac(x3_2,*(W15),&tmpre,&tmpim); - cmac(x4_2,*(W35),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = _mm_adds_epi16(*(x0),*(y2)); - - cmult(x1_2,*(W35),&tmpre,&tmpim); - cmac(x2_2,*(W15),&tmpre,&tmpim); - cmac(x3_2,*(W45),&tmpre,&tmpim); - cmac(x4_2,*(W25),&tmpre,&tmpim); - *(y3) = cpack(tmpre,tmpim); - *(y3) = _mm_adds_epi16(*(x0),*(y3)); - - cmult(x1_2,*(W45),&tmpre,&tmpim); - cmac(x2_2,*(W35),&tmpre,&tmpim); - cmac(x3_2,*(W25),&tmpre,&tmpim); - cmac(x4_2,*(W15),&tmpre,&tmpim); - *(y4) = cpack(tmpre,tmpim); - *(y4) = _mm_adds_epi16(*(x0),*(y4)); - - -} - -#ifdef __AVX2__ - -static inline void bfly5_256(__m256i *x0, __m256i *x1, __m256i *x2, __m256i *x3,__m256i *x4, - __m256i *y0, __m256i *y1, __m256i *y2, __m256i *y3,__m256i *y4, - __m256i *tw1,__m256i *tw2,__m256i *tw3,__m256i *tw4)__attribute__((always_inline)); - -static inline void bfly5_256(__m256i *x0, __m256i *x1, __m256i *x2, __m256i *x3,__m256i *x4, - __m256i *y0, __m256i *y1, __m256i *y2, __m256i *y3,__m256i *y4, - __m256i *tw1,__m256i *tw2,__m256i *tw3,__m256i *tw4) -{ - - - - __m256i x1_2,x2_2,x3_2,x4_2,tmpre,tmpim; - - packed_cmult_256(*(x1),*(tw1),&x1_2); - packed_cmult_256(*(x2),*(tw2),&x2_2); - packed_cmult_256(*(x3),*(tw3),&x3_2); - packed_cmult_256(*(x4),*(tw4),&x4_2); - - *(y0) = _mm256_adds_epi16(*(x0),_mm256_adds_epi16(x1_2,_mm256_adds_epi16(x2_2,_mm256_adds_epi16(x3_2,x4_2)))); - cmult_256(x1_2,*(W15_256),&tmpre,&tmpim); - cmac_256(x2_2,*(W25_256),&tmpre,&tmpim); - cmac_256(x3_2,*(W35_256),&tmpre,&tmpim); - cmac_256(x4_2,*(W45_256),&tmpre,&tmpim); - *(y1) = cpack_256(tmpre,tmpim); - *(y1) = _mm256_adds_epi16(*(x0),*(y1)); - - cmult_256(x1_2,*(W25_256),&tmpre,&tmpim); - cmac_256(x2_2,*(W45_256),&tmpre,&tmpim); - cmac_256(x3_2,*(W15_256),&tmpre,&tmpim); - cmac_256(x4_2,*(W35_256),&tmpre,&tmpim); - *(y2) = cpack_256(tmpre,tmpim); - *(y2) = _mm256_adds_epi16(*(x0),*(y2)); - - cmult_256(x1_2,*(W35_256),&tmpre,&tmpim); - cmac_256(x2_2,*(W15_256),&tmpre,&tmpim); - cmac_256(x3_2,*(W45_256),&tmpre,&tmpim); - cmac_256(x4_2,*(W25_256),&tmpre,&tmpim); - *(y3) = cpack_256(tmpre,tmpim); - *(y3) = _mm256_adds_epi16(*(x0),*(y3)); - - cmult_256(x1_2,*(W45_256),&tmpre,&tmpim); - cmac_256(x2_2,*(W35_256),&tmpre,&tmpim); - cmac_256(x3_2,*(W25_256),&tmpre,&tmpim); - cmac_256(x4_2,*(W15_256),&tmpre,&tmpim); - *(y4) = cpack_256(tmpre,tmpim); - *(y4) = _mm256_adds_epi16(*(x0),*(y4)); - - -} -#endif - -#elif defined(__arm__) -static inline void bfly5(int16x8_t *x0, int16x8_t *x1, int16x8_t *x2, int16x8_t *x3,int16x8_t *x4, - int16x8_t *y0, int16x8_t *y1, int16x8_t *y2, int16x8_t *y3,int16x8_t *y4, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3,int16x8_t *tw4)__attribute__((always_inline)); - -static inline void bfly5(int16x8_t *x0, int16x8_t *x1, int16x8_t *x2, int16x8_t *x3,int16x8_t *x4, - int16x8_t *y0, int16x8_t *y1, int16x8_t *y2, int16x8_t *y3,int16x8_t *y4, - int16x8_t *tw1,int16x8_t *tw2,int16x8_t *tw3,int16x8_t *tw4) -{ - - - - int16x8_t x1_2,x2_2,x3_2,x4_2; - int32x4_t tmpre,tmpim; - - packed_cmult(*(x1),*(tw1),&x1_2); - packed_cmult(*(x2),*(tw2),&x2_2); - packed_cmult(*(x3),*(tw3),&x3_2); - packed_cmult(*(x4),*(tw4),&x4_2); - - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(x1_2,vqaddq_s16(x2_2,vqaddq_s16(x3_2,x4_2)))); - cmult(x1_2,*(W15),&tmpre,&tmpim); - cmac(x2_2,*(W25),&tmpre,&tmpim); - cmac(x3_2,*(W35),&tmpre,&tmpim); - cmac(x4_2,*(W45),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = vqaddq_s16(*(x0),*(y1)); - - cmult(x1_2,*(W25),&tmpre,&tmpim); - cmac(x2_2,*(W45),&tmpre,&tmpim); - cmac(x3_2,*(W15),&tmpre,&tmpim); - cmac(x4_2,*(W35),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = vqaddq_s16(*(x0),*(y2)); - - cmult(x1_2,*(W35),&tmpre,&tmpim); - cmac(x2_2,*(W15),&tmpre,&tmpim); - cmac(x3_2,*(W45),&tmpre,&tmpim); - cmac(x4_2,*(W25),&tmpre,&tmpim); - *(y3) = cpack(tmpre,tmpim); - *(y3) = vqaddq_s16(*(x0),*(y3)); - - cmult(x1_2,*(W45),&tmpre,&tmpim); - cmac(x2_2,*(W35),&tmpre,&tmpim); - cmac(x3_2,*(W25),&tmpre,&tmpim); - cmac(x4_2,*(W15),&tmpre,&tmpim); - *(y4) = cpack(tmpre,tmpim); - *(y4) = vqaddq_s16(*(x0),*(y4)); - - -} - - -#endif - -#if defined(__x86_64__) || defined(__i386__) -static inline void bfly5_tw1(__m128i *x0, __m128i *x1, __m128i *x2, __m128i *x3,__m128i *x4, - __m128i *y0, __m128i *y1, __m128i *y2, __m128i *y3,__m128i *y4) __attribute__((always_inline)); - -static inline void bfly5_tw1(__m128i *x0, __m128i *x1, __m128i *x2, __m128i *x3,__m128i *x4, - __m128i *y0, __m128i *y1, __m128i *y2, __m128i *y3,__m128i *y4) -{ - - __m128i tmpre,tmpim; - - *(y0) = _mm_adds_epi16(*(x0),_mm_adds_epi16(*(x1),_mm_adds_epi16(*(x2),_mm_adds_epi16(*(x3),*(x4))))); - cmult(*(x1),*(W15),&tmpre,&tmpim); - cmac(*(x2),*(W25),&tmpre,&tmpim); - cmac(*(x3),*(W35),&tmpre,&tmpim); - cmac(*(x4),*(W45),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = _mm_adds_epi16(*(x0),*(y1)); - cmult(*(x1),*(W25),&tmpre,&tmpim); - cmac(*(x2),*(W45),&tmpre,&tmpim); - cmac(*(x3),*(W15),&tmpre,&tmpim); - cmac(*(x4),*(W35),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = _mm_adds_epi16(*(x0),*(y2)); - cmult(*(x1),*(W35),&tmpre,&tmpim); - cmac(*(x2),*(W15),&tmpre,&tmpim); - cmac(*(x3),*(W45),&tmpre,&tmpim); - cmac(*(x4),*(W25),&tmpre,&tmpim); - *(y3) = cpack(tmpre,tmpim); - *(y3) = _mm_adds_epi16(*(x0),*(y3)); - cmult(*(x1),*(W45),&tmpre,&tmpim); - cmac(*(x2),*(W35),&tmpre,&tmpim); - cmac(*(x3),*(W25),&tmpre,&tmpim); - cmac(*(x4),*(W15),&tmpre,&tmpim); - *(y4) = cpack(tmpre,tmpim); - *(y4) = _mm_adds_epi16(*(x0),*(y4)); -} - -#ifdef __AVX2__ -static inline void bfly5_tw1_256(__m256i *x0, __m256i *x1, __m256i *x2, __m256i *x3,__m256i *x4, - __m256i *y0, __m256i *y1, __m256i *y2, __m256i *y3,__m256i *y4) __attribute__((always_inline)); - -static inline void bfly5_tw1_256(__m256i *x0, __m256i *x1, __m256i *x2, __m256i *x3,__m256i *x4, - __m256i *y0, __m256i *y1, __m256i *y2, __m256i *y3,__m256i *y4) -{ - - __m256i tmpre,tmpim; - - *(y0) = _mm256_adds_epi16(*(x0),_mm256_adds_epi16(*(x1),_mm256_adds_epi16(*(x2),_mm256_adds_epi16(*(x3),*(x4))))); - cmult_256(*(x1),*(W15_256),&tmpre,&tmpim); - cmac_256(*(x2),*(W25_256),&tmpre,&tmpim); - cmac_256(*(x3),*(W35_256),&tmpre,&tmpim); - cmac_256(*(x4),*(W45_256),&tmpre,&tmpim); - *(y1) = cpack_256(tmpre,tmpim); - *(y1) = _mm256_adds_epi16(*(x0),*(y1)); - cmult_256(*(x1),*(W25_256),&tmpre,&tmpim); - cmac_256(*(x2),*(W45_256),&tmpre,&tmpim); - cmac_256(*(x3),*(W15_256),&tmpre,&tmpim); - cmac_256(*(x4),*(W35_256),&tmpre,&tmpim); - *(y2) = cpack_256(tmpre,tmpim); - *(y2) = _mm256_adds_epi16(*(x0),*(y2)); - cmult_256(*(x1),*(W35_256),&tmpre,&tmpim); - cmac_256(*(x2),*(W15_256),&tmpre,&tmpim); - cmac_256(*(x3),*(W45_256),&tmpre,&tmpim); - cmac_256(*(x4),*(W25_256),&tmpre,&tmpim); - *(y3) = cpack_256(tmpre,tmpim); - *(y3) = _mm256_adds_epi16(*(x0),*(y3)); - cmult_256(*(x1),*(W45_256),&tmpre,&tmpim); - cmac_256(*(x2),*(W35_256),&tmpre,&tmpim); - cmac_256(*(x3),*(W25_256),&tmpre,&tmpim); - cmac_256(*(x4),*(W15_256),&tmpre,&tmpim); - *(y4) = cpack_256(tmpre,tmpim); - *(y4) = _mm256_adds_epi16(*(x0),*(y4)); -} -#endif -#elif defined(__arm__) -static inline void bfly5_tw1(int16x8_t *x0, int16x8_t *x1, int16x8_t *x2, int16x8_t *x3,int16x8_t *x4, - int16x8_t *y0, int16x8_t *y1, int16x8_t *y2, int16x8_t *y3,int16x8_t *y4) __attribute__((always_inline)); - -static inline void bfly5_tw1(int16x8_t *x0, int16x8_t *x1, int16x8_t *x2, int16x8_t *x3,int16x8_t *x4, - int16x8_t *y0, int16x8_t *y1, int16x8_t *y2, int16x8_t *y3,int16x8_t *y4) -{ - - int32x4_t tmpre,tmpim; - - *(y0) = vqaddq_s16(*(x0),vqaddq_s16(*(x1),vqaddq_s16(*(x2),vqaddq_s16(*(x3),*(x4))))); - cmult(*(x1),*(W15),&tmpre,&tmpim); - cmac(*(x2),*(W25),&tmpre,&tmpim); - cmac(*(x3),*(W35),&tmpre,&tmpim); - cmac(*(x4),*(W45),&tmpre,&tmpim); - *(y1) = cpack(tmpre,tmpim); - *(y1) = vqaddq_s16(*(x0),*(y1)); - cmult(*(x1),*(W25),&tmpre,&tmpim); - cmac(*(x2),*(W45),&tmpre,&tmpim); - cmac(*(x3),*(W15),&tmpre,&tmpim); - cmac(*(x4),*(W35),&tmpre,&tmpim); - *(y2) = cpack(tmpre,tmpim); - *(y2) = vqaddq_s16(*(x0),*(y2)); - cmult(*(x1),*(W35),&tmpre,&tmpim); - cmac(*(x2),*(W15),&tmpre,&tmpim); - cmac(*(x3),*(W45),&tmpre,&tmpim); - cmac(*(x4),*(W25),&tmpre,&tmpim); - *(y3) = cpack(tmpre,tmpim); - *(y3) = vqaddq_s16(*(x0),*(y3)); - cmult(*(x1),*(W45),&tmpre,&tmpim); - cmac(*(x2),*(W35),&tmpre,&tmpim); - cmac(*(x3),*(W25),&tmpre,&tmpim); - cmac(*(x4),*(W15),&tmpre,&tmpim); - *(y4) = cpack(tmpre,tmpim); - *(y4) = vqaddq_s16(*(x0),*(y4)); -} - -#endif -// performs 4x4 transpose of input x (complex interleaved) using 128bit SIMD intrinsics -// i.e. x = [x0r x0i x1r x1i ... x15r x15i], y = [x0r x0i x4r x4i x8r x8i x12r x12i x1r x1i x5r x5i x9r x9i x13r x13i x2r x2i ... x15r x15i] - -#if defined(__x86_64__) || defined(__i386__) -static inline void transpose16(__m128i *x,__m128i *y) __attribute__((always_inline)); -static inline void transpose16(__m128i *x,__m128i *y) -{ - register __m128i ytmp0,ytmp1,ytmp2,ytmp3; - - ytmp0 = _mm_unpacklo_epi32(x[0],x[1]); - ytmp1 = _mm_unpackhi_epi32(x[0],x[1]); - ytmp2 = _mm_unpacklo_epi32(x[2],x[3]); - ytmp3 = _mm_unpackhi_epi32(x[2],x[3]); - y[0] = _mm_unpacklo_epi64(ytmp0,ytmp2); - y[1] = _mm_unpackhi_epi64(ytmp0,ytmp2); - y[2] = _mm_unpacklo_epi64(ytmp1,ytmp3); - y[3] = _mm_unpackhi_epi64(ytmp1,ytmp3); -} - -#elif defined(__arm__) -static inline void transpose16(int16x8_t *x,int16x8_t *y) __attribute__((always_inline)); -static inline void transpose16(int16x8_t *x,int16x8_t *y) -{ - register uint32x4x2_t ytmp0,ytmp1; - - ytmp0 = vtrnq_u32((uint32x4_t)(x[0]),(uint32x4_t)(x[1])); - ytmp1 = vtrnq_u32((uint32x4_t)(x[2]),(uint32x4_t)(x[3])); - - y[0] = vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[0]),vget_low_s16((int16x8_t)ytmp1.val[0])); - y[1] = vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[0]),vget_high_s16((int16x8_t)ytmp1.val[0])); - y[2] = vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[1]),vget_low_s16((int16x8_t)ytmp1.val[1])); - y[3] = vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[1]),vget_high_s16((int16x8_t)ytmp1.val[1])); -} - -# endif -// same as above but output is offset by off -#if defined(__x86_64__) || defined(__i386__) -static inline void transpose16_ooff(__m128i *x,__m128i *y,int off) __attribute__((always_inline)); - -static inline void transpose16_ooff(__m128i *x,__m128i *y,int off) -{ - register __m128i ytmp0,ytmp1,ytmp2,ytmp3; - __m128i *y2=y; - - ytmp0 = _mm_unpacklo_epi32(x[0],x[1]); // x00 x10 x01 x11 - ytmp1 = _mm_unpackhi_epi32(x[0],x[1]); // x02 x12 x03 x13 - ytmp2 = _mm_unpacklo_epi32(x[2],x[3]); // x20 x30 x21 x31 - ytmp3 = _mm_unpackhi_epi32(x[2],x[3]); // x22 x32 x23 x33 - *y2 = _mm_unpacklo_epi64(ytmp0,ytmp2); // x00 x10 x20 x30 - y2+=off; - *y2 = _mm_unpackhi_epi64(ytmp0,ytmp2); // x01 x11 x21 x31 - y2+=off; - *y2 = _mm_unpacklo_epi64(ytmp1,ytmp3); // x02 x12 x22 x32 - y2+=off; - *y2 = _mm_unpackhi_epi64(ytmp1,ytmp3); // x03 x13 x23 x33 -} - -#ifdef __AVX2__ - -static inline void transpose16_ooff_simd256(__m256i *x,__m256i *y,int off) __attribute__((always_inline)); -static inline void transpose16_ooff_simd256(__m256i *x,__m256i *y,int off) -{ - register __m256i ytmp0,ytmp1,ytmp2,ytmp3,ytmp4,ytmp5,ytmp6,ytmp7; - __m256i *y2=y; - __m256i const perm_mask = _mm256_set_epi32(7, 3, 5, 1, 6, 2, 4, 0); - - ytmp0 = _mm256_permutevar8x32_epi32(x[0],perm_mask); // x00 x10 x01 x11 x02 x12 x03 x13 - ytmp1 = _mm256_permutevar8x32_epi32(x[1],perm_mask); // x20 x30 x21 x31 x22 x32 x23 x33 - ytmp2 = _mm256_permutevar8x32_epi32(x[2],perm_mask); // x40 x50 x41 x51 x42 x52 x43 x53 - ytmp3 = _mm256_permutevar8x32_epi32(x[3],perm_mask); // x60 x70 x61 x71 x62 x72 x63 x73 - ytmp4 = _mm256_unpacklo_epi64(ytmp0,ytmp1); // x00 x10 x20 x30 x01 x11 x21 x31 - ytmp5 = _mm256_unpackhi_epi64(ytmp0,ytmp1); // x02 x12 x22 x32 x03 x13 x23 x33 - ytmp6 = _mm256_unpacklo_epi64(ytmp2,ytmp3); // x40 x50 x60 x70 x41 x51 x61 x71 - ytmp7 = _mm256_unpackhi_epi64(ytmp2,ytmp3); // x42 x52 x62 x72 x43 x53 x63 x73 - - *y2 = _mm256_insertf128_si256(ytmp4,_mm256_extracti128_si256(ytmp6,0),1); //x00 x10 x20 x30 x40 x50 x60 x70 - y2+=off; - *y2 = _mm256_insertf128_si256(ytmp6,_mm256_extracti128_si256(ytmp4,1),0); //x01 x11 x21 x31 x41 x51 x61 x71 - y2+=off; - *y2 = _mm256_insertf128_si256(ytmp5,_mm256_extracti128_si256(ytmp7,0),1); //x00 x10 x20 x30 x40 x50 x60 x70 - y2+=off; - *y2 = _mm256_insertf128_si256(ytmp7,_mm256_extracti128_si256(ytmp5,1),0); //x01 x11 x21 x31 x41 x51 x61 x71 -} -#endif - -#elif defined(__arm__) -static inline void transpose16_ooff(int16x8_t *x,int16x8_t *y,int off) __attribute__((always_inline)); - -static inline void transpose16_ooff(int16x8_t *x,int16x8_t *y,int off) -{ - int16x8_t *y2=y; - register uint32x4x2_t ytmp0,ytmp1; - - ytmp0 = vtrnq_u32((uint32x4_t)(x[0]),(uint32x4_t)(x[1])); - ytmp1 = vtrnq_u32((uint32x4_t)(x[2]),(uint32x4_t)(x[3])); - - *y2 = (int16x8_t)vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[0]),vget_low_s16((int16x8_t)ytmp1.val[0])); y2+=off; - *y2 = (int16x8_t)vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[1]),vget_low_s16((int16x8_t)ytmp1.val[1])); y2+=off; - *y2 = (int16x8_t)vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[0]),vget_high_s16((int16x8_t)ytmp1.val[0])); y2+=off; - *y2 = (int16x8_t)vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[1]),vget_high_s16((int16x8_t)ytmp1.val[1])); - - -} - -#endif - -#if defined(__x86_64__) || defined(__i386__) - -static inline void transpose4_ooff(__m64 *x,__m64 *y,int off)__attribute__((always_inline)); -static inline void transpose4_ooff(__m64 *x,__m64 *y,int off) -{ - y[0] = _mm_unpacklo_pi32(x[0],x[1]); - y[off] = _mm_unpackhi_pi32(x[0],x[1]); - - // x[0] = [x0 x1] - // x[1] = [x2 x3] - // y[0] = [x0 x2] - // y[off] = [x1 x3] -} -#ifdef __AVX2__ -static inline void transpose4_ooff_simd256(__m256i *x,__m256i *y,int off)__attribute__((always_inline)); -static inline void transpose4_ooff_simd256(__m256i *x,__m256i *y,int off) -{ - __m256i const perm_mask = _mm256_set_epi32(7, 5, 3, 1, 6, 4, 2, 0); - __m256i perm_tmp0,perm_tmp1; - - // x[0] = [x0 x1 x2 x3 x4 x5 x6 x7] - // x[1] = [x8 x9 x10 x11 x12 x13 x14] - // y[0] = [x0 x2 x4 x6 x8 x10 x12 x14] - // y[off] = [x1 x3 x5 x7 x9 x11 x13 x15] - perm_tmp0 = _mm256_permutevar8x32_epi32(x[0],perm_mask); - perm_tmp1 = _mm256_permutevar8x32_epi32(x[1],perm_mask); - y[0] = _mm256_insertf128_si256(perm_tmp0,_mm256_extracti128_si256(perm_tmp1,0),1); - y[off] = _mm256_insertf128_si256(perm_tmp1,_mm256_extracti128_si256(perm_tmp0,1),0); -} -#endif -#elif (__arm__) - -static inline void transpose4_ooff(int16x4_t *x,int16x4_t *y,int off)__attribute__((always_inline)); -static inline void transpose4_ooff(int16x4_t *x,int16x4_t *y,int off) -{ - uint32x2x2_t ytmp = vtrn_u32((uint32x2_t)x[0],(uint32x2_t)x[1]); - - y[0] = (int16x4_t)ytmp.val[0]; - y[off] = (int16x4_t)ytmp.val[1]; -} - -#endif - -// 16-point optimized DFT kernel - -const static int16_t tw16[24] __attribute__((aligned(32))) = { 32767,0,30272,-12540,23169 ,-23170,12539 ,-30273, - 32767,0,23169,-23170,0 ,-32767,-23170,-23170, - 32767,0,12539,-30273,-23170,-23170,-30273,12539 - }; - -const static int16_t tw16a[24] __attribute__((aligned(32))) = {32767,0,30272,12540,23169 ,23170,12539 ,30273, - 32767,0,23169,23170,0 ,32767,-23170,23170, - 32767,0,12539,30273,-23170,23170,-30273,-12539 - }; - -const static int16_t tw16b[24] __attribute__((aligned(32))) = { 0,32767,-12540,30272,-23170,23169 ,-30273,12539, - 0,32767,-23170,23169,-32767,0 ,-23170,-23170, - 0,32767,-30273,12539,-23170,-23170,12539 ,-30273 - }; - -const static int16_t tw16c[24] __attribute__((aligned(32))) = { 0,32767,12540,30272,23170,23169 ,30273 ,12539, - 0,32767,23170,23169,32767,0 ,23170 ,-23170, - 0,32767,30273,12539,23170,-23170,-12539,-30273 - }; - -#ifdef __AVX2__ - -const static int16_t tw16rep[48] __attribute__((aligned(32))) = { 32767,0,30272,-12540,23169 ,-23170,12539 ,-30273,32767,0,30272,-12540,23169 ,-23170,12539 ,-30273, - 32767,0,23169,-23170,0 ,-32767,-23170,-23170,32767,0,23169,-23170,0 ,-32767,-23170,-23170, - 32767,0,12539,-30273,-23170,-23170,-30273,12539,32767,0,12539,-30273,-23170,-23170,-30273,12539 - }; - -const static int16_t tw16arep[48] __attribute__((aligned(32))) = {32767,0,30272,12540,23169 ,23170,12539 ,30273,32767,0,30272,12540,23169 ,23170,12539 ,30273, - 32767,0,23169,23170,0 ,32767,-23170,23170,32767,0,23169,23170,0 ,32767,-23170,23170, - 32767,0,12539,30273,-23170,23170,-30273,-12539,32767,0,12539,30273,-23170,23170,-30273,-12539 - }; - -const static int16_t tw16brep[48] __attribute__((aligned(32))) = { 0,32767,-12540,30272,-23170,23169 ,-30273,12539,0,32767,-12540,30272,-23170,23169 ,-30273,12539, - 0,32767,-23170,23169,-32767,0 ,-23170,-23170,0,32767,-23170,23169,-32767,0 ,-23170,-23170, - 0,32767,-30273,12539,-23170,-23170,12539 ,-30273,0,32767,-30273,12539,-23170,-23170,12539 ,-30273 - }; - -const static int16_t tw16crep[48] __attribute__((aligned(32))) = { 0,32767,12540,30272,23170,23169 ,30273 ,12539,0,32767,12540,30272,23170,23169 ,30273 ,12539, - 0,32767,23170,23169,32767,0 ,23170 ,-23170,0,32767,23170,23169,32767,0 ,23170 ,-23170, - 0,32767,30273,12539,23170,-23170,-12539,-30273,0,32767,30273,12539,23170,-23170,-12539,-30273 - }; - -#endif /* __AVX2__ */ - - - -static inline void dft16(int16_t *x,int16_t *y) __attribute__((always_inline)); - -static inline void dft16(int16_t *x,int16_t *y) -{ - -#if defined(__x86_64__) || defined(__i386__) - - __m128i *tw16a_128=(__m128i *)tw16a,*tw16b_128=(__m128i *)tw16b,*x128=(__m128i *)x,*y128=(__m128i *)y; - - - - /* This is the original version before unrolling - - bfly4_tw1(x128,x128+1,x128+2,x128+3, - y128,y128+1,y128+2,y128+3); - - transpose16(y128,ytmp); - - bfly4_16(ytmp,ytmp+1,ytmp+2,ytmp+3, - y128,y128+1,y128+2,y128+3, - tw16_128,tw16_128+1,tw16_128+2); - */ - - register __m128i x1_flip,x3_flip,x02t,x13t; - register __m128i ytmp0,ytmp1,ytmp2,ytmp3,xtmp0,xtmp1,xtmp2,xtmp3; - register __m128i complex_shuffle = _mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - // First stage : 4 Radix-4 butterflies without input twiddles - - x02t = _mm_adds_epi16(x128[0],x128[2]); - x13t = _mm_adds_epi16(x128[1],x128[3]); - xtmp0 = _mm_adds_epi16(x02t,x13t); - xtmp2 = _mm_subs_epi16(x02t,x13t); - x1_flip = _mm_sign_epi16(x128[1],*(__m128i*)conjugatedft); - x1_flip = _mm_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm_sign_epi16(x128[3],*(__m128i*)conjugatedft); - x3_flip = _mm_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm_subs_epi16(x128[0],x128[2]); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - xtmp1 = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - xtmp3 = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - ytmp0 = _mm_unpacklo_epi32(xtmp0,xtmp1); - ytmp1 = _mm_unpackhi_epi32(xtmp0,xtmp1); - ytmp2 = _mm_unpacklo_epi32(xtmp2,xtmp3); - ytmp3 = _mm_unpackhi_epi32(xtmp2,xtmp3); - xtmp0 = _mm_unpacklo_epi64(ytmp0,ytmp2); - xtmp1 = _mm_unpackhi_epi64(ytmp0,ytmp2); - xtmp2 = _mm_unpacklo_epi64(ytmp1,ytmp3); - xtmp3 = _mm_unpackhi_epi64(ytmp1,ytmp3); - - // Second stage : 4 Radix-4 butterflies with input twiddles - xtmp1 = packed_cmult2(xtmp1,tw16a_128[0],tw16b_128[0]); - xtmp2 = packed_cmult2(xtmp2,tw16a_128[1],tw16b_128[1]); - xtmp3 = packed_cmult2(xtmp3,tw16a_128[2],tw16b_128[2]); - - x02t = _mm_adds_epi16(xtmp0,xtmp2); - x13t = _mm_adds_epi16(xtmp1,xtmp3); - y128[0] = _mm_adds_epi16(x02t,x13t); - y128[2] = _mm_subs_epi16(x02t,x13t); - x1_flip = _mm_sign_epi16(xtmp1,*(__m128i*)conjugatedft); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(xtmp3,*(__m128i*)conjugatedft); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x02t = _mm_subs_epi16(xtmp0,xtmp2); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - y128[1] = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - y128[3] = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - -#elif defined(__arm__) - - int16x8_t *tw16a_128=(int16x8_t *)tw16a,*tw16b_128=(int16x8_t *)tw16b,*x128=(int16x8_t *)x,*y128=(int16x8_t *)y; - - /* This is the original version before unrolling - - bfly4_tw1(x128,x128+1,x128+2,x128+3, - y128,y128+1,y128+2,y128+3); - - transpose16(y128,ytmp); - - bfly4_16(ytmp,ytmp+1,ytmp+2,ytmp+3, - y128,y128+1,y128+2,y128+3, - tw16_128,tw16_128+1,tw16_128+2); - */ - - register int16x8_t x1_flip,x3_flip,x02t,x13t; - register int16x8_t xtmp0,xtmp1,xtmp2,xtmp3; - register uint32x4x2_t ytmp0,ytmp1; - register int16x8_t ytmp0b,ytmp1b,ytmp2b,ytmp3b; - - // First stage : 4 Radix-4 butterflies without input twiddles - - x02t = vqaddq_s16(x128[0],x128[2]); - x13t = vqaddq_s16(x128[1],x128[3]); - xtmp0 = vqaddq_s16(x02t,x13t); - xtmp2 = vqsubq_s16(x02t,x13t); - x1_flip = vrev32q_s16(vmulq_s16(x128[1],*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(x128[3],*(int16x8_t*)conjugatedft)); - x02t = vqsubq_s16(x128[0],x128[2]); - x13t = vqsubq_s16(x1_flip,x3_flip); - xtmp1 = vqaddq_s16(x02t,x13t); // x0 + x1f - x2 - x3f - xtmp3 = vqsubq_s16(x02t,x13t); // x0 - x1f - x2 + x3f - - ytmp0 = vtrnq_u32((uint32x4_t)(xtmp0),(uint32x4_t)(xtmp1)); -// y0[0] = [x00 x10 x02 x12], y0[1] = [x01 x11 x03 x13] - ytmp1 = vtrnq_u32((uint32x4_t)(xtmp2),(uint32x4_t)(xtmp3)); -// y1[0] = [x20 x30 x22 x32], y1[1] = [x21 x31 x23 x33] - - - ytmp0b = vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[0]),vget_low_s16((int16x8_t)ytmp1.val[0])); -// y0 = [x00 x10 x20 x30] - ytmp1b = vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[1]),vget_low_s16((int16x8_t)ytmp1.val[1])); -// t1 = [x01 x11 x21 x31] - ytmp2b = vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[0]),vget_high_s16((int16x8_t)ytmp1.val[0])); -// t2 = [x02 x12 x22 x32] - ytmp3b = vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[1]),vget_high_s16((int16x8_t)ytmp1.val[1])); -// t3 = [x03 x13 x23 x33] - - - // Second stage : 4 Radix-4 butterflies with input twiddles - xtmp1 = packed_cmult2(ytmp1b,tw16a_128[0],tw16b_128[0]); - xtmp2 = packed_cmult2(ytmp2b,tw16a_128[1],tw16b_128[1]); - xtmp3 = packed_cmult2(ytmp3b,tw16a_128[2],tw16b_128[2]); - - x02t = vqaddq_s16(ytmp0b,xtmp2); - x13t = vqaddq_s16(xtmp1,xtmp3); - y128[0] = vqaddq_s16(x02t,x13t); - y128[2] = vqsubq_s16(x02t,x13t); - x1_flip = vrev32q_s16(vmulq_s16(xtmp1,*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(xtmp3,*(int16x8_t*)conjugatedft)); - x02t = vqsubq_s16(ytmp0b,xtmp2); - x13t = vqsubq_s16(x1_flip,x3_flip); - y128[1] = vqaddq_s16(x02t,x13t); // x0 + x1f - x2 - x3f - y128[3] = vqsubq_s16(x02t,x13t); // x0 - x1f - x2 + x3f - - -#endif -} - -#if defined(__x86_64__) || defined(__i386__) -#ifdef __AVX2__ -// Does two 16-point DFTS (x[0 .. 15] is 128 LSBs of input vector, x[16..31] is in 128 MSBs) -static inline void dft16_simd256(int16_t *x,int16_t *y) __attribute__((always_inline)); -static inline void dft16_simd256(int16_t *x,int16_t *y) -{ - - __m256i *tw16a_256=(__m256i *)tw16arep,*tw16b_256=(__m256i *)tw16brep,*x256=(__m256i *)x,*y256=(__m256i *)y; - - __m256i x1_flip,x3_flip,x02t,x13t; - __m256i ytmp0,ytmp1,ytmp2,ytmp3,xtmp0,xtmp1,xtmp2,xtmp3; - register __m256i complex_shuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - // First stage : 4 Radix-4 butterflies without input twiddles - - x02t = _mm256_adds_epi16(x256[0],x256[2]); - x13t = _mm256_adds_epi16(x256[1],x256[3]); - xtmp0 = _mm256_adds_epi16(x02t,x13t); - xtmp2 = _mm256_subs_epi16(x02t,x13t); - x1_flip = _mm256_sign_epi16(x256[1],*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(x256[3],*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(x256[0],x256[2]); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - xtmp1 = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - xtmp3 = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - /* print_shorts256("xtmp0",(int16_t*)&xtmp0); - print_shorts256("xtmp1",(int16_t*)&xtmp1); - print_shorts256("xtmp2",(int16_t*)&xtmp2); - print_shorts256("xtmp3",(int16_t*)&xtmp3);*/ - - ytmp0 = _mm256_unpacklo_epi32(xtmp0,xtmp1); - ytmp1 = _mm256_unpackhi_epi32(xtmp0,xtmp1); - ytmp2 = _mm256_unpacklo_epi32(xtmp2,xtmp3); - ytmp3 = _mm256_unpackhi_epi32(xtmp2,xtmp3); - xtmp0 = _mm256_unpacklo_epi64(ytmp0,ytmp2); - xtmp1 = _mm256_unpackhi_epi64(ytmp0,ytmp2); - xtmp2 = _mm256_unpacklo_epi64(ytmp1,ytmp3); - xtmp3 = _mm256_unpackhi_epi64(ytmp1,ytmp3); - - // Second stage : 4 Radix-4 butterflies with input twiddles - xtmp1 = packed_cmult2_256(xtmp1,tw16a_256[0],tw16b_256[0]); - xtmp2 = packed_cmult2_256(xtmp2,tw16a_256[1],tw16b_256[1]); - xtmp3 = packed_cmult2_256(xtmp3,tw16a_256[2],tw16b_256[2]); - - /* print_shorts256("xtmp0",(int16_t*)&xtmp0); - print_shorts256("xtmp1",(int16_t*)&xtmp1); - print_shorts256("xtmp2",(int16_t*)&xtmp2); - print_shorts256("xtmp3",(int16_t*)&xtmp3);*/ - - x02t = _mm256_adds_epi16(xtmp0,xtmp2); - x13t = _mm256_adds_epi16(xtmp1,xtmp3); - ytmp0 = _mm256_adds_epi16(x02t,x13t); - ytmp2 = _mm256_subs_epi16(x02t,x13t); - x1_flip = _mm256_sign_epi16(xtmp1,*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(xtmp3,*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(xtmp0,xtmp2); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - ytmp1 = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - ytmp3 = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - - // [y0 y1 y2 y3 y16 y17 y18 y19] - // [y4 y5 y6 y7 y20 y21 y22 y23] - // [y8 y9 y10 y11 y24 y25 y26 y27] - // [y12 y13 y14 y15 y28 y29 y30 y31] - - y256[0] = _mm256_insertf128_si256(ytmp0,_mm256_extracti128_si256(ytmp1,0),1); - y256[1] = _mm256_insertf128_si256(ytmp2,_mm256_extracti128_si256(ytmp3,0),1); - y256[2] = _mm256_insertf128_si256(ytmp1,_mm256_extracti128_si256(ytmp0,1),0); - y256[3] = _mm256_insertf128_si256(ytmp3,_mm256_extracti128_si256(ytmp2,1),0); - - // [y0 y1 y2 y3 y4 y5 y6 y7] - // [y8 y9 y10 y11 y12 y13 y14 y15] - // [y16 y17 y18 y19 y20 y21 y22 y23] - // [y24 y25 y26 y27 y28 y29 y30 y31] -} - -#endif -#endif -static inline void idft16(int16_t *x,int16_t *y) __attribute__((always_inline)); - -static inline void idft16(int16_t *x,int16_t *y) -{ - -#if defined(__x86_64__) || defined(__i386__) - __m128i *tw16a_128=(__m128i *)tw16,*tw16b_128=(__m128i *)tw16c,*x128=(__m128i *)x,*y128=(__m128i *)y; - - /* - bfly4_tw1(x128,x128+1,x128+2,x128+3, - y128,y128+1,y128+2,y128+3); - - transpose16(y128,ytmp); - - bfly4_16(ytmp,ytmp+1,ytmp+2,ytmp+3, - y128,y128+1,y128+2,y128+3, - tw16_128,tw16_128+1,tw16_128+2); - */ - - register __m128i x1_flip,x3_flip,x02t,x13t; - register __m128i ytmp0,ytmp1,ytmp2,ytmp3,xtmp0,xtmp1,xtmp2,xtmp3; - - // First stage : 4 Radix-4 butterflies without input twiddles - - x02t = _mm_adds_epi16(x128[0],x128[2]); - x13t = _mm_adds_epi16(x128[1],x128[3]); - xtmp0 = _mm_adds_epi16(x02t,x13t); - xtmp2 = _mm_subs_epi16(x02t,x13t); - x1_flip = _mm_sign_epi16(x128[1],*(__m128i*)conjugatedft); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(x128[3],*(__m128i*)conjugatedft); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x02t = _mm_subs_epi16(x128[0],x128[2]); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - xtmp3 = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - xtmp1 = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - ytmp0 = _mm_unpacklo_epi32(xtmp0,xtmp1); - ytmp1 = _mm_unpackhi_epi32(xtmp0,xtmp1); - ytmp2 = _mm_unpacklo_epi32(xtmp2,xtmp3); - ytmp3 = _mm_unpackhi_epi32(xtmp2,xtmp3); - xtmp0 = _mm_unpacklo_epi64(ytmp0,ytmp2); - xtmp1 = _mm_unpackhi_epi64(ytmp0,ytmp2); - xtmp2 = _mm_unpacklo_epi64(ytmp1,ytmp3); - xtmp3 = _mm_unpackhi_epi64(ytmp1,ytmp3); - - // Second stage : 4 Radix-4 butterflies with input twiddles - xtmp1 = packed_cmult2(xtmp1,tw16a_128[0],tw16b_128[0]); - xtmp2 = packed_cmult2(xtmp2,tw16a_128[1],tw16b_128[1]); - xtmp3 = packed_cmult2(xtmp3,tw16a_128[2],tw16b_128[2]); - - x02t = _mm_adds_epi16(xtmp0,xtmp2); - x13t = _mm_adds_epi16(xtmp1,xtmp3); - y128[0] = _mm_adds_epi16(x02t,x13t); - y128[2] = _mm_subs_epi16(x02t,x13t); - x1_flip = _mm_sign_epi16(xtmp1,*(__m128i*)conjugatedft); - x1_flip = _mm_shuffle_epi8(x1_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x3_flip = _mm_sign_epi16(xtmp3,*(__m128i*)conjugatedft); - x3_flip = _mm_shuffle_epi8(x3_flip,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2)); - x02t = _mm_subs_epi16(xtmp0,xtmp2); - x13t = _mm_subs_epi16(x1_flip,x3_flip); - y128[3] = _mm_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - y128[1] = _mm_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - -#elif defined(__arm__) - int16x8_t *tw16a_128=(int16x8_t *)tw16,*tw16b_128=(int16x8_t *)tw16c,*x128=(int16x8_t *)x,*y128=(int16x8_t *)y; - - /* This is the original version before unrolling - - bfly4_tw1(x128,x128+1,x128+2,x128+3, - y128,y128+1,y128+2,y128+3); - - transpose16(y128,ytmp); - - bfly4_16(ytmp,ytmp+1,ytmp+2,ytmp+3, - y128,y128+1,y128+2,y128+3, - tw16_128,tw16_128+1,tw16_128+2); - */ - - register int16x8_t x1_flip,x3_flip,x02t,x13t; - register int16x8_t xtmp0,xtmp1,xtmp2,xtmp3; - register uint32x4x2_t ytmp0,ytmp1; - register int16x8_t ytmp0b,ytmp1b,ytmp2b,ytmp3b; - - // First stage : 4 Radix-4 butterflies without input twiddles - - x02t = vqaddq_s16(x128[0],x128[2]); - x13t = vqaddq_s16(x128[1],x128[3]); - xtmp0 = vqaddq_s16(x02t,x13t); - xtmp2 = vqsubq_s16(x02t,x13t); - x1_flip = vrev32q_s16(vmulq_s16(x128[1],*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(x128[3],*(int16x8_t*)conjugatedft)); - x02t = vqsubq_s16(x128[0],x128[2]); - x13t = vqsubq_s16(x1_flip,x3_flip); - xtmp3 = vqaddq_s16(x02t,x13t); // x0 + x1f - x2 - x3f - xtmp1 = vqsubq_s16(x02t,x13t); // x0 - x1f - x2 + x3f - - ytmp0 = vtrnq_u32((uint32x4_t)(xtmp0),(uint32x4_t)(xtmp1)); -// y0[0] = [x00 x10 x02 x12], y0[1] = [x01 x11 x03 x13] - ytmp1 = vtrnq_u32((uint32x4_t)(xtmp2),(uint32x4_t)(xtmp3)); -// y1[0] = [x20 x30 x22 x32], y1[1] = [x21 x31 x23 x33] - - - ytmp0b = vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[0]),vget_low_s16((int16x8_t)ytmp1.val[0])); -// y0 = [x00 x10 x20 x30] - ytmp1b = vcombine_s16(vget_low_s16((int16x8_t)ytmp0.val[1]),vget_low_s16((int16x8_t)ytmp1.val[1])); -// t1 = [x01 x11 x21 x31] - ytmp2b = vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[0]),vget_high_s16((int16x8_t)ytmp1.val[0])); -// t2 = [x02 x12 x22 x32] - ytmp3b = vcombine_s16(vget_high_s16((int16x8_t)ytmp0.val[1]),vget_high_s16((int16x8_t)ytmp1.val[1])); -// t3 = [x03 x13 x23 x33] - - // Second stage : 4 Radix-4 butterflies with input twiddles - xtmp1 = packed_cmult2(ytmp1b,tw16a_128[0],tw16b_128[0]); - xtmp2 = packed_cmult2(ytmp2b,tw16a_128[1],tw16b_128[1]); - xtmp3 = packed_cmult2(ytmp3b,tw16a_128[2],tw16b_128[2]); - - x02t = vqaddq_s16(ytmp0b,xtmp2); - x13t = vqaddq_s16(xtmp1,xtmp3); - y128[0] = vqaddq_s16(x02t,x13t); - y128[2] = vqsubq_s16(x02t,x13t); - x1_flip = vrev32q_s16(vmulq_s16(xtmp1,*(int16x8_t*)conjugatedft)); - x3_flip = vrev32q_s16(vmulq_s16(xtmp3,*(int16x8_t*)conjugatedft)); - x02t = vqsubq_s16(ytmp0b,xtmp2); - x13t = vqsubq_s16(x1_flip,x3_flip); - y128[3] = vqaddq_s16(x02t,x13t); // x0 + x1f - x2 - x3f - y128[1] = vqsubq_s16(x02t,x13t); // x0 - x1f - x2 + x3f - -#endif -} - -#if defined(__x86_64__) || defined(__i386__) -#ifdef __AVX2__ -// Does two 16-point IDFTS (x[0 .. 15] is 128 LSBs of input vector, x[16..31] is in 128 MSBs) -static inline void idft16_simd256(int16_t *x,int16_t *y) __attribute__((always_inline)); -static inline void idft16_simd256(int16_t *x,int16_t *y) -{ - - __m256i *tw16a_256=(__m256i *)tw16rep,*tw16b_256=(__m256i *)tw16crep,*x256=(__m256i *)x,*y256=(__m256i *)y; - register __m256i x1_flip,x3_flip,x02t,x13t; - register __m256i ytmp0,ytmp1,ytmp2,ytmp3,xtmp0,xtmp1,xtmp2,xtmp3; - register __m256i complex_shuffle = _mm256_set_epi8(29,28,31,30,25,24,27,26,21,20,23,22,17,16,19,18,13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2); - - // First stage : 4 Radix-4 butterflies without input twiddles - - x02t = _mm256_adds_epi16(x256[0],x256[2]); - x13t = _mm256_adds_epi16(x256[1],x256[3]); - xtmp0 = _mm256_adds_epi16(x02t,x13t); - xtmp2 = _mm256_subs_epi16(x02t,x13t); - x1_flip = _mm256_sign_epi16(x256[1],*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(x256[3],*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(x256[0],x256[2]); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - xtmp3 = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - xtmp1 = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - ytmp0 = _mm256_unpacklo_epi32(xtmp0,xtmp1); - ytmp1 = _mm256_unpackhi_epi32(xtmp0,xtmp1); - ytmp2 = _mm256_unpacklo_epi32(xtmp2,xtmp3); - ytmp3 = _mm256_unpackhi_epi32(xtmp2,xtmp3); - xtmp0 = _mm256_unpacklo_epi64(ytmp0,ytmp2); - xtmp1 = _mm256_unpackhi_epi64(ytmp0,ytmp2); - xtmp2 = _mm256_unpacklo_epi64(ytmp1,ytmp3); - xtmp3 = _mm256_unpackhi_epi64(ytmp1,ytmp3); - - // Second stage : 4 Radix-4 butterflies with input twiddles - xtmp1 = packed_cmult2_256(xtmp1,tw16a_256[0],tw16b_256[0]); - xtmp2 = packed_cmult2_256(xtmp2,tw16a_256[1],tw16b_256[1]); - xtmp3 = packed_cmult2_256(xtmp3,tw16a_256[2],tw16b_256[2]); - - x02t = _mm256_adds_epi16(xtmp0,xtmp2); - x13t = _mm256_adds_epi16(xtmp1,xtmp3); - ytmp0 = _mm256_adds_epi16(x02t,x13t); - ytmp2 = _mm256_subs_epi16(x02t,x13t); - x1_flip = _mm256_sign_epi16(xtmp1,*(__m256i*)conjugatedft); - x1_flip = _mm256_shuffle_epi8(x1_flip,complex_shuffle); - x3_flip = _mm256_sign_epi16(xtmp3,*(__m256i*)conjugatedft); - x3_flip = _mm256_shuffle_epi8(x3_flip,complex_shuffle); - x02t = _mm256_subs_epi16(xtmp0,xtmp2); - x13t = _mm256_subs_epi16(x1_flip,x3_flip); - ytmp3 = _mm256_adds_epi16(x02t,x13t); // x0 + x1f - x2 - x3f - ytmp1 = _mm256_subs_epi16(x02t,x13t); // x0 - x1f - x2 + x3f - - // [y0 y1 y2 y3 y16 y17 y18 y19] - // [y4 y5 y6 y7 y20 y21 y22 y23] - // [y8 y9 y10 y11 y24 y25 y26 y27] - // [y12 y13 y14 y15 y28 y29 y30 y31] - - y256[0] = _mm256_insertf128_si256(ytmp0,_mm256_extracti128_si256(ytmp1,0),1); - y256[1] = _mm256_insertf128_si256(ytmp2,_mm256_extracti128_si256(ytmp3,0),1); - y256[2] = _mm256_insertf128_si256(ytmp1,_mm256_extracti128_si256(ytmp0,1),0); - y256[3] = _mm256_insertf128_si256(ytmp3,_mm256_extracti128_si256(ytmp2,1),0); - -} -#endif -#endif - -// 64-point optimized DFT - -const static int16_t tw64[96] __attribute__((aligned(32))) = { -32767,0,32609,-3212,32137,-6393,31356,-9512, -30272,-12540,28897,-15447,27244,-18205,25329,-20788, -23169,-23170,20787,-25330,18204,-27245,15446,-28898, -12539,-30273,9511,-31357,6392,-32138,3211,-32610, -32767,0,32137,-6393,30272,-12540,27244,-18205, -23169,-23170,18204,-27245,12539,-30273,6392,-32138, -0,-32767,-6393,-32138,-12540,-30273,-18205,-27245, --23170,-23170,-27245,-18205,-30273,-12540,-32138,-6393, -32767,0,31356,-9512,27244,-18205,20787,-25330, -12539,-30273,3211,-32610,-6393,-32138,-15447,-28898, --23170,-23170,-28898,-15447,-32138,-6393,-32610,3211, --30273,12539,-25330,20787,-18205,27244,-9512,31356 - }; -const static int16_t tw64a[96] __attribute__((aligned(32))) = { -32767,0,32609,3212,32137,6393,31356,9512, -30272,12540,28897,15447,27244,18205,25329,20788, -23169,23170,20787,25330,18204,27245,15446,28898, -12539,30273,9511,31357,6392,32138,3211,32610, -32767,0,32137,6393,30272,12540,27244,18205, -23169,23170,18204,27245,12539,30273,6392,32138, -0,32767,-6393,32138,-12540,30273,-18205,27245, --23170,23170,-27245,18205,-30273,12540,-32138,6393, -32767,0,31356,9512,27244,18205,20787,25330, -12539,30273,3211,32610,-6393,32138,-15447,28898, --23170,23170,-28898,15447,-32138,6393,-32610,-3211, --30273,-12539,-25330,-20787,-18205,-27244,-9512,-31356 - }; -const static int16_t tw64b[96] __attribute__((aligned(32))) = { -0,32767,-3212,32609,-6393,32137,-9512,31356, --12540,30272,-15447,28897,-18205,27244,-20788,25329, --23170,23169,-25330,20787,-27245,18204,-28898,15446, --30273,12539,-31357,9511,-32138,6392,-32610,3211, -0,32767,-6393,32137,-12540,30272,-18205,27244, --23170,23169,-27245,18204,-30273,12539,-32138,6392, --32767,0,-32138,-6393,-30273,-12540,-27245,-18205, --23170,-23170,-18205,-27245,-12540,-30273,-6393,-32138, -0,32767,-9512,31356,-18205,27244,-25330,20787, --30273,12539,-32610,3211,-32138,-6393,-28898,-15447, --23170,-23170,-15447,-28898,-6393,-32138,3211,-32610, -12539,-30273,20787,-25330,27244,-18205,31356,-9512 - }; -const static int16_t tw64c[96] __attribute__((aligned(32))) = { -0,32767,3212,32609,6393,32137,9512,31356, -12540,30272,15447,28897,18205,27244,20788,25329, -23170,23169,25330,20787,27245,18204,28898,15446, -30273,12539,31357,9511,32138,6392,32610,3211, -0,32767,6393,32137,12540,30272,18205,27244, -23170,23169,27245,18204,30273,12539,32138,6392, -32767,0,32138,-6393,30273,-12540,27245,-18205, -23170,-23170,18205,-27245,12540,-30273,6393,-32138, -0,32767,9512,31356,18205,27244,25330,20787, -30273,12539,32610,3211,32138,-6393,28898,-15447, -23170,-23170,15447,-28898,6393,-32138,-3211,-32610, --12539,-30273,-20787,-25330,-27244,-18205,-31356,-9512 - }; -#if defined(__x86_64__) || defined(__i386__) -#define simd_q15_t __m128i -#define simdshort_q15_t __m64 -#define shiftright_int16(a,shift) _mm_srai_epi16(a,shift) -#define set1_int16(a) _mm_set1_epi16(a); -#define mulhi_int16(a,b) _mm_mulhrs_epi16 (a,b) -#ifdef __AVX2__ -#define simd256_q15_t __m256i -#define shiftright_int16_simd256(a,shift) _mm256_srai_epi16(a,shift) -#define set1_int16_simd256(a) _mm256_set1_epi16(a); -#define mulhi_int16_simd256(a,b) _mm256_mulhrs_epi16(a,b); //_mm256_slli_epi16(_mm256_mulhi_epi16(a,b),1); -#endif - -#elif defined(__arm__) -#define simd_q15_t int16x8_t -#define simdshort_q15_t int16x4_t -#define shiftright_int16(a,shift) vshrq_n_s16(a,shift) -#define set1_int16(a) vdupq_n_s16(a) -#define mulhi_int16(a,b) vqdmulhq_s16(a,b); -#define _mm_empty() -#define _m_empty() - -#endif - -#ifndef __AVX2__ -void dft64(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[16],ytmp[16],*tw64a_128=(simd_q15_t *)tw64a,*tw64b_128=(simd_q15_t *)tw64b,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y; - - -#ifdef D64STATS - time_stats_t ts_t,ts_d,ts_b; - - reset_meas(&ts_t); - reset_meas(&ts_d); - reset_meas(&ts_b); - start_meas(&ts_t); -#endif - - - transpose16_ooff(x128,xtmp,4); - // xtmp0 = x00 x10 x20 x30 - // xtmp4 = x01 x11 x21 x31 - // xtmp8 = x02 x12 x22 x32 - // xtmp12 = x03 x13 x23 x33 - transpose16_ooff(x128+4,xtmp+1,4); - // xtmp1 = x40 x50 x60 x70 - // xtmp5 = x41 x51 x61 x71 - // xtmp9 = x42 x52 x62 x72 - // xtmp13 = x43 x53 x63 x73 - transpose16_ooff(x128+8,xtmp+2,4); - // xtmp2 = x80 x90 xa0 xb0 - // xtmp6 = x41 x51 x61 x71 - // xtmp10 = x82 x92 xa2 xb2 - // xtmp14 = x83 x93 xa3 xb3 - transpose16_ooff(x128+12,xtmp+3,4); - // xtmp3 = xc0 xd0 xe0 xf0 - // xtmp7 = xc1 xd1 xe1 xf1 - // xtmp11 = xc2 xd2 xe2 xf2 - // xtmp15 = xc3 xd3 xe3 xf3 - -#ifdef D64STATS - stop_meas(&ts_t); - start_meas(&ts_d); -#endif - - // xtmp0 = x00 x10 x20 x30 - // xtmp1 = x40 x50 x60 x70 - // xtmp2 = x80 x90 xa0 xb0 - // xtmp3 = xc0 xd0 xe0 xf0 - dft16((int16_t*)(xtmp),(int16_t*)ytmp); - - // xtmp4 = x01 x11 x21 x31 - // xtmp5 = x41 x51 x61 x71 - // xtmp6 = x81 x91 xa1 xb1 - // xtmp7 = xc1 xd1 xe1 xf1 - dft16((int16_t*)(xtmp+4),(int16_t*)(ytmp+4)); - dft16((int16_t*)(xtmp+8),(int16_t*)(ytmp+8)); - dft16((int16_t*)(xtmp+12),(int16_t*)(ytmp+12)); - - -#ifdef D64STATS - stop_meas(&ts_d); - start_meas(&ts_b); -#endif - - - bfly4_16(ytmp,ytmp+4,ytmp+8,ytmp+12, - y128,y128+4,y128+8,y128+12, - tw64a_128,tw64a_128+4,tw64a_128+8, - tw64b_128,tw64b_128+4,tw64b_128+8); - - bfly4_16(ytmp+1,ytmp+5,ytmp+9,ytmp+13, - y128+1,y128+5,y128+9,y128+13, - tw64a_128+1,tw64a_128+5,tw64a_128+9, - tw64b_128+1,tw64b_128+5,tw64b_128+9); - - bfly4_16(ytmp+2,ytmp+6,ytmp+10,ytmp+14, - y128+2,y128+6,y128+10,y128+14, - tw64a_128+2,tw64a_128+6,tw64a_128+10, - tw64b_128+2,tw64b_128+6,tw64b_128+10); - - bfly4_16(ytmp+3,ytmp+7,ytmp+11,ytmp+15, - y128+3,y128+7,y128+11,y128+15, - tw64a_128+3,tw64a_128+7,tw64a_128+11, - tw64b_128+3,tw64b_128+7,tw64b_128+11); - -#ifdef D64STATS - stop_meas(&ts_b); - printf("t: %llu cycles, d: %llu cycles, b: %llu cycles\n",ts_t.diff,ts_d.diff,ts_b.diff); -#endif - - - if (scale>0) { - y128[0] = shiftright_int16(y128[0],3); - y128[1] = shiftright_int16(y128[1],3); - y128[2] = shiftright_int16(y128[2],3); - y128[3] = shiftright_int16(y128[3],3); - y128[4] = shiftright_int16(y128[4],3); - y128[5] = shiftright_int16(y128[5],3); - y128[6] = shiftright_int16(y128[6],3); - y128[7] = shiftright_int16(y128[7],3); - y128[8] = shiftright_int16(y128[8],3); - y128[9] = shiftright_int16(y128[9],3); - y128[10] = shiftright_int16(y128[10],3); - y128[11] = shiftright_int16(y128[11],3); - y128[12] = shiftright_int16(y128[12],3); - y128[13] = shiftright_int16(y128[13],3); - y128[14] = shiftright_int16(y128[14],3); - y128[15] = shiftright_int16(y128[15],3); - } - - _mm_empty(); - _m_empty(); - -} - -#else // __AVX2__ -void dft64(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[16],ytmp[16],*tw64a_256=(simd256_q15_t *)tw64a,*tw64b_256=(simd256_q15_t *)tw64b,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y; - simd256_q15_t xintl0,xintl1,xintl2,xintl3,xintl4,xintl5,xintl6,xintl7; - simd256_q15_t const perm_mask = _mm256_set_epi32(7, 3, 5, 1, 6, 2, 4, 0); - - -#ifdef D64STATS - time_stats_t ts_t,ts_d,ts_b; - - reset_meas(&ts_t); - reset_meas(&ts_d); - reset_meas(&ts_b); - start_meas(&ts_t); -#endif - -#ifdef D64STATS - stop_meas(&ts_t); - start_meas(&ts_d); -#endif - /* - print_shorts256("x2560",(int16_t*)x256); - print_shorts256("x2561",(int16_t*)(x256+1)); - print_shorts256("x2562",(int16_t*)(x256+2)); - print_shorts256("x2563",(int16_t*)(x256+3)); - print_shorts256("x2564",(int16_t*)(x256+4)); - print_shorts256("x2565",(int16_t*)(x256+5)); - print_shorts256("x2566",(int16_t*)(x256+6)); - print_shorts256("x2567",(int16_t*)(x256+7)); - */ - xintl0 = _mm256_permutevar8x32_epi32(x256[0],perm_mask); // x0 x4 x1 x5 x2 x6 x3 x7 - xintl1 = _mm256_permutevar8x32_epi32(x256[1],perm_mask); // x8 x12 x9 x13 x10 x14 x11 x15 - xintl2 = _mm256_permutevar8x32_epi32(x256[2],perm_mask); // x16 x20 x17 x21 x18 x22 x19 x23 - xintl3 = _mm256_permutevar8x32_epi32(x256[3],perm_mask); // x24 x28 x25 x29 x26 x30 x27 x31 - xintl4 = _mm256_permutevar8x32_epi32(x256[4],perm_mask); // x32 x28 x25 x29 x26 x30 x27 x31 - xintl5 = _mm256_permutevar8x32_epi32(x256[5],perm_mask); // x40 x28 x25 x29 x26 x30 x27 x31 - xintl6 = _mm256_permutevar8x32_epi32(x256[6],perm_mask); // x48 x28 x25 x29 x26 x30 x27 x31 - xintl7 = _mm256_permutevar8x32_epi32(x256[7],perm_mask); // x56 x28 x25 x29 x26 x30 x27 x31 - /* - print_shorts256("xintl0",(int16_t*)&xintl0); - print_shorts256("xintl1",(int16_t*)&xintl1); - print_shorts256("xintl2",(int16_t*)&xintl2); - print_shorts256("xintl3",(int16_t*)&xintl3); - print_shorts256("xintl4",(int16_t*)&xintl4); - print_shorts256("xintl5",(int16_t*)&xintl5); - print_shorts256("xintl6",(int16_t*)&xintl6); - print_shorts256("xintl7",(int16_t*)&xintl7); - */ - xtmp[0] = _mm256_unpacklo_epi64(xintl0,xintl1); // x0 x4 x8 x12 x1 x5 x9 x13 - xtmp[4] = _mm256_unpackhi_epi64(xintl0,xintl1); // x2 x6 x10 x14 x3 x7 x11 x15 - xtmp[1] = _mm256_unpacklo_epi64(xintl2,xintl3); // x16 x20 x24 x28 x17 x21 x25 x29 - xtmp[5] = _mm256_unpackhi_epi64(xintl2,xintl3); // x18 x22 x26 x30 x19 x23 x27 x31 - xtmp[2] = _mm256_unpacklo_epi64(xintl4,xintl5); // x32 x36 x40 x44 x33 x37 x41 x45 - xtmp[6] = _mm256_unpackhi_epi64(xintl4,xintl5); // x34 x38 x42 x46 x35 x39 x43 x47 - xtmp[3] = _mm256_unpacklo_epi64(xintl6,xintl7); // x48 x52 x56 x60 x49 x53 x57 x61 - xtmp[7] = _mm256_unpackhi_epi64(xintl6,xintl7); // x50 x54 x58 x62 x51 x55 x59 x63 - /* - print_shorts256("xtmp0",(int16_t*)xtmp); - print_shorts256("xtmp1",(int16_t*)(xtmp+1)); - print_shorts256("xtmp2",(int16_t*)(xtmp+2)); - print_shorts256("xtmp3",(int16_t*)(xtmp+3)); - print_shorts256("xtmp4",(int16_t*)(xtmp+4)); - print_shorts256("xtmp5",(int16_t*)(xtmp+5)); - print_shorts256("xtmp6",(int16_t*)(xtmp+6)); - print_shorts256("xtmp7",(int16_t*)(xtmp+7)); - */ - dft16_simd256((int16_t*)(xtmp),(int16_t*)ytmp); - // [y0 y1 y2 y3 y4 y5 y6 y7] - // [y8 y9 y10 y11 y12 y13 y14 y15] - // [y16 y17 y18 y19 y20 y21 y22 y23] - // [y24 y25 y26 y27 y28 y29 y30 y31] - /* - print_shorts256("ytmp0",(int16_t*)ytmp); - print_shorts256("ytmp1",(int16_t*)(ytmp+1)); - print_shorts256("ytmp2",(int16_t*)(ytmp+2)); - print_shorts256("ytmp3",(int16_t*)(ytmp+3)); - */ - dft16_simd256((int16_t*)(xtmp+4),(int16_t*)(ytmp+4)); - // [y32 y33 y34 y35 y36 y37 y38 y39] - // [y40 y41 y42 y43 y44 y45 y46 y47] - // [y48 y49 y50 y51 y52 y53 y54 y55] - // [y56 y57 y58 y59 y60 y61 y62 y63] - /* - print_shorts256("ytmp4",(int16_t*)(ytmp+4)); - print_shorts256("ytmp5",(int16_t*)(ytmp+5)); - print_shorts256("ytmp6",(int16_t*)(ytmp+6)); - print_shorts256("ytmp7",(int16_t*)(ytmp+7)); - */ -#ifdef D64STATS - stop_meas(&ts_d); - start_meas(&ts_b); -#endif - - - bfly4_16_256(ytmp,ytmp+2,ytmp+4,ytmp+6, - y256,y256+2,y256+4,y256+6, - tw64a_256,tw64a_256+2,tw64a_256+4, - tw64b_256,tw64b_256+2,tw64b_256+4); - // [y0 y1 y2 y3 y4 y5 y6 y7] - // [y16 y17 y18 y19 y20 y21 y22 y23] - // [y32 y33 y34 y35 y36 y37 y38 y39] - // [y48 y49 y50 y51 y52 y53 y54 y55] - - bfly4_16_256(ytmp+1,ytmp+3,ytmp+5,ytmp+7, - y256+1,y256+3,y256+5,y256+7, - tw64a_256+1,tw64a_256+3,tw64a_256+5, - tw64b_256+1,tw64b_256+3,tw64b_256+5); - // [y8 y9 y10 y11 y12 y13 y14 y15] - // [y24 y25 y26 y27 y28 y29 y30 y31] - // [y40 y41 y42 y43 y44 y45 y46 y47] - // [y56 y57 y58 y59 y60 y61 y62 y63] - /* - print_shorts256("y256_0",(int16_t*)&y256[0]); - print_shorts256("y256_1",(int16_t*)&y256[1]); - print_shorts256("y256_2",(int16_t*)&y256[2]); - print_shorts256("y256_3",(int16_t*)&y256[3]); - print_shorts256("y256_4",(int16_t*)&y256[4]); - print_shorts256("y256_5",(int16_t*)&y256[5]); - print_shorts256("y256_6",(int16_t*)&y256[6]); - print_shorts256("y256_7",(int16_t*)&y256[7]); - */ - -#ifdef D64STATS - stop_meas(&ts_b); - printf("t: %llu cycles, d: %llu cycles, b: %llu cycles\n",ts_t.diff,ts_d.diff,ts_b.diff); -#endif - - - if (scale>0) { - y256[0] = shiftright_int16_simd256(y256[0],3); - y256[1] = shiftright_int16_simd256(y256[1],3); - y256[2] = shiftright_int16_simd256(y256[2],3); - y256[3] = shiftright_int16_simd256(y256[3],3); - y256[4] = shiftright_int16_simd256(y256[4],3); - y256[5] = shiftright_int16_simd256(y256[5],3); - y256[6] = shiftright_int16_simd256(y256[6],3); - y256[7] = shiftright_int16_simd256(y256[7],3); - } - - _mm_empty(); - _m_empty(); - - -} -#endif - -#ifndef __AVX2__ -void idft64(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[16],ytmp[16],*tw64a_128=(simd_q15_t *)tw64,*tw64b_128=(simd_q15_t *)tw64c,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y; - - -#ifdef D64STATS - time_stats_t ts_t,ts_d,ts_b; - - reset_meas(&ts_t); - reset_meas(&ts_d); - reset_meas(&ts_b); - start_meas(&ts_t); -#endif - - - transpose16_ooff(x128,xtmp,4); - transpose16_ooff(x128+4,xtmp+1,4); - transpose16_ooff(x128+8,xtmp+2,4); - transpose16_ooff(x128+12,xtmp+3,4); - - -#ifdef D64STATS - stop_meas(&ts_t); - start_meas(&ts_d); -#endif - - - idft16((int16_t*)(xtmp),(int16_t*)ytmp); - idft16((int16_t*)(xtmp+4),(int16_t*)(ytmp+4)); - idft16((int16_t*)(xtmp+8),(int16_t*)(ytmp+8)); - idft16((int16_t*)(xtmp+12),(int16_t*)(ytmp+12)); - - -#ifdef D64STATS - stop_meas(&ts_d); - start_meas(&ts_b); -#endif - - - ibfly4_16(ytmp,ytmp+4,ytmp+8,ytmp+12, - y128,y128+4,y128+8,y128+12, - tw64a_128,tw64a_128+4,tw64a_128+8, - tw64b_128,tw64b_128+4,tw64b_128+8); - ibfly4_16(ytmp+1,ytmp+5,ytmp+9,ytmp+13, - y128+1,y128+5,y128+9,y128+13, - tw64a_128+1,tw64a_128+5,tw64a_128+9, - tw64b_128+1,tw64b_128+5,tw64b_128+9); - - ibfly4_16(ytmp+2,ytmp+6,ytmp+10,ytmp+14, - y128+2,y128+6,y128+10,y128+14, - tw64a_128+2,tw64a_128+6,tw64a_128+10, - tw64b_128+2,tw64b_128+6,tw64b_128+10); - - ibfly4_16(ytmp+3,ytmp+7,ytmp+11,ytmp+15, - y128+3,y128+7,y128+11,y128+15, - tw64a_128+3,tw64a_128+7,tw64a_128+11, - tw64b_128+3,tw64b_128+7,tw64b_128+11); - -#ifdef D64STATS - stop_meas(&ts_b); - printf("t: %llu cycles, d: %llu cycles, b: %llu cycles\n",ts_t.diff,ts_d.diff,ts_b.diff); -#endif - - - if (scale>0) { - - y128[0] = shiftright_int16(y128[0],3); - y128[1] = shiftright_int16(y128[1],3); - y128[2] = shiftright_int16(y128[2],3); - y128[3] = shiftright_int16(y128[3],3); - y128[4] = shiftright_int16(y128[4],3); - y128[5] = shiftright_int16(y128[5],3); - y128[6] = shiftright_int16(y128[6],3); - y128[7] = shiftright_int16(y128[7],3); - y128[8] = shiftright_int16(y128[8],3); - y128[9] = shiftright_int16(y128[9],3); - y128[10] = shiftright_int16(y128[10],3); - y128[11] = shiftright_int16(y128[11],3); - y128[12] = shiftright_int16(y128[12],3); - y128[13] = shiftright_int16(y128[13],3); - y128[14] = shiftright_int16(y128[14],3); - y128[15] = shiftright_int16(y128[15],3); - - } - - _mm_empty(); - _m_empty(); - -} - -#else // __AVX2__ -void idft64(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[16],ytmp[16],*tw64a_256=(simd256_q15_t *)tw64,*tw64b_256=(simd256_q15_t *)tw64c,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y; - register simd256_q15_t xintl0,xintl1,xintl2,xintl3,xintl4,xintl5,xintl6,xintl7; - simd256_q15_t const perm_mask = _mm256_set_epi32(7, 3, 5, 1, 6, 2, 4, 0); - - -#ifdef D64STATS - time_stats_t ts_t,ts_d,ts_b; - - reset_meas(&ts_t); - reset_meas(&ts_d); - reset_meas(&ts_b); - start_meas(&ts_t); -#endif - -#ifdef D64STATS - stop_meas(&ts_t); - start_meas(&ts_d); -#endif - - xintl0 = _mm256_permutevar8x32_epi32(x256[0],perm_mask); // x0 x4 x1 x5 x2 x6 x3 x7 - xintl1 = _mm256_permutevar8x32_epi32(x256[1],perm_mask); // x8 x12 x9 x13 x10 x14 x11 x15 - xintl2 = _mm256_permutevar8x32_epi32(x256[2],perm_mask); // x16 x20 x17 x21 x18 x22 x19 x23 - xintl3 = _mm256_permutevar8x32_epi32(x256[3],perm_mask); // x24 x28 x25 x29 x26 x30 x27 x31 - xintl4 = _mm256_permutevar8x32_epi32(x256[4],perm_mask); // x24 x28 x25 x29 x26 x30 x27 x31 - xintl5 = _mm256_permutevar8x32_epi32(x256[5],perm_mask); // x24 x28 x25 x29 x26 x30 x27 x31 - xintl6 = _mm256_permutevar8x32_epi32(x256[6],perm_mask); // x24 x28 x25 x29 x26 x30 x27 x31 - xintl7 = _mm256_permutevar8x32_epi32(x256[7],perm_mask); // x24 x28 x25 x29 x26 x30 x27 x31 - - xtmp[0] = _mm256_unpacklo_epi64(xintl0,xintl1); // x0 x4 x8 x12 x1 x5 x9 x13 - xtmp[4] = _mm256_unpackhi_epi64(xintl0,xintl1); // x2 x6 x10 x14 x3 x7 x11 x15 - xtmp[1] = _mm256_unpacklo_epi64(xintl2,xintl3); // x16 x20 x24 x28 x17 x21 x25 x29 - xtmp[5] = _mm256_unpackhi_epi64(xintl2,xintl3); // x18 x22 x26 x30 x19 x23 x27 x31 - xtmp[2] = _mm256_unpacklo_epi64(xintl4,xintl5); // x32 x36 x40 x44 x33 x37 x41 x45 - xtmp[6] = _mm256_unpackhi_epi64(xintl4,xintl5); // x34 x38 x42 x46 x35 x39 x43 x47 - xtmp[3] = _mm256_unpacklo_epi64(xintl6,xintl7); // x48 x52 x56 x60 x49 x53 x57 x61 - xtmp[7] = _mm256_unpackhi_epi64(xintl6,xintl7); // x50 x54 x58 x62 x51 x55 x59 x63 - - - idft16_simd256((int16_t*)(xtmp),(int16_t*)ytmp); - // [y0 y1 y2 y3 y16 y17 y18 y19] - // [y4 y5 y6 y7 y20 y21 y22 y23] - // [y8 y9 y10 y11 y24 y25 y26 y27] - // [y12 y13 y14 y15 y28 y29 y30 y31] - - idft16_simd256((int16_t*)(xtmp+4),(int16_t*)(ytmp+4)); - // [y32 y33 y34 y35 y48 y49 y50 y51] - // [y36 y37 y38 y39 y52 y53 y54 y55] - // [y40 y41 y42 y43 y56 y57 y58 y59] - // [y44 y45 y46 y47 y60 y61 y62 y63] - -#ifdef D64STATS - stop_meas(&ts_d); - start_meas(&ts_b); -#endif - - - ibfly4_16_256(ytmp,ytmp+2,ytmp+4,ytmp+6, - y256,y256+2,y256+4,y256+6, - tw64a_256,tw64a_256+2,tw64a_256+4, - tw64b_256,tw64b_256+2,tw64b_256+4); - // [y0 y1 y2 y3 y4 y5 y6 y7] - // [y16 y17 y18 y19 y20 y21 y22 y23] - // [y32 y33 y34 y35 y36 y37 y38 y39] - // [y48 y49 y50 y51 y52 y53 y54 y55] - - ibfly4_16_256(ytmp+1,ytmp+3,ytmp+5,ytmp+7, - y256+1,y256+3,y256+5,y256+7, - tw64a_256+1,tw64a_256+3,tw64a_256+5, - tw64b_256+1,tw64b_256+3,tw64b_256+5); - // [y8 y9 y10 y11 y12 y13 y14 y15] - // [y24 y25 y26 y27 y28 y29 y30 y31] - // [y40 y41 y42 y43 y44 y45 y46 y47] - // [y56 y57 y58 y59 y60 y61 y62 y63] - - -#ifdef D64STATS - stop_meas(&ts_b); - printf("t: %llu cycles, d: %llu cycles, b: %llu cycles\n",ts_t.diff,ts_d.diff,ts_b.diff); -#endif - - - if (scale>0) { - y256[0] = shiftright_int16_simd256(y256[0],3); - y256[1] = shiftright_int16_simd256(y256[1],3); - y256[2] = shiftright_int16_simd256(y256[2],3); - y256[3] = shiftright_int16_simd256(y256[3],3); - y256[4] = shiftright_int16_simd256(y256[4],3); - y256[5] = shiftright_int16_simd256(y256[5],3); - y256[6] = shiftright_int16_simd256(y256[6],3); - y256[7] = shiftright_int16_simd256(y256[7],3); - } - - _mm_empty(); - _m_empty(); - -} -#endif - -int16_t tw128[128] __attribute__((aligned(32))) = { 32767,0,32727,-1608,32609,-3212,32412,-4808,32137,-6393,31785,-7962,31356,-9512,30851,-11039,30272,-12540,29621,-14010,28897,-15447,28105,-16846,27244,-18205,26318,-19520,25329,-20788,24278,-22005,23169,-23170,22004,-24279,20787,-25330,19519,-26319,18204,-27245,16845,-28106,15446,-28898,14009,-29622,12539,-30273,11038,-30852,9511,-31357,7961,-31786,6392,-32138,4807,-32413,3211,-32610,1607,-32728,0,-32767,-1608,-32728,-3212,-32610,-4808,-32413,-6393,-32138,-7962,-31786,-9512,-31357,-11039,-30852,-12540,-30273,-14010,-29622,-15447,-28898,-16846,-28106,-18205,-27245,-19520,-26319,-20788,-25330,-22005,-24279,-23170,-23170,-24279,-22005,-25330,-20788,-26319,-19520,-27245,-18205,-28106,-16846,-28898,-15447,-29622,-14010,-30273,-12540,-30852,-11039,-31357,-9512,-31786,-7962,-32138,-6393,-32413,-4808,-32610,-3212,-32728,-1608}; - -int16_t tw128a[128] __attribute__((aligned(32))) = { 32767,0,32727,1608,32609,3212,32412,4808,32137,6393,31785,7962,31356,9512,30851,11039,30272,12540,29621,14010,28897,15447,28105,16846,27244,18205,26318,19520,25329,20788,24278,22005,23169,23170,22004,24279,20787,25330,19519,26319,18204,27245,16845,28106,15446,28898,14009,29622,12539,30273,11038,30852,9511,31357,7961,31786,6392,32138,4807,32413,3211,32610,1607,32728,0,32767,-1608,32728,-3212,32610,-4808,32413,-6393,32138,-7962,31786,-9512,31357,-11039,30852,-12540,30273,-14010,29622,-15447,28898,-16846,28106,-18205,27245,-19520,26319,-20788,25330,-22005,24279,-23170,23170,-24279,22005,-25330,20788,-26319,19520,-27245,18205,-28106,16846,-28898,15447,-29622,14010,-30273,12540,-30852,11039,-31357,9512,-31786,7962,-32138,6393,-32413,4808,-32610,3212,-32728,1608}; - -int16_t tw128b[128] __attribute__((aligned(32))) = {0,32767,-1608,32727,-3212,32609,-4808,32412,-6393,32137,-7962,31785,-9512,31356,-11039,30851,-12540,30272,-14010,29621,-15447,28897,-16846,28105,-18205,27244,-19520,26318,-20788,25329,-22005,24278,-23170,23169,-24279,22004,-25330,20787,-26319,19519,-27245,18204,-28106,16845,-28898,15446,-29622,14009,-30273,12539,-30852,11038,-31357,9511,-31786,7961,-32138,6392,-32413,4807,-32610,3211,-32728,1607,-32767,0,-32728,-1608,-32610,-3212,-32413,-4808,-32138,-6393,-31786,-7962,-31357,-9512,-30852,-11039,-30273,-12540,-29622,-14010,-28898,-15447,-28106,-16846,-27245,-18205,-26319,-19520,-25330,-20788,-24279,-22005,-23170,-23170,-22005,-24279,-20788,-25330,-19520,-26319,-18205,-27245,-16846,-28106,-15447,-28898,-14010,-29622,-12540,-30273,-11039,-30852,-9512,-31357,-7962,-31786,-6393,-32138,-4808,-32413,-3212,-32610,-1608,-32728}; - -int16_t tw128c[128] __attribute__((aligned(32))) = {0,32767,1608,32727,3212,32609,4808,32412,6393,32137,7962,31785,9512,31356,11039,30851,12540,30272,14010,29621,15447,28897,16846,28105,18205,27244,19520,26318,20788,25329,22005,24278,23170,23169,24279,22004,25330,20787,26319,19519,27245,18204,28106,16845,28898,15446,29622,14009,30273,12539,30852,11038,31357,9511,31786,7961,32138,6392,32413,4807,32610,3211,32728,1607,32767,0,32728,-1608,32610,-3212,32413,-4808,32138,-6393,31786,-7962,31357,-9512,30852,-11039,30273,-12540,29622,-14010,28898,-15447,28106,-16846,27245,-18205,26319,-19520,25330,-20788,24279,-22005,23170,-23170,22005,-24279,20788,-25330,19520,-26319,18205,-27245,16846,-28106,15447,-28898,14010,-29622,12540,-30273,11039,-30852,9512,-31357,7962,-31786,6393,-32138,4808,-32413,3212,-32610,1608,-32728}; - -#ifndef __AVX2__ -void dft128(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[64],*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[32],*tw128a_128p=(simd_q15_t *)tw128a,*tw128b_128p=(simd_q15_t *)tw128b,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - - transpose4_ooff(x64 ,xtmp,32); - transpose4_ooff(x64+2,xtmp+1,32); - transpose4_ooff(x64+4,xtmp+2,32); - transpose4_ooff(x64+6,xtmp+3,32); - transpose4_ooff(x64+8,xtmp+4,32); - transpose4_ooff(x64+10,xtmp+5,32); - transpose4_ooff(x64+12,xtmp+6,32); - transpose4_ooff(x64+14,xtmp+7,32); - transpose4_ooff(x64+16,xtmp+8,32); - transpose4_ooff(x64+18,xtmp+9,32); - transpose4_ooff(x64+20,xtmp+10,32); - transpose4_ooff(x64+22,xtmp+11,32); - transpose4_ooff(x64+24,xtmp+12,32); - transpose4_ooff(x64+26,xtmp+13,32); - transpose4_ooff(x64+28,xtmp+14,32); - transpose4_ooff(x64+30,xtmp+15,32); - transpose4_ooff(x64+32,xtmp+16,32); - transpose4_ooff(x64+34,xtmp+17,32); - transpose4_ooff(x64+36,xtmp+18,32); - transpose4_ooff(x64+38,xtmp+19,32); - transpose4_ooff(x64+40,xtmp+20,32); - transpose4_ooff(x64+42,xtmp+21,32); - transpose4_ooff(x64+44,xtmp+22,32); - transpose4_ooff(x64+46,xtmp+23,32); - transpose4_ooff(x64+48,xtmp+24,32); - transpose4_ooff(x64+50,xtmp+25,32); - transpose4_ooff(x64+52,xtmp+26,32); - transpose4_ooff(x64+54,xtmp+27,32); - transpose4_ooff(x64+56,xtmp+28,32); - transpose4_ooff(x64+58,xtmp+29,32); - transpose4_ooff(x64+60,xtmp+30,32); - transpose4_ooff(x64+62,xtmp+31,32); - - dft64((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft64((int16_t*)(xtmp+32),(int16_t*)(ytmp+16),1); - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft128a.m","dfta",ytmp,64,1,1); - LOG_M("dft128b.m","dftb",ytmp+16,64,1,1); - } - for (i=0; i<16; i++) { - bfly2_16(ytmpp,ytmpp+16, - y128p,y128p+16, - tw128a_128p, - tw128b_128p); - tw128a_128p++; - tw128b_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - y128[0] = mulhi_int16(y128[0],ONE_OVER_SQRT2_Q15_128); - y128[1] = mulhi_int16(y128[1],ONE_OVER_SQRT2_Q15_128); - y128[2] = mulhi_int16(y128[2],ONE_OVER_SQRT2_Q15_128); - y128[3] = mulhi_int16(y128[3],ONE_OVER_SQRT2_Q15_128); - y128[4] = mulhi_int16(y128[4],ONE_OVER_SQRT2_Q15_128); - y128[5] = mulhi_int16(y128[5],ONE_OVER_SQRT2_Q15_128); - y128[6] = mulhi_int16(y128[6],ONE_OVER_SQRT2_Q15_128); - y128[7] = mulhi_int16(y128[7],ONE_OVER_SQRT2_Q15_128); - y128[8] = mulhi_int16(y128[8],ONE_OVER_SQRT2_Q15_128); - y128[9] = mulhi_int16(y128[9],ONE_OVER_SQRT2_Q15_128); - y128[10] = mulhi_int16(y128[10],ONE_OVER_SQRT2_Q15_128); - y128[11] = mulhi_int16(y128[11],ONE_OVER_SQRT2_Q15_128); - y128[12] = mulhi_int16(y128[12],ONE_OVER_SQRT2_Q15_128); - y128[13] = mulhi_int16(y128[13],ONE_OVER_SQRT2_Q15_128); - y128[14] = mulhi_int16(y128[14],ONE_OVER_SQRT2_Q15_128); - y128[15] = mulhi_int16(y128[15],ONE_OVER_SQRT2_Q15_128); - y128[16] = mulhi_int16(y128[16],ONE_OVER_SQRT2_Q15_128); - y128[17] = mulhi_int16(y128[17],ONE_OVER_SQRT2_Q15_128); - y128[18] = mulhi_int16(y128[18],ONE_OVER_SQRT2_Q15_128); - y128[19] = mulhi_int16(y128[19],ONE_OVER_SQRT2_Q15_128); - y128[20] = mulhi_int16(y128[20],ONE_OVER_SQRT2_Q15_128); - y128[21] = mulhi_int16(y128[21],ONE_OVER_SQRT2_Q15_128); - y128[22] = mulhi_int16(y128[22],ONE_OVER_SQRT2_Q15_128); - y128[23] = mulhi_int16(y128[23],ONE_OVER_SQRT2_Q15_128); - y128[24] = mulhi_int16(y128[24],ONE_OVER_SQRT2_Q15_128); - y128[25] = mulhi_int16(y128[25],ONE_OVER_SQRT2_Q15_128); - y128[26] = mulhi_int16(y128[26],ONE_OVER_SQRT2_Q15_128); - y128[27] = mulhi_int16(y128[27],ONE_OVER_SQRT2_Q15_128); - y128[28] = mulhi_int16(y128[28],ONE_OVER_SQRT2_Q15_128); - y128[29] = mulhi_int16(y128[29],ONE_OVER_SQRT2_Q15_128); - y128[30] = mulhi_int16(y128[30],ONE_OVER_SQRT2_Q15_128); - y128[31] = mulhi_int16(y128[31],ONE_OVER_SQRT2_Q15_128); - - - } - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft128out.m","dft128",y,128,1,1); - exit(-1); - } - _mm_empty(); - _m_empty(); - -} - -#else // __AVX2__ -void dft128(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[16],*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[16],*y256=(simd256_q15_t*)y; - simd256_q15_t *tw128a_256p=(simd256_q15_t *)tw128a,*tw128b_256p=(simd256_q15_t *)tw128b,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_256 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - transpose4_ooff_simd256(x256 ,xtmp,8); - transpose4_ooff_simd256(x256+2,xtmp+1,8); - transpose4_ooff_simd256(x256+4,xtmp+2,8); - transpose4_ooff_simd256(x256+6,xtmp+3,8); - transpose4_ooff_simd256(x256+8,xtmp+4,8); - transpose4_ooff_simd256(x256+10,xtmp+5,8); - transpose4_ooff_simd256(x256+12,xtmp+6,8); - transpose4_ooff_simd256(x256+14,xtmp+7,8); - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft128ina_256.m","dftina",xtmp,64,1,1); - LOG_M("dft128inb_256.m","dftinb",xtmp+8,64,1,1); - } - - dft64((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft64((int16_t*)(xtmp+8),(int16_t*)(ytmp+8),1); - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft128outa_256.m","dftouta",ytmp,64,1,1); - LOG_M("dft128outb_256.m","dftoutb",ytmp+8,64,1,1); - } - - for (i=0; i<8; i++) { - bfly2_16_256(ytmpp,ytmpp+8, - y256p,y256p+8, - tw128a_256p, - tw128b_256p); - tw128a_256p++; - tw128b_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - y256[0] = mulhi_int16_simd256(y256[0],ONE_OVER_SQRT2_Q15_256); - y256[1] = mulhi_int16_simd256(y256[1],ONE_OVER_SQRT2_Q15_256); - y256[2] = mulhi_int16_simd256(y256[2],ONE_OVER_SQRT2_Q15_256); - y256[3] = mulhi_int16_simd256(y256[3],ONE_OVER_SQRT2_Q15_256); - y256[4] = mulhi_int16_simd256(y256[4],ONE_OVER_SQRT2_Q15_256); - y256[5] = mulhi_int16_simd256(y256[5],ONE_OVER_SQRT2_Q15_256); - y256[6] = mulhi_int16_simd256(y256[6],ONE_OVER_SQRT2_Q15_256); - y256[7] = mulhi_int16_simd256(y256[7],ONE_OVER_SQRT2_Q15_256); - y256[8] = mulhi_int16_simd256(y256[8],ONE_OVER_SQRT2_Q15_256); - y256[9] = mulhi_int16_simd256(y256[9],ONE_OVER_SQRT2_Q15_256); - y256[10] = mulhi_int16_simd256(y256[10],ONE_OVER_SQRT2_Q15_256); - y256[11] = mulhi_int16_simd256(y256[11],ONE_OVER_SQRT2_Q15_256); - y256[12] = mulhi_int16_simd256(y256[12],ONE_OVER_SQRT2_Q15_256); - y256[13] = mulhi_int16_simd256(y256[13],ONE_OVER_SQRT2_Q15_256); - y256[14] = mulhi_int16_simd256(y256[14],ONE_OVER_SQRT2_Q15_256); - y256[15] = mulhi_int16_simd256(y256[15],ONE_OVER_SQRT2_Q15_256); - - } - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft128.m","dft",y256,128,1,1); - exit(-1); - } -} - -#endif - -#ifndef __AVX2__ -void idft128(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[64],*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[32],*tw128_128p=(simd_q15_t *)tw128,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - - transpose4_ooff(x64 ,xtmp,32); - transpose4_ooff(x64+2,xtmp+1,32); - transpose4_ooff(x64+4,xtmp+2,32); - transpose4_ooff(x64+6,xtmp+3,32); - transpose4_ooff(x64+8,xtmp+4,32); - transpose4_ooff(x64+10,xtmp+5,32); - transpose4_ooff(x64+12,xtmp+6,32); - transpose4_ooff(x64+14,xtmp+7,32); - transpose4_ooff(x64+16,xtmp+8,32); - transpose4_ooff(x64+18,xtmp+9,32); - transpose4_ooff(x64+20,xtmp+10,32); - transpose4_ooff(x64+22,xtmp+11,32); - transpose4_ooff(x64+24,xtmp+12,32); - transpose4_ooff(x64+26,xtmp+13,32); - transpose4_ooff(x64+28,xtmp+14,32); - transpose4_ooff(x64+30,xtmp+15,32); - transpose4_ooff(x64+32,xtmp+16,32); - transpose4_ooff(x64+34,xtmp+17,32); - transpose4_ooff(x64+36,xtmp+18,32); - transpose4_ooff(x64+38,xtmp+19,32); - transpose4_ooff(x64+40,xtmp+20,32); - transpose4_ooff(x64+42,xtmp+21,32); - transpose4_ooff(x64+44,xtmp+22,32); - transpose4_ooff(x64+46,xtmp+23,32); - transpose4_ooff(x64+48,xtmp+24,32); - transpose4_ooff(x64+50,xtmp+25,32); - transpose4_ooff(x64+52,xtmp+26,32); - transpose4_ooff(x64+54,xtmp+27,32); - transpose4_ooff(x64+56,xtmp+28,32); - transpose4_ooff(x64+58,xtmp+29,32); - transpose4_ooff(x64+60,xtmp+30,32); - transpose4_ooff(x64+62,xtmp+31,32); - - idft64((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft64((int16_t*)(xtmp+32),(int16_t*)(ytmp+16),1); - - - for (i=0; i<16; i++) { - ibfly2(ytmpp,ytmpp+16, - y128p,y128p+16, - tw128_128p); - tw128_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - y128[0] = mulhi_int16(y128[0],ONE_OVER_SQRT2_Q15_128); - y128[1] = mulhi_int16(y128[1],ONE_OVER_SQRT2_Q15_128); - y128[2] = mulhi_int16(y128[2],ONE_OVER_SQRT2_Q15_128); - y128[3] = mulhi_int16(y128[3],ONE_OVER_SQRT2_Q15_128); - y128[4] = mulhi_int16(y128[4],ONE_OVER_SQRT2_Q15_128); - y128[5] = mulhi_int16(y128[5],ONE_OVER_SQRT2_Q15_128); - y128[6] = mulhi_int16(y128[6],ONE_OVER_SQRT2_Q15_128); - y128[7] = mulhi_int16(y128[7],ONE_OVER_SQRT2_Q15_128); - y128[8] = mulhi_int16(y128[8],ONE_OVER_SQRT2_Q15_128); - y128[9] = mulhi_int16(y128[9],ONE_OVER_SQRT2_Q15_128); - y128[10] = mulhi_int16(y128[10],ONE_OVER_SQRT2_Q15_128); - y128[11] = mulhi_int16(y128[11],ONE_OVER_SQRT2_Q15_128); - y128[12] = mulhi_int16(y128[12],ONE_OVER_SQRT2_Q15_128); - y128[13] = mulhi_int16(y128[13],ONE_OVER_SQRT2_Q15_128); - y128[14] = mulhi_int16(y128[14],ONE_OVER_SQRT2_Q15_128); - y128[15] = mulhi_int16(y128[15],ONE_OVER_SQRT2_Q15_128); - y128[16] = mulhi_int16(y128[16],ONE_OVER_SQRT2_Q15_128); - y128[17] = mulhi_int16(y128[17],ONE_OVER_SQRT2_Q15_128); - y128[18] = mulhi_int16(y128[18],ONE_OVER_SQRT2_Q15_128); - y128[19] = mulhi_int16(y128[19],ONE_OVER_SQRT2_Q15_128); - y128[20] = mulhi_int16(y128[20],ONE_OVER_SQRT2_Q15_128); - y128[21] = mulhi_int16(y128[21],ONE_OVER_SQRT2_Q15_128); - y128[22] = mulhi_int16(y128[22],ONE_OVER_SQRT2_Q15_128); - y128[23] = mulhi_int16(y128[23],ONE_OVER_SQRT2_Q15_128); - y128[24] = mulhi_int16(y128[24],ONE_OVER_SQRT2_Q15_128); - y128[25] = mulhi_int16(y128[25],ONE_OVER_SQRT2_Q15_128); - y128[26] = mulhi_int16(y128[26],ONE_OVER_SQRT2_Q15_128); - y128[27] = mulhi_int16(y128[27],ONE_OVER_SQRT2_Q15_128); - y128[28] = mulhi_int16(y128[28],ONE_OVER_SQRT2_Q15_128); - y128[29] = mulhi_int16(y128[29],ONE_OVER_SQRT2_Q15_128); - y128[30] = mulhi_int16(y128[30],ONE_OVER_SQRT2_Q15_128); - y128[31] = mulhi_int16(y128[31],ONE_OVER_SQRT2_Q15_128); - - } - - _mm_empty(); - _m_empty(); - -} - -#else // __AVX2__ -void idft128(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[16],*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[16],*y256=(simd256_q15_t*)y; - simd256_q15_t *tw128_256p=(simd256_q15_t *)tw128,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_256 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - - transpose4_ooff_simd256(x256 ,xtmp,8); - transpose4_ooff_simd256(x256+2,xtmp+1,8); - transpose4_ooff_simd256(x256+4,xtmp+2,8); - transpose4_ooff_simd256(x256+6,xtmp+3,8); - transpose4_ooff_simd256(x256+8,xtmp+4,8); - transpose4_ooff_simd256(x256+10,xtmp+5,8); - transpose4_ooff_simd256(x256+12,xtmp+6,8); - transpose4_ooff_simd256(x256+14,xtmp+7,8); - - idft64((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft64((int16_t*)(xtmp+8),(int16_t*)(ytmp+8),1); - - - for (i=0; i<8; i++) { - ibfly2_256(ytmpp,ytmpp+8, - y256p,y256p+8, - tw128_256p); - tw128_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - y256[0] = mulhi_int16_simd256(y256[0],ONE_OVER_SQRT2_Q15_256); - y256[1] = mulhi_int16_simd256(y256[1],ONE_OVER_SQRT2_Q15_256); - y256[2] = mulhi_int16_simd256(y256[2],ONE_OVER_SQRT2_Q15_256); - y256[3] = mulhi_int16_simd256(y256[3],ONE_OVER_SQRT2_Q15_256); - y256[4] = mulhi_int16_simd256(y256[4],ONE_OVER_SQRT2_Q15_256); - y256[5] = mulhi_int16_simd256(y256[5],ONE_OVER_SQRT2_Q15_256); - y256[6] = mulhi_int16_simd256(y256[6],ONE_OVER_SQRT2_Q15_256); - y256[7] = mulhi_int16_simd256(y256[7],ONE_OVER_SQRT2_Q15_256); - y256[8] = mulhi_int16_simd256(y256[8],ONE_OVER_SQRT2_Q15_256); - y256[9] = mulhi_int16_simd256(y256[9],ONE_OVER_SQRT2_Q15_256); - y256[10] = mulhi_int16_simd256(y256[10],ONE_OVER_SQRT2_Q15_256); - y256[11] = mulhi_int16_simd256(y256[11],ONE_OVER_SQRT2_Q15_256); - y256[12] = mulhi_int16_simd256(y256[12],ONE_OVER_SQRT2_Q15_256); - y256[13] = mulhi_int16_simd256(y256[13],ONE_OVER_SQRT2_Q15_256); - y256[14] = mulhi_int16_simd256(y256[14],ONE_OVER_SQRT2_Q15_256); - y256[15] = mulhi_int16_simd256(y256[15],ONE_OVER_SQRT2_Q15_256); - - } - -} - -#endif - -int16_t tw256[384] __attribute__((aligned(32))) = { 32767,0,32757,-805,32727,-1608,32678,-2411,32609,-3212,32520,-4012,32412,-4808,32284,-5602,32137,-6393,31970,-7180,31785,-7962,31580,-8740,31356,-9512,31113,-10279,30851,-11039,30571,-11793,30272,-12540,29955,-13279,29621,-14010,29268,-14733,28897,-15447,28510,-16151,28105,-16846,27683,-17531,27244,-18205,26789,-18868,26318,-19520,25831,-20160,25329,-20788,24811,-21403,24278,-22005,23731,-22595,23169,-23170,22594,-23732,22004,-24279,21402,-24812,20787,-25330,20159,-25832,19519,-26319,18867,-26790,18204,-27245,17530,-27684,16845,-28106,16150,-28511,15446,-28898,14732,-29269,14009,-29622,13278,-29956,12539,-30273,11792,-30572,11038,-30852,10278,-31114,9511,-31357,8739,-31581,7961,-31786,7179,-31971,6392,-32138,5601,-32285,4807,-32413,4011,-32521,3211,-32610,2410,-32679,1607,-32728,804,-32758, - 32767,0,32727,-1608,32609,-3212,32412,-4808,32137,-6393,31785,-7962,31356,-9512,30851,-11039,30272,-12540,29621,-14010,28897,-15447,28105,-16846,27244,-18205,26318,-19520,25329,-20788,24278,-22005,23169,-23170,22004,-24279,20787,-25330,19519,-26319,18204,-27245,16845,-28106,15446,-28898,14009,-29622,12539,-30273,11038,-30852,9511,-31357,7961,-31786,6392,-32138,4807,-32413,3211,-32610,1607,-32728,0,-32767,-1608,-32728,-3212,-32610,-4808,-32413,-6393,-32138,-7962,-31786,-9512,-31357,-11039,-30852,-12540,-30273,-14010,-29622,-15447,-28898,-16846,-28106,-18205,-27245,-19520,-26319,-20788,-25330,-22005,-24279,-23170,-23170,-24279,-22005,-25330,-20788,-26319,-19520,-27245,-18205,-28106,-16846,-28898,-15447,-29622,-14010,-30273,-12540,-30852,-11039,-31357,-9512,-31786,-7962,-32138,-6393,-32413,-4808,-32610,-3212,-32728,-1608, - 32767,0,32678,-2411,32412,-4808,31970,-7180,31356,-9512,30571,-11793,29621,-14010,28510,-16151,27244,-18205,25831,-20160,24278,-22005,22594,-23732,20787,-25330,18867,-26790,16845,-28106,14732,-29269,12539,-30273,10278,-31114,7961,-31786,5601,-32285,3211,-32610,804,-32758,-1608,-32728,-4012,-32521,-6393,-32138,-8740,-31581,-11039,-30852,-13279,-29956,-15447,-28898,-17531,-27684,-19520,-26319,-21403,-24812,-23170,-23170,-24812,-21403,-26319,-19520,-27684,-17531,-28898,-15447,-29956,-13279,-30852,-11039,-31581,-8740,-32138,-6393,-32521,-4012,-32728,-1608,-32758,804,-32610,3211,-32285,5601,-31786,7961,-31114,10278,-30273,12539,-29269,14732,-28106,16845,-26790,18867,-25330,20787,-23732,22594,-22005,24278,-20160,25831,-18205,27244,-16151,28510,-14010,29621,-11793,30571,-9512,31356,-7180,31970,-4808,32412,-2411,32678 - }; - -int16_t tw256a[384] __attribute__((aligned(32))) = { 32767,0,32757,804,32727,1607,32678,2410,32609,3211,32520,4011,32412,4807,32284,5601,32137,6392,31970,7179,31785,7961,31580,8739,31356,9511,31113,10278,30851,11038,30571,11792,30272,12539,29955,13278,29621,14009,29268,14732,28897,15446,28510,16150,28105,16845,27683,17530,27244,18204,26789,18867,26318,19519,25831,20159,25329,20787,24811,21402,24278,22004,23731,22594,23169,23169,22594,23731,22004,24278,21402,24811,20787,25329,20159,25831,19519,26318,18867,26789,18204,27244,17530,27683,16845,28105,16150,28510,15446,28897,14732,29268,14009,29621,13278,29955,12539,30272,11792,30571,11038,30851,10278,31113,9511,31356,8739,31580,7961,31785,7179,31970,6392,32137,5601,32284,4807,32412,4011,32520,3211,32609,2410,32678,1607,32727,804,32757, - 32767,0,32727,1607,32609,3211,32412,4807,32137,6392,31785,7961,31356,9511,30851,11038,30272,12539,29621,14009,28897,15446,28105,16845,27244,18204,26318,19519,25329,20787,24278,22004,23169,23169,22004,24278,20787,25329,19519,26318,18204,27244,16845,28105,15446,28897,14009,29621,12539,30272,11038,30851,9511,31356,7961,31785,6392,32137,4807,32412,3211,32609,1607,32727,0,32767,-1608,32727,-3212,32609,-4808,32412,-6393,32137,-7962,31785,-9512,31356,-11039,30851,-12540,30272,-14010,29621,-15447,28897,-16846,28105,-18205,27244,-19520,26318,-20788,25329,-22005,24278,-23170,23169,-24279,22004,-25330,20787,-26319,19519,-27245,18204,-28106,16845,-28898,15446,-29622,14009,-30273,12539,-30852,11038,-31357,9511,-31786,7961,-32138,6392,-32413,4807,-32610,3211,-32728,1607, - 32767,0,32678,2410,32412,4807,31970,7179,31356,9511,30571,11792,29621,14009,28510,16150,27244,18204,25831,20159,24278,22004,22594,23731,20787,25329,18867,26789,16845,28105,14732,29268,12539,30272,10278,31113,7961,31785,5601,32284,3211,32609,804,32757,-1608,32727,-4012,32520,-6393,32137,-8740,31580,-11039,30851,-13279,29955,-15447,28897,-17531,27683,-19520,26318,-21403,24811,-23170,23169,-24812,21402,-26319,19519,-27684,17530,-28898,15446,-29956,13278,-30852,11038,-31581,8739,-32138,6392,-32521,4011,-32728,1607,-32758,-805,-32610,-3212,-32285,-5602,-31786,-7962,-31114,-10279,-30273,-12540,-29269,-14733,-28106,-16846,-26790,-18868,-25330,-20788,-23732,-22595,-22005,-24279,-20160,-25832,-18205,-27245,-16151,-28511,-14010,-29622,-11793,-30572,-9512,-31357,-7180,-31971,-4808,-32413,-2411,-32679 - }; - -int16_t tw256b[384] __attribute__((aligned(32))) = {0,32767,-805,32757,-1608,32727,-2411,32678,-3212,32609,-4012,32520,-4808,32412,-5602,32284,-6393,32137,-7180,31970,-7962,31785,-8740,31580,-9512,31356,-10279,31113,-11039,30851,-11793,30571,-12540,30272,-13279,29955,-14010,29621,-14733,29268,-15447,28897,-16151,28510,-16846,28105,-17531,27683,-18205,27244,-18868,26789,-19520,26318,-20160,25831,-20788,25329,-21403,24811,-22005,24278,-22595,23731,-23170,23169,-23732,22594,-24279,22004,-24812,21402,-25330,20787,-25832,20159,-26319,19519,-26790,18867,-27245,18204,-27684,17530,-28106,16845,-28511,16150,-28898,15446,-29269,14732,-29622,14009,-29956,13278,-30273,12539,-30572,11792,-30852,11038,-31114,10278,-31357,9511,-31581,8739,-31786,7961,-31971,7179,-32138,6392,-32285,5601,-32413,4807,-32521,4011,-32610,3211,-32679,2410,-32728,1607,-32758,804, - 0,32767,-1608,32727,-3212,32609,-4808,32412,-6393,32137,-7962,31785,-9512,31356,-11039,30851,-12540,30272,-14010,29621,-15447,28897,-16846,28105,-18205,27244,-19520,26318,-20788,25329,-22005,24278,-23170,23169,-24279,22004,-25330,20787,-26319,19519,-27245,18204,-28106,16845,-28898,15446,-29622,14009,-30273,12539,-30852,11038,-31357,9511,-31786,7961,-32138,6392,-32413,4807,-32610,3211,-32728,1607,-32767,0,-32728,-1608,-32610,-3212,-32413,-4808,-32138,-6393,-31786,-7962,-31357,-9512,-30852,-11039,-30273,-12540,-29622,-14010,-28898,-15447,-28106,-16846,-27245,-18205,-26319,-19520,-25330,-20788,-24279,-22005,-23170,-23170,-22005,-24279,-20788,-25330,-19520,-26319,-18205,-27245,-16846,-28106,-15447,-28898,-14010,-29622,-12540,-30273,-11039,-30852,-9512,-31357,-7962,-31786,-6393,-32138,-4808,-32413,-3212,-32610,-1608,-32728, - 0,32767,-2411,32678,-4808,32412,-7180,31970,-9512,31356,-11793,30571,-14010,29621,-16151,28510,-18205,27244,-20160,25831,-22005,24278,-23732,22594,-25330,20787,-26790,18867,-28106,16845,-29269,14732,-30273,12539,-31114,10278,-31786,7961,-32285,5601,-32610,3211,-32758,804,-32728,-1608,-32521,-4012,-32138,-6393,-31581,-8740,-30852,-11039,-29956,-13279,-28898,-15447,-27684,-17531,-26319,-19520,-24812,-21403,-23170,-23170,-21403,-24812,-19520,-26319,-17531,-27684,-15447,-28898,-13279,-29956,-11039,-30852,-8740,-31581,-6393,-32138,-4012,-32521,-1608,-32728,804,-32758,3211,-32610,5601,-32285,7961,-31786,10278,-31114,12539,-30273,14732,-29269,16845,-28106,18867,-26790,20787,-25330,22594,-23732,24278,-22005,25831,-20160,27244,-18205,28510,-16151,29621,-14010,30571,-11793,31356,-9512,31970,-7180,32412,-4808,32678,-2411 - }; -#ifndef __AVX2__ -void dft256(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[64],ytmp[64],*tw256a_128p=(simd_q15_t *)tw256a,*tw256b_128p=(simd_q15_t *)tw256b,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - -#ifdef D256STATS - time_stats_t ts_t,ts_d,ts_b; - - reset_meas(&ts_t); - reset_meas(&ts_d); - reset_meas(&ts_b); - start_meas(&ts_t); -#endif - /* - for (i=0,j=0;i<64;i+=4,j++) { - transpose16_ooff(x128+i,xtmp+j,16); - } - */ - transpose16_ooff(x128+0,xtmp+0,16); - transpose16_ooff(x128+4,xtmp+1,16); - transpose16_ooff(x128+8,xtmp+2,16); - transpose16_ooff(x128+12,xtmp+3,16); - transpose16_ooff(x128+16,xtmp+4,16); - transpose16_ooff(x128+20,xtmp+5,16); - transpose16_ooff(x128+24,xtmp+6,16); - transpose16_ooff(x128+28,xtmp+7,16); - transpose16_ooff(x128+32,xtmp+8,16); - transpose16_ooff(x128+36,xtmp+9,16); - transpose16_ooff(x128+40,xtmp+10,16); - transpose16_ooff(x128+44,xtmp+11,16); - transpose16_ooff(x128+48,xtmp+12,16); - transpose16_ooff(x128+52,xtmp+13,16); - transpose16_ooff(x128+56,xtmp+14,16); - transpose16_ooff(x128+60,xtmp+15,16); - -#ifdef D256STATS - stop_meas(&ts_t); - start_meas(&ts_d); -#endif - - dft64((int16_t*)(xtmp),(int16_t*)(ytmp),1); - dft64((int16_t*)(xtmp+16),(int16_t*)(ytmp+16),1); - dft64((int16_t*)(xtmp+32),(int16_t*)(ytmp+32),1); - dft64((int16_t*)(xtmp+48),(int16_t*)(ytmp+48),1); - -#ifdef D256STATS - stop_meas(&ts_d); - start_meas(&ts_b); -#endif - - for (i=0; i<16; i+=4) { - bfly4_16(ytmpp,ytmpp+16,ytmpp+32,ytmpp+48, - y128p,y128p+16,y128p+32,y128p+48, - tw256a_128p,tw256a_128p+16,tw256a_128p+32, - tw256b_128p,tw256b_128p+16,tw256b_128p+32); - bfly4_16(ytmpp+1,ytmpp+17,ytmpp+33,ytmpp+49, - y128p+1,y128p+17,y128p+33,y128p+49, - tw256a_128p+1,tw256a_128p+17,tw256a_128p+33, - tw256b_128p+1,tw256b_128p+17,tw256b_128p+33); - bfly4_16(ytmpp+2,ytmpp+18,ytmpp+34,ytmpp+50, - y128p+2,y128p+18,y128p+34,y128p+50, - tw256a_128p+2,tw256a_128p+18,tw256a_128p+34, - tw256b_128p+2,tw256b_128p+18,tw256b_128p+34); - bfly4_16(ytmpp+3,ytmpp+19,ytmpp+35,ytmpp+51, - y128p+3,y128p+19,y128p+35,y128p+51, - tw256a_128p+3,tw256a_128p+19,tw256a_128p+35, - tw256b_128p+3,tw256b_128p+19,tw256b_128p+35); - tw256a_128p+=4; - tw256b_128p+=4; - y128p+=4; - ytmpp+=4; - } - -#ifdef D256STATS - stop_meas(&ts_b); - printf("t: %llu cycles, d: %llu cycles, b: %llu cycles\n",ts_t.diff,ts_d.diff,ts_b.diff); -#endif - - if (scale>0) { - - for (i=0; i<4; i++) { - y128[0] = shiftright_int16(y128[0],1); - y128[1] = shiftright_int16(y128[1],1); - y128[2] = shiftright_int16(y128[2],1); - y128[3] = shiftright_int16(y128[3],1); - y128[4] = shiftright_int16(y128[4],1); - y128[5] = shiftright_int16(y128[5],1); - y128[6] = shiftright_int16(y128[6],1); - y128[7] = shiftright_int16(y128[7],1); - y128[8] = shiftright_int16(y128[8],1); - y128[9] = shiftright_int16(y128[9],1); - y128[10] = shiftright_int16(y128[10],1); - y128[11] = shiftright_int16(y128[11],1); - y128[12] = shiftright_int16(y128[12],1); - y128[13] = shiftright_int16(y128[13],1); - y128[14] = shiftright_int16(y128[14],1); - y128[15] = shiftright_int16(y128[15],1); - - y128+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - - - -void idft256(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[64],ytmp[64],*tw256_128p=(simd_q15_t *)tw256,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<64; i+=4,j++) { - transpose16_ooff(x128+i,xtmp+j,16); - } - - - idft64((int16_t*)(xtmp),(int16_t*)(ytmp),1); - idft64((int16_t*)(xtmp+16),(int16_t*)(ytmp+16),1); - idft64((int16_t*)(xtmp+32),(int16_t*)(ytmp+32),1); - idft64((int16_t*)(xtmp+48),(int16_t*)(ytmp+48),1); - - for (i=0; i<16; i++) { - ibfly4(ytmpp,ytmpp+16,ytmpp+32,ytmpp+48, - y128p,y128p+16,y128p+32,y128p+48, - tw256_128p,tw256_128p+16,tw256_128p+32); - tw256_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<4; i++) { - y128[0] = shiftright_int16(y128[0],1); - y128[1] = shiftright_int16(y128[1],1); - y128[2] = shiftright_int16(y128[2],1); - y128[3] = shiftright_int16(y128[3],1); - y128[4] = shiftright_int16(y128[4],1); - y128[5] = shiftright_int16(y128[5],1); - y128[6] = shiftright_int16(y128[6],1); - y128[7] = shiftright_int16(y128[7],1); - y128[8] = shiftright_int16(y128[8],1); - y128[9] = shiftright_int16(y128[9],1); - y128[10] = shiftright_int16(y128[10],1); - y128[11] = shiftright_int16(y128[11],1); - y128[12] = shiftright_int16(y128[12],1); - y128[13] = shiftright_int16(y128[13],1); - y128[14] = shiftright_int16(y128[14],1); - y128[15] = shiftright_int16(y128[15],1); - - y128+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -#else //__AVX2__ - -void dft256(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[32],ytmp[32],*tw256a_256p=(simd256_q15_t *)tw256a,*tw256b_256p=(simd256_q15_t *)tw256b,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - - transpose16_ooff_simd256(x256+0,xtmp+0,8); - transpose16_ooff_simd256(x256+4,xtmp+1,8); - transpose16_ooff_simd256(x256+8,xtmp+2,8); - transpose16_ooff_simd256(x256+12,xtmp+3,8); - transpose16_ooff_simd256(x256+16,xtmp+4,8); - transpose16_ooff_simd256(x256+20,xtmp+5,8); - transpose16_ooff_simd256(x256+24,xtmp+6,8); - transpose16_ooff_simd256(x256+28,xtmp+7,8); - /* - char vname[10]; - for (i=0;i<32;i++) { - sprintf(vname,"xtmp%d",i); - print_shorts256(vname,(int16_t*)(xtmp+i)); - } - exit(-1);*/ - - dft64((int16_t*)(xtmp),(int16_t*)(ytmp),1); - dft64((int16_t*)(xtmp+8),(int16_t*)(ytmp+8),1); - dft64((int16_t*)(xtmp+16),(int16_t*)(ytmp+16),1); - dft64((int16_t*)(xtmp+24),(int16_t*)(ytmp+24),1); - - - bfly4_16_256(ytmpp,ytmpp+8,ytmpp+16,ytmpp+24, - y256p,y256p+8,y256p+16,y256p+24, - tw256a_256p,tw256a_256p+8,tw256a_256p+16, - tw256b_256p,tw256b_256p+8,tw256b_256p+16); - bfly4_16_256(ytmpp+1,ytmpp+9,ytmpp+17,ytmpp+25, - y256p+1,y256p+9,y256p+17,y256p+25, - tw256a_256p+1,tw256a_256p+9,tw256a_256p+17, - tw256b_256p+1,tw256b_256p+9,tw256b_256p+17); - bfly4_16_256(ytmpp+2,ytmpp+10,ytmpp+18,ytmpp+26, - y256p+2,y256p+10,y256p+18,y256p+26, - tw256a_256p+2,tw256a_256p+10,tw256a_256p+18, - tw256b_256p+2,tw256b_256p+10,tw256b_256p+18); - bfly4_16_256(ytmpp+3,ytmpp+11,ytmpp+19,ytmpp+27, - y256p+3,y256p+11,y256p+19,y256p+27, - tw256a_256p+3,tw256a_256p+11,tw256a_256p+19, - tw256b_256p+3,tw256b_256p+11,tw256b_256p+19); - bfly4_16_256(ytmpp+4,ytmpp+12,ytmpp+20,ytmpp+28, - y256p+4,y256p+12,y256p+20,y256p+28, - tw256a_256p+4,tw256a_256p+12,tw256a_256p+20, - tw256b_256p+4,tw256b_256p+12,tw256b_256p+20); - bfly4_16_256(ytmpp+5,ytmpp+13,ytmpp+21,ytmpp+29, - y256p+5,y256p+13,y256p+21,y256p+29, - tw256a_256p+5,tw256a_256p+13,tw256a_256p+21, - tw256b_256p+5,tw256b_256p+13,tw256b_256p+21); - bfly4_16_256(ytmpp+6,ytmpp+14,ytmpp+22,ytmpp+30, - y256p+6,y256p+14,y256p+22,y256p+30, - tw256a_256p+6,tw256a_256p+14,tw256a_256p+22, - tw256b_256p+6,tw256b_256p+14,tw256b_256p+22); - bfly4_16_256(ytmpp+7,ytmpp+15,ytmpp+23,ytmpp+31, - y256p+7,y256p+15,y256p+23,y256p+31, - tw256a_256p+7,tw256a_256p+15,tw256a_256p+23, - tw256b_256p+7,tw256b_256p+15,tw256b_256p+23); - - if (scale>0) { - - for (i=0; i<2; i++) { - y256[0] = shiftright_int16_simd256(y256[0],1); - y256[1] = shiftright_int16_simd256(y256[1],1); - y256[2] = shiftright_int16_simd256(y256[2],1); - y256[3] = shiftright_int16_simd256(y256[3],1); - y256[4] = shiftright_int16_simd256(y256[4],1); - y256[5] = shiftright_int16_simd256(y256[5],1); - y256[6] = shiftright_int16_simd256(y256[6],1); - y256[7] = shiftright_int16_simd256(y256[7],1); - y256[8] = shiftright_int16_simd256(y256[8],1); - y256[9] = shiftright_int16_simd256(y256[9],1); - y256[10] = shiftright_int16_simd256(y256[10],1); - y256[11] = shiftright_int16_simd256(y256[11],1); - y256[12] = shiftright_int16_simd256(y256[12],1); - y256[13] = shiftright_int16_simd256(y256[13],1); - y256[14] = shiftright_int16_simd256(y256[14],1); - y256[15] = shiftright_int16_simd256(y256[15],1); - - y256+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -void idft256(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[32],ytmp[32],*tw256_256p=(simd256_q15_t *)tw256,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - - transpose16_ooff_simd256(x256+0,xtmp+0,8); - transpose16_ooff_simd256(x256+4,xtmp+1,8); - transpose16_ooff_simd256(x256+8,xtmp+2,8); - transpose16_ooff_simd256(x256+12,xtmp+3,8); - transpose16_ooff_simd256(x256+16,xtmp+4,8); - transpose16_ooff_simd256(x256+20,xtmp+5,8); - transpose16_ooff_simd256(x256+24,xtmp+6,8); - transpose16_ooff_simd256(x256+28,xtmp+7,8); - - idft64((int16_t*)(xtmp),(int16_t*)(ytmp),1); - idft64((int16_t*)(xtmp+8),(int16_t*)(ytmp+8),1); - idft64((int16_t*)(xtmp+16),(int16_t*)(ytmp+16),1); - idft64((int16_t*)(xtmp+24),(int16_t*)(ytmp+24),1); - - - ibfly4_256(ytmpp,ytmpp+8,ytmpp+16,ytmpp+24, - y256p,y256p+8,y256p+16,y256p+24, - tw256_256p,tw256_256p+8,tw256_256p+16); - - ibfly4_256(ytmpp+1,ytmpp+9,ytmpp+17,ytmpp+25, - y256p+1,y256p+9,y256p+17,y256p+25, - tw256_256p+1,tw256_256p+9,tw256_256p+17); - - ibfly4_256(ytmpp+2,ytmpp+10,ytmpp+18,ytmpp+26, - y256p+2,y256p+10,y256p+18,y256p+26, - tw256_256p+2,tw256_256p+10,tw256_256p+18); - - ibfly4_256(ytmpp+3,ytmpp+11,ytmpp+19,ytmpp+27, - y256p+3,y256p+11,y256p+19,y256p+27, - tw256_256p+3,tw256_256p+11,tw256_256p+19); - - ibfly4_256(ytmpp+4,ytmpp+12,ytmpp+20,ytmpp+28, - y256p+4,y256p+12,y256p+20,y256p+28, - tw256_256p+4,tw256_256p+12,tw256_256p+20); - - ibfly4_256(ytmpp+5,ytmpp+13,ytmpp+21,ytmpp+29, - y256p+5,y256p+13,y256p+21,y256p+29, - tw256_256p+5,tw256_256p+13,tw256_256p+21); - - ibfly4_256(ytmpp+6,ytmpp+14,ytmpp+22,ytmpp+30, - y256p+6,y256p+14,y256p+22,y256p+30, - tw256_256p+6,tw256_256p+14,tw256_256p+22); - - ibfly4_256(ytmpp+7,ytmpp+15,ytmpp+23,ytmpp+31, - y256p+7,y256p+15,y256p+23,y256p+31, - tw256_256p+7,tw256_256p+15,tw256_256p+23); - - - if (scale>0) { - - for (i=0; i<2; i++) { - y256[0] = shiftright_int16_simd256(y256[0],1); - y256[1] = shiftright_int16_simd256(y256[1],1); - y256[2] = shiftright_int16_simd256(y256[2],1); - y256[3] = shiftright_int16_simd256(y256[3],1); - y256[4] = shiftright_int16_simd256(y256[4],1); - y256[5] = shiftright_int16_simd256(y256[5],1); - y256[6] = shiftright_int16_simd256(y256[6],1); - y256[7] = shiftright_int16_simd256(y256[7],1); - y256[8] = shiftright_int16_simd256(y256[8],1); - y256[9] = shiftright_int16_simd256(y256[9],1); - y256[10] = shiftright_int16_simd256(y256[10],1); - y256[11] = shiftright_int16_simd256(y256[11],1); - y256[12] = shiftright_int16_simd256(y256[12],1); - y256[13] = shiftright_int16_simd256(y256[13],1); - y256[14] = shiftright_int16_simd256(y256[14],1); - y256[15] = shiftright_int16_simd256(y256[15],1); - - y256+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -#endif -int16_t tw512[512] __attribute__((aligned(32))) = { - 32767,0,32764,-403,32757,-805,32744,-1207,32727,-1608,32705,-2010,32678,-2411,32646,-2812,32609,-3212,32567,-3612,32520,-4012,32468,-4410,32412,-4808,32350,-5206,32284,-5602,32213,-5998,32137,-6393,32056,-6787,31970,-7180,31880,-7572,31785,-7962,31684,-8352,31580,-8740,31470,-9127,31356,-9512,31236,-9896,31113,-10279,30984,-10660,30851,-11039,30713,-11417,30571,-11793,30424,-12167,30272,-12540,30116,-12910,29955,-13279,29790,-13646,29621,-14010,29446,-14373,29268,-14733,29085,-15091,28897,-15447,28706,-15800,28510,-16151,28309,-16500,28105,-16846,27896,-17190,27683,-17531,27466,-17869,27244,-18205,27019,-18538,26789,-18868,26556,-19195,26318,-19520,26077,-19841,25831,-20160,25582,-20475,25329,-20788,25072,-21097,24811,-21403,24546,-21706,24278,-22005,24006,-22302,23731,-22595,23452,-22884,23169,-23170,22883,-23453,22594,-23732,22301,-24007,22004,-24279,21705,-24547,21402,-24812,21096,-25073,20787,-25330,20474,-25583,20159,-25832,19840,-26078,19519,-26319,19194,-26557,18867,-26790,18537,-27020,18204,-27245,17868,-27467,17530,-27684,17189,-27897,16845,-28106,16499,-28310,16150,-28511,15799,-28707,15446,-28898,15090,-29086,14732,-29269,14372,-29447,14009,-29622,13645,-29791,13278,-29956,12909,-30117,12539,-30273,12166,-30425,11792,-30572,11416,-30714,11038,-30852,10659,-30985,10278,-31114,9895,-31237,9511,-31357,9126,-31471,8739,-31581,8351,-31685,7961,-31786,7571,-31881,7179,-31971,6786,-32057,6392,-32138,5997,-32214,5601,-32285,5205,-32351,4807,-32413,4409,-32469,4011,-32521,3611,-32568,3211,-32610,2811,-32647,2410,-32679,2009,-32706,1607,-32728,1206,-32745,804,-32758,402,-32765,0,-32767,-403,-32765,-805,-32758,-1207,-32745,-1608,-32728,-2010,-32706,-2411,-32679,-2812,-32647,-3212,-32610,-3612,-32568,-4012,-32521,-4410,-32469,-4808,-32413,-5206,-32351,-5602,-32285,-5998,-32214,-6393,-32138,-6787,-32057,-7180,-31971,-7572,-31881,-7962,-31786,-8352,-31685,-8740,-31581,-9127,-31471,-9512,-31357,-9896,-31237,-10279,-31114,-10660,-30985,-11039,-30852,-11417,-30714,-11793,-30572,-12167,-30425,-12540,-30273,-12910,-30117,-13279,-29956,-13646,-29791,-14010,-29622,-14373,-29447,-14733,-29269,-15091,-29086,-15447,-28898,-15800,-28707,-16151,-28511,-16500,-28310,-16846,-28106,-17190,-27897,-17531,-27684,-17869,-27467,-18205,-27245,-18538,-27020,-18868,-26790,-19195,-26557,-19520,-26319,-19841,-26078,-20160,-25832,-20475,-25583,-20788,-25330,-21097,-25073,-21403,-24812,-21706,-24547,-22005,-24279,-22302,-24007,-22595,-23732,-22884,-23453,-23170,-23170,-23453,-22884,-23732,-22595,-24007,-22302,-24279,-22005,-24547,-21706,-24812,-21403,-25073,-21097,-25330,-20788,-25583,-20475,-25832,-20160,-26078,-19841,-26319,-19520,-26557,-19195,-26790,-18868,-27020,-18538,-27245,-18205,-27467,-17869,-27684,-17531,-27897,-17190,-28106,-16846,-28310,-16500,-28511,-16151,-28707,-15800,-28898,-15447,-29086,-15091,-29269,-14733,-29447,-14373,-29622,-14010,-29791,-13646,-29956,-13279,-30117,-12910,-30273,-12540,-30425,-12167,-30572,-11793,-30714,-11417,-30852,-11039,-30985,-10660,-31114,-10279,-31237,-9896,-31357,-9512,-31471,-9127,-31581,-8740,-31685,-8352,-31786,-7962,-31881,-7572,-31971,-7180,-32057,-6787,-32138,-6393,-32214,-5998,-32285,-5602,-32351,-5206,-32413,-4808,-32469,-4410,-32521,-4012,-32568,-3612,-32610,-3212,-32647,-2812,-32679,-2411,-32706,-2010,-32728,-1608,-32745,-1207,-32758,-805,-32765,-403 -}; - -int16_t tw512a[512] __attribute__((aligned(32))) = { - 32767,0,32764,403,32757,805,32744,1207,32727,1608,32705,2010,32678,2411,32646,2812,32609,3212,32567,3612,32520,4012,32468,4410,32412,4808,32350,5206,32284,5602,32213,5998,32137,6393,32056,6787,31970,7180,31880,7572,31785,7962,31684,8352,31580,8740,31470,9127,31356,9512,31236,9896,31113,10279,30984,10660,30851,11039,30713,11417,30571,11793,30424,12167,30272,12540,30116,12910,29955,13279,29790,13646,29621,14010,29446,14373,29268,14733,29085,15091,28897,15447,28706,15800,28510,16151,28309,16500,28105,16846,27896,17190,27683,17531,27466,17869,27244,18205,27019,18538,26789,18868,26556,19195,26318,19520,26077,19841,25831,20160,25582,20475,25329,20788,25072,21097,24811,21403,24546,21706,24278,22005,24006,22302,23731,22595,23452,22884,23169,23170,22883,23453,22594,23732,22301,24007,22004,24279,21705,24547,21402,24812,21096,25073,20787,25330,20474,25583,20159,25832,19840,26078,19519,26319,19194,26557,18867,26790,18537,27020,18204,27245,17868,27467,17530,27684,17189,27897,16845,28106,16499,28310,16150,28511,15799,28707,15446,28898,15090,29086,14732,29269,14372,29447,14009,29622,13645,29791,13278,29956,12909,30117,12539,30273,12166,30425,11792,30572,11416,30714,11038,30852,10659,30985,10278,31114,9895,31237,9511,31357,9126,31471,8739,31581,8351,31685,7961,31786,7571,31881,7179,31971,6786,32057,6392,32138,5997,32214,5601,32285,5205,32351,4807,32413,4409,32469,4011,32521,3611,32568,3211,32610,2811,32647,2410,32679,2009,32706,1607,32728,1206,32745,804,32758,402,32765,0,32767,-403,32765,-805,32758,-1207,32745,-1608,32728,-2010,32706,-2411,32679,-2812,32647,-3212,32610,-3612,32568,-4012,32521,-4410,32469,-4808,32413,-5206,32351,-5602,32285,-5998,32214,-6393,32138,-6787,32057,-7180,31971,-7572,31881,-7962,31786,-8352,31685,-8740,31581,-9127,31471,-9512,31357,-9896,31237,-10279,31114,-10660,30985,-11039,30852,-11417,30714,-11793,30572,-12167,30425,-12540,30273,-12910,30117,-13279,29956,-13646,29791,-14010,29622,-14373,29447,-14733,29269,-15091,29086,-15447,28898,-15800,28707,-16151,28511,-16500,28310,-16846,28106,-17190,27897,-17531,27684,-17869,27467,-18205,27245,-18538,27020,-18868,26790,-19195,26557,-19520,26319,-19841,26078,-20160,25832,-20475,25583,-20788,25330,-21097,25073,-21403,24812,-21706,24547,-22005,24279,-22302,24007,-22595,23732,-22884,23453,-23170,23170,-23453,22884,-23732,22595,-24007,22302,-24279,22005,-24547,21706,-24812,21403,-25073,21097,-25330,20788,-25583,20475,-25832,20160,-26078,19841,-26319,19520,-26557,19195,-26790,18868,-27020,18538,-27245,18205,-27467,17869,-27684,17531,-27897,17190,-28106,16846,-28310,16500,-28511,16151,-28707,15800,-28898,15447,-29086,15091,-29269,14733,-29447,14373,-29622,14010,-29791,13646,-29956,13279,-30117,12910,-30273,12540,-30425,12167,-30572,11793,-30714,11417,-30852,11039,-30985,10660,-31114,10279,-31237,9896,-31357,9512,-31471,9127,-31581,8740,-31685,8352,-31786,7962,-31881,7572,-31971,7180,-32057,6787,-32138,6393,-32214,5998,-32285,5602,-32351,5206,-32413,4808,-32469,4410,-32521,4012,-32568,3612,-32610,3212,-32647,2812,-32679,2411,-32706,2010,-32728,1608,-32745,1207,-32758,805,-32765,403 -}; - - - -int16_t tw512b[512] __attribute__((aligned(32))) = { - 0,32767,-403,32764,-805,32757,-1207,32744,-1608,32727,-2010,32705,-2411,32678,-2812,32646,-3212,32609,-3612,32567,-4012,32520,-4410,32468,-4808,32412,-5206,32350,-5602,32284,-5998,32213,-6393,32137,-6787,32056,-7180,31970,-7572,31880,-7962,31785,-8352,31684,-8740,31580,-9127,31470,-9512,31356,-9896,31236,-10279,31113,-10660,30984,-11039,30851,-11417,30713,-11793,30571,-12167,30424,-12540,30272,-12910,30116,-13279,29955,-13646,29790,-14010,29621,-14373,29446,-14733,29268,-15091,29085,-15447,28897,-15800,28706,-16151,28510,-16500,28309,-16846,28105,-17190,27896,-17531,27683,-17869,27466,-18205,27244,-18538,27019,-18868,26789,-19195,26556,-19520,26318,-19841,26077,-20160,25831,-20475,25582,-20788,25329,-21097,25072,-21403,24811,-21706,24546,-22005,24278,-22302,24006,-22595,23731,-22884,23452,-23170,23169,-23453,22883,-23732,22594,-24007,22301,-24279,22004,-24547,21705,-24812,21402,-25073,21096,-25330,20787,-25583,20474,-25832,20159,-26078,19840,-26319,19519,-26557,19194,-26790,18867,-27020,18537,-27245,18204,-27467,17868,-27684,17530,-27897,17189,-28106,16845,-28310,16499,-28511,16150,-28707,15799,-28898,15446,-29086,15090,-29269,14732,-29447,14372,-29622,14009,-29791,13645,-29956,13278,-30117,12909,-30273,12539,-30425,12166,-30572,11792,-30714,11416,-30852,11038,-30985,10659,-31114,10278,-31237,9895,-31357,9511,-31471,9126,-31581,8739,-31685,8351,-31786,7961,-31881,7571,-31971,7179,-32057,6786,-32138,6392,-32214,5997,-32285,5601,-32351,5205,-32413,4807,-32469,4409,-32521,4011,-32568,3611,-32610,3211,-32647,2811,-32679,2410,-32706,2009,-32728,1607,-32745,1206,-32758,804,-32765,402,-32767,0,-32765,-403,-32758,-805,-32745,-1207,-32728,-1608,-32706,-2010,-32679,-2411,-32647,-2812,-32610,-3212,-32568,-3612,-32521,-4012,-32469,-4410,-32413,-4808,-32351,-5206,-32285,-5602,-32214,-5998,-32138,-6393,-32057,-6787,-31971,-7180,-31881,-7572,-31786,-7962,-31685,-8352,-31581,-8740,-31471,-9127,-31357,-9512,-31237,-9896,-31114,-10279,-30985,-10660,-30852,-11039,-30714,-11417,-30572,-11793,-30425,-12167,-30273,-12540,-30117,-12910,-29956,-13279,-29791,-13646,-29622,-14010,-29447,-14373,-29269,-14733,-29086,-15091,-28898,-15447,-28707,-15800,-28511,-16151,-28310,-16500,-28106,-16846,-27897,-17190,-27684,-17531,-27467,-17869,-27245,-18205,-27020,-18538,-26790,-18868,-26557,-19195,-26319,-19520,-26078,-19841,-25832,-20160,-25583,-20475,-25330,-20788,-25073,-21097,-24812,-21403,-24547,-21706,-24279,-22005,-24007,-22302,-23732,-22595,-23453,-22884,-23170,-23170,-22884,-23453,-22595,-23732,-22302,-24007,-22005,-24279,-21706,-24547,-21403,-24812,-21097,-25073,-20788,-25330,-20475,-25583,-20160,-25832,-19841,-26078,-19520,-26319,-19195,-26557,-18868,-26790,-18538,-27020,-18205,-27245,-17869,-27467,-17531,-27684,-17190,-27897,-16846,-28106,-16500,-28310,-16151,-28511,-15800,-28707,-15447,-28898,-15091,-29086,-14733,-29269,-14373,-29447,-14010,-29622,-13646,-29791,-13279,-29956,-12910,-30117,-12540,-30273,-12167,-30425,-11793,-30572,-11417,-30714,-11039,-30852,-10660,-30985,-10279,-31114,-9896,-31237,-9512,-31357,-9127,-31471,-8740,-31581,-8352,-31685,-7962,-31786,-7572,-31881,-7180,-31971,-6787,-32057,-6393,-32138,-5998,-32214,-5602,-32285,-5206,-32351,-4808,-32413,-4410,-32469,-4012,-32521,-3612,-32568,-3212,-32610,-2812,-32647,-2411,-32679,-2010,-32706,-1608,-32728,-1207,-32745,-805,-32758,-403,-32765 -}; - -int16_t tw512c[512] __attribute__((aligned(32))) = { - 0,32767,403,32764,805,32757,1207,32744,1608,32727,2010,32705,2411,32678,2812,32646,3212,32609,3612,32567,4012,32520,4410,32468,4808,32412,5206,32350,5602,32284,5998,32213,6393,32137,6787,32056,7180,31970,7572,31880,7962,31785,8352,31684,8740,31580,9127,31470,9512,31356,9896,31236,10279,31113,10660,30984,11039,30851,11417,30713,11793,30571,12167,30424,12540,30272,12910,30116,13279,29955,13646,29790,14010,29621,14373,29446,14733,29268,15091,29085,15447,28897,15800,28706,16151,28510,16500,28309,16846,28105,17190,27896,17531,27683,17869,27466,18205,27244,18538,27019,18868,26789,19195,26556,19520,26318,19841,26077,20160,25831,20475,25582,20788,25329,21097,25072,21403,24811,21706,24546,22005,24278,22302,24006,22595,23731,22884,23452,23170,23169,23453,22883,23732,22594,24007,22301,24279,22004,24547,21705,24812,21402,25073,21096,25330,20787,25583,20474,25832,20159,26078,19840,26319,19519,26557,19194,26790,18867,27020,18537,27245,18204,27467,17868,27684,17530,27897,17189,28106,16845,28310,16499,28511,16150,28707,15799,28898,15446,29086,15090,29269,14732,29447,14372,29622,14009,29791,13645,29956,13278,30117,12909,30273,12539,30425,12166,30572,11792,30714,11416,30852,11038,30985,10659,31114,10278,31237,9895,31357,9511,31471,9126,31581,8739,31685,8351,31786,7961,31881,7571,31971,7179,32057,6786,32138,6392,32214,5997,32285,5601,32351,5205,32413,4807,32469,4409,32521,4011,32568,3611,32610,3211,32647,2811,32679,2410,32706,2009,32728,1607,32745,1206,32758,804,32765,402,32767,0,32765,-403,32758,-805,32745,-1207,32728,-1608,32706,-2010,32679,-2411,32647,-2812,32610,-3212,32568,-3612,32521,-4012,32469,-4410,32413,-4808,32351,-5206,32285,-5602,32214,-5998,32138,-6393,32057,-6787,31971,-7180,31881,-7572,31786,-7962,31685,-8352,31581,-8740,31471,-9127,31357,-9512,31237,-9896,31114,-10279,30985,-10660,30852,-11039,30714,-11417,30572,-11793,30425,-12167,30273,-12540,30117,-12910,29956,-13279,29791,-13646,29622,-14010,29447,-14373,29269,-14733,29086,-15091,28898,-15447,28707,-15800,28511,-16151,28310,-16500,28106,-16846,27897,-17190,27684,-17531,27467,-17869,27245,-18205,27020,-18538,26790,-18868,26557,-19195,26319,-19520,26078,-19841,25832,-20160,25583,-20475,25330,-20788,25073,-21097,24812,-21403,24547,-21706,24279,-22005,24007,-22302,23732,-22595,23453,-22884,23170,-23170,22884,-23453,22595,-23732,22302,-24007,22005,-24279,21706,-24547,21403,-24812,21097,-25073,20788,-25330,20475,-25583,20160,-25832,19841,-26078,19520,-26319,19195,-26557,18868,-26790,18538,-27020,18205,-27245,17869,-27467,17531,-27684,17190,-27897,16846,-28106,16500,-28310,16151,-28511,15800,-28707,15447,-28898,15091,-29086,14733,-29269,14373,-29447,14010,-29622,13646,-29791,13279,-29956,12910,-30117,12540,-30273,12167,-30425,11793,-30572,11417,-30714,11039,-30852,10660,-30985,10279,-31114,9896,-31237,9512,-31357,9127,-31471,8740,-31581,8352,-31685,7962,-31786,7572,-31881,7180,-31971,6787,-32057,6393,-32138,5998,-32214,5602,-32285,5206,-32351,4808,-32413,4410,-32469,4012,-32521,3612,-32568,3212,-32610,2812,-32647,2411,-32679,2010,-32706,1608,-32728,1207,-32745,805,-32758,403,-32765 -}; - -#ifndef __AVX2__ -void dft512(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[256],*xtmpp,*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[128],*tw512a_128p=(simd_q15_t *)tw512a,*tw512b_128p=(simd_q15_t *)tw512b,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<4; i++) { - transpose4_ooff(x64 ,xtmpp,128); - transpose4_ooff(x64+2,xtmpp+1,128); - transpose4_ooff(x64+4,xtmpp+2,128); - transpose4_ooff(x64+6,xtmpp+3,128); - transpose4_ooff(x64+8,xtmpp+4,128); - transpose4_ooff(x64+10,xtmpp+5,128); - transpose4_ooff(x64+12,xtmpp+6,128); - transpose4_ooff(x64+14,xtmpp+7,128); - transpose4_ooff(x64+16,xtmpp+8,128); - transpose4_ooff(x64+18,xtmpp+9,128); - transpose4_ooff(x64+20,xtmpp+10,128); - transpose4_ooff(x64+22,xtmpp+11,128); - transpose4_ooff(x64+24,xtmpp+12,128); - transpose4_ooff(x64+26,xtmpp+13,128); - transpose4_ooff(x64+28,xtmpp+14,128); - transpose4_ooff(x64+30,xtmpp+15,128); - transpose4_ooff(x64+32,xtmpp+16,128); - transpose4_ooff(x64+34,xtmpp+17,128); - transpose4_ooff(x64+36,xtmpp+18,128); - transpose4_ooff(x64+38,xtmpp+19,128); - transpose4_ooff(x64+40,xtmpp+20,128); - transpose4_ooff(x64+42,xtmpp+21,128); - transpose4_ooff(x64+44,xtmpp+22,128); - transpose4_ooff(x64+46,xtmpp+23,128); - transpose4_ooff(x64+48,xtmpp+24,128); - transpose4_ooff(x64+50,xtmpp+25,128); - transpose4_ooff(x64+52,xtmpp+26,128); - transpose4_ooff(x64+54,xtmpp+27,128); - transpose4_ooff(x64+56,xtmpp+28,128); - transpose4_ooff(x64+58,xtmpp+29,128); - transpose4_ooff(x64+60,xtmpp+30,128); - transpose4_ooff(x64+62,xtmpp+31,128); - x64+=64; - xtmpp+=32; - } - - dft256((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft256((int16_t*)(xtmp+128),(int16_t*)(ytmp+64),1); - - - for (i=0; i<64; i+=8) { - bfly2_16(ytmpp,ytmpp+64, - y128p,y128p+64, - tw512a_128p, - tw512b_128p); - bfly2_16(ytmpp+1,ytmpp+65, - y128p+1,y128p+65, - tw512a_128p+1, - tw512b_128p+1); - bfly2_16(ytmpp+2,ytmpp+66, - y128p+2,y128p+66, - tw512a_128p+2, - tw512b_128p+2); - bfly2_16(ytmpp+3,ytmpp+67, - y128p+3,y128p+67, - tw512a_128p+3, - tw512b_128p+3); - bfly2_16(ytmpp+4,ytmpp+68, - y128p+4,y128p+68, - tw512a_128p+4, - tw512b_128p+4); - bfly2_16(ytmpp+5,ytmpp+69, - y128p+5,y128p+69, - tw512a_128p+5, - tw512b_128p+5); - bfly2_16(ytmpp+6,ytmpp+70, - y128p+6,y128p+70, - tw512a_128p+6, - tw512b_128p+6); - bfly2_16(ytmpp+7,ytmpp+71, - y128p+7,y128p+71, - tw512a_128p+7, - tw512b_128p+7); - tw512a_128p+=8; - tw512b_128p+=8; - y128p+=8; - ytmpp+=8; - } - - if (scale>0) { - y128p = y128; - - for (i=0; i<8; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -void idft512(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[256],*xtmpp,*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[128],*tw512_128p=(simd_q15_t *)tw512,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<4; i++) { - transpose4_ooff(x64 ,xtmpp,128); - transpose4_ooff(x64+2,xtmpp+1,128); - transpose4_ooff(x64+4,xtmpp+2,128); - transpose4_ooff(x64+6,xtmpp+3,128); - transpose4_ooff(x64+8,xtmpp+4,128); - transpose4_ooff(x64+10,xtmpp+5,128); - transpose4_ooff(x64+12,xtmpp+6,128); - transpose4_ooff(x64+14,xtmpp+7,128); - transpose4_ooff(x64+16,xtmpp+8,128); - transpose4_ooff(x64+18,xtmpp+9,128); - transpose4_ooff(x64+20,xtmpp+10,128); - transpose4_ooff(x64+22,xtmpp+11,128); - transpose4_ooff(x64+24,xtmpp+12,128); - transpose4_ooff(x64+26,xtmpp+13,128); - transpose4_ooff(x64+28,xtmpp+14,128); - transpose4_ooff(x64+30,xtmpp+15,128); - transpose4_ooff(x64+32,xtmpp+16,128); - transpose4_ooff(x64+34,xtmpp+17,128); - transpose4_ooff(x64+36,xtmpp+18,128); - transpose4_ooff(x64+38,xtmpp+19,128); - transpose4_ooff(x64+40,xtmpp+20,128); - transpose4_ooff(x64+42,xtmpp+21,128); - transpose4_ooff(x64+44,xtmpp+22,128); - transpose4_ooff(x64+46,xtmpp+23,128); - transpose4_ooff(x64+48,xtmpp+24,128); - transpose4_ooff(x64+50,xtmpp+25,128); - transpose4_ooff(x64+52,xtmpp+26,128); - transpose4_ooff(x64+54,xtmpp+27,128); - transpose4_ooff(x64+56,xtmpp+28,128); - transpose4_ooff(x64+58,xtmpp+29,128); - transpose4_ooff(x64+60,xtmpp+30,128); - transpose4_ooff(x64+62,xtmpp+31,128); - x64+=64; - xtmpp+=32; - } - - idft256((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft256((int16_t*)(xtmp+128),(int16_t*)(ytmp+64),1); - - - for (i=0; i<64; i++) { - ibfly2(ytmpp,ytmpp+64, - y128p,y128p+64, - tw512_128p); - tw512_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - y128p = y128; - - for (i=0; i<8; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -#else //__AVX2__ - -void dft512(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[64],*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[64],*y256=(simd256_q15_t*)y; - simd256_q15_t *tw512_256p=(simd256_q15_t*)tw512,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_256 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - - transpose4_ooff_simd256(x256 ,xtmp,32); - transpose4_ooff_simd256(x256+2,xtmp+1,32); - transpose4_ooff_simd256(x256+4,xtmp+2,32); - transpose4_ooff_simd256(x256+6,xtmp+3,32); - transpose4_ooff_simd256(x256+8,xtmp+4,32); - transpose4_ooff_simd256(x256+10,xtmp+5,32); - transpose4_ooff_simd256(x256+12,xtmp+6,32); - transpose4_ooff_simd256(x256+14,xtmp+7,32); - transpose4_ooff_simd256(x256+16,xtmp+8,32); - transpose4_ooff_simd256(x256+18,xtmp+9,32); - transpose4_ooff_simd256(x256+20,xtmp+10,32); - transpose4_ooff_simd256(x256+22,xtmp+11,32); - transpose4_ooff_simd256(x256+24,xtmp+12,32); - transpose4_ooff_simd256(x256+26,xtmp+13,32); - transpose4_ooff_simd256(x256+28,xtmp+14,32); - transpose4_ooff_simd256(x256+30,xtmp+15,32); - transpose4_ooff_simd256(x256+32,xtmp+16,32); - transpose4_ooff_simd256(x256+34,xtmp+17,32); - transpose4_ooff_simd256(x256+36,xtmp+18,32); - transpose4_ooff_simd256(x256+38,xtmp+19,32); - transpose4_ooff_simd256(x256+40,xtmp+20,32); - transpose4_ooff_simd256(x256+42,xtmp+21,32); - transpose4_ooff_simd256(x256+44,xtmp+22,32); - transpose4_ooff_simd256(x256+46,xtmp+23,32); - transpose4_ooff_simd256(x256+48,xtmp+24,32); - transpose4_ooff_simd256(x256+50,xtmp+25,32); - transpose4_ooff_simd256(x256+52,xtmp+26,32); - transpose4_ooff_simd256(x256+54,xtmp+27,32); - transpose4_ooff_simd256(x256+56,xtmp+28,32); - transpose4_ooff_simd256(x256+58,xtmp+29,32); - transpose4_ooff_simd256(x256+60,xtmp+30,32); - transpose4_ooff_simd256(x256+62,xtmp+31,32); - - dft256((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft256((int16_t*)(xtmp+32),(int16_t*)(ytmp+32),1); - - - for (i=0; i<32; i++) { - bfly2_256(ytmpp,ytmpp+32, - y256p,y256p+32, - tw512_256p); - tw512_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0;i<4;i++) { - y256[0] = mulhi_int16_simd256(y256[0],ONE_OVER_SQRT2_Q15_256); - y256[1] = mulhi_int16_simd256(y256[1],ONE_OVER_SQRT2_Q15_256); - y256[2] = mulhi_int16_simd256(y256[2],ONE_OVER_SQRT2_Q15_256); - y256[3] = mulhi_int16_simd256(y256[3],ONE_OVER_SQRT2_Q15_256); - y256[4] = mulhi_int16_simd256(y256[4],ONE_OVER_SQRT2_Q15_256); - y256[5] = mulhi_int16_simd256(y256[5],ONE_OVER_SQRT2_Q15_256); - y256[6] = mulhi_int16_simd256(y256[6],ONE_OVER_SQRT2_Q15_256); - y256[7] = mulhi_int16_simd256(y256[7],ONE_OVER_SQRT2_Q15_256); - y256[8] = mulhi_int16_simd256(y256[8],ONE_OVER_SQRT2_Q15_256); - y256[9] = mulhi_int16_simd256(y256[9],ONE_OVER_SQRT2_Q15_256); - y256[10] = mulhi_int16_simd256(y256[10],ONE_OVER_SQRT2_Q15_256); - y256[11] = mulhi_int16_simd256(y256[11],ONE_OVER_SQRT2_Q15_256); - y256[12] = mulhi_int16_simd256(y256[12],ONE_OVER_SQRT2_Q15_256); - y256[13] = mulhi_int16_simd256(y256[13],ONE_OVER_SQRT2_Q15_256); - y256[14] = mulhi_int16_simd256(y256[14],ONE_OVER_SQRT2_Q15_256); - y256[15] = mulhi_int16_simd256(y256[15],ONE_OVER_SQRT2_Q15_256); - y256+=16; - } - } - -} - -void idft512(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[64],*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[64],*y256=(simd256_q15_t*)y; - simd256_q15_t *tw512_256p=(simd256_q15_t *)tw512,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_256 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - - transpose4_ooff_simd256(x256 ,xtmp,32); - transpose4_ooff_simd256(x256+2,xtmp+1,32); - transpose4_ooff_simd256(x256+4,xtmp+2,32); - transpose4_ooff_simd256(x256+6,xtmp+3,32); - transpose4_ooff_simd256(x256+8,xtmp+4,32); - transpose4_ooff_simd256(x256+10,xtmp+5,32); - transpose4_ooff_simd256(x256+12,xtmp+6,32); - transpose4_ooff_simd256(x256+14,xtmp+7,32); - transpose4_ooff_simd256(x256+16,xtmp+8,32); - transpose4_ooff_simd256(x256+18,xtmp+9,32); - transpose4_ooff_simd256(x256+20,xtmp+10,32); - transpose4_ooff_simd256(x256+22,xtmp+11,32); - transpose4_ooff_simd256(x256+24,xtmp+12,32); - transpose4_ooff_simd256(x256+26,xtmp+13,32); - transpose4_ooff_simd256(x256+28,xtmp+14,32); - transpose4_ooff_simd256(x256+30,xtmp+15,32); - transpose4_ooff_simd256(x256+32,xtmp+16,32); - transpose4_ooff_simd256(x256+34,xtmp+17,32); - transpose4_ooff_simd256(x256+36,xtmp+18,32); - transpose4_ooff_simd256(x256+38,xtmp+19,32); - transpose4_ooff_simd256(x256+40,xtmp+20,32); - transpose4_ooff_simd256(x256+42,xtmp+21,32); - transpose4_ooff_simd256(x256+44,xtmp+22,32); - transpose4_ooff_simd256(x256+46,xtmp+23,32); - transpose4_ooff_simd256(x256+48,xtmp+24,32); - transpose4_ooff_simd256(x256+50,xtmp+25,32); - transpose4_ooff_simd256(x256+52,xtmp+26,32); - transpose4_ooff_simd256(x256+54,xtmp+27,32); - transpose4_ooff_simd256(x256+56,xtmp+28,32); - transpose4_ooff_simd256(x256+58,xtmp+29,32); - transpose4_ooff_simd256(x256+60,xtmp+30,32); - transpose4_ooff_simd256(x256+62,xtmp+31,32); - - idft256((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft256((int16_t*)(xtmp+32),(int16_t*)(ytmp+32),1); - - - for (i=0; i<32; i++) { - ibfly2_256(ytmpp,ytmpp+32, - y256p,y256p+32, - tw512_256p); - tw512_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0;i<4;i++) { - y256[0] = mulhi_int16_simd256(y256[0],ONE_OVER_SQRT2_Q15_256); - y256[1] = mulhi_int16_simd256(y256[1],ONE_OVER_SQRT2_Q15_256); - y256[2] = mulhi_int16_simd256(y256[2],ONE_OVER_SQRT2_Q15_256); - y256[3] = mulhi_int16_simd256(y256[3],ONE_OVER_SQRT2_Q15_256); - y256[4] = mulhi_int16_simd256(y256[4],ONE_OVER_SQRT2_Q15_256); - y256[5] = mulhi_int16_simd256(y256[5],ONE_OVER_SQRT2_Q15_256); - y256[6] = mulhi_int16_simd256(y256[6],ONE_OVER_SQRT2_Q15_256); - y256[7] = mulhi_int16_simd256(y256[7],ONE_OVER_SQRT2_Q15_256); - y256[8] = mulhi_int16_simd256(y256[8],ONE_OVER_SQRT2_Q15_256); - y256[9] = mulhi_int16_simd256(y256[9],ONE_OVER_SQRT2_Q15_256); - y256[10] = mulhi_int16_simd256(y256[10],ONE_OVER_SQRT2_Q15_256); - y256[11] = mulhi_int16_simd256(y256[11],ONE_OVER_SQRT2_Q15_256); - y256[12] = mulhi_int16_simd256(y256[12],ONE_OVER_SQRT2_Q15_256); - y256[13] = mulhi_int16_simd256(y256[13],ONE_OVER_SQRT2_Q15_256); - y256[14] = mulhi_int16_simd256(y256[14],ONE_OVER_SQRT2_Q15_256); - y256[15] = mulhi_int16_simd256(y256[15],ONE_OVER_SQRT2_Q15_256); - y256+=16; - } - } - -} - -#endif - -int16_t tw1024[1536] __attribute__((aligned(32))); - -#ifndef __AVX2__ -void dft1024(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[256],ytmp[256],*tw1024_128p=(simd_q15_t *)tw1024,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<256; i+=4,j++) { - transpose16_ooff(x128+i,xtmp+j,64); - } - - - dft256((int16_t*)(xtmp),(int16_t*)(ytmp),1); - dft256((int16_t*)(xtmp+64),(int16_t*)(ytmp+64),1); - dft256((int16_t*)(xtmp+128),(int16_t*)(ytmp+128),1); - dft256((int16_t*)(xtmp+192),(int16_t*)(ytmp+192),1); - - for (i=0; i<64; i++) { - bfly4(ytmpp,ytmpp+64,ytmpp+128,ytmpp+192, - y128p,y128p+64,y128p+128,y128p+192, - tw1024_128p,tw1024_128p+64,tw1024_128p+128); - tw1024_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<16; i++) { - y128[0] = shiftright_int16(y128[0],1); - y128[1] = shiftright_int16(y128[1],1); - y128[2] = shiftright_int16(y128[2],1); - y128[3] = shiftright_int16(y128[3],1); - y128[4] = shiftright_int16(y128[4],1); - y128[5] = shiftright_int16(y128[5],1); - y128[6] = shiftright_int16(y128[6],1); - y128[7] = shiftright_int16(y128[7],1); - y128[8] = shiftright_int16(y128[8],1); - y128[9] = shiftright_int16(y128[9],1); - y128[10] = shiftright_int16(y128[10],1); - y128[11] = shiftright_int16(y128[11],1); - y128[12] = shiftright_int16(y128[12],1); - y128[13] = shiftright_int16(y128[13],1); - y128[14] = shiftright_int16(y128[14],1); - y128[15] = shiftright_int16(y128[15],1); - - y128+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -void idft1024(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[256],ytmp[256],*tw1024_128p=(simd_q15_t *)tw1024,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<256; i+=4,j++) { - transpose16_ooff(x128+i,xtmp+j,64); - } - - - idft256((int16_t*)(xtmp),(int16_t*)(ytmp),1); - idft256((int16_t*)(xtmp+64),(int16_t*)(ytmp+64),1); - idft256((int16_t*)(xtmp+128),(int16_t*)(ytmp+128),1); - idft256((int16_t*)(xtmp+192),(int16_t*)(ytmp+192),1); - - for (i=0; i<64; i++) { - ibfly4(ytmpp,ytmpp+64,ytmpp+128,ytmpp+192, - y128p,y128p+64,y128p+128,y128p+192, - tw1024_128p,tw1024_128p+64,tw1024_128p+128); - tw1024_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<16; i++) { - y128[0] = shiftright_int16(y128[0],1); - y128[1] = shiftright_int16(y128[1],1); - y128[2] = shiftright_int16(y128[2],1); - y128[3] = shiftright_int16(y128[3],1); - y128[4] = shiftright_int16(y128[4],1); - y128[5] = shiftright_int16(y128[5],1); - y128[6] = shiftright_int16(y128[6],1); - y128[7] = shiftright_int16(y128[7],1); - y128[8] = shiftright_int16(y128[8],1); - y128[9] = shiftright_int16(y128[9],1); - y128[10] = shiftright_int16(y128[10],1); - y128[11] = shiftright_int16(y128[11],1); - y128[12] = shiftright_int16(y128[12],1); - y128[13] = shiftright_int16(y128[13],1); - y128[14] = shiftright_int16(y128[14],1); - y128[15] = shiftright_int16(y128[15],1); - - y128+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -#else //__AVX2__ -void dft1024(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[128],ytmp[128],*tw1024_256p=(simd256_q15_t *)tw1024,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<128; i+=4,j++) { - transpose16_ooff_simd256(x256+i,xtmp+j,32); - } - - - dft256((int16_t*)(xtmp),(int16_t*)(ytmp),1); - dft256((int16_t*)(xtmp+32),(int16_t*)(ytmp+32),1); - dft256((int16_t*)(xtmp+64),(int16_t*)(ytmp+64),1); - dft256((int16_t*)(xtmp+96),(int16_t*)(ytmp+96),1); - - for (i=0; i<32; i++) { - bfly4_256(ytmpp,ytmpp+32,ytmpp+64,ytmpp+96, - y256p,y256p+32,y256p+64,y256p+96, - tw1024_256p,tw1024_256p+32,tw1024_256p+64); - tw1024_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<8; i++) { - y256[0] = shiftright_int16_simd256(y256[0],1); - y256[1] = shiftright_int16_simd256(y256[1],1); - y256[2] = shiftright_int16_simd256(y256[2],1); - y256[3] = shiftright_int16_simd256(y256[3],1); - y256[4] = shiftright_int16_simd256(y256[4],1); - y256[5] = shiftright_int16_simd256(y256[5],1); - y256[6] = shiftright_int16_simd256(y256[6],1); - y256[7] = shiftright_int16_simd256(y256[7],1); - y256[8] = shiftright_int16_simd256(y256[8],1); - y256[9] = shiftright_int16_simd256(y256[9],1); - y256[10] = shiftright_int16_simd256(y256[10],1); - y256[11] = shiftright_int16_simd256(y256[11],1); - y256[12] = shiftright_int16_simd256(y256[12],1); - y256[13] = shiftright_int16_simd256(y256[13],1); - y256[14] = shiftright_int16_simd256(y256[14],1); - y256[15] = shiftright_int16_simd256(y256[15],1); - - y256+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -void idft1024(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[128],ytmp[128],*tw1024_256p=(simd256_q15_t *)tw1024,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<128; i+=4,j++) { - transpose16_ooff_simd256(x256+i,xtmp+j,32); - } - - - idft256((int16_t*)(xtmp),(int16_t*)(ytmp),1); - idft256((int16_t*)(xtmp+32),(int16_t*)(ytmp+32),1); - idft256((int16_t*)(xtmp+64),(int16_t*)(ytmp+64),1); - idft256((int16_t*)(xtmp+96),(int16_t*)(ytmp+96),1); - - for (i=0; i<32; i++) { - ibfly4_256(ytmpp,ytmpp+32,ytmpp+64,ytmpp+96, - y256p,y256p+32,y256p+64,y256p+96, - tw1024_256p,tw1024_256p+32,tw1024_256p+64); - tw1024_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<8; i++) { - y256[0] = shiftright_int16_simd256(y256[0],1); - y256[1] = shiftright_int16_simd256(y256[1],1); - y256[2] = shiftright_int16_simd256(y256[2],1); - y256[3] = shiftright_int16_simd256(y256[3],1); - y256[4] = shiftright_int16_simd256(y256[4],1); - y256[5] = shiftright_int16_simd256(y256[5],1); - y256[6] = shiftright_int16_simd256(y256[6],1); - y256[7] = shiftright_int16_simd256(y256[7],1); - y256[8] = shiftright_int16_simd256(y256[8],1); - y256[9] = shiftright_int16_simd256(y256[9],1); - y256[10] = shiftright_int16_simd256(y256[10],1); - y256[11] = shiftright_int16_simd256(y256[11],1); - y256[12] = shiftright_int16_simd256(y256[12],1); - y256[13] = shiftright_int16_simd256(y256[13],1); - y256[14] = shiftright_int16_simd256(y256[14],1); - y256[15] = shiftright_int16_simd256(y256[15],1); - - y256+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} -#endif - -int16_t tw2048[2048] __attribute__((aligned(32))); - -#ifndef __AVX2__ -void dft2048(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[1024],*xtmpp,*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[512],*tw2048_128p=(simd_q15_t *)tw2048,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<16; i++) { - transpose4_ooff(x64 ,xtmpp,512); - transpose4_ooff(x64+2,xtmpp+1,512); - transpose4_ooff(x64+4,xtmpp+2,512); - transpose4_ooff(x64+6,xtmpp+3,512); - transpose4_ooff(x64+8,xtmpp+4,512); - transpose4_ooff(x64+10,xtmpp+5,512); - transpose4_ooff(x64+12,xtmpp+6,512); - transpose4_ooff(x64+14,xtmpp+7,512); - transpose4_ooff(x64+16,xtmpp+8,512); - transpose4_ooff(x64+18,xtmpp+9,512); - transpose4_ooff(x64+20,xtmpp+10,512); - transpose4_ooff(x64+22,xtmpp+11,512); - transpose4_ooff(x64+24,xtmpp+12,512); - transpose4_ooff(x64+26,xtmpp+13,512); - transpose4_ooff(x64+28,xtmpp+14,512); - transpose4_ooff(x64+30,xtmpp+15,512); - transpose4_ooff(x64+32,xtmpp+16,512); - transpose4_ooff(x64+34,xtmpp+17,512); - transpose4_ooff(x64+36,xtmpp+18,512); - transpose4_ooff(x64+38,xtmpp+19,512); - transpose4_ooff(x64+40,xtmpp+20,512); - transpose4_ooff(x64+42,xtmpp+21,512); - transpose4_ooff(x64+44,xtmpp+22,512); - transpose4_ooff(x64+46,xtmpp+23,512); - transpose4_ooff(x64+48,xtmpp+24,512); - transpose4_ooff(x64+50,xtmpp+25,512); - transpose4_ooff(x64+52,xtmpp+26,512); - transpose4_ooff(x64+54,xtmpp+27,512); - transpose4_ooff(x64+56,xtmpp+28,512); - transpose4_ooff(x64+58,xtmpp+29,512); - transpose4_ooff(x64+60,xtmpp+30,512); - transpose4_ooff(x64+62,xtmpp+31,512); - x64+=64; - xtmpp+=32; - } - - dft1024((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft1024((int16_t*)(xtmp+512),(int16_t*)(ytmp+256),1); - - - for (i=0; i<256; i++) { - bfly2(ytmpp,ytmpp+256, - y128p,y128p+256, - tw2048_128p); - tw2048_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - y128p = y128; - - for (i=0; i<32; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - - -} - -void idft2048(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[1024],*xtmpp,*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[512],*tw2048_128p=(simd_q15_t *)tw2048,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<16; i++) { - transpose4_ooff(x64 ,xtmpp,512); - transpose4_ooff(x64+2,xtmpp+1,512); - transpose4_ooff(x64+4,xtmpp+2,512); - transpose4_ooff(x64+6,xtmpp+3,512); - transpose4_ooff(x64+8,xtmpp+4,512); - transpose4_ooff(x64+10,xtmpp+5,512); - transpose4_ooff(x64+12,xtmpp+6,512); - transpose4_ooff(x64+14,xtmpp+7,512); - transpose4_ooff(x64+16,xtmpp+8,512); - transpose4_ooff(x64+18,xtmpp+9,512); - transpose4_ooff(x64+20,xtmpp+10,512); - transpose4_ooff(x64+22,xtmpp+11,512); - transpose4_ooff(x64+24,xtmpp+12,512); - transpose4_ooff(x64+26,xtmpp+13,512); - transpose4_ooff(x64+28,xtmpp+14,512); - transpose4_ooff(x64+30,xtmpp+15,512); - transpose4_ooff(x64+32,xtmpp+16,512); - transpose4_ooff(x64+34,xtmpp+17,512); - transpose4_ooff(x64+36,xtmpp+18,512); - transpose4_ooff(x64+38,xtmpp+19,512); - transpose4_ooff(x64+40,xtmpp+20,512); - transpose4_ooff(x64+42,xtmpp+21,512); - transpose4_ooff(x64+44,xtmpp+22,512); - transpose4_ooff(x64+46,xtmpp+23,512); - transpose4_ooff(x64+48,xtmpp+24,512); - transpose4_ooff(x64+50,xtmpp+25,512); - transpose4_ooff(x64+52,xtmpp+26,512); - transpose4_ooff(x64+54,xtmpp+27,512); - transpose4_ooff(x64+56,xtmpp+28,512); - transpose4_ooff(x64+58,xtmpp+29,512); - transpose4_ooff(x64+60,xtmpp+30,512); - transpose4_ooff(x64+62,xtmpp+31,512); - x64+=64; - xtmpp+=32; - } - - idft1024((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft1024((int16_t*)(xtmp+512),(int16_t*)(ytmp+256),1); - - - for (i=0; i<256; i++) { - ibfly2(ytmpp,ytmpp+256, - y128p,y128p+256, - tw2048_128p); - tw2048_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - y128p = y128; - - for (i=0; i<32; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -#else // __AVX2__ - -void dft2048(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[256],*xtmpp,*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[256],*tw2048_256p=(simd256_q15_t *)tw2048,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - - xtmpp = xtmp; - - for (i=0; i<4; i++) { - transpose4_ooff_simd256(x256 ,xtmpp,128); - transpose4_ooff_simd256(x256+2,xtmpp+1,128); - transpose4_ooff_simd256(x256+4,xtmpp+2,128); - transpose4_ooff_simd256(x256+6,xtmpp+3,128); - transpose4_ooff_simd256(x256+8,xtmpp+4,128); - transpose4_ooff_simd256(x256+10,xtmpp+5,128); - transpose4_ooff_simd256(x256+12,xtmpp+6,128); - transpose4_ooff_simd256(x256+14,xtmpp+7,128); - transpose4_ooff_simd256(x256+16,xtmpp+8,128); - transpose4_ooff_simd256(x256+18,xtmpp+9,128); - transpose4_ooff_simd256(x256+20,xtmpp+10,128); - transpose4_ooff_simd256(x256+22,xtmpp+11,128); - transpose4_ooff_simd256(x256+24,xtmpp+12,128); - transpose4_ooff_simd256(x256+26,xtmpp+13,128); - transpose4_ooff_simd256(x256+28,xtmpp+14,128); - transpose4_ooff_simd256(x256+30,xtmpp+15,128); - transpose4_ooff_simd256(x256+32,xtmpp+16,128); - transpose4_ooff_simd256(x256+34,xtmpp+17,128); - transpose4_ooff_simd256(x256+36,xtmpp+18,128); - transpose4_ooff_simd256(x256+38,xtmpp+19,128); - transpose4_ooff_simd256(x256+40,xtmpp+20,128); - transpose4_ooff_simd256(x256+42,xtmpp+21,128); - transpose4_ooff_simd256(x256+44,xtmpp+22,128); - transpose4_ooff_simd256(x256+46,xtmpp+23,128); - transpose4_ooff_simd256(x256+48,xtmpp+24,128); - transpose4_ooff_simd256(x256+50,xtmpp+25,128); - transpose4_ooff_simd256(x256+52,xtmpp+26,128); - transpose4_ooff_simd256(x256+54,xtmpp+27,128); - transpose4_ooff_simd256(x256+56,xtmpp+28,128); - transpose4_ooff_simd256(x256+58,xtmpp+29,128); - transpose4_ooff_simd256(x256+60,xtmpp+30,128); - transpose4_ooff_simd256(x256+62,xtmpp+31,128); - x256+=64; - xtmpp+=32; - } - - dft1024((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft1024((int16_t*)(xtmp+128),(int16_t*)(ytmp+128),1); - - - for (i=0; i<128; i++) { - bfly2_256(ytmpp,ytmpp+128, - y256p,y256p+128, - tw2048_256p); - tw2048_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - y256p = y256; - - for (i=0; i<16; i++) { - y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); - y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); - y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); - y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); - y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); - y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); - y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); - y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); - y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); - y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); - y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); - y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); - y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); - y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); - y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); - y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); - y256p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -void idft2048(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[256],*xtmpp,*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[256],*tw2048_256p=(simd256_q15_t *)tw2048,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<4; i++) { - transpose4_ooff_simd256(x256 ,xtmpp,128); - transpose4_ooff_simd256(x256+2,xtmpp+1,128); - transpose4_ooff_simd256(x256+4,xtmpp+2,128); - transpose4_ooff_simd256(x256+6,xtmpp+3,128); - transpose4_ooff_simd256(x256+8,xtmpp+4,128); - transpose4_ooff_simd256(x256+10,xtmpp+5,128); - transpose4_ooff_simd256(x256+12,xtmpp+6,128); - transpose4_ooff_simd256(x256+14,xtmpp+7,128); - transpose4_ooff_simd256(x256+16,xtmpp+8,128); - transpose4_ooff_simd256(x256+18,xtmpp+9,128); - transpose4_ooff_simd256(x256+20,xtmpp+10,128); - transpose4_ooff_simd256(x256+22,xtmpp+11,128); - transpose4_ooff_simd256(x256+24,xtmpp+12,128); - transpose4_ooff_simd256(x256+26,xtmpp+13,128); - transpose4_ooff_simd256(x256+28,xtmpp+14,128); - transpose4_ooff_simd256(x256+30,xtmpp+15,128); - transpose4_ooff_simd256(x256+32,xtmpp+16,128); - transpose4_ooff_simd256(x256+34,xtmpp+17,128); - transpose4_ooff_simd256(x256+36,xtmpp+18,128); - transpose4_ooff_simd256(x256+38,xtmpp+19,128); - transpose4_ooff_simd256(x256+40,xtmpp+20,128); - transpose4_ooff_simd256(x256+42,xtmpp+21,128); - transpose4_ooff_simd256(x256+44,xtmpp+22,128); - transpose4_ooff_simd256(x256+46,xtmpp+23,128); - transpose4_ooff_simd256(x256+48,xtmpp+24,128); - transpose4_ooff_simd256(x256+50,xtmpp+25,128); - transpose4_ooff_simd256(x256+52,xtmpp+26,128); - transpose4_ooff_simd256(x256+54,xtmpp+27,128); - transpose4_ooff_simd256(x256+56,xtmpp+28,128); - transpose4_ooff_simd256(x256+58,xtmpp+29,128); - transpose4_ooff_simd256(x256+60,xtmpp+30,128); - transpose4_ooff_simd256(x256+62,xtmpp+31,128); - x256+=64; - xtmpp+=32; - } - - idft1024((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft1024((int16_t*)(xtmp+128),(int16_t*)(ytmp+128),1); - - - for (i=0; i<128; i++) { - ibfly2_256(ytmpp,ytmpp+128, - y256p,y256p+128, - tw2048_256p); - tw2048_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - y256p = y256; - - for (i=0; i<16; i++) { - y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); - y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); - y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); - y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); - y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); - y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); - y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); - y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); - y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); - y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); - y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); - y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); - y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); - y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); - y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); - y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); - y256p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -#endif - - - -int16_t tw4096[3*2*1024]; - -#ifndef __AVX2__ -void dft4096(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[1024],ytmp[1024],*tw4096_128p=(simd_q15_t *)tw4096,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<1024; i+=4,j++) { - transpose16_ooff(x128+i,xtmp+j,256); - } - - - dft1024((int16_t*)(xtmp),(int16_t*)(ytmp),1); - dft1024((int16_t*)(xtmp+256),(int16_t*)(ytmp+256),1); - dft1024((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); - dft1024((int16_t*)(xtmp+768),(int16_t*)(ytmp+768),1); - - for (i=0; i<256; i++) { - bfly4(ytmpp,ytmpp+256,ytmpp+512,ytmpp+768, - y128p,y128p+256,y128p+512,y128p+768, - tw4096_128p,tw4096_128p+256,tw4096_128p+512); - tw4096_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<64; i++) { - y128[0] = shiftright_int16(y128[0],1); - y128[1] = shiftright_int16(y128[1],1); - y128[2] = shiftright_int16(y128[2],1); - y128[3] = shiftright_int16(y128[3],1); - y128[4] = shiftright_int16(y128[4],1); - y128[5] = shiftright_int16(y128[5],1); - y128[6] = shiftright_int16(y128[6],1); - y128[7] = shiftright_int16(y128[7],1); - y128[8] = shiftright_int16(y128[8],1); - y128[9] = shiftright_int16(y128[9],1); - y128[10] = shiftright_int16(y128[10],1); - y128[11] = shiftright_int16(y128[11],1); - y128[12] = shiftright_int16(y128[12],1); - y128[13] = shiftright_int16(y128[13],1); - y128[14] = shiftright_int16(y128[14],1); - y128[15] = shiftright_int16(y128[15],1); - - y128+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - - - -void idft4096(int16_t *x,int16_t *y,int scale) -{ - - simd_q15_t xtmp[1024],ytmp[1024],*tw4096_128p=(simd_q15_t *)tw4096,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<1024; i+=4,j++) { - transpose16_ooff(x128+i,xtmp+j,256); - } - - - idft1024((int16_t*)(xtmp),(int16_t*)(ytmp),1); - idft1024((int16_t*)(xtmp+256),(int16_t*)(ytmp+256),1); - idft1024((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); - idft1024((int16_t*)(xtmp+768),(int16_t*)(ytmp+768),1); - - for (i=0; i<256; i++) { - ibfly4(ytmpp,ytmpp+256,ytmpp+512,ytmpp+768, - y128p,y128p+256,y128p+512,y128p+768, - tw4096_128p,tw4096_128p+256,tw4096_128p+512); - tw4096_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<64; i++) { - y128[0] = shiftright_int16(y128[0],scale); - y128[1] = shiftright_int16(y128[1],scale); - y128[2] = shiftright_int16(y128[2],scale); - y128[3] = shiftright_int16(y128[3],scale); - y128[4] = shiftright_int16(y128[4],scale); - y128[5] = shiftright_int16(y128[5],scale); - y128[6] = shiftright_int16(y128[6],scale); - y128[7] = shiftright_int16(y128[7],scale); - y128[8] = shiftright_int16(y128[8],scale); - y128[9] = shiftright_int16(y128[9],scale); - y128[10] = shiftright_int16(y128[10],scale); - y128[11] = shiftright_int16(y128[11],scale); - y128[12] = shiftright_int16(y128[12],scale); - y128[13] = shiftright_int16(y128[13],scale); - y128[14] = shiftright_int16(y128[14],scale); - y128[15] = shiftright_int16(y128[15],scale); - - y128+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -#else //__AVX2__ -void dft4096(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[512],ytmp[512],*tw4096_256p=(simd256_q15_t *)tw4096,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<512; i+=4,j++) { - transpose16_ooff_simd256(x256+i,xtmp+j,128); - } - - - dft1024((int16_t*)(xtmp),(int16_t*)(ytmp),1); - dft1024((int16_t*)(xtmp+128),(int16_t*)(ytmp+128),1); - dft1024((int16_t*)(xtmp+256),(int16_t*)(ytmp+256),1); - dft1024((int16_t*)(xtmp+384),(int16_t*)(ytmp+384),1); - - for (i=0; i<128; i++) { - bfly4_256(ytmpp,ytmpp+128,ytmpp+256,ytmpp+384, - y256p,y256p+128,y256p+256,y256p+384, - tw4096_256p,tw4096_256p+128,tw4096_256p+256); - tw4096_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<32; i++) { - y256[0] = shiftright_int16_simd256(y256[0],1); - y256[1] = shiftright_int16_simd256(y256[1],1); - y256[2] = shiftright_int16_simd256(y256[2],1); - y256[3] = shiftright_int16_simd256(y256[3],1); - y256[4] = shiftright_int16_simd256(y256[4],1); - y256[5] = shiftright_int16_simd256(y256[5],1); - y256[6] = shiftright_int16_simd256(y256[6],1); - y256[7] = shiftright_int16_simd256(y256[7],1); - y256[8] = shiftright_int16_simd256(y256[8],1); - y256[9] = shiftright_int16_simd256(y256[9],1); - y256[10] = shiftright_int16_simd256(y256[10],1); - y256[11] = shiftright_int16_simd256(y256[11],1); - y256[12] = shiftright_int16_simd256(y256[12],1); - y256[13] = shiftright_int16_simd256(y256[13],1); - y256[14] = shiftright_int16_simd256(y256[14],1); - y256[15] = shiftright_int16_simd256(y256[15],1); - - y256+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -void idft4096(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[512],ytmp[512],*tw4096_256p=(simd256_q15_t *)tw4096,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i,j; - - for (i=0,j=0; i<512; i+=4,j++) { - transpose16_ooff_simd256(x256+i,xtmp+j,128); - } - - - idft1024((int16_t*)(xtmp),(int16_t*)(ytmp),1); - idft1024((int16_t*)(xtmp+128),(int16_t*)(ytmp+128),1); - idft1024((int16_t*)(xtmp+256),(int16_t*)(ytmp+256),1); - idft1024((int16_t*)(xtmp+384),(int16_t*)(ytmp+384),1); - - for (i=0; i<128; i++) { - ibfly4_256(ytmpp,ytmpp+128,ytmpp+256,ytmpp+384, - y256p,y256p+128,y256p+256,y256p+384, - tw4096_256p,tw4096_256p+128,tw4096_256p+256); - tw4096_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - - for (i=0; i<32; i++) { - y256[0] = shiftright_int16_simd256(y256[0],1); - y256[1] = shiftright_int16_simd256(y256[1],1); - y256[2] = shiftright_int16_simd256(y256[2],1); - y256[3] = shiftright_int16_simd256(y256[3],1); - y256[4] = shiftright_int16_simd256(y256[4],1); - y256[5] = shiftright_int16_simd256(y256[5],1); - y256[6] = shiftright_int16_simd256(y256[6],1); - y256[7] = shiftright_int16_simd256(y256[7],1); - y256[8] = shiftright_int16_simd256(y256[8],1); - y256[9] = shiftright_int16_simd256(y256[9],1); - y256[10] = shiftright_int16_simd256(y256[10],1); - y256[11] = shiftright_int16_simd256(y256[11],1); - y256[12] = shiftright_int16_simd256(y256[12],1); - y256[13] = shiftright_int16_simd256(y256[13],1); - y256[14] = shiftright_int16_simd256(y256[14],1); - y256[15] = shiftright_int16_simd256(y256[15],1); - - y256+=16; - } - - } - - _mm_empty(); - _m_empty(); - -} - -#endif //__AVX2__ - - -int16_t tw8192[2*4096] __attribute__((aligned(32))); - -#ifndef __AVX2__ -void dft8192(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[4096],*xtmpp,*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[1024],*tw8192_128p=(simd_q15_t *)tw8192,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<64; i++) { - transpose4_ooff(x64 ,xtmpp,2048); - transpose4_ooff(x64+2,xtmpp+1,2048); - transpose4_ooff(x64+4,xtmpp+2,2048); - transpose4_ooff(x64+6,xtmpp+3,2048); - transpose4_ooff(x64+8,xtmpp+4,2048); - transpose4_ooff(x64+10,xtmpp+5,2048); - transpose4_ooff(x64+12,xtmpp+6,2048); - transpose4_ooff(x64+14,xtmpp+7,2048); - transpose4_ooff(x64+16,xtmpp+8,2048); - transpose4_ooff(x64+18,xtmpp+9,2048); - transpose4_ooff(x64+20,xtmpp+10,2048); - transpose4_ooff(x64+22,xtmpp+11,2048); - transpose4_ooff(x64+24,xtmpp+12,2048); - transpose4_ooff(x64+26,xtmpp+13,2048); - transpose4_ooff(x64+28,xtmpp+14,2048); - transpose4_ooff(x64+30,xtmpp+15,2048); - transpose4_ooff(x64+32,xtmpp+16,2048); - transpose4_ooff(x64+34,xtmpp+17,2048); - transpose4_ooff(x64+36,xtmpp+18,2048); - transpose4_ooff(x64+38,xtmpp+19,2048); - transpose4_ooff(x64+40,xtmpp+20,2048); - transpose4_ooff(x64+42,xtmpp+21,2048); - transpose4_ooff(x64+44,xtmpp+22,2048); - transpose4_ooff(x64+46,xtmpp+23,2048); - transpose4_ooff(x64+48,xtmpp+24,2048); - transpose4_ooff(x64+50,xtmpp+25,2048); - transpose4_ooff(x64+52,xtmpp+26,2048); - transpose4_ooff(x64+54,xtmpp+27,2048); - transpose4_ooff(x64+56,xtmpp+28,2048); - transpose4_ooff(x64+58,xtmpp+29,2048); - transpose4_ooff(x64+60,xtmpp+30,2048); - transpose4_ooff(x64+62,xtmpp+31,2048); - x64+=64; - xtmpp+=32; - } - - dft4096((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+1024),1); - - - for (i=0; i<1024; i++) { - bfly2(ytmpp,ytmpp+1024, - y128p,y128p+1024, - tw8192_128p); - tw8192_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - y128p = y128; - - for (i=0; i<128; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -void idft8192(int16_t *x,int16_t *y,int scale) -{ - - simdshort_q15_t xtmp[4096],*xtmpp,*x64 = (simdshort_q15_t *)x; - simd_q15_t ytmp[2048],*tw8192_128p=(simd_q15_t *)tw8192,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; - simd_q15_t *ytmpp = &ytmp[0]; - int i; - simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<64; i++) { - transpose4_ooff(x64 ,xtmpp,2048); - transpose4_ooff(x64+2,xtmpp+1,2048); - transpose4_ooff(x64+4,xtmpp+2,2048); - transpose4_ooff(x64+6,xtmpp+3,2048); - transpose4_ooff(x64+8,xtmpp+4,2048); - transpose4_ooff(x64+10,xtmpp+5,2048); - transpose4_ooff(x64+12,xtmpp+6,2048); - transpose4_ooff(x64+14,xtmpp+7,2048); - transpose4_ooff(x64+16,xtmpp+8,2048); - transpose4_ooff(x64+18,xtmpp+9,2048); - transpose4_ooff(x64+20,xtmpp+10,2048); - transpose4_ooff(x64+22,xtmpp+11,2048); - transpose4_ooff(x64+24,xtmpp+12,2048); - transpose4_ooff(x64+26,xtmpp+13,2048); - transpose4_ooff(x64+28,xtmpp+14,2048); - transpose4_ooff(x64+30,xtmpp+15,2048); - transpose4_ooff(x64+32,xtmpp+16,2048); - transpose4_ooff(x64+34,xtmpp+17,2048); - transpose4_ooff(x64+36,xtmpp+18,2048); - transpose4_ooff(x64+38,xtmpp+19,2048); - transpose4_ooff(x64+40,xtmpp+20,2048); - transpose4_ooff(x64+42,xtmpp+21,2048); - transpose4_ooff(x64+44,xtmpp+22,2048); - transpose4_ooff(x64+46,xtmpp+23,2048); - transpose4_ooff(x64+48,xtmpp+24,2048); - transpose4_ooff(x64+50,xtmpp+25,2048); - transpose4_ooff(x64+52,xtmpp+26,2048); - transpose4_ooff(x64+54,xtmpp+27,2048); - transpose4_ooff(x64+56,xtmpp+28,2048); - transpose4_ooff(x64+58,xtmpp+29,2048); - transpose4_ooff(x64+60,xtmpp+30,2048); - transpose4_ooff(x64+62,xtmpp+31,2048); - x64+=64; - xtmpp+=32; - } - - idft4096((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+1024),1); - - - for (i=0; i<1024; i++) { - ibfly2(ytmpp,ytmpp+1024, - y128p,y128p+1024, - tw8192_128p); - tw8192_128p++; - y128p++; - ytmpp++; - } - - if (scale>0) { - y128p = y128; - - for (i=0; i<128; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -#else // __AVX2__ -void dft8192(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[1024],*xtmpp,*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[1024],*tw8192_256p=(simd256_q15_t *)tw8192,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<16; i++) { - transpose4_ooff_simd256(x256 ,xtmpp,512); - transpose4_ooff_simd256(x256+2,xtmpp+1,512); - transpose4_ooff_simd256(x256+4,xtmpp+2,512); - transpose4_ooff_simd256(x256+6,xtmpp+3,512); - transpose4_ooff_simd256(x256+8,xtmpp+4,512); - transpose4_ooff_simd256(x256+10,xtmpp+5,512); - transpose4_ooff_simd256(x256+12,xtmpp+6,512); - transpose4_ooff_simd256(x256+14,xtmpp+7,512); - transpose4_ooff_simd256(x256+16,xtmpp+8,512); - transpose4_ooff_simd256(x256+18,xtmpp+9,512); - transpose4_ooff_simd256(x256+20,xtmpp+10,512); - transpose4_ooff_simd256(x256+22,xtmpp+11,512); - transpose4_ooff_simd256(x256+24,xtmpp+12,512); - transpose4_ooff_simd256(x256+26,xtmpp+13,512); - transpose4_ooff_simd256(x256+28,xtmpp+14,512); - transpose4_ooff_simd256(x256+30,xtmpp+15,512); - transpose4_ooff_simd256(x256+32,xtmpp+16,512); - transpose4_ooff_simd256(x256+34,xtmpp+17,512); - transpose4_ooff_simd256(x256+36,xtmpp+18,512); - transpose4_ooff_simd256(x256+38,xtmpp+19,512); - transpose4_ooff_simd256(x256+40,xtmpp+20,512); - transpose4_ooff_simd256(x256+42,xtmpp+21,512); - transpose4_ooff_simd256(x256+44,xtmpp+22,512); - transpose4_ooff_simd256(x256+46,xtmpp+23,512); - transpose4_ooff_simd256(x256+48,xtmpp+24,512); - transpose4_ooff_simd256(x256+50,xtmpp+25,512); - transpose4_ooff_simd256(x256+52,xtmpp+26,512); - transpose4_ooff_simd256(x256+54,xtmpp+27,512); - transpose4_ooff_simd256(x256+56,xtmpp+28,512); - transpose4_ooff_simd256(x256+58,xtmpp+29,512); - transpose4_ooff_simd256(x256+60,xtmpp+30,512); - transpose4_ooff_simd256(x256+62,xtmpp+31,512); - x256+=64; - xtmpp+=32; - } - - dft4096((int16_t*)(xtmp),(int16_t*)ytmp,1); - dft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); - - - for (i=0; i<512; i++) { - bfly2_256(ytmpp,ytmpp+512, - y256p,y256p+512, - tw8192_256p); - tw8192_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - y256p = y256; - - for (i=0; i<64; i++) { - y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); - y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); - y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); - y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); - y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); - y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); - y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); - y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); - y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); - y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); - y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); - y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); - y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); - y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); - y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); - y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); - y256p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -void idft8192(int16_t *x,int16_t *y,int scale) -{ - - simd256_q15_t xtmp[1024],*xtmpp,*x256 = (simd256_q15_t *)x; - simd256_q15_t ytmp[1024],*tw8192_256p=(simd256_q15_t *)tw8192,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; - simd256_q15_t *ytmpp = &ytmp[0]; - int i; - simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); - - xtmpp = xtmp; - - for (i=0; i<16; i++) { - transpose4_ooff_simd256(x256 ,xtmpp,512); - transpose4_ooff_simd256(x256+2,xtmpp+1,512); - transpose4_ooff_simd256(x256+4,xtmpp+2,512); - transpose4_ooff_simd256(x256+6,xtmpp+3,512); - transpose4_ooff_simd256(x256+8,xtmpp+4,512); - transpose4_ooff_simd256(x256+10,xtmpp+5,512); - transpose4_ooff_simd256(x256+12,xtmpp+6,512); - transpose4_ooff_simd256(x256+14,xtmpp+7,512); - transpose4_ooff_simd256(x256+16,xtmpp+8,512); - transpose4_ooff_simd256(x256+18,xtmpp+9,512); - transpose4_ooff_simd256(x256+20,xtmpp+10,512); - transpose4_ooff_simd256(x256+22,xtmpp+11,512); - transpose4_ooff_simd256(x256+24,xtmpp+12,512); - transpose4_ooff_simd256(x256+26,xtmpp+13,512); - transpose4_ooff_simd256(x256+28,xtmpp+14,512); - transpose4_ooff_simd256(x256+30,xtmpp+15,512); - transpose4_ooff_simd256(x256+32,xtmpp+16,512); - transpose4_ooff_simd256(x256+34,xtmpp+17,512); - transpose4_ooff_simd256(x256+36,xtmpp+18,512); - transpose4_ooff_simd256(x256+38,xtmpp+19,512); - transpose4_ooff_simd256(x256+40,xtmpp+20,512); - transpose4_ooff_simd256(x256+42,xtmpp+21,512); - transpose4_ooff_simd256(x256+44,xtmpp+22,512); - transpose4_ooff_simd256(x256+46,xtmpp+23,512); - transpose4_ooff_simd256(x256+48,xtmpp+24,512); - transpose4_ooff_simd256(x256+50,xtmpp+25,512); - transpose4_ooff_simd256(x256+52,xtmpp+26,512); - transpose4_ooff_simd256(x256+54,xtmpp+27,512); - transpose4_ooff_simd256(x256+56,xtmpp+28,512); - transpose4_ooff_simd256(x256+58,xtmpp+29,512); - transpose4_ooff_simd256(x256+60,xtmpp+30,512); - transpose4_ooff_simd256(x256+62,xtmpp+31,512); - x256+=64; - xtmpp+=32; - } - - idft4096((int16_t*)(xtmp),(int16_t*)ytmp,1); - idft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); - - - for (i=0; i<512; i++) { - ibfly2_256(ytmpp,ytmpp+512, - y256p,y256p+512, - tw8192_256p); - tw8192_256p++; - y256p++; - ytmpp++; - } - - if (scale>0) { - y256p = y256; - - for (i=0; i<64; i++) { - y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); - y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); - y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); - y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); - y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); - y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); - y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); - y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); - y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); - y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); - y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); - y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); - y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); - y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); - y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); - y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); - y256p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - - -#endif - -int16_t twa1536[1024],twb1536[1024]; - -// 512 x 3 -void idft1536(int16_t *input, int16_t *output, int scale) -{ - int i,i2,j; - uint32_t tmp[3][512 ]__attribute__((aligned(32))); - uint32_t tmpo[3][512] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<512; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - idft512((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - idft512((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - idft512((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - for (i=0,i2=0; i<1024; i+=8,i2+=4) { - ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+1024+i),(simd_q15_t*)(output+2048+i), - (simd_q15_t*)(twa1536+i),(simd_q15_t*)(twb1536+i)); - } - - - if (scale==1) { - for (i=0; i<24; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -void dft1536(int16_t *input, int16_t *output, int scale) -{ - int i,i2,j; - uint32_t tmp[3][512] __attribute__((aligned(32))); - uint32_t tmpo[3][512] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<512; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - dft512((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - dft512((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - dft512((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - /* - for (i=1; i<512; i++) { - tmpo[0][i] = tmpo[0][i<<1]; - tmpo[1][i] = tmpo[1][i<<1]; - tmpo[2][i] = tmpo[2][i<<1]; - }*/ - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft1536out0.m","o0",tmpo[0],2048,1,1); - LOG_M("dft1536out1.m","o1",tmpo[1],2048,1,1); - LOG_M("dft1536out2.m","o2",tmpo[2],2048,1,1); - } - for (i=0,i2=0; i<1024; i+=8,i2+=4) { - bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+1024+i),(simd_q15_t*)(output+2048+i), - (simd_q15_t*)(twa1536+i),(simd_q15_t*)(twb1536+i)); - } - - if (scale==1) { - for (i=0; i<24; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - -int16_t twa3072[2048] __attribute__((aligned(32))); -int16_t twb3072[2048] __attribute__((aligned(32))); -// 1024 x 3 -void dft3072(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][1024] __attribute__((aligned(32))); - uint32_t tmpo[3][1024] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<1024; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - dft1024((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - dft1024((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - dft1024((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - for (i=0,i2=0; i<2048; i+=8,i2+=4) { - bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+2048+i),(simd_q15_t*)(output+4096+i), - (simd_q15_t*)(twa3072+i),(simd_q15_t*)(twb3072+i)); - } - - if (scale==1) { - for (i=0; i<48; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); -} - -void idft3072(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][1024]__attribute__((aligned(32))); - uint32_t tmpo[3][1024] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<1024; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - idft1024((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - idft1024((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - idft1024((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - for (i=0,i2=0; i<2048; i+=8,i2+=4) { - ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+2048+i),(simd_q15_t*)(output+4096+i), - (simd_q15_t*)(twa3072+i),(simd_q15_t*)(twb3072+i)); - } - - - if (scale==1) { - for (i=0; i<48; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); -} - - -int16_t twa6144[4096] __attribute__((aligned(32))); -int16_t twb6144[4096] __attribute__((aligned(32))); - -void idft6144(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][2048] __attribute__((aligned(32))); - uint32_t tmpo[3][2048] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<2048; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - idft2048((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - idft2048((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - idft2048((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("idft6144in.m","in",input,6144,1,1); - LOG_M("idft6144out0.m","o0",tmpo[0],2048,1,1); - LOG_M("idft6144out1.m","o1",tmpo[1],2048,1,1); - LOG_M("idft6144out2.m","o2",tmpo[2],2048,1,1); - } - - for (i=0,i2=0; i<4096; i+=8,i2+=4) { - ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+4096+i),(simd_q15_t*)(output+8192+i), - (simd_q15_t*)(twa6144+i),(simd_q15_t*)(twb6144+i)); - } - - - if (scale==1) { - for (i=0; i<96; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - - _mm_empty(); - _m_empty(); - -} - - -void dft6144(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][2048] __attribute__((aligned(32))); - uint32_t tmpo[3][2048] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<2048; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - dft2048((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - dft2048((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - dft2048((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - /* - for (i=1; i<2048; i++) { - tmpo[0][i] = tmpo[0][i<<1]; - tmpo[1][i] = tmpo[1][i<<1]; - tmpo[2][i] = tmpo[2][i<<1]; - }*/ - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("ft6144out0.m","o0",tmpo[0],2048,1,1); - LOG_M("ft6144out1.m","o1",tmpo[1],2048,1,1); - LOG_M("ft6144out2.m","o2",tmpo[2],2048,1,1); - } - for (i=0,i2=0; i<4096; i+=8,i2+=4) { - bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+4096+i),(simd_q15_t*)(output+8192+i), - (simd_q15_t*)(twa6144+i),(simd_q15_t*)(twb6144+i)); - } - - if (scale==1) { - for (i=0; i<96; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); - -} - -int16_t twa9216[6144] __attribute__((aligned(32))); -int16_t twb9216[6144] __attribute__((aligned(32))); -// 3072 x 3 -void dft9216(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -void idft9216(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -int16_t twa12288[8192] __attribute__((aligned(32))); -int16_t twb12288[8192] __attribute__((aligned(32))); -// 4096 x 3 -void dft12288(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][4096] __attribute__((aligned(32))); - uint32_t tmpo[3][4096] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<4096; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - dft4096((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale); - dft4096((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale); - dft4096((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale); - /* - for (i=1; i<4096; i++) { - tmpo[0][i] = tmpo[0][i<<1]; - tmpo[1][i] = tmpo[1][i<<1]; - tmpo[2][i] = tmpo[2][i<<1]; - }*/ - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft12288out0.m","o0",tmpo[0],4096,1,1); - LOG_M("dft12288out1.m","o1",tmpo[1],4096,1,1); - LOG_M("dft12288out2.m","o2",tmpo[2],4096,1,1); - } - for (i=0,i2=0; i<8192; i+=8,i2+=4) { - bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+8192+i),(simd_q15_t*)(output+16384+i), - (simd_q15_t*)(twa12288+i),(simd_q15_t*)(twb12288+i)); - } - - if (scale==1) { - for (i=0; i<192; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); - -} - -void idft12288(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][4096] __attribute__((aligned(32))); - uint32_t tmpo[3][4096] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<4096; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - - - idft4096((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale); - idft4096((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale); - idft4096((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale); - - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("idft12288in.m","in",input,12288,1,1); - LOG_M("idft12288out0.m","o0",tmpo[0],4096,1,1); - LOG_M("idft12288out1.m","o1",tmpo[1],4096,1,1); - LOG_M("idft12288out2.m","o2",tmpo[2],4096,1,1); - } - - for (i=0,i2=0; i<8192; i+=8,i2+=4) { - ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+8192+i),(simd_q15_t*)(output+16384+i), - (simd_q15_t*)(twa12288+i),(simd_q15_t*)(twb12288+i)); - } - - if (scale==1) { - for (i=0; i<192; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("idft12288out.m","out",output,6144,1,1); - } -} - -int16_t twa18432[12288] __attribute__((aligned(32))); -int16_t twb18432[12288] __attribute__((aligned(32))); -// 6144 x 3 -void dft18432(int16_t *input, int16_t *output,int scale) { - - int i,i2,j; - uint32_t tmp[3][6144] __attribute__((aligned(32))); - uint32_t tmpo[3][6144] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<6144; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - dft6144((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale); - dft6144((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale); - dft6144((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale); - - for (i=0,i2=0; i<12288; i+=8,i2+=4) { - bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+12288+i),(simd_q15_t*)(output+24576+i), - (simd_q15_t*)(twa18432+i),(simd_q15_t*)(twb18432+i)); - } - if (scale==1) { - for (i=0; i<288; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); -} - -void idft18432(int16_t *input, int16_t *output,int scale) { - - int i,i2,j; - uint32_t tmp[3][6144] __attribute__((aligned(32))); - uint32_t tmpo[3][6144] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<6144; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - idft6144((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale); - idft6144((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale); - idft6144((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale); - - for (i=0,i2=0; i<12288; i+=8,i2+=4) { - ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+12288+i),(simd_q15_t*)(output+24576+i), - (simd_q15_t*)(twa18432+i),(simd_q15_t*)(twb18432+i)); - } - if (scale==1) { - for (i=0; i<288; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); -} - - -int16_t twa24576[16384] __attribute__((aligned(32))); -int16_t twb24576[16384] __attribute__((aligned(32))); -// 8192 x 3 -void dft24576(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][8192] __attribute__((aligned(32))); - uint32_t tmpo[3][8192] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<8192; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - dft8192((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - dft8192((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - dft8192((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - /* - for (i=1; i<8192; i++) { - tmpo[0][i] = tmpo[0][i<<1]; - tmpo[1][i] = tmpo[1][i<<1]; - tmpo[2][i] = tmpo[2][i<<1]; - }*/ - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("dft24576out0.m","o0",tmpo[0],8192,1,1); - LOG_M("dft24576out1.m","o1",tmpo[1],8192,1,1); - LOG_M("dft24576out2.m","o2",tmpo[2],8192,1,1); - } - for (i=0,i2=0; i<16384; i+=8,i2+=4) { - bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+16384+i),(simd_q15_t*)(output+32768+i), - (simd_q15_t*)(twa24576+i),(simd_q15_t*)(twb24576+i)); - } - - - if (scale==1) { - for (i=0; i<384; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("out.m","out",output,24576,1,1); - } -} - -void idft24576(int16_t *input, int16_t *output,int scale) -{ - int i,i2,j; - uint32_t tmp[3][8192] __attribute__((aligned(32))); - uint32_t tmpo[3][8192] __attribute__((aligned(32))); - simd_q15_t *y128p=(simd_q15_t*)output; - simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); - - for (i=0,j=0; i<8192; i++) { - tmp[0][i] = ((uint32_t *)input)[j++]; - tmp[1][i] = ((uint32_t *)input)[j++]; - tmp[2][i] = ((uint32_t *)input)[j++]; - } - - idft8192((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); - idft8192((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); - idft8192((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); - - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("idft24576in.m","in",input,24576,1,1); - LOG_M("idft24576out0.m","o0",tmpo[0],8192,1,1); - LOG_M("idft24576out1.m","o1",tmpo[1],8192,1,1); - LOG_M("idft24576out2.m","o2",tmpo[2],8192,1,1); - } - - for (i=0,i2=0; i<16384; i+=8,i2+=4) { - ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), - (simd_q15_t*)(output+i),(simd_q15_t*)(output+16384+i),(simd_q15_t*)(output+32768+i), - (simd_q15_t*)(twa24576+i),(simd_q15_t*)(twb24576+i)); - } - if (scale==1) { - for (i=0; i<384; i++) { - y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); - y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); - y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); - y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); - y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); - y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); - y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); - y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); - y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); - y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); - y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); - y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); - y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); - y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); - y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); - y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); - y128p+=16; - } - } - _mm_empty(); - _m_empty(); - - if (LOG_DUMPFLAG(DEBUG_DFT)) { - LOG_M("idft24576out.m","out",output,24576,1,1); - } -} - -int16_t twa36864[24576] __attribute__((aligned(32))); -int16_t twb36884[24576] __attribute__((aligned(32))); -// 12288 x 3 -void dft36864(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} -void idft36864(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -int16_t twa49152[32768] __attribute__((aligned(32))); -int16_t twb49152[32768] __attribute__((aligned(32))); -// 16384 x 3 -void dft49152(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -void idft49152(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -int16_t twa73728[49152] __attribute__((aligned(32))); -int16_t twb73728[49152] __attribute__((aligned(32))); -// 24576 x 3 -void dft73728(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -void idft73728(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - - -int16_t twa98304[49152] __attribute__((aligned(32))); -int16_t twb98304[49152] __attribute__((aligned(32))); -// 32768 x 3 -void dft98304(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - -void idft98304(int16_t *input, int16_t *output,int scale) { - - AssertFatal(1==0,"Need to do this ..\n"); -} - - -/// THIS SECTION IS FOR ALL PUSCH DFTS (i.e. radix 2^a * 3^b * 4^c * 5^d) -/// They use twiddles for 4-way parallel DFTS (i.e. 4 DFTS with interleaved input/output) - -static int16_t W1_12s[8]__attribute__((aligned(32))) = {28377,-16383,28377,-16383,28377,-16383,28377,-16383}; -static int16_t W2_12s[8]__attribute__((aligned(32))) = {16383,-28377,16383,-28377,16383,-28377,16383,-28377}; -static int16_t W3_12s[8]__attribute__((aligned(32))) = {0,-32767,0,-32767,0,-32767,0,-32767}; -static int16_t W4_12s[8]__attribute__((aligned(32))) = {-16383,-28377,-16383,-28377,-16383,-28377,-16383,-28377}; -static int16_t W6_12s[8]__attribute__((aligned(32))) = {-32767,0,-32767,0,-32767,0,-32767,0}; - -simd_q15_t *W1_12=(simd_q15_t *)W1_12s; -simd_q15_t *W2_12=(simd_q15_t *)W2_12s; -simd_q15_t *W3_12=(simd_q15_t *)W3_12s; -simd_q15_t *W4_12=(simd_q15_t *)W4_12s; -simd_q15_t *W6_12=(simd_q15_t *)W6_12s; - - -static simd_q15_t norm128; - -static inline void dft12f(simd_q15_t *x0, - simd_q15_t *x1, - simd_q15_t *x2, - simd_q15_t *x3, - simd_q15_t *x4, - simd_q15_t *x5, - simd_q15_t *x6, - simd_q15_t *x7, - simd_q15_t *x8, - simd_q15_t *x9, - simd_q15_t *x10, - simd_q15_t *x11, - simd_q15_t *y0, - simd_q15_t *y1, - simd_q15_t *y2, - simd_q15_t *y3, - simd_q15_t *y4, - simd_q15_t *y5, - simd_q15_t *y6, - simd_q15_t *y7, - simd_q15_t *y8, - simd_q15_t *y9, - simd_q15_t *y10, - simd_q15_t *y11) __attribute__((always_inline)); - -static inline void dft12f(simd_q15_t *x0, - simd_q15_t *x1, - simd_q15_t *x2, - simd_q15_t *x3, - simd_q15_t *x4, - simd_q15_t *x5, - simd_q15_t *x6, - simd_q15_t *x7, - simd_q15_t *x8, - simd_q15_t *x9, - simd_q15_t *x10, - simd_q15_t *x11, - simd_q15_t *y0, - simd_q15_t *y1, - simd_q15_t *y2, - simd_q15_t *y3, - simd_q15_t *y4, - simd_q15_t *y5, - simd_q15_t *y6, - simd_q15_t *y7, - simd_q15_t *y8, - simd_q15_t *y9, - simd_q15_t *y10, - simd_q15_t *y11) -{ - - - simd_q15_t tmp_dft12[12]; - - simd_q15_t *tmp_dft12_ptr = &tmp_dft12[0]; - - // msg("dft12\n"); - - bfly4_tw1(x0, - x3, - x6, - x9, - tmp_dft12_ptr, - tmp_dft12_ptr+3, - tmp_dft12_ptr+6, - tmp_dft12_ptr+9); - - - bfly4_tw1(x1, - x4, - x7, - x10, - tmp_dft12_ptr+1, - tmp_dft12_ptr+4, - tmp_dft12_ptr+7, - tmp_dft12_ptr+10); - - - bfly4_tw1(x2, - x5, - x8, - x11, - tmp_dft12_ptr+2, - tmp_dft12_ptr+5, - tmp_dft12_ptr+8, - tmp_dft12_ptr+11); - - // k2=0; - bfly3_tw1(tmp_dft12_ptr, - tmp_dft12_ptr+1, - tmp_dft12_ptr+2, - y0, - y4, - y8); - - - - // k2=1; - bfly3(tmp_dft12_ptr+3, - tmp_dft12_ptr+4, - tmp_dft12_ptr+5, - y1, - y5, - y9, - W1_12, - W2_12); - - - - // k2=2; - bfly3(tmp_dft12_ptr+6, - tmp_dft12_ptr+7, - tmp_dft12_ptr+8, - y2, - y6, - y10, - W2_12, - W4_12); - - // k2=3; - bfly3(tmp_dft12_ptr+9, - tmp_dft12_ptr+10, - tmp_dft12_ptr+11, - y3, - y7, - y11, - W3_12, - W6_12); - -} - - - - -void dft12(int16_t *x,int16_t *y) -{ - - simd_q15_t *x128 = (simd_q15_t *)x,*y128 = (simd_q15_t *)y; - dft12f(&x128[0], - &x128[1], - &x128[2], - &x128[3], - &x128[4], - &x128[5], - &x128[6], - &x128[7], - &x128[8], - &x128[9], - &x128[10], - &x128[11], - &y128[0], - &y128[1], - &y128[2], - &y128[3], - &y128[4], - &y128[5], - &y128[6], - &y128[7], - &y128[8], - &y128[9], - &y128[10], - &y128[11]); - - _mm_empty(); - _m_empty(); - -} - -#ifdef __AVX2__ - -static int16_t W1_12s_256[16]__attribute__((aligned(32))) = {28377,-16383,28377,-16383,28377,-16383,28377,-16383,28377,-16383,28377,-16383,28377,-16383,28377,-16383}; -static int16_t W2_12s_256[16]__attribute__((aligned(32))) = {16383,-28377,16383,-28377,16383,-28377,16383,-28377,16383,-28377,16383,-28377,16383,-28377,16383,-28377}; -static int16_t W3_12s_256[16]__attribute__((aligned(32))) = {0,-32767,0,-32767,0,-32767,0,-32767,0,-32767,0,-32767,0,-32767,0,-32767}; -static int16_t W4_12s_256[16]__attribute__((aligned(32))) = {-16383,-28377,-16383,-28377,-16383,-28377,-16383,-28377,-16383,-28377,-16383,-28377,-16383,-28377,-16383,-28377}; -static int16_t W6_12s_256[16]__attribute__((aligned(32))) = {-32767,0,-32767,0,-32767,0,-32767,0,-32767,0,-32767,0,-32767,0,-32767,0}; - -simd256_q15_t *W1_12_256=(simd256_q15_t *)W1_12s_256; -simd256_q15_t *W2_12_256=(simd256_q15_t *)W2_12s_256; -simd256_q15_t *W3_12_256=(simd256_q15_t *)W3_12s_256; -simd256_q15_t *W4_12_256=(simd256_q15_t *)W4_12s_256; -simd256_q15_t *W6_12_256=(simd256_q15_t *)W6_12s_256; - - - -static inline void dft12f_simd256(simd256_q15_t *x0, - simd256_q15_t *x1, - simd256_q15_t *x2, - simd256_q15_t *x3, - simd256_q15_t *x4, - simd256_q15_t *x5, - simd256_q15_t *x6, - simd256_q15_t *x7, - simd256_q15_t *x8, - simd256_q15_t *x9, - simd256_q15_t *x10, - simd256_q15_t *x11, - simd256_q15_t *y0, - simd256_q15_t *y1, - simd256_q15_t *y2, - simd256_q15_t *y3, - simd256_q15_t *y4, - simd256_q15_t *y5, - simd256_q15_t *y6, - simd256_q15_t *y7, - simd256_q15_t *y8, - simd256_q15_t *y9, - simd256_q15_t *y10, - simd256_q15_t *y11) __attribute__((always_inline)); - -static inline void dft12f_simd256(simd256_q15_t *x0, - simd256_q15_t *x1, - simd256_q15_t *x2, - simd256_q15_t *x3, - simd256_q15_t *x4, - simd256_q15_t *x5, - simd256_q15_t *x6, - simd256_q15_t *x7, - simd256_q15_t *x8, - simd256_q15_t *x9, - simd256_q15_t *x10, - simd256_q15_t *x11, - simd256_q15_t *y0, - simd256_q15_t *y1, - simd256_q15_t *y2, - simd256_q15_t *y3, - simd256_q15_t *y4, - simd256_q15_t *y5, - simd256_q15_t *y6, - simd256_q15_t *y7, - simd256_q15_t *y8, - simd256_q15_t *y9, - simd256_q15_t *y10, - simd256_q15_t *y11) -{ - - - simd256_q15_t tmp_dft12[12]; - - simd256_q15_t *tmp_dft12_ptr = &tmp_dft12[0]; - - // msg("dft12\n"); - - bfly4_tw1_256(x0, - x3, - x6, - x9, - tmp_dft12_ptr, - tmp_dft12_ptr+3, - tmp_dft12_ptr+6, - tmp_dft12_ptr+9); - - - bfly4_tw1_256(x1, - x4, - x7, - x10, - tmp_dft12_ptr+1, - tmp_dft12_ptr+4, - tmp_dft12_ptr+7, - tmp_dft12_ptr+10); - - - bfly4_tw1_256(x2, - x5, - x8, - x11, - tmp_dft12_ptr+2, - tmp_dft12_ptr+5, - tmp_dft12_ptr+8, - tmp_dft12_ptr+11); - - // k2=0; - bfly3_tw1_256(tmp_dft12_ptr, - tmp_dft12_ptr+1, - tmp_dft12_ptr+2, - y0, - y4, - y8); - - - - // k2=1; - bfly3_256(tmp_dft12_ptr+3, - tmp_dft12_ptr+4, - tmp_dft12_ptr+5, - y1, - y5, - y9, - W1_12_256, - W2_12_256); - - - - // k2=2; - bfly3_256(tmp_dft12_ptr+6, - tmp_dft12_ptr+7, - tmp_dft12_ptr+8, - y2, - y6, - y10, - W2_12_256, - W4_12_256); - - // k2=3; - bfly3_256(tmp_dft12_ptr+9, - tmp_dft12_ptr+10, - tmp_dft12_ptr+11, - y3, - y7, - y11, - W3_12_256, - W6_12_256); - -} - - - - -void dft12_simd256(int16_t *x,int16_t *y) -{ - - simd256_q15_t *x256 = (simd256_q15_t *)x,*y256 = (simd256_q15_t *)y; - dft12f_simd256(&x256[0], - &x256[1], - &x256[2], - &x256[3], - &x256[4], - &x256[5], - &x256[6], - &x256[7], - &x256[8], - &x256[9], - &x256[10], - &x256[11], - &y256[0], - &y256[1], - &y256[2], - &y256[3], - &y256[4], - &y256[5], - &y256[6], - &y256[7], - &y256[8], - &y256[9], - &y256[10], - &y256[11]); - - _mm_empty(); - _m_empty(); - -} - -#endif - -static int16_t tw24[88]__attribute__((aligned(32))); - -void dft24(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *tw128=(simd_q15_t *)&tw24[0]; - simd_q15_t ytmp128[24];//=&ytmp128array[0]; - int i,j,k; - - // msg("dft24\n"); - dft12f(x128, - x128+2, - x128+4, - x128+6, - x128+8, - x128+10, - x128+12, - x128+14, - x128+16, - x128+18, - x128+20, - x128+22, - ytmp128, - ytmp128+2, - ytmp128+4, - ytmp128+6, - ytmp128+8, - ytmp128+10, - ytmp128+12, - ytmp128+14, - ytmp128+16, - ytmp128+18, - ytmp128+20, - ytmp128+22); - // msg("dft24b\n"); - - dft12f(x128+1, - x128+3, - x128+5, - x128+7, - x128+9, - x128+11, - x128+13, - x128+15, - x128+17, - x128+19, - x128+21, - x128+23, - ytmp128+1, - ytmp128+3, - ytmp128+5, - ytmp128+7, - ytmp128+9, - ytmp128+11, - ytmp128+13, - ytmp128+15, - ytmp128+17, - ytmp128+19, - ytmp128+21, - ytmp128+23); - - // msg("dft24c\n"); - - bfly2_tw1(ytmp128, - ytmp128+1, - y128, - y128+12); - - // msg("dft24d\n"); - - for (i=2,j=1,k=0; i<24; i+=2,j++,k++) { - - bfly2(ytmp128+i, - ytmp128+i+1, - y128+j, - y128+j+12, - tw128+k); - // msg("dft24e\n"); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[1]); - - for (i=0; i<24; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa36[88]__attribute__((aligned(32))); -static int16_t twb36[88]__attribute__((aligned(32))); - -void dft36(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa36[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb36[0]; - simd_q15_t ytmp128[36];//&ytmp128array[0]; - - - int i,j,k; - - dft12f(x128, - x128+3, - x128+6, - x128+9, - x128+12, - x128+15, - x128+18, - x128+21, - x128+24, - x128+27, - x128+30, - x128+33, - ytmp128, - ytmp128+3, - ytmp128+6, - ytmp128+9, - ytmp128+12, - ytmp128+15, - ytmp128+18, - ytmp128+21, - ytmp128+24, - ytmp128+27, - ytmp128+30, - ytmp128+33); - - dft12f(x128+1, - x128+4, - x128+7, - x128+10, - x128+13, - x128+16, - x128+19, - x128+22, - x128+25, - x128+28, - x128+31, - x128+34, - ytmp128+1, - ytmp128+4, - ytmp128+7, - ytmp128+10, - ytmp128+13, - ytmp128+16, - ytmp128+19, - ytmp128+22, - ytmp128+25, - ytmp128+28, - ytmp128+31, - ytmp128+34); - - dft12f(x128+2, - x128+5, - x128+8, - x128+11, - x128+14, - x128+17, - x128+20, - x128+23, - x128+26, - x128+29, - x128+32, - x128+35, - ytmp128+2, - ytmp128+5, - ytmp128+8, - ytmp128+11, - ytmp128+14, - ytmp128+17, - ytmp128+20, - ytmp128+23, - ytmp128+26, - ytmp128+29, - ytmp128+32, - ytmp128+35); - - - bfly3_tw1(ytmp128, - ytmp128+1, - ytmp128+2, - y128, - y128+12, - y128+24); - - for (i=3,j=1,k=0; i<36; i+=3,j++,k++) { - - bfly3(ytmp128+i, - ytmp128+i+1, - ytmp128+i+2, - y128+j, - y128+j+12, - y128+j+24, - twa128+k, - twb128+k); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[2]); - - for (i=0; i<36; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa48[88]__attribute__((aligned(32))); -static int16_t twb48[88]__attribute__((aligned(32))); -static int16_t twc48[88]__attribute__((aligned(32))); - -void dft48(int16_t *x, int16_t *y,unsigned char scale_flag) -{ - - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa48[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb48[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc48[0]; - simd_q15_t ytmp128[48];//=&ytmp128array[0]; - int i,j,k; - - - dft12f(x128, - x128+4, - x128+8, - x128+12, - x128+16, - x128+20, - x128+24, - x128+28, - x128+32, - x128+36, - x128+40, - x128+44, - ytmp128, - ytmp128+4, - ytmp128+8, - ytmp128+12, - ytmp128+16, - ytmp128+20, - ytmp128+24, - ytmp128+28, - ytmp128+32, - ytmp128+36, - ytmp128+40, - ytmp128+44); - - - dft12f(x128+1, - x128+5, - x128+9, - x128+13, - x128+17, - x128+21, - x128+25, - x128+29, - x128+33, - x128+37, - x128+41, - x128+45, - ytmp128+1, - ytmp128+5, - ytmp128+9, - ytmp128+13, - ytmp128+17, - ytmp128+21, - ytmp128+25, - ytmp128+29, - ytmp128+33, - ytmp128+37, - ytmp128+41, - ytmp128+45); - - - dft12f(x128+2, - x128+6, - x128+10, - x128+14, - x128+18, - x128+22, - x128+26, - x128+30, - x128+34, - x128+38, - x128+42, - x128+46, - ytmp128+2, - ytmp128+6, - ytmp128+10, - ytmp128+14, - ytmp128+18, - ytmp128+22, - ytmp128+26, - ytmp128+30, - ytmp128+34, - ytmp128+38, - ytmp128+42, - ytmp128+46); - - - dft12f(x128+3, - x128+7, - x128+11, - x128+15, - x128+19, - x128+23, - x128+27, - x128+31, - x128+35, - x128+39, - x128+43, - x128+47, - ytmp128+3, - ytmp128+7, - ytmp128+11, - ytmp128+15, - ytmp128+19, - ytmp128+23, - ytmp128+27, - ytmp128+31, - ytmp128+35, - ytmp128+39, - ytmp128+43, - ytmp128+47); - - - - bfly4_tw1(ytmp128, - ytmp128+1, - ytmp128+2, - ytmp128+3, - y128, - y128+12, - y128+24, - y128+36); - - - - for (i=4,j=1,k=0; i<48; i+=4,j++,k++) { - - bfly4(ytmp128+i, - ytmp128+i+1, - ytmp128+i+2, - ytmp128+i+3, - y128+j, - y128+j+12, - y128+j+24, - y128+j+36, - twa128+k, - twb128+k, - twc128+k); - - } - - if (scale_flag == 1) { - norm128 = set1_int16(dft_norm_table[3]); - - for (i=0; i<48; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa60[88]__attribute__((aligned(32))); -static int16_t twb60[88]__attribute__((aligned(32))); -static int16_t twc60[88]__attribute__((aligned(32))); -static int16_t twd60[88]__attribute__((aligned(32))); - -void dft60(int16_t *x,int16_t *y,unsigned char scale) -{ - - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa60[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb60[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc60[0]; - simd_q15_t *twd128=(simd_q15_t *)&twd60[0]; - simd_q15_t ytmp128[60];//=&ytmp128array[0]; - int i,j,k; - - dft12f(x128, - x128+5, - x128+10, - x128+15, - x128+20, - x128+25, - x128+30, - x128+35, - x128+40, - x128+45, - x128+50, - x128+55, - ytmp128, - ytmp128+5, - ytmp128+10, - ytmp128+15, - ytmp128+20, - ytmp128+25, - ytmp128+30, - ytmp128+35, - ytmp128+40, - ytmp128+45, - ytmp128+50, - ytmp128+55); - - dft12f(x128+1, - x128+6, - x128+11, - x128+16, - x128+21, - x128+26, - x128+31, - x128+36, - x128+41, - x128+46, - x128+51, - x128+56, - ytmp128+1, - ytmp128+6, - ytmp128+11, - ytmp128+16, - ytmp128+21, - ytmp128+26, - ytmp128+31, - ytmp128+36, - ytmp128+41, - ytmp128+46, - ytmp128+51, - ytmp128+56); - - dft12f(x128+2, - x128+7, - x128+12, - x128+17, - x128+22, - x128+27, - x128+32, - x128+37, - x128+42, - x128+47, - x128+52, - x128+57, - ytmp128+2, - ytmp128+7, - ytmp128+12, - ytmp128+17, - ytmp128+22, - ytmp128+27, - ytmp128+32, - ytmp128+37, - ytmp128+42, - ytmp128+47, - ytmp128+52, - ytmp128+57); - - dft12f(x128+3, - x128+8, - x128+13, - x128+18, - x128+23, - x128+28, - x128+33, - x128+38, - x128+43, - x128+48, - x128+53, - x128+58, - ytmp128+3, - ytmp128+8, - ytmp128+13, - ytmp128+18, - ytmp128+23, - ytmp128+28, - ytmp128+33, - ytmp128+38, - ytmp128+43, - ytmp128+48, - ytmp128+53, - ytmp128+58); - - dft12f(x128+4, - x128+9, - x128+14, - x128+19, - x128+24, - x128+29, - x128+34, - x128+39, - x128+44, - x128+49, - x128+54, - x128+59, - ytmp128+4, - ytmp128+9, - ytmp128+14, - ytmp128+19, - ytmp128+24, - ytmp128+29, - ytmp128+34, - ytmp128+39, - ytmp128+44, - ytmp128+49, - ytmp128+54, - ytmp128+59); - - bfly5_tw1(ytmp128, - ytmp128+1, - ytmp128+2, - ytmp128+3, - ytmp128+4, - y128, - y128+12, - y128+24, - y128+36, - y128+48); - - for (i=5,j=1,k=0; i<60; i+=5,j++,k++) { - - bfly5(ytmp128+i, - ytmp128+i+1, - ytmp128+i+2, - ytmp128+i+3, - ytmp128+i+4, - y128+j, - y128+j+12, - y128+j+24, - y128+j+36, - y128+j+48, - twa128+k, - twb128+k, - twc128+k, - twd128+k); - } - - if (scale == 1) { - norm128 = set1_int16(dft_norm_table[4]); - - for (i=0; i<60; i++) { - y128[i] = mulhi_int16(y128[i],norm128); -// printf("y[%d] = (%d,%d)\n",i,((int16_t*)&y128[i])[0],((int16_t*)&y128[i])[1]); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t tw72[280]__attribute__((aligned(32))); - -void dft72(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *tw128=(simd_q15_t *)&tw72[0]; - simd_q15_t x2128[72];// = (simd_q15_t *)&x2128array[0]; - - simd_q15_t ytmp128[72];//=&ytmp128array2[0]; - - for (i=0,j=0; i<36; i++,j+=2) { - x2128[i] = x128[j]; // even inputs - x2128[i+36] = x128[j+1]; // odd inputs - } - - dft36((int16_t *)x2128,(int16_t *)ytmp128,1); - dft36((int16_t *)(x2128+36),(int16_t *)(ytmp128+36),1); - - bfly2_tw1(ytmp128,ytmp128+36,y128,y128+36); - - for (i=1,j=0; i<36; i++,j++) { - bfly2(ytmp128+i, - ytmp128+36+i, - y128+i, - y128+36+i, - tw128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[5]); - - for (i=0; i<72; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t tw96[376]__attribute__((aligned(32))); - -void dft96(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *tw128=(simd_q15_t *)&tw96[0]; - simd_q15_t x2128[96];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[96];//=&ytmp128array2[0]; - - - for (i=0,j=0; i<48; i++,j+=2) { - x2128[i] = x128[j]; - x2128[i+48] = x128[j+1]; - } - - dft48((int16_t *)x2128,(int16_t *)ytmp128,0); - dft48((int16_t *)(x2128+48),(int16_t *)(ytmp128+48),0); - - - bfly2_tw1(ytmp128,ytmp128+48,y128,y128+48); - - for (i=1,j=0; i<48; i++,j++) { - bfly2(ytmp128+i, - ytmp128+48+i, - y128+i, - y128+48+i, - tw128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[6]); - - for (i=0; i<96; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa108[280]__attribute__((aligned(32))); -static int16_t twb108[280]__attribute__((aligned(32))); - -void dft108(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa108[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb108[0]; - simd_q15_t x2128[108];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[108];//=&ytmp128array2[0]; - - - for (i=0,j=0; i<36; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+36] = x128[j+1]; - x2128[i+72] = x128[j+2]; - } - - dft36((int16_t *)x2128,(int16_t *)ytmp128,0); - dft36((int16_t *)(x2128+36),(int16_t *)(ytmp128+36),0); - dft36((int16_t *)(x2128+72),(int16_t *)(ytmp128+72),0); - - bfly3_tw1(ytmp128,ytmp128+36,ytmp128+72,y128,y128+36,y128+72); - - for (i=1,j=0; i<36; i++,j++) { - bfly3(ytmp128+i, - ytmp128+36+i, - ytmp128+72+i, - y128+i, - y128+36+i, - y128+72+i, - twa128+j, - twb128+j); - - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[7]); - - for (i=0; i<108; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t tw120[472]__attribute__((aligned(32))); -void dft120(int16_t *x,int16_t *y, unsigned char scale_flag) -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *tw128=(simd_q15_t *)&tw120[0]; - simd_q15_t x2128[120];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[120];//=&ytmp128array2[0]; - - for (i=0,j=0; i<60; i++,j+=2) { - x2128[i] = x128[j]; - x2128[i+60] = x128[j+1]; - } - - dft60((int16_t *)x2128,(int16_t *)ytmp128,0); - dft60((int16_t *)(x2128+60),(int16_t *)(ytmp128+60),0); - - - bfly2_tw1(ytmp128,ytmp128+60,y128,y128+60); - - for (i=1,j=0; i<60; i++,j++) { - bfly2(ytmp128+i, - ytmp128+60+i, - y128+i, - y128+60+i, - tw128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[8]); - - for (i=0; i<120; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa144[376]__attribute__((aligned(32))); -static int16_t twb144[376]__attribute__((aligned(32))); - -void dft144(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa144[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb144[0]; - simd_q15_t x2128[144];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[144];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<48; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+48] = x128[j+1]; - x2128[i+96] = x128[j+2]; - } - - dft48((int16_t *)x2128,(int16_t *)ytmp128,1); - dft48((int16_t *)(x2128+48),(int16_t *)(ytmp128+48),1); - dft48((int16_t *)(x2128+96),(int16_t *)(ytmp128+96),1); - - bfly3_tw1(ytmp128,ytmp128+48,ytmp128+96,y128,y128+48,y128+96); - - for (i=1,j=0; i<48; i++,j++) { - bfly3(ytmp128+i, - ytmp128+48+i, - ytmp128+96+i, - y128+i, - y128+48+i, - y128+96+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[9]); - - for (i=0; i<144; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa180[472]__attribute__((aligned(32))); -static int16_t twb180[472]__attribute__((aligned(32))); - -void dft180(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa180[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb180[0]; - simd_q15_t x2128[180];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[180];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<60; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+60] = x128[j+1]; - x2128[i+120] = x128[j+2]; - } - - dft60((int16_t *)x2128,(int16_t *)ytmp128,1); - dft60((int16_t *)(x2128+60),(int16_t *)(ytmp128+60),1); - dft60((int16_t *)(x2128+120),(int16_t *)(ytmp128+120),1); - - bfly3_tw1(ytmp128,ytmp128+60,ytmp128+120,y128,y128+60,y128+120); - - for (i=1,j=0; i<60; i++,j++) { - bfly3(ytmp128+i, - ytmp128+60+i, - ytmp128+120+i, - y128+i, - y128+60+i, - y128+120+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[10]); - - for (i=0; i<180; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa192[376]__attribute__((aligned(32))); -static int16_t twb192[376]__attribute__((aligned(32))); -static int16_t twc192[376]__attribute__((aligned(32))); - -void dft192(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa192[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb192[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc192[0]; - simd_q15_t x2128[192];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[192];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<48; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+48] = x128[j+1]; - x2128[i+96] = x128[j+2]; - x2128[i+144] = x128[j+3]; - } - - dft48((int16_t *)x2128,(int16_t *)ytmp128,1); - dft48((int16_t *)(x2128+48),(int16_t *)(ytmp128+48),1); - dft48((int16_t *)(x2128+96),(int16_t *)(ytmp128+96),1); - dft48((int16_t *)(x2128+144),(int16_t *)(ytmp128+144),1); - - bfly4_tw1(ytmp128,ytmp128+48,ytmp128+96,ytmp128+144,y128,y128+48,y128+96,y128+144); - - for (i=1,j=0; i<48; i++,j++) { - bfly4(ytmp128+i, - ytmp128+48+i, - ytmp128+96+i, - ytmp128+144+i, - y128+i, - y128+48+i, - y128+96+i, - y128+144+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[11]); - - for (i=0; i<192; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa216[568]__attribute__((aligned(32))); -static int16_t twb216[568]__attribute__((aligned(32))); - -void dft216(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa216[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb216[0]; - simd_q15_t x2128[216];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[216];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<72; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+72] = x128[j+1]; - x2128[i+144] = x128[j+2]; - } - - dft72((int16_t *)x2128,(int16_t *)ytmp128,1); - dft72((int16_t *)(x2128+72),(int16_t *)(ytmp128+72),1); - dft72((int16_t *)(x2128+144),(int16_t *)(ytmp128+144),1); - - bfly3_tw1(ytmp128,ytmp128+72,ytmp128+144,y128,y128+72,y128+144); - - for (i=1,j=0; i<72; i++,j++) { - bfly3(ytmp128+i, - ytmp128+72+i, - ytmp128+144+i, - y128+i, - y128+72+i, - y128+144+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[12]); - - for (i=0; i<216; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa240[472]__attribute__((aligned(32))); -static int16_t twb240[472]__attribute__((aligned(32))); -static int16_t twc240[472]__attribute__((aligned(32))); - -void dft240(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa240[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb240[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc240[0]; - simd_q15_t x2128[240];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[240];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<60; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+60] = x128[j+1]; - x2128[i+120] = x128[j+2]; - x2128[i+180] = x128[j+3]; - } - - dft60((int16_t *)x2128,(int16_t *)ytmp128,1); - dft60((int16_t *)(x2128+60),(int16_t *)(ytmp128+60),1); - dft60((int16_t *)(x2128+120),(int16_t *)(ytmp128+120),1); - dft60((int16_t *)(x2128+180),(int16_t *)(ytmp128+180),1); - - bfly4_tw1(ytmp128,ytmp128+60,ytmp128+120,ytmp128+180,y128,y128+60,y128+120,y128+180); - - for (i=1,j=0; i<60; i++,j++) { - bfly4(ytmp128+i, - ytmp128+60+i, - ytmp128+120+i, - ytmp128+180+i, - y128+i, - y128+60+i, - y128+120+i, - y128+180+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[13]); - - for (i=0; i<240; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa288[760]__attribute__((aligned(32))); -static int16_t twb288[760]__attribute__((aligned(32))); - -void dft288(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa288[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb288[0]; - simd_q15_t x2128[288];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[288];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<96; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+96] = x128[j+1]; - x2128[i+192] = x128[j+2]; - } - - dft96((int16_t *)x2128,(int16_t *)ytmp128,1); - dft96((int16_t *)(x2128+96),(int16_t *)(ytmp128+96),1); - dft96((int16_t *)(x2128+192),(int16_t *)(ytmp128+192),1); - - bfly3_tw1(ytmp128,ytmp128+96,ytmp128+192,y128,y128+96,y128+192); - - for (i=1,j=0; i<96; i++,j++) { - bfly3(ytmp128+i, - ytmp128+96+i, - ytmp128+192+i, - y128+i, - y128+96+i, - y128+192+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<288; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa300[472]__attribute__((aligned(32))); -static int16_t twb300[472]__attribute__((aligned(32))); -static int16_t twc300[472]__attribute__((aligned(32))); -static int16_t twd300[472]__attribute__((aligned(32))); - -void dft300(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa300[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb300[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc300[0]; - simd_q15_t *twd128=(simd_q15_t *)&twd300[0]; - simd_q15_t x2128[300];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[300];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<60; i++,j+=5) { - x2128[i] = x128[j]; - x2128[i+60] = x128[j+1]; - x2128[i+120] = x128[j+2]; - x2128[i+180] = x128[j+3]; - x2128[i+240] = x128[j+4]; - } - - dft60((int16_t *)x2128,(int16_t *)ytmp128,1); - dft60((int16_t *)(x2128+60),(int16_t *)(ytmp128+60),1); - dft60((int16_t *)(x2128+120),(int16_t *)(ytmp128+120),1); - dft60((int16_t *)(x2128+180),(int16_t *)(ytmp128+180),1); - dft60((int16_t *)(x2128+240),(int16_t *)(ytmp128+240),1); - - bfly5_tw1(ytmp128,ytmp128+60,ytmp128+120,ytmp128+180,ytmp128+240,y128,y128+60,y128+120,y128+180,y128+240); - - for (i=1,j=0; i<60; i++,j++) { - bfly5(ytmp128+i, - ytmp128+60+i, - ytmp128+120+i, - ytmp128+180+i, - ytmp128+240+i, - y128+i, - y128+60+i, - y128+120+i, - y128+180+i, - y128+240+i, - twa128+j, - twb128+j, - twc128+j, - twd128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[15]); - - for (i=0; i<300; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -static int16_t twa324[107*2*4]; -static int16_t twb324[107*2*4]; - -void dft324(int16_t *x,int16_t *y,unsigned char scale_flag) // 108 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa324[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb324[0]; - simd_q15_t x2128[324];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[324];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<108; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+108] = x128[j+1]; - x2128[i+216] = x128[j+2]; - } - - dft108((int16_t *)x2128,(int16_t *)ytmp128,1); - dft108((int16_t *)(x2128+108),(int16_t *)(ytmp128+108),1); - dft108((int16_t *)(x2128+216),(int16_t *)(ytmp128+216),1); - - bfly3_tw1(ytmp128,ytmp128+108,ytmp128+216,y128,y128+108,y128+216); - - for (i=1,j=0; i<108; i++,j++) { - bfly3(ytmp128+i, - ytmp128+108+i, - ytmp128+216+i, - y128+i, - y128+108+i, - y128+216+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<324; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa360[119*2*4]; -static int16_t twb360[119*2*4]; - -void dft360(int16_t *x,int16_t *y,unsigned char scale_flag) // 120 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa360[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb360[0]; - simd_q15_t x2128[360];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[360];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<120; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+120] = x128[j+1]; - x2128[i+240] = x128[j+2]; - } - - dft120((int16_t *)x2128,(int16_t *)ytmp128,1); - dft120((int16_t *)(x2128+120),(int16_t *)(ytmp128+120),1); - dft120((int16_t *)(x2128+240),(int16_t *)(ytmp128+240),1); - - bfly3_tw1(ytmp128,ytmp128+120,ytmp128+240,y128,y128+120,y128+240); - - for (i=1,j=0; i<120; i++,j++) { - bfly3(ytmp128+i, - ytmp128+120+i, - ytmp128+240+i, - y128+i, - y128+120+i, - y128+240+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<360; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa384[95*2*4]; -static int16_t twb384[95*2*4]; -static int16_t twc384[95*2*4]; - -void dft384(int16_t *x,int16_t *y,unsigned char scale_flag) // 96 x 4 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa384[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb384[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc384[0]; - simd_q15_t x2128[384];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[384];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<96; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+96] = x128[j+1]; - x2128[i+192] = x128[j+2]; - x2128[i+288] = x128[j+3]; - } - - dft96((int16_t *)x2128,(int16_t *)ytmp128,1); - dft96((int16_t *)(x2128+96),(int16_t *)(ytmp128+96),1); - dft96((int16_t *)(x2128+192),(int16_t *)(ytmp128+192),1); - dft96((int16_t *)(x2128+288),(int16_t *)(ytmp128+288),1); - - bfly4_tw1(ytmp128,ytmp128+96,ytmp128+192,ytmp128+288,y128,y128+96,y128+192,y128+288); - - for (i=1,j=0; i<96; i++,j++) { - bfly4(ytmp128+i, - ytmp128+96+i, - ytmp128+192+i, - ytmp128+288+i, - y128+i, - y128+96+i, - y128+192+i, - y128+288+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<384; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa432[107*2*4]; -static int16_t twb432[107*2*4]; -static int16_t twc432[107*2*4]; - -void dft432(int16_t *x,int16_t *y,unsigned char scale_flag) // 108 x 4 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa432[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb432[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc432[0]; - simd_q15_t x2128[432];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[432];//=&ytmp128array2[0]; - - - for (i=0,j=0; i<108; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+108] = x128[j+1]; - x2128[i+216] = x128[j+2]; - x2128[i+324] = x128[j+3]; - } - - dft108((int16_t *)x2128,(int16_t *)ytmp128,1); - dft108((int16_t *)(x2128+108),(int16_t *)(ytmp128+108),1); - dft108((int16_t *)(x2128+216),(int16_t *)(ytmp128+216),1); - dft108((int16_t *)(x2128+324),(int16_t *)(ytmp128+324),1); - - bfly4_tw1(ytmp128,ytmp128+108,ytmp128+216,ytmp128+324,y128,y128+108,y128+216,y128+324); - - for (i=1,j=0; i<108; i++,j++) { - bfly4(ytmp128+i, - ytmp128+108+i, - ytmp128+216+i, - ytmp128+324+i, - y128+i, - y128+108+i, - y128+216+i, - y128+324+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<432; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; -static int16_t twa480[119*2*4]; -static int16_t twb480[119*2*4]; -static int16_t twc480[119*2*4]; - -void dft480(int16_t *x,int16_t *y,unsigned char scale_flag) // 120 x 4 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa480[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb480[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc480[0]; - simd_q15_t x2128[480];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[480];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<120; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+120] = x128[j+1]; - x2128[i+240] = x128[j+2]; - x2128[i+360] = x128[j+3]; - } - - dft120((int16_t *)x2128,(int16_t *)ytmp128,1); - dft120((int16_t *)(x2128+120),(int16_t *)(ytmp128+120),1); - dft120((int16_t *)(x2128+240),(int16_t *)(ytmp128+240),1); - dft120((int16_t *)(x2128+360),(int16_t *)(ytmp128+360),1); - - bfly4_tw1(ytmp128,ytmp128+120,ytmp128+240,ytmp128+360,y128,y128+120,y128+240,y128+360); - - for (i=1,j=0; i<120; i++,j++) { - bfly4(ytmp128+i, - ytmp128+120+i, - ytmp128+240+i, - ytmp128+360+i, - y128+i, - y128+120+i, - y128+240+i, - y128+360+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<480; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - - -static int16_t twa540[179*2*4]; -static int16_t twb540[179*2*4]; - -void dft540(int16_t *x,int16_t *y,unsigned char scale_flag) // 180 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa540[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb540[0]; - simd_q15_t x2128[540];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[540];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<180; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+180] = x128[j+1]; - x2128[i+360] = x128[j+2]; - } - - dft180((int16_t *)x2128,(int16_t *)ytmp128,1); - dft180((int16_t *)(x2128+180),(int16_t *)(ytmp128+180),1); - dft180((int16_t *)(x2128+360),(int16_t *)(ytmp128+360),1); - - bfly3_tw1(ytmp128,ytmp128+180,ytmp128+360,y128,y128+180,y128+360); - - for (i=1,j=0; i<180; i++,j++) { - bfly3(ytmp128+i, - ytmp128+180+i, - ytmp128+360+i, - y128+i, - y128+180+i, - y128+360+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<540; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa576[191*2*4]; -static int16_t twb576[191*2*4]; - -void dft576(int16_t *x,int16_t *y,unsigned char scale_flag) // 192 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa576[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb576[0]; - simd_q15_t x2128[576];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[576];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<192; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+192] = x128[j+1]; - x2128[i+384] = x128[j+2]; - } - - - dft192((int16_t *)x2128,(int16_t *)ytmp128,1); - dft192((int16_t *)(x2128+192),(int16_t *)(ytmp128+192),1); - dft192((int16_t *)(x2128+384),(int16_t *)(ytmp128+384),1); - - bfly3_tw1(ytmp128,ytmp128+192,ytmp128+384,y128,y128+192,y128+384); - - for (i=1,j=0; i<192; i++,j++) { - bfly3(ytmp128+i, - ytmp128+192+i, - ytmp128+384+i, - y128+i, - y128+192+i, - y128+384+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<576; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); -}; - - -static int16_t twa600[299*2*4]; - -void dft600(int16_t *x,int16_t *y,unsigned char scale_flag) // 300 x 2 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *tw128=(simd_q15_t *)&twa600[0]; - simd_q15_t x2128[600];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[600];//=&ytmp128array2[0]; - - - for (i=0,j=0; i<300; i++,j+=2) { - x2128[i] = x128[j]; - x2128[i+300] = x128[j+1]; - } - - dft300((int16_t *)x2128,(int16_t *)ytmp128,1); - dft300((int16_t *)(x2128+300),(int16_t *)(ytmp128+300),1); - - - bfly2_tw1(ytmp128,ytmp128+300,y128,y128+300); - - for (i=1,j=0; i<300; i++,j++) { - bfly2(ytmp128+i, - ytmp128+300+i, - y128+i, - y128+300+i, - tw128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(ONE_OVER_SQRT2_Q15); - - for (i=0; i<600; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); -}; - - -static int16_t twa648[215*2*4]; -static int16_t twb648[215*2*4]; - -void dft648(int16_t *x,int16_t *y,unsigned char scale_flag) // 216 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa648[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb648[0]; - simd_q15_t x2128[648];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[648];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<216; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+216] = x128[j+1]; - x2128[i+432] = x128[j+2]; - } - - dft216((int16_t *)x2128,(int16_t *)ytmp128,1); - dft216((int16_t *)(x2128+216),(int16_t *)(ytmp128+216),1); - dft216((int16_t *)(x2128+432),(int16_t *)(ytmp128+432),1); - - bfly3_tw1(ytmp128,ytmp128+216,ytmp128+432,y128,y128+216,y128+432); - - for (i=1,j=0; i<216; i++,j++) { - bfly3(ytmp128+i, - ytmp128+216+i, - ytmp128+432+i, - y128+i, - y128+216+i, - y128+432+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<648; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - - -static int16_t twa720[179*2*4]; -static int16_t twb720[179*2*4]; -static int16_t twc720[179*2*4]; - - -void dft720(int16_t *x,int16_t *y,unsigned char scale_flag) // 180 x 4 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa720[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb720[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc720[0]; - simd_q15_t x2128[720];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[720];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<180; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+180] = x128[j+1]; - x2128[i+360] = x128[j+2]; - x2128[i+540] = x128[j+3]; - } - - dft180((int16_t *)x2128,(int16_t *)ytmp128,1); - dft180((int16_t *)(x2128+180),(int16_t *)(ytmp128+180),1); - dft180((int16_t *)(x2128+360),(int16_t *)(ytmp128+360),1); - dft180((int16_t *)(x2128+540),(int16_t *)(ytmp128+540),1); - - bfly4_tw1(ytmp128,ytmp128+180,ytmp128+360,ytmp128+540,y128,y128+180,y128+360,y128+540); - - for (i=1,j=0; i<180; i++,j++) { - bfly4(ytmp128+i, - ytmp128+180+i, - ytmp128+360+i, - ytmp128+540+i, - y128+i, - y128+180+i, - y128+360+i, - y128+540+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<720; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa768[191*2*4]; -static int16_t twb768[191*2*4]; -static int16_t twc768[191*2*4]; - -void dft768(int16_t *x,int16_t *y,unsigned char scale_flag) { // 192x 4; - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa768[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb768[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc768[0]; - simd_q15_t x2128[768];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[768];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<192; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+192] = x128[j+1]; - x2128[i+384] = x128[j+2]; - x2128[i+576] = x128[j+3]; - } - - dft192((int16_t *)x2128,(int16_t *)ytmp128,1); - dft192((int16_t *)(x2128+192),(int16_t *)(ytmp128+192),1); - dft192((int16_t *)(x2128+384),(int16_t *)(ytmp128+384),1); - dft192((int16_t *)(x2128+576),(int16_t *)(ytmp128+576),1); - - bfly4_tw1(ytmp128,ytmp128+192,ytmp128+384,ytmp128+576,y128,y128+192,y128+384,y128+576); - - for (i=1,j=0; i<192; i++,j++) { - bfly4(ytmp128+i, - ytmp128+192+i, - ytmp128+384+i, - ytmp128+576+i, - y128+i, - y128+192+i, - y128+384+i, - y128+576+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<768; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - - -} - - -static int16_t twa864[287*2*4]; -static int16_t twb864[287*2*4]; - -void dft864(int16_t *x,int16_t *y,unsigned char scale_flag) // 288 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa864[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb864[0]; - simd_q15_t x2128[864];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[864];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<288; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+288] = x128[j+1]; - x2128[i+576] = x128[j+2]; - } - - dft288((int16_t *)x2128,(int16_t *)ytmp128,1); - dft288((int16_t *)(x2128+288),(int16_t *)(ytmp128+288),1); - dft288((int16_t *)(x2128+576),(int16_t *)(ytmp128+576),1); - - bfly3_tw1(ytmp128,ytmp128+288,ytmp128+576,y128,y128+288,y128+576); - - for (i=1,j=0; i<288; i++,j++) { - bfly3(ytmp128+i, - ytmp128+288+i, - ytmp128+576+i, - y128+i, - y128+288+i, - y128+576+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<864; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa900[299*2*4]; -static int16_t twb900[299*2*4]; - -void dft900(int16_t *x,int16_t *y,unsigned char scale_flag) // 300 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa900[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb900[0]; - simd_q15_t x2128[900];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[900];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<300; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+300] = x128[j+1]; - x2128[i+600] = x128[j+2]; - } - - dft300((int16_t *)x2128,(int16_t *)ytmp128,1); - dft300((int16_t *)(x2128+300),(int16_t *)(ytmp128+300),1); - dft300((int16_t *)(x2128+600),(int16_t *)(ytmp128+600),1); - - bfly3_tw1(ytmp128,ytmp128+300,ytmp128+600,y128,y128+300,y128+600); - - for (i=1,j=0; i<300; i++,j++) { - bfly3(ytmp128+i, - ytmp128+300+i, - ytmp128+600+i, - y128+i, - y128+300+i, - y128+600+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<900; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - - -static int16_t twa960[239*2*4]; -static int16_t twb960[239*2*4]; -static int16_t twc960[239*2*4]; - - -void dft960(int16_t *x,int16_t *y,unsigned char scale_flag) // 240 x 4 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa960[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb960[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc960[0]; - simd_q15_t x2128[960];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[960];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<240; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+240] = x128[j+1]; - x2128[i+480] = x128[j+2]; - x2128[i+720] = x128[j+3]; - } - - dft240((int16_t *)x2128,(int16_t *)ytmp128,1); - dft240((int16_t *)(x2128+240),(int16_t *)(ytmp128+240),1); - dft240((int16_t *)(x2128+480),(int16_t *)(ytmp128+480),1); - dft240((int16_t *)(x2128+720),(int16_t *)(ytmp128+720),1); - - bfly4_tw1(ytmp128,ytmp128+240,ytmp128+480,ytmp128+720,y128,y128+240,y128+480,y128+720); - - for (i=1,j=0; i<240; i++,j++) { - bfly4(ytmp128+i, - ytmp128+240+i, - ytmp128+480+i, - ytmp128+720+i, - y128+i, - y128+240+i, - y128+480+i, - y128+720+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<960; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - - -static int16_t twa972[323*2*4]; -static int16_t twb972[323*2*4]; - -void dft972(int16_t *x,int16_t *y,unsigned char scale_flag) // 324 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa972[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb972[0]; - simd_q15_t x2128[972];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[972];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<324; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+324] = x128[j+1]; - x2128[i+648] = x128[j+2]; - } - - dft324((int16_t *)x2128,(int16_t *)ytmp128,1); - dft324((int16_t *)(x2128+324),(int16_t *)(ytmp128+324),1); - dft324((int16_t *)(x2128+648),(int16_t *)(ytmp128+648),1); - - bfly3_tw1(ytmp128,ytmp128+324,ytmp128+648,y128,y128+324,y128+648); - - for (i=1,j=0; i<324; i++,j++) { - bfly3(ytmp128+i, - ytmp128+324+i, - ytmp128+648+i, - y128+i, - y128+324+i, - y128+648+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<972; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa1080[359*2*4]; -static int16_t twb1080[359*2*4]; - -void dft1080(int16_t *x,int16_t *y,unsigned char scale_flag) // 360 x 3 -{ - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa1080[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb1080[0]; - simd_q15_t x2128[1080];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[1080];//=&ytmp128array3[0]; - - - - for (i=0,j=0; i<360; i++,j+=3) { - x2128[i] = x128[j]; - x2128[i+360] = x128[j+1]; - x2128[i+720] = x128[j+2]; - } - - dft360((int16_t *)x2128,(int16_t *)ytmp128,1); - dft360((int16_t *)(x2128+360),(int16_t *)(ytmp128+360),1); - dft360((int16_t *)(x2128+720),(int16_t *)(ytmp128+720),1); - - bfly3_tw1(ytmp128,ytmp128+360,ytmp128+720,y128,y128+360,y128+720); - - for (i=1,j=0; i<360; i++,j++) { - bfly3(ytmp128+i, - ytmp128+360+i, - ytmp128+720+i, - y128+i, - y128+360+i, - y128+720+i, - twa128+j, - twb128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(dft_norm_table[14]); - - for (i=0; i<1080; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -}; - -static int16_t twa1152[287*2*4]; -static int16_t twb1152[287*2*4]; -static int16_t twc1152[287*2*4]; - -void dft1152(int16_t *x,int16_t *y,unsigned char scale_flag) // 288 x 4 -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa1152[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb1152[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc1152[0]; - simd_q15_t x2128[1152];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[1152];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<288; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+288] = x128[j+1]; - x2128[i+576] = x128[j+2]; - x2128[i+864] = x128[j+3]; - } - - dft288((int16_t *)x2128,(int16_t *)ytmp128,1); - dft288((int16_t *)(x2128+288),(int16_t *)(ytmp128+288),1); - dft288((int16_t *)(x2128+576),(int16_t *)(ytmp128+576),1); - dft288((int16_t *)(x2128+864),(int16_t *)(ytmp128+864),1); - - bfly4_tw1(ytmp128,ytmp128+288,ytmp128+576,ytmp128+864,y128,y128+288,y128+576,y128+864); - - for (i=1,j=0; i<288; i++,j++) { - bfly4(ytmp128+i, - ytmp128+288+i, - ytmp128+576+i, - ytmp128+864+i, - y128+i, - y128+288+i, - y128+576+i, - y128+864+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - - for (i=0; i<1152; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); -}; - -int16_t twa1200[4784]; -int16_t twb1200[4784]; -int16_t twc1200[4784]; - -void dft1200(int16_t *x,int16_t *y,unsigned char scale_flag) -{ - - int i,j; - simd_q15_t *x128=(simd_q15_t *)x; - simd_q15_t *y128=(simd_q15_t *)y; - simd_q15_t *twa128=(simd_q15_t *)&twa1200[0]; - simd_q15_t *twb128=(simd_q15_t *)&twb1200[0]; - simd_q15_t *twc128=(simd_q15_t *)&twc1200[0]; - simd_q15_t x2128[1200];// = (simd_q15_t *)&x2128array[0]; - simd_q15_t ytmp128[1200];//=&ytmp128array2[0]; - - - - for (i=0,j=0; i<300; i++,j+=4) { - x2128[i] = x128[j]; - x2128[i+300] = x128[j+1]; - x2128[i+600] = x128[j+2]; - x2128[i+900] = x128[j+3]; - } - - dft300((int16_t *)x2128,(int16_t *)ytmp128,1); - dft300((int16_t *)(x2128+300),(int16_t *)(ytmp128+300),1); - dft300((int16_t *)(x2128+600),(int16_t *)(ytmp128+600),1); - dft300((int16_t *)(x2128+900),(int16_t *)(ytmp128+900),1); - - bfly4_tw1(ytmp128,ytmp128+300,ytmp128+600,ytmp128+900,y128,y128+300,y128+600,y128+900); - - for (i=1,j=0; i<300; i++,j++) { - bfly4(ytmp128+i, - ytmp128+300+i, - ytmp128+600+i, - ytmp128+900+i, - y128+i, - y128+300+i, - y128+600+i, - y128+900+i, - twa128+j, - twb128+j, - twc128+j); - } - - if (scale_flag==1) { - norm128 = set1_int16(16384);//dft_norm_table[13]); - for (i=0; i<1200; i++) { - y128[i] = mulhi_int16(y128[i],norm128); - } - } - - _mm_empty(); - _m_empty(); - -} - -//#define round trunc - -void init_rad4(int N,int16_t *tw) { - - int16_t *twa = tw; - int16_t *twb = twa+(N/2); - int16_t *twc = twb+(N/2); - int i; - - for (i=0;i<(N/4);i++) { - *twa = (int16_t)round(32767.0*cos(2*M_PI*i/N)); twa++; - *twa = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); twa++; - *twb = (int16_t)round(32767.0*cos(2*M_PI*2*i/N)); twb++; - *twb = -(int16_t)round(32767.0*sin(2*M_PI*2*i/N)); twb++; - *twc = (int16_t)round(32767.0*cos(2*M_PI*3*i/N)); twc++; - *twc = -(int16_t)round(32767.0*sin(2*M_PI*3*i/N)); twc++; - } -} -void init_rad4_rep(int N,int16_t *twa,int16_t *twb,int16_t *twc) { - - int i,j; - - for (i=1;i<(N/4);i++) { - twa[0] = (int16_t)round(32767.0*cos(2*M_PI*i/N)); - twa[1] = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); - twb[0] = (int16_t)round(32767.0*cos(2*M_PI*2*i/N)); - twb[1] = -(int16_t)round(32767.0*sin(2*M_PI*2*i/N)); - twc[0] = (int16_t)round(32767.0*cos(2*M_PI*3*i/N)); - twc[1] = -(int16_t)round(32767.0*sin(2*M_PI*3*i/N)); - for (j=1;j<4;j++) { - ((int32_t*)twa)[j]=((int32_t*)twa)[0]; - ((int32_t*)twb)[j]=((int32_t*)twb)[0]; - ((int32_t*)twc)[j]=((int32_t*)twc)[0]; - } - twa+=8; - twb+=8; - twc+=8; - } -} - -void init_rad2(int N,int16_t *tw) { - - int16_t *twa = tw; - int i; - - for (i=0;i<(N>>1);i++) { - *twa = (int16_t)round(32767.0*cos(2*M_PI*i/N)); twa++; - *twa = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); twa++; - } -} - -void init_rad2_rep(int N,int16_t *twa) { - - int i,j; - - for (i=1;i<(N/2);i++) { - twa[0] = (int16_t)round(32767.0*cos(2*M_PI*i/N)); - twa[1] = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); - for (j=1;j<4;j++) { - ((int32_t*)twa)[j]=((int32_t*)twa)[0]; - } - twa+=8; - } -} - -void init_rad3(int N,int16_t *twa,int16_t *twb) { - - int i; - - for (i=0;i<(N/3);i++) { - *twa = (int16_t)round(32767.0*cos(2*M_PI*i/N)); twa++; - *twa = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); twa++; - *twb = (int16_t)round(32767.0*cos(2*M_PI*2*i/N)); twb++; - *twb = -(int16_t)round(32767.0*sin(2*M_PI*2*i/N)); twb++; - } -} - -void init_rad3_rep(int N,int16_t *twa,int16_t *twb) { - - int i,j; - - for (i=1;i<(N/3);i++) { - twa[0] = (int16_t)round(32767.0*cos(2*M_PI*i/N)); - twa[1] = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); - twb[0] = (int16_t)round(32767.0*cos(2*M_PI*2*i/N)); - twb[1] = -(int16_t)round(32767.0*sin(2*M_PI*2*i/N)); - for (j=1;j<4;j++) { - ((int32_t*)twa)[j]=((int32_t*)twa)[0]; - ((int32_t*)twb)[j]=((int32_t*)twb)[0]; - } - twa+=8; - twb+=8; - } -} - -void init_rad5_rep(int N,int16_t *twa,int16_t *twb,int16_t *twc,int16_t *twd) { - - int i,j; - - for (i=1;i<(N/5);i++) { - twa[0] = (int16_t)round(32767.0*cos(2*M_PI*i/N)); - twa[1] = -(int16_t)round(32767.0*sin(2*M_PI*i/N)); - twb[0] = (int16_t)round(32767.0*cos(2*M_PI*2*i/N)); - twb[1] = -(int16_t)round(32767.0*sin(2*M_PI*2*i/N)); - twc[0] = (int16_t)round(32767.0*cos(2*M_PI*3*i/N)); - twc[1] = -(int16_t)round(32767.0*sin(2*M_PI*3*i/N)); - twd[0] = (int16_t)round(32767.0*cos(2*M_PI*4*i/N)); - twd[1] = -(int16_t)round(32767.0*sin(2*M_PI*4*i/N)); - for (j=1;j<4;j++) { - ((int32_t*)twa)[j]=((int32_t*)twa)[0]; - ((int32_t*)twb)[j]=((int32_t*)twb)[0]; - ((int32_t*)twc)[j]=((int32_t*)twc)[0]; - ((int32_t*)twd)[j]=((int32_t*)twd)[0]; - } - twa+=8; - twb+=8; - twc+=8; - twd+=8; - } -} - - -void init_dfts(void) -{ - init_rad4(1024,tw1024); - init_rad2(2048,tw2048); - init_rad4(4096,tw4096); - init_rad2(8192,tw8192); - - init_rad3(1536,twa1536,twb1536); - init_rad3(3072,twa3072,twb3072); - init_rad3(6144,twa6144,twb6144); - init_rad3(12288,twa12288,twb12288); - init_rad3(18432,twa18432,twb18432); - init_rad3(24576,twa24576,twb24576); - - init_rad2_rep(24,tw24); - init_rad3_rep(36,twa36,twb36); - init_rad4_rep(48,twa48,twb48,twc48); - init_rad5_rep(60,twa60,twb60,twc60,twd60); - init_rad2_rep(72,tw72); - init_rad2_rep(96,tw96); - init_rad3_rep(108,twa108,twb108); - init_rad2_rep(120,tw120); - init_rad3_rep(144,twa144,twb144); - init_rad3_rep(180,twa180,twb180); - init_rad4_rep(192,twa192,twb192,twc192); - init_rad3_rep(216,twa216,twb216); - init_rad4_rep(240,twa240,twb240,twc240); - init_rad3_rep(288,twa288,twb288); - init_rad5_rep(300,twa300,twb300,twc300,twd300); - init_rad3_rep(324,twa324,twb324); - init_rad3_rep(360,twa360,twb360); - init_rad4_rep(384,twa384,twb384,twc384); - init_rad4_rep(432,twa432,twb432,twc432); - init_rad4_rep(480,twa480,twb480,twc480); - init_rad3_rep(540,twa540,twb540); - init_rad3_rep(576,twa576,twb576); - init_rad2_rep(600,twa600); - init_rad3_rep(648,twa648,twb648); - init_rad4_rep(720,twa720,twb720,twc720); - init_rad4_rep(768,twa768,twb768,twc768); - init_rad3_rep(864,twa864,twb864); - init_rad3_rep(900,twa900,twb900); - init_rad4_rep(960,twa960,twb960,twc960); - init_rad3_rep(972,twa972,twb972); - init_rad3_rep(1080,twa1080,twb1080); - init_rad4_rep(1152,twa1152,twb1152,twc1152); - init_rad4_rep(1200,twa1200,twb1200,twc1200); -} - -//#undef round - -#ifdef MR_MAIN -#include -#include - -#define LOG_M write_output -int write_output(const char *fname,const char *vname,void *data,int length,int dec,char format) -{ - - FILE *fp=NULL; - int i; - - - printf("Writing %d elements of type %d to %s\n",length,format,fname); - - - if (format == 10 || format ==11 || format == 12 || format == 13 || format == 14) { - fp = fopen(fname,"a+"); - } else if (format != 10 && format !=11 && format != 12 && format != 13 && format != 14) { - fp = fopen(fname,"w+"); - } - - - - if (fp== NULL) { - printf("[OPENAIR][FILE OUTPUT] Cannot open file %s\n",fname); - return(-1); - } - - if (format != 10 && format !=11 && format != 12 && format != 13 && format != 14) - fprintf(fp,"%s = [",vname); - - - switch (format) { - case 0: // real 16-bit - - for (i=0; i 0)) - fprintf(fp,"%d + j*(%d),",((short *)data)[i],((short *)data)[i+1]); - else if (i == 2*(length-1)) - fprintf(fp,"%d + j*(%d);",((short *)data)[i],((short *)data)[i+1]); - else if (i == 0) - fprintf(fp,"\n%d + j*(%d),",((short *)data)[i],((short *)data)[i+1]); - - - - } - - break; - - case 11 : //case eren 16 bit real for channel magnitudes: - for (i=0; i 0)) - fprintf(fp,"%d,",((short *)data)[i]); - else if (i == (length-1)) - fprintf(fp,"%d;",((short *)data)[i]); - else if (i == 0) - fprintf(fp,"\n%d,",((short *)data)[i]); - } - - printf("\n erennnnnnnnnnnnnnn: length :%d",length); - break; - - case 12 : // case eren for log2_maxh real unsigned 8 bit - fprintf(fp,"%d \n",((unsigned char *)&data)[0]); - break; - - } - - if (format != 10 && format !=11 && format !=12 && format != 13 && format != 15) { - fprintf(fp,"];\n"); - fclose(fp); - return(0); - } else if (format == 10 || format ==11 || format == 12 || format == 13 || format == 15) { - fclose(fp); - return(0); - } - - return 0; -} - - -int main(int argc, char**argv) -{ - - - time_stats_t ts; -#ifdef __AVX2__ - simd256_q15_t x[4096],x2[4096],y[4096],tw0,tw1,tw2,tw3; -#else - simd_q15_t x[8192],x2[8192],y[8192],tw0,tw1,tw2,tw3; -#endif - int i; - simd_q15_t *x128=(simd_q15_t*)x,*y128=(simd_q15_t*)y; - - init_dfts(); - - set_taus_seed(0); - opp_enabled = 1; - /* - ((int16_t *)&tw0)[0] = 32767; - ((int16_t *)&tw0)[1] = 0; - ((int16_t *)&tw0)[2] = 32767; - ((int16_t *)&tw0)[3] = 0; - ((int16_t *)&tw0)[4] = 32767; - ((int16_t *)&tw0)[5] = 0; - ((int16_t *)&tw0)[6] = 32767; - ((int16_t *)&tw0)[7] = 0; - - ((int16_t *)&tw1)[0] = 32767; - ((int16_t *)&tw1)[1] = 0; - ((int16_t *)&tw1)[2] = 32767; - ((int16_t *)&tw1)[3] = 0; - ((int16_t *)&tw1)[4] = 32767; - ((int16_t *)&tw1)[5] = 0; - ((int16_t *)&tw1)[6] = 32767; - ((int16_t *)&tw1)[7] = 0; - - ((int16_t *)&tw2)[0] = 32767; - ((int16_t *)&tw2)[1] = 0; - ((int16_t *)&tw2)[2] = 32767; - ((int16_t *)&tw2)[3] = 0; - ((int16_t *)&tw2)[4] = 32767; - ((int16_t *)&tw2)[5] = 0; - ((int16_t *)&tw2)[6] = 32767; - ((int16_t *)&tw2)[7] = 0; - - ((int16_t *)&tw3)[0] = 32767; - ((int16_t *)&tw3)[1] = 0; - ((int16_t *)&tw3)[2] = 32767; - ((int16_t *)&tw3)[3] = 0; - ((int16_t *)&tw3)[4] = 32767; - ((int16_t *)&tw3)[5] = 0; - ((int16_t *)&tw3)[6] = 32767; - ((int16_t *)&tw3)[7] = 0; - */ - for (i=0;i<300;i++) { -#if defined(__x86_64__) || defined(__i386__) -#ifndef __AVX2__ - x[i] = _mm_set1_epi32(taus()); - x[i] = _mm_srai_epi16(x[i],4); -#else - x[i] = _mm256_set1_epi32(taus()); - x[i] = _mm256_srai_epi16(x[i],4); -#endif -#elif defined(__arm__) - x[i] = (int16x8_t)vdupq_n_s32(taus()); - x[i] = vshrq_n_s16(x[i],4); -#endif - } - /* - bfly2_tw1(x,x+1,y,y+1); - printf("(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[0],((int16_t*)&y[0])[1],((int16_t*)&y[1])[0],((int16_t*)&y[1])[1]); - printf("(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[2],((int16_t*)&y[0])[3],((int16_t*)&y[1])[2],((int16_t*)&y[1])[3]); - printf("(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[4],((int16_t*)&y[0])[5],((int16_t*)&y[1])[4],((int16_t*)&y[1])[5]); - printf("(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[6],((int16_t*)&y[0])[7],((int16_t*)&y[1])[6],((int16_t*)&y[1])[7]); - bfly2(x,x+1,y,y+1, &tw0); - printf("0(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[0],((int16_t*)&y[0])[1],((int16_t*)&y[1])[0],((int16_t*)&y[1])[1]); - printf("1(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[2],((int16_t*)&y[0])[3],((int16_t*)&y[1])[2],((int16_t*)&y[1])[3]); - printf("2(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[4],((int16_t*)&y[0])[5],((int16_t*)&y[1])[4],((int16_t*)&y[1])[5]); - printf("3(%d,%d) (%d,%d) => (%d,%d) (%d,%d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&y[0])[6],((int16_t*)&y[0])[7],((int16_t*)&y[1])[6],((int16_t*)&y[1])[7]); - bfly2(x,x+1,y,y+1, &tw0); - - bfly3_tw1(x,x+1,x+2,y, y+1,y+2); - printf("0(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[0],((int16_t*)&y[0])[1],((int16_t*)&y[1])[0],((int16_t*)&y[1])[1],((int16_t*)&y[2])[0],((int16_t*)&y[2])[1]); - printf("1(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[2],((int16_t*)&y[0])[3],((int16_t*)&y[1])[2],((int16_t*)&y[1])[3],((int16_t*)&y[2])[2],((int16_t*)&y[2])[3]); - printf("2(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[4],((int16_t*)&y[0])[5],((int16_t*)&y[1])[4],((int16_t*)&y[1])[5],((int16_t*)&y[2])[4],((int16_t*)&y[2])[5]); - printf("3(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[6],((int16_t*)&y[0])[7],((int16_t*)&y[1])[6],((int16_t*)&y[1])[7],((int16_t*)&y[2])[6],((int16_t*)&y[2])[7]); - bfly3(x,x+1,x+2,y, y+1,y+2,&tw0,&tw1); - - printf("0(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[0],((int16_t*)&y[0])[1],((int16_t*)&y[1])[0],((int16_t*)&y[1])[1],((int16_t*)&y[2])[0],((int16_t*)&y[2])[1]); - printf("1(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[2],((int16_t*)&y[0])[3],((int16_t*)&y[1])[2],((int16_t*)&y[1])[3],((int16_t*)&y[2])[2],((int16_t*)&y[2])[3]); - printf("2(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[4],((int16_t*)&y[0])[5],((int16_t*)&y[1])[4],((int16_t*)&y[1])[5],((int16_t*)&y[2])[4],((int16_t*)&y[2])[5]); - printf("3(%d,%d) (%d,%d) (%d %d) => (%d,%d) (%d,%d) (%d %d)\n",((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1],((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&y[0])[6],((int16_t*)&y[0])[7],((int16_t*)&y[1])[6],((int16_t*)&y[1])[7],((int16_t*)&y[2])[6],((int16_t*)&y[2])[7]); - - - bfly4_tw1(x,x+1,x+2,x+3,y, y+1,y+2,y+3); - printf("(%d,%d) (%d,%d) (%d %d) (%d,%d) => (%d,%d) (%d,%d) (%d %d) (%d,%d)\n", - ((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1], - ((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&x[3])[0],((int16_t*)&x[3])[1], - ((int16_t*)&y[0])[0],((int16_t*)&y[0])[1],((int16_t*)&y[1])[0],((int16_t*)&y[1])[1], - ((int16_t*)&y[2])[0],((int16_t*)&y[2])[1],((int16_t*)&y[3])[0],((int16_t*)&y[3])[1]); - - bfly4(x,x+1,x+2,x+3,y, y+1,y+2,y+3,&tw0,&tw1,&tw2); - printf("0(%d,%d) (%d,%d) (%d %d) (%d,%d) => (%d,%d) (%d,%d) (%d %d) (%d,%d)\n", - ((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1], - ((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&x[3])[0],((int16_t*)&x[3])[1], - ((int16_t*)&y[0])[0],((int16_t*)&y[0])[1],((int16_t*)&y[1])[0],((int16_t*)&y[1])[1], - ((int16_t*)&y[2])[0],((int16_t*)&y[2])[1],((int16_t*)&y[3])[0],((int16_t*)&y[3])[1]); - printf("1(%d,%d) (%d,%d) (%d %d) (%d,%d) => (%d,%d) (%d,%d) (%d %d) (%d,%d)\n", - ((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1], - ((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&x[3])[0],((int16_t*)&x[3])[1], - ((int16_t*)&y[0])[2],((int16_t*)&y[0])[3],((int16_t*)&y[1])[2],((int16_t*)&y[1])[3], - ((int16_t*)&y[2])[2],((int16_t*)&y[2])[3],((int16_t*)&y[3])[2],((int16_t*)&y[3])[3]); - printf("2(%d,%d) (%d,%d) (%d %d) (%d,%d) => (%d,%d) (%d,%d) (%d %d) (%d,%d)\n", - ((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1], - ((int16_t*)&x[2])[0],((int16_t*)&x[2])[1],((int16_t*)&x[3])[0],((int16_t*)&x[3])[1], - ((int16_t*)&y[0])[4],((int16_t*)&y[0])[5],((int16_t*)&y[1])[4],((int16_t*)&y[1])[5], - ((int16_t*)&y[2])[4],((int16_t*)&y[2])[5],((int16_t*)&y[3])[4],((int16_t*)&y[3])[5]); - printf("3(%d,%d) (%d,%d) (%d %d) (%d,%d) => (%d,%d) (%d,%d) (%d %d) (%d,%d)\n", - ((int16_t*)&x[0])[0],((int16_t*)&x[0])[1],((int16_t*)&x[1])[0],((int16_t*)&x[1])[1], - ((int16_t*)&x[2])[6],((int16_t*)&x[2])[7],((int16_t*)&x[3])[6],((int16_t*)&x[3])[7], - ((int16_t*)&y[0])[6],((int16_t*)&y[0])[7],((int16_t*)&y[1])[6],((int16_t*)&y[1])[7], - ((int16_t*)&y[2])[0],((int16_t*)&y[2])[1],((int16_t*)&y[3])[0],((int16_t*)&y[3])[1]); - - bfly5_tw1(x,x+1,x+2,x+3,x+4,y,y+1,y+2,y+3,y+4); - - for (i=0;i<5;i++) - printf("%d,%d,", - ((int16_t*)&x[i])[0],((int16_t*)&x[i])[1]); - printf("\n"); - for (i=0;i<5;i++) - printf("%d,%d,", - ((int16_t*)&y[i])[0],((int16_t*)&y[i])[1]); - printf("\n"); - - bfly5(x,x+1,x+2,x+3,x+4,y, y+1,y+2,y+3,y+4,&tw0,&tw1,&tw2,&tw3); - for (i=0;i<5;i++) - printf("%d,%d,", - ((int16_t*)&x[i])[0],((int16_t*)&x[i])[1]); - printf("\n"); - for (i=0;i<5;i++) - printf("%d,%d,", - ((int16_t*)&y[i])[0],((int16_t*)&y[i])[1]); - printf("\n"); - - - printf("\n\n12-point\n"); - dft12f(x, - x+1, - x+2, - x+3, - x+4, - x+5, - x+6, - x+7, - x+8, - x+9, - x+10, - x+11, - y, - y+1, - y+2, - y+3, - y+4, - y+5, - y+6, - y+7, - y+8, - y+9, - y+10, - y+11); - - - printf("X: "); - for (i=0;i<12;i++) - printf("%d,%d,",((int16_t*)(&x[i]))[0],((int16_t *)(&x[i]))[1]); - printf("\nY:"); - for (i=0;i<12;i++) - printf("%d,%d,",((int16_t*)(&y[i]))[0],((int16_t *)(&y[i]))[1]); - printf("\n"); - - */ - - for (i=0;i<32;i++) { - ((int16_t*)x)[i] = (int16_t)((taus()&0xffff))>>5; - } - memset((void*)&y[0],0,16*4); - idft16((int16_t *)x,(int16_t *)y); - printf("\n\n16-point\n"); - printf("X: "); - for (i=0;i<4;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&x[i])[0],((int16_t *)&x[i])[1],((int16_t*)&x[i])[2],((int16_t *)&x[i])[3],((int16_t*)&x[i])[4],((int16_t*)&x[i])[5],((int16_t*)&x[i])[6],((int16_t*)&x[i])[7]); - printf("\nY:"); - - for (i=0;i<4;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&y[i])[0],((int16_t *)&y[i])[1],((int16_t*)&y[i])[2],((int16_t *)&y[i])[3],((int16_t*)&y[i])[4],((int16_t *)&y[i])[5],((int16_t*)&y[i])[6],((int16_t *)&y[i])[7]); - printf("\n"); - - memset((void*)&x[0],0,2048*4); - - for (i=0; i<2048; i+=4) { - ((int16_t*)x)[i<<1] = 1024; - ((int16_t*)x)[1+(i<<1)] = 0; - ((int16_t*)x)[2+(i<<1)] = 0; - ((int16_t*)x)[3+(i<<1)] = 1024; - ((int16_t*)x)[4+(i<<1)] = -1024; - ((int16_t*)x)[5+(i<<1)] = 0; - ((int16_t*)x)[6+(i<<1)] = 0; - ((int16_t*)x)[7+(i<<1)] = -1024; - } - /* - for (i=0; i<2048; i+=2) { - ((int16_t*)x)[i<<1] = 1024; - ((int16_t*)x)[1+(i<<1)] = 0; - ((int16_t*)x)[2+(i<<1)] = -1024; - ((int16_t*)x)[3+(i<<1)] = 0; - } - - for (i=0;i<2048*2;i++) { - ((int16_t*)x)[i] = i/2;//(int16_t)((taus()&0xffff))>>5; - } - */ - memset((void*)&x[0],0,64*sizeof(int32_t)); - for (i=2;i<36;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=(128-36);i<128;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - idft64((int16_t *)x,(int16_t *)y,1); - - - printf("64-point\n"); - printf("X: "); - for (i=0;i<8;i++) - print_shorts256("",((int16_t *)x)+(i*16)); - - printf("\nY:"); - - for (i=0;i<8;i++) - print_shorts256("",((int16_t *)y)+(i*16)); - printf("\n"); - - - - - idft64((int16_t *)x,(int16_t *)y,1); - idft64((int16_t *)x,(int16_t *)y,1); - idft64((int16_t *)x,(int16_t *)y,1); - reset_meas(&ts); - - for (i=0; i<10000000; i++) { - start_meas(&ts); - idft64((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - - } - /* - printf("\n\n64-point (%f cycles, #trials %d)\n",(double)ts.diff/(double)ts.trials,ts.trials); - // LOG_M("x64.m","x64",x,64,1,1); - LOG_M("y64.m","y64",y,64,1,1); - LOG_M("x64.m","x64",x,64,1,1); - */ -/* - printf("X: "); - for (i=0;i<16;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&x[i])[0],((int16_t *)&x[i])[1],((int16_t*)&x[i])[2],((int16_t *)&x[i])[3],((int16_t*)&x[i])[4],((int16_t*)&x[i])[5],((int16_t*)&x[i])[6],((int16_t*)&x[i])[7]); - printf("\nY:"); - - for (i=0;i<16;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&y[i])[0],((int16_t *)&y[i])[1],((int16_t*)&y[i])[2],((int16_t *)&y[i])[3],((int16_t*)&y[i])[4],((int16_t *)&y[i])[5],((int16_t*)&y[i])[6],((int16_t *)&y[i])[7]); - printf("\n"); - - idft64((int16_t*)y,(int16_t*)x,1); - printf("X: "); - for (i=0;i<16;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&x[i])[0],((int16_t *)&x[i])[1],((int16_t*)&x[i])[2],((int16_t *)&x[i])[3],((int16_t*)&x[i])[4],((int16_t*)&x[i])[5],((int16_t*)&x[i])[6],((int16_t*)&x[i])[7]); - - for (i=0; i<256; i++) { - ((int16_t*)x)[i] = (int16_t)((taus()&0xffff))>>5; - } -*/ - - memset((void*)&x[0],0,128*4); - for (i=2;i<72;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=(256-72);i<256;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft128((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n128-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y128.m","y128",y,128,1,1); - LOG_M("x128.m","x128",x,128,1,1); -/* - printf("X: "); - for (i=0;i<32;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&x[i])[0],((int16_t *)&x[i])[1],((int16_t*)&x[i])[2],((int16_t *)&x[i])[3],((int16_t*)&x[i])[4],((int16_t*)&x[i])[5],((int16_t*)&x[i])[6],((int16_t*)&x[i])[7]); - printf("\nY:"); - - for (i=0;i<32;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&y[i])[0],((int16_t *)&y[i])[1],((int16_t*)&y[i])[2],((int16_t *)&y[i])[3],((int16_t*)&y[i])[4],((int16_t *)&y[i])[5],((int16_t*)&y[i])[6],((int16_t *)&y[i])[7]); - printf("\n"); -*/ - - /* - for (i=0; i<512; i++) { - ((int16_t*)x)[i] = (int16_t)((taus()&0xffff))>>5; - } - - memset((void*)&y[0],0,256*4); - */ - memset((void*)&x[0],0,256*sizeof(int32_t)); - for (i=2;i<144;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=(512-144);i<512;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft256((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n256-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y256.m","y256",y,256,1,1); - LOG_M("x256.m","x256",x,256,1,1); - - memset((void*)&x[0],0,512*sizeof(int32_t)); - for (i=2;i<302;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=(1024-300);i<1024;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft512((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n512-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y512.m","y512",y,512,1,1); - LOG_M("x512.m","x512",x,512,1,1); - /* - printf("X: "); - for (i=0;i<64;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&x[i])[0],((int16_t *)&x[i])[1],((int16_t*)&x[i])[2],((int16_t *)&x[i])[3],((int16_t*)&x[i])[4],((int16_t*)&x[i])[5],((int16_t*)&x[i])[6],((int16_t*)&x[i])[7]); - printf("\nY:"); - - for (i=0;i<64;i++) - printf("%d,%d,%d,%d,%d,%d,%d,%d,",((int16_t*)&y[i])[0],((int16_t *)&y[i])[1],((int16_t*)&y[i])[2],((int16_t *)&y[i])[3],((int16_t*)&y[i])[4],((int16_t *)&y[i])[5],((int16_t*)&y[i])[6],((int16_t *)&y[i])[7]); - printf("\n"); - */ - - memset((void*)x,0,1024*sizeof(int32_t)); - for (i=2;i<602;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*724;i<2048;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft1024((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n1024-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y1024.m","y1024",y,1024,1,1); - LOG_M("x1024.m","x1024",x,1024,1,1); - - - memset((void*)x,0,1536*sizeof(int32_t)); - for (i=2;i<1202;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(1536-600);i<3072;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft1536((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - write_output("y1536.m","y1536",y,1536,1,1); - write_output("x1536.m","x1536",x,1536,1,1); - - - memset((void*)x,0,2048*sizeof(int32_t)); - for (i=2;i<1202;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(2048-600);i<4096;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - dft2048((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n2048-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y2048.m","y2048",y,2048,1,1); - LOG_M("x2048.m","x2048",x,2048,1,1); - -// NR 80Mhz, 217 PRB, 3/4 sampling - memset((void*)x, 0, 3072*sizeof(int32_t)); - for (i=2;i<2506;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(3072-1252);i<6144;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft3072((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n3072-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - write_output("y3072.m","y3072",y,3072,1,1); - write_output("x3072.m","x3072",x,3072,1,1); - - - memset((void*)x,0,4096*sizeof(int32_t)); - for (i=0;i<2400;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(4096-1200);i<8192;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft4096((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n4096-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y4096.m","y4096",y,4096,1,1); - LOG_M("x4096.m","x4096",x,4096,1,1); - - dft4096((int16_t *)y,(int16_t *)x2,1); - LOG_M("x4096_2.m","x4096_2",x2,4096,1,1); - -// NR 160Mhz, 434 PRB, 3/4 sampling - memset((void*)x, 0, 6144*sizeof(int32_t)); - for (i=2;i<5010;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(6144-2504);i<12288;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - - reset_meas(&ts); - - for (i=0; i<10000; i++) { - start_meas(&ts); - idft6144((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n6144-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - write_output("y6144.m","y6144",y,6144,1,1); - write_output("x6144.m","x6144",x,6144,1,1); - - memset((void*)x,0,8192*sizeof(int32_t)); - for (i=2;i<4802;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(8192-2400);i<16384;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft8192((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y8192.m","y8192",y,8192,1,1); - LOG_M("x8192.m","x8192",x,8192,1,1); - - memset((void*)x,0,1536*sizeof(int32_t)); - for (i=2;i<1202;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(1536-600);i<3072;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft1536((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y1536.m","y1536",y,1536,1,1); - LOG_M("x1536.m","x1536",x,1536,1,1); - - printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y8192.m","y8192",y,8192,1,1); - LOG_M("x8192.m","x8192",x,8192,1,1); - - memset((void*)x,0,3072*sizeof(int32_t)); - for (i=2;i<1202;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(3072-600);i<3072;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft3072((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n3072-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y3072.m","y3072",y,3072,1,1); - LOG_M("x3072.m","x3072",x,3072,1,1); - - memset((void*)x,0,6144*sizeof(int32_t)); - for (i=2;i<4802;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(6144-2400);i<12288;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft6144((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n6144-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y6144.m","y6144",y,6144,1,1); - LOG_M("x6144.m","x6144",x,6144,1,1); - - memset((void*)x,0,12288*sizeof(int32_t)); - for (i=2;i<9602;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(12288-4800);i<24576;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft12288((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n12288-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y12288.m","y12288",y,12288,1,1); - LOG_M("x12288.m","x12288",x,12288,1,1); - - memset((void*)x,0,18432*sizeof(int32_t)); - for (i=2;i<14402;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(18432-7200);i<36864;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft18432((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n18432-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y18432.m","y18432",y,18432,1,1); - LOG_M("x18432.m","x18432",x,18432,1,1); - - memset((void*)x,0,24576*sizeof(int32_t)); - for (i=2;i<19202;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - for (i=2*(24576-19200);i<49152;i++) { - if ((taus() & 1)==0) - ((int16_t*)x)[i] = 364; - else - ((int16_t*)x)[i] = -364; - } - reset_meas(&ts); - for (i=0; i<10000; i++) { - start_meas(&ts); - idft24576((int16_t *)x,(int16_t *)y,1); - stop_meas(&ts); - } - - printf("\n\n24576-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); - LOG_M("y24576.m","y24576",y,24576,1,1); - LOG_M("x24576.m","x24576",x,24576,1,1); - - int dftsizes[33]={24,36,48,60,72,96,108,120,144,180,192,216,240,288,300,324,360,384,432,480,540,576,600,648,720,768,864,900,960,972,1080,1152,1200}; - void (*dft)(int16_t *x,int16_t *y,uint8_t scale)[33] = {dft24,dft36,dft48,dft60,dft72,dft96,dft108,dft120,dft144,dft180,dft192,dft216,dft240,dft288,dft300,dft324,dft360,dft384,dft432,dft480,dft540,dft576,dft600,dft648,dft720,dft768,dft864,dft900,dft960,dft972,dft1080,dft1152,dft1200}; - for (int n=0;n<33;n++) { - // 4xN-point DFT - memset((void*)x,0,dftsizes[n]*8*sizeof(int16_t)); - for (i=0;isymbols_per_tti; k++) { for (i=0; i<12*frame_parms->N_RB_UL; i++) { - I[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i]; - Q[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1]; - ind++; + if ( pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i] > -range && + pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i] < range && + pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1] > -range && + pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1] < range ) { + I[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i]; + Q[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1]; + ind++; + } } } diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 40803c30f4..67ec027a9d 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -157,9 +157,9 @@ void phy_scope_gNB(FD_phy_scope_gnb *form, { int i, arx; //int i,i2,arx,atx,ind,k; NR_DL_FRAME_PARMS *frame_parms = &phy_vars_gnb->frame_parms; - int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; + //int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE + //uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE int16_t **rxsig_t, **rxsig_f; // int16_t **chest_t=NULL; // int16_t **chest_f=NULL; @@ -182,7 +182,7 @@ void phy_scope_gNB(FD_phy_scope_gnb *form, int Qm = 2; /* - if (!RC.nrmac[0]->UE_list.active[UE_id]) + if (!RC.nrmac[0]->UE_info.active[UE_id]) return; // choose max MCS to compute coded_bits_per_codeword @@ -966,7 +966,7 @@ FD_stats_form * create_form_stats_form( void ) { } void startScope(scopeParms_t * p) { - FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; + //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; char title[255]; fl_initialize (p->argc, p->argv, NULL, 0, 0); /* diff --git a/openair1/PHY/TOOLS/smbv.h b/openair1/PHY/TOOLS/smbv.h index ef40a9ed7d..f8fab67d01 100644 --- a/openair1/PHY/TOOLS/smbv.h +++ b/openair1/PHY/TOOLS/smbv.h @@ -23,6 +23,8 @@ This library offers some functions to remotely program the R&S SMBV100A. */ +#ifndef __PHY_TOOLS_SMBV__H__ +#define __PHY_TOOLS_SMBV__H__ #include #include @@ -93,3 +95,4 @@ int smbv_configure_common_dci(const char* fname, uint8_t subframe, const char* t // item is the row in the DCI table int smbv_configure_ue_spec_dci(const char* fname, uint8_t subframe, uint8_t user, DCI_ALLOC_t *dci_alloc, uint8_t item); #endif +#endif diff --git a/openair1/PHY/TOOLS/time_meas.h b/openair1/PHY/TOOLS/time_meas.h index b9777686ea..2deab40f27 100644 --- a/openair1/PHY/TOOLS/time_meas.h +++ b/openair1/PHY/TOOLS/time_meas.h @@ -33,7 +33,7 @@ #include // global var to enable openair performance profiler extern int opp_enabled; -double cpu_freq_GHz; +double cpu_freq_GHz __attribute__ ((aligned(32)));; #if defined(__x86_64__) || defined(__i386__) typedef struct { diff --git a/openair1/PHY/TOOLS/tools_defs.h b/openair1/PHY/TOOLS/tools_defs.h index d753b501b6..61ea785db8 100644 --- a/openair1/PHY/TOOLS/tools_defs.h +++ b/openair1/PHY/TOOLS/tools_defs.h @@ -36,6 +36,8 @@ extern "C" { #include #include "PHY/sse_intrin.h" +#define CEILIDIV(a,b) ((a+b-1)/b) +#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1)) struct complex { double x; @@ -179,44 +181,144 @@ This function performs optimized fixed-point radix-2 FFT/IFFT. ); */ -void idft1536(int16_t *sigF,int16_t *sig,int scale); -void idft6144(int16_t *sigF,int16_t *sig,int scale); -void idft12288(int16_t *sigF,int16_t *sig,int scale); -void idft18432(int16_t *sigF,int16_t *sig,int scale); -void idft3072(int16_t *sigF,int16_t *sig,int scale); -void idft24576(int16_t *sigF,int16_t *sig,int scale); -void dft1536(int16_t *sigF,int16_t *sig,int scale); +#ifdef OAIDFTS_MAIN +typedef void(*adftfunc_t)(int16_t *sigF,int16_t *sig,unsigned char scale_flag); +typedef void(*aidftfunc_t)(int16_t *sigF,int16_t *sig,unsigned char scale_flag); -void dft3072(int16_t *sigF,int16_t *sig,int scale); +void dft12(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft24(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft36(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft48(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft60(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft64(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft72(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft96(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft108(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft120(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft128(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft144(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft180(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft192(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft216(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft240(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft256(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft288(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft300(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft324(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft360(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft384(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft432(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft480(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft512(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft540(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft576(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft600(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft648(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft720(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft768(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft864(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft900(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft960(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft972(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft1024(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft1080(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft1152(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft1200(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft1536(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void dft2048(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft3072(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void dft4096(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft6144(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void dft8192(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft9216(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft12288(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft18432(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft24576(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft36864(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft49152(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft73728(int16_t *x,int16_t *y,uint8_t scale_flag); +void dft98304(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft6144(int16_t *sigF,int16_t *sig,int scale); -void dft12288(int16_t *sigF,int16_t *sig,int scale); +void idft64(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft128(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft256(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft512(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft1024(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft1536(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft2048(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft3072(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft4096(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft6144(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft8192(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft9216(int16_t *x,int16_t *y,uint8_t scale_flag); +void idft12288(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft18432(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft24576(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft36864(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft49152(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft73728(int16_t *sigF,int16_t *sig,uint8_t scale_flag); +void idft98304(int16_t *sigF,int16_t *sig,uint8_t scale_flag); -void dft18432(int16_t *sigF,int16_t *sig,int scale); -void dft24576(int16_t *sigF,int16_t *sig,int scale); -void dft49152(int16_t *sigF,int16_t *sig,int scale); -void idft49152(int16_t *sigF,int16_t *sig,int scale); -void dft9216(int16_t *sigF,int16_t *sig,int scale); -void idft9216(int16_t *sigF,int16_t *sig,int scale); +#else + typedef void(*dftfunc_t)(uint8_t sizeidx,int16_t *sigF,int16_t *sig,unsigned char scale_flag); + typedef void(*idftfunc_t)(uint8_t sizeidx,int16_t *sigF,int16_t *sig,unsigned char scale_flag); +# ifdef OAIDFTS_LOADER + dftfunc_t dft; + idftfunc_t idft; +# else + extern dftfunc_t dft; + extern idftfunc_t idft; + extern int load_dftslib(void); +# endif +#endif -void dft36864(int16_t *sigF,int16_t *sig,int scale); -void idft36864(int16_t *sigF,int16_t *sig,int scale); +typedef enum DFT_size_idx { + DFT_12, DFT_24, DFT_36, DFT_48, DFT_60, DFT_72, DFT_96, + DFT_108, DFT_120, DFT_128, DFT_144, DFT_180, DFT_192, DFT_216, DFT_240, + DFT_256, DFT_288, DFT_300, DFT_324, DFT_360, DFT_384, DFT_432, DFT_480, + DFT_512, DFT_540, DFT_576, DFT_600, DFT_648, DFT_720, DFT_768, DFT_864, + DFT_900, DFT_960, DFT_972, DFT_1024, DFT_1080, DFT_1152, DFT_1200, DFT_1536, + DFT_2048, DFT_3072, DFT_4096, DFT_6144, DFT_8192, DFT_9216, DFT_12288, DFT_18432, + DFT_24576, DFT_36864, DFT_49152, DFT_73728, DFT_98304, + DFT_SIZE_IDXTABLESIZE +} dft_size_idx_t; -void dft98304(int16_t *sigF,int16_t *sig,int scale); -void idft98304(int16_t *sigF,int16_t *sig,int scale); +#ifdef OAIDFTS_MAIN +adftfunc_t dft_ftab[]={ + dft12, dft24, dft36, dft48, dft60, dft72, dft96, + dft108, dft120, dft128, dft144, dft180, dft192, dft216, dft240, + dft256, dft288, dft300, dft324, dft360, dft384, dft432, dft480, + dft512, dft540, dft576, dft600, dft648, dft720, dft768, dft864, + dft900, dft960, dft972, dft1024, dft1080, dft1152, dft1200, dft1536, + dft2048, dft3072, dft4096, dft6144, dft8192, dft9216, dft12288, dft18432, + dft24576, dft36864, dft49152, dft73728, dft98304 +}; +#endif + +typedef enum idft_size_idx { + IDFT_128, IDFT_256, IDFT_512, IDFT_1024, IDFT_1536, IDFT_2048, IDFT_3072, IDFT_4096, + IDFT_6144, IDFT_8192, IDFT_9216, IDFT_12288, IDFT_18432, IDFT_24576, IDFT_36864, IDFT_49152, + IDFT_73728, IDFT_98304, + IDFT_SIZE_IDXTABLESIZE +} idft_size_idx_t; +#ifdef OAIDFTS_MAIN +aidftfunc_t idft_ftab[]={ + idft128, idft256, idft512, idft1024, idft1536, idft2048, idft3072, idft4096, + idft6144, idft8192, idft9216, idft12288, idft18432, idft24576, idft36864, idft49152, + idft73728, idft98304 +}; +#endif -void dft73728(int16_t *sigF,int16_t *sig,int scale); -void idft73728(int16_t *sigF,int16_t *sig,int scale); /*!\fn int32_t rotate_cpx_vector(int16_t *x,int16_t *alpha,int16_t *y,uint32_t N,uint16_t output_shift) @@ -387,57 +489,7 @@ int64_t dot_product64(int16_t *x, uint32_t N, //must be a multiple of 8 uint8_t output_shift); -void dft12(int16_t *x,int16_t *y); -void dft24(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft36(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft48(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft60(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft72(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft96(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft108(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft120(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft144(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft180(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft192(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft216(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft240(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft288(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft300(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft324(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft360(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft384(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft432(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft480(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft540(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft576(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft600(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft648(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft720(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft768(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft864(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft900(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft960(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft972(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft1080(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft1152(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft1200(int16_t *x,int16_t *y,uint8_t scale_flag); -void dft64(int16_t *x,int16_t *y,int scale); -void dft128(int16_t *x,int16_t *y,int scale); -void dft256(int16_t *x,int16_t *y,int scale); -void dft512(int16_t *x,int16_t *y,int scale); -void dft1024(int16_t *x,int16_t *y,int scale); -void dft2048(int16_t *x,int16_t *y,int scale); -void dft4096(int16_t *x,int16_t *y,int scale); -void dft8192(int16_t *x,int16_t *y,int scale); -void idft64(int16_t *x,int16_t *y,int scale); -void idft128(int16_t *x,int16_t *y,int scale); -void idft256(int16_t *x,int16_t *y,int scale); -void idft512(int16_t *x,int16_t *y,int scale); -void idft1024(int16_t *x,int16_t *y,int scale); -void idft2048(int16_t *x,int16_t *y,int scale); -void idft4096(int16_t *x,int16_t *y,int scale); -void idft8192(int16_t *x,int16_t *y,int scale); /** @} */ diff --git a/openair1/PHY/defs_L1_NB_IoT.h b/openair1/PHY/defs_L1_NB_IoT.h index f0fd7661c7..1f8c0b8eee 100644 --- a/openair1/PHY/defs_L1_NB_IoT.h +++ b/openair1/PHY/defs_L1_NB_IoT.h @@ -148,11 +148,7 @@ static inline void* malloc16_clear( size_t size ) #define NB_BANDS_MAX_NB_IoT 8 -#ifdef OCP_FRAMEWORK -#include -#else typedef enum {normal_txrx_NB_IoT=0,rx_calib_ue_NB_IoT=1,rx_calib_ue_med_NB_IoT=2,rx_calib_ue_byp_NB_IoT=3,debug_prach_NB_IoT=4,no_L2_connect_NB_IoT=5,calib_prach_tx_NB_IoT=6,rx_dump_frame_NB_IoT=7,loop_through_memory_NB_IoT=8} runmode_NB_IoT_t; -#endif /* enum transmission_access_mode { NO_ACCESS=0, diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h index 10496ced20..ce808eddf9 100644 --- a/openair1/PHY/defs_RU.h +++ b/openair1/PHY/defs_RU.h @@ -38,15 +38,13 @@ #include "openairinterface5g_limits.h" #include "PHY/TOOLS/time_meas.h" #include "defs_common.h" +#include #define MAX_BANDS_PER_RRU 4 #define MAX_RRU_CONFIG_SIZE 1024 -#ifdef OCP_FRAMEWORK -#include -#else typedef enum { normal_txrx=0, @@ -92,7 +90,6 @@ typedef enum { synch_to_other, // synch to another source_(timer, other RU) synch_to_mobipass_standalone // special case for mobipass in standalone mode } node_timing_t; -#endif typedef struct { @@ -540,6 +537,8 @@ typedef struct RU_t_s { void (*wakeup_prach_gNB)(struct PHY_VARS_gNB_s *gNB, struct RU_t_s *ru, int frame, int subframe); /// function pointer to wakeup routine in lte-enb. void (*wakeup_prach_eNB_br)(struct PHY_VARS_eNB_s *eNB, struct RU_t_s *ru, int frame, int subframe); + /// function pointer to start a thread of tx write for USRP. + int (*start_write_thread)(struct RU_t_s *ru); /// function pointer to NB entry routine void (*eNB_top)(struct PHY_VARS_eNB_s *eNB, int frame_rx, int subframe_rx, char *string, struct RU_t_s *ru); diff --git a/openair1/PHY/defs_common.h b/openair1/PHY/defs_common.h index f52558b632..75b2d54dc6 100644 --- a/openair1/PHY/defs_common.h +++ b/openair1/PHY/defs_common.h @@ -99,9 +99,6 @@ #define NB_RX_ANTENNAS_MAX 64 -#ifdef OCP_FRAMEWORK -#include "enums.h" -#else typedef enum {TDD=1,FDD=0} lte_frame_type_t; @@ -122,7 +119,6 @@ typedef enum { one=6, two=12 } PHICH_RESOURCE_t; -#endif /// PHICH-Config from 36.331 RRC spec typedef struct { /// Parameter: PHICH-Duration, see TS 36.211 (Table 6.9.3-1). @@ -250,12 +246,10 @@ typedef struct { } UL_REFERENCE_SIGNALS_PUSCH_t; /// Enumeration for parameter Hopping-mode \ref PUSCH_CONFIG_COMMON::hoppingMode. -#ifndef OCP_FRAMEWORK typedef enum { interSubFrame=0, intraAndInterSubFrame=1 } PUSCH_HOPPING_t; -#endif /// PUSCH-ConfigCommon from 36.331 RRC spec. typedef struct { @@ -434,7 +428,6 @@ typedef struct { uint8_t filterCoefficient; } UL_POWER_CONTROL_DEDICATED; -#ifndef OCP_FRAMEWORK /// Enumeration for parameter \f$\alpha\f$ \ref UL_POWER_CONTROL_CONFIG_COMMON::alpha. typedef enum { al0=0, @@ -446,7 +439,6 @@ typedef enum { al09=6, al1=7 } PUSCH_alpha_t; -#endif /// \note UNUSED typedef enum { diff --git a/openair1/PHY/defs_eNB.h b/openair1/PHY/defs_eNB.h index 7b06f6c8c7..557b8bfc30 100644 --- a/openair1/PHY/defs_eNB.h +++ b/openair1/PHY/defs_eNB.h @@ -201,41 +201,11 @@ typedef struct { int repetition_number[4]; } LTE_eNB_PRACH; -/// Context data structure for RX/TX portion of subframe processing -typedef struct { - /// Component Carrier index - uint8_t CC_id; - /// timestamp transmitted to HW - openair0_timestamp timestamp_tx; - /// subframe to act upon for transmission - int subframe_tx; - /// subframe to act upon for reception - int subframe_rx; - /// frame to act upon for transmission - int frame_tx; - /// frame to act upon for reception - int frame_rx; - /// \brief Instance count for RXn-TXnp4 processing thread. - /// \internal This variable is protected by \ref mutex_rxtx. - int instance_cnt; - /// pthread structure for RXn-TXnp4 processing thread - pthread_t pthread; - /// pthread attributes for RXn-TXnp4 processing thread - pthread_attr_t attr; - /// condition variable for tx processing thread - pthread_cond_t cond; - /// mutex for RXn-TXnp4 processing thread - pthread_mutex_t mutex; - /// scheduling parameters for RXn-TXnp4 thread - struct sched_param sched_param_rxtx; +#include "PHY/TOOLS/time_meas.h" +#include "PHY/CODING/coding_defs.h" +#include "PHY/TOOLS/tools_defs.h" +#include "PHY/LTE_TRANSPORT/transport_eNB.h" - /// \internal This variable is protected by \ref mutex_RUs. - int instance_cnt_RUs; - /// condition variable for tx processing thread - pthread_cond_t cond_RUs; - /// mutex for RXn-TXnp4 processing thread - pthread_mutex_t mutex_RUs; -} L1_rxtx_proc_t; typedef struct { struct PHY_VARS_eNB_s *eNB; @@ -694,6 +664,57 @@ typedef struct PHY_VARS_eNB_s { int32_t pusch_stats_mcs[NUMBER_OF_UE_MAX][10240]; int32_t pusch_stats_bsr[NUMBER_OF_UE_MAX][10240]; int32_t pusch_stats_BO[NUMBER_OF_UE_MAX][10240]; + uint8_t *FS6bufferZone; } PHY_VARS_eNB; + +struct turboReqId { + uint16_t rnti; + uint16_t frame; + uint8_t subframe; + uint8_t codeblock; + uint16_t spare; +} __attribute__((packed)); + +union turboReqUnion { + struct turboReqId s; + uint64_t p; +}; + +typedef struct TurboDecode_s { + PHY_VARS_eNB *eNB; + decoder_if_t *function; + uint8_t decoded_bytes[3+1768] __attribute__((aligned(32))); + int UEid; + int harq_pid; + int frame; + int subframe; + int Fbits; + int Kr; + LTE_UL_eNB_HARQ_t *ulsch_harq; + int nbSegments; + int segment_r; + int r_offset; + int offset; + int maxIterations; + int decodeIterations; +} turboDecode_t; + +#define TURBO_SIMD_SOFTBITS 96+12+3+3*6144 +typedef struct turboEncode_s { + uint8_t * input; + int Kr_bytes; + int filler; + unsigned int G; + int r; + int harq_pid; + int round; + int r_offset; + LTE_eNB_DLSCH_t *dlsch; + time_stats_t *rm_stats; + time_stats_t *te_stats; + time_stats_t *i_stats; +} turboEncode_t; + + #endif /* __PHY_DEFS_ENB__H__ */ diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index b5a24ca793..aa794da818 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -44,6 +44,13 @@ #include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" #define MAX_NUM_RU_PER_gNB MAX_NUM_RU_PER_eNB +#define MAX_PUCCH0_NID 8 + +typedef struct { + int nb_id; + int Nid[MAX_PUCCH0_NID]; + int lut[MAX_PUCCH0_NID][160][14]; +} NR_gNB_PUCCH0_LUT_t; typedef struct { uint32_t pbch_a; @@ -561,13 +568,13 @@ typedef struct { //! estimated avg noise power (dB) short n0_power_tot_dBm; //! estimated avg noise power per RB per RX ant (lin) - unsigned short n0_subband_power[MAX_NUM_RU_PER_gNB][100]; + unsigned short n0_subband_power[MAX_NUM_RU_PER_gNB][275]; //! estimated avg noise power per RB per RX ant (dB) - unsigned short n0_subband_power_dB[MAX_NUM_RU_PER_gNB][100]; + unsigned short n0_subband_power_dB[MAX_NUM_RU_PER_gNB][275]; //! estimated avg noise power per RB (dB) - short n0_subband_power_tot_dB[100]; + short n0_subband_power_tot_dB[275]; //! estimated avg noise power per RB (dBm) - short n0_subband_power_tot_dBm[100]; + short n0_subband_power_tot_dBm[275]; // gNB measurements (per user) //! estimated received spatial signal power (linear) unsigned int rx_spatial_power[NUMBER_OF_NR_DLSCH_MAX][2][2]; @@ -587,17 +594,23 @@ typedef struct { /// Wideband CQI (sum of all RX antennas, in dB) char wideband_cqi_tot[NUMBER_OF_NR_DLSCH_MAX]; /// Subband CQI per RX antenna and RB (= SINR) - int subband_cqi[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][100]; + int subband_cqi[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][275]; /// Total Subband CQI and RB (= SINR) - int subband_cqi_tot[NUMBER_OF_NR_DLSCH_MAX][100]; + int subband_cqi_tot[NUMBER_OF_NR_DLSCH_MAX][275]; /// Subband CQI in dB and RB (= SINR dB) - int subband_cqi_dB[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][100]; + int subband_cqi_dB[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][275]; /// Total Subband CQI and RB - int subband_cqi_tot_dB[NUMBER_OF_NR_DLSCH_MAX][100]; + int subband_cqi_tot_dB[NUMBER_OF_NR_DLSCH_MAX][275]; /// PRACH background noise level int prach_I0; } PHY_MEASUREMENTS_gNB; +#define MAX_NUM_NR_RX_RACH_PDUS 4 +#define MAX_NUM_NR_RX_PRACH_PREAMBLES 4 +#define MAX_UL_PDUS_PER_SLOT 100 +#define MAX_NUM_NR_SRS_PDUS 100 +#define MAX_NUM_NR_UCI_PDUS 100 + /// Top-level PHY Data Structure for gNB typedef struct PHY_VARS_gNB_s { /// Module ID indicator for this instance @@ -624,22 +637,21 @@ typedef struct PHY_VARS_gNB_s { pthread_mutex_t UL_INFO_mutex; /// NFAPI RX ULSCH information - nfapi_rx_indication_pdu_t rx_pdu_list[NFAPI_RX_IND_MAX_PDU]; + nfapi_nr_rx_data_pdu_t rx_pdu_list[MAX_UL_PDUS_PER_SLOT]; /// NFAPI RX ULSCH CRC information - nfapi_crc_indication_pdu_t crc_pdu_list[NFAPI_CRC_IND_MAX_PDU]; - /// NFAPI HARQ information - nfapi_harq_indication_pdu_t harq_pdu_list[NFAPI_HARQ_IND_MAX_PDU]; - /// NFAPI SR information - nfapi_sr_indication_pdu_t sr_pdu_list[NFAPI_SR_IND_MAX_PDU]; - /// NFAPI CQI information - nfapi_cqi_indication_pdu_t cqi_pdu_list[NFAPI_CQI_IND_MAX_PDU]; - /// NFAPI CQI information (raw component) - nfapi_cqi_indication_raw_pdu_t cqi_raw_pdu_list[NFAPI_CQI_IND_MAX_PDU]; + nfapi_nr_crc_t crc_pdu_list[MAX_UL_PDUS_PER_SLOT]; + /// NFAPI SRS information + nfapi_nr_srs_indication_pdu_t srs_pdu_list[MAX_NUM_NR_SRS_PDUS]; + /// NFAPI UCI information + nfapi_nr_uci_t uci_pdu_list[MAX_NUM_NR_UCI_PDUS]; /// NFAPI PRACH information - nfapi_preamble_pdu_t preamble_list[MAX_NUM_RX_PRACH_PREAMBLES]; + nfapi_nr_prach_indication_pdu_t prach_pdu_indication_list[MAX_NUM_NR_RX_RACH_PDUS]; + /// NFAPI PRACH information + nfapi_nr_prach_indication_preamble_t preamble_list[MAX_NUM_NR_RX_PRACH_PREAMBLES]; //Sched_Rsp_t Sched_INFO; nfapi_nr_ul_tti_request_t UL_tti_req; + nfapi_nr_uci_indication_t uci_indication; nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu; nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu; @@ -658,6 +670,8 @@ typedef struct PHY_VARS_gNB_s { uint8_t pbch_configured; char gNB_generate_rar; + // PUCCH0 Look-up table for cyclic-shifts + NR_gNB_PUCCH0_LUT_t pucch0_lut; /// NR synchronization sequences int16_t d_pss[NR_PSS_LENGTH]; int16_t d_sss[NR_SSS_LENGTH]; @@ -709,13 +723,12 @@ typedef struct PHY_VARS_gNB_s { /// counter to average prach energh over first 100 prach opportunities int prach_energy_counter; + int pucch0_thres; /* time_stats_t phy_proc; */ time_stats_t phy_proc_tx; - /* time_stats_t phy_proc_rx; - */ time_stats_t rx_prach; /* time_stats_t ofdm_mod_stats; @@ -731,18 +744,21 @@ typedef struct PHY_VARS_gNB_s { time_stats_t dlsch_rate_matching_stats; time_stats_t dlsch_interleaving_stats; time_stats_t dlsch_segmentation_stats; + + time_stats_t ulsch_decoding_stats; + time_stats_t ulsch_rate_unmatching_stats; + time_stats_t ulsch_ldpc_decoding_stats; + time_stats_t ulsch_deinterleaving_stats; + time_stats_t ulsch_unscrambling_stats; + time_stats_t ulsch_channel_estimation_stats; + time_stats_t ulsch_channel_compensation_stats; + time_stats_t ulsch_rbs_extraction_stats; + time_stats_t ulsch_llr_stats; /* time_stats_t rx_dft_stats; - time_stats_t ulsch_channel_estimation_stats; time_stats_t ulsch_freq_offset_estimation_stats; - time_stats_t ulsch_decoding_stats; - time_stats_t ulsch_demodulation_stats; - time_stats_t ulsch_rate_unmatching_stats; - time_stats_t ulsch_turbo_decoding_stats; - time_stats_t ulsch_deinterleaving_stats; - time_stats_t ulsch_demultiplexing_stats; - time_stats_t ulsch_llr_stats; */ + } PHY_VARS_gNB; #endif diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index 6f6c5ac8e9..b2d6a75265 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -954,9 +954,6 @@ typedef struct { /// PUSCH DMRS sequence uint32_t ****nr_gold_pusch_dmrs; - /// flag to indicate if PTRS is configured - uint8_t ptrs_configured; - uint32_t X_u[64][839]; uint32_t high_speed_flag; diff --git a/openair1/PHY/phy_extern.h b/openair1/PHY/phy_extern.h index deb7087c8c..165ed961b3 100644 --- a/openair1/PHY/phy_extern.h +++ b/openair1/PHY/phy_extern.h @@ -38,7 +38,7 @@ extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX]; extern unsigned int DAQ_MBOX; extern int number_of_cards; -extern short conjugate[8],conjugate2[8]; +extern const short conjugate[8],conjugate2[8]; extern RAN_CONTEXT_t RC; @@ -73,8 +73,8 @@ extern int flag_LA; extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX]; extern double sinr_bler_map_up[MCS_COUNT][2][16]; extern int table_length[MCS_COUNT]; -extern double sinr_to_cqi[4][16]; -extern int cqi_to_mcs[16]; +extern const double sinr_to_cqi[4][16]; +extern const int cqi_to_mcs[16]; //for MU-MIMO abstraction using MIESM //this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively @@ -82,23 +82,22 @@ extern double MI_map_4qam[3][162]; extern double MI_map_16qam[3][197]; extern double MI_map_64qam[3][227]; -extern double beta1_dlsch_MI[6][MCS_COUNT]; -extern double beta2_dlsch_MI[6][MCS_COUNT]; +extern const double beta1_dlsch_MI[6][MCS_COUNT]; +extern const double beta2_dlsch_MI[6][MCS_COUNT]; -extern double q_qpsk[8]; -extern double q_qam16[8]; -extern double q_qam64[8]; +extern const double q_qpsk[8]; +extern const double q_qam16[8]; +extern const double q_qam64[8]; +extern const double p_qpsk[8]; +extern const double p_qam16[8]; +extern const double p_qam64[8]; -extern double p_qpsk[8]; -extern double p_qam16[8]; -extern double p_qam64[8]; +extern const double beta1_dlsch[6][MCS_COUNT]; +extern const double beta2_dlsch[6][MCS_COUNT]; -extern double beta1_dlsch[6][MCS_COUNT]; -extern double beta2_dlsch[6][MCS_COUNT]; - -extern char NB_functions[7][20]; -extern char NB_timing[2][20]; -extern char ru_if_types[MAX_RU_IF_TYPES][20]; +extern const char NB_functions[7][20]; +extern const char NB_timing[2][20]; +extern const char ru_if_types[MAX_RU_IF_TYPES][20]; extern int16_t unscrambling_lut[65536*16]; extern uint8_t scrambling_lut[65536*16]; diff --git a/openair1/PHY/phy_extern_nr_ue.h b/openair1/PHY/phy_extern_nr_ue.h index 569bec6851..2f2a0427f4 100644 --- a/openair1/PHY/phy_extern_nr_ue.h +++ b/openair1/PHY/phy_extern_nr_ue.h @@ -34,7 +34,7 @@ extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX]; //#include "PHY/LTE_TRANSPORT/transport_extern.h" -extern short conjugate[8],conjugate2[8]; +extern const short conjugate[8],conjugate2[8]; extern int number_of_cards; @@ -70,8 +70,8 @@ extern int flag_LA; extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX]; extern double sinr_bler_map_up[MCS_COUNT][2][16]; extern int table_length[MCS_COUNT]; -extern double sinr_to_cqi[4][16]; -extern int cqi_to_mcs[16]; +extern const double sinr_to_cqi[4][16]; +extern const int cqi_to_mcs[16]; //for MU-MIMO abstraction using MIESM //this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively @@ -79,23 +79,19 @@ extern double MI_map_4qam[3][162]; extern double MI_map_16qam[3][197]; extern double MI_map_64qam[3][227]; -extern double beta1_dlsch_MI[6][MCS_COUNT]; -extern double beta2_dlsch_MI[6][MCS_COUNT]; +extern const double beta1_dlsch_MI[6][MCS_COUNT]; +extern const double beta2_dlsch_MI[6][MCS_COUNT]; -extern double q_qpsk[8]; -extern double q_qam16[8]; -extern double q_qam64[8]; +extern const double q_qpsk[8]; +extern const double q_qam16[8]; +extern const double q_qam64[8]; -extern double p_qpsk[8]; -extern double p_qam16[8]; -extern double p_qam64[8]; +extern const double beta1_dlsch[6][MCS_COUNT]; +extern const double beta2_dlsch[6][MCS_COUNT]; -extern double beta1_dlsch[6][MCS_COUNT]; -extern double beta2_dlsch[6][MCS_COUNT]; - -extern char NB_functions[7][20]; -extern char NB_timing[2][20]; -extern char ru_if_types[MAX_RU_IF_TYPES][20]; +extern const char NB_functions[7][20]; +extern const char NB_timing[2][20]; +extern const char ru_if_types[MAX_RU_IF_TYPES][20]; extern int16_t unscrambling_lut[65536*16]; extern uint8_t scrambling_lut[65536*16]; diff --git a/openair1/PHY/phy_extern_ue.h b/openair1/PHY/phy_extern_ue.h index 4f9ed0f26b..622551c2fe 100644 --- a/openair1/PHY/phy_extern_ue.h +++ b/openair1/PHY/phy_extern_ue.h @@ -36,7 +36,7 @@ extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX]; extern int number_of_cards; -extern short conjugate[8],conjugate2[8]; +extern const short conjugate[8],conjugate2[8]; extern PHY_VARS_UE ***PHY_vars_UE_g; @@ -70,8 +70,8 @@ extern int flag_LA; extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX]; extern double sinr_bler_map_up[MCS_COUNT][2][16]; extern int table_length[MCS_COUNT]; -extern double sinr_to_cqi[4][16]; -extern int cqi_to_mcs[16]; +extern const double sinr_to_cqi[4][16]; +extern const int cqi_to_mcs[16]; //for MU-MIMO abstraction using MIESM //this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively @@ -79,23 +79,23 @@ extern double MI_map_4qam[3][162]; extern double MI_map_16qam[3][197]; extern double MI_map_64qam[3][227]; -extern double beta1_dlsch_MI[6][MCS_COUNT]; -extern double beta2_dlsch_MI[6][MCS_COUNT]; +extern const double beta1_dlsch_MI[6][MCS_COUNT]; +extern const double beta2_dlsch_MI[6][MCS_COUNT]; -extern double q_qpsk[8]; -extern double q_qam16[8]; -extern double q_qam64[8]; +extern const double q_qpsk[8]; +extern const double q_qam16[8]; +extern const double q_qam64[8]; -extern double p_qpsk[8]; -extern double p_qam16[8]; -extern double p_qam64[8]; +extern const double p_qpsk[8]; +extern const double p_qam16[8]; +extern const double p_qam64[8]; -extern double beta1_dlsch[6][MCS_COUNT]; -extern double beta2_dlsch[6][MCS_COUNT]; +extern const double beta1_dlsch[6][MCS_COUNT]; +extern const double beta2_dlsch[6][MCS_COUNT]; -extern char NB_functions[7][20]; -extern char NB_timing[2][20]; -extern char ru_if_types[MAX_RU_IF_TYPES][20]; +extern const char NB_functions[7][20]; +extern const char NB_timing[2][20]; +extern const char ru_if_types[MAX_RU_IF_TYPES][20]; extern int16_t unscrambling_lut[65536*16]; extern uint8_t scrambling_lut[65536*16]; diff --git a/openair1/PHY/phy_vars.h b/openair1/PHY/phy_vars.h index 26540f6fc8..a74d148479 100644 --- a/openair1/PHY/phy_vars.h +++ b/openair1/PHY/phy_vars.h @@ -50,8 +50,8 @@ unsigned short rev[2048],rev_times4[8192],rev_half[1024]; unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192]; -short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1}; -short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; +const short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1}; +const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; #include "SIMULATION/ETH_TRANSPORT/vars.h" @@ -84,29 +84,29 @@ double MI_map_16qam[3][197]; double MI_map_64qam[3][227]; // here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs -double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424}, +const double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424}, {-2.2360, -2.2360, -1.3919, -0.0218, 1.5319, 2.9574, 4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572}, {-1, -1.0000, -0.4198, -0.0140, 1.0362, 2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392}, { -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545} }; //int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27}; -int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28}; +const int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28}; //for SNR to MI conversion 7 th order Polynomial coeff -double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639}; -double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425}; -double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898}; +const double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639}; +const double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425}; +const double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898}; //for MI to SNR conversion 7 th order Polynomial coeff -double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965}; -double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089}; -double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343}; +const double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965}; +const double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089}; +const double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343}; // ideal CE MIESM -double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}}; -double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}}; +const double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}}; +const double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}}; //real CE MIESM /* @@ -116,8 +116,8 @@ double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.8 //ideal channel estimation values //double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; //double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; -double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; -double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; +const double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; +const double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; //real channel estimation valus /* @@ -126,13 +126,9 @@ double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.1682 */ -#ifdef OCP_FRAMEWORK -#include -#else -char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",}; -char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"}; -char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"}; -#endif +const char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",}; +const char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"}; +const char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"}; /// lookup table for unscrambling in RX int16_t unscrambling_lut[65536*16] __attribute__((aligned(32))); diff --git a/openair1/PHY/phy_vars_nr_ue.h b/openair1/PHY/phy_vars_nr_ue.h index bd077b5b0c..1843d8d5bc 100644 --- a/openair1/PHY/phy_vars_nr_ue.h +++ b/openair1/PHY/phy_vars_nr_ue.h @@ -49,8 +49,8 @@ unsigned short rev[2048],rev_times4[8192],rev_half[1024]; unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192]; -short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1}; -short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; +const short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1}; +const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; #include "SIMULATION/ETH_TRANSPORT/vars.h" @@ -84,29 +84,29 @@ double MI_map_16qam[3][197]; double MI_map_64qam[3][227]; // here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs -double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424}, +const double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424}, {-2.2360, -2.2360, -1.3919, -0.0218, 1.5319, 2.9574, 4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572}, {-1, -1.0000, -0.4198, -0.0140, 1.0362, 2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392}, { -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545} }; //int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27}; -int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28}; +const int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28}; //for SNR to MI conversion 7 th order Polynomial coeff -double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639}; -double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425}; -double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898}; +const double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639}; +const double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425}; +const double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898}; //for MI to SNR conversion 7 th order Polynomial coeff -double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965}; -double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089}; -double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343}; +const double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965}; +const double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089}; +const double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343}; // ideal CE MIESM -double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}}; -double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}}; +const double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}}; +const double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}}; //real CE MIESM /* @@ -116,8 +116,8 @@ double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.8 //ideal channel estimation values //double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; //double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; -double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; -double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; +const double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; +const double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; //real channel estimation valus /* @@ -126,13 +126,9 @@ double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.1682 */ -#ifdef OCP_FRAMEWORK -#include -#else -char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",}; -char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"}; -char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"}; -#endif +const char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",}; +const char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"}; +const char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"}; /// lookup table for unscrambling in RX int16_t unscrambling_lut[65536*16] __attribute__((aligned(32))); diff --git a/openair1/PHY/phy_vars_ue.h b/openair1/PHY/phy_vars_ue.h index 05f2e1b8f1..e90c2641aa 100644 --- a/openair1/PHY/phy_vars_ue.h +++ b/openair1/PHY/phy_vars_ue.h @@ -19,8 +19,8 @@ * contact@openairinterface.org */ -#ifndef __PHY_VARS_H__ -#define __PHY_VARS_H__ +#ifndef __PHY_VARS_UE__H__ +#define __PHY_VARS_UE__H__ #include "PHY/types.h" #include "PHY/defs_UE.h" @@ -43,8 +43,8 @@ unsigned short rev[2048],rev_times4[8192],rev_half[1024]; unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192]; -short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1}; -short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; +const short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1}; +const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; #include "SIMULATION/ETH_TRANSPORT/vars.h" @@ -77,29 +77,29 @@ double MI_map_16qam[3][197]; double MI_map_64qam[3][227]; // here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs -double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424}, +const double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424}, {-2.2360, -2.2360, -1.3919, -0.0218, 1.5319, 2.9574, 4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572}, {-1, -1.0000, -0.4198, -0.0140, 1.0362, 2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392}, { -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545} }; //int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27}; -int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28}; +const int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28}; //for SNR to MI conversion 7 th order Polynomial coeff -double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639}; -double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425}; -double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898}; +const double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639}; +const double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425}; +const double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898}; //for MI to SNR conversion 7 th order Polynomial coeff -double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965}; -double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089}; -double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343}; +const double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965}; +const double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089}; +const double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343}; // ideal CE MIESM -double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}}; -double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}}; +const double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}}; +const double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}}; //real CE MIESM /* @@ -109,8 +109,8 @@ double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.8 //ideal channel estimation values //double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; //double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; -double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; -double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; +const double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}}; +const double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}}; //real channel estimation valus /* @@ -119,13 +119,9 @@ double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.1682 */ -#ifdef OCP_FRAMEWORK -#include -#else -char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",}; -char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"}; -char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"}; -#endif +const char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",}; +const char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"}; +const char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"}; /// lookup table for unscrambling in RX int16_t unscrambling_lut[65536*16] __attribute__((aligned(32))); @@ -133,4 +129,4 @@ int16_t unscrambling_lut[65536*16] __attribute__((aligned(32))); uint8_t scrambling_lut[65536*16] __attribute__((aligned(32))); uint8_t max_turbo_iterations=4; -#endif /*__PHY_VARS_H__ */ +#endif /* __PHY_VARS_UE__H__ */ diff --git a/openair1/SCHED/fapi_l1.c b/openair1/SCHED/fapi_l1.c index 8105877bc3..96a073fbb8 100644 --- a/openair1/SCHED/fapi_l1.c +++ b/openair1/SCHED/fapi_l1.c @@ -596,7 +596,7 @@ void handle_uci_sr_pdu(PHY_VARS_eNB *eNB, uci->frame = frame; uci->subframe = subframe; uci->rnti = ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti; - uci->ue_id = find_dlsch(ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE); + uci->ue_id = find_ulsch(ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE); uci->type = SR; uci->pucch_fmt = pucch_format1; uci->num_antenna_ports = 1; @@ -622,7 +622,7 @@ void handle_uci_sr_harq_pdu(PHY_VARS_eNB *eNB,int UE_id,nfapi_ul_config_request_ uci->frame = frame; uci->subframe = subframe; uci->rnti = ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti; - uci->ue_id = find_dlsch(ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE); + uci->ue_id = find_ulsch(ul_config_pdu->uci_sr_harq_pdu.ue_information.ue_information_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE); uci->type = HARQ_SR; uci->num_antenna_ports = 1; uci->num_pucch_resources = 1; @@ -644,7 +644,7 @@ void handle_uci_harq_pdu(PHY_VARS_eNB *eNB,int UE_id,nfapi_ul_config_request_pdu uci->frame = frame; uci->subframe = subframe; uci->rnti = ul_config_pdu->uci_harq_pdu.ue_information.ue_information_rel8.rnti; - uci->ue_id = find_dlsch(ul_config_pdu->uci_harq_pdu.ue_information.ue_information_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE); + uci->ue_id = find_ulsch(ul_config_pdu->uci_harq_pdu.ue_information.ue_information_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE); uci->type = HARQ; uci->srs_active = srs_active; uci->num_antenna_ports = ul_config_pdu->uci_harq_pdu.harq_information.harq_information_rel11.num_ant_ports; @@ -732,7 +732,7 @@ void handle_nfapi_ul_pdu(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_CQI_SR_PDU_TYPE) { AssertFatal(1==0,"NFAPI_UL_CONFIG_UCI_CQI_SR_PDU_TYPE not handled yet\n"); } else if (ul_config_pdu->pdu_type == NFAPI_UL_CONFIG_UCI_SR_PDU_TYPE) { - AssertFatal((UE_id = find_uci(ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti, + AssertFatal((UE_id = find_uci(ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti, proc->frame_tx,proc->subframe_tx,eNB,SEARCH_EXIST_OR_FREE))>=0, "No available UE UCI for rnti %x\n",ul_config_pdu->uci_sr_pdu.ue_information.ue_information_rel8.rnti); handle_uci_sr_pdu(eNB,UE_id,ul_config_pdu,frame,subframe,srs_present); @@ -745,9 +745,8 @@ void handle_nfapi_ul_pdu(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, } } -void schedule_response(Sched_Rsp_t *Sched_INFO) { +void schedule_response(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc) { PHY_VARS_eNB *eNB; - L1_rxtx_proc_t *proc; // copy data from L2 interface into L1 structures module_id_t Mod_id = Sched_INFO->module_id; uint8_t CC_id = Sched_INFO->CC_id; @@ -767,7 +766,6 @@ void schedule_response(Sched_Rsp_t *Sched_INFO) { AssertFatal(RC.eNB[Mod_id][CC_id]!=NULL,"RC.eNB[%d][%d] is null\n",Mod_id,CC_id); eNB = RC.eNB[Mod_id][CC_id]; fp = &eNB->frame_parms; - proc = &eNB->proc.L1_proc; /* TODO: check that following line is correct - in the meantime it is disabled */ //if ((fp->frame_type == TDD) && (subframe_select(fp,subframe)==SF_UL)) return; ul_subframe = pdcch_alloc2ul_subframe(fp,subframe); @@ -1020,11 +1018,11 @@ void schedule_response(Sched_Rsp_t *Sched_INFO) { /*Dummy functions*/ -int memcpy_dl_config_req (nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request_t *req) { +int memcpy_dl_config_req (L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request_t *req) { return 0; } -int memcpy_ul_config_req (nfapi_pnf_p7_config_t *pnf_p7, nfapi_ul_config_request_t *req) { +int memcpy_ul_config_req (L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7, nfapi_ul_config_request_t *req) { return 0; } diff --git a/openair1/SCHED/fapi_l1.h b/openair1/SCHED/fapi_l1.h index 05ec813917..4da1fa63ec 100644 --- a/openair1/SCHED/fapi_l1.h +++ b/openair1/SCHED/fapi_l1.h @@ -37,10 +37,10 @@ #include "SCHED/sched_common.h" #include "nfapi_interface.h" -void fill_uci_harq_indication(PHY_VARS_eNB *eNB,LTE_eNB_UCI *uci,int frame,int subframe,uint8_t *harq_ack,uint8_t tdd_mapping_mode,uint16_t tdd_multiplexing_mask); +void fill_uci_harq_indication(int UEid, PHY_VARS_eNB *eNB,LTE_eNB_UCI *uci,int frame,int subframe,uint8_t *harq_ack,uint8_t tdd_mapping_mode,uint16_t tdd_multiplexing_mask); void fill_ulsch_harq_indication(PHY_VARS_eNB *eNB,LTE_UL_eNB_HARQ_t *ulsch_harq,uint16_t rnti, int frame,int subframe,int bundling); void fill_ulsch_cqi_indication(PHY_VARS_eNB *eNB,uint16_t frame,uint8_t subframe,LTE_UL_eNB_HARQ_t *ulsch_harq,uint16_t rnti); -void fill_sr_indication(PHY_VARS_eNB *eNB,uint16_t rnti,int frame,int subframe,uint32_t stat); +void fill_sr_indication(int UEid, PHY_VARS_eNB *eNB,uint16_t rnti,int frame,int subframe,uint32_t stat); void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe); void fill_crc_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe,uint8_t crc_flag); void handle_nfapi_dci_dl_pdu(PHY_VARS_eNB *eNB,int frame,int subframe,L1_rxtx_proc_t *proc,nfapi_dl_config_request_pdu_t *dl_config_pdu); @@ -81,4 +81,4 @@ void handle_uci_harq_pdu(PHY_VARS_eNB *eNB,int UE_id,nfapi_ul_config_request_pdu void handle_srs_pdu(PHY_VARS_eNB *eNB,nfapi_ul_config_request_pdu_t *ul_config_pdu,uint16_t frame,uint8_t subframe); -void schedule_response(Sched_Rsp_t *Sched_INFO); +void schedule_response(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc); diff --git a/openair1/SCHED/phy_procedures_lte_eNb.c b/openair1/SCHED/phy_procedures_lte_eNb.c index 34d5a01590..ba03e79e62 100644 --- a/openair1/SCHED/phy_procedures_lte_eNb.c +++ b/openair1/SCHED/phy_procedures_lte_eNb.c @@ -47,6 +47,7 @@ #include #include "intertask_interface.h" +#include #define MBMS_NFAPI_SCHEDULER @@ -303,6 +304,7 @@ bool dlsch_procedures(PHY_VARS_eNB *eNB, start_meas(&eNB->dlsch_encoding_stats); dlsch_encoding_all(eNB, + proc, dlsch_harq->pdu, dlsch_harq->pdsch_start, dlsch, @@ -317,6 +319,14 @@ bool dlsch_procedures(PHY_VARS_eNB *eNB, &eNB->dlsch_interleaving_stats); stop_meas(&eNB->dlsch_encoding_stats); + if ( proc->threadPool->activated ) { + // Wait all other threads finish to process + while (proc->nbEncode) { + delNotifiedFIFO_elt(pullTpool(proc->respEncode, proc->threadPool)); + proc->nbEncode--; + } + } + if(eNB->dlsch_encoding_stats.p_time>500*3000 && opp_enabled == 1) { print_meas_now(&eNB->dlsch_encoding_stats,"total coding",stderr); } @@ -431,6 +441,7 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB, if (ul_subframe < 10) { // This means that there is a potential UL subframe that will be scheduled here for (i=0; iulsch[i] && eNB->ulsch[i]->ue_type >0) harq_pid = 0; + else harq_pid = subframe2harq_pid(fp,ul_frame,ul_subframe); @@ -591,7 +602,12 @@ void srs_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { } } -void fill_sr_indication(PHY_VARS_eNB *eNB,uint16_t rnti,int frame,int subframe,uint32_t stat) { +void fill_sr_indication(int UEid, PHY_VARS_eNB *eNB,uint16_t rnti,int frame,int subframe,uint32_t stat) { + if ( split73 == SPLIT73_DU ) { + sendFs6Ulharq(fs6ULindicationSr, UEid, eNB, NULL, frame, subframe, NULL,0,0, rnti, stat); + return; + } + pthread_mutex_lock(&eNB->UL_INFO_mutex); nfapi_sr_indication_t *sr_ind = &eNB->UL_INFO.sr_ind; nfapi_sr_indication_body_t *sr_ind_body = &sr_ind->sr_indication_body; @@ -604,6 +620,7 @@ void fill_sr_indication(PHY_VARS_eNB *eNB,uint16_t rnti,int frame,int subframe,u pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; pdu->rx_ue_information.rnti = rnti; int SNRtimes10 = dB_fixed_times10(stat) - 10 * eNB->measurements.n0_subband_power_dB[0][0]; + LOG_D(PHY,"stat %d subbandpower %d, SNRtimes10 %d\n", stat, eNB->measurements.n0_subband_power_dB[0][0], SNRtimes10); pdu->ul_cqi_information.tl.tag = NFAPI_UL_CQI_INFORMATION_TAG; if (SNRtimes10 < -640) pdu->ul_cqi_information.ul_cqi=0; @@ -640,6 +657,10 @@ uci_procedures(PHY_VARS_eNB *eNB, uci = &(eNB->uci_vars[i]); if ((uci->active == 1) && (uci->frame == frame) && (uci->subframe == subframe)) { + if (uci->ue_id > MAX_MOBILES_PER_ENB) { + LOG_W(PHY, "UCI for UE %d and/or but is not active in MAC\n", uci->ue_id); + continue; + } LOG_D(PHY,"Frame %d, subframe %d: Running uci procedures (type %d) for %d \n", frame, subframe, @@ -710,7 +731,7 @@ uci_procedures(PHY_VARS_eNB *eNB, if (uci->type == SR) { if (SR_payload == 1) { - fill_sr_indication(eNB,uci->rnti,frame,subframe,metric_SR); + fill_sr_indication(i, eNB,uci->rnti,frame,subframe,metric_SR); break; } else { break; @@ -744,7 +765,7 @@ uci_procedures(PHY_VARS_eNB *eNB, /* cancel SR detection if reception on n1_pucch0 is better than on SR PUCCH resource index, otherwise send it up to MAC */ if (uci->type==HARQ_SR && metric[0] > metric_SR) SR_payload = 0; - else if (SR_payload == 1) fill_sr_indication(eNB,uci->rnti,frame,subframe,metric_SR); + else if (SR_payload == 1) fill_sr_indication(i, eNB,uci->rnti,frame,subframe,metric_SR); if (uci->type==HARQ_SR && metric[0] <= metric_SR) { /* when transmitting ACK/NACK on SR PUCCH resource index, SR payload is always 1 */ @@ -769,7 +790,7 @@ uci_procedures(PHY_VARS_eNB *eNB, frame,subframe, pucch_b0b1[0][0],metric[0]); uci->stat = metric[0]; - fill_uci_harq_indication(eNB,uci,frame,subframe,pucch_b0b1[0],0,0xffff); + fill_uci_harq_indication(i, eNB,uci,frame,subframe,pucch_b0b1[0],0,0xffff); } else { // frame_type == TDD LOG_D(PHY,"Frame %d Subframe %d Demodulating PUCCH (UCI %d) for ACK/NAK (uci->pucch_fmt %d,uci->type %d.uci->frame %d, uci->subframe %d): n1_pucch0 %d SR_payload %d\n", frame,subframe,i, @@ -791,7 +812,7 @@ uci_procedures(PHY_VARS_eNB *eNB, ); if (uci->type==HARQ_SR && metric[0] > metric_SR) SR_payload = 0; - else if (SR_payload == 1) fill_sr_indication(eNB,uci->rnti,frame,subframe,metric_SR); + else if (SR_payload == 1) fill_sr_indication(i, eNB,uci->rnti,frame,subframe,metric_SR); if (uci->type==HARQ_SR && metric[0] <= metric_SR) { SR_payload = 1; @@ -873,7 +894,7 @@ uci_procedures(PHY_VARS_eNB *eNB, } uci->stat = metric[0]; - fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,2,0xffff); // special_bundling mode + fill_uci_harq_indication(i, eNB,uci,frame,subframe,harq_ack,2,0xffff); // special_bundling mode } else if ((uci->tdd_bundling == 0) && (uci->num_pucch_resources==2)) { // multiplexing + no SR, implement Table 10.1.3-5 (Rel14) for multiplexing with M=2 if (pucch_b0b1[0][0] == 4 || pucch_b0b1[1][0] == 4) { // there isn't a likely transmission @@ -909,7 +930,7 @@ uci_procedures(PHY_VARS_eNB *eNB, } uci->stat = max(metric[0],metric[1]); - fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode + fill_uci_harq_indication(i, eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode } //else if ((uci->tdd_bundling == 0) && (res==2)) else if ((uci->tdd_bundling == 0) && (uci->num_pucch_resources==3)) { // multiplexing + no SR, implement Table 10.1.3-6 (Rel14) for multiplexing with M=3 if (harq_ack[0] == 4 || @@ -980,7 +1001,7 @@ uci_procedures(PHY_VARS_eNB *eNB, } uci->stat = max_metric; - fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode + fill_uci_harq_indication(i, eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode } } //else if ((uci->tdd_bundling == 0) && (res==3)) else if ((uci->tdd_bundling == 0) && (uci->num_pucch_resources==4)) { // multiplexing + no SR, implement Table 10.1.3-7 (Rel14) for multiplexing with M=4 @@ -1102,14 +1123,14 @@ uci_procedures(PHY_VARS_eNB *eNB, } uci->stat = max_metric; - fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode + fill_uci_harq_indication(i, eNB,uci,frame,subframe,harq_ack,1,tdd_multiplexing_mask); // multiplexing mode } // else if ((uci->tdd_bundling == 0) && (res==4)) else { // bundling harq_ack[0] = pucch_b0b1[0][0]; harq_ack[1] = pucch_b0b1[0][1]; uci->stat = metric[0]; LOG_D(PHY,"bundling: (%d,%d), metric %d\n",harq_ack[0],harq_ack[1],uci->stat); - fill_uci_harq_indication(eNB,uci,frame,subframe,harq_ack,0,0xffff); // special_bundling mode + fill_uci_harq_indication(i, eNB,uci,frame,subframe,harq_ack,0,0xffff); // special_bundling mode } #ifdef DEBUG_PHY_PROC @@ -1140,8 +1161,93 @@ uci_procedures(PHY_VARS_eNB *eNB, } // end loop for (int i = 0; i < NUMBER_OF_UE_MAX; i++) { } +void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) { + turboDecode_t * rdata=(turboDecode_t *) NotifiedFifoData(req); + + LTE_eNB_ULSCH_t *ulsch = rdata->eNB->ulsch[rdata->UEid]; + LTE_UL_eNB_HARQ_t *ulsch_harq = rdata->ulsch_harq; + PHY_VARS_eNB *eNB=rdata->eNB; + + bool decodeSucess=rdata->decodeIterations <= rdata->maxIterations; + ulsch_harq->processedSegments++; + LOG_D(PHY, "processing result of segment: %d, ue %d, processed %d/%d\n", + rdata->segment_r, rdata->UEid, ulsch_harq->processedSegments, rdata->nbSegments); + proc->nbDecode--; + LOG_D(PHY,"remain to decoded in subframe: %d\n", proc->nbDecode); + if (decodeSucess) { + int Fbytes=(rdata->segment_r==0) ? rdata->Fbits>>3 : 0; + int sz=(rdata->Kr>>3) - Fbytes - ((ulsch_harq->C>1)?3:0); + memcpy(ulsch_harq->decodedBytes+rdata->offset, + rdata->decoded_bytes+Fbytes, + sz); + } else { + if ( rdata->nbSegments != ulsch_harq->processedSegments ) { + int nb=abortTpool(proc->threadPool, req->key); + nb+=abortNotifiedFIFO(proc->respDecode, req->key); + proc->nbDecode-=nb; + LOG_I(PHY,"uplink segment error %d/%d, aborted %d segments\n",rdata->segment_r,rdata->nbSegments, nb); + AssertFatal(ulsch_harq->processedSegments+nb == rdata->nbSegments,"processed: %d, aborted: %d, total %d\n", + ulsch_harq->processedSegments, nb, rdata->nbSegments); + ulsch_harq->processedSegments=rdata->nbSegments; + } + } + + // if this UE segments are all done + if ( rdata->nbSegments == ulsch_harq->processedSegments) { + //compute the expected ULSCH RX power (for the stats) + int i=rdata->UEid; + ulsch_harq->delta_TF = get_hundred_times_delta_IF_eNB(eNB,i,rdata->harq_pid, 0); // 0 means bw_factor is not considered + if (RC.mac != NULL) { /* ulsim does not use RC.mac context. */ + if (ulsch_harq->cqi_crc_status == 1) { + fill_ulsch_cqi_indication(eNB,rdata->frame,rdata->subframe,ulsch_harq,ulsch->rnti); + RC.mac[eNB->Mod_id]->UE_info.UE_sched_ctrl[i].cqi_req_flag &= (~(1 << rdata->subframe)); + } else { + if(RC.mac[eNB->Mod_id]->UE_info.UE_sched_ctrl[i].cqi_req_flag & (1 << rdata->subframe) ) { + RC.mac[eNB->Mod_id]->UE_info.UE_sched_ctrl[i].cqi_req_flag &= (~(1 << rdata->subframe)); + RC.mac[eNB->Mod_id]->UE_info.UE_sched_ctrl[i].cqi_req_timer=30; + LOG_D(PHY,"Frame %d,Subframe %d, We're supposed to get a cqi here. Set cqi_req_timer to 30.\n",rdata->frame,rdata->subframe); + } + } + } + + if (!decodeSucess) { + fill_crc_indication(eNB,i,rdata->frame,rdata->subframe,1); // indicate NAK to MAC + fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC + LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d UE %d Error receiving ULSCH, round %d/%d (ACK %d,%d)\n", + eNB->Mod_id,rdata->harq_pid, + rdata->frame,rdata->subframe, i, + ulsch_harq->round, + ulsch->Mlimit, + ulsch_harq->o_ACK[0], + ulsch_harq->o_ACK[1]); + + if (ulsch_harq->round >= 3) { + ulsch_harq->status = SCH_IDLE; + ulsch_harq->handled = 0; + ulsch->harq_mask &= ~(1 << rdata->harq_pid); + ulsch_harq->round = 0; + } + /* Mark the HARQ process to release it later if max transmission reached + * (see below). + * MAC does not send the max transmission count, we have to deal with it + * locally in PHY. + */ + ulsch_harq->handled = 1; + } // ulsch in error + else if(ulsch_harq->repetition_number == ulsch_harq->total_number_of_repetitions){ + fill_crc_indication(eNB,i,rdata->frame,rdata->subframe,0); // indicate ACK to MAC + fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC + ulsch_harq->status = SCH_IDLE; + ulsch->harq_mask &= ~(1 << rdata->harq_pid); + } // ulsch not in error + + if (ulsch_harq->O_ACK>0) + fill_ulsch_harq_indication(eNB,ulsch_harq,ulsch->rnti,rdata->frame,rdata->subframe,ulsch->bundling); + } +} + void pusch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { - uint32_t ret=0,i; + uint32_t i; uint32_t harq_pid; uint8_t nPRS; LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms; @@ -1150,7 +1256,6 @@ void pusch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { const int subframe = proc->subframe_rx; const int frame = proc->frame_rx; uint32_t harq_pid0 = subframe2harq_pid(&eNB->frame_parms,frame,subframe); - int rvidx_tab[4] = {0,2,3,1}; for (i = 0; i < NUMBER_OF_UE_MAX; i++) { ulsch = eNB->ulsch[i]; @@ -1204,127 +1309,13 @@ void pusch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { rx_ulsch(eNB,proc, i); stop_meas(&eNB->ulsch_demodulation_stats); start_meas(&eNB->ulsch_decoding_stats); - ret = ulsch_decoding(eNB,proc, + ulsch_decoding(eNB,proc, i, 0, // control_only_flag ulsch_harq->V_UL_DAI, ulsch_harq->nb_rb>20 ? 1 : 0); stop_meas(&eNB->ulsch_decoding_stats); - LOG_D(PHY, - "[eNB %d][PUSCH %d] frame %d subframe %d RNTI %x RX power (%d,%d) N0 (%d,%d) dB ACK (%d,%d), decoding iter %d ulsch_harq->cqi_crc_status:%d ackBits:%d ulsch_decoding_stats[t:%lld max:%lld]\n", - eNB->Mod_id,harq_pid, - frame,subframe, - ulsch->rnti, - dB_fixed(eNB->pusch_vars[i]->ulsch_power[0]), - dB_fixed(eNB->pusch_vars[i]->ulsch_power[1]), - 30,//eNB->measurements.n0_power_dB[0], - 30,//eNB->measurements.n0_power_dB[1], - ulsch_harq->o_ACK[0], - ulsch_harq->o_ACK[1], - ret, - ulsch_harq->cqi_crc_status, - ulsch_harq->O_ACK, - eNB->ulsch_decoding_stats.p_time, eNB->ulsch_decoding_stats.max); - if (ulsch_harq->repetition_number < ulsch_harq->total_number_of_repetitions){ - ulsch_harq->rvidx = rvidx_tab[(ulsch_harq->repetition_number%4)] ; // Set the correct rvidx for the next emtc repetitions - ulsch_harq->repetition_number +=1 ; // Increment repetition_number for the next ULSCH allocation - } - //compute the expected ULSCH RX power (for the stats) - ulsch_harq->delta_TF = get_hundred_times_delta_IF_eNB(eNB,i,harq_pid, 0); // 0 means bw_factor is not considered - - if (RC.mac != NULL) { /* ulsim does not use RC.mac context. */ - if (ulsch_harq->cqi_crc_status == 1) { -#ifdef DEBUG_PHY_PROC - //if (((frame%10) == 0) || (frame < 50)) - print_CQI(ulsch_harq->o,ulsch_harq->uci_format,0,fp->N_RB_DL); -#endif - fill_ulsch_cqi_indication(eNB,frame,subframe,ulsch_harq,ulsch->rnti); - RC.mac[eNB->Mod_id]->UE_list.UE_sched_ctrl[i].cqi_req_flag &= (~(1 << subframe)); - } else { - if(RC.mac[eNB->Mod_id]->UE_list.UE_sched_ctrl[i].cqi_req_flag & (1 << subframe) ) { - RC.mac[eNB->Mod_id]->UE_list.UE_sched_ctrl[i].cqi_req_flag &= (~(1 << subframe)); - RC.mac[eNB->Mod_id]->UE_list.UE_sched_ctrl[i].cqi_req_timer=30; - LOG_D(PHY,"Frame %d,Subframe %d, We're supposed to get a cqi here. Set cqi_req_timer to 30.\n",frame,subframe); - } - } - } - - if (ret == (1+MAX_TURBO_ITERATIONS)) { - T(T_ENB_PHY_ULSCH_UE_NACK, T_INT(eNB->Mod_id), T_INT(frame), T_INT(subframe), T_INT(ulsch->rnti), - T_INT(harq_pid)); - fill_crc_indication(eNB,i,frame,subframe,1); // indicate NAK to MAC - fill_rx_indication(eNB,i,frame,subframe); // indicate SDU to MAC - LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d UE %d Error receiving ULSCH, round %d/%d (ACK %d,%d)\n", - eNB->Mod_id,harq_pid, - frame,subframe, i, - ulsch_harq->round, - ulsch->Mlimit, - ulsch_harq->o_ACK[0], - ulsch_harq->o_ACK[1]); - - if (ulsch_harq->round >= 3) { - ulsch_harq->status = SCH_IDLE; - ulsch_harq->handled = 0; - ulsch->harq_mask &= ~(1 << harq_pid); - ulsch_harq->round = 0; - } - - MSC_LOG_RX_DISCARDED_MESSAGE( - MSC_PHY_ENB,MSC_PHY_UE, - NULL,0, - "%05u:%02u ULSCH received rnti %x harq id %u round %d", - frame,subframe, - ulsch->rnti,harq_pid, - ulsch_harq->round-1 - ); - /* Mark the HARQ process to release it later if max transmission reached - * (see below). - * MAC does not send the max transmission count, we have to deal with it - * locally in PHY. - */ - ulsch_harq->handled = 1; - } // ulsch in error - else if(ulsch_harq->repetition_number == ulsch_harq->total_number_of_repetitions){ - fill_crc_indication(eNB,i,frame,subframe,0); // indicate ACK to MAC - fill_rx_indication(eNB,i,frame,subframe); // indicate SDU to MAC - ulsch_harq->status = SCH_IDLE; - ulsch->harq_mask &= ~(1 << harq_pid); - T (T_ENB_PHY_ULSCH_UE_ACK, T_INT (eNB->Mod_id), T_INT (frame), T_INT (subframe), T_INT (ulsch->rnti), T_INT (harq_pid)); - MSC_LOG_RX_MESSAGE( - MSC_PHY_ENB,MSC_PHY_UE, - NULL,0, - "%05u:%02u ULSCH received rnti %x harq id %u", - frame,subframe, - ulsch->rnti,harq_pid - ); -#ifdef DEBUG_PHY_PROC -#ifdef DEBUG_ULSCH - LOG_D(PHY,"[eNB] Frame %d, Subframe %d : ULSCH SDU (RX harq_pid %d) %d bytes:",frame,subframe, - harq_pid,ulsch_harq->TBS>>3); - - for (j=0; jTBS>>3; j++) - LOG_T(PHY,"%x.",ulsch->harq_processes[harq_pid]->b[j]); - - LOG_T(PHY,"\n"); -#endif -#endif - } // ulsch not in error - - if (ulsch_harq->O_ACK>0) fill_ulsch_harq_indication(eNB,ulsch_harq,ulsch->rnti,frame,subframe,ulsch->bundling); - - LOG_D(PHY,"[eNB %d] Frame %d subframe %d: received ULSCH harq_pid %d for UE %d, ret = %d, CQI CRC Status %d, ACK %d,%d, ulsch_errors %d/%d\n", - eNB->Mod_id,frame,subframe, - harq_pid, - i, - ret, - ulsch_harq->cqi_crc_status, - ulsch_harq->o_ACK[0], - ulsch_harq->o_ACK[1], - eNB->UE_stats[i].ulsch_errors[harq_pid], - eNB->UE_stats[i].ulsch_decoding_attempts[harq_pid][0]); - } // if ((ulsch) && - // (ulsch->rnti>0) && - // (ulsch_harq->status == ACTIVE)) + } else if ((ulsch) && (ulsch->rnti>0) && (ulsch_harq->status == ACTIVE) && @@ -1338,6 +1329,12 @@ void pusch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { LOG_W (PHY, "Removing stale ULSCH config for UE %x harq_pid %d (harq_mask is now 0x%2.2x)\n", ulsch->rnti, harq_pid, ulsch->harq_mask); } } // for (i=0; inbDecode > 0) { + notifiedFIFO_elt_t *req=pullTpool(proc->respDecode, proc->threadPool); + postDecode(proc, req); + delNotifiedFIFO_elt(req); + } } extern int oai_exit; @@ -1345,24 +1342,29 @@ extern int oai_exit; extern void *td_thread (void *); void init_td_thread(PHY_VARS_eNB *eNB) { + /* L1_proc_t *proc = &eNB->proc; proc->tdp.eNB = eNB; proc->instance_cnt_td = -1; threadCreate(&proc->pthread_td, td_thread, (void *)&proc->tdp, "TD", -1, OAI_PRIORITY_RT); + */ } void kill_td_thread(PHY_VARS_eNB *eNB) { + /* L1_proc_t *proc = &eNB->proc; proc->instance_cnt_td = 0; pthread_cond_signal(&proc->cond_td); pthread_join(proc->pthread_td, NULL); pthread_mutex_destroy( &proc->mutex_td ); pthread_cond_destroy( &proc->cond_td ); + */ } extern void *te_thread (void *); void init_te_thread(PHY_VARS_eNB *eNB) { + /* L1_proc_t *proc = &eNB->proc; for(int i=0; i<3 ; i++) { @@ -1373,9 +1375,11 @@ void init_te_thread(PHY_VARS_eNB *eNB) { sprintf(txt,"TE_%d", i); threadCreate(&proc->tep[i].pthread_te, te_thread, (void *)&proc->tep[i], txt, -1, OAI_PRIORITY_RT); } + */ } void kill_te_thread(PHY_VARS_eNB *eNB) { + /* L1_proc_t *proc = &eNB->proc; for(int i=0; i<3 ; i++) { @@ -1385,6 +1389,7 @@ void kill_te_thread(PHY_VARS_eNB *eNB) { pthread_mutex_destroy( &proc->tep[i].mutex_te); pthread_cond_destroy( &proc->tep[i].cond_te); } + */ } void fill_rx_indication(PHY_VARS_eNB *eNB, @@ -1412,7 +1417,7 @@ void fill_rx_indication(PHY_VARS_eNB *eNB, pdu->rx_indication_rel8.tl.tag = NFAPI_RX_INDICATION_REL8_TAG; pdu->rx_indication_rel8.length = eNB->ulsch[UE_id]->harq_processes[harq_pid]->TBS>>3; pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation - pdu->data = eNB->ulsch[UE_id]->harq_processes[harq_pid]->b; + pdu->data = eNB->ulsch[UE_id]->harq_processes[harq_pid]->decodedBytes; // estimate timing advance for MAC sync_pos = lte_est_timing_advance_pusch(eNB,UE_id); timing_advance_update = sync_pos; // - eNB->frame_parms.nb_prefix_samples/4; //to check @@ -1745,7 +1750,12 @@ void fill_ulsch_harq_indication (PHY_VARS_eNB *eNB, LTE_UL_eNB_HARQ_t *ulsch_har pthread_mutex_unlock(&eNB->UL_INFO_mutex); } -void fill_uci_harq_indication (PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask) { +void fill_uci_harq_indication (int UEid, PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask) { + if ( split73 == SPLIT73_DU ) { + sendFs6Ulharq(fs6ULindicationHarq, UEid, eNB, uci, frame, subframe, harq_ack, tdd_mapping_mode, tdd_multiplexing_mask, 0, 0); + return; + } + int UE_id=find_dlsch(uci->rnti,eNB,SEARCH_EXIST); //AssertFatal(UE_id>=0,"UE_id doesn't exist rnti:%x\n", uci->rnti); diff --git a/openair1/SCHED/ru_procedures.c b/openair1/SCHED/ru_procedures.c index 6d392b0437..8846b77af9 100644 --- a/openair1/SCHED/ru_procedures.c +++ b/openair1/SCHED/ru_procedures.c @@ -321,7 +321,7 @@ void feptx_ofdm(RU_t *ru, fp->nb_prefix_samples, CYCLIC_PREFIX); } else { - if(is_pmch_subframe(ru->proc.frame_tx,subframe,fp)/*subframe==1*/){ + if(is_pmch_subframe(frame,subframe,fp)/*subframe==1*/){ normal_prefix_mod(&ru->common.txdataF_BF[aa][0], dummy_tx_b, 2, @@ -426,7 +426,7 @@ void feptx_ofdm(RU_t *ru, stop_meas(&ru->ofdm_mod_stats); LOG_D(PHY,"feptx_ofdm (TXPATH): frame %d, subframe %d: txp (time %p) %d dB, txp (freq) %d dB\n", - ru->proc.frame_tx,subframe,txdata,dB_fixed(signal_energy((int32_t*)txdata,fp->samples_per_tti)), + frame,subframe,txdata,dB_fixed(signal_energy((int32_t*)txdata,fp->samples_per_tti)), dB_fixed(signal_energy_nodc(ru->common.txdataF_BF[aa],2*slot_sizeF))); } } diff --git a/openair1/SCHED/sched_common.h b/openair1/SCHED/sched_common.h index e9af869b05..f3e43d516e 100644 --- a/openair1/SCHED/sched_common.h +++ b/openair1/SCHED/sched_common.h @@ -311,7 +311,7 @@ void get_cqipmiri_params(PHY_VARS_UE *ue,uint8_t eNB_id); int8_t get_PHR(uint8_t Mod_id, uint8_t CC_id, uint8_t eNB_index); -void schedule_response(Sched_Rsp_t *Sched_INFO); +void schedule_response(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc); LTE_eNB_UE_stats* get_UE_stats(uint8_t Mod_id, uint8_t CC_id,uint16_t rnti); diff --git a/openair1/SCHED/sched_eNB.h b/openair1/SCHED/sched_eNB.h index e74b9a312f..f04bec2e5c 100644 --- a/openair1/SCHED/sched_eNB.h +++ b/openair1/SCHED/sched_eNB.h @@ -128,8 +128,8 @@ void phy_procedures_eNB_S_RX(PHY_VARS_eNB *phy_vars_eNB,L1_rxtx_proc_t *proc); @param br_flag indicator for eMTC PRACH */ -void prach_procedures(PHY_VARS_eNB *eNB, - int br_flag); +void prach_procedures(PHY_VARS_eNB *eNB, + int br_flag); /*! \brief Function to compute timing of Msg3 transmission on UL-SCH (first UE transmission in RA procedure). This implements the timing in paragraph a) from Section 6.1.1 in 36.213 (p. 17 in version 8.6). Used by eNB upon transmission of random-access response (RA_RNTI) to program corresponding ULSCH reception procedure. Used by UE upon reception of random-access response (RA_RNTI) to program corresponding ULSCH transmission procedure. This does not support the UL_delay field in RAR (always assumed to be 0). @@ -193,7 +193,7 @@ int8_t find_ue_ulsch(uint16_t rnti, PHY_VARS_eNB *phy_vars_eNB); -void schedule_response(Sched_Rsp_t *Sched_INFO); +void schedule_response(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc); LTE_eNB_UE_stats *get_UE_stats(uint8_t Mod_id, uint8_t CC_id,uint16_t rnti); @@ -218,8 +218,6 @@ int is_srs_occasion_common(LTE_DL_FRAME_PARMS *frame_parms,int frame_tx,int subf void compute_srs_pos(lte_frame_type_t frameType,uint16_t isrs,uint16_t *psrsPeriodicity,uint16_t *psrsOffset); void release_rnti_of_phy(module_id_t mod_id); - -void ru_fep_full_2thread(RU_t *ru, int subframe); /*@}*/ diff --git a/openair1/SCHED_NR/fapi_nr_l1.h b/openair1/SCHED_NR/fapi_nr_l1.h index 07509b3bb7..d66d6e7b24 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.h +++ b/openair1/SCHED_NR/fapi_nr_l1.h @@ -46,6 +46,5 @@ void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu); -void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t harq_pid); -void nr_fill_crc_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t crc_flag); +void nr_fill_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t harq_pid, uint8_t crc_flag); diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index b9a8ba94f1..9054ddbae5 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -32,7 +32,7 @@ #include "PHY/defs_gNB.h" #include "PHY/phy_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" #include "nfapi_nr_interface_scf.h" #include "fapi_nr_l1.h" #include "nfapi_pnf.h" @@ -47,17 +47,19 @@ #include "intertask_interface.h" -extern uint32_t nfapi_mode; +extern uint8_t nfapi_mode; extern int oai_nfapi_nr_rach_ind(nfapi_rach_indication_t *rach_ind); -void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { - uint16_t max_preamble[4],max_preamble_energy[4],max_preamble_delay[4]; +void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, + nfapi_nr_prach_pdu_t *prach_pdu) { + + uint16_t max_preamble[4]={0},max_preamble_energy[4]={0},max_preamble_delay[4]={0}; uint16_t i; - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles=0; + gNB->UL_INFO.rach_ind.number_of_pdus=0; RU_t *ru; int aa=0; @@ -75,16 +77,18 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { } } - rx_nr_prach(gNB, + + /* rx_nr_prach(gNB, + prach_pdu, frame, - subframe, + slot, &max_preamble[0], &max_preamble_energy[0], &max_preamble_delay[0] - ); + );*/ - LOG_D(PHY,"[RAPROC] Frame %d, subframe %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", - frame,subframe, + LOG_D(PHY,"[RAPROC] Frame %d, slot %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", + frame,slot, max_preamble[0], max_preamble_energy[0]/10, max_preamble_delay[0], @@ -93,49 +97,43 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { if ((gNB->prach_energy_counter == 100) && (max_preamble_energy[0] > gNB->measurements.prach_I0+100)) { - LOG_I(PHY,"[gNB %d][RAPROC] Frame %d, subframe %d Initiating RA procedure with preamble %d, energy %d.%d dB, delay %d\n", + LOG_I(PHY,"[gNB %d][RAPROC] Frame %d, slot %d Initiating RA procedure with preamble %d, energy %d.%d dB, delay %d\n", gNB->Mod_id, frame, - subframe, + slot, max_preamble[0], max_preamble_energy[0]/10, max_preamble_energy[0]%10, max_preamble_delay[0]); - T(T_ENB_PHY_INITIATE_RA_PROCEDURE, T_INT(gNB->Mod_id), T_INT(frame), T_INT(subframe), + T(T_ENB_PHY_INITIATE_RA_PROCEDURE, T_INT(gNB->Mod_id), T_INT(frame), T_INT(slot), T_INT(max_preamble[0]), T_INT(max_preamble_energy[0]), T_INT(max_preamble_delay[0])); - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles = 1; - gNB->UL_INFO.rach_ind.rach_indication_body.preamble_list = &gNB->preamble_list[0]; - gNB->UL_INFO.rach_ind.rach_indication_body.tl.tag = NFAPI_RACH_INDICATION_BODY_TAG; - gNB->UL_INFO.rach_ind.header.message_id = NFAPI_RACH_INDICATION; - gNB->UL_INFO.rach_ind.sfn_sf = frame<<4 | subframe; + gNB->UL_INFO.rach_ind.number_of_pdus = 1; + gNB->UL_INFO.rach_ind.pdu_list = &gNB->prach_pdu_indication_list[0]; + gNB->UL_INFO.rach_ind.sfn = frame; + gNB->UL_INFO.rach_ind.slot = slot; - gNB->preamble_list[0].preamble_rel8.tl.tag = NFAPI_PREAMBLE_REL8_TAG; - gNB->preamble_list[0].preamble_rel8.timing_advance = max_preamble_delay[0]; - gNB->preamble_list[0].preamble_rel8.preamble = max_preamble[0]; - gNB->preamble_list[0].preamble_rel8.rnti = 1+subframe; // note: fid is implicitly 0 here - gNB->preamble_list[0].instance_length = 0; //don't know exactly what this is - - if (nfapi_mode == 1) { // If NFAPI PNF then we need to send the message to the VNF - - LOG_D(PHY,"Filling NFAPI indication for NR RACH : SFN_SF:%d TA %d, Preamble %d, rnti %x\n", - NFAPI_SFNSF2DEC(gNB->UL_INFO.rach_ind.sfn_sf), - gNB->preamble_list[0].preamble_rel8.timing_advance, - gNB->preamble_list[0].preamble_rel8.preamble, - gNB->preamble_list[0].preamble_rel8.rnti); - AssertFatal(1==0,"shouldn't be here yet..\n"); - //oai_nfapi_nr_rach_ind(&gNB->UL_INFO.rach_ind); - - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles = 0; - } - } // max_preamble_energy > prach_I0 + 100 - else { - gNB->measurements.prach_I0 = ((gNB->measurements.prach_I0*900)>>10) + ((max_preamble_energy[0]*124)>>10); - if (frame==0) LOG_I(PHY,"prach_I0 = %d.%d dB\n",gNB->measurements.prach_I0/10,gNB->measurements.prach_I0%10); - if (gNB->prach_energy_counter < 100) gNB->prach_energy_counter++; - } + gNB->prach_pdu_indication_list[0].phy_cell_id = gNB->gNB_config.cell_config.phy_cell_id.value; + gNB->prach_pdu_indication_list[0].symbol_index = prach_pdu->prach_start_symbol; // FIXME to be changed for multi-ssb (this is only the start symbol of first occasion) + gNB->prach_pdu_indication_list[0].slot_index = slot; + gNB->prach_pdu_indication_list[0].freq_index = prach_pdu->num_ra; + gNB->prach_pdu_indication_list[0].avg_rssi = (max_preamble_energy[0]<631) ? (128+(max_preamble_energy[0]/5)) : 254; + gNB->prach_pdu_indication_list[0].avg_snr = 0xff; // invalid for now + + + gNB->prach_pdu_indication_list[0].num_preamble = 1; + gNB->prach_pdu_indication_list[0].preamble_list = gNB->preamble_list; + gNB->prach_pdu_indication_list[0].preamble_list[0].preamble_index = max_preamble[0]; + gNB->prach_pdu_indication_list[0].preamble_list[0].timing_advance = max_preamble_delay[0]; + gNB->prach_pdu_indication_list[0].preamble_list[0].preamble_pwr = 0xffffffff; + } + gNB->measurements.prach_I0 = ((gNB->measurements.prach_I0*900)>>10) + ((max_preamble_energy[0]*124)>>10); + if (frame==0) LOG_I(PHY,"prach_I0 = %d.%d dB\n",gNB->measurements.prach_I0/10,gNB->measurements.prach_I0%10); + if (gNB->prach_energy_counter < 100) gNB->prach_energy_counter++; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PRACH_RX,0); } + diff --git a/openair1/SCHED_NR/phy_frame_config_nr.c b/openair1/SCHED_NR/phy_frame_config_nr.c index fa22e43661..a36cebd6ae 100644 --- a/openair1/SCHED_NR/phy_frame_config_nr.c +++ b/openair1/SCHED_NR/phy_frame_config_nr.c @@ -202,7 +202,7 @@ int set_tdd_config_nr( nfapi_nr_config_request_scf_t *cfg, void add_tdd_dedicated_configuration_nr(NR_DL_FRAME_PARMS *frame_parms, int slotIndex, int nrofDownlinkSymbols, int nrofUplinkSymbols) { TDD_UL_DL_SlotConfig_t *p_TDD_UL_DL_ConfigDedicated = frame_parms->p_TDD_UL_DL_ConfigDedicated; - TDD_UL_DL_SlotConfig_t *p_previous_TDD_UL_DL_ConfigDedicated; + TDD_UL_DL_SlotConfig_t *p_previous_TDD_UL_DL_ConfigDedicated=NULL; int next = 0; while (p_TDD_UL_DL_ConfigDedicated != NULL) { diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index d9a7ee3c69..60f9d4747a 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -28,6 +28,7 @@ #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_ESTIMATION/nr_ul_estimation.h" +#include "PHY/NR_UE_TRANSPORT/pucch_nr.h" #include "SCHED/sched_eNB.h" #include "sched_nr.h" #include "SCHED/sched_common_extern.h" @@ -242,16 +243,18 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH //------------------- ULSCH unscrambling ------------------- //---------------------------------------------------------- + start_meas(&gNB->ulsch_unscrambling_stats); nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr, G, 0, pusch_pdu->data_scrambling_id, pusch_pdu->rnti); - + stop_meas(&gNB->ulsch_unscrambling_stats); //---------------------------------------------------------- //--------------------- ULSCH decoding --------------------- //---------------------------------------------------------- + start_meas(&gNB->ulsch_decoding_stats); ret = nr_ulsch_decoding(gNB, ULSCH_id, gNB->pusch_vars[ULSCH_id]->llr, @@ -261,57 +264,30 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH slot_rx, harq_pid, G); + stop_meas(&gNB->ulsch_decoding_stats); - - if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations) + if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations){ LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id); - //gNB->ulsch[ULSCH_id+1][0]->harq_processes[harq_pid]->b + nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1); + } else if(gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->b!=NULL){ - LOG_I(PHY, "ULSCH received ok \n"); - if(IS_SOFTMODEM_NOS1){ //&& gNB->ulsch[ULSCH_id][0]->rnti == 0x1234 - nr_fill_crc_indication(gNB,frame_rx, slot_rx, ULSCH_id, 0); - nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - } + LOG_I(PHY, "ULSCH received ok \n"); + nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 0); } - } -void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_id, uint8_t harq_pid) -{ - // -------------------- - // [hna] TO BE CLEANED - // -------------------- +void nr_fill_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_id, uint8_t harq_pid, uint8_t crc_flag) { - nfapi_rx_indication_pdu_t *pdu; + pthread_mutex_lock(&gNB->UL_INFO_mutex); - int timing_advance_update; + int timing_advance_update, cqi; int sync_pos; - uint16_t mu = gNB->frame_parms.numerology_index; - // pthread_mutex_lock(&gNB->UL_INFO_mutex); NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ULSCH_id][0]; NR_UL_gNB_HARQ_t *harq_process = ulsch->harq_processes[harq_pid]; - pthread_mutex_lock(&gNB->UL_INFO_mutex); - - gNB->UL_INFO.rx_ind.sfn_sf = frame<<4| slot_rx; - gNB->UL_INFO.rx_ind.rx_indication_body.tl.tag = NFAPI_RX_INDICATION_BODY_TAG; - gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list->rx_indication_rel8.length = gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->TBS; - - pdu = &gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list[gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus]; - - //pdu->rx_ue_information.handle = gNB->ulsch[ULSCH_id+1][0]->handle; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = gNB->ulsch[ULSCH_id][0]->rnti; - pdu->rx_indication_rel8.tl.tag = NFAPI_RX_INDICATION_REL8_TAG; - pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation - pdu->data = harq_process->b;//gNB->ulsch[ULSCH_id+1][0]->harq_processes[harq_pid]->b; - // estimate timing advance for MAC - sync_pos = nr_est_timing_advance_pusch(gNB, ULSCH_id); - timing_advance_update = sync_pos; // - gNB->frame_parms.nb_prefix_samples/4; //to check - // printf("\x1B[33m" "timing_advance_update = %d\n" "\x1B[0m", timing_advance_update); - + nfapi_nr_pusch_pdu_t *pusch_pdu = &harq_process->ulsch_pdu; // pdu->data = gNB->ulsch[ULSCH_id+1][0]->harq_processes[harq_pid]->b; sync_pos = nr_est_timing_advance_pusch(gNB, ULSCH_id); // estimate timing advance for MAC @@ -335,39 +311,50 @@ void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_ LOG_D(PHY, "Estimated timing advance PUSCH is = %d, timing_advance_update is %d \n", sync_pos,timing_advance_update); - pdu->rx_indication_rel8.timing_advance = timing_advance_update; - // estimate UL_CQI for MAC (from antenna port 0 only) int SNRtimes10 = dB_fixed_times10(gNB->pusch_vars[ULSCH_id]->ulsch_power[0]) - 300;//(10*gNB->measurements.n0_power_dB[0]); - if (SNRtimes10 < -640) pdu->rx_indication_rel8.ul_cqi=0; - else if (SNRtimes10 > 635) pdu->rx_indication_rel8.ul_cqi=255; - else pdu->rx_indication_rel8.ul_cqi=(640+SNRtimes10)/5; + if (SNRtimes10 < -640) cqi=0; + else if (SNRtimes10 > 635) cqi=255; + else cqi=(640+SNRtimes10)/5; - // LOG_D(PHY,"[PUSCH %d] Frame %d Subframe %d Filling RX_indication with SNR %d (%d), timing_advance %d (update %d)\n", - // harq_pid,frame,slot_rx,SNRtimes10,pdu->rx_indication_rel8.ul_cqi,pdu->rx_indication_rel8.timing_advance, - // timing_advance_update); + // crc indication + uint16_t num_crc = gNB->UL_INFO.crc_ind.number_crcs; + gNB->UL_INFO.crc_ind.crc_list = &gNB->crc_pdu_list[0]; + gNB->UL_INFO.crc_ind.sfn = frame; + gNB->UL_INFO.crc_ind.slot = slot_rx; - gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus++; - gNB->UL_INFO.rx_ind.sfn_sf = frame<<4 | slot_rx; + gNB->crc_pdu_list[num_crc].handle = pusch_pdu->handle; + gNB->crc_pdu_list[num_crc].rnti = pusch_pdu->rnti; + gNB->crc_pdu_list[num_crc].harq_id = harq_pid; + gNB->crc_pdu_list[num_crc].tb_crc_status = crc_flag; + gNB->crc_pdu_list[num_crc].num_cb = pusch_pdu->pusch_data.num_cb; + gNB->crc_pdu_list[num_crc].ul_cqi = cqi; + gNB->crc_pdu_list[num_crc].timing_advance = timing_advance_update; + gNB->crc_pdu_list[num_crc].rssi = 0xffff; // invalid value as this is not yet computed - pthread_mutex_unlock(&gNB->UL_INFO_mutex); -} + gNB->UL_INFO.crc_ind.number_crcs++; + + // rx indication + uint16_t num_rx = gNB->UL_INFO.rx_ind.number_of_pdus; + gNB->UL_INFO.rx_ind.pdu_list = &gNB->rx_pdu_list[0]; + gNB->UL_INFO.rx_ind.sfn = frame; + gNB->UL_INFO.rx_ind.slot = slot_rx; + gNB->rx_pdu_list[num_rx].handle = pusch_pdu->handle; + gNB->rx_pdu_list[num_rx].rnti = pusch_pdu->rnti; + gNB->rx_pdu_list[num_rx].harq_id = harq_pid; + gNB->rx_pdu_list[num_rx].ul_cqi = cqi; + gNB->rx_pdu_list[num_rx].timing_advance = timing_advance_update; + gNB->rx_pdu_list[num_rx].rssi = 0xffff; // invalid value as this is not yet computed + if (crc_flag) + gNB->rx_pdu_list[num_rx].pdu_length = 0; + else { + gNB->rx_pdu_list[num_rx].pdu_length = harq_process->TBS; + gNB->rx_pdu_list[num_rx].pdu = harq_process->b; + } + + gNB->UL_INFO.rx_ind.number_of_pdus++; -void nr_fill_crc_indication (PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_id, uint8_t crc_flag) { - pthread_mutex_lock(&gNB->UL_INFO_mutex); - nfapi_crc_indication_pdu_t *pdu = &gNB->UL_INFO. crc_ind.crc_indication_body.crc_pdu_list[gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs]; - gNB->UL_INFO.crc_ind.sfn_sf = frame<<4 | slot_rx; - gNB->UL_INFO.crc_ind.header.message_id = NFAPI_CRC_INDICATION; - gNB->UL_INFO.crc_ind.crc_indication_body.tl.tag = NFAPI_CRC_INDICATION_BODY_TAG; - pdu->instance_length = 0; // don't know what to do with this - // pdu->rx_ue_information.handle = handle; - pdu->rx_ue_information.tl.tag = NFAPI_RX_UE_INFORMATION_TAG; - pdu->rx_ue_information.rnti = gNB->ulsch[ULSCH_id][0]->rnti; - pdu->crc_indication_rel8.tl.tag = NFAPI_CRC_INDICATION_REL8_TAG; - pdu->crc_indication_rel8.crc_flag = crc_flag; - gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs++; - //LOG_D(PHY, "%s() rnti:%04x crcs:%d crc_flag:%d\n", __FUNCTION__, pdu->rx_ue_information.rnti, eNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs, crc_flag); pthread_mutex_unlock(&gNB->UL_INFO_mutex); } @@ -393,34 +380,67 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; - int num_pusch_pdu = UL_tti_req->n_pdus; + nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; + int num_pdus = UL_tti_req->n_pdus; - LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pusch_pdu %d\n",frame_rx,slot_rx,num_pusch_pdu); + nfapi_nr_uci_indication_t *uci_indication = &gNB->uci_indication; + uci_indication->sfn = frame_rx; + uci_indication->slot = slot_rx; + uci_indication->num_ucis = 0; - gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; - for (int i = 0; i < num_pusch_pdu; i++) { + LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus); + + gNB->UL_INFO.rx_ind.number_of_pdus = 0; + gNB->UL_INFO.crc_ind.number_crcs = 0; + + for (int i = 0; i < num_pdus; i++) { switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:{ - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); - - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); - - uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); - uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; - uint8_t symbol_start = pusch_pdu->start_symbol_index; - uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; - - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: + { + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); + + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); + + uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); + uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; + uint8_t symbol_start = pusch_pdu->start_symbol_index; + uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; + + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC - nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); + break; + case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: + { + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx); + + nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[i].pucch_pdu; + switch (pucch_pdu->format_type) { + case 0: + uci_indication->uci_list[uci_indication->num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; + uci_indication->uci_list[uci_indication->num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &uci_indication->uci_list[uci_indication->num_ucis].pucch_pdu_format_0_1; + + nr_decode_pucch0(gNB, + slot_rx, + uci_pdu_format0, + pucch_pdu); + + uci_indication->num_ucis += 1; + break; + case 1: + break; + case 2: + break; + default: + AssertFatal(1==0,"Only PUCCH format 0,1 and 2 are currently supported\n"); + } } } } diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 69876159d6..7439c26eb7 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -116,16 +116,12 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) for(i=0; inumber_pdus; ++i){ if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH){ // pusch config pdu - fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15; - uint8_t current_harq_pid = pusch_config_pdu->harq_process_nbr; - ulsch0->harq_processes[current_harq_pid]->nb_rb = pusch_config_pdu->number_rbs; - ulsch0->harq_processes[current_harq_pid]->first_rb = pusch_config_pdu->start_rb; - ulsch0->harq_processes[current_harq_pid]->number_of_symbols = pusch_config_pdu->number_symbols; - ulsch0->harq_processes[current_harq_pid]->start_symbol = pusch_config_pdu->start_symbol; - ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs; - ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi; - ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv; - ulsch0->harq_processes[current_harq_pid]->Nl = pusch_config_pdu->n_layers; + nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu = &ul_config->ul_config_list[i].pusch_config_pdu; + uint8_t current_harq_pid = pusch_config_pdu->pusch_data.harq_process_id; + nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &ulsch0->harq_processes[current_harq_pid]->pusch_pdu; + + memcpy(pusch_pdu, pusch_config_pdu, sizeof(nfapi_nr_ue_pusch_pdu_t)); + ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; } if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){ diff --git a/openair1/SCHED_NR_UE/harq_nr.c b/openair1/SCHED_NR_UE/harq_nr.c index 31dcfcacbe..3c3017d658 100644 --- a/openair1/SCHED_NR_UE/harq_nr.c +++ b/openair1/SCHED_NR_UE/harq_nr.c @@ -296,7 +296,7 @@ harq_result_t uplink_harq_process(NR_UE_ULSCH_t *ulsch, int harq_pid, int ndi, u /* 38.321 5.4.2.1 2> if the uplink grant was received on PDCCH for the C-RNTI and the HARQ buffer of the identified process is empty */ if ((ulsch->harq_processes[harq_pid]->first_tx == 1) && (rnti_type == _C_RNTI_)) { /* no transmission yet on this process so consider its harq buffer as empty */ ulsch->harq_processes[harq_pid]->first_tx = 0; - ulsch->harq_processes[harq_pid]->DCINdi = ndi; /* store first value of ndi */ + ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator = ndi; /* store first value of ndi */ ulsch->harq_processes[harq_pid]->round = 0; ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1; @@ -306,8 +306,8 @@ harq_result_t uplink_harq_process(NR_UE_ULSCH_t *ulsch, int harq_pid, int ndi, u } /* 38.321 5.4.2.1 2> if the received grant was not addressed to a Temporary C-RNTI on PDCCH, and the NDI provided in the associated HARQ */ /* information has been toggled compared to the value in the previous transmission of this TB of this HARQ process */ - else if ((ulsch->harq_processes[harq_pid]->DCINdi != ndi) && (rnti_type != _TC_RNTI_)) { /* is ndi toogled so this is a new grant ? */ - ulsch->harq_processes[harq_pid]->DCINdi = ndi; /* store first value of ndi */ + else if ((ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator != ndi) && (rnti_type != _TC_RNTI_)) { /* is ndi toogled so this is a new grant ? */ + ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator = ndi; /* store first value of ndi */ ulsch->harq_processes[harq_pid]->round = 0; ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1; @@ -317,7 +317,7 @@ harq_result_t uplink_harq_process(NR_UE_ULSCH_t *ulsch, int harq_pid, int ndi, u } /* 38.321 5.4.2.1 2> else (i.e. retransmission): */ else { - ulsch->harq_processes[harq_pid]->DCINdi = ndi; /* ndi has not toggled si this is a retransmission */ + ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator = ndi; /* ndi has not toggled si this is a retransmission */ ulsch->harq_processes[harq_pid]->round++; /* increment number of retransmission */ result_harq = RETRANSMISSION_HARQ; diff --git a/openair1/SCHED_NR_UE/phy_frame_config_nr.h b/openair1/SCHED_NR_UE/phy_frame_config_nr.h index a939584584..81b6d373df 100644 --- a/openair1/SCHED_NR_UE/phy_frame_config_nr.h +++ b/openair1/SCHED_NR_UE/phy_frame_config_nr.h @@ -29,8 +29,8 @@ * ************************************************************************/ -#ifndef PHY_FRAME_CONFIG_NR_H -#define PHY_FRAME_CONFIG_NR_H +#ifndef PHY_FRAME_CONFIG_NR_UE_H +#define PHY_FRAME_CONFIG_NR_UE_H /************** DEFINE ********************************************/ @@ -78,5 +78,6 @@ void free_tdd_configuration_nr(NR_DL_FRAME_PARMS *frame_parms); void free_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms); +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mod); #endif /* PHY_FRAME_CONFIG_NR_H */ diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 509f4b6021..e5e48ee0ed 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -86,17 +86,6 @@ char nr_mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"}; extern double cpuf; - - -int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, - uint32_t frame, - uint32_t slot); - -uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, - int frame, - int nr_tti_rx, - fapi_nr_dci_indication_t *dci_ind); - /* int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, uint8_t eNB_id, @@ -2460,7 +2449,7 @@ ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; ue->tx_total_RE[nr_tti_tx] = 96; #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) - ue->prach_vars[eNB_id]->amp = get_tx_amp(ue->tx_power_dBm[nr_tti_tx], + ue->prach_vars[eNB_id]->amp = nr_get_tx_amp(ue->tx_power_dBm[nr_tti_tx], ue->tx_power_max_dBm, ue->frame_parms.N_RB_UL, 6); diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 326c617dfb..1b62ff81bf 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -186,6 +186,8 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ int pucch_resource_id = MAX_NB_OF_PUCCH_RESOURCES; int pucch_resource_indicator = MAX_PUCCH_RESOURCE_INDICATOR; int n_HARQ_ACK; + uint16_t crnti=0x1234; + int dmrs_scrambling_id=0,data_scrambling_id=0; /* update current context */ @@ -591,7 +593,9 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ case pucch_format2_nr: { nr_generate_pucch2(ue, - 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + crnti, + dmrs_scrambling_id, + data_scrambling_id, ue->common_vars.txdataF, &ue->frame_parms, &ue->pucch_config_dedicated[gNB_id], diff --git a/openair1/SIMULATION/ETH_TRANSPORT/socket.h b/openair1/SIMULATION/ETH_TRANSPORT/socket.h index c7a2224375..e9ca36bee2 100644 --- a/openair1/SIMULATION/ETH_TRANSPORT/socket.h +++ b/openair1/SIMULATION/ETH_TRANSPORT/socket.h @@ -28,8 +28,9 @@ * \email: lionel.gauthier@eurecom.fr */ -#ifndef __SOCKET_H__ -# define __SOCKET_H__ +#ifndef __SIMULATION_ETH_TRANSPORT_SOCKET__H__ +#define __SIMULATION_ETH_TRANSPORT_SOCKET__H__ + # ifdef SOCKET_C # define private_socket(x) x # define public_socket(x) x diff --git a/openair1/SIMULATION/LTE_PHY/dlsim.c b/openair1/SIMULATION/LTE_PHY/dlsim.c index 6706b0f912..f65e1f9633 100644 --- a/openair1/SIMULATION/LTE_PHY/dlsim.c +++ b/openair1/SIMULATION/LTE_PHY/dlsim.c @@ -59,6 +59,7 @@ #include "unitary_defs.h" #include "dummy_functions.c" #include "executables/thread-common.h" +#include "executables/split_headers.h" void feptx_ofdm(RU_t *ru, int frame, int subframe); void feptx_prec(RU_t *ru, int frame, int subframe); @@ -78,6 +79,13 @@ int n_tx_dropped = 0; /*!< \brief initial max process time for tx */ int n_rx_dropped = 0; /*!< \brief initial max process time for rx */ int emulate_rf = 0; +int split73=0; +void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_t *data, int dataLen, int r_offset) { + AssertFatal(false, "Must not be called in this context\n"); +} +void sendFs6Ulharq(enum pckType type, int UEid, PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask, uint16_t rnti, int32_t stat) { + AssertFatal(false, "Must not be called in this context\n"); +} void handler(int sig) { void *array[10]; @@ -515,7 +523,7 @@ int main(int argc, char **argv) { char fname[32],vname[32]; FILE *bler_fd; char bler_fname[256]; - FILE *time_meas_fd; + FILE *time_meas_fd=NULL; char time_meas_fname[256]; // FILE *tikz_fd; // char tikz_fname[256]; @@ -1266,6 +1274,13 @@ int main(int argc, char **argv) { } L1_rxtx_proc_t *proc_eNB = &eNB->proc.L1_proc; + proc_eNB->threadPool=(tpool_t*)malloc(sizeof(tpool_t)); + proc_eNB->respEncode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t)); + proc_eNB->respDecode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t)); + initTpool("n", proc_eNB->threadPool, true); + initNotifiedFIFO(proc_eNB->respEncode); + initNotifiedFIFO(proc_eNB->respDecode); + proc_eNB->frame_tx=0; if (input_fd==NULL) { @@ -1446,7 +1461,7 @@ int main(int argc, char **argv) { sched_resp.subframe=subframe; sched_resp.frame=proc_eNB->frame_tx; eNB->abstraction_flag=0; - schedule_response(&sched_resp); + schedule_response(&sched_resp, proc_eNB); phy_procedures_eNB_TX(eNB,proc_eNB,1); if (uncoded_ber_bit == NULL) { @@ -1480,7 +1495,7 @@ int main(int argc, char **argv) { TX_req.tx_request_body.number_of_pdus=0; proc_eNB->subframe_tx = subframe+1; sched_resp.subframe=subframe+1; - schedule_response(&sched_resp); + schedule_response(&sched_resp, proc_eNB); phy_procedures_eNB_TX(eNB,proc_eNB,0); ru->proc.tti_tx=(subframe+1)%10; feptx_prec(ru,proc_eNB->frame_tx,subframe+1); @@ -1583,11 +1598,11 @@ int main(int argc, char **argv) { subframe<<1); for (i=0; idlsch[0][0]->harq_processes[0]->e[i]==1 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] > 0)|| - (eNB->dlsch[0][0]->harq_processes[0]->e[i]==0 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] < 0)) { + if ((eNB->dlsch[0][0]->harq_processes[0]->eDL[i]==1 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] > 0)|| + (eNB->dlsch[0][0]->harq_processes[0]->eDL[i]==0 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] < 0)) { uncoded_ber_bit[bit_errors++] = 1; printf("error in pos %d : %d => %d\n",i, - eNB->dlsch[0][0]->harq_processes[0]->e[i], + eNB->dlsch[0][0]->harq_processes[0]->eDL[i], UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i]); } else { /* @@ -1634,7 +1649,7 @@ int main(int argc, char **argv) { //pdsch_vars printf("coded_bits_per_codeword %u\n",coded_bits_per_codeword); dump_dlsch2(UE,eNB_id,subframe,&coded_bits_per_codeword,round, UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid); - LOG_M("dlsch_e.m","e",eNB->dlsch[0][0]->harq_processes[0]->e,coded_bits_per_codeword,1,4); + LOG_M("dlsch_e.m","e",eNB->dlsch[0][0]->harq_processes[0]->eDL,coded_bits_per_codeword,1,4); //pdcch_vars LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1); LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1); diff --git a/openair1/SIMULATION/LTE_PHY/ulsim.c b/openair1/SIMULATION/LTE_PHY/ulsim.c index db97240ed5..c950d6f4da 100644 --- a/openair1/SIMULATION/LTE_PHY/ulsim.c +++ b/openair1/SIMULATION/LTE_PHY/ulsim.c @@ -54,6 +54,7 @@ #include "common/config/config_load_configmodule.h" #include "executables/thread-common.h" #include "targets/RT/USER/lte-softmodem.h" +#include "executables/split_headers.h" double cpuf; #define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0)) @@ -81,6 +82,14 @@ int n_tx_dropped = 0; /*!< \brief initial max process time for tx */ int n_rx_dropped = 0; /*!< \brief initial max process time for rx */ +int split73=0; +void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_t *data, int dataLen, int r_offset) { + AssertFatal(false, "Must not be called in this context\n"); +} +void sendFs6Ulharq(enum pckType type, int UEid, PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask, uint16_t rnti, int32_t stat) { + AssertFatal(false, "Must not be called in this context\n"); +} + extern void fep_full(RU_t *ru, int subframe); extern void ru_fep_full_2thread(RU_t *ru, int subframe); //extern void eNB_fep_full(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc); @@ -793,6 +802,13 @@ int main(int argc, char **argv) { proc_rxtx_ue->frame_rx = (subframe<4)?(proc_rxtx->frame_tx-1):(proc_rxtx->frame_tx); proc_rxtx_ue->subframe_tx = proc_rxtx->subframe_rx; proc_rxtx_ue->subframe_rx = (proc_rxtx->subframe_tx+6)%10; + proc_rxtx->threadPool=(tpool_t*)malloc(sizeof(tpool_t)); + proc_rxtx->respEncode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t)); + proc_rxtx->respDecode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t)); + initTpool("n",proc_rxtx->threadPool, true); + initNotifiedFIFO(proc_rxtx->respEncode); + initNotifiedFIFO(proc_rxtx->respDecode); + printf("Init UL hopping UE\n"); init_ul_hopping(&UE->frame_parms); printf("Init UL hopping eNB\n"); @@ -995,7 +1011,7 @@ int main(int argc, char **argv) { srs_flag); sched_resp.subframe=(subframe+6)%10; sched_resp.frame=(1024+eNB->proc.frame_rx+((subframe<4)?-1:0))&1023; - schedule_response(&sched_resp); + schedule_response(&sched_resp, proc_rxtx); ///////////////////// if (abstx) { @@ -1270,7 +1286,7 @@ int main(int argc, char **argv) { LOG_UDUMPMSG(SIM,dataArray(table_rx),table_rx->size,LOG_DUMP_DOUBLE,"The receiver raw data: \n"); } - printf("\n**********rb: %d ***mcs : %d *********SNR = %f dB (%f): TX %u dB (gain %f dB), N0W %f dB, I0 %d dB, delta_IF %d [ (%d,%d) dB / (%d,%d) dB ]**************************\n", + printf("\n**********rb: %d ***mcs : %d *********SNR = %f dB (%f): TX %u dB (gain %f dB), N0W %f dB, I0 %u dB, delta_IF %d [ (%d,%d) dB / (%u,%u) dB ]**************************\n", nb_rb,mcs,SNR,SNR2, tx_lev_dB, 20*log10(tx_gain), @@ -1352,7 +1368,7 @@ int main(int argc, char **argv) { printStatIndent2(&eNB->ulsch_deinterleaving_stats,"sub-block interleaving" ); printStatIndent2(&eNB->ulsch_demultiplexing_stats,"sub-block demultiplexing" ); printStatIndent2(&eNB->ulsch_rate_unmatching_stats,"sub-block rate-matching" ); - printf("|__ turbo_decoder(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n", + printf(" |__ turbo_decoder(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n", eNB->ulsch[0]->harq_processes[harq_pid]->Cminus ? eNB->ulsch[0]->harq_processes[harq_pid]->Kminus : eNB->ulsch[0]->harq_processes[harq_pid]->Kplus, diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index ebcedbaeb0..0b51901b05 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -171,6 +171,7 @@ int main(int argc, char **argv) //int pbch_tx_ant; int N_RB_DL=106,mu=1; nfapi_nr_dl_tti_pdsch_pdu_rel15_t dlsch_config; + NR_sched_pucch pucch_sched; //unsigned char frame_type = 0; @@ -412,6 +413,7 @@ int main(int argc, char **argv) printf("-c Start symbol for PDSCH (fixed for now)\n"); printf("-j Number of symbols for PDSCH (fixed for now)\n"); printf("-e MSC index\n"); + printf("-P Print DLSCH performances\n"); exit (-1); break; } @@ -706,7 +708,7 @@ int main(int argc, char **argv) memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); - if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config); + if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); else nr_schedule_css_dlsch_phytest(0,frame,slot); @@ -867,7 +869,7 @@ int main(int argc, char **argv) if (errors_scrambling > 0) { if (n_trials == 1) - printf("errors_scrambling = %d/%d (trial %d)\n", errors_scrambling, available_bits,trial); + printf("errors_scrambling = %u/%u (trial %d)\n", errors_scrambling, available_bits,trial); } if (errors_bit > 0) { @@ -901,7 +903,6 @@ int main(int argc, char **argv) break; } - if (print_perf==1) { printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n", 1000>>*scc->ssbSubcarrierSpacing,dlsch_config.rbSize,dlsch_config.mcsIndex[0], @@ -976,6 +977,8 @@ int main(int argc, char **argv) if (input_fd) fclose(input_fd); + if (scg_fd) + fclose(scg_fd); return(n_errors); } diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c index 99ca466fee..9d14391f71 100644 --- a/openair1/SIMULATION/NR_PHY/pbchsim.c +++ b/openair1/SIMULATION/NR_PHY/pbchsim.c @@ -410,7 +410,7 @@ int main(int argc, char **argv) uint8_t n_hf = 0; int cyclic_prefix_type = NFAPI_CP_NORMAL; - double fs, eps; + double fs=0, eps; double scs = 30000; double bw = 100e6; diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 5c00352515..2ad89ce897 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -108,7 +108,7 @@ int main(int argc, char **argv) uint8_t hs_flag=0; int n_frames=1; channel_desc_t *UE2gNB; - uint32_t nsymb,tx_lev; //,tx_lev_dB; + uint32_t tx_lev=0; //,tx_lev_dB; // int8_t interf1=-19,interf2=-19; NR_DL_FRAME_PARMS *frame_parms; @@ -120,7 +120,6 @@ int main(int argc, char **argv) uint32_t prach_errors=0; uint8_t subframe=9; uint16_t preamble_energy_list[64],preamble_tx=50,preamble_delay_list[64]; - uint16_t preamble_max,preamble_energy_max; PRACH_RESOURCES_t prach_resources; //uint8_t prach_fmt; //int N_ZC; @@ -189,21 +188,27 @@ int main(int argc, char **argv) case 'H': channel_model=Rayleigh8; + break; case 'I': channel_model=Rayleigh1; + break; case 'J': channel_model=Rayleigh1_corr; + break; case 'K': channel_model=Rayleigh1_anticorr; + break; case 'L': channel_model=Rice8; + break; case 'M': channel_model=Rice1; + break; case 'N': channel_model=Rayleigh1_800; @@ -397,7 +402,7 @@ int main(int argc, char **argv) frame_parms->frame_type = TDD; frame_parms->freq_range = nr_FR1; - nsymb = (frame_parms->Ncp == 0) ? 14 : 12; + //nsymb = (frame_parms->Ncp == 0) ? 14 : 12; printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d,Frame type %s, Frequency Range %s\n",NUMBER_OF_OFDM_CARRIERS, frame_parms->Ncp,frame_parms->samples_per_subframe,frame_parms->frame_type == FDD ? "FDD" : "TDD", frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2"); @@ -434,7 +439,7 @@ int main(int argc, char **argv) bw = N_RB_UL*(180e3)*(1<frame_parms.numerology_index); - AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n",gNB->frame_parms.numerology_index,N_RB_UL); + AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n",bw, gNB->frame_parms.numerology_index,N_RB_UL); if (bw <= 30.72e6) fs = 30.72e6; else if (bw <= 61.44e6) fs = 61.44e6; else if (bw <= 122.88e6) fs = 122.88e6; @@ -629,7 +634,7 @@ int main(int argc, char **argv) } } - printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); + printf("SNR %f dB, UE Speed %f km/h: errors %u/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); //printf("(%f,%f)\n",ue_speed,(double)prach_errors/(double)n_frames); } // UE Speed loop diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index 445c45693e..a754df4763 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -66,7 +66,7 @@ int main(int argc, char **argv) double sigma2, sigma2_dB=10,SNR,snr0=-2.0,snr1=2.0; double cfo=0; uint8_t snr1set=0; - int **txdata; + int **txdataF,**rxdataF; double **s_re,**s_im,**r_re,**r_im; //int sync_pos, sync_pos_slot; //FILE *rx_frame_file; @@ -87,22 +87,24 @@ int main(int argc, char **argv) uint8_t nacktoack_flag=0; int16_t amp=0x7FFF; int nr_tti_tx=0; - uint64_t actual_payload=0,payload_received;//payload bits b7b6...b2b1b0 where b7..b3=0 b2b1=HARQ b0 is SR. payload maximum value is 7 for pucch format 0 + uint64_t actual_payload=0,payload_received; int nr_bit=1; // maximum value possible is 2 uint8_t m0=0;// higher layer paramater initial cyclic shift uint8_t nrofSymbols=1; //number of OFDM symbols can be 1-2 for format 1 uint8_t startingSymbolIndex=0; // resource allocated see 9.2.1, 38.213 for more info.should be actually present in the resource set provided uint16_t startingPRB=0,startingPRB_intraSlotHopping=0; //PRB number not sure see 9.2.1, 38.213 for more info. Should be actually present in the resource set provided + uint16_t nrofPRB=2; uint8_t timeDomainOCC=0; SCM_t channel_model=AWGN;//Rayleigh1_anticorr; int N_RB_DL=273,mu=1; - float target_error_rate=0.01; + float target_error_rate=0.001; int frame_length_complex_samples; //int frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; //unsigned char frame_type = 0; int loglvl=OAILOG_WARNING; + int sr_flag = 0; cpuf = get_cpu_freq_GHz(); @@ -112,9 +114,8 @@ int main(int argc, char **argv) randominit(0); logInit(); - set_glog(loglvl); - while ((c = getopt (argc, argv, "f:hA:f:g:i:P:b:T:n:o:s:S:x:y:z:N:F:GR:IL")) != -1) { + while ((c = getopt (argc, argv, "f:hA:f:g:i:I:P:B:b:T:m:n:r:o:s:S:x:y:z:N:F:GR:IL:q:c")) != -1) { switch (c) { case 'f': //write_output_file=1; @@ -257,12 +258,30 @@ int main(int argc, char **argv) case 'i': nrofSymbols=(uint8_t)atoi(optarg); break; + case 'I': + startingSymbolIndex=(uint8_t)atoi(optarg); + break; + case 'r': + startingPRB=atoi(optarg); + break; + case 'q': + nrofPRB=atoi(optarg); + break; case 'P': format=atoi(optarg); break; + case 'm': + m0=atoi(optarg); + break; case 'b': nr_bit=atoi(optarg); break; + case 'c': + sr_flag=1; + break; + case 'B': + actual_payload=atoi(optarg); + break; case 'T': nacktoack_flag=(uint8_t)atoi(optarg); target_error_rate=0.001; @@ -292,23 +311,42 @@ int main(int argc, char **argv) printf("-f Output filename (.txt format) for Pe/SNR results\n"); printf("-F Input filename (.txt format) for RX conformance testing\n"); printf("-i Enter number of ofdm symbols for pucch\n"); + printf("-I Starting symbol index for pucch\n"); + printf("-r PUCCH starting PRB\n"); + printf("-q PUCCH number of PRB\n"); printf("-P Enter the format of PUCCH\n"); printf("-b number of HARQ bits (1-2)\n"); + printf("-B payload to be transmitted on PUCCH\n"); + printf("-m initial cyclic shift m0\n"); printf("-T to check nacktoack miss for format 1"); exit (-1); break; } } + set_glog(loglvl); + if (snr1set==0) snr1 = snr0+10; printf("Initializing gNodeB for mu %d, N_RB_DL %d\n",mu,N_RB_DL); + if((format!=0) && (format!=1) && (format!=2)){ + printf("PUCCH format %d not supported\n",format); + exit(0); + } + + AssertFatal(((format < 2)&&(nr_bit<3)&&(actual_payload<4)) || + ((format == 2)&&(nr_bit>2)&&(nr_bit<12)),"illegal combination format %d, nr_bit %d\n", + format,nr_bit); + + actual_payload &= ((1<frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; @@ -374,8 +412,10 @@ int main(int argc, char **argv) s_im = malloc(2*sizeof(double*)); r_re = malloc(2*sizeof(double*)); r_im = malloc(2*sizeof(double*)); - txdata = malloc(2*sizeof(int*)); - + txdataF = malloc(2*sizeof(int*)); + rxdataF = malloc(2*sizeof(int*)); + gNB->common_vars.rxdataF=rxdataF; + memcpy((void*)&gNB->frame_parms,(void*)frame_parms,sizeof(frame_parms)); for (i=0; i<2; i++) { s_re[i] = malloc(frame_length_complex_samples*sizeof(double)); @@ -388,16 +428,18 @@ int main(int argc, char **argv) r_im[i] = malloc(frame_length_complex_samples*sizeof(double)); bzero(r_im[i],frame_length_complex_samples*sizeof(double)); - printf("Allocating %d samples for txdata\n",frame_length_complex_samples); - txdata[i] = malloc(frame_length_complex_samples*sizeof(int)); - bzero(r_re[i],frame_length_complex_samples*sizeof(int)); - + printf("Allocating %d samples for txdataF/rxdataF\n",14*frame_parms->ofdm_symbol_size); + txdataF[i] = memalign(32,14*frame_parms->ofdm_symbol_size*sizeof(int)); + bzero(txdataF[i],14*frame_parms->ofdm_symbol_size*sizeof(int)); + rxdataF[i] = memalign(32,14*frame_parms->ofdm_symbol_size*sizeof(int)); + bzero(rxdataF[i],14*frame_parms->ofdm_symbol_size*sizeof(int)); } //configure UE UE = malloc(sizeof(PHY_VARS_NR_UE)); memcpy(&UE->frame_parms,frame_parms,sizeof(NR_DL_FRAME_PARMS)); + UE->pucch_config_common_nr->hoppingId = Nid_cell; //phy_init_nr_top(UE); //called from init_nr_ue_signal UE->perfect_ce = 0; @@ -413,83 +455,110 @@ int main(int argc, char **argv) uint8_t mcs=0; startingPRB_intraSlotHopping=N_RB_DL-1; pucch_GroupHopping_t PUCCH_GroupHopping=UE->pucch_config_common_nr->pucch_GroupHopping; - uint32_t n_id=UE->pucch_config_common_nr->hoppingId; - if((format!=0) && (format!=1)){ - printf("format not supported\n"); - exit(0); + uint32_t hopping_id=UE->pucch_config_common_nr->hoppingId; + uint32_t dmrs_scrambling_id = 0, data_scrambling_id=0; + if(format==0){ + // for now we are not considering SR just HARQ-ACK + if (nr_bit ==0) + mcs=table1_mcs[0]; + else if(nr_bit==1) + mcs=table1_mcs[actual_payload]; + else if(nr_bit==2) + mcs=table2_mcs[actual_payload]; + else AssertFatal(1==0,"Either nr_bit %d or sr_flag %d must be non-zero\n", nr_bit, sr_flag); } - if(nacktoack_flag==0){ - if(format==0){ - if(nr_bit==1){ - actual_payload=2; - mcs=table1_mcs[actual_payload]; - } - else if(nr_bit==2){ - actual_payload=6; - mcs=table2_mcs[actual_payload]; - } - else{ - printf("Number of HARQ bits possible is 1-2\n"); - exit(0); - } - } - else { - if(nr_bit==1) - actual_payload=1; - else if(nr_bit==2) - actual_payload=3; - else{ - printf("number of bits carried by PUCCH format1 is 1-2\n"); - } - } - } + for(SNR=snr0;SNR<=snr1;SNR=SNR+1){ ack_nack_errors=0; n_errors = 0; - sigma2_dB = 20*log10((double)amp/32767)-SNR; - sigma2 = pow(10,sigma2_dB/10); for (trial=0; trialofdm_symbol_size*sizeof(int)); if(format==0){ - nr_generate_pucch0(UE,txdata,frame_parms,UE->pucch_config_dedicated,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB); + nr_generate_pucch0(UE,txdataF,frame_parms,UE->pucch_config_dedicated,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB); } - else{ - nr_generate_pucch1(UE,txdata,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,0,nr_bit); + else if (format == 1){ + nr_generate_pucch1(UE,txdataF,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,0,nr_bit); } - for(i=0; i1) - r_re[aa][i]=1; - if(r_im[aa][i]<-1) - r_im[aa][i]=-1; - else if(r_im[aa][i]>1) - r_im[aa][i]=1; - ((int16_t *)txdata[aa])[(i<<1)] = (int16_t)round(r_re[aa][i]*32767); - ((int16_t *)txdata[aa])[(i<<1)+1] =(int16_t)round(r_im[aa][i]*32767); + else { + nr_generate_pucch2(UE,0x1234,dmrs_scrambling_id,data_scrambling_id,txdataF,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,nrofSymbols,startingSymbolIndex,nrofPRB,startingPRB,nr_bit); } + + int txlev = signal_energy(&txdataF[aa][startingSymbolIndex*frame_parms->ofdm_symbol_size], + frame_parms->ofdm_symbol_size); + // printf("txlev %d (%d dB), offset %d\n",txlev,dB_fixed(txlev),startingSymbolIndex*frame_parms->ofdm_symbol_size); + + // note : this scaling + int nb_re = (format == 0 || format == 1)? 12 : 12*nrofPRB; + sigma2_dB = 10*log10((double)txlev*UE->frame_parms.ofdm_symbol_size/nb_re)-SNR; + sigma2 = pow(10,sigma2_dB/10); + + for(i=startingSymbolIndex*frame_parms->ofdm_symbol_size; i<(startingSymbolIndex+1)*frame_parms->ofdm_symbol_size; i++) { + ((int16_t*)rxdataF[aa])[i<<1] = (int16_t)(100.0*((double)(((int16_t *)txdataF[aa])[(i<<1)]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))/sqrt((double)txlev)); + ((int16_t*)rxdataF[aa])[1+(i<<1)]=(int16_t)(100.0*((double)(((int16_t *)txdataF[aa])[(i<<1)+1])+ sqrt(sigma2/2)*gaussdouble(0.0,1.0))/sqrt((double)txlev)); + } + int rxlev = signal_energy(&rxdataF[aa][startingSymbolIndex*frame_parms->ofdm_symbol_size], + frame_parms->ofdm_symbol_size); + // printf("rxlev %d (%d dB), sigma2 %f dB, SNR %f, TX %f\n",rxlev,dB_fixed(rxlev),sigma2_dB,SNR,10*log10((double)txlev*UE->frame_parms.ofdm_symbol_size/12)); if(format==0){ - nr_decode_pucch0(txdata,PUCCH_GroupHopping,n_id,&(payload_received),frame_parms,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,nr_bit); + nfapi_nr_uci_pucch_pdu_format_0_1_t uci_pdu; + nfapi_nr_pucch_pdu_t pucch_pdu; + pucch_pdu.subcarrier_spacing = 1; + pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1; + pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1; + pucch_pdu.bit_len_harq = nr_bit; + pucch_pdu.sr_flag = sr_flag; + pucch_pdu.nr_of_symbols = nrofSymbols; + pucch_pdu.hopping_id = hopping_id; + pucch_pdu.initial_cyclic_shift = 0; + pucch_pdu.start_symbol_index = startingSymbolIndex; + pucch_pdu.prb_start = startingPRB; + nr_decode_pucch0(gNB,nr_tti_tx,&uci_pdu,&pucch_pdu); if(nr_bit==1) - ack_nack_errors+=(((actual_payload^payload_received)&2)>>1); + ack_nack_errors+=(actual_payload^uci_pdu.harq->harq_list[0].harq_value); else - ack_nack_errors+=(((actual_payload^payload_received)&2)>>1) + (((actual_payload^payload_received)&4)>>2); + ack_nack_errors+=(((actual_payload&1)^uci_pdu.harq->harq_list[0].harq_value)+((actual_payload>>1)^uci_pdu.harq->harq_list[1].harq_value)); + free(uci_pdu.harq->harq_list); } - else{ - nr_decode_pucch1(txdata,PUCCH_GroupHopping,n_id,&(payload_received),frame_parms,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,timeDomainOCC,nr_bit); + else if (format==1) { + + nr_decode_pucch1(rxdataF,PUCCH_GroupHopping,hopping_id,&(payload_received),frame_parms,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,timeDomainOCC,nr_bit); if(nr_bit==1) ack_nack_errors+=((actual_payload^payload_received)&1); else ack_nack_errors+=((actual_payload^payload_received)&1) + (((actual_payload^payload_received)&2)>>1); } + else if (format==2) { + nfapi_nr_uci_pucch_pdu_format_2_3_4_t uci_pdu; + nfapi_nr_pucch_pdu_t pucch_pdu; + pucch_pdu.rnti = 0x1234; + pucch_pdu.subcarrier_spacing = 1; + pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1; + pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1; + pucch_pdu.bit_len_harq = nr_bit; + pucch_pdu.sr_flag = 0; + pucch_pdu.nr_of_symbols = nrofSymbols; + pucch_pdu.hopping_id = hopping_id; + pucch_pdu.initial_cyclic_shift = 0; + pucch_pdu.start_symbol_index = startingSymbolIndex; + pucch_pdu.prb_size = nrofPRB; + pucch_pdu.prb_start = startingPRB; + pucch_pdu.dmrs_scrambling_id = dmrs_scrambling_id; + pucch_pdu.data_scrambling_id = data_scrambling_id; + nr_decode_pucch2(gNB,nr_tti_tx,&uci_pdu,&pucch_pdu); + int harq_bytes=pucch_pdu.bit_len_harq>>3; + if ((pucch_pdu.bit_len_harq&7) > 0) harq_bytes++; + for (int i=0;i>1)+(((actual_payload^payload_received)&4)>>2)+n_errors; } - printf("SNR=%f, n_trials=%d, n_bit_errors=%d\n",SNR,n_trials,n_errors); - if((float)ack_nack_errors/(float)(nr_bit*n_trials)<=target_error_rate){ + printf("SNR=%f, n_trials=%d, n_bit_errors=%d\n",SNR,n_trials,ack_nack_errors); + if((float)ack_nack_errors/(float)(n_trials)<=target_error_rate){ printf("PUCCH test OK\n"); break; } @@ -500,13 +569,15 @@ int main(int argc, char **argv) free(s_im[i]); free(r_re[i]); free(r_im[i]); - free(txdata[i]); + free(txdataF[i]); + free(rxdataF[i]); } free(s_re); free(s_im); free(r_re); free(r_im); - free(txdata); + free(txdataF); + free(rxdataF); if (output_fd) fclose(output_fd); if (input_fd) fclose(input_fd); diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index 48ea26da8f..5881b21b5f 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -402,7 +402,6 @@ int main(int argc, char **argv) rel15_ul->mcs_index = Imcs; rel15_ul->pusch_data.rv_index = rvidx; rel15_ul->nrOfLayers = Nl; - //rel15_ul->length_dmrs = length_dmrs; rel15_ul->target_code_rate = code_rate; rel15_ul->pusch_data.tb_size = TBS>>3; /////////////////////////////////////////////////// @@ -424,15 +423,6 @@ int main(int argc, char **argv) for (i = 0; i < TBS / 8; i++) test_input[i] = (unsigned char) rand(); - - /////////////////////////[adk] preparing NR_UE_ULSCH_t parameters///////////////////////// A HOT FIX until creating nfapi_nr_ul_config_ulsch_pdu_rel15_t - /////////// - ulsch_ue->nb_re_dmrs = nb_re_dmrs; - ulsch_ue->length_dmrs = length_dmrs; - ulsch_ue->rnti = n_rnti; - /////////// - //////////////////////////////////////////////////////////////////////////////////////////// - /////////////////////////[adk] preparing UL harq_process parameters///////////////////////// /////////// NR_UL_UE_HARQ_t *harq_process_ul_ue = ulsch_ue->harq_processes[harq_pid]; @@ -442,13 +432,14 @@ int main(int argc, char **argv) if (harq_process_ul_ue) { - harq_process_ul_ue->mcs = Imcs; - harq_process_ul_ue->Nl = Nl; - harq_process_ul_ue->nb_rb = nb_rb; - harq_process_ul_ue->number_of_symbols = nb_symb_sch; + harq_process_ul_ue->pusch_pdu.rnti = n_rnti; + harq_process_ul_ue->pusch_pdu.mcs_index = Imcs; + harq_process_ul_ue->pusch_pdu.nrOfLayers = Nl; + harq_process_ul_ue->pusch_pdu.rb_size = nb_rb; + harq_process_ul_ue->pusch_pdu.nr_of_symbols = nb_symb_sch; harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*nb_codewords; - harq_process_ul_ue->rvidx = rvidx; - harq_process_ul_ue->TBS = TBS; + harq_process_ul_ue->pusch_pdu.pusch_data.rv_index = rvidx; + harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = TBS; harq_process_ul_ue->a = &test_input[0]; } @@ -461,9 +452,10 @@ int main(int argc, char **argv) /////////////////////////ULSCH coding///////////////////////// /////////// + unsigned int G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, Nl); if (input_fd == NULL) { - nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid); + nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid, G); } printf("\n"); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 2adc67501a..169b82bf8d 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -55,7 +55,8 @@ #include "openair2/RRC/NR/MESSAGES/asn1_msg.h" #include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" - +#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0)) +#include "SIMULATION/LTE_PHY/common_sim.h" //#define DEBUG_ULSIM PHY_VARS_gNB *gNB; @@ -104,7 +105,7 @@ openair0_config_t openair0_cfg[MAX_CARDS]; int main(int argc, char **argv) { char c; - int i,sf; + int i; double SNR, snr0 = -2.0, snr1 = 2.0; double sigma, sigma_dB; double snr_step = 1; @@ -128,7 +129,7 @@ int main(int argc, char **argv) int loglvl = OAILOG_WARNING; uint64_t SSB_positions=0x01; uint16_t nb_symb_sch = 12; - int start_symbol = 0; + int start_symbol = 2; uint16_t nb_rb = 50; uint8_t Imcs = 9; uint8_t precod_nbr_layers = 1; @@ -140,7 +141,7 @@ int main(int argc, char **argv) int start_rb = 0; int UE_id =0; // [hna] only works for UE_id = 0 because NUMBER_OF_NR_UE_MAX is set to 1 (phy_init_nr_gNB causes segmentation fault) float target_error_rate = 0.01; - + int print_perf = 0; cpuf = get_cpu_freq_GHz(); @@ -155,7 +156,7 @@ int main(int argc, char **argv) //logInit(); randominit(0); - while ((c = getopt(argc, argv, "d:f:g:h:i:j:l:m:n:p:r:s:y:z:F:M:N:P:R:S:L:")) != -1) { + while ((c = getopt(argc, argv, "d:f:g:h:i:j:l:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) { switch (c) { /*case 'd': @@ -309,9 +310,14 @@ int main(int argc, char **argv) printf("Setting SNR1 to %f\n", snr1); break; - case 'L': - loglvl = atoi(optarg); - break; + case 'P': + print_perf=1; + opp_enabled=1; + break; + + case 'L': + loglvl = atoi(optarg); + break; default: case 'h': @@ -340,6 +346,7 @@ int main(int argc, char **argv) printf("-O oversampling factor (1,2,4,8,16)\n"); printf("-R N_RB_DL\n"); printf("-S Ending SNR, runs from SNR0 to SNR1\n"); + printf("-P Print ULSCH performances\n"); exit(-1); break; } @@ -370,10 +377,10 @@ int main(int argc, char **argv) //gNB_config = &gNB->gNB_config; //memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); - gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = (nfapi_rx_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_rx_indication_pdu_t)); - gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = (nfapi_crc_indication_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_crc_indication_pdu_t)); - gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; - gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs = 0; + gNB->UL_INFO.rx_ind.pdu_list = (nfapi_nr_rx_data_pdu_t *)malloc(NB_UE_INST*sizeof(nfapi_nr_rx_data_pdu_t)); + gNB->UL_INFO.crc_ind.crc_list = (nfapi_nr_crc_t *)malloc(NB_UE_INST*sizeof(nfapi_nr_crc_t)); + gNB->UL_INFO.rx_ind.number_of_pdus = 0; + gNB->UL_INFO.crc_ind.number_crcs = 0; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; @@ -386,7 +393,7 @@ int main(int argc, char **argv) for (i = 0; i < RC.nb_nr_macrlc_inst; i++) RC.nb_nr_mac_CC[i] = 1; mac_top_init_gNB(); - gNB_MAC_INST* gNB_mac = RC.nrmac[0]; + //gNB_MAC_INST* gNB_mac = RC.nrmac[0]; gNB_RRC_INST rrc; memset((void*)&rrc,0,sizeof(rrc)); @@ -442,7 +449,7 @@ int main(int argc, char **argv) init_nr_ue_transport(UE, 0); /* - for (sf = 0; sf < 2; sf++) { + for (int sf = 0; sf < 2; sf++) { for (i = 0; i < 2; i++) { UE->ulsch[sf][0][i] = new_nr_ue_ulsch(N_RB_UL, 8, 0); @@ -499,31 +506,47 @@ int main(int argc, char **argv) uint16_t number_dmrs_symbols = 0; unsigned int available_bits; uint8_t nb_re_dmrs; - uint8_t length_dmrs = UE->pusch_config.dmrs_UplinkConfig.pusch_maxLength; unsigned char mod_order; uint16_t code_rate; + uint8_t ptrs_mcs1 = 2; + uint8_t ptrs_mcs2 = 4; + uint8_t ptrs_mcs3 = 10; + uint16_t n_rb0 = 25; + uint16_t n_rb1 = 75; + uint8_t mcs_table = 0; + uint16_t pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; // | PUSCH_PDU_BITMAP_PUSCH_PTRS; - for (i = start_symbol; i < nb_symb_sch; i++) - number_dmrs_symbols += is_dmrs_symbol(i, - 0, - 0, - 0, - 0, - 0, - nb_symb_sch, - UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, - frame_parms->ofdm_symbol_size); + uint8_t length_dmrs = pusch_len1; // [hna] remove dmrs struct + uint16_t l_prime_mask = get_l_prime(nb_symb_sch, typeB, pusch_dmrs_pos0, length_dmrs); // [hna] remove dmrs struct + uint8_t ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, Imcs, mcs_table); + uint8_t ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, nb_rb); + + if(1<= nb_symb_sch) + pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + + for (i = 0; i < nb_symb_sch; i++) { + number_dmrs_symbols += (l_prime_mask >> i) & 0x01; + } mod_order = nr_get_Qm_ul(Imcs, 0); - nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1) ? 6 : 4) * number_dmrs_symbols; code_rate = nr_get_code_rate_ul(Imcs, 0); - available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); - TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, precod_nbr_layers); printf("\n"); for (SNR = snr0; SNR < snr1; SNR += snr_step) { + varArray_t *table_rx=initVarArray(1000,sizeof(double)); + reset_meas(&gNB->phy_proc_rx); + reset_meas(&gNB->ulsch_decoding_stats); + reset_meas(&gNB->ulsch_deinterleaving_stats); + reset_meas(&gNB->ulsch_rate_unmatching_stats); + reset_meas(&gNB->ulsch_ldpc_decoding_stats); + reset_meas(&gNB->ulsch_unscrambling_stats); + reset_meas(&gNB->ulsch_channel_estimation_stats); + reset_meas(&gNB->ulsch_llr_stats); + reset_meas(&gNB->ulsch_channel_compensation_stats); + reset_meas(&gNB->ulsch_rbs_extraction_stats); + UE_proc.nr_tti_tx = slot; UE_proc.frame_tx = frame; @@ -551,16 +574,16 @@ int main(int argc, char **argv) UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); - pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + pusch_pdu->pdu_bit_map = pdu_bit_map; pusch_pdu->rnti = n_rnti; pusch_pdu->mcs_index = Imcs; - pusch_pdu->mcs_table = 0; + pusch_pdu->mcs_table = mcs_table; pusch_pdu->target_code_rate = code_rate; pusch_pdu->qam_mod_order = mod_order; pusch_pdu->transform_precoding = 0; pusch_pdu->data_scrambling_id = 0; pusch_pdu->nrOfLayers = 1; - pusch_pdu->ul_dmrs_symb_pos = 1; + pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << start_symbol; pusch_pdu->dmrs_config_type = 0; pusch_pdu->ul_dmrs_scrambling_id = 0; pusch_pdu->scid = 0; @@ -575,9 +598,11 @@ int main(int argc, char **argv) pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; pusch_pdu->pusch_data.new_data_indicator = 0; - pusch_pdu->pusch_data.tb_size = TBS>>3; pusch_pdu->pusch_data.num_cb = 0; - + pusch_pdu->pusch_ptrs.ptrs_time_density = ptrs_time_density; + pusch_pdu->pusch_ptrs.ptrs_freq_density = ptrs_freq_density; + pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); + pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; // --------- setting parameters for UE -------- @@ -592,19 +617,33 @@ int main(int argc, char **argv) ul_config.slot = slot; ul_config.number_pdus = 1; ul_config.ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - ul_config.ul_config_list[0].ulsch_config_pdu.rnti = n_rnti; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = nb_rb; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = start_rb; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = nb_symb_sch; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = start_symbol; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.mcs = Imcs; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers; - ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid; + ul_config.ul_config_list[0].pusch_config_pdu.rnti = n_rnti; + ul_config.ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map; + ul_config.ul_config_list[0].pusch_config_pdu.rb_size = nb_rb; + ul_config.ul_config_list[0].pusch_config_pdu.rb_start = start_rb; + ul_config.ul_config_list[0].pusch_config_pdu.nr_of_symbols = nb_symb_sch; + ul_config.ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol; + ul_config.ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol; + ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type = 0; + ul_config.ul_config_list[0].pusch_config_pdu.mcs_index = Imcs; + ul_config.ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = 0; + ul_config.ul_config_list[0].pusch_config_pdu.nrOfLayers = precod_nbr_layers; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_pid; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t)); + ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; //there are plenty of other parameters that we don't seem to be using for now. e.g. - //ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0; + ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0; + nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); + available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1); + TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, precod_nbr_layers); + + pusch_pdu->pusch_data.tb_size = TBS>>3; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS; // set FAPI parameters for UE, put them in the scheduled response and call nr_ue_scheduled_response(&scheduled_response); @@ -651,15 +690,17 @@ int main(int argc, char **argv) //---------------------------------------------------------- //------------------- gNB phy procedures ------------------- //---------------------------------------------------------- - gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; - gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs = 0; + gNB->UL_INFO.rx_ind.number_of_pdus = 0; + gNB->UL_INFO.crc_ind.number_crcs = 0; + start_meas(&gNB->phy_proc_rx); phy_procedures_gNB_common_RX(gNB, frame, slot); if (n_trials==1) LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0],frame_length_complex_samples_no_prefix,1,1); phy_procedures_gNB_uespec_RX(gNB, frame, slot); + start_meas(&gNB->phy_proc_rx); //////////////////////////////////////////////////////////// if (gNB->ulsch[0][0]->last_iteration_cnt >= @@ -683,7 +724,7 @@ int main(int argc, char **argv) if (errors_scrambling > 0) { if (n_trials==1) - printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in unscrambling = %d\n" "\x1B[0m", frame, trial, errors_scrambling); + printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in unscrambling = %u\n" "\x1B[0m", frame, trial, errors_scrambling); } for (i = 0; i < TBS; i++) { @@ -701,18 +742,32 @@ int main(int argc, char **argv) if (errors_decoding > 0) { n_false_positive++; if (n_trials==1) - printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %d\n" "\x1B[0m", frame, trial, errors_decoding); + printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %u\n" "\x1B[0m", frame, trial, errors_decoding); } } // trial loop printf("*****************************************\n"); - printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %d/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, n_trials); + printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, n_trials); printf("\n"); printf("SNR %f: Channel BLER %e, Channel BER %e\n", SNR,(double)n_errors/n_trials,(double)errors_scrambling/available_bits/n_trials); printf("*****************************************\n"); printf("\n"); + if (print_perf==1) { + printDistribution(&gNB->phy_proc_rx,table_rx,"Total PHY proc rx"); + printStatIndent(&gNB->ulsch_channel_estimation_stats,"ULSCH channel estimation time"); + printStatIndent(&gNB->ulsch_rbs_extraction_stats,"ULSCH rbs extraction time"); + printStatIndent(&gNB->ulsch_channel_compensation_stats,"ULSCH channel compensation time"); + printStatIndent(&gNB->ulsch_llr_stats,"ULSCH llr computation"); + printStatIndent(&gNB->ulsch_unscrambling_stats,"ULSCH unscrambling"); + printStatIndent(&gNB->ulsch_decoding_stats,"ULSCH total decoding time"); + printStatIndent2(&gNB->ulsch_deinterleaving_stats,"ULSCH deinterleaving"); + printStatIndent2(&gNB->ulsch_rate_unmatching_stats,"ULSCH rate matching rx"); + printStatIndent2(&gNB->ulsch_ldpc_decoding_stats,"ULSCH ldpc decoding"); + printf("\n"); + } + if(n_trials==1) break; @@ -736,5 +791,8 @@ int main(int argc, char **argv) if (input_fd) fclose(input_fd); + if (scg_fd) + fclose(scg_fd); + return (n_errors); } diff --git a/openair2/COMMON/platform_constants.h b/openair2/COMMON/platform_constants.h index 7a7e984aca..1eb58b16b2 100644 --- a/openair2/COMMON/platform_constants.h +++ b/openair2/COMMON/platform_constants.h @@ -73,7 +73,9 @@ #ifdef UESIM_EXPANSION #define MAX_MOBILES_PER_ENB 256 #define MAX_MOBILES_PER_ENB_NB_IoT 256 + #define MAX_MOBILES_PER_GNB 256 #define MAX_eNB 2 + #define MAX_gNB 2 #else #ifdef LARGE_SCALE #define MAX_MOBILES_PER_ENB 128 diff --git a/openair2/COMMON/rrc_messages_def.h b/openair2/COMMON/rrc_messages_def.h index 1d0c2dfdb8..cde2497880 100644 --- a/openair2/COMMON/rrc_messages_def.h +++ b/openair2/COMMON/rrc_messages_def.h @@ -76,3 +76,6 @@ MESSAGE_DEF(NAS_DOWNLINK_DATA_IND, MESSAGE_PRIORITY_MED, NasDlDataInd // eNB: realtime -> RRC messages MESSAGE_DEF(RRC_SUBFRAME_PROCESS, MESSAGE_PRIORITY_MED, RrcSubframeProcess, rrc_subframe_process) + +// eNB: RLC -> RRC messages +MESSAGE_DEF(RLC_SDU_INDICATION, MESSAGE_PRIORITY_MED, RlcSduIndication, rlc_sdu_indication) diff --git a/openair2/COMMON/rrc_messages_types.h b/openair2/COMMON/rrc_messages_types.h index 68e1753448..7582de65ba 100644 --- a/openair2/COMMON/rrc_messages_types.h +++ b/openair2/COMMON/rrc_messages_types.h @@ -87,6 +87,8 @@ #define RRC_SUBFRAME_PROCESS(mSGpTR) (mSGpTR)->ittiMsg.rrc_subframe_process +#define RLC_SDU_INDICATION(mSGpTR) (mSGpTR)->ittiMsg.rlc_sdu_indication + //-------------------------------------------------------------------------------------------// typedef struct RrcStateInd_s { Rrc_State_t state; @@ -429,4 +431,12 @@ typedef struct rrc_subframe_process_s { int CC_id; } RrcSubframeProcess; +// eNB: RLC -> RRC messages +typedef struct rlc_sdu_indication_s { + int rnti; + int is_successful; + int srb_id; + int message_id; +} RlcSduIndication; + #endif /* RRC_MESSAGES_TYPES_H_ */ diff --git a/openair2/COMMON/s1ap_messages_types.h b/openair2/COMMON/s1ap_messages_types.h index aa718dbcf8..8e13e35d65 100644 --- a/openair2/COMMON/s1ap_messages_types.h +++ b/openair2/COMMON/s1ap_messages_types.h @@ -78,7 +78,6 @@ * the key length is 32 bytes (256 bits) */ #define SECURITY_KEY_LENGTH 32 -#ifndef OCP_FRAMEWORK typedef enum cell_type_e { CELL_MACRO_ENB, CELL_HOME_ENB, @@ -110,7 +109,6 @@ typedef enum cn_domain_s { CN_DOMAIN_PS = 1, CN_DOMAIN_CS = 2 } cn_domain_t; -#endif typedef struct net_ip_address_s { unsigned ipv4:1; @@ -126,7 +124,6 @@ typedef struct ambr_s { bitrate_t br_dl; } ambr_t; -#ifndef OCP_FRAMEWORK typedef enum priority_level_s { PRIORITY_LEVEL_SPARE = 0, PRIORITY_LEVEL_HIGHEST = 1, @@ -145,7 +142,6 @@ typedef enum pre_emp_vulnerability_e { PRE_EMPTION_VULNERABILITY_DISABLED = 1, PRE_EMPTION_VULNERABILITY_MAX, } pre_emp_vulnerability_t; -#endif typedef struct allocation_retention_priority_s { priority_level_t priority_level; diff --git a/openair2/DOCS/TEMPLATES/CODE/example_doxy.h b/openair2/DOCS/TEMPLATES/CODE/example_doxy.h index c51bdbccab..30d8ddb600 100644 --- a/openair2/DOCS/TEMPLATES/CODE/example_doxy.h +++ b/openair2/DOCS/TEMPLATES/CODE/example_doxy.h @@ -31,6 +31,9 @@ * \warning this is a warning */ +#ifndef __DOCS_TEMPLATES_CODE_EXAMPLE_DOXY__H__ +#define __DOCS_TEMPLATES_CODE_EXAMPLE_DOXY__H__ + //-----------------------------------begin group----------------------------- @@ -138,3 +141,4 @@ struct frame { int init(int src, int dst); //-----------------------end func proto------------------- +#endif diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index c489f10dae..975ac4e96f 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -939,7 +939,7 @@ int flexran_agent_mac_sf_trigger(mid_t mod_id, const void *params, Protocol__Fle for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { for (j = 0; j < 8; j++) { - if (RC.mac && RC.mac[mod_id] && RC.mac[mod_id]->UE_list.eNB_UE_stats[UE_PCCID(mod_id,i)][i].harq_pid == 1) { + if (RC.mac && RC.mac[mod_id] && RC.mac[mod_id]->UE_info.eNB_UE_stats[UE_PCCID(mod_id,i)][i].harq_pid == 1) { available_harq[i] = j; break; } @@ -977,13 +977,13 @@ int flexran_agent_mac_sf_trigger(mid_t mod_id, const void *params, Protocol__Fle dl_info[i]->harq_process_id = available_harq[UE_id]; if (RC.mac && RC.mac[mod_id]) - RC.mac[mod_id]->UE_list.eNB_UE_stats[UE_PCCID(mod_id, UE_id)][UE_id].harq_pid = 0; + RC.mac[mod_id]->UE_info.eNB_UE_stats[UE_PCCID(mod_id, UE_id)][UE_id].harq_pid = 0; dl_info[i]->has_harq_process_id = 1; /* Fill in the status of the HARQ process (2 TBs)*/ dl_info[i]->n_harq_status = 2; dl_info[i]->harq_status = malloc(sizeof(uint32_t) * dl_info[i]->n_harq_status); for (j = 0; j < dl_info[i]->n_harq_status; j++) { - dl_info[i]->harq_status[j] = RC.mac[mod_id]->UE_list.UE_sched_ctrl[UE_id].round[UE_PCCID(mod_id, UE_id)][j]; + dl_info[i]->harq_status[j] = RC.mac[mod_id]->UE_info.UE_sched_ctrl[UE_id].round[UE_PCCID(mod_id, UE_id)][j]; // TODO: This should be different per TB } // LOG_I(FLEXRAN_AGENT, "Sending subframe trigger for frame %d and subframe %d and harq %d (round %d)\n", flexran_get_current_frame(mod_id), (flexran_get_current_subframe(mod_id) + 1) % 10, dl_info[i]->harq_process_id, dl_info[i]->harq_status[0]); @@ -1357,7 +1357,7 @@ void flexran_agent_init_mac_agent(mid_t mod_id) { for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { for (j = 0; j < 8; j++) { if (RC.mac && RC.mac[mod_id]) - RC.mac[mod_id]->UE_list.eNB_UE_stats[UE_PCCID(mod_id,i)][i].harq_pid = 0; + RC.mac[mod_id]->UE_info.eNB_UE_stats[UE_PCCID(mod_id,i)][i].harq_pid = 0; } } } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index 30c10940c9..a85cbac543 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -290,7 +290,7 @@ Protocol__FlexUlCqiReport * copy_ul_cqi_report(Protocol__FlexUlCqiReport * origi full_ul_report->has_sfn_sn = original->has_sfn_sn; full_ul_report->n_cqi_meas = original->n_cqi_meas; - Protocol__FlexUlCqi **ul_report; + Protocol__FlexUlCqi **ul_report=NULL; ul_report = malloc(sizeof(Protocol__FlexUlCqi *) * full_ul_report->n_cqi_meas); if(ul_report == NULL) goto error; @@ -348,7 +348,7 @@ Protocol__FlexDlCqiReport * copy_dl_cqi_report(Protocol__FlexDlCqiReport * origi dl_report->has_sfn_sn = original->has_sfn_sn; dl_report->n_csi_report = original->n_csi_report; - Protocol__FlexDlCsi **csi_reports; + Protocol__FlexDlCsi **csi_reports=NULL; csi_reports = malloc(sizeof(Protocol__FlexDlCsi *) * dl_report->n_csi_report); if (csi_reports == NULL) goto error; @@ -383,7 +383,7 @@ Protocol__FlexPagingBufferReport * copy_paging_buffer_report(Protocol__FlexPagin protocol__flex_paging_buffer_report__init(copy); copy->n_paging_info = original->n_paging_info; - Protocol__FlexPagingInfo **p_info; + Protocol__FlexPagingInfo **p_info=NULL; p_info = malloc(sizeof(Protocol__FlexPagingInfo *) * copy->n_paging_info); if (p_info == NULL) goto error; diff --git a/openair2/ENB_APP/L1_paramdef.h b/openair2/ENB_APP/L1_paramdef.h index 210b753afb..72e77c3800 100644 --- a/openair2/ENB_APP/L1_paramdef.h +++ b/openair2/ENB_APP/L1_paramdef.h @@ -30,6 +30,8 @@ * \warning */ +#ifndef __ENB_APP_L1_PARAMDEF__H__ +#define __ENB_APP_L1_PARAMDEF__H__ /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ @@ -114,3 +116,5 @@ #define L1_PUCCH1_DTX_EMTC3_THRESHOLD_IDX 22 #define L1_PUCCH1AB_DTX_EMTC3_THRESHOLD_IDX 23 /*----------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#endif diff --git a/openair2/ENB_APP/MACRLC_paramdef.h b/openair2/ENB_APP/MACRLC_paramdef.h index 724dde6557..55ce9d5059 100644 --- a/openair2/ENB_APP/MACRLC_paramdef.h +++ b/openair2/ENB_APP/MACRLC_paramdef.h @@ -31,6 +31,8 @@ */ +#ifndef __ENB_APP_MACRLC_PARAMDEF__H__ +#define __ENB_APP_MACRLC_PARAMDEF__H__ /*----------------------------------------------------------------------------------------------------------------------------------------------------*/ @@ -104,3 +106,5 @@ #define MACRLC_PUSCH10xSNR_IDX 18 #define MACRLC_PUCCH10xSNR_IDX 19 /*---------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#endif diff --git a/openair2/ENB_APP/NB_IoT_paramdef.h b/openair2/ENB_APP/NB_IoT_paramdef.h index 6409fe63ee..8778f6d2e4 100644 --- a/openair2/ENB_APP/NB_IoT_paramdef.h +++ b/openair2/ENB_APP/NB_IoT_paramdef.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __ENB_APP_NB_IOT_PARAMDEF__H__ +#define __ENB_APP_NB_IOT_PARAMDEF__H__ + #include "common/config/config_paramdesc.h" #include "SystemInformationBlockType2.h" #include "DL-GapConfig-NB-r13.h" @@ -398,3 +401,5 @@ /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ /* NB IoT L1 configuration list section name */ #define NBIOT_L1LIST_CONFIG_STRING "NB-IoT_L1s" + +#endif diff --git a/openair2/ENB_APP/enb_paramdef.h b/openair2/ENB_APP/enb_paramdef.h index f91c7056c5..344214a1f1 100644 --- a/openair2/ENB_APP/enb_paramdef.h +++ b/openair2/ENB_APP/enb_paramdef.h @@ -90,6 +90,7 @@ typedef enum { #define CONFIG_STRING_RU_NBIOTRRC_LIST "NbIoT_RRC_instances" #define CONFIG_STRING_RU_SDR_ADDRS "sdr_addrs" #define CONFIG_STRING_RU_SDR_CLK_SRC "clock_src" +#define CONFIG_STRING_RU_SDR_TME_SRC "time_src" #define CONFIG_STRING_RU_SF_EXTENSION "sf_extension" #define CONFIG_STRING_RU_END_OF_BURST_DELAY "end_of_burst_delay" #define CONFIG_STRING_RU_OTA_SYNC_ENABLE "ota_sync_enabled" @@ -117,11 +118,12 @@ typedef enum { #define RU_NBIOTRRC_LIST_IDX 18 #define RU_SDR_ADDRS 19 #define RU_SDR_CLK_SRC 20 -#define RU_SF_EXTENSION_IDX 21 -#define RU_END_OF_BURST_DELAY_IDX 22 -#define RU_OTA_SYNC_ENABLE_IDX 23 -#define RU_BF_WEIGHTS_LIST_IDX 24 -#define RU_IF_FREQUENCY 25 +#define RU_SDR_TME_SRC 21 +#define RU_SF_EXTENSION_IDX 22 +#define RU_END_OF_BURST_DELAY_IDX 23 +#define RU_OTA_SYNC_ENABLE_IDX 24 +#define RU_BF_WEIGHTS_LIST_IDX 25 +#define RU_IF_FREQUENCY 26 /*-----------------------------------------------------------------------------------------------------------------------------------------*/ /* RU configuration parameters */ @@ -149,6 +151,7 @@ typedef enum { {CONFIG_STRING_RU_NBIOTRRC_LIST, NULL, 0, uptr:NULL, defintarrayval:DEFENBS, TYPE_INTARRAY, 1}, \ {CONFIG_STRING_RU_SDR_ADDRS, NULL, 0, strptr:NULL, defstrval:"type=b200", TYPE_STRING, 0}, \ {CONFIG_STRING_RU_SDR_CLK_SRC, NULL, 0, strptr:NULL, defstrval:"internal", TYPE_STRING, 0}, \ + {CONFIG_STRING_RU_SDR_TME_SRC, NULL, 0, strptr:NULL, defstrval:"internal", TYPE_STRING, 0}, \ {CONFIG_STRING_RU_SF_EXTENSION, NULL, 0, uptr:NULL, defuintval:312, TYPE_UINT, 0}, \ {CONFIG_STRING_RU_END_OF_BURST_DELAY, NULL, 0, uptr:NULL, defuintval:400, TYPE_UINT, 0}, \ {CONFIG_STRING_RU_OTA_SYNC_ENABLE, NULL, 0, strptr:NULL, defstrval:"no", TYPE_STRING, 0}, \ diff --git a/openair2/ENB_APP/enb_paramdef_emtc.h b/openair2/ENB_APP/enb_paramdef_emtc.h index 7ec6f4940a..de774c4ea6 100644 --- a/openair2/ENB_APP/enb_paramdef_emtc.h +++ b/openair2/ENB_APP/enb_paramdef_emtc.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __ENB_APP_ENB_PARAMDEF_EMTC__H__ +#define __ENB_APP_ENB_PARAMDEF_EMTC__H__ + #include "common/config/config_paramdesc.h" #include "RRC_paramsvalues.h" @@ -405,3 +408,5 @@ typedef struct ccparams_eMTC_s { {"sib2_interval_ULHoppingConfigCommonModeB_r13_val", NULL, 0, iptr:&eMTCconfig->sib2_interval_ULHoppingConfigCommonModeB_r13_val, defintval:0, TYPE_UINT, 0}, \ {"sib2_mpdcch_pdsch_hoppingOffset_r13", NULL, 0, iptr:&eMTCconfig->sib2_mpdcch_pdsch_hoppingOffset_r13, defintval:1, TYPE_UINT, 0} \ } + +#endif diff --git a/openair2/ENB_APP/enb_paramdef_mce.h b/openair2/ENB_APP/enb_paramdef_mce.h index 8a4dd15766..fdc2731e16 100644 --- a/openair2/ENB_APP/enb_paramdef_mce.h +++ b/openair2/ENB_APP/enb_paramdef_mce.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __ENB_APP_ENB_PARAMDEF_MCE__H__ +#define __ENB_APP_ENB_PARAMDEF_MCE__H__ + #include "common/config/config_paramdesc.h" #include "RRC_paramsvalues.h" @@ -235,5 +238,4 @@ #define MCE_CONFIG_STRING_NUM_FRAME_IDX 2 #define MCE_CONFIG_STRING_SUBFRAME_ALLOCATION_IDX 3 - - +#endif diff --git a/openair2/ENB_APP/enb_paramdef_mme.h b/openair2/ENB_APP/enb_paramdef_mme.h index 0ff1df765c..fde9b1c3a8 100644 --- a/openair2/ENB_APP/enb_paramdef_mme.h +++ b/openair2/ENB_APP/enb_paramdef_mme.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __ENB_APP_ENB_PARAMDEF_MME__H__ +#define __ENB_APP_ENB_PARAMDEF_MME__H__ + #include "common/config/config_paramdesc.h" #include "RRC_paramsvalues.h" @@ -77,6 +80,4 @@ {MME_CONFIG_STRING_MME_PORT_FOR_M3C, NULL, 0, uptr:&mme_port_for_m3c, defintval:36444L, TYPE_UINT, 0}, \ } - - - +#endif diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index a66081d99f..32cb8c74e1 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -98,7 +98,7 @@ uint16_t flexran_get_future_sfn_sf(mid_t mod_id, int ahead_of_time) { int flexran_get_mac_num_ues(mid_t mod_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.num_UEs; + return RC.mac[mod_id]->UE_info.num_UEs; } int flexran_get_num_ue_lcs(mid_t mod_id, mid_t ue_id) { @@ -123,7 +123,7 @@ int flexran_get_mac_ue_id_rnti(mid_t mod_id, rnti_t rnti) { /* get the (active) UE with RNTI i */ for (n = 0; n < MAX_MOBILES_PER_ENB; ++n) { - if (RC.mac[mod_id]->UE_list.active[n] == TRUE + if (RC.mac[mod_id]->UE_info.active[n] == TRUE && rnti == UE_RNTI(mod_id, n)) { return n; } @@ -139,7 +139,7 @@ int flexran_get_mac_ue_id(mid_t mod_id, int i) { /* get the (i+1)'th active UE */ for (n = 0; n < MAX_MOBILES_PER_ENB; ++n) { - if (RC.mac[mod_id]->UE_list.active[n] == TRUE) { + if (RC.mac[mod_id]->UE_info.active[n] == TRUE) { if (i == 0) return n; @@ -159,19 +159,19 @@ rnti_t flexran_get_mac_ue_crnti(mid_t mod_id, mid_t ue_id) { int flexran_get_ue_bsr_ul_buffer_info(mid_t mod_id, mid_t ue_id, lcid_t lcid) { if (!mac_is_present(mod_id)) return -1; - return RC.mac[mod_id]->UE_list.UE_template[UE_PCCID(mod_id, ue_id)][ue_id].ul_buffer_info[lcid]; + return RC.mac[mod_id]->UE_info.UE_template[UE_PCCID(mod_id, ue_id)][ue_id].ul_buffer_info[lcid]; } int8_t flexran_get_ue_phr(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.UE_template[UE_PCCID(mod_id, ue_id)][ue_id].phr_info; + return RC.mac[mod_id]->UE_info.UE_template[UE_PCCID(mod_id, ue_id)][ue_id].phr_info; } uint8_t flexran_get_ue_wcqi(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.UE_sched_ctrl[ue_id].dl_cqi[0]; + return RC.mac[mod_id]->UE_info.UE_sched_ctrl[ue_id].dl_cqi[0]; } rlc_buffer_occupancy_t flexran_get_tx_queue_size(mid_t mod_id, mid_t ue_id, logical_chan_id_t channel_id) { @@ -180,7 +180,7 @@ rlc_buffer_occupancy_t flexran_get_tx_queue_size(mid_t mod_id, mid_t ue_id, logi rnti_t rnti = flexran_get_mac_ue_crnti(mod_id, ue_id); frame_t frame = flexran_get_current_frame(mod_id); sub_frame_t subframe = flexran_get_current_subframe(mod_id); - mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(mod_id,rnti, mod_id, frame, subframe, ENB_FLAG_YES,MBMS_FLAG_NO, channel_id, 0,0, 0 + mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(mod_id,rnti, mod_id, frame, subframe, ENB_FLAG_YES,MBMS_FLAG_NO, channel_id, 0, 0 ); return rlc_status.bytes_in_buffer; } @@ -191,7 +191,7 @@ rlc_buffer_occupancy_t flexran_get_num_pdus_buffer(mid_t mod_id, mid_t ue_id, lo rnti_t rnti = flexran_get_mac_ue_crnti(mod_id,ue_id); frame_t frame = flexran_get_current_frame(mod_id); sub_frame_t subframe = flexran_get_current_subframe(mod_id); - mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(mod_id,rnti, mod_id, frame, subframe, ENB_FLAG_YES,MBMS_FLAG_NO, channel_id, 0,0, 0 + mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(mod_id,rnti, mod_id, frame, subframe, ENB_FLAG_YES,MBMS_FLAG_NO, channel_id, 0, 0 ); return rlc_status.pdus_in_buffer; } @@ -202,7 +202,7 @@ frame_t flexran_get_hol_delay(mid_t mod_id, mid_t ue_id, logical_chan_id_t chann rnti_t rnti = flexran_get_mac_ue_crnti(mod_id,ue_id); frame_t frame = flexran_get_current_frame(mod_id); sub_frame_t subframe = flexran_get_current_subframe(mod_id); - mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(mod_id, rnti, mod_id, frame, subframe, ENB_FLAG_YES, MBMS_FLAG_NO, channel_id, 0,0, 0 + mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(mod_id, rnti, mod_id, frame, subframe, ENB_FLAG_YES, MBMS_FLAG_NO, channel_id, 0, 0 ); return rlc_status.head_sdu_creation_time; } @@ -242,7 +242,7 @@ int32_t flexran_get_TA(mid_t mod_id, mid_t ue_id, uint8_t cc_id) { uint32_t flexran_get_total_size_dl_mac_sdus(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_sdu_bytes; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_sdu_bytes; } uint32_t flexran_get_total_size_ul_mac_sdus(mid_t mod_id, mid_t ue_id, int cc_id) { @@ -251,7 +251,7 @@ uint32_t flexran_get_total_size_ul_mac_sdus(mid_t mod_id, mid_t ue_id, int cc_id uint64_t bytes = 0; for (int i = 0; i < NB_RB_MAX; ++i) { - bytes += RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].num_bytes_rx[i]; + bytes += RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].num_bytes_rx[i]; } return bytes; @@ -260,135 +260,135 @@ uint32_t flexran_get_total_size_ul_mac_sdus(mid_t mod_id, mid_t ue_id, int cc_id uint32_t flexran_get_TBS_dl(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].TBS; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].TBS; } uint32_t flexran_get_TBS_ul(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].ulsch_TBS; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].ulsch_TBS; } uint16_t flexran_get_num_prb_retx_dl_per_ue(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].rbs_used_retx; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].rbs_used_retx; } uint32_t flexran_get_num_prb_retx_ul_per_ue(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].rbs_used_retx_rx; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].rbs_used_retx_rx; } uint16_t flexran_get_num_prb_dl_tx_per_ue(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].rbs_used; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].rbs_used; } uint16_t flexran_get_num_prb_ul_rx_per_ue(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].rbs_used_rx; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].rbs_used_rx; } uint8_t flexran_get_ue_wpmi(mid_t mod_id, mid_t ue_id, uint8_t cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.UE_sched_ctrl[ue_id].periodic_wideband_pmi[cc_id]; + return RC.mac[mod_id]->UE_info.UE_sched_ctrl[ue_id].periodic_wideband_pmi[cc_id]; } uint8_t flexran_get_mcs1_dl(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].dlsch_mcs1; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].dlsch_mcs1; } uint8_t flexran_get_mcs2_dl(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].dlsch_mcs2; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].dlsch_mcs2; } uint8_t flexran_get_mcs1_ul(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].ulsch_mcs1; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].ulsch_mcs1; } uint8_t flexran_get_mcs2_ul(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].ulsch_mcs2; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].ulsch_mcs2; } uint32_t flexran_get_total_prb_dl_tx_per_ue(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_rbs_used; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_rbs_used; } uint32_t flexran_get_total_prb_ul_rx_per_ue(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_rbs_used_rx; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_rbs_used_rx; } uint32_t flexran_get_total_num_pdu_dl(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_num_pdus; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_num_pdus; } uint32_t flexran_get_total_num_pdu_ul(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_num_pdus_rx; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_num_pdus_rx; } uint64_t flexran_get_total_TBS_dl(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_pdu_bytes; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_pdu_bytes; } uint64_t flexran_get_total_TBS_ul(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].total_ulsch_TBS; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].total_ulsch_TBS; } int flexran_get_harq_round(mid_t mod_id, uint8_t cc_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].harq_round; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].harq_round; } uint32_t flexran_get_num_mac_sdu_tx(mid_t mod_id, mid_t ue_id, int cc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].num_mac_sdu_tx; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].num_mac_sdu_tx; } unsigned char flexran_get_mac_sdu_lcid_index(mid_t mod_id, mid_t ue_id, int cc_id, int index) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].lcid_sdu[index]; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].lcid_sdu[index]; } uint32_t flexran_get_mac_sdu_size(mid_t mod_id, mid_t ue_id, int cc_id, int lcid) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.eNB_UE_stats[cc_id][ue_id].sdu_length_tx[lcid]; + return RC.mac[mod_id]->UE_info.eNB_UE_stats[cc_id][ue_id].sdu_length_tx[lcid]; } /* TODO needs to be revised */ void flexran_update_TA(mid_t mod_id, mid_t ue_id, uint8_t cc_id) { /* - UE_list_t *UE_list=&eNB_mac_inst[mod_id].UE_list; - UE_sched_ctrl *ue_sched_ctl = &UE_list->UE_sched_ctrl[ue_id]; + UE_info_t *UE_info=&eNB_mac_inst[mod_id].UE_info; + UE_sched_ctrl *ue_sched_ctl = &UE_info->UE_sched_ctrl[ue_id]; if (ue_sched_ctl->ta_timer == 0) { @@ -432,7 +432,7 @@ int flexran_get_MAC_CE_bitmap_TA(mid_t mod_id, mid_t ue_id, uint8_t cc_id) { int flexran_get_active_CC(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.numactiveCCs[ue_id]; + return RC.mac[mod_id]->UE_info.numactiveCCs[ue_id]; } uint8_t flexran_get_current_RI(mid_t mod_id, mid_t ue_id, uint8_t cc_id) { @@ -890,13 +890,13 @@ uint8_t flexran_get_rrc_status(mid_t mod_id, rnti_t rnti) { uint64_t flexran_get_ue_aggregated_max_bitrate_dl(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.UE_sched_ctrl[ue_id].ue_AggregatedMaximumBitrateDL; + return 0; //RC.mac[mod_id]->UE_info.UE_sched_ctrl[ue_id].ue_AggregatedMaximumBitrateDL; } uint64_t flexran_get_ue_aggregated_max_bitrate_ul(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.UE_sched_ctrl[ue_id].ue_AggregatedMaximumBitrateUL; + return 0; //RC.mac[mod_id]->UE_info.UE_sched_ctrl[ue_id].ue_AggregatedMaximumBitrateUL; } int flexran_get_half_duplex(mid_t mod_id, rnti_t rnti) { @@ -1235,7 +1235,7 @@ uint64_t flexran_get_ue_imsi(mid_t mod_id, rnti_t rnti) { long flexran_get_lcg(mid_t mod_id, mid_t ue_id, mid_t lc_id) { if (!mac_is_present(mod_id)) return 0; - return RC.mac[mod_id]->UE_list.UE_template[UE_PCCID(mod_id, ue_id)][ue_id].lcgidmap[lc_id]; + return RC.mac[mod_id]->UE_info.UE_template[UE_PCCID(mod_id, ue_id)][ue_id].lcgidmap[lc_id]; } /* TODO Navid: needs to be revised */ @@ -3016,7 +3016,7 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti) int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - int slice_idx = RC.mac[mod_id]->UE_list.assoc_dl_slice_idx[ue_id]; + int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id]; if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl) return RC.mac[mod_id]->slice_info.dl[slice_idx].id; @@ -3031,13 +3031,13 @@ void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { if (!flexran_dl_slice_exists(mod_id, slice_idx)) return; - RC.mac[mod_id]->UE_list.assoc_dl_slice_idx[ue_id] = slice_idx; + //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id] = slice_idx; } int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - int slice_idx = RC.mac[mod_id]->UE_list.assoc_ul_slice_idx[ue_id]; + int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id]; if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul) return RC.mac[mod_id]->slice_info.ul[slice_idx].id; @@ -3052,7 +3052,7 @@ void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { if (!flexran_ul_slice_exists(mod_id, slice_idx)) return; - RC.mac[mod_id]->UE_list.assoc_ul_slice_idx[ue_id] = slice_idx; + //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id] = slice_idx; } int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) { @@ -3103,14 +3103,14 @@ int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { memset(&sli->dl[sli->n_dl], 0, sizeof(sli->dl[sli->n_dl])); /* all UEs that have been in the old slice are put into slice index 0 */ - int *assoc_list = RC.mac[mod_id]->UE_list.assoc_dl_slice_idx; + //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_dl_slice_idx; - for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - if (assoc_list[i] == slice_idx) - assoc_list[i] = 0; - } + //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { + // if (assoc_list[i] == slice_idx) + // assoc_list[i] = 0; + //} - return sli->n_dl; + return 1; } int flexran_get_num_dl_slices(mid_t mod_id) { @@ -3397,12 +3397,12 @@ int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { memset(&sli->ul[sli->n_ul], 0, sizeof(sli->ul[sli->n_ul])); /* all UEs that have been in the old slice are put into slice index 0 */ - int *assoc_list = RC.mac[mod_id]->UE_list.assoc_ul_slice_idx; + //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_ul_slice_idx; - for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - if (assoc_list[i] == slice_idx) - assoc_list[i] = 0; - } + //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { + // if (assoc_list[i] == slice_idx) + // assoc_list[i] = 0; + //} return sli->n_ul; } diff --git a/openair2/F1AP/f1ap_cu_ue_context_management.c b/openair2/F1AP/f1ap_cu_ue_context_management.c index edc5a2c0a9..a64f2d529b 100644 --- a/openair2/F1AP/f1ap_cu_ue_context_management.c +++ b/openair2/F1AP/f1ap_cu_ue_context_management.c @@ -37,7 +37,6 @@ #include "f1ap_cu_ue_context_management.h" #include -#include "openair2/LAYER2/MAC/mac_proto.h" #include "rrc_extern.h" #include "rrc_eNB_UE_context.h" #include "rrc_eNB_S1AP.h" diff --git a/openair2/F1AP/f1ap_du_rrc_message_transfer.c b/openair2/F1AP/f1ap_du_rrc_message_transfer.c index 803551818a..fb9450728b 100644 --- a/openair2/F1AP/f1ap_du_rrc_message_transfer.c +++ b/openair2/F1AP/f1ap_du_rrc_message_transfer.c @@ -697,7 +697,7 @@ int DU_send_UL_RRC_MESSAGE_TRANSFER(instance_t instance, break; } - UE_sched_ctrl_t *UE_scheduling_control = &(RC.mac[instance]->UE_list.UE_sched_ctrl[UE_id_mac]); + UE_sched_ctrl_t *UE_scheduling_control = &(RC.mac[instance]->UE_info.UE_sched_ctrl[UE_id_mac]); if (UE_scheduling_control->cdrx_waiting_ack == TRUE) { UE_scheduling_control->cdrx_waiting_ack = FALSE; diff --git a/openair2/F1AP/f1ap_du_ue_context_management.c b/openair2/F1AP/f1ap_du_ue_context_management.c index b9c79e1f18..bae59a509e 100644 --- a/openair2/F1AP/f1ap_du_ue_context_management.c +++ b/openair2/F1AP/f1ap_du_ue_context_management.c @@ -633,9 +633,9 @@ int DU_handle_UE_CONTEXT_RELEASE_COMMAND(instance_t instance, int UE_out_of_sync = 0; for (int n = 0; n < MAX_MOBILES_PER_ENB; ++n) { - if (RC.mac[instance]->UE_list.active[n] == TRUE + if (RC.mac[instance]->UE_info.active[n] == TRUE && rnti == UE_RNTI(instance, n)) { - UE_out_of_sync = RC.mac[instance]->UE_list.UE_sched_ctrl[n].ul_out_of_sync; + UE_out_of_sync = RC.mac[instance]->UE_info.UE_sched_ctrl[n].ul_out_of_sync; break; } } diff --git a/openair2/GNB_APP/L1_nr_paramdef.h b/openair2/GNB_APP/L1_nr_paramdef.h index 889a50c814..a5a808c281 100644 --- a/openair2/GNB_APP/L1_nr_paramdef.h +++ b/openair2/GNB_APP/L1_nr_paramdef.h @@ -30,6 +30,8 @@ * \warning */ +#ifndef __GNB_APP_L1_NR_PARAMDEF__H__ +#define __GNB_APP_L1_NR_PARAMDEF__H__ /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ @@ -71,3 +73,4 @@ #define L1_REMOTE_N_PORTD_IDX 8 /*----------------------------------------------------------------------------------------------------------------------------------------------------*/ +#endif diff --git a/openair2/GNB_APP/MACRLC_nr_paramdef.h b/openair2/GNB_APP/MACRLC_nr_paramdef.h index b55aeacdce..308af2eeb9 100644 --- a/openair2/GNB_APP/MACRLC_nr_paramdef.h +++ b/openair2/GNB_APP/MACRLC_nr_paramdef.h @@ -31,6 +31,8 @@ */ +#ifndef __GNB_APP_MACRLC_NR_PARAMDEF__H__ +#define __GNB_APP_MACRLC_NR_PARAMDEF__H__ /*----------------------------------------------------------------------------------------------------------------------------------------------------*/ @@ -96,3 +98,4 @@ #define MACRLC_LOCAL_S_PORTD_IDX 15 #define MACRLC_REMOTE_S_PORTD_IDX 16 /*---------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#endif diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h index 82873f22b4..4c5da80764 100644 --- a/openair2/GNB_APP/RRC_nr_paramsvalues.h +++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h @@ -128,18 +128,18 @@ #define GNB_CONFIG_STRING_RARESPONSEWINDOW "ra_ResponseWindow" #define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSBPR "ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR" #define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSB "ssb_perRACH_OccasionAndCB_PreamblesPerSSB" -#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer" -#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB" -#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR" -#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex" -#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing" -#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" -#define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList" -#define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble" -#define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant" -#define GNB_CONFIG_STRING_PUCCHGROUPHOPPING "pucchGroupHopping" -#define GNB_CONFIG_STRING_HOPPINGID "hoppingId" -#define GNB_CONFIG_STRING_P0NOMINAL "p0_nominal" +#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer" +#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB" +#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR" +#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex" +#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing" +#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" +#define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList" +#define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble" +#define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant" +#define GNB_CONFIG_STRING_PUCCHGROUPHOPPING "pucchGroupHopping" +#define GNB_CONFIG_STRING_HOPPINGID "hoppingId" +#define GNB_CONFIG_STRING_P0NOMINAL "p0_nominal" #define GNB_CONFIG_STRING_INITIALULBWPK2_0 "initialULBWPk2_0" #define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0 "initialULBWPmappingType_0" #define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0 "initialULBWPstartSymbolAndLength_0" diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 9355517072..e7fd2f3cf8 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -978,8 +978,6 @@ void NRRCConfig(void) { paramlist_def_t RUParamList = {CONFIG_STRING_RU_LIST,NULL,0}; paramdef_t GNBSParams[] = GNBSPARAMS_DESC; - char aprefix[MAX_OPTNAME_SIZE*2 + 8]; - /* get global parameters, defined outside any section in the config file */ LOG_I(GNB_APP, "Getting GNBSParams\n"); diff --git a/openair2/GNB_APP/gnb_paramdef.h b/openair2/GNB_APP/gnb_paramdef.h index 2d9ecb8c8a..84045fc622 100644 --- a/openair2/GNB_APP/gnb_paramdef.h +++ b/openair2/GNB_APP/gnb_paramdef.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __GNB_APP_GNB_PARAMDEF__H__ +#define __GNB_APP_GNB_PARAMDEF__H__ + #include "common/config/config_paramdesc.h" #include "RRC_nr_paramsvalues.h" @@ -430,3 +433,4 @@ typedef struct ccparams_nr_x2 { #define CONFIG_HLP_WORKER "coding and FEP worker thread WORKER_DISABLE or WORKER_ENABLE\n" #define CONFIG_HLP_PARALLEL "PARALLEL_SINGLE_THREAD, PARALLEL_RU_L1_SPLIT, or PARALLEL_RU_L1_TRX_SPLIT(RU_L1_TRX_SPLIT by defult)\n" /*-------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#endif diff --git a/openair2/LAYER2/MAC/config.c b/openair2/LAYER2/MAC/config.c index 76c8e33b16..49949bd771 100644 --- a/openair2/LAYER2/MAC/config.c +++ b/openair2/LAYER2/MAC/config.c @@ -782,7 +782,7 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, int i; int UE_id = -1; eNB_MAC_INST *eNB = RC.mac[Mod_idP]; - UE_list_t *UE_list= &eNB->UE_list; + UE_info_t *UE_info= &eNB->UE_info; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_IN); LOG_D(MAC, "RC.mac:%p mib:%p\n", RC.mac, mib); @@ -882,6 +882,34 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, } } + if (logicalChannelIdentity > 0) { // is SRB1,2 or DRB + if ((UE_id = find_UE_id(Mod_idP, rntiP)) < 0) { + LOG_E(MAC,"Configuration received for unknown UE (%x), shouldn't happen\n",rntiP); + return(-1); + } + int idx = -1; + UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + for (int i = 0; i < sched_ctrl->dl_lc_num; ++i) { + if (sched_ctrl->dl_lc_ids[i] == logicalChannelIdentity) { + /* TODO this might also mean we have to remove it, not clear */ + idx = i; + break; + } + } + if (idx < 0) { + sched_ctrl->dl_lc_num++; + sched_ctrl->dl_lc_ids[sched_ctrl->dl_lc_num-1] = logicalChannelIdentity; + sched_ctrl->dl_lc_bytes[sched_ctrl->dl_lc_num-1] = 0; + LOG_I(MAC, "UE %d RNTI %x adding LC %ld idx %d to scheduling control (total %d)\n", UE_id, rntiP, logicalChannelIdentity, sched_ctrl->dl_lc_num-1, sched_ctrl->dl_lc_num); + if (logicalChannelIdentity == 1) { // if it is SRB1, add SRB2 directly because RRC does not indicate this separately + sched_ctrl->dl_lc_num++; + sched_ctrl->dl_lc_ids[sched_ctrl->dl_lc_num-1] = 2; + sched_ctrl->dl_lc_bytes[sched_ctrl->dl_lc_num-1] = 0; + LOG_I(MAC, "UE %d RNTI %x adding LC 2 idx %d to scheduling control (total %d)\n", UE_id, rntiP, sched_ctrl->dl_lc_num-1, sched_ctrl->dl_lc_num); + } + } + } + // SRB2_lchan_config->choice.explicitValue.ul_SpecificParameters->logicalChannelGroup if (logicalChannelConfig != NULL) { // check for eMTC specific things UE_id = find_UE_id(Mod_idP, rntiP); @@ -892,9 +920,9 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, } if (logicalChannelConfig) { - UE_list->UE_template[CC_idP][UE_id].lcgidmap[logicalChannelIdentity] = *logicalChannelConfig->ul_SpecificParameters->logicalChannelGroup; - UE_list->UE_template[CC_idP][UE_id].lcgidpriority[logicalChannelIdentity] = logicalChannelConfig->ul_SpecificParameters->priority; - } else UE_list->UE_template[CC_idP][UE_id].lcgidmap[logicalChannelIdentity] = 0; + UE_info->UE_template[CC_idP][UE_id].lcgidmap[logicalChannelIdentity] = *logicalChannelConfig->ul_SpecificParameters->logicalChannelGroup; + UE_info->UE_template[CC_idP][UE_id].lcgidpriority[logicalChannelIdentity] = logicalChannelConfig->ul_SpecificParameters->priority; + } else UE_info->UE_template[CC_idP][UE_id].lcgidmap[logicalChannelIdentity] = 0; } if (physicalConfigDedicated != NULL) { @@ -905,7 +933,7 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, return(-1); } - UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated = physicalConfigDedicated; + UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated = physicalConfigDedicated; LOG_I(MAC,"Added physicalConfigDedicated %p for %d.%d\n",physicalConfigDedicated,CC_idP,UE_id); } @@ -1048,15 +1076,11 @@ void eNB_Config_Local_DRX(instance_t Mod_id, rrc_mac_drx_config_req_t *rrc_mac_drx_config_req) //----------------------------------------------------------------------------- { - UE_list_t *UE_list_mac = NULL; + UE_info_t *UE_info_mac = &RC.mac[Mod_id]->UE_info; UE_sched_ctrl_t *UE_scheduling_control = NULL; - int UE_id = -1; - - rnti_t rnti = rrc_mac_drx_config_req->rnti; LTE_DRX_Config_t *const drx_Configuration = rrc_mac_drx_config_req->drx_Configuration; - - UE_list_mac = &(RC.mac[Mod_id]->UE_list); - UE_id = find_UE_id(Mod_id, rnti); + rnti_t rnti = rrc_mac_drx_config_req->rnti; + int UE_id = find_UE_id(Mod_id, rnti); /* Check UE_id */ if (UE_id == -1) { @@ -1065,7 +1089,7 @@ void eNB_Config_Local_DRX(instance_t Mod_id, } /* Get struct to modify */ - UE_scheduling_control = &(UE_list_mac->UE_sched_ctrl[UE_id]); + UE_scheduling_control = &(UE_info_mac->UE_sched_ctrl[UE_id]); UE_scheduling_control->cdrx_configured = FALSE; // will be set to true when no error /* Check drx_Configuration */ diff --git a/openair2/LAYER2/MAC/config_NB_IoT.h b/openair2/LAYER2/MAC/config_NB_IoT.h index fb8c85ebed..1821b4e12d 100644 --- a/openair2/LAYER2/MAC/config_NB_IoT.h +++ b/openair2/LAYER2/MAC/config_NB_IoT.h @@ -8,8 +8,8 @@ * */ -#ifndef _CONFIG_H_ -#define _CONFIG_H_ +#ifndef __LAYER2_MAC_CONFIG_NB_IOT__H__ +#define __LAYER2_MAC_CONFIG_NB_IOT__H__ //#include "NB_IoT_Message_definitions.h" diff --git a/openair2/LAYER2/MAC/defs.h b/openair2/LAYER2/MAC/defs.h deleted file mode 100644 index 05660b727e..0000000000 --- a/openair2/LAYER2/MAC/defs.h +++ /dev/null @@ -1,1321 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*! \file LAYER2/MAC/defs.h -* \brief MAC data structures, constant, and function prototype -* \author Navid Nikaein and Raymond Knopp -* \date 2011 -* \version 0.5 -* \email navid.nikaein@eurecom.fr - -*/ -/** @defgroup _oai2 openair2 Reference Implementation - * @ingroup _ref_implementation_ - * @{ - */ - -/*@}*/ - -#ifndef __LAYER2_MAC_DEFS_H__ -#define __LAYER2_MAC_DEFS_H__ - - - -#ifdef USER_MODE - #include - #include - #include -#endif - -//#include "COMMON/openair_defs.h" - - - -#include "PHY/defs.h" -#include "PHY/LTE_TRANSPORT/defs.h" -#include "COMMON/platform_constants.h" -#include "BCCH-BCH-Message.h" -#include "RadioResourceConfigCommon.h" -#include "RadioResourceConfigDedicated.h" -#include "MeasGapConfig.h" -#include "SchedulingInfoList.h" -#include "TDD-Config.h" -#include "RACH-ConfigCommon.h" -#include "MeasObjectToAddModList.h" -#include "MobilityControlInfo.h" -#include "MBSFN-AreaInfoList-r9.h" -#include "MBSFN-SubframeConfigList.h" -#include "PMCH-InfoList-r9.h" -#include "SCellToAddMod-r10.h" -#include "SystemInformationBlockType1-v1310-IEs.h" - - -#include "nfapi_interface.h" -#include "PHY_INTERFACE/IF_Module.h" - -/** @defgroup _mac MAC - * @ingroup _oai2 - * @{ - */ - -#define BCCH_PAYLOAD_SIZE_MAX 128 -#define CCCH_PAYLOAD_SIZE_MAX 128 -#define PCCH_PAYLOAD_SIZE_MAX 128 -#define RAR_PAYLOAD_SIZE_MAX 128 - -#define SCH_PAYLOAD_SIZE_MAX 4096 -/// Logical channel ids from 36-311 (Note BCCH is not specified in 36-311, uses the same as first DRB) - - -// Mask for identifying subframe for MBMS -#define MBSFN_TDD_SF3 0x80// for TDD -#define MBSFN_TDD_SF4 0x40 -#define MBSFN_TDD_SF7 0x20 -#define MBSFN_TDD_SF8 0x10 -#define MBSFN_TDD_SF9 0x08 -#define MBSFN_FDD_SF1 0x80// for FDD -#define MBSFN_FDD_SF2 0x40 -#define MBSFN_FDD_SF3 0x20 -#define MBSFN_FDD_SF6 0x10 -#define MBSFN_FDD_SF7 0x08 -#define MBSFN_FDD_SF8 0x04 - -#define MAX_MBSFN_AREA 8 -#define MAX_PMCH_perMBSFN 15 -/*!\brief MAX MCCH payload size */ -#define MCCH_PAYLOAD_SIZE_MAX 128 - - -#ifdef USER_MODE - #define printk printf -#endif //USER_MODE - -/*!\brief Maximum number of logical channl group IDs */ -#define MAX_NUM_LCGID 4 -/*!\brief logical channl group ID 0 */ -#define LCGID0 0 -/*!\brief logical channl group ID 1 */ -#define LCGID1 1 -/*!\brief logical channl group ID 2 */ -#define LCGID2 2 -/*!\brief logical channl group ID 3 */ -#define LCGID3 3 -/*!\brief Maximum number of logical chanels */ -#define MAX_NUM_LCID 11 -/*!\brief Maximum number od control elemenets */ -#define MAX_NUM_CE 5 -/*!\brief Maximum number of random access process */ -#define NB_RA_PROC_MAX 4 -/*!\brief size of buffer status report table */ -#define BSR_TABLE_SIZE 64 -/*!\brief The power headroom reporting range is from -23 ...+40 dB and beyond, with step 1 */ -#define PHR_MAPPING_OFFSET 23 // if ( x>= -23 ) val = floor (x + 23) -/*!\brief maximum number of resource block groups */ -#define N_RBG_MAX 25 // for 20MHz channel BW -/*!\brief minimum value for channel quality indicator */ -#define MIN_CQI_VALUE 0 -/*!\brief maximum value for channel quality indicator */ -#define MAX_CQI_VALUE 15 -/*!\briefmaximum number of supported bandwidth (1.4, 5, 10, 20 MHz) */ -#define MAX_SUPPORTED_BW 4 -/*!\brief CQI values range from 1 to 15 (4 bits) */ -#define CQI_VALUE_RANGE 16 - -/*!\brief value for indicating BSR Timer is not running */ -#define MAC_UE_BSR_TIMER_NOT_RUNNING (0xFFFF) - -#define LCID_EMPTY 0 -#define LCID_NOT_EMPTY 1 - -/*!\brief minimum RLC PDU size to be transmitted = min RLC Status PDU or RLC UM PDU SN 5 bits */ -#define MIN_RLC_PDU_SIZE (2) - -/*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */ -#define MIN_MAC_HDR_RLC_SIZE (1 + MIN_RLC_PDU_SIZE) - -/*!\brief maximum number of slices / groups */ -#define MAX_NUM_SLICES 4 - -/* - * eNB part - */ - - -/* - * UE/ENB common part - */ -/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */ -typedef struct { - uint8_t RAPID:6; - uint8_t T:1; - uint8_t E:1; -} __attribute__((__packed__))RA_HEADER_RAPID; - -/*!\brief MAC header of Random Access Response for backoff indicator (BI)*/ -typedef struct { - uint8_t BI:4; - uint8_t R:2; - uint8_t T:1; - uint8_t E:1; -} __attribute__((__packed__))RA_HEADER_BI; -/* -typedef struct { - uint64_t padding:16; - uint64_t t_crnti:16; - uint64_t hopping_flag:1; - uint64_t rb_alloc:10; - uint64_t mcs:4; - uint64_t TPC:3; - uint64_t UL_delay:1; - uint64_t cqi_req:1; - uint64_t Timing_Advance_Command:11; // first/2nd octet LSB - uint64_t R:1; // octet MSB - } __attribute__((__packed__))RAR_PDU; - -typedef struct { - uint64_t padding:16; - uint64_t R:1; // octet MSB - uint64_t Timing_Advance_Command:11; // first/2nd octet LSB - uint64_t cqi_req:1; - uint64_t UL_delay:1; - uint64_t TPC:3; - uint64_t mcs:4; - uint64_t rb_alloc:10; - uint64_t hopping_flag:1; - uint64_t t_crnti:16; - } __attribute__((__packed__))RAR_PDU; - -#define sizeof_RAR_PDU 6 -*/ -/*!\brief MAC subheader short with 7bit Length field */ -typedef struct { - uint8_t LCID:5; // octet 1 LSB - uint8_t E:1; - uint8_t R:2; // octet 1 MSB - uint8_t L:7; // octet 2 LSB - uint8_t F:1; // octet 2 MSB -} __attribute__((__packed__))SCH_SUBHEADER_SHORT; -/*!\brief MAC subheader long with 15bit Length field */ -typedef struct { - uint8_t LCID:5; // octet 1 LSB - uint8_t E:1; - uint8_t R:2; // octet 1 MSB - uint8_t L_MSB:7; - uint8_t F:1; // octet 2 MSB - uint8_t L_LSB:8; - uint8_t padding; -} __attribute__((__packed__))SCH_SUBHEADER_LONG; -/*!\brief MAC subheader short without length field */ -typedef struct { - uint8_t LCID:5; - uint8_t E:1; - uint8_t R:2; -} __attribute__((__packed__))SCH_SUBHEADER_FIXED; - -/*!\brief mac control element: short buffer status report for a specific logical channel group ID*/ -typedef struct { - uint8_t Buffer_size:6; // octet 1 LSB - uint8_t LCGID:2; // octet 1 MSB -} __attribute__((__packed__))BSR_SHORT; - -typedef BSR_SHORT BSR_TRUNCATED; -/*!\brief mac control element: long buffer status report for all logical channel group ID*/ -typedef struct { - uint8_t Buffer_size3:6; - uint8_t Buffer_size2:6; - uint8_t Buffer_size1:6; - uint8_t Buffer_size0:6; -} __attribute__((__packed__))BSR_LONG; - -#define BSR_LONG_SIZE (sizeof(BSR_LONG)) -/*!\brief mac control element: timing advance */ -typedef struct { - uint8_t TA:6; - uint8_t R:2; -} __attribute__((__packed__))TIMING_ADVANCE_CMD; -/*!\brief mac control element: power headroom report */ -typedef struct { - uint8_t PH:6; - uint8_t R:2; -} __attribute__((__packed__))POWER_HEADROOM_CMD; - -/*! \brief MIB payload */ -typedef struct { - uint8_t payload[3] ; -} __attribute__((__packed__))MIB_PDU; -/*! \brief CCCH payload */ -typedef struct { - uint8_t payload[CCCH_PAYLOAD_SIZE_MAX] ; -} __attribute__((__packed__))CCCH_PDU; -/*! \brief BCCH payload */ -typedef struct { - uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ; -} __attribute__((__packed__))BCCH_PDU; -/*! \brief RAR payload */ -typedef struct { - uint8_t payload[RAR_PAYLOAD_SIZE_MAX]; -} __attribute__ ((__packed__)) RAR_PDU; -/*! \brief BCCH payload */ -typedef struct { - uint8_t payload[PCCH_PAYLOAD_SIZE_MAX] ; -} __attribute__((__packed__))PCCH_PDU; - -/*! \brief MCCH payload */ -typedef struct { - uint8_t payload[MCCH_PAYLOAD_SIZE_MAX] ; -} __attribute__((__packed__))MCCH_PDU; -/*!< \brief MAC control element for activation and deactivation of component carriers */ -typedef struct { - uint8_t C7:1;/*!< \brief Component carrier 7 */ - uint8_t C6:1;/*!< \brief Component carrier 6 */ - uint8_t C5:1;/*!< \brief Component carrier 5 */ - uint8_t C4:1;/*!< \brief Component carrier 4 */ - uint8_t C3:1;/*!< \brief Component carrier 3 */ - uint8_t C2:1;/*!< \brief Component carrier 2 */ - uint8_t C1:1;/*!< \brief Component carrier 1 */ - uint8_t R:1;/*!< \brief Reserved */ -} __attribute__((__packed__))CC_ELEMENT; -/*! \brief MAC control element: MCH Scheduling Information */ -typedef struct { - uint8_t stop_sf_MSB:3; // octet 1 LSB - uint8_t lcid:5; // octet 2 MSB - uint8_t stop_sf_LSB:8; -} __attribute__((__packed__))MSI_ELEMENT; -/*! \brief Values of CCCH LCID for DLSCH */ -#define CCCH_LCHANID 0 -/*!\brief Values of BCCH logical channel (fake)*/ -#define BCCH 3 // SI -/*!\brief Values of PCCH logical channel (fake)*/ -#define PCCH 4 // Paging -/*!\brief Values of PCCH logical channel (fake) */ -#define MIBCH 5 // MIB -/*!\brief Values of BCCH SIB1_BR logical channel (fake) */ -#define BCCH_SIB1_BR 6 // SIB1_BR -/*!\brief Values of BCCH SIB_BR logical channel (fake) */ -#define BCCH_SI_BR 7 // SI-BR -/*!\brief Value of CCCH / SRB0 logical channel */ -#define CCCH 0 // srb0 -/*!\brief DCCH / SRB1 logical channel */ -#define DCCH 1 // srb1 -/*!\brief DCCH1 / SRB2 logical channel */ -#define DCCH1 2 // srb2 -/*!\brief DTCH DRB1 logical channel */ -#define DTCH 3 // LCID -/*!\brief MCCH logical channel */ -#define MCCH 11 -/*!\brief MTCH logical channel */ -#define MTCH 1 -// DLSCH LCHAN ID -/*!\brief LCID of UE contention resolution identity for DLSCH*/ -#define UE_CONT_RES 28 -/*!\brief LCID of timing advance for DLSCH */ -#define TIMING_ADV_CMD 29 -/*!\brief LCID of discontinous reception mode for DLSCH */ -#define DRX_CMD 30 -/*!\brief LCID of padding LCID for DLSCH */ -#define SHORT_PADDING 31 - -// MCH LCHAN IDs (table6.2.1-4 TS36.321) -/*!\brief LCID of MCCH for DL */ -#define MCCH_LCHANID 0 -/*!\brief LCID of MCH scheduling info for DL */ -#define MCH_SCHDL_INFO 3 -/*!\brief LCID of Carrier component activation/deactivation */ -#define CC_ACT_DEACT 27 - -// ULSCH LCHAN IDs -/*!\brief LCID of extended power headroom for ULSCH */ -#define EXTENDED_POWER_HEADROOM 25 -/*!\brief LCID of power headroom for ULSCH */ -#define POWER_HEADROOM 26 -/*!\brief LCID of CRNTI for ULSCH */ -#define CRNTI 27 -/*!\brief LCID of truncated BSR for ULSCH */ -#define TRUNCATED_BSR 28 -/*!\brief LCID of short BSR for ULSCH */ -#define SHORT_BSR 29 -/*!\brief LCID of long BSR for ULSCH */ -#define LONG_BSR 30 -/*!\bitmaps for BSR Triggers */ -#define BSR_TRIGGER_NONE (0) /* No BSR Trigger */ -#define BSR_TRIGGER_REGULAR (1) /* For Regular and ReTxBSR Expiry Triggers */ -#define BSR_TRIGGER_PERIODIC (2) /* For BSR Periodic Timer Expiry Trigger */ -#define BSR_TRIGGER_PADDING (4) /* For Padding BSR Trigger */ - - -/*! \brief Downlink SCH PDU Structure */ -typedef struct { - uint8_t payload[8][SCH_PAYLOAD_SIZE_MAX]; - uint16_t Pdu_size[8]; -} __attribute__ ((__packed__)) DLSCH_PDU; - - -/*! \brief MCH PDU Structure */ -typedef struct { - int8_t payload[SCH_PAYLOAD_SIZE_MAX]; - uint16_t Pdu_size; - uint8_t mcs; - uint8_t sync_area; - uint8_t msi_active; - uint8_t mcch_active; - uint8_t mtch_active; -} __attribute__ ((__packed__)) MCH_PDU; - -/*! \brief Uplink SCH PDU Structure */ -typedef struct { - int8_t payload[SCH_PAYLOAD_SIZE_MAX]; /*!< \brief SACH payload */ - uint16_t Pdu_size; -} __attribute__ ((__packed__)) ULSCH_PDU; - -#include "PHY/impl_defs_top.h" - -/*!\brief UE ULSCH scheduling states*/ -typedef enum { - S_UL_NONE =0, - S_UL_WAITING, - S_UL_SCHEDULED, - S_UL_BUFFERED, - S_UL_NUM_STATUS -} UE_ULSCH_STATUS; - -/*!\brief UE DLSCH scheduling states*/ -typedef enum { - S_DL_NONE =0, - S_DL_WAITING, - S_DL_SCHEDULED, - S_DL_BUFFERED, - S_DL_NUM_STATUS -} UE_DLSCH_STATUS; - -/*!\brief scheduling policy for the contention-based access */ -typedef enum { - CBA_ES=0, /// equal share of RB among groups w - CBA_ES_S, /// equal share of RB among groups with small allocation - CBA_PF, /// proportional fair (kind of) - CBA_PF_S, /// proportional fair (kind of) with small RB allocation - CBA_RS /// random allocation -} CBA_POLICY; - - -/*! \brief temporary struct for ULSCH sched */ -typedef struct { - rnti_t rnti; - uint16_t subframe; - uint16_t serving_num; - UE_ULSCH_STATUS status; -} eNB_ULSCH_INFO; -/*! \brief temp struct for DLSCH sched */ -typedef struct { - rnti_t rnti; - uint16_t weight; - uint16_t subframe; - uint16_t serving_num; - UE_DLSCH_STATUS status; -} eNB_DLSCH_INFO; -/*! \brief eNB overall statistics */ -typedef struct { - /// num BCCH PDU per CC - uint32_t total_num_bcch_pdu; - /// BCCH buffer size - uint32_t bcch_buffer; - /// total BCCH buffer size - uint32_t total_bcch_buffer; - /// BCCH MCS - uint32_t bcch_mcs; - - /// num CCCH PDU per CC - uint32_t total_num_ccch_pdu; - /// BCCH buffer size - uint32_t ccch_buffer; - /// total BCCH buffer size - uint32_t total_ccch_buffer; - /// BCCH MCS - uint32_t ccch_mcs; - - /// num active users - uint16_t num_dlactive_UEs; - /// available number of PRBs for a give SF - uint16_t available_prbs; - /// total number of PRB available for the user plane - uint32_t total_available_prbs; - /// aggregation - /// total avilable nccc : num control channel element - uint16_t available_ncces; - // only for a new transmission, should be extended for retransmission - // current dlsch bit rate for all transport channels - uint32_t dlsch_bitrate; - // - uint32_t dlsch_bytes_tx; - // - uint32_t dlsch_pdus_tx; - // - uint32_t total_dlsch_bitrate; - // - uint32_t total_dlsch_bytes_tx; - // - uint32_t total_dlsch_pdus_tx; - - // here for RX - // - uint32_t ulsch_bitrate; - // - uint32_t ulsch_bytes_rx; - // - uint64_t ulsch_pdus_rx; - - uint32_t total_ulsch_bitrate; - // - uint32_t total_ulsch_bytes_rx; - // - uint32_t total_ulsch_pdus_rx; - - - /// MAC agent-related stats - /// total number of scheduling decisions - int sched_decisions; - /// missed deadlines - int missed_deadlines; - -} eNB_STATS; -/*! \brief eNB statistics for the connected UEs*/ -typedef struct { - - /// CRNTI of UE - rnti_t crnti; ///user id (rnti) of connected UEs - // rrc status - uint8_t rrc_status; - /// harq pid - uint8_t harq_pid; - /// harq rounf - uint8_t harq_round; - /// total available number of PRBs for a new transmission - uint16_t rbs_used; - /// total available number of PRBs for a retransmission - uint16_t rbs_used_retx; - /// total nccc used for a new transmission: num control channel element - uint16_t ncce_used; - /// total avilable nccc for a retransmission: num control channel element - uint16_t ncce_used_retx; - - // mcs1 before the rate adaptaion - uint8_t dlsch_mcs1; - /// Target mcs2 after rate-adaptation - uint8_t dlsch_mcs2; - // current TBS with mcs2 - uint32_t TBS; - // total TBS with mcs2 - // uint32_t total_TBS; - // total rb used for a new transmission - uint32_t total_rbs_used; - // total rb used for retransmission - uint32_t total_rbs_used_retx; - - /// TX - /// Num pkt - uint32_t num_pdu_tx[NB_RB_MAX]; - /// num bytes - uint32_t num_bytes_tx[NB_RB_MAX]; - /// num retransmission / harq - uint32_t num_retransmission; - /// instantaneous tx throughput for each TTI - // uint32_t tti_throughput[NB_RB_MAX]; - - /// overall - // - uint32_t dlsch_bitrate; - //total - uint32_t total_dlsch_bitrate; - /// headers+ CE + padding bytes for a MAC PDU - uint64_t overhead_bytes; - /// headers+ CE + padding bytes for a MAC PDU - uint64_t total_overhead_bytes; - /// headers+ CE + padding bytes for a MAC PDU - uint64_t avg_overhead_bytes; - // MAC multiplexed payload - uint64_t total_sdu_bytes; - // total MAC pdu bytes - uint64_t total_pdu_bytes; - - // total num pdu - uint32_t total_num_pdus; - // - // uint32_t avg_pdu_size; - - /// RX - - /// PUCCH1a/b power (dBm) - int32_t Po_PUCCH_dBm; - /// Indicator that Po_PUCCH has been updated by PHY - int32_t Po_PUCCH_update; - /// Uplink measured RSSI - int32_t UL_rssi; - /// preassigned mcs after rate adaptation - uint8_t ulsch_mcs1; - /// adjusted mcs - uint8_t ulsch_mcs2; - - /// estimated average pdu inter-departure time - uint32_t avg_pdu_idt; - /// estimated average pdu size - uint32_t avg_pdu_ps; - /// - uint32_t aggregated_pdu_size; - uint32_t aggregated_pdu_arrival; - - /// uplink transport block size - uint32_t ulsch_TBS; - - /// total rb used for a new uplink transmission - uint32_t num_retransmission_rx; - /// total rb used for a new uplink transmission - uint32_t rbs_used_rx; - /// total rb used for a new uplink retransmission - uint32_t rbs_used_retx_rx; - /// total rb used for a new uplink transmission - uint32_t total_rbs_used_rx; - /// snr - int32_t snr; - /// target snr - int32_t target_snr; - - /// num rx pdu - uint32_t num_pdu_rx[NB_RB_MAX]; - /// num bytes rx - uint32_t num_bytes_rx[NB_RB_MAX]; - /// instantaneous rx throughput for each TTI - // uint32_t tti_goodput[NB_RB_MAX]; - /// errors - uint32_t num_errors_rx; - - uint64_t overhead_bytes_rx; - /// headers+ CE + padding bytes for a MAC PDU - uint64_t total_overhead_bytes_rx; - /// headers+ CE + padding bytes for a MAC PDU - uint64_t avg_overhead_bytes_rx; - // - uint32_t ulsch_bitrate; - //total - uint32_t total_ulsch_bitrate; - /// overall - /// MAC pdu bytes - uint64_t pdu_bytes_rx; - /// total MAC pdu bytes - uint64_t total_pdu_bytes_rx; - /// total num pdu - uint32_t total_num_pdus_rx; - /// num of error pdus - uint32_t total_num_errors_rx; - -} eNB_UE_STATS; -/*! \brief eNB template for UE context information */ -typedef struct { - /// C-RNTI of UE - rnti_t rnti; - /// NDI from last scheduling - uint8_t oldNDI[8]; - /// mcs1 from last scheduling - uint8_t oldmcs1[8]; - /// mcs2 from last scheduling - uint8_t oldmcs2[8]; - /// NDI from last UL scheduling - uint8_t oldNDI_UL[8]; - /// mcs from last UL scheduling - uint8_t mcs_UL[8]; - /// TBS from last UL scheduling - uint8_t TBS_UL[8]; - /// CQI_req from last scheduling - uint8_t oldCQI_UL[8]; - /// TPC from last scheduling - uint8_t oldTPC_UL[8]; - /// Flag to indicate UL has been scheduled at least once - boolean_t ul_active; - /// Flag to indicate UE has been configured (ACK from RRCConnectionSetup received) - boolean_t configured; - - /// MCS from last scheduling - uint8_t mcs[8]; - - /// TPC from last scheduling - uint8_t oldTPC[8]; - - // PHY interface info - - /// Number of Allocated RBs for DL after scheduling (prior to frequency allocation) - uint16_t nb_rb[8]; // num_max_harq - - /// Number of Allocated RBs for UL after scheduling - uint16_t nb_rb_ul[8]; // num_max_harq - - /// Number of Allocated RBs for UL after scheduling - uint16_t first_rb_ul[8]; // num_max_harq - - /// Is CQI requested for UL after scheduling 1st transmission - uint8_t cqi_req[8]; // num_max_harq - - /// Cyclic shift for DMRS after scheduling - uint16_t cshift[8]; // num_max_harq - - /// Number of Allocated RBs by the ulsch preprocessor - uint8_t pre_allocated_nb_rb_ul; - - /// index of Allocated RBs by the ulsch preprocessor - int8_t pre_allocated_rb_table_index_ul; - - /// total allocated RBs - int8_t total_allocated_rbs; - - /// pre-assigned MCS by the ulsch preprocessor - uint8_t pre_assigned_mcs_ul; - - /// assigned MCS by the ulsch scheduler - uint8_t assigned_mcs_ul; - - /// DL DAI - uint8_t DAI; - - /// UL DAI - uint8_t DAI_ul[10]; - - /// UL Scheduling Request Received - uint8_t ul_SR; - - ///Resource Block indication for each sub-band in MU-MIMO - uint8_t rballoc_subband[8][50]; - - // Logical channel info for link with RLC - - /// Last received UE BSR info for each logical channel group id - uint8_t bsr_info[MAX_NUM_LCGID]; - - /// LCGID mapping - long lcgidmap[11]; - - /// phr information - int8_t phr_info; - - /// phr information - int8_t phr_info_configured; - - ///dl buffer info - uint32_t dl_buffer_info[MAX_NUM_LCID]; - /// total downlink buffer info - uint32_t dl_buffer_total; - /// total downlink pdus - uint32_t dl_pdus_total; - /// downlink pdus for each LCID - uint32_t dl_pdus_in_buffer[MAX_NUM_LCID]; - /// creation time of the downlink buffer head for each LCID - uint32_t dl_buffer_head_sdu_creation_time[MAX_NUM_LCID]; - /// maximum creation time of the downlink buffer head across all LCID - uint32_t dl_buffer_head_sdu_creation_time_max; - /// a flag indicating that the downlink head SDU is segmented - uint8_t dl_buffer_head_sdu_is_segmented[MAX_NUM_LCID]; - /// size of remaining size to send for the downlink head SDU - uint32_t dl_buffer_head_sdu_remaining_size_to_send[MAX_NUM_LCID]; - - /// total uplink buffer size - uint32_t ul_total_buffer; - /// uplink buffer creation time for each LCID - uint32_t ul_buffer_creation_time[MAX_NUM_LCGID]; - /// maximum uplink buffer creation time across all the LCIDs - uint32_t ul_buffer_creation_time_max; - /// uplink buffer size per LCID - uint32_t ul_buffer_info[MAX_NUM_LCGID]; - - /// UE tx power - int32_t ue_tx_power; - - /// stores the frame where the last TPC was transmitted - uint32_t pusch_tpc_tx_frame; - uint32_t pusch_tpc_tx_subframe; - uint32_t pucch_tpc_tx_frame; - uint32_t pucch_tpc_tx_subframe; - -#ifdef LOCALIZATION - eNB_UE_estimated_distances distance; -#endif - - - uint8_t rach_resource_type; - - uint16_t mpdcch_repetition_cnt; - struct PhysicalConfigDedicated *physicalConfigDedicated; - frame_t Msg2_frame; - sub_frame_t Msg2_subframe; - -} UE_TEMPLATE; - -/*! \brief scheduling control information set through an API (not used)*/ -typedef struct { - ///UL transmission bandwidth in RBs - uint8_t ul_bandwidth[MAX_NUM_LCID]; - ///DL transmission bandwidth in RBs - uint8_t dl_bandwidth[MAX_NUM_LCID]; - - //To do GBR bearer - uint8_t min_ul_bandwidth[MAX_NUM_LCID]; - - uint8_t min_dl_bandwidth[MAX_NUM_LCID]; - - ///aggregated bit rate of non-gbr bearer per UE - uint64_t ue_AggregatedMaximumBitrateDL; - ///aggregated bit rate of non-gbr bearer per UE - uint64_t ue_AggregatedMaximumBitrateUL; - ///CQI scheduling interval in subframes. - uint16_t cqiSchedInterval; - ///Contention resolution timer used during random access - uint8_t mac_ContentionResolutionTimer; - - uint16_t max_allowed_rbs[MAX_NUM_LCID]; - - uint8_t max_mcs[MAX_NUM_LCID]; - - uint16_t priority[MAX_NUM_LCID]; - - // resource scheduling information - - /// Current DL harq round per harq_pid on each CC - uint8_t round[MAX_NUM_CCs][10]; - /// Current Active TBs per harq_pid on each CC - uint8_t tbcnt[MAX_NUM_CCs][10]; - /// Current UL harq round per harq_pid on each CC - uint8_t round_UL[MAX_NUM_CCs][8]; - uint8_t dl_pow_off[MAX_NUM_CCs]; - uint16_t pre_nb_available_rbs[MAX_NUM_CCs]; - unsigned char rballoc_sub_UE[MAX_NUM_CCs][N_RBG_MAX]; - uint16_t ta_timer; - int16_t ta_update; - uint16_t ul_consecutive_errors; - int32_t context_active_timer; - int32_t cqi_req_timer; - int32_t ul_inactivity_timer; - int32_t ul_failure_timer; - int32_t ul_scheduled; - int32_t ra_pdcch_order_sent; - int32_t ul_out_of_sync; - int32_t phr_received; - uint8_t periodic_ri_received[NFAPI_CC_MAX]; - uint8_t aperiodic_ri_received[NFAPI_CC_MAX]; - uint32_t pucch_tpc_accumulated[NFAPI_CC_MAX]; - uint8_t pucch1_cqi_update[NFAPI_CC_MAX]; - uint8_t pucch1_snr[NFAPI_CC_MAX]; - uint8_t pucch2_cqi_update[NFAPI_CC_MAX]; - uint8_t pucch2_snr[NFAPI_CC_MAX]; - uint8_t pucch3_cqi_update[NFAPI_CC_MAX]; - uint8_t pucch3_snr[NFAPI_CC_MAX]; - uint8_t pusch_snr[NFAPI_CC_MAX]; - uint16_t feedback_cnt[NFAPI_CC_MAX]; - uint16_t timing_advance; - uint16_t timing_advance_r9; - uint8_t periodic_wideband_cqi[NFAPI_CC_MAX]; - uint8_t periodic_wideband_spatial_diffcqi[NFAPI_CC_MAX]; - uint8_t periodic_wideband_pmi[NFAPI_CC_MAX]; - uint8_t periodic_subband_cqi[NFAPI_CC_MAX][16]; - uint8_t periodic_subband_spatial_diffcqi[NFAPI_CC_MAX][16]; - uint8_t aperiodic_subband_cqi0[NFAPI_CC_MAX][25]; - uint8_t aperiodic_subband_pmi[NFAPI_CC_MAX][25]; - uint8_t aperiodic_subband_diffcqi0[NFAPI_CC_MAX][25]; - uint8_t aperiodic_subband_cqi1[NFAPI_CC_MAX][25]; - uint8_t aperiodic_subband_diffcqi1[NFAPI_CC_MAX][25]; - uint8_t aperiodic_wideband_cqi0[NFAPI_CC_MAX]; - uint8_t aperiodic_wideband_pmi[NFAPI_CC_MAX]; - uint8_t aperiodic_wideband_cqi1[NFAPI_CC_MAX]; - uint8_t aperiodic_wideband_pmi1[NFAPI_CC_MAX]; - uint8_t dl_cqi[NFAPI_CC_MAX]; -} UE_sched_ctrl; -/*! \brief eNB template for the Random access information */ -typedef struct { - /// Flag to indicate this process is active - boolean_t RA_active; - /// Size of DCI for RA-Response (bytes) - uint8_t RA_dci_size_bytes1; - /// Size of DCI for RA-Response (bits) - uint8_t RA_dci_size_bits1; - /// Actual DCI to transmit for RA-Response - uint8_t RA_alloc_pdu1[(MAX_DCI_SIZE_BITS>>3)+1]; - /// DCI format for RA-Response (should be 1A) - uint8_t RA_dci_fmt1; - /// Size of DCI for Msg4/ContRes (bytes) - uint8_t RA_dci_size_bytes2; - /// Size of DCI for Msg4/ContRes (bits) - uint8_t RA_dci_size_bits2; - /// Actual DCI to transmit for Msg4/ContRes - uint8_t RA_alloc_pdu2[(MAX_DCI_SIZE_BITS>>3)+1]; - /// DCI format for Msg4/ContRes (should be 1A) - uint8_t RA_dci_fmt2; - /// Flag to indicate the eNB should generate RAR. This is triggered by detection of PRACH - uint8_t generate_rar; - /// Subframe where preamble was received - uint8_t preamble_subframe; - /// Subframe where Msg2 is to be sent - uint8_t Msg2_subframe; - /// Frame where Msg2 is to be sent - frame_t Msg2_frame; - /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_subframe; - /// Frame where Msg3 is to be sent - frame_t Msg3_frame; - /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_subframe; - /// Frame where Msg4 is to be sent - frame_t Msg4_frame; - /// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC. This is triggered by first ULSCH reception at eNB for new user. - uint8_t generate_Msg4; - /// Flag to indicate that eNB is waiting for ACK that UE has received Msg3. - uint8_t wait_ack_Msg4; - /// harq_pid used for Msg4 transmission - uint8_t harq_pid; - /// UE RNTI allocated during RAR - rnti_t rnti; - /// RA RNTI allocated from received PRACH - uint16_t RA_rnti; - /// Received preamble_index - uint8_t preamble_index; - /// Received UE Contention Resolution Identifier - uint8_t cont_res_id[6]; - /// Timing offset indicated by PHY - int16_t timing_offset; - /// Timeout for RRC connection - int16_t RRC_timer; - /// Msg3 first RB - uint8_t msg3_first_rb; - /// Msg3 number of RB - uint8_t msg3_nb_rb; - /// Msg3 MCS - uint8_t msg3_mcs; - /// Msg3 TPC command - uint8_t msg3_TPC; - /// Msg3 ULdelay command - uint8_t msg3_ULdelay; - /// Msg3 cqireq command - uint8_t msg3_cqireq; - /// Round of Msg3 HARQ - uint8_t msg3_round; - /// TBS used for Msg4 - int msg4_TBsize; - /// MCS used for Msg4 - int msg4_mcs; - /// size off piggybacked RRC SDU - uint8_t msg4_rrc_sdu_length; - uint32_t msg4_delay; - uint8_t rach_resource_type; - uint8_t msg2_mpdcch_repetition_cnt; - uint8_t msg2_mpdcch_done; - uint8_t msg4_mpdcch_repetition_cnt; - uint8_t msg4_mpdcch_done; - uint8_t msg2_narrowband; - uint32_t msg34_narrowband; -} RA_TEMPLATE; - - -/*! \brief subband bitmap confguration (for ALU icic algo purpose), in test phase */ -typedef struct { - uint8_t sbmap[NUMBER_OF_SUBBANDS_MAX]; //13 = number of SB MAX for 100 PRB - uint8_t periodicity; - uint8_t first_subframe; - uint8_t sb_size; - uint8_t nb_active_sb; -} SBMAP_CONF; -/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ -typedef struct { - /// Dedicated information for UEs - struct PhysicalConfigDedicated *physicalConfigDedicated[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; - /// DLSCH pdu - DLSCH_PDU DLSCH_pdu[MAX_NUM_CCs][2][NUMBER_OF_UE_MAX]; - /// DCI template and MAC connection parameters for UEs - UE_TEMPLATE UE_template[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; - /// DCI template and MAC connection for RA processes - int pCC_id[NUMBER_OF_UE_MAX]; - /// sorted downlink component carrier for the scheduler - int ordered_CCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; - /// number of downlink active component carrier - int numactiveCCs[NUMBER_OF_UE_MAX]; - /// sorted uplink component carrier for the scheduler - int ordered_ULCCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; - /// number of uplink active component carrier - int numactiveULCCs[NUMBER_OF_UE_MAX]; - /// number of downlink active component carrier - uint8_t dl_CC_bitmap[NUMBER_OF_UE_MAX]; - /// eNB to UE statistics - eNB_UE_STATS eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; - /// scheduling control info - UE_sched_ctrl UE_sched_ctrl[NUMBER_OF_UE_MAX]; - int next[NUMBER_OF_UE_MAX]; - int head; - int next_ul[NUMBER_OF_UE_MAX]; - int head_ul; - int avail; - int num_UEs; - boolean_t active[NUMBER_OF_UE_MAX]; -} UE_list_t; - -/*! \brief eNB common channels */ -typedef struct { - int physCellId; - int p_eNB; - int Ncp; - int eutra_band; - uint32_t dl_CarrierFreq; - BCCH_BCH_Message_t *mib; - RadioResourceConfigCommonSIB_t *radioResourceConfigCommon; - RadioResourceConfigCommonSIB_t *radioResourceConfigCommon_BR; - TDD_Config_t *tdd_Config; - SchedulingInfoList_t *schedulingInfoList; - ARFCN_ValueEUTRA_t ul_CarrierFreq; - long ul_Bandwidth; - /// Outgoing MIB PDU for PHY - MIB_PDU MIB_pdu; - /// Outgoing BCCH pdu for PHY - BCCH_PDU BCCH_pdu; - /// Outgoing BCCH DCI allocation - uint32_t BCCH_alloc_pdu; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Template for RA computations - RA_TEMPLATE RA_template[NB_RA_PROC_MAX]; - /// VRB map for common channels - uint8_t vrb_map[100]; - /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; - /// MBSFN SubframeConfig - struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[8]; - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; - /// MBMS Flag - uint8_t MBMS_flag; - /// Outgoing MCCH pdu for PHY - MCCH_PDU MCCH_pdu; - /// MCCH active flag - uint8_t msi_active; - /// MCCH active flag - uint8_t mcch_active; - /// MTCH active flag - uint8_t mtch_active; - /// number of active MBSFN area - uint8_t num_active_mbsfn_area; - /// MBSFN Area Info - struct MBSFN_AreaInfo_r9 *mbsfn_AreaInfo[MAX_MBSFN_AREA]; - /// PMCH Config - struct PMCH_Config_r9 *pmch_Config[MAX_PMCH_perMBSFN]; - /// MBMS session info list - struct MBMS_SessionInfoList_r9 *mbms_SessionList[MAX_PMCH_perMBSFN]; - /// Outgoing MCH pdu for PHY - MCH_PDU MCH_pdu; - /// Rel13 parameters from SIB1 - SystemInformationBlockType1_v1310_IEs_t *sib1_v13ext; - /// Counter for SIB1-BR scheduling - int SIB1_BR_cnt; - /// Outgoing BCCH-BR pdu for PHY - BCCH_PDU BCCH_BR_pdu[20]; -} COMMON_channels_t; -/*! \brief top level eNB MAC structure */ -typedef struct eNB_MAC_INST_s { - /// Ethernet parameters for northbound midhaul interface - eth_params_t eth_params_n; - /// Ethernet parameters for fronthaul interface - eth_params_t eth_params_s; - /// - module_id_t Mod_id; - /// frame counter - frame_t frame; - /// subframe counter - sub_frame_t subframe; - /// Pointer to IF module instance for PHY - IF_Module_t *if_inst; - /// Common cell resources - COMMON_channels_t common_channels[MAX_NUM_CCs]; - /// current PDU index (BCH,MCH,DLSCH) - uint16_t pdu_index[MAX_NUM_CCs]; - - /// NFAPI Config Request Structure - nfapi_config_request_t config[MAX_NUM_CCs]; - /// Preallocated DL pdu list - nfapi_dl_config_request_pdu_t dl_config_pdu_list[MAX_NUM_CCs][MAX_NUM_DL_PDU]; - /// NFAPI DL Config Request Structure - nfapi_dl_config_request_t DL_req[MAX_NUM_CCs]; - /// Preallocated UL pdu list - nfapi_ul_config_request_pdu_t ul_config_pdu_list[MAX_NUM_CCs][MAX_NUM_UL_PDU]; - /// Preallocated UL pdu list for ULSCH (n+k delay) - nfapi_ul_config_request_pdu_t ul_config_pdu_list_tmp[MAX_NUM_CCs][10][MAX_NUM_UL_PDU]; - /// NFAPI UL Config Request Structure, send to L1 4 subframes before processing takes place - nfapi_ul_config_request_t UL_req[MAX_NUM_CCs]; - /// NFAPI "Temporary" UL Config Request Structure, holds future UL_config requests - nfapi_ul_config_request_t UL_req_tmp[MAX_NUM_CCs][10]; - /// Preallocated HI_DCI0 pdu list - nfapi_hi_dci0_request_pdu_t hi_dci0_pdu_list[MAX_NUM_CCs][MAX_NUM_HI_DCI0_PDU]; - /// NFAPI HI/DCI0 Config Request Structure - nfapi_hi_dci0_request_t HI_DCI0_req[MAX_NUM_CCs]; - /// Prealocated TX pdu list - nfapi_tx_request_pdu_t tx_request_pdu[MAX_NUM_CCs][MAX_NUM_TX_REQUEST_PDU]; - /// NFAPI DL PDU structure - nfapi_tx_request_t TX_req[MAX_NUM_CCs]; - /// UL handle - uint32_t ul_handle; - UE_list_t UE_list; - - ///subband bitmap configuration - SBMAP_CONF sbmap_conf; - /// CCE table used to build DCI scheduling information - int CCE_table[MAX_NUM_CCs][800]; - /// active flag for Other lcid - uint8_t lcid_active[NB_RB_MAX]; - /// eNB stats - eNB_STATS eNB_stats[MAX_NUM_CCs]; - // MAC function execution peformance profiler - /// processing time of eNB scheduler - time_stats_t eNB_scheduler; - /// processing time of eNB scheduler for SI - time_stats_t schedule_si; - /// processing time of eNB scheduler for Random access - time_stats_t schedule_ra; - /// processing time of eNB ULSCH scheduler - time_stats_t schedule_ulsch; - /// processing time of eNB DCI generation - time_stats_t fill_DLSCH_dci; - /// processing time of eNB MAC preprocessor - time_stats_t schedule_dlsch_preprocessor; - /// processing time of eNB DLSCH scheduler - time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor - /// processing time of eNB MCH scheduler - time_stats_t schedule_mch; - /// processing time of eNB ULSCH reception - time_stats_t rx_ulsch_sdu; // include rlc_data_ind -} eNB_MAC_INST; - -/* - * UE part - */ - -typedef enum { - TYPE0, - TYPE1, - TYPE1A, - TYPE2, - TYPE2A, - TYPEUESPEC -} MPDCCH_TYPES_t; - -/*!\brief UE layer 2 status */ -typedef enum { - CONNECTION_OK=0, - CONNECTION_LOST, - PHY_RESYNCH, - PHY_HO_PRACH -} UE_L2_STATE_t; - -/*!\brief UE scheduling info */ -typedef struct { - /// buffer status for each lcgid - uint8_t BSR[MAX_NUM_LCGID]; // should be more for mesh topology - /// keep the number of bytes in rlc buffer for each lcgid - int32_t BSR_bytes[MAX_NUM_LCGID]; - /// after multiplexing buffer remain for each lcid - int32_t LCID_buffer_remain[MAX_NUM_LCID]; - /// sum of all lcid buffer size - uint16_t All_lcid_buffer_size_lastTTI; - /// buffer status for each lcid - uint8_t LCID_status[MAX_NUM_LCID]; - /// SR pending as defined in 36.321 - uint8_t SR_pending; - /// SR_COUNTER as defined in 36.321 - uint16_t SR_COUNTER; - /// logical channel group ide for each LCID - uint8_t LCGID[MAX_NUM_LCID]; - /// retxBSR-Timer, default value is sf2560 - uint16_t retxBSR_Timer; - /// retxBSR_SF, number of subframe before triggering a regular BSR - uint16_t retxBSR_SF; - /// periodicBSR-Timer, default to infinity - uint16_t periodicBSR_Timer; - /// periodicBSR_SF, number of subframe before triggering a periodic BSR - uint16_t periodicBSR_SF; - /// default value is 0: not configured - uint16_t sr_ProhibitTimer; - /// sr ProhibitTime running - uint8_t sr_ProhibitTimer_Running; - /// default value to n5 - uint16_t maxHARQ_Tx; - /// default value is false - uint16_t ttiBundling; - /// default value is release - struct DRX_Config *drx_config; - /// default value is release - struct MAC_MainConfig__phr_Config *phr_config; - ///timer before triggering a periodic PHR - uint16_t periodicPHR_Timer; - ///timer before triggering a prohibit PHR - uint16_t prohibitPHR_Timer; - ///DL Pathloss change value - uint16_t PathlossChange; - ///number of subframe before triggering a periodic PHR - int16_t periodicPHR_SF; - ///number of subframe before triggering a prohibit PHR - int16_t prohibitPHR_SF; - ///DL Pathloss Change in db - uint16_t PathlossChange_db; - - /// default value is false - uint16_t extendedBSR_Sizes_r10; - /// default value is false - uint16_t extendedPHR_r10; - - //Bj bucket usage per lcid - int16_t Bj[MAX_NUM_LCID]; - // Bucket size per lcid - int16_t bucket_size[MAX_NUM_LCID]; -} UE_SCHEDULING_INFO; -/*!\brief Top level UE MAC structure */ -typedef struct { - uint16_t Node_id; - /// RX frame counter - frame_t rxFrame; - /// RX subframe counter - sub_frame_t rxSubframe; - /// TX frame counter - frame_t txFrame; - /// TX subframe counter - sub_frame_t txSubframe; - /// C-RNTI of UE - uint16_t crnti; - /// C-RNTI of UE before HO - rnti_t crnti_before_ho; ///user id (rnti) of connected UEs - /// uplink active flag - uint8_t ul_active; - /// pointer to RRC PHY configuration - RadioResourceConfigCommonSIB_t *radioResourceConfigCommon; - /// pointer to RACH_ConfigDedicated (NULL when not active, i.e. upon HO completion or T304 expiry) - struct RACH_ConfigDedicated *rach_ConfigDedicated; - /// pointer to RRC PHY configuration - struct PhysicalConfigDedicated *physicalConfigDedicated; - /// pointer to RRC PHY configuration SCEll - struct PhysicalConfigDedicatedSCell_r10 *physicalConfigDedicatedSCell_r10; - /// pointer to TDD Configuration (NULL for FDD) - TDD_Config_t *tdd_Config; - /// Number of adjacent cells to measure - uint8_t n_adj_cells; - /// Array of adjacent physical cell ids - uint32_t adj_cell_id[6]; - /// Pointer to RRC MAC configuration - MAC_MainConfig_t *macConfig; - /// Pointer to RRC Measurement gap configuration - MeasGapConfig_t *measGapConfig; - /// Pointers to LogicalChannelConfig indexed by LogicalChannelIdentity. Note NULL means LCHAN is inactive. - LogicalChannelConfig_t *logicalChannelConfig[MAX_NUM_LCID]; - /// Scheduling Information - UE_SCHEDULING_INFO scheduling_info; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Incoming DLSCH pdu for PHY - DLSCH_PDU DLSCH_pdu[NUMBER_OF_UE_MAX][2]; - /// number of attempt for rach - uint8_t RA_attempt_number; - /// Random-access procedure flag - uint8_t RA_active; - /// Random-access window counter - int8_t RA_window_cnt; - /// Random-access Msg3 size in bytes - uint8_t RA_Msg3_size; - /// Random-access prachMaskIndex - uint8_t RA_prachMaskIndex; - /// Flag indicating Preamble set (A,B) used for first Msg3 transmission - uint8_t RA_usedGroupA; - /// Random-access Resources - PRACH_RESOURCES_t RA_prach_resources; - /// Random-access PREAMBLE_TRANSMISSION_COUNTER - uint8_t RA_PREAMBLE_TRANSMISSION_COUNTER; - /// Random-access backoff counter - int16_t RA_backoff_cnt; - /// Random-access variable for window calculation (frame of last change in window counter) - uint32_t RA_tx_frame; - /// Random-access variable for window calculation (subframe of last change in window counter) - uint8_t RA_tx_subframe; - /// Random-access Group B maximum path-loss - /// Random-access variable for backoff (frame of last change in backoff counter) - uint32_t RA_backoff_frame; - /// Random-access variable for backoff (subframe of last change in backoff counter) - uint8_t RA_backoff_subframe; - /// Random-access Group B maximum path-loss - uint16_t RA_maxPL; - /// Random-access Contention Resolution Timer active flag - uint8_t RA_contention_resolution_timer_active; - /// Random-access Contention Resolution Timer count value - uint8_t RA_contention_resolution_cnt; - /// power headroom reporitng reconfigured - uint8_t PHR_reconfigured; - /// power headroom state as configured by the higher layers - uint8_t PHR_state; - /// power backoff due to power management (as allowed by P-MPRc) for this cell - uint8_t PHR_reporting_active; - /// power backoff due to power management (as allowed by P-MPRc) for this cell - uint8_t power_backoff_db[NUMBER_OF_eNB_MAX]; - /// BSR report falg management - uint8_t BSR_reporting_active; - /// retxBSR-Timer expires flag - uint8_t retxBSRTimer_expires_flag; - /// periodBSR-Timer expires flag - uint8_t periodBSRTimer_expires_flag; - - /// MBSFN_Subframe Configuration - struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[8]; // FIXME replace 8 by MAX_MBSFN_AREA? - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; - /// number of active MBSFN area - uint8_t num_active_mbsfn_area; - /// MBSFN Area Info - struct MBSFN_AreaInfo_r9 *mbsfn_AreaInfo[MAX_MBSFN_AREA]; - /// PMCH Config - struct PMCH_Config_r9 *pmch_Config[MAX_PMCH_perMBSFN]; - /// MCCH status - uint8_t mcch_status; - /// MSI status - uint8_t msi_status;// could be an array if there are >1 MCH in one MBSFN area - /// CBA RNTI for each group - uint16_t cba_rnti[NUM_MAX_CBA_GROUP]; - /// last SFN for CBA channel access - uint8_t cba_last_access[NUM_MAX_CBA_GROUP]; - /// total UE scheduler processing time - time_stats_t ue_scheduler; // total - /// UE ULSCH tx processing time inlcuding RLC interface (rlc_data_req) and mac header generation - time_stats_t tx_ulsch_sdu; - /// UE DLSCH rx processing time inlcuding RLC interface (mac_rrc_data_ind or mac_rlc_status_ind+mac_rlc_data_ind) and mac header parser - time_stats_t rx_dlsch_sdu ; - /// UE query for MCH subframe processing time - time_stats_t ue_query_mch; - /// UE MCH rx processing time - time_stats_t rx_mch_sdu; - /// UE BCCH rx processing time including RLC interface (mac_rrc_data_ind) - time_stats_t rx_si; - /// UE PCCH rx processing time including RLC interface (mac_rrc_data_ind) - time_stats_t rx_p; -} UE_MAC_INST; -/*! \brief ID of the neighboring cells used for HO*/ -typedef struct { - uint16_t cell_ids[6]; - uint8_t n_adj_cells; -} neigh_cell_id_t; - -#include "proto.h" -/*@}*/ -#endif /*__LAYER2_MAC_DEFS_H__ */ diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index eef1f9c976..c46005ee2d 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -35,7 +35,6 @@ #include "LAYER2/MAC/mac_extern.h" #include "LAYER2/MAC/mac_proto.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "nfapi/oai_integration/vendor_ext.h" #include "common/utils/LOG/vcd_signal_dumper.h" @@ -89,7 +88,7 @@ void schedule_SRS(module_id_t module_idP, const uint16_t deltaTSFCTabType1[15][2] = { {1, 1}, {1, 2}, {2, 2}, {1, 5}, {2, 5}, {4, 5}, {8, 5}, {3, 5}, {12, 5}, {1, 10}, {2, 10}, {4, 10}, {8, 10}, {351, 10}, {383, 10} }; // Table 5.5.3.3-2 3GPP 36.211 FDD const uint16_t deltaTSFCTabType2[14][2] = { {2, 5}, {6, 5}, {10, 5}, {18, 5}, {14, 5}, {22, 5}, {26, 5}, {30, 5}, {70, 10}, {74, 10}, {194, 10}, {326, 10}, {586, 10}, {210, 10} }; // Table 5.5.3.3-2 3GPP 36.211 TDD eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list = &(eNB->UE_list); + UE_info_t *UE_info = &eNB->UE_info; nfapi_ul_config_request_body_t *ul_req = NULL; UE_sched_ctrl_t *UE_scheduling_control = NULL; COMMON_channels_t *cc = eNB->common_channels; @@ -117,7 +116,7 @@ void schedule_SRS(module_id_t module_idP, if ((1 << tmp) & deltaTSFC) { /* This is an SRS subframe, loop over UEs */ for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (!UE_list->active[UE_id]) { + if (!UE_info->active[UE_id]) { continue; } @@ -126,14 +125,14 @@ void schedule_SRS(module_id_t module_idP, continue; } - if(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated == NULL) { + if(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated == NULL) { LOG_E(MAC,"physicalConfigDedicated is null for UE %d\n",UE_id); printf("physicalConfigDedicated is null for UE %d\n",UE_id); return; } /* CDRX condition on Active Time and SRS type-0 report (36.321 5.7) */ - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); + UE_scheduling_control = &(UE_info->UE_sched_ctrl[UE_id]); /* Test if Active Time not running since 6+ subframes */ if (UE_scheduling_control->cdrx_configured == TRUE && UE_scheduling_control->in_active_time == FALSE) { @@ -145,7 +144,7 @@ void schedule_SRS(module_id_t module_idP, ul_req = &(eNB->UL_req[CC_id].ul_config_request_body); - if ((soundingRS_UL_ConfigDedicated = UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated) != NULL) { + if ((soundingRS_UL_ConfigDedicated = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated) != NULL) { if (soundingRS_UL_ConfigDedicated->present == LTE_SoundingRS_UL_ConfigDedicated_PR_setup) { get_srs_pos(&cc[CC_id], soundingRS_UL_ConfigDedicated->choice.setup.srs_ConfigIndex, @@ -161,7 +160,7 @@ void schedule_SRS(module_id_t module_idP, ul_config_pdu->pdu_size = 2 + (uint8_t) (2 + sizeof(nfapi_ul_config_srs_pdu)); ul_config_pdu->srs_pdu.srs_pdu_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_SRS_PDU_REL8_TAG; ul_config_pdu->srs_pdu.srs_pdu_rel8.size = (uint8_t)sizeof(nfapi_ul_config_srs_pdu); - ul_config_pdu->srs_pdu.srs_pdu_rel8.rnti = UE_list->UE_template[CC_id][UE_id].rnti; + ul_config_pdu->srs_pdu.srs_pdu_rel8.rnti = UE_info->UE_template[CC_id][UE_id].rnti; ul_config_pdu->srs_pdu.srs_pdu_rel8.srs_bandwidth = soundingRS_UL_ConfigDedicated->choice.setup.srs_Bandwidth; ul_config_pdu->srs_pdu.srs_pdu_rel8.frequency_domain_position = soundingRS_UL_ConfigDedicated->choice.setup.freqDomainPosition; ul_config_pdu->srs_pdu.srs_pdu_rel8.srs_hopping_bandwidth = soundingRS_UL_ConfigDedicated->choice.setup.srs_HoppingBandwidth;; @@ -173,7 +172,7 @@ void schedule_SRS(module_id_t module_idP, ul_req->number_of_pdus++; } // if (((10*frameP+subframeP) % srsPeriodicity) == srsOffset) } // if (soundingRS_UL_ConfigDedicated->present == SoundingRS_UL_ConfigDedicated_PR_setup) - } // if ((soundingRS_UL_ConfigDedicated = UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated)!=NULL) + } // if ((soundingRS_UL_ConfigDedicated = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated)!=NULL) } // end for loop on UE_id } // if((1<UE_list; + UE_info_t *UE_info = &eNB->UE_info; COMMON_channels_t *cc = NULL; nfapi_ul_config_request_body_t *ul_req = NULL; UE_sched_ctrl_t *UE_scheduling_control = NULL; @@ -205,7 +204,7 @@ void schedule_CSI(module_id_t module_idP, cc = &eNB->common_channels[CC_id]; for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (UE_list->active[UE_id] == FALSE) { + if (UE_info->active[UE_id] == FALSE) { continue; } @@ -214,7 +213,7 @@ void schedule_CSI(module_id_t module_idP, continue; } - AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated != NULL, + AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated != NULL, "physicalConfigDedicated is null for UE %d\n", UE_id); /* @@ -222,7 +221,7 @@ void schedule_CSI(module_id_t module_idP, * Here we consider classic periodic reports on PUCCH without PUSCH simultaneous transmission condition. * TODO: add the handling or test on simultaneous PUCCH/PUSCH transmission */ - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); + UE_scheduling_control = &(UE_info->UE_sched_ctrl[UE_id]); if (UE_scheduling_control->cdrx_configured == TRUE) { /* Test if CQI masking activated */ @@ -246,8 +245,8 @@ void schedule_CSI(module_id_t module_idP, ul_req = &(eNB->UL_req[CC_id].ul_config_request_body); - if (UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->cqi_ReportConfig != NULL) { - cqi_ReportPeriodic = UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->cqi_ReportConfig->cqi_ReportPeriodic; + if (UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->cqi_ReportConfig != NULL) { + cqi_ReportPeriodic = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->cqi_ReportConfig->cqi_ReportPeriodic; if (cqi_ReportPeriodic != NULL) { /* Rel8 Periodic CSI (CQI/PMI/RI) reporting */ @@ -262,10 +261,10 @@ void schedule_CSI(module_id_t module_idP, ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_UCI_CQI_PDU_TYPE; ul_config_pdu->pdu_size = 2 + (uint8_t) (2 + sizeof(nfapi_ul_config_uci_cqi_pdu)); ul_config_pdu->uci_cqi_pdu.ue_information.ue_information_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_UE_INFORMATION_REL8_TAG; - ul_config_pdu->uci_cqi_pdu.ue_information.ue_information_rel8.rnti = UE_list->UE_template[CC_id][UE_id].rnti; + ul_config_pdu->uci_cqi_pdu.ue_information.ue_information_rel8.rnti = UE_info->UE_template[CC_id][UE_id].rnti; ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_CQI_INFORMATION_REL8_TAG; ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.pucch_index = cqi_ReportPeriodic->choice.setup.cqi_PUCCH_ResourceIndex; - ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.dl_cqi_pmi_size = get_rel8_dl_cqi_pmi_size(&UE_list->UE_sched_ctrl[UE_id], CC_id, cc, get_tmode(module_idP, CC_id, UE_id), + ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.dl_cqi_pmi_size = get_rel8_dl_cqi_pmi_size(&UE_info->UE_sched_ctrl[UE_id], CC_id, cc, get_tmode(module_idP, CC_id, UE_id), cqi_ReportPeriodic); ul_req->number_of_pdus++; ul_req->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; @@ -279,7 +278,7 @@ void schedule_CSI(module_id_t module_idP, ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_UCI_CQI_PDU_TYPE; ul_config_pdu->pdu_size = 2 + (uint8_t) (2 + sizeof(nfapi_ul_config_uci_cqi_pdu)); ul_config_pdu->uci_cqi_pdu.ue_information.ue_information_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_UE_INFORMATION_REL8_TAG; - ul_config_pdu->uci_cqi_pdu.ue_information.ue_information_rel8.rnti = UE_list->UE_template[CC_id][UE_id].rnti; + ul_config_pdu->uci_cqi_pdu.ue_information.ue_information_rel8.rnti = UE_info->UE_template[CC_id][UE_id].rnti; ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_CQI_INFORMATION_REL8_TAG; ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.pucch_index = cqi_ReportPeriodic->choice.setup.cqi_PUCCH_ResourceIndex; ul_config_pdu->uci_cqi_pdu.cqi_information.cqi_information_rel8.dl_cqi_pmi_size = (cc->p_eNB == 2) ? 1 : 2; @@ -291,7 +290,7 @@ void schedule_CSI(module_id_t module_idP, } // if CSI Periodic is not release state } // if (cqi_ReportPeriodic != NULL) } // if cqi_ReportConfig != NULL - } // for (UE_id=UE_list->head; UE_id>=0; UE_id=UE_list->next[UE_id]) { + } // for (UE_id=UE_info->head; UE_id>=0; UE_id=UE_info->next[UE_id]) { } // for (CC_id=0; CC_idUE_list; + UE_info_t *UE_info = &eNB->UE_info; nfapi_ul_config_request_t *ul_req = NULL; nfapi_ul_config_request_body_t *ul_req_body = NULL; LTE_SchedulingRequestConfig_t *SRconfig = NULL; @@ -319,13 +318,13 @@ schedule_SR (module_id_t module_idP, eNB->UL_req[CC_id].sfn_sf = (frameP << 4) + subframeP; for (int UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (!UE_list->active[UE_id]) { + if (!UE_info->active[UE_id]) { continue; } - if (UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated == NULL) continue; + if (UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated == NULL) continue; - if ((SRconfig = UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->schedulingRequestConfig) != NULL) { + if ((SRconfig = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->schedulingRequestConfig) != NULL) { if (SRconfig->present == LTE_SchedulingRequestConfig_PR_setup) { if (SRconfig->choice.setup.sr_ConfigIndex <= 4) { // 5 ms SR period if ((subframeP % 5) != SRconfig->choice.setup.sr_ConfigIndex) continue; @@ -337,9 +336,11 @@ schedule_SR (module_id_t module_idP, if ((10 * (frameP & 3) + subframeP) != (SRconfig->choice.setup.sr_ConfigIndex - 35)) continue; } else if (SRconfig->choice.setup.sr_ConfigIndex <= 154) { // 80 ms SR period if ((10 * (frameP & 7) + subframeP) != (SRconfig->choice.setup.sr_ConfigIndex - 75)) continue; + } else if (SRconfig->choice.setup.sr_ConfigIndex <= 156) { // 2ms SR period + if ((subframeP % 2) != (SRconfig->choice.setup.sr_ConfigIndex - 155)) continue; } } // SRconfig->present == SchedulingRequestConfig_PR_setup) - } // SRconfig = UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->schedulingRequestConfig)!=NULL) + } // SRconfig = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->schedulingRequestConfig)!=NULL) /* If we get here there is some PUCCH1 reception to schedule for SR */ ul_req = &(eNB->UL_req[CC_id]); @@ -354,14 +355,14 @@ schedule_SR (module_id_t module_idP, (ul_req_body->ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE) || (ul_req_body->ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_RI_PDU_TYPE) || (ul_req_body->ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE)) && - (ul_req_body->ul_config_pdu_list[i].ulsch_pdu.ulsch_pdu_rel8.rnti == UE_list->UE_template[CC_id][UE_id].rnti)) { + (ul_req_body->ul_config_pdu_list[i].ulsch_pdu.ulsch_pdu_rel8.rnti == UE_info->UE_template[CC_id][UE_id].rnti)) { skip_ue = 1; pdu_list_index = i; break; } /* If there is already an HARQ pdu, convert to SR_HARQ */ else if ((ul_req_body->ul_config_pdu_list[i].pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE) && - (ul_req_body->ul_config_pdu_list[i].uci_harq_pdu.ue_information.ue_information_rel8.rnti == UE_list->UE_template[CC_id][UE_id].rnti)) { + (ul_req_body->ul_config_pdu_list[i].uci_harq_pdu.ue_information.ue_information_rel8.rnti == UE_info->UE_template[CC_id][UE_id].rnti)) { is_harq = 1; pdu_list_index = i; break; @@ -375,20 +376,20 @@ schedule_SR (module_id_t module_idP, frameP, subframeP, UE_id, - UE_list->UE_template[CC_id][UE_id].rnti, + UE_info->UE_template[CC_id][UE_id].rnti, is_harq); /* Check Rel10 or Rel8 SR */ - if ((UE_list-> UE_template[CC_id][UE_id].physicalConfigDedicated->ext2) && - (UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->ext2->schedulingRequestConfig_v1020) && - (UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->ext2->schedulingRequestConfig_v1020)) { + if ((UE_info-> UE_template[CC_id][UE_id].physicalConfigDedicated->ext2) && + (UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->ext2->schedulingRequestConfig_v1020) && + (UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->ext2->schedulingRequestConfig_v1020)) { sr.sr_information_rel10.tl.tag = NFAPI_UL_CONFIG_REQUEST_SR_INFORMATION_REL10_TAG; sr.sr_information_rel10.number_of_pucch_resources = 1; - sr.sr_information_rel10.pucch_index_p1 = *UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->ext2->schedulingRequestConfig_v1020->sr_PUCCH_ResourceIndexP1_r10; + sr.sr_information_rel10.pucch_index_p1 = *UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->ext2->schedulingRequestConfig_v1020->sr_PUCCH_ResourceIndexP1_r10; LOG_D(MAC, "REL10 PUCCH INDEX P1:%d \n", sr.sr_information_rel10.pucch_index_p1); } else { sr.sr_information_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_SR_INFORMATION_REL8_TAG; - sr.sr_information_rel8.pucch_index = UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->schedulingRequestConfig->choice.setup.sr_PUCCH_ResourceIndex; + sr.sr_information_rel8.pucch_index = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->schedulingRequestConfig->choice.setup.sr_PUCCH_ResourceIndex; LOG_D(MAC, "REL8 PUCCH INDEX:%d\n", sr.sr_information_rel8.pucch_index); } @@ -401,7 +402,7 @@ schedule_SR (module_id_t module_idP, } else { ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].pdu_type = NFAPI_UL_CONFIG_UCI_SR_PDU_TYPE; ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].uci_sr_pdu.ue_information.ue_information_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_UE_INFORMATION_REL8_TAG; - ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].uci_sr_pdu.ue_information.ue_information_rel8.rnti = UE_list->UE_template[CC_id][UE_id].rnti; + ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].uci_sr_pdu.ue_information.ue_information_rel8.rnti = UE_info->UE_template[CC_id][UE_id].rnti; ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].uci_sr_pdu.ue_information.ue_information_rel11.tl.tag = 0; ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].uci_sr_pdu.ue_information.ue_information_rel13.tl.tag = 0; ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus].uci_sr_pdu.sr_information = sr; @@ -416,20 +417,20 @@ schedule_SR (module_id_t module_idP, void check_ul_failure(module_id_t module_idP, int CC_id, int UE_id, frame_t frameP, sub_frame_t subframeP) { - UE_list_t *UE_list = &RC.mac[module_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[module_idP]->UE_info; nfapi_dl_config_request_t *DL_req = &RC.mac[module_idP]->DL_req[0]; uint16_t rnti = UE_RNTI(module_idP, UE_id); COMMON_channels_t *cc = RC.mac[module_idP]->common_channels; // check uplink failure - if ((UE_list->UE_sched_ctrl[UE_id].ul_failure_timer > 0) && - (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 0)) { - if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer == 1) + if ((UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0) && + (UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 0)) { + if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer == 1) LOG_I(MAC, "UE %d rnti %x: UL Failure timer %d \n", UE_id, rnti, - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer); + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer); - if (UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent == 0) { - UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 1; + if (UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent == 0) { + UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 1; // add a format 1A dci for this UE to request an RA procedure (only one UE per subframe) nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_config_request_body.dl_config_pdu_list[DL_req[CC_id].dl_config_request_body.number_pdu]; memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_config_request_pdu_t)); @@ -438,7 +439,7 @@ check_ul_failure(module_id_t module_idP, int CC_id, int UE_id, dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = get_aggregation(get_bw_index(module_idP, CC_id), - UE_list->UE_sched_ctrl[UE_id]. + UE_info->UE_sched_ctrl[UE_id]. dl_cqi[CC_id], format1A); dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications @@ -454,22 +455,22 @@ check_ul_failure(module_id_t module_idP, int CC_id, int UE_id, LOG_D(MAC, "UE %d rnti %x: sending PDCCH order for RAPROC (failure timer %d), resource_block_coding %d \n", UE_id, rnti, - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer, + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer, dl_config_pdu->dci_dl_pdu. dci_dl_pdu_rel8.resource_block_coding); } else { // ra_pdcch_sent==1 LOG_D(MAC, "UE %d rnti %x: sent PDCCH order for RAPROC waiting (failure timer %d) \n", UE_id, rnti, - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer); + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer); - if ((UE_list->UE_sched_ctrl[UE_id].ul_failure_timer % 80) == 0) UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 0; // resend every 8 frames + if ((UE_info->UE_sched_ctrl[UE_id].ul_failure_timer % 80) == 0) UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 0; // resend every 8 frames } - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer++; + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer++; // check threshold - if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer > 4000) { + if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 4000) { // note: probably ul_failure_timer should be less than UE radio link failure time(see T310/N310/N311) if (NODE_IS_DU(RC.rrc[module_idP]->node_type)) { MessageDef *m = itti_alloc_new_message(TASK_MAC_ENB, F1AP_UE_CONTEXT_RELEASE_REQ); @@ -491,17 +492,17 @@ check_ul_failure(module_id_t module_idP, int CC_id, int UE_id, rnti); } - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 0; - UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync = 1; + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer = 0; + UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync = 1; } } // ul_failure_timer>0 - UE_list->UE_sched_ctrl[UE_id].uplane_inactivity_timer++; + UE_info->UE_sched_ctrl[UE_id].uplane_inactivity_timer++; - if((U_PLANE_INACTIVITY_VALUE != 0) && (UE_list->UE_sched_ctrl[UE_id].uplane_inactivity_timer > (U_PLANE_INACTIVITY_VALUE * 10))) { + if((U_PLANE_INACTIVITY_VALUE != 0) && (UE_info->UE_sched_ctrl[UE_id].uplane_inactivity_timer > (U_PLANE_INACTIVITY_VALUE * 10))) { LOG_D(MAC,"UE %d rnti %x: U-Plane Failure after repeated PDCCH orders: Triggering RRC \n",UE_id,rnti); mac_eNB_rrc_uplane_failure(module_idP,CC_id,frameP,subframeP,rnti); - UE_list->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; + UE_info->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; }// time > 60s } @@ -565,7 +566,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, int CC_id = 0; int UE_id = -1; eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list = &(eNB->UE_list); + UE_info_t *UE_info = &(eNB->UE_info); COMMON_channels_t *cc = eNB->common_channels; UE_sched_ctrl_t *UE_scheduling_control = NULL; start_meas(&(eNB->eNB_scheduler)); @@ -584,16 +585,16 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, /* Refresh UE list based on UEs dropped by PHY in previous subframe */ for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (UE_list->active[UE_id]) { + if (UE_info->active[UE_id]) { rnti = UE_RNTI(module_idP, UE_id); CC_id = UE_PCCID(module_idP, UE_id); - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); + UE_scheduling_control = &(UE_info->UE_sched_ctrl[UE_id]); if (((frameP & 127) == 0) && (subframeP == 0)) { LOG_I(MAC,"UE rnti %x : %s, PHR %d dB DL CQI %d PUSCH SNR %d PUCCH SNR %d\n", rnti, UE_scheduling_control->ul_out_of_sync == 0 ? "in synch" : "out of sync", - UE_list->UE_template[CC_id][UE_id].phr_info, + UE_info->UE_template[CC_id][UE_id].phr_info, UE_scheduling_control->dl_cqi[CC_id], (5 * UE_scheduling_control->pusch_snr[CC_id] - 640) / 10, (5 * UE_scheduling_control->pucch1_snr[CC_id] - 640) / 10); @@ -601,7 +602,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, RC.eNB[module_idP][CC_id]->pusch_stats_bsr[UE_id][(frameP * 10) + subframeP] = -63; - if (UE_id == UE_list->head) { + if (UE_id == UE_info->list.head) { VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_BSR, RC.eNB[module_idP][CC_id]->pusch_stats_bsr[UE_id][(frameP * 10) + subframeP]); } @@ -735,7 +736,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, * here for the current subframe. The variable 'UE_scheduling_control->in_active_time' should be updated * ONLY here. The variable can then be used for testing the actual state of the UE for scheduling purpose. */ - UE_template = &(UE_list->UE_template[CC_id][UE_id]); + UE_template = &(UE_info->UE_template[CC_id][UE_id]); /* (a)synchronous HARQ processes handling for Active Time */ for (int harq_process_id = 0; harq_process_id < 8; harq_process_id++) { @@ -981,7 +982,9 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, /* Allocate CCEs for good after scheduling is done */ for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { if (cc[CC_id].tdd_Config == NULL || !(is_UL_sf(&cc[CC_id],subframeP))) { - allocate_CCEs(module_idP, CC_id, frameP, subframeP, 2); + int rc = allocate_CCEs(module_idP, CC_id, frameP, subframeP, 2); + if (rc < 0) + LOG_E(MAC, "%s() %4d.%d ERROR ALLOCATING CCEs\n", __func__, frameP, subframeP); } } diff --git a/openair2/LAYER2/MAC/eNB_scheduler_RA.c b/openair2/LAYER2/MAC/eNB_scheduler_RA.c index fb765e6dac..d1365b9ac3 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_RA.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_RA.c @@ -587,7 +587,7 @@ generate_Msg4(module_id_t module_idP, { eNB_MAC_INST *mac = RC.mac[module_idP]; COMMON_channels_t *cc = mac->common_channels; - UE_list_t *UE_list = &(mac->UE_list); + UE_info_t *UE_info = &mac->UE_info; int16_t rrc_sdu_length = 0; uint16_t msg4_padding = 0; uint16_t msg4_post_padding = 0; @@ -831,7 +831,7 @@ generate_Msg4(module_id_t module_idP, dl_req_body->number_pdu++; ra->state = WAITMSG4ACK; lcid = 0; - UE_list->UE_sched_ctrl[UE_id].round[CC_idP][ra->harq_pid] = 0; + UE_info->UE_sched_ctrl[UE_id].round[CC_idP][ra->harq_pid] = 0; msg4_header = 1 + 6 + 1; // CR header, CR CE, SDU header AssertFatal((ra->msg4_TBsize - ra->msg4_rrc_sdu_length - msg4_header)>=0, "msg4_TBS %d is too small, change mcs to increase by %d bytes\n",ra->msg4_TBsize,ra->msg4_rrc_sdu_length+msg4_header-ra->msg4_TBsize); @@ -848,7 +848,7 @@ generate_Msg4(module_id_t module_idP, module_idP, CC_idP, frameP, subframeP, ra->msg4_TBsize, ra->msg4_rrc_sdu_length, msg4_header, msg4_padding, msg4_post_padding); DevAssert (UE_id != UE_INDEX_INVALID); // FIXME not sure how to gracefully return // CHECK THIS: &cc[CC_idP].CCCH_pdu.payload[0] - offset = generate_dlsch_header ((unsigned char *) mac->UE_list.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0], 1, //num_sdus + offset = generate_dlsch_header ((unsigned char *) mac->UE_info.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0], 1, //num_sdus (unsigned short *) &ra->msg4_rrc_sdu_length, // &lcid, // sdu_lcid 255, // no drx @@ -856,7 +856,7 @@ generate_Msg4(module_id_t module_idP, ra->cont_res_id, // contention res id msg4_padding, // no padding msg4_post_padding); - memcpy ((void *) &mac->UE_list.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0][(unsigned char) offset], &cc[CC_idP].CCCH_pdu.payload[0], ra->msg4_rrc_sdu_length); + memcpy ((void *) &mac->UE_info.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0][(unsigned char) offset], &cc[CC_idP].CCCH_pdu.payload[0], ra->msg4_rrc_sdu_length); // DL request mac->TX_req[CC_idP].sfn_sf = (frameP << 4) + subframeP; TX_req = &mac->TX_req[CC_idP].tx_request_body.tx_pdu_list[mac->TX_req[CC_idP].tx_request_body.number_of_pdus]; @@ -864,7 +864,7 @@ generate_Msg4(module_id_t module_idP, TX_req->pdu_index = mac->pdu_index[CC_idP]++; TX_req->num_segments = 1; TX_req->segments[0].segment_length = ra->msg4_TBsize; - TX_req->segments[0].segment_data = mac->UE_list.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0]; + TX_req->segments[0].segment_data = mac->UE_info.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0]; mac->TX_req[CC_idP].tx_request_body.number_of_pdus++; // Program ACK/NAK for Msg4 PDSCH int absSF = (frameP * 10) + subframeP; @@ -899,8 +899,8 @@ generate_Msg4(module_id_t module_idP, ul_req_body->number_of_pdus++; T (T_ENB_MAC_UE_DL_PDU_WITH_DATA, T_INT (module_idP), T_INT (CC_idP), T_INT (ra->rnti), T_INT (frameP), T_INT (subframeP), - T_INT (0 /*harq_pid always 0? */ ), T_BUFFER (&mac->UE_list.DLSCH_pdu[CC_idP][0][UE_id].payload[0], ra->msg4_TBsize)); - trace_pdu (DIRECTION_DOWNLINK, (uint8_t *) mac->UE_list.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0], + T_INT (0 /*harq_pid always 0? */ ), T_BUFFER (&mac->UE_info.DLSCH_pdu[CC_idP][0][UE_id].payload[0], ra->msg4_TBsize)); + trace_pdu (DIRECTION_DOWNLINK, (uint8_t *) mac->UE_info.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0], ra->msg4_rrc_sdu_length, UE_id, 3, UE_RNTI (module_idP, UE_id), mac->frame, mac->subframe, 0, 0); @@ -963,10 +963,10 @@ generate_Msg4(module_id_t module_idP, 1, // tpc, none getRIV(N_RB_DL, first_rb, 4), // resource_block_coding ra->msg4_mcs, // mcs - 1 - UE_list->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid], + 1 - UE_info->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid], 0, // rv 0); // vrb_flag - UE_list->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid] = 1 - UE_list->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid]; + UE_info->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid] = 1 - UE_info->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid]; LOG_D(MAC, "Frame %d, subframe %d: Msg4 DCI pdu_num %d (rnti %x,rnti_type %d,harq_pid %d, resource_block_coding (%p) %d\n", frameP, subframeP, dl_req_body->number_pdu, @@ -1000,7 +1000,7 @@ generate_Msg4(module_id_t module_idP, lcid = 0; // put HARQ process round to 0 ra->harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP,subframeP); - UE_list->UE_sched_ctrl[UE_id].round[CC_idP][ra->harq_pid] = 0; + UE_info->UE_sched_ctrl[UE_id].round[CC_idP][ra->harq_pid] = 0; if ((ra->msg4_TBsize - rrc_sdu_length - msg4_header) <= 2) { msg4_padding = ra->msg4_TBsize - rrc_sdu_length - msg4_header; @@ -1018,7 +1018,7 @@ generate_Msg4(module_id_t module_idP, DevAssert(UE_id != UE_INDEX_INVALID); // FIXME not sure how to gracefully return // CHECK THIS: &cc[CC_idP].CCCH_pdu.payload[0] int num_sdus = rrc_sdu_length > 0 ? 1 : 0; - offset = generate_dlsch_header((unsigned char *) mac->UE_list.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0], + offset = generate_dlsch_header((unsigned char *) mac->UE_info.DLSCH_pdu[CC_idP][0][(unsigned char) UE_id].payload[0], num_sdus, //num_sdus (unsigned short *) &rrc_sdu_length, // &lcid, // sdu_lcid @@ -1027,10 +1027,14 @@ generate_Msg4(module_id_t module_idP, ra->cont_res_id, // contention res id msg4_padding, // no padding msg4_post_padding); - memcpy((void *) &mac->UE_list.DLSCH_pdu[CC_idP][0][(unsigned char)UE_id].payload[0][(unsigned char)offset], + memcpy((void *) &mac->UE_info.DLSCH_pdu[CC_idP][0][(unsigned char)UE_id].payload[0][(unsigned char)offset], &cc[CC_idP].CCCH_pdu.payload[0], rrc_sdu_length); // DLSCH Config - fill_nfapi_dlsch_config(mac, dl_req_body, ra->msg4_TBsize, mac->pdu_index[CC_idP], ra->rnti, 2, // resource_allocation_type : format 1A/1B/1D + fill_nfapi_dlsch_config(&dl_req_body->dl_config_pdu_list[dl_req_body->number_pdu], + ra->msg4_TBsize, + mac->pdu_index[CC_idP], + ra->rnti, + 2, // resource_allocation_type : format 1A/1B/1D 0, // virtual_resource_block_assignment_flag : localized getRIV(N_RB_DL, first_rb, 4), // resource_block_coding : RIV, 4 PRB 2, // modulation: QPSK @@ -1049,6 +1053,7 @@ generate_Msg4(module_id_t module_idP, (cc->p_eNB == 1) ? 1 : 2, // transmission mode 1, // num_bf_prb_per_subband 1); // num_bf_vector + dl_req_body->number_pdu++; LOG_D(MAC, "Filled DLSCH config, pdu number %d, non-dci pdu_index %d\n", dl_req_body->number_pdu, mac->pdu_index[CC_idP]); @@ -1058,7 +1063,7 @@ generate_Msg4(module_id_t module_idP, (frameP * 10) + subframeP, rrc_sdu_length+offset, mac->pdu_index[CC_idP], - mac->UE_list. + mac->UE_info. DLSCH_pdu[CC_idP][0][(unsigned char)UE_id].payload[0]); mac->pdu_index[CC_idP]++; dl_req->sfn_sf = mac->TX_req[CC_idP].sfn_sf; @@ -1074,11 +1079,11 @@ generate_Msg4(module_id_t module_idP, T(T_ENB_MAC_UE_DL_PDU_WITH_DATA, T_INT(module_idP), T_INT(CC_idP), T_INT(ra->rnti), T_INT(frameP), T_INT(subframeP), T_INT(0 /*harq_pid always 0? */ ), - T_BUFFER(&mac->UE_list.DLSCH_pdu[CC_idP][0][UE_id]. + T_BUFFER(&mac->UE_info.DLSCH_pdu[CC_idP][0][UE_id]. payload[0], ra->msg4_TBsize)); trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) mac-> - UE_list.DLSCH_pdu[CC_idP][0][(unsigned char)UE_id].payload[0], + UE_info.DLSCH_pdu[CC_idP][0][(unsigned char)UE_id].payload[0], rrc_sdu_length, UE_id, WS_C_RNTI, UE_RNTI(module_idP, UE_id), mac->frame, mac->subframe, 0, 0); @@ -1116,14 +1121,14 @@ check_Msg4_retransmission(module_id_t module_idP, int CC_idP, int first_rb; int N_RB_DL; nfapi_dl_config_request_pdu_t *dl_config_pdu; - UE_list_t *UE_list = &mac->UE_list; + UE_info_t *UE_info = &mac->UE_info; nfapi_dl_config_request_t *dl_req; nfapi_dl_config_request_body_t *dl_req_body; int round; // check HARQ status and retransmit if necessary UE_id = find_UE_id(module_idP, ra->rnti); AssertFatal(UE_id >= 0, "Can't find UE for t-crnti\n"); - round = UE_list->UE_sched_ctrl[UE_id].round[CC_idP][ra->harq_pid]; + round = UE_info->UE_sched_ctrl[UE_id].round[CC_idP][ra->harq_pid]; vrb_map = cc[CC_idP].vrb_map; dl_req = &mac->DL_req[CC_idP]; dl_req_body = &dl_req->dl_config_request_body; @@ -1156,7 +1161,7 @@ check_Msg4_retransmission(module_id_t module_idP, int CC_idP, 1, // tpc, none getRIV(N_RB_DL, first_rb, 4), // resource_block_coding ra->msg4_mcs, // mcs - UE_list->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid], + UE_info->UE_template[CC_idP][UE_id].oldNDI[ra->harq_pid], round & 3, // rv 0); // vrb_flag @@ -1173,7 +1178,8 @@ check_Msg4_retransmission(module_id_t module_idP, int CC_idP, // DLSCH Config //DJP - fix this pdu_index = -1 LOG_D(MAC, "check_Msg4_retransmission() before fill_nfapi_dlsch_config() with pdu_index = -1 \n"); - fill_nfapi_dlsch_config(mac, dl_req_body, ra->msg4_TBsize, + fill_nfapi_dlsch_config(&dl_req_body->dl_config_pdu_list[dl_req_body->number_pdu], + ra->msg4_TBsize, -1 /* retransmission, no pdu_index */ , ra->rnti, 2, // resource_allocation_type : format 1A/1B/1D @@ -1195,6 +1201,7 @@ check_Msg4_retransmission(module_id_t module_idP, int CC_idP, (cc->p_eNB == 1) ? 1 : 2, // transmission mode 1, // num_bf_prb_per_subband 1); // num_bf_vector + dl_req_body->number_pdu++; if(RC.mac[module_idP]->scheduler_mode == SCHED_MODE_FAIR_RR) { set_dl_ue_select_msg4(CC_idP, 4, UE_id, ra->rnti); @@ -1226,8 +1233,8 @@ check_Msg4_retransmission(module_id_t module_idP, int CC_idP, LOG_D(MAC,"[eNB %d][RAPROC] Frame %d, Subframe %d: state:IDLE\n", module_idP, frameP, subframeP); UE_id = find_UE_id(module_idP, ra->rnti); DevAssert(UE_id != -1); - mac->UE_list.UE_template[UE_PCCID(module_idP, UE_id)][UE_id].configured = TRUE; - mac->UE_list.UE_template[UE_PCCID(module_idP, UE_id)][UE_id].pusch_repetition_levels=ra->pusch_repetition_levels; + mac->UE_info.UE_template[UE_PCCID(module_idP, UE_id)][UE_id].configured = TRUE; + mac->UE_info.UE_template[UE_PCCID(module_idP, UE_id)][UE_id].pusch_repetition_levels=ra->pusch_repetition_levels; cancel_ra_proc(module_idP, CC_idP, frameP, ra->rnti); } } diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index eba4bdcee9..7621994ab2 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -86,31 +86,6 @@ add_ue_dlsch_info(module_id_t module_idP, return; } -//------------------------------------------------------------------------------ -int -schedule_next_dlue(module_id_t module_idP, - int CC_id, - sub_frame_t subframeP) -//------------------------------------------------------------------------------ -{ - int next_ue; - UE_list_t *UE_list = &RC.mac[module_idP]->UE_list; - - for (next_ue = UE_list->head; next_ue >= 0; next_ue = UE_list->next[next_ue]) { - if (eNB_dlsch_info[module_idP][CC_id][next_ue].status == S_DL_WAITING) { - return next_ue; - } - } - - for (next_ue = UE_list->head; next_ue >= 0; next_ue = UE_list->next[next_ue]) { - if (eNB_dlsch_info[module_idP][CC_id][next_ue].status == S_DL_BUFFERED) { - eNB_dlsch_info[module_idP][CC_id][next_ue].status = S_DL_WAITING; - } - } - - return (-1); //next_ue; -} - //------------------------------------------------------------------------------ int generate_dlsch_header(unsigned char *mac_header, @@ -317,12 +292,12 @@ set_ul_DAI(int module_idP, //------------------------------------------------------------------------------ { eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; unsigned char DAI; COMMON_channels_t *cc = &eNB->common_channels[CC_idP]; if (cc->tdd_Config != NULL) { //TDD - DAI = (UE_list->UE_template[CC_idP][UE_idP].DAI - 1) & 3; + DAI = (UE_info->UE_template[CC_idP][UE_idP].DAI - 1) & 3; LOG_D(MAC, "[eNB %d] CC_id %d Frame %d, subframe %d: DAI %d for UE %d\n", module_idP, CC_idP, @@ -341,20 +316,20 @@ set_ul_DAI(int module_idP, switch (subframeP) { case 0: case 1: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[7] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[7] = DAI; break; case 4: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[8] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[8] = DAI; break; case 5: case 6: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[2] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[2] = DAI; break; case 9: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[3] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[3] = DAI; break; } @@ -362,30 +337,30 @@ set_ul_DAI(int module_idP, case 2: // if ((subframeP==3)||(subframeP==8)) - // UE_list->UE_template[CC_idP][UE_idP].DAI_ul = DAI; + // UE_info->UE_template[CC_idP][UE_idP].DAI_ul = DAI; break; case 3: //if ((subframeP==6)||(subframeP==8)||(subframeP==0)) { // LOG_D(MAC,"schedule_ue_spec: setting UL DAI to %d for subframeP %d => %d\n",DAI,subframeP, ((subframeP+8)%10)>>1); - // UE_list->UE_template[CC_idP][UE_idP].DAI_ul[((subframeP+8)%10)>>1] = DAI; + // UE_info->UE_template[CC_idP][UE_idP].DAI_ul[((subframeP+8)%10)>>1] = DAI; //} switch (subframeP) { case 5: case 6: case 1: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[2] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[2] = DAI; break; case 7: case 8: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[3] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[3] = DAI; break; case 9: case 0: - UE_list->UE_template[CC_idP][UE_idP].DAI_ul[4] = DAI; + UE_info->UE_template[CC_idP][UE_idP].DAI_ul[4] = DAI; break; default: @@ -396,17 +371,17 @@ set_ul_DAI(int module_idP, case 4: // if ((subframeP==8)||(subframeP==9)) - // UE_list->UE_template[CC_idP][UE_idP].DAI_ul = DAI; + // UE_info->UE_template[CC_idP][UE_idP].DAI_ul = DAI; break; case 5: // if (subframeP==8) - // UE_list->UE_template[CC_idP][UE_idP].DAI_ul = DAI; + // UE_info->UE_template[CC_idP][UE_idP].DAI_ul = DAI; break; case 6: // if ((subframeP==1)||(subframeP==4)||(subframeP==6)||(subframeP==9)) - // UE_list->UE_template[CC_idP][UE_idP].DAI_ul = DAI; + // UE_info->UE_template[CC_idP][UE_idP].DAI_ul = DAI; break; default: @@ -417,20 +392,129 @@ set_ul_DAI(int module_idP, return; } +void ue_rrc_release(rnti_t rnti) { + if(rrc_release_info.num_UEs == 0 || rlc_am_mui.rrc_mui_num == 0) { + return; + } + + while(pthread_mutex_trylock(&rrc_release_freelist)) { + /* spin... */ + } + + uint16_t release_total = 0; + + for (uint16_t n = 0; n < NUMBER_OF_UE_MAX; n++) { + RRC_release_ctrl_t *release_ctrl = &rrc_release_info.RRC_release_ctrl[n]; + if(release_ctrl->flag == 0) + continue; + + release_total++; + if(release_ctrl->flag == 1 && release_ctrl->rnti == rnti) { + for(uint16_t mui_num = 0; mui_num < rlc_am_mui.rrc_mui_num; mui_num++) { + if(release_ctrl->rrc_eNB_mui == rlc_am_mui.rrc_mui[mui_num]) { + release_ctrl->flag = 3; + LOG_D(MAC, + "DLSCH Release send:index %d rnti %x mui %d mui_num %d flag 1->3\n", + n, rnti, rlc_am_mui.rrc_mui[mui_num], mui_num); + break; + } + } + } + + if(release_ctrl->flag == 2 && release_ctrl->rnti == rnti) { + for (uint16_t mui_num = 0; mui_num < rlc_am_mui.rrc_mui_num; mui_num++) { + if(release_ctrl->rrc_eNB_mui == rlc_am_mui.rrc_mui[mui_num]) { + release_ctrl->flag = 4; + LOG_D(MAC, "DLSCH Release send:index %d rnti %x mui %d mui_num %d flag 2->4\n", + n, + rnti, + rlc_am_mui.rrc_mui[mui_num], + mui_num); + break; + } + } + } + + if(release_total >= rrc_release_info.num_UEs) + break; + } + + pthread_mutex_unlock(&rrc_release_freelist); +} + +void check_ra_rnti_mui(module_id_t mod_id, int CC_id, frame_t f, sub_frame_t sf, rnti_t rnti) { + LTE_TDD_Config_t *tdd_config = RC.mac[mod_id]->common_channels[CC_id].tdd_Config; + int harq_pid = frame_subframe2_dl_harq_pid(tdd_config, f, sf); + RA_t *ra = &RC.mac[mod_id]->common_channels[CC_id].ra[0]; + for (uint8_t ra_ii = 0; ra_ii < NB_RA_PROC_MAX; ra_ii++, ra++) { + if ((ra->rnti == rnti) && (ra->state == MSGCRNTI)) { + for (uint16_t mui_num = 0; mui_num < rlc_am_mui.rrc_mui_num; mui_num++) { + if (ra->crnti_rrc_mui == rlc_am_mui.rrc_mui[mui_num]) { + ra->crnti_harq_pid = harq_pid; + ra->state = MSGCRNTI_ACK; + break; + } + } + } + } +} + //------------------------------------------------------------------------------ void schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, int *mbsfn_flag) { - int i = 0; - slice_info_t *sli = &RC.mac[module_idP]->slice_info; - memset(sli->rballoc_sub, 0, sizeof(sli->rballoc_sub)); + if (is_pmch_subframe(frameP, subframeP, &RC.eNB[module_idP][0]->frame_parms)) + return; - for (i = 0; i < sli->n_dl; i++) { - // Run each enabled slice-specific schedulers one by one - sli->dl[i].sched_cb(module_idP, - i, - frameP, - subframeP, - mbsfn_flag/*, dl_info*/); + for (int CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) { + // for TDD: check that we have to act here, otherwise skip + COMMON_channels_t *cc = &RC.mac[module_idP]->common_channels[CC_id]; + if (cc->tdd_Config) { + int tdd_sfa = cc->tdd_Config->subframeAssignment; + + switch (subframeP) { + case 0: + // always continue + break; + + case 1: + case 2: + continue; + + case 3: + if (tdd_sfa != 2 && tdd_sfa != 5) + continue; + break; + + case 4: + if (tdd_sfa != 1 && tdd_sfa != 2 && tdd_sfa != 4 && tdd_sfa != 5) + continue; + break; + + case 5: + break; + + case 6: + case 7: + if (tdd_sfa != 3 && tdd_sfa != 4 && tdd_sfa != 5) + continue; + break; + + case 8: + if (tdd_sfa != 2 && tdd_sfa != 3 && tdd_sfa != 4 && tdd_sfa != 5) + continue; + break; + + case 9: + if (tdd_sfa == 0) + continue; + break; + } + } + + if (mbsfn_flag[CC_id] != 0) + continue; + + schedule_ue_spec(module_idP, CC_id, frameP, subframeP); } } @@ -454,138 +538,35 @@ void getRepetition(UE_TEMPLATE *pue_template,unsigned int *maxRep, unsigned int */ void schedule_ue_spec(module_id_t module_idP, - int slice_idxP, + int CC_id, frame_t frameP, - sub_frame_t subframeP, - int *mbsfn_flag) + sub_frame_t subframeP) //------------------------------------------------------------------------------ { - int CC_id; - int UE_id; - int aggregation; - mac_rlc_status_resp_t rlc_status; - int ta_len = 0; - unsigned char sdu_lcids[NB_RB_MAX]; - int lcid, offset, num_sdus = 0; - int nb_rb, nb_rb_temp, nb_available_rb; - uint16_t sdu_lengths[NB_RB_MAX]; - int TBS, j, padding = 0, post_padding = 0; - rnti_t rnti; unsigned char dlsch_buffer[MAX_DLSCH_PAYLOAD_BYTES]; - int round_DL = 0; - int harq_pid = 0; - uint16_t release_num; - uint8_t ra_ii; - eNB_UE_STATS *eNB_UE_stats = NULL; - UE_TEMPLATE *ue_template = NULL; - eNB_STATS *eNB_stats = NULL; - RRC_release_ctrl_t *release_ctrl = NULL; - DLSCH_PDU *dlsch_pdu = NULL; - RA_t *ra = NULL; - int sdu_length_total = 0; eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = eNB->common_channels; - UE_list_t *UE_list = &eNB->UE_list; - int continue_flag = 0; - int32_t snr, target_snr; - int tpc = 1; - UE_sched_ctrl_t *ue_sched_ctrl; - int mcs; - int i; - int min_rb_unit[NFAPI_CC_MAX]; - int N_RB_DL[NFAPI_CC_MAX]; - int total_nb_available_rb[NFAPI_CC_MAX]; - int N_RBG[NFAPI_CC_MAX]; - nfapi_dl_config_request_body_t *dl_req; - nfapi_dl_config_request_pdu_t *dl_config_pdu; - int tdd_sfa; - int ta_update; - int header_length_last; - int header_length_total; - rrc_eNB_ue_context_t *ue_contextP = NULL; - int nb_mac_CC = RC.nb_mac_CC[module_idP]; - long dl_Bandwidth; - - if(is_pmch_subframe(frameP,subframeP,&RC.eNB[module_idP][0]->frame_parms)){ - //LOG_E(MAC,"Frame[%d] SF:%d This SF should not be allocated\n",frameP,subframeP); - return ; - } - + UE_info_t *UE_info = &eNB->UE_info; + const int dl_Bandwidth = cc[CC_id].mib->message.dl_Bandwidth; + const int N_RB_DL = to_prb(dl_Bandwidth); + const int N_RBG = to_rbg(eNB->common_channels[CC_id].mib->message.dl_Bandwidth); + int total_nb_available_rb = N_RB_DL; + nfapi_dl_config_request_body_t *dl_req = &eNB->DL_req[CC_id].dl_config_request_body; start_meas(&eNB->schedule_dlsch); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_SCHEDULE_DLSCH, VCD_FUNCTION_IN); - // for TDD: check that we have to act here, otherwise return - if (cc[0].tdd_Config) { - tdd_sfa = cc[0].tdd_Config->subframeAssignment; + for (int i = 0; i < N_RB_DL; i++) + if (cc[CC_id].vrb_map[i] != 0) + total_nb_available_rb--; - switch (subframeP) { - case 0: - // always continue - break; - - case 1: - case 2: - return; - - case 3: - if (tdd_sfa != 2 && tdd_sfa != 5) - return; - - break; - - case 4: - if (tdd_sfa != 1 && tdd_sfa != 2 && tdd_sfa != 4 && tdd_sfa != 5) - return; - - break; - - case 5: - break; - - case 6: - case 7: - if (tdd_sfa != 3 && tdd_sfa != 4 && tdd_sfa != 5) - return; - - break; - - case 8: - if (tdd_sfa != 2 && tdd_sfa != 3 && tdd_sfa != 4 && tdd_sfa != 5) - return; - - break; - - case 9: - if (tdd_sfa == 0) - return; - - break; - } - } - - aggregation = 2; - - for (CC_id = 0, eNB_stats = &eNB->eNB_stats[0]; CC_id < nb_mac_CC; CC_id++, eNB_stats++) { - dl_Bandwidth = cc[CC_id].mib->message.dl_Bandwidth; - N_RB_DL[CC_id] = to_prb(dl_Bandwidth); - min_rb_unit[CC_id] = get_min_rb_unit(module_idP, CC_id); - // get number of PRBs less those used by common channels - total_nb_available_rb[CC_id] = N_RB_DL[CC_id]; - - for (i = 0; i < N_RB_DL[CC_id]; i++) - if (cc[CC_id].vrb_map[i] != 0) - total_nb_available_rb[CC_id]--; - - N_RBG[CC_id] = to_rbg(dl_Bandwidth); - // store the global enb stats: - eNB_stats->num_dlactive_UEs = UE_list->num_UEs; - eNB_stats->available_prbs = total_nb_available_rb[CC_id]; - eNB_stats->total_available_prbs += total_nb_available_rb[CC_id]; - eNB_stats->dlsch_bytes_tx = 0; - eNB_stats->dlsch_pdus_tx = 0; - } + // store the global enb stats: + eNB->eNB_stats[CC_id].num_dlactive_UEs = UE_info->num_UEs; + eNB->eNB_stats[CC_id].available_prbs = total_nb_available_rb; + eNB->eNB_stats[CC_id].total_available_prbs += total_nb_available_rb; + eNB->eNB_stats[CC_id].dlsch_bytes_tx = 0; + eNB->eNB_stats[CC_id].dlsch_pdus_tx = 0; // CALLING Pre_Processor for downlink scheduling // (Returns estimation of RBs required by each UE and the allocation on sub-band) @@ -593,1259 +574,626 @@ schedule_ue_spec(module_id_t module_idP, VCD_FUNCTION_IN); start_meas(&eNB->schedule_dlsch_preprocessor); dlsch_scheduler_pre_processor(module_idP, - slice_idxP, + CC_id, frameP, - subframeP, - mbsfn_flag, - eNB->slice_info.rballoc_sub); + subframeP); stop_meas(&eNB->schedule_dlsch_preprocessor); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_OUT); - if (RC.mac[module_idP]->slice_info.interslice_share_active) { - dlsch_scheduler_interslice_multiplexing(module_idP, - frameP, - subframeP, - eNB->slice_info.rballoc_sub); - /* the interslice multiplexing re-sorts the UE_list for the slices it tries - * to multiplex, so we need to sort it for the current slice again */ - sort_UEs(module_idP, - slice_idxP, - frameP, - subframeP); - } + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + LOG_D(MAC, "doing schedule_ue_spec for CC_id %d UE %d\n", + CC_id, + UE_id); + UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; + eNB_UE_STATS *eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + const rnti_t rnti = ue_template->rnti; - for (CC_id = 0; CC_id < nb_mac_CC; CC_id++) { - LOG_D(MAC, "doing schedule_ue_spec for CC_id %d\n", - CC_id); - dl_req = &eNB->DL_req[CC_id].dl_config_request_body; + // If TDD + if (cc[CC_id].tdd_Config != NULL) { //TDD + set_ue_dai(subframeP, + UE_id, + CC_id, + cc[CC_id].tdd_Config->subframeAssignment, + UE_info); + // update UL DAI after DLSCH scheduling + set_ul_DAI(module_idP, + UE_id, + CC_id, + frameP, + subframeP); + } - if (mbsfn_flag[CC_id] > 0) + ue_rrc_release(rnti); + check_ra_rnti_mui(module_idP, CC_id, frameP, subframeP, rnti); + + if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0) { // no RBs allocated + LOG_D(MAC, "%d.%d: no RBs allocated for UE %d on CC_id %d\n", + frameP, + subframeP, + UE_id, + CC_id); continue; + } - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - LOG_D(MAC, "doing schedule_ue_spec for CC_id %d UE %d\n", - CC_id, - UE_id); - continue_flag = 0; // reset the flag to allow allocation for the remaining UEs - rnti = UE_RNTI(module_idP, UE_id); - ue_sched_ctrl = &UE_list->UE_sched_ctrl[UE_id]; - ue_template = &UE_list->UE_template[CC_id][UE_id]; - - if (ue_template->rach_resource_type > 0) { - continue_flag = 1; + int dci_dl_pdu_idx = ue_sched_ctrl->pre_dci_dl_pdu_idx; + if (dci_dl_pdu_idx < 0) { + dci_dl_pdu_idx = CCE_try_allocate_dlsch( + module_idP, CC_id, subframeP, UE_id, ue_sched_ctrl->dl_cqi[CC_id]); + if (dci_dl_pdu_idx < 0) { + LOG_W(MAC, "%d.%d: Dropping Allocation for RNTI 0x%04x/UE %d\n", + frameP, + subframeP, + rnti, + UE_id); + continue; } + } - if (&(UE_list->eNB_UE_stats[CC_id][UE_id]) == NULL) { - LOG_D(MAC, "[eNB] Cannot find eNB_UE_stats\n"); - continue_flag = 1; - } else { - eNB_UE_stats = &(UE_list->eNB_UE_stats[CC_id][UE_id]); - } + /* verify it is the right UE */ + nfapi_dl_config_request_pdu_t *dci = &dl_req->dl_config_pdu_list[dci_dl_pdu_idx]; + nfapi_dl_config_request_pdu_t *dlsch = &dl_req->dl_config_pdu_list[dci_dl_pdu_idx + 1]; + if (dci->pdu_type != NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE + || dci->dci_dl_pdu.dci_dl_pdu_rel8.rnti != rnti + || dlsch->pdu_type != NFAPI_DL_CONFIG_DLSCH_PDU_TYPE + || dlsch->dlsch_pdu.dlsch_pdu_rel8.rnti != rnti) { + LOG_E(MAC, "illegal dl_config_pdu_list index %d for UE %d/RNTI %04x\n", + dci_dl_pdu_idx, + UE_id, + rnti); + continue; + } - if (continue_flag != 1) { - switch (get_tmode(module_idP, - CC_id, - UE_id)) { - case 1: - case 2: - case 7: - aggregation = get_aggregation(get_bw_index(module_idP, - CC_id), - ue_sched_ctrl->dl_cqi[CC_id], - format1); - break; + const int harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, + frameP, + subframeP); + const int round_DL = ue_sched_ctrl->round[CC_id][harq_pid]; + eNB_UE_stats->crnti = rnti; + eNB_UE_stats->rrc_status = mac_eNB_get_rrc_status(module_idP, rnti); + eNB_UE_stats->harq_pid = harq_pid; + eNB_UE_stats->harq_round = round_DL; - case 3: - aggregation = get_aggregation(get_bw_index(module_idP, - CC_id), - ue_sched_ctrl->dl_cqi[CC_id], - format2A); - break; + if (eNB_UE_stats->rrc_status < RRC_RECONFIGURED) { + ue_sched_ctrl->uplane_inactivity_timer = 0; + } - default: - AssertFatal(1==0,"Unsupported transmission mode %d\n", get_tmode(module_idP, CC_id, UE_id)); - aggregation = 2; - break; - } - } + LOG_D(MAC, "[eNB %d] Frame %d: Scheduling UE %d on CC_id %d (rnti %x, harq_pid %d, round %d, rb %d, cqi %d, mcs %d, rrc %d)\n", + module_idP, + frameP, + UE_id, + CC_id, + rnti, + harq_pid, + round_DL, + ue_sched_ctrl->pre_nb_available_rbs[CC_id], + ue_sched_ctrl->dl_cqi[CC_id], + eNB_UE_stats->dlsch_mcs1, + eNB_UE_stats->rrc_status); - /* if (continue_flag != 1 */ - if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0 || // no RBs allocated - CCE_allocation_infeasible(module_idP, - CC_id, - 1, - subframeP, - aggregation, - rnti)) { - LOG_D(MAC, "[eNB %d] Frame %d : no RB allocated for UE %d on CC_id %d: continue \n", + /* Process retransmission */ + if (round_DL != 8) { + // get freq_allocation + const int nb_rb = ue_template->nb_rb[harq_pid]; + int TBS = get_TBS_DL(ue_template->oldmcs1[harq_pid], nb_rb); + const uint32_t rbc = allocate_prbs_sub( + nb_rb, N_RB_DL, N_RBG, ue_sched_ctrl->rballoc_sub_UE[CC_id]); + + if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) { + LOG_D(MAC, + "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n", module_idP, frameP, + CC_id, + UE_id); + continue; + } + + /* CDRX */ + ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer + + if (ue_sched_ctrl->cdrx_configured) { + ue_sched_ctrl->drx_retransmission_timer[harq_pid] = 0; // stop drx retransmission + + /* + * Note: contrary to the spec drx_retransmission_timer[harq_pid] is reset not stop. + */ + if (harq_pid == 0) { + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_RETRANSMISSION_HARQ0, (unsigned long) ue_sched_ctrl->drx_retransmission_timer[0]); + } + } + + if (cc[CC_id].tdd_Config != NULL) { + ue_template->DAI++; + update_ul_dci(module_idP, + CC_id, + rnti, + ue_template->DAI, + subframeP); + LOG_D(MAC, "DAI update: CC_id %d subframeP %d: UE %d, DAI %d\n", + CC_id, + subframeP, UE_id, - CC_id); - continue_flag = 1; //to next user (there might be rbs availiable for other UEs in TM5 + ue_template->DAI); } - // If TDD - if (cc[CC_id].tdd_Config != NULL) { //TDD - set_ue_dai(subframeP, - UE_id, - CC_id, - cc[CC_id].tdd_Config->subframeAssignment, - UE_list); - // update UL DAI after DLSCH scheduling - set_ul_DAI(module_idP, - UE_id, - CC_id, - frameP, - subframeP); - } - - if (continue_flag == 1) { - add_ue_dlsch_info(module_idP, - CC_id, - UE_id, - subframeP, - S_DL_NONE, - rnti); - continue; - } - - nb_available_rb = ue_sched_ctrl->pre_nb_available_rbs[CC_id]; - harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, - frameP, - subframeP); - round_DL = ue_sched_ctrl->round[CC_id][harq_pid]; - eNB_UE_stats->crnti = rnti; - eNB_UE_stats->rrc_status = mac_eNB_get_rrc_status(module_idP, rnti); - eNB_UE_stats->harq_pid = harq_pid; - eNB_UE_stats->harq_round = round_DL; - - if (eNB_UE_stats->rrc_status < RRC_RECONFIGURED) { - ue_sched_ctrl->uplane_inactivity_timer = 0; - } - - if (eNB_UE_stats->rrc_status < RRC_CONNECTED) { - LOG_D(MAC, "UE %d is not in RRC_CONNECTED\n", UE_id); - continue; - } - - header_length_total = 0; - sdu_length_total = 0; - num_sdus = 0; - - /* - DevCheck(((eNB_UE_stats->dl_cqi < MIN_CQI_VALUE) || - (eNB_UE_stats->dl_cqi > MAX_CQI_VALUE)), - eNB_UE_stats->dl_cqi, MIN_CQI_VALUE, MAX_CQI_VALUE); - */ - if (NFAPI_MODE != NFAPI_MONOLITHIC) { - eNB_UE_stats->dlsch_mcs1 = cqi_to_mcs[ue_sched_ctrl->dl_cqi[CC_id]]; - } else { // this operation is also done in the preprocessor - eNB_UE_stats->dlsch_mcs1 = cmin(eNB_UE_stats->dlsch_mcs1, - eNB->slice_info.dl[slice_idxP].maxmcs); // cmin(eNB_UE_stats->dlsch_mcs1, openair_daq_vars.target_ue_dl_mcs); - } - - // Store stats - // eNB_UE_stats->dl_cqi= eNB_UE_stats->dl_cqi; - - // Initializing the rb allocation indicator for each UE - for (j = 0; j < N_RBG[CC_id]; j++) { - ue_template->rballoc_subband[harq_pid][j] = 0; - } - - LOG_D(MAC, "[eNB %d] Frame %d: Scheduling UE %d on CC_id %d (rnti %x, harq_pid %d, round %d, rb %d, cqi %d, mcs %d, rrc %d)\n", - module_idP, - frameP, - UE_id, - CC_id, - rnti, - harq_pid, - round_DL, - nb_available_rb, - ue_sched_ctrl->dl_cqi[CC_id], - eNB_UE_stats->dlsch_mcs1, - eNB_UE_stats->rrc_status); - - /* Process retransmission */ - if (round_DL != 8) { - // get freq_allocation - nb_rb = ue_template->nb_rb[harq_pid]; - TBS = get_TBS_DL(ue_template->oldmcs1[harq_pid], - nb_rb); - - if (nb_rb <= nb_available_rb) { - /* CDRX */ - ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer - - if (ue_sched_ctrl->cdrx_configured) { - ue_sched_ctrl->drx_retransmission_timer[harq_pid] = 0; // stop drx retransmission - - /* - * Note: contrary to the spec drx_retransmission_timer[harq_pid] is reset not stop. - */ - if (harq_pid == 0) { - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_RETRANSMISSION_HARQ0, (unsigned long) ue_sched_ctrl->drx_retransmission_timer[0]); - } - } - - if (cc[CC_id].tdd_Config != NULL) { - ue_template->DAI++; - update_ul_dci(module_idP, - CC_id, - rnti, - ue_template->DAI, - subframeP); - LOG_D(MAC, "DAI update: CC_id %d subframeP %d: UE %d, DAI %d\n", - CC_id, - subframeP, - UE_id, - ue_template->DAI); - } - - if (nb_rb == ue_sched_ctrl->pre_nb_available_rbs[CC_id]) { - for (j = 0; j < N_RBG[CC_id]; j++) { // for indicating the rballoc for each sub-band - ue_template->rballoc_subband[harq_pid][j] = ue_sched_ctrl->rballoc_sub_UE[CC_id][j]; - } - } else { - nb_rb_temp = nb_rb; - j = 0; - - while ((nb_rb_temp > 0) && (j < N_RBG[CC_id])) { - if (ue_sched_ctrl->rballoc_sub_UE[CC_id][j] == 1) { - if (ue_template->rballoc_subband[harq_pid][j]) - LOG_W(MAC, "WARN: rballoc_subband not free for retrans?\n"); - - ue_template->rballoc_subband[harq_pid][j] = ue_sched_ctrl->rballoc_sub_UE[CC_id][j]; - nb_rb_temp -= min_rb_unit[CC_id]; - - if ((j == N_RBG[CC_id] - 1) && (N_RB_DL[CC_id] == 25 || N_RB_DL[CC_id] == 50)) - nb_rb_temp++; - } - - j++; - } - } - - nb_available_rb -= nb_rb; - - switch (get_tmode(module_idP, CC_id, UE_id)) { - case 1: - case 2: - case 7: - default: - LOG_D(MAC, "retransmission DL_REQ: rnti:%x\n", - rnti); - dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void *) dl_config_pdu, - 0, - sizeof(nfapi_dl_config_request_pdu_t)); - dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; - dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = - get_aggregation(get_bw_index(module_idP, - CC_id), - ue_sched_ctrl->dl_cqi[CC_id], - format1); - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI: see Table 4-10 from SCF082 - nFAPI specifications - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = harq_pid; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = 1; // Don't adjust power when retransmitting - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = ue_template->oldNDI[harq_pid]; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = ue_template->oldmcs1[harq_pid]; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = round_DL & 3; - - // TDD - if (cc[CC_id].tdd_Config != NULL) { - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = (ue_template->DAI - 1) & 3; - LOG_D(MAC, "[eNB %d] Retransmission CC_id %d : harq_pid %d, round %d, dai %d, mcs %d\n", - module_idP, - CC_id, - harq_pid, - round_DL, - ue_template->DAI - 1, - ue_template->oldmcs1[harq_pid]); - } else { - LOG_D(MAC, "[eNB %d] Retransmission CC_id %d : harq_pid %d, round %d, mcs %d\n", - module_idP, - CC_id, - harq_pid, - round_DL, - ue_template->oldmcs1[harq_pid]); - } - - if (!CCE_allocation_infeasible(module_idP, - CC_id, - 1, - subframeP, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level, - rnti)) { - dl_req->number_dci++; - dl_req->number_pdu++; - dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; - eNB->DL_req[CC_id].sfn_sf = frameP<<4 | subframeP; - eNB->DL_req[CC_id].header.message_id = NFAPI_DL_CONFIG_REQUEST; - fill_nfapi_dlsch_config(eNB, - dl_req, - TBS, - -1, // retransmission, no pdu_index - rnti, - 0, // type 0 allocation from 7.1.6 in 36.213 - 0, // virtual_resource_block_assignment_flag, unused here - 0, // resource_block_coding, to be filled in later - getQm(ue_template->oldmcs1[harq_pid]), - round_DL & 3, // redundancy version - 1, // transport blocks - 0, // transport block to codeword swap flag - cc[CC_id].p_eNB == 1 ? 0 : 1, // transmission_scheme - 1, // number of layers - 1, // number of subbands - // uint8_t codebook_index, - 4, // UE category capacity - ue_template->physicalConfigDedicated->pdsch_ConfigDedicated->p_a, - 0, // delta_power_offset for TM5 - 0, // ngap - 0, // nprb - cc[CC_id].p_eNB == 1 ? 1 : 2, // transmission mode - 0, //number of PRBs treated as one subband, not used here - 0); // number of beamforming vectors, not used here - LOG_D(MAC, "Filled NFAPI configuration for DCI/DLSCH %d, retransmission round %d\n", - eNB->pdu_index[CC_id], - round_DL); - program_dlsch_acknak(module_idP, - CC_id, - UE_id, - frameP, - subframeP, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx); - // No TX request for retransmission (check if null request for FAPI) - } else { - LOG_W(MAC, "Frame %d, Subframe %d: Dropping DLSCH allocation for UE %d\%x, infeasible CCE allocation\n", - frameP, - subframeP, - UE_id, - rnti); - } - } - - add_ue_dlsch_info(module_idP, - CC_id, UE_id, - subframeP, - S_DL_SCHEDULED, - rnti); - //eNB_UE_stats->dlsch_trials[round]++; - eNB_UE_stats->num_retransmission += 1; - eNB_UE_stats->rbs_used_retx = nb_rb; - eNB_UE_stats->total_rbs_used_retx += nb_rb; - eNB_UE_stats->dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1; - } else { - LOG_D(MAC, - "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n", - module_idP, - frameP, - CC_id, - UE_id); - } - } else { - /* This is a potentially new SDU opportunity */ - rlc_status.bytes_in_buffer = 0; - // Now check RLC information to compute number of required RBs - // get maximum TBS size for RLC request - TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, - nb_available_rb); - - // add the length for all the control elements (timing adv, drx, etc) : header + payload - - if (ue_sched_ctrl->ta_timer == 0) { - ta_update = ue_sched_ctrl->ta_update; - - /* if we send TA then set timer to not send it for a while */ - if (ta_update != 31) { - ue_sched_ctrl->ta_timer = 20; - } - - /* reset ta_update */ - ue_sched_ctrl->ta_update = 31; - } else { - ta_update = 31; - } - - ta_len = (ta_update != 31) ? 2 : 0; - - // RLC data on DCCH - if (TBS - ta_len - header_length_total - sdu_length_total - 3 > 0) { - rlc_status = mac_rlc_status_ind(module_idP, - rnti, - module_idP, - frameP, - subframeP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - DCCH, - TBS - ta_len - header_length_total - sdu_length_total - 3, 0, 0 - ); - sdu_lengths[0] = 0; - - if (rlc_status.bytes_in_buffer > 0) { - LOG_D(MAC, "[eNB %d] SFN/SF %d.%d, DL-DCCH->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n", - module_idP, - frameP, - subframeP, - CC_id, - TBS - ta_len - header_length_total - sdu_length_total - 3); - sdu_lengths[0] = mac_rlc_data_req(module_idP, - rnti, - module_idP, - frameP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - DCCH, - TBS, //not used - (char *)&dlsch_buffer[0], 0, 0 - ); - - if((rrc_release_info.num_UEs > 0) && (rlc_am_mui.rrc_mui_num > 0)) { - while(pthread_mutex_trylock(&rrc_release_freelist)) { - /* spin... */ - } - - uint16_t release_total = 0; - - for (release_num = 0, release_ctrl = &rrc_release_info.RRC_release_ctrl[0]; - release_num < NUMBER_OF_UE_MAX; - release_num++, release_ctrl++) { - if(release_ctrl->flag > 0) { - release_total++; - } else { - continue; - } - - if(release_ctrl->flag == 1) { - if(release_ctrl->rnti == rnti) { - for(uint16_t mui_num = 0; mui_num < rlc_am_mui.rrc_mui_num; mui_num++) { - if(release_ctrl->rrc_eNB_mui == rlc_am_mui.rrc_mui[mui_num]) { - release_ctrl->flag = 3; - LOG_D(MAC,"DLSCH Release send:index %d rnti %x mui %d mui_num %d flag 1->3\n", - release_num, - rnti, - rlc_am_mui.rrc_mui[mui_num], - mui_num); - break; - } - } - } - } - - if(release_ctrl->flag == 2) { - if(release_ctrl->rnti == rnti) { - for (uint16_t mui_num = 0; mui_num < rlc_am_mui.rrc_mui_num; mui_num++) { - if(release_ctrl->rrc_eNB_mui == rlc_am_mui.rrc_mui[mui_num]) { - release_ctrl->flag = 4; - LOG_D(MAC, "DLSCH Release send:index %d rnti %x mui %d mui_num %d flag 2->4\n", - release_num, - rnti, - rlc_am_mui.rrc_mui[mui_num], - mui_num); - break; - } - } - } - } - - if(release_total >= rrc_release_info.num_UEs) - break; - } - - pthread_mutex_unlock(&rrc_release_freelist); - } - - for (ra_ii = 0, ra = &eNB->common_channels[CC_id].ra[0]; ra_ii < NB_RA_PROC_MAX; ra_ii++, ra++) { - if ((ra->rnti == rnti) && (ra->state == MSGCRNTI)) { - for (uint16_t mui_num = 0; mui_num < rlc_am_mui.rrc_mui_num; mui_num++) { - if (ra->crnti_rrc_mui == rlc_am_mui.rrc_mui[mui_num]) { - ra->crnti_harq_pid = harq_pid; - ra->state = MSGCRNTI_ACK; - break; - } - } - } - } - - T(T_ENB_MAC_UE_DL_SDU, - T_INT(module_idP), - T_INT(CC_id), - T_INT(rnti), - T_INT(frameP), - T_INT(subframeP), - T_INT(harq_pid), - T_INT(DCCH), - T_INT(sdu_lengths[0])); - LOG_D(MAC, "[eNB %d][DCCH] CC_id %d Got %d bytes from RLC\n", - module_idP, - CC_id, - sdu_lengths[0]); - sdu_length_total = sdu_lengths[0]; - sdu_lcids[0] = DCCH; - eNB_UE_stats->lcid_sdu[0] = DCCH; - eNB_UE_stats->sdu_length_tx[DCCH] = sdu_lengths[0]; - eNB_UE_stats->num_pdu_tx[DCCH] += 1; - eNB_UE_stats->num_bytes_tx[DCCH] += sdu_lengths[0]; - header_length_last = 1 + 1 + (sdu_lengths[0] >= 128); - header_length_total += header_length_last; - num_sdus = 1; -#ifdef DEBUG_eNB_SCHEDULER - LOG_T(MAC, "[eNB %d][DCCH] CC_id %d Got %d bytes :", - module_idP, - CC_id, - sdu_lengths[0]); - - for (j = 0; j < sdu_lengths[0]; ++j) { - LOG_T(MAC, "%x ", - dlsch_buffer[j]); - } - - LOG_T(MAC, "\n"); -#endif - } - } - - // RLC data on DCCH1 - if (TBS - ta_len - header_length_total - sdu_length_total - 3 > 0) { - rlc_status = mac_rlc_status_ind(module_idP, - rnti, - module_idP, - frameP, - subframeP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - DCCH + 1, - TBS - ta_len - header_length_total - sdu_length_total - 3, 0, 0 - ); - // DCCH SDU - sdu_lengths[num_sdus] = 0; - - if (rlc_status.bytes_in_buffer > 0) { - LOG_D(MAC, "[eNB %d], Frame %d, DCCH1->DLSCH, CC_id %d, Requesting %d bytes from RLC (RRC message)\n", - module_idP, frameP, CC_id, - TBS - ta_len - header_length_total - sdu_length_total - 3); - sdu_lengths[num_sdus] += mac_rlc_data_req(module_idP, - rnti, - module_idP, - frameP, - ENB_FLAG_YES, - MBMS_FLAG_NO, DCCH + 1, - TBS, //not used - (char *) &dlsch_buffer[sdu_length_total], 0, 0 - ); - T(T_ENB_MAC_UE_DL_SDU, - T_INT(module_idP), - T_INT(CC_id), - T_INT(rnti), - T_INT(frameP), - T_INT(subframeP), - T_INT(harq_pid), - T_INT(DCCH + 1), - T_INT(sdu_lengths[num_sdus])); - sdu_lcids[num_sdus] = DCCH1; - sdu_length_total += sdu_lengths[num_sdus]; - eNB_UE_stats->lcid_sdu[num_sdus] = DCCH1; - eNB_UE_stats->sdu_length_tx[DCCH1] = sdu_lengths[num_sdus]; - eNB_UE_stats->num_pdu_tx[DCCH1] += 1; - eNB_UE_stats->num_bytes_tx[DCCH1] += sdu_lengths[num_sdus]; - header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128); - header_length_total += header_length_last; - num_sdus++; -#ifdef DEBUG_eNB_SCHEDULER - LOG_T(MAC, "[eNB %d][DCCH1] CC_id %d Got %d bytes :", - module_idP, - CC_id, - sdu_lengths[num_sdus]); - - for (j = 0; j < sdu_lengths[num_sdus]; ++j) { - LOG_T(MAC, "%x ", - dlsch_buffer[j]); - } - - LOG_T(MAC, "\n"); -#endif - } - } - - // TODO: lcid has to be sorted before the actual allocation (similar struct as ue_list). - for (lcid = NB_RB_MAX - 1; lcid >= DTCH; lcid--) { - // TODO: check if the lcid is active - LOG_D(MAC, "[eNB %d], Frame %d, DTCH%d->DLSCH, Checking RLC status (tbs %d, len %d)\n", - module_idP, - frameP, - lcid, - TBS, - TBS - ta_len - header_length_total - sdu_length_total - 3); - - if (TBS - ta_len - header_length_total - sdu_length_total - 3 > 0) { - rlc_status = mac_rlc_status_ind(module_idP, - rnti, - module_idP, - frameP, - subframeP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - lcid, - TBS - ta_len - header_length_total - sdu_length_total - 3, 0, 0 - ); - - if (rlc_status.bytes_in_buffer > 0) { - LOG_D(MAC, "[eNB %d][USER-PLANE DEFAULT DRB] Frame %d : DTCH->DLSCH, Requesting %d bytes from RLC (lcid %d total hdr len %d)\n", - module_idP, - frameP, - TBS - ta_len - header_length_total - sdu_length_total - 3, - lcid, - header_length_total); - sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, - rnti, - module_idP, - frameP, - ENB_FLAG_YES, - MBMS_FLAG_NO, - lcid, - TBS, //not used - (char *) &dlsch_buffer[sdu_length_total], 0, 0 - ); - T(T_ENB_MAC_UE_DL_SDU, - T_INT(module_idP), - T_INT(CC_id), - T_INT(rnti), - T_INT(frameP), - T_INT(subframeP), - T_INT(harq_pid), - T_INT(lcid), - T_INT(sdu_lengths[num_sdus])); - LOG_D(MAC, "[eNB %d][USER-PLANE DEFAULT DRB] Got %d bytes for DTCH %d \n", - module_idP, - sdu_lengths[num_sdus], - lcid); - sdu_lcids[num_sdus] = lcid; - sdu_length_total += sdu_lengths[num_sdus]; - eNB_UE_stats->num_pdu_tx[lcid]++; - eNB_UE_stats->lcid_sdu[num_sdus] = lcid; - eNB_UE_stats->sdu_length_tx[lcid] = sdu_lengths[num_sdus]; - eNB_UE_stats->num_bytes_tx[lcid] += sdu_lengths[num_sdus]; - header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128); - header_length_total += header_length_last; - num_sdus++; - ue_sched_ctrl->uplane_inactivity_timer = 0; - // reset RRC inactivity timer after uplane activity - ue_contextP = rrc_eNB_get_ue_context(RC.rrc[module_idP], rnti); - - if (ue_contextP != NULL) { - ue_contextP->ue_context.ue_rrc_inactivity_timer = 1; - } else { - LOG_E(MAC, "[eNB %d] CC_id %d Couldn't find the context associated to UE (RNTI %d) and reset RRC inactivity timer\n", - module_idP, - CC_id, - rnti); - } - } // end if (rlc_status.bytes_in_buffer > 0) - } else { // no TBS left - break; // break for (lcid = NB_RB_MAX - 1; lcid >= DTCH; lcid--) - } - } - - /* Last header does not have length field */ - if (header_length_total) { - header_length_total -= header_length_last; - header_length_total++; - } - - // there is at least one SDU or TA command - // if (num_sdus > 0 ){ - if (ta_len + sdu_length_total + header_length_total > 0) { - // Now compute number of required RBs for total sdu length - // Assume RAH format 2 - mcs = eNB_UE_stats->dlsch_mcs1; - - if (mcs == 0) { - nb_rb = 4; // don't let the TBS get too small - } else { - nb_rb = min_rb_unit[CC_id]; - } - - TBS = get_TBS_DL(mcs, nb_rb); - - while (TBS < sdu_length_total + header_length_total + ta_len) { - nb_rb += min_rb_unit[CC_id]; // - - if (nb_rb > nb_available_rb) { // if we've gone beyond the maximum number of RBs - // (can happen if N_RB_DL is odd) - TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, - nb_available_rb); - nb_rb = nb_available_rb; - break; - } - - TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, - nb_rb); - } - - if (nb_rb == ue_sched_ctrl->pre_nb_available_rbs[CC_id]) { - for (j = 0; j < N_RBG[CC_id]; ++j) { // for indicating the rballoc for each sub-band - ue_template->rballoc_subband[harq_pid][j] = ue_sched_ctrl->rballoc_sub_UE[CC_id][j]; - } - } else { - nb_rb_temp = nb_rb; - j = 0; - - while ((nb_rb_temp > 0) && (j < N_RBG[CC_id])) { - if (ue_sched_ctrl->rballoc_sub_UE[CC_id][j] == 1) { - ue_template->rballoc_subband[harq_pid][j] = ue_sched_ctrl->rballoc_sub_UE[CC_id][j]; - - if ((j == N_RBG[CC_id] - 1) && ((N_RB_DL[CC_id] == 25) || (N_RB_DL[CC_id] == 50))) { - nb_rb_temp = nb_rb_temp - min_rb_unit[CC_id] + 1; - } else { - nb_rb_temp = nb_rb_temp - min_rb_unit[CC_id]; - } - } - - j++; - } - } - - // decrease mcs until TBS falls below required length - while ((TBS > sdu_length_total + header_length_total + ta_len) && (mcs > 0)) { - mcs--; - TBS = get_TBS_DL(mcs, - nb_rb); - } - - // if we have decreased too much or we don't have enough RBs, increase MCS - while (TBS < sdu_length_total + header_length_total + ta_len && - ((ue_sched_ctrl->dl_pow_off[CC_id] > 0 && mcs < 28) || (ue_sched_ctrl->dl_pow_off[CC_id] == 0 && mcs <= 15))) { - mcs++; - TBS = get_TBS_DL(mcs, - nb_rb); - } - - LOG_D(MAC, "dlsch_mcs before and after the rate matching = (%d, %d)\n", - eNB_UE_stats->dlsch_mcs1, - mcs); -#ifdef DEBUG_eNB_SCHEDULER - LOG_D(MAC, "[eNB %d] CC_id %d Generated DLSCH header (mcs %d, TBS %d, nb_rb %d)\n", - module_idP, - CC_id, - mcs, TBS, - nb_rb); - // msg("[MAC][eNB ] Reminder of DLSCH with random data %d %d %d %d \n", - // TBS, sdu_length_total, offset, TBS-sdu_length_total-offset); -#endif - - if (TBS - header_length_total - sdu_length_total - ta_len <= 2) { - padding = TBS - header_length_total - sdu_length_total - ta_len; - post_padding = 0; - } else { - padding = 0; - post_padding = 1; - } - - offset = generate_dlsch_header((unsigned char *) UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], - num_sdus, //num_sdus - sdu_lengths, // - sdu_lcids, - 255, // no drx - ta_update, // timing advance - NULL, // contention res id - padding, - post_padding); - - //#ifdef DEBUG_eNB_SCHEDULER - if (ta_update != 31) { - LOG_D(MAC, - "[eNB %d][DLSCH] Frame %d Generate header for UE_id %d on CC_id %d: sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,timing advance value : %d, padding %d,post_padding %d,(mcs %d, TBS %d, nb_rb %d),header_length %d\n", - module_idP, - frameP, - UE_id, - CC_id, - sdu_length_total, - num_sdus, - sdu_lengths[0], - sdu_lcids[0], - offset, - ta_update, - padding, - post_padding, - mcs, - TBS, - nb_rb, - header_length_total); - } - - //#endif -#ifdef DEBUG_eNB_SCHEDULER - LOG_T(MAC, "[eNB %d] First 16 bytes of DLSCH : \n"); - - for (i = 0; i < 16; i++) { - LOG_T(MAC, "%x.", - dlsch_buffer[i]); - } - - LOG_T(MAC, "\n"); -#endif - // cycle through SDUs and place in dlsch_buffer - dlsch_pdu = &UE_list->DLSCH_pdu[CC_id][0][UE_id]; - memcpy(&dlsch_pdu->payload[0][offset], - dlsch_buffer, - sdu_length_total); - // memcpy(RC.mac[0].DLSCH_pdu[0][0].payload[0][offset],dcch_buffer,sdu_lengths[0]); - - // fill remainder of DLSCH with 0 - for (j = 0; j < (TBS - sdu_length_total - offset); j++) { - dlsch_pdu->payload[0][offset + sdu_length_total + j] = 0; - } - - trace_pdu(DIRECTION_DOWNLINK, - (uint8_t *) dlsch_pdu->payload[0], - TBS, - module_idP, - WS_C_RNTI, - UE_RNTI(module_idP, - UE_id), - eNB->frame, - eNB->subframe, - 0, - 0); - T(T_ENB_MAC_UE_DL_PDU_WITH_DATA, - T_INT(module_idP), - T_INT(CC_id), - T_INT(rnti), - T_INT(frameP), - T_INT(subframeP), - T_INT(harq_pid), - T_BUFFER(dlsch_pdu->payload[0], - TBS)); - ue_template->nb_rb[harq_pid] = nb_rb; - add_ue_dlsch_info(module_idP, - CC_id, - UE_id, - subframeP, - S_DL_SCHEDULED, - rnti); - // store stats - eNB->eNB_stats[CC_id].dlsch_bytes_tx += sdu_length_total; - eNB->eNB_stats[CC_id].dlsch_pdus_tx += 1; - eNB_UE_stats->rbs_used = nb_rb; - eNB_UE_stats->num_mac_sdu_tx = num_sdus; - eNB_UE_stats->total_rbs_used += nb_rb; - eNB_UE_stats->dlsch_mcs2 = mcs; - eNB_UE_stats->TBS = TBS; - eNB_UE_stats->overhead_bytes = TBS - sdu_length_total; - eNB_UE_stats->total_sdu_bytes += sdu_length_total; - eNB_UE_stats->total_pdu_bytes += TBS; - eNB_UE_stats->total_num_pdus += 1; - - if (cc[CC_id].tdd_Config != NULL) { // TDD - ue_template->DAI++; - update_ul_dci(module_idP, - CC_id, - rnti, - ue_template->DAI, - subframeP); - } - - // do PUCCH power control - // this is the snr - // unit is not dBm, it's special from nfapi - // converting to dBm - snr = (5 * ue_sched_ctrl->pucch1_snr[CC_id] - 640) / 10; - target_snr = eNB->puCch10xSnr / 10; - // this assumes accumulated tpc - // make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out - int32_t framex10psubframe = ue_template->pucch_tpc_tx_frame * 10 + ue_template->pucch_tpc_tx_subframe; - - if (framex10psubframe + 10 <= (frameP * 10) + subframeP || //normal case - (framex10psubframe > (frameP * 10) + subframeP && 10240 - framex10psubframe + (frameP * 10) + subframeP >= 10)) //frame wrap-around - if (ue_sched_ctrl->pucch1_cqi_update[CC_id] == 1) { - ue_sched_ctrl->pucch1_cqi_update[CC_id] = 0; - ue_template->pucch_tpc_tx_frame = frameP; - ue_template->pucch_tpc_tx_subframe = subframeP; - - if (snr > target_snr + 4) { - tpc = 0; //-1 - } else if (snr < target_snr - 4) { - tpc = 2; //+1 - } else { - tpc = 1; //0 - } - - LOG_D(MAC, "[eNB %d] DLSCH scheduler: frame %d, subframe %d, harq_pid %d, tpc %d, snr/target snr %d/%d (normal case)\n", - module_idP, - frameP, - subframeP, - harq_pid, - tpc, - snr, - target_snr); - } // Po_PUCCH has been updated - else { - tpc = 1; //0 - } // time to do TPC update - else { - tpc = 1; //0 - } - - dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void *) dl_config_pdu, - 0, - sizeof(nfapi_dl_config_request_pdu_t)); - dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; + nfapi_dl_config_request_pdu_t *dl_config_pdu = &dl_req->dl_config_pdu_list[dci_dl_pdu_idx]; + switch (get_tmode(module_idP, CC_id, UE_id)) { + case 1: + case 2: + case 7: + default: + LOG_D(MAC, "retransmission DL_REQ: rnti:%x\n", + rnti); dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = - get_aggregation(get_bw_index(module_idP, - CC_id), - ue_sched_ctrl->dl_cqi[CC_id], - format1); - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI: see Table 4-10 from SCF082 - nFAPI specifications + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = harq_pid; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = tpc; // dont adjust power when retransmitting - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = 1 - ue_template->oldNDI[harq_pid]; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = mcs; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = 0; - //deactivate second codeword - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_2 = 0; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_2 = 1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = 1; // Don't adjust power when retransmitting + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = ue_template->oldNDI[harq_pid]; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = ue_template->oldmcs1[harq_pid]; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = round_DL & 3; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = rbc; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_allocation_type = 0; - if (cc[CC_id].tdd_Config != NULL) { //TDD + // TDD + if (cc[CC_id].tdd_Config != NULL) { dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = (ue_template->DAI - 1) & 3; - LOG_D(MAC, "[eNB %d] Initial transmission CC_id %d : harq_pid %d, dai %d, mcs %d\n", + LOG_D(MAC, "[eNB %d] Retransmission CC_id %d : harq_pid %d, round %d, dai %d, mcs %d\n", module_idP, CC_id, harq_pid, - (ue_template->DAI - 1), - mcs); + round_DL, + ue_template->DAI - 1, + ue_template->oldmcs1[harq_pid]); } else { - LOG_D(MAC, "[eNB %d] Initial transmission CC_id %d : harq_pid %d, mcs %d\n", + LOG_D(MAC, "[eNB %d] Retransmission CC_id %d : harq_pid %d, round %d, mcs %d\n", module_idP, CC_id, harq_pid, - mcs); + round_DL, + ue_template->oldmcs1[harq_pid]); } - LOG_D(MAC, "Checking feasibility pdu %d (new sdu)\n", - dl_req->number_pdu); + dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + eNB->DL_req[CC_id].sfn_sf = frameP<<4 | subframeP; + eNB->DL_req[CC_id].header.message_id = NFAPI_DL_CONFIG_REQUEST; + fill_nfapi_dlsch_config(&dl_req->dl_config_pdu_list[dci_dl_pdu_idx + 1], + TBS, + -1, // retransmission, no pdu_index + rnti, + 0, // type 0 allocation from 7.1.6 in 36.213 + 0, // virtual_resource_block_assignment_flag, unused here + rbc, // resource_block_coding + getQm(ue_template->oldmcs1[harq_pid]), + round_DL & 3, // redundancy version + 1, // transport blocks + 0, // transport block to codeword swap flag + cc[CC_id].p_eNB == 1 ? 0 : 1, // transmission_scheme + 1, // number of layers + 1, // number of subbands + // uint8_t codebook_index, + 4, // UE category capacity + ue_template->physicalConfigDedicated->pdsch_ConfigDedicated->p_a, + 0, // delta_power_offset for TM5 + 0, // ngap + 0, // nprb + cc[CC_id].p_eNB == 1 ? 1 : 2, // transmission mode + 0, //number of PRBs treated as one subband, not used here + 0); // number of beamforming vectors, not used here + LOG_D(MAC, "Filled NFAPI configuration for DCI/DLSCH %d, retransmission round %d\n", + eNB->pdu_index[CC_id], + round_DL); + program_dlsch_acknak(module_idP, + CC_id, + UE_id, + frameP, + subframeP, + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx); + // No TX request for retransmission (check if null request for FAPI) + } - if (!CCE_allocation_infeasible(module_idP, - CC_id, - 1, - subframeP, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level, - rnti)) { - ue_sched_ctrl->round[CC_id][harq_pid] = 0; - dl_req->number_dci++; - dl_req->number_pdu++; - dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; - eNB->DL_req[CC_id].sfn_sf = frameP << 4 | subframeP; - eNB->DL_req[CC_id].header.message_id = NFAPI_DL_CONFIG_REQUEST; - /* CDRX */ - ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer + //eNB_UE_stats->dlsch_trials[round]++; + eNB_UE_stats->num_retransmission += 1; + eNB_UE_stats->rbs_used_retx = nb_rb; + eNB_UE_stats->total_rbs_used_retx += nb_rb; + eNB_UE_stats->dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1; + } else { + // Now check RLC information to compute number of required RBs + // get maximum TBS size for RLC request + const int nb_rb = ue_sched_ctrl->pre_nb_available_rbs[CC_id]; + int TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, nb_rb); + const uint32_t rbc = allocate_prbs_sub(nb_rb, N_RB_DL, N_RBG, ue_sched_ctrl->rballoc_sub_UE[CC_id]); - if (ue_sched_ctrl->cdrx_configured) { - ue_sched_ctrl->drx_inactivity_timer = 1; // restart drx inactivity timer when new transmission - ue_sched_ctrl->drx_retransmission_timer[harq_pid] = 0; // stop drx retransmission - /* - * Note: contrary to the spec drx_retransmission_timer[harq_pid] is reset not stop. - */ - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_INACTIVITY, (unsigned long) ue_sched_ctrl->drx_inactivity_timer); + // add the length for all the control elements (timing adv, drx, etc) : header + payload - if (harq_pid == 0) { - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_RETRANSMISSION_HARQ0, (unsigned long) ue_sched_ctrl->drx_retransmission_timer[0]); - } - } + if (ue_sched_ctrl->ta_timer) + ue_sched_ctrl->ta_timer--; - // Toggle NDI for next time - LOG_D(MAC, "CC_id %d Frame %d, subframeP %d: Toggling Format1 NDI for UE %d (rnti %x/%d) oldNDI %d\n", - CC_id, - frameP, - subframeP, - UE_id, - rnti, - harq_pid, - ue_template->oldNDI[harq_pid]); - ue_template->oldNDI[harq_pid] = 1 - ue_template->oldNDI[harq_pid]; - ue_template->oldmcs1[harq_pid] = mcs; - ue_template->oldmcs2[harq_pid] = 0; - AssertFatal(ue_template->physicalConfigDedicated != NULL, "physicalConfigDedicated is NULL\n"); - AssertFatal(ue_template->physicalConfigDedicated->pdsch_ConfigDedicated != NULL, - "physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n"); - fill_nfapi_dlsch_config(eNB, - dl_req, - TBS, - eNB->pdu_index[CC_id], - rnti, - 0, // type 0 allocation from 7.1.6 in 36.213 - 0, // virtual_resource_block_assignment_flag, unused here - 0, // resource_block_coding, to be filled in later - getQm(mcs), - 0, // redundancy version - 1, // transport blocks - 0, // transport block to codeword swap flag - cc[CC_id].p_eNB == 1 ? 0 : 1, // transmission_scheme - 1, // number of layers - 1, // number of subbands - // uint8_t codebook_index, - 4, // UE category capacity - ue_template->physicalConfigDedicated->pdsch_ConfigDedicated->p_a, - 0, // delta_power_offset for TM5 - 0, // ngap - 0, // nprb - cc[CC_id].p_eNB == 1 ? 1 : 2, // transmission mode - 0, //number of PRBs treated as one subband, not used here - 0); // number of beamforming vectors, not used here - eNB->TX_req[CC_id].sfn_sf = fill_nfapi_tx_req(&eNB->TX_req[CC_id].tx_request_body, - (frameP * 10) + subframeP, - TBS, - eNB->pdu_index[CC_id], - dlsch_pdu->payload[0]); - LOG_D(MAC, "Filled NFAPI configuration for DCI/DLSCH/TXREQ %d, new SDU\n", - eNB->pdu_index[CC_id]); - eNB->pdu_index[CC_id]++; - program_dlsch_acknak(module_idP, - CC_id, - UE_id, - frameP, - subframeP, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx); - } else { - LOG_W(MAC, "Frame %d, Subframe %d: Dropping DLSCH allocation for UE %d/%x, infeasible CCE allocations\n", - frameP, - subframeP, - UE_id, - rnti); - } - } else { // There is no data from RLC or MAC header, so don't schedule + int ta_update = 31; + if (ue_sched_ctrl->ta_timer == 0) { + ta_update = ue_sched_ctrl->ta_update; + + /* if we send TA then set timer to not send it for a while */ + if (ta_update != 31) { + ue_sched_ctrl->ta_timer = 20; + } + + /* reset ta_update */ + ue_sched_ctrl->ta_update = 31; + } + + int ta_len = (ta_update != 31) ? 2 : 0; + + + int num_sdus = 0; + uint16_t sdu_lengths[NB_RB_MAX]; + int sdu_length_total = 0; + int header_length_total = 0; + int header_length_last = 0; + unsigned char sdu_lcids[NB_RB_MAX]; + for (int i = 0; i < ue_sched_ctrl->dl_lc_num; ++i) { + const int lcid = ue_sched_ctrl->dl_lc_ids[i]; // will match DCCH, DCCH1, DTCH + + if (TBS - ta_len - header_length_total - sdu_length_total - 3 <= 0) + break; + + if (ue_sched_ctrl->dl_lc_bytes[i] == 0) // no data in this LC! + continue; + + LOG_D(MAC, "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n", + module_idP, + frameP, + subframeP, + lcid, + CC_id, + TBS - ta_len - header_length_total - sdu_length_total - 3); + + sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, + rnti, + module_idP, + frameP, + ENB_FLAG_YES, + MBMS_FLAG_NO, + lcid, + TBS - ta_len - header_length_total - sdu_length_total - 3, + (char *)&dlsch_buffer[sdu_length_total], + 0, + 0 + ); + +#ifdef DEBUG_eNB_SCHEDULER + LOG_T(MAC, "[eNB %d][%d] CC_id %d Got %d bytes :", + module_idP, + lcid, + CC_id, + sdu_lengths[num_sdus]); + for (int j = 0; j < sdu_lengths[num_sdus]; ++j) + LOG_T(MAC, "%x ", dlsch_buffer[sdu_length_total + j]); + LOG_T(MAC, "\n"); +#endif + + T(T_ENB_MAC_UE_DL_SDU, + T_INT(module_idP), + T_INT(CC_id), + T_INT(rnti), + T_INT(frameP), + T_INT(subframeP), + T_INT(harq_pid), + T_INT(lcid), + T_INT(sdu_lengths[num_sdus])); + LOG_D(MAC, "[eNB %d][LC %d] CC_id %d Got %d bytes from RLC\n", + module_idP, + lcid, + CC_id, + sdu_lengths[num_sdus]); + sdu_lcids[num_sdus] = lcid; + sdu_length_total += sdu_lengths[num_sdus]; + eNB_UE_stats->num_pdu_tx[lcid] += 1; + eNB_UE_stats->lcid_sdu[num_sdus] = lcid; + eNB_UE_stats->sdu_length_tx[lcid] = sdu_lengths[num_sdus]; + eNB_UE_stats->num_bytes_tx[lcid] += sdu_lengths[num_sdus]; + header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128); + header_length_total += header_length_last; + num_sdus += 1; + + if (lcid >= 3) { // if this is DTCH + ue_sched_ctrl->uplane_inactivity_timer = 0; + + // reset RRC inactivity timer after uplane activity + rrc_eNB_ue_context_t *ue_contextP = rrc_eNB_get_ue_context(RC.rrc[module_idP], rnti); + if (ue_contextP == NULL) + LOG_E(MAC, "[eNB %d] CC_id %d Couldn't find the context associated to UE (RNTI %d) and reset RRC inactivity timer\n", + module_idP, + CC_id, + rnti); + ue_contextP->ue_context.ue_rrc_inactivity_timer = 1; } } - if (cc[CC_id].tdd_Config != NULL) { // TDD - set_ul_DAI(module_idP, - UE_id, - CC_id, - frameP, - subframeP); + /* Last header does not have length field */ + if (header_length_total) { + header_length_total -= header_length_last; + header_length_total++; } - } // UE_id loop - } // CC_id loop - fill_DLSCH_dci(module_idP, - frameP, - subframeP, - mbsfn_flag); + // there is at least one SDU or TA command + if (ta_len + sdu_length_total + header_length_total > 0) { + // Now compute number of required RBs for total sdu length + // Assume RAH format 2 + int mcs = eNB_UE_stats->dlsch_mcs1; + + /* TODO make special function */ + // decrease mcs until TBS falls below required length + while ((TBS > sdu_length_total + header_length_total + ta_len) && (mcs > 0)) { + mcs--; + TBS = get_TBS_DL(mcs, nb_rb); + } + + // if we have decreased too much or we don't have enough RBs, increase MCS + while (TBS < sdu_length_total + header_length_total + ta_len && mcs < 28) { + // the second part of this condition is useless since dl_pow_off is + // always 2? + //&& ((ue_sched_ctrl->dl_pow_off[CC_id] > 0 && mcs < 28) || (ue_sched_ctrl->dl_pow_off[CC_id] == 0 && mcs <= 15))) { + mcs++; + TBS = get_TBS_DL(mcs, + nb_rb); + } + + LOG_D(MAC, "dlsch_mcs before and after the rate matching = (%d, %d), TBS %d, nb_rb %d\n", + eNB_UE_stats->dlsch_mcs1, mcs, TBS, nb_rb); + + int post_padding = TBS - header_length_total - sdu_length_total - ta_len > 2; + int padding = post_padding ? 0 : TBS - header_length_total - sdu_length_total - ta_len; + + const int offset = generate_dlsch_header((unsigned char *) UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], + num_sdus, //num_sdus + sdu_lengths, // + sdu_lcids, + 255, // no drx + ta_update, // timing advance + NULL, // contention res id + padding, + post_padding); + + //#ifdef DEBUG_eNB_SCHEDULER + if (ta_update != 31) { + LOG_D(MAC, + "[eNB %d][DLSCH] Frame %d Generate header for UE_id %d on CC_id %d: sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,timing advance value : %d, padding %d,post_padding %d,(mcs %d, TBS %d, nb_rb %d),header_length %d\n", + module_idP, + frameP, + UE_id, + CC_id, + sdu_length_total, + num_sdus, + sdu_lengths[0], + sdu_lcids[0], + offset, + ta_update, + padding, + post_padding, + mcs, + TBS, + nb_rb, + header_length_total); + } + + //#endif +#ifdef DEBUG_eNB_SCHEDULER + LOG_T(MAC, "[eNB %d] First 16 bytes of DLSCH : \n"); + + for (int i = 0; i < 16; i++) { + LOG_T(MAC, "%x.", + dlsch_buffer[i]); + } + + LOG_T(MAC, "\n"); +#endif + // cycle through SDUs and place in dlsch_buffer + DLSCH_PDU *dlsch_pdu = &UE_info->DLSCH_pdu[CC_id][0][UE_id]; + memcpy(&dlsch_pdu->payload[0][offset], dlsch_buffer, sdu_length_total); + + // fill remainder of DLSCH with 0 + for (int j = 0; j < TBS - sdu_length_total - offset; j++) { + dlsch_pdu->payload[0][offset + sdu_length_total + j] = 0; + } + + trace_pdu(DIRECTION_DOWNLINK, + (uint8_t *) dlsch_pdu->payload[0], + TBS, + module_idP, + WS_C_RNTI, + UE_RNTI(module_idP, + UE_id), + eNB->frame, + eNB->subframe, + 0, + 0); + T(T_ENB_MAC_UE_DL_PDU_WITH_DATA, + T_INT(module_idP), + T_INT(CC_id), + T_INT(rnti), + T_INT(frameP), + T_INT(subframeP), + T_INT(harq_pid), + T_BUFFER(dlsch_pdu->payload[0], + TBS)); + ue_template->nb_rb[harq_pid] = nb_rb; + // store stats + eNB->eNB_stats[CC_id].dlsch_bytes_tx += sdu_length_total; + eNB->eNB_stats[CC_id].dlsch_pdus_tx += 1; + eNB_UE_stats->rbs_used = nb_rb; + eNB_UE_stats->num_mac_sdu_tx = num_sdus; + eNB_UE_stats->total_rbs_used += nb_rb; + eNB_UE_stats->dlsch_mcs2 = mcs; + eNB_UE_stats->TBS = TBS; + eNB_UE_stats->overhead_bytes = TBS - sdu_length_total; + eNB_UE_stats->total_sdu_bytes += sdu_length_total; + eNB_UE_stats->total_pdu_bytes += TBS; + eNB_UE_stats->total_num_pdus += 1; + + if (cc[CC_id].tdd_Config != NULL) { // TDD + ue_template->DAI++; + update_ul_dci(module_idP, + CC_id, + rnti, + ue_template->DAI, + subframeP); + } + + // do PUCCH power control + // this is the snr + // unit is not dBm, it's special from nfapi + // converting to dBm + int snr = (5 * ue_sched_ctrl->pucch1_snr[CC_id] - 640) / 10; + int target_snr = eNB->puCch10xSnr / 10; + // this assumes accumulated tpc + // make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out + int32_t framex10psubframe = ue_template->pucch_tpc_tx_frame * 10 + ue_template->pucch_tpc_tx_subframe; + + int tpc = 1; + if (framex10psubframe + 10 <= (frameP * 10) + subframeP || //normal case + (framex10psubframe > (frameP * 10) + subframeP && 10240 - framex10psubframe + (frameP * 10) + subframeP >= 10)) { //frame wrap-around + if (ue_sched_ctrl->pucch1_cqi_update[CC_id] == 1) { + ue_sched_ctrl->pucch1_cqi_update[CC_id] = 0; + ue_template->pucch_tpc_tx_frame = frameP; + ue_template->pucch_tpc_tx_subframe = subframeP; + + if (snr > target_snr + 4) { + tpc = 0; //-1 + } else if (snr < target_snr - 4) { + tpc = 2; //+1 + } else { + tpc = 1; //0 + } + + LOG_D(MAC, "[eNB %d] DLSCH scheduler: frame %d, subframe %d, harq_pid %d, tpc %d, snr/target snr %d/%d (normal case)\n", + module_idP, + frameP, + subframeP, + harq_pid, + tpc, + snr, + target_snr); + } // Po_PUCCH has been updated + } + + nfapi_dl_config_request_pdu_t *dl_config_pdu = &dl_req->dl_config_pdu_list[dci_dl_pdu_idx]; + dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = harq_pid; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = tpc; // dont adjust power when retransmitting + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = 1 - ue_template->oldNDI[harq_pid]; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = mcs; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = 0; + //deactivate second codeword + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_2 = 0; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_2 = 1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = rbc; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_allocation_type = 0; + + if (cc[CC_id].tdd_Config != NULL) { //TDD + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = (ue_template->DAI - 1) & 3; + LOG_D(MAC, "[eNB %d] Initial transmission CC_id %d : harq_pid %d, dai %d, mcs %d\n", + module_idP, + CC_id, + harq_pid, + (ue_template->DAI - 1), + mcs); + } else { + LOG_D(MAC, "[eNB %d] Initial transmission CC_id %d : harq_pid %d, mcs %d\n", + module_idP, + CC_id, + harq_pid, + mcs); + } + + LOG_D(MAC, "Checking feasibility pdu %d (new sdu)\n", + dl_req->number_pdu); + + ue_sched_ctrl->round[CC_id][harq_pid] = 0; + dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + eNB->DL_req[CC_id].sfn_sf = frameP << 4 | subframeP; + eNB->DL_req[CC_id].header.message_id = NFAPI_DL_CONFIG_REQUEST; + /* CDRX */ + ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer + + if (ue_sched_ctrl->cdrx_configured) { + ue_sched_ctrl->drx_inactivity_timer = 1; // restart drx inactivity timer when new transmission + ue_sched_ctrl->drx_retransmission_timer[harq_pid] = 0; // stop drx retransmission + /* + * Note: contrary to the spec drx_retransmission_timer[harq_pid] is reset not stop. + */ + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_INACTIVITY, (unsigned long) ue_sched_ctrl->drx_inactivity_timer); + + if (harq_pid == 0) { + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_RETRANSMISSION_HARQ0, (unsigned long) ue_sched_ctrl->drx_retransmission_timer[0]); + } + } + + // Toggle NDI for next time + LOG_D(MAC, "CC_id %d Frame %d, subframeP %d: Toggling Format1 NDI for UE %d (rnti %x/%d) oldNDI %d\n", + CC_id, + frameP, + subframeP, + UE_id, + rnti, + harq_pid, + ue_template->oldNDI[harq_pid]); + ue_template->oldNDI[harq_pid] = 1 - ue_template->oldNDI[harq_pid]; + ue_template->oldmcs1[harq_pid] = mcs; + ue_template->oldmcs2[harq_pid] = 0; + AssertFatal(ue_template->physicalConfigDedicated != NULL, "physicalConfigDedicated is NULL\n"); + AssertFatal(ue_template->physicalConfigDedicated->pdsch_ConfigDedicated != NULL, + "physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n"); + fill_nfapi_dlsch_config(&dl_req->dl_config_pdu_list[dci_dl_pdu_idx + 1], + TBS, + eNB->pdu_index[CC_id], + rnti, + 0, // type 0 allocation from 7.1.6 in 36.213 + 0, // virtual_resource_block_assignment_flag, unused here + rbc,// resource_block_coding + getQm(mcs), + 0, // redundancy version + 1, // transport blocks + 0, // transport block to codeword swap flag + cc[CC_id].p_eNB == 1 ? 0 : 1, // transmission_scheme + 1, // number of layers + 1, // number of subbands + // uint8_t codebook_index, + 4, // UE category capacity + ue_template->physicalConfigDedicated->pdsch_ConfigDedicated->p_a, + 0, // delta_power_offset for TM5 + 0, // ngap + 0, // nprb + cc[CC_id].p_eNB == 1 ? 1 : 2, // transmission mode + 0, //number of PRBs treated as one subband, not used here + 0); // number of beamforming vectors, not used here + eNB->TX_req[CC_id].sfn_sf = fill_nfapi_tx_req(&eNB->TX_req[CC_id].tx_request_body, + (frameP * 10) + subframeP, + TBS, + eNB->pdu_index[CC_id], + dlsch_pdu->payload[0]); + LOG_D(MAC, "Filled NFAPI configuration for DCI/DLSCH/TXREQ %d, new SDU\n", + eNB->pdu_index[CC_id]); + eNB->pdu_index[CC_id]++; + program_dlsch_acknak(module_idP, + CC_id, + UE_id, + frameP, + subframeP, + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx); + } + } + } // UE_id loop stop_meas(&eNB->schedule_dlsch); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_SCHEDULE_DLSCH, VCD_FUNCTION_OUT); } -//------------------------------------------------------------------------------ -void -dlsch_scheduler_interslice_multiplexing(module_id_t Mod_id, - int frameP, - sub_frame_t subframeP, - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]) -//------------------------------------------------------------------------------ -{ - // FIXME: I'm prototyping the algorithm, so there may be arrays and variables that carry redundant information here and in pre_processor_results struct. - int UE_id, CC_id, rbg, i; - int N_RB_DL, min_rb_unit, tm; - int owned, used; - eNB_MAC_INST *eNB = RC.mac[Mod_id]; - int nb_mac_CC = RC.nb_mac_CC[Mod_id]; - UE_list_t *UE_list = &eNB->UE_list; - slice_info_t *sli = &eNB->slice_info; - UE_sched_ctrl_t *ue_sched_ctl; - COMMON_channels_t *cc; - int N_RBG[NFAPI_CC_MAX]; - int slice_sorted_list[MAX_NUM_SLICES]; - int slice_idx; - int8_t free_rbgs_map[NFAPI_CC_MAX][N_RBG_MAX]; - int has_traffic[NFAPI_CC_MAX][MAX_NUM_SLICES]; - uint8_t allocation_mask[NFAPI_CC_MAX][N_RBG_MAX]; - uint16_t (*nb_rbs_remaining)[MAX_MOBILES_PER_ENB]; - uint16_t (*nb_rbs_required)[MAX_MOBILES_PER_ENB]; - uint8_t (*MIMO_mode_indicator)[N_RBG_MAX]; - - // Initialize the free RBGs map - // free_rbgs_map[CC_id][rbg] = -1 if RBG is allocated, - // otherwise it contains the id of the slice it belongs to. - // (Information about slicing must be retained to deal with isolation). - // FIXME: This method does not consider RBGs that are free and belong to no slices - for (CC_id = 0; CC_id < nb_mac_CC; CC_id++) { - cc = &eNB->common_channels[CC_id]; - N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth); - - for (rbg = 0; rbg < N_RBG[CC_id]; rbg++) { - for (i = 0; i < sli->n_dl; ++i) { - owned = sli->pre_processor_results[i].slice_allocation_mask[CC_id][rbg]; - - if (owned) { - used = rballoc_sub[CC_id][rbg]; - free_rbgs_map[CC_id][rbg] = used ? -1 : i; - break; - } - } - } - } - - // Find out which slices need other resources. - // FIXME: I don't think is really needed since we check nb_rbs_remaining later - for (CC_id = 0; CC_id < nb_mac_CC; CC_id++) { - for (i = 0; i < sli->n_dl; i++) { - has_traffic[CC_id][i] = 0; - - for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (sli->pre_processor_results[i].nb_rbs_remaining[CC_id][UE_id] > 0) { - has_traffic[CC_id][i] = 1; - break; - } - } - } - } - - slice_priority_sort(Mod_id, - slice_sorted_list); - - // MULTIPLEXING - // This part is an adaptation of dlsch_scheduler_pre_processor_allocate() code - for (CC_id = 0; CC_id < nb_mac_CC; ++CC_id) { - N_RB_DL = to_prb(eNB->common_channels[CC_id].mib->message.dl_Bandwidth); - min_rb_unit = get_min_rb_unit(Mod_id, - CC_id); - - for (i = 0; i < sli->n_dl; ++i) { - slice_idx = slice_sorted_list[i]; - - if (has_traffic[CC_id][slice_idx] == 0) continue; - - // Build an ad-hoc allocation mask fo the slice - for (rbg = 0; rbg < N_RBG[CC_id]; ++rbg) { - if (free_rbgs_map[CC_id][rbg] == -1) { - // RBG is already allocated - allocation_mask[CC_id][rbg] = 0; - continue; - } - - if (sli->dl[free_rbgs_map[CC_id][rbg]].isol == 1) { - // RBG belongs to an isolated slice - allocation_mask[CC_id][rbg] = 0; - continue; - } - - // RBG is free - allocation_mask[CC_id][rbg] = 1; - } - - // Sort UE again - // (UE list gets sorted every time pre_processor is called so it is probably dirty at this point) - // FIXME: There is only one UE_list for all slices, so it must be sorted again each time we use it - sort_UEs(Mod_id, - slice_idx, - frameP, - subframeP); - nb_rbs_remaining = sli->pre_processor_results[slice_idx].nb_rbs_remaining; - nb_rbs_required = sli->pre_processor_results[slice_idx].nb_rbs_required; - MIMO_mode_indicator = sli->pre_processor_results[slice_idx].MIMO_mode_indicator; - - // Allocation - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - tm = get_tmode(Mod_id, - CC_id, - UE_id); - - for (rbg = 0; rbg < N_RBG[CC_id]; ++rbg) { - // FIXME: I think that some of these checks are redundant - if (allocation_mask[CC_id][rbg] == 0) continue; - - if (rballoc_sub[CC_id][rbg] != 0) continue; - - if (ue_sched_ctl->rballoc_sub_UE[CC_id][rbg] != 0) continue; - - if (nb_rbs_remaining[CC_id][UE_id] <= 0) continue; - - if (ue_sched_ctl->pre_nb_available_rbs[CC_id] >= nb_rbs_required[CC_id][UE_id]) continue; - - if (ue_sched_ctl->dl_pow_off[CC_id] == 0) continue; - - if ((rbg == N_RBG[CC_id] - 1) && ((N_RB_DL == 25) || (N_RB_DL == 50))) { - // Allocating last, smaller RBG - if (nb_rbs_remaining[CC_id][UE_id] >= min_rb_unit - 1) { - rballoc_sub[CC_id][rbg] = 1; - free_rbgs_map[CC_id][rbg] = -1; - ue_sched_ctl->rballoc_sub_UE[CC_id][rbg] = 1; - MIMO_mode_indicator[CC_id][rbg] = 1; - - if (tm == 5) { - ue_sched_ctl->dl_pow_off[CC_id] = 1; - } - - nb_rbs_remaining[CC_id][UE_id] -= (min_rb_unit - 1); - ue_sched_ctl->pre_nb_available_rbs[CC_id] += (min_rb_unit - 1); - } - } else { - // Allocating a standard-sized RBG - if (nb_rbs_remaining[CC_id][UE_id] >= min_rb_unit) { - rballoc_sub[CC_id][rbg] = 1; - free_rbgs_map[CC_id][rbg] = -1; - ue_sched_ctl->rballoc_sub_UE[CC_id][rbg] = 1; - MIMO_mode_indicator[CC_id][rbg] = 1; - - if (tm == 5) { - ue_sched_ctl->dl_pow_off[CC_id] = 1; - } - - nb_rbs_remaining[CC_id][UE_id] -= min_rb_unit; - ue_sched_ctl->pre_nb_available_rbs[CC_id] += min_rb_unit; - } - } - } - } - } - } - - return; -} - -//------------------------------------------------------------------------------ -void dlsch_scheduler_qos_multiplexing(module_id_t Mod_id, int frameP, sub_frame_t subframeP) -//------------------------------------------------------------------------------ -{ - // int UE_id; - int CC_id, i; - // UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - slice_info_t *sli = &RC.mac[Mod_id]->slice_info; - //UE_sched_ctrl *ue_sched_ctl; - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - for (i = 0; i < sli->n_dl; i++) { - // Sort UE again - // FIXME: There is only one UE_list for all slices, so it must be sorted again each time we use it - sort_UEs(Mod_id, - (uint8_t)i, - frameP, - subframeP); - /* - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - //ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - // TODO: Do something here - // ue_sched_ctl->pre_nb_available_rbs[CC_id]; - } - */ - } - } -} - //------------------------------------------------------------------------------ /* * Default DLSCH scheduler for LTE-M @@ -1886,7 +1234,7 @@ schedule_ue_spec_br(module_id_t module_idP, unsigned char dlsch_buffer[MAX_DLSCH_PAYLOAD_BYTES]; eNB_MAC_INST *mac = RC.mac[module_idP]; COMMON_channels_t *cc = mac->common_channels; - UE_list_t *UE_list = &mac->UE_list; + UE_info_t *UE_info = &mac->UE_info; UE_TEMPLATE *UE_template = NULL; UE_sched_ctrl_t *ue_sched_ctl = NULL; nfapi_dl_config_request_pdu_t *dl_config_pdu = NULL; @@ -1951,7 +1299,7 @@ schedule_ue_spec_br(module_id_t module_idP, } } - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + for (UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { int harq_pid = 0; rnti = UE_RNTI(module_idP, UE_id); @@ -1959,8 +1307,8 @@ schedule_ue_spec_br(module_id_t module_idP, continue; } - ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); - UE_template = &(UE_list->UE_template[CC_id][UE_id]); + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; + UE_template = &UE_info->UE_template[CC_id][UE_id]; if (UE_template->rach_resource_type == 0) { continue; @@ -2031,7 +1379,6 @@ schedule_ue_spec_br(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH, - (TBS-ta_len-header_len_dcch), 0, 0); // transport block set size sdu_lengths[0] = 0; @@ -2049,7 +1396,7 @@ schedule_ue_spec_br(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH, - TBS, //not used + TBS-ta_len-header_len_dcch, (char *)&dlsch_buffer[0], 0, 0); @@ -2068,8 +1415,8 @@ schedule_ue_spec_br(module_id_t module_idP, sdu_lengths[0]); sdu_length_total = sdu_lengths[0]; sdu_lcids[0] = DCCH; - UE_list->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[DCCH]+=1; - UE_list->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH]+=sdu_lengths[0]; + UE_info->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[DCCH]+=1; + UE_info->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH]+=sdu_lengths[0]; num_sdus = 1; } else { header_len_dcch = 0; @@ -2087,7 +1434,6 @@ schedule_ue_spec_br(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH + 1, - (TBS-ta_len-header_len_dcch-sdu_length_total), 0, 0); // transport block set size less allocations for timing advance and DCCH SDU sdu_lengths[num_sdus] = 0; @@ -2105,7 +1451,7 @@ schedule_ue_spec_br(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH+1, - TBS, //not used + TBS-ta_len-header_len_dcch-sdu_length_total, (char *)&dlsch_buffer[sdu_length_total], 0, 0); @@ -2121,8 +1467,8 @@ schedule_ue_spec_br(module_id_t module_idP, sdu_lcids[num_sdus] = DCCH1; sdu_length_total += sdu_lengths[num_sdus]; header_len_dcch += 2; - UE_list->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[DCCH1] += 1; - UE_list->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH1] += sdu_lengths[num_sdus]; + UE_info->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[DCCH1] += 1; + UE_info->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH1] += sdu_lengths[num_sdus]; num_sdus++; } } @@ -2152,7 +1498,6 @@ schedule_ue_spec_br(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS - ta_len - header_len_dcch - sdu_length_total - header_len_dtch, 0, 0); @@ -2183,7 +1528,7 @@ schedule_ue_spec_br(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS, //not used + TBS - ta_len - header_len_dcch - sdu_length_total - header_len_dtch, (char *) &dlsch_buffer[sdu_length_total], 0, 0); @@ -2274,7 +1619,7 @@ schedule_ue_spec_br(module_id_t module_idP, post_padding = TBS - sdu_length_total - header_len_dcch - header_len_dtch - ta_len; // 1 is for the postpadding header } - offset = generate_dlsch_header((unsigned char *)UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], + offset = generate_dlsch_header((unsigned char *)UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], num_sdus, //num_sdus sdu_lengths, // sdu_lcids, @@ -2307,15 +1652,15 @@ schedule_ue_spec_br(module_id_t module_idP, } /* Cycle through SDUs and place in dlsch_buffer */ - memcpy(&UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset], dlsch_buffer, sdu_length_total); + memcpy(&UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset], dlsch_buffer, sdu_length_total); /* Fill remainder of DLSCH with random data */ for (j = 0; j < (TBS - sdu_length_total - offset); j++) { - UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset + sdu_length_total + j] = (char)(taus()&0xff); + UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset + sdu_length_total + j] = (char)(taus()&0xff); } trace_pdu(DIRECTION_DOWNLINK, - (uint8_t *)UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], + (uint8_t *)UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], TBS, module_idP, 3, @@ -2331,7 +1676,7 @@ schedule_ue_spec_br(module_id_t module_idP, T_INT(frameP), T_INT(subframeP), T_INT(harq_pid), - T_BUFFER(UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], TBS)); + T_BUFFER(UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], TBS)); /* Do PUCCH power control */ /* This is the snr */ /* unit is not dBm, it's special from nfapi, convert to dBm */ @@ -2339,15 +1684,15 @@ schedule_ue_spec_br(module_id_t module_idP, target_snr = mac->puCch10xSnr / 10; /* This assumes accumulated tpc */ /* Make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out */ - int32_t framex10psubframe = UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_frame * 10 + UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe; + int32_t framex10psubframe = UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_frame * 10 + UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe; if (((framex10psubframe + 10) <= (frameP * 10 + subframeP)) || // normal case ((framex10psubframe > (frameP * 10 + subframeP)) && (((10240 - framex10psubframe +frameP * 10 + subframeP) >= 10)))) { // frame wrap-around if (ue_sched_ctl->pucch1_cqi_update[CC_id] == 1) { ue_sched_ctl->pucch1_cqi_update[CC_id] = 0; - UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_frame = frameP; - UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe = subframeP; + UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_frame = frameP; + UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe = subframeP; if (snr > target_snr + 4) { tpc = 0; //-1 @@ -2481,7 +1826,7 @@ schedule_ue_spec_br(module_id_t module_idP, TX_req->pdu_index = mac->pdu_index[CC_id]++; TX_req->num_segments = 1; TX_req->segments[0].segment_length = TX_req->pdu_length; - TX_req->segments[0].segment_data = mac->UE_list.DLSCH_pdu[CC_id][0][(unsigned char) UE_id].payload[0]; + TX_req->segments[0].segment_data = mac->UE_info.DLSCH_pdu[CC_id][0][(unsigned char) UE_id].payload[0]; mac->TX_req[CC_id].tx_request_body.number_of_pdus++; ackNAK_absSF = absSF + 4; ul_req = &mac->UL_req_tmp[CC_id][ackNAK_absSF % 10].ul_config_request_body; @@ -2515,9 +1860,9 @@ schedule_ue_spec_br(module_id_t module_idP, T_INT (frameP), T_INT (subframeP), T_INT (0 /* harq_pid always 0? */ ), - T_BUFFER (&mac->UE_list.DLSCH_pdu[CC_id][0][UE_id].payload[0], TX_req->pdu_length)); + T_BUFFER (&mac->UE_info.DLSCH_pdu[CC_id][0][UE_id].payload[0], TX_req->pdu_length)); trace_pdu(1, - (uint8_t *) mac->UE_list.DLSCH_pdu[CC_id][0][(unsigned char) UE_id].payload[0], + (uint8_t *) mac->UE_info.DLSCH_pdu[CC_id][0][(unsigned char) UE_id].payload[0], TX_req->pdu_length, UE_id, 3, @@ -2530,101 +1875,6 @@ schedule_ue_spec_br(module_id_t module_idP, } // end loop on UE_id } -//------------------------------------------------------------------------------ -void -fill_DLSCH_dci(module_id_t module_idP, - frame_t frameP, - sub_frame_t subframeP, - int *mbsfn_flagP) -//------------------------------------------------------------------------------ -{ - // loop over all allocated UEs and compute frequency allocations for PDSCH - int UE_id = -1; - uint8_t /* first_rb, */ nb_rb = 3; - rnti_t rnti; - //unsigned char *vrb_map; - uint8_t rballoc_sub[25]; - //uint8_t number_of_subbands=13; - //unsigned char round; - unsigned char harq_pid; - int i; - int CC_id; - eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list = &eNB->UE_list; - int N_RBG; - int N_RB_DL; - COMMON_channels_t *cc; - eNB_DLSCH_INFO *dlsch_info; - UE_TEMPLATE *ue_template; - start_meas(&eNB->fill_DLSCH_dci); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_FILL_DLSCH_DCI, - VCD_FUNCTION_IN); - - for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) { - LOG_D(MAC, "Doing fill DCI for CC_id %d\n", - CC_id); - - if (mbsfn_flagP[CC_id] > 0) - continue; - - cc = &eNB->common_channels[CC_id]; - N_RBG = to_rbg(cc->mib->message.dl_Bandwidth); - N_RB_DL = to_prb(cc->mib->message.dl_Bandwidth); - - // UE specific DCIs - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - dlsch_info = &eNB_dlsch_info[module_idP][CC_id][UE_id]; - LOG_T(MAC, "CC_id %d, UE_id: %d => status %d\n", - CC_id, - UE_id, - dlsch_info->status); - - if (dlsch_info->status == S_DL_SCHEDULED) { - // clear scheduling flag - dlsch_info->status = S_DL_WAITING; - rnti = UE_RNTI(module_idP, UE_id); - harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP, - subframeP); - ue_template = &UE_list->UE_template[CC_id][UE_id]; - nb_rb = ue_template->nb_rb[harq_pid]; - - /// Synchronizing rballoc with rballoc_sub - for (i = 0; i < N_RBG; i++) { - rballoc_sub[i] = ue_template->rballoc_subband[harq_pid][i]; - } - - nfapi_dl_config_request_body_t *dl_config_request_body = &RC.mac[module_idP]->DL_req[CC_id].dl_config_request_body; - nfapi_dl_config_request_pdu_t *dl_config_pdu; - - for (i = 0; i < dl_config_request_body->number_pdu; i++) { - dl_config_pdu = &dl_config_request_body->dl_config_pdu_list[i]; - - if (dl_config_pdu->pdu_type == NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE && - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti == rnti && - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format != 1) { - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = allocate_prbs_sub(nb_rb, - N_RB_DL, - N_RBG, - rballoc_sub); - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_allocation_type = 0; - } else if (dl_config_pdu->pdu_type == NFAPI_DL_CONFIG_DLSCH_PDU_TYPE && - dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti == rnti && - dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_allocation_type == 0) { - dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_block_coding = allocate_prbs_sub(nb_rb, - N_RB_DL, - N_RBG, - rballoc_sub); - } - } - } - } - } - - stop_meas(&eNB->fill_DLSCH_dci); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_FILL_DLSCH_DCI, - VCD_FUNCTION_OUT); -} - //------------------------------------------------------------------------------ unsigned char *get_dlsch_sdu(module_id_t module_idP, int CC_id, @@ -2661,7 +1911,7 @@ unsigned char *get_dlsch_sdu(module_id_t module_idP, CC_id, rntiP, UE_id); - return ((unsigned char *) &eNB->UE_list.DLSCH_pdu[CC_id][TBindex][UE_id].payload[0]); + return ((unsigned char *) &eNB->UE_info.DLSCH_pdu[CC_id][TBindex][UE_id].payload[0]); } LOG_E(MAC, "[eNB %d] Frame %d: CC_id %d UE with RNTI %x does not exist\n", @@ -2706,61 +1956,61 @@ set_ue_dai(sub_frame_t subframeP, int UE_id, uint8_t CC_id, uint8_t tdd_config, - UE_list_t *UE_list) + UE_info_t *UE_info) //------------------------------------------------------------------------------ { switch (tdd_config) { case 0: if (subframeP == 0 || subframeP == 1 || subframeP == 3 || subframeP == 5 || subframeP == 6 || subframeP == 8) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; case 1: if (subframeP == 0 || subframeP == 4 || subframeP == 5 || subframeP == 9) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; case 2: if (subframeP == 4 || subframeP == 5) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; case 3: if (subframeP == 5 || subframeP == 7 || subframeP == 9) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; case 4: if (subframeP == 0 || subframeP == 6) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; case 5: if (subframeP == 9) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; case 6: if (subframeP == 0 || subframeP == 1 || subframeP == 5 || subframeP == 6 || subframeP == 9) { - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; } break; default: - UE_list->UE_template[CC_id][UE_id].DAI = 0; + UE_info->UE_template[CC_id][UE_id].DAI = 0; LOG_I(MAC, "unknown TDD config %d\n", tdd_config); break; @@ -3158,37 +2408,3 @@ schedule_PCH(module_id_t module_idP, stop_meas(&eNB->schedule_pch); return; } - -static int -slice_priority_compare(const void *_a, - const void *_b, - void *_c) { - const int slice_id1 = *(const int *) _a; - const int slice_id2 = *(const int *) _b; - const module_id_t Mod_id = *(int *) _c; - const slice_info_t *sli = &RC.mac[Mod_id]->slice_info; - - if (sli->dl[slice_id1].prio > sli->dl[slice_id2].prio) { - return -1; - } - - return 1; -} - -void -slice_priority_sort(module_id_t Mod_id, - int slice_list[MAX_NUM_SLICES]) { - int i; - int n_dl = RC.mac[Mod_id]->slice_info.n_dl; - - for (i = 0; i < n_dl; i++) { - slice_list[i] = i; - } - - qsort_r(slice_list, - n_dl, - sizeof(int), - slice_priority_compare, - &Mod_id); - return; -} diff --git a/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c b/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c index 260d8a7417..00fd40109d 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c @@ -120,7 +120,7 @@ void pre_scd_nb_rbs_required( module_id_t module_idP, if(N_RB_DL==100) step_size=4; memset(nb_rbs_required, 0, sizeof(uint16_t)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); - UE_list_t *UE_list = &RC.mac[module_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[module_idP]->UE_info; for (UE_id = 0; UE_id dlsch_mcs1 = cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; + eNB_UE_stats->dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; if (UE_template.dl_buffer_total > 0) { nb_rbs_required[CC_id][UE_id] = search_rbs_required(eNB_UE_stats->dlsch_mcs1, UE_template.dl_buffer_total, N_RB_DL, step_size); @@ -175,7 +175,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( DLSCH_UE_SELECT dlsch_ue_select[MAX_NUM_CCs]) { eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = eNB->common_channels; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; UE_sched_ctrl_t *ue_sched_ctl; uint8_t CC_id; int UE_id; @@ -208,7 +208,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( DL_req = &eNB->DL_req[CC_id].dl_config_request_body; for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) { - if (UE_list->active[UE_id] == FALSE) { + if (UE_info->active[UE_id] == FALSE) { continue; } @@ -222,12 +222,12 @@ void dlsch_scheduler_pre_ue_select_fairRR( continue; } - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; harq_pid = frame_subframe2_dl_harq_pid(cc[CC_id].tdd_Config,frameP,subframeP); round = ue_sched_ctl->round[CC_id][harq_pid]; if (round != 8) { // retransmission - if(UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid] == 0) { + if(UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid] == 0) { continue; } @@ -266,7 +266,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0)?2:1; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; DL_req->number_pdu++; - nb_rbs_required[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + nb_rbs_required[CC_id][UE_id] = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; // Insert DLSCH(retransmission) UE into selected UE list dlsch_ue_select[CC_id].list[dlsch_ue_select[CC_id].ue_num].UE_id = UE_id; dlsch_ue_select[CC_id].list[dlsch_ue_select[CC_id].ue_num].ue_priority = SCH_DL_RETRANS; @@ -284,7 +284,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( UE_id, CC_id, cc[CC_id].tdd_Config->subframeAssignment, - UE_list); + UE_info); // update UL DAI after DLSCH scheduling set_ul_DAI(module_idP,UE_id,CC_id,frameP,subframeP); } @@ -324,7 +324,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( break; } - if (UE_list->active[UE_id] == FALSE) { + if (UE_info->active[UE_id] == FALSE) { continue; } @@ -337,7 +337,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( continue; } - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; for(i = 0; isubframeAssignment, - UE_list); + UE_info); // update UL DAI after DLSCH scheduling set_ul_DAI(module_idP,UE_id,CC_id,frameP,subframeP); } @@ -448,7 +448,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( break; } - if (UE_list->active[UE_id] == FALSE) { + if (UE_info->active[UE_id] == FALSE) { continue; } @@ -461,7 +461,7 @@ void dlsch_scheduler_pre_ue_select_fairRR( continue; } - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; for(i = 0; isubframeAssignment, - UE_list); + UE_info); // update UL DAI after DLSCH scheduling set_ul_DAI(module_idP,UE_id,CC_id,frameP,subframeP); } @@ -558,7 +558,331 @@ void dlsch_scheduler_pre_ue_select_fairRR( return; } +void dlsch_scheduler_pre_processor_reset_fairRR( + module_id_t module_idP, + frame_t frameP, + sub_frame_t subframeP, + int min_rb_unit[NFAPI_CC_MAX], + uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], + uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], + uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]) { + int UE_id; + uint8_t CC_id; + int i, j; + UE_info_t *UE_info; + UE_sched_ctrl_t *ue_sched_ctl; + int N_RB_DL, RBGsize, RBGsize_last; + int N_RBG[NFAPI_CC_MAX]; + rnti_t rnti; + uint8_t *vrb_map; + COMMON_channels_t *cc; + // + for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) { + // initialize harq_pid and round + cc = &RC.mac[module_idP]->common_channels[CC_id]; + N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth); + min_rb_unit[CC_id] = get_min_rb_unit(module_idP, CC_id); + + for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; ++UE_id) { + UE_info = &RC.mac[module_idP]->UE_info; + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; + rnti = UE_RNTI(module_idP, UE_id); + + if (rnti == NOT_A_RNTI) + continue; + + if (UE_info->active[UE_id] != TRUE) + continue; + + LOG_D(MAC, "Running preprocessor for UE %d (%x)\n", UE_id, rnti); + + // initialize harq_pid and round + if (ue_sched_ctl->ta_timer) + ue_sched_ctl->ta_timer--; + + /* + eNB_UE_stats *eNB_UE_stats; + + if (eNB_UE_stats == NULL) + return; + + + mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti, + frameP,subframeP, + &ue_sched_ctl->harq_pid[CC_id], + &ue_sched_ctl->round[CC_id], + openair_harq_DL); + + + if (ue_sched_ctl->ta_timer == 0) { + + // WE SHOULD PROTECT the eNB_UE_stats with a mutex here ... + + ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY + switch (N_RB_DL) { + case 6: + ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update; + break; + + case 15: + ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2; + break; + + case 25: + ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4; + break; + + case 50: + ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8; + break; + + case 75: + ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12; + break; + + case 100: + ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16; + break; + } + // clear the update in case PHY does not have a new measurement after timer expiry + eNB_UE_stats->timing_advance_update = 0; + } + else { + ue_sched_ctl->ta_timer--; + ue_sched_ctl->ta_update =0; // don't trigger a timing advance command + } + + + if (UE_id==0) { + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update); + } + */ + nb_rbs_required[CC_id][UE_id] = 0; + ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0; + ue_sched_ctl->dl_pow_off[CC_id] = 2; + + for (i = 0; i < N_RBG[CC_id]; i++) { + ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0; + } + } + + N_RB_DL = to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth); + + switch (N_RB_DL) { + case 6: + RBGsize = 1; + RBGsize_last = 1; + break; + + case 15: + RBGsize = 2; + RBGsize_last = 1; + break; + + case 25: + RBGsize = 2; + RBGsize_last = 1; + break; + + case 50: + RBGsize = 3; + RBGsize_last = 2; + break; + + case 75: + RBGsize = 4; + RBGsize_last = 3; + break; + + case 100: + RBGsize = 4; + RBGsize_last = 4; + break; + + default: + AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL); + } + + vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map; + + // Initialize Subbands according to VRB map + for (i = 0; i < N_RBG[CC_id]; i++) { + int rb_size = i == N_RBG[CC_id] - 1 ? RBGsize_last : RBGsize; + + // for SI-RNTI,RA-RNTI and P-RNTI allocations + for (j = 0; j < rb_size; j++) { + if (vrb_map[j + (i*RBGsize)] != 0) { + rballoc_sub[CC_id][i] = 1; + LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n", frameP, subframeP, j + (i*RBGsize)); + break; + } + } + + //LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n", + //frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]); + MIMO_mode_indicator[CC_id][i] = 2; + } + } +} + +// This function returns the estimated number of RBs required by each UE for downlink scheduling +void assign_rbs_required_fairRR( + module_id_t Mod_id, + frame_t frameP, + sub_frame_t subframe, + uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]) { + uint16_t TBS = 0; + int UE_id, n, i, j, CC_id, pCCid, tmp; + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + eNB_UE_STATS *eNB_UE_stats, *eNB_UE_stats_i, *eNB_UE_stats_j; + int N_RB_DL; + + // clear rb allocations across all CC_id + for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { + if (UE_info->active[UE_id] != TRUE) + continue; + + pCCid = UE_PCCID(Mod_id, UE_id); + + // update CQI information across component carriers + for (n = 0; n < UE_info->numactiveCCs[UE_id]; n++) { + CC_id = UE_info->ordered_CCids[n][UE_id]; + eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + eNB_UE_stats->dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; + } + + // provide the list of CCs sorted according to MCS + for (i = 0; i < UE_info->numactiveCCs[UE_id]; ++i) { + eNB_UE_stats_i = + &UE_info->eNB_UE_stats[UE_info->ordered_CCids[i][UE_id]][UE_id]; + + for (j = i + 1; j < UE_info->numactiveCCs[UE_id]; j++) { + DevAssert(j < NFAPI_CC_MAX); + eNB_UE_stats_j = + &UE_info->eNB_UE_stats[UE_info->ordered_CCids[j][UE_id]][UE_id]; + + if (eNB_UE_stats_j->dlsch_mcs1 > eNB_UE_stats_i->dlsch_mcs1) { + tmp = UE_info->ordered_CCids[i][UE_id]; + UE_info->ordered_CCids[i][UE_id] = UE_info->ordered_CCids[j][UE_id]; + UE_info->ordered_CCids[j][UE_id] = tmp; + } + } + } + + if (UE_info->UE_template[pCCid][UE_id].dl_buffer_total > 0) { + LOG_D(MAC, "[preprocessor] assign RB for UE %d\n", UE_id); + + for (i = 0; i < UE_info->numactiveCCs[UE_id]; i++) { + CC_id = UE_info->ordered_CCids[i][UE_id]; + eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + const int min_rb_unit = get_min_rb_unit(Mod_id, CC_id); + + if (eNB_UE_stats->dlsch_mcs1 == 0) { + nb_rbs_required[CC_id][UE_id] = 4; // don't let the TBS get too small + } else { + nb_rbs_required[CC_id][UE_id] = min_rb_unit; + } + + TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, nb_rbs_required[CC_id][UE_id]); + LOG_D(MAC, + "[preprocessor] start RB assignement for UE %d CC_id %d dl " + "buffer %d (RB unit %d, MCS %d, TBS %d) \n", + UE_id, + CC_id, + UE_info->UE_template[pCCid][UE_id].dl_buffer_total, + nb_rbs_required[CC_id][UE_id], + eNB_UE_stats->dlsch_mcs1, + TBS); + N_RB_DL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + + /* calculating required number of RBs for each UE */ + while (TBS < UE_info->UE_template[pCCid][UE_id].dl_buffer_total) { + nb_rbs_required[CC_id][UE_id] += min_rb_unit; + + if (nb_rbs_required[CC_id][UE_id] > N_RB_DL) { + TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, N_RB_DL); + nb_rbs_required[CC_id][UE_id] = N_RB_DL; + break; + } + + TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, + nb_rbs_required[CC_id][UE_id]); + } // end of while + + LOG_D(MAC, + "[eNB %d] Frame %d: UE %d on CC %d: RB unit %d, nb_required RB " + "%d (TBS %d, mcs %d)\n", + Mod_id, + frameP, + UE_id, + CC_id, + min_rb_unit, + nb_rbs_required[CC_id][UE_id], + TBS, + eNB_UE_stats->dlsch_mcs1); + } + } + } +} + +void dlsch_scheduler_pre_processor_allocate_fairRR( + module_id_t Mod_id, + int UE_id, + uint8_t CC_id, + int N_RBG, + uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], + uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], + uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]) { + int i; + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + UE_sched_ctrl_t *ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; + int N_RB_DL = + to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int min_rb_unit = get_min_rb_unit(Mod_id, CC_id); + + for (i = 0; i < N_RBG; i++) { + if (rballoc_sub[CC_id][i] != 0) + continue; + + if (ue_sched_ctl->rballoc_sub_UE[CC_id][i] != 0) + continue; + + if (nb_rbs_remaining[CC_id][UE_id] <= 0) + continue; + + if (ue_sched_ctl->pre_nb_available_rbs[CC_id] + >= nb_rbs_required[CC_id][UE_id]) + continue; + + if (ue_sched_ctl->dl_pow_off[CC_id] == 0) + continue; + + if ((i == N_RBG - 1) && ((N_RB_DL == 25) || (N_RB_DL == 50))) { + // Allocating last, smaller RBG + if (nb_rbs_remaining[CC_id][UE_id] >= min_rb_unit - 1) { + rballoc_sub[CC_id][i] = 1; + ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 1; + + nb_rbs_remaining[CC_id][UE_id] = + nb_rbs_remaining[CC_id][UE_id] - min_rb_unit + 1; + ue_sched_ctl->pre_nb_available_rbs[CC_id] = + ue_sched_ctl->pre_nb_available_rbs[CC_id] + min_rb_unit - 1; + } + } else { + // Allocating a standard-sized RBG + if (nb_rbs_remaining[CC_id][UE_id] >= min_rb_unit) { + rballoc_sub[CC_id][i] = 1; + ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 1; + + nb_rbs_remaining[CC_id][UE_id] = + nb_rbs_remaining[CC_id][UE_id] - min_rb_unit; + ue_sched_ctl->pre_nb_available_rbs[CC_id] = + ue_sched_ctl->pre_nb_available_rbs[CC_id] + min_rb_unit; + } + } + } +} // This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, @@ -570,9 +894,8 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, uint16_t temp_total_rbs_count; unsigned char temp_total_ue_count; unsigned char MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]; - uint8_t slice_allocation[MAX_NUM_CCs][N_RBG_MAX]; int UE_id, i; - uint16_t j,c; + uint16_t j; uint16_t nb_rbs_required[MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; uint16_t nb_rbs_required_remaining[MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; @@ -581,7 +904,7 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, int min_rb_unit[MAX_NUM_CCs]; // uint16_t r1=0; uint8_t CC_id; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; int N_RB_DL; UE_sched_ctrl_t *ue_sched_ctl; // int rrc_status = RRC_IDLE; @@ -607,29 +930,27 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, min_rb_unit[CC_id] = get_min_rb_unit(Mod_id, CC_id); for (i = 0; i < NUMBER_OF_UE_MAX; i++) { - if (UE_list->active[i] != TRUE) + if (UE_info->active[i] != TRUE) continue; UE_id = i; // Initialize scheduling information for all active UEs - dlsch_scheduler_pre_processor_reset(Mod_id, - 0, - frameP, - subframeP, - min_rb_unit, - (uint16_t (*)[MAX_MOBILES_PER_ENB])nb_rbs_required, - rballoc_sub, - MIMO_mode_indicator, - mbsfn_flag); + dlsch_scheduler_pre_processor_reset_fairRR( + Mod_id, + frameP, + subframeP, + min_rb_unit, + (uint16_t(*)[MAX_MOBILES_PER_ENB])nb_rbs_required, + rballoc_sub, + MIMO_mode_indicator); } } #if (!defined(PRE_SCD_THREAD)) - // Store the DLSCH buffer for each logical channel - store_dlsch_buffer(Mod_id,0, frameP, subframeP); + // Store the DLSCH buffer for each logical channel and for PCCID (assume 0) + store_dlsch_buffer(Mod_id, 0, frameP, subframeP); // Calculate the number of RBs required by each UE on the basis of logical channel's buffer - assign_rbs_required(Mod_id, 0, frameP, subframeP, nb_rbs_required, - min_rb_unit); + assign_rbs_required_fairRR(Mod_id, frameP, subframeP, nb_rbs_required); #else memcpy(nb_rbs_required, pre_nb_rbs_required[dlsch_ue_select_tbl_in_use], sizeof(uint16_t)*MAX_NUM_CCs*MAX_MOBILES_PER_ENB); #endif @@ -678,7 +999,7 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, } rnti = dlsch_ue_select[CC_id].list[i].rnti; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP,subframeP); Round = ue_sched_ctl->round[CC_id][harq_pid]; @@ -689,23 +1010,15 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, nb_rbs_required_remaining[CC_id][UE_id] = cmin(average_rbs_per_user[CC_id], dlsch_ue_select[CC_id].list[i].nb_rb); } - /* slicing support has been introduced into the scheduler. Provide dummy - * data so that the preprocessor "simply works" */ - for (c = 0; c < MAX_NUM_CCs; ++c) - for (j = 0; j < N_RBG_MAX; ++j) - slice_allocation[c][j] = 1; - LOG_T(MAC,"calling dlsch_scheduler_pre_processor_allocate .. \n "); - dlsch_scheduler_pre_processor_allocate (Mod_id, - UE_id, - CC_id, - N_RBG[CC_id], - min_rb_unit[CC_id], - (uint16_t (*)[MAX_MOBILES_PER_ENB])nb_rbs_required, - (uint16_t (*)[MAX_MOBILES_PER_ENB])nb_rbs_required_remaining, - rballoc_sub, - slice_allocation, - MIMO_mode_indicator); + dlsch_scheduler_pre_processor_allocate_fairRR( + Mod_id, + UE_id, + CC_id, + N_RBG[CC_id], + (uint16_t(*)[NUMBER_OF_UE_MAX])nb_rbs_required, + (uint16_t(*)[NUMBER_OF_UE_MAX])nb_rbs_required_remaining, + rballoc_sub); temp_total_rbs_count -= ue_sched_ctl->pre_nb_available_rbs[CC_id]; temp_total_ue_count--; @@ -782,7 +1095,7 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, } UE_id = dlsch_ue_select[CC_id].list[i].UE_id; - ue_sched_ctl = &RC.mac[Mod_id]->UE_list.UE_sched_ctrl[UE_id]; + ue_sched_ctl = &RC.mac[Mod_id]->UE_info.UE_sched_ctrl[UE_id]; //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].dl_pow_off = dl_pow_off[UE_id]; if (ue_sched_ctl->pre_nb_available_rbs[CC_id] > 0) { @@ -835,7 +1148,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, uint16_t sdu_length_total = 0; eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = eNB->common_channels; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; // int continue_flag = 0; int32_t snr, target_snr; int32_t tpc = 1; @@ -933,7 +1246,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, N_RBG[CC_id] = to_rbg(cc[CC_id].mib->message.dl_Bandwidth); // store the global enb stats: - eNB->eNB_stats[CC_id].num_dlactive_UEs = UE_list->num_UEs; + eNB->eNB_stats[CC_id].num_dlactive_UEs = UE_info->num_UEs; eNB->eNB_stats[CC_id].available_prbs = total_nb_available_rb[CC_id]; eNB->eNB_stats[CC_id].total_available_prbs += @@ -973,12 +1286,12 @@ schedule_ue_spec_fairRR(module_id_t module_idP, rnti = UE_RNTI(module_idP,UE_id); if (rnti==NOT_A_RNTI) { - LOG_E(MAC,"Cannot find rnti for UE_id %d (num_UEs %d)\n",UE_id,UE_list->num_UEs); + LOG_E(MAC,"Cannot find rnti for UE_id %d (num_UEs %d)\n",UE_id,UE_info->num_UEs); continue; } - eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id]; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; /* switch(get_tmode(module_idP,CC_id,UE_id)){ @@ -1005,7 +1318,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, UE_id, CC_id, cc[CC_id].tdd_Config->subframeAssignment, - UE_list); + UE_info); // update UL DAI after DLSCH scheduling set_ul_DAI(module_idP,UE_id,CC_id,frameP,subframeP); } @@ -1013,18 +1326,16 @@ schedule_ue_spec_fairRR(module_id_t module_idP, nb_available_rb = ue_sched_ctl->pre_nb_available_rbs[CC_id]; harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP,subframeP); round = ue_sched_ctl->round[CC_id][harq_pid]; - UE_list->eNB_UE_stats[CC_id][UE_id].crnti = rnti; - UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status = - mac_eNB_get_rrc_status(module_idP, rnti); - UE_list->eNB_UE_stats[CC_id][UE_id].harq_pid = harq_pid; - UE_list->eNB_UE_stats[CC_id][UE_id].harq_round = round; + UE_info->eNB_UE_stats[CC_id][UE_id].crnti = rnti; + UE_info->eNB_UE_stats[CC_id][UE_id].rrc_status = mac_eNB_get_rrc_status(module_idP, rnti); + UE_info->eNB_UE_stats[CC_id][UE_id].harq_pid = harq_pid; + UE_info->eNB_UE_stats[CC_id][UE_id].harq_round = round; - if (UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status < RRC_RECONFIGURED) { - UE_list->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; + if (UE_info->eNB_UE_stats[CC_id][UE_id].rrc_status < RRC_RECONFIGURED) { + UE_info->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; } - if (UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status < - RRC_CONNECTED) + if (UE_info->eNB_UE_stats[CC_id][UE_id].rrc_status < RRC_CONNECTED) continue; sdu_length_total = 0; @@ -1043,13 +1354,11 @@ schedule_ue_spec_fairRR(module_id_t module_idP, //eNB_UE_stats->dlsch_mcs1 = cmin(eNB_UE_stats->dlsch_mcs1, openair_daq_vars.target_ue_dl_mcs); // store stats - //UE_list->eNB_UE_stats[CC_id][UE_id].dl_cqi= eNB_UE_stats->dl_cqi; + //UE_info->eNB_UE_stats[CC_id][UE_id].dl_cqi= eNB_UE_stats->dl_cqi; // initializing the rb allocation indicator for each UE for (j = 0; j < N_RBG[CC_id]; j++) { - UE_list-> - UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] - = 0; + UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = 0; } LOG_D(MAC, @@ -1057,33 +1366,31 @@ schedule_ue_spec_fairRR(module_id_t module_idP, module_idP, frameP, UE_id, CC_id, rnti, harq_pid, round, nb_available_rb, ue_sched_ctl->dl_cqi[CC_id], eNB_UE_stats->dlsch_mcs1, - UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status); + UE_info->eNB_UE_stats[CC_id][UE_id].rrc_status); /* process retransmission */ if (round != 8) { // get freq_allocation - nb_rb = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; TBS = - get_TBS_DL(UE_list-> - UE_template[CC_id][UE_id].oldmcs1[harq_pid], + get_TBS_DL(UE_info->UE_template[CC_id][UE_id].oldmcs1[harq_pid], nb_rb); if (nb_rb <= nb_available_rb) { if (cc[CC_id].tdd_Config != NULL) { - UE_list->UE_template[CC_id][UE_id].DAI++; + UE_info->UE_template[CC_id][UE_id].DAI++; update_ul_dci(module_idP, CC_id, rnti, - UE_list->UE_template[CC_id][UE_id]. - DAI,subframeP); + UE_info->UE_template[CC_id][UE_id].DAI,subframeP); LOG_D(MAC, "DAI update: CC_id %d subframeP %d: UE %d, DAI %d\n", CC_id, subframeP, UE_id, - UE_list->UE_template[CC_id][UE_id].DAI); + UE_info->UE_template[CC_id][UE_id].DAI); } if (nb_rb == ue_sched_ctl->pre_nb_available_rbs[CC_id]) { for (j = 0; j < N_RBG[CC_id]; j++) { // for indicating the rballoc for each sub-band - UE_list->UE_template[CC_id][UE_id]. + UE_info->UE_template[CC_id][UE_id]. rballoc_subband[harq_pid][j] = ue_sched_ctl->rballoc_sub_UE[CC_id][j]; } @@ -1094,16 +1401,10 @@ schedule_ue_spec_fairRR(module_id_t module_idP, while ((nb_rb_temp > 0) && (j < N_RBG[CC_id])) { if (ue_sched_ctl->rballoc_sub_UE[CC_id][j] == 1) { - if (UE_list-> - UE_template[CC_id] - [UE_id].rballoc_subband[harq_pid][j]) - printf - ("WARN: rballoc_subband not free for retrans?\n"); + if (UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j]) + LOG_W(MAC, "WARN: rballoc_subband not free for retrans?\n"); - UE_list-> - UE_template[CC_id] - [UE_id].rballoc_subband[harq_pid][j] = - ue_sched_ctl->rballoc_sub_UE[CC_id][j]; + UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = ue_sched_ctl->rballoc_sub_UE[CC_id][j]; if ((j == N_RBG[CC_id] - 1) && ((N_RB_DL[CC_id] == 25) || @@ -1127,7 +1428,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, eNB->mu_mimo_mode[UE_id].dl_pow_off = ue_sched_ctl->dl_pow_off[CC_id]; for(j=0; jmu_mimo_mode[UE_id].rballoc_sub[j] = UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j]; + eNB->mu_mimo_mode[UE_id].rballoc_sub[j] = UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j]; } */ @@ -1164,36 +1465,23 @@ schedule_ue_spec_fairRR(module_id_t module_idP, harq_process = harq_pid; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = 1; // dont adjust power when retransmitting dl_config_pdu->dci_dl_pdu. - dci_dl_pdu_rel8.new_data_indicator_1 = - UE_list->UE_template[CC_id][UE_id]. - oldNDI[harq_pid]; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = - UE_list->UE_template[CC_id][UE_id]. - oldmcs1[harq_pid]; - dl_config_pdu->dci_dl_pdu. - dci_dl_pdu_rel8.redundancy_version_1 = - round & 3; + dci_dl_pdu_rel8.new_data_indicator_1 = UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = UE_info->UE_template[CC_id][UE_id].oldmcs1[harq_pid]; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = round & 3; if (cc[CC_id].tdd_Config != NULL) { //TDD dl_config_pdu->dci_dl_pdu. - dci_dl_pdu_rel8.downlink_assignment_index = - (UE_list->UE_template[CC_id][UE_id].DAI - - 1) & 3; + dci_dl_pdu_rel8.downlink_assignment_index = (UE_info->UE_template[CC_id][UE_id].DAI - 1) & 3; LOG_D(MAC, "[eNB %d] Retransmission CC_id %d : harq_pid %d, round %d, dai %d, mcs %d\n", module_idP, CC_id, harq_pid, round, - (UE_list->UE_template[CC_id][UE_id].DAI - - 1), - UE_list-> - UE_template[CC_id][UE_id].oldmcs1 - [harq_pid]); + UE_info->UE_template[CC_id][UE_id].DAI - 1, + UE_info-> UE_template[CC_id][UE_id].oldmcs1[harq_pid]); } else { LOG_D(MAC, "[eNB %d] Retransmission CC_id %d : harq_pid %d, round %d, mcs %d\n", module_idP, CC_id, harq_pid, round, - UE_list-> - UE_template[CC_id][UE_id].oldmcs1 - [harq_pid]); + UE_info->UE_template[CC_id][UE_id].oldmcs1[harq_pid]); } if (!CCE_allocation_infeasible @@ -1205,12 +1493,14 @@ schedule_ue_spec_fairRR(module_id_t module_idP, dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; eNB->DL_req[CC_id].sfn_sf = frameP<<4 | subframeP; eNB->DL_req[CC_id].header.message_id = NFAPI_DL_CONFIG_REQUEST; - fill_nfapi_dlsch_config(eNB, dl_req, TBS, -1 + fill_nfapi_dlsch_config(&dl_req->dl_config_pdu_list[dl_req->number_pdu], + TBS, + -1 /* retransmission, no pdu_index */ , rnti, 0, // type 0 allocation from 7.1.6 in 36.213 0, // virtual_resource_block_assignment_flag, unused here 0, // resource_block_coding, to be filled in later - getQm(UE_list->UE_template[CC_id][UE_id].oldmcs1[harq_pid]), round & 3, // redundancy version + getQm(UE_info->UE_template[CC_id][UE_id].oldmcs1[harq_pid]), round & 3, // redundancy version 1, // transport blocks 0, // transport block to codeword swap flag cc[CC_id].p_eNB == 1 ? 0 : 1, // transmission_scheme @@ -1218,13 +1508,14 @@ schedule_ue_spec_fairRR(module_id_t module_idP, 1, // number of subbands // uint8_t codebook_index, 4, // UE category capacity - UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated->p_a, 0, // delta_power_offset for TM5 + UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated->p_a, 0, // delta_power_offset for TM5 0, // ngap 0, // nprb cc[CC_id].p_eNB == 1 ? 1 : 2, // transmission mode 0, //number of PRBs treated as one subband, not used here 0 // number of beamforming vectors, not used here ); + dl_req->number_pdu++; LOG_D(MAC, "Filled NFAPI configuration for DCI/DLSCH %d, retransmission round %d\n", eNB->pdu_index[CC_id], round); @@ -1248,16 +1539,11 @@ schedule_ue_spec_fairRR(module_id_t module_idP, S_DL_SCHEDULED, rnti); //eNB_UE_stats->dlsch_trials[round]++; - UE_list->eNB_UE_stats[CC_id][UE_id]. - num_retransmission += 1; - UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used_retx = - nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id]. - total_rbs_used_retx += nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = - eNB_UE_stats->dlsch_mcs1; - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2 = - eNB_UE_stats->dlsch_mcs1; + UE_info->eNB_UE_stats[CC_id][UE_id].num_retransmission += 1; + UE_info->eNB_UE_stats[CC_id][UE_id].rbs_used_retx = nb_rb; + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used_retx += nb_rb; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = eNB_UE_stats->dlsch_mcs1; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1; } else { LOG_D(MAC, "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n", @@ -1289,7 +1575,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, header_len_dcch = 2; // 2 bytes DCCH SDU subheader if (TBS - ta_len - header_len_dcch > 0) { - rlc_status = mac_rlc_status_ind(module_idP, rnti, module_idP, frameP, subframeP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH, (TBS - ta_len - header_len_dcch),0, 0); // transport block set size + rlc_status = mac_rlc_status_ind(module_idP, rnti, module_idP, frameP, subframeP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH, 0, 0); // transport block set size sdu_lengths[0] = 0; if (rlc_status.bytes_in_buffer > 0) { // There is DCCH to transmit @@ -1297,7 +1583,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP, "[eNB %d] SFN/SF %d.%d, DL-DCCH->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n", module_idP, frameP, subframeP, CC_id, TBS - header_len_dcch); - sdu_lengths[0] = mac_rlc_data_req(module_idP, rnti, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH, TBS, //not used + sdu_lengths[0] = mac_rlc_data_req(module_idP, rnti, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH, + TBS - ta_len - header_len_dcch, (char *) &dlsch_buffer[0],0, 0 ); @@ -1369,11 +1656,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP, module_idP, CC_id, frameP, subframeP, UE_id, rnti, sdu_lengths[0],rlc_status.bytes_in_buffer,rrc_release_info.num_UEs); sdu_length_total = sdu_lengths[0]; sdu_lcids[0] = DCCH; - UE_list->eNB_UE_stats[CC_id][UE_id]. - num_pdu_tx[DCCH] += 1; - UE_list-> - eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH] - += sdu_lengths[0]; + UE_info->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[DCCH] += 1; + UE_info->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH] += sdu_lengths[0]; num_sdus = 1; #ifdef DEBUG_eNB_SCHEDULER LOG_T(MAC, @@ -1394,7 +1678,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, // check for DCCH1 and update header information (assume 2 byte sub-header) if (TBS - ta_len - header_len_dcch - sdu_length_total > 0) { - rlc_status = mac_rlc_status_ind(module_idP, rnti, module_idP, frameP, subframeP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH + 1, (TBS - ta_len - header_len_dcch - sdu_length_total),0, 0 + rlc_status = mac_rlc_status_ind(module_idP, rnti, module_idP, frameP, subframeP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH + 1, 0, 0 ); // transport block set size less allocations for timing advance and // DCCH SDU sdu_lengths[num_sdus] = 0; @@ -1404,7 +1688,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP, "[eNB %d], Frame %d, DCCH1->DLSCH, CC_id %d, Requesting %d bytes from RLC (RRC message)\n", module_idP, frameP, CC_id, TBS - header_len_dcch - sdu_length_total); - sdu_lengths[num_sdus] += mac_rlc_data_req(module_idP, rnti, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH + 1, TBS, //not used + sdu_lengths[num_sdus] += mac_rlc_data_req(module_idP, rnti, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_NO, DCCH + 1, + TBS - ta_len - header_len_dcch - sdu_length_total, (char *) &dlsch_buffer[sdu_length_total],0, 0 ); T(T_ENB_MAC_UE_DL_SDU, T_INT(module_idP), @@ -1414,11 +1699,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP, sdu_lcids[num_sdus] = DCCH1; sdu_length_total += sdu_lengths[num_sdus]; header_len_dcch += 2; - UE_list->eNB_UE_stats[CC_id][UE_id]. - num_pdu_tx[DCCH1] += 1; - UE_list-> - eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH1] - += sdu_lengths[num_sdus]; + UE_info->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[DCCH1] += 1; + UE_info->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[DCCH1] += sdu_lengths[num_sdus]; num_sdus++; #ifdef DEBUG_eNB_SCHEDULER LOG_T(MAC, @@ -1460,7 +1742,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS - ta_len - header_len_dcch - sdu_length_total - header_len_dtch, 0, 0 + 0, 0 ); if (rlc_status.bytes_in_buffer > 0) { @@ -1477,7 +1759,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS, //not used + TBS - ta_len - header_len_dcch - sdu_length_total - header_len_dtch, (char *)&dlsch_buffer[sdu_length_total], 0, 0 ); T(T_ENB_MAC_UE_DL_SDU, @@ -1495,8 +1777,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP, lcid); sdu_lcids[num_sdus] = lcid; sdu_length_total += sdu_lengths[num_sdus]; - UE_list->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[lcid] += 1; - UE_list->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[lcid] += sdu_lengths[num_sdus]; + UE_info->eNB_UE_stats[CC_id][UE_id].num_pdu_tx[lcid] += 1; + UE_info->eNB_UE_stats[CC_id][UE_id].num_bytes_tx[lcid] += sdu_lengths[num_sdus]; if (sdu_lengths[num_sdus] < 128) { header_len_dtch--; @@ -1504,7 +1786,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, } num_sdus++; - UE_list->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; + UE_info->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; } else { // no data for this LCID header_len_dtch -= 3; } @@ -1557,9 +1839,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, if (nb_rb == ue_sched_ctl->pre_nb_available_rbs[CC_id]) { for (j = 0; j < N_RBG[CC_id]; j++) { // for indicating the rballoc for each sub-band - UE_list->UE_template[CC_id][UE_id]. - rballoc_subband[harq_pid][j] = - ue_sched_ctl->rballoc_sub_UE[CC_id][j]; + UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = ue_sched_ctl->rballoc_sub_UE[CC_id][j]; } } else { nb_rb_temp = nb_rb; @@ -1568,10 +1848,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, while ((nb_rb_temp > 0) && (j < N_RBG[CC_id])) { if (ue_sched_ctl->rballoc_sub_UE[CC_id][j] == 1) { - UE_list-> - UE_template[CC_id] - [UE_id].rballoc_subband[harq_pid][j] = - ue_sched_ctl->rballoc_sub_UE[CC_id][j]; + UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = ue_sched_ctl->rballoc_sub_UE[CC_id][j]; if ((j == N_RBG[CC_id] - 1) && ((N_RB_DL[CC_id] == 25) || @@ -1650,7 +1927,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, } #endif - offset = generate_dlsch_header((unsigned char *) UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], num_sdus, //num_sdus + offset = generate_dlsch_header((unsigned char *) UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], num_sdus, //num_sdus sdu_lengths, // sdu_lcids, 255, // no drx ta_update, // timing advance @@ -1679,20 +1956,20 @@ schedule_ue_spec_fairRR(module_id_t module_idP, LOG_T(MAC, "\n"); #endif // cycle through SDUs and place in dlsch_buffer - memcpy(&UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset],dlsch_buffer,sdu_length_total); + memcpy(&UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset],dlsch_buffer,sdu_length_total); // memcpy(RC.mac[0].DLSCH_pdu[0][0].payload[0][offset],dcch_buffer,sdu_lengths[0]); // fill remainder of DLSCH with random data for (j=0; j<(TBS-sdu_length_total-offset); j++) { - UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset+sdu_length_total+j] = (char)(taus()&0xff); + UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset+sdu_length_total+j] = (char)(taus()&0xff); } - trace_pdu(DIRECTION_DOWNLINK, (uint8_t *)UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], + trace_pdu(DIRECTION_DOWNLINK, (uint8_t *)UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], TBS, module_idP, WS_RA_RNTI, UE_RNTI(module_idP, UE_id), eNB->frame, eNB->subframe,0,0); T(T_ENB_MAC_UE_DL_PDU_WITH_DATA, T_INT(module_idP), T_INT(CC_id), T_INT(rnti), T_INT(frameP), T_INT(subframeP), - T_INT(harq_pid), T_BUFFER(UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], TBS)); - UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid] = nb_rb; + T_INT(harq_pid), T_BUFFER(UE_info->DLSCH_pdu[CC_id][0][UE_id].payload[0], TBS)); + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid] = nb_rb; add_ue_dlsch_info(module_idP, CC_id, UE_id, @@ -1702,37 +1979,37 @@ schedule_ue_spec_fairRR(module_id_t module_idP, // store stats eNB->eNB_stats[CC_id].dlsch_bytes_tx+=sdu_length_total; eNB->eNB_stats[CC_id].dlsch_pdus_tx+=1; - UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used = nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used += nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1=eNB_UE_stats->dlsch_mcs1; - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2=mcs; - UE_list->eNB_UE_stats[CC_id][UE_id].TBS = TBS; - UE_list->eNB_UE_stats[CC_id][UE_id].overhead_bytes= TBS- sdu_length_total; - UE_list->eNB_UE_stats[CC_id][UE_id].total_sdu_bytes+= sdu_length_total; - UE_list->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes+= TBS; - UE_list->eNB_UE_stats[CC_id][UE_id].total_num_pdus+=1; + UE_info->eNB_UE_stats[CC_id][UE_id].rbs_used = nb_rb; + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used += nb_rb; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1=eNB_UE_stats->dlsch_mcs1; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2=mcs; + UE_info->eNB_UE_stats[CC_id][UE_id].TBS = TBS; + UE_info->eNB_UE_stats[CC_id][UE_id].overhead_bytes= TBS- sdu_length_total; + UE_info->eNB_UE_stats[CC_id][UE_id].total_sdu_bytes+= sdu_length_total; + UE_info->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes+= TBS; + UE_info->eNB_UE_stats[CC_id][UE_id].total_num_pdus+=1; if (cc[CC_id].tdd_Config != NULL) { // TDD - UE_list->UE_template[CC_id][UE_id].DAI++; - update_ul_dci(module_idP,CC_id,rnti,UE_list->UE_template[CC_id][UE_id].DAI,subframeP); + UE_info->UE_template[CC_id][UE_id].DAI++; + update_ul_dci(module_idP,CC_id,rnti,UE_info->UE_template[CC_id][UE_id].DAI,subframeP); } // do PUCCH power control // this is the snr - eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id]; + eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; /* Unit is not dBm, it's special from nfapi */ snr = (5 * ue_sched_ctl->pucch1_snr[CC_id] - 640) / 10; target_snr = eNB->puCch10xSnr / 10; // this assumes accumulated tpc // make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out - int32_t framex10psubframe = UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_frame*10+UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe; + int32_t framex10psubframe = UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_frame*10+UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe; if (((framex10psubframe+10)<=(frameP*10+subframeP)) || //normal case ((framex10psubframe>(frameP*10+subframeP)) && (((10240-framex10psubframe+frameP*10+subframeP)>=10)))) //frame wrap-around if (ue_sched_ctl->pucch1_cqi_update[CC_id] == 1) { ue_sched_ctl->pucch1_cqi_update[CC_id] = 0; - UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_frame=frameP; - UE_list->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe=subframeP; + UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_frame=frameP; + UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe=subframeP; if (snr > target_snr + 4) { tpc = 0; //-1 @@ -1767,7 +2044,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = harq_pid; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = tpc; // dont adjust power when retransmitting - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = 1-UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = mcs; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = 0; //deactivate second codeword @@ -1775,10 +2052,10 @@ schedule_ue_spec_fairRR(module_id_t module_idP, dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_2 = 1; if (cc[CC_id].tdd_Config != NULL) { //TDD - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = (UE_list->UE_template[CC_id][UE_id].DAI-1)&3; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = (UE_info->UE_template[CC_id][UE_id].DAI-1)&3; LOG_D(MAC,"[eNB %d] Initial transmission CC_id %d : harq_pid %d, dai %d, mcs %d\n", module_idP,CC_id,harq_pid, - (UE_list->UE_template[CC_id][UE_id].DAI-1), + (UE_info->UE_template[CC_id][UE_id].DAI-1), mcs); } else { LOG_D(MAC,"[eNB %d] Initial transmission CC_id %d : harq_pid %d, mcs %d\n", @@ -1797,13 +2074,13 @@ schedule_ue_spec_fairRR(module_id_t module_idP, // Toggle NDI for next time LOG_D(MAC,"CC_id %d Frame %d, subframeP %d: Toggling Format1 NDI for UE %d (rnti %x/%d) oldNDI %d\n", CC_id, frameP,subframeP,UE_id, - rnti,harq_pid,UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]); - UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]=1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]; - UE_list->UE_template[CC_id][UE_id].oldmcs1[harq_pid] = mcs; - UE_list->UE_template[CC_id][UE_id].oldmcs2[harq_pid] = 0; - AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated!=NULL,"physicalConfigDedicated is NULL\n"); - AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated!=NULL,"physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n"); - fill_nfapi_dlsch_config(eNB,dl_req, + rnti,harq_pid,UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]); + UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]=1-UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]; + UE_info->UE_template[CC_id][UE_id].oldmcs1[harq_pid] = mcs; + UE_info->UE_template[CC_id][UE_id].oldmcs2[harq_pid] = 0; + AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated!=NULL,"physicalConfigDedicated is NULL\n"); + AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated!=NULL,"physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n"); + fill_nfapi_dlsch_config(&dl_req->dl_config_pdu_list[dl_req->number_pdu], TBS, eNB->pdu_index[CC_id], rnti, @@ -1819,7 +2096,7 @@ schedule_ue_spec_fairRR(module_id_t module_idP, 1, // number of subbands // uint8_t codebook_index, 4, // UE category capacity - UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated->p_a, + UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated->p_a, 0, // delta_power_offset for TM5 0, // ngap 0, // nprb @@ -1827,11 +2104,12 @@ schedule_ue_spec_fairRR(module_id_t module_idP, 0, //number of PRBs treated as one subband, not used here 0 // number of beamforming vectors, not used here ); + dl_req->number_pdu++; eNB->TX_req[CC_id].sfn_sf = fill_nfapi_tx_req(&eNB->TX_req[CC_id].tx_request_body, (frameP*10)+subframeP, TBS, eNB->pdu_index[CC_id], - eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0]); + eNB->UE_info.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0]); LOG_D(MAC,"Filled NFAPI configuration for DCI/DLSCH/TXREQ %d, new SDU\n",eNB->pdu_index[CC_id]); eNB->pdu_index[CC_id]++; program_dlsch_acknak(module_idP,CC_id,UE_id,frameP,subframeP,dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx); @@ -1876,7 +2154,7 @@ fill_DLSCH_dci_fairRR( int i; int CC_id; eNB_MAC_INST *eNB =RC.mac[module_idP]; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; int N_RBG; int N_RB_DL; COMMON_channels_t *cc; @@ -1912,11 +2190,11 @@ fill_DLSCH_dci_fairRR( eNB_dlsch_info[module_idP][CC_id][UE_id].status = S_DL_WAITING; rnti = UE_RNTI(module_idP,UE_id); harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP,subframeP); - nb_rb = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; /// Synchronizing rballoc with rballoc_sub for(i=0; iUE_template[CC_id][UE_id].rballoc_subband[harq_pid][i]; + rballoc_sub[i] = UE_info->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][i]; } nfapi_dl_config_request_t *DL_req = &RC.mac[module_idP]->DL_req[0]; @@ -1962,7 +2240,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( uint8_t first_ue_total[MAX_NUM_CCs][20]; uint8_t first_ue_id[MAX_NUM_CCs][20]; uint8_t ul_inactivity_num[MAX_NUM_CCs]; - uint8_t ul_inactivity_id[MAX_NUM_CCs][20]; + uint8_t ul_inactivity_id[MAX_NUM_CCs][20]={0}; // LTE_DL_FRAME_PARMS *frame_parms; uint8_t ulsch_ue_max_num[MAX_NUM_CCs]; uint16_t saved_ulsch_dci[MAX_NUM_CCs]; @@ -1970,7 +2248,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( UE_sched_ctrl_t *UE_sched_ctl = NULL; uint8_t cc_id_flag[MAX_NUM_CCs]; uint8_t harq_pid = 0,round = 0; - UE_list_t *UE_list= &eNB->UE_list; + UE_info_t *UE_info= &eNB->UE_info; uint8_t aggregation; int format_flag; nfapi_hi_dci0_request_body_t *HI_DCI0_req; @@ -1989,7 +2267,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( // UE round >0 for ( UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++ ) { - if (UE_list->active[UE_id] == FALSE) + if (UE_info->active[UE_id] == FALSE) continue; rnti = UE_RNTI(module_idP,UE_id); @@ -1999,10 +2277,10 @@ void ulsch_scheduler_pre_ue_select_fairRR( CC_id = UE_PCCID(module_idP,UE_id); - if (UE_list->UE_template[CC_id][UE_id].configured == FALSE) + if (UE_info->UE_template[CC_id][UE_id].configured == FALSE) continue; - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) + if (UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; // UL DCI @@ -2026,12 +2304,12 @@ void ulsch_scheduler_pre_ue_select_fairRR( //harq_pid harq_pid = subframe2harqpid(cc,(frameP+(sched_subframePUE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid]; + round = UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid]; if ( round > 0 ) { hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci+HI_DCI0_req->number_of_hi]; format_flag = 2; - aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id],format0); + aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id],format0); if (CCE_allocation_infeasible(module_idP,CC_id,format_flag,subframeP,aggregation,rnti) == 1) { cc_id_flag[CC_id] = 1; @@ -2042,8 +2320,8 @@ void ulsch_scheduler_pre_ue_select_fairRR( hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; HI_DCI0_req->number_of_dci++; ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].ue_priority = SCH_UL_RETRANS; - ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].start_rb = eNB->UE_list.UE_template[CC_id][UE_id].first_rb_ul[harq_pid]; - ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].nb_rb = eNB->UE_list.UE_template[CC_id][UE_id].nb_rb_ul[harq_pid]; + ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].start_rb = eNB->UE_info.UE_template[CC_id][UE_id].first_rb_ul[harq_pid]; + ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].nb_rb = eNB->UE_info.UE_template[CC_id][UE_id].nb_rb_ul[harq_pid]; ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].UE_id = UE_id; ulsch_ue_select[CC_id].ue_num++; continue; @@ -2051,7 +2329,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( } // - int bytes_to_schedule = UE_list->UE_template[CC_id][UE_id].estimated_ul_buffer - UE_list->UE_template[CC_id][UE_id].scheduled_ul_bytes; + int bytes_to_schedule = UE_info->UE_template[CC_id][UE_id].estimated_ul_buffer - UE_info->UE_template[CC_id][UE_id].scheduled_ul_bytes; if (bytes_to_schedule < 0) bytes_to_schedule = 0; @@ -2063,14 +2341,14 @@ void ulsch_scheduler_pre_ue_select_fairRR( continue; } - if ( UE_list->UE_template[CC_id][UE_id].ul_SR > 0 ) { + if ( UE_info->UE_template[CC_id][UE_id].ul_SR > 0 ) { first_ue_id[CC_id][ue_first_num[CC_id]]= UE_id; first_ue_total[CC_id] [ue_first_num[CC_id]] = 0; ue_first_num[CC_id]++; continue; } - UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; rrc_status = mac_eNB_get_rrc_status(module_idP, rnti); if ( ((UE_sched_ctl->ul_inactivity_timer>20)&&(UE_sched_ctl->ul_scheduled==0)) || @@ -2083,7 +2361,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( } /*if ( (ulsch_ue_select[CC_id].ue_num+ul_inactivity_num[CC_id] ) < ulsch_ue_max_num[CC_id] ) { - UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; uint8_t ul_period = 0; if (cc->tdd_Config) { ul_period = 50; @@ -2113,7 +2391,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci+HI_DCI0_req->number_of_hi]; format_flag = 2; rnti = UE_RNTI(module_idP,first_ue_id[CC_id][temp]); - aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_list->UE_sched_ctrl[first_ue_id[CC_id][temp]].dl_cqi[CC_id],format0); + aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_info->UE_sched_ctrl[first_ue_id[CC_id][temp]].dl_cqi[CC_id],format0); if (CCE_allocation_infeasible(module_idP,CC_id,format_flag,subframeP,aggregation,rnti) == 1) { cc_id_flag[CC_id] = 1; @@ -2132,7 +2410,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( } for ( UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++ ) { - if (UE_list->active[UE_id] == FALSE) + if (UE_info->active[UE_id] == FALSE) continue; rnti = UE_RNTI(module_idP,UE_id); @@ -2145,10 +2423,10 @@ void ulsch_scheduler_pre_ue_select_fairRR( if (UE_id > last_ulsch_ue_id[CC_id]) continue; - if (UE_list->UE_template[CC_id][UE_id].configured == FALSE) + if (UE_info->UE_template[CC_id][UE_id].configured == FALSE) continue; - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) + if (UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; if ( (ulsch_ue_select[CC_id].ue_num >= ulsch_ue_max_num[CC_id]) || (cc_id_flag[CC_id] == 1) ) { @@ -2176,19 +2454,19 @@ void ulsch_scheduler_pre_ue_select_fairRR( HI_DCI0_req = &eNB->HI_DCI0_req[CC_id][subframeP].hi_dci0_request_body; //SR BSR - UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - int bytes_to_schedule = UE_list->UE_template[CC_id][UE_id].estimated_ul_buffer - UE_list->UE_template[CC_id][UE_id].scheduled_ul_bytes; + UE_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; + int bytes_to_schedule = UE_info->UE_template[CC_id][UE_id].estimated_ul_buffer - UE_info->UE_template[CC_id][UE_id].scheduled_ul_bytes; if (bytes_to_schedule < 0) bytes_to_schedule = 0; rrc_status = mac_eNB_get_rrc_status(module_idP, rnti); - if ( (bytes_to_schedule > 0) || (UE_list->UE_template[CC_id][UE_id].ul_SR > 0) || + if ( (bytes_to_schedule > 0) || (UE_info->UE_template[CC_id][UE_id].ul_SR > 0) || ((UE_sched_ctl->ul_inactivity_timer>20)&&(UE_sched_ctl->ul_scheduled==0)) || ((UE_sched_ctl->ul_inactivity_timer>10)&&(UE_sched_ctl->ul_scheduled==0)&&(rrc_status < RRC_CONNECTED)) || ((UE_sched_ctl->cqi_req_timer>300)&&((rrc_status >= RRC_CONNECTED))) ) { hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci+HI_DCI0_req->number_of_hi]; format_flag = 2; - aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id],format0); + aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id],format0); if (CCE_allocation_infeasible(module_idP,CC_id,format_flag,subframeP,aggregation,rnti) == 1) { cc_id_flag[CC_id] = 1; @@ -2202,7 +2480,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( if(bytes_to_schedule > 0) ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].ul_total_buffer = bytes_to_schedule; - else if(UE_list->UE_template[CC_id][UE_id].ul_SR > 0) + else if(UE_info->UE_template[CC_id][UE_id].ul_SR > 0) ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].ul_total_buffer = 0; ulsch_ue_select[CC_id].list[ulsch_ue_select[CC_id].ue_num].UE_id = UE_id; @@ -2213,7 +2491,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( //inactivity UE /* if ( (ulsch_ue_select[CC_id].ue_num+ul_inactivity_num[CC_id]) < ulsch_ue_max_num[CC_id] ) { - UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; uint8_t ul_period = 0; if (cc->tdd_Config) { ul_period = 50; @@ -2242,7 +2520,7 @@ void ulsch_scheduler_pre_ue_select_fairRR( hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci+HI_DCI0_req->number_of_hi]; format_flag = 2; rnti = UE_RNTI(module_idP,ul_inactivity_id[CC_id][temp]); - aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_list->UE_sched_ctrl[ul_inactivity_id[CC_id][temp]].dl_cqi[CC_id],format0); + aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_info->UE_sched_ctrl[ul_inactivity_id[CC_id][temp]].dl_cqi[CC_id],format0); if (CCE_allocation_infeasible(module_idP,CC_id,format_flag,subframeP,aggregation,rnti) == 1) { cc_id_flag[CC_id] = 1; @@ -2284,7 +2562,7 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ULSCH_UE_SELECT ulsch_ue_select[MAX_NUM_CCs]) { int CC_id,ulsch_ue_num; eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list= &eNB->UE_list; + UE_info_t *UE_info= &eNB->UE_info; UE_TEMPLATE *UE_template = NULL; LTE_DL_FRAME_PARMS *frame_parms = NULL; uint8_t ue_num_temp; @@ -2383,9 +2661,9 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, } } } else { - UE_template = &UE_list->UE_template[CC_id][UE_id]; + UE_template = &UE_info->UE_template[CC_id][UE_id]; - if ( UE_list->UE_sched_ctrl[UE_id].phr_received == 1 ) { + if ( UE_info->UE_sched_ctrl[UE_id].phr_received == 1 ) { mcs = 20; } else { mcs = 10; @@ -2421,9 +2699,9 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, if ( rb_table[rb_table_index] <= average_rbs ) { // assigne RBS( nb_rb) first_rb[CC_id] = first_rb[CC_id] + rb_table[rb_table_index]; - UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[0] = rb_table[rb_table_index]; - UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = rb_table_index; - UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs; + UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = rb_table[rb_table_index]; + UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = rb_table_index; + UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs; } if ( rb_table[rb_table_index] > average_rbs ) { @@ -2437,31 +2715,31 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, } first_rb[CC_id] = first_rb[CC_id] + rb_table[rb_table_index]; - UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[0] = rb_table[rb_table_index]; - UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = rb_table_index; - UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs; + UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = rb_table[rb_table_index]; + UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = rb_table_index; + UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs; } } else { if (mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP, UE_id)) < RRC_CONNECTED) { // assigne RBS( 6 RBs) first_rb[CC_id] = first_rb[CC_id] + 6; - UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[0] = 6; - UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 5; - UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; + UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = 6; + UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 5; + UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; } else { // assigne RBS( 3 RBs) first_rb[CC_id] = first_rb[CC_id] + 3; - UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[0] = 3; - UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 2; - UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; + UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = 3; + UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 2; + UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; } } } else if ( ulsch_ue_select[CC_id].list[ulsch_ue_num].ue_priority == SCH_UL_INACTIVE ) { // assigne RBS( 3 RBs) first_rb[CC_id] = first_rb[CC_id] + 3; - UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[0] = 3; - UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 2; - UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; + UE_info->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul = 3; + UE_info->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = 2; + UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = 10; } } @@ -2641,7 +2919,7 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, int N_RB_UL; eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc; - UE_list_t *UE_list=&eNB->UE_list; + UE_info_t *UE_info=&eNB->UE_info; UE_TEMPLATE *UE_template; UE_sched_ctrl_t *UE_sched_ctrl; int sched_frame=frameP; @@ -2750,8 +3028,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, continue; } - UE_template = &UE_list->UE_template[CC_id][UE_id]; - UE_sched_ctrl = &UE_list->UE_sched_ctrl[UE_id]; + UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; harq_pid = subframe2harqpid(cc,sched_frame,sched_subframeP); rnti = UE_RNTI(CC_id,UE_id); aggregation=get_aggregation(get_bw_index(module_idP,CC_id),UE_sched_ctrl[UE_id].dl_cqi[CC_id],format0); @@ -2844,9 +3122,9 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, UE_sched_ctrl->cqi_req_timer); ndi = 1-UE_template->oldNDI_UL[harq_pid]; UE_template->oldNDI_UL[harq_pid]=ndi; - UE_list->eNB_UE_stats[CC_id][UE_id].snr = snr; - UE_list->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul; + UE_info->eNB_UE_stats[CC_id][UE_id].snr = snr; + UE_info->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul; UE_template->mcs_UL[harq_pid] = UE_template->pre_assigned_mcs_ul;//cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS if (UE_template->pre_allocated_rb_table_index_ul >=0) { @@ -2856,10 +3134,10 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, rb_table_index=5; // for PHR } - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2=UE_template->mcs_UL[harq_pid]; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2=UE_template->mcs_UL[harq_pid]; UE_template->TBS_UL[harq_pid] = get_TBS_UL(UE_template->mcs_UL[harq_pid],rb_table[rb_table_index]); - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx+=rb_table[rb_table_index]; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS=UE_template->TBS_UL[harq_pid]; + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx+=rb_table[rb_table_index]; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS=UE_template->TBS_UL[harq_pid]; T(T_ENB_MAC_UE_UL_SCHEDULE, T_INT(module_idP), T_INT(CC_id), T_INT(rnti), T_INT(frameP), T_INT(subframeP), T_INT(harq_pid), T_INT(UE_template->mcs_UL[harq_pid]), T_INT(first_rb[CC_id]), T_INT(rb_table[rb_table_index]), T_INT(UE_template->TBS_UL[harq_pid]), T_INT(ndi)); @@ -2877,7 +3155,7 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, UE_template->cqi_req[harq_pid] = cqi_req; UE_sched_ctrl->ul_scheduled |= (1<head) + if (UE_id == UE_info->list.head) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED,UE_sched_ctrl->ul_scheduled); // adjust total UL buffer status by TBS, wait for UL sdus to do final update @@ -3019,8 +3297,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, T(T_ENB_MAC_UE_UL_SCHEDULE_RETRANSMISSION, T_INT(module_idP), T_INT(CC_id), T_INT(rnti), T_INT(frameP), T_INT(subframeP), T_INT(harq_pid), T_INT(UE_template->mcs_UL[harq_pid]), T_INT(ulsch_ue_select[CC_id].list[ulsch_ue_num].start_rb), T_INT(ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb), T_INT(round)); - UE_list->eNB_UE_stats[CC_id][UE_id].snr = snr; - UE_list->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; + UE_info->eNB_UE_stats[CC_id][UE_id].snr = snr; + UE_info->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; uint8_t mcs_rv = 0; if(rvidx_tab[round&3]==1) { @@ -3032,7 +3310,7 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, } UE_template->TBS_UL[harq_pid] = get_TBS_UL(UE_template->mcs_UL[harq_pid],ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb); - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS=UE_template->TBS_UL[harq_pid]; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS=UE_template->TBS_UL[harq_pid]; if (mac_eNB_get_rrc_status(module_idP,rnti) < RRC_CONNECTED) LOG_D(MAC,"[eNB %d][PUSCH %d/%x] CC_id %d Frame %d subframeP %d Scheduled UE %d (mcs %d, first rb %d, nb_rb %d, TBS %d, harq_pid %d)\n", diff --git a/openair2/LAYER2/MAC/eNB_scheduler_fairRR.h b/openair2/LAYER2/MAC/eNB_scheduler_fairRR.h index 5355a614a6..880e60ec19 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_fairRR.h +++ b/openair2/LAYER2/MAC/eNB_scheduler_fairRR.h @@ -85,6 +85,30 @@ void dlsch_scheduler_pre_ue_select_fairRR( uint16_t nb_rbs_required[MAX_NUM_CCs][MAX_MOBILES_PER_ENB], DLSCH_UE_SELECT dlsch_ue_select[MAX_NUM_CCs]); +void dlsch_scheduler_pre_processor_reset_fairRR( + module_id_t module_idP, + frame_t frameP, + sub_frame_t subframeP, + int min_rb_unit[NFAPI_CC_MAX], + uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], + uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], + uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]); + +void assign_rbs_required_fairRR( + module_id_t Mod_id, + frame_t frameP, + sub_frame_t subframe, + uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]); + +void dlsch_scheduler_pre_processor_allocate_fairRR( + module_id_t Mod_id, + int UE_id, + uint8_t CC_id, + int N_RBG, + uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], + uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], + uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]); + void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, frame_t frameP, sub_frame_t subframeP, diff --git a/openair2/LAYER2/MAC/eNB_scheduler_mch.c b/openair2/LAYER2/MAC/eNB_scheduler_mch.c index 2953c8e70b..eb5d78fd3f 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_mch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_mch.c @@ -714,13 +714,11 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, mbms_rab_id = cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9; rlc_status = - mac_rlc_status_ind(module_idP, 0/*0xfffd*/, frameP, subframeP, + mac_rlc_status_ind(module_idP, 0xfffd, frameP, subframeP, module_idP, ENB_FLAG_YES, MBMS_FLAG_YES, cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, //MTCH, - TBS - header_len_mcch - header_len_msi - - sdu_length_total - header_len_mtch - ,0, 0 + 0, 0 ); bytes_in_buffer = rlc_status.bytes_in_buffer; @@ -773,7 +771,8 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch, header_len_mtch, rlc_status.bytes_in_buffer); - sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0/*0xfffd*/, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, 0, //not used + sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0xfffd, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, + TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch, (char *) &mch_buffer[sdu_length_total] ,0, @@ -1554,13 +1553,11 @@ schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, mbms_rab_id = cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9; rlc_status = - mac_rlc_status_ind(module_idP, 0/*0xfffd*/, frameP, subframeP, + mac_rlc_status_ind(module_idP, 0xfffd, frameP, subframeP, module_idP, ENB_FLAG_YES, MBMS_FLAG_YES, cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, //MTCH, - TBS - header_len_mcch - header_len_msi - - sdu_length_total - header_len_mtch - ,0, 0 + 0, 0 ); bytes_in_buffer = rlc_status.bytes_in_buffer; @@ -1579,7 +1576,8 @@ schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch, header_len_mtch, rlc_status.bytes_in_buffer); - sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0/*0xfffd*/, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, 0, //not used + sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0xfffd, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, + TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch, (char *) &mch_buffer[sdu_length_total] ,0, diff --git a/openair2/LAYER2/MAC/eNB_scheduler_phytest.c b/openair2/LAYER2/MAC/eNB_scheduler_phytest.c index 647db3f624..689db8e208 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_phytest.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_phytest.c @@ -133,16 +133,15 @@ schedule_ue_spec_phy_test( /* LOG_D(MAC,"CC_id %d Frame %d, subframeP %d: Toggling Format1 NDI for UE %d (rnti %x/%d) oldNDI %d\n", CC_id, frameP,subframeP,UE_id, - rnti,harq_pid,UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]); + rnti,harq_pid,UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]); - UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]=1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]; - UE_list->UE_template[CC_id][UE_id].oldmcs1[harq_pid] = mcs; - UE_list->UE_template[CC_id][UE_id].oldmcs2[harq_pid] = 0; - AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated!=NULL,"physicalConfigDedicated is NULL\n"); - AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated!=NULL,"physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n"); + UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]=1-UE_info->UE_template[CC_id][UE_id].oldNDI[harq_pid]; + UE_info->UE_template[CC_id][UE_id].oldmcs1[harq_pid] = mcs; + UE_info->UE_template[CC_id][UE_id].oldmcs2[harq_pid] = 0; + AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated!=NULL,"physicalConfigDedicated is NULL\n"); + AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated!=NULL,"physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n"); */ - fill_nfapi_dlsch_config(eNB, - dl_req, + fill_nfapi_dlsch_config(&dl_req->dl_config_pdu_list[dl_req->number_pdu], TBS, eNB->pdu_index[CC_id], rnti, @@ -166,11 +165,12 @@ schedule_ue_spec_phy_test( 0, //number of PRBs treated as one subband, not used here 0 // number of beamforming vectors, not used here ); + dl_req->number_pdu++; eNB->TX_req[CC_id].sfn_sf = fill_nfapi_tx_req(&eNB->TX_req[CC_id].tx_request_body, (frameP*10)+subframeP, TBS, eNB->pdu_index[CC_id], - eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0]); + eNB->UE_info.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0]); } else { LOG_W(MAC,"[eNB_scheduler_phytest] DCI allocation infeasible!\n"); } @@ -192,7 +192,7 @@ void schedule_ulsch_phy_test(module_id_t module_idP,frame_t frameP,sub_frame_t s int N_RB_UL; eNB_MAC_INST *mac = RC.mac[module_idP]; COMMON_channels_t *cc = &mac->common_channels[0]; - UE_list_t *UE_list=&mac->UE_list; + UE_info_t *UE_info=&mac->UE_info; UE_TEMPLATE *UE_template; UE_sched_ctrl_t *UE_sched_ctrl; int sched_frame=frameP; @@ -231,8 +231,8 @@ void schedule_ulsch_phy_test(module_id_t module_idP,frame_t frameP,sub_frame_t s first_rb[CC_id] = 1; // loop over all active UEs // if (eNB_UE_stats->mode == PUSCH) { // ue has a ulsch channel - UE_template = &UE_list->UE_template[CC_id][UE_id]; - UE_sched_ctrl = &UE_list->UE_sched_ctrl[UE_id]; + UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; harq_pid = subframe2harqpid(&cc[CC_id],sched_frame,sched_subframe); RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP*10)+subframeP] = UE_template->TBS_UL[harq_pid]; //power control @@ -242,15 +242,15 @@ void schedule_ulsch_phy_test(module_id_t module_idP,frame_t frameP,sub_frame_t s // new transmission ndi = 1-UE_template->oldNDI_UL[harq_pid]; UE_template->oldNDI_UL[harq_pid]=ndi; - UE_list->eNB_UE_stats[CC_id][UE_id].snr = snr; - UE_list->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1 = mcs; + UE_info->eNB_UE_stats[CC_id][UE_id].snr = snr; + UE_info->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1 = mcs; UE_template->mcs_UL[harq_pid] = mcs;//cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = mcs; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = mcs; // buffer_occupancy = UE_template->ul_total_buffer; UE_template->TBS_UL[harq_pid] = get_TBS_UL(mcs,nb_rb); - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = get_TBS_UL(mcs,nb_rb); + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += nb_rb; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = get_TBS_UL(mcs,nb_rb); // buffer_occupancy -= TBS; // bad indices : 20 (40 PRB), 21 (45 PRB), 22 (48 PRB) //store for possible retransmission diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index e76e6b24ba..78d6f6a3d7 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -1169,14 +1169,14 @@ program_dlsch_acknak(module_id_t module_idP, { eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = eNB->common_channels; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; rnti_t rnti = UE_RNTI(module_idP, UE_idP); nfapi_ul_config_request_body_t *ul_req; nfapi_ul_config_request_pdu_t *ul_config_pdu; int use_simultaneous_pucch_pusch = 0; nfapi_ul_config_ulsch_harq_information *ulsch_harq_information = NULL; nfapi_ul_config_harq_information *harq_information = NULL; - struct LTE_PhysicalConfigDedicated__ext2 *ext2 = UE_list->UE_template[CC_idP][UE_idP].physicalConfigDedicated->ext2; + struct LTE_PhysicalConfigDedicated__ext2 *ext2 = UE_info->UE_template[CC_idP][UE_idP].physicalConfigDedicated->ext2; if (ext2 && ext2->pucch_ConfigDedicated_v1020 && @@ -1363,12 +1363,12 @@ fill_nfapi_ulsch_harq_information(module_id_t module_ { eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = &eNB->common_channels[CC_idP]; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; int UE_id = find_UE_id(module_idP, rntiP); nfapi_ul_config_ulsch_harq_information_rel10_t *harq_information_rel10 = &harq_information->harq_information_rel10; AssertFatal(UE_id >= 0, "UE_id cannot be found, impossible\n"); - AssertFatal(UE_list != NULL, "UE_list is null\n"); - LTE_PhysicalConfigDedicated_t *physicalConfigDedicated = UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated; + AssertFatal(UE_info != NULL, "UE_info is null\n"); + LTE_PhysicalConfigDedicated_t *physicalConfigDedicated = UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated; AssertFatal(physicalConfigDedicated != NULL, "physicalConfigDedicated for rnti %x is null\n", rntiP); struct LTE_PUSCH_ConfigDedicated *puschConfigDedicated = physicalConfigDedicated->pusch_ConfigDedicated; @@ -1468,14 +1468,14 @@ fill_nfapi_harq_information(module_id_t module_idP, { eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = &eNB->common_channels[CC_idP]; - UE_list_t *UE_list = &eNB->UE_list; + UE_info_t *UE_info = &eNB->UE_info; int UE_id = find_UE_id(module_idP, rntiP); AssertFatal(UE_id >= 0, "UE_id cannot be found, impossible\n"); - AssertFatal(UE_list != NULL, "UE_list is null\n"); + AssertFatal(UE_info != NULL, "UE_info is null\n"); harq_information->harq_information_rel11.tl.tag = NFAPI_UL_CONFIG_REQUEST_HARQ_INFORMATION_REL11_TAG; harq_information->harq_information_rel11.num_ant_ports = 1; - LTE_PhysicalConfigDedicated_t *physicalConfigDedicated = UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated; + LTE_PhysicalConfigDedicated_t *physicalConfigDedicated = UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated; struct LTE_PUCCH_ConfigDedicated *pucch_ConfigDedicated = NULL; if (physicalConfigDedicated != NULL) pucch_ConfigDedicated = physicalConfigDedicated->pucch_ConfigDedicated; @@ -1489,7 +1489,7 @@ fill_nfapi_harq_information(module_id_t module_idP, case 6: case 7: if (cc->tdd_Config != NULL) { - // AssertFatal(UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated->pucch_ConfigDedicated != NULL, + // AssertFatal(UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated->pucch_ConfigDedicated != NULL, // "pucch_ConfigDedicated is null for TDD!\n"); if (physicalConfigDedicated != NULL && pucch_ConfigDedicated != NULL && pucch_ConfigDedicated->tdd_AckNackFeedbackMode != NULL && @@ -1619,15 +1619,14 @@ fill_nfapi_mch_config(nfapi_dl_config_request_body_t *dl_req, //------------------------------------------------------------------------------ void -fill_nfapi_dlsch_config(eNB_MAC_INST *eNB, - nfapi_dl_config_request_body_t *dl_req, +fill_nfapi_dlsch_config(nfapi_dl_config_request_pdu_t *dl_config_pdu, uint16_t length, int16_t pdu_index, uint16_t rnti, uint8_t resource_allocation_type, uint8_t virtual_resource_block_assignment_flag, - uint16_t resource_block_coding, + uint32_t resource_block_coding, uint8_t modulation, uint8_t redundancy_version, uint8_t transport_blocks, @@ -1646,7 +1645,6 @@ fill_nfapi_dlsch_config(eNB_MAC_INST *eNB, uint8_t num_bf_vector) //------------------------------------------------------------------------------ { - nfapi_dl_config_request_pdu_t *dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; memset((void *) dl_config_pdu, 0, sizeof(nfapi_dl_config_request_pdu_t)); dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DLSCH_PDU_TYPE; dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dlsch_pdu)); @@ -1673,7 +1671,6 @@ fill_nfapi_dlsch_config(eNB_MAC_INST *eNB, dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_mode = transmission_mode; dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_prb_per_subband = num_bf_prb_per_subband; dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_vector = num_bf_vector; - dl_req->number_pdu++; return; } @@ -1879,8 +1876,7 @@ mpdcch_sf_condition(eNB_MAC_INST *eNB, break; case TYPEUESPEC: - epdcch_setconfig_r11 = - eNB->UE_list.UE_template[CC_id][UE_id].physicalConfigDedicated->ext4->epdcch_Config_r11->config_r11.choice.setup.setConfigToAddModList_r11->list.array[0]; + epdcch_setconfig_r11 = eNB->UE_info.UE_template[CC_id][UE_id].physicalConfigDedicated->ext4->epdcch_Config_r11->config_r11.choice.setup.setConfigToAddModList_r11->list.array[0]; AssertFatal(epdcch_setconfig_r11 != NULL, " epdcch_setconfig_r11 is null for UE specific \n"); AssertFatal(epdcch_setconfig_r11->ext2 != NULL, " ext2 doesn't exist in epdcch config ' \n"); @@ -1988,11 +1984,11 @@ find_UE_id(module_id_t mod_idP, //------------------------------------------------------------------------------ { int UE_id; - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (UE_list->active[UE_id] == TRUE) { - if (UE_list->UE_template[UE_PCCID(mod_idP, UE_id)][UE_id].rnti == rntiP) { + if (UE_info->active[UE_id] == TRUE) { + if (UE_info->UE_template[UE_PCCID(mod_idP, UE_id)][UE_id].rnti == rntiP) { return UE_id; } } @@ -2027,7 +2023,7 @@ find_RA_id(module_id_t mod_idP, //------------------------------------------------------------------------------ int -UE_num_active_CC(UE_list_t *listP, +UE_num_active_CC(UE_info_t *listP, int ue_idP) //------------------------------------------------------------------------------ { @@ -2040,7 +2036,7 @@ UE_PCCID(module_id_t mod_idP, int ue_idP) //------------------------------------------------------------------------------ { - return (RC.mac[mod_idP]->UE_list.pCC_id[ue_idP]); + return (RC.mac[mod_idP]->UE_info.pCC_id[ue_idP]); } //------------------------------------------------------------------------------ @@ -2051,7 +2047,7 @@ UE_RNTI(module_id_t mod_idP, { if (!RC.mac || !RC.mac[mod_idP]) return 0; - rnti_t rnti = RC.mac[mod_idP]->UE_list.UE_template[UE_PCCID(mod_idP, + rnti_t rnti = RC.mac[mod_idP]->UE_info.UE_template[UE_PCCID(mod_idP, ue_idP)][ue_idP].rnti; if (rnti > 0) { @@ -2069,7 +2065,7 @@ is_UE_active(module_id_t mod_idP, int ue_idP) //------------------------------------------------------------------------------ { - return (RC.mac[mod_idP]->UE_list.active[ue_idP]); + return (RC.mac[mod_idP]->UE_info.active[ue_idP]); } //------------------------------------------------------------------------------ @@ -2122,28 +2118,46 @@ get_aggregation(uint8_t bw_index, //------------------------------------------------------------------------------ /* - * Dump the UL or DL UE_list into LOG_T(MAC) + * Dump the UE_list into LOG_T(MAC) */ void -dump_ue_list(UE_list_t *listP, - int ul_flag) +dump_ue_list(UE_list_t *listP) { + for (int j = listP->head; j >= 0; j = listP->next[j]) + LOG_T(MAC, "DL list node %d => %d\n", j, listP->next[j]); +} + //------------------------------------------------------------------------------ -{ - if (ul_flag == 0) { - for (int j = listP->head; j >= 0; j = listP->next[j]) { - LOG_T(MAC, "DL list node %d => %d\n", - j, - listP->next[j]); - } +/* + * Add a UE to UE_list listP + */ +inline void add_ue_list(UE_list_t *listP, int UE_id) { + if (listP->head == -1) { + listP->head = UE_id; + listP->next[UE_id] = -1; } else { - for (int j = listP->head_ul; j >= 0; j = listP->next_ul[j]) { - LOG_T(MAC, "UL list node %d => %d\n", - j, - listP->next_ul[j]); - } + int i = listP->head; + while (listP->next[i] >= 0) + i = listP->next[i]; + listP->next[i] = UE_id; + listP->next[UE_id] = -1; + } +} + +//------------------------------------------------------------------------------ +/* + * Remove a UE from the UE_list listP, return the previous element + */ +inline int remove_ue_list(UE_list_t *listP, int UE_id) { + listP->next[UE_id] = -1; + if (listP->head == UE_id) { + listP->head = listP->next[UE_id]; + return -1; } - return; + int previous = prev(listP, UE_id); + if (previous != -1) + listP->next[previous] = listP->next[UE_id]; + return previous; } //------------------------------------------------------------------------------ @@ -2158,50 +2172,47 @@ add_new_ue(module_id_t mod_idP, { int UE_id; int i, j; - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; - LOG_D(MAC, "[eNB %d, CC_id %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n", + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; + LOG_D(MAC, "[eNB %d, CC_id %d] Adding UE with rnti %x (prev. num_UEs %d)\n", mod_idP, cc_idP, rntiP, - UE_list->avail, - UE_list->num_UEs); - dump_ue_list(UE_list, 0); + UE_info->num_UEs); for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { - if (UE_list->active[i] == TRUE) + if (UE_info->active[i] == TRUE) continue; UE_id = i; - memset(&UE_list->UE_template[cc_idP][UE_id], 0, sizeof(UE_TEMPLATE)); - UE_list->UE_template[cc_idP][UE_id].rnti = rntiP; - UE_list->UE_template[cc_idP][UE_id].configured = FALSE; - UE_list->numactiveCCs[UE_id] = 1; - UE_list->numactiveULCCs[UE_id] = 1; - UE_list->pCC_id[UE_id] = cc_idP; - UE_list->ordered_CCids[0][UE_id] = cc_idP; - UE_list->ordered_ULCCids[0][UE_id] = cc_idP; - UE_list->num_UEs++; - UE_list->active[UE_id] = TRUE; + memset(&UE_info->UE_template[cc_idP][UE_id], 0, sizeof(UE_TEMPLATE)); + UE_info->UE_template[cc_idP][UE_id].rnti = rntiP; + UE_info->UE_template[cc_idP][UE_id].configured = FALSE; + UE_info->numactiveCCs[UE_id] = 1; + UE_info->numactiveULCCs[UE_id] = 1; + UE_info->pCC_id[UE_id] = cc_idP; + UE_info->ordered_CCids[0][UE_id] = cc_idP; + UE_info->ordered_ULCCids[0][UE_id] = cc_idP; + UE_info->num_UEs++; + UE_info->active[UE_id] = TRUE; + add_ue_list(&UE_info->list, UE_id); + dump_ue_list(&UE_info->list); if (IS_SOFTMODEM_IQPLAYER)// not specific to record/playback ? - UE_list->UE_template[cc_idP][UE_id].pre_assigned_mcs_ul = 0; - UE_list->UE_template[cc_idP][UE_id].rach_resource_type = rach_resource_type; - memset((void *) &UE_list->UE_sched_ctrl[UE_id], + UE_info->UE_template[cc_idP][UE_id].pre_assigned_mcs_ul = 0; + UE_info->UE_template[cc_idP][UE_id].rach_resource_type = rach_resource_type; + memset((void *) &UE_info->UE_sched_ctrl[UE_id], 0, sizeof(UE_sched_ctrl_t)); - memset((void *) &UE_list->eNB_UE_stats[cc_idP][UE_id], + memset((void *) &UE_info->eNB_UE_stats[cc_idP][UE_id], 0, sizeof(eNB_UE_STATS)); - UE_list->UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 0; - /* default slice in case there was something different */ - UE_list->assoc_dl_slice_idx[UE_id] = 0; - UE_list->assoc_ul_slice_idx[UE_id] = 0; - UE_list->UE_sched_ctrl[UE_id].ta_update = 31; + UE_info->UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 0; + UE_info->UE_sched_ctrl[UE_id].ta_update = 31; for (j = 0; j < 8; j++) { - UE_list->UE_template[cc_idP][UE_id].oldNDI[j] = 0; - UE_list->UE_template[cc_idP][UE_id].oldNDI_UL[j] = 0; - UE_list->UE_sched_ctrl[UE_id].round[cc_idP][j] = 8; - UE_list->UE_sched_ctrl[UE_id].round_UL[cc_idP][j] = 0; + UE_info->UE_template[cc_idP][UE_id].oldNDI[j] = 0; + UE_info->UE_template[cc_idP][UE_id].oldNDI_UL[j] = 0; + UE_info->UE_sched_ctrl[UE_id].round[cc_idP][j] = 8; + UE_info->UE_sched_ctrl[UE_id].round_UL[cc_idP][j] = 0; } eNB_ulsch_info[mod_idP][cc_idP][UE_id].status = S_UL_WAITING; @@ -2211,15 +2222,11 @@ add_new_ue(module_id_t mod_idP, UE_id, cc_idP, rntiP); - dump_ue_list(UE_list, - 0); return (UE_id); } - // printf("MAC: cannot add new UE for rnti %x\n", rntiP); LOG_E(MAC, "error in add_new_ue(), could not find space in UE_list, Dumping UE list\n"); - dump_ue_list(UE_list, - 0); + dump_ue_list(&UE_info->list); return -1; } @@ -2232,7 +2239,7 @@ rrc_mac_remove_ue(module_id_t mod_idP, rnti_t rntiP) //------------------------------------------------------------------------------ { - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; int UE_id = find_UE_id(mod_idP, rntiP); eNB_UE_STATS *ue_stats = NULL; int pCC_id = -1; @@ -2248,37 +2255,14 @@ rrc_mac_remove_ue(module_id_t mod_idP, UE_id, pCC_id, rntiP); - dump_ue_list(UE_list, 0); // DL list displayed in LOG_T(MAC) - UE_list->active[UE_id] = FALSE; - UE_list->num_UEs--; + UE_info->active[UE_id] = FALSE; + UE_info->num_UEs--; - /* If present, remove UE from DL list */ - if (UE_list->head == UE_id) { - UE_list->head = UE_list->next[UE_id]; - } else { - int previous = prev(UE_list, UE_id, 0); - - if (previous != -1) { - UE_list->next[previous] = UE_list->next[UE_id]; - } - } - - /* If present, remove UE from UL list */ - if (UE_list->head_ul == UE_id) { - UE_list->head_ul = UE_list->next_ul[UE_id]; - } else { - int previous = prev(UE_list, UE_id, 1); - - if (previous != -1) { - UE_list->next_ul[previous] = UE_list->next_ul[UE_id]; - } - } + remove_ue_list(&UE_info->list, UE_id); /* Clear all remaining pending transmissions */ - memset(&UE_list->UE_template[pCC_id][UE_id], - 0, - sizeof(UE_TEMPLATE)); - ue_stats = &UE_list->eNB_UE_stats[pCC_id][UE_id]; + memset(&UE_info->UE_template[pCC_id][UE_id], 0, sizeof(UE_TEMPLATE)); + ue_stats = &UE_info->eNB_UE_stats[pCC_id][UE_id]; ue_stats->total_rbs_used = 0; ue_stats->total_rbs_used_retx = 0; @@ -2355,166 +2339,19 @@ rrc_mac_remove_ue(module_id_t mod_idP, /* * Returns the previous UE_id in the scheduling list in UL or DL */ -int -prev(UE_list_t *listP, - int nodeP, - int ul_flag) -//------------------------------------------------------------------------------ -{ - if (ul_flag == 0) { - if (nodeP == listP->head) { - return nodeP; - } +inline int prev(UE_list_t *listP, int nodeP) { + if (nodeP == listP->head) + return -1; /* there is no previous of the head */ - for (int j = listP->head; j >= 0; j = listP->next[j]) { - if (listP->next[j] == nodeP) { - return j; - } - } - } else { - if (nodeP == listP->head_ul) { - return nodeP; - } + for (int j = listP->head; j >= 0; j = listP->next[j]) + if (listP->next[j] == nodeP) + return j; - for (int j = listP->head_ul; j >= 0; j = listP->next_ul[j]) { - if (listP->next_ul[j] == nodeP) { - return j; - } - } - } - - LOG_E(MAC, "error in prev(), could not find previous to %d in UE_list %s, should never happen, Dumping UE list\n", - nodeP, - (ul_flag == 0) ? "DL" : "UL"); - dump_ue_list(listP, - ul_flag); + LOG_E(MAC, "%s(): could not find previous to %d in UE_list\n", __func__, nodeP); + dump_ue_list(listP); return -1; } -//------------------------------------------------------------------------------ -void -swap_UEs(UE_list_t *listP, - int nodeiP, - int nodejP, - int ul_flag) -//------------------------------------------------------------------------------ -{ - int prev_i, prev_j, next_i, next_j; - LOG_T(MAC, "Swapping UE %d,%d\n", - nodeiP, - nodejP); - dump_ue_list(listP, - ul_flag); - prev_i = prev(listP, - nodeiP, - ul_flag); - prev_j = prev(listP, - nodejP, - ul_flag); - AssertFatal((prev_i >= 0) && (prev_j >= 0), "swap_UEs: problem"); - - if (ul_flag == 0) { - next_i = listP->next[nodeiP]; - next_j = listP->next[nodejP]; - } else { - next_i = listP->next_ul[nodeiP]; - next_j = listP->next_ul[nodejP]; - } - - LOG_T(MAC, "[%s] next_i %d, next_i, next_j %d, head %d \n", - (ul_flag == 0) ? "DL" : "UL", - next_i, - next_j, - listP->head); - - if (ul_flag == 0) { - if (next_i == nodejP) { // case ... p(i) i j n(j) ... => ... p(j) j i n(i) ... - LOG_T(MAC, "Case ... p(i) i j n(j) ... => ... p(j) j i n(i) ...\n"); - listP->next[nodeiP] = next_j; - listP->next[nodejP] = nodeiP; - - if (nodeiP == listP->head) { // case i j n(j) - listP->head = nodejP; - } else { - listP->next[prev_i] = nodejP; - } - } else if (next_j == nodeiP) { // case ... p(j) j i n(i) ... => ... p(i) i j n(j) ... - LOG_T(MAC, "Case ... p(j) j i n(i) ... => ... p(i) i j n(j) ...\n"); - listP->next[nodejP] = next_i; - listP->next[nodeiP] = nodejP; - - if (nodejP == listP->head) { // case j i n(i) - listP->head = nodeiP; - } else { - listP->next[prev_j] = nodeiP; - } - } else { // case ... p(i) i n(i) ... p(j) j n(j) ... - listP->next[nodejP] = next_i; - listP->next[nodeiP] = next_j; - - if (nodeiP == listP->head) { - LOG_T(MAC, "changing head to %d\n", - nodejP); - listP->head = nodejP; - listP->next[prev_j] = nodeiP; - } else if (nodejP == listP->head) { - LOG_D(MAC, "changing head to %d\n", - nodeiP); - listP->head = nodeiP; - listP->next[prev_i] = nodejP; - } else { - listP->next[prev_i] = nodejP; - listP->next[prev_j] = nodeiP; - } - } - } else { // ul_flag - if (next_i == nodejP) { // case ... p(i) i j n(j) ... => ... p(j) j i n(i) ... - LOG_T(MAC, "[UL] Case ... p(i) i j n(j) ... => ... p(j) j i n(i) ...\n"); - listP->next_ul[nodeiP] = next_j; - listP->next_ul[nodejP] = nodeiP; - - if (nodeiP == listP->head_ul) { // case i j n(j) - listP->head_ul = nodejP; - } else { - listP->next_ul[prev_i] = nodejP; - } - } else if (next_j == nodeiP) { // case ... p(j) j i n(i) ... => ... p(i) i j n(j) ... - LOG_T(MAC, "[UL]Case ... p(j) j i n(i) ... => ... p(i) i j n(j) ...\n"); - listP->next_ul[nodejP] = next_i; - listP->next_ul[nodeiP] = nodejP; - - if (nodejP == listP->head_ul) { // case j i n(i) - listP->head_ul = nodeiP; - } else { - listP->next_ul[prev_j] = nodeiP; - } - } else { // case ... p(i) i n(i) ... p(j) j n(j) ... - listP->next_ul[nodejP] = next_i; - listP->next_ul[nodeiP] = next_j; - - if (nodeiP == listP->head_ul) { - LOG_T(MAC, "[UL]changing head to %d\n", - nodejP); - listP->head_ul = nodejP; - listP->next_ul[prev_j] = nodeiP; - } else if (nodejP == listP->head_ul) { - LOG_T(MAC, "[UL]changing head to %d\n", - nodeiP); - listP->head_ul = nodeiP; - listP->next_ul[prev_i] = nodejP; - } else { - listP->next_ul[prev_i] = nodejP; - listP->next_ul[prev_j] = nodeiP; - } - } - } - - LOG_T(MAC, "After swap\n"); - dump_ue_list(listP, - ul_flag); - return; -} - // This has to be updated to include BSR information //------------------------------------------------------------------------------ uint8_t @@ -2523,8 +2360,8 @@ UE_is_to_be_scheduled(module_id_t module_idP, uint8_t UE_id) //------------------------------------------------------------------------------ { - UE_TEMPLATE *UE_template = &RC.mac[module_idP]->UE_list.UE_template[CC_id][UE_id]; - UE_sched_ctrl_t *UE_sched_ctl = &RC.mac[module_idP]->UE_list.UE_sched_ctrl[UE_id]; + UE_TEMPLATE *UE_template = &RC.mac[module_idP]->UE_info.UE_template[CC_id][UE_id]; + UE_sched_ctrl_t *UE_sched_ctl = &RC.mac[module_idP]->UE_info.UE_sched_ctrl[UE_id]; int rrc_status; // do not schedule UE if UL is not working @@ -2566,7 +2403,7 @@ get_tmode(module_id_t module_idP, { eNB_MAC_INST *eNB = RC.mac[module_idP]; COMMON_channels_t *cc = &eNB->common_channels[CC_idP]; - struct LTE_PhysicalConfigDedicated *physicalConfigDedicated = eNB->UE_list.UE_template[CC_idP][UE_idP].physicalConfigDedicated; + struct LTE_PhysicalConfigDedicated *physicalConfigDedicated = eNB->UE_info.UE_template[CC_idP][UE_idP].physicalConfigDedicated; if (physicalConfigDedicated == NULL) { // RRCConnectionSetup not received by UE yet AssertFatal(cc->p_eNB <= 2, "p_eNB is %d, should be <2\n", @@ -2776,19 +2613,21 @@ get_min_rb_unit(module_id_t module_id, int N_RB_DL = to_prb(RC.mac[module_id]->common_channels[CC_id].mib->message.dl_Bandwidth); switch (N_RB_DL) { - case 6: // 1.4 MHz + case 6: // 1.4MHz min_rb_unit = 1; break; - case 25: // 5HMz + case 15: // 3MHz + case 25: // 5MHz min_rb_unit = 2; break; - case 50: // 10HMz + case 50: // 10MHz min_rb_unit = 3; break; - case 100: // 20HMz + case 75: // 15MHz + case 100: // 20MHz min_rb_unit = 4; break; @@ -2809,7 +2648,7 @@ uint32_t allocate_prbs_sub(int nb_rb, int N_RB_DL, int N_RBG, - uint8_t *rballoc) + const uint8_t *rballoc) //------------------------------------------------------------------------------ { int check = 0; //check1=0,check2=0; @@ -3482,7 +3321,7 @@ try_again: if (fCCE == -1) { if (DL_req->number_pdcch_ofdm_symbols == max_symbol) { - LOG_I(MAC, "subframe %d: Dropping Allocation for RNTI %x\n", + LOG_D(MAC, "subframe %d: Dropping Allocation for RNTI %x\n", subframeP, dl_config_pduLoop->dci_dl_pdu.dci_dl_pdu_rel8.rnti); @@ -3671,6 +3510,121 @@ CCE_allocation_infeasible(int module_idP, return res; } +int CCE_try_allocate_dlsch(int module_id, + int CC_id, + int subframe, + int UE_id, + uint8_t dl_cqi) { + const rnti_t rnti = RC.mac[module_id]->UE_info.UE_template[CC_id][UE_id].rnti; + nfapi_dl_config_request_body_t *DL_req = &RC.mac[module_id]->DL_req[CC_id].dl_config_request_body; + + if (DL_req->number_pdu >= MAX_NUM_DL_PDU) { + LOG_W(MAC, "Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", subframe, rnti); + return -1; + } + + int aggregation = 2; + const uint8_t tm = get_tmode(module_id, CC_id, UE_id); + switch (tm) { + case 1: + case 2: + case 7: + aggregation = get_aggregation(get_bw_index(module_id, CC_id), + dl_cqi, + format1); + break; + + case 3: + aggregation = get_aggregation(get_bw_index(module_id, CC_id), + dl_cqi, + format2A); + break; + + default: + AssertFatal(0, "Unsupported transmission mode %d\n", tm); + break; + } + + nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu]; + memset(dl_config_pdu, 0, sizeof(nfapi_dl_config_request_pdu_t)); + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; + dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; + DL_req->number_pdu++; + LOG_D(MAC, "Subframe %d: Checking CCE feasibility format 1: (%x,%d) \n", + subframe, rnti, aggregation); + + if (allocate_CCEs(module_id, CC_id, 0, subframe, 0) < 0) { + DL_req->number_pdu--; + return -1; + } + + DL_req->number_dci++; + nfapi_dl_config_request_pdu_t *dl_dlsch_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu]; + dl_dlsch_pdu->pdu_type = NFAPI_DL_CONFIG_DLSCH_PDU_TYPE; + dl_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DLSCH_PDU_REL8_TAG; + dl_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti = rnti; + DL_req->number_pdu++; + + return DL_req->number_pdu - 2; +} + +int CCE_try_allocate_ulsch(int module_id, + int CC_id, + int subframe, + int UE_id, + uint8_t dl_cqi) { + const rnti_t rnti = RC.mac[module_id]->UE_info.UE_template[CC_id][UE_id].rnti; + nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_id]->HI_DCI0_req[CC_id][subframe].hi_dci0_request_body; + + if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi >= MAX_NUM_HI_DCI0_PDU) { + LOG_W(MAC, "Subframe %d: FAPI UL structure is full, skip scheduling UE %d\n", subframe, rnti); + return -1; + } + + int aggregation = 2; + const uint8_t tm = get_tmode(module_id, CC_id, UE_id); + switch (tm) { + case 1: + case 2: + case 7: + aggregation = get_aggregation(get_bw_index(module_id, CC_id), + dl_cqi, + format1); + break; + + case 3: + aggregation = get_aggregation(get_bw_index(module_id, CC_id), + dl_cqi, + format2A); + break; + + default: + AssertFatal(0, "Unsupported transmission mode %d\n", tm); + break; + } + + const int idx = HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi; + nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[idx]; + memset(hi_dci0_pdu, 0, sizeof(nfapi_hi_dci0_request_pdu_t)); + hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_DCI_PDU_REL8_TAG; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; + HI_DCI0_req->number_of_dci++; + LOG_D(MAC, "%s() sf %d: Checking CCE feasibility format 2: RNTI %04x, agg %d\n", + __func__, subframe, rnti, aggregation); + + if (allocate_CCEs(module_id, CC_id, 0, subframe, 0) < 0) { + HI_DCI0_req->number_of_dci--; + return -1; + } + + return idx; +} + //------------------------------------------------------------------------------ void get_retransmission_timing(LTE_TDD_Config_t *tdd_Config, @@ -3931,15 +3885,15 @@ extract_harq(module_id_t mod_idP, //------------------------------------------------------------------------------ { eNB_MAC_INST *eNB = RC.mac[mod_idP]; - UE_list_t *UE_list = &eNB->UE_list; - UE_sched_ctrl_t *sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_info_t *UE_info = &eNB->UE_info; + UE_sched_ctrl_t *sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; rnti_t rnti = UE_RNTI(mod_idP, UE_id); COMMON_channels_t *cc = &eNB->common_channels[CC_idP]; nfapi_harq_indication_fdd_rel13_t *harq_indication_fdd; nfapi_harq_indication_tdd_rel13_t *harq_indication_tdd; uint16_t num_ack_nak; - int numCC = UE_list->numactiveCCs[UE_id]; - int pCCid = UE_list->pCC_id[UE_id]; + int numCC = UE_info->numactiveCCs[UE_id]; + int pCCid = UE_info->pCC_id[UE_id]; int spatial_bundling = 0; int tmode[5]; int i, j, m; @@ -3947,7 +3901,7 @@ extract_harq(module_id_t mod_idP, sub_frame_t subframe_tx; int frame_tx; uint8_t harq_pid; - LTE_PhysicalConfigDedicated_t *physicalConfigDedicated = UE_list->UE_template[pCCid][UE_id].physicalConfigDedicated; + LTE_PhysicalConfigDedicated_t *physicalConfigDedicated = UE_info->UE_template[pCCid][UE_id].physicalConfigDedicated; if (physicalConfigDedicated != NULL && physicalConfigDedicated->pucch_ConfigDedicated != NULL && physicalConfigDedicated->ext7 != NULL && physicalConfigDedicated->ext7->pucch_ConfigDedicated_r13 != NULL && @@ -4081,7 +4035,7 @@ extract_harq(module_id_t mod_idP, sched_ctl->round[CC_idP][harq_pid]); // use 1 HARQ proces of BL/CE UE for now - if (UE_list->UE_template[pCCid][UE_id].rach_resource_type > 0) harq_pid = 0; + if (UE_info->UE_template[pCCid][UE_id].rach_resource_type > 0) harq_pid = 0; switch (harq_indication_fdd->mode) { case 0: // Format 1a/b (10.1.2.1) @@ -4567,18 +4521,18 @@ extract_pucch_csi(module_id_t mod_idP, uint8_t length) //------------------------------------------------------------------------------ { - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; - UE_sched_ctrl_t *sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; + UE_sched_ctrl_t *sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; COMMON_channels_t *cc = &RC.mac[mod_idP]->common_channels[CC_idP]; int no_pmi; uint8_t Ltab[6] = { 0, 2, 4, 4, 4, 4 }; uint8_t Jtab[6] = { 0, 2, 2, 3, 4, 4 }; int feedback_cnt; - AssertFatal(UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated != NULL, "physicalConfigDedicated is null for UE %d\n", + AssertFatal(UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated != NULL, "physicalConfigDedicated is null for UE %d\n", UE_id); - AssertFatal(UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig != NULL, "cqi_ReportConfig is null for UE %d\n", + AssertFatal(UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig != NULL, "cqi_ReportConfig is null for UE %d\n", UE_id); - struct LTE_CQI_ReportPeriodic *cqi_ReportPeriodic = UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig->cqi_ReportPeriodic; + struct LTE_CQI_ReportPeriodic *cqi_ReportPeriodic = UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig->cqi_ReportPeriodic; AssertFatal(cqi_ReportPeriodic != NULL, "cqi_ReportPeriodic is null for UE %d\n", UE_id); // determine feedback mode @@ -4678,9 +4632,9 @@ extract_pusch_csi(module_id_t mod_idP, uint8_t length) //------------------------------------------------------------------------------ { - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; COMMON_channels_t *cc = &RC.mac[mod_idP]->common_channels[CC_idP]; - UE_sched_ctrl_t *sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_sched_ctrl_t *sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; int Ntab[6] = { 0, 4, 7, 9, 10, 13 }; int Ntab_uesel[6] = { 0, 8, 13, 17, 19, 25 }; int Ltab_uesel[6] = { 0, 6, 9, 13, 15, 18 }; @@ -4689,12 +4643,12 @@ extract_pusch_csi(module_id_t mod_idP, int i; uint64_t p = *(uint64_t *) pdu; int curbyte, curbit; - AssertFatal(UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated != NULL, "physicalConfigDedicated is null for UE %d\n", + AssertFatal(UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated != NULL, "physicalConfigDedicated is null for UE %d\n", UE_id); - AssertFatal(UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig != NULL, "cqi_ReportConfig is null for UE %d\n", + AssertFatal(UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig != NULL, "cqi_ReportConfig is null for UE %d\n", UE_id); LTE_CQI_ReportModeAperiodic_t *cqi_ReportModeAperiodic - = UE_list->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig->cqi_ReportModeAperiodic; + = UE_info->UE_template[CC_idP][UE_id].physicalConfigDedicated->cqi_ReportConfig->cqi_ReportModeAperiodic; AssertFatal(cqi_ReportModeAperiodic != NULL, "cqi_ReportModeAperiodic is null for UE %d\n", UE_id); int N = Ntab[cc->mib->message.dl_Bandwidth]; @@ -4964,14 +4918,14 @@ cqi_indication(module_id_t mod_idP, //------------------------------------------------------------------------------ { int UE_id = find_UE_id(mod_idP, rntiP); - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; if (UE_id == -1) { LOG_W(MAC, "cqi_indication: UE %x not found\n", rntiP); return; } - UE_sched_ctrl_t *sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_sched_ctrl_t *sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; if (UE_id >= 0) { LOG_D(MAC,"%s() UE_id:%d channel:%d cqi:%d\n", @@ -5037,11 +4991,11 @@ SR_indication(module_id_t mod_idP, T_INT(subframeP), T_INT(rntiP)); int UE_id = find_UE_id(mod_idP, rntiP); - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; UE_sched_ctrl_t *UE_scheduling_ctrl = NULL; if (UE_id != -1) { - UE_scheduling_ctrl = &(UE_list->UE_sched_ctrl[UE_id]); + UE_scheduling_ctrl = &(UE_info->UE_sched_ctrl[UE_id]); if ((UE_scheduling_ctrl->cdrx_configured == TRUE) && (UE_scheduling_ctrl->dci0_ongoing_timer > 0) && @@ -5065,8 +5019,8 @@ SR_indication(module_id_t mod_idP, cc_idP); } - UE_list->UE_template[cc_idP][UE_id].ul_SR = 1; - UE_list->UE_template[cc_idP][UE_id].ul_active = TRUE; + UE_info->UE_template[cc_idP][UE_id].ul_SR = 1; + UE_info->UE_template[cc_idP][UE_id].ul_active = TRUE; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_SR_INDICATION, 1); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_SR_INDICATION, 0); } @@ -5093,7 +5047,7 @@ UL_failure_indication(module_id_t mod_idP, //------------------------------------------------------------------------------ { int UE_id = find_UE_id(mod_idP, rntiP); - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; if (UE_id != -1) { LOG_D(MAC, "[eNB %d][UE %d/%x] Frame %d subframeP %d Signaling UL Failure for UE %d on CC_id %d (timer %d)\n", @@ -5104,9 +5058,9 @@ UL_failure_indication(module_id_t mod_idP, subframeP, UE_id, cc_idP, - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer); + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer); - if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer == 0) UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 1; + if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer == 0) UE_info->UE_sched_ctrl[UE_id].ul_failure_timer = 1; } else { // AssertFatal(0, "find_UE_id(%u,rnti %d) not found", enb_mod_idP, rntiP); // AssertError(0, 0, "Frame %d: find_UE_id(%u,rnti %d) not found\n", frameP, enb_mod_idP, rntiP); @@ -5169,8 +5123,8 @@ harq_indication(module_id_t mod_idP, return; } - UE_list_t *UE_list = &RC.mac[mod_idP]->UE_list; - UE_sched_ctrl_t *sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + UE_info_t *UE_info = &RC.mac[mod_idP]->UE_info; + UE_sched_ctrl_t *sched_ctl = &UE_info->UE_sched_ctrl[UE_id]; COMMON_channels_t *cc = &RC.mac[mod_idP]->common_channels[CC_idP]; // extract HARQ Information @@ -5201,51 +5155,3 @@ harq_indication(module_id_t mod_idP, return; } - -// Flexran Slicing functions -//------------------------------------------------------------------------------ -uint16_t -nb_rbs_allowed_slice(float rb_percentage, - int total_rbs) -//------------------------------------------------------------------------------ -{ - return (uint16_t) floor(rb_percentage * total_rbs); -} - -//------------------------------------------------------------------------------ -int -ue_dl_slice_membership(module_id_t mod_id, - int UE_id, - int slice_idx) -//------------------------------------------------------------------------------ -{ - eNB_MAC_INST *eNB = RC.mac[mod_id]; - - if (slice_idx < 0 || slice_idx >= eNB->slice_info.n_dl) { - LOG_W(MAC, "out of range slice index %d (slice ID %d)\n", - slice_idx, - eNB->slice_info.dl[slice_idx].id); - return 0; - } - - return eNB->UE_list.active[UE_id] == TRUE && eNB->UE_list.assoc_dl_slice_idx[UE_id] == slice_idx; -} - -//------------------------------------------------------------------------------ -int -ue_ul_slice_membership(module_id_t mod_id, - int UE_id, - int slice_idx) -//------------------------------------------------------------------------------ -{ - eNB_MAC_INST *eNB = RC.mac[mod_id]; - - if (slice_idx < 0 || slice_idx >= eNB->slice_info.n_ul) { - LOG_W(MAC, "out of range slice index %d (slice ID %d)\n", - slice_idx, - eNB->slice_info.dl[slice_idx].id); - return 0; - } - - return eNB->UE_list.active[UE_id] == TRUE && eNB->UE_list.assoc_ul_slice_idx[UE_id] == slice_idx; -} diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 7c3b536de2..3062e5c964 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -123,17 +123,15 @@ rx_sdu(const module_id_t enb_mod_idP, unsigned short rx_lengths[NB_RB_MAX]; uint8_t lcgid = 0; int lcgid_updated[4] = {0, 0, 0, 0}; - eNB_MAC_INST *mac = NULL; - UE_list_t *UE_list = NULL; + eNB_MAC_INST *mac = RC.mac[enb_mod_idP]; + UE_info_t *UE_info = &mac->UE_info; rrc_eNB_ue_context_t *ue_contextP = NULL; UE_sched_ctrl_t *UE_scheduling_control = NULL; UE_TEMPLATE *UE_template_ptr = NULL; /* Init */ current_rnti = rntiP; UE_id = find_UE_id(enb_mod_idP, current_rnti); - mac = RC.mac[enb_mod_idP]; harq_pid = subframe2harqpid(&mac->common_channels[CC_idP], frameP, subframeP); - UE_list = &mac->UE_list; memset(rx_ces, 0, MAX_NUM_CE * sizeof(unsigned char)); memset(rx_lcids, 0, NB_RB_MAX * sizeof(unsigned char)); memset(rx_lengths, 0, NB_RB_MAX * sizeof(unsigned short)); @@ -142,8 +140,8 @@ rx_sdu(const module_id_t enb_mod_idP, trace_pdu(DIRECTION_UPLINK, sduP, sdu_lenP, 0, WS_C_RNTI, current_rnti, frameP, subframeP, 0, 0); if (UE_id != -1) { - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); - UE_template_ptr = &(UE_list->UE_template[CC_idP][UE_id]); + UE_scheduling_control = &UE_info->UE_sched_ctrl[UE_id]; + UE_template_ptr = &UE_info->UE_template[CC_idP][UE_id]; LOG_D(MAC, "[eNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu round %d from PHY (rnti %x, UE_id %d) ul_cqi %d\n", enb_mod_idP, harq_pid, @@ -182,7 +180,7 @@ rx_sdu(const module_id_t enb_mod_idP, UE_template_ptr->scheduled_ul_bytes = 0; } } else { // sduP == NULL => error - LOG_W(MAC, "[eNB %d][PUSCH %d] CC_id %d %d.%d ULSCH in error in round %d, ul_cqi %d, UE_id %d, RNTI %x\n", + LOG_W(MAC, "[eNB %d][PUSCH %d] CC_id %d %d.%d ULSCH in error in round %d, ul_cqi %d, UE_id %d, RNTI %x (len %d)\n", enb_mod_idP, harq_pid, CC_idP, @@ -191,7 +189,8 @@ rx_sdu(const module_id_t enb_mod_idP, UE_scheduling_control->round_UL[CC_idP][harq_pid], ul_cqi, UE_id, - current_rnti); + current_rnti, + sdu_lenP); if (ul_cqi > 200) { // too high energy pattern UE_scheduling_control->pusch_snr[CC_idP] = ul_cqi; @@ -413,8 +412,8 @@ rx_sdu(const module_id_t enb_mod_idP, UE_id = old_UE_id; current_rnti = old_rnti; /* Clear timer */ - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); - UE_template_ptr = &(UE_list->UE_template[CC_idP][UE_id]); + UE_scheduling_control = &UE_info->UE_sched_ctrl[UE_id]; + UE_template_ptr = &UE_info->UE_template[CC_idP][UE_id]; UE_scheduling_control->uplane_inactivity_timer = 0; UE_scheduling_control->ul_inactivity_timer = 0; UE_scheduling_control->ul_failure_timer = 0; @@ -430,7 +429,7 @@ rx_sdu(const module_id_t enb_mod_idP, UE_template_ptr->ul_SR = 1; UE_scheduling_control->crnti_reconfigurationcomplete_flag = 1; - UE_list->UE_template[UE_PCCID(enb_mod_idP, UE_id)][UE_id].configured = 1; + UE_info->UE_template[UE_PCCID(enb_mod_idP, UE_id)][UE_id].configured = 1; cancel_ra_proc(enb_mod_idP, CC_idP, frameP, @@ -480,8 +479,8 @@ rx_sdu(const module_id_t enb_mod_idP, ra->crnti_rrc_mui = rrc_eNB_mui-1; ra->crnti_harq_pid = -1; /* Clear timer */ - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); - UE_template_ptr = &(UE_list->UE_template[CC_idP][UE_id]); + UE_scheduling_control = &UE_info->UE_sched_ctrl[UE_id]; + UE_template_ptr = &UE_info->UE_template[CC_idP][UE_id]; UE_scheduling_control->uplane_inactivity_timer = 0; UE_scheduling_control->ul_inactivity_timer = 0; UE_scheduling_control->ul_failure_timer = 0; @@ -532,7 +531,7 @@ rx_sdu(const module_id_t enb_mod_idP, UE_template_ptr->ul_buffer_info[LCGID3]; RC.eNB[enb_mod_idP][CC_idP]->pusch_stats_bsr[UE_id][(frameP * 10) + subframeP] = (payload_ptr[0] & 0x3f); - if (UE_id == UE_list->head) { + if (UE_id == UE_info->list.head) { VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_BSR, (payload_ptr[0] & 0x3f)); } @@ -689,8 +688,8 @@ rx_sdu(const module_id_t enb_mod_idP, frameP, ra->rnti, UE_id); - UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); - UE_template_ptr = &(UE_list->UE_template[CC_idP][UE_id]); + UE_scheduling_control = &UE_info->UE_sched_ctrl[UE_id]; + UE_template_ptr = &UE_info->UE_template[CC_idP][UE_id]; } } else { LOG_D(MAC, "[eNB %d][RAPROC] CC_id %d Frame %d CCCH: Received Msg3 from already registered UE %d: length %d, offset %ld\n", @@ -779,11 +778,11 @@ rx_sdu(const module_id_t enb_mod_idP, enb_mod_idP, CC_idP, frameP, rx_lengths[i], UE_id, rx_lcids[i]); mac_rlc_data_ind(enb_mod_idP, current_rnti, enb_mod_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_NO, rx_lcids[i], (char *) payload_ptr, rx_lengths[i], 1, NULL); //(unsigned int*)crc_status); - UE_list->eNB_UE_stats[CC_idP][UE_id].num_pdu_rx[rx_lcids[i]] += 1; - UE_list->eNB_UE_stats[CC_idP][UE_id].num_bytes_rx[rx_lcids[i]] += rx_lengths[i]; + UE_info->eNB_UE_stats[CC_idP][UE_id].num_pdu_rx[rx_lcids[i]] += 1; + UE_info->eNB_UE_stats[CC_idP][UE_id].num_bytes_rx[rx_lcids[i]] += rx_lengths[i]; if (mac_eNB_get_rrc_status(enb_mod_idP, current_rnti) < RRC_RECONFIGURED) { - UE_list->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; + UE_info->UE_sched_ctrl[UE_id].uplane_inactivity_timer = 0; } } @@ -840,8 +839,8 @@ rx_sdu(const module_id_t enb_mod_idP, if ((rx_lengths[i] < SCH_PAYLOAD_SIZE_MAX) && (rx_lengths[i] > 0)) { // MAX SIZE OF transport block mac_rlc_data_ind(enb_mod_idP, current_rnti, enb_mod_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_NO, rx_lcids[i], (char *) payload_ptr, rx_lengths[i], 1, NULL); - UE_list->eNB_UE_stats[CC_idP][UE_id].num_pdu_rx[rx_lcids[i]] += 1; - UE_list->eNB_UE_stats[CC_idP][UE_id].num_bytes_rx[rx_lcids[i]] += rx_lengths[i]; + UE_info->eNB_UE_stats[CC_idP][UE_id].num_pdu_rx[rx_lcids[i]] += 1; + UE_info->eNB_UE_stats[CC_idP][UE_id].num_bytes_rx[rx_lcids[i]] += rx_lengths[i]; /* Clear uplane_inactivity_timer */ UE_scheduling_control->uplane_inactivity_timer = 0; /* Reset RRC inactivity timer after uplane activity */ @@ -856,7 +855,7 @@ rx_sdu(const module_id_t enb_mod_idP, current_rnti); } } else { /* rx_length[i] Max size */ - UE_list->eNB_UE_stats[CC_idP][UE_id].num_errors_rx += 1; + UE_info->eNB_UE_stats[CC_idP][UE_id].num_errors_rx += 1; LOG_E(MAC, "[eNB %d] CC_id %d Frame %d : Max size of transport block reached LCID %d from UE %d ", enb_mod_idP, CC_idP, @@ -921,12 +920,12 @@ rx_sdu(const module_id_t enb_mod_idP, /* NN--> FK: we could either check the payload, or use a phy helper to detect a false msg3 */ if ((num_sdu == 0) && (num_ce == 0)) { if (UE_id != -1) - UE_list->eNB_UE_stats[CC_idP][UE_id].total_num_errors_rx += 1; + UE_info->eNB_UE_stats[CC_idP][UE_id].total_num_errors_rx += 1; } else { if (UE_id != -1) { - UE_list->eNB_UE_stats[CC_idP][UE_id].pdu_bytes_rx = sdu_lenP; - UE_list->eNB_UE_stats[CC_idP][UE_id].total_pdu_bytes_rx += sdu_lenP; - UE_list->eNB_UE_stats[CC_idP][UE_id].total_num_pdus_rx += 1; + UE_info->eNB_UE_stats[CC_idP][UE_id].pdu_bytes_rx = sdu_lenP; + UE_info->eNB_UE_stats[CC_idP][UE_id].total_pdu_bytes_rx += sdu_lenP; + UE_info->eNB_UE_stats[CC_idP][UE_id].total_num_pdus_rx += 1; } } @@ -1101,16 +1100,12 @@ schedule_ulsch(module_id_t module_idP, sub_frame_t subframeP) //----------------------------------------------------------------------------- { - uint16_t first_rb[NFAPI_CC_MAX]; eNB_MAC_INST *mac = NULL; - slice_info_t *sli = NULL; COMMON_channels_t *cc = NULL; int sched_subframe; int sched_frame; /* Init */ mac = RC.mac[module_idP]; - sli = &(mac->slice_info); - memset(first_rb, 0, NFAPI_CC_MAX * sizeof(uint16_t)); start_meas(&(mac->schedule_ulsch)); sched_subframe = (subframeP + 4) % 10; sched_frame = frameP; @@ -1217,60 +1212,53 @@ schedule_ulsch(module_id_t module_idP, /* Note: RC.nb_mac_CC[module_idP] should be lower than or equal to NFAPI_CC_MAX */ for (int CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++, cc++) { - first_rb[CC_id] = (emtc_active[CC_id] == 1) ? 7 : 1; - RA_t *ra_ptr = cc->ra; - - /* From Louis-Adrien to François: - * The comment bloc below is to configure with a command line. - * I took it from the equivalent part in the fairRR scheduler (around line 2578 in eNB_scheduler_fairRR.c). - * As said in the meeting, it seems to work only for small TBS. - * The cause of false RA still present with this fix is to investigate. - * - * Note: in the get_prach_prb_offset() function below, the last argument is frameP in eNB_scheduler_fairRR.c - * I think it should be sched_frame instead. This parameter has only impacts in case TDD and preamble format 4. - * To confirm. - */ - /* - int start_rb = 0; - int nb_rb = 6; - LTE_DL_FRAME_PARMS *frame_parms = &(RC.eNB[module_idP][CC_id]->frame_parms); - - if (is_prach_subframe(frame_parms, sched_frame, sched_subframe) == 1) { - start_rb = get_prach_prb_offset(frame_parms, - frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset, - 0, // tdd_mapindex - sched_frame); // Nf - - first_rb[CC_id] = start_rb + nb_rb; + LTE_DL_FRAME_PARMS *frame_parms = &RC.eNB[module_idP][CC_id]->frame_parms; + if (is_prach_subframe(frame_parms, sched_frame, sched_subframe)) { + int start_rb = get_prach_prb_offset( + frame_parms, + frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset, + 0, // tdd_mapindex + sched_frame); // Nf + for (int i = 0; i < 6; i++) + cc[CC_id].vrb_map_UL[start_rb + i] = 1; } - */ - /* - * Check if RA (Msg3) is active in this subframeP, if so skip the PRB used for Msg3 - * Msg3 is using 1 PRB so we need to increase first_rb accordingly - * Not sure about the break (can there be more than 1 active RA procedure per CC_id and per subframe?) + /* HACK: let's remove the PUCCH from available RBs + * we suppose PUCCH size is: + * - for 25 RBs: 1 RB (top and bottom of ressource grid) + * - for 50: 2 RBs + * - for 100: 3 RBs + * This is totally arbitrary and might even be wrong. */ - for (int ra_index = 0; ra_index < NB_RA_PROC_MAX; ra_index++, ra_ptr++) { - if ((ra_ptr->state == WAITMSG3) && (ra_ptr->Msg3_subframe == sched_subframe)) { - if (first_rb[CC_id] < ra_ptr->msg3_first_rb + ra_ptr->msg3_nb_rb) { - first_rb[CC_id] = ra_ptr->msg3_first_rb + ra_ptr->msg3_nb_rb; - } + switch (to_prb(cc[CC_id].ul_Bandwidth)) { + case 25: + cc[CC_id].vrb_map_UL[0] = 1; + cc[CC_id].vrb_map_UL[24] = 1; + break; - /* Louis-Adrien: I couldn't find an interdiction of multiple Msg3 scheduling - * on the same time resources. Also the performance improvement of breaking is low, - * since we will loop until the end, most of the time. - * I'm letting the break as a reminder, in case of misunderstanding the spec. - */ - // break; - } + case 50: + cc[CC_id].vrb_map_UL[0] = 1; + cc[CC_id].vrb_map_UL[1] = 1; + cc[CC_id].vrb_map_UL[48] = 1; + cc[CC_id].vrb_map_UL[49] = 1; + break; + + case 100: + cc[CC_id].vrb_map_UL[0] = 1; + cc[CC_id].vrb_map_UL[1] = 1; + cc[CC_id].vrb_map_UL[2] = 1; + cc[CC_id].vrb_map_UL[97] = 1; + cc[CC_id].vrb_map_UL[98] = 1; + cc[CC_id].vrb_map_UL[99] = 1; + break; + + default: + LOG_E(MAC, "RBs setting not handled. Todo.\n"); + exit(1); } - } - /* Run each enabled slice-specific schedulers one by one */ - for (int i = 0; i < sli->n_ul; i++) { - /* By default the scheduler is schedule_ulsch_rnti (see below) */ - sli->ul[i].sched_cb(module_idP, i, frameP, subframeP, sched_subframe, first_rb); + schedule_ulsch_rnti(module_idP, CC_id, frameP, subframeP, sched_subframe); } stop_meas(&mac->schedule_ulsch); @@ -1282,48 +1270,20 @@ schedule_ulsch(module_id_t module_idP, */ void schedule_ulsch_rnti(module_id_t module_idP, - int slice_idx, + int CC_id, frame_t frameP, sub_frame_t subframeP, - unsigned char sched_subframeP, - uint16_t *first_rb) -//----------------------------------------------------------------------------- -{ - rnti_t rnti = -1; - uint8_t aggregation = 2; - uint8_t round_index = 0; - uint8_t harq_pid = 0; - uint8_t status = 0; - uint8_t rb_table_index = -1; - uint8_t dlsch_flag = 0; - uint16_t ul_req_index = 0; - uint32_t cqi_req = 0; - uint32_t cshift = 0; - uint32_t ndi = 0; - uint32_t tpc = 0; - int32_t snr = 0; - int32_t target_snr = 0; - int32_t framex10psubframe = 0; + unsigned char sched_subframeP) { + /* TODO: does this need to be static? */ static int32_t tpc_accumulated = 0; - int sched_frame = 0; - int CC_id = 0; - eNB_MAC_INST *mac = NULL; - COMMON_channels_t *cc = NULL; - UE_list_t *UE_list = NULL; - slice_info_t *sli = NULL; - UE_TEMPLATE *UE_template_ptr = NULL; - UE_sched_ctrl_t *UE_sched_ctrl_ptr = NULL; - int rvidx_tab[4] = {0, 2, 3, 1}; - int first_rb_slice[NFAPI_CC_MAX]; - int n_rb_ul_tab[NFAPI_CC_MAX]; - /* Init */ - mac = RC.mac[module_idP]; - cc = mac->common_channels; - UE_list = &(mac->UE_list); - sli = &(mac->slice_info); - memset(first_rb_slice, 0, NFAPI_CC_MAX * sizeof(int)); - memset(n_rb_ul_tab, 0, NFAPI_CC_MAX * sizeof(int)); - sched_frame = frameP; + /* values from 0 to 7 can be used for mapping the cyclic shift + * (36.211 , Table 5.5.2.1.1-1) */ + const uint32_t cshift = 0; + eNB_MAC_INST *mac = RC.mac[module_idP]; + COMMON_channels_t *cc = mac->common_channels; + UE_info_t *UE_info = &mac->UE_info; + + int sched_frame = frameP; if (sched_subframeP < subframeP) { sched_frame++; @@ -1339,63 +1299,23 @@ schedule_ulsch_rnti(module_id_t module_idP, nfapi_ul_config_ulsch_harq_information *ulsch_harq_information; hi_dci0_req->sfn_sf = (frameP << 4) + subframeP; - /* Note: RC.nb_mac_CC[module_idP] should be lower than or equal to NFAPI_CC_MAX */ - for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) { - n_rb_ul_tab[CC_id] = to_prb(cc[CC_id].ul_Bandwidth); // return total number of PRB - - /* HACK: let's remove the PUCCH from available RBs - * we suppose PUCCH size is: - * - for 25 RBs: 1 RB (top and bottom of ressource grid) - * - for 50: 2 RBs - * - for 100: 3 RBs - * This is totally arbitrary and might even be wrong. - * We suppose 'first_rb[]' has been correctly populated by the caller, - * so we only remove the top part of the resource grid. - */ - switch (n_rb_ul_tab[CC_id]) { - case 25: - n_rb_ul_tab[CC_id] -= 1; - break; - - case 50: - n_rb_ul_tab[CC_id] -= 2; - break; - - case 100: - n_rb_ul_tab[CC_id] -= 3; - break; - - default: - LOG_E(MAC, "RBs setting not handled. Todo.\n"); - exit(1); - } - - UE_list->first_rb_offset[CC_id][slice_idx] = cmin(n_rb_ul_tab[CC_id], sli->ul[slice_idx].first_rb); - } - /* * ULSCH preprocessor: set UE_template-> * pre_allocated_nb_rb_ul[slice_idx] * pre_assigned_mcs_ul * pre_allocated_rb_table_index_ul */ - ulsch_scheduler_pre_processor(module_idP, slice_idx, frameP, subframeP, sched_frame, sched_subframeP, first_rb); + ulsch_scheduler_pre_processor(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); - for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) { - first_rb_slice[CC_id] = first_rb[CC_id] + UE_list->first_rb_offset[CC_id][slice_idx]; - } - - // loop over all active UEs until end of function - for (int UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) { - if (!ue_ul_slice_membership(module_idP, UE_id, slice_idx)) { + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + if (UE_info->UE_template[CC_id][UE_id].rach_resource_type > 0) continue; - } - - if (UE_list->UE_template[UE_PCCID(module_idP, UE_id)][UE_id].rach_resource_type > 0) continue; // don't schedule if Msg5 is not received yet - if (UE_list->UE_template[UE_PCCID(module_idP, UE_id)][UE_id].configured == FALSE) { - LOG_D(MAC, "[eNB %d] frame %d, subframe %d, UE %d: not configured, skipping UE scheduling \n", + if (UE_info->UE_template[CC_id][UE_id].configured == FALSE) { + LOG_D(MAC, + "[eNB %d] frame %d, subframe %d, UE %d: not configured, skipping " + "UE scheduling \n", module_idP, frameP, subframeP, @@ -1403,10 +1323,11 @@ schedule_ulsch_rnti(module_id_t module_idP, continue; } - rnti = UE_RNTI(module_idP, UE_id); + const rnti_t rnti = UE_RNTI(module_idP, UE_id); if (rnti == NOT_A_RNTI) { - LOG_W(MAC, "[eNB %d] frame %d, subframe %d, UE %d: no RNTI \n", + LOG_W(MAC, + "[eNB %d] frame %d, subframe %d, UE %d: no RNTI \n", module_idP, frameP, subframeP, @@ -1414,485 +1335,509 @@ schedule_ulsch_rnti(module_id_t module_idP, continue; } - // loop over all active UL CC_ids for this UE until end of function - for (int n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { - /* This is the actual CC_id in the list */ - CC_id = UE_list->ordered_ULCCids[n][UE_id]; - UE_template_ptr = &(UE_list->UE_template[CC_id][UE_id]); - UE_sched_ctrl_ptr = &(UE_list->UE_sched_ctrl[UE_id]); - harq_pid = subframe2harqpid(&cc[CC_id], sched_frame, sched_subframeP); - round_index = UE_sched_ctrl_ptr->round_UL[CC_id][harq_pid]; - AssertFatal(round_index < 8, "round %d > 7 for UE %d/%x\n", - round_index, - UE_id, - rnti); - LOG_D(MAC, "[eNB %d] frame %d subframe %d (sched_frame %d, sched_subframe %d), Checking PUSCH %d for UE %d/%x CC %d : aggregation level %d, N_RB_UL %d\n", + UE_TEMPLATE *UE_template_ptr = &UE_info->UE_template[CC_id][UE_id]; + UE_sched_ctrl_t *UE_sched_ctrl_ptr = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t harq_pid = subframe2harqpid(&cc[CC_id], sched_frame, sched_subframeP); + uint8_t round_index = UE_sched_ctrl_ptr->round_UL[CC_id][harq_pid]; + AssertFatal(round_index < 8, + "round %d > 7 for UE %d/%x\n", + round_index, + UE_id, + rnti); + + /* Seems unused, only for debug */ + RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP * 10) + subframeP] = + UE_template_ptr->estimated_ul_buffer; + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO, + UE_template_ptr->estimated_ul_buffer); + + if (UE_template_ptr->pre_allocated_nb_rb_ul < 1) + continue; + + int dci_ul_pdu_idx = UE_template_ptr->pre_dci_ul_pdu_idx; + if (dci_ul_pdu_idx < 0) { + dci_ul_pdu_idx = CCE_try_allocate_ulsch( + module_idP, CC_id, subframeP, UE_id, UE_sched_ctrl_ptr->dl_cqi[CC_id]); + if (dci_ul_pdu_idx < 0) { + LOG_W(MAC ,"%4d.%d: Dropping UL Allocation for RNTI 0x%04x/UE %d\n", + frameP, subframeP, rnti, UE_id); + continue; + } + } + + /* verify it is the right UE */ + hi_dci0_pdu = &hi_dci0_req_body->hi_dci0_pdu_list[dci_ul_pdu_idx]; + if (hi_dci0_pdu->pdu_type != NFAPI_HI_DCI0_DCI_PDU_TYPE + || hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti != rnti) { + LOG_E(MAC, "illegal hi_dci0_pdu_list index %d for UE %d/RNTI %04x\n", + dci_ul_pdu_idx, + UE_id, + rnti); + continue; + } + + LOG_D(MAC, + "[eNB %d][PUSCH %d] %d.%d Scheduling UE %d/%x in " + "round %d (SR %d, UL_inactivity timer %d, UL_failure timer " + "%d, cqi_req_timer %d)\n", + module_idP, + harq_pid, + frameP, + subframeP, + UE_id, + rnti, + round_index, + UE_template_ptr->ul_SR, + UE_sched_ctrl_ptr->ul_inactivity_timer, + UE_sched_ctrl_ptr->ul_failure_timer, + UE_sched_ctrl_ptr->cqi_req_timer); + + /* Reset the scheduling request */ + UE_template_ptr->ul_SR = 0; + const uint8_t status = mac_eNB_get_rrc_status(module_idP, rnti); + + /* Power control */ + /* + * Compute the expected ULSCH RX snr (for the stats) + * This is the normalized RX snr and this should be constant (regardless + * of mcs) Is not in dBm, unit from nfapi, converting to dBm + */ + const int32_t snr = (5 * UE_sched_ctrl_ptr->pusch_snr[CC_id] - 640) / 10; + const int32_t target_snr = mac->puSch10xSnr / 10; + + /* + * This assumes accumulated tpc + * Make sure that we are only sending a tpc update once a frame, otherwise + * the control loop will freak out + */ + const int32_t fx10psf = (UE_template_ptr->pusch_tpc_tx_frame * 10) + + UE_template_ptr->pusch_tpc_tx_subframe; + uint32_t tpc = 1; + if (((fx10psf + 10) <= (frameP * 10 + subframeP)) // normal case + || ((fx10psf > (frameP * 10 + subframeP)) + && (((10240 - fx10psf + frameP * 10 + subframeP) >= 10)))) { // frame wrap-around + UE_template_ptr->pusch_tpc_tx_frame = frameP; + UE_template_ptr->pusch_tpc_tx_subframe = subframeP; + + if (snr > target_snr + 4) { + tpc = 0; // -1 + tpc_accumulated--; + } else if (snr < target_snr - 4) { + tpc = 2; // +1 + tpc_accumulated++; + } + } + if (tpc != 1) { + LOG_D(MAC, + "[eNB %d] ULSCH scheduler: frame %d, subframe %d, harq_pid %d, " + "tpc %d, accumulated %d, snr/target snr %d/%d\n", module_idP, frameP, subframeP, - sched_frame, - sched_subframeP, harq_pid, + tpc, + tpc_accumulated, + snr, + target_snr); + } + + /* New transmission */ + if (round_index == 0) { + /* Handle the aperiodic CQI report */ + uint32_t cqi_req = 0; + LOG_D(MAC, + "RRC Connection status %d, cqi_timer %d\n", + status, + UE_sched_ctrl_ptr->cqi_req_timer); + + if (status >= RRC_CONNECTED && UE_sched_ctrl_ptr->cqi_req_timer > 30) { + if (UE_sched_ctrl_ptr->cqi_received == 0) { + cqi_req = 1; + LOG_D(MAC, + "Setting CQI_REQ (timer %d)\n", + UE_sched_ctrl_ptr->cqi_req_timer); + + /* TDD: to be safe, do not ask CQI in special + * Subframes:36.213/7.2.3 CQI definition */ + if (cc[CC_id].tdd_Config) { + switch (cc[CC_id].tdd_Config->subframeAssignment) { + case 1: + if (subframeP == 1 || subframeP == 6) + cqi_req = 0; + break; + + case 3: + if (subframeP == 1) + cqi_req = 0; + break; + + default: + LOG_E(MAC, " TDD config not supported\n"); + break; + } + } + + if (cqi_req == 1) + UE_sched_ctrl_ptr->cqi_req_flag |= 1 << sched_subframeP; + } else { + LOG_D(MAC, "Clearing CQI request timer\n"); + UE_sched_ctrl_ptr->cqi_req_flag = 0; + UE_sched_ctrl_ptr->cqi_received = 0; + UE_sched_ctrl_ptr->cqi_req_timer = 0; + } + } + + const uint8_t ndi = 1 - UE_template_ptr->oldNDI_UL[harq_pid]; // NDI: new data indicator + const uint8_t mcs = UE_template_ptr->pre_assigned_mcs_ul; + UE_template_ptr->oldNDI_UL[harq_pid] = ndi; + UE_info->eNB_UE_stats[CC_id][UE_id].snr = snr; + UE_info->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; + UE_template_ptr->mcs_UL[harq_pid] = mcs; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1 = mcs; + + /* CDRX */ + if (UE_sched_ctrl_ptr->cdrx_configured) { + // reset drx inactivity timer when new transmission + UE_sched_ctrl_ptr->drx_inactivity_timer = 1; + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( + VCD_SIGNAL_DUMPER_VARIABLES_DRX_INACTIVITY, + (unsigned long)UE_sched_ctrl_ptr->drx_inactivity_timer); + // when set the UE_template_ptr->ul_SR cannot be set to 1, + // see definition for more information + UE_sched_ctrl_ptr->dci0_ongoing_timer = 1; + } + + uint8_t rb_table_index = UE_template_ptr->pre_allocated_rb_table_index_ul; + + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = mcs; + + while (rb_table[rb_table_index] > 45 && rb_table_index > 0) + rb_table_index--; + + UE_template_ptr->TBS_UL[harq_pid] = get_TBS_UL(mcs, rb_table[rb_table_index]); + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += rb_table[rb_table_index]; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = UE_template_ptr->TBS_UL[harq_pid]; + UE_info->eNB_UE_stats[CC_id][UE_id].total_ulsch_TBS += UE_template_ptr->TBS_UL[harq_pid]; + T(T_ENB_MAC_UE_UL_SCHEDULE, + T_INT(module_idP), + T_INT(CC_id), + T_INT(rnti), + T_INT(frameP), + T_INT(subframeP), + T_INT(harq_pid), + T_INT(mcs), + T_INT(rb_table[rb_table_index]), + T_INT(UE_template_ptr->TBS_UL[harq_pid]), + T_INT(ndi)); + /* Store information for possible retransmission */ + UE_template_ptr->nb_rb_ul[harq_pid] = rb_table[rb_table_index]; + UE_template_ptr->first_rb_ul[harq_pid] = UE_template_ptr->pre_first_nb_rb_ul; + UE_template_ptr->cqi_req[harq_pid] = cqi_req; + UE_sched_ctrl_ptr->ul_scheduled |= (1 << harq_pid); + + if (UE_id == UE_info->list.head) { + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( + VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED, + UE_sched_ctrl_ptr->ul_scheduled); + } + + /* Adjust scheduled UL bytes by TBS, wait for UL sdus to do final update */ + LOG_D(MAC, + "[eNB %d] CC_id %d UE %d/%x : adjusting scheduled_ul_bytes, old " + "%d, TBS %d\n", + module_idP, + CC_id, UE_id, rnti, - CC_id, - aggregation, - n_rb_ul_tab[CC_id]); - /* Seems unused, only for debug */ - RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP * 10) + subframeP] = UE_template_ptr->estimated_ul_buffer; - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO, UE_template_ptr->estimated_ul_buffer); + UE_template_ptr->scheduled_ul_bytes, + UE_template_ptr->TBS_UL[harq_pid]); + UE_template_ptr->scheduled_ul_bytes += UE_template_ptr->TBS_UL[harq_pid]; + LOG_D(MAC, + "scheduled_ul_bytes, new %d\n", + UE_template_ptr->scheduled_ul_bytes); + /* Cyclic shift for DM-RS */ + /* Save it for a potential retransmission */ + UE_template_ptr->cshift[harq_pid] = cshift; + /* Setting DCI0 NFAPI struct */ + hi_dci0_pdu = &hi_dci0_req_body->hi_dci0_pdu_list[dci_ul_pdu_idx]; + hi_dci0_pdu->pdu_size = 2 + sizeof(nfapi_hi_dci0_dci_pdu); + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dci_format = NFAPI_UL_DCI_FORMAT_0; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.transmission_power = 6000; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.resource_block_start = UE_template_ptr->pre_first_nb_rb_ul; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.number_of_resource_block = + rb_table[rb_table_index]; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.mcs_1 = mcs; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cyclic_shift_2_for_drms = cshift; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.frequency_hopping_enabled_flag = 0; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.new_data_indication_1 = ndi; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tpc = tpc; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cqi_csi_request = cqi_req; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dl_assignment_index = + UE_template_ptr->DAI_ul[sched_subframeP]; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid; + hi_dci0_req_body->sfnsf = + sfnsf_add_subframe(sched_frame, sched_subframeP, 0); + hi_dci0_req_body->tl.tag = NFAPI_HI_DCI0_REQUEST_BODY_TAG; + hi_dci0_req->sfn_sf = frameP << 4 | subframeP; + hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST; + LOG_D(MAC, + "[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE " + "%d/%x, ulsch_frame %d, ulsch_subframe %d\n", + harq_pid, + frameP, + subframeP, + UE_id, + rnti, + sched_frame, + sched_subframeP); + uint16_t ul_req_index = 0; + uint8_t dlsch_flag = 0; - /* - * If there is information on BSR of DCCH, DTCH or if there is UL_SR, - * or if there is a packet to retransmit, or we want to schedule a periodic feedback - */ - if (UE_is_to_be_scheduled(module_idP, CC_id, UE_id) > 0 || round_index > 0) { - LOG_D(MAC, "[eNB %d][PUSCH %d] Frame %d subframe %d Scheduling UE %d/%x in round %d(SR %d,UL_inactivity timer %d,UL_failure timer %d,cqi_req_timer %d)\n", - module_idP, - harq_pid, + for (ul_req_index = 0; ul_req_index < ul_req_tmp_body->number_of_pdus; ul_req_index++) { + if (ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE && + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].uci_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) { + dlsch_flag = 1; + LOG_D(MAC, + "Frame %d, Subframe %d:rnti %x ul_req_index %d Switched UCI " + "HARQ to ULSCH HARQ(first)\n", + frameP, + subframeP, + rnti, + ul_req_index); + break; + } + } + + /* Add UL_config PDUs */ + fill_nfapi_ulsch_config_request_rel8( + &ul_req_tmp_body->ul_config_pdu_list[ul_req_index], + cqi_req, + cc, + UE_template_ptr->physicalConfigDedicated, + get_tmode(module_idP, CC_id, UE_id), + mac->ul_handle, + rnti, + UE_template_ptr->pre_first_nb_rb_ul, // resource_block_start + rb_table[rb_table_index], // number_of_resource_blocks + mcs, + cshift, // cyclic_shift_2_for_drms + 0, // frequency_hopping_enabled_flag + 0, // frequency_hopping_bits + ndi, // new_data_indication + 0, // redundancy_version + harq_pid, // harq_process_number + 0, // ul_tx_mode + 0, // current_tx_nb + 0, // n_srs + get_TBS_UL(mcs, rb_table[rb_table_index])); + + /* This is a BL/CE UE allocation */ + if (UE_template_ptr->rach_resource_type > 0) { + fill_nfapi_ulsch_config_request_emtc( + &ul_req_tmp_body->ul_config_pdu_list[ul_req_index], + UE_template_ptr->rach_resource_type > 2 ? 2 : 1, + 1, // total_number_of_repetitions + 1, // repetition_number + (frameP * 10) + subframeP); + } + + if (dlsch_flag == 1) { + if (cqi_req == 1) { + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE; + ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.harq_information; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = rb_table[rb_table_index]; + } else { + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE; + ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.harq_information; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = rb_table[rb_table_index]; + } + + fill_nfapi_ulsch_harq_information(module_idP, CC_id, rnti, ulsch_harq_information, subframeP); + } else { + ul_req_tmp_body->number_of_pdus++; + } + + ul_req_tmp->header.message_id = NFAPI_UL_CONFIG_REQUEST; + ul_req_tmp_body->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; + mac->ul_handle++; + ul_req_tmp->sfn_sf = sched_frame << 4 | sched_subframeP; + add_ue_ulsch_info(module_idP, CC_id, UE_id, subframeP, S_UL_SCHEDULED); + LOG_D(MAC, + "[eNB %d] CC_id %d Frame %d, subframeP %d: Generated ULSCH DCI for " + "next UE_id %d, format 0\n", + module_idP, + CC_id, + frameP, + subframeP, + UE_id); + LOG_D( + MAC, + "[PUSCH %d] SFN/SF:%04d%d UL_CFG:SFN/SF:%04d%d CQI:%d for UE %d/%x\n", + harq_pid, + frameP, + subframeP, + sched_frame, + sched_subframeP, + cqi_req, + UE_id, + rnti); + } else { // round_index > 0 => retransmission + uint8_t mcs_rv = 0; + const int rvidx_tab[4] = {0, 2, 3, 1}; + uint8_t round_UL = UE_sched_ctrl_ptr->round_UL[CC_id][harq_pid]; + if (rvidx_tab[round_UL & 3] == 1) { + mcs_rv = 29; + } else if (rvidx_tab[round_UL & 3] == 2) { + mcs_rv = 30; + } else if (rvidx_tab[round_UL & 3] == 3) { + mcs_rv = 31; + } + + const uint16_t first_rb = UE_template_ptr->pre_first_nb_rb_ul; + const uint8_t nb_rb = UE_template_ptr->pre_allocated_nb_rb_ul; + if (first_rb != UE_template_ptr->first_rb_ul[harq_pid] + || nb_rb != UE_template_ptr->nb_rb_ul[harq_pid]) + LOG_D(MAC, + "%4d.%d UE %4x retx: change freq allocation to %d RBs start %d (from %d RBs start %d)\n", frameP, subframeP, - UE_id, rnti, - round_index, - UE_template_ptr->ul_SR, - UE_sched_ctrl_ptr->ul_inactivity_timer, - UE_sched_ctrl_ptr->ul_failure_timer, - UE_sched_ctrl_ptr->cqi_req_timer); - /* Reset the scheduling request */ - UE_template_ptr->ul_SR = 0; - status = mac_eNB_get_rrc_status(module_idP, rnti); + nb_rb, + first_rb, + UE_template_ptr->nb_rb_ul[harq_pid], + UE_template_ptr->first_rb_ul[harq_pid]); + UE_template_ptr->first_rb_ul[harq_pid] = first_rb; + UE_template_ptr->nb_rb_ul[harq_pid] = nb_rb; - /* New transmission */ - if (round_index == 0) { - /* Be sure that there are some free RBs */ - if (first_rb_slice[CC_id] >= n_rb_ul_tab[CC_id]) { - LOG_W(MAC, "[eNB %d] frame %d, subframe %d, UE %d/%x CC %d: dropping, not enough RBs\n", - module_idP, - frameP, - subframeP, - UE_id, - rnti, - CC_id); - continue; - } + T(T_ENB_MAC_UE_UL_SCHEDULE_RETRANSMISSION, + T_INT(module_idP), + T_INT(CC_id), + T_INT(rnti), + T_INT(frameP), + T_INT(subframeP), + T_INT(harq_pid), + T_INT(mcs_rv), + T_INT(first_rb), + T_INT(nb_rb), + T_INT(round_index)); + /* Add UL_config PDUs */ + LOG_D(MAC, + "[PUSCH %d] %4d.%d: Adding UL CONFIG.Request for UE " + "%d/%x, ulsch_frame %d, ulsch_subframe %d\n", + harq_pid, + frameP, + subframeP, + UE_id, + rnti, + sched_frame, + sched_subframeP); - /* Should format_flag be 2 in CCE_allocation_infeasible??? */ - /* This test seems to be way too long, can we provide an optimization? */ - if (CCE_allocation_infeasible(module_idP, CC_id, 1, subframeP, aggregation, rnti)) { - LOG_W(MAC, "[eNB %d] frame %d, subframe %d, UE %d/%x CC %d: not enough CCE\n", - module_idP, - frameP, - subframeP, - UE_id, - rnti, - CC_id); - continue; - } + hi_dci0_pdu = &hi_dci0_req_body->hi_dci0_pdu_list[dci_ul_pdu_idx]; + hi_dci0_pdu->pdu_size = 2 + sizeof(nfapi_hi_dci0_dci_pdu); + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dci_format = NFAPI_UL_DCI_FORMAT_0; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.transmission_power = 6000; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.resource_block_start = first_rb; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.number_of_resource_block = nb_rb; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.mcs_1 = mcs_rv; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cyclic_shift_2_for_drms = cshift; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.frequency_hopping_enabled_flag = 0; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.new_data_indication_1 = UE_template_ptr->oldNDI_UL[harq_pid]; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tpc = tpc; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cqi_csi_request = UE_template_ptr->cqi_req[harq_pid]; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dl_assignment_index = UE_template_ptr->DAI_ul[sched_subframeP]; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid; - /* Handle the aperiodic CQI report */ - cqi_req = 0; - LOG_D(MAC,"RRC Conenction status %d, cqi_timer %d\n",status,UE_sched_ctrl_ptr->cqi_req_timer); - - if (status >= RRC_CONNECTED && UE_sched_ctrl_ptr->cqi_req_timer > 30) { - if (UE_sched_ctrl_ptr->cqi_received == 0) { - cqi_req = 1; - LOG_D(MAC, - "Setting CQI_REQ (timer %d)\n", - UE_sched_ctrl_ptr->cqi_req_timer); - - /* TDD: to be safe, do not ask CQI in special - * Subframes:36.213/7.2.3 CQI definition */ - if (cc[CC_id].tdd_Config) { - switch (cc[CC_id].tdd_Config->subframeAssignment) { - case 1: - if (subframeP == 1 || subframeP == 6) - cqi_req = 0; - break; - - case 3: - if (subframeP == 1) - cqi_req = 0; - break; - - default: - LOG_E(MAC, " TDD config not supported\n"); - break; - } - } - - if (cqi_req == 1) { - UE_sched_ctrl_ptr->cqi_req_flag |= 1 << sched_subframeP; - } - } else { - LOG_D(MAC,"Clearing CQI request timer\n"); - UE_sched_ctrl_ptr->cqi_req_flag = 0; - UE_sched_ctrl_ptr->cqi_received = 0; - UE_sched_ctrl_ptr->cqi_req_timer = 0; - } - } - - /* Power control */ - /* - * Compute the expected ULSCH RX snr (for the stats) - * This is the normalized RX snr and this should be constant (regardless of mcs) - * Is not in dBm, unit from nfapi, converting to dBm - */ - snr = (5 * UE_sched_ctrl_ptr->pusch_snr[CC_id] - 640) / 10; - target_snr = mac->puSch10xSnr / 10; - /* - * This assumes accumulated tpc - * Make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out - */ - framex10psubframe = (UE_template_ptr->pusch_tpc_tx_frame * 10) + UE_template_ptr->pusch_tpc_tx_subframe; - - if (((framex10psubframe + 10) <= (frameP * 10 + subframeP)) || // normal case - ((framex10psubframe > (frameP * 10 + subframeP)) && (((10240 - framex10psubframe + frameP * 10 + subframeP) >= 10)))) { //frame wrap-around - UE_template_ptr->pusch_tpc_tx_frame = frameP; - UE_template_ptr->pusch_tpc_tx_subframe = subframeP; - - if (snr > target_snr + 4) { - tpc = 0; // -1 - tpc_accumulated--; - } else if (snr < target_snr - 4) { - tpc = 2; // +1 - tpc_accumulated++; - } else { - tpc = 1; // 0 - } - } else { - tpc = 1; // 0 - } - - if (tpc != 1) { - LOG_D(MAC, "[eNB %d] ULSCH scheduler: frame %d, subframe %d, harq_pid %d, tpc %d, accumulated %d, snr/target snr %d/%d\n", - module_idP, - frameP, - subframeP, - harq_pid, - tpc, - tpc_accumulated, - snr, - target_snr); - } - - ndi = 1 - UE_template_ptr->oldNDI_UL[harq_pid]; // NDI: new data indicator - UE_template_ptr->oldNDI_UL[harq_pid] = ndi; - UE_list->eNB_UE_stats[CC_id][UE_id].snr = snr; - UE_list->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; - UE_template_ptr->mcs_UL[harq_pid] = cmin(UE_template_ptr->pre_assigned_mcs_ul, sli->ul[slice_idx].maxmcs); - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1= UE_template_ptr->mcs_UL[harq_pid]; - - /* CDRX */ - if (UE_sched_ctrl_ptr->cdrx_configured) { - UE_sched_ctrl_ptr->drx_inactivity_timer = 1; // reset drx inactivity timer when new transmission - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_DRX_INACTIVITY, (unsigned long) UE_sched_ctrl_ptr->drx_inactivity_timer); - UE_sched_ctrl_ptr->dci0_ongoing_timer = 1; // when set the UE_template_ptr->ul_SR cannot be set to 1, - // see definition for more information - } - - if (UE_template_ptr->pre_allocated_rb_table_index_ul >= 0) { - rb_table_index = UE_template_ptr->pre_allocated_rb_table_index_ul; - } else { - UE_template_ptr->mcs_UL[harq_pid] = 10; - rb_table_index = 5; // for PHR - } - - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = UE_template_ptr->mcs_UL[harq_pid]; - - while (((rb_table[rb_table_index] > (n_rb_ul_tab[CC_id] - first_rb_slice[CC_id])) || - (rb_table[rb_table_index] > 45)) && (rb_table_index > 0)) { - rb_table_index--; - } - - UE_template_ptr->TBS_UL[harq_pid] = get_TBS_UL(UE_template_ptr->mcs_UL[harq_pid], rb_table[rb_table_index]); - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += rb_table[rb_table_index]; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = UE_template_ptr->TBS_UL[harq_pid]; - UE_list->eNB_UE_stats[CC_id][UE_id].total_ulsch_TBS += UE_template_ptr->TBS_UL[harq_pid]; - T(T_ENB_MAC_UE_UL_SCHEDULE, - T_INT(module_idP), - T_INT(CC_id), - T_INT(rnti), - T_INT(frameP), - T_INT(subframeP), - T_INT(harq_pid), - T_INT(UE_template_ptr->mcs_UL[harq_pid]), - T_INT(first_rb_slice[CC_id]), - T_INT(rb_table[rb_table_index]), - T_INT(UE_template_ptr->TBS_UL[harq_pid]), - T_INT(ndi)); - /* Store information for possible retransmission */ - UE_template_ptr->nb_rb_ul[harq_pid] = rb_table[rb_table_index]; - UE_template_ptr->first_rb_ul[harq_pid] = first_rb_slice[CC_id]; - UE_template_ptr->cqi_req[harq_pid] = cqi_req; - UE_sched_ctrl_ptr->ul_scheduled |= (1 << harq_pid); - - if (UE_id == UE_list->head) { - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED, UE_sched_ctrl_ptr->ul_scheduled); - } - - /* Adjust scheduled UL bytes by TBS, wait for UL sdus to do final update */ - LOG_D(MAC, "[eNB %d] CC_id %d UE %d/%x : adjusting scheduled_ul_bytes, old %d, TBS %d\n", - module_idP, - CC_id, - UE_id, + uint16_t ul_req_index = 0; + uint8_t dlsch_flag = 0; + uint32_t cqi_req = UE_template_ptr->cqi_req[harq_pid]; + for (ul_req_index = 0; ul_req_index < ul_req_tmp_body->number_of_pdus; ul_req_index++) { + if (ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE && + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].uci_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) { + dlsch_flag = 1; + LOG_D(MAC, + "Frame %d, Subframe %d:rnti %x ul_req_index %d Switched UCI " + "HARQ to ULSCH HARQ(first)\n", + frameP, + subframeP, rnti, - UE_template_ptr->scheduled_ul_bytes, - UE_template_ptr->TBS_UL[harq_pid]); - UE_template_ptr->scheduled_ul_bytes += UE_template_ptr->TBS_UL[harq_pid]; - LOG_D(MAC, "scheduled_ul_bytes, new %d\n", - UE_template_ptr->scheduled_ul_bytes); - /* Cyclic shift for DM-RS */ - cshift = 0; // values from 0 to 7 can be used for mapping the cyclic shift (36.211 , Table 5.5.2.1.1-1) - /* Save it for a potential retransmission */ - UE_template_ptr->cshift[harq_pid] = cshift; - /* Setting DCI0 NFAPI struct */ - hi_dci0_pdu = &hi_dci0_req_body->hi_dci0_pdu_list[hi_dci0_req_body->number_of_dci + hi_dci0_req_body->number_of_hi]; - memset((void *) hi_dci0_pdu, 0,sizeof(nfapi_hi_dci0_request_pdu_t)); - hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE; - hi_dci0_pdu->pdu_size = 2 + sizeof(nfapi_hi_dci0_dci_pdu); - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_DCI_PDU_REL8_TAG; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dci_format = NFAPI_UL_DCI_FORMAT_0; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.transmission_power = 6000; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.resource_block_start = first_rb_slice[CC_id]; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.number_of_resource_block = rb_table[rb_table_index]; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.mcs_1 = UE_template_ptr->mcs_UL[harq_pid]; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cyclic_shift_2_for_drms = cshift; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.frequency_hopping_enabled_flag = 0; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.new_data_indication_1 = ndi; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tpc = tpc; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cqi_csi_request = cqi_req; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dl_assignment_index = UE_template_ptr->DAI_ul[sched_subframeP]; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid; - hi_dci0_req_body->number_of_dci++; - hi_dci0_req_body->sfnsf = sfnsf_add_subframe(sched_frame, sched_subframeP, 0); - hi_dci0_req_body->tl.tag = NFAPI_HI_DCI0_REQUEST_BODY_TAG; - hi_dci0_req->sfn_sf = frameP << 4 | subframeP; - hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST; - LOG_D(MAC, "[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d\n", - harq_pid, - frameP, - subframeP, - UE_id, - rnti, - sched_frame, - sched_subframeP); - ul_req_index = 0; - dlsch_flag = 0; + ul_req_index); + break; + } + } - for(ul_req_index = 0; ul_req_index < ul_req_tmp_body->number_of_pdus; ul_req_index++) { - if(ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE && - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].uci_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) { - dlsch_flag = 1; - LOG_D(MAC, "Frame %d, Subframe %d:rnti %x ul_req_index %d Switched UCI HARQ to ULSCH HARQ(first)\n", - frameP, - subframeP, - rnti, - ul_req_index); - break; - } - } + fill_nfapi_ulsch_config_request_rel8( + &ul_req_tmp_body->ul_config_pdu_list[ul_req_index], + cqi_req, + cc, + UE_template_ptr->physicalConfigDedicated, + get_tmode(module_idP, CC_id, UE_id), + mac->ul_handle, + rnti, + first_rb, // resource_block_start + nb_rb, // number_of_resource_blocks + mcs_rv, + cshift, // cyclic_shift_2_for_drms + 0, // frequency_hopping_enabled_flag + 0, // frequency_hopping_bits + UE_template_ptr->oldNDI_UL[harq_pid], // new_data_indication + rvidx_tab[round_index & 3], // redundancy_version + harq_pid, // harq_process_number + 0, // ul_tx_mode + 0, // current_tx_nb + 0, // n_srs + UE_template_ptr->TBS_UL[harq_pid]); - /* Add UL_config PDUs */ - fill_nfapi_ulsch_config_request_rel8(&ul_req_tmp_body->ul_config_pdu_list[ul_req_index], - cqi_req, - cc, - UE_template_ptr->physicalConfigDedicated, - get_tmode(module_idP, CC_id, UE_id), - mac->ul_handle, - rnti, - first_rb_slice[CC_id], // resource_block_start - rb_table[rb_table_index], // number_of_resource_blocks - UE_template_ptr->mcs_UL[harq_pid], - cshift, // cyclic_shift_2_for_drms - 0, // frequency_hopping_enabled_flag - 0, // frequency_hopping_bits - ndi, // new_data_indication - 0, // redundancy_version - harq_pid, // harq_process_number - 0, // ul_tx_mode - 0, // current_tx_nb - 0, // n_srs - get_TBS_UL(UE_template_ptr->mcs_UL[harq_pid], rb_table[rb_table_index])); + /* This is a BL/CE UE allocation */ + if (UE_template_ptr->rach_resource_type > 0) { + fill_nfapi_ulsch_config_request_emtc( + &ul_req_tmp_body->ul_config_pdu_list[ul_req_index], + UE_template_ptr->rach_resource_type > 2 ? 2 : 1, + 1, // total_number_of_repetitions + 1, // repetition_number + (frameP * 10) + subframeP); + } - /* This is a BL/CE UE allocation */ - if (UE_template_ptr->rach_resource_type > 0) { - fill_nfapi_ulsch_config_request_emtc(&ul_req_tmp_body->ul_config_pdu_list[ul_req_index], - UE_template_ptr->rach_resource_type > 2 ? 2 : 1, - 1, // total_number_of_repetitions - 1, // repetition_number - (frameP * 10) + subframeP); - } + if (dlsch_flag == 1) { + if (cqi_req == 1) { + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE; + ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.harq_information; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = UE_template_ptr->nb_rb_ul[harq_pid]; + } else { + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE; + ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.harq_information; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured + ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = UE_template_ptr->nb_rb_ul[harq_pid]; + } - if (dlsch_flag == 1) { - if (cqi_req == 1) { - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE; - ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.harq_information; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = - NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = - rb_table[rb_table_index]; - } else { - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE; - ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.harq_information; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = - NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = rb_table[rb_table_index]; - } + fill_nfapi_ulsch_harq_information(module_idP, CC_id, rnti, ulsch_harq_information, subframeP); + } else { + ul_req_tmp_body->number_of_pdus++; + } - fill_nfapi_ulsch_harq_information(module_idP, CC_id,rnti, ulsch_harq_information,subframeP); - } else { - ul_req_tmp_body->number_of_pdus++; - } - - ul_req_tmp->header.message_id = NFAPI_UL_CONFIG_REQUEST; - ul_req_tmp_body->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; - mac->ul_handle++; - ul_req_tmp->sfn_sf = sched_frame << 4 | sched_subframeP; - add_ue_ulsch_info(module_idP, CC_id, UE_id, subframeP, S_UL_SCHEDULED); - LOG_D(MAC, "[eNB %d] CC_id %d Frame %d, subframeP %d: Generated ULSCH DCI for next UE_id %d, format 0\n", - module_idP, - CC_id, - frameP, - subframeP, - UE_id); - LOG_D(MAC, "[PUSCH %d] SFN/SF:%04d%d UL_CFG:SFN/SF:%04d%d CQI:%d for UE %d/%x\n", - harq_pid, - frameP, - subframeP, - sched_frame, - sched_subframeP, - cqi_req, - UE_id, - rnti); - /* Increment first rb for next UE allocation */ - first_rb_slice[CC_id] += rb_table[rb_table_index]; - } else { // round_index > 0 => retransmission - T(T_ENB_MAC_UE_UL_SCHEDULE_RETRANSMISSION, - T_INT(module_idP), - T_INT(CC_id), - T_INT(rnti), - T_INT(frameP), - T_INT(subframeP), - T_INT(harq_pid), - T_INT(UE_template_ptr->mcs_UL[harq_pid]), - T_INT(UE_template_ptr->first_rb_ul[harq_pid]), - T_INT(UE_template_ptr->nb_rb_ul[harq_pid]), - T_INT(round_index)); - /* Add UL_config PDUs */ - LOG_D(MAC, "[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d\n", - harq_pid, - frameP, - subframeP, - UE_id, - rnti, - sched_frame, - sched_subframeP); - ul_req_index = 0; - dlsch_flag = 0; - cqi_req = UE_template_ptr->cqi_req[harq_pid]; - - for(ul_req_index = 0; ul_req_index < ul_req_tmp_body->number_of_pdus; ul_req_index++) { - if(ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type == NFAPI_UL_CONFIG_UCI_HARQ_PDU_TYPE && - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].uci_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) { - dlsch_flag = 1; - LOG_D(MAC, "Frame %d, Subframe %d:rnti %x ul_req_index %d Switched UCI HARQ to ULSCH HARQ(first)\n", - frameP, - subframeP, - rnti, - ul_req_index); - break; - } - } - - fill_nfapi_ulsch_config_request_rel8(&ul_req_tmp_body->ul_config_pdu_list[ul_req_index], - cqi_req, - cc, - UE_template_ptr->physicalConfigDedicated, - get_tmode(module_idP, CC_id, UE_id), - mac->ul_handle, - rnti, - UE_template_ptr->first_rb_ul[harq_pid], // resource_block_start - UE_template_ptr->nb_rb_ul[harq_pid], // number_of_resource_blocks - UE_template_ptr->mcs_UL[harq_pid], - cshift, // cyclic_shift_2_for_drms - 0, // frequency_hopping_enabled_flag - 0, // frequency_hopping_bits - UE_template_ptr->oldNDI_UL[harq_pid], // new_data_indication - rvidx_tab[round_index & 3], // redundancy_version - harq_pid, // harq_process_number - 0, // ul_tx_mode - 0, // current_tx_nb - 0, // n_srs - UE_template_ptr->TBS_UL[harq_pid]); - - /* This is a BL/CE UE allocation */ - if (UE_template_ptr->rach_resource_type > 0) { - fill_nfapi_ulsch_config_request_emtc(&ul_req_tmp_body->ul_config_pdu_list[ul_req_index], - UE_template_ptr->rach_resource_type > 2 ? 2 : 1, - 1, // total_number_of_repetitions - 1, // repetition_number - (frameP * 10) + subframeP); - } - - if(dlsch_flag == 1) { - if(cqi_req == 1) { - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_CQI_HARQ_RI_PDU_TYPE; - ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.harq_information; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag= - NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_cqi_harq_ri_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = - UE_template_ptr->nb_rb_ul[harq_pid]; - } else { - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].pdu_type = NFAPI_UL_CONFIG_ULSCH_HARQ_PDU_TYPE; - ulsch_harq_information = &ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.harq_information; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.tl.tag = - NFAPI_UL_CONFIG_REQUEST_INITIAL_TRANSMISSION_PARAMETERS_REL8_TAG; - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.n_srs_initial = 0; // last symbol not punctured - ul_req_tmp_body->ul_config_pdu_list[ul_req_index].ulsch_harq_pdu.initial_transmission_parameters.initial_transmission_parameters_rel8.initial_number_of_resource_blocks = - UE_template_ptr->nb_rb_ul[harq_pid]; - } - - fill_nfapi_ulsch_harq_information(module_idP, CC_id,rnti, ulsch_harq_information, subframeP); - } else { - ul_req_tmp_body->number_of_pdus++; - } - - mac->ul_handle++; - ul_req_tmp_body->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; - ul_req_tmp->sfn_sf = sched_frame<<4|sched_subframeP; - ul_req_tmp->header.message_id = NFAPI_UL_CONFIG_REQUEST; - LOG_D(MAC, "[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d cqi_req %d\n", - harq_pid, - frameP, - subframeP, - UE_id, - rnti, - sched_frame, - sched_subframeP, - cqi_req); - - /* HACK: RBs used by retransmission have to be reserved. - * The current mechanism uses the notion of 'first_rb', so - * we skip all RBs below the ones retransmitted. This is - * not correct. Imagine only RB 23 is retransmitted, then all - * RBs < 23 will be marked unusable for new transmissions (case where round == 0). - * Note also that this code works only if the preprocessor orders - * UEs with retransmission with higher priority than UEs with new - * transmission. - * All this should be cleaned up properly. - */ - if (first_rb_slice[CC_id] < UE_template_ptr->first_rb_ul[harq_pid] + UE_template_ptr->nb_rb_ul[harq_pid]) - first_rb_slice[CC_id] = UE_template_ptr->first_rb_ul[harq_pid] + UE_template_ptr->nb_rb_ul[harq_pid]; - } // end of round > 0 - } // UE_is_to_be_scheduled - } // loop over all active CC_ids - } // loop over UE_ids + mac->ul_handle++; + ul_req_tmp_body->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; + ul_req_tmp->sfn_sf = sched_frame << 4 | sched_subframeP; + ul_req_tmp->header.message_id = NFAPI_UL_CONFIG_REQUEST; + LOG_D(MAC, + "[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE " + "%d/%x, ulsch_frame %d, ulsch_subframe %d cqi_req %d\n", + harq_pid, + frameP, + subframeP, + UE_id, + rnti, + sched_frame, + sched_subframeP, + cqi_req); + } // end of round > 0 + } // loop over UE_ids } @@ -1926,7 +1871,7 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, eNB_MAC_INST *eNB = RC.mac[module_idP]; eNB_RRC_INST *rrc = RC.rrc[module_idP]; COMMON_channels_t *cc = eNB->common_channels; - UE_list_t *UE_list = &(eNB->UE_list); + UE_info_t *UE_info = &eNB->UE_info; UE_TEMPLATE *UE_template = NULL; UE_sched_ctrl_t *UE_sched_ctrl = NULL; uint8_t Total_Num_Rep_ULSCH,pusch_maxNumRepetitionCEmodeA_r13; @@ -1944,8 +1889,8 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, nfapi_ul_config_request_pdu_t *ul_config_pdu_Rep; /* Loop over all active UEs */ - for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) { - UE_template = &(UE_list->UE_template[UE_PCCID(module_idP, UE_id)][UE_id]); + for (UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_template = &UE_info->UE_template[UE_PCCID(module_idP, UE_id)][UE_id]; /* LTE-M device */ if (UE_template->rach_resource_type == 0) { @@ -1974,12 +1919,12 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, } /* Loop over all active UL CC_ids for this UE */ - for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { + for (n = 0; n < UE_info->numactiveULCCs[UE_id]; n++) { /* This is the actual CC_id in the list */ - CC_id = UE_list->ordered_ULCCids[n][UE_id]; + CC_id = UE_info->ordered_ULCCids[n][UE_id]; N_RB_UL = to_prb(cc[CC_id].ul_Bandwidth); - UE_template = &(UE_list->UE_template[CC_id][UE_id]); - UE_sched_ctrl = &UE_list->UE_sched_ctrl[UE_id]; + UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; harq_pid = 0; round_UL = UE_sched_ctrl->round_UL[CC_id][harq_pid]; AssertFatal(round_UL < 8,"round_UL %d > 7 for UE %d/%x\n", @@ -2027,6 +1972,12 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, UE_sched_ctrl->cqi_req_timer); /* Reset the scheduling request */ emtc_active[CC_id] = 1; + cc[CC_id].vrb_map_UL[1] = 1; + cc[CC_id].vrb_map_UL[2] = 1; + cc[CC_id].vrb_map_UL[3] = 1; + cc[CC_id].vrb_map_UL[4] = 1; + cc[CC_id].vrb_map_UL[5] = 1; + cc[CC_id].vrb_map_UL[6] = 1; UE_template->ul_SR = 0; status = mac_eNB_get_rrc_status(module_idP,rnti); cqi_req = 0; @@ -2074,12 +2025,12 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, UE_template->oldNDI_UL[harq_pid] = ndi; UE_template->mcs_UL[harq_pid] = 4; UE_template->TBS_UL[harq_pid] = get_TBS_UL(UE_template->mcs_UL[harq_pid], 6); - UE_list->eNB_UE_stats[CC_id][UE_id].snr = snr; - UE_list->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1 = 4; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = UE_template->mcs_UL[harq_pid]; - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += 6; - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = UE_template->TBS_UL[harq_pid]; + UE_info->eNB_UE_stats[CC_id][UE_id].snr = snr; + UE_info->eNB_UE_stats[CC_id][UE_id].target_snr = target_snr; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1 = 4; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = UE_template->mcs_UL[harq_pid]; + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += 6; + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = UE_template->TBS_UL[harq_pid]; T(T_ENB_MAC_UE_UL_SCHEDULE, T_INT(module_idP), T_INT(CC_id), @@ -2096,7 +2047,7 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, UE_template->nb_rb_ul[harq_pid] = 6; UE_sched_ctrl->ul_scheduled |= (1 << harq_pid); - if (UE_id == UE_list->head) { + if (UE_id == UE_info->list.head) { VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED, UE_sched_ctrl->ul_scheduled); } diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index ac9819cfe2..329e262c82 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -824,11 +824,16 @@ typedef struct { uint16_t cshift[8]; // num_max_harq /// Number of Allocated RBs by the ulsch preprocessor - uint8_t pre_allocated_nb_rb_ul[MAX_NUM_SLICES]; + uint8_t pre_allocated_nb_rb_ul; + /// Start of Allocated RBs by the USLCH preprocessor + uint8_t pre_first_nb_rb_ul; /// index of Allocated RBs by the ulsch preprocessor int8_t pre_allocated_rb_table_index_ul; + /// index of allocated HI_DCI0 + int pre_dci_ul_pdu_idx; + /// total allocated RBs int8_t total_allocated_rbs; @@ -852,10 +857,10 @@ typedef struct { // Logical channel info for link with RLC - /// LCGID mapping + /// LCGID mapping (UL) long lcgidmap[11]; - ///UE logical channel priority + ///UE logical channel priority (UL) long lcgidpriority[11]; /// phr information @@ -913,31 +918,12 @@ typedef struct { /*! \brief scheduling control information set through an API (not used)*/ typedef struct { - ///UL transmission bandwidth in RBs - uint8_t ul_bandwidth[MAX_NUM_LCID]; - ///DL transmission bandwidth in RBs - uint8_t dl_bandwidth[MAX_NUM_LCID]; - - //To do GBR bearer - uint8_t min_ul_bandwidth[MAX_NUM_LCID]; - - uint8_t min_dl_bandwidth[MAX_NUM_LCID]; - - ///aggregated bit rate of non-gbr bearer per UE - uint64_t ue_AggregatedMaximumBitrateDL; - ///aggregated bit rate of non-gbr bearer per UE - uint64_t ue_AggregatedMaximumBitrateUL; - ///CQI scheduling interval in subframes. - uint16_t cqiSchedInterval; - ///Contention resolution timer used during random access - uint8_t mac_ContentionResolutionTimer; - - uint16_t max_rbs_allowed_slice[NFAPI_CC_MAX][MAX_NUM_SLICES]; - uint16_t max_rbs_allowed_slice_uplink[NFAPI_CC_MAX][MAX_NUM_SLICES]; - - uint8_t max_mcs[MAX_NUM_LCID]; - - uint16_t priority[MAX_NUM_LCID]; + /// number of active DL LCs + uint8_t dl_lc_num; + /// order in which DLSCH scheduler should allocate LCs + uint8_t dl_lc_ids[MAX_NUM_LCID]; + /// number of bytes to schedule for each LC + uint32_t dl_lc_bytes[MAX_NUM_LCID]; // resource scheduling information @@ -950,6 +936,7 @@ typedef struct { uint8_t dl_pow_off[NFAPI_CC_MAX]; uint16_t pre_nb_available_rbs[NFAPI_CC_MAX]; unsigned char rballoc_sub_UE[NFAPI_CC_MAX][N_RBG_MAX]; + int pre_dci_dl_pdu_idx; uint16_t ta_timer; int16_t ta_update; uint16_t ul_consecutive_errors; @@ -1130,7 +1117,15 @@ typedef struct { uint8_t sb_size; uint8_t nb_active_sb; } SBMAP_CONF; -/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ + +/*! \brief UE_list_t is a "list" of users within UE_info_t. Especial useful in + * the scheduler and to keep "classes" of users. */ +typedef struct { + int head; + int next[MAX_MOBILES_PER_ENB]; +} UE_list_t; + +/*! \brief UE info used by eNB to order UEs/CC for scheduling*/ typedef struct { DLSCH_PDU DLSCH_pdu[NFAPI_CC_MAX][2][MAX_MOBILES_PER_ENB]; @@ -1152,21 +1147,13 @@ typedef struct { eNB_UE_STATS eNB_UE_stats[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; /// scheduling control info UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_ENB]; - int next[MAX_MOBILES_PER_ENB]; - int head; - int next_ul[MAX_MOBILES_PER_ENB]; - int head_ul; - int avail; + UE_list_t list; int num_UEs; boolean_t active[MAX_MOBILES_PER_ENB]; /// Sorting criteria for the UE list in the MAC preprocessor uint16_t sorting_criteria[MAX_NUM_SLICES][CR_NUM]; - uint16_t first_rb_offset[NFAPI_CC_MAX][MAX_NUM_SLICES]; - - int assoc_dl_slice_idx[MAX_MOBILES_PER_ENB]; - int assoc_ul_slice_idx[MAX_MOBILES_PER_ENB]; -} UE_list_t; +} UE_info_t; /*! \brief deleting control information*/ typedef struct { @@ -1184,20 +1171,6 @@ typedef struct { int tail_freelist; ///the tail position of the delete list } UE_free_list_t; -/// Structure for saving the output of each pre_processor instance -typedef struct { - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX]; - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]; - - uint32_t bytes_lcid[MAX_MOBILES_PER_ENB][MAX_NUM_LCID]; - uint32_t wb_pmi[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - uint8_t mcs[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - -} pre_processor_results_t; - /** * slice specific scheduler for the DL */ @@ -1289,12 +1262,18 @@ typedef struct { int n_ul; slice_sched_conf_ul_t ul[MAX_NUM_SLICES]; - pre_processor_results_t pre_processor_results[MAX_NUM_SLICES]; - /// common rb allocation list between slices uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]; } slice_info_t; +/** + * describes contiguous RBs + */ +typedef struct { + int start; + int length; +} contig_rbs_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1414,7 +1393,7 @@ typedef struct eNB_MAC_INST_s { nfapi_ue_release_request_t UE_release_req; /// UL handle uint32_t ul_handle; - UE_list_t UE_list; + UE_info_t UE_info; /// slice-related configuration slice_info_t slice_info; diff --git a/openair2/LAYER2/MAC/mac_extern.h b/openair2/LAYER2/MAC/mac_extern.h index dbf5b57b6b..cee6066a9e 100644 --- a/openair2/LAYER2/MAC/mac_extern.h +++ b/openair2/LAYER2/MAC/mac_extern.h @@ -60,7 +60,7 @@ extern uint16_t NB_THREAD_INST; extern unsigned char NB_RN_INST; extern unsigned short NODE_ID[1]; -extern int cqi_to_mcs[16]; +extern const int cqi_to_mcs[16]; extern uint32_t RRC_CONNECTION_FLAG; diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 476fb68584..2cb86c25af 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -122,15 +122,14 @@ void schedule_ulsch(module_id_t module_idP, frame_t frameP, /** \brief ULSCH Scheduling per RNTI @param Mod_id Instance ID of eNB -@param slice_idx Slice instance index for this eNB +@param CC_id The component carrier to schedule @param frame Frame index @param subframe Subframe number on which to act @param sched_subframe Subframe number where PUSCH is transmitted (for DAI lookup) */ -void schedule_ulsch_rnti(module_id_t module_idP, int slice_idx, frame_t frameP, +void schedule_ulsch_rnti(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t subframe, - unsigned char sched_subframe, - uint16_t *first_rb); + unsigned char sched_subframe); void schedule_ulsch_rnti_emtc(module_id_t module_idP, frame_t frameP, @@ -138,14 +137,6 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP, unsigned char sched_subframeP, int *emtc_active); -/** \brief Second stage of DLSCH scheduling, after schedule_SI, schedule_RA and schedule_dlsch have been called. This routine first allocates random frequency assignments for SI and RA SDUs using distributed VRB allocations and adds the corresponding DCI SDU to the DCI buffer for PHY. It then loops over the UE specific DCIs previously allocated and fills in the remaining DCI fields related to frequency allocation. It assumes localized allocation of type 0 (DCI.rah=0). The allocation is done for tranmission modes 1,2,4. -@param Mod_id Instance of eNB -@param frame Frame index -@param subframe Index of subframe -@param mbsfn_flag Indicates that this subframe is for MCH/MCCH -*/ -void fill_DLSCH_dci(module_id_t module_idP,frame_t frameP,sub_frame_t subframe,int *mbsfn_flag); - /** \brief UE specific DLSCH scheduling. Retrieves next ue to be schduled from round-robin scheduler and gets the appropriate harq_pid for the subframe from PHY. If the process is active and requires a retransmission, it schedules the retransmission with the same PRB count and MCS as the first transmission. Otherwise it consults RLC for DCCH/DTCH SDUs (status with maximum number of available PRBS), builds the MAC header (timing advance sent by default) and copies @param Mod_id Instance ID of eNB @param frame Frame index @@ -156,8 +147,10 @@ void fill_DLSCH_dci(module_id_t module_idP,frame_t frameP,sub_frame_t subframe,i void schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframe, int *mbsfn_flag); -void schedule_ue_spec(module_id_t module_idP, int slice_idxP, - frame_t frameP,sub_frame_t subframe, int *mbsfn_flag); +void schedule_ue_spec(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t subframe); void schedule_ue_spec_br(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP); @@ -192,7 +185,7 @@ void add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP, //main.c -void init_UE_list(UE_list_t *UE_list); +void init_UE_info(UE_info_t *UE_info); void init_slice_info(slice_info_t *sli); @@ -231,73 +224,9 @@ void clear_nfapi_information(eNB_MAC_INST *eNB, int CC_idP, void dlsch_scheduler_pre_processor(module_id_t module_idP, - int slice_idxP, + int CC_id, frame_t frameP, - sub_frame_t subframe, - int *mbsfn_flag, - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]); - -void dlsch_scheduler_pre_processor_reset(module_id_t module_idP, - int slice_idx, - frame_t frameP, - sub_frame_t subframeP, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX], - int *mbsfn_flag); - -void dlsch_scheduler_pre_processor_partitioning(module_id_t Mod_id, - int slice_idx, - const uint8_t rbs_retx[NFAPI_CC_MAX]); - -void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, - int slice_idx, - frame_t frameP, - sub_frame_t subframeP, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]); - -void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id, - int slice_idx, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]); - -void dlsch_scheduler_pre_processor_intraslice_sharing(module_id_t Mod_id, - int slice_idx, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]); - -void slice_priority_sort(module_id_t Mod_id, int slice_list[MAX_NUM_SLICES]); - -void dlsch_scheduler_interslice_multiplexing(module_id_t Mod_id, - int frameP, - sub_frame_t subframeP, - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]); - -void dlsch_scheduler_qos_multiplexing(module_id_t Mod_id, - int frameP, - sub_frame_t subframeP); - -void dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id, - int UE_id, - uint8_t CC_id, - int N_RBG, - int min_rb_unit, - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]); + sub_frame_t subframe); /* \brief Function to trigger the eNB scheduling procedure. It is called by PHY at the beginning of each subframe, \f$n$\f and generates all DLSCH allocations for subframe \f$n\f$ and ULSCH allocations for subframe \f$n+k$\f. @@ -484,10 +413,23 @@ boolean_t CCE_allocation_infeasible(int module_idP, int common_flag, int subframe, int aggregation, int rnti); +/* tries to allocate a CCE. If it succeeds, reserves NFAPI DCI and DLSCH config */ +int CCE_try_allocate_dlsch(int module_id, + int CC_id, + int subframe, + int UE_id, + uint8_t dl_cqi); + +/* tries to allocate a CCE for UL. If it succeeds, reserves the NFAPI DCI */ +int CCE_try_allocate_ulsch(int module_id, + int CC_id, + int subframe, + int UE_id, + uint8_t dl_cqi); void set_ue_dai(sub_frame_t subframeP, int UE_id, - uint8_t CC_id, uint8_t tdd_config, UE_list_t *UE_list); + uint8_t CC_id, uint8_t tdd_config, UE_info_t *UE_info); uint8_t frame_subframe2_dl_harq_pid(LTE_TDD_Config_t *tdd_Config, int abs_frameP, sub_frame_t subframeP); /** \brief First stage of PCH Scheduling. Gets a PCH SDU from RRC if available and computes the MCS required to transport it as a function of the SDU length. It assumes a length less than or equal to 64 bytes (MCS 6, 3 PRBs). @@ -510,14 +452,6 @@ uint8_t UE_is_to_be_scheduled(module_id_t module_idP, int CC_id, module_id_t schedule_next_ulue(module_id_t module_idP, int UE_id, sub_frame_t subframe); -/** \brief Round-robin scheduler for DLSCH traffic. -@param Mod_id Instance ID for eNB -@param subframe Subframe number on which to act -@returns UE index that is to be scheduled if needed/room -*/ -int schedule_next_dlue(module_id_t module_idP, int CC_id, - sub_frame_t subframe); - /* \brief Allocates a set of PRBS for a particular UE. This is a simple function for the moment, later it should process frequency-domain CQI information and/or PMI information. Currently it just returns the first PRBS that are available in the subframe based on the number requested. @param UE_id Index of UE on which to act @param nb_rb Number of PRBs allocated to UE by scheduler @@ -721,13 +655,13 @@ int mac_init(void); int add_new_ue(module_id_t Mod_id, int CC_id, rnti_t rnti, int harq_pid, uint8_t rach_resource_type); int rrc_mac_remove_ue(module_id_t Mod_id, rnti_t rntiP); -void store_dlsch_buffer(module_id_t Mod_id, int slice_idx, frame_t frameP, sub_frame_t subframeP); -void assign_rbs_required(module_id_t Mod_id, int slice_idx, frame_t frameP, sub_frame_t subframe, uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], int min_rb_unit[NFAPI_CC_MAX]); +void store_dlsch_buffer(module_id_t Mod_id, int CC_id, frame_t frameP, sub_frame_t subframeP); -void swap_UEs(UE_list_t *listP, int nodeiP, int nodejP, int ul_flag); -int prev(UE_list_t *listP, int nodeP, int ul_flag); -void dump_ue_list(UE_list_t *listP, int ul_flag); -int UE_num_active_CC(UE_list_t *listP, int ue_idP); +int prev(UE_list_t *listP, int nodeP); +void add_ue_list(UE_list_t *listP, int UE_id); +int remove_ue_list(UE_list_t *listP, int UE_id); +void dump_ue_list(UE_list_t *listP); +int UE_num_active_CC(UE_info_t *listP, int ue_idP); int UE_PCCID(module_id_t mod_idP, int ue_idP); rnti_t UE_RNTI(module_id_t mod_idP, int ue_idP); @@ -739,20 +673,14 @@ void set_ul_DAI(int module_idP, int frameP, int subframeP); -void ulsch_scheduler_pre_processor(module_id_t module_idP, int slice_idx, int frameP, +void ulsch_scheduler_pre_processor(module_id_t module_idP, + int CC_id, + int frameP, sub_frame_t subframeP, int sched_frameP, - unsigned char sched_subframeP, - uint16_t *first_rb); -void store_ulsch_buffer(module_id_t module_idP, int frameP, - sub_frame_t subframeP); -void assign_max_mcs_min_rb(module_id_t module_idP, int slice_idx, int frameP, - sub_frame_t subframeP, uint16_t *first_rb); -void adjust_bsr_info(int buffer_occupancy, uint16_t TBS, - UE_TEMPLATE *UE_template); + unsigned char sched_subframeP); int phy_stats_exist(module_id_t Mod_id, int rnti); -void sort_UEs(module_id_t Mod_idP, int slice_idx, int frameP, sub_frame_t subframeP); /*! \fn UE_L2_state_t ue_scheduler(const module_id_t module_idP,const frame_t frameP, const sub_frame_t subframe, const lte_subframe_t direction,const uint8_t eNB_index) \brief UE scheduler where all the ue background tasks are done. This function performs the following: 1) Trigger PDCP every 5ms 2) Call RRC for link status return to PHY3) Perform SR/BSR procedures for scheduling feedback 4) Perform PHR procedures. @@ -913,8 +841,7 @@ void add_common_dci(DCI_PDU *DCI_pdu, uint8_t ra_flag); */ -uint32_t allocate_prbs_sub(int nb_rb, int N_RB_DL, int N_RBG, - uint8_t *rballoc); +uint32_t allocate_prbs_sub(int nb_rb, int N_RB_DL, int N_RBG, const uint8_t *rballoc); void update_ul_dci(module_id_t module_idP, uint8_t CC_id, rnti_t rnti, uint8_t dai, sub_frame_t subframe); @@ -1176,14 +1103,13 @@ void program_dlsch_acknak(module_id_t module_idP, int CC_idP, int UE_idP, frame_t frameP, sub_frame_t subframeP, uint8_t cce_idx); -void fill_nfapi_dlsch_config(eNB_MAC_INST *eNB, - nfapi_dl_config_request_body_t *dl_req, +void fill_nfapi_dlsch_config(nfapi_dl_config_request_pdu_t *dl_config_pdu, uint16_t length, int16_t pdu_index, uint16_t rnti, uint8_t resource_allocation_type, uint8_t virtual_resource_block_assignment_flag, - uint16_t resource_block_coding, + uint32_t resource_block_coding, uint8_t modulation, uint8_t redundancy_version, uint8_t transport_blocks, @@ -1277,11 +1203,6 @@ void pre_scd_nb_rbs_required( module_id_t module_idP, uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX]); #endif -/* Slice related functions */ -uint16_t nb_rbs_allowed_slice(float rb_percentage, int total_rbs); -int ue_dl_slice_membership(module_id_t mod_id, int UE_id, int slice_idx); -int ue_ul_slice_membership(module_id_t mod_id, int UE_id, int slice_idx); - /* DRX Configuration */ /* Configure local DRX timers and thresholds in UE context, following the drx_configuration input */ void eNB_Config_Local_DRX(instance_t Mod_id, rrc_mac_drx_config_req_t *rrc_mac_drx_config_req); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index fe8980101d..1a88623a1f 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -43,26 +43,18 @@ extern RAN_CONTEXT_t RC; -void init_UE_list(UE_list_t *UE_list) +void init_UE_info(UE_info_t *UE_info) { int list_el; - UE_list->num_UEs = 0; - UE_list->head = -1; - UE_list->head_ul = -1; - UE_list->avail = 0; - for (list_el = 0; list_el < MAX_MOBILES_PER_ENB - 1; list_el++) { - UE_list->next[list_el] = list_el + 1; - UE_list->next_ul[list_el] = list_el + 1; - } - UE_list->next[list_el] = -1; - UE_list->next_ul[list_el] = -1; - memset(UE_list->DLSCH_pdu, 0, sizeof(UE_list->DLSCH_pdu)); - memset(UE_list->UE_template, 0, sizeof(UE_list->UE_template)); - memset(UE_list->eNB_UE_stats, 0, sizeof(UE_list->eNB_UE_stats)); - memset(UE_list->UE_sched_ctrl, 0, sizeof(UE_list->UE_sched_ctrl)); - memset(UE_list->active, 0, sizeof(UE_list->active)); - memset(UE_list->assoc_dl_slice_idx, 0, sizeof(UE_list->assoc_dl_slice_idx)); - memset(UE_list->assoc_ul_slice_idx, 0, sizeof(UE_list->assoc_ul_slice_idx)); + UE_info->num_UEs = 0; + UE_info->list.head = -1; + for (list_el = 0; list_el < MAX_MOBILES_PER_ENB; list_el++) + UE_info->list.next[list_el] = -1; + memset(UE_info->DLSCH_pdu, 0, sizeof(UE_info->DLSCH_pdu)); + memset(UE_info->UE_template, 0, sizeof(UE_info->UE_template)); + memset(UE_info->eNB_UE_stats, 0, sizeof(UE_info->eNB_UE_stats)); + memset(UE_info->UE_sched_ctrl, 0, sizeof(UE_info->UE_sched_ctrl)); + memset(UE_info->active, 0, sizeof(UE_info->active)); } void init_slice_info(slice_info_t *sli) @@ -137,7 +129,7 @@ void mac_top_init_eNB(void) mac[i]->if_inst = IF_Module_init(i); - init_UE_list(&mac[i]->UE_list); + init_UE_info(&mac[i]->UE_info); init_slice_info(&mac[i]->slice_info); } @@ -163,12 +155,12 @@ void mac_init_cell_params(int Mod_idP, int CC_idP) memset(&RC.mac[Mod_idP]->eNB_stats, 0, sizeof(eNB_STATS)); UE_template = - (UE_TEMPLATE *) & RC.mac[Mod_idP]->UE_list.UE_template[CC_idP][0]; + (UE_TEMPLATE *) & RC.mac[Mod_idP]->UE_info.UE_template[CC_idP][0]; for (j = 0; j < MAX_MOBILES_PER_ENB; j++) { UE_template[j].rnti = 0; // initiallize the eNB to UE statistics - memset(&RC.mac[Mod_idP]->UE_list.eNB_UE_stats[CC_idP][j], 0, + memset(&RC.mac[Mod_idP]->UE_info.eNB_UE_stats[CC_idP][j], 0, sizeof(eNB_UE_STATS)); } @@ -263,4 +255,4 @@ void *mac_enb_task(void *arg) } // end while return NULL; -} \ No newline at end of file +} diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index bd4e4de2a4..8569d8f166 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -36,6 +36,7 @@ #include "LAYER2/MAC/mac.h" #include "LAYER2/MAC/mac_proto.h" #include "LAYER2/MAC/mac_extern.h" +#include #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "UTIL/OPT/opt.h" @@ -50,109 +51,247 @@ extern RAN_CONTEXT_t RC; -#define DEBUG_eNB_SCHEDULER 1 +#define DEBUG_eNB_SCHEDULER #define DEBUG_HEADER_PARSING 1 -//#define DEBUG_PACKET_TRACE 1 -//#define ICIC 0 - -void -sort_ue_ul(module_id_t module_idP, - int slice_idx, - int sched_frameP, - sub_frame_t sched_subframeP, - rnti_t *rntiTable); - -/* this function checks that get_eNB_UE_stats returns - * a non-NULL pointer for all the active CCs of an UE - */ -/* -int phy_stats_exist(module_id_t Mod_id, int rnti) -{ - int CC_id; - int i; - int UE_id = find_UE_id(Mod_id, rnti); - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - if (UE_id == -1) { - LOG_W(MAC, "[eNB %d] UE %x not found, should be there (in phy_stats_exist)\n", - Mod_id, rnti); - return 0; +int next_ue_list_looped(UE_list_t* list, int UE_id) { + if (UE_id < 0) + return list->head; + return list->next[UE_id] < 0 ? list->head : list->next[UE_id]; +} + +int get_rbg_size_last(module_id_t Mod_id, int CC_id) { + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int N_RB_DL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + if (N_RB_DL == 15 || N_RB_DL == 25 || N_RB_DL == 50 || N_RB_DL == 75) + return RBGsize - 1; + else + return RBGsize; +} + +int g_start_ue_dl = -1; +int round_robin_dl(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + int num_ue_req = 0; + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request + memset(rb_required, 0, sizeof(rb_required)); + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + // Calculate the amount of RBs every UE wants to send. + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + continue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + continue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + continue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + const int dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = dlsch_mcs1; + rb_required[UE_id] = + find_nb_rb_DL(dlsch_mcs1, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); + if (rb_required[UE_id] > 0) + num_ue_req++; + LOG_D(MAC, + "%d/%d UE_id %d rb_required %d n_rbg_sched %d\n", + frame, + subframe, + UE_id, + rb_required[UE_id], + n_rbg_sched); + } } - if (UE_list->numactiveCCs[UE_id] == 0) { - LOG_W(MAC, "[eNB %d] UE %x has no active CC (in phy_stats_exist)\n", - Mod_id, rnti); - return 0; + + if (num_ue_req == 0) + return n_rbg_sched; // no UE has a transmission + + // after allocating retransmissions: build list of UE to allocate. + // if start_UE does not exist anymore (detach etc), start at first UE + if (g_start_ue_dl == -1) + g_start_ue_dl = UE_list->head; + int UE_id = g_start_ue_dl; + UE_list_t UE_sched; + int rb_required_total = 0; + int num_ue_sched = 0; + max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); + int *cur_UE = &UE_sched.head; + while (num_ue_sched < max_num_ue) { + while (rb_required[UE_id] == 0) + UE_id = next_ue_list_looped(UE_list, UE_id); + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) { + LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id); + num_ue_req--; + max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); + UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate + continue; + } + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + *cur_UE = UE_id; + cur_UE = &UE_sched.next[UE_id]; + rb_required_total += rb_required[UE_id]; + num_ue_sched++; + UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate } - for (i = 0; i < UE_list->numactiveCCs[UE_id]; i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - if (mac_xface->get_eNB_UE_stats(Mod_id, CC_id, rnti) == NULL) - return 0; + *cur_UE = -1; + + /* for one UE after the next: allocate resources */ + for (int UE_id = UE_sched.head; UE_id >= 0; + UE_id = next_ue_list_looped(&UE_sched, UE_id)) { + if (rb_required[UE_id] <= 0) + continue; + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + rb_required[UE_id] -= sRBG; + rb_required_total -= sRBG; + if (rb_required_total <= 0) + break; + n_rbg_sched--; + if (n_rbg_sched <= 0) + break; + for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } - return 1; + + /* if not all UEs could be allocated in this round */ + if (num_ue_req > max_num_ue) { + /* go to the first one we missed */ + for (int i = 0; i < max_num_ue; ++i) + g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + } else { + /* else, just start with the next UE next time */ + g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + } + + return n_rbg_sched; } -*/ // This function stores the downlink buffer for all the logical channels void store_dlsch_buffer(module_id_t Mod_id, - int slice_idx, + int CC_id, frame_t frameP, sub_frame_t subframeP) { - int UE_id, lcid; - rnti_t rnti; - mac_rlc_status_resp_t rlc_status; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - UE_TEMPLATE *UE_template; + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (UE_list->active[UE_id] != TRUE) - continue; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) - continue; - - UE_template = &UE_list->UE_template[UE_PCCID(Mod_id, UE_id)][UE_id]; - // clear logical channel interface variables + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_sched_ctrl_t *UE_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; UE_template->dl_buffer_total = 0; UE_template->dl_pdus_total = 0; - for (lcid = 0; lcid < MAX_NUM_LCID; ++lcid) { - UE_template->dl_buffer_info[lcid] = 0; - UE_template->dl_pdus_in_buffer[lcid] = 0; - UE_template->dl_buffer_head_sdu_creation_time[lcid] = 0; - UE_template->dl_buffer_head_sdu_remaining_size_to_send[lcid] = 0; - } - - rnti = UE_RNTI(Mod_id, UE_id); - - for (lcid = 0; lcid < MAX_NUM_LCID; ++lcid) { // loop over all the logical channels - rlc_status = mac_rlc_status_ind(Mod_id, rnti, Mod_id, frameP, subframeP, - ENB_FLAG_YES, MBMS_FLAG_NO, lcid, 0,0, 0 - ); - UE_template->dl_buffer_info[lcid] = rlc_status.bytes_in_buffer; //storing the dlsch buffer for each logical channel + /* loop over all activated logical channels */ + for (int i = 0; i < UE_sched_ctrl->dl_lc_num; ++i) { + const int lcid = UE_sched_ctrl->dl_lc_ids[i]; + const mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(Mod_id, + UE_template->rnti, + Mod_id, + frameP, + subframeP, + ENB_FLAG_YES, + MBMS_FLAG_NO, + lcid, + 0, + 0 + ); + UE_template->dl_buffer_info[lcid] = rlc_status.bytes_in_buffer; UE_template->dl_pdus_in_buffer[lcid] = rlc_status.pdus_in_buffer; UE_template->dl_buffer_head_sdu_creation_time[lcid] = rlc_status.head_sdu_creation_time; UE_template->dl_buffer_head_sdu_creation_time_max = cmax(UE_template->dl_buffer_head_sdu_creation_time_max, rlc_status.head_sdu_creation_time); UE_template->dl_buffer_head_sdu_remaining_size_to_send[lcid] = rlc_status.head_sdu_remaining_size_to_send; UE_template->dl_buffer_head_sdu_is_segmented[lcid] = rlc_status.head_sdu_is_segmented; - UE_template->dl_buffer_total += UE_template->dl_buffer_info[lcid]; //storing the total dlsch buffer + UE_template->dl_buffer_total += UE_template->dl_buffer_info[lcid]; UE_template->dl_pdus_total += UE_template->dl_pdus_in_buffer[lcid]; -#ifdef DEBUG_eNB_SCHEDULER + /* update the number of bytes in the UE_sched_ctrl. The DLSCH will use + * this to request the corresponding data from the RLC, and this might be + * limited in the preprocessor */ + UE_sched_ctrl->dl_lc_bytes[i] = rlc_status.bytes_in_buffer; + +#ifdef DEBUG_eNB_SCHEDULER /* note for dl_buffer_head_sdu_remaining_size_to_send[lcid] : * 0 if head SDU has not been segmented (yet), else remaining size not already segmented and sent */ if (UE_template->dl_buffer_info[lcid] > 0) LOG_D(MAC, - "[eNB %d][SLICE %d] Frame %d Subframe %d : RLC status for UE %d in LCID%d: total of %d pdus and size %d, head sdu queuing time %d, remaining size %d, is segmeneted %d \n", - Mod_id, RC.mac[Mod_id]->slice_info.dl[slice_idx].id, frameP, + "[eNB %d] Frame %d Subframe %d : RLC status for UE %d in LCID%d: total of %d pdus and size %d, head sdu queuing time %d, remaining size %d, is segmeneted %d \n", + Mod_id, frameP, subframeP, UE_id, lcid, UE_template->dl_pdus_in_buffer[lcid], UE_template->dl_buffer_info[lcid], UE_template->dl_buffer_head_sdu_creation_time[lcid], UE_template->dl_buffer_head_sdu_remaining_size_to_send[lcid], UE_template->dl_buffer_head_sdu_is_segmented[lcid]); - #endif } @@ -165,1914 +304,572 @@ store_dlsch_buffer(module_id_t Mod_id, } } -int cqi2mcs(int cqi) { - return cqi_to_mcs[cqi]; -} - -// This function returns the estimated number of RBs required by each UE for downlink scheduling -void -assign_rbs_required(module_id_t Mod_id, - int slice_idx, - frame_t frameP, - sub_frame_t subframe, - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - int min_rb_unit[NFAPI_CC_MAX]) { - uint16_t TBS = 0; - int UE_id, n, i, j, CC_id, pCCid, tmp; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - slice_info_t *sli = &RC.mac[Mod_id]->slice_info; - eNB_UE_STATS *eNB_UE_stats, *eNB_UE_stats_i, *eNB_UE_stats_j; - int N_RB_DL; - - // clear rb allocations across all CC_id - for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; UE_id++) { - if (UE_list->active[UE_id] != TRUE) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - pCCid = UE_PCCID(Mod_id, UE_id); - - //update CQI information across component carriers - for (n = 0; n < UE_list->numactiveCCs[UE_id]; n++) { - CC_id = UE_list->ordered_CCids[n][UE_id]; - eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id]; - // eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], sli->dl[slice_idx].maxmcs); - eNB_UE_stats->dlsch_mcs1 = cmin(cqi2mcs(UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]), sli->dl[slice_idx].maxmcs); - } - - // provide the list of CCs sorted according to MCS - for (i = 0; i < UE_list->numactiveCCs[UE_id]; ++i) { - eNB_UE_stats_i = &UE_list->eNB_UE_stats[UE_list->ordered_CCids[i][UE_id]][UE_id]; - - for (j = i + 1; j < UE_list->numactiveCCs[UE_id]; j++) { - DevAssert(j < NFAPI_CC_MAX); - eNB_UE_stats_j = &UE_list->eNB_UE_stats[UE_list->ordered_CCids[j][UE_id]][UE_id]; - - if (eNB_UE_stats_j->dlsch_mcs1 > eNB_UE_stats_i->dlsch_mcs1) { - tmp = UE_list->ordered_CCids[i][UE_id]; - UE_list->ordered_CCids[i][UE_id] = UE_list->ordered_CCids[j][UE_id]; - UE_list->ordered_CCids[j][UE_id] = tmp; - } - } - } - - if (UE_list->UE_template[pCCid][UE_id].dl_buffer_total > 0) { - LOG_D(MAC, "[preprocessor] assign RB for UE %d\n", UE_id); - - for (i = 0; i < UE_list->numactiveCCs[UE_id]; i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id]; - - if (eNB_UE_stats->dlsch_mcs1 == 0) { - nb_rbs_required[CC_id][UE_id] = 4; // don't let the TBS get too small - } else { - nb_rbs_required[CC_id][UE_id] = min_rb_unit[CC_id]; - } - - TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, nb_rbs_required[CC_id][UE_id]); - LOG_D(MAC, - "[preprocessor] start RB assignement for UE %d CC_id %d dl buffer %d (RB unit %d, MCS %d, TBS %d) \n", - UE_id, CC_id, - UE_list->UE_template[pCCid][UE_id].dl_buffer_total, - nb_rbs_required[CC_id][UE_id], - eNB_UE_stats->dlsch_mcs1, TBS); - N_RB_DL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); - UE_list->UE_sched_ctrl[UE_id].max_rbs_allowed_slice[CC_id][slice_idx] = - nb_rbs_allowed_slice(sli->dl[slice_idx].pct, N_RB_DL); - - /* calculating required number of RBs for each UE */ - while (TBS < UE_list->UE_template[pCCid][UE_id].dl_buffer_total) { - nb_rbs_required[CC_id][UE_id] += min_rb_unit[CC_id]; - - if (nb_rbs_required[CC_id][UE_id] > UE_list->UE_sched_ctrl[UE_id].max_rbs_allowed_slice[CC_id][slice_idx]) { - TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, UE_list->UE_sched_ctrl[UE_id].max_rbs_allowed_slice[CC_id][slice_idx]); - nb_rbs_required[CC_id][UE_id] = UE_list->UE_sched_ctrl[UE_id].max_rbs_allowed_slice[CC_id][slice_idx]; - break; - } - - TBS = get_TBS_DL(eNB_UE_stats->dlsch_mcs1, nb_rbs_required[CC_id][UE_id]); - } // end of while - - LOG_D(MAC, - "[eNB %d] Frame %d: UE %d on CC %d: RB unit %d, nb_required RB %d (TBS %d, mcs %d)\n", - Mod_id, frameP, UE_id, CC_id, min_rb_unit[CC_id], - nb_rbs_required[CC_id][UE_id], TBS, - eNB_UE_stats->dlsch_mcs1); - sli->pre_processor_results[slice_idx].mcs[CC_id][UE_id] = eNB_UE_stats->dlsch_mcs1; - } - } - } -} - - -// This function scans all CC_ids for a particular UE to find the maximum round index of its HARQ processes -int -maxround(module_id_t Mod_id, uint16_t rnti, int frame, - sub_frame_t subframe) { - uint8_t round, round_max = 0, UE_id; - int CC_id, harq_pid; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - COMMON_channels_t *cc; - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - cc = &RC.mac[Mod_id]->common_channels[CC_id]; - UE_id = find_UE_id(Mod_id, rnti); - - if(UE_id == -1) - continue; - - harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frame,subframe); - round = UE_list->UE_sched_ctrl[UE_id].round[CC_id][harq_pid]; - - if (round > round_max) { - round_max = round; - } - } - - return round_max; -} - -int -maxround_ul(module_id_t Mod_id, uint16_t rnti, int sched_frame, - sub_frame_t sched_subframe) { - uint8_t round, round_max = 0, UE_id; - int CC_id, harq_pid; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - COMMON_channels_t *cc; - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - cc = &RC.mac[Mod_id]->common_channels[CC_id]; - UE_id = find_UE_id(Mod_id, rnti); - - if(UE_id == -1) - continue; - - harq_pid = subframe2harqpid(cc, sched_frame, sched_subframe); - round = UE_list->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid]; - - if (round > round_max) { - round_max = round; - } - } - - return round_max; -} - -// This function scans all CC_ids for a particular UE to find the maximum DL CQI -// it returns -1 if the UE is not found in PHY layer (get_eNB_UE_stats gives NULL) -int maxcqi(module_id_t Mod_id, int32_t UE_id) { - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - int CC_id, n; - int CQI = 0; - - for (n = 0; n < UE_list->numactiveCCs[UE_id]; n++) { - CC_id = UE_list->ordered_CCids[n][UE_id]; - - if (UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id] > CQI) { - CQI = UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; - } - } - - return CQI; -} - -long min_lcgidpriority(module_id_t Mod_id, int32_t UE_id) { - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - int i; - int pCC_id = UE_PCCID(Mod_id, UE_id); - long ret = UE_list->UE_template[pCC_id][UE_id].lcgidpriority[0]; - - for (i = 1; i < 11; ++i) { - if (UE_list->UE_template[pCC_id][UE_id].lcgidpriority[i] < ret) - ret = UE_list->UE_template[pCC_id][UE_id].lcgidpriority[i]; - } - - return ret; -} - -struct sort_ue_dl_params { - int Mod_idP; - int frameP; - int subframeP; - int slice_idx; -}; - -static int ue_dl_compare(const void *_a, const void *_b, void *_params) { - struct sort_ue_dl_params *params = _params; - UE_list_t *UE_list = &RC.mac[params->Mod_idP]->UE_list; - int i; - int slice_idx = params->slice_idx; - int UE_id1 = *(const int *) _a; - int UE_id2 = *(const int *) _b; - int rnti1 = UE_RNTI(params->Mod_idP, UE_id1); - int pCC_id1 = UE_PCCID(params->Mod_idP, UE_id1); - int round1 = maxround(params->Mod_idP, rnti1, params->frameP, params->subframeP); - int rnti2 = UE_RNTI(params->Mod_idP, UE_id2); - int pCC_id2 = UE_PCCID(params->Mod_idP, UE_id2); - int round2 = maxround(params->Mod_idP, rnti2, params->frameP, params->subframeP); - int cqi1 = maxcqi(params->Mod_idP, UE_id1); - int cqi2 = maxcqi(params->Mod_idP, UE_id2); - long lcgid1 = min_lcgidpriority(params->Mod_idP, UE_id1); - long lcgid2 = min_lcgidpriority(params->Mod_idP, UE_id2); - - for (i = 0; i < CR_NUM; ++i) { - switch (UE_list->sorting_criteria[slice_idx][i]) { - case CR_ROUND : - if (round1 > round2) - return -1; - - if (round1 < round2) - return 1; - - break; - - case CR_SRB12 : - if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] + - UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2] > - UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] + - UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2]) - return -1; - - if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] + - UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2] < - UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] + - UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2]) - return 1; - - break; - - case CR_HOL : - if (UE_list-> UE_template[pCC_id1][UE_id1].dl_buffer_head_sdu_creation_time_max > - UE_list-> UE_template[pCC_id2][UE_id2].dl_buffer_head_sdu_creation_time_max) - return -1; - - if (UE_list-> UE_template[pCC_id1][UE_id1].dl_buffer_head_sdu_creation_time_max < - UE_list-> UE_template[pCC_id2][UE_id2].dl_buffer_head_sdu_creation_time_max) - return 1; - - break; - - case CR_LC : - if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total > - UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total) - return -1; - - if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total < - UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total) - return 1; - - break; - - case CR_CQI : - if (cqi1 > cqi2) - return -1; - - if (cqi1 < cqi2) - return 1; - - break; - - case CR_LCP : - if (lcgid1 < lcgid2) - return -1; - - if (lcgid1 > lcgid2) - return 1; - - default : - break; - } - } - - return 0; -} - -void decode_sorting_policy(module_id_t Mod_idP, int slice_idx) { - int i; - UE_list_t *UE_list = &RC.mac[Mod_idP]->UE_list; - uint32_t policy = RC.mac[Mod_idP]->slice_info.dl[slice_idx].sorting; - uint32_t mask = 0x0000000F; - uint16_t criterion; - - for (i = 0; i < CR_NUM; ++i) { - criterion = (uint16_t) (policy >> 4 * (CR_NUM - 1 - i) & mask); - - if (criterion >= CR_NUM) { - LOG_W(MAC, - "Invalid criterion in slice index %d ID %d policy, revert to default policy \n", - slice_idx, RC.mac[Mod_idP]->slice_info.dl[slice_idx].id); - RC.mac[Mod_idP]->slice_info.dl[slice_idx].sorting = 0x12345; - break; - } - - UE_list->sorting_criteria[slice_idx][i] = criterion; - } -} - -void decode_slice_positioning(module_id_t Mod_idP, - int slice_idx, - uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX]) { - uint8_t CC_id; - int RBG, start_frequency, end_frequency; - - // Init slice_alloc_mask - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_idP]; ++CC_id) { - for (RBG = 0; RBG < N_RBG_MAX; ++RBG) { - slice_allocation_mask[CC_id][RBG] = 0; - } - } - - start_frequency = RC.mac[Mod_idP]->slice_info.dl[slice_idx].pos_low; - end_frequency = RC.mac[Mod_idP]->slice_info.dl[slice_idx].pos_high; - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_idP]; ++CC_id) { - for (RBG = start_frequency; RBG <= end_frequency; ++RBG) { - slice_allocation_mask[CC_id][RBG] = 1; - } - } -} - -//----------------------------------------------------------------------------- -/* - * This function sorts the UEs in order, depending on their dlsch buffer and CQI - */ -void sort_UEs(module_id_t Mod_idP, - int slice_idx, - int frameP, - sub_frame_t subframeP) -//----------------------------------------------------------------------------- -{ - int list[MAX_MOBILES_PER_ENB]; - int list_size = 0; - struct sort_ue_dl_params params = {Mod_idP, frameP, subframeP, slice_idx}; - UE_list_t *UE_list = &(RC.mac[Mod_idP]->UE_list); - UE_sched_ctrl_t *UE_scheduling_control = NULL; - - for (int i = 0; i < MAX_MOBILES_PER_ENB; i++) { - UE_scheduling_control = &(UE_list->UE_sched_ctrl[i]); - - /* Check CDRX configuration and if UE is in active time for this subframe */ - if (UE_scheduling_control->cdrx_configured == TRUE) { - if (UE_scheduling_control->in_active_time == FALSE) { - continue; - } - } - - if (UE_list->active[i] == TRUE && - UE_RNTI(Mod_idP, i) != NOT_A_RNTI && - UE_list->UE_sched_ctrl[i].ul_out_of_sync != 1 && - ue_dl_slice_membership(Mod_idP, i, slice_idx)) { - list[list_size++] = i; - } - } - - decode_sorting_policy(Mod_idP, slice_idx); - qsort_r(list, list_size, sizeof(int), ue_dl_compare, ¶ms); - - if (list_size) { - for (int i = 0; i < list_size - 1; ++i) { - UE_list->next[list[i]] = list[i + 1]; - } - - UE_list->next[list[list_size - 1]] = -1; - UE_list->head = list[0]; - } else { - UE_list->head = -1; - } -} - -void dlsch_scheduler_pre_processor_partitioning(module_id_t Mod_id, - int slice_idx, - const uint8_t rbs_retx[NFAPI_CC_MAX]) { - int UE_id, CC_id, N_RB_DL, i; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - UE_sched_ctrl_t *ue_sched_ctl; - uint16_t available_rbs; - - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - if (UE_RNTI(Mod_id, UE_id) == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); ++i) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - N_RB_DL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); - available_rbs = nb_rbs_allowed_slice(RC.mac[Mod_id]->slice_info.dl[slice_idx].pct, N_RB_DL); - - if (rbs_retx[CC_id] < available_rbs) - ue_sched_ctl->max_rbs_allowed_slice[CC_id][slice_idx] = available_rbs - rbs_retx[CC_id]; - else - ue_sched_ctl->max_rbs_allowed_slice[CC_id][slice_idx] = 0; - } - } -} - -void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, - int slice_idx, - frame_t frameP, - sub_frame_t subframeP, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]) { - int UE_id, CC_id; - int i; - rnti_t rnti; - uint8_t harq_pid, round; - uint16_t available_rbs[NFAPI_CC_MAX]; - uint8_t rbs_retx[NFAPI_CC_MAX]; - uint16_t average_rbs_per_user[NFAPI_CC_MAX]; - int total_ue_count[NFAPI_CC_MAX]; - int ue_count_newtx[NFAPI_CC_MAX]; - int ue_count_retx[NFAPI_CC_MAX]; - //uint8_t ue_retx_flag[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - UE_sched_ctrl_t *ue_sched_ctl; - COMMON_channels_t *cc; - - // Reset - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - total_ue_count[CC_id] = 0; - ue_count_newtx[CC_id] = 0; - ue_count_retx[CC_id] = 0; - rbs_retx[CC_id] = 0; - average_rbs_per_user[CC_id] = 0; - available_rbs[CC_id] = 0; - //for (UE_id = 0; UE_id < NFAPI_CC_MAX; ++UE_id) { - // ue_retx_flag[CC_id][UE_id] = 0; - //} - } - - // Find total UE count, and account the RBs required for retransmissions - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - rnti = UE_RNTI(Mod_id, UE_id); - - if (rnti == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); ++i) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - cc = &RC.mac[Mod_id]->common_channels[CC_id]; - harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP,subframeP); - round = ue_sched_ctl->round[CC_id][harq_pid]; - - if (nb_rbs_required[CC_id][UE_id] > 0) { - total_ue_count[CC_id]++; - } - - if (round != 8) { - nb_rbs_required[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid]; - rbs_retx[CC_id] += nb_rbs_required[CC_id][UE_id]; - ue_count_retx[CC_id]++; - //ue_retx_flag[CC_id][UE_id] = 1; - } else { - ue_count_newtx[CC_id]++; - } - } - } - - // PARTITIONING - // Reduces the available RBs according to slicing configuration - dlsch_scheduler_pre_processor_partitioning(Mod_id, slice_idx, rbs_retx); - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; ++CC_id) { - if (UE_list->head < 0) continue; // no UEs in list - - // max_rbs_allowed_slice is saved in every UE, so take it from the first one - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_list->head]; - available_rbs[CC_id] = ue_sched_ctl->max_rbs_allowed_slice[CC_id][slice_idx]; - } - - switch (RC.mac[Mod_id]->slice_info.dl[slice_idx].accounting) { - // If greedy scheduling, try to account all the required RBs - case POL_GREEDY: - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - rnti = UE_RNTI(Mod_id, UE_id); - - if (rnti == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - - if (available_rbs[CC_id] == 0) continue; - - nb_rbs_accounted[CC_id][UE_id] = cmin(nb_rbs_required[CC_id][UE_id], available_rbs[CC_id]); - available_rbs[CC_id] -= nb_rbs_accounted[CC_id][UE_id]; - } - } - - break; - - // Use the old, fair algorithm - // Loop over all active UEs and account the avg number of RBs to each UE, based on all non-retx UEs. - // case POL_FAIR: - default: - - // FIXME: This is not ideal, why loop on UEs to find average_rbs_per_user[], that is per-CC? - // TODO: Look how to loop on active CCs only without using the UE_num_active_CC() function. - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - rnti = UE_RNTI(Mod_id, UE_id); - - if (rnti == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); ++i) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - available_rbs[CC_id] = ue_sched_ctl->max_rbs_allowed_slice[CC_id][slice_idx]; - - if (ue_count_newtx[CC_id] == 0) { - average_rbs_per_user[CC_id] = 0; - } else if (min_rb_unit[CC_id]*ue_count_newtx[CC_id] <= available_rbs[CC_id]) { - average_rbs_per_user[CC_id] = (uint16_t)floor(available_rbs[CC_id]/ue_count_newtx[CC_id]); - } else { - // consider the total number of use that can be scheduled UE - average_rbs_per_user[CC_id] = (uint16_t)min_rb_unit[CC_id]; - } - } - } - - // note: nb_rbs_required is assigned according to total_buffer_dl - // extend nb_rbs_required to capture per LCID RB required - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - rnti = UE_RNTI(Mod_id, UE_id); - - if (rnti == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - nb_rbs_accounted[CC_id][UE_id] = cmin(average_rbs_per_user[CC_id], nb_rbs_required[CC_id][UE_id]); - } - } - - break; - } - - // Check retransmissions - // TODO: Do this once at the beginning - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - rnti = UE_RNTI(Mod_id, UE_id); - - if (rnti == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - cc = &RC.mac[Mod_id]->common_channels[CC_id]; - harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP,subframeP); - round = ue_sched_ctl->round[CC_id][harq_pid]; - - // control channel or retransmission - /* TODO: do we have to check for retransmission? */ - if (mac_eNB_get_rrc_status(Mod_id, rnti) < RRC_RECONFIGURED || round != 8) { - nb_rbs_accounted[CC_id][UE_id] = nb_rbs_required[CC_id][UE_id]; - } - } - } -} - -void dlsch_scheduler_pre_processor_positioning(module_id_t Mod_id, - int slice_idx, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]) { - int UE_id, CC_id; - int i; -#ifdef TM5 - uint8_t transmission_mode; -#endif - uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX]; - int N_RBG[NFAPI_CC_MAX]; - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - decode_slice_positioning(Mod_id, slice_idx, slice_allocation_mask); - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; - N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth); - } - - // Try to allocate accounted RBs - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - if (UE_RNTI(Mod_id, UE_id) == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - nb_rbs_remaining[CC_id][UE_id] = nb_rbs_accounted[CC_id][UE_id]; -#ifdef TM5 - transmission_mode = get_tmode(Mod_id, CC_id, UE_id); -#endif - - if (nb_rbs_required[CC_id][UE_id] > 0) - LOG_D(MAC, - "Step 1: nb_rbs_remaining[%d][%d]= %d (accounted %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n", - CC_id, - UE_id, - nb_rbs_remaining[CC_id][UE_id], - nb_rbs_accounted[CC_id][UE_id], - nb_rbs_required[CC_id][UE_id], - UE_list->UE_sched_ctrl[UE_id].pre_nb_available_rbs[CC_id], - N_RBG[CC_id], - min_rb_unit[CC_id]); - - LOG_T(MAC, "calling dlsch_scheduler_pre_processor_allocate .. \n "); - dlsch_scheduler_pre_processor_allocate(Mod_id, - UE_id, - CC_id, - N_RBG[CC_id], - min_rb_unit[CC_id], - nb_rbs_required, - nb_rbs_remaining, - rballoc_sub, - slice_allocation_mask, - MIMO_mode_indicator); -#ifdef TM5 - - // data chanel TM5: to be revisited - if ((round == 0) && - (transmission_mode == 5) && - (ue_sched_ctl->dl_pow_off[CC_id] != 1)) { - for (j = 0; j < N_RBG[CC_id]; j += 2) { - if ((((j == (N_RBG[CC_id] - 1)) - && (rballoc_sub[CC_id][j] == 0) - && (ue_sched_ctl-> - rballoc_sub_UE[CC_id][j] == 0)) - || ((j < (N_RBG[CC_id] - 1)) - && (rballoc_sub[CC_id][j + 1] == 0) - && - (ue_sched_ctl->rballoc_sub_UE - [CC_id][j + 1] == 0))) - && (nb_rbs_remaining[CC_id][UE_id] - > 0)) { - for (i = UE_list->next[UE_id + 1]; i >= 0; - i = UE_list->next[i]) { - UE_id2 = i; - rnti2 = UE_RNTI(Mod_id, UE_id2); - ue_sched_ctl2 = - &UE_list->UE_sched_ctrl[UE_id2]; - round2 = ue_sched_ctl2->round[CC_id]; - - if (rnti2 == NOT_A_RNTI) - continue; - - if (UE_list-> - UE_sched_ctrl - [UE_id2].ul_out_of_sync == 1) - continue; - - eNB_UE_stats2 = - UE_list-> - eNB_UE_stats[CC_id][UE_id2]; - //mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti2,frameP,subframeP,&harq_pid2,&round2,0); - - if ((mac_eNB_get_rrc_status - (Mod_id, - rnti2) >= RRC_RECONFIGURED) - && (round2 == 0) - && - (get_tmode(Mod_id, CC_id, UE_id2) - == 5) - && (ue_sched_ctl-> - dl_pow_off[CC_id] != 1)) { - if ((((j == (N_RBG[CC_id] - 1)) - && - (ue_sched_ctl->rballoc_sub_UE - [CC_id][j] == 0)) - || ((j < (N_RBG[CC_id] - 1)) - && - (ue_sched_ctl-> - rballoc_sub_UE[CC_id][j + - 1] - == 0))) - && - (nb_rbs_remaining - [CC_id] - [UE_id2] > 0)) { - if ((((eNB_UE_stats2-> - DL_pmi_single ^ - eNB_UE_stats1-> - DL_pmi_single) - << (14 - j)) & 0xc000) == 0x4000) { //MU-MIMO only for 25 RBs configuration - rballoc_sub[CC_id][j] = 1; - ue_sched_ctl-> - rballoc_sub_UE[CC_id] - [j] = 1; - ue_sched_ctl2-> - rballoc_sub_UE[CC_id] - [j] = 1; - MIMO_mode_indicator[CC_id] - [j] = 0; - - if (j < N_RBG[CC_id] - 1) { - rballoc_sub[CC_id][j + - 1] = - 1; - ue_sched_ctl-> - rballoc_sub_UE - [CC_id][j + 1] = 1; - ue_sched_ctl2->rballoc_sub_UE - [CC_id][j + 1] = 1; - MIMO_mode_indicator - [CC_id][j + 1] - = 0; - } - - ue_sched_ctl-> - dl_pow_off[CC_id] - = 0; - ue_sched_ctl2-> - dl_pow_off[CC_id] - = 0; - - if ((j == N_RBG[CC_id] - 1) - && ((N_RB_DL == 25) - || (N_RB_DL == - 50))) { - nb_rbs_remaining - [CC_id][UE_id] = - nb_rbs_remaining - [CC_id][UE_id] - - min_rb_unit[CC_id] - + 1; - ue_sched_ctl->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl->pre_nb_available_rbs - [CC_id] + - min_rb_unit[CC_id] - - 1; - nb_rbs_remaining - [CC_id][UE_id2] = - nb_rbs_remaining - [CC_id][UE_id2] - - min_rb_unit[CC_id] - + 1; - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] + - min_rb_unit[CC_id] - - 1; - } else { - nb_rbs_remaining - [CC_id][UE_id] = - nb_rbs_remaining - [CC_id][UE_id] - 4; - ue_sched_ctl->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl->pre_nb_available_rbs - [CC_id] + 4; - nb_rbs_remaining - [CC_id][UE_id2] = - nb_rbs_remaining - [CC_id][UE_id2] - - 4; - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] + 4; - } - - break; - } - } - } - } - } - } - } - -#endif - } - } -} - -void dlsch_scheduler_pre_processor_intraslice_sharing(module_id_t Mod_id, - int slice_idx, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_accounted[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]) { - int UE_id, CC_id; - int i; -#ifdef TM5 - uint8_t transmission_mode; -#endif - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - int N_RBG[NFAPI_CC_MAX]; - slice_info_t *sli = &RC.mac[Mod_id]->slice_info; - uint8_t (*slice_allocation_mask)[N_RBG_MAX] = sli->pre_processor_results[slice_idx].slice_allocation_mask; - decode_slice_positioning(Mod_id, slice_idx, slice_allocation_mask); - - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; - N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth); - } - - // Remaining RBs are allocated to high priority UEs - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - if (UE_RNTI(Mod_id, UE_id) == NOT_A_RNTI) continue; - - if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue; - - if (!ue_dl_slice_membership(Mod_id, UE_id, slice_idx)) continue; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - nb_rbs_remaining[CC_id][UE_id] = - nb_rbs_required[CC_id][UE_id] - nb_rbs_accounted[CC_id][UE_id] + nb_rbs_remaining[CC_id][UE_id]; - - if (nb_rbs_remaining[CC_id][UE_id] < 0) - abort(); - -#ifdef TM5 - transmission_mode = get_tmode(Mod_id, CC_id, UE_id); -#endif - - if (nb_rbs_required[CC_id][UE_id] > 0) - LOG_D(MAC, - "Step 2: nb_rbs_remaining[%d][%d]= %d (accounted %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n", - CC_id, - UE_id, - nb_rbs_remaining[CC_id][UE_id], - nb_rbs_accounted[CC_id][UE_id], - nb_rbs_required[CC_id][UE_id], - UE_list->UE_sched_ctrl[UE_id].pre_nb_available_rbs[CC_id], - N_RBG[CC_id], - min_rb_unit[CC_id]); - - LOG_T(MAC, "calling dlsch_scheduler_pre_processor_allocate .. \n "); - dlsch_scheduler_pre_processor_allocate(Mod_id, - UE_id, - CC_id, - N_RBG[CC_id], - min_rb_unit[CC_id], - nb_rbs_required, - nb_rbs_remaining, - rballoc_sub, - slice_allocation_mask, - MIMO_mode_indicator); -#ifdef TM5 - - // data chanel TM5: to be revisited - if ((round == 0) && - (transmission_mode == 5) && - (ue_sched_ctl->dl_pow_off[CC_id] != 1)) { - for (j = 0; j < N_RBG[CC_id]; j += 2) { - if ((((j == (N_RBG[CC_id] - 1)) - && (rballoc_sub[CC_id][j] == 0) - && (ue_sched_ctl-> - rballoc_sub_UE[CC_id][j] == 0)) - || ((j < (N_RBG[CC_id] - 1)) - && (rballoc_sub[CC_id][j + 1] == 0) - && - (ue_sched_ctl->rballoc_sub_UE - [CC_id][j + 1] == 0))) - && (nb_rbs_remaining[CC_id][UE_id] - > 0)) { - for (i = UE_list->next[UE_id + 1]; i >= 0; - i = UE_list->next[i]) { - UE_id2 = i; - rnti2 = UE_RNTI(Mod_id, UE_id2); - ue_sched_ctl2 = - &UE_list->UE_sched_ctrl[UE_id2]; - round2 = ue_sched_ctl2->round[CC_id]; - - if (rnti2 == NOT_A_RNTI) - continue; - - if (UE_list-> - UE_sched_ctrl - [UE_id2].ul_out_of_sync == 1) - continue; - - eNB_UE_stats2 = - UE_list-> - eNB_UE_stats[CC_id][UE_id2]; - //mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti2,frameP,subframeP,&harq_pid2,&round2,0); - - if ((mac_eNB_get_rrc_status - (Mod_id, - rnti2) >= RRC_RECONFIGURED) - && (round2 == 0) - && - (get_tmode(Mod_id, CC_id, UE_id2) - == 5) - && (ue_sched_ctl-> - dl_pow_off[CC_id] != 1)) { - if ((((j == (N_RBG[CC_id] - 1)) - && - (ue_sched_ctl->rballoc_sub_UE - [CC_id][j] == 0)) - || ((j < (N_RBG[CC_id] - 1)) - && - (ue_sched_ctl-> - rballoc_sub_UE[CC_id][j + - 1] - == 0))) - && - (nb_rbs_remaining - [CC_id] - [UE_id2] > 0)) { - if ((((eNB_UE_stats2-> - DL_pmi_single ^ - eNB_UE_stats1-> - DL_pmi_single) - << (14 - j)) & 0xc000) == 0x4000) { //MU-MIMO only for 25 RBs configuration - rballoc_sub[CC_id][j] = 1; - ue_sched_ctl-> - rballoc_sub_UE[CC_id] - [j] = 1; - ue_sched_ctl2-> - rballoc_sub_UE[CC_id] - [j] = 1; - MIMO_mode_indicator[CC_id] - [j] = 0; - - if (j < N_RBG[CC_id] - 1) { - rballoc_sub[CC_id][j + - 1] = - 1; - ue_sched_ctl-> - rballoc_sub_UE - [CC_id][j + 1] = 1; - ue_sched_ctl2->rballoc_sub_UE - [CC_id][j + 1] = 1; - MIMO_mode_indicator - [CC_id][j + 1] - = 0; - } - - ue_sched_ctl-> - dl_pow_off[CC_id] - = 0; - ue_sched_ctl2-> - dl_pow_off[CC_id] - = 0; - - if ((j == N_RBG[CC_id] - 1) - && ((N_RB_DL == 25) - || (N_RB_DL == - 50))) { - nb_rbs_remaining - [CC_id][UE_id] = - nb_rbs_remaining - [CC_id][UE_id] - - min_rb_unit[CC_id] - + 1; - ue_sched_ctl->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl->pre_nb_available_rbs - [CC_id] + - min_rb_unit[CC_id] - - 1; - nb_rbs_remaining - [CC_id][UE_id2] = - nb_rbs_remaining - [CC_id][UE_id2] - - min_rb_unit[CC_id] - + 1; - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] + - min_rb_unit[CC_id] - - 1; - } else { - nb_rbs_remaining - [CC_id][UE_id] = - nb_rbs_remaining - [CC_id][UE_id] - 4; - ue_sched_ctl->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl->pre_nb_available_rbs - [CC_id] + 4; - nb_rbs_remaining - [CC_id][UE_id2] = - nb_rbs_remaining - [CC_id][UE_id2] - - 4; - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] = - ue_sched_ctl2->pre_nb_available_rbs - [CC_id] + 4; - } - - break; - } - } - } - } - } - } - } - -#endif - } - } -} // This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done void dlsch_scheduler_pre_processor(module_id_t Mod_id, - int slice_idx, + int CC_id, frame_t frameP, - sub_frame_t subframeP, - int *mbsfn_flag, - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]) { - int UE_id; - uint8_t CC_id; - uint16_t i, j; - int min_rb_unit[NFAPI_CC_MAX]; - eNB_MAC_INST *eNB = RC.mac[Mod_id]; - slice_info_t *sli = &eNB->slice_info; - uint16_t (*nb_rbs_required)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_required; - uint16_t (*nb_rbs_accounted)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_accounted; - uint16_t (*nb_rbs_remaining)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_remaining; - uint8_t (*MIMO_mode_indicator)[N_RBG_MAX] = sli->pre_processor_results[slice_idx].MIMO_mode_indicator; - UE_list_t *UE_list = &eNB->UE_list; - UE_sched_ctrl_t *ue_sched_ctl; - // int rrc_status = RRC_IDLE; -#ifdef TM5 - int harq_pid1 = 0; - int round1 = 0, round2 = 0; - int UE_id2; - uint16_t i1, i2, i3; - rnti_t rnti1, rnti2; - LTE_eNB_UE_stats *eNB_UE_stats1 = NULL; - LTE_eNB_UE_stats *eNB_UE_stats2 = NULL; - UE_sched_ctrl_t *ue_sched_ctl1, *ue_sched_ctl2; -#endif - // Initialize scheduling information for all active UEs - memset(&sli->pre_processor_results[slice_idx], 0, sizeof(sli->pre_processor_results[slice_idx])); - // FIXME: After the memset above, some of the resets in reset() are redundant - dlsch_scheduler_pre_processor_reset(Mod_id, - slice_idx, - frameP, - subframeP, - min_rb_unit, - nb_rbs_required, - rballoc_sub, - MIMO_mode_indicator, - mbsfn_flag); // FIXME: Not sure if useful - // STATUS - // Store the DLSCH buffer for each logical channel - store_dlsch_buffer(Mod_id, - slice_idx, - frameP, - subframeP); - // Calculate the number of RBs required by each UE on the basis of logical channel's buffer - assign_rbs_required(Mod_id, - slice_idx, - frameP, - subframeP, - nb_rbs_required, - min_rb_unit); - // Sorts the user on the basis of dlsch logical channel buffer and CQI - sort_UEs(Mod_id, - slice_idx, - frameP, - subframeP); - // ACCOUNTING - // This procedure decides the number of RBs to allocate - dlsch_scheduler_pre_processor_accounting(Mod_id, - slice_idx, - frameP, - subframeP, - min_rb_unit, - nb_rbs_required, - nb_rbs_accounted); - // POSITIONING - // This procedure does the main allocation of the RBs - dlsch_scheduler_pre_processor_positioning(Mod_id, - slice_idx, - min_rb_unit, - nb_rbs_required, - nb_rbs_accounted, - nb_rbs_remaining, - rballoc_sub, - MIMO_mode_indicator); + sub_frame_t subframeP) { + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); - // SHARING - // If there are available RBs left in the slice, allocate them to the highest priority UEs - if (eNB->slice_info.intraslice_share_active) { - dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, - slice_idx, - min_rb_unit, - nb_rbs_required, - nb_rbs_accounted, - nb_rbs_remaining, - rballoc_sub, - MIMO_mode_indicator); - } + store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP); -#ifdef TM5 + UE_list_t UE_to_sched; + UE_to_sched.head = -1; + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + UE_to_sched.next[i] = -1; - // This has to be revisited!!!! - for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { - COMMON_channels_t *cc = &eNB->common_channels[CC_id]; - int N_RBG = to_rbg(cc->mib->message.dl_Bandwidth); - i1 = 0; - i2 = 0; - i3 = 0; + int first = 1; + int last_UE_id = -1; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; - for (j = 0; j < N_RBG; j++) { - if (MIMO_mode_indicator[CC_id][j] == 2) { - i1++; - } else if (MIMO_mode_indicator[CC_id][j] == 1) { - i2++; - } else if (MIMO_mode_indicator[CC_id][j] == 0) { - i3++; - } + /* initialize per-UE scheduling information */ + ue_sched_ctrl->pre_nb_available_rbs[CC_id] = 0; + ue_sched_ctrl->dl_pow_off[CC_id] = 2; + memset(ue_sched_ctrl->rballoc_sub_UE[CC_id], 0, sizeof(ue_sched_ctrl->rballoc_sub_UE[CC_id])); + ue_sched_ctrl->pre_dci_dl_pdu_idx = -1; + + const rnti_t rnti = UE_RNTI(Mod_id, UE_id); + if (rnti == NOT_A_RNTI) { + LOG_E(MAC, "UE %d has RNTI NOT_A_RNTI!\n", UE_id); + continue; + } + if (UE_info->active[UE_id] != TRUE) { + LOG_E(MAC, "UE %d RNTI %x is NOT active!\n", UE_id, rnti); + continue; + } + if (ue_template->rach_resource_type > 0) { + LOG_D(MAC, + "UE %d is RACH resource type %d\n", + UE_id, + ue_template->rach_resource_type); + continue; + } + if (mac_eNB_get_rrc_status(Mod_id, rnti) < RRC_CONNECTED) { + LOG_D(MAC, "UE %d is not in RRC_CONNECTED\n", UE_id); + continue; } - if (i1 < N_RBG) { - if (i2 > 0 && i3 == 0) { - PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions + 1; - } else if (i3 > 0) { - PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions + 1; - } - } else if (i3 == N_RBG && i1 == 0 && i2 == 0) { - PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions + 1; + /* define UEs to schedule */ + if (first) { + first = 0; + UE_to_sched.head = UE_id; + } else { + UE_to_sched.next[last_UE_id] = UE_id; } - - PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions + 1; + UE_to_sched.next[UE_id] = -1; + last_UE_id = UE_id; } -#endif + if (UE_to_sched.head < 0) + return; - for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - - for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { - CC_id = UE_list->ordered_CCids[i][UE_id]; - //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].dl_pow_off = dl_pow_off[UE_id]; - COMMON_channels_t *cc = &eNB->common_channels[CC_id]; - int N_RBG = to_rbg(cc->mib->message.dl_Bandwidth); - - if (ue_sched_ctl->pre_nb_available_rbs[CC_id] > 0) { - LOG_D(MAC, "******************DL Scheduling Information for UE%d ************************\n", - UE_id); - LOG_D(MAC, "dl power offset UE%d = %d \n", - UE_id, - ue_sched_ctl->dl_pow_off[CC_id]); - LOG_D(MAC, "***********RB Alloc for every subband for UE%d ***********\n", - UE_id); - - for (j = 0; j < N_RBG; j++) { - //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[UE_id] = rballoc_sub_UE[CC_id][UE_id][UE_id]; - LOG_D(MAC, "RB Alloc for UE%d and Subband%d = %d\n", - UE_id, j, - ue_sched_ctl->rballoc_sub_UE[CC_id][j]); - } - - //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].pre_nb_available_rbs = pre_nb_available_rbs[CC_id][UE_id]; - LOG_D(MAC, "[eNB %d][SLICE %d]Total RBs allocated for UE%d = %d\n", - Mod_id, - eNB->slice_info.dl[slice_idx].id, - UE_id, - ue_sched_ctl->pre_nb_available_rbs[CC_id]); - } - } + uint8_t *vrb_map = RC.mac[Mod_id]->common_channels[CC_id].vrb_map; + uint8_t rbgalloc_mask[N_RBG_MAX]; + int n_rbg_sched = 0; + for (int i = 0; i < N_RBG; i++) { + // calculate mask: init to one + "AND" with vrb_map: + // if any RB in vrb_map is blocked (1), the current RBG will be 0 + rbgalloc_mask[i] = 1; + for (int j = 0; j < RBGsize; j++) + rbgalloc_mask[i] &= !vrb_map[RBGsize * i + j]; + n_rbg_sched += rbgalloc_mask[i]; } -} -#define SF0_LIMIT 1 + round_robin_dl(Mod_id, + CC_id, + frameP, + subframeP, + &UE_to_sched, + 4, // max_num_ue + n_rbg_sched, + rbgalloc_mask); -void -dlsch_scheduler_pre_processor_reset(module_id_t module_idP, - int slice_idx, - frame_t frameP, - sub_frame_t subframeP, - int min_rb_unit[NFAPI_CC_MAX], - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX], - int *mbsfn_flag) { - int UE_id; - uint8_t CC_id; - int i, j; - UE_list_t *UE_list; - UE_sched_ctrl_t *ue_sched_ctl; - int N_RB_DL, RBGsize, RBGsize_last; - int N_RBG[NFAPI_CC_MAX]; -#ifdef SF0_LIMIT - int sf0_lower, sf0_upper; -#endif - rnti_t rnti; - uint8_t *vrb_map; - COMMON_channels_t *cc; + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality +#ifdef DEBUG_eNB_SCHEDULER + char t[26] = "_________________________"; + t[N_RBG] = 0; + for (int i = 0; i < N_RBG; i++) + for (int j = 0; j < RBGsize; j++) + if (vrb_map[RBGsize*i+j] != 0) + t[i] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + const UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; - // - for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) { - // initialize harq_pid and round - cc = &RC.mac[module_idP]->common_channels[CC_id]; - N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth); - min_rb_unit[CC_id] = get_min_rb_unit(module_idP, CC_id); - - if (mbsfn_flag[CC_id] > 0) // If this CC is allocated for MBSFN skip it here + if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0) continue; - for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; ++UE_id) { - UE_list = &RC.mac[module_idP]->UE_list; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - rnti = UE_RNTI(module_idP, UE_id); + LOG_D(MAC, + "%4d.%d UE%d %d RBs allocated, pre MCS %d\n", + frameP, + subframeP, + UE_id, + ue_sched_ctrl->pre_nb_available_rbs[CC_id], + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1); - if (rnti == NOT_A_RNTI) + print = 1; + + for (int i = 0; i < N_RBG; i++) { + if (!ue_sched_ctrl->rballoc_sub_UE[CC_id][i]) continue; - - if (UE_list->active[UE_id] != TRUE) - continue; - - if (!ue_dl_slice_membership(module_idP, UE_id, slice_idx)) - continue; - - LOG_D(MAC, "Running preprocessor for UE %d (%x)\n", UE_id, rnti); - - // initialize harq_pid and round - if (ue_sched_ctl->ta_timer) - ue_sched_ctl->ta_timer--; - - /* - eNB_UE_stats *eNB_UE_stats; - - if (eNB_UE_stats == NULL) - return; - - - mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti, - frameP,subframeP, - &ue_sched_ctl->harq_pid[CC_id], - &ue_sched_ctl->round[CC_id], - openair_harq_DL); - - - if (ue_sched_ctl->ta_timer == 0) { - - // WE SHOULD PROTECT the eNB_UE_stats with a mutex here ... - - ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY - switch (N_RB_DL) { - case 6: - ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update; - break; - - case 15: - ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2; - break; - - case 25: - ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4; - break; - - case 50: - ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8; - break; - - case 75: - ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12; - break; - - case 100: - ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16; - break; - } - // clear the update in case PHY does not have a new measurement after timer expiry - eNB_UE_stats->timing_advance_update = 0; - } - else { - ue_sched_ctl->ta_timer--; - ue_sched_ctl->ta_update =0; // don't trigger a timing advance command - } - - - if (UE_id==0) { - VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update); - } - */ - nb_rbs_required[CC_id][UE_id] = 0; - ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0; - ue_sched_ctl->dl_pow_off[CC_id] = 2; - - for (i = 0; i < N_RBG[CC_id]; i++) { - ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0; - } - } - - N_RB_DL = to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth); -#ifdef SF0_LIMIT - - switch (N_RBG[CC_id]) { - case 6: - sf0_lower = 0; - sf0_upper = 5; - break; - - case 8: - sf0_lower = 2; - sf0_upper = 5; - break; - - case 13: - sf0_lower = 4; - sf0_upper = 7; - break; - - case 17: - sf0_lower = 7; - sf0_upper = 9; - break; - - case 25: - sf0_lower = 11; - sf0_upper = 13; - break; - - default: - AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL); - } - -#endif - - switch (N_RB_DL) { - case 6: - RBGsize = 1; - RBGsize_last = 1; - break; - - case 15: - RBGsize = 2; - RBGsize_last = 1; - break; - - case 25: - RBGsize = 2; - RBGsize_last = 1; - break; - - case 50: - RBGsize = 3; - RBGsize_last = 2; - break; - - case 75: - RBGsize = 4; - RBGsize_last = 3; - break; - - case 100: - RBGsize = 4; - RBGsize_last = 4; - break; - - default: - AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL); - } - - vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map; - - // Initialize Subbands according to VRB map - for (i = 0; i < N_RBG[CC_id]; i++) { - int rb_size = i == N_RBG[CC_id] - 1 ? RBGsize_last : RBGsize; -#ifdef SF0_LIMIT - - // for avoiding 6+ PRBs around DC in subframe 0 (avoid excessive errors) - /* TODO: make it proper - allocate those RBs, do not "protect" them, but - * compute number of available REs and limit MCS according to the - * TBS table 36.213 7.1.7.2.1-1 (can be done after pre-processor) - */ - if (subframeP == 0 && i >= sf0_lower && i <= sf0_upper) - rballoc_sub[CC_id][i] = 1; - -#endif - - // for SI-RNTI,RA-RNTI and P-RNTI allocations - for (j = 0; j < rb_size; j++) { - if (vrb_map[j + (i*RBGsize)] != 0) { - rballoc_sub[CC_id][i] = 1; - LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n", frameP, subframeP, j + (i*RBGsize)); - break; + for (int j = 0; j < RBGsize; j++) { + if (vrb_map[RBGsize*i+j] != 0) { + LOG_I(MAC, "%4d.%d DL scheduler allocation list: %s\n", frameP, subframeP, t); + LOG_E(MAC, "%4d.%d: UE %d allocated at locked RB %d/RBG %d\n", frameP, + subframeP, UE_id, RBGsize * i + j, i); } + vrb_map[RBGsize*i+j] = 1; } - - //LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n", - //frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]); - MIMO_mode_indicator[CC_id][i] = 2; + t[i] = '0' + UE_id; } } + if (print) + LOG_D(MAC, "%4d.%d DL scheduler allocation list: %s\n", frameP, subframeP, t); +#endif } - -void -dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id, - int UE_id, - uint8_t CC_id, - int N_RBG, - int min_rb_unit, - uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint16_t nb_rbs_remaining[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB], - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX], - uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]) { - int i; - int tm = get_tmode(Mod_id, CC_id, UE_id); - UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list; - UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - int N_RB_DL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); - - for (i = 0; i < N_RBG; i++) { - if (rballoc_sub[CC_id][i] != 0) continue; - - if (ue_sched_ctl->rballoc_sub_UE[CC_id][i] != 0) continue; - - if (nb_rbs_remaining[CC_id][UE_id] <= 0) continue; - - if (ue_sched_ctl->pre_nb_available_rbs[CC_id] >= nb_rbs_required[CC_id][UE_id]) continue; - - if (ue_sched_ctl->dl_pow_off[CC_id] == 0) continue; - - if (slice_allocation_mask[CC_id][i] == 0) continue; - - if ((i == N_RBG - 1) && ((N_RB_DL == 25) || (N_RB_DL == 50))) { - // Allocating last, smaller RBG - if (nb_rbs_remaining[CC_id][UE_id] >= min_rb_unit - 1) { - rballoc_sub[CC_id][i] = 1; - ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 1; - MIMO_mode_indicator[CC_id][i] = 1; - - if (tm == 5) { - ue_sched_ctl->dl_pow_off[CC_id] = 1; - } - - nb_rbs_remaining[CC_id][UE_id] = nb_rbs_remaining[CC_id][UE_id] - min_rb_unit + 1; - ue_sched_ctl->pre_nb_available_rbs[CC_id] = ue_sched_ctl->pre_nb_available_rbs[CC_id] + min_rb_unit - 1; - } - } else { - // Allocating a standard-sized RBG - if (nb_rbs_remaining[CC_id][UE_id] >= min_rb_unit) { - rballoc_sub[CC_id][i] = 1; - ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 1; - MIMO_mode_indicator[CC_id][i] = 1; - - if (tm == 5) { - ue_sched_ctl->dl_pow_off[CC_id] = 1; - } - - nb_rbs_remaining[CC_id][UE_id] = nb_rbs_remaining[CC_id][UE_id] - min_rb_unit; - ue_sched_ctl->pre_nb_available_rbs[CC_id] = ue_sched_ctl->pre_nb_available_rbs[CC_id] + min_rb_unit; - } - } - } -} - - /// ULSCH PRE_PROCESSOR -void ulsch_scheduler_pre_processor(module_id_t module_idP, - int slice_idx, +void calculate_max_mcs_min_rb(module_id_t mod_id, + int CC_id, + int bytes, + int phr, + int max_mcs, + int *mcs, + int max_rbs, + int *rb_index, + int *tx_power) { + const int Ncp = RC.mac[mod_id]->common_channels[CC_id].Ncp; + /* TODO shouldn't we consider the SRS or other quality indicators? */ + *mcs = max_mcs; + *rb_index = 2; + int tbs = get_TBS_UL(*mcs, rb_table[*rb_index]); + + // fixme: set use_srs flag + *tx_power = estimate_ue_tx_power(tbs * 8, rb_table[*rb_index], 0, Ncp, 0); + + /* find maximum MCS */ + while ((phr - *tx_power < 0 || tbs > bytes) && *mcs > 3) { + mcs--; + tbs = get_TBS_UL(*mcs, rb_table[*rb_index]); + *tx_power = estimate_ue_tx_power(tbs * 8, rb_table[*rb_index], 0, Ncp, 0); + } + + /* find minimum necessary RBs */ + while (tbs < bytes + && *rb_index < 32 + && rb_table[*rb_index] < max_rbs + && phr - *tx_power > 0) { + (*rb_index)++; + tbs = get_TBS_UL(*mcs, rb_table[*rb_index]); + *tx_power = estimate_ue_tx_power(tbs * 8, rb_table[*rb_index], 0, Ncp, 0); + } + + /* Decrease if we went to far in last iteration */ + if (rb_table[*rb_index] > max_rbs) + (*rb_index)--; + + // 1 or 2 PRB with cqi enabled does not work well + if (rb_table[*rb_index] < 3) { + *rb_index = 2; //3PRB + } +} + +int pp_find_rb_table_index(int approximate) { + int lo = 2; + if (approximate <= rb_table[lo]) + return lo; + int hi = sizeof(rb_table) - 1; + if (approximate >= rb_table[hi]) + return hi; + int p = (hi + lo) / 2; + for (; lo + 1 != hi; p = (hi + lo) / 2) { + if (approximate <= rb_table[p]) + hi = p; + else + lo = p; + } + return p + 1; +} + +int g_start_ue_ul = -1; +int round_robin_ul(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + int sched_frame, + int sched_subframe, + UE_list_t *UE_list, + int max_num_ue, + int num_contig_rb, + contig_rbs_t *rbs) { + AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n"); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length; + + /* for every UE: check whether we have to handle a retransmission (and + * allocate, if so). If not, compute how much RBs this UE would need */ + int rb_idx_required[MAX_MOBILES_PER_ENB]; + memset(rb_idx_required, 0, sizeof(rb_idx_required)); + int num_ue_req = 0; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id], + sched_frame, sched_subframe); + if (UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0) { + /* this UE has a retransmission, allocate it right away */ + const int nb_rb = UE_template->nb_rb_ul[harq_pid]; + if (nb_rb == 0) { + LOG_E(MAC, + "%4d.%d UE %d retransmission of 0 RBs in round %d, ignoring\n", + sched_frame, sched_subframe, UE_id, + UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid]); + continue; + } + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_ulsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + UE_template->pre_dci_ul_pdu_idx = idx; + if (rbs[0].length >= nb_rb) { // fits in first contiguous region + UE_template->pre_first_nb_rb_ul = rbs[0].start; + rbs[0].length -= nb_rb; + rbs[0].start += nb_rb; + } else if (num_contig_rb == 2 && rbs[1].length >= nb_rb) { // in second + UE_template->pre_first_nb_rb_ul = rbs[1].start; + rbs[1].length -= nb_rb; + rbs[1].start += nb_rb; + } else if (num_contig_rb == 2 + && rbs[1].start + rbs[1].length - rbs[0].start >= nb_rb) { // overlapping the middle + UE_template->pre_first_nb_rb_ul = rbs[0].start; + rbs[0].length = 0; + int ol = nb_rb - (rbs[1].start - rbs[0].start); // how much overlap in second region + if (ol > 0) { + rbs[1].length -= ol; + rbs[1].start += ol; + } + } else { + LOG_W(MAC, + "cannot allocate UL retransmission for UE %d (nb_rb %d)\n", + UE_id, + nb_rb); + UE_template->pre_dci_ul_pdu_idx = -1; // do not need CCE + RC.mac[Mod_id]->HI_DCI0_req[CC_id][subframe].hi_dci0_request_body.number_of_dci--; + continue; + } + LOG_D(MAC, "%4d.%d UE %d retx %d RBs at start %d\n", + sched_frame, + sched_subframe, + UE_id, + UE_template->pre_allocated_nb_rb_ul, + UE_template->pre_first_nb_rb_ul); + UE_template->pre_allocated_nb_rb_ul = nb_rb; + max_num_ue--; + if (max_num_ue == 0) /* in this case, cannot allocate any other UE anymore */ + return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); + continue; + } + + const int B = cmax(UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes, 0); + const int UE_to_be_scheduled = UE_is_to_be_scheduled(Mod_id, CC_id, UE_id); + if (B == 0 && !UE_to_be_scheduled) + continue; + + num_ue_req++; + + /* if UE has pending scheduling request then pre-allocate 3 RBs */ + if (B == 0 && UE_to_be_scheduled) { + UE_template->pre_assigned_mcs_ul = 10; /* use QPSK mcs only */ + rb_idx_required[UE_id] = 2; + //UE_template->pre_allocated_nb_rb_ul = 3; + continue; + } + + int mcs; + int rb_table_index; + int tx_power; + calculate_max_mcs_min_rb( + Mod_id, + CC_id, + B, + UE_template->phr_info, + UE_info->UE_sched_ctrl[UE_id].phr_received == 1 ? 20 : 10, + &mcs, + max_rb, + &rb_table_index, + &tx_power); + + UE_template->pre_assigned_mcs_ul = mcs; + rb_idx_required[UE_id] = rb_table_index; + //UE_template->pre_allocated_nb_rb_ul = rb_table[rb_table_index]; + /* only print log when PHR changed */ + static int phr = 0; + if (phr != UE_template->phr_info) { + phr = UE_template->phr_info; + LOG_D(MAC, "%d.%d UE %d CC %d: pre mcs %d, pre rb_table[%d]=%d RBs (phr %d, tx power %d, bytes %d)\n", + frame, + subframe, + UE_id, + CC_id, + UE_template->pre_assigned_mcs_ul, + UE_template->pre_allocated_rb_table_index_ul, + UE_template->pre_allocated_nb_rb_ul, + UE_template->phr_info, + tx_power, + B); + } + } + + if (num_ue_req == 0) + return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); + + // calculate how many users should be in both regions, and to maximize usage, + // go from the larger to the smaller one which at least will handle a single + // full load case better. + const int n = min(num_ue_req, max_num_ue); + int nr[2] = {n, 0}; + int step = 1; // the order if we have two regions + int start = 0; + int end = 1; + if (num_contig_rb > 1) { + // proportionally divide between both regions + int la = rbs[0].length > 0 ? rbs[0].length : 1; + int lb = rbs[1].length > 0 ? rbs[1].length : 1; + nr[1] = min(max(n/(la/lb + 1), 1), n - 1); + nr[0] = n - nr[1]; + step = la > lb ? 1 : -1; // 1: from 0 to 1, -1: from 1 to 0 + start = la > lb ? 0 : 1; + end = la > lb ? 2 : -1; + } + + if (g_start_ue_ul == -1) + g_start_ue_ul = UE_list->head; + int sUE_id = g_start_ue_ul; + int rb_idx_given[MAX_MOBILES_PER_ENB]; + memset(rb_idx_given, 0, sizeof(rb_idx_given)); + + for (int r = start; r != end; r += step) { + // don't allocate if we have too little RBs + if (rbs[r].length < 3) + continue; + if (nr[r] <= 0) + continue; + + UE_list_t UE_sched; + // average RB index: just below the index that fits all UEs + int start_idx = pp_find_rb_table_index(rbs[r].length / nr[r]) - 1; + int num_ue_sched = 0; + int rb_required_add = 0; + int *cur_UE = &UE_sched.head; + while (num_ue_sched < nr[r]) { + while (rb_idx_required[sUE_id] == 0) + sUE_id = next_ue_list_looped(UE_list, sUE_id); + const int cqi = UE_info->UE_sched_ctrl[sUE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_ulsch(Mod_id, CC_id, subframe, sUE_id, cqi); + if (idx < 0) { + LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", sUE_id); + nr[r]--; + sUE_id = next_ue_list_looped(UE_list, sUE_id); // next candidate + continue; + } + UE_info->UE_template[CC_id][sUE_id].pre_dci_ul_pdu_idx = idx; + *cur_UE = sUE_id; + cur_UE = &UE_sched.next[sUE_id]; + rb_idx_given[sUE_id] = min(start_idx, rb_idx_required[sUE_id]); + rb_required_add += rb_table[rb_idx_required[sUE_id]] - rb_table[rb_idx_given[sUE_id]]; + rbs[r].length -= rb_table[rb_idx_given[sUE_id]]; + num_ue_sched++; + sUE_id = next_ue_list_looped(UE_list, sUE_id); + } + *cur_UE = -1; + + /* give remaining RBs in RR fashion. Since we don't know in advance the + * amount of RBs we can give (the "step size" in rb_table is non-linear), go + * through all UEs and try to give a bit more. Continue until no UE can be + * given a higher index because the remaining RBs do not suffice to increase */ + int UE_id = UE_sched.head; + int rb_required_add_old; + do { + rb_required_add_old = rb_required_add; + for (int UE_id = UE_sched.head; UE_id >= 0; UE_id = UE_sched.next[UE_id]) { + if (rb_idx_given[UE_id] >= rb_idx_required[UE_id]) + continue; // this UE does not need more + const int new_idx = rb_idx_given[UE_id] + 1; + const int rb_inc = rb_table[new_idx] - rb_table[rb_idx_given[UE_id]]; + if (rbs[r].length < rb_inc) + continue; + rb_idx_given[UE_id] = new_idx; + rbs[r].length -= rb_inc; + rb_required_add -= rb_inc; + } + } while (rb_required_add != rb_required_add_old); + + for (UE_id = UE_sched.head; UE_id >= 0; UE_id = UE_sched.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + + /* MCS has been allocated previously */ + UE_template->pre_first_nb_rb_ul = rbs[r].start; + UE_template->pre_allocated_rb_table_index_ul = rb_idx_given[UE_id]; + UE_template->pre_allocated_nb_rb_ul = rb_table[rb_idx_given[UE_id]]; + rbs[r].start += rb_table[rb_idx_given[UE_id]]; + LOG_D(MAC, "%4d.%d UE %d allocated %d RBs start %d new start %d\n", + sched_frame, + sched_subframe, + UE_id, + UE_template->pre_allocated_nb_rb_ul, + UE_template->pre_first_nb_rb_ul, + rbs[r].start); + } + } + + /* if not all UEs could be allocated in this round */ + if (num_ue_req > max_num_ue) { + /* go to the first one we missed */ + for (int i = 0; i < max_num_ue; ++i) + g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); + } else { + /* else, just start with the next UE next time */ + g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); + } + + return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); +} + +void ulsch_scheduler_pre_processor(module_id_t Mod_id, + int CC_id, int frameP, sub_frame_t subframeP, int sched_frameP, - unsigned char sched_subframeP, - uint16_t *first_rb) { - int UE_id; - uint16_t n; - uint8_t CC_id, harq_pid; - uint16_t nb_allocated_rbs[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; - uint16_t total_allocated_rbs[NFAPI_CC_MAX]; - uint16_t average_rbs_per_user[NFAPI_CC_MAX]; - int16_t total_remaining_rbs[NFAPI_CC_MAX]; - uint16_t total_ue_count[NFAPI_CC_MAX]; - eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list = &eNB->UE_list; - slice_info_t *sli = &eNB->slice_info; - UE_TEMPLATE *UE_template = 0; - UE_sched_ctrl_t *ue_sched_ctl; - int N_RB_UL = 0; - uint16_t available_rbs, first_rb_offset; - rnti_t rntiTable[MAX_MOBILES_PER_ENB]; - // sort ues - LOG_D(MAC, "In ulsch_preprocessor: sort ue \n"); - sort_ue_ul(module_idP, slice_idx, sched_frameP, sched_subframeP, rntiTable); - // maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB - LOG_D(MAC, "In ulsch_preprocessor: assign max mcs min rb\n"); - assign_max_mcs_min_rb(module_idP, slice_idx, frameP, subframeP, first_rb); - // we need to distribute RBs among UEs - // step1: reset the vars - uint8_t CC_nb = (uint8_t) RC.nb_mac_CC[module_idP]; + unsigned char sched_subframeP) { + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + const int N_RB_UL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; - for (CC_id = 0; CC_id < CC_nb; CC_id++) { - total_allocated_rbs[CC_id] = 0; - total_remaining_rbs[CC_id] = 0; - average_rbs_per_user[CC_id] = 0; - total_ue_count[CC_id] = 0; + UE_list_t UE_to_sched; + UE_to_sched.head = -1; + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + UE_to_sched.next[i] = -1; + + int last_UE_id = -1; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + /* initialize per-UE scheduling information */ + UE_template->pre_assigned_mcs_ul = 0; + UE_template->pre_allocated_nb_rb_ul = 0; + UE_template->pre_allocated_rb_table_index_ul = -1; + UE_template->pre_first_nb_rb_ul = 0; + UE_template->pre_dci_ul_pdu_idx = -1; + + const rnti_t rnti = UE_RNTI(Mod_id, UE_id); + if (rnti == NOT_A_RNTI) { + LOG_E(MAC, "UE %d has RNTI NOT_A_RNTI!\n", UE_id); + continue; + } + if (ue_sched_ctrl->cdrx_configured && !ue_sched_ctrl->in_active_time) + continue; + if (UE_info->UE_template[CC_id][UE_id].rach_resource_type > 0) + continue; + + /* define UEs to schedule */ + if (UE_to_sched.head < 0) + UE_to_sched.head = UE_id; + else + UE_to_sched.next[last_UE_id] = UE_id; + UE_to_sched.next[UE_id] = -1; + last_UE_id = UE_id; } - // Step 1.5: Calculate total_ue_count - for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) { - // This is not the actual CC_id in the list - for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { - CC_id = UE_list->ordered_ULCCids[n][UE_id]; - UE_template = &UE_list->UE_template[CC_id][UE_id]; + if (UE_to_sched.head < 0) + return; - if (UE_template->pre_allocated_nb_rb_ul[slice_idx] > 0) { - total_ue_count[CC_id]++; - } + int last_rb_blocked = 1; + int n_contig = 0; + contig_rbs_t rbs[2]; // up to two contig RBs for PRACH in between + for (int i = 0; i < N_RB_UL; ++i) { + if (cc->vrb_map_UL[i] == 0 && last_rb_blocked == 1) { + last_rb_blocked = 0; + n_contig++; + AssertFatal(n_contig <= 2, "cannot handle more than two contiguous RB regions\n"); + rbs[n_contig - 1].start = i; + } + if (cc->vrb_map_UL[i] == 1 && last_rb_blocked == 0) { + last_rb_blocked = 1; + rbs[n_contig - 1].length = i - rbs[n_contig - 1].start; } } - // step 2: calculate the average rb per UE - LOG_D(MAC, "In ulsch_preprocessor: step2 \n"); + round_robin_ul(Mod_id, + CC_id, + frameP, + subframeP, + sched_frameP, + sched_subframeP, + &UE_to_sched, + 4, // max_num_ue + n_contig, + rbs); - for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) { - if (UE_list->UE_template[CC_id][UE_id].rach_resource_type > 0) continue; + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality +#ifdef DEBUG_eNB_SCHEDULER + char t[101] = "__________________________________________________" + "__________________________________________________"; + t[N_RB_UL] = 0; + for (int j = 0; j < N_RB_UL; j++) + if (cc->vrb_map_UL[j] != 0) + t[j] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + if (UE_template->pre_allocated_nb_rb_ul == 0) + continue; - LOG_D(MAC, "In ulsch_preprocessor: handling UE %d/%x\n", + print = 1; + uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id], + sched_frameP, sched_subframeP); + LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", + frameP, + subframeP, UE_id, - rntiTable[UE_id]); + UE_template->pre_allocated_nb_rb_ul, + UE_template->pre_allocated_rb_table_index_ul, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_assigned_mcs_ul, + UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0 ? "(retx)" : ""); - for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { - // This is the actual CC_id in the list - CC_id = UE_list->ordered_ULCCids[n][UE_id]; - LOG_D(MAC, "In ulsch_preprocessor: handling UE %d/%x CCid %d\n", - UE_id, - rntiTable[UE_id], - CC_id); - /* - if((mac_xface->get_nCCE_max(module_idP,CC_id,3,subframeP) - nCCE_to_be_used[CC_id]) > (1<common_channels[CC_id].ul_Bandwidth); - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx] = - nb_rbs_allowed_slice(sli->ul[slice_idx].pct, N_RB_UL); - first_rb_offset = UE_list->first_rb_offset[CC_id][slice_idx]; - available_rbs = - cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset); + for (int i = 0; i < UE_template->pre_allocated_nb_rb_ul; ++i) { + /* only check if this is not a retransmission */ + if (UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] == 0 + && cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] == 1) { - if (available_rbs < 0) - available_rbs = 0; - - if (total_ue_count[CC_id] == 0) { - average_rbs_per_user[CC_id] = 0; - } else if (total_ue_count[CC_id] == 1) { // increase the available RBs, special case, - average_rbs_per_user[CC_id] = (uint16_t) (available_rbs + 1); - } else if (total_ue_count[CC_id] <= available_rbs) { - average_rbs_per_user[CC_id] = (uint16_t) floor(available_rbs / total_ue_count[CC_id]); - } else { - average_rbs_per_user[CC_id] = 1; - LOG_W(MAC, "[eNB %d] frame %d subframe %d: UE %d CC %d: can't get average rb per user (should not be here)\n", - module_idP, - frameP, - subframeP, - UE_id, - CC_id); - } - - if (total_ue_count[CC_id] > 0) { - LOG_D(MAC, "[eNB %d] Frame %d subframe %d: total ue to be scheduled %d\n", - module_idP, - frameP, - subframeP, - total_ue_count[CC_id]); + LOG_I(MAC, "%4d.%d UL scheduler allocation list: %s\n", frameP, subframeP, t); + LOG_E(MAC, + "%4d.%d: UE %d allocated at locked RB %d (is: allocated start " + "%d/length %d)\n", + frameP, subframeP, UE_id, UE_template->pre_first_nb_rb_ul + i, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_allocated_nb_rb_ul); } + cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] = 1; + t[UE_template->pre_first_nb_rb_ul + i] = UE_id + '0'; } } - - // step 3: assigne RBS - for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) { - // if (continueTable[UE_id]) continue; - for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { - // This is the actual CC_id in the list - CC_id = UE_list->ordered_ULCCids[n][UE_id]; - UE_template = &UE_list->UE_template[CC_id][UE_id]; - harq_pid = subframe2harqpid(&RC.mac[module_idP]->common_channels[CC_id], - sched_frameP, sched_subframeP); - - // mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,frameP,subframeP,&harq_pid,&round,openair_harq_UL); - - if (UE_list->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0) { - nb_allocated_rbs[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb_ul[harq_pid]; - } else { - nb_allocated_rbs[CC_id][UE_id] = - cmin(UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_idx], average_rbs_per_user[CC_id]); - } - - total_allocated_rbs[CC_id] += nb_allocated_rbs[CC_id][UE_id]; - LOG_D(MAC, "In ulsch_preprocessor: assigning %d RBs for UE %d/%x CCid %d, harq_pid %d\n", - nb_allocated_rbs[CC_id][UE_id], - UE_id, - rntiTable[UE_id], - CC_id, - harq_pid); - } - } - - // step 4: assigne the remaining RBs and set the pre_allocated rbs accordingly - for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) { - // if (continueTable[UE_id]) continue; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - - for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { - // This is the actual CC_id in the list - CC_id = UE_list->ordered_ULCCids[n][UE_id]; - UE_template = &UE_list->UE_template[CC_id][UE_id]; - N_RB_UL = to_prb(eNB->common_channels[CC_id].ul_Bandwidth); - first_rb_offset = UE_list->first_rb_offset[CC_id][slice_idx]; - available_rbs = cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset); - total_remaining_rbs[CC_id] = available_rbs - total_allocated_rbs[CC_id]; - - if (total_ue_count[CC_id] == 1) { - total_remaining_rbs[CC_id]++; - } - - while (UE_template->pre_allocated_nb_rb_ul[slice_idx] > 0 && - nb_allocated_rbs[CC_id][UE_id] < UE_template->pre_allocated_nb_rb_ul[slice_idx] && - total_remaining_rbs[CC_id] > 0) { - nb_allocated_rbs[CC_id][UE_id] = cmin(nb_allocated_rbs[CC_id][UE_id] + 1, UE_template->pre_allocated_nb_rb_ul[slice_idx]); - total_remaining_rbs[CC_id]--; - total_allocated_rbs[CC_id]++; - } - - UE_template->pre_allocated_nb_rb_ul[slice_idx] = nb_allocated_rbs[CC_id][UE_id]; - LOG_D(MAC, "******************UL Scheduling Information for UE%d CC_id %d ************************\n", - UE_id, - CC_id); - LOG_D(MAC, "[eNB %d] total RB allocated for UE%d CC_id %d = %d\n", - module_idP, - UE_id, - CC_id, - UE_template->pre_allocated_nb_rb_ul[slice_idx]); - } - } - - return; -} - -void -assign_max_mcs_min_rb(module_id_t module_idP, - int slice_idx, - int frameP, - sub_frame_t subframeP, - uint16_t *first_rb) { - int i; - uint16_t n, UE_id; - uint8_t CC_id; - int mcs; - int rb_table_index = 0, tbs, tx_power; - eNB_MAC_INST *eNB = RC.mac[module_idP]; - UE_list_t *UE_list = &eNB->UE_list; - slice_info_t *sli = &eNB->slice_info; - UE_TEMPLATE *UE_template; - UE_sched_ctrl_t *ue_sched_ctl; - int Ncp; - int N_RB_UL; - int first_rb_offset, available_rbs; - - for (i = UE_list->head_ul; i >= 0; i = UE_list->next_ul[i]) { - if (UE_list->UE_sched_ctrl[i].phr_received == 1) { - /* if we've received the power headroom information the UE, we can go to - * maximum mcs */ - mcs = cmin(20, sli->ul[slice_idx].maxmcs); - } else { - /* otherwise, limit to QPSK PUSCH */ - mcs = cmin(10, sli->ul[slice_idx].maxmcs); - } - - UE_id = i; - - for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { - // This is the actual CC_id in the list - CC_id = UE_list->ordered_ULCCids[n][UE_id]; - AssertFatal(CC_id < RC.nb_mac_CC[module_idP], "CC_id %u should be < %u, loop n=%u < numactiveULCCs[%u]=%u", - CC_id, - NFAPI_CC_MAX, - n, - UE_id, - UE_list->numactiveULCCs[UE_id]); - UE_template = &UE_list->UE_template[CC_id][UE_id]; - UE_template->pre_assigned_mcs_ul = mcs; - ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - Ncp = eNB->common_channels[CC_id].Ncp; - N_RB_UL = to_prb(eNB->common_channels[CC_id].ul_Bandwidth); - ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx] = nb_rbs_allowed_slice(sli->ul[slice_idx].pct, N_RB_UL); - int bytes_to_schedule = UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes; - - if (bytes_to_schedule < 0) bytes_to_schedule = 0; - - int bits_to_schedule = bytes_to_schedule * 8; - - // if this UE has UL traffic - if (bits_to_schedule > 0) { - tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, 3) << 3; // 1 or 2 PRB with cqi enabled does not work well! - rb_table_index = 2; - // fixme: set use_srs flag - tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0); - - while ((UE_template->phr_info - tx_power < 0 || tbs > bits_to_schedule) && UE_template->pre_assigned_mcs_ul > 3) { - // LOG_I(MAC,"UE_template->phr_info %d tx_power %d mcs %d\n", UE_template->phr_info,tx_power, mcs); - UE_template->pre_assigned_mcs_ul--; - tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3; - tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0); // fixme: set use_srs - } - - first_rb_offset = UE_list->first_rb_offset[CC_id][slice_idx]; - available_rbs = - cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset); - - while (tbs < bits_to_schedule && - rb_table[rb_table_index] < available_rbs && - UE_template->phr_info - tx_power > 0 && - rb_table_index < 32) { - rb_table_index++; - tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3; - tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0); - } - - if (rb_table[rb_table_index] > (available_rbs - 1)) { - rb_table_index--; - } - - // 1 or 2 PRB with cqi enabled does not work well - if (rb_table[rb_table_index] < 3) { - rb_table_index = 2; //3PRB - } - - UE_template->pre_allocated_rb_table_index_ul = rb_table_index; - UE_template->pre_allocated_nb_rb_ul[slice_idx] = rb_table[rb_table_index]; - LOG_D(MAC, "[eNB %d] frame %d subframe %d: for UE %d CC %d: pre-assigned mcs %d, pre-allocated rb_table[%d]=%d RBs (phr %d, tx power %d)\n", - module_idP, - frameP, - subframeP, - UE_id, - CC_id, - UE_template->pre_assigned_mcs_ul, - UE_template->pre_allocated_rb_table_index_ul, - UE_template->pre_allocated_nb_rb_ul[slice_idx], - UE_template->phr_info, tx_power); - } else { - /* if UE has pending scheduling request then pre-allocate 3 RBs */ - //if (UE_template->ul_active == 1 && UE_template->ul_SR == 1) { - if (UE_is_to_be_scheduled(module_idP, CC_id, i)) { - /* use QPSK mcs */ - UE_template->pre_assigned_mcs_ul = 10; - UE_template->pre_allocated_rb_table_index_ul = 2; - UE_template->pre_allocated_nb_rb_ul[slice_idx] = 3; - } else { - UE_template->pre_assigned_mcs_ul = 0; - UE_template->pre_allocated_rb_table_index_ul = -1; - UE_template->pre_allocated_nb_rb_ul[slice_idx] = 0; - } - } - } - } -} - -struct sort_ue_ul_params { - int module_idP; - int sched_frameP; - int sched_subframeP; -}; - -static int ue_ul_compare(const void *_a, const void *_b, void *_params) { - struct sort_ue_ul_params *params = _params; - UE_list_t *UE_list = &RC.mac[params->module_idP]->UE_list; - int UE_id1 = *(const int *) _a; - int UE_id2 = *(const int *) _b; - int rnti1 = UE_RNTI(params->module_idP, UE_id1); - int pCCid1 = UE_PCCID(params->module_idP, UE_id1); - int round1 = maxround_ul(params->module_idP, rnti1, params->sched_frameP, - params->sched_subframeP); - int rnti2 = UE_RNTI(params->module_idP, UE_id2); - int pCCid2 = UE_PCCID(params->module_idP, UE_id2); - int round2 = maxround_ul(params->module_idP, rnti2, params->sched_frameP, - params->sched_subframeP); - - if (round1 > round2) - return -1; - - if (round1 < round2) - return 1; - - if (UE_list->UE_template[pCCid1][UE_id1].ul_buffer_info[LCGID0] > - UE_list->UE_template[pCCid2][UE_id2].ul_buffer_info[LCGID0]) - return -1; - - if (UE_list->UE_template[pCCid1][UE_id1].ul_buffer_info[LCGID0] < - UE_list->UE_template[pCCid2][UE_id2].ul_buffer_info[LCGID0]) - return 1; - - int bytes_to_schedule1 = UE_list->UE_template[pCCid1][UE_id1].estimated_ul_buffer - UE_list->UE_template[pCCid1][UE_id1].scheduled_ul_bytes; - - if (bytes_to_schedule1 < 0) bytes_to_schedule1 = 0; - - int bytes_to_schedule2 = UE_list->UE_template[pCCid2][UE_id2].estimated_ul_buffer - UE_list->UE_template[pCCid2][UE_id2].scheduled_ul_bytes; - - if (bytes_to_schedule2 < 0) bytes_to_schedule2 = 0; - - if (bytes_to_schedule1 > bytes_to_schedule2) - return -1; - - if (bytes_to_schedule1 < bytes_to_schedule2) - return 1; - - if (UE_list->UE_template[pCCid1][UE_id1].pre_assigned_mcs_ul > - UE_list->UE_template[pCCid2][UE_id2].pre_assigned_mcs_ul) - return -1; - - if (UE_list->UE_template[pCCid1][UE_id1].pre_assigned_mcs_ul < - UE_list->UE_template[pCCid2][UE_id2].pre_assigned_mcs_ul) - return 1; - - if (UE_list->UE_sched_ctrl[UE_id1].cqi_req_timer > - UE_list->UE_sched_ctrl[UE_id2].cqi_req_timer) - return -1; - - if (UE_list->UE_sched_ctrl[UE_id1].cqi_req_timer < - UE_list->UE_sched_ctrl[UE_id2].cqi_req_timer) - return 1; - - return 0; -} - -//----------------------------------------------------------------------------- -/* - * This function sorts the UEs in order, depending on their ulsch buffer and CQI - */ -void sort_ue_ul(module_id_t module_idP, - int slice_idx, - int sched_frameP, - sub_frame_t sched_subframeP, - rnti_t *rntiTable) -//----------------------------------------------------------------------------- -{ - int list[MAX_MOBILES_PER_ENB]; - int list_size = 0; - struct sort_ue_ul_params params = { module_idP, sched_frameP, sched_subframeP }; - UE_list_t *UE_list = &RC.mac[module_idP]->UE_list; - UE_sched_ctrl_t *UE_scheduling_control = NULL; - - for (int i = 0; i < MAX_MOBILES_PER_ENB; i++) { - UE_scheduling_control = &(UE_list->UE_sched_ctrl[i]); - - /* Check CDRX configuration and if UE is in active time for this subframe */ - if (UE_scheduling_control->cdrx_configured == TRUE) { - if (UE_scheduling_control->in_active_time == FALSE) { - continue; - } - } - - rntiTable[i] = UE_RNTI(module_idP, i); - - // Valid element and is not the actual CC_id in the list - if (UE_list->active[i] == TRUE && - rntiTable[i] != NOT_A_RNTI && - UE_list->UE_sched_ctrl[i].ul_out_of_sync != 1 && - ue_ul_slice_membership(module_idP, i, slice_idx)) { - list[list_size++] = i; // Add to list - } - } - - qsort_r(list, list_size, sizeof(int), ue_ul_compare, ¶ms); - - if (list_size) { // At mimimum one list element - for (int i = 0; i < list_size - 1; i++) { - UE_list->next_ul[list[i]] = list[i + 1]; - } - - UE_list->next_ul[list[list_size - 1]] = -1; - UE_list->head_ul = list[0]; - } else { // No element - UE_list->head_ul = -1; - } + if (print) + LOG_D(MAC, + "%4d.%d UL scheduler allocation list: %s\n", + sched_frameP, + sched_subframeP, + t); +#endif } diff --git a/openair2/LAYER2/MAC/ra_procedures.c b/openair2/LAYER2/MAC/ra_procedures.c index 19b1c7708b..0d1afdf2a2 100644 --- a/openair2/LAYER2/MAC/ra_procedures.c +++ b/openair2/LAYER2/MAC/ra_procedures.c @@ -390,7 +390,7 @@ PRACH_RESOURCES_t *ue_get_rach(module_id_t module_idP, int CC_id, LOG_USEDINLOG_VAR(mac_rlc_status_resp_t,rlc_status)=mac_rlc_status_ind(module_idP, UE_mac_inst[module_idP].crnti, eNB_indexP, frameP, subframeP, - ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6,0, 0 + ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 0, 0 ); if (UE_mac_inst[module_idP].crnti_before_ho) @@ -406,7 +406,7 @@ PRACH_RESOURCES_t *ue_get_rach(module_id_t module_idP, int CC_id, module_idP, frameP, rlc_status.bytes_in_buffer, dcch_header_len); - sdu_lengths = mac_rlc_data_req(module_idP, UE_mac_inst[module_idP].crnti, eNB_indexP, frameP, ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6, //not used + sdu_lengths = mac_rlc_data_req(module_idP, UE_mac_inst[module_idP].crnti, eNB_indexP, frameP, ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6, (char *) &ulsch_buff[0],0, 0 ); diff --git a/openair2/LAYER2/MAC/ue_procedures.c b/openair2/LAYER2/MAC/ue_procedures.c index 1205851915..24630c0fe2 100644 --- a/openair2/LAYER2/MAC/ue_procedures.c +++ b/openair2/LAYER2/MAC/ue_procedures.c @@ -1972,6 +1972,10 @@ ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, subframe, ENB_FLAG_NO, lcid); lcid_buffer_occupancy_new = lcid_buffer_occupancy_old; +#if 0 + /* TODO: those assert crash the L2 simulator with the new RLC. + * Are they necessary? + */ AssertFatal(lcid_buffer_occupancy_new == UE_mac_inst[module_idP]. scheduling_info.LCID_buffer_remain[lcid], @@ -1990,6 +1994,7 @@ ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, scheduling_info.BSR_bytes[UE_mac_inst[module_idP]. scheduling_info.LCGID [lcid]]); +#endif //Multiplex all available DCCH RLC PDUs considering to multiplex the last PDU each time for maximize the data //Adjust at the end of the loop @@ -2085,18 +2090,10 @@ ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, } //Update Buffer remain and BSR bytes after transmission - AssertFatal(lcid_buffer_occupancy_new <= - lcid_buffer_occupancy_old, - "MAC UE Tx error : Buffer Occupancy After Tx=%d greater than before=%d BO! for LCID=%d RLC PDU nb=%d Frame %d Subrame %d\n", - lcid_buffer_occupancy_new, - lcid_buffer_occupancy_old, lcid, - lcid_rlc_pdu_count, frameP, subframe); - UE_mac_inst[module_idP].scheduling_info. - LCID_buffer_remain[lcid] = lcid_buffer_occupancy_new; - UE_mac_inst[module_idP]. - scheduling_info.BSR_bytes[UE_mac_inst[module_idP]. - scheduling_info.LCGID[lcid]] += - (lcid_buffer_occupancy_new - lcid_buffer_occupancy_old); + UE_mac_inst[module_idP].scheduling_info.LCID_buffer_remain[lcid] = lcid_buffer_occupancy_new; + UE_mac_inst[module_idP].scheduling_info.BSR_bytes[UE_mac_inst[module_idP].scheduling_info.LCGID[lcid]] += (lcid_buffer_occupancy_new - lcid_buffer_occupancy_old); + if (UE_mac_inst[module_idP].scheduling_info.BSR_bytes[UE_mac_inst[module_idP].scheduling_info.LCGID[lcid]] < 0) + UE_mac_inst[module_idP].scheduling_info.BSR_bytes[UE_mac_inst[module_idP].scheduling_info.LCGID[lcid]] = 0; //Update the number of LCGID with data as BSR shall reflect status after BSR transmission if ((num_lcg_id_with_data > 1) @@ -2809,7 +2806,6 @@ update_bsr(module_id_t module_idP, frame_t frameP, rlc_status = mac_rlc_status_ind(module_idP, UE_mac_inst[module_idP].crnti,eNB_index,frameP,subframeP,ENB_FLAG_NO,MBMS_FLAG_NO, lcid, - 0xFFFF, //TBS is not used in RLC at this step, set a special value for debug 0, 0 ); lcid_bytes_in_buffer[lcid] = rlc_status.bytes_in_buffer; @@ -3176,7 +3172,7 @@ SLSCH_t *ue_get_slsch(module_id_t module_idP,int CC_id,frame_t frameP,sub_frame_ for (int j = 0; j < ue->numCommFlows; j++) { if ((ue->sourceL2Id > 0) && (ue->destinationList[j] >0) ) { rlc_status = mac_rlc_status_ind(module_idP, 0x1234,0,frameP,subframeP,ENB_FLAG_NO,MBMS_FLAG_NO, - ue->SL_LCID[i], 0xFFFF, ue->sourceL2Id, ue->destinationList[j]); + ue->SL_LCID[i], ue->sourceL2Id, ue->destinationList[j]); if (rlc_status.bytes_in_buffer > 2) { LOG_I(MAC,"SFN.SF %d.%d: Scheduling for %d bytes in Sidelink buffer\n",frameP,subframeP,rlc_status.bytes_in_buffer); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index ae23164194..cfde40daad 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -79,6 +79,47 @@ nr_bandentry_t nr_bandtable[] = { {261,27500000,28350000,27500000,28350000, 2,2070833, 120} }; + +// TS 38.211 Table 6.4.1.1.3-3: PUSCH DMRS positions l' within a slot for single-symbol DMRS and intra-slot frequency hopping disabled. +// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B. +// When l' = l0, it is represented by 1 +// E.g. when symbol duration is 12 in colomn 7, value 1057 ('10000100001') which means l' = l0, 5, 10. + +int32_t table_6_4_1_1_3_3_pusch_dmrs_positions_l [12][8] = { // Duration in symbols +{-1, -1, -1, -1, 1, 1, 1, 1}, //<4 // (DMRS l' position) +{1, 1, 1, 1, 1, 1, 1, 1}, //4 // (DMRS l' position) +{1, 1, 1, 1, 1, 5, 5, 5}, //5 // (DMRS l' position) +{1, 1, 1, 1, 1, 5, 5, 5}, //6 // (DMRS l' position) +{1, 1, 1, 1, 1, 5, 5, 5}, //7 // (DMRS l' position) +{1, 129, 129, 129, 1, 65, 73, 73}, //8 // (DMRS l' position) +{1, 129, 129, 129, 1, 65, 73, 73}, //9 // (DMRS l' position) +{1, 513, 577, 577, 1, 257, 273, 585}, //10 // (DMRS l' position) +{1, 513, 577, 577, 1, 257, 273, 585}, //11 // (DMRS l' position) +{1, 513, 577, 2337, 1, 1025, 1057, 585}, //12 // (DMRS l' position) +{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //13 // (DMRS l' position) +{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //14 // (DMRS l' position) +}; + + +// TS 38.211 Table 6.4.1.1.3-4: PUSCH DMRS positions l' within a slot for double-symbol DMRS and intra-slot frequency hopping disabled. +// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B. +// When l' = l0, it is represented by 1 + +int32_t table_6_4_1_1_3_4_pusch_dmrs_positions_l [12][8] = { // Duration in symbols +{-1, -1, -1, -1, -1, -1, -1, -1}, //<4 // (DMRS l' position) +{1, 1, -1, -1, -1, -1, -1, -1}, //4 // (DMRS l' position) +{1, 1, -1, -1, 1, 1, -1, -1}, //5 // (DMRS l' position) +{1, 1, -1, -1, 1, 1, -1, -1}, //6 // (DMRS l' position) +{1, 1, -1, -1, 1, 1, -1, -1}, //7 // (DMRS l' position) +{1, 1, -1, -1, 1, 33, -1, -1}, //8 // (DMRS l' position) +{1, 1, -1, -1, 1, 33, -1, -1}, //9 // (DMRS l' position) +{1, 257, -1, -1, 1, 129, -1, -1}, //10 // (DMRS l' position) +{1, 257, -1, -1, 1, 129, -1, -1}, //11 // (DMRS l' position) +{1, 257, -1, -1, 1, 513, -1, -1}, //12 // (DMRS l' position) +{1, 1025, -1, -1, 1, 513, -1, -1}, //13 // (DMRS l' position) +{1, 1025, -1, -1, 1, 513, -1, -1}, //14 // (DMRS l' position) +}; + #define NR_BANDTABLE_SIZE (sizeof(nr_bandtable)/sizeof(nr_bandentry_t)) void get_band(uint64_t downlink_frequency, @@ -517,6 +558,112 @@ int get_num_dmrs(uint16_t dmrs_mask ) { return(num_dmrs); } +/******************************************************************* +* +* NAME : get_l0_ul +* +* PARAMETERS : mapping_type : PUSCH mapping type +* dmrs_typeA_position : higher layer parameter +* +* RETURN : demodulation reference signal for PUSCH +* +* DESCRIPTION : see TS 38.211 V15.4.0 Demodulation reference signals for PUSCH +* +*********************************************************************/ + +uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position) { + + return ((mapping_type==typeA)?dmrs_typeA_position:0); + +} + +int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength) { + + uint8_t row, colomn; + int32_t l_prime; + + colomn = additional_pos; + + if (mapping_type == typeB) + colomn += 4; + + if (duration_in_symbols < 4) + row = 0; + else + row = duration_in_symbols - 3; + + if (pusch_maxLength == pusch_len1) + l_prime = table_6_4_1_1_3_3_pusch_dmrs_positions_l[row][colomn]; + else + l_prime = table_6_4_1_1_3_4_pusch_dmrs_positions_l[row][colomn]; + + AssertFatal(l_prime>0,"invalid l_prime < 0\n"); + + return l_prime; +} + +/******************************************************************* +* +* NAME : get_L_ptrs +* +* PARAMETERS : mcs(i) higher layer parameter in PTRS-UplinkConfig +* I_mcs MCS index used for PUSCH +* mcs_table 0 for table 5.1.3.1-1, 1 for table 5.1.3.1-1 +* +* RETURN : the parameter L_ptrs +* +* DESCRIPTION : 3GPP TS 38.214 section 6.2.3.1 +* +*********************************************************************/ + +uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table) { + + uint8_t mcs4; + + if(mcs_table == 0) + mcs4 = 29; + else + mcs4 = 28; + + if (I_mcs < mcs1) { + LOG_I(PHY, "PUSH PT-RS is not present.\n"); + return -1; + } else if (I_mcs >= mcs1 && I_mcs < mcs2) + return 2; + else if (I_mcs >= mcs2 && I_mcs < mcs3) + return 1; + else if (I_mcs >= mcs3 && I_mcs < mcs4) + return 0; + else { + LOG_I(PHY, "PT-RS time-density determination is obtained from the DCI for the same transport block in the initial transmission\n"); + return -1; + } +} + +/******************************************************************* +* +* NAME : get_K_ptrs +* +* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration +* N_RB number of RBs scheduled for PUSCH +* +* RETURN : the parameter K_ptrs +* +* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-2 +* +*********************************************************************/ + +uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB) { + + if (N_RB < nrb0) { + LOG_I(PHY,"PUSH PT-RS is not present.\n"); + return -1; + } else if (N_RB >= nrb0 && N_RB < nrb1) + return 0; + else + return 1; +} + uint16_t nr_dci_size(nr_dci_format_t format, nr_rnti_type_t rnti_type, uint16_t N_RB) { diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h index 2cfce4766f..63c81def82 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h @@ -45,7 +45,7 @@ extern const uint8_t cqi2fmt2x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern UE_RRC_INST *UE_rrc_inst; extern eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 extern eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 -extern int cqi_to_mcs[16]; +extern const int cqi_to_mcs[16]; extern uint32_t RRC_CONNECTION_FLAG; extern uint8_t rb_table[34]; extern mac_rlc_am_muilist_t rlc_am_mui; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 36d285e320..3c625ec2ff 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -166,6 +166,11 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, nr_dci_pdu_rel15_t *nr_pdci_info_extracted); +uint8_t +nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, + sub_frame_t subframe, uint8_t eNB_index, + uint8_t *ulsch_buffer, uint16_t buflen, uint8_t *access_mode) ; + int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, int nrofDownlinkSlots, int nrofDownlinkSymbols, int nrofUplinkSlots, int nrofUplinkSymbols); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 58b312038a..a49a3f51a3 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -118,7 +118,7 @@ int8_t nr_ue_process_dlsch(module_id_t module_id, //fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; nr_phy_config_t *phy_config = &mac->phy_config; - //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rnti = rnti; // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ. ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; for (int i=0; i<10; i++) { @@ -128,29 +128,28 @@ int8_t nr_ue_process_dlsch(module_id_t module_id, } if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) { // fill in the elements in config request inside P5 message - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0; - for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0; - //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0; + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.bandwidth_part_ind = 0; //FIXME + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rb_size = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rb_start = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.nr_of_symbols = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.start_symbol_index = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.frequency_hopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.mcs_index = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.pusch_data.new_data_indicator = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.pusch_data.rv_index = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.pusch_data.harq_process_id = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.absolute_delta_PUSCH = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.nrOfLayers = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.transform_precoding = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.dmrs_ports = 0; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.dmrs_config_type = 0; + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.n_front_load_symb = 0; //FIXME + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.srs_config = 0; //FIXME + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.csi_reportTriggerSize = 0; //FIXME + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.maxCodeBlockGroupsPerTransportBlock = 0; //FIXME + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.ptrs_dmrs_association_port = 0; FIXME + //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.beta_offset_ind = 0; //FIXME } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; // If we handle PUCCH common @@ -468,7 +467,6 @@ int8_t nr_ue_decode_mib(module_id_t module_id, uint32_t number_of_search_space_per_slot=UINT_MAX; uint32_t first_symbol_index=UINT_MAX; uint32_t search_space_duration; // element of search space - uint32_t coreset_duration; // element of coreset // 38.213 table 10.1-1 /// MUX PATTERN 1 @@ -604,8 +602,8 @@ int8_t nr_ue_decode_mib(module_id_t module_id, } AssertFatal(number_of_search_space_per_slot!=UINT_MAX,""); - coreset_duration = num_symbols * number_of_search_space_per_slot; /* + uint32_t coreset_duration = num_symbols * number_of_search_space_per_slot; mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0]; mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1]; mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4 @@ -1669,7 +1667,7 @@ uint8_t table_7_3_2_3_3_4_twoCodeword[6][10] = { {2,0,1,2,3,6,7,8,0,2}, {2,0,1,2,3,6,7,8,9,2} }; -int8_t nr_ue_process_dci_freq_dom_resource_assignment(fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu, +int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu, fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu, uint16_t n_RB_ULBWP, uint16_t n_RB_DLBWP, @@ -1692,7 +1690,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(fapi_nr_ul_config_pusch_pd dlsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_DLBWP); } - if(ulsch_config_pdu != NULL){ + if(pusch_config_pdu != NULL){ /* * TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink) */ @@ -1703,14 +1701,14 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(fapi_nr_ul_config_pusch_pd * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1 */ - ulsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_ULBWP); - ulsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_ULBWP); + pusch_config_pdu->rb_size = NRRIV2BW(riv,n_RB_ULBWP); + pusch_config_pdu->rb_start = NRRIV2PRBOFFSET(riv,n_RB_ULBWP); } return 0; } int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, - fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu, + nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu, fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu, uint8_t time_domain_ind ){ @@ -1849,9 +1847,6 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, SLIV2SL(startSymbolAndLength,&S,&L); dlsch_config_pdu->start_symbol=S; dlsch_config_pdu->number_symbols=L; - dlsch_config_pdu->frame_offset = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0!=NULL ? - *pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0 : - 0; } else {// Default configuration from tables k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0]; @@ -1866,14 +1861,13 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, // k_offset = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][0]; // sliv_S = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][1]; // sliv_L = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - dlsch_config_pdu->frame_offset = k_offset; dlsch_config_pdu->number_symbols = sliv_L; dlsch_config_pdu->start_symbol = sliv_S; } } /* * TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink) */ - if(ulsch_config_pdu != NULL){ + if(pusch_config_pdu != NULL){ NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = NULL; if (mac->ULbwp[0]->bwp_Dedicated->pusch_Config) pusch_TimeDomainAllocationList = mac->ULbwp[0]->bwp_Dedicated->pusch_Config->choice.setup->pusch_TimeDomainAllocationList->choice.setup; @@ -1885,12 +1879,8 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, int startSymbolAndLength = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength; int S,L; SLIV2SL(startSymbolAndLength,&S,&L); - ulsch_config_pdu->start_symbol=S; - ulsch_config_pdu->number_symbols=L; - ulsch_config_pdu->frame_offset = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2!=NULL ? - *pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2 : - mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz60 ? 1 : - mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz120 ? 2 : 3; + pusch_config_pdu->start_symbol_index=S; + pusch_config_pdu->nr_of_symbols=L; } else { k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0]; @@ -1899,9 +1889,8 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, // k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0]; // sliv_S = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1]; // sliv_L = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2]; - ulsch_config_pdu->frame_offset = k_offset; - ulsch_config_pdu->number_symbols = sliv_L; - ulsch_config_pdu->start_symbol = sliv_S; + pusch_config_pdu->nr_of_symbols = sliv_L; + pusch_config_pdu->start_symbol_index = sliv_S; } } return 0; @@ -1917,6 +1906,7 @@ int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_in nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15); nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format); + return 0; } int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ @@ -1953,45 +1943,41 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr * 50 SUL_IND_0_0: */ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; - fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rnti = rnti; + nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu; /* IDENTIFIER_DCI_FORMATS */ /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); /* TIME_DOM_RESOURCE_ASSIGNMENT */ nr_ue_process_dci_time_dom_resource_assignment(mac, - ulsch_config_pdu_0_0,NULL, + pusch_config_pdu_0_0,NULL, dci->time_dom_resource_assignment); /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; + pusch_config_pdu_0_0->frequency_hopping = dci->freq_hopping_flag; /* MCS */ - ulsch_config_pdu_0_0->mcs = dci->mcs; + pusch_config_pdu_0_0->mcs_index = dci->mcs; /* NDI */ - ulsch_config_pdu_0_0->ndi = dci->ndi; + pusch_config_pdu_0_0->pusch_data.new_data_indicator = dci->ndi; /* RV */ - ulsch_config_pdu_0_0->rv = dci->rv; + pusch_config_pdu_0_0->pusch_data.rv_index = dci->rv; /* HARQ_PROCESS_NUMBER */ - ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number; + pusch_config_pdu_0_0->pusch_data.harq_process_id = dci->harq_process_number; /* TPC_PUSCH */ // according to TS 38.213 Table Table 7.1.1-1 if (dci->tpc_pusch == 0) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4; + pusch_config_pdu_0_0->absolute_delta_PUSCH = -4; } if (dci->tpc_pusch == 1) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1; + pusch_config_pdu_0_0->absolute_delta_PUSCH = -1; } if (dci->tpc_pusch == 2) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1; + pusch_config_pdu_0_0->absolute_delta_PUSCH = 1; } if (dci->tpc_pusch == 3) { - ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3; - ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4; + pusch_config_pdu_0_0->absolute_delta_PUSCH = 4; } /* SUL_IND_0_0 */ // To be implemented, FIXME!!! @@ -2028,49 +2014,45 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space */ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; - fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; + ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rnti = rnti; + nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu; /* IDENTIFIER_DCI_FORMATS */ /* CARRIER_IND */ /* SUL_IND_0_1 */ /* BANDWIDTH_PART_IND */ - ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind; + //pusch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind; //FIXME /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,ulsch_config_pdu_0_1,NULL, + nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_1,NULL, dci->time_dom_resource_assignment); /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; + pusch_config_pdu_0_1->frequency_hopping = dci->freq_hopping_flag; /* MCS */ - ulsch_config_pdu_0_1->mcs = dci->mcs; + pusch_config_pdu_0_1->mcs_index = dci->mcs; /* NDI */ - ulsch_config_pdu_0_1->ndi = dci->ndi; + pusch_config_pdu_0_1->pusch_data.new_data_indicator = dci->ndi; /* RV */ - ulsch_config_pdu_0_1->rv = dci->rv; + pusch_config_pdu_0_1->pusch_data.rv_index = dci->rv; /* HARQ_PROCESS_NUMBER */ - ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number; + pusch_config_pdu_0_1->pusch_data.harq_process_id = dci->harq_process_number; /* FIRST_DAI */ //To be implemented, FIXME!!! /* SECOND_DAI */ //To be implemented, FIXME!!! /* TPC_PUSCH */ // according to TS 38.213 Table Table 7.1.1-1 if (dci->tpc_pusch == 0) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4; + pusch_config_pdu_0_1->absolute_delta_PUSCH = -4; } if (dci->tpc_pusch == 1) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1; + pusch_config_pdu_0_1->absolute_delta_PUSCH = -1; } if (dci->tpc_pusch == 2) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1; + pusch_config_pdu_0_1->absolute_delta_PUSCH = 1; } if (dci->tpc_pusch == 3) { - ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3; - ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4; + pusch_config_pdu_0_1->absolute_delta_PUSCH = 4; } /* SRS_RESOURCE_IND */ //FIXME!! @@ -2087,16 +2069,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5]; } } // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1 @@ -2104,16 +2086,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11]; } } } @@ -2122,12 +2104,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15]; } } // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1 @@ -2135,12 +2117,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19]; } } } @@ -2150,146 +2132,158 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6 - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = dci->antenna_ports; //TBC } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7 - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports); - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports); //TBC + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; //FIXME } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports); + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 1)?2:1; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports); //TBC } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0; - ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?2:1; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0; + //pusch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1; } if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = 0; - ulsch_config_pdu_0_1->dmrs_ports[1] = 1; - ulsch_config_pdu_0_1->dmrs_ports[2] = 2; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = 0; + //pusch_config_pdu_0_1->dmrs_ports[1] = 1; + //pusch_config_pdu_0_1->dmrs_ports[2] = 2; } if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = 0; - ulsch_config_pdu_0_1->dmrs_ports[1] = 1; - ulsch_config_pdu_0_1->dmrs_ports[2] = 2; - ulsch_config_pdu_0_1->dmrs_ports[3] = 3; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = 0; + //pusch_config_pdu_0_1->dmrs_ports[1] = 1; + //pusch_config_pdu_0_1->dmrs_ports[2] = 2; + //pusch_config_pdu_0_1->dmrs_ports[3] = 3; } } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 1)?2:1; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; //TBC + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1; //FIXME } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?2:1; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; // FIXME } if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3]; + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; //FIXME } if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3]; + //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4]; + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; //FIXME } } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; //TBC } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2]; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2]; } if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3]; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?3:2; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3]; } if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = 0; - ulsch_config_pdu_0_1->dmrs_ports[1] = 1; - ulsch_config_pdu_0_1->dmrs_ports[2] = 2; - ulsch_config_pdu_0_1->dmrs_ports[3] = 3; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = dci->antenna_ports + 2; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = 0; + //pusch_config_pdu_0_1->dmrs_ports[1] = 1; + //pusch_config_pdu_0_1->dmrs_ports[2] = 2; + //pusch_config_pdu_0_1->dmrs_ports[3] = 3; } } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2]; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_20[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->dmrs_ports = table_7_3_1_1_2_20[dci->antenna_ports][1]; //TBC + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2]; //FIXME } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3]; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_21[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3]; //FIXME } if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4]; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_22[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3]; + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4]; //FIXME } if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5]; + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_23[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3]; + //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4]; + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5]; //FIXME } } /* SRS_REQUEST */ // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 + //pusch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 //FIXME /* CSI_REQUEST */ - ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request; + //pusch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request; //FIXME /* CBGTI */ - ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti; + //pusch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti; //FIXME /* PTRS_DMRS */ if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) || ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){ } else { - ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs; + //pusch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs; //FIXME } /* BETA_OFFSET_IND */ // Table 9.3-3 in [5, TS 38.213] - ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind; + //pusch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind; //FIXME /* DMRS_SEQ_INI */ // FIXME!! /* UL_SCH_IND */ diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index c911fbd56a..b5fdea6760 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -51,7 +51,6 @@ extern RAN_CONTEXT_t RC; extern void mac_top_init_gNB(void); extern uint8_t nfapi_mode; - void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigCommon_t *scc) { nfapi_nr_config_request_scf_t *cfg = &RC.nrmac[Mod_idP]->config[0]; @@ -283,7 +282,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm else LOG_I(PHY,"TDD has been properly configurated\n"); } - /* // PDCCH-ConfigCommon cfg->pdcch_config.controlResourceSetZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index e5840d9cd1..702b034809 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -61,6 +61,8 @@ uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 }; +uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; + void clear_nr_nfapi_information(gNB_MAC_INST * gNB, int CC_idP, frame_t frameP, @@ -299,6 +301,67 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) } */ +void nr_schedule_pucch(int Mod_idP, + int UE_id, + frame_t frameP, + sub_frame_t slotP) { + + uint16_t O_uci; + uint16_t O_ack; + uint8_t SR_flag = 0; // no SR in PUCCH implemented for now + NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; + AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id); + + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + int bwp_id=1; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; + + NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; + NR_sched_pucch *temp_pucch; + int release_pucch = 0; + + if (curr_pucch != NULL) { + if ((frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { + UL_tti_req->SFN = frameP; + UL_tti_req->Slot = slotP; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pucch_pdu_t); + nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pucch_pdu; + memset(pucch_pdu,0,sizeof(nfapi_nr_pucch_pdu_t)); + UL_tti_req->n_pdus+=1; + O_ack = curr_pucch->dai_c; + O_uci = O_ack; // for now we are just sending acknacks in pucch + + nr_configure_pucch(pucch_pdu, + scc, + ubwp, + curr_pucch->resource_indicator, + O_uci, + O_ack, + SR_flag); + + release_pucch = 1; + } + } + + if (release_pucch) { + temp_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; + UE_list->UE_sched_ctrl[UE_id].sched_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch->next_sched_pucch; + free(temp_pucch); + } + +} + +bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){ + + if((bitmap>>slot)&0x01) + return true; + else + return false; +} + void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame_rxP, sub_frame_t slot_rxP, @@ -312,8 +375,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, int CC_id, UE_id = 0; gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_UE_list_t *UE_list = &gNB->UE_list; - UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; NR_COMMON_channels_t *cc = gNB->common_channels; + NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); start_meas(&RC.nrmac[module_idP]->eNB_scheduler); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); @@ -327,27 +391,27 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Check if there are downlink symbols in the slot, if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) { - memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - //mbsfn_status[CC_id] = 0; + memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { + //mbsfn_status[CC_id] = 0; - // clear vrb_maps - memset(cc[CC_id].vrb_map, 0, 100); - memset(cc[CC_id].vrb_map_UL, 0, 100); + // clear vrb_maps + memset(cc[CC_id].vrb_map, 0, 100); + memset(cc[CC_id].vrb_map_UL, 0, 100); - clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); - } + clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); + } - // refresh UE list based on UEs dropped by PHY in previous subframe - /* - for (i = 0; i < MAX_MOBILES_PER_GNB; i++) { - if (UE_list->active[i]) { + // refresh UE list based on UEs dropped by PHY in previous subframe + /* + for (i = 0; i < MAX_MOBILES_PER_GNB; i++) { + if (UE_list->active[i]) { - nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; + nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; - rnti = 0;//UE_RNTI(module_idP, i); - CC_id = 0;//UE_PCCID(module_idP, i); + rnti = 0;//UE_RNTI(module_idP, i); + CC_id = 0;//UE_PCCID(module_idP, i); } //END if (UE_list->active[i]) } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) @@ -359,7 +423,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } // TbD once RACH is available, start ta_timer when UE is connected - if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; +#if 0 + if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; if (ue_sched_ctl->ta_timer == 0) { gNB->ta_command = ue_sched_ctl->ta_update; @@ -371,19 +436,20 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, /* MAC CE flag indicating TA length */ gNB->ta_len = 2; } +#endif // Phytest scheduling if (get_softmodem_params()->phy_test && slot_txP==1){ - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); - // resetting ta flag + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); + // resetting ta flag gNB->ta_len = 0; } - /* - // Allocate CCEs for good after scheduling is done - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) - allocate_CCEs(module_idP, CC_id, subframeP, 0); - */ + /* + // Allocate CCEs for good after scheduling is done + for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) + allocate_CCEs(module_idP, CC_id, subframeP, 0); + */ } //is_nr_DL_slot diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 1e0fd8d9a2..050f07ba67 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -249,9 +249,14 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, } } + + + + int configure_fapi_dl_pdu(int Mod_idP, int *CCEIndex, nfapi_nr_dl_tti_request_body_t *dl_req, + NR_sched_pucch *pucch_sched, uint8_t *mcsIndex, uint16_t *rbSize, uint16_t *rbStart) { @@ -260,13 +265,12 @@ int configure_fapi_dl_pdu(int Mod_idP, gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; NR_COMMON_channels_t *cc = nr_mac->common_channels; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu; nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; int TBS, bwp_id = 1, UE_id = 0; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; - NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList has %d BWP!\n", @@ -351,10 +355,10 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].ndi = 1; dci_pdu_rel15[0].rv = 0; dci_pdu_rel15[0].harq_pid = 0; - dci_pdu_rel15[0].dai = 2; + dci_pdu_rel15[0].dai = (pucch_sched->dai_c-1)&3; dci_pdu_rel15[0].tpc = 2; - dci_pdu_rel15[0].pucch_resource_indicator = 7; - dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; + dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator; + dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = pucch_sched->timing_indicator; LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", dci_pdu_rel15[0].frequency_domain_assignment, @@ -413,7 +417,6 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->NrOfCodewords, pdsch_pdu_rel15->mcsIndex[0], TBS); - return TBS; //Return TBS in bytes } @@ -491,6 +494,7 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP, void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, + NR_sched_pucch *pucch_sched, nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){ LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n"); @@ -537,7 +541,8 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, TBS_bytes = configure_fapi_dl_pdu(module_idP, CCEIndices, - dl_req, + dl_req, + pucch_sched, dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL, dlsch_config!=NULL ? &dlsch_config->rbSize : NULL, dlsch_config!=NULL ? &dlsch_config->rbStart : NULL); @@ -562,7 +567,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS_bytes - ta_len - header_length_total - sdu_length_total - 3, 0, 0); @@ -579,7 +583,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS_bytes, + TBS_bytes - ta_len - header_length_total - sdu_length_total - 3, (char *)&mac_sdus[sdu_length_total], 0, 0); @@ -599,13 +603,11 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, break; } } - } //if (IS_SOFTMODEM_NOS1) else { //When the --NOS1 option is not enabled, DLSCH transmissions with random data //occur every time that the current function is called (dlsch phytest mode) - LOG_D(MAC,"Configuring DL_TX in %d.%d\n", frameP, slotP); // fill dlsch_buffer with random data @@ -719,12 +721,12 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, UL_tti_req->SFN = frameP; UL_tti_req->Slot = slotP; - UL_tti_req->n_pdus = 1; - UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; - UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pusch_pdu; memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); - + UL_tti_req->n_pdus+=1; + LOG_D(MAC, "Scheduling UE specific PUSCH\n"); //UL_tti_req = &nr_mac->UL_tti_req[CC_id]; /* @@ -758,14 +760,6 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->transform_precoding = 0; pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.; pusch_pdu->nrOfLayers = 1; - //DMRS - pusch_pdu->ul_dmrs_symb_pos = 1<<2; //for now the gnb assumes dmrs in the first symbol of the scheduled pusch resource - pusch_pdu->dmrs_config_type = 0; //dmrs-type 1 (the one with a single DMRS symbol in the beginning) - pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. - pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. - //pusch_pdu->num_dmrs_cdm_grps_no_data; - //pusch_pdu->dmrs_ports; //DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used - //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] pusch_pdu->resource_alloc = 1; //type 1 //pusch_pdu->rb_bitmap;// for ressource alloc type 0 pusch_pdu->rb_start = 0; @@ -777,6 +771,40 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, //Resource Allocation in time domain pusch_pdu->start_symbol_index = 2; pusch_pdu->nr_of_symbols = 12; + + // -------------------- + // ------- DMRS ------- + // -------------------- + uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); + pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index; + pusch_pdu->dmrs_config_type = 0; // dmrs-type 1 (the one with a single DMRS symbol in the beginning) + pusch_pdu->ul_dmrs_scrambling_id = 0; // If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id + pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1] + // Should match what is sent in DCI 0_1, otherwise set to 0 + //pusch_pdu->num_dmrs_cdm_grps_no_data; + //pusch_pdu->dmrs_ports; // DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports + // Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011, + // and for each bit 0: DMRS port not used 1: DMRS port used + // -------------------------------------------------------------------------------------------------------------------------------------------- + + // -------------------- + // ------- PTRS ------- + // -------------------- + uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig + uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig + uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig + uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig + uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig + pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table); + pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size); + pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); + pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + + if(1<pusch_ptrs.ptrs_time_density >= pusch_pdu->nr_of_symbols) + pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + // -------------------------------------------------------------------------------------------------------------------------------------------- + + //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] //Optional Data only included if indicated in pduBitmap pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; @@ -785,7 +813,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->target_code_rate, pusch_pdu->rb_size, pusch_pdu->nr_of_symbols, - 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + pusch_pdu->dmrs_config_type?4:6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI 0, //nb_rb_oh pusch_pdu->nrOfLayers)>>3; pusch_pdu->pusch_data.num_cb = 0; //CBG not supported @@ -821,7 +849,6 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, 1, // ue-specific, scc, bwp); - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 9376855882..6d3f69f217 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -507,7 +507,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss; + NR_SearchSpace_t *ss=NULL; int found=0; int target_ss = NR_SearchSpace__searchSpaceType_PR_common; if (ss_type == 1) { @@ -545,12 +545,196 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } +// This function configures pucch pdu fapi structure +void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Uplink_t *bwp, + uint8_t pucch_resource, + uint16_t O_uci, + uint16_t O_ack, + uint8_t SR_flag) { + + NR_PUCCH_Config_t *pucch_Config; + NR_PUCCH_Resource_t *pucchres; + NR_PUCCH_ResourceSet_t *pucchresset; + NR_PUCCH_FormatConfig_t *pucchfmt; + NR_PUCCH_ResourceId_t *resource_id = NULL; + + long *id0 = NULL; + int n_list, n_set; + uint16_t N2,N3; + int res_found = 0; + + pucch_pdu->bit_len_harq = O_ack; + + if (bwp) { // This is not the InitialBWP + + NR_PUSCH_Config_t *pusch_Config = bwp->bwp_Dedicated->pusch_Config->choice.setup; + long *pusch_id = pusch_Config->dataScramblingIdentityPUSCH; + + if (pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA != NULL) + id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup->transformPrecodingDisabled->scramblingID0; + if (pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB != NULL) + id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup->transformPrecodingDisabled->scramblingID0; + + // hop flags and hopping id are valid for any BWP + switch (bwp->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping){ + case 0 : + // if neither, both disabled + pucch_pdu->group_hop_flag = 0; + pucch_pdu->sequence_hop_flag = 0; + break; + case 1 : + // if enable, group enabled + pucch_pdu->group_hop_flag = 1; + pucch_pdu->sequence_hop_flag = 0; + break; + case 2 : + // if disable, sequence disabled + pucch_pdu->group_hop_flag = 0; + pucch_pdu->sequence_hop_flag = 1; + break; + default: + AssertFatal(1==0,"Group hopping flag %ld undefined (0,1,2) \n", bwp->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping); + } + + if (bwp->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId != NULL) + pucch_pdu->hopping_id = *bwp->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId; + else + pucch_pdu->hopping_id = *scc->physCellId; + + pucch_pdu->bwp_size = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pucch_pdu->bwp_start = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pucch_pdu->subcarrier_spacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; + pucch_pdu->cyclic_prefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix; + + pucch_Config = bwp->bwp_Dedicated->pucch_Config->choice.setup; + + AssertFatal(pucch_Config->resourceSetToAddModList!=NULL, + "PUCCH resourceSetToAddModList is null\n"); + + n_set = pucch_Config->resourceSetToAddModList->list.count; + AssertFatal(n_set>0,"PUCCH resourceSetToAddModList is empty\n"); + + N2 = 2; + // procedure to select pucch resource id from resource sets according to + // number of uci bits and pucch resource indicator pucch_resource + // ( see table 9.2.3.2 in 38.213) + for (int i=0; iresourceSetToAddModList->list.array[i]; + n_list = pucchresset->resourceList.list.count; + if (pucchresset->pucch_ResourceSetId == 0 && O_uci<3) { + if (pucch_resource < n_list) + resource_id = pucchresset->resourceList.list.array[pucch_resource]; + else + AssertFatal(1==0,"Couldn't fine pucch resource indicator %d in PUCCH resource set %d for %d UCI bits",pucch_resource,i,O_uci); + } + else { + N3 = pucchresset->maxPayloadMinus1!= NULL ? *pucchresset->maxPayloadMinus1 : 1706; + if (N2O_uci) { + if (pucch_resource < n_list) + resource_id = pucchresset->resourceList.list.array[pucch_resource]; + else + AssertFatal(1==0,"Couldn't fine pucch resource indicator %d in PUCCH resource set %d for %d UCI bits",pucch_resource,i,O_uci); + } + else N2 = N3; + } + } + + AssertFatal(resource_id!=NULL,"Couldn-t find any matching PUCCH resource in the PUCCH resource sets"); + + AssertFatal(pucch_Config->resourceToAddModList!=NULL, + "PUCCH resourceToAddModList is null\n"); + + n_list = pucch_Config->resourceToAddModList->list.count; + AssertFatal(n_list>0,"PUCCH resourceToAddModList is empty\n"); + + // going through the list of PUCCH resources to find the one indexed by resource_id + for (int i=0; iresourceToAddModList->list.array[i]; + if (pucchres->pucch_ResourceId == *resource_id) { + res_found = 1; + pucch_pdu->prb_start = pucchres->startingPRB; + // FIXME why there is only one frequency hopping flag + // what about inter slot frequency hopping? + pucch_pdu->freq_hop_flag = pucchres->intraSlotFrequencyHopping!= NULL ? 1 : 0; + pucch_pdu->second_hop_prb = pucchres->secondHopPRB!= NULL ? *pucchres->secondHopPRB : 0; + switch(pucchres->format.present) { + case NR_PUCCH_Resource__format_PR_format0 : + pucch_pdu->format_type = 0; + pucch_pdu->initial_cyclic_shift = pucchres->format.choice.format0->initialCyclicShift; + pucch_pdu->nr_of_symbols = pucchres->format.choice.format0->nrofSymbols; + pucch_pdu->start_symbol_index = pucchres->format.choice.format0->startingSymbolIndex; + pucch_pdu->sr_flag = SR_flag; + break; + case NR_PUCCH_Resource__format_PR_format1 : + pucch_pdu->format_type = 1; + pucch_pdu->initial_cyclic_shift = pucchres->format.choice.format1->initialCyclicShift; + pucch_pdu->nr_of_symbols = pucchres->format.choice.format1->nrofSymbols; + pucch_pdu->start_symbol_index = pucchres->format.choice.format1->startingSymbolIndex; + pucch_pdu->time_domain_occ_idx = pucchres->format.choice.format1->timeDomainOCC; + pucch_pdu->sr_flag = SR_flag; + break; + case NR_PUCCH_Resource__format_PR_format2 : + pucch_pdu->format_type = 2; + pucch_pdu->nr_of_symbols = pucchres->format.choice.format2->nrofSymbols; + pucch_pdu->start_symbol_index = pucchres->format.choice.format2->startingSymbolIndex; + pucch_pdu->prb_size = pucchres->format.choice.format2->nrofPRBs; + pucch_pdu->data_scrambling_id = pusch_id!= NULL ? *pusch_id : *scc->physCellId; + pucch_pdu->dmrs_scrambling_id = id0!= NULL ? *id0 : *scc->physCellId; + break; + case NR_PUCCH_Resource__format_PR_format3 : + pucch_pdu->format_type = 3; + pucch_pdu->nr_of_symbols = pucchres->format.choice.format3->nrofSymbols; + pucch_pdu->start_symbol_index = pucchres->format.choice.format3->startingSymbolIndex; + pucch_pdu->prb_size = pucchres->format.choice.format3->nrofPRBs; + pucch_pdu->data_scrambling_id = pusch_id!= NULL ? *pusch_id : *scc->physCellId; + if (pucch_Config->format3 == NULL) { + pucch_pdu->pi_2bpsk = 0; + pucch_pdu->add_dmrs_flag = 0; + } + else { + pucchfmt = pucch_Config->format3->choice.setup; + pucch_pdu->pi_2bpsk = pucchfmt->pi2BPSK!= NULL ? 1 : 0; + pucch_pdu->add_dmrs_flag = pucchfmt->additionalDMRS!= NULL ? 1 : 0; + } + break; + case NR_PUCCH_Resource__format_PR_format4 : + pucch_pdu->format_type = 4; + pucch_pdu->nr_of_symbols = pucchres->format.choice.format4->nrofSymbols; + pucch_pdu->start_symbol_index = pucchres->format.choice.format4->startingSymbolIndex; + pucch_pdu->pre_dft_occ_len = pucchres->format.choice.format4->occ_Length; + pucch_pdu->pre_dft_occ_idx = pucchres->format.choice.format4->occ_Index; + pucch_pdu->data_scrambling_id = pusch_id!= NULL ? *pusch_id : *scc->physCellId; + if (pucch_Config->format3 == NULL) { + pucch_pdu->pi_2bpsk = 0; + pucch_pdu->add_dmrs_flag = 0; + } + else { + pucchfmt = pucch_Config->format3->choice.setup; + pucch_pdu->pi_2bpsk = pucchfmt->pi2BPSK!= NULL ? 1 : 0; + pucch_pdu->add_dmrs_flag = pucchfmt->additionalDMRS!= NULL ? 1 : 0; + } + break; + default : + AssertFatal(1==0,"Undefined PUCCH format \n"); + } + } + } + AssertFatal(res_found==1,"No PUCCH resource found corresponding to id %ld\n",*resource_id); + } + else { // this is for InitialBWP + AssertFatal(1==0,"Fill in InitialBWP PUCCH configuration\n"); + } + +} + + void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, - int *rnti_types - ) { + int *rnti_types) { uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; @@ -1003,6 +1187,171 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ return -1; } + +void get_pdsch_to_harq_feedback(int Mod_idP, + int UE_id, + NR_SearchSpace__searchSpaceType_PR ss_type, + uint8_t *pdsch_to_harq_feedback) { + + int bwp_id=1; + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + + NR_SearchSpace_t *ss; + + // common search type uses DCI format 1_0 + if (ss_type == NR_SearchSpace__searchSpaceType_PR_common) { + for (int i=0; i<8; i++) + pdsch_to_harq_feedback[i] = i+1; + } + else { + // searching for a ue specific search space + int found=0; + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (ss->searchSpaceType->present == ss_type) { + found=1; + break; + } + } + AssertFatal(found==1,"Couldn't find a ue specific searchspace\n"); + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats == NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) { + for (int i=0; i<8; i++) + pdsch_to_harq_feedback[i] = i+1; + } + else { + if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) + pdsch_to_harq_feedback = (uint8_t *)ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK; + else + AssertFatal(found==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n"); + } + } +} + + +// function to update pucch scheduling parameters in UE list when a USS DL is scheduled +void nr_update_pucch_scheduling(int Mod_idP, + int UE_id, + frame_t frameP, + sub_frame_t slotP, + int slots_per_tdd, + NR_sched_pucch *sched_pucch) { + + NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; + int first_ul_slot_tdd,k; + NR_sched_pucch *curr_pucch; + uint8_t pdsch_to_harq_feedback[8]; + int found = 0; + int i = 0; + int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) + nr_ulmix_slots++; + + // this is hardcoded for now as ue specific + NR_SearchSpace__searchSpaceType_PR ss_type = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + get_pdsch_to_harq_feedback(Mod_idP,UE_id,ss_type,pdsch_to_harq_feedback); + + // if the list of pucch to be scheduled is empty + if (UE_list->UE_sched_ctrl[UE_id].sched_pucch == NULL) { + sched_pucch->frame = frameP; + sched_pucch->next_sched_pucch = NULL; + sched_pucch->dai_c = 1; + sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource + if ( nr_ulmix_slots > 0 ) { + // first pucch occasion in first UL or MIXED slot + first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; + for (k=0; kul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); + sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + } + else + AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n"); + } + else + AssertFatal(1==0,"No Uplink Slots in this Frame\n"); + + UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; + } + else { // to be tested + curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; + if (curr_pucch->dai_cul_slot % slots_per_tdd)-(slotP % slots_per_tdd)) + found = 1; + if (found == 0) i++; + } + if (found == 1) { // scheduling this harq-ack in current pucch + sched_pucch = curr_pucch; + sched_pucch->dai_c = 1 + sched_pucch->dai_c; + sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + } + } + if (curr_pucch->dai_c==MAX_ACK_BITS || found == 0) { // if current pucch is full or no timing indicator allowed + // look for pucch occasions in other UL of mixed slots + for (k=scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; kul_slot % slots_per_tdd)) { // skip current scheduled slot (already checked) + i = 0; + while (i<8 && found == 0) { // look if timing indicator is among allowed values + if (pdsch_to_harq_feedback[i]==k-(slotP % slots_per_tdd)) + found = 1; + if (found == 0) i++; + } + if (found == 1) { + if (k<(curr_pucch->ul_slot % slots_per_tdd)) { // we need to add a pucch occasion before current pucch + sched_pucch->frame = frameP; + sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); + sched_pucch->next_sched_pucch = curr_pucch; + sched_pucch->dai_c = 1; + sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource + sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; + } + else { + while (curr_pucch->next_sched_pucch != NULL && k!=(curr_pucch->ul_slot % slots_per_tdd)) + curr_pucch = curr_pucch->next_sched_pucch; + if (curr_pucch == NULL) { // creating a new item in the list + sched_pucch->frame = frameP; + sched_pucch->next_sched_pucch = NULL; + sched_pucch->dai_c = 1; + sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource + sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); + curr_pucch->next_sched_pucch = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); + curr_pucch->next_sched_pucch = sched_pucch; + } + else { + if (curr_pucch->dai_c==MAX_ACK_BITS) + found = 0; // if pucch at index k is already full we have to find a new one in a following occasion + else { // scheduling this harq-ack in current pucch + sched_pucch = curr_pucch; + sched_pucch->dai_c = 1 + sched_pucch->dai_c; + sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + } + } + } + } + } + } + } + } +} + + /*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg, nfapi_nr_coreset_t *coreset, nfapi_nr_search_space_t *search_space) { diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index ade5200627..eb8d338949 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -236,7 +236,7 @@ void nr_process_mac_pdu( void nr_rx_sdu(const module_id_t gnb_mod_idP, const int CC_idP, const frame_t frameP, - const sub_frame_t subframeP, + const sub_frame_t slotP, const rnti_t rntiP, uint8_t *sduP, const uint16_t sdu_lenP, @@ -245,7 +245,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, int current_rnti = 0, UE_id = -1, harq_pid = 0; gNB_MAC_INST *gNB_mac = NULL; NR_UE_list_t *UE_list = NULL; - UE_sched_ctrl_t *UE_scheduling_control = NULL; + NR_UE_sched_ctrl_t *UE_scheduling_control = NULL; current_rnti = rntiP; UE_id = find_nr_UE_id(gnb_mod_idP, current_rnti); @@ -255,13 +255,12 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, if (UE_id != -1) { UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]); - LOG_D(MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu round %d from PHY (rnti %x, UE_id %d) ul_cqi %d\n", + LOG_D(MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu from PHY (rnti %x, UE_id %d) ul_cqi %d\n", gnb_mod_idP, harq_pid, CC_idP, frameP, - subframeP, - UE_scheduling_control->round_UL[CC_idP][harq_pid], + slotP, current_rnti, UE_id, ul_cqi); @@ -277,7 +276,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, #endif if (sduP != NULL){ - UE_scheduling_control->ta_update = timing_advance; + //UE_scheduling_control->ta_update = timing_advance; LOG_D(MAC, "Received PDU at MAC gNB \n"); nr_process_mac_pdu(gnb_mod_idP, CC_idP, frameP, sduP, sdu_lenP); } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index d55a188817..c0f4053c03 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -35,6 +35,8 @@ #include "PHY/defs_gNB.h" #include "NR_TAG-Id.h" +#define MAX_ACK_BITS 2 //only format 0 is available for now + void set_cset_offset(uint16_t); void mac_top_init_gNB(void); @@ -83,6 +85,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, int configure_fapi_dl_pdu(int Mod_id, int *CCEIndeces, nfapi_nr_dl_tti_request_body_t *dl_req, + NR_sched_pucch *pucch_sched, uint8_t *mcsIndex, uint16_t *rbSize, uint16_t *rbStart); @@ -100,11 +103,24 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP, void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, + NR_sched_pucch *pucch_sched, nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_config); void nr_schedule_uss_ulsch_phytest(int Mod_idP, frame_t frameP, sub_frame_t slotP); + +void nr_update_pucch_scheduling(int Mod_idP, + int UE_id, + frame_t frameP, + sub_frame_t slotP, + int slots_per_tdd, + NR_sched_pucch *sched_pucch); + +void get_pdsch_to_harq_feedback(int Mod_idP, + int UE_id, + NR_SearchSpace__searchSpaceType_PR ss_type, + uint8_t *pdsch_to_harq_feedback); void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, nr_scs_e scs_common, @@ -124,7 +140,13 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, uint16_t slot, nfapi_nr_config_request_scf_t cfg); */ - +void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Uplink_t *bwp, + uint8_t pucch_resource, + uint16_t O_uci, + uint16_t O_ack, + uint8_t SR_flag); void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, int ss_type, NR_ServingCellConfigCommon_t *scc, @@ -134,7 +156,6 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types); - int get_spf(nfapi_nr_config_request_scf_t *cfg); int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); @@ -162,6 +183,11 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP); int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); int get_num_dmrs(uint16_t dmrs_mask ); +uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position); +int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength); + +uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table); +uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB); uint16_t nr_dci_size(nr_dci_format_t format, nr_rnti_type_t rnti_type, diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 5bc320d5e2..bf9358dd43 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -102,9 +102,22 @@ typedef struct { uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; -/*! \brief scheduling control information set through an API (not used)*/ +typedef struct NR_sched_pucch { + int frame; + int ul_slot; + uint8_t dai_c; + uint8_t timing_indicator; + uint8_t resource_indicator; + struct NR_sched_pucch *next_sched_pucch; +} NR_sched_pucch; + +/*! \brief scheduling control information set through an API */ typedef struct { - int dummy; + uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch + uint64_t ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch + NR_sched_pucch *sched_pucch; + uint16_t ta_timer; + int16_t ta_update; } NR_UE_sched_ctrl_t; /*! \brief UE list used by eNB to order UEs/CC for scheduling*/ @@ -112,7 +125,7 @@ typedef struct { DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; /// scheduling control info - UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; + NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; int next[MAX_MOBILES_PER_GNB]; int head; int next_ul[MAX_MOBILES_PER_GNB]; @@ -124,7 +137,7 @@ typedef struct { NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; -/*! \brief top level eNB MAC structure */ +/*! \brief top level gNB MAC structure */ typedef struct gNB_MAC_INST_s { /// Ethernet parameters for northbound midhaul interface eth_params_t eth_params_n; @@ -191,64 +204,62 @@ typedef struct gNB_MAC_INST_s { } gNB_MAC_INST; typedef struct { - - -uint8_t format_indicator; //1 bit -uint16_t frequency_domain_assignment; //up to 16 bits -uint8_t time_domain_assignment; // 4 bits -uint8_t frequency_hopping_flag; //1 bit - -uint8_t ra_preamble_index; //6 bits -uint8_t ss_pbch_index; //6 bits -uint8_t prach_mask_index; //4 bits - -uint8_t vrb_to_prb_mapping; //0 or 1 bit -uint8_t mcs; //5 bits -uint8_t ndi; //1 bit -uint8_t rv; //2 bits -uint8_t harq_pid; //4 bits -uint8_t dai; //0, 2 or 4 bits -uint8_t dai1; //1 or 2 bits -uint8_t dai2; //0 or 2 bits -uint8_t tpc; //2 bits -uint8_t pucch_resource_indicator; //3 bits -uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - -uint8_t short_messages_indicator; //2 bits -uint8_t short_messages; //8 bits -uint8_t tb_scaling; //2 bits - -uint8_t carrier_indicator; //0 or 3 bits -uint8_t bwp_indicator; //0, 1 or 2 bits -uint8_t prb_bundling_size_indicator; //0 or 1 bits -uint8_t rate_matching_indicator; //0, 1 or 2 bits -uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits -uint8_t transmission_configuration_indication; //0 or 3 bits -uint8_t srs_request; //2 bits -uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits -uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit -uint8_t dmrs_sequence_initialization; //0 or 1 bit - -uint8_t srs_resource_indicator; -uint8_t precoding_information; -uint8_t csi_request; -uint8_t ptrs_dmrs_association; -uint8_t beta_offset_indicator; //0 or 2 bits - -uint8_t slot_format_indicator_count; -uint8_t *slot_format_indicators; - -uint8_t pre_emption_indication_count; -uint16_t *pre_emption_indications; //14 bit - -uint8_t block_number_count; -uint8_t *block_numbers; - -uint8_t ul_sul_indicator; //0 or 1 bit -uint8_t antenna_ports; - -uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits -uint16_t padding; + uint8_t format_indicator; //1 bit + uint16_t frequency_domain_assignment; //up to 16 bits + uint8_t time_domain_assignment; // 4 bits + uint8_t frequency_hopping_flag; //1 bit + + uint8_t ra_preamble_index; //6 bits + uint8_t ss_pbch_index; //6 bits + uint8_t prach_mask_index; //4 bits + + uint8_t vrb_to_prb_mapping; //0 or 1 bit + uint8_t mcs; //5 bits + uint8_t ndi; //1 bit + uint8_t rv; //2 bits + uint8_t harq_pid; //4 bits + uint8_t dai; //0, 2 or 4 bits + uint8_t dai1; //1 or 2 bits + uint8_t dai2; //0 or 2 bits + uint8_t tpc; //2 bits + uint8_t pucch_resource_indicator; //3 bits + uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + + uint8_t short_messages_indicator; //2 bits + uint8_t short_messages; //8 bits + uint8_t tb_scaling; //2 bits + + uint8_t carrier_indicator; //0 or 3 bits + uint8_t bwp_indicator; //0, 1 or 2 bits + uint8_t prb_bundling_size_indicator; //0 or 1 bits + uint8_t rate_matching_indicator; //0, 1 or 2 bits + uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits + uint8_t transmission_configuration_indication; //0 or 3 bits + uint8_t srs_request; //2 bits + uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits + uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit + uint8_t dmrs_sequence_initialization; //0 or 1 bit + + uint8_t srs_resource_indicator; + uint8_t precoding_information; + uint8_t csi_request; + uint8_t ptrs_dmrs_association; + uint8_t beta_offset_indicator; //0 or 2 bits + + uint8_t slot_format_indicator_count; + uint8_t *slot_format_indicators; + + uint8_t pre_emption_indication_count; + uint16_t *pre_emption_indications; //14 bit + + uint8_t block_number_count; + uint8_t *block_numbers; + + uint8_t ul_sul_indicator; //0 or 1 bit + uint8_t antenna_ports; + + uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + uint16_t padding; } dci_pdu_rel15_t; diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h b/openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h deleted file mode 100644 index b9f62acc3c..0000000000 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/* - pdcp_proto_extern.h - ------------------- - AUTHOR : Lionel GAUTHIER - COMPANY : EURECOM - EMAIL : Lionel.Gauthier@eurecom.fr - - ***************************************************************************/ -#ifndef __PDCP_PROTO_EXTERN_H__ -# define __PDCP_PROTO_EXTERN_H__ - -//# include "pdcp_entity.h" -//# include "rb_mux.h" -# include "mem_block.h" - -#ifdef ROHC -extern void pdcp_data_ind (module_id_t module_idP, rb_id_t rab_idP, sdu_size_t data_sizeP, mem_block_t *sduP); -extern void pdcp_data_req (struct pdcp_entity *pdcpP, mem_block *sduP); -extern void send_pdcp_control_primitive (struct pdcp_entity *pdcpP, mem_block *cprimitiveP); -extern void control_pdcp (struct pdcp_entity *pdcpP); -extern void pdcp_process_input_sdus_high(struct pdcp_entity *pdcpP); -extern void pdcp_process_input_sdus_am (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP); -extern void pdcp_process_output_sdus (struct pdcp_entity *pdcpP, mem_block *sduP, uint8_t rb_idP); -extern void pdcp_process_output_sdus_high (struct pdcp_entity *pdcpP, mem_block *sduP, uint16_t data_sizeP, uint16_t rb_idP); -extern void pdcp_process_input_sdus_um (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP); -extern void pdcp_process_input_sdus_tr (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP); -extern void init_pdcp (struct pdcp_entity *pdcpP, struct rb_dispatcher *rbP, uint8_t rb_idP); -extern void *pdcp_tx (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP); -extern int reception_from_rohc_mt(void); -extern int reception_from_rohc_bs(void); -#else -extern BOOL pdcp_data_ind (module_id_t module_idP, rb_id_t rab_idP, sdu_size_t data_sizeP, mem_block_t *sduP, uint8_t is_data_plane); -extern BOOL pdcp_data_req (module_id_t module_id, uint32_t frame, uint8_t eNB_flag, rb_id_t rab_id, uint32_t muiP, uint32_t confirmP, sdu_size_t sdu_buffer_size, unsigned char *sdu_buffer, - uint8_t is_data_pdu,const uint32_t *const sourceL2Id,const uint32_t *const destinationL2Id - ); -//extern BOOL pdcp_data_req (struct pdcp_entity *pdcpP, mem_block * sduP); -extern void send_pdcp_control_primitive (struct pdcp_entity *pdcpP, mem_block *cprimitiveP); -extern void control_pdcp (struct pdcp_entity *pdcpP); -extern void pdcp_process_input_sdus_am (struct pdcp_entity *pdcpP); -extern void pdcp_process_output_sdus (struct pdcp_entity *pdcpP, mem_block *sduP, uint8_t rb_idP); -extern void pdcp_process_input_sdus_um (struct pdcp_entity *pdcpP); -extern void pdcp_process_input_sdus_tr (struct pdcp_entity *pdcpP); -extern void init_pdcp (struct pdcp_entity *pdcpP, struct rb_dispatcher *rbP, uint8_t rb_idP); -extern void *pdcp_tx (void *argP); -#endif - -extern void pdcp_pc5_socket_init(void); - -#endif diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent.c b/openair2/LAYER2/PROTO_AGENT/proto_agent.c index bead6ad28d..6bf9cdce22 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent.c +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent.c @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent.h * \brief top level enb agent receive thread and itti task diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent.h b/openair2/LAYER2/PROTO_AGENT/proto_agent.h index 927b714b2c..6898c9e447 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent.h +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent.h @@ -1,32 +1,23 @@ - -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file proto_agent.h * \brief top level protocol agent diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_async.c b/openair2/LAYER2/PROTO_AGENT/proto_agent_async.c index eef697c5bb..df3684ee27 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_async.c +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_async.c @@ -1,32 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ - +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ #include "proto_agent_async.h" #include "proto_agent_defs.h" diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_async.h b/openair2/LAYER2/PROTO_AGENT/proto_agent_async.h index 27030924cd..6bc952e804 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_async.h +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_async.h @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent_async.h * \brief channel implementation for async interface diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_common.c b/openair2/LAYER2/PROTO_AGENT/proto_agent_common.c index a11c029bd3..6e343343cd 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_common.c +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_common.c @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file proto_agent_common.c * \brief common primitives for all agents diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_common.h b/openair2/LAYER2/PROTO_AGENT/proto_agent_common.h index 70e6b2a84e..c805b81543 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_common.h +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_common.h @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent_common.h * \brief common message primitves and utilities diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_defs.h b/openair2/LAYER2/PROTO_AGENT/proto_agent_defs.h index 08c91e7085..cd730a6de8 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_defs.h +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_defs.h @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2016 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent_defs.h * \brief enb agent common definitions diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_handler.c b/openair2/LAYER2/PROTO_AGENT/proto_agent_handler.c index cb65da2803..82f7849717 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_handler.c +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_handler.c @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2014 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent_handler.c * \brief enb agent tx and rx message handler diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.c b/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.c index f64a58f8e1..9a63427ed5 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.c +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.c @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2016 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent_net_comm.c * \brief enb agent network interface abstraction diff --git a/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.h b/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.h index c956bf48b1..55fca5a928 100644 --- a/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.h +++ b/openair2/LAYER2/PROTO_AGENT/proto_agent_net_comm.h @@ -1,31 +1,23 @@ -/******************************************************************************* - OpenAirInterface - Copyright(c) 1999 - 2016 Eurecom - - OpenAirInterface is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - - OpenAirInterface is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with OpenAirInterface.The full GNU General Public License is - included in this distribution in the file called "COPYING". If not, - see . - - Contact Information - OpenAirInterface Admin: openair_admin@eurecom.fr - OpenAirInterface Tech : openair_tech@eurecom.fr - OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr - - Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France. - - *******************************************************************************/ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ /*! \file enb_agent_net_comm.h * \brief enb agent network interface abstraction diff --git a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c index 865a815359..de947225bb 100644 --- a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c +++ b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c @@ -459,7 +459,6 @@ struct mac_status_resp rlc_am_mac_status_indication ( const protocol_ctxt_t *const ctxt_pP, void *const rlc_pP, - const uint16_t tb_sizeP, struct mac_status_ind tx_statusP, const eNB_flag_t enb_flagP) { struct mac_status_resp status_resp; @@ -491,10 +490,6 @@ rlc_am_mac_status_indication ( rlc->last_absolute_subframe_status_indication = PROTOCOL_CTXT_TIME_MILLI_SECONDS(ctxt_pP); - if (tb_sizeP > 0) { - rlc->nb_bytes_requested_by_mac = tb_sizeP; - } - status_resp.buffer_occupancy_in_bytes = rlc_am_get_buffer_occupancy_in_bytes(ctxt_pP, rlc); // For eNB scheduler : Add Max RLC header size for new PDU @@ -549,8 +544,7 @@ rlc_am_mac_status_indication ( NULL,0, MSC_AS_TIME_FMT" "PROTOCOL_RLC_AM_MSC_FMT" STATUS-IND %u", MSC_AS_TIME_ARGS(ctxt_pP), - PROTOCOL_RLC_AM_MSC_ARGS(ctxt_pP, rlc), - tb_sizeP); + PROTOCOL_RLC_AM_MSC_ARGS(ctxt_pP, rlc)); MSC_LOG_TX_MESSAGE( (ctxt_pP->enb_flag == ENB_FLAG_YES) ? MSC_RLC_ENB:MSC_RLC_UE, (ctxt_pP->enb_flag == ENB_FLAG_YES) ? MSC_MAC_ENB:MSC_MAC_UE, @@ -565,26 +559,14 @@ rlc_am_mac_status_indication ( } if (LOG_DEBUGFLAG(DEBUG_RLC)) { - if (tb_sizeP > 0) { - LOG_UI(RLC, PROTOCOL_RLC_AM_CTXT_FMT" MAC_STATUS_INDICATION (DATA) %d bytes -> %d bytes\n", - PROTOCOL_RLC_AM_CTXT_ARGS(ctxt_pP,rlc), - tb_sizeP, - status_resp.buffer_occupancy_in_bytes); - } + LOG_UI(RLC, PROTOCOL_RLC_AM_CTXT_FMT" MAC_STATUS_INDICATION (DATA) -> %d bytes\n", + PROTOCOL_RLC_AM_CTXT_ARGS(ctxt_pP,rlc), + status_resp.buffer_occupancy_in_bytes); } return status_resp; } -//----------------------------------------------------------------------------- -void -rlc_am_set_nb_bytes_requested_by_mac ( - void *const rlc_pP, - const tb_size_t tb_sizeP -) { - ((rlc_am_entity_t *) rlc_pP)->nb_bytes_requested_by_mac = tb_sizeP; -} - //----------------------------------------------------------------------------- struct mac_data_req rlc_am_mac_data_request ( diff --git a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.h b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.h index f2cb456e8c..3127f67eca 100644 --- a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.h +++ b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.h @@ -255,23 +255,15 @@ rlc_am_get_pdus ( */ void rlc_am_rx (const protocol_ctxt_t* const ctxtP,void * const rlc_pP, struct mac_data_ind); -/*! \fn struct mac_status_resp rlc_am_mac_status_indication (const protocol_ctxt_t* const ctxtP,void * const rlc_pP, uint16_t tbs_sizeP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP) +/*! \fn struct mac_status_resp rlc_am_mac_status_indication (const protocol_ctxt_t* const ctxtP,void * const rlc_pP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP) * \brief Request the maximum number of bytes that can be served by RLC instance to MAC and fix the amount of bytes requested by MAC for next RLC transmission. * \param[in] ctxt_pP Running context. * \param[in] rlc_pP RLC AM protocol instance pointer. -* \param[in] tbs_sizeP Number of bytes requested by MAC for next transmission. * \param[in] tx_statusP Transmission status given by MAC on previous MAC transmission of the PDU. * \param[in] enb_flagP eNB or UE flag indication. * \return The maximum number of bytes that can be served by RLC instance to MAC. */ -struct mac_status_resp rlc_am_mac_status_indication (const protocol_ctxt_t* const ctxtP, void * const rlc_pP, uint16_t tbs_sizeP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP); - -/*! \fn void rlc_am_set_nb_bytes_requested_by_mac (void * const rlc_pP,const tb_size_t tb_sizeP) -* \brief Set available TBS for RLC Tx just before am_mac_data_request. Used for UE only. -* \param[in] rlc_pP RLC AM protocol instance pointer. -* \param[in] tb_sizeP Available Tx Transport Block size in bytes. -*/ -void rlc_am_set_nb_bytes_requested_by_mac (void * const rlc_pP,const tb_size_t tb_sizeP); +struct mac_status_resp rlc_am_mac_status_indication (const protocol_ctxt_t* const ctxtP, void * const rlc_pP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP); /*! \fn struct mac_data_req rlc_am_mac_data_request (const protocol_ctxt_t* const ctxtP,void * const rlc_pP,const eNB_flag_t enb_flagP) * \brief Gives PDUs to lower layer MAC. diff --git a/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.c b/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.c index e481550a46..4e3fffe176 100644 --- a/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.c +++ b/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.c @@ -151,13 +151,10 @@ struct mac_status_resp rlc_tm_mac_status_indication ( const protocol_ctxt_t* const ctxt_pP, void * const rlc_pP, - const tb_size_t tb_sizeP, struct mac_status_ind tx_statusP) { struct mac_status_resp status_resp; - ((rlc_tm_entity_t *) rlc_pP)->rlc_pdu_size = tb_sizeP; - status_resp.buffer_occupancy_in_bytes = ((rlc_tm_entity_t *) rlc_pP)->buffer_occupancy; status_resp.buffer_occupancy_in_pdus = status_resp.buffer_occupancy_in_bytes / ((rlc_tm_entity_t *) rlc_pP)->rlc_pdu_size; status_resp.rlc_info.rlc_protocol_state = ((rlc_tm_entity_t *) rlc_pP)->protocol_state; diff --git a/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.h b/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.h index 1ea9988707..d2bab33b1a 100644 --- a/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.h +++ b/openair2/LAYER2/RLC/TM_v9.3.0/rlc_tm.h @@ -88,11 +88,10 @@ void rlc_tm_rx ( struct mac_data_ind data_indP); -/*! \fn struct mac_status_resp rlc_tm_mac_status_indication (const protocol_ctxt_t* const ctxt_pP, void * const rlcP, const uint16_t tbs_sizeP, struct mac_status_ind tx_statusP) +/*! \fn struct mac_status_resp rlc_tm_mac_status_indication (const protocol_ctxt_t* const ctxt_pP, void * const rlcP, struct mac_status_ind tx_statusP) * \brief Request the maximum number of bytes that can be served by RLC instance to MAC and fix the amount of bytes requested by MAC for next RLC transmission. * \param[in] ctxtP Running context. * \param[in] rlcP RLC TM protocol instance pointer. -* \param[in] tbs_sizeP Number of bytes requested by MAC for next transmission. * \param[in] tx_statusP Transmission status given by MAC on previous MAC transmission of the PDU. * \return The maximum number of bytes that can be served by RLC instance to MAC. */ @@ -100,7 +99,6 @@ struct mac_status_resp rlc_tm_mac_status_indication ( const protocol_ctxt_t* const ctxt_pP, void * const rlc_pP, - const tb_size_t tb_sizeP, struct mac_status_ind tx_statusP); diff --git a/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.c b/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.c index c7dc11f51d..654ddb8da7 100644 --- a/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.c +++ b/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.c @@ -370,7 +370,7 @@ rlc_um_rx (const protocol_ctxt_t *const ctxt_pP, void *argP, struct mac_data_ind //----------------------------------------------------------------------------- struct mac_status_resp -rlc_um_mac_status_indication (const protocol_ctxt_t *const ctxt_pP, void *rlc_pP, uint16_t tbs_sizeP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP) { +rlc_um_mac_status_indication (const protocol_ctxt_t *const ctxt_pP, void *rlc_pP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP) { struct mac_status_resp status_resp; uint16_t sdu_size = 0; uint16_t sdu_remaining_size = 0; @@ -386,7 +386,6 @@ rlc_um_mac_status_indication (const protocol_ctxt_t *const ctxt_pP, void *rlc_pP if (rlc_pP) { status_resp.rlc_info.rlc_protocol_state = rlc_p->protocol_state; rlc_um_check_timer_dar_time_out(ctxt_pP, rlc_p); - rlc_p->nb_bytes_requested_by_mac = tbs_sizeP; status_resp.buffer_occupancy_in_bytes = rlc_um_get_buffer_occupancy (rlc_p); if ((status_resp.buffer_occupancy_in_bytes > 0) && ((mb_p = list_get_head(&rlc_p->input_sdus)) != NULL)) { @@ -416,9 +415,8 @@ rlc_um_mac_status_indication (const protocol_ctxt_t *const ctxt_pP, void *rlc_pP if (LOG_DEBUGFLAG(DEBUG_RLC)) { if (( rlc_p->rb_id > 0) && (status_resp.buffer_occupancy_in_bytes > 0)) { - LOG_UI(RLC, PROTOCOL_RLC_UM_CTXT_FMT"MAC_STATUS_INDICATION (DATA) %d bytes requested -> %d bytes available\n", + LOG_UI(RLC, PROTOCOL_RLC_UM_CTXT_FMT"MAC_STATUS_INDICATION (DATA) -> %d bytes available\n", PROTOCOL_RLC_UM_CTXT_ARGS(ctxt_pP,rlc_p), - tbs_sizeP, status_resp.buffer_occupancy_in_bytes); if ((tx_statusP.tx_status == MAC_TX_STATUS_SUCCESSFUL) && (tx_statusP.no_pdu)) { @@ -441,15 +439,6 @@ rlc_um_mac_status_indication (const protocol_ctxt_t *const ctxt_pP, void *rlc_pP return status_resp; } -//----------------------------------------------------------------------------- -void -rlc_um_set_nb_bytes_requested_by_mac ( - void *rlc_pP, - const tb_size_t tb_sizeP -) { - ((rlc_um_entity_t *) rlc_pP)->nb_bytes_requested_by_mac = tb_sizeP; -} - //----------------------------------------------------------------------------- struct mac_data_req rlc_um_mac_data_request (const protocol_ctxt_t *const ctxt_pP, void *rlc_pP,const eNB_flag_t enb_flagP) { diff --git a/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.h b/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.h index 8000196b32..be06551dde 100644 --- a/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.h +++ b/openair2/LAYER2/RLC/UM_v9.3.0/rlc_um.h @@ -160,27 +160,15 @@ rlc_um_get_pdus (const protocol_ctxt_t* const ctxt_pP, void *argP); */ void rlc_um_rx (const protocol_ctxt_t* const ctxt_pP, void *argP, struct mac_data_ind data_indP); -/*! \fn struct mac_status_resp rlc_um_mac_status_indication (const protocol_ctxt_t* const ctxt_pP, rlc_um_entity_t * const rlc_pP, uint16_t tbs_sizeP, struct mac_status_ind tx_statusP) +/*! \fn struct mac_status_resp rlc_um_mac_status_indication (const protocol_ctxt_t* const ctxt_pP, rlc_um_entity_t * const rlc_pP, struct mac_status_ind tx_statusP) * \brief Request the maximum number of bytes that can be served by RLC instance to MAC and fix the amount of bytes requested by MAC for next RLC transmission. * \param[in] ctxt_pP Running context. * \param[in] rlc_pP RLC UM protocol instance pointer. -* \param[in] tbs_sizeP Number of bytes requested by MAC for next transmission. * \param[in] tx_statusP Transmission status given by MAC on previous MAC transmission of the PDU. * \return The maximum number of bytes that can be served by RLC instance to MAC. */ struct mac_status_resp -rlc_um_mac_status_indication (const protocol_ctxt_t* const ctxt_pP, void *rlc_pP, uint16_t tbs_sizeP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP); - -/*! \fn void rlc_um_set_nb_bytes_requested_by_mac (rlc_um_entity_t * const rlc_pP, const tb_size_t tb_sizeP) -* \brief Set available TBS size for MAC Tx. -* \param[in] rlc_pP RLC UM protocol instance pointer. -* \param[in] tb_sizeP remaining TBS in bytes. -*/ -void -rlc_um_set_nb_bytes_requested_by_mac ( - void * rlc_pP, - const tb_size_t tb_sizeP -); +rlc_um_mac_status_indication (const protocol_ctxt_t* const ctxt_pP, void *rlc_pP, struct mac_status_ind tx_statusP,const eNB_flag_t enb_flagP); /*! \fn struct mac_data_req rlc_um_mac_data_request (const protocol_ctxt_t* const ctxt_pP, rlc_um_entity_t * const rlc_pP,const eNB_flag_t enb_flagP) * \brief Gives PDUs to lower layer MAC. diff --git a/openair2/LAYER2/RLC/rlc.h b/openair2/LAYER2/RLC/rlc.h index dfdf527123..27ca18ed7e 100644 --- a/openair2/LAYER2/RLC/rlc.h +++ b/openair2/LAYER2/RLC/rlc.h @@ -137,7 +137,7 @@ void (*rlc_rrc_data_ind)( const protocol_ctxt_t *const ctxtP, const rb_id_t rb_idP, const sdu_size_t sdu_sizeP, - const uint8_t *const sduP); + const uint8_t *const sduP) __attribute__ ((aligned(32))); void (*rlc_rrc_data_conf)( const protocol_ctxt_t *const ctxtP, @@ -250,7 +250,7 @@ logical_chan_id_t rlc_mbms_rbid2lcid_eNB[MAX_eNB][NB_RB_MBMS_MAX]; (((hash_key_t)(sESSION_ID)) << 37) | \ (((hash_key_t)(0x0000000000000001)) << 63)) -hash_table_t *rlc_coll_p; +hash_table_t *rlc_coll_p __attribute__ ((aligned(32))); /*! \fn tbs_size_t mac_rlc_serialize_tb (char* bufferP, list_t transport_blocksP) * \brief Serialize a list of transport blocks coming from RLC in order to be processed by MAC. @@ -391,7 +391,7 @@ void rrc_rlc_register_rrc (rrc_data_ind_cb_t rrc_data_indP, rrc_data_conf_cb_t r * \param [in] eNB_flagP Flag to indicate eNB (1) or UE (0) * \param [in] MBMS_flagP Flag to indicate whether this is the MBMS service (1) or not (0) * \param [in] rb_idP Radio bearer identifier. -* \param [in] tb_sizeP Available Tx TBS in bytes. For UE only. +* \param [in] tb_sizeP Requested Tx TBS in bytes. * \param [in,out] bufferP Memory area to fill with the bytes requested by MAC. * \return A status about the processing, OK or error code. */ @@ -416,7 +416,7 @@ tbs_size_t mac_rlc_data_req (const module_id_t, const rnti_t, con void mac_rlc_data_ind (const module_id_t, const rnti_t, const eNB_index_t,const frame_t, const eNB_flag_t, const MBMS_flag_t, logical_chan_id_t, char *, tb_size_t, num_tb_t, crc_t * ); -/*! \fn mac_rlc_status_resp_t mac_rlc_status_ind (const module_id_t mod_idP, const rnti_t rntiP, const frame_t frameP, const sub_frame_t subframeP, const eNB_flag_t eNB_flagP, const MBMS_flag_t MBMS_flagP, logical_chan_id_t rb_idP, tb_size_t tb_sizeP) +/*! \fn mac_rlc_status_resp_t mac_rlc_status_ind (const module_id_t mod_idP, const rnti_t rntiP, const frame_t frameP, const sub_frame_t subframeP, const eNB_flag_t eNB_flagP, const MBMS_flag_t MBMS_flagP, logical_chan_id_t rb_idP) * \brief Interface with MAC layer, request and set the number of bytes scheduled for transmission by the RLC instance corresponding to the radio bearer identifier. * \param[in] mod_idP Virtualized module identifier. * \param[in] rntiP UE identifier. @@ -425,10 +425,9 @@ void mac_rlc_data_ind (const module_id_t, const rnti_t, con * \param[in] eNB_flagP Flag to indicate eNB operation (1 true, 0 false) * \param[in] MBMS_flagP Flag to indicate whether this is the MBMS service (1) or not (0) * \param[in] rb_idP Radio bearer identifier. -* \param[in] tb_sizeP Size of a transport block set in bytes. * \return The maximum number of bytes that the RLC instance can send in the next transmission sequence. */ -mac_rlc_status_resp_t mac_rlc_status_ind (const module_id_t, const rnti_t, const eNB_index_t, const frame_t, const sub_frame_t, const eNB_flag_t, const MBMS_flag_t, logical_chan_id_t, tb_size_t +mac_rlc_status_resp_t mac_rlc_status_ind (const module_id_t, const rnti_t, const eNB_index_t, const frame_t, const sub_frame_t, const eNB_flag_t, const MBMS_flag_t, logical_chan_id_t ,const uint32_t sourceL2Id ,const uint32_t destinationL2Id ); diff --git a/openair2/LAYER2/RLC/rlc_mac.c b/openair2/LAYER2/RLC/rlc_mac.c index 9cf6cb739a..89cbe4c406 100644 --- a/openair2/LAYER2/RLC/rlc_mac.c +++ b/openair2/LAYER2/RLC/rlc_mac.c @@ -191,20 +191,19 @@ tbs_size_t mac_rlc_data_req( case RLC_MODE_AM: rlc_am_mui.rrc_mui_num = 0; - if (!enb_flagP) rlc_am_set_nb_bytes_requested_by_mac(&rlc_union_p->rlc.am,tb_sizeP); - + ((rlc_am_entity_t *) &rlc_union_p->rlc.am)->nb_bytes_requested_by_mac = tb_sizeP; data_request = rlc_am_mac_data_request(&ctxt, &rlc_union_p->rlc.am,enb_flagP); ret_tb_size =mac_rlc_serialize_tb(buffer_pP, data_request.data); break; case RLC_MODE_UM: - if (!enb_flagP) rlc_um_set_nb_bytes_requested_by_mac(&rlc_union_p->rlc.um,tb_sizeP); - + ((rlc_um_entity_t *) &rlc_union_p->rlc.um)->nb_bytes_requested_by_mac = tb_sizeP; data_request = rlc_um_mac_data_request(&ctxt, &rlc_union_p->rlc.um,enb_flagP); ret_tb_size = mac_rlc_serialize_tb(buffer_pP, data_request.data); break; case RLC_MODE_TM: + ((rlc_tm_entity_t *) &rlc_union_p->rlc.tm)->rlc_pdu_size = tb_sizeP; data_request = rlc_tm_mac_data_request(&ctxt, &rlc_union_p->rlc.tm); ret_tb_size = mac_rlc_serialize_tb(buffer_pP, data_request.data); break; @@ -317,7 +316,6 @@ mac_rlc_status_resp_t mac_rlc_status_ind( const eNB_flag_t enb_flagP, const MBMS_flag_t MBMS_flagP, const logical_chan_id_t channel_idP, - const tb_size_t tb_sizeP, const uint32_t sourceL2Id, const uint32_t destinationL2Id ) { @@ -370,7 +368,7 @@ mac_rlc_status_resp_t mac_rlc_status_ind( break; case RLC_MODE_AM: - status_resp = rlc_am_mac_status_indication(&ctxt, &rlc_union_p->rlc.am, tb_sizeP, tx_status,enb_flagP); + status_resp = rlc_am_mac_status_indication(&ctxt, &rlc_union_p->rlc.am, tx_status,enb_flagP); mac_rlc_status_resp.bytes_in_buffer = status_resp.buffer_occupancy_in_bytes; mac_rlc_status_resp.head_sdu_creation_time = status_resp.head_sdu_creation_time; mac_rlc_status_resp.head_sdu_remaining_size_to_send = status_resp.head_sdu_remaining_size_to_send; @@ -379,7 +377,7 @@ mac_rlc_status_resp_t mac_rlc_status_ind( break; case RLC_MODE_UM: - status_resp = rlc_um_mac_status_indication(&ctxt, &rlc_union_p->rlc.um, tb_sizeP, tx_status, enb_flagP); + status_resp = rlc_um_mac_status_indication(&ctxt, &rlc_union_p->rlc.um, tx_status, enb_flagP); mac_rlc_status_resp.bytes_in_buffer = status_resp.buffer_occupancy_in_bytes; mac_rlc_status_resp.pdus_in_buffer = status_resp.buffer_occupancy_in_pdus; mac_rlc_status_resp.head_sdu_creation_time = status_resp.head_sdu_creation_time; @@ -389,7 +387,7 @@ mac_rlc_status_resp_t mac_rlc_status_ind( break; case RLC_MODE_TM: - status_resp = rlc_tm_mac_status_indication(&ctxt, &rlc_union_p->rlc.tm, tb_sizeP, tx_status); + status_resp = rlc_tm_mac_status_indication(&ctxt, &rlc_union_p->rlc.tm, tx_status); mac_rlc_status_resp.bytes_in_buffer = status_resp.buffer_occupancy_in_bytes; mac_rlc_status_resp.pdus_in_buffer = status_resp.buffer_occupancy_in_pdus; // return mac_rlc_status_resp; diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c index 88bde65107..ff0d446e3f 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c @@ -107,7 +107,6 @@ tbs_size_t mac_rlc_data_req( int ret; nr_rlc_ue_t *ue; nr_rlc_entity_t *rb; - int is_enb; int maxsize; nr_rlc_manager_lock(nr_rlc_ue_manager); @@ -121,12 +120,7 @@ tbs_size_t mac_rlc_data_req( if (rb != NULL) { rb->set_time(rb, nr_rlc_current_time); - /* UE does not seem to use saved_status_ind_tb_size */ - is_enb = nr_rlc_manager_get_enb_flag(nr_rlc_ue_manager); - if (is_enb) - maxsize = ue->saved_status_ind_tb_size[channel_idP - 1]; - else - maxsize = tb_sizeP; + maxsize = tb_sizeP; ret = rb->generate_pdu(rb, buffer_pP, maxsize); } else { LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB\n", __FILE__, __LINE__, __FUNCTION__); @@ -152,7 +146,6 @@ mac_rlc_status_resp_t mac_rlc_status_ind( const eNB_flag_t enb_flagP, const MBMS_flag_t MBMS_flagP, const logical_chan_id_t channel_idP, - const tb_size_t tb_sizeP, const uint32_t sourceL2Id, const uint32_t destinationL2Id ) @@ -189,7 +182,6 @@ mac_rlc_status_resp_t mac_rlc_status_ind( ret.bytes_in_buffer = buf_stat.status_size + buf_stat.retx_size + buf_stat.tx_size; - ue->saved_status_ind_tb_size[channel_idP - 1] = tb_sizeP; } else { ret.bytes_in_buffer = 0; } diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h index 97da28cdce..464cf3d083 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h +++ b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h @@ -28,10 +28,6 @@ typedef void nr_rlc_ue_manager_t; typedef struct nr_rlc_ue_t { int rnti; - /* due to openair calling status_ind/data_req, we need to keep this. - * To be considered 'hackish'. - */ - int saved_status_ind_tb_size[2+5]; nr_rlc_entity_t *srb[2]; nr_rlc_entity_t *drb[5]; } nr_rlc_ue_t; diff --git a/openair2/LAYER2/openair2_proc.c b/openair2/LAYER2/openair2_proc.c index 32c4d9788c..bbdc55e036 100644 --- a/openair2/LAYER2/openair2_proc.c +++ b/openair2/LAYER2/openair2_proc.c @@ -91,12 +91,12 @@ int dump_eNB_l2_stats(char *buffer, int length) { number_of_cards=NB_eNB_INST; #endif eNB_MAC_INST *eNB; - UE_list_t *UE_list; + UE_info_t *UE_info; for (eNB_id=0; eNB_idUE_list; + UE_info = &eNB->UE_info; for (CC_id=0 ; CC_id < MAX_NUM_CCs; CC_id++) { eNB->eNB_stats[CC_id].dlsch_bitrate= 0; @@ -141,76 +141,76 @@ int dump_eNB_l2_stats(char *buffer, int length) { len += sprintf(&buffer[len],"\n"); - for (UE_id=UE_list->head; UE_id>=0; UE_id=UE_list->next[UE_id]) { - for (i=0; inumactiveCCs[UE_id]; i++) { - CC_id=UE_list->ordered_CCids[i][UE_id]; - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_bitrate=((UE_list->eNB_UE_stats[CC_id][UE_id].TBS*8)/((eNB->frame + 1)*10)); - UE_list->eNB_UE_stats[CC_id][UE_id].total_dlsch_bitrate= ((UE_list->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes*8)/((eNB->frame + 1)*10)); - UE_list->eNB_UE_stats[CC_id][UE_id].total_overhead_bytes+= UE_list->eNB_UE_stats[CC_id][UE_id].overhead_bytes; - UE_list->eNB_UE_stats[CC_id][UE_id].avg_overhead_bytes=((UE_list->eNB_UE_stats[CC_id][UE_id].total_overhead_bytes*8)/((eNB->frame + 1)*10)); - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_bitrate=((UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS*8)/((eNB->frame + 1)*10)); - UE_list->eNB_UE_stats[CC_id][UE_id].total_ulsch_bitrate= ((UE_list->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes_rx*8)/((eNB->frame + 1)*10)); + for (UE_id=UE_info->list.head; UE_id>=0; UE_id=UE_info->list.next[UE_id]) { + for (i=0; inumactiveCCs[UE_id]; i++) { + CC_id=UE_info->ordered_CCids[i][UE_id]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_bitrate=((UE_info->eNB_UE_stats[CC_id][UE_id].TBS*8)/((eNB->frame + 1)*10)); + UE_info->eNB_UE_stats[CC_id][UE_id].total_dlsch_bitrate= ((UE_info->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes*8)/((eNB->frame + 1)*10)); + UE_info->eNB_UE_stats[CC_id][UE_id].total_overhead_bytes+= UE_info->eNB_UE_stats[CC_id][UE_id].overhead_bytes; + UE_info->eNB_UE_stats[CC_id][UE_id].avg_overhead_bytes=((UE_info->eNB_UE_stats[CC_id][UE_id].total_overhead_bytes*8)/((eNB->frame + 1)*10)); + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_bitrate=((UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS*8)/((eNB->frame + 1)*10)); + UE_info->eNB_UE_stats[CC_id][UE_id].total_ulsch_bitrate= ((UE_info->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes_rx*8)/((eNB->frame + 1)*10)); len += sprintf(&buffer[len],"[MAC] UE %d (DLSCH),status %s, RNTI %x : CQI %d, MCS1 %d, MCS2 %d, RB (tx %d, retx %d, total %d), ncce (tx %d, retx %d) \n", UE_id, - map_int_to_str(rrc_status_names, UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status), - UE_list->eNB_UE_stats[CC_id][UE_id].crnti, - UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id], - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1, - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2, - UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used, - UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used_retx, - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used, - UE_list->eNB_UE_stats[CC_id][UE_id].ncce_used, - UE_list->eNB_UE_stats[CC_id][UE_id].ncce_used_retx + map_int_to_str(rrc_status_names, UE_info->eNB_UE_stats[CC_id][UE_id].rrc_status), + UE_info->eNB_UE_stats[CC_id][UE_id].crnti, + UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id], + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1, + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2, + UE_info->eNB_UE_stats[CC_id][UE_id].rbs_used, + UE_info->eNB_UE_stats[CC_id][UE_id].rbs_used_retx, + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used, + UE_info->eNB_UE_stats[CC_id][UE_id].ncce_used, + UE_info->eNB_UE_stats[CC_id][UE_id].ncce_used_retx ); len += sprintf(&buffer[len], "[MAC] DLSCH bitrate (TTI %d, avg %d), Transmitted bytes " "(TTI %d, total %"PRIu64"), Total Transmitted PDU %d, Overhead " "(TTI %"PRIu64", total %"PRIu64", avg %"PRIu64")\n", - UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_bitrate, - UE_list->eNB_UE_stats[CC_id][UE_id].total_dlsch_bitrate, - UE_list->eNB_UE_stats[CC_id][UE_id].TBS, - UE_list->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes, - UE_list->eNB_UE_stats[CC_id][UE_id].total_num_pdus, - UE_list->eNB_UE_stats[CC_id][UE_id].overhead_bytes, - UE_list->eNB_UE_stats[CC_id][UE_id].total_overhead_bytes, - UE_list->eNB_UE_stats[CC_id][UE_id].avg_overhead_bytes + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_bitrate, + UE_info->eNB_UE_stats[CC_id][UE_id].total_dlsch_bitrate, + UE_info->eNB_UE_stats[CC_id][UE_id].TBS, + UE_info->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes, + UE_info->eNB_UE_stats[CC_id][UE_id].total_num_pdus, + UE_info->eNB_UE_stats[CC_id][UE_id].overhead_bytes, + UE_info->eNB_UE_stats[CC_id][UE_id].total_overhead_bytes, + UE_info->eNB_UE_stats[CC_id][UE_id].avg_overhead_bytes ); len += sprintf(&buffer[len],"[MAC] UE %d (ULSCH), Status %s, Failute timer %d, RNTI %x : snr (%d, target %d), MCS (pre %d, post %d), RB (rx %d, retx %d, total %d), Current TBS %d \n", UE_id, - map_int_to_str(rrc_status_names, UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status), - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer, - UE_list->eNB_UE_stats[CC_id][UE_id].crnti, - UE_list->eNB_UE_stats[CC_id][UE_id].snr, - UE_list->eNB_UE_stats[CC_id][UE_id].target_snr, - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1, - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2, - UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used_rx, - UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used_retx_rx, - UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx, - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS + map_int_to_str(rrc_status_names, UE_info->eNB_UE_stats[CC_id][UE_id].rrc_status), + UE_info->UE_sched_ctrl[UE_id].ul_failure_timer, + UE_info->eNB_UE_stats[CC_id][UE_id].crnti, + UE_info->eNB_UE_stats[CC_id][UE_id].snr, + UE_info->eNB_UE_stats[CC_id][UE_id].target_snr, + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1, + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2, + UE_info->eNB_UE_stats[CC_id][UE_id].rbs_used_rx, + UE_info->eNB_UE_stats[CC_id][UE_id].rbs_used_retx_rx, + UE_info->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx, + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_TBS ); len += sprintf(&buffer[len], "[MAC] ULSCH bitrate (TTI %d, avg %d), received bytes (total %"PRIu64")," "Total received PDU %d, Total errors %d\n", - UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_bitrate, - UE_list->eNB_UE_stats[CC_id][UE_id].total_ulsch_bitrate, - UE_list->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes_rx, - UE_list->eNB_UE_stats[CC_id][UE_id].total_num_pdus_rx, - UE_list->eNB_UE_stats[CC_id][UE_id].num_errors_rx); - len+= sprintf(&buffer[len],"[MAC] Received PHR PH = %d (db)\n", UE_list->UE_template[CC_id][UE_id].phr_info); + UE_info->eNB_UE_stats[CC_id][UE_id].ulsch_bitrate, + UE_info->eNB_UE_stats[CC_id][UE_id].total_ulsch_bitrate, + UE_info->eNB_UE_stats[CC_id][UE_id].total_pdu_bytes_rx, + UE_info->eNB_UE_stats[CC_id][UE_id].total_num_pdus_rx, + UE_info->eNB_UE_stats[CC_id][UE_id].num_errors_rx); + len+= sprintf(&buffer[len],"[MAC] Received PHR PH = %d (db)\n", UE_info->UE_template[CC_id][UE_id].phr_info); len+= sprintf(&buffer[len],"[MAC] Estimated size LCGID[0][1][2][3] = %u %u %u %u\n", - UE_list->UE_template[CC_id][UE_id].ul_buffer_info[LCGID0], - UE_list->UE_template[CC_id][UE_id].ul_buffer_info[LCGID1], - UE_list->UE_template[CC_id][UE_id].ul_buffer_info[LCGID2], - UE_list->UE_template[CC_id][UE_id].ul_buffer_info[LCGID3] + UE_info->UE_template[CC_id][UE_id].ul_buffer_info[LCGID0], + UE_info->UE_template[CC_id][UE_id].ul_buffer_info[LCGID1], + UE_info->UE_template[CC_id][UE_id].ul_buffer_info[LCGID2], + UE_info->UE_template[CC_id][UE_id].ul_buffer_info[LCGID3] ); } PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, eNB_id, ENB_FLAG_YES, - UE_list->eNB_UE_stats[0][UE_id].crnti,//UE_PCCID(eNB_id,UE_id)][UE_id].crnti, + UE_info->eNB_UE_stats[0][UE_id].crnti,//UE_PCCID(eNB_id,UE_id)][UE_id].crnti, eNB->frame, eNB->subframe, eNB_id); @@ -509,7 +509,7 @@ int openair2_stats_read(char *buffer, char **my_buffer, off_t off, int length) { for(i=1; i<=NB_CNX_CH; i++) { if (CH_mac_inst[Mod_id].Dcch_lchan[i].Active==1) { len+=sprintf(&buffer[len],"\nMR index %u: DL SINR (feedback) %d dB, CQI: %s\n\n", - i,//CH_rrc_inst[Mod_id].Info.UE_list[i].L2_id[0], + i,//CH_rrc_inst[Mod_id].Info.UE_info[i].L2_id[0], CH_mac_inst[Mod_id].Def_meas[i].Wideband_sinr, print_cqi(CH_mac_inst[Mod_id].Def_meas[i].cqi)); len+=sprintf(&buffer[len], diff --git a/openair2/M2AP/m2ap_MCE_handler.h b/openair2/M2AP/m2ap_MCE_handler.h index e9faae8f5d..68cab5c8ac 100644 --- a/openair2/M2AP/m2ap_MCE_handler.h +++ b/openair2/M2AP/m2ap_MCE_handler.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M2AP_MCE_HANDLERS_H_ -#define M2AP_MCE_HANDLERS_H_ +#ifndef __M2AP_MCE_HANDLERS__H__ +#define __M2AP_MCE_HANDLERS__H__ #include "m2ap_MCE_defs.h" @@ -40,4 +40,4 @@ int m2ap_MCE_handle_message(instance_t instance, uint32_t assoc_id, int32_t stre //const uint8_t * const data, const uint32_t data_length); -#endif /* M2AP_MCE_HANDLERS_H_ */ +#endif /* __M2AP_MCE_HANDLERS__H__ */ diff --git a/openair2/M2AP/m2ap_MCE_management_procedures.h b/openair2/M2AP/m2ap_MCE_management_procedures.h index 9e13e723c9..4e8997dbc5 100644 --- a/openair2/M2AP/m2ap_MCE_management_procedures.h +++ b/openair2/M2AP/m2ap_MCE_management_procedures.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M2AP_MCE_MANAGEMENT_PROCEDURES_H_ -#define M2AP_MCE_MANAGEMENT_PROCEDURES_H +#ifndef __M2AP_MCE_MANAGEMENT_PROCEDURES__H__ +#define __M2AP_MCE_MANAGEMENT_PROCEDURES__H__ void m2ap_MCE_prepare_internal_data(void); @@ -51,4 +51,4 @@ struct m2ap_MCE_data_s *m2ap_get_MCE(m2ap_MCE_instance_t *instance_p, int32_t assoc_id, uint16_t cnx_id); -#endif /* M2AP_MCE_MANAGEMENT_PROCEDURES_H_ */ +#endif /* __M2AP_MCE_MANAGEMENT_PROCEDURES__H__ */ diff --git a/openair2/M2AP/m2ap_eNB_generate_messages.h b/openair2/M2AP/m2ap_eNB_generate_messages.h index 49247405f7..793f7f18cf 100644 --- a/openair2/M2AP/m2ap_eNB_generate_messages.h +++ b/openair2/M2AP/m2ap_eNB_generate_messages.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M2AP_ENB_GENERATE_MESSAGES_H_ -#define M2AP_ENB_GENERATE_MESSAGES_H_ +#ifndef __M2AP_ENB_GENERATE_MESSAGES__H__ +#define __M2AP_ENB_GENERATE_MESSAGES__H__ #include "m2ap_eNB_defs.h" #include "m2ap_common.h" @@ -60,4 +60,4 @@ int m2ap_eNB_set_cause (M2AP_Cause_t * cause_p, // int m2_ue_id, // m2ap_handover_cancel_cause_t cause); -#endif /* M2AP_ENB_GENERATE_MESSAGES_H_ */ +#endif /* __M2AP_ENB_GENERATE_MESSAGES__H__ */ diff --git a/openair2/M2AP/m2ap_eNB_management_procedures.h b/openair2/M2AP/m2ap_eNB_management_procedures.h index fbc49d0169..2b1dc4a44b 100644 --- a/openair2/M2AP/m2ap_eNB_management_procedures.h +++ b/openair2/M2AP/m2ap_eNB_management_procedures.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M2AP_ENB_MANAGEMENT_PROCEDURES_H_ -#define M2AP_ENB_MANAGEMENT_PROCEDURES_H +#ifndef __M2AP_ENB_MANAGEMENT_PROCEDURES__H__ +#define __M2AP_ENB_MANAGEMENT_PROCEDURES__H__ void m2ap_eNB_prepare_internal_data(void); @@ -51,4 +51,4 @@ struct m2ap_eNB_data_s *m2ap_get_eNB(m2ap_eNB_instance_t *instance_p, int32_t assoc_id, uint16_t cnx_id); -#endif /* M2AP_ENB_MANAGEMENT_PROCEDURES_H_ */ +#endif /* __M2AP_ENB_MANAGEMENT_PROCEDURES__H__ */ diff --git a/openair2/MCE_APP/mce_app.c b/openair2/MCE_APP/mce_app.c index 32dfa5cc42..6f7454c321 100644 --- a/openair2/MCE_APP/mce_app.c +++ b/openair2/MCE_APP/mce_app.c @@ -343,7 +343,9 @@ void *MCE_app_task(void *args_p) { /* Try to register each MCE */ // This assumes that node_type of all RRC instances is the same - if (EPC_MODE_ENABLED) { + if ( EPC_MODE_ENABLED && RC.rrc == NULL ) + LOG_E(RRC, "inconsistent global variables\n"); + if (EPC_MODE_ENABLED && RC.rrc ) { register_mce_pending = MCE_app_register(RC.rrc[0]->node_type, mce_id_start, mce_id_end); } diff --git a/openair2/NETWORK_DRIVER/LITE/proto_extern.h b/openair2/NETWORK_DRIVER/LITE/proto_extern.h index f07083921f..d4289ca1f2 100644 --- a/openair2/NETWORK_DRIVER/LITE/proto_extern.h +++ b/openair2/NETWORK_DRIVER/LITE/proto_extern.h @@ -30,8 +30,8 @@ ***************************************************************************/ -#ifndef _NAS_PROTO_H -#define _NAS_PROTO_H +#ifndef __NETWORK_DRIVER_LITE_PROTO_EXTERN__H__ +#define __NETWORK_DRIVER_LITE_PROTO_EXTERN__H__ #include #include diff --git a/openair2/NETWORK_DRIVER/MESH/proto_extern.h b/openair2/NETWORK_DRIVER/MESH/proto_extern.h index 2eae034257..ac92b2f8bd 100644 --- a/openair2/NETWORK_DRIVER/MESH/proto_extern.h +++ b/openair2/NETWORK_DRIVER/MESH/proto_extern.h @@ -29,8 +29,8 @@ ***************************************************************************/ -#ifndef _NAS_PROTO_H -#define _NAS_PROTO_H +#ifndef __NETWORK_DRIVER_MESH_PROTO_EXTERN__H__ +#define __NETWORK_DRIVER_MESH_PROTO_EXTERN__H__ #include #include diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 91c75ac67f..4dacef3dbb 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -54,34 +54,32 @@ extern uint16_t sf_ahead; extern uint16_t sl_ahead; void handle_nr_rach(NR_UL_IND_t *UL_info) { - if (UL_info->rach_ind.rach_indication_body.number_of_preambles>0) { - AssertFatal(UL_info->rach_ind.rach_indication_body.number_of_preambles==1,"More than 1 preamble not supported\n"); - UL_info->rach_ind.rach_indication_body.number_of_preambles=0; - LOG_D(MAC,"UL_info[Frame %d, Slot %d] Calling initiate_ra_proc RACH:SFN/SF:%d\n",UL_info->frame,UL_info->slot, NFAPI_SFNSF2DEC(UL_info->rach_ind.sfn_sf)); - /* - initiate_ra_proc(UL_info->module_id, + if (UL_info->rach_ind.number_of_pdus>0) { + AssertFatal(UL_info->rach_ind.number_of_pdus==1,"More than 1 RACH pdu not supported\n"); + UL_info->rach_ind.number_of_pdus=0; + LOG_D(MAC,"UL_info[Frame %d, Slot %d] Calling initiate_ra_proc RACH:SFN/SLOT:%d/%d\n",UL_info->frame,UL_info->slot, UL_info->rach_ind.sfn,UL_info->rach_ind.slot); - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rach_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti -#if (NR_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) || (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) -//#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - ,0 -#endif + if (UL_info->rach_ind.pdu_list[0].num_preamble>0) + AssertFatal(UL_info->rach_ind.pdu_list[0].num_preamble==1, + "More than 1 preamble not supported\n"); + + /*nr_initiate_ra_proc(UL_info->module_id, + UL_info->CC_id, + UL_info->rach_ind.sfn, + UL_info->rach_ind.slot, + UL_info->rach_ind.pdu_list[0].preamble_list[0].preamble_index, + UL_info->rach_ind.pdu_list[0].freq_index, + UL_info->rach_ind.pdu_list[0].symbol_index, + UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance);*/ - ); - */ } - } + void handle_nr_sr(NR_UL_IND_t *UL_info) { - if (nfapi_mode == 1) // PNF + /* if (nfapi_mode == 1) // PNF { if (UL_info->sr_ind.sr_indication_body.number_of_srs>0) { @@ -91,20 +89,20 @@ void handle_nr_sr(NR_UL_IND_t *UL_info) { else { - /* + for (int i=0;isr_ind.sr_indication_body.number_of_srs;i++) SR_indication(UL_info->module_id, UL_info->CC_id, UL_info->frame, UL_info->slot, UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi);*/ + UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi); } - UL_info->sr_ind.sr_indication_body.number_of_srs=0; + UL_info->sr_ind.sr_indication_body.number_of_srs=0;*/ } void handle_nr_cqi(NR_UL_IND_t *UL_info) { @@ -119,103 +117,99 @@ void handle_nr_cqi(NR_UL_IND_t *UL_info) { &UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9, UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu, &UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information); - */ - UL_info->cqi_ind.number_of_cqis=0; + + UL_info->cqi_ind.number_of_cqis=0;*/ } void handle_nr_harq(NR_UL_IND_t *UL_info) { - if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF + /* if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF //LOG_D(PHY, "UL_info->harq_ind.harq_indication_body.number_of_harqs:%d Send to VNF\n", UL_info->harq_ind.harq_indication_body.number_of_harqs); - /* int retval = oai_nfapi_harq_indication(&UL_info->harq_ind); + int retval = oai_nfapi_harq_indication(&UL_info->harq_ind); if (retval!=0) { LOG_E(PHY, "Failed to encode NFAPI HARQ_IND retval:%d\n", retval); } - */ + UL_info->harq_ind.harq_indication_body.number_of_harqs = 0; } else { - /* + for (int i=0;iharq_ind.harq_indication_body.number_of_harqs;i++) harq_indication(UL_info->module_id, UL_info->CC_id, NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf), NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf), &UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]); - */ + UL_info->harq_ind.harq_indication_body.number_of_harqs=0; - } + }*/ } void handle_nr_ulsch(NR_UL_IND_t *UL_info) { if(nfapi_mode == 1) { - if (UL_info->crc_ind.crc_indication_body.number_of_crcs>0) { + if (UL_info->crc_ind.number_crcs>0) { //LOG_D(PHY,"UL_info->crc_ind.crc_indication_body.number_of_crcs:%d CRC_IND:SFN/SF:%d\n", UL_info->crc_ind.crc_indication_body.number_of_crcs, NFAPI_SFNSF2DEC(UL_info->crc_ind.sfn_sf)); // oai_nfapi_crc_indication(&UL_info->crc_ind); - UL_info->crc_ind.crc_indication_body.number_of_crcs = 0; + UL_info->crc_ind.number_crcs = 0; } - if (UL_info->rx_ind.rx_indication_body.number_of_pdus>0) { + if (UL_info->rx_ind.number_of_pdus>0) { //LOG_D(PHY,"UL_info->rx_ind.number_of_pdus:%d RX_IND:SFN/SF:%d\n", UL_info->rx_ind.rx_indication_body.number_of_pdus, NFAPI_SFNSF2DEC(UL_info->rx_ind.sfn_sf)); // oai_nfapi_rx_ind(&UL_info->rx_ind); - UL_info->rx_ind.rx_indication_body.number_of_pdus = 0; + UL_info->rx_ind.number_of_pdus = 0; } } else { - if (UL_info->rx_ind.rx_indication_body.number_of_pdus>0 && UL_info->crc_ind.crc_indication_body.number_of_crcs>0) { - for (int i=0; irx_ind.rx_indication_body.number_of_pdus; i++) { - for (int j=0; jcrc_ind.crc_indication_body.number_of_crcs; j++) { + if (UL_info->rx_ind.number_of_pdus>0 && UL_info->crc_ind.number_crcs>0) { + for (int i=0; irx_ind.number_of_pdus; i++) { + for (int j=0; jcrc_ind.number_crcs; j++) { // find crc_indication j corresponding rx_indication i LOG_D(PHY,"UL_info->crc_ind.crc_indication_body.crc_pdu_list[%d].rx_ue_information.rnti:%04x UL_info->rx_ind.rx_indication_body.rx_pdu_list[%d].rx_ue_information.rnti:%04x\n", j, - UL_info->crc_ind.crc_indication_body.crc_pdu_list[j].rx_ue_information.rnti, i, UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti); + UL_info->crc_ind.crc_list[j].rnti, i, UL_info->rx_ind.pdu_list[i].rnti); - if (UL_info->crc_ind.crc_indication_body.crc_pdu_list[j].rx_ue_information.rnti == - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti) { - LOG_D(PHY, "UL_info->crc_ind.crc_indication_body.crc_pdu_list[%d].crc_indication_rel8.crc_flag:%d\n", j, UL_info->crc_ind.crc_indication_body.crc_pdu_list[j].crc_indication_rel8.crc_flag); + if (UL_info->crc_ind.crc_list[j].rnti == + UL_info->rx_ind.pdu_list[i].rnti) { + LOG_D(PHY, "UL_info->crc_ind.crc_indication_body.crc_pdu_list[%d].crc_indication_rel8.crc_flag:%d\n", j, UL_info->crc_ind.crc_list[j].tb_crc_status); - if (UL_info->crc_ind.crc_indication_body.crc_pdu_list[j].crc_indication_rel8.crc_flag == 1) { // CRC error indication + if (UL_info->crc_ind.crc_list[j].tb_crc_status == 1) { // CRC error indication LOG_D(MAC,"Frame %d, Slot %d Calling rx_sdu (CRC error) \n",UL_info->frame,UL_info->slot); nr_rx_sdu(UL_info->module_id, UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rx_ind.sfn_sf), //UL_info->frame, - NFAPI_SFNSF2SF(UL_info->rx_ind.sfn_sf), //UL_info->slot, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti, + UL_info->rx_ind.sfn, //UL_info->frame, + UL_info->rx_ind.slot, //UL_info->slot, + UL_info->rx_ind.pdu_list[i].rnti, (uint8_t *)NULL, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.ul_cqi); + UL_info->rx_ind.pdu_list[i].pdu_length, + UL_info->rx_ind.pdu_list[i].timing_advance, + UL_info->rx_ind.pdu_list[i].ul_cqi); } else { LOG_D(MAC,"Frame %d, Slot %d Calling rx_sdu (CRC ok) \n",UL_info->frame,UL_info->slot); nr_rx_sdu(UL_info->module_id, UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rx_ind.sfn_sf), //UL_info->frame, - NFAPI_SFNSF2SF(UL_info->rx_ind.sfn_sf), //UL_info->slot, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_ue_information.rnti, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].data, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.length, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance, - UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.ul_cqi); + UL_info->rx_ind.sfn, //UL_info->frame, + UL_info->rx_ind.slot, //UL_info->slot, + UL_info->rx_ind.pdu_list[i].rnti, + UL_info->rx_ind.pdu_list[i].pdu, + UL_info->rx_ind.pdu_list[i].pdu_length, + UL_info->rx_ind.pdu_list[i].timing_advance, + UL_info->rx_ind.pdu_list[i].ul_cqi); } - //printf("rx_indication_rel8.timing_advance %d\n", UL_info->rx_ind.rx_indication_body.rx_pdu_list[i].rx_indication_rel8.timing_advance); break; - } //if (UL_info->crc_ind.crc_pdu_list[j].rx_ue_information.rnti == - - // UL_info->rx_ind.rx_pdu_list[i].rx_ue_information.rnti) - } // for (j=0;jcrc_ind.crc_indication_body.number_of_crcs;j++) + } + } // for (j=0;jcrc_ind.number_crcs;j++) } // for (i=0;irx_ind.number_of_pdus;i++) - UL_info->crc_ind.crc_indication_body.number_of_crcs=0; - UL_info->rx_ind.rx_indication_body.number_of_pdus = 0; - } // UL_info->rx_ind.rx_indication_body.number_of_pdus>0 && UL_info->slot && UL_info->crc_ind.crc_indication_body.number_of_crcs>0 - else if (UL_info->rx_ind.rx_indication_body.number_of_pdus!=0 || UL_info->crc_ind.crc_indication_body.number_of_crcs!=0) { - LOG_E(PHY,"hoping not to have mis-match between CRC ind and RX ind - hopefully the missing message is coming shortly rx_ind:%d(SFN/SF:%05d) crc_ind:%d(SFN/SF:%05d) UL_info(SFN/SF):%04d%d\n", - UL_info->rx_ind.rx_indication_body.number_of_pdus, NFAPI_SFNSF2DEC(UL_info->rx_ind.sfn_sf), - UL_info->crc_ind.crc_indication_body.number_of_crcs, NFAPI_SFNSF2DEC(UL_info->crc_ind.sfn_sf), - UL_info->frame, UL_info->slot); + UL_info->crc_ind.number_crcs=0; + UL_info->rx_ind.number_of_pdus = 0; + } + else if (UL_info->rx_ind.number_of_pdus!=0 || UL_info->crc_ind.number_crcs!=0) { + LOG_E(PHY,"hoping not to have mis-match between CRC ind and RX ind - hopefully the missing message is coming shortly rx_ind:%d(SFN/SL:%d/%d) crc_ind:%d(SFN/SL:%d/%d) \n", + UL_info->rx_ind.number_of_pdus, UL_info->rx_ind.sfn, UL_info->rx_ind.slot, + UL_info->crc_ind.number_crcs, UL_info->rx_ind.sfn, UL_info->rx_ind.slot); } } } @@ -230,11 +224,10 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { NR_Sched_Rsp_t *sched_info = &Sched_INFO[module_id][CC_id]; NR_IF_Module_t *ifi = if_inst[module_id]; gNB_MAC_INST *mac = RC.nrmac[module_id]; - LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rx_ind:%d harqs:%d crcs:%d cqis:%d preambles:%d sr_ind:%d]\n", + LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rx_ind:%d crcs:%d]\n", UL_info->frame,UL_info->slot, module_id,CC_id, - UL_info->rx_ind.rx_indication_body.number_of_pdus, UL_info->harq_ind.harq_indication_body.number_of_harqs, UL_info->crc_ind.crc_indication_body.number_of_crcs, UL_info->cqi_ind.number_of_cqis, - UL_info->rach_ind.rach_indication_body.number_of_preambles, UL_info->sr_ind.sr_indication_body.number_of_srs); + UL_info->rx_ind.number_of_pdus, UL_info->crc_ind.number_crcs); if (nfapi_mode != 1) { if (ifi->CC_mask==0) { diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h index 14355781d0..d523d6e0f0 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h @@ -61,29 +61,20 @@ typedef struct { /// slot slot_t slot; - /// harq indication list - nfapi_harq_indication_t harq_ind; - /// crc indication list - nfapi_crc_indication_t crc_ind; - - /// SR indication list - nfapi_sr_indication_t sr_ind; - - /// CQI indication list - nfapi_cqi_indication_body_t cqi_ind; + nfapi_nr_crc_indication_t crc_ind; /// RACH indication list - nfapi_rach_indication_t rach_ind; - - /// RACH indication list for BR UEs - nfapi_rach_indication_t rach_ind_br; + nfapi_nr_rach_indication_t rach_ind; /// SRS indication list - nfapi_srs_indication_body_t srs_ind; + nfapi_nr_srs_indication_t srs_ind; /// RX indication - nfapi_rx_indication_t rx_ind; + nfapi_nr_rx_data_indication_t rx_ind; + + /// UCI indication + nfapi_nr_uci_indication_t uci_ind; } NR_UL_IND_t; diff --git a/openair2/PHY_INTERFACE/IF_Module.c b/openair2/PHY_INTERFACE/IF_Module.c index b5cda35193..d98c603d78 100644 --- a/openair2/PHY_INTERFACE/IF_Module.c +++ b/openair2/PHY_INTERFACE/IF_Module.c @@ -685,7 +685,7 @@ static void dump_dl(Sched_Rsp_t *d) { /* debug utility functions end */ /****************************************************************************/ -void UL_indication(UL_IND_t *UL_info) { +void UL_indication(UL_IND_t *UL_info, L1_rxtx_proc_t *proc) { AssertFatal(UL_info!=NULL,"UL_INFO is null\n"); #ifdef DUMP_FAPI dump_ul(UL_info); @@ -767,7 +767,7 @@ void UL_indication(UL_IND_t *UL_info) { "schedule_response is null (mod %d, cc %d)\n", module_id, CC_id); - ifi->schedule_response(sched_info); + ifi->schedule_response(sched_info, proc ); } LOG_D(PHY,"Schedule_response: SFN_SF:%d%d dl_pdus:%d\n",sched_info->frame,sched_info->subframe,sched_info->DL_req->dl_config_request_body.number_pdu); diff --git a/openair2/PHY_INTERFACE/IF_Module.h b/openair2/PHY_INTERFACE/IF_Module.h index f260222097..42a4459732 100644 --- a/openair2/PHY_INTERFACE/IF_Module.h +++ b/openair2/PHY_INTERFACE/IF_Module.h @@ -34,10 +34,12 @@ #include +#include //#include "openair1/PHY/LTE_TRANSPORT/transport_eNB.h" #include "nfapi_interface.h" #include "platform_constants.h" #include "platform_types.h" +#include #define MAX_NUM_DL_PDU 100 #define MAX_NUM_UL_PDU 100 @@ -130,16 +132,69 @@ typedef struct { } Sched_Rsp_t; typedef struct { - uint8_t Mod_id; - int CC_id; - nfapi_config_request_t *cfg; -} PHY_Config_t; + uint8_t Mod_id; + int CC_id; + nfapi_config_request_t *cfg; +}PHY_Config_t; +#include +/// Context data structure for RX/TX portion of subframe processing +typedef struct { + /// Component Carrier index + uint8_t CC_id; + /// timestamp transmitted to HW + openair0_timestamp timestamp_tx; + openair0_timestamp timestamp_rx; + /// subframe to act upon for transmission + int subframe_tx; + /// subframe to act upon for reception + int subframe_rx; + /// frame to act upon for transmission + int frame_tx; + /// frame to act upon for reception + int frame_rx; + int frame_prach; + int subframe_prach; + int frame_prach_br; + int subframe_prach_br; + /// \brief Instance count for RXn-TXnp4 processing thread. + /// \internal This variable is protected by \ref mutex_rxtx. + int instance_cnt; + /// pthread structure for RXn-TXnp4 processing thread + pthread_t pthread; + /// pthread attributes for RXn-TXnp4 processing thread + pthread_attr_t attr; + /// condition variable for tx processing thread + pthread_cond_t cond; + /// mutex for RXn-TXnp4 processing thread + pthread_mutex_t mutex; + /// scheduling parameters for RXn-TXnp4 thread + struct sched_param sched_param_rxtx; + + /// \internal This variable is protected by \ref mutex_RUs. + int instance_cnt_RUs; + /// condition variable for tx processing thread + pthread_cond_t cond_RUs; + /// mutex for RXn-TXnp4 processing thread + pthread_mutex_t mutex_RUs; + tpool_t *threadPool; + int nbEncode; + int nbDecode; + notifiedFIFO_t *respEncode; + notifiedFIFO_t *respDecode; + pthread_mutex_t mutex_emulateRF; + int instance_cnt_emulateRF; + pthread_t pthread_emulateRF; + pthread_attr_t attr_emulateRF; + pthread_cond_t cond_emulateRF; + int first_rx; +} L1_rxtx_proc_t; + +typedef struct IF_Module_s{ +//define the function pointer + void (*UL_indication)(UL_IND_t *UL_INFO, L1_rxtx_proc_t *proc); + void (*schedule_response)(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc); + void (*PHY_config_req)(PHY_Config_t* config_INFO); -typedef struct IF_Module_s { - //define the function pointer - void (*UL_indication)(UL_IND_t *UL_INFO); - void (*schedule_response)(Sched_Rsp_t *Sched_INFO); - void (*PHY_config_req)(PHY_Config_t *config_INFO); void (*PHY_config_update_sib2_req)(PHY_Config_t* config_INFO); void (*PHY_config_update_sib13_req)(PHY_Config_t* config_INFO); uint32_t CC_mask; @@ -165,7 +220,7 @@ void IF_Module_kill(int Mod_id); /*Interface for uplink, transmitting the Preamble(list), ULSCH SDU, NAK, Tick (trigger scheduler) */ -void UL_indication(UL_IND_t *UL_INFO); +void UL_indication(UL_IND_t *UL_INFO, L1_rxtx_proc_t *proc); /*Interface for Downlink, transmitting the DLSCH SDU, DCI SDU*/ void Schedule_Response(Sched_Rsp_t *Sched_INFO); diff --git a/openair2/PHY_INTERFACE/phy_stub_UE.c b/openair2/PHY_INTERFACE/phy_stub_UE.c index bf2bbf7429..41fb3ddc3a 100644 --- a/openair2/PHY_INTERFACE/phy_stub_UE.c +++ b/openair2/PHY_INTERFACE/phy_stub_UE.c @@ -708,200 +708,182 @@ int tx_req_UE_MAC(nfapi_tx_request_t *req) { return 0; } -int dl_config_req_UE_MAC(nfapi_dl_config_request_t* req, module_id_t Mod_id) { - int sfn = NFAPI_SFNSF2SFN(req->sfn_sf); - int sf = NFAPI_SFNSF2SF(req->sfn_sf); +void dl_config_req_UE_MAC_dci(int sfn, + int sf, + nfapi_dl_config_request_pdu_t *dci, + nfapi_dl_config_request_pdu_t *dlsch, + int num_ue) { + DevAssert(dci->pdu_type == NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE); + DevAssert(dlsch->pdu_type == NFAPI_DL_CONFIG_DLSCH_PDU_TYPE); - nfapi_dl_config_request_pdu_t* dl_config_pdu_list = req->dl_config_request_body.dl_config_pdu_list; + const rnti_t rnti = dci->dci_dl_pdu.dci_dl_pdu_rel8.rnti; + const int rnti_type = dci->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type; + if (rnti != dlsch->dlsch_pdu.dlsch_pdu_rel8.rnti) { + LOG_E(MAC, + "%s(): sfn/sf %d.%d DLSCH PDU RNTI %x does not match DCI RNTI %x\n", + __func__, sfn, sf, rnti, dlsch->dlsch_pdu.dlsch_pdu_rel8.rnti); + return; + } - for (int i = 0; i < req->dl_config_request_body.number_pdu; i++) { - if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE) { - const rnti_t rnti = dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti; - const int rnti_type = dl_config_pdu_list[i].dci_dl_pdu.dci_dl_pdu_rel8.rnti_type; - /* We assume the DCI DL PDU is followed by the DLSCH (the standard is - * more free), so advance by one more and directly process the - * following DLSCH PDU */ - i++; - AssertFatal(i < req->dl_config_request_body.number_pdu, - "Need PDU following DCI at index %d, but not found\n", - i); - nfapi_dl_config_request_pdu_t *dl_config_pdu_tmp = &dl_config_pdu_list[i]; - if (dl_config_pdu_tmp->pdu_type != NFAPI_DL_CONFIG_DLSCH_PDU_TYPE) { - LOG_E(MAC, "expected DLSCH PDU at index %d\n", i); - continue; - } - if (rnti != dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti) { - LOG_I(MAC, - "%s(): sfn/sf %d DLSCH PDU RNTI %x does not match DCI RNTI %x\n", - __func__, - NFAPI_SFNSF2DEC(req->sfn_sf), - rnti, - dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti); - continue; - } - const int pdu_index = dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index; - if (pdu_index < 0 && pdu_index >= tx_req_num_elems) { - LOG_E(MAC, - "dl_config_req_UE_MAC 2: Problem with receiving data: " - "sfn/sf:%d PDU[%d] size:%d, TX_PDU index: %d\n", - NFAPI_SFNSF2DEC(req->sfn_sf), - i, - dl_config_pdu_list[i].pdu_size, - dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index); - continue; - } - if (rnti_type == 1) { - // C-RNTI (Normal DLSCH case) - if (UE_mac_inst[Mod_id].crnti != rnti) { - LOG_D(MAC, - "sfn/sf %d/%d DCI not for UE %d/RNTI %x but for RNTI %x, " - "skipping\n", - sfn, sf, Mod_id, UE_mac_inst[Mod_id].crnti, rnti); - continue; - } + const int pdu_index = dlsch->dlsch_pdu.dlsch_pdu_rel8.pdu_index; + if (pdu_index < 0 || pdu_index >= tx_req_num_elems) { + LOG_E(MAC, + "%s(): Problem with receiving data: " + "sfn/sf:%d.%d PDU size:%d, TX_PDU index: %d\n", + __func__, + sfn, sf, dci->pdu_size, dlsch->dlsch_pdu.dlsch_pdu_rel8.pdu_index); + return; + } + if (rnti_type == 1) { // C-RNTI (Normal DLSCH case) + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + if (UE_mac_inst[ue_id].crnti == rnti) { LOG_D(MAC, - "%s() Received data: sfn/sf:%d PDU[%d] " + "%s() Received data: sfn/sf:%d.%d " "size:%d, TX_PDU index: %d, tx_req_num_elems: %d \n", __func__, - NFAPI_SFNSF2DEC(req->sfn_sf), - i, - dl_config_pdu_list[i].pdu_size, - dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index, + sfn, sf, dci->pdu_size, + dlsch->dlsch_pdu.dlsch_pdu_rel8.pdu_index, tx_req_num_elems); - ue_send_sdu(Mod_id, 0, sfn, sf, + ue_send_sdu(ue_id, 0, sfn, sf, tx_request_pdu_list[pdu_index].segments[0].segment_data, tx_request_pdu_list[pdu_index].segments[0].segment_length, 0); - } else if (rnti_type == 2) { - if (rnti == 0xFFFF) { /* SI-RNTI */ - if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED) { - /* this check is in the code before refactoring, but I don't know - * why. Leave it in here for the moment */ - continue; - } - - ue_decode_si(Mod_id, 0, sfn, 0, - tx_request_pdu_list[pdu_index].segments[0].segment_data, - tx_request_pdu_list[pdu_index].segments[0].segment_length); - } else if (rnti == 0xFFFE) { /* PI-RNTI */ - LOG_I(MAC, "%s() Received paging message: sfn/sf:%d PDU[%d]\n", - __func__, NFAPI_SFNSF2DEC(req->sfn_sf), i); - ue_decode_p(Mod_id, 0, sfn, 0, - tx_request_pdu_list[pdu_index].segments[0].segment_data, - tx_request_pdu_list[pdu_index].segments[0].segment_length); - } else if (rnti == 0x0002) { /* RA-RNTI */ - LOG_E(MAC, "%s(): Received RAR?\n", __func__); - // RNTI parameter not actually used. Provided only to comply with - // existing function definition. Not sure about parameters to fill - // the preamble index. - const rnti_t ra_rnti = UE_mac_inst[Mod_id].RA_prach_resources.ra_RNTI; - DevAssert(ra_rnti == 0x0002); - if (UE_mac_inst[Mod_id].UE_mode[0] != PUSCH - && UE_mac_inst[Mod_id].RA_prach_resources.Msg3 != NULL - && ra_rnti == dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti) { - LOG_E(MAC, - "dl_config_req_UE_MAC 5 Received RAR, PreambleIndex: %d \n", - UE_mac_inst[Mod_id].RA_prach_resources.ra_PreambleIndex); - ue_process_rar(Mod_id, 0, sfn, - ra_rnti, //RA-RNTI - tx_request_pdu_list[pdu_index].segments[0].segment_data, - &dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.rnti, //t-crnti - UE_mac_inst[Mod_id].RA_prach_resources.ra_PreambleIndex, - tx_request_pdu_list[pdu_index].segments[0].segment_data); - UE_mac_inst[Mod_id].UE_mode[0] = RA_RESPONSE; - // Expecting an UL_CONFIG_ULSCH_PDU to enable Msg3 Txon (first - // ULSCH Txon for the UE) - UE_mac_inst[Mod_id].first_ULSCH_Tx = 1; - } - } else { - LOG_W(MAC, "can not handle special RNTI %x\n", rnti); - } - } - } else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE) { - // BCH case: Last parameter is 1 if first time synchronization and zero - // otherwise. Not sure which value to put for our case. - if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED){ - dl_phy_sync_success(Mod_id, sfn, 0, 1); - LOG_E(MAC, - "%s(): Received MIB: UE_mode: %d, sfn/sf: %d.%d\n", - __func__, - UE_mac_inst[Mod_id].UE_mode[0], - sfn, - sf); - UE_mac_inst[Mod_id].UE_mode[0] = PRACH; - } else { - dl_phy_sync_success(Mod_id, sfn, 0, 0); + return; } } + } else if (rnti_type == 2) { + if (rnti == 0xFFFF) { /* SI-RNTI */ + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + if (UE_mac_inst[ue_id].UE_mode[0] == NOT_SYNCHED) + continue; + + ue_decode_si(ue_id, 0, sfn, 0, + tx_request_pdu_list[pdu_index].segments[0].segment_data, + tx_request_pdu_list[pdu_index].segments[0].segment_length); + } + } else if (rnti == 0xFFFE) { /* PI-RNTI */ + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + LOG_I(MAC, "%s() Received paging message: sfn/sf:%d.%d\n", + __func__, sfn, sf); + ue_decode_p(ue_id, 0, sfn, 0, + tx_request_pdu_list[pdu_index].segments[0].segment_data, + tx_request_pdu_list[pdu_index].segments[0].segment_length); + } + } else if (rnti == 0x0002) { /* RA-RNTI */ + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + if (UE_mac_inst[ue_id].UE_mode[0] != RA_RESPONSE) { + LOG_D(MAC, "UE %d not awaiting RAR, is in mode %d\n", + ue_id, UE_mac_inst[ue_id].UE_mode[0]); + continue; + } + // RNTI parameter not actually used. Provided only to comply with + // existing function definition. Not sure about parameters to fill + // the preamble index. + const rnti_t ra_rnti = UE_mac_inst[ue_id].RA_prach_resources.ra_RNTI; + DevAssert(ra_rnti == 0x0002); + if (UE_mac_inst[ue_id].UE_mode[0] != PUSCH + && UE_mac_inst[ue_id].RA_prach_resources.Msg3 != NULL + && ra_rnti == dlsch->dlsch_pdu.dlsch_pdu_rel8.rnti) { + LOG_E(MAC, + "%s(): Received RAR, PreambleIndex: %d\n", + __func__, UE_mac_inst[ue_id].RA_prach_resources.ra_PreambleIndex); + ue_process_rar(ue_id, 0, sfn, + ra_rnti, //RA-RNTI + tx_request_pdu_list[pdu_index].segments[0].segment_data, + &UE_mac_inst[ue_id].crnti, //t-crnti + UE_mac_inst[ue_id].RA_prach_resources.ra_PreambleIndex, + tx_request_pdu_list[pdu_index].segments[0].segment_data); + UE_mac_inst[ue_id].UE_mode[0] = RA_RESPONSE; + // Expecting an UL_CONFIG_ULSCH_PDU to enable Msg3 Txon (first + // ULSCH Txon for the UE) + UE_mac_inst[ue_id].first_ULSCH_Tx = 1; + } + } + } else { + LOG_W(MAC, "can not handle special RNTI %x\n", rnti); + } } - return 0; } -int hi_dci0_req_UE_MAC(nfapi_hi_dci0_request_t *req, module_id_t Mod_id) { - if (req != NULL && req->hi_dci0_request_body.hi_dci0_pdu_list != NULL) { - LOG_D(PHY, - "[UE-PHY_STUB] hi dci0 request sfn_sf:%d number_of_dci:%d " - "number_of_hi:%d\n", - NFAPI_SFNSF2DEC(req->sfn_sf), - req->hi_dci0_request_body.number_of_dci, - req->hi_dci0_request_body.number_of_hi); +void dl_config_req_UE_MAC_bch(int sfn, + int sf, + nfapi_dl_config_request_pdu_t *bch, + int num_ue) { + DevAssert(bch->pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE); - for (int i = 0; i < req->hi_dci0_request_body.number_of_dci - + req->hi_dci0_request_body.number_of_hi; - i++) { - LOG_D(PHY, - "[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d]\n", - NFAPI_SFNSF2DEC(req->sfn_sf), - i); - - if (req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type - == NFAPI_HI_DCI0_DCI_PDU_TYPE) { - LOG_D(PHY, - "[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - " - "NFAPI_HI_DCI0_DCI_PDU_TYPE\n", - NFAPI_SFNSF2DEC(req->sfn_sf), - i); - const nfapi_hi_dci0_dci_pdu_rel8_t *dci = - &req->hi_dci0_request_body.hi_dci0_pdu_list[i].dci_pdu.dci_pdu_rel8; - if (dci->rnti != UE_mac_inst[Mod_id].crnti) - continue; - const int sfn = NFAPI_SFNSF2SFN(req->sfn_sf); - const int sf = NFAPI_SFNSF2SF(req->sfn_sf); - if (dci->cqi_csi_request) - fill_ulsch_cqi_indication_UE_MAC(Mod_id, sfn, sf, UL_INFO, dci->rnti); - } else if (req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type - == NFAPI_HI_DCI0_HI_PDU_TYPE) { - nfapi_hi_dci0_request_pdu_t *hi_dci0_req_pdu = - &req->hi_dci0_request_body.hi_dci0_pdu_list[i]; - - // This is meaningful only after ACKnowledging the first ULSCH Txon - // (i.e. Msg3) - if (hi_dci0_req_pdu->hi_pdu.hi_pdu_rel8.hi_value == 1 - && UE_mac_inst[Mod_id].first_ULSCH_Tx == 1) { - // LOG_I(MAC,"[UE-PHY_STUB] HI_DCI0_REQ 2 sfn_sf:%d PDU[%d] - - // NFAPI_HI_DCI0_HI_PDU_TYPE\n", NFAPI_SFNSF2DEC(req->sfn_sf), i); - // UE_mac_inst[Mod_id].UE_mode[0] = PUSCH; - // UE_mac_inst[Mod_id].first_ULSCH_Tx = 0; - } - - } else { - LOG_E(PHY, - "[UE-PHY_STUB] HI_DCI0_REQ sfn_sf:%d PDU[%d] - unknown pdu " - "type:%d\n", - NFAPI_SFNSF2DEC(req->sfn_sf), - i, - req->hi_dci0_request_body.hi_dci0_pdu_list[i].pdu_type); - } + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + if (UE_mac_inst[ue_id].UE_mode[0] == NOT_SYNCHED){ + dl_phy_sync_success(ue_id, sfn, 0, 1); + LOG_E(MAC, + "%s(): Received MIB: UE_mode: %d, sfn/sf: %d.%d\n", + __func__, + UE_mac_inst[ue_id].UE_mode[0], + sfn, + sf); + UE_mac_inst[ue_id].UE_mode[0] = PRACH; + } else { + dl_phy_sync_success(ue_id, sfn, 0, 0); } } +} - return 0; +void dl_config_req_UE_MAC_mch(int sfn, + int sf, + nfapi_dl_config_request_pdu_t *mch, + int num_ue) { + DevAssert(mch->pdu_type == NFAPI_DL_CONFIG_MCH_PDU_TYPE); + + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + if (UE_mac_inst[ue_id].UE_mode[0] == NOT_SYNCHED){ + LOG_D(MAC, + "%s(): Received MCH in NOT_SYNCHED: UE_mode: %d, sfn/sf: %d.%d\n", + __func__, + UE_mac_inst[ue_id].UE_mode[0], + sfn, + sf); + return; + + } else { + const int pdu_index = mch->mch_pdu.mch_pdu_rel8.pdu_index; + if (pdu_index < 0 || pdu_index >= tx_req_num_elems) { + LOG_E(MAC, + "%s(): Problem with receiving data: " + "sfn/sf:%d.%d PDU size:%d, TX_PDU index: %d\n", + __func__, + sfn, sf, mch->pdu_size, mch->mch_pdu.mch_pdu_rel8.pdu_index); + return; + } + ue_send_mch_sdu(ue_id, 0, sfn, + tx_request_pdu_list[pdu_index].segments[0].segment_data, + tx_request_pdu_list[pdu_index].segments[0].segment_length, + 0,0); + } + } +} + +void hi_dci0_req_UE_MAC(int sfn, + int sf, + nfapi_hi_dci0_request_pdu_t* hi_dci0, + int num_ue) { + if (hi_dci0->pdu_type != NFAPI_HI_DCI0_DCI_PDU_TYPE) + return; + + const nfapi_hi_dci0_dci_pdu_rel8_t *dci = &hi_dci0->dci_pdu.dci_pdu_rel8; + if (!dci->cqi_csi_request) + return; + for (int ue_id = 0; ue_id < num_ue; ue_id++) { + if (dci->rnti == UE_mac_inst[ue_id].crnti) { + fill_ulsch_cqi_indication_UE_MAC(ue_id, sfn, sf, UL_INFO, dci->rnti); + return; + } + } } // The following set of memcpy functions should be getting called as callback // functions from pnf_p7_subframe_ind. -int memcpy_dl_config_req(nfapi_pnf_p7_config_t *pnf_p7, +int memcpy_dl_config_req(L1_rxtx_proc_t *proc, + nfapi_pnf_p7_config_t *pnf_p7, nfapi_dl_config_request_t *req) { dl_config_req = (nfapi_dl_config_request_t *)malloc(sizeof(nfapi_dl_config_request_t)); @@ -929,10 +911,11 @@ int memcpy_dl_config_req(nfapi_pnf_p7_config_t *pnf_p7, return 0; } -int memcpy_ul_config_req(nfapi_pnf_p7_config_t *pnf_p7, - nfapi_ul_config_request_t *req) { +int memcpy_ul_config_req (L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t* pnf_p7, nfapi_ul_config_request_t* req) +{ ul_config_req = malloc(sizeof(nfapi_ul_config_request_t)); + ul_config_req->sfn_sf = req->sfn_sf; ul_config_req->vendor_extension = req->vendor_extension; @@ -976,9 +959,12 @@ int memcpy_tx_req(nfapi_pnf_p7_config_t *pnf_p7, nfapi_tx_request_t *req) { return 0; } -int memcpy_hi_dci0_req(nfapi_pnf_p7_config_t *pnf_p7, - nfapi_hi_dci0_request_t *req) { +int memcpy_hi_dci0_req (L1_rxtx_proc_t *proc, + nfapi_pnf_p7_config_t* pnf_p7, + nfapi_hi_dci0_request_t* req) { hi_dci0_req = (nfapi_hi_dci0_request_t *)malloc(sizeof(nfapi_hi_dci0_request_t)); + //if(req!=0){ + hi_dci0_req->sfn_sf = req->sfn_sf; hi_dci0_req->vendor_extension = req->vendor_extension; @@ -1093,7 +1079,7 @@ void handle_nfapi_dlsch_pdu(PHY_VARS_eNB *eNB, int frame, int subframe, L1_rxtx_proc_t *proc, - nfapi_dl_config_request_pdu_t *dl_config_pdu, + nfapi_dl_config_request_pdu_t *dl_config_pdu, uint8_t codeword_index, uint8_t *sdu) { } @@ -1105,6 +1091,11 @@ void handle_nfapi_ul_pdu(PHY_VARS_eNB *eNB, uint8_t subframe, uint8_t srs_present) { } +void handle_nfapi_mch_pdu(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, + nfapi_dl_config_request_pdu_t *dl_config_pdu, + uint8_t *sdu) { +} void phy_config_request(PHY_Config_t *phy_config) { } diff --git a/openair2/PHY_INTERFACE/phy_stub_UE.h b/openair2/PHY_INTERFACE/phy_stub_UE.h index 21fb8518fa..09356fc9f8 100644 --- a/openair2/PHY_INTERFACE/phy_stub_UE.h +++ b/openair2/PHY_INTERFACE/phy_stub_UE.h @@ -93,27 +93,41 @@ void handle_nfapi_ul_pdu_UE_MAC(module_id_t Mod_id, nfapi_ul_config_request_pdu_t *ul_config_pdu, uint16_t frame,uint8_t subframe,uint8_t srs_present, int index); -//int dl_config_req_UE_MAC(nfapi_dl_config_request_t* req, nfapi_tx_request_pdu_t* tx_request_pdu_list); -int dl_config_req_UE_MAC(nfapi_dl_config_request_t* req, module_id_t Mod_id); +void dl_config_req_UE_MAC_dci(int sfn, + int sf, + nfapi_dl_config_request_pdu_t *dci, + nfapi_dl_config_request_pdu_t *dlsch, + int num_ue); +void dl_config_req_UE_MAC_bch(int sfn, + int sf, + nfapi_dl_config_request_pdu_t *bch, + int num_ue); +void dl_config_req_UE_MAC_mch(int sfn, + int sf, + nfapi_dl_config_request_pdu_t *bch, + int num_ue); int tx_req_UE_MAC(nfapi_tx_request_t* req); -int hi_dci0_req_UE_MAC(nfapi_hi_dci0_request_t* req, module_id_t Mod_id); +void hi_dci0_req_UE_MAC(int sfn, + int sf, + nfapi_hi_dci0_request_pdu_t* bch, + int num_ue); // The following set of memcpy functions should be getting called as callback functions from // pnf_p7_subframe_ind. -int memcpy_dl_config_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_dl_config_request_t* req); +int memcpy_dl_config_req (L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t* pnf_p7, nfapi_dl_config_request_t* req); -int memcpy_ul_config_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_ul_config_request_t* req); +int memcpy_ul_config_req (L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t* pnf_p7, nfapi_ul_config_request_t* req); int memcpy_tx_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_tx_request_t* req); -int memcpy_hi_dci0_req (nfapi_pnf_p7_config_t* pnf_p7, nfapi_hi_dci0_request_t* req); +int memcpy_hi_dci0_req (L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t* pnf_p7, nfapi_hi_dci0_request_t* req); void UE_config_stub_pnf(void); diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 1d25bf180a..5965e51720 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -656,7 +656,7 @@ rrc_eNB_get_next_transaction_identifier( // AssertFatal(enb_mod_idP < NB_eNB_INST, "eNB index invalid (%d/%d)!", enb_mod_idP, NB_eNB_INST); // // for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { -// if (RC.rrc[enb_mod_idP]->Info.UE_list[i] == UE_identity) { +// if (RC.rrc[enb_mod_idP]->Info.UE_info[i] == UE_identity) { // // UE_identity already registered // reg = TRUE; // break; @@ -1476,9 +1476,9 @@ rrc_eNB_generate_RRCConnectionReestablishment( if (UE_id != -1) { /* Activate reject timer, if RRCComplete not received after 10 frames, reject UE */ - RC.mac[module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1; + RC.mac[module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1; /* Reject UE after 10 frames, LTE_RRCConnectionReestablishmentReject is triggered */ - RC.mac[module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres = 100; + RC.mac[module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres = 100; } else { LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Generating LTE_RRCConnectionReestablishment without UE_id(MAC) rnti %x\n", PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), @@ -2086,8 +2086,8 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( int UE_id = find_UE_id(ctxt_pP->module_id, ctxt_pP->rnti); if(UE_id != -1) { - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1; - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres = 20; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres = 20; } else { LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Generating LTE_RRCConnectionReestablishmentReject without UE_id(MAC) rnti %x\n", @@ -2134,6 +2134,8 @@ rrc_eNB_generate_RRCConnectionRelease( { uint8_t buffer[RRC_BUF_SIZE]; uint16_t size = 0; + int release_num; + memset(buffer, 0, RRC_BUF_SIZE); T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); @@ -2161,12 +2163,9 @@ rrc_eNB_generate_RRCConnectionRelease( ue_context_pP->ue_context.rnti, rrc_eNB_mui, size); + pthread_mutex_lock(&rrc_release_freelist); - while (pthread_mutex_trylock(&rrc_release_freelist)) { - /* spin... */ - } - - for (uint16_t release_num = 0; release_num < NUMBER_OF_UE_MAX; release_num++) { + for (release_num = 0; release_num < NUMBER_OF_UE_MAX; release_num++) { if (rrc_release_info.RRC_release_ctrl[release_num].flag == 0) { if (ue_context_pP->ue_context.ue_release_timer_s1 > 0) { rrc_release_info.RRC_release_ctrl[release_num].flag = 1; @@ -2186,6 +2185,12 @@ rrc_eNB_generate_RRCConnectionRelease( } } + /* TODO: what to do if RRC_release_ctrl is full? For now, exit. */ + if (release_num == NUMBER_OF_UE_MAX) { + LOG_E(RRC, "fatal: rrc_release_info.RRC_release_ctrl is full\n"); + exit(1); + } + pthread_mutex_unlock(&rrc_release_freelist); if (NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type)) { @@ -3512,6 +3517,35 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t size, buffer, PDCP_TRANSMISSION_MODE_CONTROL); + + /* Refresh SRBs/DRBs */ + rrc_pdcp_config_asn1_req(ctxt_pP, + *SRB_configList2, // NULL, + *DRB_configList, + NULL, + 0xff, // already configured during the securitymodecommand + NULL, + NULL, + NULL +#if (LTE_RRC_VERSION >= MAKE_VERSION(9, 0, 0)) + , (LTE_PMCH_InfoList_r9_t *) NULL +#endif + , NULL); + + /* Refresh SRBs/DRBs */ + if (!NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type)) { + rrc_rlc_config_asn1_req(ctxt_pP, + *SRB_configList2, // NULL, + *DRB_configList, + NULL +#if (LTE_RRC_VERSION >= MAKE_VERSION(9, 0, 0)) + , (LTE_PMCH_InfoList_r9_t *) NULL, + 0, + 0 +#endif + ); + } + free(Sparams); Sparams = NULL; free(quantityConfig->quantityConfigEUTRA->filterCoefficientRSRP); @@ -5192,13 +5226,13 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct DRB_rlc_config = CALLOC(1, sizeof(*DRB_rlc_config)); DRB_config->rlc_Config = DRB_rlc_config; #ifdef RRC_DEFAULT_RAB_IS_AM - DRB_rlc_config->present = RLC_Config_PR_am; - DRB_rlc_config->choice.am.ul_AM_RLC.t_PollRetransmit = T_PollRetransmit_ms50; - DRB_rlc_config->choice.am.ul_AM_RLC.pollPDU = PollPDU_p16; - DRB_rlc_config->choice.am.ul_AM_RLC.pollByte = PollByte_kBinfinity; - DRB_rlc_config->choice.am.ul_AM_RLC.maxRetxThreshold = UL_AM_RLC__maxRetxThreshold_t8; - DRB_rlc_config->choice.am.dl_AM_RLC.t_Reordering = T_Reordering_ms35; - DRB_rlc_config->choice.am.dl_AM_RLC.t_StatusProhibit = T_StatusProhibit_ms25; + DRB_rlc_config->present = LTE_RLC_Config_PR_am; + DRB_rlc_config->choice.am.ul_AM_RLC.t_PollRetransmit = LTE_T_PollRetransmit_ms50; + DRB_rlc_config->choice.am.ul_AM_RLC.pollPDU = LTE_PollPDU_p16; + DRB_rlc_config->choice.am.ul_AM_RLC.pollByte = LTE_PollByte_kBinfinity; + DRB_rlc_config->choice.am.ul_AM_RLC.maxRetxThreshold = LTE_UL_AM_RLC__maxRetxThreshold_t8; + DRB_rlc_config->choice.am.dl_AM_RLC.t_Reordering = LTE_T_Reordering_ms35; + DRB_rlc_config->choice.am.dl_AM_RLC.t_StatusProhibit = LTE_T_StatusProhibit_ms25; #else DRB_rlc_config->present = LTE_RLC_Config_PR_um_Bi_Directional; DRB_rlc_config->choice.um_Bi_Directional.ul_UM_RLC.sn_FieldLength = LTE_SN_FieldLength_size10; @@ -6029,6 +6063,35 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct ue_context_pP->ue_context.rnti, rrc_eNB_mui, size); + + /* Refresh SRBs/DRBs */ + rrc_pdcp_config_asn1_req(ctxt_pP, + *SRB_configList2, // NULL, + *DRB_configList, + NULL, + 0xff, // already configured during the securitymodecommand + NULL, + NULL, + NULL +#if (LTE_RRC_VERSION >= MAKE_VERSION(9, 0, 0)) + , (LTE_PMCH_InfoList_r9_t *) NULL +#endif + , NULL); + + /* Refresh SRBs/DRBs */ + if (!NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type)) { + rrc_rlc_config_asn1_req(ctxt_pP, + *SRB_configList2, // NULL, + *DRB_configList, + NULL +#if (LTE_RRC_VERSION >= MAKE_VERSION(9, 0, 0)) + , (LTE_PMCH_InfoList_r9_t *) NULL, + 0, + 0 +#endif + ); + } + free(quantityConfig->quantityConfigEUTRA->filterCoefficientRSRQ); quantityConfig->quantityConfigEUTRA->filterCoefficientRSRQ = NULL; free(quantityConfig->quantityConfigEUTRA->filterCoefficientRSRP); @@ -6072,12 +6135,14 @@ rrc_eNB_configure_rbs_handover(struct rrc_eNB_ue_context_s *ue_context_p, protoc NULL, NULL, (LTE_PMCH_InfoList_r9_t *) NULL, NULL); - rrc_rlc_config_asn1_req(ctxt_pP, - ue_context_p->ue_context.SRB_configList, - (LTE_DRB_ToAddModList_t *) NULL, - (LTE_DRB_ToReleaseList_t *) NULL, - (LTE_PMCH_InfoList_r9_t *) NULL, 0, 0 - ); + if (!NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type)) { + rrc_rlc_config_asn1_req(ctxt_pP, + ue_context_p->ue_context.SRB_configList, + (LTE_DRB_ToAddModList_t *) NULL, + (LTE_DRB_ToReleaseList_t *) NULL, + (LTE_PMCH_InfoList_r9_t *) NULL, 0, 0 + ); + } if (EPC_MODE_ENABLED) { rrc_eNB_process_security ( @@ -6168,7 +6233,7 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( return; } - UE_sched_ctrl_t *UE_scheduling_control = &(RC.mac[module_id]->UE_list.UE_sched_ctrl[UE_id_mac]); + UE_sched_ctrl_t *UE_scheduling_control = &(RC.mac[module_id]->UE_info.UE_sched_ctrl[UE_id_mac]); if (UE_scheduling_control->cdrx_waiting_ack == TRUE) { UE_scheduling_control->cdrx_waiting_ack = FALSE; @@ -6212,14 +6277,16 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( (LTE_PMCH_InfoList_r9_t *) NULL, NULL); /* Refresh SRBs/DRBs */ - rrc_rlc_config_asn1_req(ctxt_pP, - SRB_configList, // NULL, - DRB_configList, - DRB_Release_configList2, - (LTE_PMCH_InfoList_r9_t *) NULL, - 0, - 0 - ); + if (!NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type)) { + rrc_rlc_config_asn1_req(ctxt_pP, + SRB_configList, // NULL, + DRB_configList, + DRB_Release_configList2, + (LTE_PMCH_InfoList_r9_t *) NULL, + 0, + 0 + ); + } /* Set the SRB active in UE context */ if (SRB_configList != NULL) { @@ -6615,14 +6682,6 @@ char openair_rrc_eNB_configuration( LOG_I(RRC, PROTOCOL_RRC_CTXT_FMT" Init...\n", PROTOCOL_RRC_CTXT_ARGS(&ctxt)); -#if OCP_FRAMEWORK - - while ( RC.rrc[enb_mod_idP] == NULL ) { - LOG_E(RRC, "RC.rrc not yet initialized, waiting 1 second\n"); - sleep(1); - } - -#endif AssertFatal(RC.rrc[enb_mod_idP] != NULL, "RC.rrc not initialized!"); AssertFatal(MAX_MOBILES_PER_ENB < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow"); AssertFatal(configuration!=NULL,"configuration input is null\n"); @@ -6831,12 +6890,12 @@ rrc_eNB_decode_ccch( break; } - if((RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer > 0) && - (RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres > 20)) { + if((RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer > 0) && + (RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres > 20)) { LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RCConnectionReestablishmentComplete(Previous) don't receive, delete the c-rnti UE\n", PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP)); - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1000; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1000; rrc_eNB_previous_SRB2(ue_context_p); ue_context_p->ue_context.ue_reestablishment_timer = 0; } @@ -6862,12 +6921,12 @@ rrc_eNB_decode_ccch( break; } - if((RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer > 0) && - (RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres > 20)) { + if((RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer > 0) && + (RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer_thres > 20)) { LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RCConnectionReestablishmentComplete(Previous) don't receive, delete the Previous UE\n", PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP)); - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1000; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1000; rrc_eNB_previous_SRB2(ue_context_p); ue_context_p->ue_context.ue_reestablishment_timer = 0; } @@ -7439,12 +7498,12 @@ rrc_eNB_decode_dcch( AssertFatal(!NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type), "CU cannot decode DCCH: no access to RC.mac[]\n"); - if(RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].crnti_reconfigurationcomplete_flag == 1) { + if(RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].crnti_reconfigurationcomplete_flag == 1) { LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" UE State = RRC_RECONFIGURED (dedicated DRB, xid %ld) C-RNTI Complete\n", PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.rrc_TransactionIdentifier); dedicated_DRB = 2; - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].crnti_reconfigurationcomplete_flag = 0; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].crnti_reconfigurationcomplete_flag = 0; } } else if (ue_context_p->ue_context.Status == RRC_HO_EXECUTION) { int16_t UE_id = find_UE_id(ctxt_pP->module_id, ctxt_pP->rnti); @@ -7459,7 +7518,7 @@ rrc_eNB_decode_dcch( flexran_agent_handover = 1; RC.rrc[ctxt_pP->module_id]->Nb_ue++; dedicated_DRB = 3; - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].crnti_reconfigurationcomplete_flag = 0; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].crnti_reconfigurationcomplete_flag = 0; ue_context_p->ue_context.Status = RRC_RECONFIGURED; if(ue_context_p->ue_context.handover_info) { @@ -7637,7 +7696,7 @@ rrc_eNB_decode_dcch( break; } - RC.mac[ctxt_pP->module_id]->UE_list.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 0; + RC.mac[ctxt_pP->module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 0; ue_context_p->ue_context.reestablishment_xid = -1; if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReestablishmentComplete.criticalExtensions.present == @@ -8166,6 +8225,143 @@ void rrc_enb_init(void) { memset(&rrc_release_info,0,sizeof(RRC_release_list_t)); } +//----------------------------------------------------------------------------- +void process_successful_rlc_sdu_indication(int instance, + int rnti, + int message_id) +{ + int release_num; + int release_total; + RRC_release_ctrl_t *release_ctrl; + + /* Check if the message sent was RRC Connection Release. + * If yes then continue the release process. + */ + + pthread_mutex_lock(&rrc_release_freelist); + + if (rrc_release_info.num_UEs > 0) { + release_total = 0; + + for (release_num = 0, release_ctrl = &rrc_release_info.RRC_release_ctrl[0]; + release_num < NUMBER_OF_UE_MAX; + release_num++, release_ctrl++) { + if(release_ctrl->flag > 0) { + release_total++; + } else { + continue; + } + + if (release_ctrl->flag == 1 && release_ctrl->rnti == rnti && release_ctrl->rrc_eNB_mui == message_id) { + release_ctrl->flag = 3; + LOG_D(MAC,"DLSCH Release send:index %d rnti %x mui %d flag 1->3\n", + release_num, + rnti, + message_id); + break; + } + + if (release_ctrl->flag == 2 && release_ctrl->rnti == rnti && release_ctrl->rrc_eNB_mui == message_id) { + release_ctrl->flag = 4; + LOG_D(MAC, "DLSCH Release send:index %d rnti %x mui %d flag 2->4\n", + release_num, + rnti, + message_id); + break; + } + + if(release_total >= rrc_release_info.num_UEs) + break; + } + } + + pthread_mutex_unlock(&rrc_release_freelist); +} + +//----------------------------------------------------------------------------- +void process_unsuccessful_rlc_sdu_indication(int instance, int rnti) +{ + int release_num; + int release_total; + RRC_release_ctrl_t *release_ctrl; + + /* radio link failure detected by RLC layer, remove UE properly */ + + pthread_mutex_lock(&rrc_release_freelist); + + /* first, check if the rnti is in the list rrc_release_info.RRC_release_ctrl */ + + if (rrc_release_info.num_UEs > 0) { + release_total = 0; + + for (release_num = 0, release_ctrl = &rrc_release_info.RRC_release_ctrl[0]; + release_num < NUMBER_OF_UE_MAX; + release_num++, release_ctrl++) { + if(release_ctrl->flag > 0) { + release_total++; + } else { + continue; + } + + if (release_ctrl->flag == 1 && release_ctrl->rnti == rnti) { + release_ctrl->flag = 3; + LOG_D(MAC,"DLSCH Release send:index %d rnti %x flag 1->3\n", + release_num, + rnti); + goto done; + } + + if (release_ctrl->flag == 2 && release_ctrl->rnti == rnti) { + release_ctrl->flag = 4; + LOG_D(MAC, "DLSCH Release send:index %d rnti %x flag 2->4\n", + release_num, + rnti); + goto done; + } + + if(release_total >= rrc_release_info.num_UEs) + break; + } + } + + /* it's not in the list, put it with flag = 4 */ + for (release_num = 0; release_num < NUMBER_OF_UE_MAX; release_num++) { + if (rrc_release_info.RRC_release_ctrl[release_num].flag == 0) { + rrc_release_info.RRC_release_ctrl[release_num].flag = 4; + rrc_release_info.RRC_release_ctrl[release_num].rnti = rnti; + rrc_release_info.RRC_release_ctrl[release_num].rrc_eNB_mui = -1; /* not defined */ + rrc_release_info.num_UEs++; + LOG_D(RRC, "radio link failure detected: index %d rnti %x flag %d \n", + release_num, + rnti, + rrc_release_info.RRC_release_ctrl[release_num].flag); + break; + } + } + + /* TODO: what to do if rrc_release_info.RRC_release_ctrl is full? */ + if (release_num == NUMBER_OF_UE_MAX) { + LOG_E(RRC, "fatal: radio link failure: rrc_release_info.RRC_release_ctrl is full\n"); + exit(1); + } + +done: + pthread_mutex_unlock(&rrc_release_freelist); +} + +//----------------------------------------------------------------------------- +void process_rlc_sdu_indication(int instance, + int rnti, + int is_successful, + int srb_id, + int message_id) +{ + if (is_successful) + process_successful_rlc_sdu_indication(instance, rnti, message_id); + else + process_unsuccessful_rlc_sdu_indication(instance, rnti); +} + //----------------------------------------------------------------------------- int add_ue_to_remove(struct rrc_eNB_ue_context_s **ue_to_be_removed, int removed_ue_count, @@ -8868,6 +9064,13 @@ void *rrc_enb_process_itti_msg(void *notUsed) { rrc_eNB_process_M2AP_MCE_CONFIGURATION_UPDATE(&ctxt,&M2AP_MCE_CONFIGURATION_UPDATE(msg_p)); break; + case RLC_SDU_INDICATION: + process_rlc_sdu_indication(instance, + RLC_SDU_INDICATION(msg_p).rnti, + RLC_SDU_INDICATION(msg_p).is_successful, + RLC_SDU_INDICATION(msg_p).srb_id, + RLC_SDU_INDICATION(msg_p).message_id); + break; default: LOG_E(RRC, "[eNB %d] Received unexpected message %s\n", instance, msg_name_p); @@ -8904,7 +9107,7 @@ rrc_enb_task( //if (go_nr) rrc_go_nr(); } } -} + } /*------------------------------------------------------------------------------*/ void diff --git a/openair2/RRC/LTE/rrc_eNB_UE_context.h b/openair2/RRC/LTE/rrc_eNB_UE_context.h index 289b4d69d6..e22f517d50 100644 --- a/openair2/RRC/LTE/rrc_eNB_UE_context.h +++ b/openair2/RRC/LTE/rrc_eNB_UE_context.h @@ -28,6 +28,8 @@ * \email: lionel.gauthier@eurecom.fr */ #ifndef __RRC_ENB_UE_CONTEXT_H__ +#define __RRC_ENB_UE_CONTEXT_H__ + #include "collection/tree.h" #include "COMMON/platform_types.h" #include "rrc_defs.h" diff --git a/openair2/RRC/LTE/utils.c b/openair2/RRC/LTE/utils.c index 08637e0e67..c84a2be476 100644 --- a/openair2/RRC/LTE/utils.c +++ b/openair2/RRC/LTE/utils.c @@ -60,11 +60,11 @@ uint8_t rrc_find_free_ue_index(uint8_t Mod_id) { uint16_t i; for(i=1; i<=NB_CNX_CH; i++) - if ( (CH_rrc_inst[Mod_id].Info.UE_list[i][0] == 0) && - (CH_rrc_inst[Mod_id].Info.UE_list[i][1] == 0) && - (CH_rrc_inst[Mod_id].Info.UE_list[i][2] == 0) && - (CH_rrc_inst[Mod_id].Info.UE_list[i][3] == 0) && - (CH_rrc_inst[Mod_id].Info.UE_list[i][4] == 0)) { + if ( (CH_rrc_inst[Mod_id].Info.UE_info[i][0] == 0) && + (CH_rrc_inst[Mod_id].Info.UE_info[i][1] == 0) && + (CH_rrc_inst[Mod_id].Info.UE_info[i][2] == 0) && + (CH_rrc_inst[Mod_id].Info.UE_info[i][3] == 0) && + (CH_rrc_inst[Mod_id].Info.UE_info[i][4] == 0)) { return i; } @@ -78,7 +78,7 @@ unsigned short rrc_find_ue_index(unsigned char Mod_id, L2_ID Mac_id) { unsigned char i; /* for(i=0;i<=NB_CNX_CH;i++) - if( bcmp(Mac_id.L2_id,CH_rrc_inst[Mod_id].Info.UE_list[i].L2_id,sizeof(L2_ID))==0) + if( bcmp(Mac_id.L2_id,CH_rrc_inst[Mod_id].Info.UE_info[i].L2_id,sizeof(L2_ID))==0) return i; return i; */ @@ -167,7 +167,7 @@ unsigned char rrc_is_mobile_already_associated(uint8_t Mod_id, L2_ID Mac_id) { /* unsigned char i; for(i=0;iconfiguration = common_configuration; diff --git a/openair2/RRC/NR/nr_rrc_extern.h b/openair2/RRC/NR/nr_rrc_extern.h index 8373a53584..04e0392236 100644 --- a/openair2/RRC/NR/nr_rrc_extern.h +++ b/openair2/RRC/NR/nr_rrc_extern.h @@ -28,8 +28,8 @@ * \email: navid.nikaein@eurecom.fr, kroempa@gmail.com */ -#ifndef __OPENAIR_RRC_EXTERN_H__ -#define __OPENAIR_RRC_EXTERN_H__ +#ifndef __OPENAIR_NR_RRC_EXTERN_H__ +#define __OPENAIR_NR_RRC_EXTERN_H__ #include "nr_rrc_defs.h" #include "COMMON/mac_rrc_primitives.h" #include "LAYER2/MAC/mac.h" @@ -69,10 +69,12 @@ extern uint32_t timeToTrigger_ms[16]; extern float RSRP_meas_mapping[98]; extern float RSRQ_meas_mapping[35]; -extern UE_PF_PO_t UE_PF_PO[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; +extern UE_PF_PO_t UE_PF_PO[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; + extern pthread_mutex_t ue_pf_po_mutex; -extern uint16_t reestablish_rnti_map[NUMBER_OF_UE_MAX][2]; +extern uint16_t reestablish_rnti_map[MAX_MOBILES_PER_ENB][2]; +char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigurationReq *configuration); #endif diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index fba6610554..5ece5f9169 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -81,6 +81,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #include "executables/softmodem-common.h" +#include //#define XER_PRINT @@ -267,13 +268,6 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Init...\n", PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); -#if OCP_FRAMEWORK - - while (rrc == NULL ) { - LOG_E(NR_RRC, "RC.nrrrc not yet initialized, waiting 1 second\n"); - sleep(1); - } -#endif AssertFatal(rrc != NULL, "RC.nrrrc not initialized!"); AssertFatal(NUMBER_OF_UE_MAX < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow"); AssertFatal(configuration!=NULL,"configuration input is null\n"); diff --git a/openair2/RRC/NR/rrc_gNB_UE_context.h b/openair2/RRC/NR/rrc_gNB_UE_context.h index 4681cabb8f..d703c4c34c 100644 --- a/openair2/RRC/NR/rrc_gNB_UE_context.h +++ b/openair2/RRC/NR/rrc_gNB_UE_context.h @@ -27,7 +27,9 @@ * \company Eurecom * \email: lionel.gauthier@eurecom.fr */ -#ifndef __RRC_ENB_UE_CONTEXT_H__ +#ifndef __RRC_GNB_UE_CONTEXT_H__ +#define __RRC_GNB_UE_CONTEXT_H__ + #include "collection/tree.h" #include "COMMON/platform_types.h" #include "nr_rrc_defs.h" @@ -58,7 +60,7 @@ int rrc_gNB_compare_ue_rnti_id( struct rrc_gNB_ue_context_s* c2_pP ); -RB_PROTOTYPE(rrc_ue_tree_s, rrc_gNB_ue_context_s, entries, rrc_gNB_compare_ue_rnti_id); +RB_PROTOTYPE(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s, entries, rrc_gNB_compare_ue_rnti_id); struct rrc_gNB_ue_context_s* rrc_gNB_allocate_new_UE_context( diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index cf48aef459..763c208dfe 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -41,9 +41,9 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; - OCTET_STRING_t *ueCapabilityRAT_Container_nr; - OCTET_STRING_t *ueCapabilityRAT_Container_MRDC; - int list_size; + OCTET_STRING_t *ueCapabilityRAT_Container_nr=NULL; + OCTET_STRING_t *ueCapabilityRAT_Container_MRDC=NULL; + int list_size=0; AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n"); AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count); for (int i=0;imem_lists[pool_index], "POOL"); - - for (index = 0; index < pool_sizes[pool_index]; index++) { - //memory->mem_blocks[mb_index + index].previous = NULL; -> done in memset 0 - //memory->mem_blocks[mb_index + index].next = NULL; -> done in memset 0 - switch (pool_index) { - case 0: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool0[index][0]); - break; - - case 1: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool1[index][0]); - break; - - case 2: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool2[index][0]); - break; - - case 3: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool3[index][0]); - break; - - case 4: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool4[index][0]); - break; - - case 5: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool5[index][0]); - break; - - case 6: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool6[index][0]); - break; - - case 7: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool7[index][0]); - break; - - case 8: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool8[index][0]); - break; - - case 9: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool9[index][0]); - break; - - case 10: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool10[index][0]); - break; - - case 11: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool11[index][0]); - break; - - case 12: - memory->mem_blocks[mb_index + index].data = (unsigned char*)&(memory->mem_pool12[index][0]); - break; - - default: - ; - memory->mem_blocks[mb_index + index].data = NULL; // pool copy - - } - - memory->mem_blocks[mb_index + index].pool_id = pool_index; - list_add_tail_eurecom (&memory->mem_blocks[mb_index + index], &memory->mem_lists[pool_index]); - } - - mb_index += pool_sizes[pool_index]; - } - -#ifdef MEMBLOCK_BIG_LOCK - if (pthread_mutex_unlock(&mtex)) abort(); -#endif - - return 0; -} - -//----------------------------------------------------------------------------- -void * -pool_buffer_clean (void *arg) -{ - //----------------------------------------------------------------------------- - return 0; -} -//----------------------------------------------------------------------------- -void -free_mem_block (mem_block_t * leP, const char* caller) -{ - //----------------------------------------------------------------------------- - - if (!(leP)) { - LOG_W (RLC,"[MEM_MNGT][FREE] WARNING FREE NULL MEM_BLOCK\n"); - return; - } - -#ifdef MEMBLOCK_BIG_LOCK - if (pthread_mutex_lock(&mtex)) abort(); -#endif - -#ifdef DEBUG_MEM_MNGT_FREE - LOG_D (RLC,"[MEM_MNGT][FREE] free_mem_block() %p pool: %d\n", leP, leP->pool_id); -#endif -#ifdef DEBUG_MEM_MNGT_ALLOC - check_free_mem_block (leP); -#endif - - if (leP->pool_id <= MEM_MNGT_POOL_ID_COPY) { - list_add_tail_eurecom (leP, &mem_block_var.mem_lists[leP->pool_id]); -#ifdef DEBUG_MEM_MNGT_ALLOC - counters[leP->pool_id] -= 1; - LGO_D (RLC,"[%s][MEM_MNGT][INFO] after pool[%2d] freed: counters = {%2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d}\n", - caller, leP->pool_id, - counters[0],counters[1],counters[2],counters[3],counters[4], - counters[5],counters[6],counters[7],counters[8],counters[9], - counters[10],counters[11]); -#endif - leP = NULL; // this prevent from freeing the block twice - } else { - LOG_E (RLC,"[MEM_MNGT][FREE] ERROR free_mem_block() unknown pool_id : %d\n", leP->pool_id); - } - -#ifdef MEMBLOCK_BIG_LOCK - if (pthread_mutex_unlock(&mtex)) abort(); -#endif -} - -//----------------------------------------------------------------------------- -mem_block_t * -get_free_mem_block (uint32_t sizeP, const char* caller) -{ - //----------------------------------------------------------------------------- - mem_block_t *le = NULL; - int pool_selected; - int size; - - if (sizeP > MEM_MNGT_MB12_BLOCK_SIZE) { - LOG_E (RLC,"[MEM_MNGT][ERROR][FATAL] size requested %d out of bounds\n", sizeP); - display_mem_load (); - AssertFatal(1==0,"get_free_mem_block size requested out of bounds"); - return NULL; - } - -#ifdef MEMBLOCK_BIG_LOCK - if (pthread_mutex_lock(&mtex)) abort(); -#endif - - size = sizeP >> 6; - pool_selected = 0; - - while ((size)) { - pool_selected += 1; - size = size >> 1; - } - - // pool is selected according to the size requested, now get a block - // if no block is available pick one in an other pool - do { - if ((le = list_remove_head (&mem_block_var.mem_lists[pool_selected]))) { -#ifdef DEBUG_MEM_MNGT_ALLOC - counters[pool_selected] += 1; - LOG_D (RLC,"[%s][MEM_MNGT][INFO] after pool[%2d] allocated: counters = {%2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d}\n", - caller, - pool_selected, - counters[0],counters[1],counters[2],counters[3],counters[4], - counters[5],counters[6],counters[7],counters[8],counters[9], - counters[10],counters[11]); -#endif -#ifdef DEBUG_MEM_MNGT_ALLOC_SIZE - LOG_D (RLC,"[MEM_MNGT][INFO] ALLOC MEM_BLOCK SIZE %d bytes pool %d (%p)\n", sizeP, pool_selected,le); -#endif - - AssertFatal(le->pool_id == pool_selected, "Unexpected pool ID!"); - -#ifdef MEMBLOCK_BIG_LOCK - if (pthread_mutex_unlock(&mtex)) abort(); -#endif - - return le; - } - -#ifdef DEBUG_MEM_MNGT_ALLOC - LOG_E (RLC,"[MEM_MNGT][ERROR][MINOR] memory pool %d is empty trying next pool alloc count = %d\n", pool_selected, counters[pool_selected]); - // display_mem_load (); - // check_mem_area ((void *)&mem_block_var); -#endif - } while (pool_selected++ < 12); - - LOG_E(PHY, "[MEM_MNGT][ERROR][FATAL] failed allocating MEM_BLOCK size %d byes (pool_selected=%d size=%d)\n", sizeP, pool_selected, size); -// display_mem_load(); -// AssertFatal(1==0,"get_free_mem_block failed"); - LOG_E(MAC,"[MEM_MNGT][ERROR][FATAL] get_free_mem_block failed!!!\n"); -#ifdef MEMBLOCK_BIG_LOCK - if (pthread_mutex_unlock(&mtex)) abort(); -#endif - - return NULL; -}; - -//----------------------------------------------------------------------------- -mem_block_t * -get_free_copy_mem_block (void) -{ - //----------------------------------------------------------------------------- - mem_block_t *le; - -#ifdef MEMBLOCK_BIG_LOCK - AssertFatal(0, "This function is not handled properly but not used anywhere. FIXME?\n"); -#endif - - if ((le = list_remove_head (&mem_block_var.mem_lists[MEM_MNGT_POOL_ID_COPY]))) { -#ifdef DEBUG_MEM_MNGT_ALLOC_SIZE - LOG_D (RLC,"[MEM_MNGT][INFO] ALLOC COPY MEM BLOCK (%p)\n",le); -#endif -#ifdef DEBUG_MEM_MNGT_ALLOC - counters[MEM_MNGT_POOL_ID_COPY] += 1; - LOG_D (RLC,"[MEM_MNGT][INFO] pool counters = {%2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d}\n", - counters[0],counters[1],counters[2],counters[3],counters[4], - counters[5],counters[6],counters[7],counters[8],counters[9], - counters[10],counters[11]); -#endif - return le; - } else { - LOG_E (RLC,"[MEM_MNGT][ERROR] POOL COPY IS EMPTY\n"); - //#ifdef DEBUG_MEM_MNGT_ALLOC - check_mem_area (); - // break_point (); - //#endif - - AssertFatal(1==0,"mem pool is empty"); - return NULL; - } -} - -//----------------------------------------------------------------------------- -mem_block_t * -copy_mem_block (mem_block_t * leP, mem_block_t * destP) -{ - //----------------------------------------------------------------------------- - -#ifdef MEMBLOCK_BIG_LOCK - AssertFatal(0, "This function is not handled properly but not used anywhere. FIXME?\n"); -#endif - - if ((destP != NULL) && (leP != NULL) && (destP->pool_id == MEM_MNGT_POOL_ID_COPY)) { - destP->data = leP->data; - } else { - LOG_E (RLC,"[MEM_MNGT][COPY] copy_mem_block() pool dest src or dest is NULL\n"); - } - - return destP; -} - -//----------------------------------------------------------------------------- -void -display_mem_load (void) -{ - //----------------------------------------------------------------------------- -#ifdef MEMBLOCK_BIG_LOCK - /* this function does not need to be protected, do nothing */ -#endif - - mem_pool *memory = (mem_pool *) &mem_block_var; - - LOG_D (RLC,"POOL 0 (%d elements of %d Bytes): ", MEM_MNGT_MB0_NB_BLOCKS, MEM_MNGT_MB0_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID0]); - LOG_D (RLC,"POOL 1 (%d elements of %d Bytes): ", MEM_MNGT_MB1_NB_BLOCKS, MEM_MNGT_MB1_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID1]); - LOG_D (RLC,"POOL 2 (%d elements of %d Bytes): ", MEM_MNGT_MB2_NB_BLOCKS, MEM_MNGT_MB2_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID2]); - LOG_D (RLC,"POOL 3 (%d elements of %d Bytes): ", MEM_MNGT_MB3_NB_BLOCKS, MEM_MNGT_MB3_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID3]); - LOG_D (RLC,"POOL 4 (%d elements of %d Bytes): ", MEM_MNGT_MB4_NB_BLOCKS, MEM_MNGT_MB4_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID4]); - LOG_D (RLC,"POOL 5 (%d elements of %d Bytes): ", MEM_MNGT_MB5_NB_BLOCKS, MEM_MNGT_MB5_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID5]); - LOG_D (RLC,"POOL 6 (%d elements of %d Bytes): ", MEM_MNGT_MB6_NB_BLOCKS, MEM_MNGT_MB6_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID6]); - LOG_D (RLC,"POOL 7 (%d elements of %d Bytes): ", MEM_MNGT_MB7_NB_BLOCKS, MEM_MNGT_MB7_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID7]); - LOG_D (RLC,"POOL 8 (%d elements of %d Bytes): ", MEM_MNGT_MB8_NB_BLOCKS, MEM_MNGT_MB8_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID8]); - LOG_D (RLC,"POOL 9 (%d elements of %d Bytes): ", MEM_MNGT_MB9_NB_BLOCKS, MEM_MNGT_MB9_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID9]); - LOG_D (RLC,"POOL 10 (%d elements of %d Bytes): ", MEM_MNGT_MB10_NB_BLOCKS, MEM_MNGT_MB10_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID10]); - LOG_D (RLC,"POOL 11 (%d elements of %d Bytes): ", MEM_MNGT_MB11_NB_BLOCKS, MEM_MNGT_MB11_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID11]); - LOG_D (RLC,"POOL 12 (%d elements of %d Bytes): ", MEM_MNGT_MB12_NB_BLOCKS, MEM_MNGT_MB12_BLOCK_SIZE); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID12]); - LOG_D (RLC,"POOL C (%d elements): ", MEM_MNGT_MBCOPY_NB_BLOCKS); - list_display (&memory->mem_lists[MEM_MNGT_POOL_ID_COPY]); -} - -//----------------------------------------------------------------------------- -void -check_mem_area (void) -{ - //----------------------------------------------------------------------------- - int index, mb_index; - mem_pool *memory = (mem_pool *) &mem_block_var; - -#ifdef MEMBLOCK_BIG_LOCK - AssertFatal(0, "This function is not handled properly but not used anywhere. FIXME?\n"); -#endif - - for (index = 0; index < MEM_MNGT_MB0_NB_BLOCKS; index++) { - if ((memory->mem_blocks[index].data != (unsigned char*)&(memory->mem_pool0[index][0])) && (memory->mem_blocks[index].pool_id != MEM_MNGT_POOL_ID0)) { - LOG_D (RLC,"[MEM] ERROR POOL0 block index %d\n", index); - } - } - - mb_index = MEM_MNGT_MB0_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB1_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool1[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID1)) { - LOG_D (RLC,"[MEM] ERROR POOL1 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB1_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB2_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool2[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID2)) { - LOG_D (RLC,"[MEM] ERROR POOL2 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB2_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB3_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool3[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID3)) { - LOG_D (RLC,"[MEM] ERROR POOL3 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB3_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB4_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool4[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID4)) { - LOG_D (RLC,"[MEM] ERROR POOL4 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB4_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB5_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool5[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID5)) { - LOG_D (RLC,"[MEM] ERROR POOL5 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB5_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB6_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool6[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID6)) { - LOG_D (RLC,"[MEM] ERROR POOL6 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB6_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB7_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool7[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID7)) { - LOG_D (RLC,"[MEM] ERROR POOL7 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB7_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB8_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool8[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID8)) { - LOG_D (RLC,"[MEM] ERROR POOL8 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB8_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB9_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool9[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID9)) { - LOG_D (RLC,"[MEM] ERROR POOL9 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB9_NB_BLOCKS; - - for (index = mb_index; index < MEM_MNGT_MB10_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool10[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID10)) { - LOG_D (RLC,"[MEM] ERROR POOL10 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB10_NB_BLOCKS; - - for (index = mb_index; index < MEM_MNGT_MB11_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool11[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID11)) { - LOG_D (RLC,"[MEM] ERROR POOL11 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB11_NB_BLOCKS; - - for (index = mb_index; index < MEM_MNGT_MB12_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != (unsigned char*)&(memory->mem_pool12[index][0])) - && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID12)) { - LOG_D (RLC,"[MEM] ERROR POOL12 block index %d\n", index); - } - } - - mb_index += MEM_MNGT_MB12_NB_BLOCKS; - - for (index = mb_index; index < MEM_MNGT_NB_ELEMENTS; index++) { - if ((memory->mem_blocks[index].data != NULL) && (memory->mem_blocks[index].pool_id != MEM_MNGT_POOL_ID_COPY)) { - LOG_D (RLC,"[MEM] ERROR POOL COPY block index %d\n", index); - } - } -} - -//----------------------------------------------------------------------------- -void -check_free_mem_block (mem_block_t * leP) -{ - //----------------------------------------------------------------------------- - ptrdiff_t block_index; - -#ifdef MEMBLOCK_BIG_LOCK - /* this function does not SEEM TO need to be protected, do nothing (for the moment) */ -#endif - - if ((leP >= mem_block_var.mem_blocks) && (leP <= &mem_block_var.mem_blocks[MEM_MNGT_NB_ELEMENTS-1])) { - // the pointer is inside the memory region - block_index = leP - mem_block_var.mem_blocks; - // block_index is now: 0 <= block_index < MEM_MNGT_NB_ELEMENTS - - if (block_index < MEM_MNGT_MB0_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool0[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID0)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB0_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB1_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool1[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID1)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB1_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB2_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool2[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID2)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB2_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB3_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool3[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID3)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB3_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB4_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool4[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID4)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB4_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB5_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool5[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID5)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB5_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB6_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool6[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID6)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB6_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB7_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool7[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID7)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB7_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB8_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool8[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID8)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB8_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB9_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool9[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID9)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB9_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB10_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool10[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID10)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB10_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB11_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool11[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID11)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - - block_index -= MEM_MNGT_MB11_NB_BLOCKS; - - if (block_index < MEM_MNGT_MB12_NB_BLOCKS) { - if ((leP->data != (unsigned char*)mem_block_var.mem_pool12[block_index]) && (leP->pool_id != MEM_MNGT_POOL_ID12)) { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - return; - } - } else { - LOG_D (RLC,"[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - - // the block is ok -} diff --git a/openair2/UTIL/MEM/mem_block.h b/openair2/UTIL/MEM/mem_block.h index f40566f6ed..0d99430640 100644 --- a/openair2/UTIL/MEM/mem_block.h +++ b/openair2/UTIL/MEM/mem_block.h @@ -57,91 +57,8 @@ mem_block_t *get_free_copy_mem_block (void); mem_block_t *get_free_copy_mem_block_up (void); mem_block_t *copy_mem_block (mem_block_t * leP, mem_block_t * destP); void display_mem_load (void); - -void check_mem_area (void); -void check_free_mem_block (mem_block_t * leP); -# define MEM_SCALE MAX_MOBILES_PER_ENB -// definition of the size of the allocated memory area -# define MEM_MNGT_MB0_BLOCK_SIZE 64 -// 64 -# define MEM_MNGT_MB0_NB_BLOCKS 4096 * MEM_SCALE -# define MEM_MNGT_POOL_ID0 0 - -# define MEM_MNGT_MB1_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*2 -// 128 -# define MEM_MNGT_MB1_NB_BLOCKS 4096 * MEM_SCALE -# define MEM_MNGT_POOL_ID1 1 - -# define MEM_MNGT_MB2_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*4 -// 256 -# define MEM_MNGT_MB2_NB_BLOCKS 2048 * MEM_SCALE -# define MEM_MNGT_POOL_ID2 2 - -# define MEM_MNGT_MB3_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*8 -// 512 -# define MEM_MNGT_MB3_NB_BLOCKS 2048 * MEM_SCALE -# define MEM_MNGT_POOL_ID3 3 - -# define MEM_MNGT_MB4_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*16 -// 1024 -# define MEM_MNGT_MB4_NB_BLOCKS 1024 * MEM_SCALE -# define MEM_MNGT_POOL_ID4 4 - -# define MEM_MNGT_MB5_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*32 -// 2048 -# define MEM_MNGT_MB5_NB_BLOCKS 1024 * MEM_SCALE // LG WAS 1024 -# define MEM_MNGT_POOL_ID5 5 - -# define MEM_MNGT_MB6_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*64 -// 4096 -# define MEM_MNGT_MB6_NB_BLOCKS 1024 * MEM_SCALE // LG WAS 256 -# define MEM_MNGT_POOL_ID6 6 - -# define MEM_MNGT_MB7_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*128 -// 8192 -# define MEM_MNGT_MB7_NB_BLOCKS 64* MEM_SCALE // LG WAS 32 -# define MEM_MNGT_POOL_ID7 7 - -# define MEM_MNGT_MB8_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*256 - -#ifdef JUMBO_FRAMES -# define MEM_MNGT_MB8_NB_BLOCKS 256 * MEM_SCALE -#else -# define MEM_MNGT_MB8_NB_BLOCKS 16 * MEM_SCALE -// 16384 -#endif -# define MEM_MNGT_POOL_ID8 8 - -# define MEM_MNGT_MB9_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*512 -// 32768 -# define MEM_MNGT_MB9_NB_BLOCKS 8 * MEM_SCALE -# define MEM_MNGT_POOL_ID9 9 - -# define MEM_MNGT_MB10_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*1024 -// 65536 -# define MEM_MNGT_MB10_NB_BLOCKS 0 * MEM_SCALE -# define MEM_MNGT_POOL_ID10 10 - -# define MEM_MNGT_MB11_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*2048 -// 131072 -# define MEM_MNGT_MB11_NB_BLOCKS 0 * MEM_SCALE -# define MEM_MNGT_POOL_ID11 11 - -# define MEM_MNGT_MB12_BLOCK_SIZE MEM_MNGT_MB0_BLOCK_SIZE*4096 -// 262144 -# define MEM_MNGT_MB12_NB_BLOCKS 32 * MEM_SCALE -//# define MEM_MNGT_MB12_NB_BLOCKS 4096 * MEM_SCALE - -# define MEM_MNGT_POOL_ID12 12 - - -# define MEM_MNGT_MBCOPY_NB_BLOCKS 1024 -# define MEM_MNGT_NB_ELEMENTS MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS + MEM_MNGT_MB5_NB_BLOCKS + MEM_MNGT_MB6_NB_BLOCKS + MEM_MNGT_MB7_NB_BLOCKS + MEM_MNGT_MB8_NB_BLOCKS + MEM_MNGT_MB9_NB_BLOCKS + MEM_MNGT_MB10_NB_BLOCKS + MEM_MNGT_MB11_NB_BLOCKS + MEM_MNGT_MB12_NB_BLOCKS + MEM_MNGT_MBCOPY_NB_BLOCKS -# define MEM_MNGT_POOL_ID_COPY 13 - #define LIST_NAME_MAX_CHAR 32 - typedef struct { struct mem_block_t *head; struct mem_block_t *tail; @@ -156,31 +73,6 @@ typedef struct { char name[LIST_NAME_MAX_CHAR]; } list_t; - - -typedef struct { - //----------------------------------------------------------- - // basic memory management - //----------------------------------------------------------- - char mem_pool0[MEM_MNGT_MB0_NB_BLOCKS][MEM_MNGT_MB0_BLOCK_SIZE]; - char mem_pool1[MEM_MNGT_MB1_NB_BLOCKS][MEM_MNGT_MB1_BLOCK_SIZE]; - char mem_pool2[MEM_MNGT_MB2_NB_BLOCKS][MEM_MNGT_MB2_BLOCK_SIZE]; - char mem_pool3[MEM_MNGT_MB3_NB_BLOCKS][MEM_MNGT_MB3_BLOCK_SIZE]; - char mem_pool4[MEM_MNGT_MB4_NB_BLOCKS][MEM_MNGT_MB4_BLOCK_SIZE]; - char mem_pool5[MEM_MNGT_MB5_NB_BLOCKS][MEM_MNGT_MB5_BLOCK_SIZE]; - char mem_pool6[MEM_MNGT_MB6_NB_BLOCKS][MEM_MNGT_MB6_BLOCK_SIZE]; - char mem_pool7[MEM_MNGT_MB7_NB_BLOCKS][MEM_MNGT_MB7_BLOCK_SIZE]; - char mem_pool8[MEM_MNGT_MB8_NB_BLOCKS][MEM_MNGT_MB8_BLOCK_SIZE]; - char mem_pool9[MEM_MNGT_MB9_NB_BLOCKS][MEM_MNGT_MB9_BLOCK_SIZE]; - char mem_pool10[MEM_MNGT_MB10_NB_BLOCKS][MEM_MNGT_MB10_BLOCK_SIZE]; - char mem_pool11[MEM_MNGT_MB11_NB_BLOCKS][MEM_MNGT_MB11_BLOCK_SIZE]; - char mem_pool12[MEM_MNGT_MB12_NB_BLOCKS][MEM_MNGT_MB12_BLOCK_SIZE]; - mem_block_t mem_blocks[MEM_MNGT_NB_ELEMENTS]; - list_t mem_lists[14]; - -} mem_pool; - - #ifdef __cplusplus } #endif diff --git a/openair2/UTIL/MEM/mem_mngt.c b/openair2/UTIL/MEM/mem_mngt.c deleted file mode 100644 index 57c90ea4f9..0000000000 --- a/openair2/UTIL/MEM/mem_mngt.c +++ /dev/null @@ -1,489 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*************************************************************************** - mem_mngt.c - description - ------------------- - AUTHOR : Lionel GAUTHIER - COMPANY : EURECOM - EMAIL : Lionel.Gauthier@eurecom.fr - - - ***************************************************************************/ -#define MEM_MNGT_C -#include "rtos_header.h" -#include "platform.h" -#include "protocol_vars_extern.h" -#include "print.h" - -#include "mem_block.h" -#include "mem_pool.h" -#include "lists_proto_extern.h" -#include "umts_sched.h" -//----------------------------------------------------------------------------- -#define DEBUG_MEM_MNGT_FREE -#define DEBUG_MEM_MNGT_ALLOC_SIZE -#define DEBUG_MEM_MNGT_ALLOC -#ifdef DEBUG_MEM_MNGT_ADDR -# define PRINT_MEM_MNGT_ADDR msg -#else -# define PRINT_MEM_MNGT_ADDR -// -#endif -//----------------------------------------------------------------------------- -uint32_t counters[11] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -//----------------------------------------------------------------------------- -/* - * initialize all ures - */ -void * -pool_buffer_init (void *arg) -{ - //----------------------------------------------------------------------------- - - uint32_t index, mb_index, pool_index; - mem_pool *memory = (mem_pool *) arg; - int pool_sizes[11] = { MEM_MNGT_MB0_NB_BLOCKS, MEM_MNGT_MB1_NB_BLOCKS, - MEM_MNGT_MB2_NB_BLOCKS, MEM_MNGT_MB3_NB_BLOCKS, - MEM_MNGT_MB4_NB_BLOCKS, MEM_MNGT_MB5_NB_BLOCKS, - MEM_MNGT_MB6_NB_BLOCKS, MEM_MNGT_MB7_NB_BLOCKS, - MEM_MNGT_MB8_NB_BLOCKS, MEM_MNGT_MB9_NB_BLOCKS, - MEM_MNGT_MBCOPY_NB_BLOCKS - }; - - memset (memory, 0, sizeof (mem_pool)); - mb_index = 0; - - // LG_TEST - for (pool_index = 0; pool_index <= MEM_MNGT_POOL_ID_COPY; pool_index++) { - init_list (&memory->mem_lists[pool_index], "POOL"); - - for (index = 0; index < pool_sizes[pool_index]; index++) { - //memory->mem_blocks[mb_index + index].previous = NULL; -> done in memset 0 - //memory->mem_blocks[mb_index + index].next = NULL; -> done in memset 0 - switch (pool_index) { - case 0: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool0[index][0]); - break; - - case 1: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool1[index][0]); - break; - - case 2: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool2[index][0]); - break; - - case 3: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool3[index][0]); - break; - - case 4: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool4[index][0]); - break; - - case 5: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool5[index][0]); - break; - - case 6: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool6[index][0]); - break; - - case 7: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool7[index][0]); - break; - - case 8: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool8[index][0]); - break; - - case 9: - memory->mem_blocks[mb_index + index].data = &(memory->mem_pool9[index][0]); - break; - - default: - ; - memory->mem_blocks[mb_index + index].data = NULL; // pool copy - - } - - memory->mem_blocks[mb_index + index].pool_id = pool_index; - add_tail (&memory->mem_blocks[mb_index + index], &memory->mem_lists[pool_index]); - } - - mb_index += pool_sizes[pool_index]; - } - - return 0; -} - -//----------------------------------------------------------------------------- -void * -pool_buffer_clean (void *arg) -{ - //----------------------------------------------------------------------------- -#ifndef NO_THREAD_SAFE - mem_pool *memory = (mem_pool *) arg; - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID0].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID1].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID2].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID3].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID4].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID5].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID6].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID7].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID8].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID9].mutex); - pthread_mutex_destroy (&memory->mem_lists[MEM_MNGT_POOL_ID_COPY].mutex); -#endif - return 0; -} -//----------------------------------------------------------------------------- -void -free_mem_block (mem_block_t * leP, __func__) -{ - //----------------------------------------------------------------------------- - - if (!(leP)) { - msg ("[MEM_MNGT][FREE] WARNING FREE NULL MEM_BLOCK\n"); - return; - } - -#ifdef DEBUG_MEM_MNGT_FREE - msg ("[MEM_MNGT][FREE] free_mem_block() %p pool: %d\n", leP, leP->pool_id, __func__); -#endif -#ifdef DEBUG_MEM_MNGT_ALLOC - check_free_mem_block (leP, __func__); -#endif - - if (leP->pool_id <= MEM_MNGT_POOL_ID_COPY) { - add_tail (leP, &mem->mem_lists[leP->pool_id]); -#ifdef DEBUG_MEM_MNGT_ALLOC - counters[leP->pool_id] -= 1; -#endif - leP = NULL; // this prevent from freeing the block twice - } else { - msg ("[MEM_MNGT][FREE] ERROR free_mem_block() unknown pool_id : %d\n", leP->pool_id, __func__); - } -} - - -//----------------------------------------------------------------------------- -mem_block_t * -get_free_mem_block (uint16_t sizeP, __func__) -{ - //----------------------------------------------------------------------------- - mem_block_t *le = NULL; - int pool_selected; - int size; - - if (sizeP > MEM_MNGT_MB9_BLOCK_SIZE) { - msg ("[MEM_MNGT][ERROR][FATAL] size requested %d out of bounds %d\n",sizeP,MEM_MNGT_MB9_BLOCK_SIZE); - wcdma_handle_error (WCDMA_ERROR_OUT_OF_MEM_BLOCK); - return NULL; - } - - size = sizeP >> 6; - pool_selected = 0; - - while ((size)) { - pool_selected += 1; - size = size >> 1; - } - - // pool is selected according to the size requested, now get a block - // if no block is available pick one in an other pool - do { - if ((le = remove_head (&mem->mem_lists[pool_selected]))) { -#ifdef DEBUG_MEM_MNGT_ALLOC - counters[pool_selected] += 1; -#endif -#ifdef DEBUG_MEM_MNGT_ALLOC_SIZE - msg ("[MEM_MNGT][INFO] ALLOC MEM_BLOCK SIZE %d bytes pool %d\n", sizeP, pool_selected); -#endif - return le; - } - -#ifdef DEBUG_MEM_MNGT_ALLOC - msg ("[MEM_MNGT][ERROR][MINOR] memory pool %d is empty trying next pool alloc count = %d\n", pool_selected, counters[pool_selected]); - display_mem_load (); - check_mem_area (mem); -#endif - } while (pool_selected++ < 9); - - msg ("[MEM_MNGT][ERROR][FATAL] size %d requested out of bounds or memory pools empty\n", sizeP); - wcdma_handle_error (WCDMA_ERROR_OUT_OF_MEM_BLOCK); - return NULL; -}; - -//----------------------------------------------------------------------------- -mem_block_t * -get_free_copy_mem_block (void) -{ - //----------------------------------------------------------------------------- - mem_block_t *le; - - if ((le = remove_head (&mem->mem_lists[MEM_MNGT_POOL_ID_COPY]))) { - return le; - } else { - msg ("[MEM_MNGT][ERROR] POOL COPY IS EMPTY\n"); - display_mem_load (); -#ifdef DEBUG_MEM_MNGT_ALLOC - check_mem_area (mem); - break_point (); -#endif - wcdma_handle_error (WCDMA_ERROR_OUT_OF_MEM_BLOCK); - - return NULL; - } -} - -//----------------------------------------------------------------------------- -mem_block_t * -copy_mem_block (mem_block_t * leP, mem_block_t * destP) -{ - //----------------------------------------------------------------------------- - - if ((destP != NULL) && (leP != NULL) && (destP->pool_id == MEM_MNGT_POOL_ID_COPY)) { - destP->data = leP->data; - } else { - msg ("[MEM_MNGT][COPY] copy_mem_block() pool dest src or dest is NULL\n"); - } - - return destP; -} - -//----------------------------------------------------------------------------- -void -display_mem_load (void) -{ - //----------------------------------------------------------------------------- - - msg ("POOL 0 (%d elements of %d Bytes): \n", MEM_MNGT_MB0_NB_BLOCKS, MEM_MNGT_MB0_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID0]); - msg ("POOL 1 (%d elements of %d Bytes): \n", MEM_MNGT_MB1_NB_BLOCKS, MEM_MNGT_MB1_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID1]); - msg ("POOL 2 (%d elements of %d Bytes): \n", MEM_MNGT_MB2_NB_BLOCKS, MEM_MNGT_MB2_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID2]); - msg ("POOL 3 (%d elements of %d Bytes): \n", MEM_MNGT_MB3_NB_BLOCKS, MEM_MNGT_MB3_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID3]); - msg ("POOL 4 (%d elements of %d Bytes): \n", MEM_MNGT_MB4_NB_BLOCKS, MEM_MNGT_MB4_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID4]); - msg ("POOL 5 (%d elements of %d Bytes): \n", MEM_MNGT_MB5_NB_BLOCKS, MEM_MNGT_MB5_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID5]); - msg ("POOL 6 (%d elements of %d Bytes): \n", MEM_MNGT_MB6_NB_BLOCKS, MEM_MNGT_MB6_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID6]); - msg ("POOL 7 (%d elements of %d Bytes): \n", MEM_MNGT_MB7_NB_BLOCKS, MEM_MNGT_MB7_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID7]); - msg ("POOL 8 (%d elements of %d Bytes): \n", MEM_MNGT_MB8_NB_BLOCKS, MEM_MNGT_MB8_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID8]); - msg ("POOL 9 (%d elements of %d Bytes): \n", MEM_MNGT_MB9_NB_BLOCKS, MEM_MNGT_MB9_BLOCK_SIZE); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID9]); - msg ("POOL C (%d elements): \n", MEM_MNGT_MBCOPY_NB_BLOCKS); - display_list (&mem->mem_lists[MEM_MNGT_POOL_ID_COPY]); -} - -//----------------------------------------------------------------------------- -void -check_mem_area (void *arg) -{ - //----------------------------------------------------------------------------- - int index, mb_index; - mem_pool *memory = (mem_pool *) arg; - - for (index = 0; index < MEM_MNGT_MB0_NB_BLOCKS; index++) { - if ((memory->mem_blocks[index].data != &(memory->mem_pool0[index][0])) && (memory->mem_blocks[index].pool_id != MEM_MNGT_POOL_ID0)) { - msg ("[MEM] ERROR POOL0 block index %d\n", index); - break_point (); - } - } - - mb_index = MEM_MNGT_MB0_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB1_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool1[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID1)) { - msg ("[MEM] ERROR POOL1 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB1_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB2_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool2[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID2)) { - msg ("[MEM] ERROR POOL2 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB2_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB3_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool3[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID3)) { - msg ("[MEM] ERROR POOL3 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB3_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB4_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool4[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID4)) { - msg ("[MEM] ERROR POOL4 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB4_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB5_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool5[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID5)) { - msg ("[MEM] ERROR POOL5 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB5_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB6_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool6[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID6)) { - msg ("[MEM] ERROR POOL6 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB6_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB7_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool7[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID7)) { - msg ("[MEM] ERROR POOL7 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB7_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB8_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool8[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID8)) { - msg ("[MEM] ERROR POOL8 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB8_NB_BLOCKS; - - for (index = 0; index < MEM_MNGT_MB9_NB_BLOCKS; index++) { - if ((memory->mem_blocks[mb_index + index].data != &(memory->mem_pool9[index][0])) && (memory->mem_blocks[mb_index + index].pool_id != MEM_MNGT_POOL_ID9)) { - msg ("[MEM] ERROR POOL9 block index %d\n", index); - break_point (); - } - } - - mb_index += MEM_MNGT_MB9_NB_BLOCKS; - - for (index = mb_index; index < MEM_MNGT_NB_ELEMENTS; index++) { - if ((memory->mem_blocks[index].data != NULL) && (memory->mem_blocks[index].pool_id != MEM_MNGT_POOL_ID_COPY)) { - msg ("[MEM] ERROR POOL COPY block index %d\n", index); - break_point (); - } - } -} - -//----------------------------------------------------------------------------- -void -check_free_mem_block (mem_block_t * leP, __func__) -{ - //----------------------------------------------------------------------------- - int block_index; - - if ((leP >= &mem->mem_blocks[0]) && (leP <= &mem->mem_blocks[MEM_MNGT_NB_ELEMENTS])) { - block_index = ((uint32_t) leP - (uint32_t) (&mem->mem_blocks[0])) / sizeof (mem_block_t); - - if (block_index < MEM_MNGT_MB0_NB_BLOCKS) { - if (((uint32_t) (leP->data) != (uint32_t) (&(mem->mem_pool0[block_index][0]))) && (leP->pool_id != MEM_MNGT_POOL_ID0)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < (MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS)) { - if ((leP->data != &(mem->mem_pool1[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID1)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool2[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID2)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool3[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID3)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool4[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID4)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS + - MEM_MNGT_MB5_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool5[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID5)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < - MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS + MEM_MNGT_MB5_NB_BLOCKS + - MEM_MNGT_MB6_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool6[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID6)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < - MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS + MEM_MNGT_MB5_NB_BLOCKS + - MEM_MNGT_MB6_NB_BLOCKS + - MEM_MNGT_MB7_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool7[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID7)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < - MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS + MEM_MNGT_MB5_NB_BLOCKS + - MEM_MNGT_MB6_NB_BLOCKS + - MEM_MNGT_MB7_NB_BLOCKS + MEM_MNGT_MB8_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool8[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID8)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } else if (block_index < - MEM_MNGT_MB0_NB_BLOCKS + MEM_MNGT_MB1_NB_BLOCKS + MEM_MNGT_MB2_NB_BLOCKS + MEM_MNGT_MB3_NB_BLOCKS + MEM_MNGT_MB4_NB_BLOCKS + MEM_MNGT_MB5_NB_BLOCKS + - MEM_MNGT_MB6_NB_BLOCKS + - MEM_MNGT_MB7_NB_BLOCKS + MEM_MNGT_MB8_NB_BLOCKS + MEM_MNGT_MB9_NB_BLOCKS) { - if ((leP->data != &(mem->mem_pool9[block_index][0])) && (leP->pool_id != MEM_MNGT_POOL_ID9)) { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } - } - - } else { - msg ("[MEM][ERROR][FATAL] free mem block is corrupted\n"); - } -} - -//----------------------------------------------------------------------------- -void -break_point (void) -{ - //----------------------------------------------------------------------------- - int break_var; - - msg ("[BREAK_POINT]\n"); - break_var = 1; -} diff --git a/openair2/UTIL/MEM/mem_mngt_proto_extern.h b/openair2/UTIL/MEM/mem_mngt_proto_extern.h deleted file mode 100644 index 4690bba42e..0000000000 --- a/openair2/UTIL/MEM/mem_mngt_proto_extern.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - diff --git a/openair2/UTIL/MEM/mem_pool.h b/openair2/UTIL/MEM/mem_pool.h deleted file mode 100644 index cc0face78c..0000000000 --- a/openair2/UTIL/MEM/mem_pool.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*************************************************************************** - mem_pool.h - description - ------------------- - AUTHOR : Lionel GAUTHIER - COMPANY : EURECOM - EMAIL : Lionel.Gauthier@eurecom.fr - - - ***************************************************************************/ -#ifndef __MEM_POOL_H__ -# define __MEM_POOL_H__ - -# include "list.h" -# include "mem_block.h" - - -#endif diff --git a/openair2/UTIL/OCG/OCG_if.h b/openair2/UTIL/OCG/OCG_if.h index c515d9746d..cc55b56f36 100644 --- a/openair2/UTIL/OCG/OCG_if.h +++ b/openair2/UTIL/OCG/OCG_if.h @@ -30,8 +30,8 @@ * \warning */ -#ifndef __CONFIGEN_IF_H__ -#define __CONFIG_IF_H__ +#ifndef __UTIL_OCG_OCG_IF__H__ +#define __UTIL_OCG_OCG_IF__H__ #ifdef __cplusplus extern "C" { diff --git a/openair2/UTIL/OPT/mac_pcap.h b/openair2/UTIL/OPT/mac_pcap.h index 48b31bb3c0..3141d17d59 100644 --- a/openair2/UTIL/OPT/mac_pcap.h +++ b/openair2/UTIL/OPT/mac_pcap.h @@ -1,3 +1,6 @@ +#ifndef __UTIL_OPT_MAC_PCAP__H__ +#define __UTIL_OPT_MAC_PCAP__H__ + #include #include #include @@ -42,4 +45,4 @@ typedef struct MAC_Context_Info_t { unsigned int subframesSinceCaptureStart; } MAC_Context_Info_t; - +#endif diff --git a/openair2/UTIL/OPT/opt.h b/openair2/UTIL/OPT/opt.h index 86f1a045d8..6861e09cb1 100644 --- a/openair2/UTIL/OPT/opt.h +++ b/openair2/UTIL/OPT/opt.h @@ -88,16 +88,12 @@ typedef guint8 gboolean; { .s5= {NULL }} , \ } -#ifdef OCP_FRAMEWORK -#include -#else typedef enum trace_mode_e { OPT_WIRESHARK, OPT_PCAP, OPT_TSHARK, OPT_NONE } trace_mode_t; -#endif typedef enum radio_type_e { RADIO_TYPE_FDD = 1, diff --git a/openair2/UTIL/OPT/packet-mac-lte.h b/openair2/UTIL/OPT/packet-mac-lte.h index 4dfbe7912e..2d36e02df4 100644 --- a/openair2/UTIL/OPT/packet-mac-lte.h +++ b/openair2/UTIL/OPT/packet-mac-lte.h @@ -22,6 +22,8 @@ modified to be used in OpenAir to create the LTE MAC/RLC encapsulated in UDP as per Wireshark feature */ +#ifndef __UTIL_OPT_PACKET_MAC_LTE__H__ +#define __UTIL_OPT_PACKET_MAC_LTE__H__ #include "ws_symbol_export.h" @@ -376,3 +378,5 @@ typedef enum { * vi: set shiftwidth=4 tabstop=8 expandtab: * :indentSize=4:tabSize=8:noTabs=true: */ + +#endif diff --git a/openair2/UTIL/OPT/probe.c b/openair2/UTIL/OPT/probe.c index f8cd0ef64c..8c6a74e042 100644 --- a/openair2/UTIL/OPT/probe.c +++ b/openair2/UTIL/OPT/probe.c @@ -99,8 +99,8 @@ int opt_enabled=0; //static unsigned char g_PDUBuffer[1600]; //static unsigned int g_PDUOffset; -static char *in_ip; -static char *in_path; +static char in_ip[128]={0}; +static char in_path[128]={0}; FILE *file_fd = NULL; pcap_hdr_t file_header = { 0xa1b2c3d4, /* magic number */ @@ -447,9 +447,11 @@ int init_opt(void) char *in_type=NULL; paramdef_t opt_params[] = OPT_PARAMS_DESC ; checkedparam_t opt_checkParams[] = OPTPARAMS_CHECK_DESC; - uint16_t in_port; - config_set_checkfunctions(opt_params, opt_checkParams, sizeof(opt_params)/sizeof(paramdef_t)); - config_get(opt_params, sizeof(opt_params)/sizeof(paramdef_t), OPT_CONFIGPREFIX); + uint16_t in_port=0; + config_set_checkfunctions(opt_params, opt_checkParams, + sizeof(opt_params)/sizeof(paramdef_t)); + config_get( opt_params,sizeof(opt_params)/sizeof(paramdef_t),OPT_CONFIGPREFIX); + subframesSinceCaptureStart = 0; int tmptype = config_get_processedint( &(opt_params[OPTTYPE_IDX])); diff --git a/openair2/UTIL/OSA/osa_defs.h b/openair2/UTIL/OSA/osa_defs.h index 4812d82d91..3df350541f 100644 --- a/openair2/UTIL/OSA/osa_defs.h +++ b/openair2/UTIL/OSA/osa_defs.h @@ -29,8 +29,8 @@ * @ingroup security */ -#ifndef SECU_DEFS_H_ -#define SECU_DEFS_H_ +#ifndef __UTIL_OSA_OSA_DEFS__H__ +#define __UTIL_OSA_OSA_DEFS__H__ #define EIA0_ALG_ID 0x00 #define EIA1_128_ALG_ID 0x01 @@ -115,4 +115,4 @@ int stream_decrypt(uint8_t algorithm, stream_cipher_t *stream_cipher, uint8_t ** int stream_check_integrity(uint8_t algorithm, stream_cipher_t *stream_cipher, uint8_t *expected); #undef SECU_DEBUG -#endif /* SECU_DEFS_H_ */ +#endif /* __UTIL_OSA_OSA_DEFS__H__ */ diff --git a/openair2/UTIL/OTG/traffic_config.h b/openair2/UTIL/OTG/traffic_config.h index 2f47682706..c0a64a3465 100644 --- a/openair2/UTIL/OTG/traffic_config.h +++ b/openair2/UTIL/OTG/traffic_config.h @@ -19,6 +19,9 @@ * contact@openairinterface.org */ +#ifndef __UTIL_OTG_TRAFFIC_CONFIG__H__ +#define __UTIL_OTG_TRAFFIC_CONFIG__H__ + //IDT DISTRIBUTION PARAMETERS #define IDT_DIST GAUSSIAN #define IDT_MIN 2 @@ -40,3 +43,5 @@ //SOCKET MODE #define DST_PORT 1234; #define DST_IP "127.0.0.1" + +#endif diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index 47a3475063..0aeabce0d2 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1691,11 +1691,11 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted // with values coming from RRC. - uint16_t nRencryptionAlgorithms = 0; - uint16_t nRintegrityProtectionAlgorithms = 0; - uint8_t SgNBSecurityKey[32] = { 0 }; - int uEaggregateMaximumBitRateDownlink = 100000000; - int uEaggregateMaximumBitRateUplink = 100000000; + //uint16_t nRencryptionAlgorithms = 0; + //uint16_t nRintegrityProtectionAlgorithms = 0; + //uint8_t SgNBSecurityKey[32] = { 0 }; + //int uEaggregateMaximumBitRateDownlink = 100000000; + //int uEaggregateMaximumBitRateUplink = 100000000; int e_rabs_admitted_tobeadded = 1; int e_RAB_ID = 1; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index b7a9b70596..afaae1756d 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1772,8 +1772,8 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer, true); X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; - - if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s + //X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; + if (container->size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); @@ -1943,7 +1943,6 @@ int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; MessageDef *msg; - int ue_id; DevAssert (pdu != NULL); x2SgNBReconfigurationComplete = &pdu->choice.initiatingMessage.value.choice.SgNBReconfigurationComplete; diff --git a/openair2/X2AP/x2ap_eNB_management_procedures.h b/openair2/X2AP/x2ap_eNB_management_procedures.h index c5217341c5..7082f5ac95 100644 --- a/openair2/X2AP/x2ap_eNB_management_procedures.h +++ b/openair2/X2AP/x2ap_eNB_management_procedures.h @@ -26,8 +26,8 @@ * \version 1.0 */ -#ifndef X2AP_ENB_MANAGEMENT_PROCEDURES_H_ -#define X2AP_ENB_MANAGEMENT_PROCEDURES_H +#ifndef __X2AP_ENB_MANAGEMENT_PROCEDURES__H__ +#define __X2AP_ENB_MANAGEMENT_PROCEDURES__H__ void x2ap_eNB_prepare_internal_data(void); @@ -51,4 +51,4 @@ struct x2ap_eNB_data_s *x2ap_get_eNB(x2ap_eNB_instance_t *instance_p, int32_t assoc_id, uint16_t cnx_id); -#endif /* X2AP_ENB_MANAGEMENT_PROCEDURES_H_ */ +#endif /* __X2AP_ENB_MANAGEMENT_PROCEDURES__H__ */ diff --git a/openair3/M3AP/m3ap_MCE_generate_messages.h b/openair3/M3AP/m3ap_MCE_generate_messages.h index 0884e8216e..1a5733acc3 100644 --- a/openair3/M3AP/m3ap_MCE_generate_messages.h +++ b/openair3/M3AP/m3ap_MCE_generate_messages.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M2AP_ENB_GENERATE_MESSAGES_H_ -#define M2AP_ENB_GENERATE_MESSAGES_H_ +#ifndef __M3AP_MCE_GENERATE_MESSAGES__H__ +#define __M3AP_MCE_GENERATE_MESSAGES__H__ #include "m2ap_eNB_defs.h" #include "m2ap_common.h" @@ -37,27 +37,8 @@ int m2ap_eNB_generate_m2_setup_request(m2ap_eNB_instance_t *instance_p, int m2ap_MCE_generate_m2_setup_response(m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p); -/*int m2ap_MCE_generate_m2_setup_failure(instance_t instance, - uint32_t assoc_id, - M2AP_Cause_PR cause_type, - long cause_value, - long time_to_wait);*/ - int m2ap_eNB_set_cause (M2AP_Cause_t * cause_p, M2AP_Cause_PR cause_type, long cause_value); -//int m2ap_eNB_generate_m2_handover_request (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p, -// m2ap_handover_req_t *m2ap_handover_req, int ue_id); -// -//int m2ap_eNB_generate_m2_handover_request_ack (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p, -// m2ap_handover_req_ack_t *m2ap_handover_req_ack); -// -//int m2ap_eNB_generate_m2_ue_context_release (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p, -// m2ap_ue_context_release_t *m2ap_ue_context_release); -// -//int m2ap_eNB_generate_m2_handover_cancel (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p, -// int m2_ue_id, -// m2ap_handover_cancel_cause_t cause); - -#endif /* M2AP_ENB_GENERATE_MESSAGES_H_ */ +#endif /* __M3AP_MCE_GENERATE_MESSAGES__H__ */ diff --git a/openair3/M3AP/m3ap_MCE_handler.h b/openair3/M3AP/m3ap_MCE_handler.h index ce4997e80d..09eca351b6 100644 --- a/openair3/M3AP/m3ap_MCE_handler.h +++ b/openair3/M3AP/m3ap_MCE_handler.h @@ -19,15 +19,15 @@ * contact@openairinterface.org */ -/*! \file m2ap_handler.h - * \brief m2ap handler procedures for eNB +/*! \file m3ap_handler.h + * \brief m3ap handler procedures for eNB * \author Javier Morgade * \date 2019 * \version 0.1 */ -#ifndef M2AP_MCE_HANDLERS_H_ -#define M2AP_MCE_HANDLERS_H_ +#ifndef __M3AP_MCE_HANDLER__H__ +#define __M3AP_MCE_HANDLER__H__ #include "m2ap_MCE_defs.h" @@ -40,4 +40,4 @@ int m3ap_MCE_handle_message(instance_t instance, uint32_t assoc_id, int32_t stre const uint8_t * const data, const uint32_t data_length); -#endif /* M2AP_MCE_HANDLERS_H_ */ +#endif /* __M3AP_MCE_HANDLER__H__ */ diff --git a/openair3/M3AP/m3ap_MCE_management_procedures.h b/openair3/M3AP/m3ap_MCE_management_procedures.h index 2d18df8c26..27e8c928a0 100644 --- a/openair3/M3AP/m3ap_MCE_management_procedures.h +++ b/openair3/M3AP/m3ap_MCE_management_procedures.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M3AP_MCE_MANAGEMENT_PROCEDURES_H_ -#define M3AP_MCE_MANAGEMENT_PROCEDURES_H +#ifndef __M3AP_MCE_MANAGEMENT_PROCEDURES__H__ +#define __M3AP_MCE_MANAGEMENT_PROCEDURES__H__ void m3ap_MCE_prepare_internal_data(void); @@ -50,4 +50,4 @@ struct m3ap_MCE_data_s *m3ap_get_MCE(m3ap_MCE_instance_t *instance_p, int32_t assoc_id, uint16_t cnx_id); -#endif /* M3AP_MCE_MANAGEMENT_PROCEDURES_H_ */ +#endif /* __M3AP_MCE_MANAGEMENT_PROCEDURES__H__ */ diff --git a/openair3/M3AP/m3ap_MME_generate_messages.h b/openair3/M3AP/m3ap_MME_generate_messages.h index 1632dc807a..146f58825a 100644 --- a/openair3/M3AP/m3ap_MME_generate_messages.h +++ b/openair3/M3AP/m3ap_MME_generate_messages.h @@ -19,15 +19,15 @@ * contact@openairinterface.org */ -/*! \file m2ap_MCE_generate_messages.h - * \brief m2ap procedures for MCE +/*! \file m3ap_MCE_generate_messages.h + * \brief m3ap procedures for MCE * \author Javier Morgade * \date 2019 * \version 0.1 */ -#ifndef M2AP_MCE_GENERATE_MESSAGES_H_ -#define M2AP_MCE_GENERATE_MESSAGES_H_ +#ifndef M3AP_MCE_GENERATE_MESSAGES_H_ +#define M3AP_MCE_GENERATE_MESSAGES_H_ #include "m2ap_MCE_defs.h" #include "m2ap_common.h" diff --git a/openair3/M3AP/m3ap_MME_management_procedures.h b/openair3/M3AP/m3ap_MME_management_procedures.h index e966ee1f17..b21189b915 100644 --- a/openair3/M3AP/m3ap_MME_management_procedures.h +++ b/openair3/M3AP/m3ap_MME_management_procedures.h @@ -26,8 +26,8 @@ * \version 0.1 */ -#ifndef M3AP_MME_MANAGEMENT_PROCEDURES_H_ -#define M3AP_MME_MANAGEMENT_PROCEDURES_H +#ifndef __M3AP_MME_MANAGEMENT_PROCEDURES__H__ +#define __M3AP_MME_MANAGEMENT_PROCEDURES__H__ void m3ap_MME_prepare_internal_data(void); @@ -51,4 +51,4 @@ struct m3ap_MME_data_s *m3ap_get_MME(m3ap_MME_instance_t *instance_p, int32_t assoc_id, uint16_t cnx_id); -#endif /* M3AP_MME_MANAGEMENT_PROCEDURES_H_ */ +#endif /* __M3AP_MME_MANAGEMENT_PROCEDURES__H__ */ diff --git a/openair3/MME_APP/enb_paramdef_mme.h b/openair3/MME_APP/enb_paramdef_mme.h index 3d65036553..127c1855e7 100644 --- a/openair3/MME_APP/enb_paramdef_mme.h +++ b/openair3/MME_APP/enb_paramdef_mme.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __MME_APP_ENB_PARAMDEF_MME__H__ +#define __MME_APP_ENB_PARAMDEF_MME__H__ + #include "common/config/config_paramdesc.h" #include "RRC_paramsvalues.h" @@ -172,3 +175,4 @@ typedef struct ccparams_MME_s { { .s5= {NULL }} \ } +#endif diff --git a/openair3/MME_APP/mme_config.h b/openair3/MME_APP/mme_config.h index 4371ad55f6..2eb0a66e85 100644 --- a/openair3/MME_APP/mme_config.h +++ b/openair3/MME_APP/mme_config.h @@ -26,8 +26,9 @@ EMAIL : javier.morgade@ieee.org */ -#ifndef MME_CONFIG_H_ -#define MME_CONFIG_H_ +#ifndef __MME_APP_MME_CONFIG__H__ +#define __MME_APP_MME_CONFIG__H__ + #include #include #include @@ -48,5 +49,5 @@ int RCconfig_MME(void); -#endif /* MME_CONFIG_H_ */ +#endif /* __MME_APP_MME_CONFIG__H__ */ /** @} */ diff --git a/openair3/NAS/COMMON/API/NETWORK/as_message.h b/openair3/NAS/COMMON/API/NETWORK/as_message.h deleted file mode 100644 index 30810a325e..0000000000 --- a/openair3/NAS/COMMON/API/NETWORK/as_message.h +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Copyright (c) 2015, EURECOM (www.eurecom.fr) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * The views and conclusions contained in the software and documentation are those - * of the authors and should not be interpreted as representing official policies, - * either expressed or implied, of the FreeBSD Project. - */ - - -/***************************************************************************** - -Source as_message.h - -Version 0.1 - -Date 2012/10/18 - -Product NAS stack - -Subsystem Application Programming Interface - -Author Frederic Maurel - -Description Defines the messages supported by the Access Stratum sublayer - protocol (usually RRC and S1AP for E-UTRAN) and functions used - to encode and decode - -*****************************************************************************/ -#ifndef __AS_MESSAGE_H__ -#define __AS_MESSAGE_H__ - -#include "commonDef.h" -#include "networkDef.h" - -/****************************************************************************/ -/********************* G L O B A L C O N S T A N T S *******************/ -/****************************************************************************/ - -/* - * -------------------------------------------------------------------------- - * Access Stratum message types - * -------------------------------------------------------------------------- - */ -#define AS_REQUEST 0x0100 -#define AS_RESPONSE 0x0200 -#define AS_INDICATION 0x0400 -#define AS_CONFIRM 0x0800 - -/* - * -------------------------------------------------------------------------- - * Access Stratum message identifiers - * -------------------------------------------------------------------------- - */ - -/* Broadcast information */ -#define AS_BROADCAST_INFO 0x01 -#define AS_BROADCAST_INFO_IND (AS_BROADCAST_INFO | AS_INDICATION) - -/* Cell information relevant for cell selection processing */ -#define AS_CELL_INFO 0x02 -#define AS_CELL_INFO_REQ (AS_CELL_INFO | AS_REQUEST) -#define AS_CELL_INFO_CNF (AS_CELL_INFO | AS_CONFIRM) -#define AS_CELL_INFO_IND (AS_CELL_INFO | AS_INDICATION) - -/* Paging information */ -#define AS_PAGING 0x03 -#define AS_PAGING_REQ (AS_PAGING | AS_REQUEST) -#define AS_PAGING_IND (AS_PAGING | AS_INDICATION) - -/* NAS signalling connection establishment */ -#define AS_NAS_ESTABLISH 0x04 -#define AS_NAS_ESTABLISH_REQ (AS_NAS_ESTABLISH | AS_REQUEST) -#define AS_NAS_ESTABLISH_IND (AS_NAS_ESTABLISH | AS_INDICATION) -#define AS_NAS_ESTABLISH_RSP (AS_NAS_ESTABLISH | AS_RESPONSE) -#define AS_NAS_ESTABLISH_CNF (AS_NAS_ESTABLISH | AS_CONFIRM) - -/* NAS signalling connection release */ -#define AS_NAS_RELEASE 0x05 -#define AS_NAS_RELEASE_REQ (AS_NAS_RELEASE | AS_REQUEST) -#define AS_NAS_RELEASE_IND (AS_NAS_RELEASE | AS_INDICATION) - -/* Uplink information transfer */ -#define AS_UL_INFO_TRANSFER 0x06 -#define AS_UL_INFO_TRANSFER_REQ (AS_UL_INFO_TRANSFER | AS_REQUEST) -#define AS_UL_INFO_TRANSFER_CNF (AS_UL_INFO_TRANSFER | AS_CONFIRM) -#define AS_UL_INFO_TRANSFER_IND (AS_UL_INFO_TRANSFER | AS_INDICATION) - -/* Downlink information transfer */ -#define AS_DL_INFO_TRANSFER 0x07 -#define AS_DL_INFO_TRANSFER_REQ (AS_DL_INFO_TRANSFER | AS_REQUEST) -#define AS_DL_INFO_TRANSFER_CNF (AS_DL_INFO_TRANSFER | AS_CONFIRM) -#define AS_DL_INFO_TRANSFER_IND (AS_DL_INFO_TRANSFER | AS_INDICATION) - -/* Radio Access Bearer establishment */ -#define AS_RAB_ESTABLISH 0x08 -#define AS_RAB_ESTABLISH_REQ (AS_RAB_ESTABLISH | AS_REQUEST) -#define AS_RAB_ESTABLISH_IND (AS_RAB_ESTABLISH | AS_INDICATION) -#define AS_RAB_ESTABLISH_RSP (AS_RAB_ESTABLISH | AS_RESPONSE) -#define AS_RAB_ESTABLISH_CNF (AS_RAB_ESTABLISH | AS_CONFIRM) - -/* Radio Access Bearer release */ -#define AS_RAB_RELEASE 0x09 -#define AS_RAB_RELEASE_REQ (AS_RAB_RELEASE | AS_REQUEST) -#define AS_RAB_RELEASE_IND (AS_RAB_RELEASE | AS_INDICATION) - -/* NAS Cause */ -#define EPS_SERVICES_AND_NON_EPS_SERVICES_NOT_ALLOWED (8) -#define EPS_SERVICES_NOT_ALLOWED (7) -#define PLMN_NOT_ALLOWED (11) -#define TRACKING_AREA_NOT_ALLOWED (12) -#define ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA (13) -#define EPS_SERVICES_NOT_ALLOWED_IN_THIS_PLMN (14) -#define NO_SUITABLE_CELLS_IN_TRACKING_AREA (15) -#define NETWORK_FAILURE (17) -#define ESM_FAILURE (19) - -typedef enum nas_cause_s { - NAS_CAUSE_EPS_SERVICES_AND_NON_EPS_SERVICES_NOT_ALLOWED = EPS_SERVICES_AND_NON_EPS_SERVICES_NOT_ALLOWED, - NAS_CAUSE_EPS_SERVICES_NOT_ALLOWED = EPS_SERVICES_NOT_ALLOWED, - NAS_CAUSE_PLMN_NOT_ALLOWED = PLMN_NOT_ALLOWED, - NAS_CAUSE_TRACKING_AREA_NOT_ALLOWED = TRACKING_AREA_NOT_ALLOWED, - NAS_CAUSE_ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA = ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA, - NAS_CAUSE_EPS_SERVICES_NOT_ALLOWED_IN_THIS_PLMN = EPS_SERVICES_NOT_ALLOWED_IN_THIS_PLMN, - NAS_CAUSE_NO_SUITABLE_CELLS_IN_TRACKING_AREA = NO_SUITABLE_CELLS_IN_TRACKING_AREA, - NAS_CAUSE_NETWORK_FAILURE = NETWORK_FAILURE, - NAS_CAUSE_ESM_FAILURE = ESM_FAILURE -} nas_cause_t; - -/* - * -------------------------------------------------------------------------- - * Access Stratum message global parameters - * -------------------------------------------------------------------------- - */ - -/* Error code */ -typedef enum nas_error_code_s { - AS_SUCCESS = 1, /* Success code, transaction is going on */ - AS_TERMINATED_NAS, /* Transaction terminated by NAS */ - AS_TERMINATED_AS, /* Transaction terminated by AS */ - AS_FAILURE /* Failure code */ -} nas_error_code_t; - -/* Core network domain */ -typedef enum core_network_s { - AS_PS = 1, /* Packet-Switched */ - AS_CS /* Circuit-Switched */ -} core_network_t; - -/* SAE Temporary Mobile Subscriber Identity */ -typedef struct as_stmsi_s { - uint8_t MMEcode; /* MME code that allocated the GUTI */ - uint32_t m_tmsi; /* M-Temporary Mobile Subscriber Identity */ -} as_stmsi_t; - -/* Dedicated NAS information */ -typedef struct as_nas_info_s { - uint32_t length; /* Length of the NAS information data */ - Byte_t* data; /* Dedicated NAS information data container */ -} as_nas_info_t; - -/* Radio Access Bearer identity */ -typedef uint8_t as_rab_id_t; - -/****************************************************************************/ -/************************ G L O B A L T Y P E S ************************/ -/****************************************************************************/ - -/* - * -------------------------------------------------------------------------- - * Broadcast information - * -------------------------------------------------------------------------- - */ - -/* - * AS->NAS - Broadcast information indication - * AS may asynchronously report to NAS available PLMNs within specific - * location area - */ -typedef struct broadcast_info_ind_s { -#define PLMN_LIST_MAX_SIZE 6 - PLMN_LIST_T(PLMN_LIST_MAX_SIZE) plmnIDs; /* List of PLMN identifiers */ - ci_t cellID; /* Identity of the cell serving the listed PLMNs */ - tac_t tac; /* Code of the tracking area the cell belongs to */ -} broadcast_info_ind_t; - -/* - * -------------------------------------------------------------------------- - * Cell information relevant for cell selection processing - * -------------------------------------------------------------------------- - */ - -/* Radio access technologies supported by the network */ -#define AS_GSM (1 << NET_ACCESS_GSM) -#define AS_COMPACT (1 << NET_ACCESS_COMPACT) -#define AS_UTRAN (1 << NET_ACCESS_UTRAN) -#define AS_EGPRS (1 << NET_ACCESS_EGPRS) -#define AS_HSDPA (1 << NET_ACCESS_HSDPA) -#define AS_HSUPA (1 << NET_ACCESS_HSUPA) -#define AS_HSDUPA (1 << NET_ACCESS_HSDUPA) -#define AS_EUTRAN (1 << NET_ACCESS_EUTRAN) - -/* - * NAS->AS - Cell Information request - * NAS request AS to search for a suitable cell belonging to the selected - * PLMN to camp on. - */ -typedef struct cell_info_req_s { - plmn_t plmnID; /* Selected PLMN identity */ - Byte_t rat; /* Bitmap - set of radio access technologies */ -} cell_info_req_t; - -/* - * AS->NAS - Cell Information confirm - * AS search for a suitable cell and respond to NAS. If found, the cell - * is selected to camp on. - */ -typedef struct cell_info_cnf_s { - uint8_t errCode; /* Error code */ - ci_t cellID; /* Identity of the cell serving the selected PLMN */ - tac_t tac; /* Code of the tracking area the cell belongs to */ - AcT_t rat; /* Radio access technology supported by the cell */ - uint8_t rsrq; /* Reference signal received quality */ - uint8_t rsrp; /* Reference signal received power */ -} cell_info_cnf_t; - -/* - * AS->NAS - Cell Information indication - * AS may change cell selection if a more suitable cell is found. - */ -typedef struct cell_info_ind_s { - ci_t cellID; /* Identity of the new serving cell */ - tac_t tac; /* Code of the tracking area the cell belongs to */ -} cell_info_ind_t; - -/* - * -------------------------------------------------------------------------- - * Paging information - * -------------------------------------------------------------------------- - */ - -/* Paging cause */ -typedef enum paging_cause_s { - AS_CONNECTION_ESTABLISH, /* Establish NAS signalling connection */ - AS_EPS_ATTACH, /* Perform local detach and initiate EPS - * attach procedure */ - AS_CS_FALLBACK /* Inititate CS fallback procedure */ -} paging_cause_t; - -/* - * NAS->AS - Paging Information request - * NAS requests the AS that NAS signalling messages or user data is pending - * to be sent. - */ -typedef struct paging_req_s { - as_stmsi_t s_tmsi; /* UE identity */ - uint8_t CN_domain; /* Core network domain */ -} paging_req_t; - -/* - * AS->NAS - Paging Information indication - * AS reports to the NAS that appropriate procedure has to be initiated. - */ -typedef struct paging_ind_s { - paging_cause_t cause; /* Paging cause */ -} paging_ind_t; - -/* - * -------------------------------------------------------------------------- - * NAS signalling connection establishment - * -------------------------------------------------------------------------- - */ - -/* Cause of RRC connection establishment */ -typedef enum as_cause_s { - AS_CAUSE_UNKNOWN = 0, - AS_CAUSE_EMERGENCY = NET_ESTABLISH_CAUSE_EMERGENCY, - AS_CAUSE_HIGH_PRIO = NET_ESTABLISH_CAUSE_HIGH_PRIO, - AS_CAUSE_MT_ACCESS = NET_ESTABLISH_CAUSE_MT_ACCESS, - AS_CAUSE_MO_SIGNAL = NET_ESTABLISH_CAUSE_MO_SIGNAL, - AS_CAUSE_MO_DATA = NET_ESTABLISH_CAUSE_MO_DATA, - AS_CAUSE_V1020 = NET_ESTABLISH_CAUSE_V1020 -} as_cause_t; - -/* Type of the call associated to the RRC connection establishment */ -typedef enum as_call_type_s { - AS_TYPE_ORIGINATING_SIGNAL = NET_ESTABLISH_TYPE_ORIGINATING_SIGNAL, - AS_TYPE_EMERGENCY_CALLS = NET_ESTABLISH_TYPE_EMERGENCY_CALLS, - AS_TYPE_ORIGINATING_CALLS = NET_ESTABLISH_TYPE_ORIGINATING_CALLS, - AS_TYPE_TERMINATING_CALLS = NET_ESTABLISH_TYPE_TERMINATING_CALLS, - AS_TYPE_MO_CS_FALLBACK = NET_ESTABLISH_TYPE_MO_CS_FALLBACK -} as_call_type_t; - -/* - * NAS->AS - NAS signalling connection establishment request - * NAS requests the AS to perform the RRC connection establishment procedure - * to transfer initial NAS message to the network while UE is in IDLE mode. - */ -typedef struct nas_establish_req_s { - as_cause_t cause; /* RRC connection establishment cause */ - as_call_type_t type; /* RRC associated call type */ - as_stmsi_t s_tmsi; /* UE identity */ - plmn_t plmnID; /* Selected PLMN identity */ - as_nas_info_t initialNasMsg; /* Initial NAS message to transfer */ -} nas_establish_req_t; - -/* - * AS->NAS - NAS signalling connection establishment indication - * AS transfers the initial NAS message to the NAS. - */ -typedef struct nas_establish_ind_s { - uint32_t UEid; /* UE lower layer identifier */ - tac_t tac; /* Code of the tracking area the initiating - * UE belongs to */ - as_cause_t asCause; /* Establishment cause */ - as_nas_info_t initialNasMsg; /* Initial NAS message to transfer */ -} nas_establish_ind_t; - -/* - * NAS->AS - NAS signalling connection establishment response - * NAS responds to the AS that initial answer message has to be provided to - * the UE. - */ -typedef struct nas_establish_rsp_s { - uint32_t UEid; /* UE lower layer identifier */ - as_stmsi_t s_tmsi; /* UE identity */ - nas_error_code_t errCode; /* Transaction status */ - as_nas_info_t nasMsg; /* NAS message to transfer */ - uint32_t nas_ul_count; /* UL NAS COUNT */ - uint16_t selected_encryption_algorithm; - uint16_t selected_integrity_algorithm; -} nas_establish_rsp_t; - -/* - * AS->NAS - NAS signalling connection establishment confirm - * AS transfers the initial answer message to the NAS. - */ -typedef struct nas_establish_cnf_s { - uint32_t UEid; /* UE lower layer identifier */ - nas_error_code_t errCode; /* Transaction status */ - as_nas_info_t nasMsg; /* NAS message to transfer */ - uint32_t ul_nas_count; - uint16_t selected_encryption_algorithm; - uint16_t selected_integrity_algorithm; -} nas_establish_cnf_t; - -/* - * -------------------------------------------------------------------------- - * NAS signalling connection release - * -------------------------------------------------------------------------- - */ - -/* Release cause */ -typedef enum release_cause_s { - AS_AUTHENTICATION_FAILURE = 1, /* Authentication procedure failed */ - AS_DETACH /* Detach requested */ -} release_cause_t; - -/* - * NAS->AS - NAS signalling connection release request - * NAS requests the termination of the connection with the UE. - */ -typedef struct nas_release_req_s { - uint32_t UEid; /* UE lower layer identifier */ - as_stmsi_t s_tmsi; /* UE identity */ - release_cause_t cause; /* Release cause */ -} nas_release_req_t; - -/* - * AS->NAS - NAS signalling connection release indication - * AS reports that connection has been terminated by the network. - */ -typedef struct nas_release_ind_s { - release_cause_t cause; /* Release cause */ -} nas_release_ind_t; - -/* - * -------------------------------------------------------------------------- - * NAS information transfer - * -------------------------------------------------------------------------- - */ - -/* - * NAS->AS - Uplink data transfer request - * NAS requests the AS to transfer uplink information to the NAS that - * operates at the network side. - */ -typedef struct ul_info_transfer_req_s { - uint32_t UEid; /* UE lower layer identifier */ - as_stmsi_t s_tmsi; /* UE identity */ - as_nas_info_t nasMsg; /* Uplink NAS message */ -} ul_info_transfer_req_t; - -/* - * AS->NAS - Uplink data transfer confirm - * AS immediately notifies the NAS whether uplink information has been - * successfully sent to the network or not. - */ -typedef struct ul_info_transfer_cnf_s { - uint32_t UEid; /* UE lower layer identifier */ - nas_error_code_t errCode; /* Transaction status */ -} ul_info_transfer_cnf_t; - -/* - * AS->NAS - Uplink data transfer indication - * AS delivers the uplink information message to the NAS that operates - * at the network side. - */ -typedef struct ul_info_transfer_ind_s { - uint32_t UEid; /* UE lower layer identifier */ - as_nas_info_t nasMsg; /* Uplink NAS message */ -} ul_info_transfer_ind_t; - -/* - * NAS->AS - Downlink data transfer request - * NAS requests the AS to transfer downlink information to the NAS that - * operates at the UE side. - */ -typedef ul_info_transfer_req_t dl_info_transfer_req_t; - -/* - * AS->NAS - Downlink data transfer confirm - * AS immediately notifies the NAS whether downlink information has been - * successfully sent to the network or not. - */ -typedef ul_info_transfer_cnf_t dl_info_transfer_cnf_t; - -/* - * AS->NAS - Downlink data transfer indication - * AS delivers the downlink information message to the NAS that operates - * at the UE side. - */ -typedef ul_info_transfer_ind_t dl_info_transfer_ind_t; - -/* - * -------------------------------------------------------------------------- - * Radio Access Bearer establishment - * -------------------------------------------------------------------------- - */ - -/* TODO: Quality of Service parameters */ -typedef struct {} as_qos_t; - -/* - * NAS->AS - Radio access bearer establishment request - * NAS requests the AS to allocate transmission resources to radio access - * bearer initialized at the network side. - */ -typedef struct rab_establish_req_s { - as_stmsi_t s_tmsi; /* UE identity */ - as_rab_id_t rabID; /* Radio access bearer identity */ - as_qos_t QoS; /* Requested Quality of Service */ -} rab_establish_req_t; - -/* - * AS->NAS - Radio access bearer establishment indication - * AS notifies the NAS that specific radio access bearer has to be setup. - */ -typedef struct rab_establish_ind_s { - as_rab_id_t rabID; /* Radio access bearer identity */ -} rab_establish_ind_t; - -/* - * NAS->AS - Radio access bearer establishment response - * NAS responds to AS whether the specified radio access bearer has been - * successfully setup or not. - */ -typedef struct rab_establish_rsp_s { - as_stmsi_t s_tmsi; /* UE identity */ - as_rab_id_t rabID; /* Radio access bearer identity */ - nas_error_code_t errCode; /* Transaction status */ -} rab_establish_rsp_t; - -/* - * AS->NAS - Radio access bearer establishment confirm - * AS notifies NAS whether the specified radio access bearer has been - * successfully setup at the UE side or not. - */ -typedef struct rab_establish_cnf_s { - as_rab_id_t rabID; /* Radio access bearer identity */ - nas_error_code_t errCode; /* Transaction status */ -} rab_establish_cnf_t; - -/* - * -------------------------------------------------------------------------- - * Radio Access Bearer release - * -------------------------------------------------------------------------- - */ - -/* - * NAS->AS - Radio access bearer release request - * NAS requests the AS to release transmission resources previously allocated - * to specific radio access bearer at the network side. - */ -typedef struct rab_release_req_s { - as_stmsi_t s_tmsi; /* UE identity */ - as_rab_id_t rabID; /* Radio access bearer identity */ -} rab_release_req_t; - -/* - * AS->NAS - Radio access bearer release indication - * AS notifies NAS that specific radio access bearer has been released. - */ -typedef struct rab_release_ind_s { - as_rab_id_t rabID; /* Radio access bearer identity */ -} rab_release_ind_t; - -/* - * -------------------------------------------------------------------------- - * Structure of the AS messages handled by the network sublayer - * -------------------------------------------------------------------------- - */ -typedef struct as_message_s { - uint16_t msgID; - union { - broadcast_info_ind_t broadcast_info_ind; - cell_info_req_t cell_info_req; - cell_info_cnf_t cell_info_cnf; - cell_info_ind_t cell_info_ind; - paging_req_t paging_req; - paging_ind_t paging_ind; - nas_establish_req_t nas_establish_req; - nas_establish_ind_t nas_establish_ind; - nas_establish_rsp_t nas_establish_rsp; - nas_establish_cnf_t nas_establish_cnf; - nas_release_req_t nas_release_req; - nas_release_ind_t nas_release_ind; - ul_info_transfer_req_t ul_info_transfer_req; - ul_info_transfer_cnf_t ul_info_transfer_cnf; - ul_info_transfer_ind_t ul_info_transfer_ind; - dl_info_transfer_req_t dl_info_transfer_req; - dl_info_transfer_cnf_t dl_info_transfer_cnf; - dl_info_transfer_ind_t dl_info_transfer_ind; - rab_establish_req_t rab_establish_req; - rab_establish_ind_t rab_establish_ind; - rab_establish_rsp_t rab_establish_rsp; - rab_establish_cnf_t rab_establish_cnf; - rab_release_req_t rab_release_req; - rab_release_ind_t rab_release_ind; - } __attribute__((__packed__)) msg; -} as_message_t; - -/****************************************************************************/ -/******************** G L O B A L V A R I A B L E S ********************/ -/****************************************************************************/ - -/****************************************************************************/ -/****************** E X P O R T E D F U N C T I O N S ******************/ -/****************************************************************************/ - -int as_message_decode(const char* buffer, as_message_t* msg, int length); - -int as_message_encode(char* buffer, as_message_t* msg, int length); - -/* Implemented in the network_api.c body file */ -int as_message_send(as_message_t* as_msg); - -#endif /* __AS_MESSAGE_H__*/ diff --git a/openair3/NAS/COMMON/UTIL/socket.c b/openair3/NAS/COMMON/UTIL/socket.c index 25876c3e6f..53a6ec8823 100644 --- a/openair3/NAS/COMMON/UTIL/socket.c +++ b/openair3/NAS/COMMON/UTIL/socket.c @@ -107,7 +107,7 @@ void* socket_udp_open(int type, const char* host, const char* port) { struct addrinfo socket_info; /* endpoint information */ struct addrinfo *socket_addr, *sp; /* endpoint address */ - int sfd; /* socket file descriptor */ + int sfd=-1; /* socket file descriptor */ /* * Parameters sanity check diff --git a/openair3/NAS/COMMON/UTIL/socket.h b/openair3/NAS/COMMON/UTIL/socket.h index 033046d98c..58bc6b8527 100644 --- a/openair3/NAS/COMMON/UTIL/socket.h +++ b/openair3/NAS/COMMON/UTIL/socket.h @@ -35,8 +35,8 @@ Author Frederic Maurel Description Implements TCP socket handlers *****************************************************************************/ -#ifndef __SOCKET_H__ -#define __SOCKET_H__ +#ifndef __NAS_COMMON_UTIL_SOCKET__H__ +#define __NAS_COMMON_UTIL_SOCKET__H__ #include @@ -71,4 +71,4 @@ ssize_t socket_send(const void* id, const char* buffer, size_t length); void socket_close(void* id); -#endif /* __SOCKET_H__*/ +#endif /* __NAS_COMMON_UTIL_SOCKET__H__ */ diff --git a/openair3/NAS/COMMON/commonDef.h b/openair3/NAS/COMMON/commonDef.h deleted file mode 100644 index e9f769db55..0000000000 --- a/openair3/NAS/COMMON/commonDef.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright (c) 2015, EURECOM (www.eurecom.fr) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * The views and conclusions contained in the software and documentation are those - * of the authors and should not be interpreted as representing official policies, - * either expressed or implied, of the FreeBSD Project. - */ -/* - -Source commonDef.h - -Version 0.1 - -Date 2012/02/27 - -Product NAS stack - -Subsystem include - -Author Frederic Maurel - -Description Contains global common definitions - -*****************************************************************************/ -#ifndef __COMMONDEF_H__ -#define __COMMONDEF_H__ - -#include -#include -#include - -typedef signed char boolean_t; - -#if !defined(TRUE) -#define TRUE (boolean_t)0x01 -#endif - -#if !defined(FALSE) -#define FALSE (boolean_t)0x00 -#endif - -#define BOOL_NOT(b) (b^TRUE) - -#define NAS_UE_ID_FMT "0x%06x" - -/****************************************************************************/ -/********************* G L O B A L C O N S T A N T S *******************/ -/****************************************************************************/ - -#define RETURNok (0) -#define RETURNerror (-1) - -/* - * Name of the environment variable which defines the default directory - * where the NAS application is executed and where are located files - * where non-volatile data are stored - */ -#define DEFAULT_NAS_PATH "PWD" - -/****************************************************************************/ -/************************ G L O B A L T Y P E S ************************/ -/****************************************************************************/ - -/* ------------------------------------------------------------------------------ - Standard data type definitions ------------------------------------------------------------------------------ -*/ -typedef int8_t SByte_t; /* 8 bit signed integer */ -typedef uint8_t Byte_t; /* 8 bit unsigned integer */ - - -/* ------------------------------------------------------------------------------ - Common NAS data type definitions ------------------------------------------------------------------------------ -*/ - -typedef uint8_t Stat_t; /* Registration status */ -typedef uint16_t lac_t; /* Location Area Code */ -typedef uint8_t rac_t; /* Routing Area Code */ -typedef uint16_t tac_t; /* Tracking Area Code */ -typedef uint32_t ci_t; /* Cell Identifier */ -typedef uint8_t AcT_t; /* Access Technology */ - -/* - * International Mobile Subscriber Identity - */ -typedef struct { - Byte_t length; - union { - struct { - Byte_t digit2:4; - Byte_t digit1:4; - Byte_t digit4:4; - Byte_t digit3:4; - Byte_t digit6:4; - Byte_t digit5:4; - Byte_t digit8:4; - Byte_t digit7:4; - Byte_t digit10:4; - Byte_t digit9:4; - Byte_t digit12:4; - Byte_t digit11:4; - Byte_t digit14:4; - Byte_t digit13:4; -#define EVEN_PARITY 0 -#define ODD_PARITY 1 - Byte_t parity:4; - Byte_t digit15:4; - } num; -#define IMSI_SIZE 8 - Byte_t value[IMSI_SIZE]; - } u; -} imsi_t; - -#define NAS_IMSI2STR(iMsI_t_PtR,iMsI_sTr, MaXlEn) \ - {\ - int l_offset = 0;\ - int l_ret = 0;\ - l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u%u%u%u%u",\ - iMsI_t_PtR->u.num.digit1, iMsI_t_PtR->u.num.digit2,\ - iMsI_t_PtR->u.num.digit3, iMsI_t_PtR->u.num.digit4,\ - iMsI_t_PtR->u.num.digit5);\ - if ((iMsI_t_PtR->u.num.digit6 != 0xf) && (l_ret > 0)) {\ - l_offset += l_ret;\ - l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u", iMsI_t_PtR->u.num.digit6);\ - }\ - if (l_ret > 0) {\ - l_offset += l_ret;\ - l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u%u%u%u%u%u%u%u",\ - iMsI_t_PtR->u.num.digit7, iMsI_t_PtR->u.num.digit8,\ - iMsI_t_PtR->u.num.digit9, iMsI_t_PtR->u.num.digit10,\ - iMsI_t_PtR->u.num.digit11, iMsI_t_PtR->u.num.digit12,\ - iMsI_t_PtR->u.num.digit13, iMsI_t_PtR->u.num.digit14);\ - }\ - if ((iMsI_t_PtR->u.num.digit15 != 0xf) && (l_ret > 0)) {\ - l_offset += l_ret;\ - l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u", iMsI_t_PtR->u.num.digit15);\ - }\ - } - -/* - * Mobile subscriber dialing number - */ -typedef struct { - Byte_t ext:1; - /* Type Of Number */ -#define MSISDN_TON_UNKNOWKN 0b000 -#define MSISDN_TON_INTERNATIONAL 0b001 -#define MSISDN_TON_NATIONAL 0b010 -#define MSISDN_TON_NETWORK 0b011 -#define MSISDN_TON_SUBCRIBER 0b100 -#define MSISDN_TON_ABBREVIATED 0b110 -#define MSISDN_TON_RESERVED 0b111 - Byte_t ton:3; - /* Numbering Plan Identification */ -#define MSISDN_NPI_UNKNOWN 0b0000 -#define MSISDN_NPI_ISDN_TELEPHONY 0b0001 -#define MSISDN_NPI_GENERIC 0b0010 -#define MSISDN_NPI_DATA 0b0011 -#define MSISDN_NPI_TELEX 0b0100 -#define MSISDN_NPI_MARITIME_MOBILE 0b0101 -#define MSISDN_NPI_LAND_MOBILE 0b0110 -#define MSISDN_NPI_ISDN_MOBILE 0b0111 -#define MSISDN_NPI_PRIVATE 0b1110 -#define MSISDN_NPI_RESERVED 0b1111 - Byte_t npi:4; - /* Dialing Number */ - struct { - Byte_t lsb:4; - Byte_t msb:4; -#define MSISDN_DIGIT_SIZE 10 - } digit[MSISDN_DIGIT_SIZE]; -} msisdn_t; - -/* - * International Mobile Equipment Identity - */ -typedef imsi_t imei_t; - -/* - * Public Land Mobile Network identifier - * PLMN = BCD encoding (Mobile Country Code + Mobile Network Code) - */ -typedef struct { - Byte_t MCCdigit2:4; - Byte_t MCCdigit1:4; - Byte_t MNCdigit3:4; - Byte_t MCCdigit3:4; - Byte_t MNCdigit2:4; - Byte_t MNCdigit1:4; -} plmn_t; - -/* - * Location Area Identification - */ -typedef struct { - plmn_t plmn; /* + */ - lac_t lac; /* Location Area Code */ -} lai_t; - -/* - * GPRS Routing Area Identification - */ -typedef struct { - plmn_t plmn; /* + */ - lac_t lac; /* Location Area Code */ - rac_t rac; /* Routing Area Code */ -} RAI_t; - -/* - * EPS Tracking Area Identification - */ -typedef struct { - plmn_t plmn; /* + */ - tac_t tac; /* Tracking Area Code */ -} tai_t; - -/* - * EPS Globally Unique MME Identity - */ -typedef struct { - plmn_t plmn; /* + */ - uint16_t MMEgid; /* MME group identifier */ - uint8_t MMEcode; /* MME code */ -} gummei_t; - -/* - * EPS Globally Unique Temporary UE Identity - */ -typedef struct { - gummei_t gummei; /* Globally Unique MME Identity */ - uint32_t m_tmsi; /* M-Temporary Mobile Subscriber Identity */ -} GUTI_t; -#define GUTI2STR(GuTi_PtR, GuTi_StR, MaXlEn) \ - {\ - int l_offset = 0;\ - int l_ret = 0;\ - l_ret += snprintf(GuTi_StR + l_offset,MaXlEn-l_offset, "%03u.",\ - GuTi_PtR->gummei.plmn.MCCdigit3 * 100 +\ - GuTi_PtR->gummei.plmn.MCCdigit2 * 10 +\ - GuTi_PtR->gummei.plmn.MCCdigit1);\ - if (l_ret > 0) {\ - l_offset += l_ret;\ - } else {\ - l_offset = MaXlEn;\ - }\ - if (GuTi_PtR->gummei.plmn.MNCdigit1 != 0xf) {\ - l_ret += snprintf(GuTi_StR + l_offset,MaXlEn-l_offset, "%03u|%04x|%02x|%08x",\ - GuTi_PtR->gummei.plmn.MNCdigit3 * 100 +\ - GuTi_PtR->gummei.plmn.MNCdigit2 * 10 +\ - GuTi_PtR->gummei.plmn.MNCdigit1,\ - GuTi_PtR->gummei.MMEgid,\ - GuTi_PtR->gummei.MMEcode,\ - GuTi_PtR->m_tmsi);\ - } else {\ - l_ret += snprintf(GuTi_StR + l_offset,MaXlEn-l_offset, "%02u|%04x|%02x|%08x",\ - GuTi_PtR->gummei.plmn.MNCdigit2 * 10 +\ - GuTi_PtR->gummei.plmn.MNCdigit1,\ - GuTi_PtR->gummei.MMEgid,\ - GuTi_PtR->gummei.MMEcode,\ - GuTi_PtR->m_tmsi);\ - }\ - } - - - - -/* Checks PLMN validity */ -#define PLMN_IS_VALID(plmn) (((plmn).MCCdigit1 & \ - (plmn).MCCdigit2 & \ - (plmn).MCCdigit3) != 0x0F) - -/* Checks TAC validity */ -#define TAC_IS_VALID(tac) (((tac) != 0x0000) && ((tac) != 0xFFF0)) - -/* Checks TAI validity */ -#define TAI_IS_VALID(tai) (PLMN_IS_VALID((tai).plmn) && \ - TAC_IS_VALID((tai).tac)) -/* - * A list of PLMNs - */ -#define PLMN_LIST_T(SIZE) struct {Byte_t n_plmns; plmn_t plmn[SIZE];} - -/* - * A list of TACs - */ -#define TAC_LIST_T(SIZE) struct {Byte_t n_tacs; TAC_t tac[SIZE];} - -/* - * A list of TAIs - */ -#define TAI_LIST_T(SIZE) struct {Byte_t n_tais; tai_t tai[SIZE];} - -typedef enum eps_protocol_discriminator_e { - /* Protocol discriminator identifier for EPS Mobility Management */ - EPS_MOBILITY_MANAGEMENT_MESSAGE = 0x7, - - /* Protocol discriminator identifier for EPS Session Management */ - EPS_SESSION_MANAGEMENT_MESSAGE = 0x2, -} eps_protocol_discriminator_t; - -/****************************************************************************/ -/******************** G L O B A L V A R I A B L E S ********************/ -/****************************************************************************/ - -/****************************************************************************/ -/****************** E X P O R T E D F U N C T I O N S ******************/ -/****************************************************************************/ - -#endif /* __COMMONDEF_H__*/ diff --git a/openair3/NAS/COMMON/networkDef.h b/openair3/NAS/COMMON/networkDef.h deleted file mode 100644 index 5390eac2f0..0000000000 --- a/openair3/NAS/COMMON/networkDef.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2015, EURECOM (www.eurecom.fr) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * The views and conclusions contained in the software and documentation are those - * of the authors and should not be interpreted as representing official policies, - * either expressed or implied, of the FreeBSD Project. - */ - -/***************************************************************************** - -Source networkDef.h - -Version 0.1 - -Date 2012/09/21 - -Product NAS stack - -Subsystem include - -Author Frederic Maurel - -Description Contains network's global definitions - -*****************************************************************************/ -#ifndef __NETWORKDEF_H__ -#define __NETWORKDEF_H__ - -/****************************************************************************/ -/********************* G L O B A L C O N S T A N T S *******************/ -/****************************************************************************/ - -/* - * ---------------------- - * Network selection mode - * ---------------------- - */ -#define NET_PLMN_AUTO 0 -#define NET_PLMN_MANUAL 1 - -/* - * --------------------------- - * Network registration status - * --------------------------- - */ -/* not registered, not currently searching an operator to register to */ -#define NET_REG_STATE_OFF 0 -/* registered, home network */ -#define NET_REG_STATE_HN 1 -/* not registered, currently trying to attach or searching an operator - * to register to */ -#define NET_REG_STATE_ON 2 -/* registration denied */ -#define NET_REG_STATE_DENIED 3 -/* unknown (e.g. out of GERAN/UTRAN/E-UTRAN coverage) */ -#define NET_REG_STATE_UNKNOWN 4 -/* registered, roaming */ -#define NET_REG_STATE_ROAMING 5 -/* registered for "SMS only", home network */ -#define NET_REG_STATE_SMS_HN 6 -/* registered, for "SMS only", roaming */ -#define NET_REG_STATE_SMS_ROAMING 7 -/* attached for emergency bearer services only (applicable to UTRAN) */ -#define NET_REG_STATE_EMERGENCY 8 - -/* - * ------------------------------------ - * Network access technology indicators - * ------------------------------------ - */ -#define NET_ACCESS_UNAVAILABLE (-1) /* Not available */ -#define NET_ACCESS_GSM 0 /* GSM */ -#define NET_ACCESS_COMPACT 1 /* GSM Compact */ -#define NET_ACCESS_UTRAN 2 /* UTRAN */ -#define NET_ACCESS_EGPRS 3 /* GSM w/EGPRS */ -#define NET_ACCESS_HSDPA 4 /* UTRAN w/HSDPA */ -#define NET_ACCESS_HSUPA 5 /* UTRAN w/HSUPA */ -#define NET_ACCESS_HSDUPA 6 /* UTRAN w/HSDPA and HSUPA */ -#define NET_ACCESS_EUTRAN 7 /* E-UTRAN */ - -/* - * --------------------------------------- - * Network operator representation formats - * --------------------------------------- - */ -#define NET_FORMAT_LONG 0 /* long format alphanumeric */ -#define NET_FORMAT_SHORT 1 /* short format alphanumeric */ -#define NET_FORMAT_NUM 2 /* numeric format */ - -#define NET_FORMAT_MAX_SIZE NET_FORMAT_LONG_SIZE - -/* - * ----------------------------- - * Network operator availability - * ----------------------------- - */ -#define NET_OPER_UNKNOWN 0 /* unknown operator */ -#define NET_OPER_AVAILABLE 1 /* available operator */ -#define NET_OPER_CURRENT 2 /* currently selected operator */ -#define NET_OPER_FORBIDDEN 3 /* forbidden operator */ - -/* - * -------------------------------------- - * Network connection establishment cause - * -------------------------------------- - */ -#define NET_ESTABLISH_CAUSE_EMERGENCY 0x01 -#define NET_ESTABLISH_CAUSE_HIGH_PRIO 0x02 -#define NET_ESTABLISH_CAUSE_MT_ACCESS 0x03 -#define NET_ESTABLISH_CAUSE_MO_SIGNAL 0x04 -#define NET_ESTABLISH_CAUSE_MO_DATA 0x05 -#define NET_ESTABLISH_CAUSE_V1020 0x06 - -/* - * -------------------------------------- - * Network connection establishment type - * -------------------------------------- - */ -#define NET_ESTABLISH_TYPE_ORIGINATING_SIGNAL 0x10 -#define NET_ESTABLISH_TYPE_EMERGENCY_CALLS 0x20 -#define NET_ESTABLISH_TYPE_ORIGINATING_CALLS 0x30 -#define NET_ESTABLISH_TYPE_TERMINATING_CALLS 0x40 -#define NET_ESTABLISH_TYPE_MO_CS_FALLBACK 0x50 - -/* - * ------------------- - * PDN connection type - * ------------------- - */ -#define NET_PDN_TYPE_IPV4 (0 + 1) -#define NET_PDN_TYPE_IPV6 (1 + 1) -#define NET_PDN_TYPE_IPV4V6 (2 + 1) - -/****************************************************************************/ -/************************ G L O B A L T Y P E S ************************/ -/****************************************************************************/ - -/* - * --------------------- - * PDN connection status - * --------------------- - */ -typedef enum { - /* MT = The Mobile Terminal, NW = The Network */ - NET_PDN_MT_DEFAULT_ACT = 1, /* MT has activated a PDN connection */ - NET_PDN_NW_DEFAULT_DEACT, /* NW has deactivated a PDN connection */ - NET_PDN_MT_DEFAULT_DEACT, /* MT has deactivated a PDN connection */ - NET_PDN_NW_DEDICATED_ACT, /* NW has activated an EPS bearer context */ - NET_PDN_MT_DEDICATED_ACT, /* MT has activated an EPS bearer context */ - NET_PDN_NW_DEDICATED_DEACT, /* NW has deactivated an EPS bearer context */ - NET_PDN_MT_DEDICATED_DEACT, /* MT has deactivated an EPS bearer context */ -} network_pdn_state_t; - -/* - * --------------------------- - * Network operator identifier - * --------------------------- - */ -typedef struct { -#define NET_FORMAT_LONG_SIZE 16 /* Long alphanumeric format */ -#define NET_FORMAT_SHORT_SIZE 8 /* Short alphanumeric format */ -#define NET_FORMAT_NUM_SIZE 6 /* Numeric format (PLMN identifier */ - union { - unsigned char alpha_long[NET_FORMAT_LONG_SIZE+1]; - unsigned char alpha_short[NET_FORMAT_SHORT_SIZE+1]; - unsigned char num[NET_FORMAT_NUM_SIZE+1]; - } id; -} network_plmn_t; - -/* - * ------------------------------- - * EPS bearer level QoS parameters - * ------------------------------- - */ -typedef struct { - int gbrUL; /* Guaranteed Bit Rate for uplink */ - int gbrDL; /* Guaranteed Bit Rate for downlink */ - int mbrUL; /* Maximum Bit Rate for uplink */ - int mbrDL; /* Maximum Bit Rate for downlink */ - int qci; /* QoS Class Identifier */ -} network_qos_t; - -/* - * ----------------------------- - * IPv4 packet filter parameters - * ----------------------------- - */ -typedef struct { - unsigned char protocol; /* Protocol identifier */ - unsigned char tos; /* Type of service */ -#define NET_PACKET_FILTER_IPV4_ADDR_SIZE 4 - unsigned char addr[NET_PACKET_FILTER_IPV4_ADDR_SIZE]; - unsigned char mask[NET_PACKET_FILTER_IPV4_ADDR_SIZE]; -} network_ipv4_data_t; - -/* - * ----------------------------- - * IPv6 packet filter parameters - * ----------------------------- - */ -typedef struct { - unsigned char nh; /* Next header type */ - unsigned char tf; /* Traffic class */ -#define NET_PACKET_FILTER_IPV6_ADDR_SIZE 16 - unsigned char addr[NET_PACKET_FILTER_IPV6_ADDR_SIZE]; - unsigned char mask[NET_PACKET_FILTER_IPV6_ADDR_SIZE]; - unsigned int ipsec; /* IPSec security parameter index */ - unsigned int fl; /* Flow label */ -} network_ipv6_data_t; - -/* - * ------------- - * Packet Filter - * ------------- - */ -typedef struct { - unsigned char id; /* Packet filter identifier */ -#define NET_PACKET_FILTER_DOWNLINK 0x01 -#define NET_PACKET_FILTER_UPLINK 0x02 -#define NET_PACKET_FILTER_BIDIR 0x03 - unsigned char dir; /* Packet filter direction */ - unsigned char precedence; /* Evaluation precedence */ - union { - network_ipv4_data_t ipv4; - network_ipv6_data_t ipv6; - } data; - unsigned short lport; /* Local (UE) port number */ - unsigned short rport; /* Remote (network) port number */ -} network_pkf_t; - -/* - * --------------------- - * Traffic Flow Template - * --------------------- - */ -typedef struct { - int n_pkfs; -#define NET_PACKET_FILTER_MAX 16 - network_pkf_t* pkf[NET_PACKET_FILTER_MAX]; -} network_tft_t; - -/****************************************************************************/ -/******************** G L O B A L V A R I A B L E S ********************/ -/****************************************************************************/ - -/****************************************************************************/ -/****************** E X P O R T E D F U N C T I O N S ******************/ -/****************************************************************************/ - -#endif /* __NETWORKDEF_H__*/ diff --git a/openair3/NAS/TEST/USER/user_parser.h b/openair3/NAS/TEST/USER/user_parser.h index d1972de028..e7fc07ee32 100644 --- a/openair3/NAS/TEST/USER/user_parser.h +++ b/openair3/NAS/TEST/USER/user_parser.h @@ -39,8 +39,8 @@ Description Command line parser of the user simulator process *****************************************************************************/ -#ifndef __USER_PARSER_H__ -#define __USER_PARSER__H__ +#ifndef __NAS_TEST_USER_USER_PARSER__H__ +#define __NAS_TEST_USER_USER_PARSER__H__ /****************************************************************************/ /********************* G L O B A L C O N S T A N T S *******************/ @@ -74,4 +74,4 @@ const char* user_parser_get_port(void); const char* user_parser_get_devpath(void); const char* user_parser_get_devattr(void); -#endif /* __USER_PARSER_H__*/ +#endif /* __NAS_TEST_USER_USER_PARSER__H__ */ diff --git a/openair3/NAS/TOOLS/conf_network.c b/openair3/NAS/TOOLS/conf_network.c index 96e2183327..054189a130 100644 --- a/openair3/NAS/TOOLS/conf_network.c +++ b/openair3/NAS/TOOLS/conf_network.c @@ -43,7 +43,7 @@ void gen_network_record_from_conf(const plmn_conf_param_t *conf, network_record_ strcpy(record->fullname, conf->fullname); strcpy(record->shortname, conf->shortname); - char num[6]; + char num[60]; sprintf(num, "%s%s", conf->mcc, conf->mnc); record->num = atoi(num); @@ -80,7 +80,7 @@ bool parse_plmn_param(config_setting_t *plmn_setting, plmn_conf_param_t *conf) { bool parse_plmns(config_setting_t *all_plmn_setting, networks_t *networks) { config_setting_t *plmn_setting = NULL; - char plmn[10]; + char plmn[100]; int size = 0; size = config_setting_length(all_plmn_setting); diff --git a/openair3/NAS/TOOLS/conf_parser.c b/openair3/NAS/TOOLS/conf_parser.c index d46142c461..3ea1e29554 100644 --- a/openair3/NAS/TOOLS/conf_parser.c +++ b/openair3/NAS/TOOLS/conf_parser.c @@ -13,7 +13,7 @@ bool parse_config_file(const char *output_dir, const char *conf_filename, int ou config_setting_t *root_setting = NULL; config_setting_t *ue_setting = NULL; config_setting_t *all_plmn_setting = NULL; - char user[10]; + char user[100]; config_t cfg; networks_t networks;; diff --git a/openair3/TEST/oaisim_mme_test_s1c_s1ap.h b/openair3/TEST/oaisim_mme_test_s1c_s1ap.h index 3633f11e86..4faec0e66e 100644 --- a/openair3/TEST/oaisim_mme_test_s1c_s1ap.h +++ b/openair3/TEST/oaisim_mme_test_s1c_s1ap.h @@ -19,6 +19,9 @@ * contact@openairinterface.org */ +#ifndef __TEST_OAISIM_MME_TEST_S1C_S1AP__H__ +#define __TEST_OAISIM_MME_TEST_S1C_S1AP__H__ + #define _GNU_SOURCE #include #include @@ -53,3 +56,5 @@ void s1ap_eNB_register_mme(s1ap_eNB_instance_t *instance_p, uint16_t out_streams); void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t *s1ap_register_eNB); void *s1ap_eNB_task(void *arg); + +#endif diff --git a/openair3/TEST/oaisim_mme_test_s1c_scenario.h b/openair3/TEST/oaisim_mme_test_s1c_scenario.h index 8c33f45741..8b9a8dd54a 100644 --- a/openair3/TEST/oaisim_mme_test_s1c_scenario.h +++ b/openair3/TEST/oaisim_mme_test_s1c_scenario.h @@ -19,6 +19,9 @@ * contact@openairinterface.org */ +#ifndef __TEST_OAISIM_MME_TEST_S1C_SCENARIO__H__ +#define __TEST_OAISIM_MME_TEST_S1C_SCENARIO__H__ + #include #include @@ -49,3 +52,5 @@ int compare_buffer(const uint8_t *buffer, const uint32_t length_buffer, con unsigned decode_hex_length(const char *h); int decode_hex(uint8_t *dst, const char *h); uint8_t *decode_hex_dup(const char *hex); + +#endif diff --git a/openair3/UTILS/mme_config.h b/openair3/UTILS/mme_config.h index 37b7dff865..417c8bbd5f 100644 --- a/openair3/UTILS/mme_config.h +++ b/openair3/UTILS/mme_config.h @@ -19,14 +19,14 @@ * contact@openairinterface.org */ +#ifndef __UTILS_MME_CONFIG__H__ +#define __UTILS_MME_CONFIG__H__ + #include #include #include "mme_default_values.h" -#ifndef MME_CONFIG_H_ -#define MME_CONFIG_H_ - #define MME_CONFIG_STRING_MME_CONFIG "MME" #define MME_CONFIG_STRING_REALM "REALM" #define MME_CONFIG_STRING_MAXENB "MAXENB" @@ -183,4 +183,4 @@ int config_parse_opt_line(int argc, char *argv[], mme_config_t *mme_config); //int yyparse(struct mme_config_s *mme_config_p); -#endif /* MME_CONFIG_H_ */ +#endif /* __UTILS_MME_CONFIG__H__ */ diff --git a/openair3/UTILS/queue.h b/openair3/UTILS/queue.h deleted file mode 100644 index f8665c0f1a..0000000000 --- a/openair3/UTILS/queue.h +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright (c) 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)queue.h 8.5 (Berkeley) 8/20/94 - */ - -#ifndef _SYS_QUEUE_H_ -#define _SYS_QUEUE_H_ - -/* - * This file defines five types of data structures: singly-linked lists, - * lists, simple queues, tail queues, and circular queues. - * - * A singly-linked list is headed by a single forward pointer. The - * elements are singly linked for minimum space and pointer manipulation - * overhead at the expense of O(n) removal for arbitrary elements. New - * elements can be added to the list after an existing element or at the - * head of the list. Elements being removed from the head of the list - * should use the explicit macro for this purpose for optimum - * efficiency. A singly-linked list may only be traversed in the forward - * direction. Singly-linked lists are ideal for applications with large - * datasets and few or no removals or for implementing a LIFO queue. - * - * A list is headed by a single forward pointer (or an array of forward - * pointers for a hash table header). The elements are doubly linked - * so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before - * or after an existing element or at the head of the list. A list - * may only be traversed in the forward direction. - * - * A simple queue is headed by a pair of pointers, one the head of the - * list and the other to the tail of the list. The elements are singly - * linked to save space, so elements can only be removed from the - * head of the list. New elements can be added to the list after - * an existing element, at the head of the list, or at the end of the - * list. A simple queue may only be traversed in the forward direction. - * - * A tail queue is headed by a pair of pointers, one to the head of the - * list and the other to the tail of the list. The elements are doubly - * linked so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before or - * after an existing element, at the head of the list, or at the end of - * the list. A tail queue may be traversed in either direction. - * - * A circle queue is headed by a pair of pointers, one to the head of the - * list and the other to the tail of the list. The elements are doubly - * linked so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before or after - * an existing element, at the head of the list, or at the end of the list. - * A circle queue may be traversed in either direction, but has a more - * complex end of list detection. - * - * For details on the use of these macros, see the queue(3) manual page. - * SLIST LIST STAILQ TAILQ CIRCLEQ - * _HEAD + + + + + - * _HEAD_INITIALIZER + + + + + - * _ENTRY + + + + + - * _INIT + + + + + - * _EMPTY + + + + + - * _FIRST + + + + + - * _NEXT + + + + + - * _PREV - - - + + - * _LAST - - + + + - * _FOREACH + + + + + - * _FOREACH_REVERSE - - - + + - * _INSERT_HEAD + + + + + - * _INSERT_BEFORE - + - + + - * _INSERT_AFTER + + + + + - * _INSERT_TAIL - - + + + - * _REMOVE_HEAD + - + - - - * _REMOVE + + + + + - */ - -/* - * List definitions. - */ -#define LIST_HEAD(name, type) \ -struct name { \ - struct type *lh_first; /* first element */ \ -} - -#define LIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define LIST_ENTRY(type) \ -struct { \ - struct type *le_next; /* next element */ \ - struct type **le_prev; /* address of previous next element */ \ -} - -/* - * List functions. - */ -#define LIST_INIT(head) do { \ - (head)->lh_first = NULL; \ -} while (/*CONSTCOND*/0) - -#define LIST_INSERT_AFTER(listelm, elm, field) do { \ - if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ - (listelm)->field.le_next->field.le_prev = \ - &(elm)->field.le_next; \ - (listelm)->field.le_next = (elm); \ - (elm)->field.le_prev = &(listelm)->field.le_next; \ -} while (/*CONSTCOND*/0) - -#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ - (elm)->field.le_prev = (listelm)->field.le_prev; \ - (elm)->field.le_next = (listelm); \ - *(listelm)->field.le_prev = (elm); \ - (listelm)->field.le_prev = &(elm)->field.le_next; \ -} while (/*CONSTCOND*/0) - -#define LIST_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.le_next = (head)->lh_first) != NULL) \ - (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ - (head)->lh_first = (elm); \ - (elm)->field.le_prev = &(head)->lh_first; \ -} while (/*CONSTCOND*/0) - -#define LIST_REMOVE(elm, field) do { \ - if ((elm)->field.le_next != NULL) \ - (elm)->field.le_next->field.le_prev = \ - (elm)->field.le_prev; \ - *(elm)->field.le_prev = (elm)->field.le_next; \ -} while (/*CONSTCOND*/0) - -#define LIST_FOREACH(var, head, field) \ - for ((var) = ((head)->lh_first); \ - (var); \ - (var) = ((var)->field.le_next)) - -/* - * List access methods. - */ -#define LIST_EMPTY(head) ((head)->lh_first == NULL) -#define LIST_FIRST(head) ((head)->lh_first) -#define LIST_NEXT(elm, field) ((elm)->field.le_next) - - -/* - * Singly-linked List definitions. - */ -#define SLIST_HEAD(name, type) \ -struct name { \ - struct type *slh_first; /* first element */ \ -} - -#define SLIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define SLIST_ENTRY(type) \ -struct { \ - struct type *sle_next; /* next element */ \ -} - -/* - * Singly-linked List functions. - */ -#define SLIST_INIT(head) do { \ - (head)->slh_first = NULL; \ -} while (/*CONSTCOND*/0) - -#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ - (elm)->field.sle_next = (slistelm)->field.sle_next; \ - (slistelm)->field.sle_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define SLIST_INSERT_HEAD(head, elm, field) do { \ - (elm)->field.sle_next = (head)->slh_first; \ - (head)->slh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define SLIST_REMOVE_HEAD(head, field) do { \ - (head)->slh_first = (head)->slh_first->field.sle_next; \ -} while (/*CONSTCOND*/0) - -#define SLIST_REMOVE(head, elm, type, field) do { \ - if ((head)->slh_first == (elm)) { \ - SLIST_REMOVE_HEAD((head), field); \ - } \ - else { \ - struct type *curelm = (head)->slh_first; \ - while(curelm->field.sle_next != (elm)) \ - curelm = curelm->field.sle_next; \ - curelm->field.sle_next = \ - curelm->field.sle_next->field.sle_next; \ - } \ -} while (/*CONSTCOND*/0) - -#define SLIST_FOREACH(var, head, field) \ - for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next) - -/* - * Singly-linked List access methods. - */ -#define SLIST_EMPTY(head) ((head)->slh_first == NULL) -#define SLIST_FIRST(head) ((head)->slh_first) -#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) - - -/* - * Singly-linked Tail queue declarations. - */ -#define STAILQ_HEAD(name, type) \ -struct name { \ - struct type *stqh_first; /* first element */ \ - struct type **stqh_last; /* addr of last next element */ \ -} - -#define STAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).stqh_first } - -#define STAILQ_ENTRY(type) \ -struct { \ - struct type *stqe_next; /* next element */ \ -} - -/* - * Singly-linked Tail queue functions. - */ -#define STAILQ_INIT(head) do { \ - (head)->stqh_first = NULL; \ - (head)->stqh_last = &(head)->stqh_first; \ -} while (/*CONSTCOND*/0) - -#define STAILQ_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ - (head)->stqh_last = &(elm)->field.stqe_next; \ - (head)->stqh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define STAILQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.stqe_next = NULL; \ - *(head)->stqh_last = (elm); \ - (head)->stqh_last = &(elm)->field.stqe_next; \ -} while (/*CONSTCOND*/0) - -#define STAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ - if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\ - (head)->stqh_last = &(elm)->field.stqe_next; \ - (listelm)->field.stqe_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define STAILQ_REMOVE_HEAD(head, field) do { \ - if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \ - (head)->stqh_last = &(head)->stqh_first; \ -} while (/*CONSTCOND*/0) - -#define STAILQ_REMOVE(head, elm, type, field) do { \ - if ((head)->stqh_first == (elm)) { \ - STAILQ_REMOVE_HEAD((head), field); \ - } else { \ - struct type *curelm = (head)->stqh_first; \ - while (curelm->field.stqe_next != (elm)) \ - curelm = curelm->field.stqe_next; \ - if ((curelm->field.stqe_next = \ - curelm->field.stqe_next->field.stqe_next) == NULL) \ - (head)->stqh_last = &(curelm)->field.stqe_next; \ - } \ -} while (/*CONSTCOND*/0) - -#define STAILQ_FOREACH(var, head, field) \ - for ((var) = ((head)->stqh_first); \ - (var); \ - (var) = ((var)->field.stqe_next)) - -#define STAILQ_CONCAT(head1, head2) do { \ - if (!STAILQ_EMPTY((head2))) { \ - *(head1)->stqh_last = (head2)->stqh_first; \ - (head1)->stqh_last = (head2)->stqh_last; \ - STAILQ_INIT((head2)); \ - } \ -} while (/*CONSTCOND*/0) - -/* - * Singly-linked Tail queue access methods. - */ -#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) -#define STAILQ_FIRST(head) ((head)->stqh_first) -#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) - - -/* - * Simple queue definitions. - */ -#define SIMPLEQ_HEAD(name, type) \ -struct name { \ - struct type *sqh_first; /* first element */ \ - struct type **sqh_last; /* addr of last next element */ \ -} - -#define SIMPLEQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).sqh_first } - -#define SIMPLEQ_ENTRY(type) \ -struct { \ - struct type *sqe_next; /* next element */ \ -} - -/* - * Simple queue functions. - */ -#define SIMPLEQ_INIT(head) do { \ - (head)->sqh_first = NULL; \ - (head)->sqh_last = &(head)->sqh_first; \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ - (head)->sqh_last = &(elm)->field.sqe_next; \ - (head)->sqh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.sqe_next = NULL; \ - *(head)->sqh_last = (elm); \ - (head)->sqh_last = &(elm)->field.sqe_next; \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ - if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ - (head)->sqh_last = &(elm)->field.sqe_next; \ - (listelm)->field.sqe_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_REMOVE_HEAD(head, field) do { \ - if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ - (head)->sqh_last = &(head)->sqh_first; \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_REMOVE(head, elm, type, field) do { \ - if ((head)->sqh_first == (elm)) { \ - SIMPLEQ_REMOVE_HEAD((head), field); \ - } else { \ - struct type *curelm = (head)->sqh_first; \ - while (curelm->field.sqe_next != (elm)) \ - curelm = curelm->field.sqe_next; \ - if ((curelm->field.sqe_next = \ - curelm->field.sqe_next->field.sqe_next) == NULL) \ - (head)->sqh_last = &(curelm)->field.sqe_next; \ - } \ -} while (/*CONSTCOND*/0) - -#define SIMPLEQ_FOREACH(var, head, field) \ - for ((var) = ((head)->sqh_first); \ - (var); \ - (var) = ((var)->field.sqe_next)) - -/* - * Simple queue access methods. - */ -#define SIMPLEQ_EMPTY(head) ((head)->sqh_first == NULL) -#define SIMPLEQ_FIRST(head) ((head)->sqh_first) -#define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) - - -/* - * Tail queue definitions. - */ -#define _TAILQ_HEAD(name, type, qual) \ -struct name { \ - qual type *tqh_first; /* first element */ \ - qual type *qual *tqh_last; /* addr of last next element */ \ -} -#define TAILQ_HEAD(name, type) _TAILQ_HEAD(name, struct type,) - -#define TAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).tqh_first } - -#define _TAILQ_ENTRY(type, qual) \ -struct { \ - qual type *tqe_next; /* next element */ \ - qual type *qual *tqe_prev; /* address of previous next element */\ -} -#define TAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,) - -/* - * Tail queue functions. - */ -#define TAILQ_INIT(head) do { \ - (head)->tqh_first = NULL; \ - (head)->tqh_last = &(head)->tqh_first; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_HEAD(head, elm, field) do { \ - if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ - (head)->tqh_first->field.tqe_prev = \ - &(elm)->field.tqe_next; \ - else \ - (head)->tqh_last = &(elm)->field.tqe_next; \ - (head)->tqh_first = (elm); \ - (elm)->field.tqe_prev = &(head)->tqh_first; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.tqe_next = NULL; \ - (elm)->field.tqe_prev = (head)->tqh_last; \ - *(head)->tqh_last = (elm); \ - (head)->tqh_last = &(elm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ - if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ - (elm)->field.tqe_next->field.tqe_prev = \ - &(elm)->field.tqe_next; \ - else \ - (head)->tqh_last = &(elm)->field.tqe_next; \ - (listelm)->field.tqe_next = (elm); \ - (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ - (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ - (elm)->field.tqe_next = (listelm); \ - *(listelm)->field.tqe_prev = (elm); \ - (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_REMOVE(head, elm, field) do { \ - if (((elm)->field.tqe_next) != NULL) \ - (elm)->field.tqe_next->field.tqe_prev = \ - (elm)->field.tqe_prev; \ - else \ - (head)->tqh_last = (elm)->field.tqe_prev; \ - *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ -} while (/*CONSTCOND*/0) - -#define TAILQ_FOREACH(var, head, field) \ - for ((var) = ((head)->tqh_first); \ - (var); \ - (var) = ((var)->field.tqe_next)) - -#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ - for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); \ - (var); \ - (var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last))) - -#define TAILQ_CONCAT(head1, head2, field) do { \ - if (!TAILQ_EMPTY(head2)) { \ - *(head1)->tqh_last = (head2)->tqh_first; \ - (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ - (head1)->tqh_last = (head2)->tqh_last; \ - TAILQ_INIT((head2)); \ - } \ -} while (/*CONSTCOND*/0) - -/* - * Tail queue access methods. - */ -#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) -#define TAILQ_FIRST(head) ((head)->tqh_first) -#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) - -#define TAILQ_LAST(head, headname) \ - (*(((struct headname *)((head)->tqh_last))->tqh_last)) -#define TAILQ_PREV(elm, headname, field) \ - (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) - - -/* - * Circular queue definitions. - */ -#define CIRCLEQ_HEAD(name, type) \ -struct name { \ - struct type *cqh_first; /* first element */ \ - struct type *cqh_last; /* last element */ \ -} - -#define CIRCLEQ_HEAD_INITIALIZER(head) \ - { (void *)&head, (void *)&head } - -#define CIRCLEQ_ENTRY(type) \ -struct { \ - struct type *cqe_next; /* next element */ \ - struct type *cqe_prev; /* previous element */ \ -} - -/* - * Circular queue functions. - */ -#define CIRCLEQ_INIT(head) do { \ - (head)->cqh_first = (void *)(head); \ - (head)->cqh_last = (void *)(head); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ - (elm)->field.cqe_next = (listelm)->field.cqe_next; \ - (elm)->field.cqe_prev = (listelm); \ - if ((listelm)->field.cqe_next == (void *)(head)) \ - (head)->cqh_last = (elm); \ - else \ - (listelm)->field.cqe_next->field.cqe_prev = (elm); \ - (listelm)->field.cqe_next = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ - (elm)->field.cqe_next = (listelm); \ - (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ - if ((listelm)->field.cqe_prev == (void *)(head)) \ - (head)->cqh_first = (elm); \ - else \ - (listelm)->field.cqe_prev->field.cqe_next = (elm); \ - (listelm)->field.cqe_prev = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ - (elm)->field.cqe_next = (head)->cqh_first; \ - (elm)->field.cqe_prev = (void *)(head); \ - if ((head)->cqh_last == (void *)(head)) \ - (head)->cqh_last = (elm); \ - else \ - (head)->cqh_first->field.cqe_prev = (elm); \ - (head)->cqh_first = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ - (elm)->field.cqe_next = (void *)(head); \ - (elm)->field.cqe_prev = (head)->cqh_last; \ - if ((head)->cqh_first == (void *)(head)) \ - (head)->cqh_first = (elm); \ - else \ - (head)->cqh_last->field.cqe_next = (elm); \ - (head)->cqh_last = (elm); \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_REMOVE(head, elm, field) do { \ - if ((elm)->field.cqe_next == (void *)(head)) \ - (head)->cqh_last = (elm)->field.cqe_prev; \ - else \ - (elm)->field.cqe_next->field.cqe_prev = \ - (elm)->field.cqe_prev; \ - if ((elm)->field.cqe_prev == (void *)(head)) \ - (head)->cqh_first = (elm)->field.cqe_next; \ - else \ - (elm)->field.cqe_prev->field.cqe_next = \ - (elm)->field.cqe_next; \ -} while (/*CONSTCOND*/0) - -#define CIRCLEQ_FOREACH(var, head, field) \ - for ((var) = ((head)->cqh_first); \ - (var) != (const void *)(head); \ - (var) = ((var)->field.cqe_next)) - -#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \ - for ((var) = ((head)->cqh_last); \ - (var) != (const void *)(head); \ - (var) = ((var)->field.cqe_prev)) - -/* - * Circular queue access methods. - */ -#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) -#define CIRCLEQ_FIRST(head) ((head)->cqh_first) -#define CIRCLEQ_LAST(head) ((head)->cqh_last) -#define CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) -#define CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) - -#define CIRCLEQ_LOOP_NEXT(head, elm, field) \ - (((elm)->field.cqe_next == (void *)(head)) \ - ? ((head)->cqh_first) \ - : (elm->field.cqe_next)) -#define CIRCLEQ_LOOP_PREV(head, elm, field) \ - (((elm)->field.cqe_prev == (void *)(head)) \ - ? ((head)->cqh_last) \ - : (elm->field.cqe_prev)) - -#endif /* sys/queue.h */ diff --git a/openair3/UTILS/tree.h b/openair3/UTILS/tree.h deleted file mode 100644 index 351df9dfc5..0000000000 --- a/openair3/UTILS/tree.h +++ /dev/null @@ -1,678 +0,0 @@ -/* - * Copyright 2002 Niels Provos - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _SYS_TREE_H_ -#define _SYS_TREE_H_ - -/* - * This file defines data structures for different types of trees: - * splay trees and red-black trees. - * - * A splay tree is a self-organizing data structure. Every operation - * on the tree causes a splay to happen. The splay moves the requested - * node to the root of the tree and partly rebalances it. - * - * This has the benefit that request locality causes faster lookups as - * the requested nodes move to the top of the tree. On the other hand, - * every lookup causes memory writes. - * - * The Balance Theorem bounds the total access time for m operations - * and n inserts on an initially empty tree as O((m + n)lg n). The - * amortized cost for a sequence of m accesses to a splay tree is O(lg n); - * - * A red-black tree is a binary search tree with the node color as an - * extra attribute. It fulfills a set of conditions: - * - every search path from the root to a leaf consists of the - * same number of black nodes, - * - each red node (except for the root) has a black parent, - * - each leaf node is black. - * - * Every operation on a red-black tree is bounded as O(lg n). - * The maximum height of a red-black tree is 2lg (n+1). - */ - -#define SPLAY_HEAD(name, type) \ -struct name { \ - struct type *sph_root; /* root of the tree */ \ -} - -#define SPLAY_INITIALIZER(root) \ - { NULL } - -#define SPLAY_INIT(root) do { \ - (root)->sph_root = NULL; \ -} while (0) - -#define SPLAY_ENTRY(type) \ -struct { \ - struct type *spe_left; /* left element */ \ - struct type *spe_right; /* right element */ \ -} - -#define SPLAY_LEFT(elm, field) (elm)->field.spe_left -#define SPLAY_RIGHT(elm, field) (elm)->field.spe_right -#define SPLAY_ROOT(head) (head)->sph_root -#define SPLAY_EMPTY(head) (SPLAY_ROOT(head) == NULL) - -/* SPLAY_ROTATE_{LEFT,RIGHT} expect that tmp hold SPLAY_{RIGHT,LEFT} */ -#define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \ - SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \ - SPLAY_RIGHT(tmp, field) = (head)->sph_root; \ - (head)->sph_root = tmp; \ -} while (0) - -#define SPLAY_ROTATE_LEFT(head, tmp, field) do { \ - SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \ - SPLAY_LEFT(tmp, field) = (head)->sph_root; \ - (head)->sph_root = tmp; \ -} while (0) - -#define SPLAY_LINKLEFT(head, tmp, field) do { \ - SPLAY_LEFT(tmp, field) = (head)->sph_root; \ - tmp = (head)->sph_root; \ - (head)->sph_root = SPLAY_LEFT((head)->sph_root, field); \ -} while (0) - -#define SPLAY_LINKRIGHT(head, tmp, field) do { \ - SPLAY_RIGHT(tmp, field) = (head)->sph_root; \ - tmp = (head)->sph_root; \ - (head)->sph_root = SPLAY_RIGHT((head)->sph_root, field); \ -} while (0) - -#define SPLAY_ASSEMBLE(head, node, left, right, field) do { \ - SPLAY_RIGHT(left, field) = SPLAY_LEFT((head)->sph_root, field); \ - SPLAY_LEFT(right, field) = SPLAY_RIGHT((head)->sph_root, field);\ - SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(node, field); \ - SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(node, field); \ -} while (0) - -/* Generates prototypes and inline functions */ - -#define SPLAY_PROTOTYPE(name, type, field, cmp) \ -void name##_SPLAY(struct name *, struct type *); \ -void name##_SPLAY_MINMAX(struct name *, int); \ -struct type *name##_SPLAY_INSERT(struct name *, struct type *); \ -struct type *name##_SPLAY_REMOVE(struct name *, struct type *); \ - \ -/* Finds the node with the same key as elm */ \ -static __inline struct type * \ -name##_SPLAY_FIND(struct name *head, struct type *elm) \ -{ \ - if (SPLAY_EMPTY(head)) \ - return(NULL); \ - name##_SPLAY(head, elm); \ - if ((cmp)(elm, (head)->sph_root) == 0) \ - return (head->sph_root); \ - return (NULL); \ -} \ - \ -static __inline struct type * \ -name##_SPLAY_NEXT(struct name *head, struct type *elm) \ -{ \ - name##_SPLAY(head, elm); \ - if (SPLAY_RIGHT(elm, field) != NULL) { \ - elm = SPLAY_RIGHT(elm, field); \ - while (SPLAY_LEFT(elm, field) != NULL) { \ - elm = SPLAY_LEFT(elm, field); \ - } \ - } else \ - elm = NULL; \ - return (elm); \ -} \ - \ -static __inline struct type * \ -name##_SPLAY_MIN_MAX(struct name *head, int val) \ -{ \ - name##_SPLAY_MINMAX(head, val); \ - return (SPLAY_ROOT(head)); \ -} - -/* Main splay operation. - * Moves node close to the key of elm to top - */ -#define SPLAY_GENERATE(name, type, field, cmp) \ -struct type * \ -name##_SPLAY_INSERT(struct name *head, struct type *elm) \ -{ \ - if (SPLAY_EMPTY(head)) { \ - SPLAY_LEFT(elm, field) = SPLAY_RIGHT(elm, field) = NULL; \ - } else { \ - int __comp; \ - name##_SPLAY(head, elm); \ - __comp = (cmp)(elm, (head)->sph_root); \ - if(__comp < 0) { \ - SPLAY_LEFT(elm, field) = SPLAY_LEFT((head)->sph_root, field);\ - SPLAY_RIGHT(elm, field) = (head)->sph_root; \ - SPLAY_LEFT((head)->sph_root, field) = NULL; \ - } else if (__comp > 0) { \ - SPLAY_RIGHT(elm, field) = SPLAY_RIGHT((head)->sph_root, field);\ - SPLAY_LEFT(elm, field) = (head)->sph_root; \ - SPLAY_RIGHT((head)->sph_root, field) = NULL; \ - } else \ - return ((head)->sph_root); \ - } \ - (head)->sph_root = (elm); \ - return (NULL); \ -} \ - \ -struct type * \ -name##_SPLAY_REMOVE(struct name *head, struct type *elm) \ -{ \ - struct type *__tmp; \ - if (SPLAY_EMPTY(head)) \ - return (NULL); \ - name##_SPLAY(head, elm); \ - if ((cmp)(elm, (head)->sph_root) == 0) { \ - if (SPLAY_LEFT((head)->sph_root, field) == NULL) { \ - (head)->sph_root = SPLAY_RIGHT((head)->sph_root, field);\ - } else { \ - __tmp = SPLAY_RIGHT((head)->sph_root, field); \ - (head)->sph_root = SPLAY_LEFT((head)->sph_root, field);\ - name##_SPLAY(head, elm); \ - SPLAY_RIGHT((head)->sph_root, field) = __tmp; \ - } \ - return (elm); \ - } \ - return (NULL); \ -} \ - \ -void \ -name##_SPLAY(struct name *head, struct type *elm) \ -{ \ - struct type __node, *__left, *__right, *__tmp; \ - int __comp; \ -\ - SPLAY_LEFT(&__node, field) = SPLAY_RIGHT(&__node, field) = NULL;\ - __left = __right = &__node; \ -\ - while ((__comp = (cmp)(elm, (head)->sph_root))) { \ - if (__comp < 0) { \ - __tmp = SPLAY_LEFT((head)->sph_root, field); \ - if (__tmp == NULL) \ - break; \ - if ((cmp)(elm, __tmp) < 0){ \ - SPLAY_ROTATE_RIGHT(head, __tmp, field); \ - if (SPLAY_LEFT((head)->sph_root, field) == NULL)\ - break; \ - } \ - SPLAY_LINKLEFT(head, __right, field); \ - } else if (__comp > 0) { \ - __tmp = SPLAY_RIGHT((head)->sph_root, field); \ - if (__tmp == NULL) \ - break; \ - if ((cmp)(elm, __tmp) > 0){ \ - SPLAY_ROTATE_LEFT(head, __tmp, field); \ - if (SPLAY_RIGHT((head)->sph_root, field) == NULL)\ - break; \ - } \ - SPLAY_LINKRIGHT(head, __left, field); \ - } \ - } \ - SPLAY_ASSEMBLE(head, &__node, __left, __right, field); \ -} \ - \ -/* Splay with either the minimum or the maximum element \ - * Used to find minimum or maximum element in tree. \ - */ \ -void name##_SPLAY_MINMAX(struct name *head, int __comp) \ -{ \ - struct type __node, *__left, *__right, *__tmp; \ -\ - SPLAY_LEFT(&__node, field) = SPLAY_RIGHT(&__node, field) = NULL;\ - __left = __right = &__node; \ -\ - while (1) { \ - if (__comp < 0) { \ - __tmp = SPLAY_LEFT((head)->sph_root, field); \ - if (__tmp == NULL) \ - break; \ - if (__comp < 0){ \ - SPLAY_ROTATE_RIGHT(head, __tmp, field); \ - if (SPLAY_LEFT((head)->sph_root, field) == NULL)\ - break; \ - } \ - SPLAY_LINKLEFT(head, __right, field); \ - } else if (__comp > 0) { \ - __tmp = SPLAY_RIGHT((head)->sph_root, field); \ - if (__tmp == NULL) \ - break; \ - if (__comp > 0) { \ - SPLAY_ROTATE_LEFT(head, __tmp, field); \ - if (SPLAY_RIGHT((head)->sph_root, field) == NULL)\ - break; \ - } \ - SPLAY_LINKRIGHT(head, __left, field); \ - } \ - } \ - SPLAY_ASSEMBLE(head, &__node, __left, __right, field); \ -} - -#define SPLAY_NEGINF -1 -#define SPLAY_INF 1 - -#define SPLAY_INSERT(name, x, y) name##_SPLAY_INSERT(x, y) -#define SPLAY_REMOVE(name, x, y) name##_SPLAY_REMOVE(x, y) -#define SPLAY_FIND(name, x, y) name##_SPLAY_FIND(x, y) -#define SPLAY_NEXT(name, x, y) name##_SPLAY_NEXT(x, y) -#define SPLAY_MIN(name, x) (SPLAY_EMPTY(x) ? NULL \ - : name##_SPLAY_MIN_MAX(x, SPLAY_NEGINF)) -#define SPLAY_MAX(name, x) (SPLAY_EMPTY(x) ? NULL \ - : name##_SPLAY_MIN_MAX(x, SPLAY_INF)) - -#define SPLAY_FOREACH(x, name, head) \ - for ((x) = SPLAY_MIN(name, head); \ - (x) != NULL; \ - (x) = SPLAY_NEXT(name, head, x)) - -/* Macros that define a red-back tree */ -#define RB_HEAD(name, type) \ -struct name { \ - struct type *rbh_root; /* root of the tree */ \ -} - -#define RB_INITIALIZER(root) \ - { NULL } - -#define RB_INIT(root) do { \ - (root)->rbh_root = NULL; \ -} while (0) - -#define RB_BLACK 0 -#define RB_RED 1 -#define RB_ENTRY(type) \ -struct { \ - struct type *rbe_left; /* left element */ \ - struct type *rbe_right; /* right element */ \ - struct type *rbe_parent; /* parent element */ \ - int rbe_color; /* node color */ \ -} - -#define RB_LEFT(elm, field) (elm)->field.rbe_left -#define RB_RIGHT(elm, field) (elm)->field.rbe_right -#define RB_PARENT(elm, field) (elm)->field.rbe_parent -#define RB_COLOR(elm, field) (elm)->field.rbe_color -#define RB_ROOT(head) (head)->rbh_root -#define RB_EMPTY(head) (RB_ROOT(head) == NULL) - -#define RB_SET(elm, parent, field) do { \ - RB_PARENT(elm, field) = parent; \ - RB_LEFT(elm, field) = RB_RIGHT(elm, field) = NULL; \ - RB_COLOR(elm, field) = RB_RED; \ -} while (0) - -#define RB_SET_BLACKRED(black, red, field) do { \ - RB_COLOR(black, field) = RB_BLACK; \ - RB_COLOR(red, field) = RB_RED; \ -} while (0) - -#ifndef RB_AUGMENT -#define RB_AUGMENT(x) -#endif - -#define RB_ROTATE_LEFT(head, elm, tmp, field) do { \ - (tmp) = RB_RIGHT(elm, field); \ - if ((RB_RIGHT(elm, field) = RB_LEFT(tmp, field))) { \ - RB_PARENT(RB_LEFT(tmp, field), field) = (elm); \ - } \ - RB_AUGMENT(elm); \ - if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \ - if ((elm) == RB_LEFT(RB_PARENT(elm, field), field)) \ - RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \ - else \ - RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \ - } else \ - (head)->rbh_root = (tmp); \ - RB_LEFT(tmp, field) = (elm); \ - RB_PARENT(elm, field) = (tmp); \ - RB_AUGMENT(tmp); \ - if ((RB_PARENT(tmp, field))) \ - RB_AUGMENT(RB_PARENT(tmp, field)); \ -} while (0) - -#define RB_ROTATE_RIGHT(head, elm, tmp, field) do { \ - (tmp) = RB_LEFT(elm, field); \ - if ((RB_LEFT(elm, field) = RB_RIGHT(tmp, field))) { \ - RB_PARENT(RB_RIGHT(tmp, field), field) = (elm); \ - } \ - RB_AUGMENT(elm); \ - if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \ - if ((elm) == RB_LEFT(RB_PARENT(elm, field), field)) \ - RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \ - else \ - RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \ - } else \ - (head)->rbh_root = (tmp); \ - RB_RIGHT(tmp, field) = (elm); \ - RB_PARENT(elm, field) = (tmp); \ - RB_AUGMENT(tmp); \ - if ((RB_PARENT(tmp, field))) \ - RB_AUGMENT(RB_PARENT(tmp, field)); \ -} while (0) - -/* Generates prototypes and inline functions */ -#define RB_PROTOTYPE(name, type, field, cmp) \ -void name##_RB_INSERT_COLOR(struct name *, struct type *); \ -void name##_RB_REMOVE_COLOR(struct name *, struct type *, struct type *);\ -struct type *name##_RB_REMOVE(struct name *, struct type *); \ -struct type *name##_RB_INSERT(struct name *, struct type *); \ -struct type *name##_RB_FIND(struct name *, struct type *); \ -struct type *name##_RB_NEXT(struct type *); \ -struct type *name##_RB_MINMAX(struct name *, int); \ - \ - -/* Main rb operation. - * Moves node close to the key of elm to top - */ -#define RB_GENERATE(name, type, field, cmp) \ -void \ -name##_RB_INSERT_COLOR(struct name *head, struct type *elm) \ -{ \ - struct type *parent, *gparent, *tmp; \ - while ((parent = RB_PARENT(elm, field)) && \ - RB_COLOR(parent, field) == RB_RED) { \ - gparent = RB_PARENT(parent, field); \ - if (parent == RB_LEFT(gparent, field)) { \ - tmp = RB_RIGHT(gparent, field); \ - if (tmp && RB_COLOR(tmp, field) == RB_RED) { \ - RB_COLOR(tmp, field) = RB_BLACK; \ - RB_SET_BLACKRED(parent, gparent, field);\ - elm = gparent; \ - continue; \ - } \ - if (RB_RIGHT(parent, field) == elm) { \ - RB_ROTATE_LEFT(head, parent, tmp, field);\ - tmp = parent; \ - parent = elm; \ - elm = tmp; \ - } \ - RB_SET_BLACKRED(parent, gparent, field); \ - RB_ROTATE_RIGHT(head, gparent, tmp, field); \ - } else { \ - tmp = RB_LEFT(gparent, field); \ - if (tmp && RB_COLOR(tmp, field) == RB_RED) { \ - RB_COLOR(tmp, field) = RB_BLACK; \ - RB_SET_BLACKRED(parent, gparent, field);\ - elm = gparent; \ - continue; \ - } \ - if (RB_LEFT(parent, field) == elm) { \ - RB_ROTATE_RIGHT(head, parent, tmp, field);\ - tmp = parent; \ - parent = elm; \ - elm = tmp; \ - } \ - RB_SET_BLACKRED(parent, gparent, field); \ - RB_ROTATE_LEFT(head, gparent, tmp, field); \ - } \ - } \ - RB_COLOR(head->rbh_root, field) = RB_BLACK; \ -} \ - \ -void \ -name##_RB_REMOVE_COLOR(struct name *head, struct type *parent, struct type *elm) \ -{ \ - struct type *tmp; \ - while ((elm == NULL || RB_COLOR(elm, field) == RB_BLACK) && \ - elm != RB_ROOT(head)) { \ - if (RB_LEFT(parent, field) == elm) { \ - tmp = RB_RIGHT(parent, field); \ - if (RB_COLOR(tmp, field) == RB_RED) { \ - RB_SET_BLACKRED(tmp, parent, field); \ - RB_ROTATE_LEFT(head, parent, tmp, field);\ - tmp = RB_RIGHT(parent, field); \ - } \ - if ((RB_LEFT(tmp, field) == NULL || \ - RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\ - (RB_RIGHT(tmp, field) == NULL || \ - RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\ - RB_COLOR(tmp, field) = RB_RED; \ - elm = parent; \ - parent = RB_PARENT(elm, field); \ - } else { \ - if (RB_RIGHT(tmp, field) == NULL || \ - RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK) {\ - struct type *oleft; \ - if ((oleft = RB_LEFT(tmp, field)))\ - RB_COLOR(oleft, field) = RB_BLACK;\ - RB_COLOR(tmp, field) = RB_RED; \ - RB_ROTATE_RIGHT(head, tmp, oleft, field);\ - tmp = RB_RIGHT(parent, field); \ - } \ - RB_COLOR(tmp, field) = RB_COLOR(parent, field);\ - RB_COLOR(parent, field) = RB_BLACK; \ - if (RB_RIGHT(tmp, field)) \ - RB_COLOR(RB_RIGHT(tmp, field), field) = RB_BLACK;\ - RB_ROTATE_LEFT(head, parent, tmp, field);\ - elm = RB_ROOT(head); \ - break; \ - } \ - } else { \ - tmp = RB_LEFT(parent, field); \ - if (RB_COLOR(tmp, field) == RB_RED) { \ - RB_SET_BLACKRED(tmp, parent, field); \ - RB_ROTATE_RIGHT(head, parent, tmp, field);\ - tmp = RB_LEFT(parent, field); \ - } \ - if ((RB_LEFT(tmp, field) == NULL || \ - RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\ - (RB_RIGHT(tmp, field) == NULL || \ - RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\ - RB_COLOR(tmp, field) = RB_RED; \ - elm = parent; \ - parent = RB_PARENT(elm, field); \ - } else { \ - if (RB_LEFT(tmp, field) == NULL || \ - RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) {\ - struct type *oright; \ - if ((oright = RB_RIGHT(tmp, field)))\ - RB_COLOR(oright, field) = RB_BLACK;\ - RB_COLOR(tmp, field) = RB_RED; \ - RB_ROTATE_LEFT(head, tmp, oright, field);\ - tmp = RB_LEFT(parent, field); \ - } \ - RB_COLOR(tmp, field) = RB_COLOR(parent, field);\ - RB_COLOR(parent, field) = RB_BLACK; \ - if (RB_LEFT(tmp, field)) \ - RB_COLOR(RB_LEFT(tmp, field), field) = RB_BLACK;\ - RB_ROTATE_RIGHT(head, parent, tmp, field);\ - elm = RB_ROOT(head); \ - break; \ - } \ - } \ - } \ - if (elm) \ - RB_COLOR(elm, field) = RB_BLACK; \ -} \ - \ -struct type * \ -name##_RB_REMOVE(struct name *head, struct type *elm) \ -{ \ - struct type *child, *parent, *old = elm; \ - int color; \ - if (RB_LEFT(elm, field) == NULL) \ - child = RB_RIGHT(elm, field); \ - else if (RB_RIGHT(elm, field) == NULL) \ - child = RB_LEFT(elm, field); \ - else { \ - struct type *left; \ - elm = RB_RIGHT(elm, field); \ - while ((left = RB_LEFT(elm, field))) \ - elm = left; \ - child = RB_RIGHT(elm, field); \ - parent = RB_PARENT(elm, field); \ - color = RB_COLOR(elm, field); \ - if (child) \ - RB_PARENT(child, field) = parent; \ - if (parent) { \ - if (RB_LEFT(parent, field) == elm) \ - RB_LEFT(parent, field) = child; \ - else \ - RB_RIGHT(parent, field) = child; \ - RB_AUGMENT(parent); \ - } else \ - RB_ROOT(head) = child; \ - if (RB_PARENT(elm, field) == old) \ - parent = elm; \ - (elm)->field = (old)->field; \ - if (RB_PARENT(old, field)) { \ - if (RB_LEFT(RB_PARENT(old, field), field) == old)\ - RB_LEFT(RB_PARENT(old, field), field) = elm;\ - else \ - RB_RIGHT(RB_PARENT(old, field), field) = elm;\ - RB_AUGMENT(RB_PARENT(old, field)); \ - } else \ - RB_ROOT(head) = elm; \ - RB_PARENT(RB_LEFT(old, field), field) = elm; \ - if (RB_RIGHT(old, field)) \ - RB_PARENT(RB_RIGHT(old, field), field) = elm; \ - if (parent) { \ - left = parent; \ - do { \ - RB_AUGMENT(left); \ - } while ((left = RB_PARENT(left, field))); \ - } \ - goto color; \ - } \ - parent = RB_PARENT(elm, field); \ - color = RB_COLOR(elm, field); \ - if (child) \ - RB_PARENT(child, field) = parent; \ - if (parent) { \ - if (RB_LEFT(parent, field) == elm) \ - RB_LEFT(parent, field) = child; \ - else \ - RB_RIGHT(parent, field) = child; \ - RB_AUGMENT(parent); \ - } else \ - RB_ROOT(head) = child; \ -color: \ - if (color == RB_BLACK) \ - name##_RB_REMOVE_COLOR(head, parent, child); \ - return (old); \ -} \ - \ -/* Inserts a node into the RB tree */ \ -struct type * \ -name##_RB_INSERT(struct name *head, struct type *elm) \ -{ \ - struct type *tmp; \ - struct type *parent = NULL; \ - int comp = 0; \ - tmp = RB_ROOT(head); \ - while (tmp) { \ - parent = tmp; \ - comp = (cmp)(elm, parent); \ - if (comp < 0) \ - tmp = RB_LEFT(tmp, field); \ - else if (comp > 0) \ - tmp = RB_RIGHT(tmp, field); \ - else \ - return (tmp); \ - } \ - RB_SET(elm, parent, field); \ - if (parent != NULL) { \ - if (comp < 0) \ - RB_LEFT(parent, field) = elm; \ - else \ - RB_RIGHT(parent, field) = elm; \ - RB_AUGMENT(parent); \ - } else \ - { \ - RB_ROOT(head) = elm; \ - } \ - name##_RB_INSERT_COLOR(head, elm); \ - return (NULL); \ -} \ - \ -/* Finds the node with the same key as elm */ \ -struct type * \ -name##_RB_FIND(struct name *head, struct type *elm) \ -{ \ - struct type *tmp = RB_ROOT(head); \ - int comp; \ - while (tmp) { \ - comp = cmp(elm, tmp); \ - if (comp < 0) \ - tmp = RB_LEFT(tmp, field); \ - else if (comp > 0) \ - tmp = RB_RIGHT(tmp, field); \ - else \ - return (tmp); \ - } \ - return (NULL); \ -} \ - \ -struct type * \ -name##_RB_NEXT(struct type *elm) \ -{ \ - if (RB_RIGHT(elm, field)) { \ - elm = RB_RIGHT(elm, field); \ - while (RB_LEFT(elm, field)) \ - elm = RB_LEFT(elm, field); \ - } else { \ - if (RB_PARENT(elm, field) && \ - (elm == RB_LEFT(RB_PARENT(elm, field), field))) \ - elm = RB_PARENT(elm, field); \ - else { \ - while (RB_PARENT(elm, field) && \ - (elm == RB_RIGHT(RB_PARENT(elm, field), field)))\ - elm = RB_PARENT(elm, field); \ - elm = RB_PARENT(elm, field); \ - } \ - } \ - return (elm); \ -} \ - \ -struct type * \ -name##_RB_MINMAX(struct name *head, int val) \ -{ \ - struct type *tmp = RB_ROOT(head); \ - struct type *parent = NULL; \ - while (tmp) { \ - parent = tmp; \ - if (val < 0) \ - tmp = RB_LEFT(tmp, field); \ - else \ - tmp = RB_RIGHT(tmp, field); \ - } \ - return (parent); \ -} - -#define RB_NEGINF -1 -#define RB_INF 1 - -#define RB_INSERT(name, x, y) name##_RB_INSERT(x, y) -#define RB_REMOVE(name, x, y) name##_RB_REMOVE(x, y) -#define RB_FIND(name, x, y) name##_RB_FIND(x, y) -#define RB_NEXT(name, x, y) name##_RB_NEXT(y) -#define RB_MIN(name, x) name##_RB_MINMAX(x, RB_NEGINF) -#define RB_MAX(name, x) name##_RB_MINMAX(x, RB_INF) - -#define RB_FOREACH(x, name, head) \ - for ((x) = RB_MIN(name, head); \ - (x) != NULL; \ - (x) = name##_RB_NEXT(x)) - -#endif /* _SYS_TREE_H_ */ diff --git a/targets/ARCH/COMMON/common_lib.h b/targets/ARCH/COMMON/common_lib.h index ecadb68c0c..d086c0e13a 100644 --- a/targets/ARCH/COMMON/common_lib.h +++ b/targets/ARCH/COMMON/common_lib.h @@ -52,6 +52,9 @@ #define RAU_LOCAL_RADIO_HEAD 0 #define RAU_REMOTE_RADIO_HEAD 1 +#define MAX_WRITE_THREAD_PACKAGE 10 +#define MAX_WRITE_THREAD_BUFFER_SIZE 8 + #ifndef MAX_CARDS #define MAX_CARDS 8 #endif @@ -69,13 +72,9 @@ typedef enum { max_gain=0,med_gain,byp_gain } rx_gain_t; -#if OCP_FRAMEWORK -#include -#else typedef enum { duplex_mode_TDD=1,duplex_mode_FDD=0 } duplex_mode_t; -#endif /** @addtogroup _GENERIC_PHY_RF_INTERFACE_ @@ -275,8 +274,37 @@ typedef struct { void *rx; } if_buffer_t; +typedef struct { + openair0_timestamp timestamp; + void *buff[MAX_WRITE_THREAD_BUFFER_SIZE];// buffer to be write; + int nsamps; + int cc; + signed char first_packet; + signed char last_packet; + int flags_msb; +} openair0_write_package_t; + +typedef struct { + openair0_write_package_t write_package[MAX_WRITE_THREAD_PACKAGE]; + int start; + int end; + /// \internal This variable is protected by \ref mutex_write + int count_write; + /// pthread struct for trx write thread + pthread_t pthread_write; + /// pthread attributes for trx write thread + pthread_attr_t attr_write; + /// condition varible for trx write thread + pthread_cond_t cond_write; + /// mutex for trx write thread + pthread_mutex_t mutex_write; +} openair0_thread_t; + /*!\brief structure holds the parameters to configure USRP devices */ struct openair0_device_t { + /*!tx write thread*/ + openair0_thread_t write_thread; + /*!brief Module ID of this device */ int Mod_id; @@ -400,6 +428,12 @@ struct openair0_device_t { * \param arg pointer to capabilities or configuration */ void (*configure_rru)(int idx, void *arg); + + /*! \brief RRU Configuration callback + * \param idx RU index + * \param arg pointer to capabilities or configuration + */ + int (*trx_write_init)(openair0_device *device); }; /* type of device init function, implemented in shared lib */ diff --git a/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h b/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h index 95d0029027..0f2147847a 100644 --- a/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h +++ b/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h @@ -30,6 +30,9 @@ * \warning */ +#ifndef __ETHERNET_USERSPACE_LIB_IF_DEFS__H__ +#define __ETHERNET_USERSPACE_LIB_IF_DEFS__H__ + #include #include @@ -37,15 +40,11 @@ #include "PHY/LTE_TRANSPORT/if5_tools.h" // ETH transport preference modes -#ifdef OCP_FRAMEWORK -#include "enums.h" -#else #define ETH_UDP_MODE 0 #define ETH_RAW_MODE 1 #define ETH_UDP_IF4p5_MODE 2 #define ETH_RAW_IF4p5_MODE 3 #define ETH_RAW_IF5_MOBIPASS 4 -#endif // COMMOM HEADER LENGTHS @@ -84,3 +83,5 @@ #define RAW_IF5_MOBIPASS_BLOCK_SIZE_BYTES 1280 #define RAW_IF5_MOBIPASS_SIZE_BYTES (MAC_HEADER_SIZE_BYTES + sizeof_IF5_mobipass_header_t + RAW_IF5_MOBIPASS_BLOCK_SIZE_BYTES) #define PAYLOAD_MOBIPASS_NUM_SAMPLES 640 + +#endif diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp index f37c8cf5cf..08f0cd720b 100644 --- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp +++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp @@ -50,6 +50,8 @@ #include "common_lib.h" #include "assertions.h" +#include "common/utils/LOG/vcd_signal_dumper.h" + #include #ifdef __SSE4_1__ @@ -341,37 +343,13 @@ static int trx_usrp_write(openair0_device *device, int flags_lsb = flags&0xff; int flags_msb = (flags>>8)&0xff; - -#if defined(__x86_64) || defined(__i386__) - #ifdef __AVX2__ - nsamps2 = (nsamps+7)>>3; - __m256i buff_tx[8][nsamps2]; - #else - nsamps2 = (nsamps+3)>>2; - __m128i buff_tx[8][nsamps2]; - #endif -#elif defined(__arm__) - nsamps2 = (nsamps+3)>>2; - int16x8_t buff_tx[8][nsamps2]; -#else -#error Unsupported CPU architecture, USRP device cannot be built -#endif - // bring RX data into 12 LSBs for softmodem RX - for (int i=0; iwrite_thread; + openair0_write_package_t *write_package = write_thread->write_package; + AssertFatal( MAX_WRITE_THREAD_BUFFER_SIZE >= cc,"Do not support more than %d cc number\n", MAX_WRITE_THREAD_BUFFER_SIZE); boolean_t first_packet_state=false,last_packet_state=false; @@ -404,7 +382,37 @@ static int trx_usrp_write(openair0_device *device, last_packet_state = true; } - + if(write_tread == 0){ +#if defined(__x86_64) || defined(__i386__) + #ifdef __AVX2__ + nsamps2 = (nsamps+7)>>3; + __m256i buff_tx[8][nsamps2]; + #else + nsamps2 = (nsamps+3)>>2; + __m128i buff_tx[8][nsamps2]; + #endif +#elif defined(__arm__) + nsamps2 = (nsamps+3)>>2; + int16x8_t buff_tx[8][nsamps2]; +#else +#error Unsupported CPU architecture, USRP device cannot be built +#endif + + // bring RX data into 12 LSBs for softmodem RX + for (int i=0; itx_md.has_time_spec = true; s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet_state; s->tx_md.end_of_burst = last_packet_state; @@ -432,11 +440,170 @@ static int trx_usrp_write(openair0_device *device, ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md); } - if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps); + if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps); + return ret; + } + else{ + pthread_mutex_lock(&write_thread->mutex_write); + + if(write_thread->count_write >= MAX_WRITE_THREAD_PACKAGE){ + LOG_W(HW,"Buffer overflow, count_write = %d, start = %d end = %d, resetting write package\n", write_thread->count_write, write_thread->start, write_thread->end); + write_thread->end = write_thread->start; + write_thread->count_write = 0; + } + + end = write_thread->end; + write_package[end].timestamp = timestamp; + write_package[end].nsamps = nsamps; + write_package[end].cc = cc; + write_package[end].first_packet = first_packet_state; + write_package[end].last_packet = last_packet_state; + write_package[end].flags_msb = flags_msb; + for (int i = 0; i < cc; i++) + write_package[end].buff[i] = buff[i]; + write_thread->count_write++; + write_thread->end = (write_thread->end + 1)% MAX_WRITE_THREAD_PACKAGE; + pthread_cond_signal(&write_thread->cond_write); + pthread_mutex_unlock(&write_thread->mutex_write); + return 0; + } - return ret; } +//-----------------------start-------------------------- +/*! \brief Called to send samples to the USRP RF target + @param device pointer to the device structure specific to the RF hardware target + @param timestamp The timestamp at which the first sample MUST be sent + @param buff Buffer which holds the samples + @param nsamps number of samples to be sent + @param antenna_id index of the antenna if the device has multiple antennas + @param flags flags must be set to TRUE if timestamp parameter needs to be applied +*/ +void *trx_usrp_write_thread(void * arg){ + int ret=0; + openair0_device *device=(openair0_device *)arg; + openair0_thread_t *write_thread = &device->write_thread; + openair0_write_package_t *write_package = write_thread->write_package; + + usrp_state_t *s; + int nsamps2; // aligned to upper 32 or 16 byte boundary + int start; + openair0_timestamp timestamp; + void **buff; + int nsamps; + int cc; + signed char first_packet; + signed char last_packet; + int flags_msb; + + while(1){ + pthread_mutex_lock(&write_thread->mutex_write); + while (write_thread->count_write == 0) { + pthread_cond_wait(&write_thread->cond_write,&write_thread->mutex_write); // this unlocks mutex_rxtx while waiting and then locks it again + } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD, 1 ); + s = (usrp_state_t *)device->priv; + start = write_thread->start; + timestamp = write_package[start].timestamp; + buff = write_package[start].buff; + nsamps = write_package[start].nsamps; + cc = write_package[start].cc; + first_packet = write_package[start].first_packet; + last_packet = write_package[start].last_packet; + flags_msb = write_package[start].flags_msb; + write_thread->start = (write_thread->start + 1)% MAX_WRITE_THREAD_PACKAGE; + write_thread->count_write--; + pthread_mutex_unlock(&write_thread->mutex_write); + /*if(write_thread->count_write != 0){ + LOG_W(HW,"count write = %d, start = %d, end = %d\n", write_thread->count_write, write_thread->start, write_thread->end); + }*/ + + #if defined(__x86_64) || defined(__i386__) + #ifdef __AVX2__ + nsamps2 = (nsamps+7)>>3; + __m256i buff_tx[8][nsamps2]; + #else + nsamps2 = (nsamps+3)>>2; + __m128i buff_tx[8][nsamps2]; + #endif + #elif defined(__arm__) + nsamps2 = (nsamps+3)>>2; + int16x8_t buff_tx[8][nsamps2]; + #else + #error Unsupported CPU architecture, USRP device cannot be built + #endif + + // bring RX data into 12 LSBs for softmodem RX + for (int i=0; itx_md.has_time_spec = true; + s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet; + s->tx_md.end_of_burst = last_packet; + s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate); + s->tx_count++; + + // bit 3 enables gpio (for backward compatibility) + if (flags_msb&8) { + // push GPIO bits 7-9 from flags_msb + int gpio789=(flags_msb&7)<<7; + s->usrp->set_command_time(s->tx_md.time_spec); + s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380); + s->usrp->clear_command_time(); + } + + if (cc>1) { + std::vector buff_ptrs; + + for (int i=0; itx_stream->send(buff_ptrs, nsamps, s->tx_md); + } + else { + ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md); + } + + if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps); + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_USRP_SEND_RETURN, ret ); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD, 0 ); + + if(0) break; + } + + return NULL; +} + +int trx_write_init(openair0_device *device){ + + uhd::set_thread_priority_safe(1.0); + openair0_thread_t *write_thread = &device->write_thread; + printf("initializing tx write thread\n"); + + write_thread->start = 0; + write_thread->end = 0; + write_thread->count_write = 0; + printf("end of tx write thread\n"); + + pthread_create(&write_thread->pthread_write,NULL,trx_usrp_write_thread,(void *)device); + + return(0); +} + +//---------------------end------------------------- + /*! \brief Receive samples from hardware. * Read \ref nsamps samples from each channel to buffers. buff[0] is the array for * the first channel. *ptimestamp is the time at which the first sample @@ -765,6 +932,7 @@ extern "C" { device->trx_stop_func = trx_usrp_stop; device->trx_set_freq_func = trx_usrp_set_freq; device->trx_set_gains_func = trx_usrp_set_gains; + device->trx_write_init = trx_write_init; // hotfix! to be checked later @@ -835,22 +1003,16 @@ extern "C" { if (args.find("clock_source")==std::string::npos) { if (openair0_cfg[0].clock_source == internal) { - //in UHD 3.14 we could use - //s->usrp->set_sync_source("clock_source=internal","time_source=internal"); - s->usrp->set_time_source("internal"); s->usrp->set_clock_source("internal"); - LOG_D(HW,"Setting time and clock source to internal\n"); + LOG_D(HW,"Setting clock source to internal\n"); } else if (openair0_cfg[0].clock_source == external ) { - //s->usrp->set_sync_source("clock_source=external","time_source=external"); - s->usrp->set_time_source("external"); s->usrp->set_clock_source("external"); - LOG_D(HW,"Setting time and clock source to external\n"); + LOG_D(HW,"Setting clock source to external\n"); } else if (openair0_cfg[0].clock_source==gpsdo) { s->usrp->set_clock_source("gpsdo"); - s->usrp->set_time_source("gpsdo"); - LOG_D(HW,"Setting time and clock source to gpsdo\n"); + LOG_D(HW,"Setting clock source to gpsdo\n"); } else { LOG_W(HW,"Clock source set neither in usrp_args nor on command line, using default!\n"); @@ -861,7 +1023,31 @@ extern "C" { LOG_W(HW,"Clock source set in both usrp_args and in clock_source, ingnoring the latter!\n"); } } - + + if (args.find("time_source")==std::string::npos) { + if (openair0_cfg[0].time_source == internal) { + s->usrp->set_time_source("internal"); + LOG_D(HW,"Setting time source to internal\n"); + } + else if (openair0_cfg[0].time_source == external ) { + s->usrp->set_time_source("external"); + LOG_D(HW,"Setting time source to external\n"); + } + else if (openair0_cfg[0].time_source==gpsdo) { + s->usrp->set_time_source("gpsdo"); + LOG_D(HW,"Setting time source to gpsdo\n"); + } + else { + LOG_W(HW,"Time source set neither in usrp_args nor on command line, using default!\n"); + } + } + else { + if (openair0_cfg[0].clock_source != unset) { + LOG_W(HW,"Time source set in both usrp_args and in time_source, ingnoring the latter!\n"); + } + } + + if (s->usrp->get_clock_source(0) == "gpsdo") { s->use_gps = 1; @@ -1061,7 +1247,9 @@ extern "C" { //s->usrp->set_time_source("external"); // display USRP settings LOG_I(HW,"Actual master clock: %fMHz...\n",s->usrp->get_master_clock_rate()/1e6); - sleep(1); + LOG_I(HW,"Actual clock source %s...\n",s->usrp->get_clock_source(0).c_str()); + LOG_I(HW,"Actual time source %s...\n",s->usrp->get_time_source(0).c_str()); + sleep(1); // create tx & rx streamer uhd::stream_args_t stream_args_rx("sc16", "sc16"); int samples=openair0_cfg[0].sample_rate; diff --git a/targets/ARCH/rfsimulator/README.md b/targets/ARCH/rfsimulator/README.md index e3ce219d73..421cc662bb 100644 --- a/targets/ARCH/rfsimulator/README.md +++ b/targets/ARCH/rfsimulator/README.md @@ -3,6 +3,12 @@ This is an RF simulator that allows to test OAI without an RF board. It replaces As much as possible, it works like an RF board, but not in real-time: It can run faster than real-time if there is enough CPU, or slower (it is CPU-bound instead of real-time RF sampling-bound). +It can be run either in: + +- "noS1" mode: the generated IP traffic is sent and received between gNB and UE IP tunnel interfaces ("oaitun") by applications like ping and iperf +- "phy-test" mode: random UL and DL traffic is generated at every scheduling opportunity + + # build ## From [build_oai](../../../doc/BUILD.md) script @@ -84,19 +90,40 @@ make rfsimulator ### Launch gNB in one window ```bash -sudo RFSIMULATOR=server ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf --parallel-config PARALLEL_SINGLE_THREAD +sudo RFSIMULATOR=server ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf --parallel-config PARALLEL_SINGLE_THREAD --rfsim --phy-test ``` ### Launch UE in another window ```bash -sudo RFSIMULATOR=127.0.0.1 ./nr-uesoftmodem --numerology 1 -r 106 -C 3510000000 +sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path ../../../ci-scripts/rrc-files ``` +Note: +1. can be 127.0.0.1 if both gNB and nrUE executables run on the same host, OR the IP interface address of the remote host running the gNB executable, if the gNB and nrUE run on separate hosts +2. the --rrc_config_path parameter can be omitted (but not necessarily) if the gNB and nrUE run on the same host, in which case the gNB provides the nrUE with the necessary rrc configuration +3. to enable the noS1 mode --noS1 and --nokrnmod 1 options should be added to the command line -Of course, set the gNB machine IP address if the UE and the gNB are not on the same machine. In the UE, you can add `-d` option to get the softscope. +### Testing IP traffic (ping and iperf) + +``` +ping -I oaitun_enb1 10.0.1.2 (from gNB mchine) +ping -I oaitun_ue1 10.0.1.1 (from nrUE mchine) +``` + +```iperf (Downlink): +Server nrUE machine: iperf -s -i 1 -u -B 10.0.1.2 +Client gNB machine: iperf -c 10.0.1.2 -u -b 0.1M --bind 10.0.1.1 +``` + +```iperf (Uplink): +Server gNB machine: iperf -s -i 1 -u -B 10.0.1.1 +Client nrUE machine: iperf -c 10.0.1.1 -u -b 0.1M --bind 10.0.1.2 +Note: iperf tests can be performed only when running gNB and nrUE on separate hosts. +``` + ### Store and replay You can store emitted I/Q samples. If you set the option `saviq`, the simulator will write all the I/Q samples into this file. Then, you can replay with the executable `replay_node`. diff --git a/targets/ARCH/rfsimulator/apply_channelmod.c b/targets/ARCH/rfsimulator/apply_channelmod.c index ef4e564343..faf84bb0aa 100644 --- a/targets/ARCH/rfsimulator/apply_channelmod.c +++ b/targets/ARCH/rfsimulator/apply_channelmod.c @@ -1,7 +1,24 @@ /* - Author: Laurent THOMAS, Open Cells for Nokia - copyleft: OpenAirInterface Software Alliance and it's licence - +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index 54dfd3b888..222a3e9f80 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -1,8 +1,27 @@ /* - Author: Laurent THOMAS, Open Cells for Nokia - copyleft: OpenAirInterface Software Alliance and it's licence +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + /* * Open issues and limitations * The read and write should be called in the same thread, that is not new USRP UHD design @@ -33,7 +52,7 @@ #include #define PORT 4043 //default TCP port for this simulator -#define CirSize 3072000 // 100ms is enough +#define CirSize 307200 // 100ms is enough #define sampleToByte(a,b) ((a)*(b)*sizeof(sample_t)) #define byteToSample(a,b) ((a)/(sizeof(sample_t)*(b))) @@ -346,7 +365,8 @@ static int rfsimulator_write_internal(rfsimulator_state_t *t, openair0_timestamp if ( t->lastWroteTS != 0 && abs((double)t->lastWroteTS-timestamp) > (double)CirSize) LOG_E(HW,"Discontinuous TX gap too large Tx:%lu, %lu\n", t->lastWroteTS, timestamp); - AssertFatal(t->lastWroteTS <= timestamp+1, " Not supported to send Tx out of order (same in USRP) %lu, %lu\n", + if (t->lastWroteTS > timestamp+nsamps) + LOG_E(HW,"Not supported to send Tx out of order (same in USRP) %lu, %lu\n", t->lastWroteTS, timestamp); t->lastWroteTS=timestamp+nsamps; @@ -420,7 +440,7 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi if ( sz < 0 ) { if ( errno != EAGAIN ) { LOG_E(HW,"socket failed %s\n", strerror(errno)); - abort(); + //abort(); } } else if ( sz == 0 ) continue; @@ -439,11 +459,15 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi b->headerMode=false; if ( t->nextTimestamp == 0 ) { // First block in UE, resync with the eNB current TS - t->nextTimestamp = b->th.timestamp > nsamps_for_initial ? b->th.timestamp - nsamps_for_initial : 0; - b->lastReceivedTS = b->th.timestamp > nsamps_for_initial ? b->th.timestamp : nsamps_for_initial; - LOG_W(HW,"UE got first timestamp: starting at %lu\n", t->nextTimestamp); - b->trashingPacket=true; - } else if ( b->lastReceivedTS < b->th.timestamp) { + t->nextTimestamp=b->th.timestamp> nsamps_for_initial ? + b->th.timestamp - nsamps_for_initial : + 0; + b->lastReceivedTS=b->th.timestamp> nsamps_for_initial ? + b->th.timestamp : + nsamps_for_initial; + LOG_W(HW,"UE got first timestamp: starting at %lu\n", t->nextTimestamp); + b->trashingPacket=true; + } else if ( b->lastReceivedTS < b->th.timestamp) { int nbAnt= b->th.nbAnt; for (uint64_t index=b->lastReceivedTS; index < b->th.timestamp; index++ ) { @@ -463,8 +487,8 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi } else if ( b->lastReceivedTS == b->th.timestamp ) { // normal case } else { - abort(); - AssertFatal(false, "received data in past: current is %lu, new reception: %lu!\n", b->lastReceivedTS, b->th.timestamp); + LOG_E(HW, "received data in past: current is %lu, new reception: %lu!\n", b->lastReceivedTS, b->th.timestamp); + b->trashingPacket=true; } pthread_mutex_lock(&Sockmutex); @@ -655,6 +679,9 @@ int rfsimulator_set_freq(openair0_device *device, openair0_config_t *openair0_cf int rfsimulator_set_gains(openair0_device *device, openair0_config_t *openair0_cfg) { return 0; } +int rfsimulator_write_init(openair0_device *device){ + return 0; +} __attribute__((__visibility__("default"))) int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { // to change the log level, use this on command line @@ -678,6 +705,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { device->type = USRP_B200_DEV; device->openair0_cfg=&openair0_cfg[0]; device->priv = rfsimulator; + device->trx_write_init = rfsimulator_write_init; for (int i=0; ibuf[i].conn_sock=-1; diff --git a/targets/ARCH/rfsimulator/stored_node.c b/targets/ARCH/rfsimulator/stored_node.c index 2b77c5322d..73f6321ffe 100644 --- a/targets/ARCH/rfsimulator/stored_node.c +++ b/targets/ARCH/rfsimulator/stored_node.c @@ -1,8 +1,27 @@ /* - Author: Laurent THOMAS, Open Cells - copyleft: OpenAirInterface Software Alliance and it's licence +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org */ + #include volatile int oai_exit = 0; diff --git a/targets/COMMON/create_tasks.c b/targets/COMMON/create_tasks.c index cbbd30b62c..4d57ab4e16 100644 --- a/targets/COMMON/create_tasks.c +++ b/targets/COMMON/create_tasks.c @@ -41,6 +41,7 @@ # include "f1ap_du_task.h" # include "enb_app.h" # include "openair2/LAYER2/MAC/mac_proto.h" +#include extern RAN_CONTEXT_t RC; @@ -59,12 +60,12 @@ int create_tasks(uint32_t enb_nb) { rc = itti_create_task (TASK_RRC_ENB, rrc_enb_task, NULL); AssertFatal(rc >= 0, "Create task for RRC eNB failed\n"); - if (EPC_MODE_ENABLED) { + if (EPC_MODE_ENABLED && ! ( split73==SPLIT73_DU ) ) { rc = itti_create_task(TASK_SCTP, sctp_eNB_task, NULL); AssertFatal(rc >= 0, "Create task for SCTP failed\n"); } - if (EPC_MODE_ENABLED && !NODE_IS_DU(type)) { + if (EPC_MODE_ENABLED && !NODE_IS_DU(type) && ! ( split73==SPLIT73_DU ) ) { rc = itti_create_task(TASK_S1AP, s1ap_eNB_task, NULL); AssertFatal(rc >= 0, "Create task for S1AP failed\n"); if (!(get_softmodem_params()->emulate_rf)){ diff --git a/targets/COMMON/create_tasks_mbms.h b/targets/COMMON/create_tasks_mbms.h deleted file mode 100644 index 843897cefb..0000000000 --- a/targets/COMMON/create_tasks_mbms.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -#ifndef CREATE_TASKS_H_ -#define CREATE_TASKS_H_ - -/* External declaration of L2L1 task that depend on the target */ -extern void *l2l1_task(void *arg); - -int create_tasks(uint32_t enb_nb); -int create_tasks_ue(uint32_t ue_nb); -int create_tasks_mbms(uint32_t enb_nb); - -#endif /* CREATE_TASKS_H_ */ diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index 904a455600..fed15739cf 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -237,8 +237,8 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2"; - #clock_src = "external"; + sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2,second_addr=192.168.20.2"; + clock_src = "external"; } ); diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf index f5e2298a99..08bfeea7ee 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf @@ -237,7 +237,7 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2"; + sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2,second_addr=192.168.20.2"; clock_src = "external"; } ); diff --git a/targets/RT/USER/gNB_usrp.gtkw b/targets/RT/USER/gNB_usrp.gtkw index e6726e7d9f..6ece894bb6 100644 --- a/targets/RT/USER/gNB_usrp.gtkw +++ b/targets/RT/USER/gNB_usrp.gtkw @@ -1,21 +1,25 @@ [*] [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI -[*] Tue Dec 17 15:31:51 2019 +[*] Wed Mar 4 14:05:43 2020 [*] -[dumpfile] "/tmp/gNB.vcd" -[dumpfile_mtime] "Tue Dec 17 15:25:49 2019" -[dumpfile_size] 6343431 +[dumpfile] "/tmp/gNB_trx_thread.vcd" +[dumpfile_mtime] "Wed Mar 4 14:05:10 2020" +[dumpfile_size] 10750468 [savefile] "/home/wangts/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw" -[timestart] 1517712000 -[size] 1920 1018 -[pos] -9 -33 -*-19.276148 1518358451 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[timestart] 31148700000 +[size] 1916 1002 +[pos] -1 -25 +*-23.852516 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [sst_width] 386 [signals_width] 344 [sst_expanded] 1 -[sst_vpaned_height] 267 +[sst_vpaned_height] 262 @28 functions.trx_read +functions.trx_write_thread +@25 +variables.trx_write_flags[63:0] +@28 functions.trx_write @420 variables.frame_number_TX0_UE[63:0] diff --git a/targets/RT/USER/lte-enb.c b/targets/RT/USER/lte-enb.c index 8c5c50836f..147bc955ae 100644 --- a/targets/RT/USER/lte-enb.c +++ b/targets/RT/USER/lte-enb.c @@ -235,10 +235,10 @@ static inline int rxtx(PHY_VARS_eNB *eNB, new_dlsch_ue_select_tbl_in_use = dlsch_ue_select_tbl_in_use; dlsch_ue_select_tbl_in_use = !dlsch_ue_select_tbl_in_use; // L2-emulator can work only one eNB. - // memcpy(&pre_scd_eNB_UE_stats,&RC.mac[ru->eNB_list[0]->Mod_id]->UE_list.eNB_UE_stats, sizeof(eNB_UE_STATS)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); - // memcpy(&pre_scd_activeUE, &RC.mac[ru->eNB_list[0]->Mod_id]->UE_list.active, sizeof(boolean_t)*NUMBER_OF_UE_MAX); - memcpy(&pre_scd_eNB_UE_stats,&RC.mac[0]->UE_list.eNB_UE_stats, sizeof(eNB_UE_STATS)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); - memcpy(&pre_scd_activeUE, &RC.mac[0]->UE_list.active, sizeof(boolean_t)*NUMBER_OF_UE_MAX); + // memcpy(&pre_scd_eNB_UE_stats,&RC.mac[ru->eNB_list[0]->Mod_id]->UE_info.eNB_UE_stats, sizeof(eNB_UE_STATS)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); + // memcpy(&pre_scd_activeUE, &RC.mac[ru->eNB_list[0]->Mod_id]->UE_info.active, sizeof(boolean_t)*NUMBER_OF_UE_MAX); + memcpy(&pre_scd_eNB_UE_stats,&RC.mac[0]->UE_info.eNB_UE_stats, sizeof(eNB_UE_STATS)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); + memcpy(&pre_scd_activeUE, &RC.mac[0]->UE_info.active, sizeof(boolean_t)*NUMBER_OF_UE_MAX); AssertFatal((ret= pthread_mutex_lock(&ru->proc.mutex_pre_scd))==0,"[eNB] error locking proc mutex for eNB pre scd, return %d\n",ret); ru->proc.instance_pre_scd++; @@ -261,7 +261,7 @@ static inline int rxtx(PHY_VARS_eNB *eNB, eNB->UL_INFO.subframe = proc->subframe_rx; eNB->UL_INFO.module_id = eNB->Mod_id; eNB->UL_INFO.CC_id = eNB->CC_id; - eNB->if_inst->UL_indication(&eNB->UL_INFO); + eNB->if_inst->UL_indication(&eNB->UL_INFO, proc); AssertFatal((ret= pthread_mutex_unlock(&eNB->UL_INFO_mutex))==0,"error unlocking UL_INFO_mutex, return %d\n",ret); /* this conflict resolution may be totally wrong, to be tested */ /* CONFLICT RESOLUTION: BEGIN */ @@ -851,9 +851,7 @@ void init_eNB_proc(int inst) { for (CC_id=0; CC_idproc; L1_proc = &proc->L1_proc; L1_proc_tx = &proc->L1_proc_tx; @@ -1247,9 +1245,7 @@ void init_eNB(int single_thread_flag, eNB->abstraction_flag = 0; eNB->single_thread_flag = single_thread_flag; LOG_I(PHY,"Initializing eNB %d CC_id %d single_thread_flag:%d\n",inst,CC_id,single_thread_flag); -#ifndef OCP_FRAMEWORK LOG_I(PHY,"Initializing eNB %d CC_id %d\n",inst,CC_id); -#endif LOG_I(PHY,"Registering with MAC interface module\n"); AssertFatal((eNB->if_inst = IF_Module_init(inst))!=NULL,"Cannot register interface"); eNB->if_inst->schedule_response = schedule_response; diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index e6364cad23..d2e734f205 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -1405,7 +1405,6 @@ void fill_rf_config(RU_t *ru, cfg->num_rb_dl=fp->N_RB_DL; cfg->tx_num_channels=ru->nb_tx; cfg->rx_num_channels=ru->nb_rx; - cfg->clock_source=get_softmodem_params()->clock_source; for (int i=0; inb_tx; i++) { cfg->tx_freq[i] = (double)fp->dl_CarrierFreq; @@ -1866,8 +1865,8 @@ static void *ru_thread( void *param ) { #if defined(PRE_SCD_THREAD) new_dlsch_ue_select_tbl_in_use = dlsch_ue_select_tbl_in_use; dlsch_ue_select_tbl_in_use = !dlsch_ue_select_tbl_in_use; - memcpy(&pre_scd_eNB_UE_stats,&RC.mac[ru->eNB_list[0]->Mod_id]->UE_list.eNB_UE_stats, sizeof(eNB_UE_STATS)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); - memcpy(&pre_scd_activeUE, &RC.mac[ru->eNB_list[0]->Mod_id]->UE_list.active, sizeof(boolean_t)*NUMBER_OF_UE_MAX); + memcpy(&pre_scd_eNB_UE_stats,&RC.mac[ru->eNB_list[0]->Mod_id]->UE_info.eNB_UE_stats, sizeof(eNB_UE_STATS)*MAX_NUM_CCs*NUMBER_OF_UE_MAX); + memcpy(&pre_scd_activeUE, &RC.mac[ru->eNB_list[0]->Mod_id]->UE_info.active, sizeof(boolean_t)*NUMBER_OF_UE_MAX); AssertFatal((ret=pthread_mutex_lock(&ru->proc.mutex_pre_scd))==0,"[eNB] error locking proc mutex for eNB pre scd\n"); ru->proc.instance_pre_scd++; @@ -2234,9 +2233,7 @@ void init_RU_proc(RU_t *ru) { RU_proc_t *proc; pthread_attr_t *attr_FH=NULL, *attr_FH1=NULL, *attr_prach=NULL, *attr_asynch=NULL, *attr_synch=NULL, *attr_emulateRF=NULL, *attr_ctrl=NULL, *attr_prach_br=NULL; //pthread_attr_t *attr_fep=NULL; -#ifndef OCP_FRAMEWORK LOG_I(PHY,"Initializing RU proc %d (%s,%s),\n",ru->idx,NB_functions[ru->function],NB_timing[ru->if_timing]); -#endif proc = &ru->proc; memset((void *)proc,0,sizeof(RU_proc_t)); proc->ru = ru; @@ -2683,7 +2680,7 @@ void set_function_spec_param(RU_t *ru) { //extern void RCconfig_RU(void); -void init_RU(char *rf_config_file, clock_source_t clock_source, clock_source_t time_source, int send_dmrssync) { +void init_RU(char *rf_config_file, int send_dmrssync) { int ru_id, i, CC_id; RU_t *ru; PHY_VARS_eNB *eNB0 = (PHY_VARS_eNB *)NULL; @@ -2718,8 +2715,6 @@ void init_RU(char *rf_config_file, clock_source_t clock_source, clock_source_t t ru->south_out_cnt = 0; // use eNB_list[0] as a reference for RU frame parameters // NOTE: multiple CC_id are not handled here yet! - ru->openair0_cfg.clock_source = clock_source; - ru->openair0_cfg.time_source = time_source; //ru->generate_dmrs_sync = (ru->is_slave == 0) ? 1 : 0; if ((ru->is_slave == 0) && (ru->ota_sync_enable == 1)) @@ -2956,6 +2951,27 @@ void RCconfig_RU(void) { LOG_E(PHY, "Erroneous RU clock source in the provided configuration file: '%s'\n", *(RUParamList.paramarray[j][RU_SDR_CLK_SRC].strptr)); } } + else { + RC.ru[j]->openair0_cfg.clock_source = unset; + } + + if (config_isparamset(RUParamList.paramarray[j], RU_SDR_TME_SRC)) { + if (strcmp(*(RUParamList.paramarray[j][RU_SDR_TME_SRC].strptr), "internal") == 0) { + RC.ru[j]->openair0_cfg.time_source = internal; + LOG_D(PHY, "RU time source set as internal\n"); + } else if (strcmp(*(RUParamList.paramarray[j][RU_SDR_TME_SRC].strptr), "external") == 0) { + RC.ru[j]->openair0_cfg.time_source = external; + LOG_D(PHY, "RU time source set as external\n"); + } else if (strcmp(*(RUParamList.paramarray[j][RU_SDR_TME_SRC].strptr), "gpsdo") == 0) { + RC.ru[j]->openair0_cfg.time_source = gpsdo; + LOG_D(PHY, "RU time source set as gpsdo\n"); + } else { + LOG_E(PHY, "Erroneous RU time source in the provided configuration file: '%s'\n", *(RUParamList.paramarray[j][RU_SDR_CLK_SRC].strptr)); + } + } + else { + RC.ru[j]->openair0_cfg.time_source = unset; + } if (strcmp(*(RUParamList.paramarray[j][RU_LOCAL_RF_IDX].strptr), "yes") == 0) { if ( !(config_isparamset(RUParamList.paramarray[j],RU_LOCAL_IF_NAME_IDX)) ) { diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c index 0b365ea938..d8c5e25593 100644 --- a/targets/RT/USER/lte-softmodem.c +++ b/targets/RT/USER/lte-softmodem.c @@ -80,7 +80,7 @@ unsigned short config_frames[4] = {2,9,11,13}; //#include "PHY/TOOLS/time_meas.h" #ifndef OPENAIR2 -#include "UTIL/OTG/otg_vars.h" + #include "UTIL/OTG/otg_vars.h" #endif @@ -93,6 +93,7 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "lte-softmodem.h" #include "NB_IoT_interface.h" +#include pthread_cond_t nfapi_sync_cond; @@ -152,6 +153,13 @@ int otg_enabled; uint64_t num_missed_slots=0; // counter for the number of missed slots +int split73=0; +void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_t *data, int dataLen, int r_offset) { + AssertFatal(false, "Must not be called in this context\n"); +} +void sendFs6Ulharq(enum pckType type, int UEid, PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask, uint16_t rnti, int32_t stat) { + AssertFatal(false, "Must not be called in this context\n"); +} extern void reset_opp_meas(void); extern void print_opp_meas(void); @@ -170,7 +178,7 @@ eth_params_t *eth_params; double cpuf; int oaisim_flag=0; -//threads_t threads= {-1,-1,-1,-1,-1,-1,-1,-1}; + /* forward declarations */ void set_default_frame_parms(LTE_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs]); @@ -435,7 +443,7 @@ int restart_L1L2(module_id_t enb_id) { set_function_spec_param(RC.ru[enb_id]); /* reset the list of connected UEs in the MAC, since in this process with * loose all UEs (have to reconnect) */ - init_UE_list(&RC.mac[enb_id]->UE_list); + init_UE_info(&RC.mac[enb_id]->UE_info); LOG_I(ENB_APP, "attempting to create ITTI tasks\n"); if (itti_create_task (TASK_RRC_ENB, rrc_enb_task, NULL) < 0) { @@ -539,7 +547,7 @@ int main ( int argc, char **argv ) cpuf=get_cpu_freq_GHz(); printf("ITTI init, useMME: %i\n",EPC_MODE_ENABLED); itti_init(TASK_MAX, THREAD_MAX, MESSAGES_ID_MAX, tasks_info, messages_info); - + // allows to forward in wireshark L2 protocol for decoding // initialize mscgen log after ITTI if (get_softmodem_params()->start_msc) { load_module_shlib("msc",NULL,0,&msc_interface); @@ -547,8 +555,6 @@ int main ( int argc, char **argv ) MSC_INIT(MSC_E_UTRAN, THREAD_MAX+TASK_MAX); init_opt(); - // to make a graceful exit when ctrl-c is pressed - set_softmodem_sighandler(); check_clock(); #ifndef PACKAGE_VERSION # define PACKAGE_VERSION "UNKNOWN-EXPERIMENTAL" @@ -579,11 +585,11 @@ int main ( int argc, char **argv ) for (i = 0; i < RC.nb_inst; i++) { flexran_agent_start(i); } - + /* initializes PDCP and sets correct RLC Request/PDCP Indication callbacks * for monolithic/F1 modes */ - init_pdcp(); - + init_pdcp(); + if (create_tasks(1) < 0) { printf("cannot create ITTI tasks\n"); exit(-1); @@ -607,7 +613,7 @@ int main ( int argc, char **argv ) ctxt.subframe = 0; pdcp_run(&ctxt); } - + /* start threads if only L1 or not a CU */ if (RC.nb_inst == 0 || !NODE_IS_CU(node_type) || NFAPI_MODE == NFAPI_MODE_PNF || NFAPI_MODE == NFAPI_MODE_VNF) { // init UE_PF_PO and mutex lock @@ -618,31 +624,44 @@ int main ( int argc, char **argv ) pthread_mutex_init(&sync_mutex, NULL); rt_sleep_ns(10*100000000ULL); - + if (NFAPI_MODE!=NFAPI_MONOLITHIC) { LOG_I(ENB_APP,"NFAPI*** - mutex and cond created - will block shortly for completion of PNF connection\n"); pthread_cond_init(&sync_cond,NULL); pthread_mutex_init(&sync_mutex, NULL); } - + if (NFAPI_MODE==NFAPI_MODE_VNF) {// VNF #if defined(PRE_SCD_THREAD) init_ru_vnf(); // ru pointer is necessary for pre_scd. #endif wait_nfapi_init("main?"); } - + LOG_I(ENB_APP,"START MAIN THREADS\n"); // start the main threads number_of_cards = 1; printf("RC.nb_L1_inst:%d\n", RC.nb_L1_inst); - + if (RC.nb_L1_inst > 0) { printf("Initializing eNB threads single_thread_flag:%d wait_for_sync:%d\n", get_softmodem_params()->single_thread_flag,get_softmodem_params()->wait_for_sync); init_eNB(get_softmodem_params()->single_thread_flag,get_softmodem_params()->wait_for_sync); - // for (inst=0;instproc.L1_proc; + L1proc->threadPool=(tpool_t*)malloc(sizeof(tpool_t)); + L1proc->respEncode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t)); + L1proc->respDecode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t)); + if ( strlen(get_softmodem_params()->threadPoolConfig) > 0 ) + initTpool(get_softmodem_params()->threadPoolConfig, L1proc->threadPool, true); + else + initTpool("n", L1proc->threadPool, true); + initNotifiedFIFO(L1proc->respEncode); + initNotifiedFIFO(L1proc->respDecode); + } + + } printf("wait_eNBs()\n"); @@ -654,29 +673,29 @@ int main ( int argc, char **argv ) // some initialization is necessary and init_ru_vnf do this. if (RC.nb_RU >0 && NFAPI_MODE!=NFAPI_MODE_VNF) { printf("Initializing RU threads\n"); - init_RU(get_softmodem_params()->rf_config_file,get_softmodem_params()->clock_source,get_softmodem_params()->timing_source,get_softmodem_params()->send_dmrs_sync); + init_RU(get_softmodem_params()->rf_config_file,get_softmodem_params()->send_dmrs_sync); for (ru_id=0; ru_idrf_map.card=0; RC.ru[ru_id]->rf_map.chain=CC_id+(get_softmodem_params()->chain_offset); } - + config_sync_var=0; - + if (NFAPI_MODE==NFAPI_MODE_PNF) { // PNF wait_nfapi_init("main?"); } - + printf("wait RUs\n"); - // CI -- Flushing the std outputs for the previous marker to show on the eNB / RRU log file + // end of CI modifications fflush(stdout); fflush(stderr); - // end of CI modifications + // wait_RUs() is wrong and over complex! wait_RUs(); LOG_I(ENB_APP,"RC.nb_RU:%d\n", RC.nb_RU); // once all RUs are ready intiailize the rest of the eNBs ((dependence on final RU parameters after configuration) printf("ALL RUs ready - init eNBs\n"); - + if (NFAPI_MODE!=NFAPI_MODE_PNF && NFAPI_MODE!=NFAPI_MODE_VNF) { LOG_I(ENB_APP,"Not NFAPI mode - call init_eNB_afterRU()\n"); init_eNB_afterRU(); @@ -723,7 +742,7 @@ int main ( int argc, char **argv ) for (int inst = 0; inst < NB_eNB_INST; inst++) { for (int cc_id = 0; cc_id < RC.nb_CC[inst]; cc_id++) { free_transport(RC.eNB[inst][cc_id]); - phy_free_lte_eNB(RC.eNB[inst][cc_id]); + phy_free_lte_eNB(RC.eNB[inst][cc_id]); } } @@ -741,17 +760,17 @@ int main ( int argc, char **argv ) for(ru_id=0; ru_idrfdevice.trx_end_func) { - RC.ru[ru_id]->rfdevice.trx_end_func(&RC.ru[ru_id]->rfdevice); - RC.ru[ru_id]->rfdevice.trx_end_func = NULL; + RC.ru[ru_id]->rfdevice.trx_end_func(&RC.ru[ru_id]->rfdevice); + RC.ru[ru_id]->rfdevice.trx_end_func = NULL; } if (RC.ru[ru_id]->ifdevice.trx_end_func) { - RC.ru[ru_id]->ifdevice.trx_end_func(&RC.ru[ru_id]->ifdevice); - RC.ru[ru_id]->ifdevice.trx_end_func = NULL; + RC.ru[ru_id]->ifdevice.trx_end_func(&RC.ru[ru_id]->ifdevice); + RC.ru[ru_id]->ifdevice.trx_end_func = NULL; } } } - + terminate_opt(); logClean(); printf("Bye.\n"); diff --git a/targets/RT/USER/lte-softmodem.h b/targets/RT/USER/lte-softmodem.h index 5e1bf36160..c5fdb5f546 100644 --- a/targets/RT/USER/lte-softmodem.h +++ b/targets/RT/USER/lte-softmodem.h @@ -81,7 +81,6 @@ #define CONFIG_HLP_DLSHIFT "dynamic shift for LLR compuation for TM3/4 (default 0)\n" #define CONFIG_HLP_USRP_ARGS "set the arguments to identify USRP (same syntax as in UHD)\n" #define CONFIG_HLP_DMAMAP "sets flag for improved EXMIMO UE performance\n" -#define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n" #define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n" #define CONFIG_HLP_TADV "Set timing_advance\n" @@ -115,7 +114,6 @@ {"dlsch-demod-shift", CONFIG_HLP_DLSHIFT, 0, iptr:(int32_t *)&dlsch_demod_shift, defintval:0, TYPE_INT, 0}, \ {"usrp-args", CONFIG_HLP_USRP_ARGS, 0, strptr:(char **)&usrp_args, defstrval:"type=b200",TYPE_STRING, 0}, \ {"mmapped-dma", CONFIG_HLP_DMAMAP, PARAMFLAG_BOOL, uptr:&mmapped_dma, defintval:0, TYPE_INT, 0}, \ - {"clock-source", CONFIG_HLP_CLK, 0, iptr:&clock_source, defintval:0, TYPE_INT, 0}, \ {"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, iptr:&tddflag, defintval:0, TYPE_INT, 0}, \ {"A", CONFIG_HLP_TADV, 0, iptr:&(timingadv), defintval:0, TYPE_INT, 0} \ } @@ -169,7 +167,7 @@ extern void init_RU_proc(RU_t *ru); extern void stop_RU(int nb_ru); extern void kill_RU_proc(RU_t *ru); extern void set_function_spec_param(RU_t *ru); -extern void init_RU(char *, clock_source_t clock_source, clock_source_t time_source, int send_dmrssync); +extern void init_RU(char *, int send_dmrssync); // In lte-ue.c extern int setup_ue_buffers(PHY_VARS_UE **phy_vars_ue, openair0_config_t *openair0_cfg); diff --git a/targets/RT/USER/lte-ue.c b/targets/RT/USER/lte-ue.c index 75ed018434..0962bb6a2d 100644 --- a/targets/RT/USER/lte-ue.c +++ b/targets/RT/USER/lte-ue.c @@ -589,7 +589,7 @@ static void *UE_thread_synch(void *arg) LOG_I(PHY, "[UE thread Synch] Running Initial Synch (mode %d)\n",UE->mode); if (initial_sync( UE, UE->mode ) == 0) { - LOG_I( HW, "Got synch: hw_slot_offset %d, carrier off %d Hz, rxgain %d (DL %u, UL %u), UE_scan_carrier %d\n", + LOG_I( HW, "Got synch: hw_slot_offset %d, carrier off %d Hz, rxgain %d (DL %lu, UL %lu), UE_scan_carrier %d\n", (UE->rx_offset<<1) / UE->frame_parms.samples_per_tti, freq_offset, UE->rx_total_gain_dB, @@ -714,7 +714,7 @@ static void *UE_thread_synch(void *arg) } } - LOG_I(PHY, "[initial_sync] trying carrier off %d Hz, rxgain %d (DL %u, UL %u)\n", + LOG_I(PHY, "[initial_sync] trying carrier off %d Hz, rxgain %d (DL %lu, UL %lu)\n", freq_offset, UE->rx_total_gain_dB, downlink_frequency[0][0]+freq_offset, @@ -1108,6 +1108,50 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) } } + if (dl_config_req && tx_request_pdu_list) { + nfapi_dl_config_request_body_t* dl_config_req_body = &dl_config_req->dl_config_request_body; + for (int i = 0; i < dl_config_req_body->number_pdu; ++i) { + nfapi_dl_config_request_pdu_t* pdu = &dl_config_req_body->dl_config_pdu_list[i]; + if (pdu->pdu_type == NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE) { + i += 1; + AssertFatal(i < dl_config_req->dl_config_request_body.number_pdu, + "Need PDU following DCI at index %d, but not found\n", + i); + nfapi_dl_config_request_pdu_t *dlsch = &dl_config_req_body->dl_config_pdu_list[i]; + if (dlsch->pdu_type != NFAPI_DL_CONFIG_DLSCH_PDU_TYPE) { + LOG_E(MAC, "expected DLSCH PDU at index %d\n", i); + continue; + } + dl_config_req_UE_MAC_dci(NFAPI_SFNSF2SFN(dl_config_req->sfn_sf), + NFAPI_SFNSF2SF(dl_config_req->sfn_sf), + pdu, + dlsch, + ue_num); + } else if (pdu->pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE) { + dl_config_req_UE_MAC_bch(NFAPI_SFNSF2SFN(dl_config_req->sfn_sf), + NFAPI_SFNSF2SF(dl_config_req->sfn_sf), + pdu, + ue_num); + } else if (pdu->pdu_type == NFAPI_DL_CONFIG_MCH_PDU_TYPE) { + dl_config_req_UE_MAC_mch(NFAPI_SFNSF2SFN(dl_config_req->sfn_sf), + NFAPI_SFNSF2SF(dl_config_req->sfn_sf), + pdu, + ue_num); + } + } + } + + if (hi_dci0_req) { + nfapi_hi_dci0_request_body_t *hi_dci0_body = &hi_dci0_req->hi_dci0_request_body; + for (int i = 0; i < hi_dci0_body->number_of_dci + hi_dci0_body->number_of_hi; i++) { + nfapi_hi_dci0_request_pdu_t* pdu = &hi_dci0_body->hi_dci0_pdu_list[i]; + hi_dci0_req_UE_MAC(NFAPI_SFNSF2SFN(hi_dci0_req->sfn_sf), + NFAPI_SFNSF2SF(hi_dci0_req->sfn_sf), + pdu, + ue_num); + } + } + //for (Mod_id=0; Mod_idhi_dci0_request_body.hi_dci0_pdu_list!=NULL) { - hi_dci0_req_UE_MAC(hi_dci0_req, ue_Mod_id); - } - if(NFAPI_MODE!=NFAPI_UE_STUB_PNF) phy_procedures_UE_SL_TX(UE,proc); } @@ -1183,7 +1218,7 @@ static void *UE_phy_stub_single_thread_rxn_txnp4(void *arg) if (UE_mac_inst[ue_Mod_id].UE_mode[0] == PRACH && ue_Mod_id == next_Mod_id) { next_ra_frame++; - if(next_ra_frame > 200) { + if(next_ra_frame > 500) { // check if we have PRACH opportunity if (is_prach_subframe(&UE->frame_parms,proc->frame_tx, proc->subframe_tx) && UE_mac_inst[ue_Mod_id].SI_Decoded == 1) { // The one working strangely... @@ -1413,12 +1448,14 @@ static void *UE_phy_stub_thread_rxn_txnp4(void *arg) oai_subframe_ind(timer_frame, timer_subframe); if(dl_config_req!= NULL) { - dl_config_req_UE_MAC(dl_config_req, Mod_id); + AssertFatal(0, "dl_config_req_UE_MAC() not handled\n"); + //dl_config_req_UE_MAC(dl_config_req, Mod_id); } //if(UE_mac_inst[Mod_id].hi_dci0_req!= NULL){ if (hi_dci0_req!=NULL && hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list!=NULL) { - hi_dci0_req_UE_MAC(hi_dci0_req, Mod_id); + AssertFatal(0, "hi_dci0_req_UE_MAC() not handled\n"); + //hi_dci0_req_UE_MAC(hi_dci0_req, Mod_id); //if(UE_mac_inst[Mod_id].hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list!=NULL){ free(hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list); hi_dci0_req->hi_dci0_request_body.hi_dci0_pdu_list = NULL; @@ -1525,12 +1562,12 @@ void write_dummy(PHY_VARS_UE *UE, openair0_timestamp timestamp) { for ( int i=0; i < UE->frame_parms.nb_antennas_tx; i++) samplesVoid[i]=(void *)&v; - AssertFatal(1 == UE->rfdevice.trx_write_func(&UE->rfdevice, - timestamp+2*UE->frame_parms.samples_per_tti, - samplesVoid, - 1, - UE->frame_parms.nb_antennas_tx, - 1),""); + AssertFatal( 1 == UE->rfdevice.trx_write_func(&UE->rfdevice, + timestamp+2*UE->frame_parms.samples_per_tti, + samplesVoid, + 1, + UE->frame_parms.nb_antennas_tx, + 1),""); } void *UE_thread(void *arg) @@ -1581,36 +1618,36 @@ void *UE_thread(void *arg) int instance_cnt_synch = UE->proc.instance_cnt_synch; int is_synchronized = UE->is_synchronized; AssertFatal ( 0== pthread_mutex_unlock(&UE->proc.mutex_synch), ""); - + if (is_synchronized == 0) { if (instance_cnt_synch < 0) { // we can invoke the synch // grab 10 ms of signal and wakeup synch thread if (UE->mode != loop_through_memory) { - if (IS_SOFTMODEM_RFSIM) { - for(int sf=0; sf<10; sf++) { - for (int i=0; iframe_parms.nb_antennas_rx; i++) - rxp[i] = (void *)&UE->common_vars.rxdata[i][UE->frame_parms.samples_per_tti*sf]; - + if (IS_SOFTMODEM_RFSIM ) { + for(int sf=0; sf<10; sf++) { + for (int i=0; iframe_parms.nb_antennas_rx; i++) + rxp[i] = (void *)&UE->common_vars.rxdata[i][UE->frame_parms.samples_per_tti*sf]; + AssertFatal(UE->frame_parms.samples_per_tti == UE->rfdevice.trx_read_func(&UE->rfdevice, - ×tamp, - rxp, - UE->frame_parms.samples_per_tti, - UE->frame_parms.nb_antennas_rx), ""); - write_dummy(UE, timestamp); - } - } else { - for (int i=0; iframe_parms.nb_antennas_rx; i++) - rxp[i] = (void *)&UE->common_vars.rxdata[i][0]; - - AssertFatal( UE->frame_parms.samples_per_tti*10 == + ×tamp, + rxp, + UE->frame_parms.samples_per_tti, + UE->frame_parms.nb_antennas_rx), ""); + write_dummy(UE, timestamp); + } + } else { + for (int i=0; iframe_parms.nb_antennas_rx; i++) + rxp[i] = (void *)&UE->common_vars.rxdata[i][0]; + + AssertFatal( UE->frame_parms.samples_per_tti*10 == UE->rfdevice.trx_read_func(&UE->rfdevice, ×tamp, rxp, UE->frame_parms.samples_per_tti*10, UE->frame_parms.nb_antennas_rx), ""); - } - } + } + } AssertFatal ( 0== pthread_mutex_lock(&UE->proc.mutex_synch), ""); instance_cnt_synch = ++UE->proc.instance_cnt_synch; @@ -1640,10 +1677,10 @@ void *UE_thread(void *arg) rxp, UE->frame_parms.samples_per_tti, UE->frame_parms.nb_antennas_rx); - if (IS_SOFTMODEM_RFSIM ) - write_dummy(UE, timestamp); - } - } + if (IS_SOFTMODEM_RFSIM ) + write_dummy(UE, timestamp); + } + } #endif } } // UE->is_synchronized==0 @@ -1654,17 +1691,17 @@ void *UE_thread(void *arg) if (UE->mode != loop_through_memory) { if (UE->no_timing_correction==0) { LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode); - while ( UE->rx_offset ) { - size_t s=min(UE->rx_offset,UE->frame_parms.samples_per_tti); + while ( UE->rx_offset ) { + size_t s=min(UE->rx_offset,UE->frame_parms.samples_per_tti); AssertFatal(s == UE->rfdevice.trx_read_func(&UE->rfdevice, - ×tamp, - (void **)UE->common_vars.rxdata, - s, - UE->frame_parms.nb_antennas_rx),""); - if (IS_SOFTMODEM_RFSIM ) - write_dummy(UE, timestamp); - UE->rx_offset-=s; - } + ×tamp, + (void **)UE->common_vars.rxdata, + s, + UE->frame_parms.nb_antennas_rx),""); + if (IS_SOFTMODEM_RFSIM ) + write_dummy(UE, timestamp); + UE->rx_offset-=s; + } } UE->rx_offset=0; @@ -1705,7 +1742,7 @@ void *UE_thread(void *arg) pthread_mutex_unlock(&proc->mutex_rxtx); } - usleep(300); + usleep(300); } LOG_D(PHY,"Process Subframe %d thread Idx %d \n", sub_frame, UE->current_thread_id[sub_frame]); @@ -2071,7 +2108,7 @@ int setup_ue_buffers(PHY_VARS_UE **phy_vars_ue, txdata = (int32_t **)malloc16( frame_parms->nb_antennas_tx*sizeof(int32_t *) ); for (i=0; inb_antennas_rx; i++) { - LOG_I(PHY, "Mapping UE CC_id %d, rx_ant %d, freq %u on card %d, chain %d\n", + LOG_I(PHY, "Mapping UE CC_id %d, rx_ant %d, freq %lu on card %d, chain %d\n", CC_id, i, downlink_frequency[CC_id][i], phy_vars_ue[CC_id]->rf_map.card, (phy_vars_ue[CC_id]->rf_map.chain)+i ); free( phy_vars_ue[CC_id]->common_vars.rxdata[i] ); rxdata[i] = (int32_t *)malloc16_clear( 307200*sizeof(int32_t) ); @@ -2079,7 +2116,7 @@ int setup_ue_buffers(PHY_VARS_UE **phy_vars_ue, } for (i=0; inb_antennas_tx; i++) { - LOG_I(PHY, "Mapping UE CC_id %d, tx_ant %d, freq %u on card %d, chain %d\n", + LOG_I(PHY, "Mapping UE CC_id %d, tx_ant %d, freq %lu on card %d, chain %d\n", CC_id, i, downlink_frequency[CC_id][i], phy_vars_ue[CC_id]->rf_map.card, (phy_vars_ue[CC_id]->rf_map.chain)+i ); free( phy_vars_ue[CC_id]->common_vars.txdata[i] ); txdata[i] = (int32_t *)malloc16_clear( 307200*sizeof(int32_t) ); diff --git a/targets/RT/USER/lte-uesoftmodem.c b/targets/RT/USER/lte-uesoftmodem.c index 25371260bf..2c9271888b 100644 --- a/targets/RT/USER/lte-uesoftmodem.c +++ b/targets/RT/USER/lte-uesoftmodem.c @@ -113,10 +113,6 @@ uint16_t runtime_phy_tx[29][6]; // SISO [MCS 0-28][RBs 0-5 : 6, 15, 25, 50, 75, volatile int oai_exit = 0; - -clock_source_t clock_source = internal,time_source=internal; - - unsigned int mmapped_dma=0; @@ -285,13 +281,13 @@ void exit_function(const char *file, const char *function, const int line, const extern int16_t dlsch_demod_shift; static void get_options(void) { - int CC_id; - int tddflag = 0; - char *loopfile = NULL; - int dumpframe = 0; - int timingadv = 0; + int CC_id=0; + int tddflag=0; + char *loopfile=NULL; + int dumpframe=0; + int timingadv=0; uint8_t nfapi_mode = NFAPI_MONOLITHIC; - int simL1flag = 0; + int simL1flag =0; set_default_frame_parms(frame_parms); CONFIG_SETRTFLAG(CONFIG_NOEXITONHELP); @@ -467,7 +463,8 @@ void init_openair0(LTE_DL_FRAME_PARMS *frame_parms,int rxgain) { openair0_cfg[card].Mod_id = 0; openair0_cfg[card].num_rb_dl=frame_parms->N_RB_DL; - openair0_cfg[card].clock_source = clock_source; + openair0_cfg[card].clock_source = get_softmodem_params()->clock_source; + openair0_cfg[card].time_source = get_softmodem_params()->timing_source; openair0_cfg[card].tx_num_channels=min(2,frame_parms->nb_antennas_tx); openair0_cfg[card].rx_num_channels=min(2,frame_parms->nb_antennas_rx); diff --git a/targets/RT/USER/rfsim.c b/targets/RT/USER/rfsim.c index bd8305682c..a9a0912433 100644 --- a/targets/RT/USER/rfsim.c +++ b/targets/RT/USER/rfsim.c @@ -64,7 +64,7 @@ sim_t sim; void init_ru_devices(void); -void init_RU(char *,clock_source_t clock_source,clock_source_t time_source,int send_dmrssync); +void init_RU(char *,int send_dmrssync); void *rfsim_top(void *n_frames); @@ -101,7 +101,7 @@ void RCConfig_sim(void) { RC.nb_RU = RUParamList.numelt; AssertFatal(RC.nb_RU>0,"we need at least 1 RU for simulation\n"); printf("returned with %d rus\n",RC.nb_RU); - init_RU(NULL,internal,internal,0); + init_RU(NULL,0); printf("Waiting for RUs to get set up\n"); wait_RUs(); init_ru_devices(); From 43dc75f92fea0785782ff93a3f596768ac62a7f0 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:39:12 +0200 Subject: [PATCH 10/70] fembms: reference config files re-arranged --- .../conf_files/enb.band17.tm1.25PRB.usrpb210.conf | 1 + .../enb.band17.tm1.mbms.25PRB.usrpb210.conf | 14 ++++++++------ ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf | 14 +++++++++++--- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf index db1c5eae2a..d834b23e30 100644 --- a/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf +++ b/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf @@ -105,6 +105,7 @@ eNBs = ue_TimersAndConstants_n310 = 20; ue_TimersAndConstants_n311 = 1; ue_TransmissionMode = 1; + mbms_dedicated_serving_cell = "DISABLE" //Parameters for SIB18 rxPool_sc_CP_Len = "normal"; diff --git a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf index de58950df4..e36d970b5b 100644 --- a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf +++ b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf @@ -105,6 +105,8 @@ eNBs = ue_TimersAndConstants_n310 = 20; ue_TimersAndConstants_n311 = 1; ue_TransmissionMode = 1; + mbms_dedicated_serving_cell = "DISABLE" + //Parameters for SIB18 rxPool_sc_CP_Len = "normal"; @@ -271,12 +273,12 @@ MCEs = ( mcch_update_time = 10; mbms_area_config_list = ( { - common_sf_allocation_period = 2; #rf4(0) rf8(1) rf16(2) rf32(3) rf64(4) rf128(5) rf256(6) + common_sf_allocation_period = 1; #rf4(0) rf8(1) rf16(2) rf32(3) rf64(4) rf128(5) rf256(6) mbms_area_id = 0; pmch_config_list = ( { - allocated_sf_end=64; - data_mcs=10; + allocated_sf_end=40; + data_mcs=20; mch_scheduling_period = 0; #rf8(0) mbms_session_list = ( { @@ -288,7 +290,7 @@ MCEs = ( mnc_length = 2; } service_id=0; - lcid=5; #this must be properly defined lcid:8+service:0 -> rab_id:5 + lcid=5; #this must be properly defined lcid:8+service:0 -> rab_id:5 //with new RLC set lcid either 4 or 5 } ); } @@ -296,10 +298,10 @@ MCEs = ( mbms_sf_config_list = ( { - radioframe_allocation_period=1; #n1(0) n2(1) n4(2) n8(3) n16(4) n32(5) + radioframe_allocation_period=0; #n1(0) n2(1) n4(2) n8(3) n16(4) n32(5) radioframe_alloocation_offset=0; num_frame="oneFrame"; - subframe_allocation=57; #xx100000 + subframe_allocation=59; #xx111011 #57; #xx111001 //num_frame="fourFrame"; //subframe_allocation=14548987; # } diff --git a/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf b/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf index 53261ec32d..3d5a859156 100644 --- a/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf +++ b/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf @@ -102,6 +102,7 @@ eNBs = ue_TimersAndConstants_n310 = 20; ue_TimersAndConstants_n311 = 1; ue_TransmissionMode = 1; + mbms_dedicated_serving_cell = "DISABLE" //Parameters for SIB18 rxPool_sc_CP_Len = "normal"; @@ -295,8 +296,8 @@ MCEs = ( pmch_config_list = ( { allocated_sf_end=32; - data_mcs=14; - mch_scheduling_period = 0; #rf8(0) + data_mcs=15; + mch_scheduling_period = 0; #rf8(0) rf16(1) rf32(2) rf64(3) rf128(4) rf256(5) rf512(6) rf1024(7) mbms_session_list = ( { #plnm + service_id ->tmgi @@ -337,7 +338,7 @@ MCEs = ( offset = 0; modification_period = 0; #rf512(0; rf1024(1) subframe_allocation_info = 32; #BITSTRING (6bits -> one frame) xx100000 - mcs = 1; #n2(0), n7(1), n13(2), n19(3) + mcs = 0; #n2(0), n7(1), n13(2), n19(3) } ); @@ -416,3 +417,10 @@ NETWORK_CONTROLLER : rrc_log_level ="info"; rrc_log_verbosity ="medium"; }; + +//rfsimulator : +//{ + //options = ("chanmod"); + //modelname = "AWGN"; +//}; + From eb0dacc4432158807ebff8adba6a798c4c1c62c7 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:41:56 +0200 Subject: [PATCH 11/70] fembms: L1 prototypes and params added --- executables/split_headers.h | 2 +- openair1/PHY/INIT/lte_init.c | 1 + openair1/PHY/INIT/lte_init_ue.c | 6 +++--- openair1/PHY/INIT/lte_parms.c | 15 +++++++++++++++ 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/executables/split_headers.h b/executables/split_headers.h index 4e328f74c4..1866e42159 100644 --- a/executables/split_headers.h +++ b/executables/split_headers.h @@ -279,7 +279,7 @@ int init_rf(RU_t *ru); void rx_rf(RU_t *ru, L1_rxtx_proc_t *proc); void tx_rf(RU_t *ru, L1_rxtx_proc_t *proc); void common_signal_procedures (PHY_VARS_eNB *eNB,int frame, int subframe); -void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc); +void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, int fembms_flag); bool dlsch_procedures(PHY_VARS_eNB *eNB, L1_rxtx_proc_t *proc, int harq_pid, diff --git a/openair1/PHY/INIT/lte_init.c b/openair1/PHY/INIT/lte_init.c index 2d65521ab3..2c7e3e88eb 100644 --- a/openair1/PHY/INIT/lte_init.c +++ b/openair1/PHY/INIT/lte_init.c @@ -275,6 +275,7 @@ void phy_config_request(PHY_Config_t *phy_config) { fp->soundingrs_ul_config_common.srs_MaxUpPts = cfg->srs_config.max_up_pts.value; fp->num_MBSFN_config = 0; fp->NonMBSFN_config_flag =cfg->fembms_config.non_mbsfn_config_flag.value; + fp->FeMBMS_active = fp->NonMBSFN_config_flag; fp->NonMBSFN_config.non_mbsfn_SubframeConfig = cfg->fembms_config.non_mbsfn_subframeconfig.value; fp->NonMBSFN_config.radioframeAllocationPeriod = cfg->fembms_config.radioframe_allocation_period.value; fp->NonMBSFN_config.radioframeAllocationOffset = cfg->fembms_config.radioframe_allocation_offset.value; diff --git a/openair1/PHY/INIT/lte_init_ue.c b/openair1/PHY/INIT/lte_init_ue.c index 082db61da9..64a5992a64 100644 --- a/openair1/PHY/INIT/lte_init_ue.c +++ b/openair1/PHY/INIT/lte_init_ue.c @@ -137,7 +137,7 @@ void phy_config_sib2_ue(module_id_t Mod_id,int CC_id, if (mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) { fp->MBSFN_config[i].fourFrames_flag = 0; fp->MBSFN_config[i].mbsfn_SubframeConfig = mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]; // 6-bit subframe configuration - LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] pattern is %d\n", i, + LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] oneFrame pattern is %d\n", i, fp->MBSFN_config[i].mbsfn_SubframeConfig); } else if (mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames) { // 24-bit subframe configuration fp->MBSFN_config[i].fourFrames_flag = 1; @@ -145,7 +145,7 @@ void phy_config_sib2_ue(module_id_t Mod_id,int CC_id, mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[2]| (mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[1]<<8)| (mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]<<16); - LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] pattern is %x\n", i, + LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] fourFrame pattern is %x\n", i, fp->MBSFN_config[i].mbsfn_SubframeConfig); } } @@ -212,7 +212,7 @@ void phy_config_sib1_fembms_ue(module_id_t Mod_id,int CC_id, LTE_DL_FRAME_PARMS *fp = &ue->frame_parms; if (nonMBSFN_SubframeConfig != NULL) { - fp->NonMBSFN_config_flag = 0; + fp->NonMBSFN_config_flag = 1; fp->NonMBSFN_config.radioframeAllocationPeriod=nonMBSFN_SubframeConfig->radioFrameAllocationPeriod_r14; fp->NonMBSFN_config.radioframeAllocationOffset=nonMBSFN_SubframeConfig->radioFrameAllocationOffset_r14; fp->NonMBSFN_config.non_mbsfn_SubframeConfig=(nonMBSFN_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | nonMBSFN_SubframeConfig->subframeAllocation_r14.buf[0]>>7); diff --git a/openair1/PHY/INIT/lte_parms.c b/openair1/PHY/INIT/lte_parms.c index 12a5646df6..f5b7a6c7e8 100644 --- a/openair1/PHY/INIT/lte_parms.c +++ b/openair1/PHY/INIT/lte_parms.c @@ -93,6 +93,11 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms, frame_parms->N_RBGS = 4; frame_parms->N_RBG = 25; + frame_parms->ofdm_symbol_size_khz_1dot25 = 2*2*6144*osf; + frame_parms->first_carrier_offset_khz_1dot25 = frame_parms->ofdm_symbol_size_khz_1dot25 - 1800*2*2; + frame_parms->nb_prefix_samples_khz_1dot25>>=(2-log2_osf); + frame_parms->nb_prefix_samples0_khz_1dot25>>=(2-log2_osf); + break; case 75: @@ -104,6 +109,12 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms, frame_parms->nb_prefix_samples0=(frame_parms->nb_prefix_samples0*3)>>2; frame_parms->N_RBGS = 4; frame_parms->N_RBG = 25; + + frame_parms->ofdm_symbol_size_khz_1dot25 = 2*6144*osf; + frame_parms->first_carrier_offset_khz_1dot25 = frame_parms->ofdm_symbol_size_khz_1dot25 - 1800*2; + frame_parms->nb_prefix_samples_khz_1dot25>>=(2-log2_osf); + frame_parms->nb_prefix_samples0_khz_1dot25>>=(2-log2_osf); + break; case 50: @@ -115,6 +126,10 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms, frame_parms->nb_prefix_samples0>>=(1-log2_osf); frame_parms->N_RBGS = 3; frame_parms->N_RBG = 17; + frame_parms->ofdm_symbol_size_khz_1dot25 = 2*6144*osf; + frame_parms->first_carrier_offset_khz_1dot25 = frame_parms->ofdm_symbol_size_khz_1dot25 - 1800*2; + frame_parms->nb_prefix_samples_khz_1dot25>>=(2-log2_osf); + frame_parms->nb_prefix_samples0_khz_1dot25>>=(2-log2_osf); break; case 25: From c5799e1ccac1dcad93f0c275c0dba7e3e32e0815 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:42:47 +0200 Subject: [PATCH 12/70] fembms: missing protype added --- openair1/PHY/LTE_REFSIG/lte_refsig.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openair1/PHY/LTE_REFSIG/lte_refsig.h b/openair1/PHY/LTE_REFSIG/lte_refsig.h index 45402436f7..84a2676082 100644 --- a/openair1/PHY/LTE_REFSIG/lte_refsig.h +++ b/openair1/PHY/LTE_REFSIG/lte_refsig.h @@ -106,6 +106,16 @@ int lte_dl_mbsfn(PHY_VARS_eNB *phy_vars_eNB, int32_t *output, short amp, int subframe, unsigned char l); +/*! \brief This function generates the 1.25KHz MBSFN reference signal sequence (36-211, Sec 6.10.1.2) +@param phy_vars_eNB Pointer to eNB variables +@param output Output vector for OFDM symbol (Frequency Domain) +@param amp Q15 amplitude +*/ + +int lte_dl_mbsfn_khz_1dot25(PHY_VARS_eNB *phy_vars_eNB, int32_t *output, + short amp, + int subframe); + /*!\brief This function generates the cell-specific reference signal sequence (36-211, Sec 6.10.1.1) for channel estimation upon reception From da5ae9c8d1ddafa56b41323984ff31519434610d Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:48:26 +0200 Subject: [PATCH 13/70] fembms: L1 prototypes for FeMBMS eNB procedures Signed-off-by: Javier Morgade --- openair1/PHY/LTE_TRANSPORT/transport_common.h | 1 + .../LTE_TRANSPORT/transport_common_proto.h | 3 + openair1/PHY/LTE_TRANSPORT/transport_proto.h | 73 +++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/openair1/PHY/LTE_TRANSPORT/transport_common.h b/openair1/PHY/LTE_TRANSPORT/transport_common.h index 321789d54b..ab2921c2b9 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_common.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_common.h @@ -67,6 +67,7 @@ #if !defined(SI_RNTI) #define SI_RNTI (rnti_t)0xffff + #define SI_RNTI_MBMS (rnti_t)0xfff9 #endif #if !defined(M_RNTI) #define M_RNTI (rnti_t)0xfffd diff --git a/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h b/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h index e4f5d9a17f..1944f06fab 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h @@ -270,6 +270,9 @@ int is_pmch_subframe(frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parm */ int is_fembms_cas_subframe(frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms); +int is_fembms_nonMBSFN_subframe (frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms); + + /*! \brief Return the status of MBSFN in this frame/subframe @param frame Frame index diff --git a/openair1/PHY/LTE_TRANSPORT/transport_proto.h b/openair1/PHY/LTE_TRANSPORT/transport_proto.h index 3988923bb9..4ce113f78e 100644 --- a/openair1/PHY/LTE_TRANSPORT/transport_proto.h +++ b/openair1/PHY/LTE_TRANSPORT/transport_proto.h @@ -123,6 +123,42 @@ int32_t dlsch_encoding(PHY_VARS_eNB *eNB, time_stats_t *te_stats, time_stats_t *i_stats); +/** \fn dlsch_encoding(PHY_VARS_eNB *eNB, + uint8_t *input_buffer, + LTE_DL_FRAME_PARMS *frame_parms, + uint8_t num_pdcch_symbols, + LTE_eNB_DLSCH_t *dlsch, + int frame, + uint8_t subframe) + \brief This function performs a subset of the bit-coding functions for LTE as described in 36-212, Release 8.Support is limited to turbo-coded channels (DLSCH/ULSCH). The implemented functions are: + - CRC computation and addition + - Code block segmentation and sub-block CRC addition + - Channel coding (Turbo coding) + - Rate matching (sub-block interleaving, bit collection, selection and transmission + - Code block concatenation + @param eNB Pointer to eNB PHY context + @param input_buffer Pointer to input buffer for sub-frame + @param frame_parms Pointer to frame descriptor structure + @param num_pdcch_symbols Number of PDCCH symbols in this subframe + @param dlsch Pointer to dlsch to be encoded + @param frame Frame number + @param subframe Subframe number + @param rm_stats Time statistics for rate-matching + @param te_stats Time statistics for turbo-encoding + @param i_stats Time statistics for interleaving + @returns status +*/ +int32_t dlsch_encoding_fembms_pmch(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, + uint8_t *a, + uint8_t num_pdcch_symbols, + LTE_eNB_DLSCH_t *dlsch, + int frame, + uint8_t subframe, + time_stats_t *rm_stats, + time_stats_t *te_stats, + time_stats_t *i_stats); + @@ -269,6 +305,30 @@ int mch_modulation(int32_t **txdataF, LTE_DL_FRAME_PARMS *frame_parms, LTE_eNB_DLSCH_t *dlsch); +/* + \brief This function is the top-level routine for generation of the sub-frame signal (frequency-domain) for MCH. + @param txdataF Table of pointers for frequency-domain TX signals + @param amp Amplitude of signal + @param subframe_offset Offset of this subframe in units of subframes (usually 0) + @param frame_parms Pointer to frame descriptor + @param dlsch Pointer to DLSCH descriptor for this allocation +*/ +int mch_modulation_khz_1dot25(int32_t **txdataF, + int16_t amp, + uint32_t subframe_offset, + LTE_DL_FRAME_PARMS *frame_parms, + LTE_eNB_DLSCH_t *dlsch); + + +/** \brief Top-level generation function for eNB TX of MBSFN + @param phy_vars_eNB Pointer to eNB variables + @param a Pointer to transport block + @param abstraction_flag + +*/ +void generate_mch_khz_1dot25(PHY_VARS_eNB *phy_vars_eNB,L1_rxtx_proc_t *proc,uint8_t *a); + + /** \brief Top-level generation function for eNB TX of MBSFN @param phy_vars_eNB Pointer to eNB variables @param a Pointer to transport block @@ -318,6 +378,12 @@ int32_t generate_pilots_slot(PHY_VARS_eNB *phy_vars_eNB, uint16_t slot, int first_pilot_only); +int32_t generate_mbsfn_pilot_khz_1dot25(PHY_VARS_eNB *phy_vars_eNB, + L1_rxtx_proc_t *proc, + int32_t **txdataF, + int16_t amp); + + int32_t generate_mbsfn_pilot(PHY_VARS_eNB *phy_vars_eNB, L1_rxtx_proc_t *proc, int32_t **txdataF, @@ -350,6 +416,13 @@ int32_t generate_pbch(LTE_eNB_PBCH *eNB_pbch, uint8_t *pbch_pdu, uint8_t frame_mod4); +int32_t generate_pbch_fembms(LTE_eNB_PBCH *eNB_pbch, + int32_t **txdataF, + int32_t amp, + LTE_DL_FRAME_PARMS *frame_parms, + uint8_t *pbch_pdu, + uint8_t frame_mod16); + From 4923ba301a4e15fbdb1a41429e206284505018ca Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:49:58 +0200 Subject: [PATCH 14/70] fembms: Addapting top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212 with FeMBMS support Signed-off-by: Javier Morgade --- openair1/PHY/LTE_TRANSPORT/dlsch_coding.c | 109 +++++++++++++++++++++- 1 file changed, 107 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c index 14036ad43a..ce4e6fba9f 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c @@ -20,12 +20,12 @@ */ /*! \file PHY/LTE_TRANSPORT/dlsch_coding.c - * \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03 + * \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03, V14.1 2017 (includes FeMBMS support) * \author R. Knopp * \date 2011 * \version 0.1 * \company Eurecom - * \email: knopp@eurecom.fr + * \email: knopp@eurecom.fr, jaiver.morgade@ieee.org * \note * \warning */ @@ -425,3 +425,108 @@ int dlsch_encoding(PHY_VARS_eNB *eNB, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); return(0); } + +int dlsch_encoding_fembms_pmch(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, + unsigned char *a, + uint8_t num_pdcch_symbols, + LTE_eNB_DLSCH_t *dlsch, + int frame, + uint8_t subframe, + time_stats_t *rm_stats, + time_stats_t *te_stats, + time_stats_t *i_stats) { + LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms; + unsigned char harq_pid = dlsch->harq_ids[frame%2][subframe]; + if((harq_pid < 0) || (harq_pid >= dlsch->Mdlharq)) { + LOG_E(PHY,"dlsch_encoding illegal harq_pid %d %s:%d\n", harq_pid, __FILE__, __LINE__); + return(-1); + } + + LTE_DL_eNB_HARQ_t *hadlsch=dlsch->harq_processes[harq_pid]; + uint8_t beamforming_mode=0; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); + + if(hadlsch->mimo_mode == TM7) + beamforming_mode = 7; + else if(hadlsch->mimo_mode == TM8) + beamforming_mode = 8; + else if(hadlsch->mimo_mode == TM9_10) + beamforming_mode = 9; + + unsigned int G = get_G_khz_1dot25(frame_parms,hadlsch->nb_rb, + hadlsch->rb_alloc, + hadlsch->Qm, // mod order + hadlsch->Nl, + num_pdcch_symbols, + frame,subframe,beamforming_mode); + + proc->nbEncode=0; + + // if (hadlsch->Ndi == 1) { // this is a new packet + if (hadlsch->round == 0) { // this is a new packet + // Add 24-bit crc (polynomial A) to payload + unsigned int A=hadlsch->TBS; //6228; + unsigned int crc = crc24a(a, + A)>>8; + a[A>>3] = ((uint8_t *)&crc)[2]; + a[1+(A>>3)] = ((uint8_t *)&crc)[1]; + a[2+(A>>3)] = ((uint8_t *)&crc)[0]; + // printf("CRC %x (A %d)\n",crc,A); + hadlsch->B = A+24; + // hadlsch->b = a; + memcpy(hadlsch->b,a,(A/8)+4); + + if (lte_segmentation(hadlsch->b, + hadlsch->c, + hadlsch->B, + &hadlsch->C, + &hadlsch->Cplus, + &hadlsch->Cminus, + &hadlsch->Kplus, + &hadlsch->Kminus, + &hadlsch->F)<0) + return(-1); + } + + for (int r=0, r_offset=0; rC; r++) { + + union turboReqUnion id= {.s={dlsch->rnti,frame,subframe,r,0}}; + notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboEncode_t), id.p, proc->respEncode, TPencode); + turboEncode_t * rdata=(turboEncode_t *) NotifiedFifoData(req); + rdata->input=hadlsch->c[r]; + rdata->Kr_bytes= ( rCminus ? hadlsch->Kminus : hadlsch->Kplus) >>3; + rdata->filler=(r==0) ? hadlsch->F : 0; + rdata->r=r; + rdata->harq_pid=harq_pid; + rdata->dlsch=dlsch; + rdata->rm_stats=rm_stats; + rdata->te_stats=te_stats; + rdata->i_stats=i_stats; + rdata->round=hadlsch->round; + rdata->r_offset=r_offset; + rdata->G=G; + + if ( proc->threadPool->activated ) { + pushTpool(proc->threadPool,req); + proc->nbEncode++; + } else { + TPencode(rdata); + delNotifiedFIFO_elt(req); + } + + int Qm=hadlsch->Qm; + int C=hadlsch->C; + int Nl=hadlsch->Nl; + int Gp = G/Nl/Qm; + int GpmodC = Gp%C; + if (r < (C-(GpmodC))) + r_offset += Nl*Qm * (Gp/C); + else + r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C)); + } + + return(0); +} + + From 3d11b3d65dd794942bf5540dc578b854c3f2dc93 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:51:51 +0200 Subject: [PATCH 15/70] fembms: FeMBMS (eNB) Top-level routines for generating the PDSCH physical channel from 36-211 V14.1 Signed-off-by: Javier Morgade --- openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c | 261 +++++++++++++++++- 1 file changed, 259 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c index 475c8bd521..eeb701657a 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c @@ -20,12 +20,12 @@ */ /*! \file PHY/LTE_TRANSPORT/dlsch_modulation.c - * \brief Top-level routines for generating the PDSCH physical channel from 36-211, V8.6 2009-03 + * \brief Top-level routines for generating the PDSCH physical channel from 36-211, V8.6 2009-03, V14.1 2017 (FeMBMS) * \author R. Knopp, F. Kaltenberger * \date 2011 * \version 0.1 * \company Eurecom - * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr + * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr, javier.morgade@ieee.irg * \note * \warning */ @@ -2910,3 +2910,260 @@ int mch_modulation(int32_t **txdataF, return (re_allocated); } + +int allocate_REs_in_RB_MCH_khz_1dot25(int32_t **txdataF, + uint32_t *jj, + uint16_t re_offset, + uint32_t symbol_offset, + uint8_t *x0, + uint8_t subframe, + uint8_t mod_order, + int16_t amp, + int16_t *qam_table_s, + uint32_t *re_allocated, + uint8_t skip_dc, + LTE_DL_FRAME_PARMS *frame_parms) +{ + uint32_t tti_offset; + uint8_t re,offset; + uint8_t qam64_table_offset_re = 0; + uint8_t qam64_table_offset_im = 0; + uint8_t qam16_table_offset_re = 0; + uint8_t qam16_table_offset_im = 0; + int16_t gain_lin_QPSK;//,gain_lin_16QAM1,gain_lin_16QAM2; + int16_t re_off=re_offset; + gain_lin_QPSK = (int16_t)((amp*ONE_OVER_SQRT2_Q15)>>15); + uint8_t first_re,last_re; + int inc; +#ifdef DEBUG_DLSCH_MODULATION + LOG_I(PHY,"allocate_re_MCH khz_1dot25 (mod %d): symbol_offset %d re_offset %d (%d), jj %d -> %d,%d, gain_lin_QPSK %d,txdataF %p\n",mod_order,symbol_offset,re_offset,skip_dc,*jj, x0[*jj], x0[1+*jj],gain_lin_QPSK,&txdataF[0][symbol_offset]); +#endif + + /*last_re=12; + first_re=0; + inc=1; + + if ((l==2)||(l==10)) { + inc=2; + first_re=1; + } else if (l==6) { + inc=2; + }*/ + last_re=144; //12*12 + if ((subframe&0x1)==0){ // n_sf mod 2 == 0: even + first_re=1; + offset=0; + }else{ + first_re=0; + offset=3; + } + inc=1; + + for (re=first_re; reofdm_symbol_size_khz_1dot25+1; + } + + tti_offset = symbol_offset + re_off + re; + + //LOG_I(PHY,"re %d (jj %d)\n",re,*jj); + *re_allocated = *re_allocated + 1; + + + switch (mod_order) { + + case 2: //QPSK + + LOG_D(PHY,"%d : %d,%d => ",tti_offset,((int16_t*)&txdataF[0][tti_offset])[0],((int16_t*)&txdataF[0][tti_offset])[1]); + ((int16_t*)&txdataF[0][tti_offset])[0] = (x0[*jj]==1) ? (-gain_lin_QPSK) : gain_lin_QPSK; //I //b_i + + *jj = *jj + 1; + + ((int16_t*)&txdataF[0][tti_offset])[1] = (x0[*jj]==1) ? (-gain_lin_QPSK) : gain_lin_QPSK; //Q //b_{i+1} + + *jj = *jj + 1; + + LOG_D(PHY,"subframe%d alloc[%d][%d][%d](%d,%d)\n",subframe,tti_offset,symbol_offset,tti_offset-symbol_offset,((int16_t*)&txdataF[0][tti_offset])[0],((int16_t*)&txdataF[0][tti_offset])[1]); + break; + + + case 4: //16QAM + + qam16_table_offset_re = 0; + qam16_table_offset_im = 0; + + if (x0[*jj] == 1) + qam16_table_offset_re+=2; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam16_table_offset_im+=2; + + *jj=*jj+1; + + + if (x0[*jj] == 1) + qam16_table_offset_re+=1; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam16_table_offset_im+=1; + + *jj=*jj+1; + + + ((int16_t *)&txdataF[0][tti_offset])[0]=qam_table_s[qam16_table_offset_re];//(int16_t)(((int32_t)amp*qam16_table[qam16_table_offset_re])>>15); + ((int16_t *)&txdataF[0][tti_offset])[1]=qam_table_s[qam16_table_offset_im];//(int16_t)(((int32_t)amp*qam16_table[qam16_table_offset_im])>>15); + + break; + + case 6: //64QAM + + qam64_table_offset_re = 0; + qam64_table_offset_im = 0; + + if (x0[*jj] == 1) + qam64_table_offset_re+=4; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam64_table_offset_im+=4; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam64_table_offset_re+=2; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam64_table_offset_im+=2; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam64_table_offset_re+=1; + + *jj=*jj+1; + + if (x0[*jj] == 1) + qam64_table_offset_im+=1; + + *jj=*jj+1; + + ((int16_t *)&txdataF[0][tti_offset])[0]=qam_table_s[qam64_table_offset_re];//(int16_t)(((int32_t)amp*qam64_table[qam64_table_offset_re])>>15); + ((int16_t *)&txdataF[0][tti_offset])[1]=qam_table_s[qam64_table_offset_im];//(int16_t)(((int32_t)amp*qam64_table[qam64_table_offset_im])>>15); + + break; + + } + } + return(0); +} + +int mch_modulation_khz_1dot25(int32_t **txdataF, + int16_t amp, + uint32_t subframe_offset, + LTE_DL_FRAME_PARMS *frame_parms, + LTE_eNB_DLSCH_t *dlsch) +{ + uint8_t nsymb,nsymb_pmch; + uint32_t i,jj,re_allocated,symbol_offset; + uint16_t l,rb,re_offset; + uint8_t skip_dc=0; + uint8_t mod_order = dlsch->harq_processes[0]->Qm; + int16_t qam16_table_a[4],qam64_table_a[8];//,qam16_table_b[4],qam64_table_b[8]; + int16_t *qam_table_s; + + nsymb_pmch = 1; + nsymb = (frame_parms->Ncp == NORMAL) ? 14 : 12; + + if (mod_order == 4) + for (i=0; i<4; i++) { + qam16_table_a[i] = (int16_t)(((int32_t)qam16_table[i]*amp)>>15); + } + else if (mod_order == 6) + for (i=0; i<8; i++) { + qam64_table_a[i] = (int16_t)(((int32_t)qam64_table[i]*amp)>>15); + } + + jj=0; + re_allocated=0; + + + + + + // LOG_I(PHY,"num_pdcch_symbols %d, nsymb %d\n",num_pdcch_symbols,nsymb); + for (l=0; lfirst_carrier_offset_khz_1dot25; + symbol_offset = (uint32_t)frame_parms->ofdm_symbol_size*(l+(subframe_offset*nsymb)); + + for (rb=0; rbN_RB_DL; rb++) { + + + if ((frame_parms->N_RB_DL&1) == 1) { // ODD N_RB_DL + + if (rb==(frame_parms->N_RB_DL>>1)) + skip_dc = 1; + else + skip_dc = 0; + + } + + if (mod_order == 4) + qam_table_s = qam16_table_a; + else if (mod_order == 6) + qam_table_s = qam64_table_a; + else + qam_table_s = NULL; + + //LOG_I(PHY,"Allocated rb %d, subframe_offset %d,amp %d\n",rb,subframe_offset,amp); + allocate_REs_in_RB_MCH_khz_1dot25(txdataF, + &jj, + re_offset, + symbol_offset, + dlsch->harq_processes[0]->eDL, + subframe_offset, + mod_order, + amp, + qam_table_s, + &re_allocated, + skip_dc, + frame_parms); + + re_offset+=144; // go to next RB 12*12 + + // check if we crossed the symbol boundary and skip DC + if (re_offset >= frame_parms->ofdm_symbol_size_khz_1dot25) { + if (skip_dc == 0) //even number of RBs (doesn't straddle DC) + re_offset=1; + else + re_offset=73; // odd number of RBs + } + } + } + +#ifdef DEBUG_DLSCH_MODULATION + LOG_I(PHY,"generate_dlsch(MCH) : jj = %d,re_allocated = %d (G %d)\n",jj,re_allocated,get_G(frame_parms,dlsch->harq_processes[0]->nb_rb,dlsch->harq_processes[0]->rb_alloc,mod_order,1,2,0,subframe_offset,1/*transmission mode*/)); + LOG_I(PHY,"generate_dlsch(MCH) : jj = %d,re_allocated = %d\n",jj,re_allocated); +#endif + + return (re_allocated); +} + From 3fca8304a446b82966c38dd11af4d5116bb52490 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:54:01 +0200 Subject: [PATCH 16/70] fembms: FeMBMS top-level routines for generating and decoding the PBCH/BCH physical/transport channel Signed-off-by: Javier Morgade --- openair1/PHY/LTE_TRANSPORT/pbch.c | 283 +++++++++++++++++++++++++++++- 1 file changed, 281 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/pbch.c b/openair1/PHY/LTE_TRANSPORT/pbch.c index 37997c94b4..a142f22a54 100644 --- a/openair1/PHY/LTE_TRANSPORT/pbch.c +++ b/openair1/PHY/LTE_TRANSPORT/pbch.c @@ -20,12 +20,12 @@ */ /*! \file PHY/LTE_TRANSPORT/pbch.c -* \brief Top-level routines for generating and decoding the PBCH/BCH physical/transport channel V8.6 2009-03 +* \brief Top-level routines for generating and decoding the PBCH/BCH physical/transport channel V8.6 2009-03, V14.1 (FeMBMS) * \author R. Knopp, F. Kaltenberger * \date 2011 * \version 0.1 * \company Eurecom -* \email: knopp@eurecom.fr,florian.kaltenberger.fr +* \email: knopp@eurecom.fr,florian.kaltenberger.fr, javier.morgade@ieee.org * \note * \warning */ @@ -139,6 +139,285 @@ int allocate_pbch_REs_in_RB(LTE_DL_FRAME_PARMS *frame_parms, return(0); } +void pbch_scrambling_fembms(LTE_DL_FRAME_PARMS *frame_parms, + uint8_t *pbch_e, + uint32_t length) +{ + int i; + uint8_t reset; + uint32_t x1, x2, s=0; + + reset = 1; + // x1 is set in lte_gold_generic + x2 = frame_parms->Nid_cell + (1<<9); //this is c_init for FeMBMS in 36.211 Sec 6.6.1 + // msg("pbch_scrambling: Nid_cell = %d\n",x2); + + for (i=0; i>(i&0x1f))&1); + + } +} + +int generate_pbch_fembms(LTE_eNB_PBCH *eNB_pbch, + int32_t **txdataF, + int amp, + LTE_DL_FRAME_PARMS *frame_parms, + uint8_t *pbch_pdu, + uint8_t frame_mod4) +{ + + int i, l; + + uint32_t pbch_D,pbch_E;//,pbch_coded_bytes; + uint8_t pbch_a[PBCH_A>>3]; + uint8_t RCC; + + uint32_t nsymb = (frame_parms->Ncp==NORMAL) ? 14:12; + uint32_t pilots; +#ifdef INTERFERENCE_MITIGATION + uint32_t pilots_2; +#endif + uint32_t second_pilot = (frame_parms->Ncp==NORMAL) ? 4 : 3; + uint32_t jj=0; + uint32_t re_allocated=0; + uint32_t rb, re_offset, symbol_offset; + uint16_t amask=0; + + pbch_D = 16+PBCH_A; + + pbch_E = (frame_parms->Ncp==NORMAL) ? 1920 : 1728; //RE/RB * #RB * bits/RB (QPSK) + // pbch_E_bytes = pbch_coded_bits>>3; + + LOG_D(PHY,"%s(eNB_pbch:%p txdataF:%p amp:%d frame_parms:%p pbch_pdu:%p frame_mod4:%d)\n", __FUNCTION__, eNB_pbch, txdataF, amp, frame_parms, pbch_pdu, frame_mod4==0); + + if (frame_mod4==0) { + bzero(pbch_a,PBCH_A>>3); + bzero(eNB_pbch->pbch_e,pbch_E); + memset(eNB_pbch->pbch_d,LTE_NULL,96); + // Encode data + + // CRC attachment + // crc = (uint16_t) (crc16(pbch_pdu, pbch_crc_bits-16) >> 16); + + /* + // scramble crc with PBCH CRC mask (Table 5.3.1.1-1 of 3GPP 36.212-860) + switch (frame_parms->nb_antenna_ports_eNB) { + case 1: + crc = crc ^ (uint16_t) 0; + break; + case 2: + crc = crc ^ (uint16_t) 0xFFFF; + break; + case 4: + crc = crc ^ (uint16_t) 0xAAAA; + break; + default: + msg("[PBCH] Unknown number of TX antennas!\n"); + break; + } + */ + + // Fix byte endian of PBCH (bit 23 goes in first) + for (i=0; i<(PBCH_A>>3); i++) + pbch_a[(PBCH_A>>3)-i-1] = pbch_pdu[i]; + + // pbch_data[i] = ((char*) &crc)[0]; + // pbch_data[i+1] = ((char*) &crc)[1]; + //#ifdef DEBUG_PBCH + + for (i=0; i<(PBCH_A>>3); i++) + LOG_D(PHY,"[PBCH] pbch_data[%d] = %x\n",i,pbch_a[i]); + + //#endif + + if (frame_parms->nb_antenna_ports_eNB == 1) + amask = 0x0000; + else { + switch (frame_parms->nb_antenna_ports_eNB) { + case 1: + amask = 0x0000; + break; + + case 2: + amask = 0xffff; + break; + + case 4: + amask = 0x5555; + } + } + + ccodelte_encode(PBCH_A,2,pbch_a,eNB_pbch->pbch_d+96,amask); + + +#ifdef DEBUG_PBCH_ENCODING + + for (i=0; i<16+PBCH_A; i++) + LOG_D(PHY,"%d : (%d,%d,%d)\n",i,*(eNB_pbch->pbch_d+96+(3*i)),*(eNB_pbch->pbch_d+97+(3*i)),*(eNB_pbch->pbch_d+98+(3*i))); + +#endif //DEBUG_PBCH_ENCODING + + // Bit collection + /* + j2=0; + for (j=0;j 0) { // bit is to be transmitted + pbch_coded_data2[j2++] = pbch_coded_data[j]&1; + //Bit is repeated + if ((pbch_coded_data[j]&0x40)>0) + pbch_coded_data2[j2++] = pbch_coded_data[j]&1; + } + } + + #ifdef DEBUG_PBCH + msg("[PBCH] rate matched bits=%d, pbch_coded_bits=%d, pbch_crc_bits=%d\n",j2,pbch_coded_bits,pbch_crc_bits); + #endif + + #ifdef DEBUG_PBCH + LOG_M"pbch_encoded_output2.m","pbch_encoded_out2", + pbch_coded_data2, + pbch_coded_bits, + 1, + 4); + #endif //DEBUG_PBCH + */ +#ifdef DEBUG_PBCH_ENCODING + LOG_D(PHY,"Doing PBCH interleaving for %d coded bits, e %p\n",pbch_D,eNB_pbch->pbch_e); +#endif + RCC = sub_block_interleaving_cc(pbch_D,eNB_pbch->pbch_d+96,eNB_pbch->pbch_w); + + lte_rate_matching_cc(RCC,pbch_E,eNB_pbch->pbch_w,eNB_pbch->pbch_e); + +#ifdef DEBUG_PBCH_ENCODING + LOG_D(PHY,"PBCH_e:\n"); + + for (i=0; ipbch_e+i)); + + LOG_D(PHY,"\n"); +#endif + + + +#ifdef DEBUG_PBCH + if (frame_mod4==0) { + LOG_M("pbch_e.m","pbch_e", + eNB_pbch->pbch_e, + pbch_E, + 1, + 4); + + for (i=0; i<16; i++) + printf("e[%d] %d\n",i,eNB_pbch->pbch_e[i]); + } +#endif //DEBUG_PBCH + // scrambling + + pbch_scrambling_fembms(frame_parms, + eNB_pbch->pbch_e, + pbch_E); +#ifdef DEBUG_PBCH + if (frame_mod4==0) { + LOG_M("pbch_e_s.m","pbch_e_s", + eNB_pbch->pbch_e, + pbch_E, + 1, + 4); + + for (i=0; i<16; i++) + printf("e_s[%d] %d\n",i,eNB_pbch->pbch_e[i]); + } +#endif //DEBUG_PBCH + } // frame_mod4==0 + + // modulation and mapping (slot 1, symbols 0..3) + for (l=(nsymb>>1); l<(nsymb>>1)+4; l++) { + + pilots=0; +#ifdef INTERFERENCE_MITIGATION + pilots_2 = 0; +#endif + + if ((l==0) || (l==(nsymb>>1))) { + pilots=1; +#ifdef INTERFERENCE_MITIGATION + pilots_2=1; +#endif + } + + if ((l==1) || (l==(nsymb>>1)+1)) { + pilots=1; + } + + if ((l==second_pilot)||(l==(second_pilot+(nsymb>>1)))) { + pilots=1; + } + +#ifdef DEBUG_PBCH + LOG_D(PHY,"[PBCH] l=%d, pilots=%d\n",l,pilots); +#endif + + + re_offset = frame_parms->ofdm_symbol_size-3*12; + symbol_offset = frame_parms->ofdm_symbol_size*l; + + for (rb=0; rb<6; rb++) { + +#ifdef DEBUG_PBCH + LOG_D(PHY,"RB %d, jj %d, re_offset %d, symbol_offset %d, pilots %d, nushift %d\n",rb,jj,re_offset, symbol_offset, pilots,frame_parms->nushift); +#endif + allocate_pbch_REs_in_RB(frame_parms, + txdataF, + &jj, + re_offset, + symbol_offset, + &eNB_pbch->pbch_e[frame_mod4*(pbch_E>>2)], + pilots, +#ifdef INTERFERENCE_MITIGATION + (pilots_2==1)?(amp/3):amp, +#else + amp, +#endif + &re_allocated); + + re_offset+=12; // go to next RB + + // check if we crossed the symbol boundary and skip DC + + if (re_offset >= frame_parms->ofdm_symbol_size) + re_offset=1; + } + + // } + } + +#ifdef DEBUG_PBCH + printf("[PBCH] txdataF=\n"); + + for (i=0; iofdm_symbol_size; i++) { + printf("%d=>(%d,%d)",i,((short*)&txdataF[0][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[0], + ((short*)&txdataF[0][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[1]); + + if (frame_parms->nb_antenna_ports_eNB!=1) { + printf("(%d,%d)\n",((short*)&txdataF[1][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[0], + ((short*)&txdataF[1][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[1]); + } else { + printf("\n"); + } + } + +#endif + + + return(0); +} + void pbch_scrambling(LTE_DL_FRAME_PARMS *frame_parms, uint8_t *pbch_e, uint32_t length) From 459eff02d1488ac190a20773f8f3730411848ad6 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 10:58:57 +0200 Subject: [PATCH 17/70] fembms: Top-level routines for generating DL mbsfn reference signals for FeMBMS (eNB) Signed-off-by: Javier Morgade --- openair1/PHY/LTE_TRANSPORT/dlsch_coding.c | 2 +- openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c | 2 +- openair1/PHY/LTE_TRANSPORT/pbch.c | 2 +- openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c | 34 +++++++++++++++++-- 4 files changed, 34 insertions(+), 6 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c index ce4e6fba9f..3eb44d98fa 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c @@ -21,7 +21,7 @@ /*! \file PHY/LTE_TRANSPORT/dlsch_coding.c * \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03, V14.1 2017 (includes FeMBMS support) - * \author R. Knopp + * \author R. Knopp, J. Morgade * \date 2011 * \version 0.1 * \company Eurecom diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c index eeb701657a..8c07421b7e 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c @@ -21,7 +21,7 @@ /*! \file PHY/LTE_TRANSPORT/dlsch_modulation.c * \brief Top-level routines for generating the PDSCH physical channel from 36-211, V8.6 2009-03, V14.1 2017 (FeMBMS) - * \author R. Knopp, F. Kaltenberger + * \author R. Knopp, F. Kaltenberger, J. Morgade * \date 2011 * \version 0.1 * \company Eurecom diff --git a/openair1/PHY/LTE_TRANSPORT/pbch.c b/openair1/PHY/LTE_TRANSPORT/pbch.c index a142f22a54..dfa990269e 100644 --- a/openair1/PHY/LTE_TRANSPORT/pbch.c +++ b/openair1/PHY/LTE_TRANSPORT/pbch.c @@ -21,7 +21,7 @@ /*! \file PHY/LTE_TRANSPORT/pbch.c * \brief Top-level routines for generating and decoding the PBCH/BCH physical/transport channel V8.6 2009-03, V14.1 (FeMBMS) -* \author R. Knopp, F. Kaltenberger +* \author R. Knopp, F. Kaltenberger, J. Morgade * \date 2011 * \version 0.1 * \company Eurecom diff --git a/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c b/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c index 475102b57c..47ef6428cb 100644 --- a/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c +++ b/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c @@ -20,12 +20,12 @@ */ /*! \file PHY/LTE_TRANSPORT/pilots_mbsfn.c -* \brief Top-level routines for generating DL mbsfn reference signals -* \authors S. Paranche, R. Knopp +* \brief Top-level routines for generating DL mbsfn reference signals / DL mbsfn reference signals for FeMBMS +* \authors S. Paranche, R. Knopp, J. Morgade * \date 2012 * \version 0.1 * \company Eurecom -* \email: knopp@eurecom.fr +* \email: knopp@eurecom.fr, javier.morgade@ieee.org * \note * \warning */ @@ -85,3 +85,31 @@ int generate_mbsfn_pilot(PHY_VARS_eNB *eNB, } +int generate_mbsfn_pilot_khz_1dot25(PHY_VARS_eNB *eNB, + L1_rxtx_proc_t *proc, + int32_t **txdataF, + int16_t amp) + +{ + + LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms; + uint32_t subframe_offset,Nsymb; + int subframe = proc->subframe_tx; + + + if (subframe<0 || subframe>= 10) { + LOG_E(PHY,"generate_mbsfn_pilots_subframe: subframe not in range (%d)\n",subframe); + return(-1); + } + + Nsymb = (frame_parms->Ncp==NORMAL) ? 7 : 6; + + subframe_offset = subframe*frame_parms->ofdm_symbol_size*Nsymb<<1; + + lte_dl_mbsfn_khz_1dot25(eNB, + &txdataF[0][subframe_offset+0], + amp,subframe); + + return(0); +} + From 58bd55b9b39ffdca2a234871c707f32a357c7a3d Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 20 Jul 2020 11:02:18 +0200 Subject: [PATCH 18/70] fembms: -Increase buffer size in PHY_ofdm_mod to accomodate FeMBMS sizes -New FFT sizes added (IDFT_12288, IDFT_24576) to enable support for FeMBMS 10MHz and 20MHz channels BWs Signed-off-by: Javier Morgade --- openair1/PHY/MODULATION/ofdm_mod.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/MODULATION/ofdm_mod.c b/openair1/PHY/MODULATION/ofdm_mod.c index 855e649cc5..e1d21af9b9 100644 --- a/openair1/PHY/MODULATION/ofdm_mod.c +++ b/openair1/PHY/MODULATION/ofdm_mod.c @@ -88,7 +88,7 @@ void PHY_ofdm_mod(int *input, /// pointer to complex input if(nb_symbols == 0) return; - short temp[4096*4] __attribute__((aligned(32))); + short temp[2*2*6144*4] __attribute__((aligned(32))); unsigned short i,j; short k; @@ -125,9 +125,23 @@ void PHY_ofdm_mod(int *input, /// pointer to complex input case 3072: idftsize = IDFT_3072; break; + case 4096: idftsize = IDFT_4096; break; + + case 6144: + idftsize= IDFT_6144; + break; + + case 12288: + idftsize= IDFT_12288; + break; + + case 24576: + idftsize= IDFT_24576; + break; + default: idftsize = IDFT_512; break; From 8eac27b83b4b3792921e6758d000c649f8d6af2e Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 15:07:05 +0200 Subject: [PATCH 19/70] fembms: Added support for FeMBMS UE Channel Estimation Procedures for 10 and 20 MHz BWs @ FeMBMS 1.25KHz Carrier Spacing Signed-off-by: Javier Morgade --- .../lte_dl_mbsfn_channel_estimation.c | 40 +++++++++++++++---- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c index 333a6f0866..4ad050ccea 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c @@ -22,7 +22,7 @@ /*! \file config_ue.c * \brief This includes FeMBMS UE Channel Estimation Procedures for FeMBMS 1.25KHz Carrier Spacing * \author Javier Morgade - * \date 2019 + * \date 2020 * \version 0.1 * \email: javier.morgade@ieee.org * @ingroup _phy @@ -768,8 +768,8 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue, module_id_t eNB_id, uint8_t eNB_offset, int subframe) { - int pilot_khz_1dot25[600] __attribute__((aligned(16))); - unsigned char aarx/*,aa*/; + int pilot_khz_1dot25[2*2*600] __attribute__((aligned(16))); + unsigned char aarx,aa; //unsigned int rb; int16_t ch[2]; short *pil,*rxF,*dl_ch/*,*ch0,*ch1,*ch11,*chp,*ch_prev*/; @@ -783,7 +783,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue, int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF; ch_offset = 0;//(l*(ue->frame_parms.ofdm_symbol_size)); symbol_offset = 0;//ch_offset;//phy_vars_ue->lte_frame_parms.ofdm_symbol_size*l; - AssertFatal( ue->frame_parms.N_RB_DL==25,"OFDM symbol size %d not yet supported for FeMBMS\n",ue->frame_parms.N_RB_DL); + //AssertFatal( ue->frame_parms.N_RB_DL==25,"OFDM symbol size %d not yet supported for FeMBMS\n",ue->frame_parms.N_RB_DL); if( (subframe&0x1) == 0) { f=filt24_0_khz_1dot25; @@ -823,7 +823,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue, k=3; } - if(ue->frame_parms.N_RB_DL==25) { + if(1/*ue->frame_parms.N_RB_DL==25*/) { ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); multadd_real_vector_complex_scalar(fl, @@ -843,7 +843,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue, rxF+=12; dl_ch+=16; - for(pilot_cnt=2; pilot_cnt<299; pilot_cnt+=2) { + for(pilot_cnt=2; pilot_cntframe_parms.N_RB_DL*12-1/*299*/; pilot_cnt+=2) { ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); multadd_real_vector_complex_scalar(f, @@ -866,7 +866,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue, rxF = (int16_t *)&rxdataF[aarx][((symbol_offset+1+k))]; //Skip DC offset - for(pilot_cnt=0; pilot_cnt<297; pilot_cnt+=2) { + for(pilot_cnt=0; pilot_cntframe_parms.N_RB_DL*12-3/*297*/; pilot_cnt+=2) { ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); multadd_real_vector_complex_scalar(f, @@ -905,6 +905,32 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue, } } + // do ifft of channel estimate + for (aa=0; aaframe_parms.nb_antennas_rx*ue->frame_parms.nb_antennas_tx; aa++) { + if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa]) { + switch (ue->frame_parms.N_RB_DL) { + case 25: + idft(IDFT_6144,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8], + (int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa], + 1); + break; + case 50: + idft(IDFT_12288,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8], + (int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa], + 1); + break; + case 100: + idft(IDFT_24576,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8], + (int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa], + 1); + break; + default: + break; + } + } + } + + return(0); } From 5eb6dac7db84acf874107e3b14ba83e31f13db3a Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 15:09:38 +0200 Subject: [PATCH 20/70] fembms: routines for decoding the UE FeMBMS/PMCH physical/multicast/transport channel 3GPP TS 36.211 version 14.2.0 Signed-off-by: Javier Morgade --- openair1/PHY/LTE_TRANSPORT/pmch.c | 50 ++++++++++++ openair1/PHY/LTE_TRANSPORT/pmch_common.c | 99 ++++++++++++++++++++---- 2 files changed, 132 insertions(+), 17 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/pmch.c b/openair1/PHY/LTE_TRANSPORT/pmch.c index 90e2836b1e..7b508239a9 100644 --- a/openair1/PHY/LTE_TRANSPORT/pmch.c +++ b/openair1/PHY/LTE_TRANSPORT/pmch.c @@ -128,3 +128,53 @@ void generate_mch(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc,uint8_t *a) } +void generate_mch_khz_1dot25(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc,uint8_t *a) +{ + + int G; + int subframe = proc->subframe_tx; + int frame = proc->frame_tx; + //int bits; + + G = get_G_khz_1dot25(&eNB->frame_parms, + eNB->frame_parms.N_RB_DL, + eNB->dlsch_MCH->harq_processes[0]->rb_alloc, + get_Qm(eNB->dlsch_MCH->harq_processes[0]->mcs),1, + 2,proc->frame_tx,subframe,0); + + //FeMBMS + eNB->dlsch_MCH->harq_processes[0]->Qm = get_Qm(eNB->dlsch_MCH->harq_processes[0]->mcs); + + + generate_mbsfn_pilot_khz_1dot25(eNB,proc, + eNB->common_vars.txdataF, + AMP); + + + AssertFatal(dlsch_encoding_fembms_pmch(eNB, + proc, + // a, + eNB->dlsch_MCH->harq_processes[0]->pdu, + 1, + eNB->dlsch_MCH, + proc->frame_tx, + subframe, + &eNB->dlsch_rate_matching_stats, + &eNB->dlsch_turbo_encoding_stats, + &eNB->dlsch_interleaving_stats)==0, + "problem in dlsch_encoding"); + + + /*for(bits=0;bitsdlsch_MCH->harq_processes[0]->e[bits]); + printf("\n");*/ + + dlsch_scrambling(&eNB->frame_parms,1,eNB->dlsch_MCH,0,G,0,frame,subframe<<1); + + mch_modulation_khz_1dot25(eNB->common_vars.txdataF, + AMP, + subframe, + &eNB->frame_parms, + eNB->dlsch_MCH); +} + diff --git a/openair1/PHY/LTE_TRANSPORT/pmch_common.c b/openair1/PHY/LTE_TRANSPORT/pmch_common.c index 03bf5a378b..8d65dd2744 100644 --- a/openair1/PHY/LTE_TRANSPORT/pmch_common.c +++ b/openair1/PHY/LTE_TRANSPORT/pmch_common.c @@ -37,23 +37,84 @@ int is_fembms_cas_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms) { - uint32_t period; + //uint32_t period; - if(frame_parms->NonMBSFN_config_flag ) { - period = 4<NonMBSFN_config.radioframeAllocationPeriod; + //if(frame_parms->NonMBSFN_config_flag ) { + // period = 4<NonMBSFN_config.radioframeAllocationPeriod; - if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) { + // if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) { + // switch (subframe) { + // case 0: + // return(1); //This should be CAS + // break; + // } + // } + //} + if(frame_parms->NonMBSFN_config_flag || frame_parms->FeMBMS_active){ + if ((frame&3)==0) { switch (subframe) { case 0: - return(1); //This should be CAS - break; + return(1); //This should be CAS + break; } - } + } + } return (0); } +int is_fembms_nonMBSFN_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms){ + uint32_t period; + if(frame_parms->NonMBSFN_config_flag ) { + period = 4<NonMBSFN_config.radioframeAllocationPeriod; + if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) { + switch (subframe) { + case 0: + return(1); //This should be CAS + break; + case 1: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x100) > 0) + return(1); + break; + case 2: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x80) > 0) + return(1); + break; + case 3: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x40) > 0) + return(1); + break; + case 4: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x20) > 0) + return(1); + break; + case 5: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x10) > 0) + return(1); + break; + case 6: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x8) > 0) + return(1); + break; + case 7: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x4) > 0) + return(1); + break; + case 8: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x2) > 0) + return(1); + break; + case 9: + if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x1) > 0) + return(1); + break; + } + } + } + return (0); +} + int is_fembms_pmch_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms) { uint32_t period; @@ -62,63 +123,67 @@ int is_fembms_pmch_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *fr if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) { switch (subframe) { + case 0: + return(0); + break; case 1: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x100) > 0) - return(1); + return(0); break; case 2: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x80) > 0) - return(1); + return(0); break; case 3: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x40) > 0) - return(1); + return(0); break; case 4: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x20) > 0) - return(1); + return(0); break; case 5: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x10) > 0) - return(1); + return(0); break; case 6: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x8) > 0) - return(1); + return(0); break; case 7: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x4) > 0) - return(1); + return(0); break; case 8: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x2) > 0) - return(1); + return(0); break; case 9: if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x1) > 0) - return(1); + return(0); break; } - } else { //Then regular MBSFN FeMBMS subframe + } else if((frame_parms->FeMBMS_active == 1 || frame_parms->NonMBSFN_config_flag == 1 ) && !is_fembms_cas_subframe(frame,subframe,frame_parms) ) { //Then regular MBSFN FeMBMS subframe return(1); } + return(1); } return(0); From 0bef84d0a5bf4027a9538590e3d6f4119568fbe2 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 15:16:49 +0200 Subject: [PATCH 21/70] fembms: - FeMBMS 36.213 eNB procedures v14.2 - FeMBMS 36.213 UE procedures v14.2 - Implementation of OFDM encoding for FeMBMS/eNB v14.2 Signed-off-by: Javier Morgade --- openair1/SCHED/phy_procedures_lte_eNb.c | 138 ++++++++++++++++++++-- openair1/SCHED/ru_procedures.c | 25 +++- openair1/SCHED_UE/phy_procedures_lte_ue.c | 50 +++++++- 3 files changed, 198 insertions(+), 15 deletions(-) diff --git a/openair1/SCHED/phy_procedures_lte_eNb.c b/openair1/SCHED/phy_procedures_lte_eNb.c index fc9407f8d0..6717b045ac 100644 --- a/openair1/SCHED/phy_procedures_lte_eNb.c +++ b/openair1/SCHED/phy_procedures_lte_eNb.c @@ -20,12 +20,12 @@ */ /*! \file phy_procedures_lte_eNB.c - * \brief Implementation of eNB procedures from 36.213 LTE specifications - * \author R. Knopp, F. Kaltenberger, N. Nikaein, X. Foukas + * \brief Implementation of eNB procedures from 36.213 LTE specifications / FeMBMS 36.231 LTE procedures v14.2 + * \author R. Knopp, F. Kaltenberger, N. Nikaein, X. Foukas, J. Morgade * \date 2011 * \version 0.1 * \company Eurecom - * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr,navid.nikaein@eurecom.fr, x.foukas@sms.ed.ac.uk + * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr,navid.nikaein@eurecom.fr, x.foukas@sms.ed.ac.uk, javier.morgade@ieee.org * \note * \warning */ @@ -122,12 +122,32 @@ lte_subframe_t get_subframe_direction(uint8_t Mod_id,uint8_t CC_id,uint8_t subfr } #ifdef MBMS_NFAPI_SCHEDULER -void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { +void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, int fembms_flag) { int subframe = proc->subframe_tx; // This is DL-Cell spec pilots in Control region - generate_pilots_slot (eNB, eNB->common_vars.txdataF, AMP, subframe << 1, 1); - if(eNB->dlsch_MCH->active==1) - generate_mch (eNB, proc,NULL/*, eNB->dlsch_MCH->harq_processes[0]->pdu*/); + if(!fembms_flag){ + generate_pilots_slot (eNB, eNB->common_vars.txdataF, AMP, subframe << 1, 1); + generate_mbsfn_pilot(eNB,proc, + eNB->common_vars.txdataF, + AMP); + }else + generate_mbsfn_pilot_khz_1dot25(eNB,proc, + eNB->common_vars.txdataF, + AMP); + + if(eNB->dlsch_MCH->active==1){ + if(!fembms_flag){ + generate_mch (eNB, proc,NULL/*, eNB->dlsch_MCH->harq_processes[0]->pdu*/); + } + else{ + generate_mch_khz_1dot25 (eNB, proc,NULL/*, eNB->dlsch_MCH->harq_processes[0]->pdu*/); + } + + LOG_D(PHY,"[eNB%"PRIu8"] Frame %d subframe %d : Got MCH pdu for MBSFN (TBS %d) fembms %d \n", + eNB->Mod_id,proc->frame_tx,subframe, + eNB->dlsch_MCH->harq_processes[0]->TBS>>3,fembms_flag); + + } eNB->dlsch_MCH->active = 0; } #else @@ -171,6 +191,80 @@ void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) { } #endif +void common_signal_procedures_fembms (PHY_VARS_eNB *eNB,int frame, int subframe) { + LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms; + int **txdataF = eNB->common_vars.txdataF; + uint8_t *pbch_pdu=&eNB->pbch_pdu[0]; + + if((frame&3)!=0 /*&& subframe != 0*/) + return; + + LOG_I(PHY,"common_signal_procedures: frame %d, subframe %d fdd:%s dir:%s index:%d\n",frame,subframe,fp->frame_type == FDD?"FDD":"TDD", subframe_select(fp,subframe) == SF_DL?"DL":"UL?",(frame&15)/4); + // generate Cell-Specific Reference Signals for both slots + //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_RS_TX,1); + + + if(subframe_select(fp,subframe) == SF_S) + generate_pilots_slot(eNB, + txdataF, + AMP, + subframe<<1,1); + else + generate_pilots_slot(eNB, + txdataF, + AMP, + subframe<<1,0); + + // check that 2nd slot is for DL + if (subframe_select (fp, subframe) == SF_DL) + generate_pilots_slot (eNB, txdataF, AMP, (subframe << 1) + 1, 0); + + //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME (VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_RS_TX, 0); + + // First half of PSS/SSS (FDD, slot 0) + if (subframe == 0) { + //if (fp->frame_type == FDD) { + generate_pss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 6 : 5, 0); + generate_sss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 5 : 4, 0); + //} + + /// First half of SSS (TDD, slot 1) + + //if (fp->frame_type == TDD) { + generate_sss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 6 : 5, 1); + //} + + // generate PBCH (Physical Broadcast CHannel) info + + /// generate PBCH + if ((frame&15)==0) { + //AssertFatal(eNB->pbch_configured==1,"PBCH was not configured by MAC\n"); + if (eNB->pbch_configured!=1) return; + + eNB->pbch_configured=0; + } + + T(T_ENB_PHY_MIB, T_INT(eNB->Mod_id), T_INT(frame), T_INT(subframe), + T_BUFFER(pbch_pdu, 3)); + generate_pbch_fembms (&eNB->pbch, txdataF, AMP, fp, pbch_pdu, (frame & 15)/4); + } //else if ((subframe == 1) && (fp->frame_type == TDD)) { + //generate_pss (txdataF, AMP, fp, 2, 2); + // } + // Second half of PSS/SSS (FDD, slot 10) + else if ((subframe == 5) && (fp->frame_type == FDD) && is_fembms_nonMBSFN_subframe(frame,subframe,fp)) { + generate_pss (txdataF, AMP, &eNB->frame_parms, (fp->Ncp == NORMAL) ? 6 : 5, 10); + generate_sss (txdataF, AMP, &eNB->frame_parms, (fp->Ncp == NORMAL) ? 5 : 4, 10); + } + // Second-half of SSS (TDD, slot 11) + // else if ((subframe == 5) && (fp->frame_type == TDD)) { + // generate_sss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 6 : 5, 11); + // } + // Second half of PSS (TDD, slot 12) + // else if ((subframe == 6) && (fp->frame_type == TDD)) { + // generate_pss (txdataF, AMP, fp, 2, 12); + // } +} + void common_signal_procedures (PHY_VARS_eNB *eNB,int frame, int subframe) { LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms; int **txdataF = eNB->common_vars.txdataF; @@ -417,12 +511,30 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB, } if (NFAPI_MODE==NFAPI_MONOLITHIC || NFAPI_MODE==NFAPI_MODE_PNF) { + if (is_fembms_pmch_subframe(frame,subframe,fp)) { +#ifdef MBMS_NFAPI_SCHEDULER + pmch_procedures(eNB,proc,1); + LOG_D(MAC,"frame %d, subframe %d -> PMCH\n",frame,subframe); + return; +#endif + }else if(is_fembms_cas_subframe(frame,subframe,fp) || is_fembms_nonMBSFN_subframe(frame,subframe,fp)){ + LOG_D(MAC,"frame %d, subframe %d -> CAS\n",frame,subframe); + common_signal_procedures_fembms(eNB,proc->frame_tx, proc->subframe_tx); + //return; + } + + if((!is_fembms_cas_subframe(frame,subframe,fp)) && (!is_fembms_nonMBSFN_subframe(frame,subframe,fp))){ if (is_pmch_subframe(frame,subframe,fp)) { +#ifdef MBMS_NFAPI_SCHEDULER + pmch_procedures(eNB,proc,0); +#else pmch_procedures(eNB,proc); +#endif } else { // this is not a pmch subframe, so generate PSS/SSS/PBCH common_signal_procedures(eNB,proc->frame_tx, proc->subframe_tx); } + } } // clear existing ulsch dci allocations before applying info from MAC (this is table @@ -508,6 +620,18 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB, if (do_meas==1) start_meas(&eNB->dlsch_ue_specific); + if (NFAPI_MODE==NFAPI_MONOLITHIC || NFAPI_MODE==NFAPI_MODE_PNF) { + if (is_fembms_pmch_subframe(frame,subframe,fp)) { +#ifdef MBMS_NFAPI_SCHEDULER + pmch_procedures(eNB,proc,1); + return; +#endif + }else if(is_fembms_cas_subframe(frame,subframe,fp)){ + common_signal_procedures_fembms(eNB,proc->frame_tx, proc->subframe_tx); + } + } + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1); // Now scan UE specific DLSCH diff --git a/openair1/SCHED/ru_procedures.c b/openair1/SCHED/ru_procedures.c index cb03821388..e472d64db4 100644 --- a/openair1/SCHED/ru_procedures.c +++ b/openair1/SCHED/ru_procedures.c @@ -41,6 +41,17 @@ * \warning */ +/*! \function feptx0 + * \brief Implementation of ofdm encoding for FeMBMS profile in one eNB + * \author J. Morgade + * \date 2020 + * \version 0.1 + * \email: javier.morgade@ieee.org + * \note + * \warning + */ + + #include "PHY/defs_eNB.h" #include "PHY/phy_extern.h" @@ -76,7 +87,7 @@ void feptx0(RU_t *ru, int slot_sizeF = (fp->ofdm_symbol_size) * ((fp->Ncp==1) ? 6 : 7); int subframe = ru->proc.tti_tx; - //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+slot , 1 ); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+(slot&1) , 1 ); slot_offset = slot*(fp->samples_per_tti>>1); //slot_offset = subframe*fp->samples_per_tti + (slot*(fp->samples_per_tti>>1)); @@ -91,7 +102,17 @@ void feptx0(RU_t *ru, fp->nb_prefix_samples, CYCLIC_PREFIX); } else { - if(is_pmch_subframe(ru->proc.frame_tx,subframe,fp)){ + if(is_fembms_pmch_subframe(ru->proc.frame_tx,subframe,fp)){ + if((slot&1)==0){//just use one slot chance + PHY_ofdm_mod(&ru->common.txdataF_BF[aa][(slot&1)*slot_sizeF], + (int*)&ru->common.txdata[aa][slot_offset], + fp->ofdm_symbol_size_khz_1dot25, + 1, + fp->ofdm_symbol_size_khz_1dot25>>2, + CYCLIC_PREFIX); + LOG_D(HW,"Generating PMCH FeMBMS TX subframe %d %d\n",subframe,fp->ofdm_symbol_size_khz_1dot25); + } + } else if(is_pmch_subframe(ru->proc.frame_tx,subframe,fp)){ if ((slot&1) == 0) {//just use one slot chance normal_prefix_mod(&ru->common.txdataF_BF[aa][(slot&1)*slot_sizeF], (int*)&ru->common.txdata[aa][slot_offset], diff --git a/openair1/SCHED_UE/phy_procedures_lte_ue.c b/openair1/SCHED_UE/phy_procedures_lte_ue.c index e0ea4ef2b2..9f0b965e0c 100644 --- a/openair1/SCHED_UE/phy_procedures_lte_ue.c +++ b/openair1/SCHED_UE/phy_procedures_lte_ue.c @@ -2383,10 +2383,12 @@ void ue_pbch_procedures(uint8_t eNB_id, if (pbch_phase>=4) pbch_phase=0; +if((ue->frame_parms.FeMBMS_active == 0)|| is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || first_run) { + for (pbch_trials=0; pbch_trials<4; pbch_trials++) { //for (pbch_phase=0;pbch_phase<4;pbch_phase++) { //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, eNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,eNB_id); - if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms)) { + if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || ue->frame_parms.FeMBMS_active) { pbch_tx_ant = rx_pbch_fembms(&ue->common_vars, ue->pbch_vars[eNB_id], &ue->frame_parms, @@ -2431,9 +2433,10 @@ void ue_pbch_procedures(uint8_t eNB_id, ue->pbch_vars[eNB_id]->pdu_errors_conseq = 0; - if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms)) { + if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || ue->frame_parms.FeMBMS_active) { frame_tx = (int)((ue->pbch_vars[eNB_id]->decoded_output[2]&31)<<1); frame_tx += ue->pbch_vars[eNB_id]->decoded_output[1]>>7; + frame_tx = frame_tx<<4; frame_tx +=4*pbch_phase; } else { frame_tx = (((int)(ue->pbch_vars[eNB_id]->decoded_output[2]&0x03))<<8); @@ -2501,6 +2504,17 @@ void ue_pbch_procedures(uint8_t eNB_id, ue->frame_parms.phich_config_common.phich_duration, ue->frame_parms.phich_config_common.phich_resource); } + LOG_I(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n", + ue->Mod_id, + frame_rx, + subframe_rx, + ue->frame_parms.nb_antenna_ports_eNB, + pbch_tx_ant, + frame_tx, + ue->frame_parms.N_RB_DL, + ue->frame_parms.phich_config_common.phich_duration, + ue->frame_parms.phich_config_common.phich_resource); + } else { if (LOG_DUMPFLAG(DEBUG_UE_PHYPROC)) { LOG_E(PHY,"[UE %d] frame %d, subframe %d, Error decoding PBCH!\n", @@ -2533,6 +2547,8 @@ void ue_pbch_procedures(uint8_t eNB_id, ue->pbch_vars[eNB_id]->pdu_errors_conseq); } +} //if((ue->frame_parms.FeMBMS_active == 0)|| is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || first_run) + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_OUT); } @@ -2691,6 +2707,7 @@ int ue_pdcch_procedures(uint8_t eNB_id, if (LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) { LOG_D(PHY,"[UE %d] subframe %d: Found rnti %x, format 1%s, dci_cnt %d\n",ue->Mod_id,subframe_rx,dci_alloc_rx[i].rnti,dci_alloc_rx[i].format==format1A?"A":"C",i); } + LOG_W(PHY,"[UE %d] subframe %d: Found rnti %x, format 1%s, dci_cnt %d\n",ue->Mod_id,subframe_rx,dci_alloc_rx[i].rnti,dci_alloc_rx[i].format==format1A?"A":"C",i); if (generate_ue_dlsch_params_from_dci(frame_rx, subframe_rx, @@ -2709,7 +2726,7 @@ int ue_pdcch_procedures(uint8_t eNB_id, ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id], 0)==0) { ue->dlsch_SI_received[eNB_id]++; - LOG_D(PHY,"[UE %d] Frame %d, subframe %d : Generate UE DLSCH SI_RNTI format 1%s\n",ue->Mod_id,frame_rx,subframe_rx,dci_alloc_rx[i].format==format1A?"A":"C"); + LOG_W(PHY,"[UE %d] Frame %d, subframe %d : Generate UE DLSCH SI_RNTI format 1%s\n",ue->Mod_id,frame_rx,subframe_rx,dci_alloc_rx[i].format==format1A?"A":"C"); //dump_dci(&ue->frame_parms, &dci_alloc_rx[i]); } } else if ((dci_alloc_rx[i].rnti == P_RNTI) && @@ -2877,10 +2894,19 @@ void ue_pmch_procedures(PHY_VARS_UE *ue, int l; int ret=0; - if (is_pmch_subframe(frame_rx,subframe_rx,&ue->frame_parms)) { + if (is_pmch_subframe(frame_rx,subframe_rx,&ue->frame_parms) || fembms_flag) { // LOG_D(PHY,"ue calling pmch subframe ..\n "); LOG_D(PHY,"[UE %d] Frame %d, subframe %d: Querying for PMCH demodulation\n", ue->Mod_id,frame_rx,subframe_rx); + if(fembms_flag) + pmch_mcs = ue_query_mch_fembms(ue->Mod_id, + CC_id, + frame_rx, + subframe_rx, + eNB_id, + &sync_area, + &mcch_active); + else pmch_mcs = ue_query_mch(ue->Mod_id, CC_id, frame_rx, @@ -2960,6 +2986,7 @@ void ue_pmch_procedures(PHY_VARS_UE *ue, LOG_D(PHY,"start turbo decode for MCH %d.%d --> Nl %d \n", frame_rx, subframe_rx, ue->dlsch_MCH[0]->harq_processes[0]->Nl); LOG_D(PHY,"start turbo decode for MCH %d.%d --> G %d \n", frame_rx, subframe_rx, ue->dlsch_MCH[0]->harq_processes[0]->G); LOG_D(PHY,"start turbo decode for MCH %d.%d --> Kmimo %d \n", frame_rx, subframe_rx, ue->dlsch_MCH[0]->Kmimo); + ret = dlsch_decoding(ue, ue->pdsch_vars_MCH[ue->current_thread_id[subframe_rx]][0]->llr[0], &ue->frame_parms, @@ -3007,14 +3034,14 @@ void ue_pmch_procedures(PHY_VARS_UE *ue, // if (subframe_rx==9) // mac_xface->macphy_exit("Why are we exiting here?"); } else { // decoding successful - LOG_D(PHY,"[UE %d] Frame %d, subframe %d: PMCH OK (%d,%d), passing to L2 (TBS %d, iter %d,G %d)\n", + LOG_I(PHY,"[UE %d] Frame %d, subframe %d: PMCH OK (%d,%d), passing to L2 (TBS %d, iter %d,G %d) ret %d\n", ue->Mod_id, frame_rx,subframe_rx, ue->dlsch_mcch_errors[sync_area][0], ue->dlsch_mtch_errors[sync_area][0], ue->dlsch_MCH[0]->harq_processes[0]->TBS>>3, ue->dlsch_MCH[0]->max_turbo_iterations, - ue->dlsch_MCH[0]->harq_processes[0]->G); + ue->dlsch_MCH[0]->harq_processes[0]->G,ret); ue_send_mch_sdu(ue->Mod_id, CC_id, frame_rx, @@ -3022,6 +3049,8 @@ void ue_pmch_procedures(PHY_VARS_UE *ue, ue->dlsch_MCH[0]->harq_processes[0]->TBS>>3, eNB_id,// not relevant in eMBMS context sync_area); + //dump_mch(ue,0,ue->dlsch_MCH[0]->harq_processes[0]->G,subframe_rx); + //exit_fun("nothing to add"); if (mcch_active == 1) ue->dlsch_mcch_received[sync_area][0]++; @@ -4429,6 +4458,15 @@ int phy_procedures_UE_RX(PHY_VARS_UE *ue, ue_pmch_procedures(ue,proc,eNB_id,abstraction_flag,1); return 0; } else { // this gets closed at end + if (is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || is_fembms_nonMBSFN_subframe(frame_rx,subframe_rx,&ue->frame_parms) ) { + l=0; + slot_fep(ue, + l, + subframe_rx<<1, + 0, + 0, + 0); + } pmch_flag = is_pmch_subframe(frame_rx,subframe_rx,&ue->frame_parms) ? 1 : 0; if (do_pdcch_flag) { From 220ba2ebc83a5a7ffcd114e439f0a5c07e095bcf Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 15:20:10 +0200 Subject: [PATCH 22/70] fembms: new mbmssim target (TOCHECK) Signed-off-by: Javier Morgade --- openair1/SIMULATION/LTE_PHY/mbmssim.c | 2596 +++++++++++++++++++++---- 1 file changed, 2205 insertions(+), 391 deletions(-) diff --git a/openair1/SIMULATION/LTE_PHY/mbmssim.c b/openair1/SIMULATION/LTE_PHY/mbmssim.c index 65415e7c68..5073be24f5 100644 --- a/openair1/SIMULATION/LTE_PHY/mbmssim.c +++ b/openair1/SIMULATION/LTE_PHY/mbmssim.c @@ -19,204 +19,1048 @@ * contact@openairinterface.org */ +/*! \file mbmssim.c + \brief Top-level MBMS DL simulator + \authors R. Knopp, J. Morgade + \date 2011 - 2014 (Knopp) / 2020 (Morgade) + \version 0.1 + \company Eurecom + \email: knopp@eurecom.fr, javier.morgade@ieee.org + \note + \warning +*/ + #include #include #include -#include -#include -#include +#include +#include -#include "SIMULATION/TOOLS/defs.h" -#include "SIMULATION/RF/defs.h" +#include "SIMULATION/TOOLS/sim.h" #include "PHY/types.h" -#include "PHY/defs.h" -#include "PHY/vars.h" -#include "SCHED/defs.h" -#include "SCHED/vars.h" -#include "LAYER2/MAC/vars.h" - -#ifdef XFORMS - #include "PHY/TOOLS/lte_phy_scope.h" -#endif //XFORMS +#include "PHY/defs_eNB.h" +#include "PHY/defs_UE.h" +#include "PHY/phy_vars.h" +#include "SCHED/sched_eNB.h" +#include "SCHED/sched_common_vars.h" +#include "LAYER2/MAC/mac_vars.h" #include "OCG_vars.h" +#include "common/utils/LOG/log.h" +#include "UTIL/LISTS/list.h" + #include "unitary_defs.h" -PHY_VARS_eNB *eNB; -PHY_VARS_UE *UE; +#include "PHY/TOOLS/lte_phy_scope.h" + +#include "dummy_functions.c" + +#include "PHY/MODULATION/modulation_common.h" +#include "PHY/MODULATION/modulation_eNB.h" +#include "PHY/MODULATION/modulation_UE.h" +#include "PHY/LTE_TRANSPORT/transport_proto.h" +#include "PHY/LTE_UE_TRANSPORT/transport_proto_ue.h" +#include "SCHED/sched_eNB.h" +#include "SCHED_UE/sched_UE.h" +#include "common/config/config_load_configmodule.h" +#include "PHY/INIT/phy_init.h" +#include "nfapi/oai_integration/vendor_ext.h" + +#define ENABLE_MBMS_SIM + +int enable_fembms=1; + +void feptx_ofdm(RU_t *ru); +void feptx_prec(RU_t *ru); double cpuf; +#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0)) +//#define MCS_COUNT 23//added for PHY abstraction +#include + +int otg_enabled=0; +/*the following parameters are used to control the processing times calculations*/ +double t_tx_max = -1000000000; /*!< \brief initial max process time for tx */ +double t_rx_max = -1000000000; /*!< \brief initial max process time for rx */ +double t_tx_min = 1000000000; /*!< \brief initial min process time for tx */ +double t_rx_min = 1000000000; /*!< \brief initial min process time for rx */ +int n_tx_dropped = 0; /*!< \brief initial max process time for tx */ +int n_rx_dropped = 0; /*!< \brief initial max process time for rx */ + +THREAD_STRUCT thread_struct; + +int emulate_rf = 0; + +void handler(int sig) { + void *array[10]; + size_t size; + // get void*'s for all entries on the stack + size = backtrace(array, 10); + // print out all the frames to stderr + fprintf(stderr, "Error: signal %d:\n", sig); + backtrace_symbols_fd(array, size, 2); + exit(1); +} + + + +//DCI2_5MHz_2A_M10PRB_TDD_t DLSCH_alloc_pdu2_2A[2]; DCI1E_5MHz_2A_M10PRB_TDD_t DLSCH_alloc_pdu2_1E[2]; +uint64_t DLSCH_alloc_pdu_1[2]; + #define UL_RB_ALLOC 0x1ff; #define CCCH_RB_ALLOC computeRIV(eNB->frame_parms.N_RB_UL,0,2) +//#define DLSCH_RB_ALLOC 0x1fbf // igore DC component,RB13 +//#define DLSCH_RB_ALLOC 0x0001 +void do_OFDM_mod_l(int32_t **txdataF, int32_t **txdata, uint16_t next_slot, LTE_DL_FRAME_PARMS *frame_parms) { + int aa, slot_offset, slot_offset_F; + slot_offset_F = (next_slot)*(frame_parms->ofdm_symbol_size)*((frame_parms->Ncp==1) ? 6 : 7); + slot_offset = (next_slot)*(frame_parms->samples_per_tti>>1); + + for (aa=0; aanb_antennas_tx; aa++) { + // printf("Thread %d starting ... aa %d (%llu)\n",omp_get_thread_num(),aa,rdtsc()); + if (frame_parms->Ncp == 1) + PHY_ofdm_mod(&txdataF[aa][slot_offset_F], // input + &txdata[aa][slot_offset], // output + frame_parms->ofdm_symbol_size, + 6, // number of symbols + frame_parms->nb_prefix_samples, // number of prefix samples + CYCLIC_PREFIX); + else { + normal_prefix_mod(&txdataF[aa][slot_offset_F], + &txdata[aa][slot_offset], + 7, + frame_parms); + } + } +} + +void DL_channel(RU_t *ru,PHY_VARS_UE *UE,uint subframe,int awgn_flag,double SNR, int tx_lev,int hold_channel,int abstx, int num_rounds, int trials, int round, channel_desc_t *eNB2UE[4], + double *s_re[2],double *s_im[2],double *r_re[2],double *r_im[2],FILE *csv_fd) { + int i,u; + int aa,aarx,aatx; + double channelx,channely; + double sigma2_dB,sigma2; + double iqim=0.0; + + // printf("Copying tx ..., nsymb %d (n_tx %d), awgn %d\n",nsymb,eNB->frame_parms.nb_antennas_tx,awgn_flag); + for (i=0; i<2*UE->frame_parms.samples_per_tti; i++) { + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { + if (awgn_flag == 0) { + s_re[aa][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) + (i<<1)]); + s_im[aa][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]); + } else { + for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { + if (aa==0) { + r_re[aarx][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)]); + r_im[aarx][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]); + } else { + r_re[aarx][i] += ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)]); + r_im[aarx][i] += ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]); + } + } + } + } + } + + // Multipath channel + if (awgn_flag == 0) { + multipath_channel(eNB2UE[round],s_re,s_im,r_re,r_im, + 2*UE->frame_parms.samples_per_tti,hold_channel); + + // printf("amc: ****************** eNB2UE[%d]->n_rx = %d,dd %d\n",round,eNB2UE[round]->nb_rx,eNB2UE[round]->channel_offset); + if(abstx==1 && num_rounds>1) + if(round==0 && hold_channel==0) { + random_channel(eNB2UE[1],0); + random_channel(eNB2UE[2],0); + random_channel(eNB2UE[3],0); + } + + if (UE->perfect_ce==1) { + // fill in perfect channel estimates + freq_channel(eNB2UE[round],UE->frame_parms.N_RB_DL,12*UE->frame_parms.N_RB_DL + 1); + /* + LOG_M("channel.m","ch",eNB2UE[round]->ch[0],eNB2UE[round]->channel_length,1,8); + LOG_M("channelF.m","chF",eNB2UE[round]->chF[0],12*UE->frame_parms.N_RB_DL + 1,1,8); + */ + } + } + + if(abstx) { + if (trials==0 && round==0) { + // calculate freq domain representation to compute SINR + freq_channel(eNB2UE[0], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1); + // snr=pow(10.0,.1*SNR); + fprintf(csv_fd,"%f,",SNR); + + for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) { + for (aarx=0; aarxnb_rx; aarx++) { + for (aatx=0; aatxnb_tx; aatx++) { + channelx = eNB2UE[0]->chF[aarx+(aatx*eNB2UE[0]->nb_rx)][u].x; + channely = eNB2UE[0]->chF[aarx+(aatx*eNB2UE[0]->nb_rx)][u].y; + fprintf(csv_fd,"%e+i*(%e),",channelx,channely); + } + } + } + + if(num_rounds>1) { + freq_channel(eNB2UE[1], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1); + + for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) { + for (aarx=0; aarxnb_rx; aarx++) { + for (aatx=0; aatxnb_tx; aatx++) { + channelx = eNB2UE[1]->chF[aarx+(aatx*eNB2UE[1]->nb_rx)][u].x; + channely = eNB2UE[1]->chF[aarx+(aatx*eNB2UE[1]->nb_rx)][u].y; + fprintf(csv_fd,"%e+i*(%e),",channelx,channely); + } + } + } + + freq_channel(eNB2UE[2], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1); + + for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) { + for (aarx=0; aarxnb_rx; aarx++) { + for (aatx=0; aatxnb_tx; aatx++) { + channelx = eNB2UE[2]->chF[aarx+(aatx*eNB2UE[2]->nb_rx)][u].x; + channely = eNB2UE[2]->chF[aarx+(aatx*eNB2UE[2]->nb_rx)][u].y; + fprintf(csv_fd,"%e+i*(%e),",channelx,channely); + } + } + } + + freq_channel(eNB2UE[3], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1); + + for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) { + for (aarx=0; aarxnb_rx; aarx++) { + for (aatx=0; aatxnb_tx; aatx++) { + channelx = eNB2UE[3]->chF[aarx+(aatx*eNB2UE[3]->nb_rx)][u].x; + channely = eNB2UE[3]->chF[aarx+(aatx*eNB2UE[3]->nb_rx)][u].y; + fprintf(csv_fd,"%e+i*(%e),",channelx,channely); + } + } + } + } + } + } + + //AWGN + // tx_lev is the average energy over the whole subframe + // but SNR should be better defined wrt the energy in the reference symbols + sigma2_dB = 10*log10((double)tx_lev) +10*log10((double)ru->frame_parms.ofdm_symbol_size/(double)(ru->frame_parms.N_RB_DL*12)) - SNR; + sigma2 = pow(10,sigma2_dB/10); + + for (i=0; i<2*UE->frame_parms.samples_per_tti; i++) { + for (aa=0; aaframe_parms.nb_antennas_rx; aa++) { + //printf("s_re[0][%d]=> %f , r_re[0][%d]=> %f\n",i,s_re[aa][i],i,r_re[aa][i]); + ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i] = + (short) (r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)); + ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i+1] = + (short) (r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0)); + } + } +} + +uint16_t +fill_tx_req(nfapi_tx_request_body_t *tx_req_body, + uint16_t absSF, + uint16_t pdu_length, + uint16_t pdu_index, + uint8_t *pdu) { + nfapi_tx_request_pdu_t *TX_req = &tx_req_body->tx_pdu_list[tx_req_body->number_of_pdus]; + LOG_D(MAC, "Filling TX_req %d for pdu length %d\n", + tx_req_body->number_of_pdus, pdu_length); + TX_req->pdu_length = pdu_length; + TX_req->pdu_index = pdu_index; + TX_req->num_segments = 1; + TX_req->segments[0].segment_length = pdu_length; + TX_req->segments[0].segment_data = pdu; + tx_req_body->tl.tag = NFAPI_TX_REQUEST_BODY_TAG; + tx_req_body->number_of_pdus++; + return (((absSF / 10) << 4) + (absSF % 10)); +} + +void +fill_mch_config(nfapi_dl_config_request_body_t *dl_req, + uint16_t length, + uint16_t pdu_index, + uint16_t rnti, + uint8_t resource_allocation_type, + uint16_t resource_block_coding, + uint8_t modulation, + uint16_t transmission_power, + uint8_t mbsfn_area_id){ + nfapi_dl_config_request_pdu_t *dl_config_pdu = + &dl_req->dl_config_pdu_list[dl_req->number_pdu]; + memset((void *) dl_config_pdu, 0, + sizeof(nfapi_dl_config_request_pdu_t)); + dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_MCH_PDU_TYPE; + dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_mch_pdu)); + dl_config_pdu->mch_pdu.mch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_MCH_PDU_REL8_TAG; + dl_config_pdu->mch_pdu.mch_pdu_rel8.length = length; + dl_config_pdu->mch_pdu.mch_pdu_rel8.pdu_index = pdu_index; + dl_config_pdu->mch_pdu.mch_pdu_rel8.rnti = rnti; + dl_config_pdu->mch_pdu.mch_pdu_rel8.resource_allocation_type = resource_allocation_type; + dl_config_pdu->mch_pdu.mch_pdu_rel8.resource_block_coding = resource_block_coding; + dl_config_pdu->mch_pdu.mch_pdu_rel8.modulation = modulation; + dl_config_pdu->mch_pdu.mch_pdu_rel8.transmission_power = transmission_power; + dl_config_pdu->mch_pdu.mch_pdu_rel8.mbsfn_area_id = mbsfn_area_id; + dl_req->number_pdu++; +} + +void +fill_dlsch_config(nfapi_dl_config_request_body_t *dl_req, + uint16_t length, + uint16_t pdu_index, + uint16_t rnti, + uint8_t resource_allocation_type, + uint8_t virtual_resource_block_assignment_flag, + uint16_t resource_block_coding, + uint8_t modulation, + uint8_t redundancy_version, + uint8_t transport_blocks, + uint8_t transport_block_to_codeword_swap_flag, + uint8_t transmission_scheme, + uint8_t number_of_layers, + uint8_t number_of_subbands, + // uint8_t codebook_index, + uint8_t ue_category_capacity, + uint8_t pa, + uint8_t delta_power_offset_index, + uint8_t ngap, + uint8_t nprb, + uint8_t transmission_mode, + uint8_t num_bf_prb_per_subband, + uint8_t num_bf_vector) { + nfapi_dl_config_request_pdu_t *dl_config_pdu = + &dl_req->dl_config_pdu_list[dl_req->number_pdu]; + memset((void *) dl_config_pdu, 0, + sizeof(nfapi_dl_config_request_pdu_t)); + dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DLSCH_PDU_TYPE; + dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dlsch_pdu)); + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DLSCH_PDU_REL8_TAG; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.length = length; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index = pdu_index; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti = rnti; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_allocation_type = resource_allocation_type; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.virtual_resource_block_assignment_flag = virtual_resource_block_assignment_flag; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_block_coding = resource_block_coding; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.modulation = modulation; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.redundancy_version = redundancy_version; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_blocks = transport_blocks; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_block_to_codeword_swap_flag = transport_block_to_codeword_swap_flag; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_scheme = transmission_scheme; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_layers = number_of_layers; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_subbands = number_of_subbands; + // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.codebook_index = codebook_index; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ue_category_capacity = ue_category_capacity; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pa = pa; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.delta_power_offset_index = delta_power_offset_index; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ngap = ngap; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.nprb = nprb; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_mode = transmission_mode; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_prb_per_subband = num_bf_prb_per_subband; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_vector = num_bf_vector; + dl_config_pdu->dlsch_pdu.dlsch_pdu_rel13.initial_transmission_sf_io = 0xFFFF; + dl_req->number_pdu++; +} + +void fill_MCH(PHY_VARS_eNB *eNB, + int frame, + int subframe, + Sched_Rsp_t *sched_resp, + uint8_t input_buffer[NUMBER_OF_UE_MAX][20000], + int n_rnti, + int common_flag, + int NB_RB, + int TPC, + int mcs1){ + + nfapi_dl_config_request_body_t *dl_req=&sched_resp->DL_req->dl_config_request_body; + nfapi_dl_config_request_pdu_t *dl_config_pdu; + nfapi_tx_request_body_t *TX_req=&sched_resp->TX_req->tx_request_body; + int NB_RB4TBS = common_flag == 0 ? NB_RB : (2+TPC); + dl_req->number_dci=0; + dl_req->number_pdu=0; + TX_req->number_of_pdus=0; + dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + fill_mch_config( + dl_req, + get_TBS_DL(mcs1,NB_RB4TBS), + 0, + 0xfffd, + 0, + get_Qm(mcs1), + mcs1, + 6000, //equal to RS power + 0 //mbsfn_area_id + ); + + fill_tx_req(TX_req, + (frame * 10) + subframe, + get_TBS_DL(mcs1,NB_RB4TBS), + 0, + input_buffer[0]); +} + +void fill_DCI(PHY_VARS_eNB *eNB, + int frame, + int subframe, + Sched_Rsp_t *sched_resp, + uint8_t input_buffer[NUMBER_OF_UE_MAX][20000], + int n_rnti, + int n_users, + int transmission_mode, + int retrans, + int common_flag, + int NB_RB, + int DLSCH_RB_ALLOC, + int TPC, + int mcs1, + int mcs2, + int ndi, + int rv, + int pa, + int *num_common_dci, + int *num_ue_spec_dci, + int *num_dci) { + int k; + nfapi_dl_config_request_body_t *dl_req=&sched_resp->DL_req->dl_config_request_body; + nfapi_dl_config_request_pdu_t *dl_config_pdu; + nfapi_tx_request_body_t *TX_req=&sched_resp->TX_req->tx_request_body; + int NB_RB4TBS = common_flag == 0 ? NB_RB : (2+TPC); + dl_req->number_dci=0; + dl_req->number_pdu=0; + TX_req->number_of_pdus=0; + + for(k=0; kdl_config_pdu_list[dl_req->number_pdu]; + memset((void *) dl_config_pdu, 0, + sizeof(nfapi_dl_config_request_pdu_t)); + dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; + dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = (common_flag == 0) ? NFAPI_DL_DCI_FORMAT_1 : NFAPI_DL_DCI_FORMAT_1A; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = 4; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = (common_flag == 0) ? n_rnti+k : SI_RNTI; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (common_flag ==0 ) ? 1: 2; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = 0; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = TPC; // dont adjust power when retransmitting + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = (common_flag == 0) ? ndi : 0; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = mcs1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = rv; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = (common_flag == 0) ? DLSCH_RB_ALLOC : computeRIV(eNB->frame_parms.N_RB_DL,0,NB_RB); + //deactivate second codeword + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_2 = 0; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_2 = 1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = 0; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx = 0; + dl_req->number_dci++; + dl_req->number_pdu++; + dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + AssertFatal(TPC>=0 && TPC<2, "TPC should be 0 or 1\n"); + if(1){ + fill_mch_config( + dl_req, + get_TBS_DL(mcs1,NB_RB4TBS), + 0, + 0xfffd, + 0, + get_Qm(mcs1), + mcs1, + 6000, //equal to RS power + 0 //mbsfn_area_id + ); + + fill_tx_req(TX_req, + (frame * 10) + subframe, + get_TBS_DL(mcs1,NB_RB4TBS), + 0, + input_buffer[0]); + + }else{ + fill_dlsch_config(dl_req, + get_TBS_DL(mcs1,NB_RB4TBS), + (retrans > 0) ? -1 : 0, /* retransmission, no pdu_index */ + (common_flag == 0) ? n_rnti : SI_RNTI, + 0, // type 0 allocation from 7.1.6 in 36.213 + 0, // virtual_resource_block_assignment_flag, unused here + DLSCH_RB_ALLOC, // resource_block_coding, + get_Qm(mcs1), + rv, // redundancy version + 1, // transport blocks + 0, // transport block to codeword swap flag + transmission_mode == 1 ? 0 : 1, // transmission_scheme + 1, // number of layers + 1, // number of subbands + // uint8_t codebook_index, + 4, // UE category capacity + pa, // pa + 0, // delta_power_offset for TM5 + 0, // ngap + 0, // nprb + transmission_mode, + 0, //number of PRBs treated as one subband, not used here + 0 // number of beamforming vectors, not used here + ); + fill_tx_req(TX_req, + (frame * 10) + subframe, + get_TBS_DL(mcs1,NB_RB4TBS), + 0, + input_buffer[k]); + } + break; + + case 3: + if (common_flag == 0) { + if (eNB->frame_parms.nb_antennas_tx == 2) { + if (eNB->frame_parms.frame_type == TDD) { + } else { + } + } + } + + break; + + case 4: + if (common_flag == 0) { + if (eNB->frame_parms.nb_antennas_tx == 2) { + if (eNB->frame_parms.frame_type == TDD) { + } else { + } + } else if (eNB->frame_parms.nb_antennas_tx == 4) { + } + } else { + } + + break; + + case 5: + case 6: + break; + + default: + printf("Unsupported Transmission Mode %d!!!\n",transmission_mode); + exit(-1); + break; + } + } + + *num_dci = dl_req->number_dci; + *num_ue_spec_dci = dl_req->number_dci; + *num_common_dci = 0; +} + +int n_users = 1; +int subframe=7; +int num_common_dci=0,num_ue_spec_dci=0,num_dci=0,num_pdcch_symbols=1; +uint16_t n_rnti=0x1234; + +int abstx=0; +int Nid_cell=0; +int N_RB_DL=25; +int tdd_config=3; +int dci_flag=0; +int threequarter_fs=0; +double snr_step=1,input_snr_step=1, snr_int=30; +double forgetting_factor=0.0; //in [0,1] 0 means a new channel every time, 1 means keep the same channel +int test_perf=0; +int n_frames; +int n_ch_rlz = 1; +int rx_sample_offset = 0; +int xforms=0; +int dump_table=0; +int loglvl=OAILOG_WARNING; +int mcs1=0,mcs2=0,mcs_i=0,dual_stream_UE = 0,awgn_flag=0; +int two_thread_flag=0; +int num_rounds = 4;//,fix_rounds=0; +int perfect_ce = 0; +int extended_prefix_flag=0; +int verbose=0, help=0; +double SNR,snr0=-2.0,snr1,rate = 0; +int print_perf=0; + int main(int argc, char **argv) { - char c; - int i,l,l2,aa,aarx,k; - double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0; - uint8_t snr1set=0; - double snr_step=1,input_snr_step=1; - int **txdata; - double s_re0[2*30720],s_im0[2*30720],s_re1[2*30720],s_im1[2*30720]; - double r_re0[2*30720],r_im0[2*30720],r_re1[2*30720],r_im1[2*30720]; - double *s_re[2]= {s_re0,s_re1},*s_im[2]= {s_im0,s_im1},*r_re[2]= {r_re0,r_re1},*r_im[2]= {r_im0,r_im1}; - double iqim = 0.0; - int subframe=1; - char fname[40];//, vname[40]; - uint8_t transmission_mode = 1,n_tx=1,n_rx=2; - uint16_t Nid_cell=0; - FILE *fd; - int eNB_id = 0; - unsigned char mcs=0,awgn_flag=0,round; - int n_frames=1; - channel_desc_t *eNB2UE; - uint32_t nsymb,tx_lev,tx_lev_dB; - uint8_t extended_prefix_flag=1; + int k,i,j,aa; + int re; + int s,Kr,Kr_bytes; LTE_DL_FRAME_PARMS *frame_parms; + double s_re0[30720*2],s_im0[30720*2],r_re0[30720*2],r_im0[30720*2]; + double s_re1[30720*2],s_im1[30720*2],r_re1[30720*2],r_im1[30720*2]; + double *s_re[2]= {s_re0,s_re1}; + double *s_im[2]= {s_im0,s_im1}; + double *r_re[2]= {r_re0,r_re1}; + double *r_im[2]= {r_im0,r_im1}; + uint8_t transmission_mode=1,n_tx_port=1,n_tx_phy=1,n_rx=2; + int eNB_id = 0; + unsigned char round; + unsigned char i_mod = 2; + int NB_RB; + SCM_t channel_model=Rayleigh1; + // unsigned char *input_data,*decoded_output; + DCI_ALLOC_t da; + DCI_ALLOC_t *dci_alloc = &da; + unsigned int coded_bits_per_codeword=0,nsymb; //,tbs=0; + unsigned int tx_lev=0,tx_lev_dB=0,trials; + unsigned int errs[4],errs2[4],round_trials[4],dci_errors[4];//,num_layers; + memset(errs,0,4*sizeof(unsigned int)); + memset(errs2,0,4*sizeof(unsigned int)); + memset(round_trials,0,4*sizeof(unsigned int)); + memset(dci_errors,0,4*sizeof(unsigned int)); + //int re_allocated; + char fname[32],vname[32]; + FILE *bler_fd; + char bler_fname[256]; + FILE *time_meas_fd; + char time_meas_fname[256]; + // FILE *tikz_fd; + // char tikz_fname[256]; + FILE *input_trch_fd=NULL; + unsigned char input_trch_file=0; + FILE *input_fd=NULL; + unsigned char input_file=0; + channel_desc_t *eNB2UE[4]; + //uint8_t num_pdcch_symbols_2=0; + //char stats_buffer[4096]; + //int len; + //int u; + int n=0; + //int iii; + int ch_realization; + //int pmi_feedback=0; int hold_channel=0; - uint16_t NB_RB=25; - int tdd_config=3; - SCM_t channel_model=MBSFN; - unsigned char *input_buffer; - unsigned short input_buffer_length; - unsigned int ret; - unsigned int trials,errs[4]= {0,0,0,0}; //,round_trials[4]={0,0,0,0}; - uint8_t N_RB_DL=25,osf=1; - uint32_t perfect_ce = 0; - lte_frame_type_t frame_type = FDD; - uint32_t Nsoft = 1827072; - /* - #ifdef XFORMS - FD_lte_phy_scope_ue *form_ue; + // void *data; + // int ii; + // int bler; + double blerr[4]; + short *uncoded_ber_bit=NULL; + int osf=1; + frame_t frame_type = FDD; + FD_lte_phy_scope_ue *form_ue = NULL; char title[255]; + int numCCE=0; + //int dci_length_bytes=0,dci_length=0; + //double channel_bandwidth = 5.0, sampling_rate=7.68; + int common_flag=0,TPC=0; + double cpu_freq_GHz; + // time_stats_t ts;//,sts,usts; + int avg_iter,iter_trials; + int rballocset=0; + int test_passed=0; + double effective_rate=0.0; + char channel_model_input[10]="I"; + int TB0_active = 1; + // LTE_DL_UE_HARQ_t *dlsch0_ue_harq; + // LTE_DL_eNB_HARQ_t *dlsch0_eNB_harq; + uint8_t Kmimo; + uint8_t ue_category=4; + uint32_t Nsoft; + int sf; + int CCE_table[800]; + opp_enabled=1; // to enable the time meas + FILE *csv_fd=NULL; + char csv_fname[FILENAME_MAX]; + int DLSCH_RB_ALLOC = 0; + int dci_received; + PHY_VARS_eNB *eNB; + RU_t *ru; + PHY_VARS_UE *UE=NULL; + nfapi_dl_config_request_t DL_req; + nfapi_ul_config_request_t UL_req; + nfapi_hi_dci0_request_t HI_DCI0_req; + nfapi_dl_config_request_pdu_t dl_config_pdu_list[MAX_NUM_DL_PDU]; + nfapi_tx_request_pdu_t tx_pdu_list[MAX_NUM_TX_REQUEST_PDU]; + nfapi_tx_request_t TX_req; + Sched_Rsp_t sched_resp; + int pa=dB0; +#if defined(__arm__) + FILE *proc_fd = NULL; + char buf[64]; + memset(buf,0,sizeof(buf)); + proc_fd = fopen("/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq", "r"); - fl_initialize (&argc, argv, NULL, 0, 0); - form_ue = create_lte_phy_scope_ue(); - sprintf (title, "LTE DL SCOPE UE"); - fl_show_form (form_ue->lte_phy_scope_ue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - #endif - */ - cpuf = get_cpu_freq_GHz(); - logInit(); - number_of_cards = 1; + if(!proc_fd) + printf("cannot open /sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq"); + else { + while(fgets(buf, 63, proc_fd)) + printf("%s", buf); + } - while ((c = getopt (argc, argv, "ahA:Cp:n:s:S:t:x:y:z:N:F:R:O:dm:i:Y")) != -1) { - switch (c) { + fclose(proc_fd); + cpu_freq_GHz = ((double)atof(buf))/1e6; +#else + cpu_freq_GHz = get_cpu_freq_GHz(); +#endif + printf("Detected cpu_freq %f GHz\n",cpu_freq_GHz); + memset((void *)&sched_resp,0,sizeof(sched_resp)); + sched_resp.DL_req = &DL_req; + sched_resp.UL_req = &UL_req; + sched_resp.HI_DCI0_req = &HI_DCI0_req; + sched_resp.TX_req = &TX_req; + memset((void *)&DL_req,0,sizeof(DL_req)); + memset((void *)&UL_req,0,sizeof(UL_req)); + memset((void *)&HI_DCI0_req,0,sizeof(HI_DCI0_req)); + memset((void *)&TX_req,0,sizeof(TX_req)); + DL_req.dl_config_request_body.dl_config_pdu_list = dl_config_pdu_list; + TX_req.tx_request_body.tx_pdu_list = tx_pdu_list; + set_parallel_conf("PARALLEL_SINGLE_THREAD"); + cpuf = cpu_freq_GHz; + //signal(SIGSEGV, handler); + //signal(SIGABRT, handler); + // default parameters + n_frames = 1000; + snr0 = 0; + // num_layers = 1; + perfect_ce = 0; + static paramdef_t options[] = { + { "awgn", "Use AWGN channel and not multipath", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL }, + { "Abstx", "Turns on calibration mode for abstraction.", PARAMFLAG_BOOL, iptr:&abstx, defintval:0, TYPE_INT, 0 }, + { "bTDD", "Set the tdd configuration mode",0, iptr:&tdd_config, defintval:3, TYPE_INT, 0 }, + { "BnbRBs", "The LTE bandwith in RBs (100 is 20MHz)",0, iptr:&N_RB_DL, defintval:25, TYPE_INT, 0 }, + { "cPdcch", "Number of PDCCH symbols",0, iptr:&num_pdcch_symbols, defintval:1, TYPE_INT, 0 }, + { "CnidCell", "The cell id ",0, iptr:&Nid_cell, defintval:0, TYPE_INT, 0 }, + { "dciFlag", "Transmit the DCI and compute its error statistics", PARAMFLAG_BOOL, iptr:&dci_flag, defintval:0, TYPE_INT, 0 }, + { "Dtdd", "Enable tdd", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL }, + { "eRounds", "Number of rounds",0, iptr:NULL, defintval:25, TYPE_INT, 0 }, + { "EsubSampling","three quarters sub-sampling",PARAMFLAG_BOOL, iptr:&threequarter_fs, defintval:0, TYPE_INT, 0 }, + { "f_snr_step", "step size of SNR, default value is 1.",0, dblptr:&input_snr_step, defdblval:1, TYPE_DOUBLE, 0 }, + { "Forgetting", "forgetting factor (0 new channel every trial, 1 channel constant)",0, dblptr:&forgetting_factor, defdblval:0.0, TYPE_DOUBLE, 0 }, + { "input_file", "input IQ data file",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "Input_file_trch", " Input filename for TrCH data (binary)",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "WtwoThreads", "two_thread_flag", PARAMFLAG_BOOL, iptr:&two_thread_flag, defintval:0, TYPE_INT, 0 }, + { "lMuMimo", "offset_mumimo_llr_drange_fix",0, u8ptr:&offset_mumimo_llr_drange_fix, defintval:0, TYPE_UINT8, 0 }, + { "mcs1", "The MCS for TB 1", 0, iptr:&mcs1, defintval:0, TYPE_INT, 0 }, + { "Mcs2", "The MCS for TB 2", 0, iptr:&mcs2, defintval:0, TYPE_INT, 0 }, + { "Operf", "Set the percenatge of effective rate to testbench the modem performance (typically 30 and 70, range 1-100)",0, iptr:&test_perf, defintval:0, TYPE_INT, 0 }, + { "tmcs_i", "MCS of interfering UE",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "nb_frame", "number of frame in a test",0, iptr:&n_frames, defintval:1, TYPE_INT, 0 }, + { "offsetRxSample", "Sample offset for receiver", 0, iptr:&rx_sample_offset, defintval:0, TYPE_INT, 0 }, + { "rballocset", "ressource block allocation (see section 7.1.6.3 in 36.213)",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "snr", "Starting SNR, runs from SNR to SNR+%.1fdB in steps of %.1fdB. If n_frames is 1 then just SNR is simulated and MATLAB/OCTAVE output is generated", dblptr:&snr0, defdblval:-2.0, TYPE_DOUBLE, 0 }, + { "wsnrInterrupt", "snr int ?", 0, dblptr:&snr_int, defdblval:30, TYPE_DOUBLE, 0 }, + { "N_ch_rlzN0", "Determines the number of Channel Realizations in Abstraction mode. Default value is 1",0, iptr:&n_ch_rlz, defintval:1, TYPE_INT, 0 }, + { "prefix_extended","Enable extended prefix", PARAMFLAG_BOOL, iptr:&extended_prefix_flag, defintval:0, TYPE_INT, 0 }, + { "RNumRound", "Number of HARQ rounds (fixed)",0, iptr:&num_rounds, defintval:4, TYPE_INT, 0 }, + { "Subframe", "subframe ",0, iptr:&subframe, defintval:7, TYPE_INT, 0 }, + { "Trnti", "rnti",0, u16ptr:&n_rnti, defuintval:0x1234, TYPE_UINT16, 0 }, + { "vi_mod", "i_mod",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "Qparallel", "Enable parallel execution",0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0 }, + { "Performance", "Display CPU perfomance of each L1 piece", PARAMFLAG_BOOL, iptr:&print_perf, defintval:0, TYPE_INT, 0 }, + { "q_tx_port", "Number of TX antennas ports used in eNB",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "uEdual", "Enables the Interference Aware Receiver for TM5 (default is normal receiver)",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + { "xTransmission","Transmission mode (1,2,6,7 for the moment)",0, iptr:NULL, defintval:25, TYPE_INT, 0 }, + { "yn_tx_phy","Number of TX antennas used in eNB",0, iptr:NULL, defintval:25, TYPE_INT, 0 }, + { "XForms", "Display the soft scope", PARAMFLAG_BOOL, iptr:&xforms, defintval:0, TYPE_INT, 0 }, + { "Yperfect_ce","Perfect CE", PARAMFLAG_BOOL, iptr:&perfect_ce, defintval:0, TYPE_INT, 0 }, + { "Zdump", "dump table",PARAMFLAG_BOOL, iptr:&dump_table, defintval:0, TYPE_INT, 0 }, + { "Loglvl", "log level",0, iptr:&loglvl, defintval:OAILOG_DEBUG, TYPE_INT, 0 }, + { "zn_rx", "Number of RX antennas used in UE",0, iptr:NULL, defintval:2, TYPE_INT, 0 }, + { "gchannel", "[A:M] Use 3GPP 25.814 SCM-A/B/C/D('A','B','C','D') or 36-101 EPA('E'), EVA ('F'),ETU('G') models (ignores delay spread and Ricean factor), Rayghleigh8 ('H'), Rayleigh1('I'), Rayleigh1_corr('J'), Rayleigh1_anticorr ('K'), Rice8('L'), Rice1('M')",0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0 }, + { "verbose", "display debug text", PARAMFLAG_BOOL, iptr:&verbose, defintval:0, TYPE_INT, 0 }, + { "mmse", "Use MMSE whitening", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL }, + { "help", "display help and exit", PARAMFLAG_BOOL, iptr:&help, defintval:0, TYPE_INT, 0 }, + { "", "",0, iptr:NULL, defintval:0, TYPE_INT, 0 }, + }; + struct option *long_options = parse_oai_options(options); + int option_index; + int res; + + while ((res=getopt_long_only(argc, argv, "", long_options, &option_index)) == 0) { + if (options[option_index].voidptr != NULL ) { + if (long_options[option_index].has_arg==no_argument) + *(bool *)options[option_index].iptr=1; + else switch (options[option_index].type) { + case TYPE_INT: + *(int *)options[option_index].iptr=atoi(optarg); + break; + + case TYPE_DOUBLE: + *(double *)options[option_index].dblptr=atof(optarg); + break; + + case TYPE_UINT8: + *(uint8_t *)options[option_index].dblptr=atoi(optarg); + break; + + case TYPE_UINT16: + *(uint16_t *)options[option_index].dblptr=atoi(optarg); + break; + + default: + printf("not decoded type.\n"); + exit(1); + } + + continue; + } + + switch (long_options[option_index].name[0]) { case 'a': - awgn_flag=1; + awgn_flag = 1; + channel_model = AWGN; break; - case 'd': - frame_type = 0; + case 'D': + frame_type=TDD; break; - case 'n': - n_frames = atoi(optarg); - break; - - case 'm': - mcs=atoi(optarg); - break; - - case 's': - snr0 = atof(optarg); - msg("Setting SNR0 to %f\n",snr0); + case 'e': + num_rounds=1; + common_flag = 1; + TPC = atoi(optarg); break; case 'i': - input_snr_step = atof(optarg); + input_fd = fopen(optarg,"r"); + input_file=1; + dci_flag = 1; break; - case 'S': - snr1 = atof(optarg); - snr1set=1; - msg("Setting SNR1 to %f\n",snr1); + case 'I': + input_trch_fd = fopen(optarg,"r"); + input_trch_file=1; break; - case 'p': // subframe no; - subframe=atoi(optarg); + case 't': + mcs_i = atoi(optarg); + i_mod = get_Qm(mcs_i); + break; + + case 'r': + DLSCH_RB_ALLOC = atoi(optarg); + rballocset = 1; + break; + + case 'g': + strncpy(channel_model_input,optarg,9); + struct tmp { + char opt; + int m; + int M; + } + tmp[]= { + {'A',SCM_A,2}, + {'B',SCM_B,3}, + {'C',SCM_C,4}, + {'D',SCM_D,5}, + {'E',EPA,6}, + {'F',EVA,6}, + {'G',ETU,8}, + {'H',Rayleigh8,9}, + {'I',Rayleigh1,10}, + {'J',Rayleigh1_corr,11}, + {'K',Rayleigh1_anticorr,12}, + {'L',Rice8,13}, + {'M',Rice1,14}, + {'N',AWGN,1}, + {0,0,0} + }; + struct tmp *ptr; + + for (ptr=tmp; ptr->opt!=0; ptr++) + if ( ptr->opt == optarg[0] ) { + channel_model=ptr->m; + break; + } + + AssertFatal(ptr->opt != 0, "Unsupported channel model: %s !\n", optarg ); + break; + + case 'u': + dual_stream_UE=1; + + if (UE != NULL) + UE->use_ia_receiver = 1; + else { + printf("UE is NULL\n"); + exit(-1); + } + + if ((n_tx_port!=2) || (transmission_mode!=5)) { + printf("IA receiver only supported for TM5!"); + exit(-1); + } + + break; + + case 'v': + i_mod = atoi(optarg); + + if (i_mod!=2 && i_mod!=4 && i_mod!=6) { + printf("Wrong i_mod %d, should be 2,4 or 6\n",i_mod); + exit(-1); + } + + break; + + case 'q': + n_tx_port=atoi(optarg); + + if ((n_tx_port==0) || ((n_tx_port>2))) { + printf("Unsupported number of cell specific antennas ports %d\n",n_tx_port); + exit(-1); + } + + break; + + case 'x': + transmission_mode=atoi(optarg); + + if ((transmission_mode!=1) && + (transmission_mode!=2) && + (transmission_mode!=3) && + (transmission_mode!=4) && + (transmission_mode!=5) && + (transmission_mode!=6) && + (transmission_mode!=7)) { + printf("Unsupported transmission mode %d\n",transmission_mode); + exit(-1); + } + + if (transmission_mode>1 && transmission_mode<7) { + n_tx_port = 2; + } + + break; + + case 'y': + n_tx_phy=atoi(optarg); + + if (n_tx_phy < n_tx_port) { + printf("n_tx_phy mush not be smaller than n_tx_port"); + exit(-1); + } + + if ((transmission_mode>1 && transmission_mode<7) && n_tx_port<2) { + printf("n_tx_port must be >1 for transmission_mode %d\n",transmission_mode); + exit(-1); + } + + if (transmission_mode==7 && (n_tx_phy!=1 && n_tx_phy!=2 && n_tx_phy!=4 && n_tx_phy!=8 && n_tx_phy!=16 && n_tx_phy!=64 && n_tx_phy!=128)) { + printf("Physical number of antennas not supported for TM7.\n"); + exit(-1); + } + break; case 'z': n_rx=atoi(optarg); if ((n_rx==0) || (n_rx>2)) { - msg("Unsupported number of rx antennas %d\n",n_rx); + printf("Unsupported number of rx antennas %d\n",n_rx); exit(-1); } break; - case 'N': - Nid_cell = atoi(optarg); - break; - - case 'R': - N_RB_DL = atoi(optarg); - - if ((N_RB_DL!=6) && (N_RB_DL!=25) && (N_RB_DL!=50) && (N_RB_DL!=100)) { - printf("Unsupported Bandwidth %d\n",N_RB_DL); - exit(-1); - } - - break; - - case 'O': - osf = atoi(optarg); - break; - - case 'Y': - perfect_ce = 1; + case 'Q': + set_parallel_conf(optarg); break; default: - case 'h': - printf("%s -h(elp) -p(subframe) -N cell_id -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -i snr increment -z RXant \n",argv[0]); - printf("-h This message\n"); - printf("-a Use AWGN Channel\n"); - printf("-p Use extended prefix mode\n"); - printf("-d Use TDD\n"); - printf("-n Number of frames to simulate\n"); - printf("-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated\n"); - printf("-S Ending SNR, runs from SNR0 to SNR1\n"); - printf("-t Delay spread for multipath channel\n"); - printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n"); - printf("-x Transmission mode (1,2,6 for the moment)\n"); - printf("-y Number of TX antennas used in eNB\n"); - printf("-z Number of RX antennas used in UE\n"); - printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n"); - printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); - printf("-N Nid_cell\n"); - printf("-R N_RB_DL\n"); - printf("-O oversampling factor (1,2,4,8,16)\n"); - printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); - printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); - printf("-f Output filename (.txt format) for Pe/SNR results\n"); - printf("-F Input filename (.txt format) for RX conformance testing\n"); - exit (-1); + printf("Wrong option: %s\n",long_options[option_index].name); + exit(1); break; } } - if (awgn_flag == 1) - channel_model = AWGN; - - // check that subframe is legal for eMBMS - - if ((subframe == 0) || (subframe == 5) || // TDD and FDD SFn 0,5; - ((frame_type == FDD) && ((subframe == 4) || (subframe == 9))) || // FDD SFn 4,9; - ((frame_type == TDD ) && ((subframe<3) || (subframe==6)))) { // TDD SFn 1,2,6; - printf("Illegal subframe %d for eMBMS transmission (frame_type %d)\n",subframe,frame_type); - exit(-1); + if ( res != -1 ) { + printf("A wrong option has been found\n"); + exit(1); } - if (transmission_mode==2) - n_tx=2; + if (help || verbose ) + display_options_values(options, true); - lte_param_init(n_tx, - n_tx, + if (help) + exit(0); + if (thread_struct.parallel_conf != PARALLEL_SINGLE_THREAD) + set_worker_conf("WORKER_ENABLE"); + + if (transmission_mode>1) pa=dBm3; + + printf("dlsim: tmode %d, pa %d\n",transmission_mode,pa); + AssertFatal(load_configmodule(argc,argv, CONFIG_ENABLECMDLINEONLY) != NULL, + "cannot load configuration module, exiting\n"); + logInit(); + set_glog_onlinelog(true); + // enable these lines if you need debug info + set_glog(loglvl); + SET_LOG_DEBUG(UE_TIMING); + // moreover you need to init itti with the following line + // however itti will catch all signals, so ctrl-c won't work anymore + // alternatively you can disable ITTI completely in CMakeLists.txt + //itti_init(TASK_MAX, THREAD_MAX, MESSAGES_ID_MAX, tasks_info, messages_info, messages_definition_xml, NULL); + + if (common_flag == 0) { + switch (N_RB_DL) { + case 6: + if (rballocset==0) DLSCH_RB_ALLOC = 0x3f; + + num_pdcch_symbols = 3; + break; + + case 25: + if (rballocset==0) DLSCH_RB_ALLOC = 0x1fff; + + break; + + case 50: + if (rballocset==0) DLSCH_RB_ALLOC = 0x1ffff; + + break; + + case 100: + if (rballocset==0) DLSCH_RB_ALLOC = 0x1ffffff; + + break; + } + + NB_RB = conv_nprb(0,DLSCH_RB_ALLOC,N_RB_DL); + } else { + if (rballocset==0) NB_RB = 8; + else NB_RB = DLSCH_RB_ALLOC; + + AssertFatal(NB_RB <= N_RB_DL,"illegal NB_RB %d\n",NB_RB); + } + + if (xforms==1) { + fl_initialize (&argc, argv, NULL, 0, 0); + form_ue = create_lte_phy_scope_ue(); + sprintf (title, "LTE PHY SCOPE eNB"); + fl_show_form (form_ue->lte_phy_scope_ue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); + + if (!dual_stream_UE==0) { + if (UE) { + UE->use_ia_receiver = 1; + fl_set_button(form_ue->button_0,1); + fl_set_object_label(form_ue->button_0, "IA Receiver ON"); + fl_set_object_color(form_ue->button_0, FL_GREEN, FL_GREEN); + } else { + printf("UE is NULL\n"); + exit(-1); + } + } + } + + if (transmission_mode==5) { + n_users = 2; + printf("dual_stream_UE=%d\n", dual_stream_UE); + } + + RC.nb_L1_inst = 1; + RC.nb_RU = 1; + lte_param_init(&eNB,&UE,&ru, + n_tx_port, + n_tx_phy, + 1, n_rx, transmission_mode, extended_prefix_flag, @@ -224,281 +1068,1251 @@ int main(int argc, char **argv) { Nid_cell, tdd_config, N_RB_DL, - 0, + pa, + threequarter_fs, osf, perfect_ce); + RC.eNB = (PHY_VARS_eNB ** *)malloc(sizeof(PHY_VARS_eNB **)); + RC.eNB[0] = (PHY_VARS_eNB **)malloc(sizeof(PHY_VARS_eNB *)); + RC.ru = (RU_t **)malloc(sizeof(RC.ru)); + RC.eNB[0][0] = eNB; + RC.ru[0] = ru; + printf("lte_param_init done\n"); - if (snr1set==0) { - if (n_frames==1) - snr1 = snr0+.1; - else - snr1 = snr0+5.0; + if ((transmission_mode==1) || (transmission_mode==7)) { + for (aa=0; aanb_tx; aa++) + for (re=0; reframe_parms.ofdm_symbol_size; re++) + ru->beam_weights[0][0][aa][re] = 0x00007fff/eNB->frame_parms.nb_antennas_tx; } + if (transmission_mode<7) + ru->do_precoding=0; + else + ru->do_precoding=1; + + eNB->mac_enabled=1; + + +#ifdef ENABLE_MBMS_SIM + //eNB->pbch_configured=1; + eNB_MAC_INST ** mac; + mac = malloc16(1 * sizeof(eNB_MAC_INST *)); + for (int ii = 0;ii < 1; ii++) { + mac[ii] = malloc16(sizeof(eNB_MAC_INST)); + bzero(mac[ii], sizeof(eNB_MAC_INST)); + } + RC.mac = mac; + COMMON_channels_t *cc = &RC.mac[0]->common_channels[0]; + cc->MCH_pdu.mcs = 9; + cc->MCH_pdu.Pdu_size = get_TBS_DL(cc->MCH_pdu.mcs,N_RB_DL); + printf("MCH_pdu.Pdu_size %d\n",cc->MCH_pdu.Pdu_size); + cc->MCH_pdu.sync_area =0; + for(int ii=0; ii < cc->MCH_pdu.Pdu_size; ii++) + cc->MCH_pdu.payload[ii] = (char)(taus() & 0xff); + eNB->frame_parms.Nid_cell_mbsfn=0; +#endif + + + if(get_thread_worker_conf() == WORKER_ENABLE) { + extern void init_td_thread(PHY_VARS_eNB *); + extern void init_te_thread(PHY_VARS_eNB *); + init_td_thread(eNB); + init_te_thread(eNB); + } + + // callback functions required for phy_procedures_tx + // eNB_id_i = UE->n_connected_eNB; + printf("Setting mcs1 = %d\n",mcs1); + printf("Setting mcs2 = %d\n",mcs2); + printf("NPRB = %d\n",NB_RB); + printf("n_frames = %d\n",n_frames); + printf("Transmission mode %d with %dx%d antenna configuration, Extended Prefix %d\n",transmission_mode,n_tx_phy,n_rx,extended_prefix_flag); + snr1 = snr0+snr_int; printf("SNR0 %f, SNR1 %f\n",snr0,snr1); + uint8_t input_buffer[NUMBER_OF_UE_MAX][20000]; + + for (i=0; iframe_parms; + nsymb = (eNB->frame_parms.Ncp == 0) ? 14 : 12; + printf("Channel Model= (%s,%d)\n",channel_model_input, channel_model); + printf("SCM-A=%d, SCM-B=%d, SCM-C=%d, SCM-D=%d, EPA=%d, EVA=%d, ETU=%d, Rayleigh8=%d, Rayleigh1=%d, Rayleigh1_corr=%d, Rayleigh1_anticorr=%d, Rice1=%d, Rice8=%d\n", + SCM_A, SCM_B, SCM_C, SCM_D, EPA, EVA, ETU, Rayleigh8, Rayleigh1, Rayleigh1_corr, Rayleigh1_anticorr, Rice1, Rice8); - if (awgn_flag == 0) - sprintf(fname,"embms_%d_%d.m",mcs,N_RB_DL); + if(transmission_mode==5) + sprintf(bler_fname,"bler_tx%d_chan%d_nrx%d_mcs%d_mcsi%d_u%d_imod%d.csv",transmission_mode,channel_model,n_rx,mcs1,mcs_i,dual_stream_UE,i_mod); else - sprintf(fname,"embms_awgn_%d_%d.m",mcs,N_RB_DL); + sprintf(bler_fname,"bler_tx%d_chan%d_nrx%d_mcs%d.csv",transmission_mode,channel_model,n_rx,mcs1); - if (!(fd = fopen(fname,"w"))) { - printf("Cannot open %s, check permissions\n",fname); + bler_fd = fopen(bler_fname,"w"); + + if (bler_fd==NULL) { + fprintf(stderr,"Cannot create file %s!\n",bler_fname); exit(-1); } - if (awgn_flag==0) - fprintf(fd,"SNR_%d_%d=[];errs_mch_%d_%d=[];mch_trials_%d_%d=[];\n", - mcs,N_RB_DL, - mcs,N_RB_DL, - mcs,N_RB_DL); - else - fprintf(fd,"SNR_awgn_%d_%d=[];errs_mch_awgn_%d_%d=[];mch_trials_awgn_%d_%d=[];\n", - mcs,N_RB_DL, - mcs,N_RB_DL, - mcs,N_RB_DL); + fprintf(bler_fd,"SNR; MCS; TBS; rate; err0; trials0; err1; trials1; err2; trials2; err3; trials3; dci_err\n"); - fflush(fd); - txdata = eNB->common_vars.txdata[0]; - nsymb = 12; - printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d, Symbols per subframe %d, AWGN %d\n",NUMBER_OF_OFDM_CARRIERS, - frame_parms->Ncp,frame_parms->samples_per_tti,nsymb,awgn_flag); - eNB2UE = new_channel_desc_scm(eNB->frame_parms.nb_antennas_tx, - UE->frame_parms.nb_antennas_rx, - channel_model, - N_RB2sampling_rate(eNB->frame_parms.N_RB_DL), - N_RB2channel_bandwidth(eNB->frame_parms.N_RB_DL), - 0, - 0, - 0); - // Create transport channel structures for 2 transport blocks (MIMO) - eNB->dlsch_MCH = new_eNB_dlsch(1,8,Nsoft,N_RB_DL,0,&eNB->frame_parms); + if (test_perf != 0) { + char hostname[1024]; + hostname[1023] = '\0'; + gethostname(hostname, 1023); + printf("Hostname: %s\n", hostname); + //char dirname[FILENAME_MAX]; + //sprintf(dirname, "%s/SIMU/USER/pre-ci-logs-%s", getenv("OPENAIR_TARGETS"),hostname ); + sprintf(time_meas_fname,"time_meas_prb%d_mcs%d_anttx%d_antrx%d_pdcch%d_channel%s_tx%d.csv", + N_RB_DL,mcs1,n_tx_phy,n_rx,num_pdcch_symbols,channel_model_input,transmission_mode); + //mkdir(dirname,0777); + time_meas_fd = fopen(time_meas_fname,"w"); - if (!eNB->dlsch_MCH) { - printf("Can't get eNB dlsch structures\n"); - exit(-1); + if (time_meas_fd==NULL) { + fprintf(stderr,"Cannot create file %s!\n",time_meas_fname); + exit(-1); + } } - UE->dlsch_MCH[0] = new_ue_dlsch(1,8,Nsoft,MAX_TURBO_ITERATIONS_MBSFN,N_RB_DL,0); - eNB->frame_parms.num_MBSFN_config = 1; - eNB->frame_parms.MBSFN_config[0].radioframeAllocationPeriod = 0; - eNB->frame_parms.MBSFN_config[0].radioframeAllocationOffset = 0; - eNB->frame_parms.MBSFN_config[0].fourFrames_flag = 0; - eNB->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xff; // activate all possible subframes - UE->frame_parms.num_MBSFN_config = 1; - UE->frame_parms.MBSFN_config[0].radioframeAllocationPeriod = 0; - UE->frame_parms.MBSFN_config[0].radioframeAllocationOffset = 0; - UE->frame_parms.MBSFN_config[0].fourFrames_flag = 0; - UE->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xff; // activate all possible subframes - fill_eNB_dlsch_MCH(eNB,mcs,1,0); - fill_UE_dlsch_MCH(UE,mcs,1,0,0); + if(abstx) { + // CSV file + sprintf(csv_fname,"dataout_tx%d_u2%d_mcs%d_chan%d_nsimus%d_R%d.m",transmission_mode,dual_stream_UE,mcs1,channel_model,n_frames,num_rounds); + csv_fd = fopen(csv_fname,"w"); - if (is_pmch_subframe(0,subframe,&eNB->frame_parms)==0) { - printf("eNB is not configured for MBSFN in subframe %d\n",subframe); - exit(-1); - } else if (is_pmch_subframe(0,subframe,&UE->frame_parms)==0) { - printf("UE is not configured for MBSFN in subframe %d\n",subframe); - exit(-1); - } - - input_buffer_length = eNB->dlsch_MCH->harq_processes[0]->TBS/8; - input_buffer = (unsigned char *)malloc(input_buffer_length+4); - memset(input_buffer,0,input_buffer_length+4); - - for (i=0; iproc.proc_rxtx[0].frame_tx=0; - eNB->proc.proc_rxtx[0].frame_tx=0; - eNB->proc.proc_rxtx[0].subframe_tx=subframe; - errs[0]=0; - errs[1]=0; - errs[2]=0; - errs[3]=0; - /* - round_trials[0] = 0; - round_trials[1] = 0; - round_trials[2] = 0; - round_trials[3] = 0;*/ - printf("********************** SNR %f (step %f)\n",SNR,snr_step); - - for (trials = 0; trialsfirst_run = 1; - eNB2UE->first_run = 1; - memset(&eNB->common_vars.txdataF[0][0][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t)); - generate_mch(eNB,&eNB->proc.proc_rxtx[0],input_buffer); - PHY_ofdm_mod(eNB->common_vars.txdataF[0][0], // input, - txdata[0], // output - frame_parms->ofdm_symbol_size, - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*nsymb, // number of symbols - frame_parms->nb_prefix_samples, // number of prefix samples - CYCLIC_PREFIX); - - if (n_frames==1) { - LOG_M("txsigF0.m","txsF0", &eNB->common_vars.txdataF[0][0][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size], - nsymb*eNB->frame_parms.ofdm_symbol_size,1,1); - //if (eNB->frame_parms.nb_antennas_tx>1) - //LOG_M("txsigF1.m","txsF1", &eNB->lte_eNB_common_vars.txdataF[eNB_id][1][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],nsymb*eNB->frame_parms.ofdm_symbol_size,1,1); - } - - tx_lev = 0; - - for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { - tx_lev += signal_energy(&eNB->common_vars.txdata[eNB_id][aa] - [subframe*eNB->frame_parms.samples_per_tti], - eNB->frame_parms.samples_per_tti); - } - - tx_lev_dB = (unsigned int) dB_fixed(tx_lev); - - if (n_frames==1) { - printf("tx_lev = %d (%d dB)\n",tx_lev,tx_lev_dB); - // LOG_M("txsig0.m","txs0", &eNB->common_vars.txdata[0][0][subframe* eNB->frame_parms.samples_per_tti], - // eNB->frame_parms.samples_per_tti,1,1); - } - - for (i=0; i<2*frame_parms->samples_per_tti; i++) { - for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { - s_re[aa][i] = ((double)(((short *)eNB->common_vars.txdata[0][aa]))[(2*subframe*UE->frame_parms.samples_per_tti) + (i<<1)]); - s_im[aa][i] = ((double)(((short *)eNB->common_vars.txdata[0][aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]); - } - } - - //Multipath channel - multipath_channel(eNB2UE,s_re,s_im,r_re,r_im, - 2*frame_parms->samples_per_tti,hold_channel); - //AWGN - sigma2_dB = 10*log10((double)tx_lev) +10*log10((double)eNB->frame_parms.ofdm_symbol_size/(NB_RB*12)) - SNR; - sigma2 = pow(10,sigma2_dB/10); - - if (n_frames==1) - printf("Sigma2 %f (sigma2_dB %f)\n",sigma2,sigma2_dB); - - for (i=0; i<2*frame_parms->samples_per_tti; i++) { - for (aa=0; aaframe_parms.nb_antennas_rx; aa++) { - //printf("s_re[0][%d]=> %f , r_re[0][%d]=> %f\n",i,s_re[aa][i],i,r_re[aa][i]); - ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i] = - (short) (r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)); - ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i+1] = - (short) (r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0)); - } - } - - for (l=2; l<12; l++) { - slot_fep_mbsfn(UE, - l, - subframe%10, - 0, - 0); - - if (UE->perfect_ce==1) { - // fill in perfect channel estimates - freq_channel(eNB2UE,UE->frame_parms.N_RB_DL,12*UE->frame_parms.N_RB_DL + 1); - - for(k=0; knb_antennas_tx; aa++) { - for (aarx=0; aarxnb_antennas_rx; aarx++) { - for (i=0; iN_RB_DL*12; i++) { - ((int16_t *) UE->common_vars.common_vars_rx_data_per_thread[subframe&0x1].dl_ch_estimates[k][(aa<<1)+aarx])[2*i+(l*frame_parms->ofdm_symbol_size+LTE_CE_FILTER_LENGTH)*2]=(int16_t)(eNB2UE->chF[aarx+ - (aa*frame_parms->nb_antennas_rx)][i].x*AMP); - ((int16_t *) UE->common_vars.common_vars_rx_data_per_thread[subframe&0x1].dl_ch_estimates[k][(aa<<1)+aarx])[2*i+1+(l*frame_parms->ofdm_symbol_size+LTE_CE_FILTER_LENGTH)*2]=(int16_t)(eNB2UE->chF[aarx+ - (aa*frame_parms->nb_antennas_rx)][i].y*AMP); - } - } - } - } - } - - if (l==6) - for (l2=2; l2<7; l2++) - rx_pmch(UE, - 0, - subframe%10, - l2); - - if (l==6) - for (l2=2; l2<7; l2++) - rx_pmch(UE, - 0, - subframe%10, - l2); - - if (l==11) - for (l2=7; l2<12; l2++) - rx_pmch(UE, - 0, - subframe%10, - l2); - } - - UE->dlsch_MCH[0]->harq_processes[0]->G = get_G(&UE->frame_parms, - UE->dlsch_MCH[0]->harq_processes[0]->nb_rb, - UE->dlsch_MCH[0]->harq_processes[0]->rb_alloc_even, - get_Qm(UE->dlsch_MCH[0]->harq_processes[0]->mcs), - 1,2, - UE->proc.proc_rxtx[0].frame_tx,subframe,0); - UE->dlsch_MCH[0]->harq_processes[0]->Qm = get_Qm(UE->dlsch_MCH[0]->harq_processes[0]->mcs); - dlsch_unscrambling(&UE->frame_parms,1,UE->dlsch_MCH[0], - UE->dlsch_MCH[0]->harq_processes[0]->G, - UE->pdsch_vars_MCH[0]->llr[0],0,subframe<<1); - ret = dlsch_decoding(UE, - UE->pdsch_vars_MCH[0]->llr[0], - &UE->frame_parms, - UE->dlsch_MCH[0], - UE->dlsch_MCH[0]->harq_processes[0], - trials, - subframe, - 0,0,0); - - if (n_frames==1) - printf("MCH decoding returns %u\n",ret); - - if (ret == (1+UE->dlsch_MCH[0]->max_turbo_iterations)) - errs[0]++; - - UE->proc.proc_rxtx[0].frame_tx++; - eNB->proc.proc_rxtx[0].frame_tx++; + if (csv_fd==NULL) { + fprintf(stderr,"Cannot create file %s!\n",csv_fname); + exit(-1); } - printf("errors %u/%u (Pe %e)\n",errs[round],trials,(double)errs[round]/trials); + fprintf(csv_fd,"data_all%d=[",mcs1); + } - if (awgn_flag==0) - fprintf(fd,"SNR_%d_%d = [SNR_%d_%d %f]; errs_mch_%d_%d =[errs_mch_%d_%d %u]; mch_trials_%d_%d =[mch_trials_%d_%d %u];\n", - mcs,N_RB_DL,mcs,N_RB_DL,SNR, - mcs,N_RB_DL,mcs,N_RB_DL,errs[0], - mcs,N_RB_DL,mcs,N_RB_DL,trials); - else - fprintf(fd,"SNR_awgn_%d = [SNR_awgn_%d %f]; errs_mch_awgn_%d =[errs_mch_awgn_%d %u]; mch_trials_awgn_%d =[mch_trials_awgn_%d %u];\n", - N_RB_DL,N_RB_DL,SNR, - N_RB_DL,N_RB_DL,errs[0], - N_RB_DL,N_RB_DL,trials); + /* + //sprintf(tikz_fname, "second_bler_tx%d_u2=%d_mcs%d_chan%d_nsimus%d.tex",transmission_mode,dual_stream_UE,mcs,channel_model,n_frames); + sprintf(tikz_fname, "second_bler_tx%d_u2%d_mcs%d_chan%d_nsimus%d",transmission_mode,dual_stream_UE,mcs,channel_model,n_frames); + tikz_fd = fopen(tikz_fname,"w"); + //fprintf(tikz_fd,"\\addplot[color=red, mark=o] plot coordinates {"); + switch (mcs) + { + case 0: + fprintf(tikz_fd,"\\addplot[color=blue, mark=star] plot coordinates {"); + break; + case 1: + fprintf(tikz_fd,"\\addplot[color=red, mark=star] plot coordinates {"); + break; + case 2: + fprintf(tikz_fd,"\\addplot[color=green, mark=star] plot coordinates {"); + break; + case 3: + fprintf(tikz_fd,"\\addplot[color=yellow, mark=star] plot coordinates {"); + break; + case 4: + fprintf(tikz_fd,"\\addplot[color=black, mark=star] plot coordinates {"); + break; + case 5: + fprintf(tikz_fd,"\\addplot[color=blue, mark=o] plot coordinates {"); + break; + case 6: + fprintf(tikz_fd,"\\addplot[color=red, mark=o] plot coordinates {"); + break; + case 7: + fprintf(tikz_fd,"\\addplot[color=green, mark=o] plot coordinates {"); + break; + case 8: + fprintf(tikz_fd,"\\addplot[color=yellow, mark=o] plot coordinates {"); + break; + case 9: + fprintf(tikz_fd,"\\addplot[color=black, mark=o] plot coordinates {"); + break; + case 10: + fprintf(tikz_fd,"\\addplot[color=blue, mark=square] plot coordinates {"); + break; + case 11: + fprintf(tikz_fd,"\\addplot[color=red, mark=square] plot coordinates {"); + break; + case 12: + fprintf(tikz_fd,"\\addplot[color=green, mark=square] plot coordinates {"); + break; + case 13: + fprintf(tikz_fd,"\\addplot[color=yellow, mark=square] plot coordinates {"); + break; + case 14: + fprintf(tikz_fd,"\\addplot[color=black, mark=square] plot coordinates {"); + break; + case 15: + fprintf(tikz_fd,"\\addplot[color=blue, mark=diamond] plot coordinates {"); + break; + case 16: + fprintf(tikz_fd,"\\addplot[color=red, mark=diamond] plot coordinates {"); + break; + case 17: + fprintf(tikz_fd,"\\addplot[color=green, mark=diamond] plot coordinates {"); + break; + case 18: + fprintf(tikz_fd,"\\addplot[color=yellow, mark=diamond] plot coordinates {"); + break; + case 19: + fprintf(tikz_fd,"\\addplot[color=black, mark=diamond] plot coordinates {"); + break; + case 20: + fprintf(tikz_fd,"\\addplot[color=blue, mark=x] plot coordinates {"); + break; + case 21: + fprintf(tikz_fd,"\\addplot[color=red, mark=x] plot coordinates {"); + break; + case 22: + fprintf(tikz_fd,"\\addplot[color=green, mark=x] plot coordinates {"); + break; + case 23: + fprintf(tikz_fd,"\\addplot[color=yellow, mark=x] plot coordinates {"); + break; + case 24: + fprintf(tikz_fd,"\\addplot[color=black, mark=x] plot coordinates {"); + break; + case 25: + fprintf(tikz_fd,"\\addplot[color=blue, mark=x] plot coordinates {"); + break; + case 26: + fprintf(tikz_fd,"\\addplot[color=red, mark=+] plot coordinates {"); + break; + case 27: + fprintf(tikz_fd,"\\addplot[color=green, mark=+] plot coordinates {"); + break; + case 28: + fprintf(tikz_fd,"\\addplot[color=yellow, mark=+] plot coordinates {"); + break; + } + */ + UE->pdcch_vars[UE->current_thread_id[subframe]][0]->crnti = n_rnti; + UE->n_connected_eNB = 1; + printf("Allocating %dx%d eNB->UE channel descriptor\n",eNB->frame_parms.nb_antennas_tx,UE->frame_parms.nb_antennas_rx); + eNB2UE[0] = new_channel_desc_scm(eNB->frame_parms.nb_antennas_tx, + UE->frame_parms.nb_antennas_rx, + channel_model, + N_RB2sampling_rate(eNB->frame_parms.N_RB_DL), + N_RB2channel_bandwidth(eNB->frame_parms.N_RB_DL), + forgetting_factor, + rx_sample_offset, + 0); + reset_meas(&eNB2UE[0]->random_channel); + reset_meas(&eNB2UE[0]->interp_time); - fflush(fd); + if(num_rounds>1) { + for(n=1; n<4; n++) { + eNB2UE[n] = new_channel_desc_scm(eNB->frame_parms.nb_antennas_tx, + UE->frame_parms.nb_antennas_rx, + channel_model, + N_RB2sampling_rate(eNB->frame_parms.N_RB_DL), + N_RB2channel_bandwidth(eNB->frame_parms.N_RB_DL), + forgetting_factor, + rx_sample_offset, + 0); + reset_meas(&eNB2UE[n]->random_channel); + reset_meas(&eNB2UE[n]->interp_time); + } + } - if (errs[0] == 0) + if (eNB2UE[0]==NULL) { + printf("Problem generating channel model. Exiting.\n"); + exit(-1); + } + + if ((transmission_mode == 3) || (transmission_mode==4)) + Kmimo=2; + else + Kmimo=1; + + switch (ue_category) { + case 1: + Nsoft = 250368; + break; + + case 2: + case 3: + Nsoft = 1237248; + break; + + case 4: + Nsoft = 1827072; + break; + + default: + printf("Unsupported UE category %d\n",ue_category); + exit(-1); break; } - if (n_frames==1) { - printf("Dumping PMCH files ( G %d)\n",UE->dlsch_MCH[0]->harq_processes[0]->G); - dump_mch(UE,0, - UE->dlsch_MCH[0]->harq_processes[0]->G, - subframe); + for (k=0; kdlsch[k][i] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0,&eNB->frame_parms); + + if (!eNB->dlsch[k][i]) { + printf("Can't get eNB dlsch structures\n"); + exit(-1); + } + + eNB->dlsch[k][i]->rnti = n_rnti+k; + } } - printf("Freeing dlsch structures\n"); - free_eNB_dlsch(eNB->dlsch_MCH); - free_ue_dlsch(UE->dlsch_MCH[0]); - fclose(fd); - return(0); -} +#ifdef ENABLE_MBMS_SIM + eNB->dlsch_MCH = new_eNB_dlsch(1,8,Nsoft,N_RB_DL, 0, &eNB->frame_parms); +#endif + + /* allocate memory for both subframes (only one is really used + * but there is now "copy_harq_proc_struct" which needs both + * to be valid) + * TODO: refine this somehow (necessary?) + */ + for (sf = 0; sf < 2; sf++) { + for (i=0; i<2; i++) { + UE->dlsch[sf][0][i] = new_ue_dlsch(Kmimo,8,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0); + + if (!UE->dlsch[sf][0][i]) { + printf("Can't get ue dlsch structures\n"); + exit(-1); + } + + UE->dlsch[sf][0][i]->rnti = n_rnti; + } + } + +#ifdef ENABLE_MBMS_SIM + UE->dlsch_MCH[0] = new_ue_dlsch(1,8,Nsoft,MAX_TURBO_ITERATIONS_MBSFN,N_RB_DL,0); + UE->dlsch_MCH[0]->active = 1; + UE->dlsch_MCH[0]->harq_processes[0]->mcs = mcs1; +#endif + + UE->dlsch_SI[0] = new_ue_dlsch(1,1,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0); + UE->dlsch_ra[0] = new_ue_dlsch(1,1,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0); + UE->ulsch[0] = new_ue_ulsch(N_RB_DL,0); + // structure for SIC at UE + UE->dlsch_eNB[0] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0,&eNB->frame_parms); + + if (DLSCH_alloc_pdu2_1E[0].tpmi == 5) { + eNB->UE_stats[0].DL_pmi_single = (unsigned short)(taus()&0xffff); + + if (n_users>1) + eNB->UE_stats[1].DL_pmi_single = (eNB->UE_stats[0].DL_pmi_single ^ 0x1555); //opposite PMI + } else { + eNB->UE_stats[0].DL_pmi_single = 0; + + if (n_users>1) + eNB->UE_stats[1].DL_pmi_single = 0; + } + + L1_rxtx_proc_t *proc_eNB = &eNB->proc.L1_proc; + + if (input_fd==NULL) { + DL_req.dl_config_request_body.number_pdcch_ofdm_symbols = num_pdcch_symbols; + DL_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe; + TX_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe; + // UE specific DCI + fill_DCI(eNB, + proc_eNB->frame_tx,subframe, + &sched_resp, + input_buffer, + n_rnti, + n_users, + transmission_mode, + 0, + common_flag, + NB_RB, + DLSCH_RB_ALLOC, + TPC, + mcs1, + mcs2, + 1, + 0, + pa, + &num_common_dci, + &num_ue_spec_dci, + &num_dci); + numCCE = get_nCCE(num_pdcch_symbols,&eNB->frame_parms,get_mi(&eNB->frame_parms,subframe)); + + if (n_frames==1) printf("num_pdcch_symbols %d, numCCE %d, num_dci %d/%d/%d\n",num_pdcch_symbols,numCCE, num_dci,num_ue_spec_dci,num_common_dci); + } + + eNB->frame_parms.Nid_cell_mbsfn=0; + if(enable_fembms){ + lte_gold_mbsfn_khz_1dot25 (&eNB->frame_parms, eNB->lte_gold_mbsfn_khz_1dot25_table, eNB->frame_parms.Nid_cell_mbsfn); + eNB->frame_parms.NonMBSFN_config_flag=1; + }else{ + lte_gold_mbsfn (&eNB->frame_parms, eNB->lte_gold_mbsfn_table, eNB->frame_parms.Nid_cell_mbsfn); + eNB->frame_parms.num_MBSFN_config=1; + eNB->frame_parms.MBSFN_config[0].radioframeAllocationPeriod=0; + eNB->frame_parms.MBSFN_config[0].fourFrames_flag=0; + eNB->frame_parms.MBSFN_config[0].radioframeAllocationOffset=0; + //eNB->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xC0; + eNB->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xFC; + } + + + + snr_step = input_snr_step; + UE->high_speed_flag = 1; + UE->ch_est_alpha=0; + + for (ch_realization=0; ch_realizationproc.proc_rxtx[UE->current_thread_id[subframe]].frame_rx=0; + errs[0]=0; + errs[1]=0; + errs[2]=0; + errs[3]=0; + errs2[0]=0; + errs2[1]=0; + errs2[2]=0; + errs2[3]=0; + round_trials[0] = 0; + round_trials[1] = 0; + round_trials[2] = 0; + round_trials[3] = 0; + dci_errors[0]=0; + dci_errors[1]=0; + dci_errors[2]=0; + dci_errors[3]=0; + // avg_ber = 0; + round=0; + avg_iter = 0; + iter_trials=0; + reset_meas(&eNB->phy_proc_tx); // total eNB tx + reset_meas(&eNB->dlsch_scrambling_stats); + reset_meas(&UE->dlsch_unscrambling_stats); + reset_meas(&eNB->ofdm_mod_stats); + reset_meas(&eNB->dlsch_modulation_stats); + reset_meas(&eNB->dlsch_encoding_stats); + reset_meas(&eNB->dlsch_interleaving_stats); + reset_meas(&eNB->dlsch_rate_matching_stats); + reset_meas(&eNB->dlsch_turbo_encoding_stats); + reset_meas(&eNB->dlsch_common_and_dci); + reset_meas(&eNB->dlsch_ue_specific); + + for (int i=0; iphy_proc_rx[i]); // total UE rx + reset_meas(&UE->ue_front_end_stat[i]); + reset_meas(&UE->pdsch_procedures_stat[i]); + reset_meas(&UE->dlsch_procedures_stat[i]); + reset_meas(&UE->dlsch_decoding_stats[i]); + reset_meas(&UE->dlsch_llr_stats_parallelization[i][0]); + reset_meas(&UE->dlsch_llr_stats_parallelization[i][1]); + } + + reset_meas(&UE->ofdm_demod_stats); + reset_meas(&UE->crnti_procedures_stats); + reset_meas(&UE->dlsch_channel_estimation_stats); + reset_meas(&UE->dlsch_freq_offset_estimation_stats); + reset_meas(&UE->rx_dft_stats); + reset_meas(&UE->dlsch_decoding_stats[0]); + reset_meas(&UE->dlsch_decoding_stats[1]); + reset_meas(&UE->dlsch_turbo_decoding_stats); + reset_meas(&UE->dlsch_deinterleaving_stats); + reset_meas(&UE->dlsch_rate_unmatching_stats); + reset_meas(&UE->dlsch_tc_init_stats); + reset_meas(&UE->dlsch_tc_alpha_stats); + reset_meas(&UE->dlsch_tc_beta_stats); + reset_meas(&UE->dlsch_tc_gamma_stats); + reset_meas(&UE->dlsch_tc_ext_stats); + reset_meas(&UE->dlsch_tc_intl1_stats); + reset_meas(&UE->dlsch_tc_intl2_stats); + // initialization + // initialization + varArray_t *table_tx=initVarArray(1000,sizeof(double)); + varArray_t *table_tx_ifft=initVarArray(1000,sizeof(double)); + varArray_t *table_tx_mod=initVarArray(1000,sizeof(double)); + varArray_t *table_tx_enc=initVarArray(1000,sizeof(double)); + varArray_t *table_rx=initVarArray(1000,sizeof(double)); + time_stats_t phy_proc_rx_tot; + time_stats_t pdsch_procedures_tot; + time_stats_t dlsch_procedures_tot; + time_stats_t dlsch_decoding_tot; + time_stats_t dlsch_llr_tot; + time_stats_t ue_front_end_tot; + varArray_t *table_rx_fft=initVarArray(1000,sizeof(double)); + varArray_t *table_rx_demod=initVarArray(1000,sizeof(double)); + varArray_t *table_rx_dec=initVarArray(1000,sizeof(double)); + + for (trials = 0; trialsfirst_run = 1; + UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_ack[subframe].ack = 0; + UE->dlsch[UE->current_thread_id[subframe]][eNB_id][1]->harq_ack[subframe].ack = 0; + + while ((round < num_rounds) && (UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_ack[subframe].ack == 0)) { + // printf("Trial %d, round %d\n",trials,round); + round_trials[round]++; + + //if(transmission_mode>=5) + // pmi_feedback=1; + //else + // pmi_feedback=0; + + if (abstx) { + if (trials==0 && round==0 && SNR==snr0) //generate a new channel + hold_channel = 0; + else + hold_channel = 1; + } else + hold_channel = 0;//(round==0) ? 0 : 1; + + //PMI_FEEDBACK: + + // printf("Trial %d : Round %d, pmi_feedback %d \n",trials,round,pmi_feedback); + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { + memset(&eNB->common_vars.txdataF[aa][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t)); + } + + if (input_fd==NULL) { + // Simulate HARQ procedures!!! + memset(CCE_table,0,800*sizeof(int)); + + if (/*common_flag == 0*/ 1) { + num_dci=0; + num_common_dci=0; + num_ue_spec_dci=0; + + if (round == 0) { // First round + TB0_active = 1; + eNB->dlsch[0][0]->harq_processes[0]->rvidx = round&3; + DL_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe; + TX_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe; + fill_DCI(eNB,proc_eNB->frame_tx,subframe,&sched_resp,input_buffer,n_rnti,n_users,transmission_mode,0,common_flag,NB_RB,DLSCH_RB_ALLOC,TPC, + mcs1,mcs2,!(trials&1),round&3,pa,&num_common_dci,&num_ue_spec_dci,&num_dci); + } else { + DL_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe; + TX_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe; + fill_DCI(eNB,proc_eNB->frame_tx,subframe,&sched_resp,input_buffer,n_rnti,n_users,transmission_mode,1,common_flag,NB_RB,DLSCH_RB_ALLOC,TPC, + (TB0_active==1)?mcs1:0,mcs2,!(trials&1),(TB0_active==1)?round&3:0,pa,&num_common_dci,&num_ue_spec_dci,&num_dci); + } + } + +//#ifdef ENABLE_MBMS_SIM +// eNB->frame_parms.Nid_cell_mbsfn=0; +// lte_gold_mbsfn (&eNB->frame_parms, eNB->lte_gold_mbsfn_table, eNB->frame_parms.Nid_cell_mbsfn); +//#endif + + UE->measurements.n0_power_tot_dB = 10*log10((double)tx_lev) +10*log10((double)ru->frame_parms.ofdm_symbol_size/(double)(ru->frame_parms.N_RB_DL*12)) - SNR; + UE->measurements.n0_power_tot = pow(10,( 10*log10((double)tx_lev) +10*log10((double)ru->frame_parms.ofdm_symbol_size/(double)(ru->frame_parms.N_RB_DL*12)) - SNR)/10); + + proc_eNB->subframe_tx = subframe; + sched_resp.subframe=subframe; + sched_resp.frame=proc_eNB->frame_tx; + eNB->abstraction_flag=0; + schedule_response(&sched_resp); + phy_procedures_eNB_TX(eNB,proc_eNB,1); + + if (uncoded_ber_bit == NULL) { + // this is for user 0 only + printf("nb_rb %d, rb_alloc %x, mcs %d\n", + eNB->dlsch[0][0]->harq_processes[0]->nb_rb, + eNB->dlsch[0][0]->harq_processes[0]->rb_alloc[0], + eNB->dlsch[0][0]->harq_processes[0]->mcs); + coded_bits_per_codeword = get_G(&eNB->frame_parms, + eNB->dlsch[0][0]->harq_processes[0]->nb_rb, + eNB->dlsch[0][0]->harq_processes[0]->rb_alloc, + get_Qm(eNB->dlsch[0][0]->harq_processes[0]->mcs), + eNB->dlsch[0][0]->harq_processes[0]->Nl, + num_pdcch_symbols, + 0, + subframe, + transmission_mode>=7?transmission_mode:0); + uncoded_ber_bit = (short *) malloc(sizeof(short)*coded_bits_per_codeword); + printf("uncoded_ber_bit=%p\n",uncoded_ber_bit); + } + + + + start_meas(&eNB->ofdm_mod_stats); + ru->proc.subframe_tx=subframe; + LOG_W(PHY,"eNB %d\n",eNB->frame_parms.num_MBSFN_config); + LOG_W(PHY,"eNB %d\n",eNB->frame_parms.NonMBSFN_config_flag); + memcpy((void *)&ru->frame_parms,(void *)&eNB->frame_parms,sizeof(LTE_DL_FRAME_PARMS)); + LOG_W(PHY,"RU %d\n",ru->frame_parms.num_MBSFN_config); + LOG_W(PHY,"RU %d\n",ru->frame_parms.NonMBSFN_config_flag); + feptx_prec(ru); + feptx_ofdm(ru); + stop_meas(&eNB->ofdm_mod_stats); + // generate next subframe for channel estimation + DL_req.dl_config_request_body.number_dci=0; + DL_req.dl_config_request_body.number_pdu=0; + TX_req.tx_request_body.number_of_pdus=0; + proc_eNB->subframe_tx = subframe+1; + sched_resp.subframe=subframe+1; + schedule_response(&sched_resp); + + phy_procedures_eNB_TX(eNB,proc_eNB,0); + ru->proc.subframe_tx=(subframe+1)%10; + feptx_prec(ru); + feptx_ofdm(ru); + proc_eNB->frame_tx++; + tx_lev = 0; + + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { + tx_lev += signal_energy(&ru->common.txdata[aa] + [subframe*eNB->frame_parms.samples_per_tti], + eNB->frame_parms.samples_per_tti); + } + + tx_lev_dB = (unsigned int) dB_fixed(tx_lev); + + if (n_frames==1) { + printf("tx_lev = %u (%u dB)\n",tx_lev,tx_lev_dB); + LOG_M("txsig0.m","txs0", &ru->common.txdata[0][subframe* eNB->frame_parms.samples_per_tti], eNB->frame_parms.samples_per_tti,1,1); + + if (transmission_mode<7) { + LOG_M("txsigF0.m","txsF0x", &ru->common.txdataF_BF[0][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],nsymb*eNB->frame_parms.ofdm_symbol_size,1,1); + } else if (transmission_mode == 7) { + LOG_M("txsigF0.m","txsF0", &ru->common.txdataF_BF[5][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],nsymb*eNB->frame_parms.ofdm_symbol_size,1,1); + LOG_M("txsigF0_BF.m","txsF0_BF", &ru->common.txdataF_BF[0][0],eNB->frame_parms.ofdm_symbol_size,1,1); + } + } + } + + DL_channel(ru,UE,subframe,awgn_flag,SNR,tx_lev,hold_channel,abstx,num_rounds,trials,round,eNB2UE,s_re,s_im,r_re,r_im,csv_fd); + UE_rxtx_proc_t *proc = &UE->proc.proc_rxtx[UE->current_thread_id[subframe]]; + proc->subframe_rx = subframe; + UE->UE_mode[0] = PUSCH; + // first symbol has to be done separately in one-shot mode + slot_fep(UE, + 0, + (proc->subframe_rx<<1), + UE->rx_offset, + 0, + 0); + + if (n_frames==1) printf("Running phy_procedures_UE_RX\n"); + + if (dci_flag==0) { + memcpy(dci_alloc,eNB->pdcch_vars[subframe&1].dci_alloc,num_dci*sizeof(DCI_ALLOC_t)); + UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->num_pdcch_symbols = num_pdcch_symbols; + + if (n_frames==1) + printf("bypassing PDCCH/DCI detection\n"); + + if (generate_ue_dlsch_params_from_dci(proc->frame_rx, + proc->subframe_rx, + (void *)&dci_alloc[0].dci_pdu, + common_flag == 0 ? n_rnti : SI_RNTI, + dci_alloc[0].format, + UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id], + UE->pdsch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id], + UE->dlsch[UE->current_thread_id[proc->subframe_rx]][0], + &UE->frame_parms, + UE->pdsch_config_dedicated, + SI_RNTI, + 0, + P_RNTI, + UE->transmission_mode[eNB_id]<7?0:UE->transmission_mode[eNB_id], + 0)==0) { + dump_dci(&UE->frame_parms, &dci_alloc[0]); + //UE->dlsch[UE->current_thread_id[proc->subframe_rx]][eNB_id][0]->active = 1; + //UE->dlsch[UE->current_thread_id[proc->subframe_rx]][eNB_id][1]->active = 1; + UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->num_pdcch_symbols = num_pdcch_symbols; + UE->dlsch_received[eNB_id]++; + } else { + LOG_E(PHY,"Problem in DCI!\n"); + } + } + + + UE->frame_parms.Nid_cell_mbsfn=0; + if(enable_fembms){ + lte_gold_mbsfn_khz_1dot25 (&UE->frame_parms, UE->lte_gold_mbsfn_khz_1dot25_table, UE->frame_parms.Nid_cell_mbsfn); + UE->frame_parms.NonMBSFN_config_flag=1; + }else{ + lte_gold_mbsfn (&UE->frame_parms, UE->lte_gold_mbsfn_table, UE->frame_parms.Nid_cell_mbsfn); + UE->frame_parms.num_MBSFN_config=1; + UE->frame_parms.MBSFN_config[0].radioframeAllocationPeriod=0; + UE->frame_parms.MBSFN_config[0].fourFrames_flag=0; + UE->frame_parms.MBSFN_config[0].radioframeAllocationOffset=0; + UE->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xC0; + } + + + + + dci_received = UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->dci_received; + phy_procedures_UE_RX(UE,proc,0,0,dci_flag,normal_txrx); + dci_received = dci_received - UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->dci_received; + + if (dci_flag && (dci_received == 0)) { + printf("DCI not received\n"); + dci_errors[round]++; + LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1); + LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1); + LOG_M("pdcch_rxF_comp0.m","pdcch0_rxF_comp0",UE->pdcch_vars[0][eNB_id]->rxdataF_comp[0],4*300,1,1); + LOG_M("pdcch_rxF_llr.m","pdcch_llr",UE->pdcch_vars[0][eNB_id]->llr,2400,1,4); + LOG_M("rxsig0.m","rxs0", &UE->common_vars.rxdata[0][0],10*UE->frame_parms.samples_per_tti,1,1); + LOG_M("rxsigF0.m","rxsF0", &UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[0][0],UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + exit(-1); + } + + int bit_errors=0; + + if ((test_perf ==0 ) && (n_frames==1)) { + dlsch_unscrambling(&eNB->frame_parms, + 0, + UE->dlsch[UE->current_thread_id[subframe]][0][0], + coded_bits_per_codeword, + UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0], + 0, + subframe<<1); + + for (i=0; idlsch[0][0]->harq_processes[0]->e[i]==1 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] > 0)|| + (eNB->dlsch[0][0]->harq_processes[0]->e[i]==0 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] < 0)) { + uncoded_ber_bit[bit_errors++] = 1; + printf("error in pos %d : %d => %d\n",i, + eNB->dlsch[0][0]->harq_processes[0]->e[i], + UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i]); + } else { + /* + printf("no error in pos %d : %d => %d\n",i, + eNB->dlsch[0][0]->harq_processes[0]->e[i], + UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i]); + */ + } + + LOG_M("dlsch_ber_bit.m","ber_bit",uncoded_ber_bit,coded_bits_per_codeword,1,0); + LOG_M("ch0.m","ch0",eNB2UE[0]->ch[0],eNB2UE[0]->channel_length,1,8); + + if (eNB->frame_parms.nb_antennas_tx>1) + LOG_M("ch1.m","ch1",eNB2UE[0]->ch[eNB->frame_parms.nb_antennas_rx],eNB2UE[0]->channel_length,1,8); + + //common vars + LOG_M("rxsig0.m","rxs0", &UE->common_vars.rxdata[0][0],10*UE->frame_parms.samples_per_tti,1,1); + LOG_M("rxsigF0.m","rxsF0", &UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[0][0],UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + + if (UE->frame_parms.nb_antennas_rx>1) { + LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1],UE->frame_parms.samples_per_tti,1,1); + LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[1],UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + } + + LOG_M("dlsch00_r0.m","dl00_r0", + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][0][0]), + UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + + if (UE->frame_parms.nb_antennas_rx>1) + LOG_M("dlsch01_r0.m","dl01_r0", + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][1][0]), + UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + + if (eNB->frame_parms.nb_antennas_tx>1) + LOG_M("dlsch10_r0.m","dl10_r0", + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][2][0]), + UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + + if ((UE->frame_parms.nb_antennas_rx>1) && (eNB->frame_parms.nb_antennas_tx>1)) + LOG_M("dlsch11_r0.m","dl11_r0", + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][3][0]), + UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1); + + //pdsch_vars + printf("coded_bits_per_codeword %u\n",coded_bits_per_codeword); + dump_dlsch2(UE,eNB_id,subframe,&coded_bits_per_codeword,round, UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid); + LOG_M("dlsch_e.m","e",eNB->dlsch[0][0]->harq_processes[0]->e,coded_bits_per_codeword,1,4); + //pdcch_vars + LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1); + LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1); + LOG_M("pdcch_rxF_comp0.m","pdcch0_rxF_comp0",UE->pdcch_vars[0][eNB_id]->rxdataF_comp[0],4*300,1,1); + LOG_M("pdcch_rxF_llr.m","pdcch_llr",UE->pdcch_vars[0][eNB_id]->llr,2400,1,4); + } + + if (UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_ack[subframe].ack == 1) { + avg_iter += UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->last_iteration_cnt; + iter_trials++; + + if (n_frames==1) + printf("No DLSCH errors found (round %d),uncoded ber %f\n",round,(double)bit_errors/coded_bits_per_codeword); + + UE->total_TBS[eNB_id] = UE->total_TBS[eNB_id] + UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_processes[UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->current_harq_pid]->TBS; + TB0_active = 0; + } // DLSCH received ok + else { + errs[round]++; + avg_iter += UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->last_iteration_cnt-1; + iter_trials++; + + if (n_frames==1) { + //if ((n_frames==1) || (SNR>=30)) { + printf("DLSCH errors found (round %d), uncoded ber %f\n",round,(double)bit_errors/coded_bits_per_codeword); + + for (s=0; sdlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->C; s++) { + if (sdlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus) + Kr = UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus; + else + Kr = UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus; + + Kr_bytes = Kr>>3; + printf("Decoded_output (Segment %d):\n",s); + + for (i=0; idlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->c[s][i], + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->c[s][i]^eNB->dlsch[0][0]->harq_processes[0]->c[s][i]); + } + + sprintf(fname,"rxsig0_r%d.m",round); + sprintf(vname,"rxs0_r%d",round); + LOG_M(fname,vname, &UE->common_vars.rxdata[0][0],10*UE->frame_parms.samples_per_tti,1,1); + sprintf(fname,"rxsigF0_r%d.m",round); + sprintf(vname,"rxs0F_r%d",round); + LOG_M(fname,vname, &UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[0][0],UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + + if (UE->frame_parms.nb_antennas_rx>1) { + sprintf(fname,"rxsig1_r%d.m",round); + sprintf(vname,"rxs1_r%d.m",round); + LOG_M(fname,vname, UE->common_vars.rxdata[1],UE->frame_parms.samples_per_tti,1,1); + sprintf(fname,"rxsigF1_r%d.m",round); + sprintf(vname,"rxs1F_r%d.m",round); + LOG_M(fname,vname, UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[1],UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + } + + sprintf(fname,"dlsch00_r%d.m",round); + sprintf(vname,"dl00_r%d",round); + LOG_M(fname,vname, + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][0][0]), + UE->frame_parms.ofdm_symbol_size*nsymb,1,1); + + if (UE->frame_parms.nb_antennas_rx>1) { + sprintf(fname,"dlsch01_r%d.m",round); + sprintf(vname,"dl01_r%d",round); + LOG_M(fname,vname, + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][1][0]), + UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1); + } + + if (eNB->frame_parms.nb_antennas_tx>1) { + sprintf(fname,"dlsch10_r%d.m",round); + sprintf(vname,"dl10_r%d",round); + LOG_M(fname,vname, + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][2][0]), + UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1); + } + + if ((UE->frame_parms.nb_antennas_rx>1) && (eNB->frame_parms.nb_antennas_tx>1)) { + sprintf(fname,"dlsch11_r%d.m",round); + sprintf(vname,"dl11_r%d",round); + LOG_M(fname,vname, + &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][3][0]), + UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1); + } + + //pdsch_vars + dump_dlsch2(UE,eNB_id,subframe,&coded_bits_per_codeword,round, UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid); + //LOG_M("dlsch_e.m","e",eNB->dlsch[0][0]->harq_processes[0]->e,coded_bits_per_codeword,1,4); + //LOG_M("dlsch_ber_bit.m","ber_bit",uncoded_ber_bit,coded_bits_per_codeword,1,0); + //LOG_M("dlsch_w.m","w",eNB->dlsch[0][0]->harq_processes[0]->w[0],3*(tbs+64),1,4); + //LOG_M("dlsch_w.m","w",UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->w[0],3*(tbs+64),1,0); + //pdcch_vars + LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1); + LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1); + LOG_M("pdcch_rxF_comp0.m","pdcch0_rxF_comp0",UE->pdcch_vars[0][eNB_id]->rxdataF_comp[0],4*300,1,1); + LOG_M("pdcch_rxF_llr.m","pdcch_llr",UE->pdcch_vars[0][eNB_id]->llr,2400,1,4); + + if (round == 3) exit(-1); + } + + // printf("round %d errors %d/%d\n",round,errs[round],trials); + round++; + // UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->round++; + } + + if (xforms==1) { + phy_scope_UE(form_ue, + UE, + eNB_id, + 0,// UE_id + subframe); + } + + UE->proc.proc_rxtx[UE->current_thread_id[subframe]].frame_rx++; + } //round + + // printf("\n"); + + if ((errs[0]>=n_frames/10) && (trials>(n_frames/2))) + break; + + //len = chbch_stats_read(stats_buffer,NULL,0,4096); + //printf("%s\n\n",stats_buffer); + + if (UE->proc.proc_rxtx[UE->current_thread_id[subframe]].frame_rx % 10 == 0) { + UE->bitrate[eNB_id] = (UE->total_TBS[eNB_id] - UE->total_TBS_last[eNB_id])*10; + LOG_D(PHY,"[UE %d] Calculating bitrate: total_TBS = %d, total_TBS_last = %d, bitrate = %d kbits/s\n",UE->Mod_id,UE->total_TBS[eNB_id],UE->total_TBS_last[eNB_id], + UE->bitrate[eNB_id]/1000); + UE->total_TBS_last[eNB_id] = UE->total_TBS[eNB_id]; + } + + /* calculate the total processing time for each packet, + * get the max, min, and number of packets that exceed t>2000us + */ + double t_tx = inMicroS(eNB->phy_proc_tx.p_time); + double t_tx_ifft = inMicroS(eNB->ofdm_mod_stats.p_time); + double t_rx = inMicroS(UE->phy_proc_rx[UE->current_thread_id[subframe]].p_time); + sumUpStats(&phy_proc_rx_tot, UE->phy_proc_rx, UE->current_thread_id[subframe]); + sumUpStats(&ue_front_end_tot, UE->ue_front_end_stat, UE->current_thread_id[subframe]); + sumUpStats(&pdsch_procedures_tot, UE->pdsch_procedures_stat, UE->current_thread_id[subframe]); + sumUpStats(&dlsch_procedures_tot, UE->dlsch_procedures_stat, UE->current_thread_id[subframe]); + sumUpStats(&dlsch_decoding_tot, UE->dlsch_decoding_stats, UE->current_thread_id[subframe]); + sumUpStatsSlot(&dlsch_llr_tot, UE->dlsch_llr_stats_parallelization, UE->current_thread_id[subframe]); + double t_rx_fft = inMicroS(UE->ofdm_demod_stats.p_time); + double t_rx_demod = inMicroS(UE->dlsch_rx_pdcch_stats.p_time); + double t_rx_dec = inMicroS(UE->dlsch_decoding_stats[UE->current_thread_id[subframe]].p_time); + + if (t_tx > 2000 )// 2ms is too much time for a subframe + n_tx_dropped++; + + if (t_rx > 2000 ) + n_rx_dropped++; + + appendVarArray(table_tx, &t_tx); + appendVarArray(table_tx_ifft, &t_tx_ifft); + appendVarArray(table_rx, &t_rx ); + appendVarArray(table_rx_fft, &t_rx_fft ); + appendVarArray(table_rx_demod, &t_rx_demod ); + appendVarArray(table_rx_dec, &t_rx_dec ); + } //trials + + // round_trials[0]: number of code word : goodput the protocol + // sort table + qsort (dataArray(table_tx), table_tx->size, table_tx->atomSize, &cmpdouble); + qsort (dataArray(table_tx_ifft), table_tx_ifft->size, table_tx_ifft->atomSize, &cmpdouble); + qsort (dataArray(table_tx_mod), table_tx_mod->size, table_tx_mod->atomSize, &cmpdouble); + qsort (dataArray(table_tx_enc), table_tx_enc->size, table_tx_enc->atomSize, &cmpdouble); + qsort (dataArray(table_rx), table_rx->size, table_rx->atomSize, &cmpdouble); + qsort (dataArray(table_rx_fft), table_rx_fft->size, table_rx_fft->atomSize, &cmpdouble); + qsort (dataArray(table_rx_demod), table_rx_demod->size, table_rx_demod->atomSize, &cmpdouble); + qsort (dataArray(table_rx_dec), table_rx_dec->size, table_rx_dec->atomSize, &cmpdouble); + + if (dump_table == 1 ) { + set_component_filelog(SIM); // file located in /tmp/usim.txt + LOG_UDUMPMSG(SIM,table_tx,table_tx->size,LOG_DUMP_DOUBLE,"The transmitter raw data: \n"); + LOG_UDUMPMSG(SIM,table_rx,table_rx->size,LOG_DUMP_DOUBLE,"Thereceiver raw data: \n"); + } + + effective_rate = 1.0-((double)(errs[0]+errs[1]+errs[2]+errs[3])/((double)round_trials[0] + round_trials[1] + round_trials[2] + round_trials[3])); + printf("\n**********************SNR = %f dB (tx_lev %f)**************************\n", + SNR, + (double)tx_lev_dB+10*log10(UE->frame_parms.ofdm_symbol_size/(NB_RB*12))); + printf("Errors (%u(%u)/%u %u/%u %u/%u %u/%u), Pe = (%e,%e,%e,%e), dci_errors %u/%u, Pe = %e => effective rate %f, normalized delay %f (%f)\n", + errs[0], + errs2[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + (double)errs[0]/(round_trials[0]), + (double)errs[1]/(round_trials[1]), + (double)errs[2]/(round_trials[2]), + (double)errs[3]/(round_trials[3]), + dci_errors[0]+dci_errors[1]+dci_errors[2]+dci_errors[3], + round_trials[0]+round_trials[1]+round_trials[2]+round_trials[3], + (double)(dci_errors[0]+dci_errors[1]+dci_errors[2]+dci_errors[3])/(round_trials[0]+round_trials[1]+round_trials[2]+round_trials[3]), + //rate*effective_rate, + 100*effective_rate, + //rate, + //rate*get_Qm(UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid]->mcs), + (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])/ + (double)eNB->dlsch[0][0]->harq_processes[0]->TBS, + (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])); + double timeBase=1/(1000*cpu_freq_GHz); + + if (print_perf==1) { + printf("\neNB TX function statistics (per 1ms subframe)\n"); + printDistribution(&eNB->phy_proc_tx,table_tx,"PHY proc tx"); + printStatIndent(&eNB->dlsch_common_and_dci,"DL common channels and dci time"); + printStatIndent(&eNB->dlsch_ue_specific,"DL per ue part time"); + printStatIndent2(&eNB->dlsch_encoding_stats,"DLSCH encoding time"); + printStatIndent3(&eNB->dlsch_rate_matching_stats,"DLSCH rate matching time"); + printStatIndent3(&eNB->dlsch_turbo_encoding_stats,"DLSCH turbo encoding time"); + printStatIndent3(&eNB->dlsch_interleaving_stats,"DLSCH interleaving time"); + printStatIndent2(&eNB->dlsch_scrambling_stats, "DLSCH scrambling time"); + printStatIndent2(&eNB->dlsch_modulation_stats, "DLSCH modulation time"); + printDistribution(&eNB->ofdm_mod_stats,table_tx_ifft,"OFDM_mod (idft) time"); + printf("\nUE RX function statistics (per 1ms subframe)\n"); + printDistribution(&phy_proc_rx_tot, table_rx,"Total PHY proc rx"); + printStatIndent(&ue_front_end_tot,"Front end processing"); + printStatIndent(&dlsch_llr_tot,"rx_pdsch processing"); + printStatIndent2(&pdsch_procedures_tot,"pdsch processing"); + printStatIndent2(&dlsch_procedures_tot,"dlsch processing"); + printStatIndent2(&UE->crnti_procedures_stats,"C-RNTI processing"); + printStatIndent(&UE->ofdm_demod_stats,"ofdm demodulation"); + printStatIndent(&UE->dlsch_channel_estimation_stats,"DLSCH channel estimation time"); + printStatIndent(&UE->dlsch_freq_offset_estimation_stats,"DLSCH frequency offset estimation time"); + printStatIndent(&dlsch_decoding_tot, "DLSCH Decoding time "); + printStatIndent(&UE->dlsch_unscrambling_stats,"DLSCH unscrambling time"); + printStatIndent(&UE->dlsch_rate_unmatching_stats,"DLSCH Rate Unmatching"); + printf("|__ DLSCH Turbo Decoding(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n", + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus ? + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus : + UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus, + UE->dlsch_tc_intl1_stats.trials/(double)UE->dlsch_tc_init_stats.trials, + (double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials*timeBase, + (int)((double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials), + UE->dlsch_turbo_decoding_stats.trials); + printStatIndent2(&UE->dlsch_tc_init_stats,"init"); + printStatIndent2(&UE->dlsch_tc_alpha_stats,"alpha"); + printStatIndent2(&UE->dlsch_tc_beta_stats,"beta"); + printStatIndent2(&UE->dlsch_tc_gamma_stats,"gamma"); + printStatIndent2(&UE->dlsch_tc_ext_stats,"ext"); + printStatIndent2(&UE->dlsch_tc_intl1_stats,"turbo internal interleaver"); + printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC"); + } + + if ((transmission_mode != 3) && (transmission_mode != 4)) { + fprintf(bler_fd,"%f;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u\n", + SNR, + mcs1, + eNB->dlsch[0][0]->harq_processes[0]->TBS, + rate, + errs[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + dci_errors[0]); + } else { + fprintf(bler_fd,"%f;%d;%d;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u\n", + SNR, + mcs1,mcs2, + eNB->dlsch[0][0]->harq_processes[0]->TBS, + eNB->dlsch[0][1]->harq_processes[0]->TBS, + rate, + errs[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + dci_errors[0]); + } + + if(abstx) { //ABSTRACTION + blerr[0] = (double)errs[0]/(round_trials[0]); + + if(num_rounds>1) { + blerr[1] = (double)errs[1]/(round_trials[1]); + blerr[2] = (double)errs[2]/(round_trials[2]); + blerr[3] = (double)errs[3]/(round_trials[3]); + fprintf(csv_fd,"%e,%e,%e,%e;\n",blerr[0],blerr[1],blerr[2],blerr[3]); + } else { + fprintf(csv_fd,"%e;\n",blerr[0]); + } + } //ABStraction + + if ( (test_perf != 0) && (100 * effective_rate > test_perf )) { + //fprintf(time_meas_fd,"SNR; MCS; TBS; rate; err0; trials0; err1; trials1; err2; trials2; err3; trials3; dci_err\n"); + if ((transmission_mode != 3) && (transmission_mode != 4)) { + fprintf(time_meas_fd,"%f;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u;", + SNR, + mcs1, + eNB->dlsch[0][0]->harq_processes[0]->TBS, + rate, + errs[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + dci_errors[0]); + //fprintf(time_meas_fd,"SNR; MCS; TBS; rate; DL_DECOD_ITER; err0; trials0; err1; trials1; err2; trials2; err3; trials3; PE; dci_err;PE;ND;\n"); + fprintf(time_meas_fd,"%f;%d;%d;%f; %2.1f%%;%f;%f;%u;%u;%u;%u;%u;%u;%u;%u;%e;%e;%e;%e;%u;%u;%e;%f;%f;", + SNR, + mcs1, + eNB->dlsch[0][0]->harq_processes[0]->TBS, + rate*effective_rate, + 100*effective_rate, + rate, + (double)avg_iter/iter_trials, + errs[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + (double)errs[0]/(round_trials[0]), + (double)errs[1]/(round_trials[0]), + (double)errs[2]/(round_trials[0]), + (double)errs[3]/(round_trials[0]), + dci_errors[0], + round_trials[0], + (double)dci_errors[0]/(round_trials[0]), + (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])/ + (double)eNB->dlsch[0][0]->harq_processes[0]->TBS, + (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])); + } else { + fprintf(time_meas_fd,"%f;%d;%d;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u;", + SNR, + mcs1,mcs2, + eNB->dlsch[0][0]->harq_processes[0]->TBS, + eNB->dlsch[0][1]->harq_processes[0]->TBS, + rate, + errs[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + dci_errors[0]); + //fprintf(time_meas_fd,"SNR; MCS; TBS; rate; DL_DECOD_ITER; err0; trials0; err1; trials1; err2; trials2; err3; trials3; PE; dci_err;PE;ND;\n"); + fprintf(time_meas_fd,"%f;%d;%d;%d;%d;%f;%2.1f;%f;%f;%u;%u;%u;%u;%u;%u;%u;%u;%e;%e;%e;%e;%u;%u;%e;%f;%f;", + SNR, + mcs1,mcs2, + eNB->dlsch[0][0]->harq_processes[0]->TBS, + eNB->dlsch[0][1]->harq_processes[0]->TBS, + rate*effective_rate, + 100*effective_rate, + rate, + (double)avg_iter/iter_trials, + errs[0], + round_trials[0], + errs[1], + round_trials[1], + errs[2], + round_trials[2], + errs[3], + round_trials[3], + (double)errs[0]/(round_trials[0]), + (double)errs[1]/(round_trials[0]), + (double)errs[2]/(round_trials[0]), + (double)errs[3]/(round_trials[0]), + dci_errors[0], + round_trials[0], + (double)dci_errors[0]/(round_trials[0]), + (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])/ + (double)eNB->dlsch[0][0]->harq_processes[0]->TBS, + (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])); + } + + //fprintf(time_meas_fd,"eNB_PROC_TX(%d); OFDM_MOD(%d); DL_MOD(%d); DL_SCR(%d); DL_ENC(%d); UE_PROC_RX(%d); OFDM_DEMOD_CH_EST(%d); RX_PDCCH(%d); CH_COMP_LLR(%d); DL_USCR(%d); DL_DECOD(%d);\n", + fprintf(time_meas_fd,"%d; %d; %d; %d; %d; %d; %d; %d; %d; %d; %d;", + eNB->phy_proc_tx.trials, + eNB->ofdm_mod_stats.trials, + eNB->dlsch_modulation_stats.trials, + eNB->dlsch_scrambling_stats.trials, + eNB->dlsch_encoding_stats.trials, + phy_proc_rx_tot.trials, + UE->ofdm_demod_stats.trials, + UE->dlsch_rx_pdcch_stats.trials, + UE->dlsch_llr_stats.trials, + UE->dlsch_unscrambling_stats.trials, + UE->dlsch_decoding_stats[UE->current_thread_id[subframe]].trials + ); + fprintf(time_meas_fd,"%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;", + get_time_meas_us(&eNB->phy_proc_tx), + get_time_meas_us(&eNB->ofdm_mod_stats), + get_time_meas_us(&eNB->dlsch_modulation_stats), + get_time_meas_us(&eNB->dlsch_scrambling_stats), + get_time_meas_us(&eNB->dlsch_encoding_stats), + get_time_meas_us(&phy_proc_rx_tot), + nsymb*get_time_meas_us(&UE->ofdm_demod_stats), + get_time_meas_us(&UE->dlsch_rx_pdcch_stats), + 3*get_time_meas_us(&UE->dlsch_llr_stats), + get_time_meas_us(&UE->dlsch_unscrambling_stats), + get_time_meas_us(&UE->dlsch_decoding_stats[UE->current_thread_id[subframe]]) + ); + //fprintf(time_meas_fd,"eNB_PROC_TX_STD;eNB_PROC_TX_MAX;eNB_PROC_TX_MIN;eNB_PROC_TX_MED;eNB_PROC_TX_Q1;eNB_PROC_TX_Q3;eNB_PROC_TX_DROPPED;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;%f;%f;%d;",squareRoot(&UE->phy_proc_tx), t_tx_max, t_tx_min, median(table_tx), q1(table_tx), q3(table_tx), n_tx_dropped); + //fprintf(time_meas_fd,"IFFT;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;", + squareRoot(&eNB->ofdm_mod_stats), + median(table_tx_ifft),q1(table_tx_ifft),q3(table_tx_ifft)); + //fprintf(time_meas_fd,"MOD;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;", + squareRoot(&eNB->dlsch_modulation_stats), + median(table_tx_mod), q1(table_tx_mod), q3(table_tx_mod)); + //fprintf(time_meas_fd,"ENC;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;", + squareRoot(&eNB->dlsch_encoding_stats), + median(table_tx_enc),q1(table_tx_enc),q3(table_tx_enc)); + //fprintf(time_meas_fd,"eNB_PROC_RX_STD;eNB_PROC_RX_MAX;eNB_PROC_RX_MIN;eNB_PROC_RX_MED;eNB_PROC_RX_Q1;eNB_PROC_RX_Q3;eNB_PROC_RX_DROPPED;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;%f;%f;%d;", + squareRoot(&phy_proc_rx_tot), t_rx_max, t_rx_min, + median(table_rx), q1(table_rx), q3(table_rx), n_rx_dropped); + //fprintf(time_meas_fd,"FFT;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;", + squareRoot(&UE->ofdm_demod_stats), + median(table_rx_fft), q1(table_rx_fft), q3(table_rx_fft)); + //fprintf(time_meas_fd,"DEMOD;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f;", + squareRoot(&UE->dlsch_demodulation_stats), + median(table_rx_demod), q1(table_rx_demod), q3(table_rx_demod)); + //fprintf(time_meas_fd,"DEC;\n"); + fprintf(time_meas_fd,"%f;%f;%f;%f\n", + squareRoot(&UE->dlsch_decoding_stats[subframe]), + median(table_rx_dec), q1(table_rx_dec), q3(table_rx_dec)); + printf("[passed] effective rate : %f (%2.1f%%,%f)): log and break \n",rate*effective_rate, 100*effective_rate, rate ); + test_passed = 1; + break; + } else if (test_perf !=0 ) { + printf("[continue] effective rate : %f (%2.1f%%,%f)): increase snr \n",rate*effective_rate, 100*effective_rate, rate); + test_passed = 0; + } + + if (((double)errs[0]/(round_trials[0]))<(10.0/n_frames)) + break; + }// SNR + } //ch_realization + + fclose(bler_fd); + + if (test_perf !=0) + fclose (time_meas_fd); + + //fprintf(tikz_fd,"};\n"); + //fclose(tikz_fd); + + if (input_trch_file==1) + fclose(input_trch_fd); + + if (input_file==1) + fclose(input_fd); + + if(abstx) { // ABSTRACTION + fprintf(csv_fd,"];"); + fclose(csv_fd); + } + + if (uncoded_ber_bit) + free(uncoded_ber_bit); + + uncoded_ber_bit = NULL; + printf("Freeing dlsch structures\n"); + + for (i=0; i<2; i++) { + printf("eNB %d\n",i); + free_eNB_dlsch(eNB->dlsch[0][i]); + printf("UE %d\n",i); + free_ue_dlsch(UE->dlsch[UE->current_thread_id[subframe]][0][i]); + } + + if (test_perf && !test_passed) + return(-1); + else + return(0); +} +/* temporary dummy implem of get_softmodem_optmask, till basic simulators implemented as device */ +uint64_t get_softmodem_optmask(void) { + return 0; +} From f1d51cc0be02f9e2f8a8d2520ba9f510333bf560 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 18:08:41 +0200 Subject: [PATCH 23/70] fembms: handle L2 eNB config in softmodem Signed-off-by: Javier Morgade --- openair2/COMMON/m2ap_messages_def.h | 1 + openair2/COMMON/m2ap_messages_types.h | 11 ++++++++++- openair2/ENB_APP/enb_app.c | 25 ++++++++++--------------- openair2/ENB_APP/enb_config.c | 3 ++- 4 files changed, 23 insertions(+), 17 deletions(-) diff --git a/openair2/COMMON/m2ap_messages_def.h b/openair2/COMMON/m2ap_messages_def.h index adad70c9cc..743ca126fb 100644 --- a/openair2/COMMON/m2ap_messages_def.h +++ b/openair2/COMMON/m2ap_messages_def.h @@ -50,6 +50,7 @@ MESSAGE_DEF(M2AP_DEREGISTERED_ENB_IND , MESSAGE_PRIORITY_MED, m2ap_der /* M2AP -> SCTP */ MESSAGE_DEF(M2AP_MCE_SCTP_REQ , MESSAGE_PRIORITY_MED, m2ap_mce_sctp_req_t , m2ap_mce_sctp_req) +MESSAGE_DEF(M2AP_ENB_SCTP_REQ , MESSAGE_PRIORITY_MED, m2ap_enb_sctp_req_t , m2ap_enb_sctp_req) //MESSAGE_DEF(M2AP_ENB_SCTP_REQ , MESSAGE_PRIORITY_MED, m2ap_enb_setup_req_t , f1ap_enb_setup_req) /* eNB_DU application layer -> M2AP messages or CU M2AP -> RRC*/ diff --git a/openair2/COMMON/m2ap_messages_types.h b/openair2/COMMON/m2ap_messages_types.h index 501414f296..c70c50fc64 100644 --- a/openair2/COMMON/m2ap_messages_types.h +++ b/openair2/COMMON/m2ap_messages_types.h @@ -480,7 +480,7 @@ typedef struct m2ap_mbms_scheduling_information_s { uint8_t common_sf_allocation_period; uint8_t mbms_area_id; struct{ - uint8_t allocated_sf_end; + uint16_t allocated_sf_end; uint8_t data_mcs; uint8_t mch_scheduling_period; struct{ @@ -533,6 +533,15 @@ typedef struct m2ap_mce_sctp_req_s { uint32_t mce_port_for_M2C; }m2ap_mce_sctp_req_t; +typedef struct m2ap_enb_sctp_req_s { + /* The local MCE IP address to bind */ + net_ip_address_t enb_m2_ip_address; + + /* eNB port for M2C*/ + uint32_t enb_port_for_M2C; +}m2ap_enb_sctp_req_t; + + typedef struct m2ap_mbms_scheduling_information_resp_s { } m2ap_mbms_scheduling_information_resp_t; typedef struct m2ap_session_start_req_s { diff --git a/openair2/ENB_APP/enb_app.c b/openair2/ENB_APP/enb_app.c index 0e1c7e64bc..4b592f27cf 100644 --- a/openair2/ENB_APP/enb_app.c +++ b/openair2/ENB_APP/enb_app.c @@ -214,7 +214,7 @@ void *eNB_app_task(void *args_p) { long x2_enb_register_retry_timer_id; uint32_t m2_register_enb_pending = 0; uint32_t m2_registered_enb = 0; - long m2_enb_register_retry_timer_id; + //long m2_enb_register_retry_timer_id; MessageDef *msg_p = NULL; instance_t instance; int result; @@ -236,16 +236,11 @@ void *eNB_app_task(void *args_p) { /* Try to register each eNB with MCE each other */ if (is_m2ap_eNB_enabled() /*&& !NODE_IS_DU(RC.rrc[0]->node_type)*/) { //eNB_app_register_MBMS_STA(RC.rrc[0]->node_type, enb_id_start, enb_id_end); - //m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end); + m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end); - if (timer_setup (5, 0, TASK_ENB_APP, INSTANCE_DEFAULT, TIMER_ONE_SHOT, - NULL, &m2_enb_register_retry_timer_id) < 0) { - //LOG_E(ENB_APP, " Can not start eNB register retry timer, use \"sleep\" instead!\n"); - //sleep(ENB_REGISTER_RETRY_DELAY); - /* Restart the registration process */ - //registered_enb = 0; - //register_enb_pending = eNB_app_register (RC.rrc[0]->node_type,enb_id_start, enb_id_end); - } + //if (timer_setup (5, 0, TASK_ENB_APP, INSTANCE_DEFAULT, TIMER_ONE_SHOT, + // NULL, &m2_enb_register_retry_timer_id) < 0) { + //} } @@ -377,11 +372,11 @@ void *eNB_app_task(void *args_p) { } } /* if (EPC_MODE_ENABLED) */ - if(TIMER_HAS_EXPIRED (msg_p).timer_id == m2_enb_register_retry_timer_id) { - - LOG_I(ENB_APP, " Received %s: timer_id %ld M2 register\n", ITTI_MSG_NAME (msg_p), TIMER_HAS_EXPIRED(msg_p).timer_id); - m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end); - } +// if(TIMER_HAS_EXPIRED (msg_p).timer_id == m2_enb_register_retry_timer_id) { +// +// LOG_I(ENB_APP, " Received %s: timer_id %ld M2 register\n", ITTI_MSG_NAME (msg_p), TIMER_HAS_EXPIRED(msg_p).timer_id); +// m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end); +// } break; diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 6dcc574746..df8238bf25 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -3041,7 +3041,8 @@ void configure_du_mac(int inst) { (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } From 1f034ab40453d562f1e0abcde441bfb72d1f5d9d Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 18:10:25 +0200 Subject: [PATCH 24/70] fembms: prototype overload (legacy code for F1AP) Signed-off-by: Javier Morgade --- openair2/F1AP/f1ap_du_rrc_message_transfer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openair2/F1AP/f1ap_du_rrc_message_transfer.c b/openair2/F1AP/f1ap_du_rrc_message_transfer.c index fb9450728b..6953588818 100644 --- a/openair2/F1AP/f1ap_du_rrc_message_transfer.c +++ b/openair2/F1AP/f1ap_du_rrc_message_transfer.c @@ -306,7 +306,8 @@ int DU_handle_DL_RRC_MESSAGE_TRANSFER(instance_t instance, (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); break; } // case @@ -480,7 +481,8 @@ int DU_handle_DL_RRC_MESSAGE_TRANSFER(instance_t instance, (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } From e3cf9bcf1f473990d7e23fcd8cc34e0baccb765e Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 18:11:51 +0200 Subject: [PATCH 25/70] fembms: handle L2 eNB/UE config Signed-off-by: Javier Morgade --- openair2/LAYER2/MAC/config.c | 23 ++++++++++++++++++++--- openair2/LAYER2/MAC/config_ue.c | 1 + 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/MAC/config.c b/openair2/LAYER2/MAC/config.c index 49949bd771..781347abaa 100644 --- a/openair2/LAYER2/MAC/config.c +++ b/openair2/LAYER2/MAC/config.c @@ -660,7 +660,7 @@ config_sib2_mbsfn_part( int Mod_idP, if (mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) { phycfg.cfg->embms_mbsfn_config.fourframes_flag[i] = 0; phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i] = mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]; // 6-bit subframe configuration - LOG_I (MAC, "[CONFIG] MBSFN_SubframeConfig[%d] pattern is %d\n", i, phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i]); + LOG_I (MAC, "[CONFIG] MBSFN_SubframeConfig[%d] oneFrame pattern is %d\n", i, phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i]); } else if (mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames) { // 24-bit subframe configuration phycfg.cfg->embms_mbsfn_config.fourframes_flag[i] = 1; phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i] = @@ -668,7 +668,7 @@ config_sib2_mbsfn_part( int Mod_idP, (mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.choice.oneFrame.buf[1]<<8)| (mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]<<16); - LOG_I(MAC, "[CONFIG] MBSFN_SubframeConfig[%d] pattern is %x\n", i, + LOG_I(MAC, "[CONFIG] MBSFN_SubframeConfig[%d] fourFrame pattern is %x\n", i, phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i]); } } @@ -777,7 +777,8 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo_fembms, struct LTE_NonMBSFN_SubframeConfig_r14 *nonMBSFN_SubframeConfig, LTE_SystemInformationBlockType1_MBMS_r14_t *sib1_mbms_r14_fembms, - LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms + LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms, + LTE_MBSFNAreaConfiguration_r9_t*mbms_AreaConfig ) { int i; int UE_id = -1; @@ -989,6 +990,7 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, cfg->num_tlv++; //We need to reuse current MCH scheduler //TOCHECK whether we can simply reuse current mbsfn_SubframeConfig stuff + RC.mac[Mod_idP]->common_channels[0].FeMBMS_flag = FeMBMS_Flag; } if (mbsfn_AreaInfoList != NULL) { @@ -1005,6 +1007,21 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP, } } + if(mbms_AreaConfig != NULL) { + RC.mac[Mod_idP]->common_channels[0].commonSF_AllocPeriod_r9 = mbms_AreaConfig->commonSF_AllocPeriod_r9; + LOG_I(MAC, "[eNB %d][CONFIG] LTE_MBSFNAreaConfiguration_r9_t(%p) commonSF_AllocPeriod_r9(%d)\n",Mod_idP,mbms_AreaConfig, RC.mac[Mod_idP]->common_channels[0].commonSF_AllocPeriod_r9); + for(i=0; i < mbms_AreaConfig->commonSF_Alloc_r9.list.count; i++){ + RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i] = mbms_AreaConfig->commonSF_Alloc_r9.list.array[i]; + LOG_I(RRC,"[eNB %d][CONFIG] MBSFNArea[%d] commonSF_Alloc_r9: radioframeAllocationPeriod(%ldn),radioframeAllocationOffset(%ld), subframeAllocation(%x,%x,%x)\n" + ,Mod_idP,i + ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->radioframeAllocationPeriod + ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->radioframeAllocationOffset + ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->subframeAllocation.choice.oneFrame.buf[0] + ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->subframeAllocation.choice.oneFrame.buf[1] + ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->subframeAllocation.choice.oneFrame.buf[2]); + } + } + if (pmch_InfoList != NULL) { // LOG_I(MAC,"DUY: lcid when entering rrc_mac config_req is %02d\n",(pmch_InfoList->list.array[0]->mbms_SessionInfoList_r9.list.array[0]->logicalChannelIdentity_r9)); LOG_I(MAC, "[CONFIG] Number of PMCH in this MBSFN Area %d\n", diff --git a/openair2/LAYER2/MAC/config_ue.c b/openair2/LAYER2/MAC/config_ue.c index 897afbf62b..1c5e706218 100644 --- a/openair2/LAYER2/MAC/config_ue.c +++ b/openair2/LAYER2/MAC/config_ue.c @@ -530,6 +530,7 @@ rrc_mac_config_req_ue(module_id_t Mod_idP, LOG_I(MAC, "[UE %d] Configuring LTE_NonMBSFN \n", Mod_idP); phy_config_sib1_fembms_ue(Mod_idP, CC_idP, 0, nonMBSFN_SubframeConfig); + UE_mac_inst[Mod_idP].non_mbsfn_SubframeConfig = nonMBSFN_SubframeConfig; } VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME From 9b37dcecdb07fc90ef77674bdd48c78e68909068 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 18:14:44 +0200 Subject: [PATCH 26/70] fembms: handle MBMS in new RLC Signed-off-by: Javier Morgade --- openair2/LAYER2/RLC/rlc.c | 2 +- openair2/LAYER2/RLC/rlc_rrc.c | 3 ++- openair2/PHY_INTERFACE/phy_stub_UE.c | 32 +++++++++++++++++++++++++++- 3 files changed, 34 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/RLC/rlc.c b/openair2/LAYER2/RLC/rlc.c index 2fb844f05a..98c8c3e252 100644 --- a/openair2/LAYER2/RLC/rlc.c +++ b/openair2/LAYER2/RLC/rlc.c @@ -519,7 +519,7 @@ rlc_op_status_t rlc_data_req (const protocol_ctxt_t *const ctxt_pP, // LOG_I(RLC,"DUY rlc_data_req: mbms_rb_id in RLC instant is: %d\n", mbms_rb_id); if (sdu_pP != NULL) { if (sdu_sizeP > 0) { - LOG_I(RLC,"received a packet with size %d for MBMS \n", sdu_sizeP); + LOG_D(RLC,"received a packet with size %d for MBMS \n", sdu_sizeP); new_sdu_p = get_free_mem_block (sdu_sizeP + sizeof (struct rlc_um_data_req_alloc), __func__); if (new_sdu_p != NULL) { diff --git a/openair2/LAYER2/RLC/rlc_rrc.c b/openair2/LAYER2/RLC/rlc_rrc.c index 85ee4e0571..4313f379fe 100644 --- a/openair2/LAYER2/RLC/rlc_rrc.c +++ b/openair2/LAYER2/RLC/rlc_rrc.c @@ -640,7 +640,8 @@ rlc_union_t *rrc_rlc_add_rlc ( } else if (h_rc == HASH_TABLE_KEY_NOT_EXISTS) { rlc_union_p = calloc(1, sizeof(rlc_union_t)); h_rc = hashtable_insert(rlc_coll_p, key, rlc_union_p); - h_lcid_rc = hashtable_insert(rlc_coll_p, key_lcid, rlc_union_p); + if(MBMS_flagP != TRUE) + h_lcid_rc = hashtable_insert(rlc_coll_p, key_lcid, rlc_union_p); if ((h_rc == HASH_TABLE_OK) && (h_lcid_rc == HASH_TABLE_OK)) { if (MBMS_flagP == TRUE) { diff --git a/openair2/PHY_INTERFACE/phy_stub_UE.c b/openair2/PHY_INTERFACE/phy_stub_UE.c index 41fb3ddc3a..de42d67624 100644 --- a/openair2/PHY_INTERFACE/phy_stub_UE.c +++ b/openair2/PHY_INTERFACE/phy_stub_UE.c @@ -800,7 +800,37 @@ void dl_config_req_UE_MAC_dci(int sfn, UE_mac_inst[ue_id].first_ULSCH_Tx = 1; } } - } else { + } + //else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE) { + // // BCH case: Last parameter is 1 if first time synchronization and zero + // // otherwise. Not sure which value to put for our case. + // if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED){ + // dl_phy_sync_success(Mod_id, sfn, 0, 1); + // LOG_E(MAC, + // "%s(): Received MIB: UE_mode: %d, sfn/sf: %d.%d\n", + // __func__, + // UE_mac_inst[Mod_id].UE_mode[0], + // sfn, + // sf); + // UE_mac_inst[Mod_id].UE_mode[0] = PRACH; + // } else { + // dl_phy_sync_success(Mod_id, sfn, 0, 0); + // } + //} else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_MCH_PDU_TYPE){ + // if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED) { + // /* this check is in the code before refactoring, but I don't know + // * why. Leave it in here for the moment */ + // continue; + // } + // nfapi_dl_config_request_pdu_t *dl_config_pdu_tmp = &dl_config_pdu_list[i]; + // const int pdu_index = dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index; + // ue_send_mch_sdu(Mod_id, 0, sfn, + // tx_request_pdu_list[pdu_index].segments[0].segment_data, + // tx_request_pdu_list[pdu_index].segments[0].segment_length, + // 0,0); + + //} + else { LOG_W(MAC, "can not handle special RNTI %x\n", rnti); } } From 3aaa152e4e34f84a264e369f50457c83d4a20d80 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 18:16:46 +0200 Subject: [PATCH 27/70] fembms: new FeMBMS/eMBMS MCH eNB/UE scheduler implemented - MBMS scheduler re-worked to enable dedicated MBMS serving cells - added support for multiple eMBMS MCH sessions - added support for multiple FeMBMS MCH sessions Signed-off-by: Javier Morgade --- openair2/LAYER2/MAC/eNB_scheduler.c | 21 +- openair2/LAYER2/MAC/eNB_scheduler_bch.c | 59 + openair2/LAYER2/MAC/eNB_scheduler_mch.c | 1249 ++++++++++++---------- openair2/LAYER2/MAC/mac.h | 9 +- openair2/LAYER2/MAC/mac_proto.h | 18 +- openair2/LAYER2/MAC/ue_procedures.c | 610 ++++++++++- openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c | 2 +- 7 files changed, 1388 insertions(+), 580 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index c46005ee2d..c36bd0d56a 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -904,6 +904,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, } #endif + int do_fembms_si=0; for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { if (cc[CC_id].MBMS_flag > 0) { start_meas(&RC.mac[module_idP]->schedule_mch); @@ -914,6 +915,10 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, } stop_meas(&RC.mac[module_idP]->schedule_mch); } + if (cc[CC_id].FeMBMS_flag > 0) { + do_fembms_si = 1; + } + } static int debug_flag = 0; @@ -935,12 +940,22 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, } /* This schedules MIB */ - if ((subframeP == 0) && (frameP & 3) == 0) - schedule_mib(module_idP, frameP, subframeP); + if(!do_fembms_si/*get_softmodem_params()->fembms*/){ + if ((subframeP == 0) && (frameP & 3) == 0) + schedule_mib(module_idP, frameP, subframeP); + }else{ + if ((subframeP == 0) && (frameP & 15) == 0 ){ + schedule_fembms_mib(module_idP, frameP, subframeP); + //schedule_SI_MBMS(module_idP, frameP, subframeP); + } + } if (get_softmodem_params()->phy_test == 0) { /* This schedules SI for legacy LTE and eMTC starting in subframeP */ - schedule_SI(module_idP, frameP, subframeP); + if(!do_fembms_si/*get_softmodem_params()->fembms*/) + schedule_SI(module_idP, frameP, subframeP); + else + schedule_SI_MBMS(module_idP, frameP, subframeP); /* This schedules Paging in subframeP */ schedule_PCH(module_idP,frameP,subframeP); /* This schedules Random-Access for legacy LTE and eMTC starting in subframeP */ diff --git a/openair2/LAYER2/MAC/eNB_scheduler_bch.c b/openair2/LAYER2/MAC/eNB_scheduler_bch.c index 5b99578d57..e4b9a7a65b 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_bch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_bch.c @@ -731,6 +731,7 @@ schedule_SI_MBMS(module_id_t module_idP, frame_t frameP, if (subframeP == 0) { for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { cc = &eNB->common_channels[CC_id]; + //printf("*cc->sib1_MBMS->si_WindowLength_r14 %d \n", *cc->sib1_MBMS->si_WindowLength_r14); vrb_map = (void *) &cc->vrb_map; N_RB_DL = to_prb(cc->mib->message.dl_Bandwidth); dl_config_request = &eNB->DL_req[CC_id]; @@ -911,6 +912,64 @@ schedule_SI_MBMS(module_id_t module_idP, frame_t frameP, stop_meas(&eNB->schedule_si_mbms); } +void +schedule_fembms_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { + eNB_MAC_INST *eNB = RC.mac[module_idP]; + COMMON_channels_t *cc; + nfapi_dl_config_request_pdu_t *dl_config_pdu; + nfapi_tx_request_pdu_t *TX_req; + int mib_sdu_length; + int CC_id; + nfapi_dl_config_request_t *dl_config_request; + nfapi_dl_config_request_body_t *dl_req; + uint16_t sfn_sf = frameP << 4 | subframeP; + AssertFatal(subframeP == 0, "Subframe must be 0\n"); + AssertFatal((frameP & 15) == 0, "Frame must be a multiple of 16\n"); + + for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { + dl_config_request = &eNB->DL_req[CC_id]; + dl_req = &dl_config_request->dl_config_request_body; + cc = &eNB->common_channels[CC_id]; + mib_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MIBCH_MBMS, 0xFFFF, 1, &cc->MIB_pdu.payload[0], 0); // not used in this case + LOG_D(MAC, "Frame %d, subframe %d: BCH PDU length %d\n", frameP, subframeP, mib_sdu_length); + + if (mib_sdu_length > 0) { + LOG_D(MAC, "Frame %d, subframe %d: Adding BCH PDU in position %d (length %d)\n", frameP, subframeP, dl_req->number_pdu, mib_sdu_length); + + if ((frameP & 1023) < 40) + LOG_D(MAC, + "[eNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes (cc->mib->message.schedulingInfoSIB1_BR_r13 %d)\n", + module_idP, frameP, CC_id, mib_sdu_length, + (int) cc->mib->message.schedulingInfoSIB1_BR_r13); + + dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; + memset((void *) dl_config_pdu, 0, + sizeof(nfapi_dl_config_request_pdu_t)); + dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_BCH_PDU_TYPE, dl_config_pdu->pdu_size = + 2 + sizeof(nfapi_dl_config_bch_pdu); + dl_config_pdu->bch_pdu.bch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_BCH_PDU_REL8_TAG; + dl_config_pdu->bch_pdu.bch_pdu_rel8.length = mib_sdu_length; + dl_config_pdu->bch_pdu.bch_pdu_rel8.pdu_index = eNB->pdu_index[CC_id]; + dl_config_pdu->bch_pdu.bch_pdu_rel8.transmission_power = 6000; + dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + dl_req->number_pdu++; + dl_config_request->header.message_id = NFAPI_DL_CONFIG_REQUEST; + dl_config_request->sfn_sf = sfn_sf; + LOG_D(MAC, "eNB->DL_req[0].number_pdu %d (%p)\n", dl_req->number_pdu, &dl_req->number_pdu); + // DL request + TX_req = &eNB->TX_req[CC_id].tx_request_body.tx_pdu_list[eNB->TX_req[CC_id].tx_request_body.number_of_pdus]; + TX_req->pdu_length = 3; + TX_req->pdu_index = eNB->pdu_index[CC_id]++; + TX_req->num_segments = 1; + TX_req->segments[0].segment_length = 3; + TX_req->segments[0].segment_data = cc[CC_id].MIB_pdu.payload; + eNB->TX_req[CC_id].tx_request_body.number_of_pdus++; + eNB->TX_req[CC_id].sfn_sf = sfn_sf; + eNB->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; + eNB->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + } + } +} void schedule_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { diff --git a/openair2/LAYER2/MAC/eNB_scheduler_mch.c b/openair2/LAYER2/MAC/eNB_scheduler_mch.c index eb5d78fd3f..cb90419d43 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_mch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_mch.c @@ -66,7 +66,11 @@ get_mbsfn_sf_alloction(module_id_t module_idP, uint8_t CC_id, "[eNB %d] CC_id %d MBSFN synchronization area %d out of range\n ", module_idP, CC_id, mbsfn_sync_area); return -1; - } else if (RC.mac[module_idP]-> + }else if (RC.mac[module_idP]-> + common_channels[CC_id].non_mbsfn_SubframeConfig + != NULL) { + return mbsfn_sync_area; + }else if (RC.mac[module_idP]-> common_channels[CC_id].mbsfn_SubframeConfig[mbsfn_sync_area] != NULL) { return mbsfn_sync_area; @@ -80,14 +84,30 @@ get_mbsfn_sf_alloction(module_id_t module_idP, uint8_t CC_id, static uint32_t bytes_in_buffer=0; static uint32_t msi_pmch_stop=0; -//static uint8_t msi_active=0; -//static uint8_t msi_pmch_stop2=0; -uint16_t mbms_rab_id = 2047; +uint16_t mbms_rab_id=2047;//[8] = {2047,2047,2047,2047,2047,2047,2047,2047}; static uint32_t msi_sfs=0; //MSI_ELEMENT * ptr =NULL; +static int check_CAS_sf(frame_t frameP,sub_frame_t subframeP){ + if( ((frameP&3)==0) && (subframeP == 0)) + return 1; + else + return 0; +} +static int check_nonMBSFN_sf(frame_t frameP,COMMON_channels_t *cc,int sf){ + uint32_t non_mbsfn_SubframeConfig = (cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7); + if( frameP % (4<non_mbsfn_SubframeConfig->radioFrameAllocationPeriod_r14) == cc->non_mbsfn_SubframeConfig->radioFrameAllocationOffset_r14 ){ + return (non_mbsfn_SubframeConfig & (0x200>>(sf)))==(0x200 >> (sf)); + } + return 0; +} + + +static int x=0; +static int mbms_mch_i=0; + int schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_frame_t subframeP) @@ -99,29 +119,28 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, int mcch_flag = 0, mtch_flag = 0, msi_flag = 0; int mbsfn_period = 0; // 1<<(RC.mac[module_idP]->mbsfn_SubframeConfig[0]->radioframeAllocationPeriod); int mcch_period = 0; //32<<(RC.mac[module_idP]->mbsfn_AreaInfo[0]->mcch_Config_r9.mcch_RepetitionPeriod_r9); + //TOCHECK mtch index here if(RC.mac[module_idP]->common_channels[CC_id]. pmch_Config[0] == NULL ) - return 0; - - - + //TOCHECK mtch index here int mch_scheduling_period = 8 << (RC.mac[module_idP]->common_channels[CC_id]. pmch_Config[0]->mch_SchedulingPeriod_r9); + unsigned char mcch_sdu_length; unsigned char header_len_mcch = 0, header_len_msi = 0, header_len_mtch = 0, header_len_mtch_temp = 0, header_len_mcch_temp = 0, header_len_msi_temp = 0; - int ii = 0, msi_pos = 0; + int ii = 0, msi_pos = -1; int mcch_mcs = -1; + int shifted_sf = 0; uint16_t TBS, j = -1, padding = 0, post_padding = 0; mac_rlc_status_resp_t rlc_status; - //mac_rlc_status_resp_t rlc_status2; - int num_mtch; + int num_mtch=0; int msi_length=0, i, k; - //uint8_t l =0; + unsigned char sdu_lcids[11], num_sdus = 0, offset = 0; uint16_t sdu_lengths[11], sdu_length_total = 0; unsigned char mch_buffer[MAX_DLSCH_PAYLOAD_BYTES]; // check the max value, this is for dlsch only @@ -136,358 +155,535 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, return 0; } - mbsfn_period = - 1 << (cc->mbsfn_SubframeConfig[j]->radioframeAllocationPeriod); - mcch_period = - 32 << (cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_RepetitionPeriod_r9); - msi_pos = 0; - ii = 0; - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d subframeP %d : Checking MBSFN Sync Area %d/%d with SF allocation %d/%d for MCCH and MTCH (mbsfn period %d, mcch period %d)\n", - module_idP, CC_id, frameP, subframeP, i, - cc->num_active_mbsfn_area, j, cc->num_sf_allocation_pattern, - mbsfn_period, mcch_period); + if(cc->non_mbsfn_SubframeConfig){ + int alloc_offset=0; + uint32_t period; + uint32_t non_mbsfn_SubframeConfig = (cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7); + long mcch_offset = cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9; - switch (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) { - case 0: - mcch_mcs = 2; - break; + period = 4<non_mbsfn_SubframeConfig->radioFrameAllocationPeriod_r14; + alloc_offset = cc->non_mbsfn_SubframeConfig->radioFrameAllocationOffset_r14; + mcch_period = 32 << cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_RepetitionPeriod_r9; + + // get the real MCS value + switch (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) { + case 0: + mcch_mcs = 2; + break; - case 1: - mcch_mcs = 7; - break; + case 1: + mcch_mcs = 7; + break; - case 2: - mcch_mcs = 13; - break; + case 2: + mcch_mcs = 13; + break; - case 3: - mcch_mcs = 19; - break; - } + case 3: + mcch_mcs = 19; + break; + } + + if (cc->pmch_Config[0]) { + mch_scheduling_period = 8 << cc->pmch_Config[0]->mch_SchedulingPeriod_r9; + } - // 1st: Check the MBSFN subframes from SIB2 info (SF allocation pattern i, max 8 non-overlapping patterns exist) - if (frameP % mbsfn_period == cc->mbsfn_SubframeConfig[j]->radioframeAllocationOffset) { // MBSFN frameP - if (cc->mbsfn_SubframeConfig[j]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) { // one-frameP format - - // Find the first subframeP in this MCH to transmit MSI - if (frameP % mch_scheduling_period == - cc->mbsfn_SubframeConfig[j]-> - radioframeAllocationOffset) { - while (ii == 0) { - ii = cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & (0x80 >> msi_pos); + LOG_D(MAC,"frameP %d subframe %d period %d alloc_offset %d mcch_mcs %d mcch_period %d mcch_offset %ld buf %x mch_scheduling_period %d\n",frameP, subframeP, period, alloc_offset,mcch_mcs, mcch_period, mcch_offset,(cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0]),mch_scheduling_period); + //if( (frameP % (4 << cc->commonSF_AllocPeriod_r9) ) == 0 ){ + // if((subframeP==0)){ + // x=0; + // mbms_mch_i=0; + // } + //} + //if (frameP % (4 << cc->commonSF_AllocPeriod_r9 ) == 0) { + // if((subframeP==0)){ + // x=0; + // mbms_mch_i=0; + // } + //} + if (cc->pmch_Config[0]) { + // Find the first subframe in this MCH to transmit MSI + if (frameP % 1 == 0) { + if (frameP % mch_scheduling_period == 0) { + msi_pos=0; + if((frameP&3)==0) msi_pos++; - } + while((non_mbsfn_SubframeConfig & (0x100 >> msi_pos)) == (0x100>>msi_pos)) + msi_pos++; + mbms_mch_i=0; - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d subframeP %d : sync area %d sf allocation pattern %d sf alloc %x msi pos is %d \n", - module_idP, CC_id, frameP, subframeP, i, j, - cc->mbsfn_SubframeConfig[j]-> - subframeAllocation.choice.oneFrame.buf[0], - msi_pos); + if((subframeP==0)){ + x=0; + mbms_mch_i=0; + } + } - // Check if the subframeP is for MSI, MCCH or MTCHs and Set the correspoding flag to 1 - switch (subframeP) { - case 1: - if (cc->tdd_Config == NULL) { - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == - MBSFN_FDD_SF1) { - if (msi_pos == 1) { - msi_flag = 1; - } + } + } - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_FDD_SF1) == - MBSFN_FDD_SF1)) { - mcch_flag = 1; - } + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9+shifted_sf){ - mtch_flag = 1; - } - } - - break; - - case 2: - if (cc->tdd_Config == NULL) { - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == - MBSFN_FDD_SF2) { - if (msi_pos == 2) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_FDD_SF2) == - MBSFN_FDD_SF2)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - - case 3: - if (cc->tdd_Config != NULL) { // TDD - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_TDD_SF3) == - MBSFN_TDD_SF3) { - if (msi_pos == 1) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_TDD_SF3) == - MBSFN_TDD_SF3)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } else { // FDD - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_FDD_SF3) == - MBSFN_FDD_SF3) { - if (msi_pos == 3) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_FDD_SF3) == - MBSFN_FDD_SF3)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - - case 4: - if (cc->tdd_Config != NULL) { - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_TDD_SF4) == - MBSFN_TDD_SF4) { - if (msi_pos == 2) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_TDD_SF4) == - MBSFN_TDD_SF4)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - - case 6: - if (cc->tdd_Config == NULL) { - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == - MBSFN_FDD_SF6) { - if (msi_pos == 4) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_FDD_SF6) == - MBSFN_FDD_SF6)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - - case 7: - if (cc->tdd_Config != NULL) { // TDD - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_TDD_SF7) == - MBSFN_TDD_SF7) { - if (msi_pos == 3) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_TDD_SF7) == - MBSFN_TDD_SF7)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } else { // FDD - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_FDD_SF7) == - MBSFN_FDD_SF7) { - if (msi_pos == 5) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_FDD_SF7) == - MBSFN_FDD_SF7)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - - case 8: - if (cc->tdd_Config != NULL) { //TDD - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_TDD_SF8) == - MBSFN_TDD_SF8) { - if (msi_pos == 4) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_TDD_SF8) == - MBSFN_TDD_SF8)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } else { // FDD - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_FDD_SF8) == - MBSFN_FDD_SF8) { - if (msi_pos == 6) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_FDD_SF8) == - MBSFN_FDD_SF8)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - - case 9: - if (cc->tdd_Config != NULL) { - if ((cc-> - mbsfn_SubframeConfig[j]->subframeAllocation. - choice.oneFrame.buf[0] & MBSFN_TDD_SF9) == - MBSFN_TDD_SF9) { - if (msi_pos == 5) { - msi_flag = 1; - } - - if ((frameP % mcch_period == - cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.mcch_Offset_r9) - && - ((cc->mbsfn_AreaInfo[i]-> - mcch_Config_r9.sf_AllocInfo_r9. - buf[0] & MBSFN_TDD_SF9) == - MBSFN_TDD_SF9)) { - mcch_flag = 1; - } - - mtch_flag = 1; - } - } - - break; - } // end switch - - // sf allocation is non-overlapping - if ((msi_flag == 1) || (mcch_flag == 1) - || (mtch_flag == 1)) { - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n", - module_idP, CC_id, frameP, subframeP, i, j, - msi_flag, mcch_flag, mtch_flag); - break; + shifted_sf = check_nonMBSFN_sf(frameP,cc,subframeP)+check_CAS_sf(frameP,subframeP); + msi_pos=subframeP+shifted_sf; + if(shifted_sf==0) + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d shifted_sf %d\n",frameP, subframeP, msi_pos,mbms_mch_i,shifted_sf); } - } else { // four-frameP format } - } - } // end of for loop + + // Check if the subframe is for MSI, MCCH or MTCHs and Set the correspoding flag to 1 + switch (subframeP) { + case 0: + if (msi_pos == 0) { + msi_flag = 1; + } + mtch_flag = 1; + break; + case 1: + if (msi_pos == 1) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1)) { + mcch_flag = 1; + } + mtch_flag = 1; + break; + + case 2: + if (msi_pos == 2) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2)) { + mcch_flag = 1; + } + mtch_flag = 1; + + break; + + case 3: + if (msi_pos == 3) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3)) { + mcch_flag = 1; + } + mtch_flag = 1; + break; + + case 4: + if (msi_pos == 4) { + msi_flag = 1; + } + mtch_flag = 1; + break; + + case 5: + if (msi_pos == 5) { + msi_flag = 1; + } + mtch_flag = 1; + break; + + case 6: + if (msi_pos == 6) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6)) { + mcch_flag = 1; + } + mtch_flag = 1; + break; + + case 7: + if (msi_pos == 7) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7)) { + mcch_flag = 1; + } + mtch_flag = 1; + break; + + case 8: + if (msi_pos == 8) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8)) { + mcch_flag = 1; + } + mtch_flag = 1; + break; + + case 9: + if (msi_pos == 9) { + msi_flag = 1; + } + mtch_flag = 1; + break; + }// end switch + + if ((msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1)) { + LOG_D(MAC, + "[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n", + module_idP, CC_id, frameP, subframeP, i, j, + msi_flag, mcch_flag, mtch_flag); + } + + //TODO quitar la subframe 0 del otro switch ... está mal interpretado ? + // if((frameP&3) == 0){ + // mtch_flag=0;mcch_flag=0;msi_flag=0; + // } + + if((frameP % period ) == alloc_offset){ + LOG_D(MAC,"non_mbsfn_SubframeConfig %x\n",non_mbsfn_SubframeConfig); + switch(subframeP){ + case 0:{ + mtch_flag=0;mcch_flag=0;msi_flag=0; + } + break; + case 1:{ + if ((non_mbsfn_SubframeConfig & 0x100) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 2:{ + if ((non_mbsfn_SubframeConfig & 0x80) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 3:{ + if ((non_mbsfn_SubframeConfig & 0x40) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 4:{ + if ((non_mbsfn_SubframeConfig & 0x20) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 5:{ + if ((non_mbsfn_SubframeConfig & 0x10) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 6:{ + if ((non_mbsfn_SubframeConfig & 0x8) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 7:{ + if ((non_mbsfn_SubframeConfig & 0x4) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 8:{ + if ((non_mbsfn_SubframeConfig & 0x2) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + case 9:{ + if ((non_mbsfn_SubframeConfig & 0x1) > 0) + {mtch_flag=0;mcch_flag=0;msi_flag=0;} + } + break; + } + } + // sf allocation is non-overlapping + if ((msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1)) { + x++; + //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){ + //x++; + //} + + if(msi_flag==1){ + if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %( 4 << cc->commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 << cc->pmch_Config[mbms_mch_i]->mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){ + msi_flag=0; + LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframeP, mbms_mch_i); + } + + } + + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d, x %d\n", + module_idP, CC_id, frameP, subframeP, i, j, + msi_flag, mcch_flag, mtch_flag,x); + break; + } + + + }else if(cc->mbsfn_SubframeConfig[j]){ + + mbsfn_period = + 1 << (cc->mbsfn_SubframeConfig[j]->radioframeAllocationPeriod); + mcch_period = + 32 << (cc->mbsfn_AreaInfo[i]-> + mcch_Config_r9.mcch_RepetitionPeriod_r9); + msi_pos = 0; + ii = 0; + LOG_D(MAC, "[eNB %d] CC_id %d Frame %d subframeP %d : Checking MBSFN Sync Area %d/%d with SF allocation %d/%d for MCCH and MTCH (mbsfn period %d, mcch period %d)\n", + module_idP, CC_id, frameP, subframeP, i, + cc->num_active_mbsfn_area, j, cc->num_sf_allocation_pattern, + mbsfn_period, mcch_period); + + switch (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) { + case 0: + mcch_mcs = 2; + break; + + case 1: + mcch_mcs = 7; + break; + + case 2: + mcch_mcs = 13; + break; + + case 3: + mcch_mcs = 19; + break; + } + + // 1st: Check the MBSFN subframes from SIB2 info (SF allocation pattern i, max 8 non-overlapping patterns exist) + if (frameP % mbsfn_period == cc->mbsfn_SubframeConfig[j]->radioframeAllocationOffset) { // MBSFN frameP + if (cc->mbsfn_SubframeConfig[j]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) { // one-frameP format + // Find the first subframeP in this MCH to transmit MSI + if (frameP % mch_scheduling_period == cc->mbsfn_SubframeConfig[j]->radioframeAllocationOffset) { + while (ii == 0) { + ii = cc-> + mbsfn_SubframeConfig[j]->subframeAllocation. + choice.oneFrame.buf[0] & (0x80 >> msi_pos); + msi_pos++; + } + LOG_D(MAC, "[eNB %d] CC_id %d Frame %d subframeP %d : sync area %d sf allocation pattern %d sf alloc %x msi pos is %d \n", + module_idP, CC_id, frameP, subframeP, i, j, + cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0], + msi_pos); + if((subframeP==1)){ + x=0; + mbms_mch_i=0; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + + // Check if the subframeP is for MSI, MCCH or MTCHs and Set the correspoding flag to 1 + switch (subframeP) { + case 1: + if (cc->tdd_Config == NULL) { + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) { + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=1; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 1) { + msi_flag = 1; + } + if ( (frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + && ( (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) ) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 2: + if (cc->tdd_Config == NULL) { + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2) { + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=2; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + + if (msi_pos == 2) { + msi_flag = 1; + } + if ( (frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 3: + if (cc->tdd_Config != NULL) { + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF3) == MBSFN_TDD_SF3) { + if (msi_pos == 1) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF3) == MBSFN_TDD_SF3)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } else { // FDD + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3) { + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=3; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 3) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 4: + if (cc->tdd_Config != NULL) { + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF4) == MBSFN_TDD_SF4) { + if (msi_pos == 2) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF4) == MBSFN_TDD_SF4)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 6: + if (cc->tdd_Config == NULL) { + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6) { + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=4; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 4) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 7: + if (cc->tdd_Config != NULL) { // TDD + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF7) == MBSFN_TDD_SF7) { + if (msi_pos == 3) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF7) == MBSFN_TDD_SF7)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } else { // FDD + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7) { + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=5; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + + if (msi_pos == 5) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 8: + if (cc->tdd_Config != NULL) { //TDD + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF8) == MBSFN_TDD_SF8) { + if (msi_pos == 4) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF8) == MBSFN_TDD_SF8)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } else { // FDD + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8) { + if(cc->pmch_Config[mbms_mch_i+1]!=NULL){ + if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=6; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 6) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + case 9: + if (cc->tdd_Config != NULL) { + if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF9) == MBSFN_TDD_SF9) { + if (msi_pos == 5) { + msi_flag = 1; + } + if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9) + &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF9) == MBSFN_TDD_SF9)) { + mcch_flag = 1; + } + mtch_flag = 1; + } + } + break; + } // end switch + // sf allocation is non-overlapping + if ((msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1)) { + x++; + //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){ + //x++; + //} + if(msi_flag==1){ + if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %( 4 << cc->commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 << cc->pmch_Config[mbms_mch_i]->mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){ + msi_flag=0; + LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframeP, mbms_mch_i); + } + + } + + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d x %d\n", + module_idP, CC_id, frameP, subframeP, i, j, + msi_flag, mcch_flag, mtch_flag,x); + break; + } + } else {// four-frameP format + printf("Hola\n"); + AssertFatal(1==0,"four-frameP format: not implemented yet\n"); + } + } + } // MBMS format + }// end of for loop cc->msi_active = 0; cc->mcch_active = 0; @@ -497,7 +693,7 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, if ((msi_flag == 1) || (mcch_flag == 1)) { cc->MCH_pdu.mcs = mcch_mcs; } else if (mtch_flag == 1) { // only MTCH in this subframeP - cc->MCH_pdu.mcs = cc->pmch_Config[0]->dataMCS_r9; + cc->MCH_pdu.mcs = cc->pmch_Config[mbms_mch_i]->dataMCS_r9; } @@ -510,26 +706,14 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, // there is MSI (MCH Scheduling Info) uint16_t msi_control_element[29], *msi_ptr; + // MSI buffer pointer char *buffer_pointer=NULL; if (msi_flag == 1) { // Create MSI here - //uint16_t msi_control_element[29], *msi_ptr; - msi_ptr = &msi_control_element[0]; - //((MSI_ELEMENT *) msi_ptr)->lcid = MCCH_LCHANID; //MCCH - - //if (mcch_flag == 1) { - // ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0; - // ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0; - //} else { // no mcch for this MSP - // ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // stop value is 2047 - // ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xff; - //} - - //msi_ptr += sizeof(MSI_ELEMENT); //Header for MTCHs - num_mtch = cc->mbms_SessionList[0]->list.count; + num_mtch = cc->mbms_SessionList[mbms_mch_i]->list.count; TBS = get_TBS_DL(cc->MCH_pdu.mcs, to_prb(cc->mib->message.dl_Bandwidth)); @@ -537,7 +721,7 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, for (k = 0; k < num_mtch; k++) { // loop for all session in this MCH (MCH[0]) at this moment - ((MSI_ELEMENT *) msi_ptr)->lcid = cc->mbms_SessionList[0]->list.array[k]->logicalChannelIdentity_r9; //mtch_lcid; + ((MSI_ELEMENT *) msi_ptr)->lcid = cc->mbms_SessionList[mbms_mch_i]->list.array[k]->logicalChannelIdentity_r9; //mtch_lcid; if( msi_sfs != 0 ) msi_pmch_stop = msi_sfs-1; @@ -546,22 +730,15 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, msi_pmch_stop = msi_sfs; - //if( msi_pmch_stop > cc->pmch_Config[0]->sf_AllocEnd_r9) - //LOG_W(MAC,"e-MBMS Buffer Overflow\n"); - if(msi_pmch_stop>=num_sf_alloc /*&& msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9*/) { - ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0; // last subframeP of this mtch (only one mtch now) & stop_sf limited to 256 - //((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = msi_pmch_stop; - ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9); - msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9); + ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = (((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) >> 8) & 0x7f); + ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = ((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) & 0xff); + msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9); }else{ ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // last subframeP of this mtch (only one mtch now) ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF; msi_pmch_stop=0; } - - - msi_ptr += sizeof(MSI_ELEMENT); } @@ -573,15 +750,11 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, header_len_msi = 3; } - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d : MSI->MCH, length of MSI is %d bytes TBS %d, bytes in buffer %d stop_sf_LSB %d msi_sfs %d cc->pmch_Config[0]->sf_AllocEnd_r9 %ld\n", - module_idP, CC_id, frameP, msi_length,TBS, bytes_in_buffer,msi_pmch_stop,msi_sfs,cc->pmch_Config[0]->sf_AllocEnd_r9); + LOG_D(MAC, "[eNB %d] CC_id %d Frame %d : MSI->MCH, length of MSI is %d bytes TBS %d, bytes in buffer %d stop_sf_LSB %d msi_sfs %d cc->pmch_Config[0]->sf_AllocEnd_r9 %ld\n", + module_idP, CC_id, frameP, msi_length,TBS, bytes_in_buffer,msi_pmch_stop,msi_sfs,cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9); msi_sfs = 0; - //LOG_D(MAC,"Scheduler: MSI is transmitted in this subframeP \n" ); - - // LOG_D(MAC,"Scheduler: MSI length is %d bytes\n",msi_length); // Store MSI data to mch_buffer[0] memcpy((char *) &mch_buffer[sdu_length_total], msi_control_element, msi_length); @@ -598,75 +771,93 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, } // there is MCCH if (mcch_flag == 1) { + //MCCH scheduling if !FeMBMS + if(!cc->non_mbsfn_SubframeConfig){ + mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH_COUNTING, 0xFFFC, 1, &cc->MCCH_pdu.payload[0], + i); // this is the mbsfn sync area index + if(mcch_sdu_length>0) + LOG_I(MAC, "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE COUNTING (area %d, sfAlloc %d)\n", + module_idP, CC_id, frameP, subframeP, i, j); - //LOG_E(MAC, - //"[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE COUNTING (mod %d)\n",module_idP, CC_id, frameP, subframeP,frameP%2==0); - if(1/*frameP%2==0*/){ - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE (area %d, sfAlloc %d)\n", - module_idP, CC_id, frameP, subframeP, i, j); + if (mcch_sdu_length > 0) { + mcch_sdu_length+=1; //RLC ? + LOG_D(MAC, "[eNB %d] CC_id %d Frame %d subframeP %d : MCCH->MCH, Received %d bytes from RRC \n", + module_idP, CC_id, frameP, subframeP, mcch_sdu_length); - mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH, 0xFFFC, 1, &cc->MCCH_pdu.payload[0], - i); // this is the mbsfn sync area index - } - else{ - LOG_E(MAC, - "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE COUNTING (area %d, sfAlloc %d)\n", - module_idP, CC_id, frameP, subframeP, i, j); + header_len_mcch = 2; -// -// mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH_COUNTING, 0xFFFC, 1, &cc->MCCH_pdu.payload[0], -// i); // this is the mbsfn sync area index + if (cc->tdd_Config != NULL) { + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n", + module_idP, CC_id, frameP, subframeP, + mcch_sdu_length, mcch_mcs); + } else { + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (FDD) for MCCH message %d bytes (mcs %d)\n", + module_idP, CC_id, frameP, subframeP, + mcch_sdu_length, mcch_mcs); + } + + cc->mcch_active = 1; + + memcpy((char *) &mch_buffer[sdu_length_total]+1, + &cc->MCCH_pdu.payload[0], mcch_sdu_length); + sdu_lcids[num_sdus] = MCCH_LCHANID; + sdu_lengths[num_sdus] = mcch_sdu_length; + + if (sdu_lengths[num_sdus] > 128) { + header_len_mcch = 3; + } + + sdu_length_total += sdu_lengths[num_sdus]; + LOG_D(MAC, + "[eNB %d] CC_id %d Got %d bytes for MCCH from RRC \n", + module_idP, CC_id, sdu_lengths[num_sdus]); + num_sdus++; + } } - mcch_sdu_length+=1; //RLC ? + //MCCH scheduling ... do it anyway + { + LOG_I(MAC, "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE (area %d, sfAlloc %d)\n", + module_idP, CC_id, frameP, subframeP, i, j); - if (mcch_sdu_length > 0) { - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d subframeP %d : MCCH->MCH, Received %d bytes from RRC \n", - module_idP, CC_id, frameP, subframeP, mcch_sdu_length); + mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH, 0xFFFC, 1, &cc->MCCH_pdu.payload[0], + i); // this is the mbsfn sync area index - header_len_mcch = 2; + if (mcch_sdu_length > 0) { + mcch_sdu_length+=1; //RLC ? + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d : MCCH->MCH, Received %d bytes from RRC \n", + module_idP, CC_id, frameP, subframeP, mcch_sdu_length); - if (cc->tdd_Config != NULL) { - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n", - module_idP, CC_id, frameP, subframeP, - mcch_sdu_length, mcch_mcs); - } else { - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (FDD) for MCCH message %d bytes (mcs %d)\n", - module_idP, CC_id, frameP, subframeP, - mcch_sdu_length, mcch_mcs); + header_len_mcch = 2; + + if (cc->tdd_Config != NULL) { + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n", + module_idP, CC_id, frameP, subframeP, + mcch_sdu_length, mcch_mcs); + } else { + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (FDD) for MCCH message %d bytes (mcs %d)\n", + module_idP, CC_id, frameP, subframeP, + mcch_sdu_length, mcch_mcs); + } + + cc->mcch_active = 1; + + memcpy((char *) &mch_buffer[sdu_length_total]+1, + &cc->MCCH_pdu.payload[0], mcch_sdu_length); + sdu_lcids[num_sdus] = MCCH_LCHANID; + sdu_lengths[num_sdus] = mcch_sdu_length; + + if (sdu_lengths[num_sdus] > 128) { + header_len_mcch = 3; + } + + sdu_length_total += sdu_lengths[num_sdus]; + LOG_D(MAC,"[eNB %d] CC_id %d Got %d bytes for MCCH from RRC \n", + module_idP, CC_id, sdu_lengths[num_sdus]); + num_sdus++; } - - cc->mcch_active = 1; - - memcpy((char *) &mch_buffer[sdu_length_total]+1, - &cc->MCCH_pdu.payload[0], mcch_sdu_length); - sdu_lcids[num_sdus] = MCCH_LCHANID; - sdu_lengths[num_sdus] = mcch_sdu_length; - - // LOG_W(MAC,"MCCH RLC %x:",(unsigned char)mch_buffer[sdu_length_total]); - // for (int kk = 7; kk >= 0; kk--) - // { - // printf("%d",(((unsigned char)mch_buffer[sdu_length_total]) >> kk) & 1 ? '1' : '0'); - // } - // printf("\n"); - //mch_buffer[sdu_length_total] = (unsigned char)0; - - - if (sdu_lengths[num_sdus] > 128) { - header_len_mcch = 3; - } - - sdu_length_total += sdu_lengths[num_sdus]; - LOG_D(MAC, - "[eNB %d] CC_id %d Got %d bytes for MCCH from RRC \n", - module_idP, CC_id, sdu_lengths[num_sdus]); - num_sdus++; } - } + }// mcch_flag TBS = @@ -678,154 +869,108 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, // there is MTCHs, loop if there are more than 1 if (mtch_flag == 1 ) { // Calculate TBS - /* if ((msi_flag==1) || (mcch_flag==1)) { - TBS = mac_xface->get_TBS(mcch_mcs, mac_xface->frame_parms->N_RB_DL); - } - else { // only MTCH in this subframeP - TBS = mac_xface->get_TBS(RC.mac[module_idP]->pmch_Config[0]->dataMCS_r9, mac_xface->frame_parms->N_RB_DL); - } - - // get MTCH data from RLC (like for DTCH) - LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframe %d: Schedule MTCH (area %d, sfAlloc %d)\n",Mod_id,CC_id,frame,subframe,i,j); - - header_len_mtch = 3; - LOG_D(MAC,"[eNB %d], CC_id %d, Frame %d, MTCH->MCH, Checking RLC status (rab %d, tbs %d, len %d)\n", - Mod_id,CC_id,frame,MTCH,TBS, - TBS-header_len_mcch-header_len_msi-sdu_length_total-header_len_mtch); - - rlc_status = mac_rlc_status_ind(Mod_id,frame,1,RLC_MBMS_YES,MTCH+ (maxDRB + 3) * MAX_MOBILES_PER_RG, - TBS-header_len_mcch-header_len_msi-sdu_length_total-header_len_mtch); - printf("frame %d, subframe %d, rlc_status.bytes_in_buffer is %d\n",frame,subframe, rlc_status.bytes_in_buffer); - - */ - // get MTCH data from RLC (like for DTCH) - LOG_D(MAC, - "[eNB %d] CC_id %d Frame %d subframeP %d: Schedule MTCH (area %d, sfAlloc %d)\n", + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Schedule MTCH (area %d, sfAlloc %d)\n", module_idP, CC_id, frameP, subframeP, i, j); header_len_mtch = 3; - LOG_D(MAC, - "[eNB %d], CC_id %d, Frame %d, MTCH->MCH, Checking RLC status (rab %d, tbs %d, len %d)\n", + LOG_D(MAC,"[eNB %d], CC_id %d, Frame %d, MTCH->MCH, Checking RLC status (rab %d, tbs %d, len %d)\n", module_idP, CC_id, frameP, MTCH, TBS, TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch); - mbms_rab_id = cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9; + //TODO + mbms_rab_id = cc->mbms_SessionList[0/*mbms_mch_i*/]->list.array[0]->logicalChannelIdentity_r9; rlc_status = mac_rlc_status_ind(module_idP, 0xfffd, frameP, subframeP, module_idP, ENB_FLAG_YES, MBMS_FLAG_YES, - cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, + cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9, //MTCH, 0, 0 ); + bytes_in_buffer = rlc_status.bytes_in_buffer; - + //TOCHECK is this really neede? if( !(mcch_flag==1 || msi_flag==1) ) msi_sfs = rlc_status.bytes_in_buffer/(TBS- header_len_mcch - header_len_msi -sdu_length_total - header_len_mtch)+(rlc_status.bytes_in_buffer%(TBS- header_len_mcch - header_len_msi -sdu_length_total - header_len_mtch)?1:0); - //uint16_t msi_control_element[29], *msi_ptr; - // - // - uint16_t TBS_MTCH = - get_TBS_DL(cc->pmch_Config[0]->dataMCS_r9, to_prb(cc->mib->message.dl_Bandwidth)); + + uint16_t TBS_MTCH = + get_TBS_DL(cc->pmch_Config[mbms_mch_i]->dataMCS_r9, to_prb(cc->mib->message.dl_Bandwidth)); + if(msi_flag==1 && buffer_pointer!=NULL){ - msi_ptr = &msi_control_element[0]; + // msi_ptr = &msi_control_element[0]; - //memcpy(buffer_pointer, - // msi_control_element, msi_length); - - // msi_pmch_stop = rlc_status.bytes_in_buffer/TBS+(rlc_status.bytes_in_buffer%TBS?1:0); msi_pmch_stop = (rlc_status.bytes_in_buffer - header_len_mcch - header_len_msi -sdu_length_total - header_len_mtch)/(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)+((rlc_status.bytes_in_buffer-TBS-header_len_mcch - header_len_msi -sdu_length_total)%(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)?0:0); - if( msi_pmch_stop > cc->pmch_Config[0]->sf_AllocEnd_r9) - LOG_E(MAC,"e-MBMS Buffer Overflow\n"); - if(msi_pmch_stop>=num_sf_alloc /*&& msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9*/) { - ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0; // last subframeP of this mtch (only one mtch now) & stop_sf limited to 256 - //((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = msi_pmch_stop; - ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9); - msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9); - }else{ - ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // last subframeP of this mtch (only one mtch now) - ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF; - msi_pmch_stop=0; - } - LOG_I(MAC,"frameP %d, subframeP %d rlc_status.bytes_in_buffer %d stop_sf_LSB %d\n",frameP,subframeP,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB); - //LOG_W(MAC,"frameP %d, subframeP %d rlc_status.bytes_in_buffer %d stop_sf_LSB %d msi_calc:%d remainder %d\n",frameP,subframeP,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB,rlc_status.bytes_in_buffer/(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)+((rlc_status.bytes_in_buffer-TBS-header_len_mcch - header_len_msi -sdu_length_total)%(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)?0:0),((rlc_status.bytes_in_buffer-TBS-header_len_mcch - header_len_msi -sdu_length_total)%(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)?0:0)); + for (k = 0; k < num_mtch; k++) { // loop for all session in this MCH (MCH[0]) at this moment + msi_ptr = &msi_control_element[k]; - memcpy(buffer_pointer, + ((MSI_ELEMENT *) msi_ptr)->lcid = cc->mbms_SessionList[mbms_mch_i]->list.array[k]->logicalChannelIdentity_r9; //mtch_lcid; + + if( msi_pmch_stop > cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) + LOG_E(MAC,"e-MBMS Buffer Overflow\n"); + + if(msi_pmch_stop>=num_sf_alloc /*&& msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9*/) { + ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = (((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) >> 8) & 0x7f); + ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = ((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) & 0xff); + msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9); + }else{ + ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // last subframeP of this mtch (only one mtch now) + ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF; + msi_pmch_stop=0; + } + LOG_I(MAC,"frameP %d, subframeP %d LCID %ld rlc_status.bytes_in_buffer %d stop_sf_LSB %d stop_sf_MSB %d msi_pmch_stop %d sf_AllocEnd_r9 %ld, msi_length %d\n",frameP,subframeP,((MSI_ELEMENT *) msi_ptr)->lcid,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB,((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB, msi_pmch_stop,cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9, msi_length); + } + + memcpy((char*)buffer_pointer, msi_control_element, msi_length); - } - LOG_D(MAC, - "e-MBMS log channel %u frameP %d, subframeP %d, rlc_status.bytes_in_buffer is %d TBS_MTCH %d pmch_stop %d msi_sfs %d\n", + LOG_D(MAC, "e-MBMS log channel %u frameP %d, subframeP %d, rlc_status.bytes_in_buffer is %d TBS_MTCH %d pmch_stop %d msi_sfs %d\n", MTCH, frameP, subframeP, rlc_status.bytes_in_buffer,TBS_MTCH,msi_pmch_stop,msi_sfs); - if ((rlc_status.bytes_in_buffer > 0 && msi_pmch_stop > 0) && ((msi_flag!=1 || mcch_flag!=1)) /*|| (rlc_status.bytes_in_buffer > 0 && (msi_flag==1 || mcch_flag==1))*//*|| msi_sfs > cc->pmch_Config[0]->sf_AllocEnd_r9 */ /*msi_pmch_stop>=num_sf_alloc*/ ) { - //if(rlc_status.bytes_in_buffer > 0){ - LOG_D(MAC, - "[eNB %d][MBMS USER-PLANE], CC_id %d, Frame %d, MTCH->MCH, Requesting %d bytes from RLC (header len mtch %d) rlc_status.bytes_in_buffer %d\n", - module_idP, CC_id, frameP, + //TODO not sure whether msi and mch MCH should be precluded ... keep in mind this konditions just in case if ((rlc_status.bytes_in_buffer > 0 && msi_pmch_stop > 0) && ((msi_flag!=1 || mcch_flag!=1)) + if ((rlc_status.bytes_in_buffer > 0 && msi_pmch_stop > 0) /*&& ((msi_flag!=1 || mcch_flag!=1))*/ /*|| (rlc_status.bytes_in_buffer > 0 && (msi_flag==1 || mcch_flag==1))*//*|| msi_sfs > cc->pmch_Config[0]->sf_AllocEnd_r9 */ /*msi_pmch_stop>=num_sf_alloc*/ ) { + LOG_I(MAC,"[eNB %d][MBMS USER-PLANE], CC_id %d, Frame %d, Subframe %d MTCH->MCH, Requesting %d bytes from RLC (header len mtch %d) rlc_status.bytes_in_buffer %d, LCID %ld\n", + module_idP, CC_id, frameP, subframeP, TBS - header_len_mcch - header_len_msi - - sdu_length_total - header_len_mtch, header_len_mtch, rlc_status.bytes_in_buffer); + sdu_length_total - header_len_mtch, header_len_mtch, rlc_status.bytes_in_buffer,cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9); - sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0xfffd, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9, + sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0xfffd, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9, TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch, (char *) &mch_buffer[sdu_length_total] ,0, 0 ); - - // LOG_I(MAC,"RLC %x:",(unsigned char)mch_buffer[sdu_length_total]); - // for (int kk = 7; kk >= 0; kk--) - // { - // printf("%d",(((unsigned char)mch_buffer[sdu_length_total]) >> kk) & 1 ? '1' : '0'); - // } - // printf("\n"); - - //sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP,frameP, MBMS_FLAG_NO, MTCH+(MAX_NUM_RB*(MAX_MOBILES_PER_ENB+1)), (char*)&mch_buffer[sdu_length_total]); - LOG_D(MAC, - "[eNB %d][MBMS USER-PLANE] CC_id %d Got %d bytes for MTCH %d msi_pmch_stop %d msi_sfs %d sdu_lengths[num_sdus] %d\n", + LOG_D(MAC,"[eNB %d][MBMS USER-PLANE] CC_id %d Got %d bytes for MTCH %d msi_pmch_stop %d msi_sfs %d sdu_lengths[num_sdus] %d\n", module_idP, CC_id, sdu_lengths[num_sdus], MTCH,msi_pmch_stop,msi_sfs, sdu_lengths[num_sdus]); + cc->mtch_active = 1; - sdu_lcids[num_sdus] = cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9/*MTCH*/; + + sdu_lcids[num_sdus] = cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9/*MTCH*/; sdu_length_total += sdu_lengths[num_sdus]; if (msi_pmch_stop != 0 && msi_flag !=1) msi_pmch_stop--; - if (sdu_lengths[num_sdus] < 128) { header_len_mtch = 2; } num_sdus++; - //} } else { - // LOG_E(MAC, - // "[eNB %d][MBMS USER-PLANE] CC_id %d Got %d bytes for MTCH %d msi_pmch_stop %d msi_buffer %d msi_sfs %ld msi_buffer_act %ld sdu_lengths[num_sdus] %d\n", - // module_idP, CC_id, sdu_lengths[num_sdus], MTCH,msi_pmch_stop,msi_sfs,msi_buffer_act, sdu_lengths[num_sdus]); - header_len_mtch = 0; } } - // } // FINAL STEP: Prepare and multiplexe MSI, MCCH and MTCHs - if ((sdu_length_total + header_len_msi + header_len_mcch + - header_len_mtch) > 0) { + if ((sdu_length_total + header_len_msi + header_len_mcch + header_len_mtch) > 0) { + // Adjust the last subheader - /* if ((msi_flag==1) || (mcch_flag==1)) { - RC.mac[module_idP]->MCH_pdu.mcs = mcch_mcs; - } - else if (mtch_flag == 1) { // only MTCH in this subframeP - RC.mac[module_idP]->MCH_pdu.mcs = RC.mac[module_idP]->pmch_Config[0]->dataMCS_r9; - } - */ header_len_mtch_temp = header_len_mtch; header_len_mcch_temp = header_len_mcch; header_len_msi_temp = header_len_msi; @@ -881,12 +1026,10 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, cc->MCH_pdu.msi_active = cc->msi_active; cc->MCH_pdu.mcch_active = cc->mcch_active; cc->MCH_pdu.mtch_active = cc->mtch_active; - LOG_D(MAC, - " MCS for this sf is %d (mcch active %d, mtch active %d)\n", + LOG_D(MAC, " MCS for this sf is %d (mcch active %d, mtch active %d)\n", cc->MCH_pdu.mcs, cc->MCH_pdu.mcch_active, cc->MCH_pdu.mtch_active); - LOG_D(MAC, - "[eNB %d][MBMS USER-PLANE ] CC_id %d Generate header : sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,padding %d,post_padding %d (mcs %d, TBS %d), header MTCH %d, header MCCH %d, header MSI %d\n", + LOG_D(MAC, "[eNB %d][MBMS USER-PLANE ] CC_id %d Generate header : sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,padding %d,post_padding %d (mcs %d, TBS %d), header MTCH %d, header MCCH %d, header MSI %d\n", module_idP, CC_id, sdu_length_total, num_sdus, sdu_lengths[0], sdu_lcids[0], offset, padding, post_padding, cc->MCH_pdu.mcs, TBS, header_len_mtch, header_len_mcch, @@ -902,20 +1045,15 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, /* Tracing of PDU is done on UE side */ //if (opt_enabled == 1) { - trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) cc->MCH_pdu.payload, TBS, module_idP, WS_M_RNTI , 0xfffd, // M_RNTI = 6 in wirehsark - RC.mac[module_idP]->frame, - RC.mac[module_idP]->subframe, 0, 0); - LOG_D(OPT, - "[eNB %d][MCH] CC_id %d Frame %d : MAC PDU with size %d\n", + trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) cc->MCH_pdu.payload, TBS, module_idP, WS_M_RNTI , 0xfffd, // M_RNTI = 6 in wirehsark + RC.mac[module_idP]->frame, + RC.mac[module_idP]->subframe, 0, 0); + LOG_D(OPT, "[eNB %d][MCH] CC_id %d Frame %d : MAC PDU with size %d\n", module_idP, CC_id, frameP, TBS); //} eNB_MAC_INST *eNB = RC.mac[module_idP]; dl_req = &eNB->DL_req[CC_id].dl_config_request_body; - // dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - // memset((void *) dl_config_pdu, - // 0, - // sizeof(nfapi_dl_config_request_pdu_t)); dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; fill_nfapi_mch_config( dl_req, @@ -934,12 +1072,6 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, TBS, eNB->pdu_index[CC_id], (uint8_t*)cc->MCH_pdu.payload); - - - /* - for (j=0;jMCH_pdu.payload[j+offset]); - printf(" \n"); */ return 1; } else { cc->MCH_pdu.Pdu_size = 0; @@ -947,21 +1079,8 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, cc->MCH_pdu.msi_active = 0; cc->MCH_pdu.mcch_active = 0; cc->MCH_pdu.mtch_active = 0; - // for testing purpose, fill with random data - //for (j=0;j<(TBS-sdu_length_total-offset);j++) - // RC.mac[module_idP]->MCH_pdu.payload[offset+sdu_length_total+j] = (char)(taus()&0xff); return 0; } - - //this is for testing - /* - if (mtch_flag == 1) { - // LOG_D(MAC,"DUY: mch_buffer length so far is : %ld\n", &mch_buffer[sdu_length_total]-&mch_buffer[0]); - return 1; - } - else - return 0; - */ } int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 329e262c82..d3bf40afa4 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -56,6 +56,7 @@ #include "LTE_MobilityControlInfo.h" #include "LTE_MBSFN-AreaInfoList-r9.h" #include "LTE_MBSFN-SubframeConfigList.h" +#include "LTE_MBSFNAreaConfiguration-r9.h" #include "LTE_PMCH-InfoList-r9.h" #include "LTE_SCellToAddMod-r10.h" #include "LTE_SystemInformationBlockType1-v1310-IEs.h" @@ -412,9 +413,11 @@ typedef struct { /*!\brief Values of BCCH SIB_BR logical channel (fake) */ #define BCCH_SI_BR 7 // SI-BR /*!\brief Values of BCCH SIB1_MBMS logical channel (fake) */ -#define BCCH_SIB1_MBMS 60 // SIB1_MBMS //TODO better armonize index +#define MIBCH_MBMS 10 // SIB1_MBMS //TODO better armonize index +#define BCCH_SIB1_MBMS 12 // SIB1_MBMS //TODO better armonize index /*!\brief Values of BCCH SI_MBMS logical channel (fake) */ -#define BCCH_SI_MBMS 61 // SIB_MBMS //TODO better armonize index +#define BCCH_SI_MBMS 13 // SIB_MBMS //TODO better armonize index +#define MCCH_COUNTING 14 /*!\brief Value of CCCH / SRB0 logical channel */ #define CCCH 0 // srb0 /*!\brief DCCH / SRB1 logical channel */ @@ -1312,6 +1315,8 @@ typedef struct { /// MBSFN SubframeConfig struct LTE_MBSFN_SubframeConfig *mbsfn_SubframeConfig[8]; struct LTE_NonMBSFN_SubframeConfig_r14 *non_mbsfn_SubframeConfig; + struct LTE_MBSFN_SubframeConfig *commonSF_Alloc_r9_mbsfn_SubframeConfig[8]; // FIXME replace 8 by MAX_MBSFN_AREA? + uint8_t commonSF_AllocPeriod_r9; /// number of subframe allocation pattern available for MBSFN sync area uint8_t num_sf_allocation_pattern; /// MBMS Flag diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 2cb86c25af..d3bf1bd2ac 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -33,6 +33,16 @@ #include "PHY/defs_common.h" // for PRACH_RESOURCES_t and lte_subframe_t #include "openair2/COMMON/mac_messages_types.h" +/** \fn void schedule_fembms_mib(module_id_t module_idP,frame_t frameP,sub_frame_t subframe); +\brief MIB scheduling for PBCH. This function requests the MIB from RRC and provides it to L1. +@param Mod_id Instance ID of eNB +@param frame Frame index +@param subframe Subframe number on which to act + +*/ + +void schedule_fembms_mib(module_id_t module_idP, + frame_t frameP, sub_frame_t subframeP); /** \addtogroup _mac * @{ @@ -534,6 +544,10 @@ int ue_query_mch(module_id_t Mod_id, uint8_t CC_id, uint32_t frame, sub_frame_t subframe, uint8_t eNB_index, uint8_t *sync_area, uint8_t *mcch_active); +int ue_query_mch_fembms(module_id_t Mod_id, uint8_t CC_id, uint32_t frame, + sub_frame_t subframe, uint8_t eNB_index, + uint8_t * sync_area, uint8_t * mcch_active); + /* \brief Called by PHY to get sdu for PUSCH transmission. It performs the following operations: Checks BSR for DCCH, DCCH1 and DTCH corresponding to previous values computed either in SR or BSR procedures. It gets rlc status indications on DCCH,DCCH1 and DTCH and forms BSR elements and PHR in MAC header. CRNTI element is not supported yet. It computes transport block for up to 3 SDUs and generates header and forms the complete MAC SDU. @param Mod_id Instance id of UE in machine @@ -900,6 +914,7 @@ int generate_dlsch_header(unsigned char *mac_header, @param non_MBSFN_SubframeConfig pointer to FeMBMS Non MBSFN Subframe Config @param sib1_mbms_r14_fembms pointer SI Scheduling infomration for SI-MBMS @param mbsfn_AreaInfoList_fembms pointer to FeMBMS MBSFN Area Info list from SIB1-MBMS +@param mbms_AreaConfiguration pointer to eMBMS MBSFN Area Configuration */ int rrc_mac_config_req_eNB(module_id_t module_idP, @@ -936,7 +951,8 @@ int rrc_mac_config_req_eNB(module_id_t module_idP, LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo_fembms, struct LTE_NonMBSFN_SubframeConfig_r14 *nonMBSFN_SubframeConfig, LTE_SystemInformationBlockType1_MBMS_r14_t *sib1_mbms_r14_fembms, - LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms + LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms, + LTE_MBSFNAreaConfiguration_r9_t * mbms_AreaConfiguration ); /** \brief RRC eNB Configuration primitive for PHY/MAC. Allows configuration of PHY/MAC resources based on System Information (SI), RRCConnectionSetup and RRCConnectionReconfiguration messages. diff --git a/openair2/LAYER2/MAC/ue_procedures.c b/openair2/LAYER2/MAC/ue_procedures.c index 24630c0fe2..54d9f687e1 100644 --- a/openair2/LAYER2/MAC/ue_procedures.c +++ b/openair2/LAYER2/MAC/ue_procedures.c @@ -72,7 +72,10 @@ extern UL_IND_t *UL_INFO; extern int next_ra_frame; extern module_id_t next_Mod_id; -int mbms_rab_id = 2047; +int mbms_rab_id=2047;//[8] = {2047,2047,2047,2047,2047,2047,2047,2047}; +static int mbms_mch_i=0; +static int num_msi_per_CSA[28]; + /* * @@ -753,13 +756,14 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, LOG_E(MAC,"MCH Scheduling Information MAC Control Element should have an even size\n"); } - LOG_D(MAC,"MCH Scheduling Information, len(%d)\n",rx_lengths[i]); + LOG_D(MAC,"MCH Scheduling Information, len(%d)\n",rx_lengths[i]); + for (j=0; j> 3; UE_mac_inst[module_idP].pmch_stop_mtch[j] = stop_mtch_val; - LOG_D(MAC,"lcid(%d),stop_mtch_val %d frameP(%d)\n", UE_mac_inst[module_idP].pmch_lcids[j], stop_mtch_val, frameP); + LOG_I(MAC,"lcid(%d),stop_mtch_val %d frameP(%d)\n", UE_mac_inst[module_idP].pmch_lcids[j], stop_mtch_val, frameP); if ((stop_mtch_val >= 2043) && (stop_mtch_val <= 2046)) { LOG_D(MAC,"(reserved)\n"); @@ -768,7 +772,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, UE_mac_inst[module_idP].msi_status_v[j] = 0; if (UE_mac_inst[module_idP].mcch_status==1) { - LOG_D(MAC,"[UE %d] Frame %d : MCH->MSI for sync area %d (eNB %d, %d bytes), i(%d)\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], UE_mac_inst[module_idP].pmch_stop_mtch[j]); + LOG_I(MAC,"[UE %d] Frame %d : MCH->MSI for sync area %d (eNB %d, %d bytes), LCID(%d)(%d)\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], UE_mac_inst[module_idP].pmch_lcids[j] , UE_mac_inst[module_idP].pmch_stop_mtch[j]); if (UE_mac_inst[module_idP].pmch_stop_mtch[j] < 2043) { UE_mac_inst[module_idP].pmch_stop_mtch[j] += UE_mac_inst[module_idP].msi_current_alloc; @@ -777,7 +781,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, } } } else if (rx_lcids[i] == MCCH_LCHANID) { - LOG_D(MAC,"[UE %d] Frame %d : SDU %d MCH->MCCH for sync area %d (eNB %d, %d bytes)\n",module_idP,frameP, i, sync_area, eNB_index, rx_lengths[i]); + LOG_I(MAC,"[UE %d] Frame %d : SDU %d MCH->MCCH for sync area %d (eNB %d, %d bytes)\n",module_idP,frameP, i, sync_area, eNB_index, rx_lengths[i]); mac_rrc_data_ind_ue(module_idP, CC_id, frameP,0, // unknown subframe @@ -794,7 +798,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, } if (j<28 && UE_mac_inst[module_idP].msi_status_v[j]==1) { - LOG_D(MAC,"[UE %d] Frame %d : MCH->MTCH for sync area %d (eNB %d, %d bytes), j=%d\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], j); + LOG_D(MAC,"[UE %d] Frame %d : MCH->MTCH for sync area %d (eNB %d, %d bytes), j=%d lcid %d\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], j,rx_lcids[i]); //This sucks I know ... workaround ! mbms_rab_id = rx_lcids[i]; //end sucks :-( @@ -951,7 +955,9 @@ int ue_query_p_mch_info(module_id_t module_idP, uint32_t frameP, uint32_t subfra } } else { //more that one MCH ?? check better this condition //msi and mtch are mutally excluded then the break is safe + //TODO if ((num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[i-1]->sf_AllocEnd_r9 + 1) && (sf_AllocEnd_r9 >= (num_sf_alloc+1))) { + //if ((num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[i-1]->sf_AllocEnd_r9) && (sf_AllocEnd_r9 >= (num_sf_alloc))) { //msi should be just after msi_flag = 1; LOG_D(MAC,"msi(%d) should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),sf_AllocEnd_r9(%d),common_num_sf_alloc(%d)\n",i,frameP,subframe,num_sf_alloc,sf_AllocEnd_r9, @@ -986,6 +992,458 @@ int ue_query_p_mch_info(module_id_t module_idP, uint32_t frameP, uint32_t subfra return mtch_mcs; } +//static int common_num_sf_alloc=0; +//static int x=0; +int ue_query_mch_fembms(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_t subframe, uint8_t eNB_index,uint8_t *sync_area, uint8_t *mcch_active) { + int i = 0, j = 0,/* ii = 0,*/ msi_pos = -1, mcch_mcs = -1, mtch_mcs = -1, l=0,ii=0; + int mcch_flag = 0, mtch_flag = 0, msi_flag = 0; + int alloc_offset=0; + uint32_t period; + //uint16_t num_non_mbsfn_SubframeConfig=0; + long mch_scheduling_period = -1; + uint8_t mch_lcid = 0; + int first_pos=0; + + if(UE_mac_inst[module_idP].non_mbsfn_SubframeConfig == NULL ) + return -1; + + int non_mbsfn_SubframeConfig = (UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7); + + period = 4<radioFrameAllocationPeriod_r14; + alloc_offset = UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->radioFrameAllocationOffset_r14; + + long mcch_period = 32 << UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_RepetitionPeriod_r9; + long mcch_offset = UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9; + + if (UE_mac_inst[module_idP].pmch_Config[0]) { + mch_scheduling_period = 8 << UE_mac_inst[module_idP].pmch_Config[0]->mch_SchedulingPeriod_r9; + } + + +// for(l=0;l<8;l++){ +// if(UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]!=NULL){ +// if(frameP%(4<> msi_pos)) == (0x100>>msi_pos)) +// first_pos++; +// if(first_pos == subframe){ +// ii=0; +// while(UE_mac_inst[module_idP].pmch_Config[ii]!=NULL){ +// num_msi_per_CSA[ii]= ( ( 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9) / (8 << UE_mac_inst[module_idP].pmch_Config[ii]->mch_SchedulingPeriod_r9) ); +// ii++; +// LOG_D(MAC,"frameP %d subframe %d num_msi_per_CSA[%d] %d\n",frameP,subframe,ii,num_msi_per_CSA[ii]); +// } +// } +// +// } +// } +// } +// + + // get the real MCS value + switch (UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) { + case 0: + mcch_mcs = 2; + break; + + case 1: + mcch_mcs = 7; + break; + + case 2: + mcch_mcs = 13; + break; + + case 3: + mcch_mcs = 19; + break; + } + LOG_D(MAC,"frameP %d subframe %d period %d alloc_offset %d mcch_mcs %d mcch_period %ld mcch_offset %ld buf %x mch_scheduling_period %ld\n",frameP, subframe, period, alloc_offset,mcch_mcs, mcch_period, mcch_offset,(UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0]),mch_scheduling_period); + + if((frameP % period ) == alloc_offset){ + switch(subframe){ + case 0: + return (-1); + break; + case 1: + if ((non_mbsfn_SubframeConfig & 0x100) > 0) + return (-1); + break; + case 2: + if ((non_mbsfn_SubframeConfig & 0x80) > 0) + return (-1); + break; + case 3: + if ((non_mbsfn_SubframeConfig & 0x40) > 0) + return (-1); + break; + case 4: + if ((non_mbsfn_SubframeConfig & 0x20) > 0) + return (-1); + break; + case 5: + if ((non_mbsfn_SubframeConfig & 0x10) > 0) + return (-1); + break; + case 6: + if ((non_mbsfn_SubframeConfig & 0x8) > 0) + return (-1); + break; + case 7: + if ((non_mbsfn_SubframeConfig & 0x4) > 0) + return (-1); + break; + case 8: + if ((non_mbsfn_SubframeConfig & 0x2) > 0) + return (-1); + break; + case 9: + if ((non_mbsfn_SubframeConfig & 0x1) > 0) + return (-1); + break; + } + } + + if (UE_mac_inst[module_idP].pmch_Config[0]) { + // Find the first subframe in this MCH to transmit MSI + if (frameP % 1 == 0) { + if (frameP % mch_scheduling_period == 0) { + msi_pos=0; + if((frameP&3)==0) + msi_pos++; + while((non_mbsfn_SubframeConfig & (0x100 >> msi_pos)) == (0x100>>msi_pos)) + msi_pos++; + if(msi_pos == subframe){ + UE_mac_inst[module_idP].common_num_sf_alloc=0; + mbms_mch_i=0; + //LOG_W(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + } + } + + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=subframe; + mbms_mch_i++; + // LOG_W(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + + + // Check if the subframe is for MSI, MCCH or MTCHs and Set the correspoding flag to 1 + switch (subframe) { + case 0: + if (msi_pos == 0) { + msi_flag = 1; + } + mtch_flag = 1; + break; + case 1: + if (msi_pos == 1) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && + ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1)) { + mcch_flag = 1; + } + + mtch_flag = 1; + break; + + case 2: + if (msi_pos == 2) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && + ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2)) { + mcch_flag = 1; + } + + mtch_flag = 1; + + break; + + case 3: + if (msi_pos == 3) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && + ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3)) { + mcch_flag = 1; + } + + mtch_flag = 1; + + break; + case 4: + if (msi_pos == 4) { + msi_flag = 1; + } + mtch_flag = 1; + break; + case 5: + if (msi_pos == 5) { + msi_flag = 1; + } + mtch_flag = 1; + break; + + case 6: + if (msi_pos == 6) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && + ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6)) { + mcch_flag = 1; + } + + mtch_flag = 1; + + break; + + case 7: + if (msi_pos == 7) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && + ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7)) { + mcch_flag = 1; + } + + mtch_flag = 1; + + break; + + case 8: + if (msi_pos == 8) { + msi_flag = 1; + } + if ((frameP % mcch_period == mcch_offset) && + ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8)) { + mcch_flag = 1; + } + + mtch_flag = 1; + break; + + case 9: + if (msi_pos == 9) { + msi_flag = 1; + } + mtch_flag = 1; + break; + }// end switch + + if( (msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1) ){ + UE_mac_inst[module_idP].common_num_sf_alloc++; + //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){ + //UE_mac_inst[module_idP].common_num_sf_alloc++; + //if(msi_flag == 1) + // if((num_msi_per_CSA[mbms_mch_i]--)==0){ + // LOG_E(MAC,"Both MSI and MTCH Should be reset?\n"); + // msi_flag=0; + //} + //} + + } + + + + +#ifdef OLD + // Acount for sf_allocable in CSA + int num_sf_alloc = 0; + + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) + continue; + + uint32_t common_mbsfn_SubframeConfig = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.choice.oneFrame.buf[0]; + + + for (j = 0; j < 6; j++) + num_sf_alloc += ((common_mbsfn_SubframeConfig & (0x80 >> j)) == (0x80 >> j)); + //num_sf_alloc=1; + } + + num_sf_alloc = 10; + + num_non_mbsfn_SubframeConfig = (UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7); + int ones=0; + for(j=0; j < 16; j++){ + if(num_non_mbsfn_SubframeConfig & 1) + ones++; + num_non_mbsfn_SubframeConfig>>=1; + } + + for (l = 0; l < 28; l++) { + if (UE_mac_inst[module_idP].pmch_stop_mtch[l] >= 1/*num_sf_alloc*/) { + if (UE_mac_inst[module_idP].pmch_stop_mtch[l] != 2047) { + if (UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch] != NULL){ + mtch_mcs = UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch]->dataMCS_r9; + //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[0]->radioframeAllocationOffset; + long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[0]->radioframeAllocationPeriod; + long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9; + if(UE_mac_inst[module_idP].common_num_sf_alloc >= UE_mac_inst[module_idP].pmch_stop_mtch[l]){ + //LOG_E(MAC,"Attemp to UE_mac_inst[module_idP].common_num_sf_alloc %d\n",UE_mac_inst[module_idP].common_num_sf_alloc); + + mtch_mcs = -1; + }/*else + OG_W(MAC,"Attemp to UE_mac_inst[module_idP].common_num_sf_alloc %d\n",UE_mac_inst[module_idP].common_num_sf_alloc);*/ + LOG_D(MAC,"Attemp to UE_mac_inst[module_idP].common_num_sf_alloc %d num_sf_alloc %d commonSF_AllocPeriod %ld, common_mbsfn_period %ld num_non_mbsfn_SubframeConfig %x ones %d\n",UE_mac_inst[module_idP].common_num_sf_alloc,num_sf_alloc, commonSF_AllocPeriod,common_mbsfn_period,num_non_mbsfn_SubframeConfig,ones); + UE_mac_inst[module_idP].common_num_sf_alloc++; + UE_mac_inst[module_idP].common_num_sf_alloc = UE_mac_inst[module_idP].common_num_sf_alloc % (num_sf_alloc * commonSF_AllocPeriod / common_mbsfn_period-(1+ones)*(commonSF_AllocPeriod/4)); //TODO + } + else + mtch_mcs = -1; + + mch_lcid = (uint8_t)l; + break; + } + } + } +#endif + +{ + // Acount for sf_allocable in Common SF Allocation + int num_sf_alloc = 0; + + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) + continue; + + //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset; + long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod; + long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9; + + + num_sf_alloc =10*commonSF_AllocPeriod/common_mbsfn_period; + num_sf_alloc -=1*((commonSF_AllocPeriod/common_mbsfn_period)/4); //CAS sfs + uint32_t num_non_mbsfn_SubframeConfig2 = (UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7); + for (j = 0; j < 10; j++) + num_sf_alloc -= ((num_non_mbsfn_SubframeConfig2 & (0x200 >> j)) == (0x200 >> j))*((commonSF_AllocPeriod/common_mbsfn_period)/period); + + } + + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) + continue; + + //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset; + long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod; + //long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9; + + + if(msi_flag==1 && UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){ + LOG_D(MAC,"msi(%d) should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),sf_AllocEnd_r9(%ld),common_num_sf_alloc(%d)\n",mbms_mch_i,frameP,subframe,num_sf_alloc,UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9, + UE_mac_inst[module_idP].common_num_sf_alloc); + UE_mac_inst[module_idP].msi_current_alloc = UE_mac_inst[module_idP].common_num_sf_alloc;//num_sf_alloc; + UE_mac_inst[module_idP].msi_pmch = mbms_mch_i; + }else if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){ + if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] >= UE_mac_inst[module_idP].common_num_sf_alloc/*num_sf_alloc*/) { + if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] != 2047) { + mtch_flag = 1; + if (UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch] != NULL) + mtch_mcs = UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch]->dataMCS_r9; + else + mtch_mcs = -1; + mch_lcid = (uint8_t)mbms_mch_i; + LOG_D(MAC,"mtch should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),mtch_mcs(%d),pmch_stop_mtch(%d),lcid(%d),msi_pmch(%d)\n",frameP,subframe,num_sf_alloc,mtch_mcs, + UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i],UE_mac_inst[module_idP].pmch_lcids[mbms_mch_i],UE_mac_inst[module_idP].msi_pmch); + } + } + } + UE_mac_inst[module_idP].common_num_sf_alloc = UE_mac_inst[module_idP].common_num_sf_alloc % ((num_sf_alloc-mbms_mch_i) /** commonSF_AllocPeriod *// common_mbsfn_period);//48; + + if(mtch_flag) + break; + } + if(msi_flag==1){ + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %(4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 <mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){ + msi_flag=0; + LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframe, mbms_mch_i); + } + } + } +} + + // sf allocation is non-overlapping + if ((msi_flag==1) || (mcch_flag==1) || (mtch_flag==1)) { + LOG_D(MAC,"[UE %d] Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n", + module_idP, frameP, subframe,l,j,msi_flag,mcch_flag,mtch_flag); + *sync_area=i; + } + + //if(msi_flag == 1) + // if((num_msi_per_CSA[mbms_mch_i]--)==0){ + // LOG_E(MAC,"Both MSI and MTCH Should be reset?\n"); + // msi_flag=mtch_flag=0; + //} + + + if ((mcch_flag == 1)) { // || (msi_flag==1)) + *mcch_active = 1; + } + + if ( (mcch_flag==1) || ((msi_flag==1) && (UE_mac_inst[module_idP].mcch_status==1)) ) { + if (msi_flag!=1) { + for (i=0; i<8; i++) + UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[i] = NULL; + + for (i=0; i<15; i++) + UE_mac_inst[module_idP].pmch_Config[i] = NULL; + + for (i=0; i<28 ; i++) { + UE_mac_inst[module_idP].pmch_lcids[i] = -1; + UE_mac_inst[module_idP].pmch_stop_mtch[i] = 2047; + UE_mac_inst[module_idP].msi_status_v[i] = 0; + } + } else { + for (i=0; i<28; i++) { + UE_mac_inst[module_idP].pmch_lcids[i] = -1; + UE_mac_inst[module_idP].pmch_stop_mtch[i] = 2047; + UE_mac_inst[module_idP].msi_status_v[i] = 0; + } + } + + return mcch_mcs; + } else if ((mtch_flag==1) && (UE_mac_inst[module_idP].msi_status_v[(mch_lcid > 27) ? 27 : mch_lcid] == 1)) { + return mtch_mcs; + } else { + return -1; + } + + + + // if(mcch_flag == 1 || msi_flag == 1 ){ + // *mcch_active = 1; + // return (mcch_mcs); + // }else if(mtch_flag == 1){ + // mtch_mcs=-1; + // return (mtch_mcs); + // } + + // return -1; + +} + + int ue_query_p_mch(module_id_t module_idP, uint32_t frameP, uint32_t subframe, int *mtch_active, int *msi_active, uint8_t *mch_lcid) { int i, j, mtch_mcs = -1; int mtch_flag = 0; @@ -1100,6 +1558,7 @@ int ue_query_p_mch(module_id_t module_idP, uint32_t frameP, uint32_t subframe, i return mtch_mcs; } + int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_t subframe, uint8_t eNB_index,uint8_t *sync_area, uint8_t *mcch_active) { int i = 0, j = 0, ii = 0, jj = 0, msi_pos = 0, mcch_mcs = -1, mtch_mcs = -1; int l =0; @@ -1162,6 +1621,11 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ ii = UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & (0x80 >> msi_pos); msi_pos++; } + if(msi_pos == subframe){ + UE_mac_inst[module_idP].common_num_sf_alloc=0; + mbms_mch_i=0; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } } } @@ -1170,6 +1634,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ case 1: if (UE_mac_inst[module_idP].tdd_Config == NULL) { if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) { + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=1; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 1) { msi_flag = 1; } @@ -1188,6 +1660,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ case 2: if (UE_mac_inst[module_idP].tdd_Config == NULL) { if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2) { + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=2; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 2) { msi_flag = 1; } @@ -1219,6 +1699,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ } } else { // FDD if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3) { + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=3; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 3) { msi_flag = 1; } @@ -1255,6 +1743,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ case 6: if (UE_mac_inst[module_idP].tdd_Config == NULL) { if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6) { + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=6; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 4) { msi_flag = 1; } @@ -1286,6 +1782,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ } } else { // FDD if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7) { + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=5; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } + if (msi_pos == 5) { msi_flag = 1; } @@ -1317,6 +1821,13 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ } } else { // FDD if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8) { + if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){ + if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){ + msi_pos=6; + mbms_mch_i++; + LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i); + } + } if (msi_pos == 6) { msi_flag = 1; } @@ -1351,6 +1862,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ break; }// end switch + if( (msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1) ){ + UE_mac_inst[module_idP].common_num_sf_alloc++; + //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){ + //UE_mac_inst[module_idP].common_num_sf_alloc++; + //} + } + +#ifdef OLD // Acount for sf_allocable in CSA int num_sf_alloc = 0; @@ -1392,11 +1911,86 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_ } } } +#endif + +{ + // Acount for sf_allocable in Common SF Allocation + int num_sf_alloc = 0; + + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) + continue; + + //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset; + //long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod; + //long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9; + + uint32_t common_mbsfn_SubframeConfig = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.choice.oneFrame.buf[0]; + + for (j = 0; j < 6; j++) + num_sf_alloc += ((common_mbsfn_SubframeConfig & (0x80 >> j)) == (0x80 >> j)); + } + + + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) + continue; + + //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset; + long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod; + long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9; + + + if(msi_flag==1 && UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){ + LOG_D(MAC,"msi(%d) should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),sf_AllocEnd_r9(%ld),common_num_sf_alloc(%d)\n",mbms_mch_i,frameP,subframe,num_sf_alloc,UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9, + UE_mac_inst[module_idP].common_num_sf_alloc); + UE_mac_inst[module_idP].msi_current_alloc = UE_mac_inst[module_idP].common_num_sf_alloc;//num_sf_alloc; + UE_mac_inst[module_idP].msi_pmch = mbms_mch_i; + }else if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){ + if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] >= UE_mac_inst[module_idP].common_num_sf_alloc/*num_sf_alloc*/) { + if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] != 2047) { + mtch_flag = 1; + if (UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch] != NULL) + mtch_mcs = UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch]->dataMCS_r9; + else + mtch_mcs = -1; + mch_lcid = (uint8_t)mbms_mch_i; + LOG_D(MAC,"mtch should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),mtch_mcs(%d),pmch_stop_mtch(%d),lcid(%d),msi_pmch(%d)\n",frameP,subframe,num_sf_alloc,mtch_mcs, + UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i],UE_mac_inst[module_idP].pmch_lcids[mbms_mch_i],UE_mac_inst[module_idP].msi_pmch); + } + } + } + //LOG_D(MAC,"UE_mac_inst[module_idP].common_num_sf_alloc: %d num_sf_alloc %d mbms_mch_i %d commonSF_AllocPeriod %d common_mbsfn_period %d\n",UE_mac_inst[module_idP].common_num_sf_alloc,num_sf_alloc,mbms_mch_i,commonSF_AllocPeriod,common_mbsfn_period); + UE_mac_inst[module_idP].common_num_sf_alloc = UE_mac_inst[module_idP].common_num_sf_alloc % ((num_sf_alloc* commonSF_AllocPeriod-mbms_mch_i) / common_mbsfn_period);//48; + + + if(mtch_flag) + break; + } + if(msi_flag==1){ + for (l = 0; l < 8; l++) { + if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL) + continue; + + if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %(4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 <mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){ + msi_flag=0; + LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframe, mbms_mch_i); + } + } + } + +} // sf allocation is non-overlapping if ((msi_flag==1) || (mcch_flag==1) || (mtch_flag==1)) { - LOG_D(MAC,"[UE %d] Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n", - module_idP, frameP, subframe,l,j,msi_flag,mcch_flag,mtch_flag); + LOG_D(MAC,"[UE %d] Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d x %d\n", + module_idP, frameP, subframe,l,j,msi_flag,mcch_flag,mtch_flag,UE_mac_inst[module_idP].common_num_sf_alloc); *sync_area=i; break; } diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c index 6c23332687..7286aad455 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c @@ -308,7 +308,7 @@ int pdcp_fifo_read_input_mbms_sdus_fromtun (const protocol_ctxt_t *const ctxt_p ctxt.module_id, ctxt.rnti, ctxt.enb_flag); if (h_rc == HASH_TABLE_OK) { - LOG_I(PDCP, "[FRAME %5u][UE][NETLINK][IP->PDCP] INST %d: Received socket with length %d on Rab %ld \n", + LOG_D(PDCP, "[FRAME %5u][UE][NETLINK][IP->PDCP] INST %d: Received socket with length %d on Rab %ld \n", ctxt.frame, ctxt.instance, len, rab_id); LOG_D(PDCP, "[FRAME %5u][UE][IP][INSTANCE %u][RB %ld][--- PDCP_DATA_REQ / %d Bytes --->][PDCP][MOD %u][UE %04x][RB %ld]\n", ctxt.frame, ctxt.instance, rab_id, len, ctxt.module_id, From 6db9fca1b77aa2dd8972d24e2c7370a021522c3a Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Tue, 21 Jul 2020 21:07:42 +0200 Subject: [PATCH 28/70] fembms: code cleanup Signed-off-by: Javier Morgade --- openair2/LAYER2/MAC/eNB_scheduler_mch.c | 2 +- openair2/LAYER2/MAC/ue_procedures.c | 6 +- openair2/M2AP/m2ap_MCE_interface_management.c | 143 ++++++++++++- openair2/M2AP/m2ap_MCE_interface_management.h | 10 +- openair2/M2AP/m2ap_eNB.c | 18 ++ openair2/M2AP/m2ap_eNB_interface_management.c | 200 +++++++++++++++++- openair2/MCE_APP/mce_app.c | 5 +- 7 files changed, 352 insertions(+), 32 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_mch.c b/openair2/LAYER2/MAC/eNB_scheduler_mch.c index cb90419d43..0c686a6475 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_mch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_mch.c @@ -921,7 +921,7 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP, ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF; msi_pmch_stop=0; } - LOG_I(MAC,"frameP %d, subframeP %d LCID %ld rlc_status.bytes_in_buffer %d stop_sf_LSB %d stop_sf_MSB %d msi_pmch_stop %d sf_AllocEnd_r9 %ld, msi_length %d\n",frameP,subframeP,((MSI_ELEMENT *) msi_ptr)->lcid,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB,((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB, msi_pmch_stop,cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9, msi_length); + LOG_I(MAC,"frameP %d, subframeP %d LCID %d rlc_status.bytes_in_buffer %d stop_sf_LSB %d stop_sf_MSB %d msi_pmch_stop %d sf_AllocEnd_r9 %ld, msi_length %d\n",frameP,subframeP,((MSI_ELEMENT *) msi_ptr)->lcid,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB,((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB, msi_pmch_stop,cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9, msi_length); } memcpy((char*)buffer_pointer, diff --git a/openair2/LAYER2/MAC/ue_procedures.c b/openair2/LAYER2/MAC/ue_procedures.c index 54d9f687e1..f81c66e269 100644 --- a/openair2/LAYER2/MAC/ue_procedures.c +++ b/openair2/LAYER2/MAC/ue_procedures.c @@ -74,7 +74,7 @@ extern module_id_t next_Mod_id; int mbms_rab_id=2047;//[8] = {2047,2047,2047,2047,2047,2047,2047,2047}; static int mbms_mch_i=0; -static int num_msi_per_CSA[28]; +//static int num_msi_per_CSA[28]; /* @@ -995,14 +995,14 @@ int ue_query_p_mch_info(module_id_t module_idP, uint32_t frameP, uint32_t subfra //static int common_num_sf_alloc=0; //static int x=0; int ue_query_mch_fembms(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_t subframe, uint8_t eNB_index,uint8_t *sync_area, uint8_t *mcch_active) { - int i = 0, j = 0,/* ii = 0,*/ msi_pos = -1, mcch_mcs = -1, mtch_mcs = -1, l=0,ii=0; + int i = 0, j = 0,/* ii = 0,*/ msi_pos = -1, mcch_mcs = -1, mtch_mcs = -1, l=0/*,ii=0*/; int mcch_flag = 0, mtch_flag = 0, msi_flag = 0; int alloc_offset=0; uint32_t period; //uint16_t num_non_mbsfn_SubframeConfig=0; long mch_scheduling_period = -1; uint8_t mch_lcid = 0; - int first_pos=0; + //int first_pos=0; if(UE_mac_inst[module_idP].non_mbsfn_SubframeConfig == NULL ) return -1; diff --git a/openair2/M2AP/m2ap_MCE_interface_management.c b/openair2/M2AP/m2ap_MCE_interface_management.c index 1bef834179..e162c9a5de 100644 --- a/openair2/M2AP/m2ap_MCE_interface_management.c +++ b/openair2/M2AP/m2ap_MCE_interface_management.c @@ -521,6 +521,7 @@ int MCE_send_MBMS_SCHEDULING_INFORMATION(instance_t instance, /*uint32_t assoc_i mbsfn_subframe_configuration->radioframeAllocationPeriod = m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_period; mbsfn_subframe_configuration->radioframeAllocationOffset = m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_offset; if(m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf){ + LOG_I(M2AP,"is_four_sf\n"); mbsfn_subframe_configuration->subframeAllocation.present = M2AP_MBSFN_Subframe_Configuration__subframeAllocation_PR_fourFrames; mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.buf = MALLOC(3); mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation) & 0xFF); @@ -530,6 +531,7 @@ int MCE_send_MBMS_SCHEDULING_INFORMATION(instance_t instance, /*uint32_t assoc_i mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.bits_unused = 0; }else{ + LOG_I(M2AP,"is_one_sf\n"); mbsfn_subframe_configuration->subframeAllocation.present = M2AP_MBSFN_Subframe_Configuration__subframeAllocation_PR_oneFrame; mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.buf = MALLOC(1); mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.size = 1; @@ -1357,11 +1359,10 @@ int MCE_handle_MBMS_SESSION_UPDATE_RESPONSE(instance_t instance, -int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance, - uint32_t assoc_id, - uint32_t stream, - M2AP_M2AP_PDU_t *pdu){ +int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance,module_id_t du_mod_idP){ + AssertFatal(1==0,"Not implemented yet\n"); + } /* @@ -1378,16 +1379,138 @@ int MCE_handle_MBMS_SERVICE_COUNTING_RESPONSE(instance_t instance, uint32_t assoc_id, uint32_t stream, M2AP_M2AP_PDU_t *pdu){ - AssertFatal(1==0,"Not implemented yet\n"); + //int i; + //AssertFatal(1==0,"Not implemented yet\n"); + LOG_D(M2AP, "MCE_handle_MBMS_SERVICE_COUNTING_RESPONSE\n"); + + AssertFatal(pdu->present == M2AP_M2AP_PDU_PR_successfulOutcome, + "pdu->present != M2AP_M2AP_PDU_PR_successfulOutcome\n"); + AssertFatal(pdu->choice.successfulOutcome.procedureCode == M2AP_ProcedureCode_id_mbmsServiceCounting, + "pdu->choice.successfulOutcome->procedureCode != M2AP_ProcedureCode_id_mbmsServiceCounting\n"); + AssertFatal(pdu->choice.successfulOutcome.criticality == M2AP_Criticality_reject, + "pdu->choice.successfulOutcome->criticality != M2AP_Criticality_reject\n"); + AssertFatal(pdu->choice.successfulOutcome.value.present == M2AP_SuccessfulOutcome__value_PR_MbmsServiceCountingResponse, + "pdu->choice.successfulOutcome.value.present != M2AP_SuccessfulOutcome__value_PR_MbmsServiceCountingResponse\n"); + + + M2AP_MbmsServiceCountingResponse_t *in = &pdu->choice.successfulOutcome.value.choice.MbmsServiceCountingResponse; + //M2AP_MbmsServiceCountingResponse_Ies_t *ie; + //int MCE_MBMS_M2AP_ID=-1; + //int ENB_MBMS_M2AP_ID=-1; + + + MessageDef *msg_g = itti_alloc_new_message(TASK_M2AP_MCE,M2AP_MBMS_SERVICE_COUNTING_RESP); //TODO + + LOG_D(M2AP, "M2AP: MbmsServiceCounting-Resp: protocolIEs.list.count %d\n", + in->protocolIEs.list.count); + for (int i=0;i < in->protocolIEs.list.count; i++) { + //ie = in->protocolIEs.list.array[i]; + // switch (ie->id) { + // case M2AP_ProtocolIE_ID_id_MCE_MBMS_M2AP_ID: + // AssertFatal(ie->criticality == M2AP_Criticality_reject, + // "ie->criticality != M2AP_Criticality_reject\n"); + // AssertFatal(ie->value.present == M2AP_SessionStartResponse_Ies__value_PR_MCE_MBMS_M2AP_ID, + // "ie->value.present != M2AP_sessionStartResponse_IEs__value_PR_MCE_MBMS_M2AP_ID\n"); + // MCE_MBMS_M2AP_ID=ie->value.choice.MCE_MBMS_M2AP_ID; + // LOG_D(M2AP, "M2AP: SessionStart-Resp: MCE_MBMS_M2AP_ID %d\n", + // MCE_MBMS_M2AP_ID); + // break; + // case M2AP_ProtocolIE_ID_id_ENB_MBMS_M2AP_ID: + // AssertFatal(ie->criticality == M2AP_Criticality_reject, + // "ie->criticality != M2AP_Criticality_reject\n"); + // AssertFatal(ie->value.present == M2AP_SessionStartResponse_Ies__value_PR_ENB_MBMS_M2AP_ID, + // "ie->value.present != M2AP_sessionStartResponse_Ies__value_PR_ENB_MBMS_M2AP_ID\n"); + // ENB_MBMS_M2AP_ID=ie->value.choice.ENB_MBMS_M2AP_ID; + // LOG_D(M2AP, "M2AP: SessionStart-Resp: ENB_MBMS_M2AP_ID %d\n", + // ENB_MBMS_M2AP_ID); + // break; + // } + } + + //AssertFatal(MCE_MBMS_M2AP_ID!=-1,"MCE_MBMS_M2AP_ID was not sent\n"); + //AssertFatal(ENB_MBMS_M2AP_ID!=-1,"ENB_MBMS_M2AP_ID was not sent\n"); + //M2AP_SESSION_START_RESP(msg_p). +// MSC_LOG_RX_MESSAGE( +// MSC_M2AP_MCE, +// MSC_M2AP_ENB, + //return 0; +// 0, +// 0, +// MSC_AS_TIME_FMT" MCE_handle_M2_SESSION_START_RESPONSE successfulOutcome assoc_id %d", +// 0,0,//MSC_AS_TIME_ARGS(ctxt_pP), +// assoc_id); +// + //LOG_D(M2AP, "Sending ITTI message to ENB_APP with assoc_id (%d->%d)\n", + //assoc_id,ENB_MODULE_ID_TO_INSTANCE(assoc_id)); + + itti_send_msg_to_task(TASK_MCE_APP, ENB_MODULE_ID_TO_INSTANCE(assoc_id), msg_g); + return 0; + } -int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance, - uint32_t assoc_id, - uint32_t stream, - M2AP_M2AP_PDU_t *pdu){ - AssertFatal(1==0,"Not implemented yet\n"); +int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance, module_id_t du_mod_idP){ + + M2AP_M2AP_PDU_t pdu; + M2AP_MbmsServiceCountingRequest_t *out; + M2AP_MbmsServiceCountingRequest_Ies_t *ie; + + uint8_t *buffer; + uint32_t len; + //int i=0; + //int j=0; + + /* Create */ + /* 0. pdu Type */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = M2AP_M2AP_PDU_PR_initiatingMessage; + //pdu.choice.initiatingMessage = (M2AP_InitiatingMessage_t *)calloc(1, sizeof(M2AP_InitiatingMessage_t)); + pdu.choice.initiatingMessage.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCounting; + pdu.choice.initiatingMessage.criticality = M2AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = M2AP_InitiatingMessage__value_PR_MbmsServiceCountingRequest; + out = &pdu.choice.initiatingMessage.value.choice.MbmsServiceCountingRequest; + + /* mandatory */ + /* c1. MCCH_Update_Time */ //long + ie=(M2AP_MbmsServiceCountingRequest_Ies_t *)calloc(1,sizeof(M2AP_MbmsSchedulingInformation_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_MCCH_Update_Time; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingRequest_Ies__value_PR_MCCH_Update_Time; + //ie->value.choice.MCCH_Update_Time = ; + //ie->value.choice.MCCH_Update_Time = m2ap_mbms_scheduling_information->mcch_update_time; + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + + /* mandatory */ + /* c1. MCE_MBMS_M2AP_ID (integer value) */ //long + ie = (M2AP_MbmsServiceCountingRequest_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingRequest_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_MBSFN_Area_ID; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBSFN_Area_ID; + //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //? + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + /* mandatory */ + /* c2. TMGI (integrer value) */ + ie = (M2AP_MbmsServiceCountingRequest_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingRequest_Ies_t )); + ie->id = M2AP_ProtocolIE_ID_id_MBMS_Counting_Request_Session; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBMS_Counting_Request_Session; + + //M2AP_MBMS_Counting_Request_Session_t * m2ap_mbms_counting_request_session = &ie->value.choice.MBMS_Counting_Request_Session; + + //&ie->choice.TMGI.pLMN_Identity); + //INT16_TO_OCTET_STRING(0,&ie->choice.TMGI.serviceId); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) { + LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n"); + return -1; + } + + return 0; } diff --git a/openair2/M2AP/m2ap_MCE_interface_management.h b/openair2/M2AP/m2ap_MCE_interface_management.h index 6b899e9ea2..2b1d5824af 100644 --- a/openair2/M2AP/m2ap_MCE_interface_management.h +++ b/openair2/M2AP/m2ap_MCE_interface_management.h @@ -150,10 +150,7 @@ int MCE_handle_MBMS_SESSION_UPDATE_RESPONSE(instance_t instance, uint32_t stream, M2AP_M2AP_PDU_t *pdu); -int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance, - uint32_t assoc_id, - uint32_t stream, - M2AP_M2AP_PDU_t *pdu); +int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance,module_id_t du_mod_idP); /* * Service Counting Request @@ -165,10 +162,7 @@ int MCE_handle_MBMS_SERVICE_COUNTING_RESPONSE(instance_t instance, uint32_t stream, M2AP_M2AP_PDU_t *pdu); -int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance, - uint32_t assoc_id, - uint32_t stream, - M2AP_M2AP_PDU_t *pdu); +int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance, module_id_t du_mod_idP); /* * Service Counting Results Report */ diff --git a/openair2/M2AP/m2ap_eNB.c b/openair2/M2AP/m2ap_eNB.c index 206b7cf8ca..39c769a43d 100644 --- a/openair2/M2AP/m2ap_eNB.c +++ b/openair2/M2AP/m2ap_eNB.c @@ -142,6 +142,22 @@ void m2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa sctp_new_association_resp->ulp_cnx_id); //m2ap_handle_m2_setup_message(instance_p, m2ap_enb_data_p, // sctp_new_association_resp->sctp_state == SCTP_STATE_SHUTDOWN); + + sleep(4); + int index; + /* Trying to connect to the provided list of eNB ip address */ + for (index = 0; index < instance_p->nb_m2; index++) { + //M2AP_INFO("eNB[%d] eNB id %u acting as an initiator (client)\n", + // instance_id, instance->eNB_id); + m2ap_eNB_register_eNB(instance_p, + &instance_p->target_mce_m2_ip_address[index], + &instance_p->enb_m2_ip_address, + instance_p->sctp_in_streams, + instance_p->sctp_out_streams, + instance_p->enb_port_for_M2C, + instance_p->multi_sd); + } + return; } @@ -304,6 +320,8 @@ void m2ap_eNB_handle_register_eNB(instance_t instance, DevCheck(new_instance->mcc == m2ap_register_eNB->mcc, new_instance->mcc, m2ap_register_eNB->mcc, 0); DevCheck(new_instance->mnc == m2ap_register_eNB->mnc, new_instance->mnc, m2ap_register_eNB->mnc, 0); M2AP_WARN("eNB[%d] already registered\n", instance); + + } else { new_instance = calloc(1, sizeof(m2ap_eNB_instance_t)); DevAssert(new_instance != NULL); diff --git a/openair2/M2AP/m2ap_eNB_interface_management.c b/openair2/M2AP/m2ap_eNB_interface_management.c index 95b8372025..9649d919c3 100644 --- a/openair2/M2AP/m2ap_eNB_interface_management.c +++ b/openair2/M2AP/m2ap_eNB_interface_management.c @@ -163,8 +163,12 @@ int eNB_handle_MBMS_SCHEDULING_INFORMATION(instance_t instance, M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_period = m2ap_mbsfn_sf_configuration->radioframeAllocationPeriod; M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_offset = m2ap_mbsfn_sf_configuration->radioframeAllocationOffset; if( m2ap_mbsfn_sf_configuration->subframeAllocation.present == M2AP_MBSFN_Subframe_Configuration__subframeAllocation_PR_fourFrames ) { + LOG_I(RRC,"is_four_sf\n"); + M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf = 1; M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation = m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[0] | (m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[1]<<8) | (m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[0]<<16); }else{ + LOG_I(RRC,"is_one_sf\n"); + M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf = 0; M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation = (m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[0] >> 2) & 0x3F; } } @@ -1262,46 +1266,226 @@ int eNB_handle_MBMS_SERVICE_COUNTING_REQ(instance_t instance, uint32_t stream, M2AP_M2AP_PDU_t *pdu) { - LOG_D(M2AP, "eNB_handle_MBMS_SERVICE_COUNTING_REQUEST assoc_id %d\n",assoc_id); - MessageDef *message_p; + LOG_D(M2AP, "eNB_handle_MBMS_SERVICE_COUNTING_REQUEST assoc_id %d\n",assoc_id); + + //MessageDef *message_p; //M2AP_MbmsServiceCountingRequest_t *container; //M2AP_MbmsServiceCountingRequest_Ies_t *ie; + M2AP_MbmsServiceCountingRequest_t *in; + M2AP_MbmsServiceCountingRequest_Ies_t *ie; //int i = 0; + int j; DevAssert(pdu != NULL); // container = &pdu->choice.initiatingMessage.value.choice.MbmsServiceCountingRequest; + in = &pdu->choice.initiatingMessage.value.choice.MbmsServiceCountingRequest; /* M2 Setup Request == Non UE-related procedure -> stream 0 */ if (stream != 0) { - LOG_D(M2AP, "[SCTP %d] Received MMBS session start request on stream != 0 (%d)\n", + LOG_D(M2AP, "[SCTP %d] Received MMBS service Counting Request on stream != 0 (%d)\n", assoc_id, stream); } - message_p = itti_alloc_new_message (TASK_M2AP_ENB, M2AP_MBMS_SERVICE_COUNTING_REQ); + for (j=0;j < in->protocolIEs.list.count; j++) { + ie = in->protocolIEs.list.array[j]; + switch (ie->id) { + case M2AP_ProtocolIE_ID_id_MCCH_Update_Time: + AssertFatal(ie->criticality == M2AP_Criticality_reject, + "ie->criticality != M2AP_Criticality_reject\n"); + AssertFatal(ie->value.present == M2AP_MbmsServiceCountingRequest_Ies__value_PR_MCCH_Update_Time, + "ie->value.present != M2AP_MbmsServiceCountingRequest_Ies__value_PR_MCCH_Update_Time\n"); + LOG_D(M2AP, "M2AP: : MCCH_Update_Time \n"); + break; + case M2AP_ProtocolIE_ID_id_MBSFN_Area_ID: + AssertFatal(ie->criticality == M2AP_Criticality_reject, + "ie->criticality != M2AP_Criticality_reject\n"); + AssertFatal(ie->value.present == M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBSFN_Area_ID, + "ie->value.present != M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBSFN_Area_ID\n"); + LOG_D(M2AP, "M2AP: : MBSFN_Area_ID \n"); + break; + case M2AP_ProtocolIE_ID_id_MBMS_Counting_Request_Session: + AssertFatal(ie->criticality == M2AP_Criticality_reject, + "ie->criticality != M2AP_Criticality_reject\n"); + AssertFatal(ie->value.present == M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBMS_Counting_Request_Session, + "ie->value.present != M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBMS_Counting_Request_Session\n"); + LOG_D(M2AP, "M2AP: : MBMS_Counting_Request_Session \n"); + + //ie->value.choice.MBMS_Counting_Request_Session.list.count; + + break; + + } + } - itti_send_msg_to_task(TASK_ENB_APP, ENB_MODULE_ID_TO_INSTANCE(instance), message_p); - + //message_p = itti_alloc_new_message (TASK_M2AP_ENB, M2AP_MBMS_SERVICE_COUNTING_REQ); return 0; } int eNB_send_MBMS_SERVICE_COUNTING_REPORT(instance_t instance, m2ap_mbms_service_counting_report_t * m2ap_mbms_service_counting_report) { - AssertFatal(1==0,"Not implemented yet\n"); + M2AP_M2AP_PDU_t pdu; + M2AP_MbmsServiceCountingResultsReport_t *out; + M2AP_MbmsServiceCountingResultsReport_Ies_t *ie; + + uint8_t *buffer; + uint32_t len; + //int i = 0; + // + // memset(&pdu, 0, sizeof(pdu)); + pdu.present = M2AP_M2AP_PDU_PR_initiatingMessage; + //pdu.choice.initiatingMessage = (M2AP_InitiatingMessage_t *)calloc(1, sizeof(M2AP_InitiatingMessage_t)); + pdu.choice.initiatingMessage.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCountingResultsReport; + pdu.choice.initiatingMessage.criticality = M2AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = M2AP_InitiatingMessage__value_PR_MbmsServiceCountingResultsReport; + out = &pdu.choice.initiatingMessage.value.choice.MbmsServiceCountingResultsReport; + + + /* Create */ + /* 0. Message Type */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = M2AP_M2AP_PDU_PR_initiatingMessage; + //pdu.choice.successfulOutcome = (M2AP_SuccessfulOutcome_t *)calloc(1, sizeof(M2AP_SuccessfulOutcome_t)); + pdu.choice.initiatingMessage.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCountingResultsReport; + pdu.choice.initiatingMessage.criticality = M2AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = M2AP_InitiatingMessage__value_PR_MbmsServiceCountingResultsReport; + out = &pdu.choice.initiatingMessage.value.choice.MbmsServiceCountingResultsReport; + + /* mandatory */ + /* c1. MBSFN_Area_ID (integer value) */ //long + ie = (M2AP_MbmsServiceCountingResultsReport_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingResultsReport_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_MBSFN_Area_ID; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingResultsReport_Ies__value_PR_MBSFN_Area_ID; + //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //? + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + /* mandatory */ + /* c1. MBSFN_Area_ID (integer value) */ //long + ie = (M2AP_MbmsServiceCountingResultsReport_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingResultsReport_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_MBMS_Counting_Result_List; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingResultsReport_Ies__value_PR_MBMS_Counting_Result_List; + //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //? + M2AP_MBMS_Counting_Result_List_t * m2ap_mbms_counting_result_list = &ie->value.choice.MBMS_Counting_Result_List; + + M2AP_MBMS_Counting_Result_Item_t * m2ap_mbms_counting_result_item = (M2AP_MBMS_Counting_Result_Item_t*)calloc(1,sizeof(M2AP_MBMS_Counting_Result_Item_t)); + m2ap_mbms_counting_result_item->id = M2AP_ProtocolIE_ID_id_MBMS_Counting_Result_Item; + m2ap_mbms_counting_result_item->criticality = M2AP_Criticality_reject; + m2ap_mbms_counting_result_item->value.present = M2AP_MBMS_Counting_Result_Item__value_PR_MBMS_Counting_Result; + M2AP_MBMS_Counting_Result_t * m2ap_mbms_counting_result = &m2ap_mbms_counting_result_item->value.choice.MBMS_Counting_Result; + + M2AP_TMGI_t * tmgi = &m2ap_mbms_counting_result->tmgi; + MCC_MNC_TO_PLMNID(0,0,3,&tmgi->pLMNidentity);/*instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length,*/ + uint8_t TMGI[5] = {4,3,2,1,0}; + OCTET_STRING_fromBuf(&tmgi->serviceID,(const char*)&TMGI[2],3); + + //M2AP_CountingResult_t * m2ap_counting_result = &m2ap_mbms_counting_result->countingResult; + + ASN_SEQUENCE_ADD(&m2ap_mbms_counting_result_list->list,m2ap_mbms_counting_result_item); + + + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) { + LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n"); + return -1; + } return 0; } + int eNB_send_MBMS_SERVICE_COUNTING_RESP(instance_t instance, m2ap_mbms_service_counting_resp_t * m2ap_mbms_service_counting_resp) { AssertFatal(1==0,"Not implemented yet\n"); + M2AP_M2AP_PDU_t pdu; + M2AP_MbmsServiceCountingResponse_t *out; + M2AP_MbmsServiceCountingResponse_Ies_t *ie; + + uint8_t *buffer; + uint32_t len; + //int i = 0; + + /* Create */ + /* 0. Message Type */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = M2AP_M2AP_PDU_PR_successfulOutcome; + //pdu.choice.successfulOutcome = (M2AP_SuccessfulOutcome_t *)calloc(1, sizeof(M2AP_SuccessfulOutcome_t)); + pdu.choice.successfulOutcome.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCounting; + pdu.choice.successfulOutcome.criticality = M2AP_Criticality_reject; + pdu.choice.successfulOutcome.value.present = M2AP_SuccessfulOutcome__value_PR_MbmsServiceCountingResponse; + out = &pdu.choice.successfulOutcome.value.choice.MbmsServiceCountingResponse; + + + /* mandatory */ + /* c1. MCE_MBMS_M2AP_ID (integer value) */ //long + ie = (M2AP_MbmsServiceCountingResponse_Ies_t*)calloc(1, sizeof(M2AP_MbmsServiceCountingResponse_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_MCE_MBMS_M2AP_ID; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingResponse_Ies__value_PR_CriticalityDiagnostics; + //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //? + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) { + LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n"); + return -1; + } + + return 0; return 0; } + int eNB_send_MBMS_SERVICE_COUNTING_FAILURE(instance_t instance, m2ap_mbms_service_counting_failure_t * m2ap_mbms_service_counting_failure) { - AssertFatal(1==0,"Not implemented yet\n"); + M2AP_M2AP_PDU_t pdu; + M2AP_MbmsServiceCountingFailure_t *out; + M2AP_MbmsServiceCountingFailure_Ies_t *ie; + + uint8_t *buffer; + uint32_t len; + //int i = 0; + + /* Create */ + /* 0. Message Type */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = M2AP_M2AP_PDU_PR_unsuccessfulOutcome; + //pdu.choice.successfulOutcome = (M2AP_SuccessfulOutcome_t *)calloc(1, sizeof(M2AP_SuccessfulOutcome_t)); + pdu.choice.unsuccessfulOutcome.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCounting; + pdu.choice.unsuccessfulOutcome.criticality = M2AP_Criticality_reject; + pdu.choice.unsuccessfulOutcome.value.present = M2AP_UnsuccessfulOutcome__value_PR_MbmsServiceCountingFailure; + out = &pdu.choice.unsuccessfulOutcome.value.choice.MbmsServiceCountingFailure; + + + /* mandatory */ + /* c1. MCE_MBMS_M2AP_ID (integer value) */ //long + ie = (M2AP_MbmsServiceCountingFailure_Ies_t*)calloc(1, sizeof(M2AP_MbmsServiceCountingFailure_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_ENB_MBMS_M2AP_ID; + ie->criticality = M2AP_Criticality_reject; + ie->value.present = M2AP_MbmsServiceCountingFailure_Ies__value_PR_CriticalityDiagnostics; + //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //? + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + /* mandatory */ + /* c2. Cause */ + ie = (M2AP_MbmsServiceCountingFailure_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingFailure_Ies_t)); + ie->id = M2AP_ProtocolIE_ID_id_Cause; + ie->criticality = M2AP_Criticality_ignore; + ie->value.present = M2AP_MbmsServiceCountingFailure_Ies__value_PR_Cause; + ie->value.choice.Cause.present = M2AP_Cause_PR_radioNetwork; + ie->value.choice.Cause.choice.radioNetwork = M2AP_CauseRadioNetwork_unspecified; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + + if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) { + LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n"); + return -1; + } + + return 0; } diff --git a/openair2/MCE_APP/mce_app.c b/openair2/MCE_APP/mce_app.c index 6f7454c321..817c863f7b 100644 --- a/openair2/MCE_APP/mce_app.c +++ b/openair2/MCE_APP/mce_app.c @@ -372,7 +372,8 @@ void *MCE_app_task(void *args_p) { // /* Try to register each MCE with MCE each other */ if (is_m3ap_MCE_enabled() /*&& !NODE_IS_DU(RC.rrc[0]->node_type)*/) { - ///*m3_register_mce_pending =*/ MCE_app_register_m3 (mce_id_start, mce_id_end); + ///*m3_register_mce_pending =*/ + MCE_app_register_m3 (mce_id_start, mce_id_end); } do { @@ -627,7 +628,7 @@ void *MCE_app_task(void *args_p) { //} - /*m3_register_mce_pending =*/ MCE_app_register_m3 (mce_id_start, mce_id_end); + /*m3_register_mce_pending =*/ //MCE_app_register_m3 (mce_id_start, mce_id_end); //MCE_app_send_m2ap_session_start_req(0); break; From 9e789c84be0cd6576a32215ab53039fe0b92de7c Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Wed, 22 Jul 2020 07:34:09 +0200 Subject: [PATCH 29/70] fembms: - added suppor for FeMBMS RRC sublayer / l2 interface - added primitives to build asn1 messages for FeMBMS eNB Signed-off-by: Javier Morgade --- openair2/RRC/LTE/L2_interface.c | 57 +++++++++++++++++++++++++++- openair2/RRC/LTE/L2_interface_ue.c | 17 ++++++++- openair2/RRC/LTE/MESSAGES/asn1_msg.c | 40 +++++++++++++------ 3 files changed, 100 insertions(+), 14 deletions(-) diff --git a/openair2/RRC/LTE/L2_interface.c b/openair2/RRC/LTE/L2_interface.c index 68017be85b..3917b4b5a8 100644 --- a/openair2/RRC/LTE/L2_interface.c +++ b/openair2/RRC/LTE/L2_interface.c @@ -28,6 +28,15 @@ * \email: raymond.knopp@eurecom.fr */ +/*! \file l2_interface.c + * \brief layer 2 interface, added support for FeMBMS RRC sublayer + * \author J. Morgade + * \date 2020 + * \version 1.0 + * \email: javier.morgade@ieee.org + */ + + #include "platform_types.h" #include "rrc_defs.h" #include "rrc_extern.h" @@ -65,6 +74,9 @@ mac_rrc_data_req( uint8_t Sdu_size = 0; uint8_t sfn = (uint8_t)((frameP>>2)&0xff); + uint8_t sfn_fembms = (uint8_t)((frameP>>4)&0xff); + sfn_fembms = sfn_fembms<<2; + if (LOG_DEBUGFLAG(DEBUG_RRC)) { LOG_D(RRC,"[eNB %d] mac_rrc_data_req to SRB ID=%ld\n",Mod_idP,Srb_id); } @@ -72,12 +84,14 @@ mac_rrc_data_req( eNB_RRC_INST *rrc; rrc_eNB_carrier_data_t *carrier; LTE_BCCH_BCH_Message_t *mib; + LTE_BCCH_BCH_Message_MBMS_t *mib_fembms; rrc = RC.rrc[Mod_idP]; carrier = &rrc->carrier[0]; mib = &carrier->mib; + mib_fembms = &carrier->mib_fembms; if((Srb_id & RAB_OFFSET) == BCCH_SI_MBMS){ - if (frameP%4 == 0) { + if (frameP%8 == 0) { memcpy(&buffer_pP[0], RC.rrc[Mod_idP]->carrier[CC_id].SIB1_MBMS, RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB1_MBMS); @@ -159,6 +173,22 @@ mac_rrc_data_req( return(3); } + if( (Srb_id & RAB_OFFSET ) == MIBCH_MBMS) { + mib_fembms->message.systemFrameNumber_r14.buf = &sfn_fembms; + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_BCH_Message_MBMS, + NULL, + (void *)mib_fembms, + carrier->MIB_FeMBMS, + 24); + LOG_I(RRC,"Encoded MIB MBMS for frame %d (%p), bits %lu %x,%x,%x %x bits_unused %d\n",sfn_fembms>>2,carrier->MIB_FeMBMS,enc_rval.encoded,carrier->MIB_FeMBMS[0],carrier->MIB_FeMBMS[1],carrier->MIB_FeMBMS[2],mib_fembms->message.systemFrameNumber_r14.buf[0],mib_fembms->message.systemFrameNumber_r14.bits_unused); + buffer_pP[0]=carrier->MIB_FeMBMS[0]; + buffer_pP[1]=carrier->MIB_FeMBMS[1]; + buffer_pP[2]=carrier->MIB_FeMBMS[2]; + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + return(3); + } + if( (Srb_id & RAB_OFFSET ) == CCCH) { struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti); @@ -203,6 +233,8 @@ mac_rrc_data_req( RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESSAGE[mbsfn_sync_area], RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]); + LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP); + if (LOG_DEBUGFLAG(DEBUG_RRC)) { LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP); @@ -216,6 +248,29 @@ mac_rrc_data_req( return (RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]); } + if((Srb_id & RAB_OFFSET) == MCCH_COUNTING) { + if(RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESS_COUNTING[mbsfn_sync_area].Active==0) { + return 0; // this parameter is set in function init_mcch in rrc_eNB.c + } + + memcpy(&buffer_pP[0], + RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[mbsfn_sync_area], + RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[mbsfn_sync_area]); + + if (LOG_DEBUGFLAG(DEBUG_RRC)) { + LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE_COUNTING \n",Mod_idP,frameP); + + for (int i=0; icarrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[mbsfn_sync_area]; i++) { + LOG_T(RRC,"%x.",buffer_pP[i]); + } + + LOG_T(RRC,"\n"); + } /* LOG_DEBUGFLAG(DEBUG_RRC) */ + + return (RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[mbsfn_sync_area]); + } + + if ((Srb_id & RAB_OFFSET) == BCCH_SIB1_BR) { memcpy(&buffer_pP[0], RC.rrc[Mod_idP]->carrier[CC_id].SIB1_BR, diff --git a/openair2/RRC/LTE/L2_interface_ue.c b/openair2/RRC/LTE/L2_interface_ue.c index 61ab63955d..c413df49bb 100644 --- a/openair2/RRC/LTE/L2_interface_ue.c +++ b/openair2/RRC/LTE/L2_interface_ue.c @@ -19,7 +19,7 @@ * contact@openairinterface.org */ -/*! \file l2_interface.c +/*! \file l2_interface_ue.c * \brief layer 2 interface, used to support different RRC sublayer * \author Raymond Knopp and Navid Nikaein * \date 2010-2014 @@ -28,6 +28,16 @@ * \email: raymond.knopp@eurecom.fr */ + +/*! \file l2_interface_ue.c + * \brief layer 2 interface, added support for FeMBMS RRC sublayer + * \author J. Morgade + * \date 2020 + * \version 1.0 + * \email: javier.morgade@ieee.org + */ + + #include "platform_types.h" #include "rrc_defs.h" #include "rrc_extern.h" @@ -217,7 +227,10 @@ mac_rrc_data_ind_ue( } if ((srb_idP & RAB_OFFSET) == MCCH) { - LOG_T(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n", + //LOG_T(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n", + //module_idP,frameP, mbsfn_sync_areaP, srb_idP & RAB_OFFSET,eNB_indexP); + + LOG_W(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n", module_idP,frameP, mbsfn_sync_areaP, srb_idP & RAB_OFFSET,eNB_indexP); { MessageDef *message_p; diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.c b/openair2/RRC/LTE/MESSAGES/asn1_msg.c index 583e10da94..5c5a5575fe 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.c +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.c @@ -28,6 +28,14 @@ * \email: raymond.knopp@eurecom.fr and navid.nikaein@eurecom.fr */ +/*! \file asn1_msg.c + * \brief added primitives to build the asn1 messages for FeMBMS + * \author Javier Morgade + * \date 2019-2020 + * \version 1.0 + * \email: javier.morgade@ieee.org + */ + #include #include #include /* for atoi(3) */ @@ -185,7 +193,8 @@ uint8_t get_adjacent_cell_mod_id(uint16_t phyCellId) { uint8_t do_MIB_FeMBMS(rrc_eNB_carrier_data_t *carrier, uint32_t N_RB_DL, uint32_t additionalNonMBSFN, uint32_t frame) { asn_enc_rval_t enc_rval; LTE_BCCH_BCH_Message_MBMS_t *mib_fembms=&carrier->mib_fembms; - uint8_t sfn = (uint8_t)((frame>>2)&0xff); + frame=198; + uint8_t sfn = (uint8_t)((frame>>4)&0xff); uint16_t *spare = calloc(1,sizeof(uint16_t)); if( spare == NULL ) abort(); @@ -223,15 +232,16 @@ uint8_t do_MIB_FeMBMS(rrc_eNB_carrier_data_t *carrier, uint32_t N_RB_DL, uint32_ (uint32_t)mib_fembms->message.dl_Bandwidth_MBMS_r14, (uint32_t)additionalNonMBSFN, (uint32_t)sfn); + sfn = sfn<<2; mib_fembms->message.systemFrameNumber_r14.buf = &sfn; mib_fembms->message.systemFrameNumber_r14.size = 1; - mib_fembms->message.systemFrameNumber_r14.bits_unused=0; + mib_fembms->message.systemFrameNumber_r14.bits_unused=2; mib_fembms->message.spare.buf = (uint8_t *)spare; mib_fembms->message.spare.size = 2; - mib_fembms->message.spare.bits_unused = 6; // This makes a spare of 10 bits + mib_fembms->message.spare.bits_unused = 3; // This makes a spare of 10 bits //TODO additionalNonBMSFNSubframes-r14 INTEGER (0..3) ? //if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { - //xer_fprint(stdout, &asn_DEF_LTE_BCCH_BCH_Message_MBMS, (void *)mib_fembms); + xer_fprint(stdout, &asn_DEF_LTE_BCCH_BCH_Message_MBMS, (void *)mib_fembms); //} enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_BCH_Message_MBMS, NULL, @@ -387,7 +397,11 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier, // SystemInformation_t systemInformation; int num_plmn = configuration->num_plmn; - LTE_PLMN_IdentityInfo_t *PLMN_identity_info; + //LTE_PLMN_IdentityInfo_t *PLMN_identity_info; + LTE_PLMN_IdentityInfo_t * PLMN_identity_info = &carrier->PLMN_identity_info_MBMS[0]; + //LTE_MCC_MNC_Digit_t dummy_mcc[num_plmn][3], dummy_mnc[num_plmn][3]; + //LTE_MCC_MNC_Digit_t *dummy_mcc = &carrier->dummy_mcc_MBMS[0][0]; + //LTE_MCC_MNC_Digit_t *dummy_mnc = &carrier->dummy_mnc_MBMS[0][0]; LTE_MCC_MNC_Digit_t *dummy_mcc_0; LTE_MCC_MNC_Digit_t *dummy_mcc_1; LTE_MCC_MNC_Digit_t *dummy_mcc_2; @@ -395,7 +409,9 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier, LTE_MCC_MNC_Digit_t *dummy_mnc_1; LTE_MCC_MNC_Digit_t *dummy_mnc_2; asn_enc_rval_t enc_rval; - LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo; + //LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo; + //LTE_SchedulingInfo_MBMS_r14_t schedulingInfo; + LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo = &carrier->schedulingInfo_MBMS; LTE_SIB_Type_t *sib_type; uint8_t *buffer = carrier->SIB1_MBMS; LTE_BCCH_DL_SCH_Message_MBMS_t *bcch_message = &carrier->siblock1_MBMS; @@ -408,6 +424,8 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier, // memcpy(&bcch_message.message.choice.c1.choice.systemInformationBlockType1,sib1,sizeof(SystemInformationBlockType1_t)); *sib1_MBMS = &bcch_message->message.choice.c1.choice.systemInformationBlockType1_MBMS_r14; PLMN_identity_info = CALLOC(1, sizeof(LTE_PLMN_IdentityInfo_t) * num_plmn); + //memset(&schedulingInfo,0,sizeof(LTE_SchedulingInfo_MBMS_r14_t)); + memset(schedulingInfo,0,sizeof(LTE_SchedulingInfo_MBMS_r14_t)); if (PLMN_identity_info == NULL) exit(1); @@ -528,7 +546,7 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier, MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.size= 1; MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf[0]=0x20<<2; // FDD: SF1 MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.bits_unused= 2; - MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__signallingMCS_r9_n7; + MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__signallingMCS_r9_n2; (MBSFN_Area1)->ext1 = CALLOC (1, sizeof(*(MBSFN_Area1)->ext1)); memset((MBSFN_Area1)->ext1,0,sizeof(*(MBSFN_Area1)->ext1)); MBSFN_Area1->ext1->subcarrierSpacingMBMS_r14 = CALLOC(1,sizeof(*( MBSFN_Area1->ext1)->subcarrierSpacingMBMS_r14)); @@ -541,18 +559,18 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier, if(1) { (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14 = CALLOC(1,sizeof(struct LTE_NonMBSFN_SubframeConfig_r14)); memset((*sib1_MBMS)->nonMBSFN_SubframeConfig_r14,0,sizeof(struct LTE_NonMBSFN_SubframeConfig_r14)); - (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->radioFrameAllocationPeriod_r14 = LTE_NonMBSFN_SubframeConfig_r14__radioFrameAllocationPeriod_r14_rf8; + (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->radioFrameAllocationPeriod_r14 = LTE_NonMBSFN_SubframeConfig_r14__radioFrameAllocationPeriod_r14_rf4; (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->radioFrameAllocationOffset_r14 = 0; (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf = MALLOC(2); //100000001 byte(0)=10000000 byte(1)=xxxxxxx1 - (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[0] = 0x80<<0; - (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[1] = 0x1<<7; + (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[0] = 0x8<<0; + (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[1] = 0; (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.size = 2; (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.bits_unused = 7; } //if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { - //xer_fprint(stdout, &asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS, (void *)bcch_message); + xer_fprint(stdout, &asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS, (void *)bcch_message); //} enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS, NULL, From 8f8b16a84ee2b15faec4ea13d72cfee640238ee2 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Wed, 22 Jul 2020 07:40:32 +0200 Subject: [PATCH 30/70] embms: Experimental MBMS Couting support added / 3GPP TS 36.44 (*) (*) The MBMS Counting function allows the MCE to request the eNB(s) to count and report per MBSFN area for one or more MBMS services the number of connected UEs receiving the MBMS Service or interested in receiving it. Signed-off-by: Javier Morgade --- openair2/RRC/LTE/L2_interface.c | 2 +- openair2/RRC/LTE/rrc_UE.c | 121 ++++++++- openair2/RRC/LTE/rrc_defs.h | 9 + openair2/RRC/LTE/rrc_eNB.c | 38 ++- openair2/RRC/LTE/rrc_eNB_M2AP.c | 463 ++++++++++++++++++++++++++++++-- openair3/M3AP/m3ap_MCE.c | 14 + targets/RT/USER/lte-softmodem.c | 5 +- 7 files changed, 608 insertions(+), 44 deletions(-) diff --git a/openair2/RRC/LTE/L2_interface.c b/openair2/RRC/LTE/L2_interface.c index 3917b4b5a8..fe1cbd32ef 100644 --- a/openair2/RRC/LTE/L2_interface.c +++ b/openair2/RRC/LTE/L2_interface.c @@ -30,7 +30,7 @@ /*! \file l2_interface.c * \brief layer 2 interface, added support for FeMBMS RRC sublayer - * \author J. Morgade + * \author Javier Morgade * \date 2020 * \version 1.0 * \email: javier.morgade@ieee.org diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 4116f5367e..5955c2221c 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -150,14 +150,19 @@ static uint8_t check_trigger_meas_event( LTE_Q_OffsetRange_t ofs, LTE_Q_OffsetRange_t ocs, long a3_offset, LTE_TimeToTrigger_t ttt); static void decode_MBSFNAreaConfiguration(module_id_t module_idP, uint8_t eNB_index, frame_t frameP,uint8_t mbsfn_sync_area); +static void decode_MBMSCountingRequest(module_id_t module_idP, uint8_t eNB_index, frame_t frameP,uint8_t mbsfn_sync_area); + uint8_t rrc_ue_generate_SidelinkUEInformation( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index,LTE_SL_DestinationInfoList_r12_t *destinationInfoList, long *discTxResourceReq, SL_TRIGGER_t mode); - - - - - +void +rrc_ue_process_MBMSCountingRequest( + const protocol_ctxt_t *const ctxt_pP, + LTE_MBMSCountingRequest_r10_t *MBMSCountingRequest, + uint8_t eNB_index + ); + +protocol_ctxt_t ctxt_pP_local; /*------------------------------------------------------------------------------*/ @@ -510,6 +515,7 @@ static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *c LOG_D(RLC, "[FRAME %05d][RRC_UE][MOD %02d][][--- PDCP_DATA_REQ/%d Bytes (RRCConnectionSetupComplete to eNB %d MUI %d) --->][PDCP][MOD %02d][RB %02d]\n", ctxt_pP->frame, ctxt_pP->module_id+NB_eNB_INST, size, eNB_index, rrc_mui, ctxt_pP->module_id+NB_eNB_INST, DCCH); + ctxt_pP_local.rnti = ctxt_pP->rnti; rrc_data_req_ue ( ctxt_pP, DCCH, @@ -1561,6 +1567,65 @@ rrc_ue_process_securityModeCommand( securityModeCommand->criticalExtensions.present); } +void +rrc_ue_process_MBMSCountingRequest( + const protocol_ctxt_t *const ctxt_pP, + LTE_MBMSCountingRequest_r10_t *MBMSCountingRequest, + uint8_t eNB_index +) +{ + asn_enc_rval_t enc_rval; + LTE_UL_DCCH_Message_t ul_dcch_msg; + struct LTE_CountingResponseInfo_r10 CountingResponse; + uint8_t buffer[200]; + //int i; + LOG_I(RRC,"[UE %d] Frame %d: Receiving from (MCCH), Processing MBMSCoutingRequest (eNB %d)\n", + ctxt_pP->module_id, + ctxt_pP->frame, + eNB_index); + memset((void *)&ul_dcch_msg,0,sizeof(LTE_UL_DCCH_Message_t)); + memset((void *)&CountingResponse,0,sizeof(struct LTE_CountingResponseInfo_r10)); + + + ul_dcch_msg.message.present = LTE_UL_DCCH_MessageType_PR_c1; + ul_dcch_msg.message.choice.c1.present = LTE_UL_DCCH_MessageType__c1_PR_mbmsCountingResponse_r10; + LTE_MBMSCountingResponse_r10_t *MBMSCountingResponse = &ul_dcch_msg.message.choice.c1.choice.mbmsCountingResponse_r10; + + MBMSCountingResponse->criticalExtensions.present = LTE_MBMSCountingResponse_r10__criticalExtensions_PR_c1; + MBMSCountingResponse->criticalExtensions.choice.c1.present = LTE_MBMSCountingResponse_r10__criticalExtensions__c1_PR_countingResponse_r10; + LTE_MBMSCountingResponse_r10_IEs_t *MBMSCountingResponse_r10_IEs = &MBMSCountingResponse->criticalExtensions.choice.c1.choice.countingResponse_r10; + + MBMSCountingResponse_r10_IEs->mbsfn_AreaIndex_r10 = calloc(1,sizeof(long)); + // MBMSCountingResponse_r10_IEs->countingResponseList_r10 = calloc(1,sizeof(struct LTE_CountingResponseList_r10)); +// +// ASN_SEQUENCE_ADD( +// &MBMSCountingResponse->criticalExtensions.choice.c1.choice.countingResponse_r10.countingResponseList_r10.list, +// &CountingResponse); +// + + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UL_DCCH_Message, NULL, (void *) &ul_dcch_msg, buffer, 100); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + + if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)&ul_dcch_msg); + } + xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)&ul_dcch_msg); + + + LOG_I(RRC,"MBMSCountingResponse Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8); + rrc_data_req_ue ( + &ctxt_pP_local, + DCCH, + rrc_mui++, + SDU_CONFIRM_NO, + (enc_rval.encoded + 7) / 8, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); + +} + + //----------------------------------------------------------------------------- void rrc_ue_process_ueCapabilityEnquiry( @@ -2178,8 +2243,8 @@ rrc_ue_decode_dcch( #endif } -const char siWindowLength[8][5] = {"1ms","2ms","5ms","10ms","15ms","20ms","40ms","ERR"}; -const char siWindowLength_int[7] = {1,2,5,10,15,20,40}; +const char siWindowLength[9][5] = {"1ms","2ms","5ms","10ms","15ms","20ms","40ms","80ms","ERR"}; +const char siWindowLength_int[8] = {1,2,5,10,15,20,40,80}; const char SIBType[12][6] = {"SIB3","SIB4","SIB5","SIB6","SIB7","SIB8","SIB9","SIB10","SIB11","SIB12","SIB13","Spare"}; const char SIBPeriod[8][6]= {"rf8","rf16","rf32","rf64","rf128","rf256","rf512","ERR"}; @@ -2689,7 +2754,7 @@ int decode_SIB1_MBMS( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_in //LOG_I( RRC, "TDD subframeAssignment : %ld\n", sib1_MBMS->tdd_Config->subframeAssignment ); //LOG_I( RRC, "TDD specialSubframePatterns : %ld\n", sib1_MBMS->tdd_Config->specialSubframePatterns ); //} - LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1_MBMS->si_WindowLength_r14,7)] ); + LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1_MBMS->si_WindowLength_r14,8)] ); LOG_I( RRC, "systemInfoValueTag : %ld\n", sib1_MBMS->systemInfoValueTag_r14 ); UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIperiod_MBMS = siPeriod_int[sib1_MBMS->schedulingInfoList_MBMS_r14.list.array[0]->si_Periodicity_r14]; UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIwindowsize_MBMS = siWindowLength_int[sib1_MBMS->si_WindowLength_r14]; @@ -2888,7 +2953,7 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, LOG_I( RRC, "TDD specialSubframePatterns : %ld\n", sib1->tdd_Config->specialSubframePatterns ); } - LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1->si_WindowLength,7)] ); + LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1->si_WindowLength,8)] ); LOG_I( RRC, "systemInfoValueTag : %ld\n", sib1->systemInfoValueTag ); UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIperiod = siPeriod_int[sib1->schedulingInfoList.list.array[0]->si_Periodicity]; UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIwindowsize = siWindowLength_int[sib1->si_WindowLength]; @@ -4205,12 +4270,12 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB asn_dec_rval_t dec_rval; if (UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].MCCHStatus[mbsfn_sync_area] == 1) { - LOG_D(RRC,"[UE %d] Frame %d: MCCH MESSAGE for MBSFN sync area %d has been already received!\n", + LOG_W(RRC,"[UE %d] Frame %d: MCCH MESSAGE for MBSFN sync area %d has been already received!\n", ctxt_pP->module_id, ctxt_pP->frame, mbsfn_sync_area); return 0; // avoid decoding to prevent memory bloating - } else if(UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State >= RRC_CONNECTED /*|| UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State == RRC_RECONFIGURED*/){ + } else if(1/*UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State >= RRC_CONNECTED*/ /*|| UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State == RRC_RECONFIGURED*/){ dec_rval = uper_decode_complete(NULL, &asn_DEF_LTE_MCCH_Message, (void **)&mcch, @@ -4229,6 +4294,7 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { xer_fprint(stdout, &asn_DEF_LTE_MCCH_Message, (void *)mcch); } + xer_fprint(stdout, &asn_DEF_LTE_MCCH_Message, (void *)mcch); if (mcch->message.present == LTE_MCCH_MessageType_PR_c1) { LOG_D(RRC,"[UE %d] Found mcch message \n", @@ -4250,7 +4316,29 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB ctxt_pP->frame, mbsfn_sync_area); } + }else if(mcch->message.present == LTE_MCCH_MessageType_PR_later){ + LOG_D(RRC,"[UE %d] Found mcch message \n", + ctxt_pP->module_id); + if(mcch->message.choice.later.present == LTE_MCCH_MessageType__later_PR_c2){ + if(mcch->message.choice.later.choice.c2.present == LTE_MCCH_MessageType__later__c2_PR_mbmsCountingRequest_r10){ + LOG_I(RRC,"[UE %d] Frame %d : Found MBMSCountingRequest from eNB %d %p\n", + ctxt_pP->module_id, + ctxt_pP->frame, + eNB_index,&mcch->message.choice.later.choice.c2.choice.mbmsCountingRequest_r10); + + rrc_ue_process_MBMSCountingRequest(ctxt_pP,&mcch->message.choice.later.choice.c2.choice.mbmsCountingRequest_r10,eNB_index); + + decode_MBMSCountingRequest( + ctxt_pP->module_id, + eNB_index, + ctxt_pP->frame, + mbsfn_sync_area); + + + } + } } + } return 0; @@ -4308,7 +4396,7 @@ void decode_MBSFNAreaConfiguration( module_id_t ue_mod_idP, uint8_t eNB_index, f (struct LTE_NonMBSFN_SubframeConfig_r14 *)NULL, (LTE_MBSFN_AreaInfoList_r9_t *)NULL ); - if(UE_rrc_inst[ue_mod_idP].Info[eNB_index].State >= RRC_CONNECTED /*|| UE_rrc_inst[ue_mod_idP].Info[eNB_index].State == RRC_RECONFIGURED*/) + if(1/*UE_rrc_inst[ue_mod_idP].Info[eNB_index].State >= RRC_CONNECTED*/ /*|| UE_rrc_inst[ue_mod_idP].Info[eNB_index].State == RRC_RECONFIGURED*/) UE_rrc_inst[ue_mod_idP].Info[eNB_index].MCCHStatus[mbsfn_sync_area] = 1; PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, ue_mod_idP, ENB_FLAG_NO, UE_rrc_inst[ue_mod_idP].Info[eNB_index].rnti, frameP, 0,eNB_index); // Config Radio Bearer for MBMS user data (similar way to configure for eNB side in init_MBMS function) @@ -4332,6 +4420,13 @@ void decode_MBSFNAreaConfiguration( module_id_t ue_mod_idP, uint8_t eNB_index, f // */ } +void decode_MBMSCountingRequest( module_id_t ue_mod_idP, uint8_t eNB_index, frame_t frameP, uint8_t mbsfn_sync_area ) { + //uint8_t i; + //protocol_ctxt_t ctxt; + + + +} //----------------------------------------------------------------------------- void *rrc_ue_task( void *args_p ) { @@ -4429,7 +4524,7 @@ void *rrc_ue_task( void *args_p ) { break; case RRC_MAC_MCCH_DATA_IND: - LOG_D(RRC, "[UE %d] Received %s: frameP %d, eNB %d, mbsfn SA %d\n", ue_mod_id, ITTI_MSG_NAME (msg_p), + LOG_W(RRC, "[UE %d] Received %s: frameP %d, eNB %d, mbsfn SA %d\n", ue_mod_id, ITTI_MSG_NAME (msg_p), RRC_MAC_MCCH_DATA_IND (msg_p).frame, RRC_MAC_MCCH_DATA_IND (msg_p).enb_index, RRC_MAC_MCCH_DATA_IND (msg_p).mbsfn_sync_area); //PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, instance, ENB_FLAG_NO, M_RNTI, RRC_MAC_MCCH_DATA_IND (msg_p).frame, 0); PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, ue_mod_id, ENB_FLAG_NO, M_RNTI, RRC_MAC_MCCH_DATA_IND (msg_p).frame, 0,RRC_MAC_MCCH_DATA_IND (msg_p).enb_index); diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index 42fa5f6de1..f3380a054e 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -715,6 +715,9 @@ typedef struct { LTE_BCCH_BCH_Message_MBMS_t mib_fembms; LTE_BCCH_DL_SCH_Message_MBMS_t siblock1_MBMS; LTE_BCCH_DL_SCH_Message_MBMS_t systemInformation_MBMS; + LTE_SchedulingInfo_MBMS_r14_t schedulingInfo_MBMS; + LTE_PLMN_IdentityInfo_t PLMN_identity_info_MBMS[6]; + LTE_MCC_MNC_Digit_t dummy_mcc_MBMS[6][3], dummy_mnc_MBMS[6][3]; LTE_SystemInformationBlockType1_t *sib1; LTE_SystemInformationBlockType2_t *sib2; LTE_SystemInformationBlockType3_t *sib3; @@ -731,6 +734,12 @@ typedef struct { LTE_MCCH_Message_t mcch; LTE_MBSFNAreaConfiguration_r9_t *mcch_message; SRB_INFO MCCH_MESS[8];// MAX_MBSFN_AREA + uint8_t **MCCH_MESSAGE_COUNTING; // MAX_MBSFN_AREA + uint8_t sizeof_MCCH_MESSAGE_COUNTING[8];// MAX_MBSFN_AREA + LTE_MCCH_Message_t mcch_counting; + LTE_MBMSCountingRequest_r10_t *mcch_message_counting; + SRB_INFO MCCH_MESS_COUNTING[8];// MAX_MBSFN_AREA + //TTN - SIB 18,19,21 for D2D LTE_SystemInformationBlockType18_r12_t *sib18; LTE_SystemInformationBlockType19_r12_t *sib19; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 08c322f9b8..b665555b5d 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -155,6 +155,7 @@ init_SI( LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__); if(configuration->radioresourceconfig[CC_id].mbms_dedicated_serving_cell == TRUE) { + LOG_I(RRC, "Configuring MIB FeMBMS (N_RB_DL %d)\n", (int)configuration->N_RB_DL[CC_id]); RC.rrc[ctxt_pP->module_id]->carrier[CC_id].MIB_FeMBMS = (uint8_t *) malloc16(4); @@ -231,6 +232,7 @@ init_SI( RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sib1_MBMS->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf); } + RC.rrc[ctxt_pP->module_id]->carrier[CC_id].FeMBMS_flag=1; //AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1 != 255,"FATAL, RC.rrc[enb_mod_idP].carrier[CC_id].sizeof_SIB1 == 255"); } @@ -496,12 +498,15 @@ init_SI( (LTE_PMCH_InfoList_r9_t *) NULL, sib1_v13ext, RC.rrc[ctxt_pP->module_id]->carrier[CC_id].FeMBMS_flag, - (LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL, + (carrier->sib1_MBMS==NULL?(LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL:(LTE_BCCH_DL_SCH_Message_MBMS_t *)carrier->sib1_MBMS),//(LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL, (LTE_SchedulingInfo_MBMS_r14_t *) NULL, - (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, - (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL - ); + (carrier->sib1_MBMS==NULL?(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL:(struct LTE_NonMBSFN_SubframeConfig_r14 *)carrier->sib1_MBMS->nonMBSFN_SubframeConfig_r14),//(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, + (carrier->sib1_MBMS==NULL?(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL:(LTE_SystemInformationBlockType1_MBMS_r14_t *)carrier->sib1_MBMS->systemInformationBlockType13_r14),//(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, + (carrier->sib1_MBMS==NULL?(LTE_MBSFN_AreaInfoList_r9_t *) NULL:(LTE_MBSFN_AreaInfoList_r9_t *)&carrier->sib1_MBMS->systemInformationBlockType13_r14->mbsfn_AreaInfoList_r9)//(LTE_MBSFN_AreaInfoList_r9_t *) NULL + + ,(LTE_MBSFNAreaConfiguration_r9_t*) NULL + + ); } /* set flag to indicate that cell information is configured. This is required @@ -584,7 +589,8 @@ init_MCCH( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } @@ -1458,7 +1464,8 @@ rrc_eNB_generate_RRCConnectionReestablishment( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); break; } @@ -5759,7 +5766,8 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); // Configure target eNB SRB2 /// SRB2 @@ -6439,7 +6447,8 @@ rrc_eNB_configure_rbs_handover(struct rrc_eNB_ue_context_s *ue_context_p, protoc (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } @@ -6655,7 +6664,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } } else { // remove LCHAN from MAC/PHY @@ -6714,7 +6724,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } } // end else of if (ue_context_pP->ue_context.DRB_active[drb_id] == 0) @@ -6876,7 +6887,8 @@ rrc_eNB_generate_RRCConnectionSetup( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); break; } @@ -8352,6 +8364,8 @@ rrc_eNB_decode_dcch( case LTE_UL_DCCH_MessageType__c1_PR_mbmsCountingResponse_r10: T(T_ENB_RRC_MBMS_COUNTING_RESPONSE_R10, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); + LOG_E(RRC, "THINH [LTE_UL_DCCH_MessageType__c1_PR_mbmsCountingResponse_r10]\n"); + break; case LTE_UL_DCCH_MessageType__c1_PR_interFreqRSTDMeasurementIndication_r10: diff --git a/openair2/RRC/LTE/rrc_eNB_M2AP.c b/openair2/RRC/LTE/rrc_eNB_M2AP.c index bd586dfc71..98a72895a0 100644 --- a/openair2/RRC/LTE/rrc_eNB_M2AP.c +++ b/openair2/RRC/LTE/rrc_eNB_M2AP.c @@ -63,6 +63,71 @@ rrc_M2AP_openair_rrc_top_init_MBMS(int eMBMS_active){ } +static uint8_t rrc_M2AP_do_MBSFNCountingRequest( + uint8_t Mod_id, + uint8_t sync_area, + uint8_t *buffer, + LTE_MCCH_Message_t *mcch_message, + LTE_MBMSCountingRequest_r10_t **mbsfnCoutingRequest, + const m2ap_mbms_service_counting_req_t *const m2ap_mbms_service_counting_req +) { + //int i,j,k; + + asn_enc_rval_t enc_rval; + //LTE_MBSFN_SubframeConfig_t *mbsfn_SubframeConfig1; + //LTE_PMCH_Info_r9_t *pmch_Info_1; + //LTE_MBMS_SessionInfo_r9_t *mbms_Session_1; + // MBMS_SessionInfo_r9_t *mbms_Session_2; + //eNB_RRC_INST *rrc = RC.rrc[Mod_id]; + //rrc_eNB_carrier_data_t *carrier = &rrc->carrier[0]; + memset(mcch_message,0,sizeof(LTE_MCCH_Message_t)); + //mcch_message->message.present = LTE_MCCH_MessageType_PR_c1; + mcch_message->message.present = LTE_MCCH_MessageType_PR_later; + //mcch_message->message.choice.c1.present = LTE_MCCH_MessageType__c1_PR_mbsfnAreaConfiguration_r9; + mcch_message->message.choice.later.present = LTE_MCCH_MessageType__later_PR_c2; + mcch_message->message.choice.later.choice.c2.present = LTE_MCCH_MessageType__later__c2_PR_mbmsCountingRequest_r10; + *mbsfnCoutingRequest = &mcch_message->message.choice.later.choice.c2.choice.mbmsCountingRequest_r10; + + + //LTE_CountingRequestList_r10_t countingRequestList_r10; // A_SEQUENCE_OF(struct LTE_CountingRequestInfo_r10) list; + struct LTE_CountingRequestInfo_r10 *lte_counting_request_info; //LTE_TMGI_r9_t tmgi_r10; + lte_counting_request_info = CALLOC(1,sizeof(struct LTE_CountingRequestInfo_r10)); + uint8_t TMGI[5] = {4,3,2,1,0}; + lte_counting_request_info->tmgi_r10.plmn_Id_r9.present = LTE_TMGI_r9__plmn_Id_r9_PR_plmn_Index_r9; + lte_counting_request_info->tmgi_r10.plmn_Id_r9.choice.plmn_Index_r9= 1; + memset(<e_counting_request_info->tmgi_r10.serviceId_r9,0,sizeof(OCTET_STRING_t)); + OCTET_STRING_fromBuf(<e_counting_request_info->tmgi_r10.serviceId_r9,(const char*)&TMGI[2],3); + ASN_SEQUENCE_ADD(&(*mbsfnCoutingRequest)->countingRequestList_r10.list,lte_counting_request_info); + + if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + xer_fprint(stdout,&asn_DEF_LTE_MCCH_Message,(void *)mcch_message); + } + + xer_fprint(stdout,&asn_DEF_LTE_MCCH_Message,(void *)mcch_message); + + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_MCCH_Message, + NULL, + (void *)mcch_message, + buffer, + 100); + + if(enc_rval.encoded == -1) { + LOG_I(RRC, "[eNB AssertFatal]ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + return -1; + } + + LOG_I(RRC,"[eNB] MCCH Message Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8); + + if (enc_rval.encoded==-1) { + msg("[RRC] ASN1 : MCCH encoding failed for MBSFNAreaConfiguration\n"); + return(-1); + } + + return((enc_rval.encoded+7)/8); + +} + static uint8_t rrc_M2AP_do_MBSFNAreaConfig( uint8_t Mod_id, @@ -96,6 +161,7 @@ static uint8_t rrc_M2AP_do_MBSFNAreaConfig( mbsfn_SubframeConfig1->radioframeAllocationPeriod= m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_period;//LTE_MBSFN_SubframeConfig__radioframeAllocationPeriod_n4; mbsfn_SubframeConfig1->radioframeAllocationOffset= m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_offset; if(m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf){ + LOG_I(RRC,"is_four_sf\n"); mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames; mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3); mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation) & 0xFF); @@ -106,6 +172,7 @@ static uint8_t rrc_M2AP_do_MBSFNAreaConfig( }else { + LOG_I(RRC,"is_one_sf\n"); mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame; mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1); mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1; @@ -128,7 +195,8 @@ static uint8_t rrc_M2AP_do_MBSFNAreaConfig( */ pmch_Info_1->pmch_Config_r9.sf_AllocEnd_r9= m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].allocated_sf_end; pmch_Info_1->pmch_Config_r9.dataMCS_r9= m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].data_mcs; - pmch_Info_1->pmch_Config_r9.mch_SchedulingPeriod_r9= LTE_PMCH_Config_r9__mch_SchedulingPeriod_r9_rf16; + //pmch_Info_1->pmch_Config_r9.mch_SchedulingPeriod_r9= LTE_PMCH_Config_r9__mch_SchedulingPeriod_r9_rf16; + pmch_Info_1->pmch_Config_r9.mch_SchedulingPeriod_r9 = m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].mch_scheduling_period; // MBMSs-SessionInfoList-r9 for(k=0; k < m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].num_mbms_session_list; k++){ // pmch_Info_1->mbms_SessionInfoList_r9 = CALLOC(1,sizeof(struct MBMS_SessionInfoList_r9)); @@ -240,6 +308,9 @@ static void rrc_M2AP_init_MCCH( RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE = malloc(RC.rrc[enb_mod_idP]->carrier[CC_id].num_mbsfn_sync_area * sizeof(uint8_t *)); + + RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING = + malloc(RC.rrc[enb_mod_idP]->carrier[CC_id].num_mbsfn_sync_area * sizeof(uint8_t *)); for (sync_area = 0; sync_area < RC.rrc[enb_mod_idP]->carrier[CC_id].num_mbsfn_sync_area; sync_area++) { RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] = 0; @@ -253,6 +324,20 @@ static void rrc_M2AP_init_MCCH( &RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message, m2ap_mbms_scheduling_information ); + + RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[sync_area] = 0; + RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[sync_area] = (uint8_t *) malloc16(32); + AssertFatal(RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[sync_area] != NULL, + "[eNB %d]init_MCCH: FATAL, no memory for MCCH MESSAGE allocated \n", enb_mod_idP); + + RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[sync_area] = rrc_M2AP_do_MBSFNCountingRequest(enb_mod_idP, + sync_area, + (uint8_t *)RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[sync_area], + &RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_counting, + &RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message_counting, + NULL//m2ap_mbms_scheduling_information + ); + LOG_I(RRC, "mcch message pointer %p for sync area %d \n", RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE[sync_area], sync_area); @@ -269,6 +354,8 @@ static void rrc_M2AP_init_MCCH( AssertFatal(RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] != 255, "RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] == 255"); RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESS[sync_area].Active = 1; + + RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESS_COUNTING[sync_area].Active = 1; } @@ -297,17 +384,348 @@ static void rrc_M2AP_init_MCCH( (LTE_MBSFN_AreaInfoList_r9_t *) NULL, (LTE_PMCH_InfoList_r9_t *) & (RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message->pmch_InfoList_r9), (LTE_SystemInformationBlockType1_v1310_IEs_t *)NULL, - 0, - (LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL, - (LTE_SchedulingInfo_MBMS_r14_t *) NULL, - (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, - (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + 0, + (LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL, + (LTE_SchedulingInfo_MBMS_r14_t *) NULL, + (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, + (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*)(RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message) ); } return; } + + +static uint8_t rrc_M2AP_do_SIB1_MBMS_SIB13( + const protocol_ctxt_t *const ctxt_pP, + uint8_t Mod_id, + int CC_id, + const m2ap_setup_resp_t *const m2ap_setup_resp, + const m2ap_mbms_scheduling_information_t *const m2ap_mbms_scheduling_information +){ + + int i,j,l; + + eNB_RRC_INST *rrc = RC.rrc[ctxt_pP->module_id]; + rrc_eNB_carrier_data_t *carrier=&rrc->carrier[CC_id]; + + + struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member *sib13_part=NULL; + LTE_MBSFN_SubframeConfigList_t *MBSFNSubframeConfigList/*,*MBSFNSubframeConfigList_copy*/; + + asn_enc_rval_t enc_rval; + + LTE_BCCH_DL_SCH_Message_t *bcch_message = &RC.rrc[Mod_id]->carrier[CC_id].systemInformation; + LTE_BCCH_DL_SCH_Message_MBMS_t *bcch_message_fembms = &RC.rrc[Mod_id]->carrier[CC_id].siblock1_MBMS; + uint8_t *buffer; + uint8_t *buffer_fembms; + LTE_SystemInformationBlockType2_t **sib2; + + + LTE_MBSFN_AreaInfoList_r9_t *MBSFNArea_list/*,*MBSFNArea_list_copy*/; + LTE_SystemInformationBlockType13_r9_t **sib13 = &RC.rrc[Mod_id]->carrier[CC_id].sib13; + struct LTE_MBSFN_AreaInfo_r9 *MBSFN_Area1; + + LTE_SystemInformationBlockType1_MBMS_r14_t **sib1_MBMS = &RC.rrc[Mod_id]->carrier[CC_id].sib1_MBMS; + + + + if(ctxt_pP->brOption){ + buffer = RC.rrc[Mod_id]->carrier[CC_id].SIB23_BR; + sib2 = &RC.rrc[Mod_id]->carrier[CC_id].sib2_BR; + LOG_I(RRC,"Running SIB2/3 Encoding for eMTC\n"); + + + }else + { + buffer = RC.rrc[Mod_id]->carrier[CC_id].SIB23; + sib2 = &RC.rrc[Mod_id]->carrier[CC_id].sib2; + } + + buffer_fembms = RC.rrc[Mod_id]->carrier[CC_id].SIB1_MBMS; + + + if (bcch_message) { + //memset(bcch_message,0,sizeof(LTE_BCCH_DL_SCH_Message_t)); + } else { + LOG_E(RRC,"[eNB %d] BCCH_MESSAGE is null, exiting\n", Mod_id); + exit(-1); + } + + if (!sib2) { + LOG_E(RRC,"[eNB %d] sib2 is null, exiting\n", Mod_id); + exit(-1); + } + + if(!sib13){ + LOG_I(RRC,"[eNB %d] sib13 is null, it should get created\n",Mod_id); + } + + + if(!sib1_MBMS){ + LOG_I(RRC,"[eNB %d] sib1_MBMS is null, it should get created\n",Mod_id); + } + + //if (!sib3) { + // LOG_E(RRC,"[eNB %d] sib3 is null, exiting\n", Mod_id); + // exit(-1); + //} + + for (i=0; i < bcch_message->message.choice.c1.choice.systemInformation.criticalExtensions.choice.systemInformation_r8.sib_TypeAndInfo.list.count; i++) { + struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member *typeandinfo; + typeandinfo = bcch_message->message.choice.c1.choice.systemInformation.criticalExtensions.choice.systemInformation_r8.sib_TypeAndInfo.list.array[i]; + switch(typeandinfo->present) { + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_NOTHING: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib3: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib4: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib5: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib6: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib7: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib8: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib9: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib10: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib11: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib12_v920: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib13_v920: + *sib13=&typeandinfo->choice.sib13_v920; + (*sib13)->notificationConfig_r9.notificationRepetitionCoeff_r9=LTE_MBMS_NotificationConfig_r9__notificationRepetitionCoeff_r9_n2; + (*sib13)->notificationConfig_r9.notificationOffset_r9=0; + (*sib13)->notificationConfig_r9.notificationSF_Index_r9=1; + // MBSFN-AreaInfoList + MBSFNArea_list= &(*sib13)->mbsfn_AreaInfoList_r9;//CALLOC(1,sizeof(*MBSFNArea_list)); + memset(MBSFNArea_list,0,sizeof(*MBSFNArea_list)); + + for( j=0; j < m2ap_setup_resp->num_mcch_config_per_mbsfn; j++){ + // MBSFN Area 1 + MBSFN_Area1= CALLOC(1, sizeof(*MBSFN_Area1)); + MBSFN_Area1->mbsfn_AreaId_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].mbsfn_area; + MBSFN_Area1->non_MBSFNregionLength= m2ap_setup_resp->mcch_config_per_mbsfn[j].pdcch_length; + MBSFN_Area1->notificationIndicator_r9= 0; + MBSFN_Area1->mcch_Config_r9.mcch_RepetitionPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].repetition_period;//LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__mcch_RepetitionPeriod_r9_rf32; + MBSFN_Area1->mcch_Config_r9.mcch_Offset_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].offset; // in accordance with mbsfn subframe configuration in sib2 + MBSFN_Area1->mcch_Config_r9.mcch_ModificationPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].modification_period; + + // Subframe Allocation Info + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf= MALLOC(1); + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.size= 1; + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf[0]=m2ap_setup_resp->mcch_config_per_mbsfn[j].subframe_allocation_info<<2; // FDD: SF1 + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.bits_unused= 2; + MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].mcs; + ASN_SEQUENCE_ADD(&MBSFNArea_list->list,MBSFN_Area1); + } + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib14_v1130: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib15_v1130: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib16_v1130: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib17_v1250: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib18_v1250: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib19_v1250: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib20_v1310: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib21_v1430: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib24_v1530: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib25_v1530: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib26_v1530: + break; + case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib2: + + LOG_I(RRC,"Adding MBSFN subframe Configuration 1 to SIB2, %p %p\n",&typeandinfo->choice.sib2,*sib2); + + for(j=0; j < m2ap_mbms_scheduling_information->num_mbms_area_config_list ; j++) { + + (&typeandinfo->choice.sib2)->mbsfn_SubframeConfigList = CALLOC(1,sizeof(struct LTE_MBSFN_SubframeConfigList)); + MBSFNSubframeConfigList = (&typeandinfo->choice.sib2)->mbsfn_SubframeConfigList; + + for(l=0; l < m2ap_mbms_scheduling_information->mbms_area_config_list[j].num_mbms_sf_config_list; l++){ + LTE_MBSFN_SubframeConfig_t *sib2_mbsfn_SubframeConfig1; + sib2_mbsfn_SubframeConfig1= CALLOC(1,sizeof(*sib2_mbsfn_SubframeConfig1)); + memset((void *)sib2_mbsfn_SubframeConfig1,0,sizeof(*sib2_mbsfn_SubframeConfig1)); + + sib2_mbsfn_SubframeConfig1->radioframeAllocationPeriod = m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].radioframe_allocation_period; + sib2_mbsfn_SubframeConfig1->radioframeAllocationOffset = m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].radioframe_allocation_offset; + + + if(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].is_four_sf){ + LOG_I(RRC,"is_four_sf\n"); + sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames; + + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 3; + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 0; + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation) & 0xFF); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>8) & 0xFF); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>16) & 0xFF); + + }else{ + LOG_I(RRC,"is_one_sf\n"); + sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame; + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1; + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 2; + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation<<2); + + + } + + ASN_SEQUENCE_ADD(&MBSFNSubframeConfigList->list,sib2_mbsfn_SubframeConfig1); + } + } + + break; + + } + } + + + if(*sib13==NULL){ + sib13_part = CALLOC(1,sizeof(struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member)); + memset(sib13_part,0,sizeof(struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member)); + sib13_part->present = LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib13_v920; + + *sib13 = &sib13_part->choice.sib13_v920; + + (*sib13)->notificationConfig_r9.notificationRepetitionCoeff_r9=LTE_MBMS_NotificationConfig_r9__notificationRepetitionCoeff_r9_n2; + (*sib13)->notificationConfig_r9.notificationOffset_r9=0; + (*sib13)->notificationConfig_r9.notificationSF_Index_r9=1; + + // MBSFN-AreaInfoList + MBSFNArea_list= &(*sib13)->mbsfn_AreaInfoList_r9;//CALLOC(1,sizeof(*MBSFNArea_list)); + memset(MBSFNArea_list,0,sizeof(*MBSFNArea_list)); + + for( i=0; i < m2ap_setup_resp->num_mcch_config_per_mbsfn; i++){ + // MBSFN Area 1 + MBSFN_Area1= CALLOC(1, sizeof(*MBSFN_Area1)); + MBSFN_Area1->mbsfn_AreaId_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].mbsfn_area; + MBSFN_Area1->non_MBSFNregionLength= m2ap_setup_resp->mcch_config_per_mbsfn[i].pdcch_length; + MBSFN_Area1->notificationIndicator_r9= 0; + MBSFN_Area1->mcch_Config_r9.mcch_RepetitionPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].repetition_period;//LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__mcch_RepetitionPeriod_r9_rf32; + MBSFN_Area1->mcch_Config_r9.mcch_Offset_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].offset; // in accordance with mbsfn subframe configuration in sib2 + MBSFN_Area1->mcch_Config_r9.mcch_ModificationPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].modification_period; + + // Subframe Allocation Info + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf= MALLOC(1); + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.size= 1; + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf[0]=m2ap_setup_resp->mcch_config_per_mbsfn[i].subframe_allocation_info<<2; // FDD: SF1 + MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.bits_unused= 2; + MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].mcs; + ASN_SEQUENCE_ADD(&MBSFNArea_list->list,MBSFN_Area1); + } + + ASN_SEQUENCE_ADD(&bcch_message->message.choice.c1.choice.systemInformation.criticalExtensions.choice.systemInformation_r8.sib_TypeAndInfo.list, sib13_part); + + } + + *sib1_MBMS = &bcch_message_fembms->message.choice.c1.choice.systemInformationBlockType1_MBMS_r14; + + + if((*sib1_MBMS)->systemInformationBlockType13_r14==NULL){ + (*sib1_MBMS)->systemInformationBlockType13_r14 = CALLOC(1,sizeof(struct LTE_SystemInformationBlockType13_r9)); + memset((*sib1_MBMS)->systemInformationBlockType13_r14,0,sizeof(struct LTE_SystemInformationBlockType13_r9)); + } + + + memcpy((*sib1_MBMS)->systemInformationBlockType13_r14,*sib13,sizeof(struct LTE_SystemInformationBlockType13_r9)); + + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS, + NULL, + (void *)bcch_message_fembms, + buffer_fembms, + 100); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + + LOG_I(RRC,"[eNB] MBMS SIB1_MBMS SystemInformation Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8); + + if (enc_rval.encoded==-1) { + msg("[RRC] ASN1 : SI encoding failed for SIB23\n"); + return(-1); + } + + + + //xer_fprint(stdout, &asn_DEF_LTE_BCCH_DL_SCH_Message, (void *)bcch_message); + + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_DL_SCH_Message, + NULL, + (void *)bcch_message, + buffer, + 900); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + + LOG_I(RRC,"[eNB] MBMS SIB2 SystemInformation Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8); + + if (enc_rval.encoded==-1) { + msg("[RRC] ASN1 : SI encoding failed for SIB23\n"); + return(-1); + } + + carrier->MBMS_flag =1; + + if (NODE_IS_MONOLITHIC(rrc->node_type)) { + rrc_mac_config_req_eNB(ctxt_pP->module_id, CC_id, + 0,0,0,0,0, + 0, + 0xfffd,//rnti + (LTE_BCCH_BCH_Message_t *)NULL, + (LTE_RadioResourceConfigCommonSIB_t *) NULL, + (LTE_RadioResourceConfigCommonSIB_t *) NULL, + (struct LTE_PhysicalConfigDedicated *)NULL, + (LTE_SCellToAddMod_r10_t *)NULL, + //(struct LTE_PhysicalConfigDedicatedSCell_r10 *)NULL, + (LTE_MeasObjectToAddMod_t **) NULL, + (LTE_MAC_MainConfig_t *) NULL, + 0, + (struct LTE_LogicalChannelConfig *)NULL, + (LTE_MeasGapConfig_t *) NULL, + (LTE_TDD_Config_t *) NULL, + (LTE_MobilityControlInfo_t *)NULL, + (LTE_SchedulingInfoList_t *) NULL, + 0, NULL, + (LTE_AdditionalSpectrumEmission_t *)NULL, + (LTE_MBSFN_SubframeConfigList_t *) carrier->sib2->mbsfn_SubframeConfigList, + carrier->MBMS_flag, + (LTE_MBSFN_AreaInfoList_r9_t *) & carrier->sib13->mbsfn_AreaInfoList_r9, + (LTE_PMCH_InfoList_r9_t *) NULL + , + (LTE_SystemInformationBlockType1_v1310_IEs_t *)NULL + , + carrier->FeMBMS_flag, + (LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL, + (LTE_SchedulingInfo_MBMS_r14_t *) NULL, + (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, + (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL + ); + } + + RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB23 = ((enc_rval.encoded+7)/8); + + return 0; +} //static uint8_t rrc_M2AP_do_SIB1( // const protocol_ctxt_t *const ctxt_pP, // uint8_t Mod_id, @@ -501,21 +919,23 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2( if(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].is_four_sf){ + LOG_I(RRC,"is_four_sf\n"); sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 3; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 0; - sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation) & 0xFF); - sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation>>8) & 0xFF); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation) & 0xFF); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>8) & 0xFF); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>16) & 0xFF); }else{ + LOG_I(RRC,"is_one_sf\n"); sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 2; - sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation<<2); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation<<2); } @@ -580,7 +1000,8 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } @@ -752,7 +1173,8 @@ for( i=0; i < m2ap_setup_resp->num_mcch_config_per_mbsfn; i++){ (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } @@ -917,20 +1339,22 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2_SIB13( if(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].is_four_sf){ sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames; + LOG_I(RRC,"rrc_M2AP_do_SIB23_SIB2_SIB13 is_four_sf\n"); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 3; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 0; - sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation) & 0xFF); - sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation>>8) & 0xFF); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation) & 0xFF); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>8) & 0xFF); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>16) & 0xFF); }else{ + LOG_I(RRC,"rrc_M2AP_do_SIB23_SIB2_SIB13 rs_one_sf\n"); sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1); sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1; sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 2; - sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation<<2); + sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation<<2); } @@ -1030,7 +1454,8 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2_SIB13( (LTE_SchedulingInfo_MBMS_r14_t *) NULL, (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL, (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL, - (LTE_MBSFN_AreaInfoList_r9_t *) NULL + (LTE_MBSFN_AreaInfoList_r9_t *) NULL, + (LTE_MBSFNAreaConfiguration_r9_t*) NULL ); } @@ -1122,7 +1547,11 @@ rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ( rrc_M2AP_do_SIB23_SIB2(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_mbms_scheduling_information_g); rrc_M2AP_do_SIB23_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g); }else{ - rrc_M2AP_do_SIB23_SIB2_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g,m2ap_mbms_scheduling_information_g); + if(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].FeMBMS_flag){ + rrc_M2AP_do_SIB1_MBMS_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g,m2ap_mbms_scheduling_information_g); + }else{ + rrc_M2AP_do_SIB23_SIB2_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g,m2ap_mbms_scheduling_information_g); + } } rrc_M2AP_init_MCCH(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_mbms_scheduling_information_g); rrc_M2AP_init_MBMS(ctxt_pP->module_id, CC_id, 0); diff --git a/openair3/M3AP/m3ap_MCE.c b/openair3/M3AP/m3ap_MCE.c index 232b0c0ece..dec9b96897 100644 --- a/openair3/M3AP/m3ap_MCE.c +++ b/openair3/M3AP/m3ap_MCE.c @@ -142,6 +142,20 @@ void m3ap_MCE_handle_sctp_association_resp(instance_t instance, sctp_new_associa sctp_new_association_resp->ulp_cnx_id); //m3ap_handle_m3_setup_message(instance_p, m3ap_enb_data_p, //sctp_new_association_resp->sctp_state == SCTP_STATE_SHUTDOWN); + sleep(4); + int index; + /* Trying to connect to the provided list of eNB ip address */ + for (index = 0; index < instance_p->nb_m3; index++) { + //M2AP_INFO("eNB[%d] eNB id %u acting as an initiator (client)\n", + // instance_id, instance->eNB_id); + m3ap_MCE_register_MCE(instance_p, + &instance_p->target_mme_m3_ip_address[index], + &instance_p->mme_m3_ip_address, + instance_p->sctp_in_streams, + instance_p->sctp_out_streams, + instance_p->mce_port_for_M3C, + instance_p->multi_sd); + } return; } diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c index 4715a4e995..faeed94c06 100644 --- a/targets/RT/USER/lte-softmodem.c +++ b/targets/RT/USER/lte-softmodem.c @@ -713,9 +713,12 @@ int main ( int argc, char **argv ) sync_var=0; pthread_cond_broadcast(&sync_cond); pthread_mutex_unlock(&sync_mutex); + create_tasks_mbms(1); config_check_unknown_cmdlineopt(CONFIG_CHECKALLSECTIONS); } - create_tasks_mbms(1); + else + create_tasks_mbms(1); + //create_tasks_mbms(1); // wait for end of program LOG_UI(ENB_APP,"TYPE TO TERMINATE\n"); From 543457f377be4eec6affaa95f714e92c1a946752 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Wed, 22 Jul 2020 08:09:51 +0200 Subject: [PATCH 31/70] fembms: removing debug log Signed-off-by: Javier Morgade --- openair1/SCHED_UE/phy_procedures_lte_ue.c | 3 +-- openair2/RRC/LTE/L2_interface.c | 4 ++-- openair2/RRC/LTE/L2_interface_ue.c | 6 ++---- openair2/RRC/LTE/rrc_UE.c | 4 ++-- 4 files changed, 7 insertions(+), 10 deletions(-) diff --git a/openair1/SCHED_UE/phy_procedures_lte_ue.c b/openair1/SCHED_UE/phy_procedures_lte_ue.c index 9f0b965e0c..35631c4ac3 100644 --- a/openair1/SCHED_UE/phy_procedures_lte_ue.c +++ b/openair1/SCHED_UE/phy_procedures_lte_ue.c @@ -2707,7 +2707,6 @@ int ue_pdcch_procedures(uint8_t eNB_id, if (LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) { LOG_D(PHY,"[UE %d] subframe %d: Found rnti %x, format 1%s, dci_cnt %d\n",ue->Mod_id,subframe_rx,dci_alloc_rx[i].rnti,dci_alloc_rx[i].format==format1A?"A":"C",i); } - LOG_W(PHY,"[UE %d] subframe %d: Found rnti %x, format 1%s, dci_cnt %d\n",ue->Mod_id,subframe_rx,dci_alloc_rx[i].rnti,dci_alloc_rx[i].format==format1A?"A":"C",i); if (generate_ue_dlsch_params_from_dci(frame_rx, subframe_rx, @@ -2726,7 +2725,7 @@ int ue_pdcch_procedures(uint8_t eNB_id, ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id], 0)==0) { ue->dlsch_SI_received[eNB_id]++; - LOG_W(PHY,"[UE %d] Frame %d, subframe %d : Generate UE DLSCH SI_RNTI format 1%s\n",ue->Mod_id,frame_rx,subframe_rx,dci_alloc_rx[i].format==format1A?"A":"C"); + LOG_D(PHY,"[UE %d] Frame %d, subframe %d : Generate UE DLSCH SI_RNTI format 1%s\n",ue->Mod_id,frame_rx,subframe_rx,dci_alloc_rx[i].format==format1A?"A":"C"); //dump_dci(&ue->frame_parms, &dci_alloc_rx[i]); } } else if ((dci_alloc_rx[i].rnti == P_RNTI) && diff --git a/openair2/RRC/LTE/L2_interface.c b/openair2/RRC/LTE/L2_interface.c index fe1cbd32ef..d9682b466f 100644 --- a/openair2/RRC/LTE/L2_interface.c +++ b/openair2/RRC/LTE/L2_interface.c @@ -233,10 +233,10 @@ mac_rrc_data_req( RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESSAGE[mbsfn_sync_area], RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]); - LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP); + LOG_D(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP); if (LOG_DEBUGFLAG(DEBUG_RRC)) { - LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP); + LOG_D(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP); for (int i=0; icarrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]; i++) { LOG_T(RRC,"%x.",buffer_pP[i]); diff --git a/openair2/RRC/LTE/L2_interface_ue.c b/openair2/RRC/LTE/L2_interface_ue.c index c413df49bb..8c55dbaeb5 100644 --- a/openair2/RRC/LTE/L2_interface_ue.c +++ b/openair2/RRC/LTE/L2_interface_ue.c @@ -227,11 +227,9 @@ mac_rrc_data_ind_ue( } if ((srb_idP & RAB_OFFSET) == MCCH) { - //LOG_T(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n", - //module_idP,frameP, mbsfn_sync_areaP, srb_idP & RAB_OFFSET,eNB_indexP); - - LOG_W(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n", + LOG_T(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n", module_idP,frameP, mbsfn_sync_areaP, srb_idP & RAB_OFFSET,eNB_indexP); + { MessageDef *message_p; int msg_sdu_size = sizeof(RRC_MAC_MCCH_DATA_IND (message_p).sdu); diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 5955c2221c..1e788a1762 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -4270,7 +4270,7 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB asn_dec_rval_t dec_rval; if (UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].MCCHStatus[mbsfn_sync_area] == 1) { - LOG_W(RRC,"[UE %d] Frame %d: MCCH MESSAGE for MBSFN sync area %d has been already received!\n", + LOG_D(RRC,"[UE %d] Frame %d: MCCH MESSAGE for MBSFN sync area %d has been already received!\n", ctxt_pP->module_id, ctxt_pP->frame, mbsfn_sync_area); @@ -4524,7 +4524,7 @@ void *rrc_ue_task( void *args_p ) { break; case RRC_MAC_MCCH_DATA_IND: - LOG_W(RRC, "[UE %d] Received %s: frameP %d, eNB %d, mbsfn SA %d\n", ue_mod_id, ITTI_MSG_NAME (msg_p), + LOG_D(RRC, "[UE %d] Received %s: frameP %d, eNB %d, mbsfn SA %d\n", ue_mod_id, ITTI_MSG_NAME (msg_p), RRC_MAC_MCCH_DATA_IND (msg_p).frame, RRC_MAC_MCCH_DATA_IND (msg_p).enb_index, RRC_MAC_MCCH_DATA_IND (msg_p).mbsfn_sync_area); //PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, instance, ENB_FLAG_NO, M_RNTI, RRC_MAC_MCCH_DATA_IND (msg_p).frame, 0); PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, ue_mod_id, ENB_FLAG_NO, M_RNTI, RRC_MAC_MCCH_DATA_IND (msg_p).frame, 0,RRC_MAC_MCCH_DATA_IND (msg_p).enb_index); From df58e251d81083f083134b2e7d4749380374c23b Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Wed, 22 Jul 2020 10:35:22 +0200 Subject: [PATCH 32/70] fembms: -FIX phy_simulators compiling error - adding missing dummy functions Signed-off-by: Javier Morgade --- openair1/SIMULATION/LTE_PHY/dummy_functions.c | 5 +++++ .../SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/openair1/SIMULATION/LTE_PHY/dummy_functions.c b/openair1/SIMULATION/LTE_PHY/dummy_functions.c index 5ec0f6e696..120e4845d9 100644 --- a/openair1/SIMULATION/LTE_PHY/dummy_functions.c +++ b/openair1/SIMULATION/LTE_PHY/dummy_functions.c @@ -67,6 +67,11 @@ int ue_query_mch(module_id_t Mod_id, uint8_t CC_id, uint32_t frame, sub_frame_t subframe, uint8_t eNB_index, uint8_t * sync_area, uint8_t * mcch_active){ return(0);} + +int ue_query_mch_fembms(module_id_t Mod_id, uint8_t CC_id, uint32_t frame, + sub_frame_t subframe, uint8_t eNB_index, + uint8_t * sync_area, uint8_t * mcch_active){ return(0);} + void dl_phy_sync_success(module_id_t module_idP, frame_t frameP, unsigned char eNB_index, uint8_t first_sync){} diff --git a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c index a93f0d48f3..cc8c62a36d 100644 --- a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c +++ b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c @@ -115,6 +115,11 @@ int ue_query_mch(module_id_t Mod_id, uint8_t CC_id, uint32_t frame, sub_frame_t subframe, uint8_t eNB_index, uint8_t * sync_area, uint8_t * mcch_active){ return(0);} + +int ue_query_mch_fembms(module_id_t Mod_id, uint8_t CC_id, uint32_t frame, + sub_frame_t subframe, uint8_t eNB_index, + uint8_t * sync_area, uint8_t * mcch_active){ return(0);} + void dl_phy_sync_success(module_id_t module_idP, frame_t frameP, unsigned char eNB_index, uint8_t first_sync){} From 5a68767d6a69765d24ed63ed9e1b0011b09c5305 Mon Sep 17 00:00:00 2001 From: "Dr.-Ing. Javier Morgade" Date: Wed, 22 Jul 2020 16:57:51 +0200 Subject: [PATCH 33/70] Update enb.band17.tm1.mbms.25PRB.usrpb210.conf --- ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf index e36d970b5b..a9ccb9f783 100644 --- a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf +++ b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf @@ -249,7 +249,6 @@ MCEs = ( ); - NETWORK_INTERFACES : { MCE_INTERFACE_NAME_FOR_M2_ENB = "lo"; From 63ed400e28fc54a7413855ef298565be78f0eba1 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Fri, 24 Jul 2020 09:44:13 +0200 Subject: [PATCH 34/70] fembms: CI/CD Adding FeMBMS RFSIM coverage test Signed-off-by: Javier Morgade --- .../conf_files/lte-fdd-fmbms-basic-sim.conf | 426 ++++++++++++++++++ 1 file changed, 426 insertions(+) create mode 100644 ci-scripts/conf_files/lte-fdd-fmbms-basic-sim.conf diff --git a/ci-scripts/conf_files/lte-fdd-fmbms-basic-sim.conf b/ci-scripts/conf_files/lte-fdd-fmbms-basic-sim.conf new file mode 100644 index 0000000000..e3adedbf4a --- /dev/null +++ b/ci-scripts/conf_files/lte-fdd-fmbms-basic-sim.conf @@ -0,0 +1,426 @@ +Active_eNBs = ( "eNB-Eurecom-LTEBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +eNBs = +( + { + ////////// Identification parameters: + eNB_ID = 0xe00; + + cell_type = "CELL_MACRO_ENB"; + + eNB_name = "eNB-Eurecom-LTEBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + plmn_list = ( { mcc = 208; mnc = 93; mnc_length = 2; } ); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "3GPP_eNODEB"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + frame_type = "FDD"; + tdd_config = 3; + tdd_config_s = 0; + prefix_type = "NORMAL"; + eutra_band = 7; + downlink_frequency = 2680000000L; + uplink_frequency_offset = -120000000; + Nid_cell = 0; + N_RB_DL = 25; + Nid_cell_mbsfn = 0; + nb_antenna_ports = 1; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + tx_gain = 90; + rx_gain = 125; + pbch_repetition = "FALSE"; + prach_root = 0; + prach_config_index = 0; + prach_high_speed = "DISABLE"; + prach_zero_correlation = 1; + prach_freq_offset = 2; + pucch_delta_shift = 1; + pucch_nRB_CQI = 0; + pucch_nCS_AN = 0; + pucch_n1_AN = 0; + pdsch_referenceSignalPower = -27; + pdsch_p_b = 0; + pusch_n_SB = 1; + pusch_enable64QAM = "DISABLE"; + pusch_hoppingMode = "interSubFrame"; + pusch_hoppingOffset = 0; + pusch_groupHoppingEnabled = "ENABLE"; + pusch_groupAssignment = 0; + pusch_sequenceHoppingEnabled = "DISABLE"; + pusch_nDMRS1 = 1; + phich_duration = "NORMAL"; + phich_resource = "ONESIXTH"; + srs_enable = "DISABLE"; + /* srs_BandwidthConfig =; + srs_SubframeConfig =; + srs_ackNackST =; + srs_MaxUpPts =;*/ + + pusch_p0_Nominal = -96; + pusch_alpha = "AL1"; + pucch_p0_Nominal = -104; + msg3_delta_Preamble = 6; + pucch_deltaF_Format1 = "deltaF2"; + pucch_deltaF_Format1b = "deltaF3"; + pucch_deltaF_Format2 = "deltaF0"; + pucch_deltaF_Format2a = "deltaF0"; + pucch_deltaF_Format2b = "deltaF0"; + + rach_numberOfRA_Preambles = 64; + rach_preamblesGroupAConfig = "DISABLE"; + /* + rach_sizeOfRA_PreamblesGroupA = ; + rach_messageSizeGroupA = ; + rach_messagePowerOffsetGroupB = ; + */ + rach_powerRampingStep = 4; + rach_preambleInitialReceivedTargetPower = -108; + rach_preambleTransMax = 10; + rach_raResponseWindowSize = 10; + rach_macContentionResolutionTimer = 48; + rach_maxHARQ_Msg3Tx = 4; + + pcch_default_PagingCycle = 128; + pcch_nB = "oneT"; + bcch_modificationPeriodCoeff = 2; + ue_TimersAndConstants_t300 = 1000; + ue_TimersAndConstants_t301 = 1000; + ue_TimersAndConstants_t310 = 1000; + ue_TimersAndConstants_t311 = 10000; + ue_TimersAndConstants_n310 = 20; + ue_TimersAndConstants_n311 = 1; + ue_TransmissionMode = 1; + mbms_dedicated_serving_cell = "ENABLE" + + //Parameters for SIB18 + rxPool_sc_CP_Len = "normal"; + rxPool_sc_Period = "sf40"; + rxPool_data_CP_Len = "normal"; + rxPool_ResourceConfig_prb_Num = 20; + rxPool_ResourceConfig_prb_Start = 5; + rxPool_ResourceConfig_prb_End = 44; + rxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + rxPool_ResourceConfig_offsetIndicator_choice = 0; + rxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; +/* rxPool_dataHoppingConfig_hoppingParameter = 0; + rxPool_dataHoppingConfig_numSubbands = "ns1"; + rxPool_dataHoppingConfig_rbOffset = 0; + rxPool_commTxResourceUC-ReqAllowed = "TRUE"; +*/ + // Parameters for SIB19 + discRxPool_cp_Len = "normal" + discRxPool_discPeriod = "rf32" + discRxPool_numRetx = 1; + discRxPool_numRepetition = 2; + discRxPool_ResourceConfig_prb_Num = 5; + discRxPool_ResourceConfig_prb_Start = 3; + discRxPool_ResourceConfig_prb_End = 21; + discRxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + discRxPool_ResourceConfig_offsetIndicator_choice = 0; + discRxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; + + } + ); + + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + enable_measurement_reports = "no"; + + ///X2 + enable_x2 = "no"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + ////////// MCE parameters: + target_mce_m2_ip_address = ( { ipv4 = "127.0.0.7"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///M2 + enable_enb_m2 = "yes"; + + + mbms_configuration_data_list = ( + { + mbsfn_sync_area = 0x0001; + mbms_service_area_list=( + { + mbms_service_area=0x0001; + } + ); + } + + ); + + + + NETWORK_INTERFACES : + { + + ENB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "CI_ENB_IP_ADDR"; + ENB_INTERFACE_NAME_FOR_S1U = "eth0"; + ENB_IPV4_ADDRESS_FOR_S1U = "CI_ENB_IP_ADDR"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + ENB_IPV4_ADDRESS_FOR_X2C = "CI_ENB_IP_ADDR"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + + ENB_IPV4_ADDRESS_FOR_M2C = "127.0.0.2/24"; + ENB_PORT_FOR_M2C = 36443; # Spec 36443 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 200; + puCch10xSnr = 200; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +MCEs = ( + { + MCE_ID = 0xe00; + + MCE_name = "MCE-Vicomtech-LTEBox"; + + //M2 + enable_mce_m2 = "yes"; + + //M3 + enable_mce_m3 = "yes"; + + target_mme_m3_ip_address = ( { ipv4 = "127.0.0.18"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + + + NETWORK_INTERFACES : + { + MCE_INTERFACE_NAME_FOR_M2_ENB = "lo"; + MCE_IPV4_ADDRESS_FOR_M2C = "127.0.0.7/24"; + MCE_PORT_FOR_M2C = 36443; # Spec 36443 + + MCE_INTERFACE_NAME_FOR_M3_MME = "lo"; + MCE_IPV4_ADDRESS_FOR_M3C = "127.0.0.3/24"; + MCE_PORT_FOR_M3C = 36444; # Spec 36444 + }; + + plnm: + { + mcc = 208; + mnc = 93; + mnc_length = 2; + }; + + mbms_sched_info : + { + mcch_update_time = 10; + mbms_area_config_list = ( + { + common_sf_allocation_period = 1; #rf4(0) rf8(1) rf16(2) rf32(3) rf64(4) rf128(5) rf256(6) + mbms_area_id = 0; + pmch_config_list = ( + { + allocated_sf_end=512; + data_mcs=15; + mch_scheduling_period = 0; #rf8(0) rf16(1) rf32(2) rf64(3) rf128(4) rf256(5) rf512(6) rf1024(7) + mbms_session_list = ( + { + #plnm + service_id ->tmgi + plnm: + { + mcc = 208; + mnc = 93; + mnc_length = 2; + } + service_id=0; #keep this allways as 0 (workaround for TUN if) + lcid=5; #this must be properly defined lcid:6+service:0 -> rab_id:5 //with new RLC set lcid either 4 or 5 + } + ); + } + ); + + mbms_sf_config_list = ( + { + radioframe_allocation_period=0; #n1(0) n2(1) n4(2) n8(3) n16(4) n32(5) + radioframe_alloocation_offset=0; + num_frame="oneFrame"; + subframe_allocation=57; #xx111001 + //num_frame="fourFrame"; + //subframe_allocation=14548987; # + } + ); + + } + ); + }; + + + mcch_config_per_mbsfn_area = ( + { + mbsfn_area = 0; + pdcch_length = 1; #s1(0), s2(1) + repetition_period = 0; #rf32(0), rf64(1), rf128(2), rf256(3) + offset = 0; + modification_period = 0; #rf512(0; rf1024(1) + subframe_allocation_info = 32; #BITSTRING (6bits -> one frame) xx100000 + mcs = 0; #n2(0), n7(1), n13(2), n19(3) + } + ); + + #); #end mbms_scheduling_info + + } +); + +MMEs = ( + { + MME_ID = 0xe00; + + MME_name = "MME-MBMS-Vicomtech-LTEBox"; + + //M3 + enable_mme_m3 = "yes"; + NETWORK_INTERFACES : + { + MME_INTERFACE_NAME_FOR_M3_MCE = "lo"; + MME_IPV4_ADDRESS_FOR_M3C = "127.0.0.18/24"; + MME_PORT_FOR_M3C = 36444; # Spec 36444 + + }; + } +); + + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 125; + eNB_instances = [0]; + + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + +NETWORK_CONTROLLER : +{ + FLEXRAN_ENABLED = "no"; + FLEXRAN_INTERFACE_NAME = "ens3"; + FLEXRAN_IPV4_ADDRESS = "CI_FLEXRAN_CTL_IP_ADDR"; + FLEXRAN_PORT = 2210; + FLEXRAN_CACHE = "/mnt/oai_agent_cache"; + FLEXRAN_AWAIT_RECONF = "no"; +}; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + +//rfsimulator : +//{ + //options = ("chanmod"); + //modelname = "AWGN"; +//}; + From 27b9fa6935cecbef130121499d5c278ec21871ab Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Fri, 24 Jul 2020 09:46:02 +0200 Subject: [PATCH 35/70] fembms: CI/DC adding missing commit Signed-off-by: Javier Morgade --- ci-scripts/reportTestLocally.sh | 95 +++++++++++++++++++++++++++++++++ ci-scripts/runTestOnVM.sh | 89 ++++++++++++++++++++++++++++++ 2 files changed, 184 insertions(+) diff --git a/ci-scripts/reportTestLocally.sh b/ci-scripts/reportTestLocally.sh index 897f9285e9..b05ccf39db 100755 --- a/ci-scripts/reportTestLocally.sh +++ b/ci-scripts/reportTestLocally.sh @@ -620,6 +620,101 @@ function report_test { #IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_ul*client*txt | grep -v mbms 2> /dev/null` #analyzeIperfFiles done + + # FeMBMS Case + CN_CONFIG="noS1" + TMODE="fdd" + BW_CASES=(05) + for BW in ${BW_CASES[@]} + do + echo " " >> ./test_simulator_results.html + echo " Test FeMBMS without EPC (aka noS1): ${TMODE} -- ${BW}MHz " >> ./test_simulator_results.html + echo " " >> ./test_simulator_results.html + ENB_LOG=$ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_enb_fembms.log + UE_LOG=`echo $ENB_LOG | sed -e "s#enb#ue#"` + if [ -f $ENB_LOG ] && [ -f $UE_LOG ] + then + NAME_ENB=`echo $ENB_LOG | sed -e "s#$ARCHIVES_LOC/##"` + NAME_UE=`echo $UE_LOG | sed -e "s#$ARCHIVES_LOC/##"` + echo " " >> ./test_simulator_results.html + echo " $NAME_ENB --- $NAME_UE" >> ./test_simulator_results.html + echo " N/A" >> ./test_simulator_results.html + #NB_ENB_GOT_SYNC=`egrep -c "got sync" $ENB_LOG` + NB_ENB_TUNNEL_UP=`egrep -c "Interface oaitun_enb1 successfully configured" $ENB_LOG` + NB_ENB_MTUNNEL_UP=`egrep -c "Interface oaitun_enm1 successfully configured" $ENB_LOG` + #NB_UE_GOT_SYNC=`egrep -c "rfsimulator: Success" $UE_LOG` + #NB_ENB_SYNCED_WITH_UE=`egrep -c "Generating RRCConnectionReconfigurationComplete" $UE_LOG` + NB_UE_TUNNEL_UP=`egrep -c "Interface oaitun_ue1 successfully configured" $UE_LOG` + NB_UE_MTUNNEL_UP=`egrep -c "Interface oaitun_uem1 successfully configured" $UE_LOG` + NB_UE_MBMS_PUSH_MSG=`egrep -c "TRIED TO PUSH MBMS DATA TO" $UE_LOG` + #if [ $NB_ENB_GOT_SYNC -gt 0 ] && [ $NB_UE_GOT_SYNC -gt 0 ] && [ $NB_ENB_SYNCED_WITH_UE -gt 0 ] && [ $NB_UE_MBMS_PUSH_MSG -gt 0 ] + if [ $NB_UE_MBMS_PUSH_MSG -gt 0 ] + then + echo " OK" >> ./test_simulator_results.html + else + echo " KO" >> ./test_simulator_results.html + fi + echo " 
" >> ./test_simulator_results.html
+                #if [ $NB_ENB_GOT_SYNC -gt 0 ]
+                #then
+                #    echo "- eNB --> got sync" >> ./test_simulator_results.html
+                #else
+                #    echo "- eNB NEVER got sync" >> ./test_simulator_results.html
+                #fi
+                if [ $NB_ENB_TUNNEL_UP -gt 0 ]
+                then
+                    echo "- eNB mounted oaitun_enb1 interface" >> ./test_simulator_results.html
+                else
+                    echo "- eNB NEVER mounted oaitun_enb1 interface" >> ./test_simulator_results.html
+                fi
+                if [ $NB_ENB_MTUNNEL_UP -gt 0 ]
+                then
+                    echo "- eNB mounted oaitun_enm1 interface" >> ./test_simulator_results.html
+                else
+                    echo "- eNB NEVER mounted oaitun_enm1 interface" >> ./test_simulator_results.html
+                fi
+                #if [ $NB_UE_GOT_SYNC -gt 0 ]
+                #then
+                #    echo "- LTE UE --> got sync" >> ./test_simulator_results.html
+                #else
+                #    echo "- LTE UE NEVER got sync" >> ./test_simulator_results.html
+                #fi
+                #if [ $NB_ENB_SYNCED_WITH_UE -gt 0 ]
+                #then
+                #    echo "- LTE UE attached to eNB" >> ./test_simulator_results.html
+                #else
+                #    echo "- LTE UE NEVER attached to eNB" >> ./test_simulator_results.html
+                #fi
+                if [ $NB_UE_TUNNEL_UP -gt 0 ]
+                then
+                    echo "- LTE UE mounted oaitun_ue1 interface" >> ./test_simulator_results.html
+                else
+                    echo "- LTE UE NEVER mounted oaitun_ue1 interface" >> ./test_simulator_results.html
+                fi
+                if [ $NB_UE_MTUNNEL_UP -gt 0 ]
+                then
+                    echo "- LTE UE mounted oaitun_uem1 interface" >> ./test_simulator_results.html
+                else
+                    echo "- LTE UE NEVER mounted oaitun_uem1 interface" >> ./test_simulator_results.html
+                fi
+                if [ $NB_UE_MBMS_PUSH_MSG -gt 0 ]
+                then
+                    echo "- LTE UE tried to push ${NB_UE_MBMS_PUSH_MSG} MBMS DATA" >> ./test_simulator_results.html
+                else
+                    echo "- LTE UE NEVER pushed MBMS DATA" >> ./test_simulator_results.html
+                fi
+                echo "
" >> ./test_simulator_results.html + echo " " >> ./test_simulator_results.html + fi + #PING_LOGS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_ping*.log 2> /dev/null` + #analyzePingFiles + + #IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_dl*client*txt | grep -v mbms 2> /dev/null` + #analyzeIperfFiles + + #IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_ul*client*txt | grep -v mbms 2> /dev/null` + #analyzeIperfFiles + done echo " " >> ./test_simulator_results.html echo " " >> ./test_simulator_results.html diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index 0db2264c76..1ac5e3a920 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -2050,6 +2050,95 @@ function run_test_on_vm { echo "LTE RFSIM seems to FAIL" echo "LTE: TEST_KO" > $ARCHIVES_LOC/test_final_status.log fi + + #################### + ## FeMSMS CASE noS1 ## + #################### + CONF_FILE=lte-fdd-fembms-basic-sim.conf + CN_CONFIG="noS1" + S1_NOS1_CFG=0 + LTEBOX=0 + TMODE="fdd" + FREQUENCY=2680 + BW_CASES=(05) + FeMBMS_STATUS=0 + + for BW in ${BW_CASES[@]} + do + if [[ $BW =~ .*05.* ]]; then PRB=25; fi + if [[ $BW =~ .*10.* ]]; then PRB=50; fi + if [[ $BW =~ .*20.* ]]; then PRB=100; fi + + echo "############################################################" + echo "${CN_CONFIG} : Starting the eNB with MSMS in ${TMODE}-${BW}MHz mode" + echo "############################################################" + CURRENT_ENB_LOG_FILE=${TMODE}_${BW}MHz_${CN_CONFIG}_enb_fembms.log + start_rf_sim_enb $ENB_VM_CMDS "$ENB_VM_IP_ADDR" "$EPC_VM_IP_ADDR" $CURRENT_ENB_LOG_FILE $PRB $CONF_FILE $S1_NOS1_CFG + + echo "############################################################" + echo "${CN_CONFIG} : Starting the UE" + echo "############################################################" + CURRENT_UE_LOG_FILE=${TMODE}_${BW}MHz_${CN_CONFIG}_ue_fembms.log + start_rf_sim_ue $UE_VM_CMDS $UE_VM_IP_ADDR $ENB_VM_IP_ADDR $CURRENT_UE_LOG_FILE $PRB $FREQUENCY $S1_NOS1_CFG 1 + if [ $UE_SYNC -eq 0 ] + then + echo "Problem w/ eNB and UE not syncing" + terminate_enb_ue_basic_sim $ENB_VM_CMDS $ENB_VM_IP_ADDR 1 + terminate_enb_ue_basic_sim $UE_VM_CMDS $UE_VM_IP_ADDR 2 + scp -o StrictHostKeyChecking=no ubuntu@$ENB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_ENB_LOG_FILE $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_UE_LOG_FILE $ARCHIVES_LOC + STATUS=-1 + break + fi + + echo "############################################################" + echo "${CN_CONFIG} : iperf DL -- UE is server and eNB is client" + echo "############################################################" + get_enb_mbms_noS1_ip_addr $ENB_VM_CMDS $ENB_VM_IP_ADDR + IPERF_LOG_FILE=${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_dl_fembms + get_ue_mbms_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR 1 + THROUGHPUT=2 + generic_iperf $UE_VM_CMDS $UE_VM_IP_ADDR $UE_IP_ADDR $ENB_VM_CMDS $ENB_VM_IP_ADDR $ENB_IP_ADDR $THROUGHPUT $IPERF_LOG_FILE 1 0 + scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/${IPERF_LOG_FILE}_server.txt $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$ENB_VM_IP_ADDR:/home/ubuntu/${IPERF_LOG_FILE}_client.txt $ARCHIVES_LOC + #check_iperf $ARCHIVES_LOC/$IPERF_LOG_FILE $THROUGHPUT + + echo "############################################################" + echo "${CN_CONFIG} : Terminate enb/ue simulators" + echo "############################################################" + terminate_enb_ue_basic_sim $ENB_VM_CMDS $ENB_VM_IP_ADDR 1 + terminate_enb_ue_basic_sim $UE_VM_CMDS $UE_VM_IP_ADDR 2 + scp -o StrictHostKeyChecking=no ubuntu@$ENB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_ENB_LOG_FILE $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_UE_LOG_FILE $ARCHIVES_LOC + NB_UE_FeMBMS_MESSAGES=`egrep -c "TRIED TO PUSH MBMS DATA TO" $ARCHIVES_LOC/$CURRENT_UE_LOG_FILE` + if [ $NB_UE_FeMBMS_MESSAGES -eq 0 ]; then FeMBMS_STATUS=-1; fi + + done + + full_l2_sim_destroy + + echo "############################################################" + echo "Checking run status" + echo "############################################################" + + if [ $PING_STATUS -ne 0 ]; then STATUS=-1; fi + if [ $IPERF_STATUS -ne 0 ]; then STATUS=-1; fi + if [ $FeMBMS_STATUS -eq 0 ] + then + echo "LTE FeMBMS RFSIM seems OK" + else + echo "LTE FeMBMS RFSIM seems to FAIL" + STATUS=-1 + fi + if [ $STATUS -eq 0 ] + then + echo "LTE RFSIM seems OK" + echo "LTE: TEST_OK" > $ARCHIVES_LOC/test_final_status.log + else + echo "LTE RFSIM seems to FAIL" + echo "LTE: TEST_KO" > $ARCHIVES_LOC/test_final_status.log + fi + fi if [[ "$RUN_OPTIONS" == "complex" ]] && [[ $VM_NAME =~ .*-rf-sim.* ]] From c681e800bacc9e03df36aa969f24a3c27ff32540 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Fri, 24 Jul 2020 14:45:28 +0200 Subject: [PATCH 36/70] fembms: CI/CD Adding USRP coverage tests for FeMBMS Signed-off-by: Javier Morgade --- ...p210_band7_test_05mhz_tm1_fembms_no_s1.xml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml new file mode 100644 index 0000000000..02a62561a5 --- /dev/null +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml @@ -0,0 +1,82 @@ + + + test-05-tm1-fembms-nos1-tunnel + Test-05MHz-FeMBMS-TM1-noS1-tunnel + tasks + 2 + + 030201 090109 + 030103 000001 090103 000002 040605 000001 090109 030201 + + + + + IdleSleep + Sleep + 10 + + + + IdleSleep + Sleep + 15 + + + + IdleSleep + Sleep + 60 + + + + Initialize_eNB + Initialize eNB (FDD/Band7/5MHz/MBMS) + -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 + + + + Terminate_eNB + Terminate eNB + + + + Initialize_OAI_UE + Initialize OAI UE (FDD/Band7/5MHz/MBMS) + -C 2680000000 -r 25 --ue-rxgain 120 --ue-txgain 0 --ue-max-power 0 --ue-scan-carrier --nokrnmod 1 --noS1 + + + + Terminate_OAI_UE + Terminate OAI UE + + + + Iperf + iperf (5MHz - DL/1.5Mbps/UDP/MBMS-sink)(20 sec) + -c 10.0.2.2 -u -b 1.5M -t 20 -i 1 -fm -B 10.0.2.1 + 50 + sink + + + From 8e9a989aa53dfc36c5d0a2a907952170acb66f83 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Fri, 24 Jul 2020 17:48:51 +0200 Subject: [PATCH 37/70] fembms: FIX filename typo Signed-off-by: Javier Morgade --- ...lte-fdd-fmbms-basic-sim.conf => lte-fdd-fembms-basic-sim.conf} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename ci-scripts/conf_files/{lte-fdd-fmbms-basic-sim.conf => lte-fdd-fembms-basic-sim.conf} (100%) diff --git a/ci-scripts/conf_files/lte-fdd-fmbms-basic-sim.conf b/ci-scripts/conf_files/lte-fdd-fembms-basic-sim.conf similarity index 100% rename from ci-scripts/conf_files/lte-fdd-fmbms-basic-sim.conf rename to ci-scripts/conf_files/lte-fdd-fembms-basic-sim.conf From 7f9dbdd3f4c8c3f0ec7e37a6aaec1f2e375e2034 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Sat, 25 Jul 2020 08:06:04 +0200 Subject: [PATCH 38/70] fembms: CI/CD Test Signed-off-by: Javier Morgade --- ci-scripts/runTestOnVM.sh | 2 +- .../enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index 1ac5e3a920..b9b9a2bafa 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -2052,7 +2052,7 @@ function run_test_on_vm { fi #################### - ## FeMSMS CASE noS1 ## + ## FeMBMS CASE noS1 ## #################### CONF_FILE=lte-fdd-fembms-basic-sim.conf CN_CONFIG="noS1" diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml index 02a62561a5..49aa516e8c 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml @@ -27,7 +27,7 @@ 2 030201 090109 - 030103 000001 090103 000002 040605 000001 090109 030201 + 030104 000001 090104 000002 040606 000001 090109 030201 @@ -49,7 +49,7 @@ 60 - + Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 @@ -60,7 +60,7 @@ Terminate eNB - + Initialize_OAI_UE Initialize OAI UE (FDD/Band7/5MHz/MBMS) -C 2680000000 -r 25 --ue-rxgain 120 --ue-txgain 0 --ue-max-power 0 --ue-scan-carrier --nokrnmod 1 --noS1 @@ -71,7 +71,7 @@ Terminate OAI UE - + Iperf iperf (5MHz - DL/1.5Mbps/UDP/MBMS-sink)(20 sec) -c 10.0.2.2 -u -b 1.5M -t 20 -i 1 -fm -B 10.0.2.1 From 1d4bd3358a35b37d426153cb4e6287abc93e3e3e Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Sat, 25 Jul 2020 11:42:23 +0200 Subject: [PATCH 39/70] fembms: CI/CD fixing USRP Test Signed-off-by: Javier Morgade --- .../enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml index 49aa516e8c..8736ab2082 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml @@ -27,7 +27,7 @@ 2 030201 090109 - 030104 000001 090104 000002 040606 000001 090109 030201 + 030104 000001 090104 000002 040605 000001 090109 030201 @@ -71,7 +71,7 @@ Terminate OAI UE - + Iperf iperf (5MHz - DL/1.5Mbps/UDP/MBMS-sink)(20 sec) -c 10.0.2.2 -u -b 1.5M -t 20 -i 1 -fm -B 10.0.2.1 From 0c31b449caec54eadf1a9c7b4e7499a22e12e578 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Sat, 25 Jul 2020 15:48:05 +0200 Subject: [PATCH 40/70] fembms: CI/CD fixing USRP Test Signed-off-by: Javier Morgade --- .../enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml index b841d3bab4..3780c52bb7 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml @@ -52,7 +52,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) - -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 + -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 From e10b0646e48579aedd28f9a8c6560718ab644ac6 Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Sun, 26 Jul 2020 08:41:42 +0200 Subject: [PATCH 41/70] fembms: CI/CD fallback USRP tests Signed-off-by: Javier Morgade --- ..._ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml | 12 ++++++------ ...nb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml index 8736ab2082..3780c52bb7 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml @@ -21,13 +21,13 @@ --> - test-05-tm1-fembms-nos1-tunnel - Test-05MHz-FeMBMS-TM1-noS1-tunnel + test-05-tm1-mbms-nos1-tunnel + Test-05MHz-MBMS-TM1-noS1-tunnel tasks 2 030201 090109 - 030104 000001 090104 000002 040605 000001 090109 030201 + 030103 000001 090103 000002 040605 000001 090109 030201 @@ -49,10 +49,10 @@ 60 - + Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) - -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 + -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 @@ -60,7 +60,7 @@ Terminate eNB - + Initialize_OAI_UE Initialize OAI UE (FDD/Band7/5MHz/MBMS) -C 2680000000 -r 25 --ue-rxgain 120 --ue-txgain 0 --ue-max-power 0 --ue-scan-carrier --nokrnmod 1 --noS1 diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml index 3780c52bb7..b841d3bab4 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml @@ -52,7 +52,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) - -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 + -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 From 73dd4715944f36446977850a7915f4a2b5f300fa Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 27 Jul 2020 10:34:43 +0200 Subject: [PATCH 42/70] fembms: CI/CD using MBMS config to lauch FeMBMS test Signed-off-by: Javier Morgade --- .../enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml index b841d3bab4..3780c52bb7 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml @@ -52,7 +52,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) - -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 + -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 From a061c8acc58097564f4152223aa1b0dbf19bb3ee Mon Sep 17 00:00:00 2001 From: Javier Morgade Date: Mon, 27 Jul 2020 14:17:58 +0200 Subject: [PATCH 43/70] fembms: CI/CD fallback to original MBMS settings Signed-off-by: Javier Morgade --- .../enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml index 3780c52bb7..b841d3bab4 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_mbms_no_s1.xml @@ -52,7 +52,7 @@ Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) - -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 + -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 From 5fa775580ceca0365b5a731cdb195270314204db Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 29 Jul 2020 13:01:09 +0200 Subject: [PATCH 44/70] Removed unwanted loop and if Reordered mod_table to support new changes in the function --- executables/nr-softmodem.c | 3 +-- openair1/PHY/MODULATION/nr_modulation.c | 10 ++-------- openair1/PHY/NR_REFSIG/nr_mod_table.h | 2 +- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index bf77125975..77f6dc14b1 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -84,8 +84,7 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "NB_IoT_interface.h" #include "x2ap_eNB.h" -short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,16384,-16384,-16384,16384,-16384,-16384,7327,7327,7327,21981,21981,7327,21981,21981,7327,-7327,7327,-21981,21981,-7327,21981,-21981,-7327,7327,-7327,21981,-21981,7327,-21981,21981,-7327,-7327,-7327,-21981,-21981,-7327,-21981,-21981,10726,10726,10726,3576,3576,10726,3576,3576,10726,17876,10726,25027,3576,17876,3576,25027,17876,10726,17876,3576,25027,10726,25027,3576,17876,17876,17876,25027,25027,17876,25027,25027,10726,-10726,10726,-3576,3576,-10726,3576,-3576,10726,-17876,10726,-25027,3576,-17876,3576,-25027,17876,-10726,17876,-3576,25027,-10726,25027,-3576,17876,-17876,17876,-25027,25027,-17876,25027,-25027,-10726,10726,-10726,3576,-3576,10726,-3576,3576,-10726,17876,-10726,25027,-3576,17876,-3576,25027,-17876,10726,-17876,3576,-25027,10726,-25027,3576,-17876,17876,-17876,25027,-25027,17876,-25027,25027,-10726,-10726,-10726,-3576,-3576,-10726,-3576,-3576,-10726,-17876,-10726,-25027,-3576,-17876,-3576,-25027,-17876,-10726,-17876,-3576,-25027,-10726,-25027,-3576,-17876,-17876,-17876,-25027,-25027,-17876,-25027,-25027,8886,8886,8886,12439,12439,8886,12439,12439,8886,5332,8886,1778,12439,5332,12439,1778,5332,8886,5332,12439,1778,8886,1778,12439,5332,5332,5332,1778,1778,5332,1778,1778,8886,19547,8886,15993,12439,19547,12439,15993,8886,23101,8886,26655,12439,23101,12439,26655,5332,19547,5332,15993,1778,19547,1778,15993,5332,23101,5332,26655,1778,23101,1778,26655,19547,8886,19547,12439,15993,8886,15993,12439,19547,5332,19547,1778,15993,5332,15993,1778,23101,8886,23101,12439,26655,8886,26655,12439,23101,5332,23101,1778,26655,5332,26655,1778,19547,19547,19547,15993,15993,19547,15993,15993,19547,23101,19547,26655,15993,23101,15993,26655,23101,19547,23101,15993,26655,19547,26655,15993,23101,23101,23101,26655,26655,23101,26655,26655,8886,-8886,8886,-12439,12439,-8886,12439,-12439,8886,-5332,8886,-1778,12439,-5332,12439,-1778,5332,-8886,5332,-12439,1778,-8886,1778,-12439,5332,-5332,5332,-1778,1778,-5332,1778,-1778,8886,-19547,8886,-15993,12439,-19547,12439,-15993,8886,-23101,8886,-26655,12439,-23101,12439,-26655,5332,-19547,5332,-15993,1778,-19547,1778,-15993,5332,-23101,5332,-26655,1778,-23101,1778,-26655,19547,-8886,19547,-12439,15993,-8886,15993,-12439,19547,-5332,19547,-1778,15993,-5332,15993,-1778,23101,-8886,23101,-12439,26655,-8886,26655,-12439,23101,-5332,23101,-1778,26655,-5332,26655,-1778,19547,-19547,19547,-15993,15993,-19547,15993,-15993,19547,-23101,19547,-26655,15993,-23101,15993,-26655,23101,-19547,23101,-15993,26655,-19547,26655,-15993,23101,-23101,23101,-26655,26655,-23101,26655,-26655,-8886,8886,-8886,12439,-12439,8886,-12439,12439,-8886,5332,-8886,1778,-12439,5332,-12439,1778,-5332,8886,-5332,12439,-1778,8886,-1778,12439,-5332,5332,-5332,1778,-1778,5332,-1778,1778,-8886,19547,-8886,15993,-12439,19547,-12439,15993,-8886,23101,-8886,26655,-12439,23101,-12439,26655,-5332,19547,-5332,15993,-1778,19547,-1778,15993,-5332,23101,-5332,26655,-1778,23101,-1778,26655,-19547,8886,-19547,12439,-15993,8886,-15993,12439,-19547,5332,-19547,1778,-15993,5332,-15993,1778,-23101,8886,-23101,12439,-26655,8886,-26655,12439,-23101,5332,-23101,1778,-26655,5332,-26655,1778,-19547,19547,-19547,15993,-15993,19547,-15993,15993,-19547,23101,-19547,26655,-15993,23101,-15993,26655,-23101,19547,-23101,15993,-26655,19547,-26655,15993,-23101,23101,-23101,26655,-26655,23101,-26655,26655,-8886,-8886,-8886,-12439,-12439,-8886,-12439,-12439,-8886,-5332,-8886,-1778,-12439,-5332,-12439,-1778,-5332,-8886,-5332,-12439,-1778,-8886,-1778,-12439,-5332,-5332,-5332,-1778,-1778,-5332,-1778,-1778,-8886,-19547,-8886,-15993,-12439,-19547,-12439,-15993,-8886,-23101,-8886,-26655,-12439,-23101,-12439,-26655,-5332,-19547,-5332,-15993,-1778,-19547,-1778,-15993,-5332,-23101,-5332,-26655,-1778,-23101,-1778,-26655,-19547,-8886,-19547,-12439,-15993,-8886,-15993,-12439,-19547,-5332,-19547,-1778,-15993,-5332,-15993,-1778,-23101,-8886,-23101,-12439,-26655,-8886,-26655,-12439,-23101,-5332,-23101,-1778,-26655,-5332,-26655,-1778,-19547,-19547,-19547,-15993,-15993,-19547,-15993,-15993,-19547,-23101,-19547,-26655,-15993,-23101,-15993,-26655,-23101,-19547,-23101,-15993,-26655,-19547,-26655,-15993,-23101,-23101,-23101,-26655,-26655,-23101,-26655,-26655}; - +short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,-16384,16384,16384,-16384,-16384,-16384,7327,7327,-7327,7327,7327,-7327,-7327,-7327,21981,7327,-21981,7327,21981,-7327,-21981,-7327,7327,21981,-7327,21981,7327,-21981,-7327,-21981,21981,21981,-21981,21981,21981,-21981,-21981,-21981,10726,10726,-10726,10726,10726,-10726,-10726,-10726,17876,10726,-17876,10726,17876,-10726,-17876,-10726,10726,17876,-10726,17876,10726,-17876,-10726,-17876,17876,17876,-17876,17876,17876,-17876,-17876,-17876,3576,10726,-3576,10726,3576,-10726,-3576,-10726,25027,10726,-25027,10726,25027,-10726,-25027,-10726,3576,17876,-3576,17876,3576,-17876,-3576,-17876,25027,17876,-25027,17876,25027,-17876,-25027,-17876,10726,3576,-10726,3576,10726,-3576,-10726,-3576,17876,3576,-17876,3576,17876,-3576,-17876,-3576,10726,25027,-10726,25027,10726,-25027,-10726,-25027,17876,25027,-17876,25027,17876,-25027,-17876,-25027,3576,3576,-3576,3576,3576,-3576,-3576,-3576,25027,3576,-25027,3576,25027,-3576,-25027,-3576,3576,25027,-3576,25027,3576,-25027,-3576,-25027,25027,25027,-25027,25027,25027,-25027,-25027,-25027,8886,8886,-8886,8886,8886,-8886,-8886,-8886,19547,8886,-19547,8886,19547,-8886,-19547,-8886,8886,19547,-8886,19547,8886,-19547,-8886,-19547,19547,19547,-19547,19547,19547,-19547,-19547,-19547,5332,8886,-5332,8886,5332,-8886,-5332,-8886,23101,8886,-23101,8886,23101,-8886,-23101,-8886,5332,19547,-5332,19547,5332,-19547,-5332,-19547,23101,19547,-23101,19547,23101,-19547,-23101,-19547,8886,5332,-8886,5332,8886,-5332,-8886,-5332,19547,5332,-19547,5332,19547,-5332,-19547,-5332,8886,23101,-8886,23101,8886,-23101,-8886,-23101,19547,23101,-19547,23101,19547,-23101,-19547,-23101,5332,5332,-5332,5332,5332,-5332,-5332,-5332,23101,5332,-23101,5332,23101,-5332,-23101,-5332,5332,23101,-5332,23101,5332,-23101,-5332,-23101,23101,23101,-23101,23101,23101,-23101,-23101,-23101,12439,8886,-12439,8886,12439,-8886,-12439,-8886,15993,8886,-15993,8886,15993,-8886,-15993,-8886,12439,19547,-12439,19547,12439,-19547,-12439,-19547,15993,19547,-15993,19547,15993,-19547,-15993,-19547,1778,8886,-1778,8886,1778,-8886,-1778,-8886,26655,8886,-26655,8886,26655,-8886,-26655,-8886,1778,19547,-1778,19547,1778,-19547,-1778,-19547,26655,19547,-26655,19547,26655,-19547,-26655,-19547,12439,5332,-12439,5332,12439,-5332,-12439,-5332,15993,5332,-15993,5332,15993,-5332,-15993,-5332,12439,23101,-12439,23101,12439,-23101,-12439,-23101,15993,23101,-15993,23101,15993,-23101,-15993,-23101,1778,5332,-1778,5332,1778,-5332,-1778,-5332,26655,5332,-26655,5332,26655,-5332,-26655,-5332,1778,23101,-1778,23101,1778,-23101,-1778,-23101,26655,23101,-26655,23101,26655,-23101,-26655,-23101,8886,12439,-8886,12439,8886,-12439,-8886,-12439,19547,12439,-19547,12439,19547,-12439,-19547,-12439,8886,15993,-8886,15993,8886,-15993,-8886,-15993,19547,15993,-19547,15993,19547,-15993,-19547,-15993,5332,12439,-5332,12439,5332,-12439,-5332,-12439,23101,12439,-23101,12439,23101,-12439,-23101,-12439,5332,15993,-5332,15993,5332,-15993,-5332,-15993,23101,15993,-23101,15993,23101,-15993,-23101,-15993,8886,1778,-8886,1778,8886,-1778,-8886,-1778,19547,1778,-19547,1778,19547,-1778,-19547,-1778,8886,26655,-8886,26655,8886,-26655,-8886,-26655,19547,26655,-19547,26655,19547,-26655,-19547,-26655,5332,1778,-5332,1778,5332,-1778,-5332,-1778,23101,1778,-23101,1778,23101,-1778,-23101,-1778,5332,26655,-5332,26655,5332,-26655,-5332,-26655,23101,26655,-23101,26655,23101,-26655,-23101,-26655,12439,12439,-12439,12439,12439,-12439,-12439,-12439,15993,12439,-15993,12439,15993,-12439,-15993,-12439,12439,15993,-12439,15993,12439,-15993,-12439,-15993,15993,15993,-15993,15993,15993,-15993,-15993,-15993,1778,12439,-1778,12439,1778,-12439,-1778,-12439,26655,12439,-26655,12439,26655,-12439,-26655,-12439,1778,15993,-1778,15993,1778,-15993,-1778,-15993,26655,15993,-26655,15993,26655,-15993,-26655,-15993,12439,1778,-12439,1778,12439,-1778,-12439,-1778,15993,1778,-15993,1778,15993,-1778,-15993,-1778,12439,26655,-12439,26655,12439,-26655,-12439,-26655,15993,26655,-15993,26655,15993,-26655,-15993,-26655,1778,1778,-1778,1778,1778,-1778,-1778,-1778,26655,1778,-26655,1778,26655,-1778,-26655,-1778,1778,26655,-1778,26655,1778,-26655,-1778,-26655,26655,26655,-26655,26655,26655,-26655,-26655,-26655}; pthread_cond_t nfapi_sync_cond; pthread_mutex_t nfapi_sync_mutex; diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index dbfe93adee..289ac1df5f 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -36,16 +36,10 @@ void nr_modulation(uint32_t *in, LOG_D(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); + uint16_t mask = ((1<>b_idx)&1)<<(mod_order-j-1); - } + idx = ((in[i*mod_order/32]>>(i*mod_order)) & mask); out[i<<1] = nr_mod_table[(offset+idx)<<1]; out[(i<<1)+1] = nr_mod_table[((offset+idx)<<1)+1]; diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index c34dadb663..99d207ecc8 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -28,6 +28,6 @@ #define NR_MOD_TABLE_QAM16_OFFSET 7 #define NR_MOD_TABLE_QAM64_OFFSET 23 #define NR_MOD_TABLE_QAM256_OFFSET 87 -short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,16384,-16384,-16384,16384,-16384,-16384,7327,7327,7327,21981,21981,7327,21981,21981,7327,-7327,7327,-21981,21981,-7327,21981,-21981,-7327,7327,-7327,21981,-21981,7327,-21981,21981,-7327,-7327,-7327,-21981,-21981,-7327,-21981,-21981,10726,10726,10726,3576,3576,10726,3576,3576,10726,17876,10726,25027,3576,17876,3576,25027,17876,10726,17876,3576,25027,10726,25027,3576,17876,17876,17876,25027,25027,17876,25027,25027,10726,-10726,10726,-3576,3576,-10726,3576,-3576,10726,-17876,10726,-25027,3576,-17876,3576,-25027,17876,-10726,17876,-3576,25027,-10726,25027,-3576,17876,-17876,17876,-25027,25027,-17876,25027,-25027,-10726,10726,-10726,3576,-3576,10726,-3576,3576,-10726,17876,-10726,25027,-3576,17876,-3576,25027,-17876,10726,-17876,3576,-25027,10726,-25027,3576,-17876,17876,-17876,25027,-25027,17876,-25027,25027,-10726,-10726,-10726,-3576,-3576,-10726,-3576,-3576,-10726,-17876,-10726,-25027,-3576,-17876,-3576,-25027,-17876,-10726,-17876,-3576,-25027,-10726,-25027,-3576,-17876,-17876,-17876,-25027,-25027,-17876,-25027,-25027,8886,8886,8886,12439,12439,8886,12439,12439,8886,5332,8886,1778,12439,5332,12439,1778,5332,8886,5332,12439,1778,8886,1778,12439,5332,5332,5332,1778,1778,5332,1778,1778,8886,19547,8886,15993,12439,19547,12439,15993,8886,23101,8886,26655,12439,23101,12439,26655,5332,19547,5332,15993,1778,19547,1778,15993,5332,23101,5332,26655,1778,23101,1778,26655,19547,8886,19547,12439,15993,8886,15993,12439,19547,5332,19547,1778,15993,5332,15993,1778,23101,8886,23101,12439,26655,8886,26655,12439,23101,5332,23101,1778,26655,5332,26655,1778,19547,19547,19547,15993,15993,19547,15993,15993,19547,23101,19547,26655,15993,23101,15993,26655,23101,19547,23101,15993,26655,19547,26655,15993,23101,23101,23101,26655,26655,23101,26655,26655,8886,-8886,8886,-12439,12439,-8886,12439,-12439,8886,-5332,8886,-1778,12439,-5332,12439,-1778,5332,-8886,5332,-12439,1778,-8886,1778,-12439,5332,-5332,5332,-1778,1778,-5332,1778,-1778,8886,-19547,8886,-15993,12439,-19547,12439,-15993,8886,-23101,8886,-26655,12439,-23101,12439,-26655,5332,-19547,5332,-15993,1778,-19547,1778,-15993,5332,-23101,5332,-26655,1778,-23101,1778,-26655,19547,-8886,19547,-12439,15993,-8886,15993,-12439,19547,-5332,19547,-1778,15993,-5332,15993,-1778,23101,-8886,23101,-12439,26655,-8886,26655,-12439,23101,-5332,23101,-1778,26655,-5332,26655,-1778,19547,-19547,19547,-15993,15993,-19547,15993,-15993,19547,-23101,19547,-26655,15993,-23101,15993,-26655,23101,-19547,23101,-15993,26655,-19547,26655,-15993,23101,-23101,23101,-26655,26655,-23101,26655,-26655,-8886,8886,-8886,12439,-12439,8886,-12439,12439,-8886,5332,-8886,1778,-12439,5332,-12439,1778,-5332,8886,-5332,12439,-1778,8886,-1778,12439,-5332,5332,-5332,1778,-1778,5332,-1778,1778,-8886,19547,-8886,15993,-12439,19547,-12439,15993,-8886,23101,-8886,26655,-12439,23101,-12439,26655,-5332,19547,-5332,15993,-1778,19547,-1778,15993,-5332,23101,-5332,26655,-1778,23101,-1778,26655,-19547,8886,-19547,12439,-15993,8886,-15993,12439,-19547,5332,-19547,1778,-15993,5332,-15993,1778,-23101,8886,-23101,12439,-26655,8886,-26655,12439,-23101,5332,-23101,1778,-26655,5332,-26655,1778,-19547,19547,-19547,15993,-15993,19547,-15993,15993,-19547,23101,-19547,26655,-15993,23101,-15993,26655,-23101,19547,-23101,15993,-26655,19547,-26655,15993,-23101,23101,-23101,26655,-26655,23101,-26655,26655,-8886,-8886,-8886,-12439,-12439,-8886,-12439,-12439,-8886,-5332,-8886,-1778,-12439,-5332,-12439,-1778,-5332,-8886,-5332,-12439,-1778,-8886,-1778,-12439,-5332,-5332,-5332,-1778,-1778,-5332,-1778,-1778,-8886,-19547,-8886,-15993,-12439,-19547,-12439,-15993,-8886,-23101,-8886,-26655,-12439,-23101,-12439,-26655,-5332,-19547,-5332,-15993,-1778,-19547,-1778,-15993,-5332,-23101,-5332,-26655,-1778,-23101,-1778,-26655,-19547,-8886,-19547,-12439,-15993,-8886,-15993,-12439,-19547,-5332,-19547,-1778,-15993,-5332,-15993,-1778,-23101,-8886,-23101,-12439,-26655,-8886,-26655,-12439,-23101,-5332,-23101,-1778,-26655,-5332,-26655,-1778,-19547,-19547,-19547,-15993,-15993,-19547,-15993,-15993,-19547,-23101,-19547,-26655,-15993,-23101,-15993,-26655,-23101,-19547,-23101,-15993,-26655,-19547,-26655,-15993,-23101,-23101,-23101,-26655,-26655,-23101,-26655,-26655}; +short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,-16384,16384,16384,-16384,-16384,-16384,7327,7327,-7327,7327,7327,-7327,-7327,-7327,21981,7327,-21981,7327,21981,-7327,-21981,-7327,7327,21981,-7327,21981,7327,-21981,-7327,-21981,21981,21981,-21981,21981,21981,-21981,-21981,-21981,10726,10726,-10726,10726,10726,-10726,-10726,-10726,17876,10726,-17876,10726,17876,-10726,-17876,-10726,10726,17876,-10726,17876,10726,-17876,-10726,-17876,17876,17876,-17876,17876,17876,-17876,-17876,-17876,3576,10726,-3576,10726,3576,-10726,-3576,-10726,25027,10726,-25027,10726,25027,-10726,-25027,-10726,3576,17876,-3576,17876,3576,-17876,-3576,-17876,25027,17876,-25027,17876,25027,-17876,-25027,-17876,10726,3576,-10726,3576,10726,-3576,-10726,-3576,17876,3576,-17876,3576,17876,-3576,-17876,-3576,10726,25027,-10726,25027,10726,-25027,-10726,-25027,17876,25027,-17876,25027,17876,-25027,-17876,-25027,3576,3576,-3576,3576,3576,-3576,-3576,-3576,25027,3576,-25027,3576,25027,-3576,-25027,-3576,3576,25027,-3576,25027,3576,-25027,-3576,-25027,25027,25027,-25027,25027,25027,-25027,-25027,-25027,8886,8886,-8886,8886,8886,-8886,-8886,-8886,19547,8886,-19547,8886,19547,-8886,-19547,-8886,8886,19547,-8886,19547,8886,-19547,-8886,-19547,19547,19547,-19547,19547,19547,-19547,-19547,-19547,5332,8886,-5332,8886,5332,-8886,-5332,-8886,23101,8886,-23101,8886,23101,-8886,-23101,-8886,5332,19547,-5332,19547,5332,-19547,-5332,-19547,23101,19547,-23101,19547,23101,-19547,-23101,-19547,8886,5332,-8886,5332,8886,-5332,-8886,-5332,19547,5332,-19547,5332,19547,-5332,-19547,-5332,8886,23101,-8886,23101,8886,-23101,-8886,-23101,19547,23101,-19547,23101,19547,-23101,-19547,-23101,5332,5332,-5332,5332,5332,-5332,-5332,-5332,23101,5332,-23101,5332,23101,-5332,-23101,-5332,5332,23101,-5332,23101,5332,-23101,-5332,-23101,23101,23101,-23101,23101,23101,-23101,-23101,-23101,12439,8886,-12439,8886,12439,-8886,-12439,-8886,15993,8886,-15993,8886,15993,-8886,-15993,-8886,12439,19547,-12439,19547,12439,-19547,-12439,-19547,15993,19547,-15993,19547,15993,-19547,-15993,-19547,1778,8886,-1778,8886,1778,-8886,-1778,-8886,26655,8886,-26655,8886,26655,-8886,-26655,-8886,1778,19547,-1778,19547,1778,-19547,-1778,-19547,26655,19547,-26655,19547,26655,-19547,-26655,-19547,12439,5332,-12439,5332,12439,-5332,-12439,-5332,15993,5332,-15993,5332,15993,-5332,-15993,-5332,12439,23101,-12439,23101,12439,-23101,-12439,-23101,15993,23101,-15993,23101,15993,-23101,-15993,-23101,1778,5332,-1778,5332,1778,-5332,-1778,-5332,26655,5332,-26655,5332,26655,-5332,-26655,-5332,1778,23101,-1778,23101,1778,-23101,-1778,-23101,26655,23101,-26655,23101,26655,-23101,-26655,-23101,8886,12439,-8886,12439,8886,-12439,-8886,-12439,19547,12439,-19547,12439,19547,-12439,-19547,-12439,8886,15993,-8886,15993,8886,-15993,-8886,-15993,19547,15993,-19547,15993,19547,-15993,-19547,-15993,5332,12439,-5332,12439,5332,-12439,-5332,-12439,23101,12439,-23101,12439,23101,-12439,-23101,-12439,5332,15993,-5332,15993,5332,-15993,-5332,-15993,23101,15993,-23101,15993,23101,-15993,-23101,-15993,8886,1778,-8886,1778,8886,-1778,-8886,-1778,19547,1778,-19547,1778,19547,-1778,-19547,-1778,8886,26655,-8886,26655,8886,-26655,-8886,-26655,19547,26655,-19547,26655,19547,-26655,-19547,-26655,5332,1778,-5332,1778,5332,-1778,-5332,-1778,23101,1778,-23101,1778,23101,-1778,-23101,-1778,5332,26655,-5332,26655,5332,-26655,-5332,-26655,23101,26655,-23101,26655,23101,-26655,-23101,-26655,12439,12439,-12439,12439,12439,-12439,-12439,-12439,15993,12439,-15993,12439,15993,-12439,-15993,-12439,12439,15993,-12439,15993,12439,-15993,-12439,-15993,15993,15993,-15993,15993,15993,-15993,-15993,-15993,1778,12439,-1778,12439,1778,-12439,-1778,-12439,26655,12439,-26655,12439,26655,-12439,-26655,-12439,1778,15993,-1778,15993,1778,-15993,-1778,-15993,26655,15993,-26655,15993,26655,-15993,-26655,-15993,12439,1778,-12439,1778,12439,-1778,-12439,-1778,15993,1778,-15993,1778,15993,-1778,-15993,-1778,12439,26655,-12439,26655,12439,-26655,-12439,-26655,15993,26655,-15993,26655,15993,-26655,-15993,-26655,1778,1778,-1778,1778,1778,-1778,-1778,-1778,26655,1778,-26655,1778,26655,-1778,-26655,-1778,1778,26655,-1778,26655,1778,-26655,-1778,-26655,26655,26655,-26655,26655,26655,-26655,-26655,-26655}; #endif From 7bcf468e1b4c3d19904977dc05a915e38c53965a Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 29 Jul 2020 13:11:31 +0200 Subject: [PATCH 45/70] Added the changed octave script --- openair1/PHY/NR_REFSIG/nr_gen_mod_table.m | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m index 13a8d4ad09..3fe03b2dc5 100644 --- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m @@ -45,7 +45,7 @@ for r=0:1 %0 -- 1 LS for j=0:1 %0 -- 1 MS %% Formula is dispalayed -qpsk_table(2*r+j+1) = ((1-r*2)*QPSK + 1j*(1-2*j)*QPSK); +qpsk_table(2*j+r+1) = ((1-r*2)*QPSK + 1j*(1-2*j)*QPSK); end end @@ -61,7 +61,7 @@ for b0=0:1 for b1=0:1 for b2=0:1 for b3=0:1 -qam16_table2(b0*8+b1*4+b2*2+b3*1+1) = qam16_table(b0*2+b2*1+1) + 1j*qam16_table(b1*2+b3*1+1); +qam16_table2(b3*8+b2*4+b1*2+b0*1+1) = qam16_table(b0*2+b2*1+1) + 1j*qam16_table(b1*2+b3*1+1); end end end @@ -84,7 +84,7 @@ for b2=0:1 for b3=0:1 for b4=0:1 for b5=0:1 -qam64_table2(b0*32+b1*16+b2*8+b3*4+b4*2+b5*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1); +qam64_table2(b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1); end end end @@ -116,7 +116,7 @@ for b6=0:1 for b7=0:1 %%qam64_table2(b0*32+b1*16+b2*8+b3*4+b4*2+b5*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1); -qam256_table2(b0*128+b1*64+b2*32+b3*16+b4*8+b5*4+b6*2+b7*1+1) = qam256_table(b0*8+b2*4+b4*2+b6*1+1) + 1j*qam256_table(b1*8+b3*4+b5*2+b7*1+1); +qam256_table2(b7*128+b6*64+b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1) = qam256_table(b0*8+b2*4+b4*2+b6*1+1) + 1j*qam256_table(b1*8+b3*4+b5*2+b7*1+1); end end end From 82be36533b47a427689ab46d90df38dea1abe2ca Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 30 Jul 2020 16:49:00 +0200 Subject: [PATCH 46/70] Included special case for 64qam --- openair1/PHY/MODULATION/nr_modulation.c | 30 +++++++++++++++++++------ 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index 289ac1df5f..e0a4254563 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -29,20 +29,36 @@ void nr_modulation(uint32_t *in, int16_t *out) { uint16_t offset; - uint8_t idx, b_idx; + uint16_t mask = ((1<>(i*mod_order)) & mask); + if (mod_order==6) { + uint16_t u = 1; + uint8_t shift_lut[3] = {0, 2, 4}; + for (int i=0; i>((i*mod_order)&0x1f)) & mask); + if ((((i+1)*mod_order)>32*u) && (i!=0)) + idx |= (in[(i*mod_order/32)+1]<>((i*mod_order)&0x1f)) & mask); + + out[i<<1] = nr_mod_table[(offset+idx)<<1]; + out[(i<<1)+1] = nr_mod_table[((offset+idx)<<1)+1]; + } } } From fbd4df014cbad0c7dee0ef89db21c5fce98c7cd6 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 3 Aug 2020 11:22:34 +0200 Subject: [PATCH 47/70] Further improvements additional 50% speed improvement with SIMD vectors --- openair1/PHY/MODULATION/nr_modulation.c | 64 ++++++++++++++++++++----- openair1/PHY/NR_REFSIG/nr_mod_table.h | 4 ++ openair1/PHY/NR_TRANSPORT/nr_dci.c | 4 +- openair1/SIMULATION/NR_PHY/dlschsim.c | 1 - openair1/SIMULATION/NR_PHY/dlsim.c | 1 - openair1/SIMULATION/NR_PHY/pbchsim.c | 1 - openair1/SIMULATION/NR_PHY/prachsim.c | 1 - openair1/SIMULATION/NR_PHY/pucchsim.c | 1 - openair1/SIMULATION/NR_PHY/ulschsim.c | 1 - openair1/SIMULATION/NR_PHY/ulsim.c | 1 - 10 files changed, 57 insertions(+), 22 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index e0a4254563..ee880f8c2a 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -20,6 +20,7 @@ */ #include "nr_modulation.h" +#include "PHY/NR_REFSIG/nr_mod_table.h" extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT]; @@ -30,16 +31,29 @@ void nr_modulation(uint32_t *in, { uint16_t offset; uint16_t mask = ((1<>((i*mod_order)&0x1f)) & mask); @@ -47,18 +61,42 @@ void nr_modulation(uint32_t *in, idx |= (in[(i*mod_order/32)+1]<>((i*mod_order)&0x1f)) & mask); + return; - out[i<<1] = nr_mod_table[(offset+idx)<<1]; - out[(i<<1)+1] = nr_mod_table[((offset+idx)<<1)+1]; - } + case 8: + nr_mod_table32 = (int32_t*) nr_mod_table; + for (int i=0; i>((i*mod_order)&0x1f)) & mask); + + out32[i] = nr_mod_table32[(offset+idx)]; } } diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index 99d207ecc8..f644e86359 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -30,4 +30,8 @@ #define NR_MOD_TABLE_QAM256_OFFSET 87 short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = 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+ +short nr_qpsk_byte_mod_table[2048] = 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+ +short nr_qam16_byte_mod_table[1024] = {7327,7327,7327,7327,-7327,7327,7327,7327,7327,-7327,7327,7327,-7327,-7327,7327,7327,21981,7327,7327,7327,-21981,7327,7327,7327,21981,-7327,7327,7327,-21981,-7327,7327,7327,7327,21981,7327,7327,-7327,21981,7327,7327,7327,-21981,7327,7327,-7327,-21981,7327,7327,21981,21981,7327,7327,-21981,21981,7327,7327,21981,-21981,7327,7327,-21981,-21981,7327,7327,7327,7327,-7327,7327,-7327,7327,-7327,7327,7327,-7327,-7327,7327,-7327,-7327,-7327,7327,21981,7327,-7327,7327,-21981,7327,-7327,7327,21981,-7327,-7327,7327,-21981,-7327,-7327,7327,7327,21981,-7327,7327,-7327,21981,-7327,7327,7327,-21981,-7327,7327,-7327,-21981,-7327,7327,21981,21981,-7327,7327,-21981,21981,-7327,7327,21981,-21981,-7327,7327,-21981,-21981,-7327,7327,7327,7327,7327,-7327,-7327,7327,7327,-7327,7327,-7327,7327,-7327,-7327,-7327,7327,-7327,21981,7327,7327,-7327,-21981,7327,7327,-7327,21981,-7327,7327,-7327,-21981,-7327,7327,-7327,7327,21981,7327,-7327,-7327,21981,7327,-7327,7327,-21981,7327,-7327,-7327,-21981,7327,-7327,21981,21981,7327,-7327,-21981,21981,7327,-7327,21981,-21981,7327,-7327,-21981,-21981,7327,-7327,7327,7327,-7327,-7327,-7327,7327,-7327,-7327,7327,-7327,-7327,-7327,-7327,-7327,-7327,-7327,21981,7327,-7327,-7327,-21981,7327,-7327,-7327,21981,-7327,-7327,-7327,-21981,-7327,-7327,-7327,7327,21981,-7327,-7327,-7327,21981,-7327,-7327,7327,-21981,-7327,-7327,-7327,-21981,-7327,-7327,21981,21981,-7327,-7327,-21981,21981,-7327,-7327,21981,-21981,-7327,-7327,-21981,-21981,-7327,-7327,7327,7327,21981,7327,-7327,7327,21981,7327,7327,-7327,21981,7327,-7327,-7327,21981,7327,21981,7327,21981,7327,-21981,7327,21981,7327,21981,-7327,21981,7327,-21981,-7327,21981,7327,7327,21981,21981,7327,-7327,21981,21981,7327,7327,-21981,21981,7327,-7327,-21981,21981,7327,21981,21981,21981,7327,-21981,21981,21981,7327,21981,-21981,21981,7327,-21981,-21981,21981,7327,7327,7327,-21981,7327,-7327,7327,-21981,7327,7327,-7327,-21981,7327,-7327,-7327,-21981,7327,21981,7327,-21981,7327,-21981,7327,-21981,7327,21981,-7327,-21981,7327,-21981,-7327,-21981,7327,7327,21981,-21981,7327,-7327,21981,-21981,7327,7327,-21981,-21981,7327,-7327,-21981,-21981,7327,21981,21981,-21981,7327,-21981,21981,-21981,7327,21981,-21981,-21981,7327,-21981,-21981,-21981,7327,7327,7327,21981,-7327,-7327,7327,21981,-7327,7327,-7327,21981,-7327,-7327,-7327,21981,-7327,21981,7327,21981,-7327,-21981,7327,21981,-7327,21981,-7327,21981,-7327,-21981,-7327,21981,-7327,7327,21981,21981,-7327,-7327,21981,21981,-7327,7327,-21981,21981,-7327,-7327,-21981,21981,-7327,21981,21981,21981,-7327,-21981,21981,21981,-7327,21981,-21981,21981,-7327,-21981,-21981,21981,-7327,7327,7327,-21981,-7327,-7327,7327,-21981,-7327,7327,-7327,-21981,-7327,-7327,-7327,-21981,-7327,21981,7327,-21981,-7327,-21981,7327,-21981,-7327,21981,-7327,-21981,-7327,-21981,-7327,-21981,-7327,7327,21981,-21981,-7327,-7327,21981,-21981,-7327,7327,-21981,-21981,-7327,-7327,-21981,-21981,-7327,21981,21981,-21981,-7327,-21981,21981,-21981,-7327,21981,-21981,-21981,-7327,-21981,-21981,-21981,-7327,7327,7327,7327,21981,-7327,7327,7327,21981,7327,-7327,7327,21981,-7327,-7327,7327,21981,21981,7327,7327,21981,-21981,7327,7327,21981,21981,-7327,7327,21981,-21981,-7327,7327,21981,7327,21981,7327,21981,-7327,21981,7327,21981,7327,-21981,7327,21981,-7327,-21981,7327,21981,21981,21981,7327,21981,-21981,21981,7327,21981,21981,-21981,7327,21981,-21981,-21981,7327,21981,7327,7327,-7327,21981,-7327,7327,-7327,21981,7327,-7327,-7327,21981,-7327,-7327,-7327,21981,21981,7327,-7327,21981,-21981,7327,-7327,21981,21981,-7327,-7327,21981,-21981,-7327,-7327,21981,7327,21981,-7327,21981,-7327,21981,-7327,21981,7327,-21981,-7327,21981,-7327,-21981,-7327,21981,21981,21981,-7327,21981,-21981,21981,-7327,21981,21981,-21981,-7327,21981,-21981,-21981,-7327,21981,7327,7327,7327,-21981,-7327,7327,7327,-21981,7327,-7327,7327,-21981,-7327,-7327,7327,-21981,21981,7327,7327,-21981,-21981,7327,7327,-21981,21981,-7327,7327,-21981,-21981,-7327,7327,-21981,7327,21981,7327,-21981,-7327,21981,7327,-21981,7327,-21981,7327,-21981,-7327,-21981,7327,-21981,21981,21981,7327,-21981,-21981,21981,7327,-21981,21981,-21981,7327,-21981,-21981,-21981,7327,-21981,7327,7327,-7327,-21981,-7327,7327,-7327,-21981,7327,-7327,-7327,-21981,-7327,-7327,-7327,-21981,21981,7327,-7327,-21981,-21981,7327,-7327,-21981,21981,-7327,-7327,-21981,-21981,-7327,-7327,-21981,7327,21981,-7327,-21981,-7327,21981,-7327,-21981,7327,-21981,-7327,-21981,-7327,-21981,-7327,-21981,21981,21981,-7327,-21981,-21981,21981,-7327,-21981,21981,-21981,-7327,-21981,-21981,-21981,-7327,-21981,7327,7327,21981,21981,-7327,7327,21981,21981,7327,-7327,21981,21981,-7327,-7327,21981,21981,21981,7327,21981,21981,-21981,7327,21981,21981,21981,-7327,21981,21981,-21981,-7327,21981,21981,7327,21981,21981,21981,-7327,21981,21981,21981,7327,-21981,21981,21981,-7327,-21981,21981,21981,21981,21981,21981,21981,-21981,21981,21981,21981,21981,-21981,21981,21981,-21981,-21981,21981,21981,7327,7327,-21981,21981,-7327,7327,-21981,21981,7327,-7327,-21981,21981,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#endif diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index a29211b55b..3344682f20 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -161,7 +161,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, int16_t amp, NR_DL_FRAME_PARMS frame_parms) { - int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1]; // 3 for the max coreset duration + int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1] __attribute__((aligned(128))); // 3 for the max coreset duration uint16_t cset_start_sc; uint8_t cset_start_symb, cset_nsymb; int k,l,k_prime,dci_idx, dmrs_idx; @@ -260,7 +260,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, scrambled_output[6], scrambled_output[7], scrambled_output[8], scrambled_output[9], scrambled_output[10],scrambled_output[11] ); #endif /// QPSK modulation - int16_t mod_dci[NR_MAX_DCI_SIZE>>1]; + int16_t mod_dci[NR_MAX_DCI_SIZE>>1] __attribute__((aligned(128))); nr_modulation(scrambled_output, encoded_length, DMRS_MOD_ORDER, mod_dci); //Qm = 2 as DMRS is QPSK modulated #ifdef DEBUG_DCI diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index 9374050e58..8f53b9acc4 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -37,7 +37,6 @@ #include "PHY/INIT/phy_init.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 137c358d7f..90aa3f6333 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -39,7 +39,6 @@ #include "PHY/INIT/phy_init.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c index 2144652f86..8c37024858 100644 --- a/openair1/SIMULATION/NR_PHY/pbchsim.c +++ b/openair1/SIMULATION/NR_PHY/pbchsim.c @@ -33,7 +33,6 @@ #include "PHY/defs_nr_UE.h" #include "PHY/defs_gNB.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 2db5bc905c..950f9a67f6 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -37,7 +37,6 @@ #include "SCHED_NR_UE/phy_frame_config_nr.h" #include "PHY/phy_vars_nr_ue.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index 004a7b8de8..86f7d651e4 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -33,7 +33,6 @@ #include "PHY/defs_nr_UE.h" #include "PHY/defs_gNB.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index b0557ef1b4..af49aa757b 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -34,7 +34,6 @@ #include "PHY/defs_gNB.h" #include "PHY/INIT/phy_init.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index bcaa967a30..f016092442 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -37,7 +37,6 @@ #include "PHY/MODULATION/modulation_UE.h" #include "PHY/MODULATION/nr_modulation.h" #include "PHY/NR_REFSIG/dmrs_nr.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_sch_dmrs.h" From 18a3747e82431efb5659cc74b72ecd93c2836a9f Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 3 Aug 2020 11:46:33 +0200 Subject: [PATCH 48/70] added the changed octave script --- openair1/PHY/NR_REFSIG/nr_gen_mod_table.m | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m index 3fe03b2dc5..6e1415bf28 100644 --- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m @@ -126,6 +126,49 @@ end end end +%%QPSK byte +for b0=0:1 +for b1=0:1 +for b2=0:1 +for b3=0:1 +for b4=0:1 +for b5=0:1 +for b6=0:1 +for b7=0:1 +qpsk_byte_table2(b7*128+b6*64+b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1,:)=[(1-b0*2)*QPSK (1-2*b1)*QPSK (1-b2*2)*QPSK (1-2*b3)*QPSK ... + (1-b4*2)*QPSK (1-2*b5)*QPSK (1-b6*2)*QPSK (1-2*b7)*QPSK]; + +end +end +end +end +end +end +end +end + +%%16QAM byte +qam16_byte_table2=[]; +for b0=0:1 +for b1=0:1 +for b2=0:1 +for b3=0:1 +for b4=0:1 +for b5=0:1 +for b6=0:1 +for b7=0:1 +qam16_byte_table2(b7*128+b6*64+b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1,:)=[qam16_table(b0*2+b2*1+1) qam16_table(b1*2+b3*1+1) ... + qam16_table(b4*2+b6*1+1) qam16_table(b5*2+b7*1+1) ]; + +end +end +end +end +end +end +end +end + table = round(K * [ 0; bpsk_table(:); qpsk_table(:);qam16_table2(:); qam64_table2(:);qam256_table2(:) ]); %scatter (real(qam256_table2), imag(qam256_table2), 'x'); save mod_table.mat table @@ -133,6 +176,8 @@ save mod_table.mat table table2 = zeros(1,length(table)*2); table2(1:2:end) = real(table); table2(2:2:end) = imag(table); +qpsk_byte_table2=round(K * qpsk_byte_table2'(:)); +qam16_byte_table2=round(K * qam16_byte_table2'(:)); fd = fopen("nr_mod_table.h","w"); fprintf(fd,"#define NR_MOD_TABLE_SIZE_SHORT %d\n", length(table)*2); @@ -144,4 +189,10 @@ fprintf(fd,"#define NR_MOD_TABLE_QAM256_OFFSET %d\n", 87); fprintf(fd,"short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {"); fprintf(fd,"%d,",table2(1:end-1)); fprintf(fd,"%d};\n",table2(end)); +fprintf(fd,"short nr_qpsk_mod_table[2048] = {"); +fprintf(fd,"%d,",qpsk_byte_table2(1:end-1)); +fprintf(fd,"%d};\n",qpsk_byte_table2(end)); +fprintf(fd,"short nr_qam16_mod_table[1024] = {"); +fprintf(fd,"%d,",qam16_byte_table2(1:end-1)); +fprintf(fd,"%d};\n",qam16_byte_table2(end)); fclose(fd); From f8675c258dc2e5a7a1327667c5f22e3628cdf254 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 3 Aug 2020 14:11:52 +0200 Subject: [PATCH 49/70] Fixed linking errors --- executables/nr-softmodem.c | 2 -- executables/nr-uesoftmodem.c | 1 - 2 files changed, 3 deletions(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 77f6dc14b1..22fca57970 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -84,8 +84,6 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "NB_IoT_interface.h" #include "x2ap_eNB.h" -short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,-16384,16384,16384,-16384,-16384,-16384,7327,7327,-7327,7327,7327,-7327,-7327,-7327,21981,7327,-21981,7327,21981,-7327,-21981,-7327,7327,21981,-7327,21981,7327,-21981,-7327,-21981,21981,21981,-21981,21981,21981,-21981,-21981,-21981,10726,10726,-10726,10726,10726,-10726,-10726,-10726,17876,10726,-17876,10726,17876,-10726,-17876,-10726,10726,17876,-10726,17876,10726,-17876,-10726,-17876,17876,17876,-17876,17876,17876,-17876,-17876,-17876,3576,10726,-3576,10726,3576,-10726,-3576,-10726,25027,10726,-25027,10726,25027,-10726,-25027,-10726,3576,17876,-3576,17876,3576,-17876,-3576,-17876,25027,17876,-25027,17876,25027,-17876,-25027,-17876,10726,3576,-10726,3576,10726,-3576,-10726,-3576,17876,3576,-17876,3576,17876,-3576,-17876,-3576,10726,25027,-10726,25027,10726,-25027,-10726,-25027,17876,25027,-17876,25027,17876,-25027,-17876,-25027,3576,3576,-3576,3576,3576,-3576,-3576,-3576,25027,3576,-25027,3576,25027,-3576,-25027,-3576,3576,25027,-3576,25027,3576,-25027,-3576,-25027,25027,25027,-25027,25027,25027,-25027,-25027,-25027,8886,8886,-8886,8886,8886,-8886,-8886,-8886,19547,8886,-19547,8886,19547,-8886,-19547,-8886,8886,19547,-8886,19547,8886,-19547,-8886,-19547,19547,19547,-19547,19547,19547,-19547,-19547,-19547,5332,8886,-5332,8886,5332,-8886,-5332,-8886,23101,8886,-23101,8886,23101,-8886,-23101,-8886,5332,19547,-5332,19547,5332,-19547,-5332,-19547,23101,19547,-23101,19547,23101,-19547,-23101,-19547,8886,5332,-8886,5332,8886,-5332,-8886,-5332,19547,5332,-19547,5332,19547,-5332,-19547,-5332,8886,23101,-8886,23101,8886,-23101,-8886,-23101,19547,23101,-19547,23101,19547,-23101,-19547,-23101,5332,5332,-5332,5332,5332,-5332,-5332,-5332,23101,5332,-23101,5332,23101,-5332,-23101,-5332,5332,23101,-5332,23101,5332,-23101,-5332,-23101,23101,23101,-23101,23101,23101,-23101,-23101,-23101,12439,8886,-12439,8886,12439,-8886,-12439,-8886,15993,8886,-15993,8886,15993,-8886,-15993,-8886,12439,19547,-12439,19547,12439,-19547,-12439,-19547,15993,19547,-15993,19547,15993,-19547,-15993,-19547,1778,8886,-1778,8886,1778,-8886,-1778,-8886,26655,8886,-26655,8886,26655,-8886,-26655,-8886,1778,19547,-1778,19547,1778,-19547,-1778,-19547,26655,19547,-26655,19547,26655,-19547,-26655,-19547,12439,5332,-12439,5332,12439,-5332,-12439,-5332,15993,5332,-15993,5332,15993,-5332,-15993,-5332,12439,23101,-12439,23101,12439,-23101,-12439,-23101,15993,23101,-15993,23101,15993,-23101,-15993,-23101,1778,5332,-1778,5332,1778,-5332,-1778,-5332,26655,5332,-26655,5332,26655,-5332,-26655,-5332,1778,23101,-1778,23101,1778,-23101,-1778,-23101,26655,23101,-26655,23101,26655,-23101,-26655,-23101,8886,12439,-8886,12439,8886,-12439,-8886,-12439,19547,12439,-19547,12439,19547,-12439,-19547,-12439,8886,15993,-8886,15993,8886,-15993,-8886,-15993,19547,15993,-19547,15993,19547,-15993,-19547,-15993,5332,12439,-5332,12439,5332,-12439,-5332,-12439,23101,12439,-23101,12439,23101,-12439,-23101,-12439,5332,15993,-5332,15993,5332,-15993,-5332,-15993,23101,15993,-23101,15993,23101,-15993,-23101,-15993,8886,1778,-8886,1778,8886,-1778,-8886,-1778,19547,1778,-19547,1778,19547,-1778,-19547,-1778,8886,26655,-8886,26655,8886,-26655,-8886,-26655,19547,26655,-19547,26655,19547,-26655,-19547,-26655,5332,1778,-5332,1778,5332,-1778,-5332,-1778,23101,1778,-23101,1778,23101,-1778,-23101,-1778,5332,26655,-5332,26655,5332,-26655,-5332,-26655,23101,26655,-23101,26655,23101,-26655,-23101,-26655,12439,12439,-12439,12439,12439,-12439,-12439,-12439,15993,12439,-15993,12439,15993,-12439,-15993,-12439,12439,15993,-12439,15993,12439,-15993,-12439,-15993,15993,15993,-15993,15993,15993,-15993,-15993,-15993,1778,12439,-1778,12439,1778,-12439,-1778,-12439,26655,12439,-26655,12439,26655,-12439,-26655,-12439,1778,15993,-1778,15993,1778,-15993,-1778,-15993,26655,15993,-26655,15993,26655,-15993,-26655,-15993,12439,1778,-12439,1778,12439,-1778,-12439,-1778,15993,1778,-15993,1778,15993,-1778,-15993,-1778,12439,26655,-12439,26655,12439,-26655,-12439,-26655,15993,26655,-15993,26655,15993,-26655,-15993,-26655,1778,1778,-1778,1778,1778,-1778,-1778,-1778,26655,1778,-26655,1778,26655,-1778,-26655,-1778,1778,26655,-1778,26655,1778,-26655,-1778,-26655,26655,26655,-26655,26655,26655,-26655,-26655,-26655}; - pthread_cond_t nfapi_sync_cond; pthread_mutex_t nfapi_sync_mutex; int nfapi_sync_var=-1; //!< protected by mutex \ref nfapi_sync_mutex diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 6d3bbc9038..3630ef91d4 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -44,7 +44,6 @@ #include "SCHED/sched_common_vars.h" #include "PHY/MODULATION/modulation_vars.h" //#include "../../SIMU/USER/init_lte.h" -#include "PHY/NR_REFSIG/nr_mod_table.h" #include "LAYER2/MAC/mac_vars.h" #include "RRC/LTE/rrc_vars.h" From 0e5d4fe2687956d2c9baa98ac40f4aa745c362c5 Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Thu, 6 Aug 2020 15:32:30 +0800 Subject: [PATCH 50/70] fix CUDA latency --- CONTRIBUTING.md | 9 +- ci-scripts/.gitignore | 1 + ci-scripts/checkAddedWarnings.sh | 2 +- ci-scripts/constants.py | 1 + ci-scripts/cppcheck_suppressions.list | 1 + ci-scripts/doc/vm_based_simulator_env.md | 1 - ci-scripts/html.py | 2 +- ci-scripts/main.py | 76 +- ci-scripts/oai-ci-vm-tool | 4 +- ci-scripts/ran.py | 57 +- ci-scripts/reportBuildLocally.sh | 4 +- ci-scripts/reportTestLocally.sh | 4 +- ci-scripts/rrc-files/rbconfig.raw | Bin 8 -> 0 bytes ci-scripts/rrc-files/reconfig.raw | Bin 479 -> 0 bytes ci-scripts/runTestOnVM.sh | 56 +- .../enb_ue_usrp210_band7_epc_start.xml | 13 - ...st_05mhz_tm1_rrc_inactivity_no_flexran.xml | 1 + ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml | 2 +- ci-scripts/xml_files/gnb_usrp_build.xml | 1 + .../if4p5_usrp210_band40_test_10mhz.xml | 1 + .../xml_files/multi_rru_band38_build.xml | 12 +- .../multi_rru_band38_test_10mhz_tm1.xml | 2 +- ci-scripts/xml_files/nr_ue_usrp_build.xml | 1 + cmake_targets/CMakeLists.txt | 295 +-- cmake_targets/autotests/README.txt | 12 +- cmake_targets/autotests/test_case_list.xml | 81 +- cmake_targets/build_oai | 8 +- cmake_targets/tools/build_helper | 31 +- common/config/libconfig/config_libconfig.c | 4 +- common/utils/LOG/vcd_signal_dumper.c | 24 +- common/utils/LOG/vcd_signal_dumper.h | 23 + common/utils/T/T_defs.h | 2 +- common/utils/T/T_messages.txt | 103 + common/utils/nr/nr_common.c | 10 +- common/utils/ocp_itti/intertask_interface.cpp | 12 +- common/utils/ocp_itti/intertask_interface.h | 3 +- doc/BUILD.md | 1 - doc/FEATURE_SET.md | 175 +- doc/RUNMODEM.md | 47 + executables/main-ocp.c | 2 + executables/nr-gnb.c | 18 +- executables/nr-ru.c | 131 +- executables/nr-softmodem-common.h | 6 + executables/nr-softmodem.c | 62 +- executables/nr-softmodem.h | 1 + executables/nr-ue.c | 175 +- executables/nr-uesoftmodem.c | 118 +- executables/nr-uesoftmodem.h | 1 - executables/softmodem-common.h | 4 + .../nfapi/public_inc/fapi_nr_ue_constants.h | 2 + .../nfapi/public_inc/fapi_nr_ue_interface.h | 41 +- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 83 +- nfapi/open-nFAPI/nfapi/src/nfapi.c | 2 +- openair1/PHY/CODING/TESTBENCH/ldpctest.c | 32 +- openair1/PHY/CODING/TESTBENCH/polartest.c | 17 +- openair1/PHY/CODING/coding_defs.h | 13 + openair1/PHY/CODING/crc_byte.c | 41 + .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu | 288 +-- .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h | 8 +- .../CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h | 212 --- .../nrLDPC_decoder_LYC/nrLDPC_init_mem.h | 86 - .../CODING/nrLDPC_decoder_LYC/nrLDPC_types.h | 106 -- .../CODING/nrPolar_tools/nr_polar_decoder.c | 10 +- .../nrPolar_tools/nr_polar_decoding_tools.c | 6 +- .../PHY/CODING/nrPolar_tools/nr_polar_defs.h | 2 +- .../CODING/nrPolar_tools/nr_polar_encoder.c | 27 +- .../CODING/nrPolar_tools/nr_polar_uci_defs.h | 4 +- openair1/PHY/CODING/nr_polar_init.c | 48 +- openair1/PHY/CODING/nr_rate_matching.c | 9 +- openair1/PHY/INIT/nr_init.c | 26 +- openair1/PHY/INIT/nr_init_ru.c | 10 +- openair1/PHY/INIT/nr_init_ue.c | 50 +- .../PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c | 12 +- openair1/PHY/LTE_ESTIMATION/lte_estimation.h | 9 +- .../lte_ul_channel_estimation.c | 26 +- openair1/PHY/LTE_TRANSPORT/dci_tools.c | 5 - openair1/PHY/LTE_TRANSPORT/dlsch_coding.c | 2 +- .../PHY/LTE_TRANSPORT/ulsch_demodulation.c | 6 +- .../PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c | 7 +- openair1/PHY/MODULATION/nr_modulation.c | 2 + openair1/PHY/MODULATION/slot_fep_nr.c | 38 +- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 135 +- openair1/PHY/NR_REFSIG/dmrs_nr.c | 27 +- openair1/PHY/NR_REFSIG/dmrs_nr.h | 5 + openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 34 +- openair1/PHY/NR_REFSIG/nr_gold.c | 1 + openair1/PHY/NR_REFSIG/nr_refsig.h | 1 + openair1/PHY/NR_REFSIG/scrambling_luts.c | 3 +- openair1/PHY/NR_TRANSPORT/nr_dci.c | 39 +- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 20 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 44 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 21 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c | 41 - openair1/PHY/NR_TRANSPORT/nr_pbch.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 763 +++++--- openair1/PHY/NR_TRANSPORT/nr_prach.h | 796 -------- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 229 +-- openair1/PHY/NR_TRANSPORT/nr_pss.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_sss.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_transport.h | 154 -- .../NR_TRANSPORT/nr_transport_common_proto.h | 26 +- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 188 +- .../NR_TRANSPORT/nr_transport_proto_common.h | 1691 ----------------- openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 57 +- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 22 +- .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 214 ++- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 942 ++++++--- .../PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c | 19 +- openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h | 4 +- .../PHY/NR_UE_ESTIMATION/nr_ue_measurements.c | 8 +- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 56 +- .../PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 46 +- .../NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 236 +-- .../PHY/NR_UE_TRANSPORT/nr_initial_sync.c | 7 +- openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 1279 +++++++------ .../NR_UE_TRANSPORT/nr_transport_proto_ue.h | 41 +- .../PHY/NR_UE_TRANSPORT/nr_transport_ue.h | 3 +- .../PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c | 22 +- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 128 +- openair1/PHY/NR_UE_TRANSPORT/pss_nr.c | 5 + openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 74 +- openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h | 3 +- openair1/PHY/TOOLS/Makefile | 20 +- openair1/PHY/TOOLS/nr_phy_scope.c | 1645 +++++++--------- openair1/PHY/TOOLS/nr_phy_scope.h | 57 +- openair1/PHY/TOOLS/oai_dfts.c | 982 +++++++++- openair1/PHY/TOOLS/tools_defs.h | 4 - openair1/PHY/defs_RU.h | 19 +- openair1/PHY/defs_gNB.h | 34 +- openair1/PHY/defs_nr_UE.h | 19 +- openair1/PHY/defs_nr_common.h | 55 +- openair1/PHY/impl_defs_nr.h | 10 +- openair1/SCHED/phy_procedures_lte_eNb.c | 6 +- openair1/SCHED/ru_procedures.c | 8 +- openair1/SCHED_NR/fapi_nr_l1.c | 52 +- openair1/SCHED_NR/nr_prach_procedures.c | 7 +- openair1/SCHED_NR/nr_ru_procedures.c | 6 +- openair1/SCHED_NR/phy_frame_config_nr.c | 67 + openair1/SCHED_NR/phy_frame_config_nr.h | 2 + openair1/SCHED_NR/phy_procedures_nr_gNB.c | 163 +- openair1/SCHED_NR/sched_nr.h | 1 + openair1/SCHED_NR_UE/defs.h | 14 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 265 +-- openair1/SCHED_NR_UE/phy_frame_config_nr.h | 1 - openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 1095 ++++++----- .../SCHED_NR_UE/pucch_power_control_ue_nr.c | 2 +- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 317 ++- openair1/SCHED_NR_UE/pucch_uci_ue_nr.h | 16 +- openair1/SIMULATION/NR_PHY/dlschsim.c | 9 +- openair1/SIMULATION/NR_PHY/dlsim.c | 300 +-- .../SIMULATION/NR_PHY/nr_dummy_functions.c | 2 +- openair1/SIMULATION/NR_PHY/nr_unitary_defs.h | 18 + openair1/SIMULATION/NR_PHY/pbchsim.c | 4 +- openair1/SIMULATION/NR_PHY/prachsim.c | 598 +++--- openair1/SIMULATION/NR_PHY/pucchsim.c | 36 +- openair1/SIMULATION/NR_PHY/ulschsim.c | 6 +- openair1/SIMULATION/NR_PHY/ulsim.c | 608 +++--- .../SIMULATION/TOOLS/multipath_tv_channel.c | 18 +- openair1/SIMULATION/TOOLS/sim.h | 11 +- openair1/SIMULATION/TOOLS/taus.c | 3 +- openair2/COMMON/platform_constants.h | 1 + openair2/COMMON/s1ap_messages_def.h | 1 + openair2/COMMON/s1ap_messages_types.h | 38 +- openair2/COMMON/x2ap_messages_types.h | 5 +- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 425 ++--- .../CONTROL_MODULES/MAC/flexran_agent_mac.h | 13 +- .../MAC/flexran_agent_mac_internal.c | 858 ++------- .../MAC/flexran_agent_mac_internal.h | 40 +- .../flexran_agent_mac_slice_verification.c | 343 ---- .../flexran_agent_mac_slice_verification.h | 6 - .../CONTROL_MODULES/RRC/flexran_agent_rrc.c | 5 +- .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.c | 57 + .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.h | 11 + openair2/ENB_APP/MACRLC_paramdef.h | 3 + .../ENB_APP/MESSAGES/V2/config_common.proto | 88 +- .../ENB_APP/MESSAGES/V2/config_messages.proto | 10 +- openair2/ENB_APP/enb_app.c | 1 - openair2/ENB_APP/enb_config.c | 15 +- openair2/ENB_APP/flexran_agent_common.c | 81 +- openair2/ENB_APP/flexran_agent_extern.h | 9 +- openair2/ENB_APP/flexran_agent_ran_api.c | 829 ++++---- openair2/ENB_APP/flexran_agent_ran_api.h | 185 +- openair2/F1AP/f1ap_cu_ue_context_management.c | 2 +- openair2/GNB_APP/RRC_nr_paramsvalues.h | 28 +- openair2/GNB_APP/gnb_app.c | 24 +- openair2/GNB_APP/gnb_config.c | 22 +- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 28 +- .../LAYER2/MAC/eNB_scheduler_primitives.c | 55 +- openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 4 +- openair2/LAYER2/MAC/mac.h | 186 +- openair2/LAYER2/MAC/mac_proto.h | 9 +- openair2/LAYER2/MAC/main.c | 48 +- openair2/LAYER2/MAC/pre_processor.c | 641 +++++-- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 246 ++- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 1569 ++++++++++++++- openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h | 23 +- openair2/LAYER2/NR_MAC_UE/config_ue.c | 87 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 114 +- openair2/LAYER2/NR_MAC_UE/mac_extern.h | 4 +- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 135 +- openair2/LAYER2/NR_MAC_UE/main_ue_nr.c | 4 +- .../NR_MAC_UE/nr_ue_dci_configuration.c | 319 ++-- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 1449 ++++++++++---- openair2/LAYER2/NR_MAC_gNB/config.c | 38 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 180 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 810 +++++++- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 6 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 233 ++- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 530 ++++-- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 786 +++++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 51 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 122 +- openair2/LAYER2/NR_MAC_gNB/main.c | 9 +- .../LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c | 3 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h | 70 - openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 250 ++- openair2/LAYER2/PDCP_v10.1.0/pdcp.c | 53 +- openair2/LAYER2/PDCP_v10.1.0/pdcp.h | 6 +- openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c | 80 +- openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c | 3 +- openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c | 22 +- openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h | 2 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 126 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 250 ++- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h | 15 +- openair2/RRC/LTE/MESSAGES/asn1_msg.c | 4 +- openair2/RRC/LTE/MESSAGES/asn1_msg.h | 6 +- openair2/RRC/LTE/rrc_UE.c | 91 +- openair2/RRC/LTE/rrc_defs.h | 16 + openair2/RRC/LTE/rrc_eNB.c | 727 +++++-- openair2/RRC/LTE/rrc_eNB_GTPV1U.c | 1 + openair2/RRC/LTE/rrc_eNB_GTPV1U.h | 7 + openair2/RRC/LTE/rrc_eNB_S1AP.c | 98 +- openair2/RRC/LTE/rrc_eNB_S1AP.h | 2 + openair2/RRC/NR/L2_nr_interface.c | 36 +- openair2/RRC/NR/nr_rrc_defs.h | 7 +- openair2/RRC/NR/nr_rrc_proto.h | 6 +- openair2/RRC/NR/rrc_gNB.c | 151 +- openair2/RRC/NR/rrc_gNB_internode.c | 82 +- openair2/RRC/NR/rrc_gNB_nsa.c | 205 +- openair2/RRC/NR/rrc_gNB_reconfig.c | 247 +-- openair2/RRC/NR_UE/L2_interface_ue.c | 11 + openair2/RRC/NR_UE/rrc_UE.c | 4 +- openair2/RRC/NR_UE/rrc_defs.h | 4 +- openair2/RRC/NR_UE/rrc_proto.h | 12 + openair2/X2AP/x2ap_eNB.c | 66 +- openair2/X2AP/x2ap_eNB_decoder.c | 4 +- openair2/X2AP/x2ap_eNB_generate_messages.c | 115 +- openair2/X2AP/x2ap_eNB_generate_messages.h | 2 +- openair2/X2AP/x2ap_eNB_handler.c | 47 +- openair3/GTPV1-U/gtpv1u_eNB.c | 11 + openair3/S1AP/s1ap_eNB.c | 26 +- openair3/S1AP/s1ap_eNB_decoder.c | 6 + openair3/S1AP/s1ap_eNB_encoder.c | 5 + openair3/S1AP/s1ap_eNB_handlers.c | 18 + openair3/S1AP/s1ap_eNB_nas_procedures.c | 316 +++ openair3/S1AP/s1ap_eNB_nas_procedures.h | 4 + .../ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c | 6 +- .../ETHERNET/USERSPACE/LIB/ethernet_lib.c | 9 +- targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp | 6 + targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp | 5 + targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 11 +- targets/ARCH/rfsimulator/README.md | 14 +- targets/ARCH/rfsimulator/apply_channelmod.c | 8 +- targets/ARCH/rfsimulator/simulator.c | 28 +- targets/ARCH/tcp_bridge/tcp_bridge.c | 6 + targets/COMMON/create_nr_tasks.c | 20 +- .../CONF/gnb.band257.tm1.32PRB.usrpx300.conf | 8 +- .../CONF/gnb.band257.tm1.66PRB.usrpn300.conf | 8 +- .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 27 +- .../CONF/gnb.band78.tm1.106PRB.usrpx300.conf | 26 +- .../CONF/gnb.band78.tm1.217PRB.usrpn300.conf | 15 +- .../CONF/gnb.band78.tm1.217PRB.usrpx300.conf | 15 +- .../CONF/gnb.band78.tm1.273PRB.usrpn300.conf | 15 +- targets/RT/USER/gNB_usrp.gtkw | 59 +- targets/RT/USER/lte-ru.c | 33 +- targets/RT/USER/lte-softmodem.c | 2 + targets/RT/USER/lte-softmodem.h | 4 + targets/RT/USER/lte-uesoftmodem.c | 2 + 283 files changed, 17631 insertions(+), 13409 deletions(-) delete mode 100644 ci-scripts/rrc-files/rbconfig.raw delete mode 100644 ci-scripts/rrc-files/reconfig.raw delete mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h delete mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h delete mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h delete mode 100644 openair1/PHY/NR_TRANSPORT/nr_transport.h delete mode 100644 openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h delete mode 100644 openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 61e44bdd55..7a8634f468 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -2,13 +2,12 @@ We want to make contributing to this project as easy and transparent as possible. -Please refer to the steps described on our website: [How to contribute to OAI](https://www.openairinterface.org/?page_id=112) - 1. Sign and return a Contributor License Agreement to OAI team. -2. Create an account on [Eurecom GitLab Server](https://gitlab.eurecom.fr). -3. Provide the identifiant of this account to the OAI team (mailto:contact@openairinterface.org) so you have developer rights on this repository. +2. We recommend that you provide us with a professional or student email address +2. Register on [Eurecom GitLab Server](https://gitlab.eurecom.fr/users/sign_in) +3. Provide the OAI team with the **username** of this account to (mailto:contact@openairinterface.org) ; we will give you the developer rights on this repository. 4. The policies are described in these wiki pages: [OAI Policies](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/oai-policies-home) - - PLEASE DO NOT FORK the OAI repository on your own Eurecom GitLab account. It just eats up space on our servers. + - PLEASE DO NOT FORK the OAI repository on your own Eurecom GitLab account. It just eats up space on our servers. - You can fork onto another hosting system. But we will NOT accept a merge request from a forked repository. * This decision was made for the license reasons. * The Continuous Integration will reject your merge request. diff --git a/ci-scripts/.gitignore b/ci-scripts/.gitignore index dc5e7c7476..34d19403a7 100644 --- a/ci-scripts/.gitignore +++ b/ci-scripts/.gitignore @@ -1,3 +1,4 @@ +r*.raw enb_*.log ue_*.log ping_*.* diff --git a/ci-scripts/checkAddedWarnings.sh b/ci-scripts/checkAddedWarnings.sh index d366059a85..bda8287a78 100755 --- a/ci-scripts/checkAddedWarnings.sh +++ b/ci-scripts/checkAddedWarnings.sh @@ -110,7 +110,7 @@ MODIFIED_FILES=`git log $TARGET_INIT_COMMIT..$MERGE_COMMMIT --oneline --name-sta NB_WARNINGS_FILES=0 # Retrieve list of warnings -LIST_WARNING_FILES=`egrep "error:|warning:" archives/*/*.Rel15.txt archives/*/basic_simulator_*txt | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto" | sed -e "s#^.*/home/ubuntu/tmp/##" -e "s#^.*/tmp/CI-eNB/##" -e "s#common/utils/.*/itti#common/utils/itti#" | awk -F ":" '{print $1}' | sort | uniq` +LIST_WARNING_FILES=`egrep "error:|warning:" archives/*/*.Rel15.txt | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto" | sed -e "s#^.*/home/ubuntu/tmp/##" -e "s#^.*/tmp/CI-eNB/##" -e "s#common/utils/.*/itti#common/utils/itti#" | awk -F ":" '{print $1}' | sort | uniq` echo "" echo "List of files that have been modified by the Merge Request AND" diff --git a/ci-scripts/constants.py b/ci-scripts/constants.py index 1e7e84fb32..c5698c5a3e 100644 --- a/ci-scripts/constants.py +++ b/ci-scripts/constants.py @@ -57,6 +57,7 @@ OAI_UE_PROCESS_ASSERTION = -22 OAI_UE_PROCESS_FAILED = -23 OAI_UE_PROCESS_NO_TUNNEL_INTERFACE = -24 OAI_UE_PROCESS_SEG_FAULT = -25 +OAI_UE_PROCESS_NO_MBMS_MSGS = -26 OAI_UE_PROCESS_OK = +6 UE_STATUS_DETACHED = 0 diff --git a/ci-scripts/cppcheck_suppressions.list b/ci-scripts/cppcheck_suppressions.list index cad2aab88b..727fd22e74 100644 --- a/ci-scripts/cppcheck_suppressions.list +++ b/ci-scripts/cppcheck_suppressions.list @@ -37,6 +37,7 @@ memleak:openair2/UTIL/OMG/omg_hashtable.c // _emm_as_encode function creates the encoded buffer // memleak:openair3/NAS/UE/EMM/SAP/emm_as.c +memleak:openair1/PHY/INIT/nr_init_ue.c //----------------------------------------------------------------------------- //***************************************************************************** // section for files not used in oai exec's included in CI. diff --git a/ci-scripts/doc/vm_based_simulator_env.md b/ci-scripts/doc/vm_based_simulator_env.md index 5dbcfbd931..95b9d920d5 100644 --- a/ci-scripts/doc/vm_based_simulator_env.md +++ b/ci-scripts/doc/vm_based_simulator_env.md @@ -38,7 +38,6 @@ Last point, this documentation is valid for all CI-supported branches: * `master` * `develop` -* `develop-nr` But the feature set may not be aligned. **The principles still apply.** diff --git a/ci-scripts/html.py b/ci-scripts/html.py index 1a6e3f8fdb..8fa99fa61b 100644 --- a/ci-scripts/html.py +++ b/ci-scripts/html.py @@ -326,7 +326,7 @@ class HTMLManagement(): continue self.htmlFile.write(' \n') - self.htmlFile.write(' ' + str('eNB') + ' Server Characteristics\n') + self.htmlFile.write(' ' + str(machine) + ' Server Characteristics\n') self.htmlFile.write(' \n') self.htmlFile.write(' \n') self.htmlFile.write(' OS Version\n') diff --git a/ci-scripts/main.py b/ci-scripts/main.py index e9313051fc..63358eca38 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -30,6 +30,7 @@ import constants as CONST + #----------------------------------------------------------- # Import #----------------------------------------------------------- @@ -332,12 +333,6 @@ class OaiCiTest(): logging.debug('Found a N3xx device --> resetting it') SSH.command('cd ' + self.UESourceCodePath, '\$', 5) # Initialize_OAI_UE_args usually start with -C and followed by the location in repository - # in case of NR-UE, we may have rrc_config_path (Temporary?) - modifiedUeOptions = str(self.Initialize_OAI_UE_args) - if RAN.Getair_interface() == 'nr': - result = re.search('--rrc_config_path ', modifiedUeOptions) - if result is not None: - modifiedUeOptions = modifiedUeOptions.replace('rrc_config_path ', 'rrc_config_path ' + self.UESourceCodePath + '/') SSH.command('source oaienv', '\$', 5) SSH.command('cd cmake_targets/ran_build/build', '\$', 5) if RAN.Getair_interface() == 'lte': @@ -352,7 +347,17 @@ class OaiCiTest(): SSH.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) - SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + else: + SSH.command('if [ -e rbconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) + SSH.command('if [ -e reconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm reconfig.raw; fi', '\$', 5) + # Copy the RAW files from gNB running directory (maybe on another machine) + copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/rbconfig.raw', '.') + if (copyin_res == 0): + SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './rbconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build') + copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/reconfig.raw', '.') + if (copyin_res == 0): + SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './reconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build') + SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + self.Initialize_OAI_UE_args + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) self.UELogFile = 'ue_' + self.testCase_id + '.log' @@ -2432,6 +2437,7 @@ class OaiCiTest(): nrCRCOK = 0 mbms_messages = 0 HTML.SethtmlUEFailureMsg('') + global_status = CONST.ALL_PROCESSES_OK for line in ue_log_file.readlines(): result = re.search('nr_synchro_time', str(line)) if result is not None: @@ -2554,14 +2560,14 @@ class OaiCiTest(): logging.debug('\033[94m' + mibMsg + '\033[0m') except Exception as e: logging.error('\033[91m' + "SIB5 InterFreqCarrierFreq element not found" + '\033[0m') - result = re.search("DL Carrier Frequency/ARFCN : (?P\d{1,15}/\d{1,4})", str(line)) + result = re.search("DL Carrier Frequency/ARFCN : \-*(?P\d{1,15}/\d{1,4})", str(line)) if result is not None: try: freq = result.group('carrier_frequency') new_freq = re.sub('/[0-9]+','',freq) float_freq = float(new_freq) / 1000000 - HTMLSethtmlUEFailureMsg(HTMLGethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz') - logging.debug('\033[94m' + " DL Carrier Frequency is: " + freq + '\033[0m') + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz') + logging.debug('\033[94m' + " DL Carrier Frequency is: " + str(freq) + '\033[0m') except Exception as e: logging.error('\033[91m' + " DL Carrier Frequency not found" + '\033[0m') result = re.search("AllowedMeasBandwidth : (?P\d{1,7})", str(line)) @@ -2625,36 +2631,36 @@ class OaiCiTest(): else: statMsg = 'UE did NOT SHOW "TRIED TO PUSH MBMS DATA" message(s)' logging.debug('\u001B[1;30;41m ' + statMsg + ' \u001B[0m') + global_status = OAI_UE_PROCESS_NO_MBMS_MSGS HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') if foundSegFault: logging.debug('\u001B[1;37;41m UE ended with a Segmentation Fault! \u001B[0m') if not nrUEFlag: - return CONST.OAI_UE_PROCESS_SEG_FAULT + global_status = CONST.OAI_UE_PROCESS_SEG_FAULT else: if not frequency_found: - return CONST.OAI_UE_PROCESS_SEG_FAULT + global_status = CONST.OAI_UE_PROCESS_SEG_FAULT if foundAssertion: logging.debug('\u001B[1;30;43m UE showed an assertion! \u001B[0m') HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE showed an assertion!\n') if not nrUEFlag: if not mib_found or not frequency_found: - return CONST.OAI_UE_PROCESS_ASSERTION + global_status = CONST.OAI_UE_PROCESS_ASSERTION else: if not frequency_found: - return CONST.OAI_UE_PROCESS_ASSERTION + global_status = CONST.OAI_UE_PROCESS_ASSERTION if foundRealTimeIssue: logging.debug('\u001B[1;37;41m UE faced real time issues! \u001B[0m') HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE faced real time issues!\n') - #return CONST.ENB_PROCESS_REALTIME_ISSUE if nrUEFlag: if not frequency_found: - return CONST.OAI_UE_PROCESS_COULD_NOT_SYNC + global_status = CONST.OAI_UE_PROCESS_COULD_NOT_SYNC else: if no_cell_sync_found and not mib_found: logging.debug('\u001B[1;37;41m UE could not synchronize ! \u001B[0m') HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE could not synchronize!\n') - return CONST.OAI_UE_PROCESS_COULD_NOT_SYNC - return 0 + global_status = CONST.OAI_UE_PROCESS_COULD_NOT_SYNC + return global_status def TerminateFlexranCtrl(self): @@ -3061,7 +3067,7 @@ class OaiCiTest(): logging.debug('\u001B[1m----------------------------------------\u001B[0m') def CheckClassValidity(action,id): - if action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': + if action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': logging.debug('ERROR: test-case ' + id + ' has wrong class ' + action) return False return True @@ -3208,6 +3214,19 @@ def GetParametersFromXML(action): else: CiTestObj.x2_ho_options = string_field + if action == 'Build_PhySim': + ldpc.buildargs = test.findtext('physim_build_args') + forced_workspace_cleanup = test.findtext('forced_workspace_cleanup') + if (forced_workspace_cleanup is None): + ldpc.forced_workspace_cleanup=False + else: + if re.match('true', forced_workspace_cleanup, re.IGNORECASE): + ldpc.forced_workspace_cleanup=True + else: + ldpc.forced_workspace_cleanup=False + + if action == 'Run_PhySim': + ldpc.runargs = test.findtext('physim_run_args') #check if given test is in list #it is in list if one of the strings in 'list' is at the beginning of 'test' @@ -3243,6 +3262,9 @@ EPC.SetHtmlObj(HTML) RAN.SetHtmlObj(HTML) RAN.SetEpcObj(EPC) +import cls_physim #class PhySim for physical simulators build and test +ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build + argvs = sys.argv argc = len(argvs) cwd = os.getcwd() @@ -3264,12 +3286,14 @@ while len(argvs) > 1: CiTestObj.ranRepository = matchReg.group(1) RAN.SetranRepository(matchReg.group(1)) HTML.SetranRepository(matchReg.group(1)) + ldpc.ranRepository=matchReg.group(1) elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) else: matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) doMerge = matchReg.group(1) + ldpc.ranAllowMerge=matchReg.group(1) if ((doMerge == 'true') or (doMerge == 'True')): CiTestObj.ranAllowMerge = True RAN.SetranAllowMerge(True) @@ -3282,6 +3306,7 @@ while len(argvs) > 1: CiTestObj.ranBranch = matchReg.group(1) RAN.SetranBranch(matchReg.group(1)) HTML.SetranBranch(matchReg.group(1)) + ldpc.ranBranch=matchReg.group(1) elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) @@ -3290,6 +3315,7 @@ while len(argvs) > 1: CiTestObj.ranCommitID = matchReg.group(1) RAN.SetranCommitID(matchReg.group(1)) HTML.SetranCommitID(matchReg.group(1)) + ldpc.ranCommitID=matchReg.group(1) elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) @@ -3298,10 +3324,12 @@ while len(argvs) > 1: CiTestObj.ranTargetBranch = matchReg.group(1) RAN.SetranTargetBranch(matchReg.group(1)) HTML.SetranTargetBranch(matchReg.group(1)) + ldpc.ranTargetBranch=matchReg.group(1) elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBIPAddress(matchReg.group(1)) + ldpc.eNBIpAddr=matchReg.group(1) elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1IPAddress(matchReg.group(1)) @@ -3312,6 +3340,7 @@ while len(argvs) > 1: if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBUserName(matchReg.group(1)) + ldpc.eNBUserName=matchReg.group(1) elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1UserName(matchReg.group(1)) @@ -3322,6 +3351,7 @@ while len(argvs) > 1: if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBPassword(matchReg.group(1)) + ldpc.eNBPassWord=matchReg.group(1) elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1Password(matchReg.group(1)) @@ -3332,6 +3362,7 @@ while len(argvs) > 1: if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBSourceCodePath(matchReg.group(1)) + ldpc.eNBSourceCodePath=matchReg.group(1) elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1SourceCodePath(matchReg.group(1)) @@ -3499,7 +3530,7 @@ elif re.match('^InitiateHtml$', mode, re.IGNORECASE): foundCount += 1 count += 1 if foundCount != HTML.GetnbTestXMLfiles(): - HTML.SetnbTestXMLfiles(foundcount) + HTML.SetnbTestXMLfiles(foundCount) if (CiTestObj.ADBIPAddress != 'none'): terminate_ue_flag = False @@ -3702,6 +3733,11 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re CiTestObj.IdleSleep() elif action == 'Perform_X2_Handover': CiTestObj.Perform_X2_Handover() + elif action == 'Build_PhySim': + HTML=ldpc.Build_PhySim(HTML,CONST) + if ldpc.exitStatus==1:sys.exit() + elif action == 'Run_PhySim': + HTML=ldpc.Run_PhySim(HTML,CONST,id) else: sys.exit('Invalid action') CiTestObj.FailReportCnt += 1 diff --git a/ci-scripts/oai-ci-vm-tool b/ci-scripts/oai-ci-vm-tool index 9d6349077f..9b9fe462f1 100755 --- a/ci-scripts/oai-ci-vm-tool +++ b/ci-scripts/oai-ci-vm-tool @@ -186,7 +186,7 @@ function variant__v3__phy_sim { BUILD_OPTIONS="--phy_simulators" VM_MEMORY=8192 VM_DISK=20 - RUN_OPTIONS="./run_exec_autotests.bash -g \"01510* 015111\" -q -np -b" + RUN_OPTIONS="./run_exec_autotests.bash -g \"01510* 015111 015112\" -q -np -b" } function variant__v4__cppcheck { @@ -197,7 +197,7 @@ function variant__v4__cppcheck { } function variant__v5__gnb_usrp { - VM_MEMORY=8192 + VM_MEMORY=10240 VM_CPU=8 NB_PATTERN_FILES=9 BUILD_OPTIONS="--gNB -w USRP" diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 5b5add0adb..287c18021e 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -366,7 +366,7 @@ class RANManagement(): count = 40 buildOAIprocess = True while (count > 0) and buildOAIprocess: - mySSH.command('ps aux | grep --color=never build_ | grep -v grep', '\$', 3) + mySSH.command('ps aux | grep --color=never build_ | grep -v grep', '\$', 6) result = re.search('build_oai', mySSH.getBefore()) if result is None: buildOAIprocess = False @@ -546,6 +546,9 @@ class RANManagement(): # Launch eNB with the modified config file mySSH.command('source oaienv', '\$', 5) mySSH.command('cd cmake_targets', '\$', 5) + if self.air_interface == 'nr': + mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) + mySSH.command('if [ -e reconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm reconfig.raw; fi', '\$', 5) mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) @@ -607,7 +610,11 @@ class RANManagement(): enbDidSync = True time.sleep(10) - if enbDidSync and eNBinNoS1: + rruCheck = False + result = re.search('^rru|^du.band', str(config_file)) + if result is not None: + rruCheck = True + if enbDidSync and eNBinNoS1 and not rruCheck: mySSH.command('ifconfig oaitun_enb1', '\$', 4) mySSH.command('ifconfig oaitun_enb1', '\$', 4) result = re.search('inet addr:1|inet 1', mySSH.getBefore()) @@ -774,7 +781,7 @@ class RANManagement(): mySSH.command('cd ' + self.eNBSourceCodePath, '\$', 5) mySSH.command('cd cmake_targets', '\$', 5) mySSH.command('echo ' + self.eNBPassword + ' | sudo -S rm -f enb.log.zip', '\$', 5) - mySSH.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 60) + mySSH.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt physim_*.log', '\$', 60) mySSH.command('echo ' + self.eNBPassword + ' | sudo -S rm enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 5) mySSH.close() @@ -800,8 +807,11 @@ class RANManagement(): uciStatMsgCount = 0 pdcpFailure = 0 ulschFailure = 0 + ulschAllocateCCEerror = 0 + uplinkSegmentsAborted = 0 ulschReceiveOK = 0 gnbRxTxWakeUpFailure = 0 + gnbTxWriteThreadEnabled = False cdrxActivationMessageCount = 0 dropNotEnoughRBs = 0 mbmsRequestMsg = 0 @@ -812,6 +822,7 @@ class RANManagement(): X2HO_state = CONST.X2_HO_REQ_STATE__IDLE X2HO_inNbProcedures = 0 X2HO_outNbProcedures = 0 + global_status = CONST.ALL_PROCESSES_OK for line in enb_log_file.readlines(): if X2HO_state == CONST.X2_HO_REQ_STATE__IDLE: result = re.search('target eNB Receives X2 HO Req X2AP_HANDOVER_REQ', str(line)) @@ -914,9 +925,18 @@ class RANManagement(): result = re.search('could not wakeup gNB rxtx process', str(line)) if result is not None: gnbRxTxWakeUpFailure += 1 + result = re.search('tx write thread ready', str(line)) + if result is not None: + gnbTxWriteThreadEnabled = True result = re.search('ULSCH in error in round|ULSCH 0 in error', str(line)) if result is not None: ulschFailure += 1 + result = re.search('ERROR ALLOCATING CCEs', str(line)) + if result is not None: + ulschAllocateCCEerror += 1 + result = re.search('uplink segment error.*aborted [1-9] segments', str(line)) + if result is not None: + uplinkSegmentsAborted += 1 result = re.search('ULSCH received ok', str(line)) if result is not None: ulschReceiveOK += 1 @@ -948,6 +968,10 @@ class RANManagement(): statMsg = nodeB_prefix + 'NB showed ' + str(gnbRxTxWakeUpFailure) + ' "could not wakeup gNB rxtx process" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') htmleNBFailureMsg += statMsg + '\n' + if gnbTxWriteThreadEnabled: + statMsg = nodeB_prefix + 'NB ran with TX Write thread enabled' + logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') + htmleNBFailureMsg += statMsg + '\n' if uciStatMsgCount > 0: statMsg = nodeB_prefix + 'NB showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') @@ -960,6 +984,14 @@ class RANManagement(): statMsg = nodeB_prefix + 'NB showed ' + str(ulschFailure) + ' "ULSCH in error in round" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') htmleNBFailureMsg += statMsg + '\n' + if ulschAllocateCCEerror > 0: + statMsg = nodeB_prefix + 'NB showed ' + str(ulschAllocateCCEerror) + ' "eNB_dlsch_ulsch_scheduler(); ERROR ALLOCATING CCEs" message(s)' + logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') + htmleNBFailureMsg += statMsg + '\n' + if uplinkSegmentsAborted > 0: + statMsg = nodeB_prefix + 'NB showed ' + str(uplinkSegmentsAborted) + ' "uplink segment error 0/2, aborted * segments" message(s)' + logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') + htmleNBFailureMsg += statMsg + '\n' if dropNotEnoughRBs > 0: statMsg = 'eNB showed ' + str(dropNotEnoughRBs) + ' "dropping, not enough RBs" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') @@ -1030,30 +1062,23 @@ class RANManagement(): rruMsg = 'Slave RRU DID NOT receive the RRU_frame_resynch command from RAU' logging.debug('\u001B[1;37;41m ' + rruMsg + ' \u001B[0m') htmleNBFailureMsg += rruMsg + '\n' - self.prematureExit(True) - return CONST.ENB_PROCESS_SLAVE_RRU_NOT_SYNCED + self.prematureExit = True + global_status = CONST.ENB_PROCESS_SLAVE_RRU_NOT_SYNCED if foundSegFault: logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB ended with a Segmentation Fault! \u001B[0m') - if self.htmlObj is not None: - self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg) - return CONST.ENB_PROCESS_SEG_FAULT + global_status = CONST.ENB_PROCESS_SEG_FAULT if foundAssertion: logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB ended with an assertion! \u001B[0m') htmleNBFailureMsg += msgAssertion - if self.htmlObj is not None: - self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg) - return CONST.ENB_PROCESS_ASSERTION + global_status = CONST.ENB_PROCESS_ASSERTION if foundRealTimeIssue: logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB faced real time issues! \u001B[0m') htmleNBFailureMsg += nodeB_prefix + 'NB faced real time issues!\n' - #return CONST.ENB_PROCESS_REALTIME_ISSUE if rlcDiscardBuffer > 0: rlcMsg = nodeB_prefix + 'NB RLC discarded ' + str(rlcDiscardBuffer) + ' buffer(s)' logging.debug('\u001B[1;37;41m ' + rlcMsg + ' \u001B[0m') htmleNBFailureMsg += rlcMsg + '\n' - if self.htmlObj is not None: - self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg) - return CONST.ENB_PROCESS_REALTIME_ISSUE + global_status = CONST.ENB_PROCESS_REALTIME_ISSUE if self.htmlObj is not None: self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg) - return 0 + return global_status diff --git a/ci-scripts/reportBuildLocally.sh b/ci-scripts/reportBuildLocally.sh index 0a75ff25b7..44d200c3b6 100755 --- a/ci-scripts/reportBuildLocally.sh +++ b/ci-scripts/reportBuildLocally.sh @@ -53,7 +53,7 @@ function details_table { echo " Message" >> $3 echo " " >> $3 - LIST_MESSAGES=`egrep "error:|warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto"` + LIST_MESSAGES=`egrep "error:|warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto|disabling jobserver mode"` COMPLETE_MESSAGE="start" for MESSAGE in $LIST_MESSAGES do @@ -146,7 +146,7 @@ function summary_table_row { else echo " $NB_ERRORS" >> ./build_results.html fi - NB_WARNINGS=`egrep "warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto" | egrep -c "warning:"` + NB_WARNINGS=`egrep "warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto|disabling jobserver mode" | egrep -c "warning:"` if [ $NB_WARNINGS -eq 0 ] then echo " $NB_WARNINGS" >> ./build_results.html diff --git a/ci-scripts/reportTestLocally.sh b/ci-scripts/reportTestLocally.sh index b74fe93a1f..897f9285e9 100755 --- a/ci-scripts/reportTestLocally.sh +++ b/ci-scripts/reportTestLocally.sh @@ -724,8 +724,8 @@ function report_test { echo " " >> ./test_simulator_results.html echo " " >> ./test_simulator_results.html fi - #PING_LOGS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping*.log 2> /dev/null` - #analyzePingFiles + PING_LOGS=`ls $ARCHIVES_LOC/${TMODE}_${BW}prb_${CN_CONFIG}_ping*.log 2> /dev/null` + analyzePingFiles IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}prb_${CN_CONFIG}_iperf_dl*client*txt 2> /dev/null` analyzeIperfFiles diff --git a/ci-scripts/rrc-files/rbconfig.raw b/ci-scripts/rrc-files/rbconfig.raw deleted file mode 100644 index b03f18d1219201d789d1c70e1dced3e84a932990..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8 PcmWgP)DUkvz{3Cl2C4z8 diff --git a/ci-scripts/rrc-files/reconfig.raw b/ci-scripts/rrc-files/reconfig.raw deleted file mode 100644 index 97b41d9b6b0f0662487ca39848f85e9c1f7f8594..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 479 zcmZvXK}Zx)0EYiJZ+7;%j_XKUh%ENXDK?21#KRUHp2H>+lyvMMF*~+WLFgem)aA{% zl66`(S%faD6@&yyL3n&?+qPmv2;D@MEa;eCx>&Z|yM5p7`&hU&j$JjxrW$?heDiE# zrp~RxosN$_z1U>h&8!6U&Bpv>RXxWN$Vq{N}IvEipfZ!CNn4gOq0Wp{R}^Kfa2pe-7*}_6@%Q6AZjd^V@W_3Ne!j2yN1Yorg8CJ&MSq*vtF|z9Rf}kw9 zOx9^wP&>JogICi$s@0-2 zPoAI>dgr#}5FkI0;q=V(#{Xt(%cWbI-oqTJ2GB)JI7a5$XTEsf?jL>hsog_Mw{JWI@5GhC+Q#8h* qJUD$YnWS13stM;DOiNO|EftB=CGW!CtAm++osPf`dKT!uA^!qOo0Vh$ diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index 64af11c8ba..0db2264c76 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -89,6 +89,9 @@ function start_basic_sim_enb { fi done ENB_SYNC=0 + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -151,6 +154,9 @@ function start_basic_sim_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$2 < $1 rm $1 if [ $i -lt 50 ] then @@ -523,9 +529,9 @@ function install_epc_on_vm { echo "############################################################" echo "[ -f 01proxy ] && sudo cp 01proxy /etc/apt/apt.conf.d/" > $LOC_EPC_VM_CMDS echo "touch /home/ubuntu/.hushlogin" >> $LOC_EPC_VM_CMDS - echo "echo \"sudo apt-get --yes --quiet install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev daemon iperf\"" >> $LOC_EPC_VM_CMDS + echo "echo \"sudo apt-get --yes --quiet install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev iperf\"" >> $LOC_EPC_VM_CMDS echo "sudo apt-get update > zip-install.txt 2>&1" >> $LOC_EPC_VM_CMDS - echo "sudo apt-get --yes install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev daemon iperf >> zip-install.txt 2>&1" >> $LOC_EPC_VM_CMDS + echo "sudo apt-get --yes install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev iperf >> zip-install.txt 2>&1" >> $LOC_EPC_VM_CMDS # Installing HSS echo "echo \"cd /opt\"" >> $LOC_EPC_VM_CMDS @@ -588,8 +594,6 @@ function start_epc { echo "echo \"cd /opt/hss_sim0609\"" > $LOC_EPC_VM_CMDS echo "cd /opt/hss_sim0609" >> $LOC_EPC_VM_CMDS echo "sudo rm -f hss.log" >> $LOC_EPC_VM_CMDS - #echo "echo \"sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real\"" >> $LOC_EPC_VM_CMDS - #echo "sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real" >> $LOC_EPC_VM_CMDS echo "echo \"screen -dm -S simulated_hss ./starthss_real\"" >> $LOC_EPC_VM_CMDS echo "sudo su -c \"screen -dm -S simulated_hss ./starthss_real\"" >> $LOC_EPC_VM_CMDS @@ -656,8 +660,6 @@ function terminate_epc { echo "cd /opt/ltebox/tools" >> $1 echo "echo \"sudo ./stop_ltebox\"" >> $1 echo "sudo ./stop_ltebox" >> $1 - echo "echo \"sudo daemon --name=simulated_hss --stop\"" >> $1 - echo "sudo daemon --name=simulated_hss --stop" >> $1 echo "echo \"sudo killall --signal SIGKILL hss_sim\"" >> $1 echo "sudo killall --signal SIGKILL hss_sim" >> $1 ssh -T -o StrictHostKeyChecking=no ubuntu@$2 < $1 @@ -764,6 +766,9 @@ function start_l2_sim_enb { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_ENB_VM_IP_ADDR < $1 rm $1 ENB_SYNC=1 if [ $i -lt 50 ] @@ -872,6 +877,9 @@ function start_l2_sim_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_UE_VM_IP_ADDR < $1 rm $1 UE_SYNC=1 if [ $i -lt 50 ] @@ -985,6 +993,9 @@ function start_rf_sim_enb { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_ENB_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -1114,6 +1125,9 @@ function start_rf_sim_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_UE_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -1158,6 +1172,10 @@ function start_rf_sim_gnb { local LOC_CONF_FILE=$5 # 1 is with S1 and 0 without S1 aka noS1 local LOC_S1_CONFIGURATION=$6 + + if [ -e rbconfig.raw ]; then rm -f rbconfig.raw; fi + if [ -e reconfig.raw ]; then rm -f reconfig.raw; fi + echo "cd /home/ubuntu/tmp" > $1 echo "echo \"sudo apt-get --yes --quiet install daemon \"" >> $1 echo "sudo apt-get --yes install daemon >> /home/ubuntu/tmp/cmake_targets/log/daemon-install.txt 2>&1" >> $1 @@ -1171,6 +1189,7 @@ function start_rf_sim_gnb { echo "echo \"cd /home/ubuntu/tmp/cmake_targets/ran_build/build/\"" >> $1 echo "sudo chmod 777 /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 + echo "sudo rm -f r*config.raw" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then echo "echo \"RFSIMULATOR=server ./nr-softmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --log_config.global_log_options level,nocolor --parallel-config PARALLEL_SINGLE_THREAD --noS1 --nokrnmod 1 --rfsim --phy-test\" > ./my-nr-softmodem-run.sh " >> $1 @@ -1231,6 +1250,13 @@ function start_rf_sim_gnb { fi fi sleep 10 + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR < $1 + rm $1 + # Copy the RAW files from the gNB run for the NR-UE + scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/rbconfig.raw . + scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/reconfig.raw . } function start_rf_sim_nr_ue { @@ -1241,14 +1267,21 @@ function start_rf_sim_nr_ue { local LOC_FREQUENCY=$6 # 1 is with S1 and 0 without S1 aka noS1 local LOC_S1_CONFIGURATION=$7 + + # Copy the RAW files from the gNB run + scp -o StrictHostKeyChecking=no rbconfig.raw ubuntu@$LOC_NR_UE_VM_IP_ADDR:/home/ubuntu/tmp + scp -o StrictHostKeyChecking=no reconfig.raw ubuntu@$LOC_NR_UE_VM_IP_ADDR:/home/ubuntu/tmp + echo "echo \"sudo apt-get --yes --quiet install daemon \"" > $1 echo "sudo apt-get --yes install daemon >> /home/ubuntu/tmp/cmake_targets/log/daemon-install.txt 2>&1" >> $1 echo "echo \"cd /home/ubuntu/tmp/cmake_targets/ran_build/build/\"" >> $1 echo "sudo chmod 777 /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 + echo "sudo cp /home/ubuntu/tmp/r*config.raw /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 + echo "sudo chmod 666 /home/ubuntu/tmp/cmake_targets/ran_build/build/r*config.raw" >> $1 echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then - echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/ci-scripts/rrc-files --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 + echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/cmake_targets/ran_build/build/ --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 fi echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1 echo "cat ./my-nr-softmodem-run.sh" >> $1 @@ -1295,6 +1328,9 @@ function start_rf_sim_nr_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_NR_UE_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -2028,7 +2064,7 @@ function run_test_on_vm { NR_STATUS=0 ######### start of loop - while [ $try_cnt -lt 5 ] + while [ $try_cnt -lt 1 ] do SYNC_STATUS=0 PING_STATUS=0 @@ -2050,6 +2086,8 @@ function run_test_on_vm { echo "Problem w/ gNB and NR-UE not syncing" terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC SYNC_STATUS=-1 try_cnt=$[$try_cnt+1] continue @@ -2089,6 +2127,8 @@ function run_test_on_vm { echo "DL test not OK" terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC try_cnt=$[$try_cnt+1] continue fi diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml index 4dbfe00821..aac71198f1 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml @@ -25,23 +25,10 @@ EPC-Start log-in - 010101 090101 050101 060101 070101 - - Build_eNB - Build eNB (USRP) - -w USRP -c --eNB - - - - Build_OAI_UE - Build OAI UE - -w USRP --UE - - Initialize_HSS Initialize HSS diff --git a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml index 41e746bc85..73d1216199 100644 --- a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml +++ b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml @@ -24,6 +24,7 @@ test-05-tm1-rrc-no-flex Test-05MHz-TM1-RRC-Inactivity tasks + 2 030201 040101 diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml index f3e80c576a..c51093c178 100644 --- a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml +++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml @@ -52,7 +52,7 @@ Initialize_OAI_UE Initialize NR UE USRP - --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path ci-scripts/rrc-files + --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path . NR diff --git a/ci-scripts/xml_files/gnb_usrp_build.xml b/ci-scripts/xml_files/gnb_usrp_build.xml index bba92930c5..97d6ef06f6 100644 --- a/ci-scripts/xml_files/gnb_usrp_build.xml +++ b/ci-scripts/xml_files/gnb_usrp_build.xml @@ -24,6 +24,7 @@ gnb-build-tab Build-gNB wrench + 4 010101 diff --git a/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml b/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml index e1644f3931..8276294e9a 100644 --- a/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml +++ b/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml @@ -24,6 +24,7 @@ test-10 Test-10MHz tasks + 2 030201 040101 diff --git a/ci-scripts/xml_files/multi_rru_band38_build.xml b/ci-scripts/xml_files/multi_rru_band38_build.xml index 614ef394f3..ba45eab10a 100644 --- a/ci-scripts/xml_files/multi_rru_band38_build.xml +++ b/ci-scripts/xml_files/multi_rru_band38_build.xml @@ -33,7 +33,7 @@ Build_eNB Build RCC - -w USRP -c --eNB + -w USRP -c --eNB --ninja 0 0 True @@ -42,7 +42,7 @@ WaitEndBuild_eNB Wait for end of Build RCC - -w USRP -c --eNB + -w USRP -c --eNB --ninja 0 0 @@ -50,7 +50,7 @@ Build_eNB Build Master RRU - -w USRP -c --eNB + -w USRP -c --eNB --ninja 1 1 True @@ -59,7 +59,7 @@ WaitEndBuild_eNB Wait for end of Build Master RRU - -w USRP -c --eNB + -w USRP -c --eNB --ninja 1 1 @@ -67,7 +67,7 @@ Build_eNB Build Slave RRU - -w USRP -c --eNB + -w USRP -c --eNB --ninja 2 2 True @@ -76,7 +76,7 @@ WaitEndBuild_eNB Wait for end of Build Slave RRU - -w USRP -c --eNB + -w USRP -c --eNB --ninja 2 2 diff --git a/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml b/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml index 7658f8a0e5..cca14c0696 100644 --- a/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml +++ b/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml @@ -24,7 +24,7 @@ test-multi-rru-10 Test-Multi-RRU-10MHz tasks - 4 + 2 030211 030212 030213 030111 030112 030113 diff --git a/ci-scripts/xml_files/nr_ue_usrp_build.xml b/ci-scripts/xml_files/nr_ue_usrp_build.xml index 7d8d97d2c5..c3c842b85a 100644 --- a/ci-scripts/xml_files/nr_ue_usrp_build.xml +++ b/ci-scripts/xml_files/nr_ue_usrp_build.xml @@ -24,6 +24,7 @@ nr-ue-build-tab Build-NR-UE wrench + 2 010102 diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index dcd063ff5c..0b60172747 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -20,34 +20,9 @@ # */ # Author: laurent THOMAS, Lionel GAUTHIER -###################### FOR CUDA############################# -# author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN: -# Add for PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu -# email tyhsu@cs.nctu.edu.tw -###################### FOR CUDA############################# + cmake_minimum_required (VERSION 3.0) - - -############################################## -# Base CUDA setting -############################################## -find_package(CUDA) -message ("cuda include ${CUDA_INCLUDE_DIRS}") -message ("cuda library ${CUDA_LIBRARY_DIRS}") - -add_definitions("-L/usr/local/cuda/lib64") - -SET(CUDA_NVCC_FLAGS - "${CUDA_NVCC_FLAGS};-arch=sm_75;") - -# Disable warnings for CUDA -SET(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS};-lpthread;-w;-O3;--default-stream;per-thread;-I/usr/local/cuda/inc;-L/usr/local/cuda/lib -lcutil;-rdc=true;-lcudadevrt") -SET(CUDA_VERBOSE_BUILD ON) -SET(CUDA_HOST_COMPILER "/usr/bin/g++") - -SET(CUDA_SEPARABLE_COMPILATION ON) - ######################################################### # Base directories, compatible with legacy OAI building # ######################################################### @@ -64,6 +39,33 @@ set (OPENAIR_BIN_DIR ${CMAKE_CURRENT_BINARY_DIR}${CMAKE_FILES_DIRECTORY}) project (OpenAirInterface) + + +############################################## +# Base CUDA setting +############################################## +find_package(CUDA) +if (CUDA_FOUND) + message ("cuda include ${CUDA_INCLUDE_DIRS}") + message ("cuda library ${CUDA_LIBRARY_DIRS}") + + add_definitions("-L/usr/local/cuda/lib64") + + SET(CUDA_NVCC_FLAGS + "${CUDA_NVCC_FLAGS};-arch=sm_60;") + + # Disable warnings for CUDA + SET(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS};-lpthread;-w;-O3;--default-stream;per-thread;-I/usr/local/cuda/inc;-L/usr/local/cuda/lib -lcutil;-rdc=true;-lcudadevrt") + SET(CUDA_VERBOSE_BUILD ON) + SET(CUDA_HOST_COMPILER "/usr/bin/g++") + + SET(CUDA_SEPARABLE_COMPILATION ON) + +else (CUDA_FOUND) + message ("No CUDA tool installed") +endif () + + ########################################### # macros to define options as there is numerous options in oai ################################################ @@ -194,13 +196,30 @@ endif() set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${C_FLAGS_PROCESSOR} -pipe -std=gnu99 -Wall -Wstrict-prototypes -fno-strict-aliasing -rdynamic -funroll-loops -Wno-packed-bitfield-compat -fPIC") # add autotools definitions that were maybe used! -# set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'") -set(CMAKE_C_FLAGS - "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP " -) -set(CMAKE_CXX_FLAGS - "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 " -) +if (CUDA_FOUND) + set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'") + set(CUDA_CMAKE_C_FLAGS + "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D CUDA_FLAG" + ) + set(CUDA_CMAKE_CXX_FLAGS + "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D CUDA_FLAG" + ) + + set(CMAKE_C_FLAGS + "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER} -D CUDA_FLAG" + ) + set(CMAKE_CXX_FLAGS + "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D${MKVER} -D CUDA_FLAG" + ) +else (CUDA_FOUND) + set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'") + set(CMAKE_C_FLAGS + "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER}" + ) + set(CMAKE_CXX_FLAGS + "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D${MKVER}" + ) +endif () add_definitions("-DASN_DISABLE_OER_SUPPORT") @@ -1655,7 +1674,7 @@ add_library(PHY_MEX ${PHY_MEX_UE} ${CONFIG_LIB}) #Layer 2 library ##################### set(MAC_DIR ${OPENAIR2_DIR}/LAYER2/MAC) -set(NR_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB) +set(NR_GNB_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB) set(NR_UE_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_UE) set(PHY_INTERFACE_DIR ${OPENAIR2_DIR}/PHY_INTERFACE) set(NR_PHY_INTERFACE_DIR ${OPENAIR2_DIR}/NR_PHY_INTERFACE) @@ -1811,20 +1830,22 @@ set (MAC_SRC ${MAC_DIR}/eNB_scheduler_fairRR.c ${MAC_DIR}/eNB_scheduler_phytest.c ${MAC_DIR}/pre_processor.c + ${MAC_DIR}/slicing/slicing.c ${MAC_DIR}/config.c ${MAC_DIR}/config_ue.c ) set (MAC_NR_SRC ${NR_PHY_INTERFACE_DIR}/NR_IF_Module.c - ${NR_MAC_DIR}/main.c - ${NR_MAC_DIR}/config.c - ${NR_MAC_DIR}/gNB_scheduler.c - ${NR_MAC_DIR}/gNB_scheduler_bch.c - ${NR_MAC_DIR}/gNB_scheduler_dlsch.c - ${NR_MAC_DIR}/gNB_scheduler_ulsch.c - ${NR_MAC_DIR}/gNB_scheduler_primitives.c - ${NR_MAC_DIR}/gNB_scheduler_phytest.c + ${NR_GNB_MAC_DIR}/main.c + ${NR_GNB_MAC_DIR}/config.c + ${NR_GNB_MAC_DIR}/gNB_scheduler.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_bch.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_dlsch.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_ulsch.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_primitives.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_phytest.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_RA.c ) @@ -1836,7 +1857,6 @@ set (MAC_SRC_UE ${MAC_DIR}/l1_helpers.c ${MAC_DIR}/rar_tools_ue.c ${MAC_DIR}/config_ue.c - ) set (MAC_NR_SRC_UE @@ -1846,6 +1866,9 @@ set (MAC_NR_SRC_UE ${NR_UE_MAC_DIR}/main_ue_nr.c ${NR_UE_MAC_DIR}/nr_ue_procedures.c ${NR_UE_MAC_DIR}/nr_ue_dci_configuration.c + ${NR_UE_MAC_DIR}/nr_l1_helpers.c + ${NR_UE_MAC_DIR}/nr_ra_procedures.c + ${NR_UE_MAC_DIR}/rar_tools_nrUE.c ) set (ENB_APP_SRC @@ -1909,7 +1932,7 @@ add_library( NR_L2_UE ${NR_L2_SRC_UE} ${MAC_NR_SRC_UE} ) add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_COMMON/nr_mac_common.c ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c) include_directories("${OPENAIR2_DIR}/NR_UE_PHY_INTERFACE") -include_directories("${OPENAIR2_DIR}/LAYER2/NR_MAC_UE") +include_directories("${OPENAIR2_DIR}/LAYER2") include_directories("${OPENAIR1_DIR}/SCHED_NR_UE") #include_directories("${NFAPI_USER_DIR}"") @@ -1937,6 +1960,19 @@ set (GTPV1U_SRC add_library(GTPV1U ${GTPV1U_SRC}) add_dependencies(GTPV1U rrc_flag) +#NR case +set (NR_GTPV1U_SRC + ${NR_RRC_DIR}/rrc_gNB_GTPV1U.c + ${RRC_DIR}/rrc_eNB_GTPV1U.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uTunnelEndPoint.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uTrxn.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uMsg.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1u.c + ${GTPV1U_DIR}/gtpv1u_teid_pool.c +) +add_library(NR_GTPV1U ${NR_GTPV1U_SRC}) +add_dependencies(NR_GTPV1U rrc_flag) + set (MME_APP_SRC ${OPENAIR3_DIR}/MME_APP/mme_app.c ${OPENAIR3_DIR}/MME_APP/mme_config.c @@ -2264,26 +2300,28 @@ add_library(LFDS7 ${lfds7_queue} ${lfds7_ring} ${lfds7_qbss} ${lfds7_stack} ${lfds7_freelist} ${lfds7_btree} ${lfds7_hash} ${lfds7_ordered_list} ${lfds7_unordered_list} ${lfds7_misc} ) -# Simulation library -########################## -set (SIMUSRC -${OPENAIR1_DIR}/SIMULATION/TOOLS/random_channel.c -${OPENAIR1_DIR}/SIMULATION/TOOLS/rangen_double.c -${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c -${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_channel.c -${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_tv_channel.c -${OPENAIR1_DIR}/SIMULATION/TOOLS/abstraction.c -${OPENAIR1_DIR}/SIMULATION/TOOLS/channel_sim.c -${OPENAIR1_DIR}/SIMULATION/RF/rf.c -${OPENAIR1_DIR}/SIMULATION/RF/dac.c -${OPENAIR1_DIR}/SIMULATION/RF/adc.c -${OPENAIR_DIR}/targets/ARCH/rfsimulator/apply_channelmod.c -#${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c -) +add_library(SIMU_COMMON + ${OPENAIR1_DIR}/SIMULATION/TOOLS/random_channel.c + ${OPENAIR1_DIR}/SIMULATION/TOOLS/rangen_double.c + ) # Simulation library ########################## -add_library( SIMU SHARED ${SIMUSRC} ) +set (SIMUSRC + ${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c + ${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_channel.c + ${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_tv_channel.c + ${OPENAIR1_DIR}/SIMULATION/TOOLS/abstraction.c + ${OPENAIR1_DIR}/SIMULATION/TOOLS/channel_sim.c + ${OPENAIR1_DIR}/SIMULATION/RF/rf.c + ${OPENAIR1_DIR}/SIMULATION/RF/dac.c + ${OPENAIR1_DIR}/SIMULATION/RF/adc.c + #${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c + ) + +# Simulation library +########################## +add_library(SIMU SHARED ${SIMUSRC} ) add_library(SIMU_ETH ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c @@ -2441,9 +2479,11 @@ target_link_libraries(gnbscope ${XFORMS_LIBRARIES}) add_library(rfsimulator MODULE - ${OPENAIR_TARGETS}/ARCH/rfsimulator/simulator.c + ${OPENAIR_TARGETS}/ARCH/rfsimulator/simulator.c + ${OPENAIR_TARGETS}/ARCH/rfsimulator/apply_channelmod.c + ${OPENAIR_TARGETS}/ARCH/rfsimulator/new_channel_sim.c ) -target_link_libraries(rfsimulator SIMU ${ATLAS_LIBRARIES}) +target_link_libraries(rfsimulator SIMU_COMMON ${ATLAS_LIBRARIES}) add_library(oai_iqplayer MODULE ${OPENAIR_TARGETS}/ARCH/iqplayer/iqplayer_lib.c @@ -2466,7 +2506,7 @@ endif (${T_TRACER}) add_custom_command ( OUTPUT ${OPENAIR_DIR}/common/utils/T/T_IDs.h COMMAND make clean - COMMAND make + COMMAND make -j2 COMMAND make check_vcd WORKING_DIRECTORY ${OPENAIR_DIR}/common/utils/T DEPENDS ${OPENAIR_DIR}/common/utils/T/T_messages.txt @@ -2589,7 +2629,7 @@ add_dependencies(ocp-enb rrc_flag s1ap_flag x2_flag oai_iqplayer) target_link_libraries (ocp-enb -Wl,--start-group RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB SCHED_RU_LIB - PHY_COMMON PHY PHY_RU LFDS L2 L2_LTE NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB LFDS7 + PHY_COMMON PHY PHY_RU LFDS L2 L2_LTE NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB LFDS7 SIMU_COMMON ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} ${FSPT_MSG_LIB} ${PROTO_AGENT_LIB} -Wl,--end-group z dl) target_link_libraries (ocp-enb ${LIBXML2_LIBRARIES} pthread m ${CONFIG_LIBRARIES} rt crypt ${CRYPTO_LIBRARIES} ${OPENSSL_LIBRARIES} ${NETTLE_LIBRARIES} sctp ${PROTOBUF_LIB} ${CMAKE_DL_LIBS} ${LIBYAML_LIBRARIES} ${LIB_LMS_LIBRARIES} ${T_LIB}) @@ -2659,7 +2699,7 @@ target_link_libraries (lte-uesoftmodem -Wl,--start-group RRC_LIB S1AP_LIB S1AP_ENB X2AP_LIB X2AP_ENB M2AP_LIB M2AP_ENB M3AP_LIB M3AP_ENB F1AP F1AP_LIB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON - PHY_UE PHY_RU LFDS L2_UE L2_LTE LFDS7 SIMU NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB + PHY_UE PHY_RU LFDS L2_UE L2_LTE LFDS7 SIMU_COMMON SIMU NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${ATLAS_LIBRARIES} -Wl,--end-group z dl) @@ -2685,6 +2725,7 @@ add_executable(nr-softmodem ${OPENAIR_TARGETS}/ARCH/COMMON/record_player.c ${OPENAIR2_DIR}/RRC/NAS/nas_config.c ${OPENAIR2_DIR}/RRC/NAS/rb_config.c + ${OPENAIR3_DIR}/GTPV1-U/gtpv1u_gNB.c ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c ${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/system.c @@ -2698,7 +2739,7 @@ add_executable(nr-softmodem target_link_libraries (nr-softmodem -Wl,--start-group - UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS GTPV1U SECU_CN SECU_OSA + UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS NR_GTPV1U SECU_CN SECU_OSA ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} LFDS7 ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB L2 L2_NR MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB X2AP_LIB X2AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB M3AP_LIB M3AP_ENB ${PROTO_AGENT_LIB} ${FSPT_MSG_LIB} @@ -2742,9 +2783,9 @@ add_executable(nr-uesoftmodem target_link_libraries (nr-uesoftmodem -Wl,--start-group RRC_LIB NR_RRC_LIB SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT UDP SCHED_RU_LIB SCHED_UE_LIB SCHED_NR_UE_LIB + PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS NR_L2_UE L2_UE MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB + NFAPI_USER_LIB S1AP_LIB S1AP_ENB ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} LFDS7 ${ATLAS_LIBRARIES} - PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS L2_UE NR_L2_UE MAC_NR_COMMON S1AP_LIB S1AP_ENB - NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB -Wl,--end-group z dl) target_link_libraries (nr-uesoftmodem ${LIBXML2_LIBRARIES}) @@ -2754,29 +2795,6 @@ target_link_libraries (nr-uesoftmodem ${T_LIB}) add_dependencies( nr-uesoftmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc ) -# USIM process -################# -#add_executable(usim -# ${OPENAIR3_DIR}/NAS/TOOLS/usim_data.c -# ${OPENAIR3_DIR}/NAS/USER/API/USIM/usim_api.c -# ${OPENAIR3_DIR}/NAS/USER/API/USIM/aka_functions.c -# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/memory.c -# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/nas_log.c -# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/OctetString.c -# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/TLVEncoder.c -# ) -#target_link_libraries (usim ${NAS_LIB} UTIL ${ITTI_LIB} LFDS pthread rt nettle crypto m) - -# ??? -##################### -#add_executable(nvram -# ${OPENAIR3_DIR}/NAS/TOOLS/ue_data.c -# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/memory.c -# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/nas_log.c -# ) -#target_link_libraries (nvram LIB_NAS_UE UTIL ${ITTI_LIB} LFDS pthread rt nettle crypto m) - - ###################################" # Addexecutables for tests #################################### @@ -2793,7 +2811,7 @@ add_executable(dlsim_tm4 ${T_SOURCE} ) target_link_libraries (dlsim_tm4 - -Wl,--start-group SIMU UTIL SCHED_LIB SCHED_RU_LIB PHY LFDS ${ITTI_LIB} -Wl,--end-group + -Wl,--start-group SIMU_COMMON SIMU UTIL SCHED_LIB SCHED_RU_LIB PHY LFDS ${ITTI_LIB} -Wl,--end-group pthread m rt ${CONFIG_LIB} ${ATLAS_LIBRARIES} ${T_LIB} ) @@ -2806,7 +2824,7 @@ add_executable(polartest ${SHLIB_LOADER_SOURCES} ) target_link_libraries(polartest - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE CONFIG_LIB -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} dl ) @@ -2821,35 +2839,51 @@ add_executable(smallblocktest target_link_libraries(smallblocktest - -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} dl ) -<<<<<<< HEAD + +# temp_C_flag = CMAKE_C_FLAGS +#set(CMAKE_C_FLAGS " ") +set (TEMP_C_FLAG ${CMAKE_C_FLAGS}) +set (CMAKE_C_FLAGS ${CUDA_CMAKE_C_FLAGS}) + +set (TEMP_CXX_FLAG ${CMAKE_CXX_FLAGS}) +set (CMAKE_CXX_FLAGS ${CUDA_CMAKE_CXX_FLAGS}) +if (CUDA_FOUND) ################################################### # For CUDA library ################################################### -CUDA_ADD_LIBRARY(LDPC_CU - ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu - ) -CUDA_ADD_CUFFT_TO_TARGET(LDPC_CU) -cuda_add_executable(ldpctest -======= -add_executable(ldpctest - ${PHY_NR_CODINGIF} ->>>>>>> origin/develop - ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c - ${T_SOURCE} - ${SHLIB_LOADER_SOURCES} - ) -<<<<<<< HEAD + + CUDA_ADD_LIBRARY(LDPC_CU + ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu + ) + CUDA_ADD_CUFFT_TO_TARGET(LDPC_CU) + cuda_add_executable(ldpctest + ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c + ${T_SOURCE} + ${SHLIB_LOADER_SOURCES} + ) + target_link_libraries(ldpctest -ldl + -Wl,--start-group + LDPC_CU UTIL SIMU PHY_NR CONFIG_LIB + -Wl,--end-group + m pthread ${ATLAS_LIBRARIES} dl + ) + +else (CUDA_FOUND) + add_executable(ldpctest + ${PHY_NR_CODINGIF} + ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c + ${T_SOURCE} + ${SHLIB_LOADER_SOURCES} + ) + +endif () +set (CMAKE_C_FLAGS ${TEMP_C_FLAG}) +set (CMAKE_CXX_FLAGS ${TEMP_CXX_FLAG}) -target_link_libraries(ldpctest -ldl - -Wl,--start-group - LDPC_CU UTIL SIMU PHY_NR CONFIG_LIB - -Wl,--end-group - m pthread ${ATLAS_LIBRARIES} dl - ) # add_executable(ldpctest # ${PHY_NR_CODINGIF} @@ -2857,36 +2891,36 @@ target_link_libraries(ldpctest -ldl # ${T_SOURCE} # ${SHLIB_LOADER_SOURCES} # ) -======= ->>>>>>> origin/develop add_dependencies( ldpctest ldpc_orig ldpc_optim ldpc_optim8seg ldpc ) target_link_libraries(ldpctest - -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} dl ) add_executable(nr_dlschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_dlschsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) add_executable(nr_pbchsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/pbchsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_pbchsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) @@ -2901,7 +2935,7 @@ add_executable(nr_pucchsim ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_pucchsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) @@ -2915,7 +2949,7 @@ add_executable(nr_dlsim ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_dlsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) target_compile_definitions(nr_dlsim PUBLIC -DPHYSICAL_SIMULATOR) @@ -2929,17 +2963,18 @@ add_executable(nr_prachsim ${T_SOURCE} ${SHLIB_LOADER_SOURCES}) target_link_libraries(nr_prachsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl) + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB MAC_UE_NR SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl) add_executable(nr_ulschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/ulschsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_ulschsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) @@ -2953,7 +2988,7 @@ add_executable(nr_ulsim ${SHLIB_LOADER_SOURCES} ) target_link_libraries(nr_ulsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group + -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl ) target_compile_definitions(nr_ulsim PUBLIC -DPHYSICAL_SIMULATOR) @@ -2972,7 +3007,7 @@ foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim pr ${NFAPI_USER_DIR}/nfapi.c ) target_link_libraries (${myExe} - -Wl,--start-group SIMU UTIL SCHED_LIB SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON PHY_NR_COMMON PHY PHY_UE PHY_RU LFDS ${ITTI_LIB} LFDS7 -Wl,--end-group + -Wl,--start-group SIMU_COMMON SIMU UTIL SCHED_LIB SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON PHY_NR_COMMON PHY PHY_UE PHY_RU LFDS ${ITTI_LIB} LFDS7 -Wl,--end-group pthread m rt ${CONFIG_LIB} ${ATLAS_LIBRARIES} ${XFORMS_LIBRARIES} ${T_LIB} dl ) @@ -3052,8 +3087,8 @@ if (${T_TRACER}) NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_VNF_LIB NFAPI_USER_LIB PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_COMMON PHY_NR_UE PHY_RU PHY_MEX L2 L2_LTE L2_NR L2_UE NR_L2_UE MAC_NR_COMMON MAC_NR MAC_UE_NR - CN_UTILS GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU SIMU_ETH OPENAIR0_LIB - ldpc_orig ldpc_optim ldpc_optim8seg ldpc PROTO_AGENT) + CN_UTILS GTPV1U NR_GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU_COMMON SIMU SIMU_ETH OPENAIR0_LIB + ldpc_orig ldpc_optim ldpc_optim8seg ldpc PROTO_AGENT dfts) if (TARGET ${i}) add_dependencies(${i} generate_T) endif() @@ -3096,7 +3131,7 @@ function(make_driver name dir) endforeach() CONFIGURE_FILE(${OPENAIR_CMAKE}/tools/Kbuild.cmake ${OPENAIR_BIN_DIR}/${name}/Kbuild) add_custom_command(OUTPUT ${name}.ko - COMMAND make -C ${module_build_path} M=${OPENAIR_BIN_DIR}/${name} + COMMAND make -j2 -C ${module_build_path} M=${OPENAIR_BIN_DIR}/${name} WORKING_DIRECTORY ${OPENAIR_BIN_DIR}/${name} COMMENT "building ${module}.ko" VERBATIM diff --git a/cmake_targets/autotests/README.txt b/cmake_targets/autotests/README.txt index 10c14fd59a..19a333c626 100644 --- a/cmake_targets/autotests/README.txt +++ b/cmake_targets/autotests/README.txt @@ -142,10 +142,14 @@ Obj.# Case# Test# Description (Test 11: 10 MHz, R7.FDD (MCS 25), EVA5, 17.7dB (70%)) (TM2 Test 1 10 MHz, R.11 FDD (MCS 14), EVA5, 6.8 dB (70%)), (TM2 Test 1b 20 MHz, R.11-2 FDD (MCS 13), EVA5, 5.9 dB (70%)), -01 51 11 nr_ulsim Test cases. (Test1: MCS 9), - (Test2: MCS 16), - (Test3: MCS 28) - +01 51 11 nr_ulsim Test cases. (Test1: MCS 9 106 PRBs), + (Test2: MCS 16 50 PRBs), + (Test3: MCS 28 50 PRBs), + (Test4: MCS 9 217 PRBs), + (Test5: MCS 9 273 PRBs) +01 51 12 nr_prachsim Test cases.(Test1: 106 PRBs), + (Test2: 217 PRBs), + (Test3: 273 PRBs) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 882670727b..786002e982 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1036,7 +1036,9 @@ execution polartest Test cases. (Test1: PBCH polar test), - (Test2: DCI polar test) + (Test2: DCI polar test), + (Test3: UCI polar test,6-bit CRC), + (Test4: UCI polar test,11-bit CRC) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c @@ -1044,8 +1046,10 @@ $OPENAIR_DIR/targets/bin/polartest.Rel15 -q -s-10 -f0 - -q -s-10 -f0 -m1 - polartest.test1 polartest.test2 + -q -s-10 -f0 -m1 + -q -s-2 -f2 -m2 -k12 + -q -s-2 -f2 -m2 -k20 + polartest.test1 polartest.test2 polartest.test3 polartest.test4 BLER= 0.000000 segmentation fault|assertion|exiting|fatal 3 @@ -1067,9 +1071,9 @@ $OPENAIR_DIR/targets/bin/nr_pbchsim.Rel15 -s0 -S1 -n1000 -R106 -s0 -S1 -n10 -I -R106 - -s0 -S1 -n1000 -R217 + -s0 -S1 -n1000 -R217 -s0 -S1 -n10 -I -R217 - -s0 -S1 -n1000 -R273 + -s0 -S1 -n1000 -R273 -s0 -S1 -n10 -I -R273 nr_pbchsim.test1 nr_pbchsim.test2 nr_pbchsim.test3 nr_pbchsim.test4 nr_pbchsim.test5 nr_pbchsim.test6 PBCH test OK @@ -1087,8 +1091,11 @@ (Test6: 217 PRB 100 PDSCH-PRBs), (Test7: 217 PRB 80 PDSCH-Offset), (Test8: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset), - (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27) - (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16) + (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27), + (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16), + (Test11: HARQ test 25% TP (4 rounds), + (Test12: HARQ test 33% TP (3 rounds), + (Test13: HARQ test 50% TP (2 rounds) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c @@ -1104,8 +1111,11 @@ -n100 -R217 -a80 -s5 -n100 -R217 -a110 -s5 -b100 -n100 -e27 -s30 - -n100 -e16 -s10 - nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 + -n100 -e16 -s10 + -n100 -s1 -t25 + -n100 -s1 -t33 + -n100 -s1 -t50 + nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 PDSCH test OK segmentation fault|assertion|exiting|fatal 3 @@ -1179,15 +1189,20 @@ nr_pucchsim Test cases. (Test1: Format 0 1-bit ACK miss 106 PRB), (Test2: Format 0 2-bit ACK miss 106 PRB), (Test3: Format 0 2-bit ACK miss, 1-bit SR 106 PRB), - (Test4: Format 2 3-bit 106 PRB), - (Test5: Format 2 4-bit 106 PRB), - (Test6: Format 2 5-bit 106 PRB), - (Test7: Format 2 6-bit 106 PRB), - (Test8: Format 2 7-bit 106 PRB), - (Test9: Format 2 8-bit 106 PRB), - (Test10: Format 2 9-bit 106 PRB), - (Test11: Format 2 10-bit 106 PRB), - (Test12: Format 2 11-bit 106 PRB) + (Test4: Format 2 3-bit 2/106 PRB), + (Test5: Format 2 4-bit 2/106 PRB), + (Test6: Format 2 5-bit 2/106 PRB), + (Test7: Format 2 6-bit 2/106 PRB), + (Test8: Format 2 7-bit 2/106 PRB), + (Test9: Format 2 8-bit 2/106 PRB), + (Test10: Format 2 9-bit 2/106 PRB), + (Test11: Format 2 10-bit 2/106 PRB), + (Test12: Format 2 11-bit 2/106 PRB), + (Test13: Format 2 12-bit 8/106 PRB), + (Test14: Format 2 19-bit 8/106 PRB), + (Test15: Format 2 32-bit 8/106 PRB), + (Test16: Format 2 32-bit 16/106 PRB), + (Test17: Format 2 64-bit 16/106 PRB) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c @@ -1206,8 +1221,12 @@ -R 106 -i 1 -P 2 -b 9 -s5 -n1000 -R 106 -i 1 -P 2 -b 10 -s6 -n1000 -R 106 -i 1 -P 2 -b 11 -s6 -n1000 - - nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 + -R 106 -i 1 -P 2 -q8 -b 12 -s-3 -n1000 + -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000 + -R 106 -i 1 -P 2 -q8 -b 32 -s-3 -n1000 + -R 106 -i 1 -P 2 -q16 -b 32 -s-3 -n1000 + -R 106 -i 1 -P 2 -q16 -b 64 -s-3 -n1000 + nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 nr_pucchsim.test13 nr_pucchsim.test14 nr_pucchsim.test15 nr_pucchsim.test16 nr_pucchsim.test17 PUCCH test OK segmentation fault|assertion|exiting|fatal 3 @@ -1275,6 +1294,28 @@ 3 + + execution + nr_prachsim Test cases. (Test1: 106 PRBs - Prach format A2), + (Test2: 217 PRBs - Prach format A2), + (Test3: 273 PRBs - Prach format A2), + (Test4: 106 PRBs - Prach format 0) + + $OPENAIR_DIR/cmake_targets/build_oai + --phy_simulators -c + $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash + + $OPENAIR_DIR/targets/bin/nr_prachsim.Rel15 + -a -s -30 -n 100 -p 63 -R 106 + -a -s -30 -n 100 -p 63 -R 217 + -a -s -30 -n 100 -p 63 -R 273 + -a -s -30 -n 100 -p 63 -R 106 -c 4 + nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 nr_prachsim.test4 + PRACH test OK + segmentation fault|assertion|exiting|fatal + 3 + + lte-softmodem diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 9a5d5f370c..a7adc33db3 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -406,7 +406,7 @@ function main() { shift 1;; -k | --skip-shared-libraries) SKIP_SHARED_LIB_FLAG="True" - echo_info "Skipping build of shared libraries, rfsimulator, basicsimulator and transport protocol libraries" + echo_info "Skipping build of shared libraries, rfsimulator and transport protocol libraries" shift;; --ninja) CMAKE_CMD="$CMAKE_CMD -GNinja" @@ -701,7 +701,8 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim - simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" + # simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" + simlist="ldpctest" for f in $simlist ; do compilations \ phy_simulators $f \ @@ -896,7 +897,7 @@ function main() { $build_dir rfsimulator \ librfsimulator.so $dbin/librfsimulator.so.$REL - echo_info "Compiling basicsimulator" + echo_info "Compiling tcp_bridge_oai" compilations \ $build_dir tcp_bridge_oai \ libtcp_bridge_oai.so $dbin/libtcp_bridge_oai.so.$REL @@ -958,6 +959,7 @@ function main() { wait else echo_info "10. Bypassing the Tests ..." + echo_success "BUILD SHOULD BE SUCCESSFUL" fi } diff --git a/cmake_targets/tools/build_helper b/cmake_targets/tools/build_helper index 20bc5dc2b9..b8f0125b10 100755 --- a/cmake_targets/tools/build_helper +++ b/cmake_targets/tools/build_helper @@ -150,7 +150,9 @@ clean_all_files() { set_openair_env dir=$OPENAIR_DIR/cmake_targets rm -rf $dir/log $OPENAIR_DIR/targets/bin/* - rm -rf $dir/ran_build $dir/lte-simulators/build + rm -rf $dir/ran_build $dir/ran_build_noLOG + rm -rf $dir/lte-simulators/build + rm -rf $dir/phy_simulators/build $dir/nas_sim_tools/build rm -rf $dir/oaisim_build_oai/build $dir/oaisim_build_oai/CMakeLists.txt rm -rf $dir/autotests/bin $dir/autotests/log $dir/autotests/*/build } @@ -167,17 +169,29 @@ check_warnings() { #we look for 'warning:' in the compilation log file #this is how gcc starts a warning #this is not perfect, we may get false positive - warning_count=`grep "warning:" "$1"|wc -l` + warning_count=`grep "warning:" "$1" | egrep -v "jobserver unavailable|disabling jobserver mode" | wc -l` if [ $warning_count -gt 0 ]; then echo_error "WARNING: $warning_count warnings. See $1" fi } +#check_errors: +# print error message if the compilation had errors +#argument: +# $1: log file +check_errors() { + #we look for 'warning:' in the compilation log file + error_count=`grep "error:" "$1" | wc -l` + if [ $error_count -gt 0 ]; then + echo_error "ERROR: $error_count error. See $1" + fi +} + compilations() { cd $OPENAIR_DIR/cmake_targets/$1/build + echo_info "Log file for compilation is being written to: $dlog/$2.$REL.txt" set +e { - rm -f $3 if [ "$BUILD_COVERITY_SCAN" == "1" ]; then COV_SCAN_PREFIX="cov-build --dir cov-int" else @@ -192,15 +206,22 @@ compilations() { $COV_SCAN_PREFIX make -j`nproc` $2 fi fi - + ret=$? } > $dlog/$2.$REL.txt 2>&1 set -e - echo_info "Log file for compilation has been written to: $dlog/$2.$REL.txt" + if [[ $ret -ne 0 ]]; then + check_warnings "$dlog/$2.$REL.txt" + check_errors "$dlog/$2.$REL.txt" + echo_error "$2 compilation failed" + exit 1 + fi if [ -s $3 ] ; then cp $3 $4 echo_success "$2 compiled" check_warnings "$dlog/$2.$REL.txt" else + check_warnings "$dlog/$2.$REL.txt" + check_errors "$dlog/$2.$REL.txt" echo_error "$2 compilation failed" exit 1 fi diff --git a/common/config/libconfig/config_libconfig.c b/common/config/libconfig/config_libconfig.c index 2d861f2dc3..2e9fd614c5 100644 --- a/common/config/libconfig/config_libconfig.c +++ b/common/config/libconfig/config_libconfig.c @@ -179,8 +179,8 @@ int config_libconfig_get(paramdef_t *cfgoptions,int numoptions, char *prefix ) { *(cfgoptions[i].u64ptr) = (uint64_t)llu; printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) ); } else { - *(cfgoptions[i].iptr) = llu; - printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].i64ptr)) ); + *(cfgoptions[i].i64ptr) = llu; + printf_params("[LIBCONFIG] %s: %lld\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) ); } } else { defval=config_setdefault_int64(&(cfgoptions[i]),prefix); diff --git a/common/utils/LOG/vcd_signal_dumper.c b/common/utils/LOG/vcd_signal_dumper.c index 79db7f1c0e..90857d7cd9 100644 --- a/common/utils/LOG/vcd_signal_dumper.c +++ b/common/utils/LOG/vcd_signal_dumper.c @@ -518,7 +518,29 @@ const char* eurecomFunctionsNames[] = { "wakeup_txfh", "gNB_thread_rxtx0", "gNB_thread_rxtx1", - "ru_thread_tx_wait" + "ru_thread_tx_wait", + "gNB_ulsch_decoding", + "gNB_pdsch_codeword_scrambling", + "gNB_dlsch_encoding", + "gNB_pdsch_modulation", + "gNB_pdcch_tx", + "phy_procedures_gNB_tx", + "phy_procedures_gNB_common_tx", + "phy_procedures_gNB_uespec_rx", + "nr_rx_pusch", + "nr_ulsch_procedures_rx", + "macxface_gNB_dlsch_ulsch_scheduler", + + /*NR ue-softmodem signal*/ + "nr_ue_ulsch_encoding", + "nr_segmentation", + "ldpc_encoder_optim", + "nr_rate_matching_ldpc", + "nr_interleaving_ldpc", + "pss_synchro_nr", + "pss_search_time_nr", + "nr_initial_ue_sync", + "beam_switching_gpio" }; struct vcd_module_s vcd_modules[] = { diff --git a/common/utils/LOG/vcd_signal_dumper.h b/common/utils/LOG/vcd_signal_dumper.h index 88655977bb..601465c628 100644 --- a/common/utils/LOG/vcd_signal_dumper.h +++ b/common/utils/LOG/vcd_signal_dumper.h @@ -511,6 +511,29 @@ typedef enum { VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX0, VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX1, VCD_SIGNAL_DUMPER_FUNCTIONS_RU_TX_WAIT, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER, + +/* NR ue-softmodem signal*/ + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, + VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, + VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, + VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, + VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO, + VCD_SIGNAL_DUMPER_FUNCTIONS_END } vcd_signal_dump_functions; diff --git a/common/utils/T/T_defs.h b/common/utils/T/T_defs.h index 2221dbbcac..7b5304b1cb 100644 --- a/common/utils/T/T_defs.h +++ b/common/utils/T/T_defs.h @@ -73,7 +73,7 @@ typedef struct { } T_cache_t; /* number of VCD functions (to be kept up to date! see in T_messages.txt) */ -#define VCD_NUM_FUNCTIONS (249) +#define VCD_NUM_FUNCTIONS (269) /* number of VCD variables (to be kept up to date! see in T_messages.txt) */ #define VCD_NUM_VARIABLES (187) diff --git a/common/utils/T/T_messages.txt b/common/utils/T/T_messages.txt index 3838518834..d036b40560 100644 --- a/common/utils/T/T_messages.txt +++ b/common/utils/T/T_messages.txt @@ -3393,3 +3393,106 @@ ID = VCD_FUNCTION_RU_TX_WAIT GROUP = ALL:VCD:ENB:VCD_FUNCTION FORMAT = int,value VCD_NAME = ru_thread_tx_wait +ID = VCD_FUNCTION_PHY_gNB_ULSCH_DECODING + DESC = VCD function PHY_gNB_ULSCH_DECODING + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_ulsch_decoding +ID = VCD_FUNCTION_gNB_PDSCH_CODEWORD_SCRAMBLING + DESC = VCD function gNB_PDSCH_CODEWORD_SCRAMBLING + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_pdsch_codeword_scrambling +ID = VCD_FUNCTION_gNB_DLSCH_ENCODING + DESC = VCD function gNB_DLSCH_ENCODING + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_dlsch_encoding +ID = VCD_FUNCTION_gNB_PDSCH_MODULATION + DESC = VCD function gNB_PDSCH_MODULATION + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_pdsch_modulation +ID = VCD_FUNCTION_PHY_gNB_PDCCH_TX + DESC = VCD function PHY_gNB_PDCCH_TX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_pdcch_tx +ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_TX + DESC = VCD function PHY_PROCEDURES_gNB_TX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = phy_procedures_gNB_tx +ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_COMMON_TX + DESC = VCD function PHY_PROCEDURES_gNB_COMMON_TX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = phy_procedures_gNB_common_tx +ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_UESPEC_RX + DESC = VCD function PHY_PROCEDURES_gNB_UESPEC_RX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = phy_procedures_gNB_uespec_rx +ID = VCD_FUNCTION_NR_RX_PUSCH + DESC = VCD function NR_RX_PUSCH + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_rx_pusch +ID = VCD_FUNCTION_NR_ULSCH_PROCEDURES_RX + DESC = VCD function NR_ULSCH_PROCEDURES_RX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_ulsch_procedures_rx +ID = VCD_FUNCTION_gNB_DLSCH_ULSCH_SCHEDULER + DESC = VCD function gNB_DLSCH_ULSCH_SCHEDULER + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = macxface_gNB_dlsch_ulsch_scheduler + + #function for nrUE +ID = VCD_FUNCTION_NR_UE_ULSCH_ENCODING + DESC = VCD function NR_UE_ULSCH_ENCODING + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_ue_ulsch_encoding +ID = VCD_FUNCTION_NR_SEGMENTATION + DESC = VCD function NR_SEGMENTATION + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_segmentation +ID = VCD_FUNCTION_LDPC_ENCODER_OPTIM + DESC = VCD function LDPC_ENCODER_OPTIM + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = ldpc_encoder_optim +ID = VCD_FUNCTION_NR_RATE_MATCHING_LDPC + DESC = VCD function NR_RATE_MATCHING_LDPC + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_rate_matching_ldpc +ID = VCD_FUNCTION_NR_INTERLEAVING_LDPC + DESC = VCD function NR_INTERLEAVING_LDPC + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_interleaving_ldpc +ID = VCD_FUNCTION_PSS_SYNCHRO_NR + DESC = VCD function PSS_SYNCHRO_NR + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = pss_synchro_nr +ID = VCD_FUNCTION_PSS_SEARCH_TIME_NR + DESC = VCD function PSS_SEARCH_TIME_NR + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = pss_search_time_nr +ID = VCD_FUNCTION_NR_INITIAL_UE_SYNC + DESC = VCD function NR_INITIAL_UE_SYNC + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_initial_ue_sync +ID = VCD_FUNCTION_BEAM_SWITCHING_GPIO + DESC = VCD function BEAM_SWITCHING_GPIO + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = beam_switching_gpio + diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c index 8a236c49f9..5f07fc00aa 100644 --- a/common/utils/nr/nr_common.c +++ b/common/utils/nr/nr_common.c @@ -52,6 +52,7 @@ int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB) { else return(N_RB-1-tmp2); } +/* TS 38.214 ch. 6.1.2.2.2 - Resource allocation type 1 for DL and UL */ int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) { AssertFatal(NPRB>0 && (NPRB + RBstart <= BWPsize),"Illegal NPRB/RBstart Configuration (%d,%d) for BWPsize %d\n",NPRB,RBstart,BWPsize); @@ -62,14 +63,21 @@ int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) { int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) { return(PRBalloc_to_locationandbandwidth0(NPRB,RBstart,275)); } + /// Target code rate tables indexed by Imcs +/* TS 38.214 table 5.1.3.1-1 - MCS index table 1 for PDSCH */ uint16_t nr_target_code_rate_table1[29] = {120, 157, 193, 251, 308, 379, 449, 526, 602, 679, 340, 378, 434, 490, 553, \ 616, 658, 438, 466, 517, 567, 616, 666, 719, 772, 822, 873, 910, 948}; - // Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point + +/* TS 38.214 table 5.1.3.1-2 - MCS index table 2 for PDSCH */ +// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point uint16_t nr_target_code_rate_table2[28] = {120, 193, 308, 449, 602, 378, 434, 490, 553, 616, 658, 466, 517, 567, \ 616, 666, 719, 772, 822, 873, 1365, 711, 754, 797, 841, 885, 1833, 948}; + +/* TS 38.214 table 5.1.3.1-3 - MCS index table 3 for PDSCH */ uint16_t nr_target_code_rate_table3[29] = {30, 40, 50, 64, 78, 99, 120, 157, 193, 251, 308, 379, 449, 526, 602, 340, \ 378, 434, 490, 553, 616, 438, 466, 517, 567, 616, 666, 719, 772}; + uint16_t nr_tbs_table[93] = {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, \ 336, 352, 368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, 640, 672, 704, 736, 768, 808, 848, 888, 928, 984, 1032, 1064, 1128, 1160, 1192, 1224, 1256, \ 1288, 1320, 1352, 1416, 1480, 1544, 1608, 1672, 1736, 1800, 1864, 1928, 2024, 2088, 2152, 2216, 2280, 2408, 2472, 2536, 2600, 2664, 2728, 2792, 2856, 2976, \ diff --git a/common/utils/ocp_itti/intertask_interface.cpp b/common/utils/ocp_itti/intertask_interface.cpp index 3d4d356dcf..22933fdd5b 100644 --- a/common/utils/ocp_itti/intertask_interface.cpp +++ b/common/utils/ocp_itti/intertask_interface.cpp @@ -91,8 +91,16 @@ task_list_t tasks[TASK_MAX]; return (EXIT_SUCCESS); } + // in the two following functions, the +32 in malloc is there to deal with gcc memory alignment + // because a struct size can be larger than sum(sizeof(struct components)) + // We should remove the itti principle of a huge union for all types of messages in paramter "msg_t ittiMsg" + // to use a more C classical pointer casting "void * ittiMsg", later casted in the right struct + // but we would have to change all legacy macros, as per this example + // #define S1AP_REGISTER_ENB_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_register_enb_req + // would become + // #define S1AP_REGISTER_ENB_REQ(mSGpTR) (s1ap_register_enb_req) mSGpTR)->ittiMsg MessageDef *itti_alloc_new_message_sized(task_id_t origin_task_id, MessagesIds message_id, MessageHeaderSize size) { - MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, sizeof(MessageHeader) + size); + MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, sizeof(MessageHeader) +32 + size); temp->ittiMsgHeader.messageId = message_id; temp->ittiMsgHeader.originTaskId = origin_task_id; temp->ittiMsgHeader.ittiMsgSize = size; @@ -100,7 +108,7 @@ task_list_t tasks[TASK_MAX]; } MessageDef *itti_alloc_new_message(task_id_t origin_task_id, MessagesIds message_id) { - int size=sizeof(MessageHeader) + messages_info[message_id].size; + int size=sizeof(MessageHeader) + 32 + messages_info[message_id].size; MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, size); temp->ittiMsgHeader.messageId = message_id; temp->ittiMsgHeader.originTaskId = origin_task_id; diff --git a/common/utils/ocp_itti/intertask_interface.h b/common/utils/ocp_itti/intertask_interface.h index 0cd25ee231..026c8270d7 100644 --- a/common/utils/ocp_itti/intertask_interface.h +++ b/common/utils/ocp_itti/intertask_interface.h @@ -256,6 +256,7 @@ typedef struct IttiMsgText_s { //#include #include +#include void *rrc_enb_process_itti_msg(void *); #include #include @@ -414,7 +415,7 @@ static const message_info_t messages_info[] = { #undef MESSAGE_DEF }; -typedef struct __attribute__ ((__packed__)) MessageDef_s { +typedef struct MessageDef_s { MessageHeader ittiMsgHeader; /**< Message header */ msg_t ittiMsg; } MessageDef; diff --git a/doc/BUILD.md b/doc/BUILD.md index 9ada32e532..97f9047596 100644 --- a/doc/BUILD.md +++ b/doc/BUILD.md @@ -16,7 +16,6 @@ This page is valid on tags starting from **`2019.w09`**. # Soft Modem Build Script -oai EPC is developed in a distinct project with it's own [documentation](https://github.com/OPENAIRINTERFACE/openair-cn/wiki) , it is not described here. OAI softmodem sources, which aim to implement 3GPP compliant UEs, eNodeB and gNodeB can be downloaded from the Eurecom [gitlab repository](./GET_SOURCES.md). diff --git a/doc/FEATURE_SET.md b/doc/FEATURE_SET.md index f71b9acb33..23d32effbb 100644 --- a/doc/FEATURE_SET.md +++ b/doc/FEATURE_SET.md @@ -1,6 +1,8 @@ **Table of Contents** -1. [OpenAirInterface eNB Feature Set](#openairinterface-enb-feature-set) +1. [Functional Split Architecture](#functional-split-architecture) +2. [OpenAirInterface Block Diagram](#openairinterface-block-diagram) +2. [OpenAirInterface 4G-LTE eNB Feature Set](#openairinterface-4g-lte-enb-feature-set) 1. [eNB PHY Layer](#enb-phy-layer) 2. [eNB MAC Layer](#enb-mac-layer) 3. [eNB RLC Layer](#enb-rlc-layer) @@ -9,29 +11,38 @@ 6. [eNB X2AP](#enb-x2ap) 7. [eNB/MCE M2AP](#enbmce-m2ap) 8. [MCE/MME M3AP](#mcemme-m3ap) - 9. [eNB Advanced Features](#enb-advanced-features) -2. [OpenAirInterface Functional Split](#openairinterface-functional-split) -3. [OpenAirInterface UE Feature Set](#openairinterface-ue-feature-set) +3. [OpenAirInterface 4G-LTE UE Feature Set](#openairinterface-4g-lte-ue-feature-set) 1. [LTE UE PHY Layer](#lte-ue-phy-layer) 2. [LTE UE MAC Layer](#lte-ue-mac-layer) 3. [LTE UE RLC Layer](#lte-ue-rlc-layer) 4. [LTE UE PDCP Layer](#lte-ue-pdcp-layer) 5. [LTE UE RRC Layer](#lte-ue-rrc-layer) -4. [OpenAirInterface Functional Split](#openairinterface-functional-split) -5. [OpenAirInterface 5G-NR Feature Set](#openairinterface-5g-nr-feature-set) +4. [OpenAirInterface 5G-NR gNB Feature Set](#openairinterface-5g-nr-feature-set) 1. [General Parameters](#general-parameters) - 2. [gNB Features](#gnb-features) - 1. [gNB Physical Layer](#gnb-phy-layer) - 2. [gNB Higher Layers](#gnb-higher-layers) - 3. [NR UE Features](#nr-ue-features) - 1. [NR UE Physical Layer](#nr-ue-phy-layer) - 2. [NR UE Higher Layers](#nr-ue-higher-layers) + 2. [gNB Physical Layer](#gnb-phy-layer) + 3. [gNB Higher Layers](#gnb-higher-layers) +5. [OpenAirInterface 5G-NR UE Feature Set](#openairinterface-5g-nr-ue-feature-set) + 1. [UE Physical Layer](#ue-phy-layer) + 2. [UE Higher Layers](#ue-higher-layers) -# OpenAirInterface Block diagram # + +# Functional Split Architecture # + +- RCC: Radio-Cloud Center +- RAU: Radio-Access Unit +- RRU: Remote Radio-Unit +- IF4.5 / IF5 : similar to IEEE P1914.1 +- FAPI (IF2) : specified by Small Cell Forum (open-nFAPI implementation) +- IF1 : F1 in 3GPP Release 15 + +![Functional Split Architecture](./oai_enb_func_split_arch.png) + + +# OpenAirInterface Block Diagram # ![Block Diagram](./oai_enb_block_diagram.png) -# OpenAirInterface eNB Feature Set # +# OpenAirInterface 4G LTE eNB Feature Set # ## eNB PHY Layer ## @@ -82,7 +93,11 @@ TDD UL: 20 MHz, 100 PRBS/ MCS **XX** | 3.0 Mbit/s | TM1: 4.21 Mbits/s The MAC layer implements a subset of the **3GPP 36.321** release v8.6 in support of BCH, DLSCH, RACH, and ULSCH channels. - RRC interface for CCCH, DCCH, and DTCH -- Proportional fair scheduler (round robin scheduler soon) +- Proportional fair scheduler (round robin scheduler soon), with the following improvements: + - Up to 30 users tested in the L2 simulator, CCE allocation in the preprocessor ; the scheduler was also simplified and made more modular + - Adaptative UL-HARQ + - Remove out-of-sync UEs + - No use of the `first_rb` in the UL scheduler ; respects `vrb_map_UL` and `vrb_map` in the DL - DCI generation - HARQ Support - RA procedures and RNTI management @@ -123,7 +138,7 @@ The current PDCP layer is header compliant with **3GPP 36.323** Rel 10.1.0 and i ## eNB RRC Layer ## -The RRC layer is based on **3GPP 36.331** v14.3.0 and implements the following functions: +The RRC layer is based on **3GPP 36.331** v15.6 and implements the following functions: - System Information broadcast (SIB 1, 2, 3, and 13) * SIB1: Up to 6 PLMN IDs broadcast @@ -150,6 +165,10 @@ The X2AP layer is based on **3GPP 36.423** v14.6.0 and implements the following - X2 timers (t_reloc_prep, tx2_reloc_overall) - Handover Cancel - X2-U interface implemented + - EN-DC is implemented + - X2AP : Handling of SgNB Addition Request / Addition Request Acknowledge / Reconfiguration Complete + - RRC : Handling of RRC Connection Reconfiguration with 5G cell info, configuration of 5G-NR measurements + - S1AP : Handling of E-RAB Modification Indication / Confirmation ## eNB/MCE M2AP ## @@ -171,11 +190,8 @@ The M3AP layer is based on **3GPP 36.444** v14.0.1: - M3 Session Start Request - M3 Session Start Response -## eNB Advanced Features ## -**To be completed** - -# OpenAirInterface UE Feature Set # +# OpenAirInterface 4G LTE UE Feature Set # ## LTE UE PHY Layer ## @@ -230,17 +246,6 @@ The NAS layer is based on **3GPP 24.301** and implements the following functions - EMM attach/detach, authentication, tracking area update, and more - ESM default/dedicated bearer, PDN connectivity, and more -# OpenAirInterface Functional Split # - -- RCC: Radio-Cloud Center -- RAU: Radio-Access Unit -- RRU: Remote Radio-Unit - -![Functional Split Architecture](./oai_enb_func_split_arch.png) - -- IF4.5 / IF5 : similar to IEEE P1914.1 -- FAPI (IF2) : specified by Small Cell Forum (open-nFAPI implementation) -- IF1 : F1 in 3GPP Release 15 # OpenAirInterface 5G-NR Feature Set # @@ -258,49 +263,103 @@ The following features are valid for the gNB and the 5G-NR UE. * Highly efficient 3GPP compliant polar encoder and decoder * Encoder and decoder for short blocks -## gNB Features ## -### gNB PHY Layer ### +## gNB PHY Layer ## -* Generation of PSS/SSS/PBCH for multiple beams and -* Generation of PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc) +* 30KHz SCS for FR1 and 120 KHz SCS for FR2 +* Generation of NR-PSS/NR-SSS +* NR-PBCH supports multiple SSBs and flexible periodicity +* Generation of NR-PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc) - common search space configured by MIB - user-specific search space configured by RRC - - DCI formats: 00, 10 -* Generation of PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). - - Single symbol DMRS, dmrs-TypeA-Position Pos2, DMRS configuration type 1 - - PDSCH mapping type A + - DCI formats: 00, 10 (01 and 11 **under integration**) +* Generation of NR-PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). + - Single symbol DMRS, DMRS-TypeA-Position Pos2, DMRS configuration type 1 + - PDSCH mapping type A +* NR-CSI Generation of sequence at PHY (**under integration**) * NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). * NR-PUCCH - - Format 0 (ACK/NACK) + - Format 0 (2 bits, mainly for ACK/NACK) + - Format 2 (up to 64 bits, mainly for CSI feedback) +* NR-PRACH + - Formats 0,1,2,3, A1-A3, B1-B3 +* Highly efficient 3GPP compliant LDPC encoder and decoder (BG1 and BG2 are supported) +* Highly efficient 3GPP compliant polar encoder and decoder +* Encoder and decoder for short block -### gNB higher Layers ### - +## gNB Higher Layers ## + +**gNB RRC** - NR RRC (38.331) Rel 15 messages using new asn1c - LTE RRC (36.331) also updated to Rel 15 -- Generation of MIB +- Generation of CellGroupConfig (for eNB) and MIB - Application to read configuration file and program gNB RRC -- RRC -> MAC configuration -- MAC -> PHY configuration (using NR FAPI P5 interface) -- FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU +- RRC can configure PDCP, RLC, MAC -For more details see [this document](https://gitlab.eurecom.fr/oai/openairinterface5g/uploads/ba5368448d627743a28c770c29e8978e/OAI_Software_Architecture_for_Dual_Connectivity_in_E-UTRA_and_5G-NR_and_nFAPI_for_MAC-PHY_Interface.docx) +**gNB X2AP** +- X2 setup with eNB +- Handling of SgNB Addition Request / Addition Request Acknowledge / Reconfiguration Complete -## NR UE Features ## +**gNB MAC** +- MAC -> PHY configuration using NR FAPI P5 interface +- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU +- Scheduler for RA procedreat gNB +- MAC downlink scheduler (fixed allocations) +- MAC header generation (including timing advance) +- ACK / NACK handling and HARQ procedures for downlink +- **As of May 2020** only DL was validated with COTS phone ; UL in progress, validated with OAI UE in noS1 mode -### NR UE PHY Layer ### +# OpenAirInterface 5G-NR UE Feature Set # -- initial synchronization -- Time tracking based on PDCCH DMRS -- Frequency offset estimation -- PBCH RX -- PDCCH RX -- PDSCH RX - - including first version of dual stream receiver for PDSCH +**as of May 2020** only supporting "noS1" mode (DL): +- Creates TUN interface to PDCP to inject and receive user-place traffic +- Will only work with OAI gNB configured in the same mode + +## UE PHY Layer ## + +* Initial synchronization +* Time tracking based on PBCH DMRS +* Time tracking based on PBCH DMRS +* Frequency offset estimation +* PBCH RX +* PDCCH RX +* PDSCH RX, including a first version of dual stream receiver for PDSCH +* 30KHz SCS for FR1 and 120 KHz SCS for FR2 +* Generation of NR-PSS/NR-SSS +* NR-PBCH supports multiple SSBs and flexible periodicity +* Generation of NR-PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc) + - common search space configured by MIB + - user-specific search space configured by RRC + - DCI formats: 00, 10 (01 and 11 **under integration**) +* Generation of NR-PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). + - Single symbol DMRS, DMRS-TypeA-Position Pos2, DMRS configuration type 1 + - PDSCH mapping type A +* NR-CSI Generation of sequence at PHY (**under integration**) +* NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). +* NR-PUCCH + - Format 0 (2 bits, mainly for ACK/NACK) + - Format 2 (up to 64 bits, mainly for CSI feedback) +* NR-PRACH + - Formats 0,1,2,3, A1-A3, B1-B3 +* Highly efficient 3GPP compliant LDPC encoder and decoder (BG1 and BG2 are supported) +* Highly efficient 3GPP compliant polar encoder and decoder +* Encoder and decoder for short block + + +## UE Higher Layers ## + +**gNB MAC** +- Initial sync and MIB detection +- MAC -> PHY configuration of PHY via UE FAPI P5 interface +- Basic MAC to control PHY via UE FAPI P7 interface +- Random access procedure + + +**RLC** + +**PDCP** -### NR UE higher Layers ### -For more details see [this document](https://gitlab.eurecom.fr/oai/openairinterface5g/uploads/f7386f3a64806fd6b2ac1fc3d0252fff/UE_FAPI-like_interface.docx) [OAI wiki home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home) diff --git a/doc/RUNMODEM.md b/doc/RUNMODEM.md index 0c66b58547..37eadd92f3 100644 --- a/doc/RUNMODEM.md +++ b/doc/RUNMODEM.md @@ -56,9 +56,56 @@ oai supports [number of deployment](FEATURE_SET.md) model, the following are tes 1. [Monolithic eNodeB](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/HowToConnectCOTSUEwithOAIeNBNew) where the whole signal processing is performed in a single process 2. if4p5 mode, where frequency domain samples are carried over ethernet, from the RRU which implement part of L1(FFT,IFFT,part of PRACH), to a RAU +# 5G NR + +As of February 2020, all 5G NR development is part of the develop branch (the branch develop-nr is no longer maintained). This also means that all new development will be merged into there once it passes all the CI. + +## NSA setup with COTS UE + +This setup requires an EPC, an OAI eNB and gNB, and a COTS Phone. A dedicated page describe the setup can be found [here](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home/gNB-COTS-UE-testing). + +### Launch gNB + +```bash sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf``` + +### Launch eNB + +```bash sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf``` +## phy-test setup with OAI UE + +The OAI UE can also be used in front of a OAI gNB without the support of eNB or EPC. In this case both gNB and eNB need to be run with the --phy-test flag. At the gNB this flag does the following + - it reads the RRC configuration from the configuration file + - it encodes the RRCConfiguration and the RBconfig message and stores them in the binary files rbconfig.raw and reconfig.raw + - the MAC uses a pre-configured allocation of PDSCH and PUSCH with randomly generated payload + +At the UE the --phy-test flag will + - read the binary files rbconfig.raw and reconfig.raw from the current directory (a different directory can be specified with the flag --rrc_config_path) and process them. + + +### Launch gNB + +```bash sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test``` + +### Launch UE in another window + +```bash sudo ./nr-uesoftmodem --phy-test [--rrc_config_path ../../../ci-scripts/rrc-files]``` + +Some other useful paramters of the UE are + + - --ue-fo-compensation: enables the frequency offset compenstation at the UE. This is useful when running over the air and/or without an external clock/time source + - --usrp-args: this is the equivalend paramter of sdr_addrs field in the gNB config file and can be used to identify the USRP and set some basic paramters (like the clock source) + - --clock-source: sets the clock-source (internal or external). + - --time-source: sets the time-source (internal or external). + + +## noS1 setup with OAI UE + +Instead of randomly generated payload, in the phy-test mode we can also inject/receive user-plane traffic over a TUN interface. This is the so-called noS1 mode. + +This setup is described in the [rfsimulator page](../targets/ARCH/rfsimulator/README.md#5g-case). In theory this should also work with the real hardware target although this has yet to be tested. diff --git a/executables/main-ocp.c b/executables/main-ocp.c index d2ee9418dc..e4e42b4f23 100644 --- a/executables/main-ocp.c +++ b/executables/main-ocp.c @@ -80,6 +80,7 @@ int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; int split73; char * split73_config; int split73; +int usrp_tx_thread = 0; static void *ru_thread( void *param ); void kill_RU_proc(RU_t *ru) { @@ -1152,6 +1153,7 @@ int restart_L1L2(module_id_t enb_id) { } int main ( int argc, char **argv ) { + //mtrace(); int i; int CC_id = 0; int node_type = ngran_eNB; diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index aa16c771ae..27b0ed08dd 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -47,7 +47,7 @@ #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" #include "SCHED_NR/fapi_nr_l1.h" -#include "PHY/LTE_TRANSPORT/transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all //#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all @@ -61,7 +61,6 @@ #include "PHY/phy_extern.h" - #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" #include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface.h" @@ -162,14 +161,14 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t /*if (gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus|| gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs || gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs || - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles || + gNB->UL_INFO.rach_ind.number_of_pdus || gNB->UL_INFO.cqi_ind.number_of_cqis ) { - LOG_D(PHY, "UL_info[rx_ind:%05d:%d harqs:%05d:%d crcs:%05d:%d preambles:%05d:%d cqis:%d] RX:%04d%d TX:%04d%d \n", + LOG_D(PHY, "UL_info[rx_ind:%05d:%d harqs:%05d:%d crcs:%05d:%d rach_pdus:%0d.%d:%d cqis:%d] RX:%04d%d TX:%04d%d \n", NFAPI_SFNSF2DEC(gNB->UL_INFO.rx_ind.sfn_sf), gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus, NFAPI_SFNSF2DEC(gNB->UL_INFO.harq_ind.sfn_sf), gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs, NFAPI_SFNSF2DEC(gNB->UL_INFO.crc_ind.sfn_sf), gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs, - NFAPI_SFNSF2DEC(gNB->UL_INFO.rach_ind.sfn_sf), gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles, + gNB->UL_INFO.rach_ind.sfn, gNB->UL_INFO.rach_ind.slot,gNB->UL_INFO.rach_ind.number_of_pdus, gNB->UL_INFO.cqi_ind.number_of_cqis, frame_rx, slot_rx, frame_tx, slot_tx); @@ -202,6 +201,13 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t if (rx_slot_type == NR_UPLINK_SLOT || rx_slot_type == NR_MIXED_SLOT) { // UE-specific RX processing for subframe n // TODO: check if this is correct for PARALLEL_RU_L1_TRX_SPLIT + + // Do PRACH RU processing + int prach_id=find_nr_prach(gNB,frame_rx,slot_rx,0,SEARCH_EXIST); + if (prach_id>=0) { + L1_nr_prach_procedures(gNB,frame_rx,slot_rx,&gNB->prach_vars.list[prach_id].pdu); + gNB->prach_vars.list[prach_id].frame=-1; + } phy_procedures_gNB_uespec_RX(gNB, frame_rx, slot_rx); } @@ -957,12 +963,14 @@ void init_gNB(int single_thread_flag,int wait_for_sync) { gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); LOG_I(PHY,"Setting indication lists\n"); + gNB->UL_INFO.rx_ind.pdu_list = gNB->rx_pdu_list; gNB->UL_INFO.crc_ind.crc_list = gNB->crc_pdu_list; /*gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list; gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = gNB->harq_pdu_list; gNB->UL_INFO.cqi_ind.cqi_pdu_list = gNB->cqi_pdu_list; gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list;*/ + gNB->prach_energy_counter = 0; } diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 3ea026f6e6..969ad21b8e 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -51,6 +51,7 @@ #include "PHY/defs_nr_common.h" #include "PHY/phy_extern.h" #include "PHY/LTE_TRANSPORT/transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/INIT/phy_init.h" #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" @@ -117,6 +118,7 @@ uint16_t sl_ahead; extern int emulate_rf; extern int numerology; +extern int usrp_tx_thread; /*************************************************************/ /* Functions to attach and configure RRU */ @@ -289,7 +291,7 @@ void fh_if5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) // southbound IF4p5 fronthaul void fh_if4p5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) { - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; if (ru == RC.ru[0]) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, ru->proc.timestamp_tx&0xffffffff ); LOG_D(PHY,"Sending IF4p5 for frame %d subframe %d\n",ru->proc.frame_tx,ru->proc.tti_tx); @@ -500,7 +502,7 @@ void fh_if5_north_asynch_in(RU_t *ru,int *frame,int *slot) { void fh_if4p5_north_asynch_in(RU_t *ru,int *frame,int *slot) { NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; RU_proc_t *proc = &ru->proc; uint16_t packet_type; uint32_t symbol_number,symbol_mask,symbol_mask_full=0; @@ -697,7 +699,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { RU_proc_t *proc = &ru->proc; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; void *txp[ru->nb_tx]; unsigned int txs; int i,txsymb; @@ -770,8 +772,8 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { siglen+sf_extension, ru->nb_tx, flags); - LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %d\n",ru->idx, - (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot); + LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %di, returned %d\n",ru->idx, + (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot, txs); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0 ); //AssertFatal(txs == 0,"trx write function error %d\n", txs); } @@ -789,7 +791,7 @@ void *ru_thread_asynch_rxtx( void *param ) { static int ru_thread_asynch_rxtx_status; RU_t *ru = (RU_t *)param; RU_proc_t *proc = &ru->proc; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; int slot=0, frame=0; // wait for top-level synchronization and do one acquisition to get timestamp for setting frame/subframe wait_sync("ru_thread_asynch_rxtx"); @@ -1034,10 +1036,10 @@ int wakeup_prach_ru(RU_t *ru) { void fill_rf_config(RU_t *ru, char *rf_config_file) { int i; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; //tmp index + nfapi_nr_config_request_scf_t *config = &ru->config; //tmp index openair0_config_t *cfg = &ru->openair0_cfg; - int mu = gNB_config->ssb_config.scs_common.value; - int N_RB = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; + int mu = config->ssb_config.scs_common.value; + int N_RB = config->carrier_config.dl_grid_size[config->ssb_config.scs_common.value].value; if (mu == NR_MU_0) { //or if LTE if(N_RB == 100) { @@ -1122,7 +1124,7 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) { AssertFatal(0 == 1,"Numerology %d not supported for the moment\n",mu); } - if (gNB_config->cell_config.frame_duplex_type.value==TDD) + if (config->cell_config.frame_duplex_type.value==TDD) cfg->duplex_mode = duplex_mode_TDD; else //FDD cfg->duplex_mode = duplex_mode_FDD; @@ -1161,7 +1163,7 @@ int setup_RU_buffers(RU_t *ru) { int card,ant; //uint16_t N_TA_offset = 0; NR_DL_FRAME_PARMS *frame_parms; - //nfapi_nr_config_request_t *gNB_config = ru->gNB_list[0]->gNB_config; //tmp index + nfapi_nr_config_request_scf_t *config = &ru->config; if (ru) { frame_parms = ru->nr_frame_parms; @@ -1170,12 +1172,54 @@ int setup_RU_buffers(RU_t *ru) { printf("ru pointer is NULL\n"); return(-1); } + int mu = config->ssb_config.scs_common.value; + int N_RB = config->carrier_config.dl_grid_size[config->ssb_config.scs_common.value].value; - /* if (frame_parms->frame_type == TDD) { - if (frame_parms->N_RB_DL == 100) ru->N_TA_offset = 624; - else if (frame_parms->N_RB_DL == 50) ru->N_TA_offset = 624/2; - else if (frame_parms->N_RB_DL == 25) ru->N_TA_offset = 624/4; - } */ + + if (config->cell_config.frame_duplex_type.value == TDD) { + int N_TA_offset = config->carrier_config.uplink_frequency.value < 6000000 ? 400 : 431; // reference samples for 25600Tc @ 30.72 Ms/s for FR1, same @ 61.44 Ms/s for FR2 + + double factor=1; + + switch (mu) { + case 0: //15 kHz scs + AssertFatal(N_TA_offset == 400,"scs_common 15kHz only for FR1\n"); + if (N_RB <= 25) factor = .25; // 7.68 Ms/s + else if (N_RB <=50) factor = .5; // 15.36 Ms/s + else if (N_RB <=75) factor = 1.0; // 30.72 Ms/s + else if (N_RB <=100) factor = 1.0; // 30.72 Ms/s + else AssertFatal(1==0,"Too many PRBS for mu=0\n"); + break; + case 1: //30 kHz sc + AssertFatal(N_TA_offset == 400,"scs_common 30kHz only for FR1\n"); + if (N_RB <= 106) factor = 2.0; // 61.44 Ms/s + else if (N_RB <= 275) factor = 4.0; // 122.88 Ms/s + break; + case 2: //60 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + break; + case 3: //120 kHz scs + AssertFatal(N_TA_offset == 431,"scs_common 120kHz only for FR2\n"); + break; + case 4: //240 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + if (N_RB <= 32) factor = 1.0; // 61.44 Ms/s + else if (N_RB <= 66) factor = 2.0; // 122.88 Ms/s + else AssertFatal(1==0,"N_RB %d is too big for curretn FR2 implementation\n",N_RB); + break; + + if (N_RB == 100) ru->N_TA_offset = 624; + else if (N_RB == 50) ru->N_TA_offset = 624/2; + else if (N_RB == 25) ru->N_TA_offset = 624/4; + } + if (frame_parms->threequarter_fs == 1) factor = factor*.75; + ru->N_TA_offset = (int)(N_TA_offset * factor); + LOG_I(PHY,"RU %d Setting N_TA_offset to %d samples (factor %f, UL Freq %d, N_RB %d)\n",ru->idx,ru->N_TA_offset,factor, + config->carrier_config.uplink_frequency.value, N_RB); + } + else ru->N_TA_offset = 0; + + if (ru->openair0_cfg.mmapped_dma == 1) { // replace RX signal buffers with mmaped HW versions for (i=0; inb_rx; i++) { @@ -1388,7 +1432,7 @@ void *ru_thread( void *param ) { int i = 0; int aa; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; // set default return value ru_thread_status = 0; @@ -1400,7 +1444,7 @@ void *ru_thread( void *param ) { if(emulate_rf) { fill_rf_config(ru,ru->rf_config_file); - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, fp); + nr_init_frame_parms(&ru->config, fp); nr_dump_frame_parms(fp); nr_phy_init_RU(ru); @@ -1420,8 +1464,10 @@ void *ru_thread( void *param ) { AssertFatal(ret==0,"Cannot connect to remote radio\n"); } + memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); + if (ru->if_south == LOCAL_RF) { // configure RF parameters only - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, fp); + nr_init_frame_parms(&ru->config, fp); nr_dump_frame_parms(fp); fill_rf_config(ru,ru->rf_config_file); nr_phy_init_RU(ru); @@ -1465,12 +1511,14 @@ void *ru_thread( void *param ) { if ((ru->is_slave) && (ru->if_south == LOCAL_RF)) do_ru_synch(ru); // start trx write thread - if (ru->start_write_thread){ - if(ru->start_write_thread(ru) != 0){ - LOG_E(HW,"Could not start tx write thread\n"); - } - else{ - LOG_I(PHY,"tx write thread ready\n"); + if(usrp_tx_thread == 1){ + if (ru->start_write_thread){ + if(ru->start_write_thread(ru) != 0){ + LOG_E(HW,"Could not start tx write thread\n"); + } + else{ + LOG_I(PHY,"tx write thread ready\n"); + } } } } @@ -1532,6 +1580,17 @@ void *ru_thread( void *param ) { for (aa=0;aanb_rx;aa++) memcpy((void*)RC.gNB[0]->common_vars.rxdataF[aa], (void*)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t)); + + // Do PRACH RU processing + int prach_id=find_nr_prach_ru(ru,proc->frame_rx,proc->tti_rx,SEARCH_EXIST); + if (prach_id>=0) { + rx_nr_prach_ru(ru, + ru->prach_list[prach_id].fmt, + ru->prach_list[prach_id].numRA, + ru->prach_list[prach_id].prachStartSymbol, + proc->frame_rx,proc->tti_rx); + free_nr_ru_prach_entry(ru,prach_id); + } } // At this point, all information for subframe has been received on FH interface @@ -1903,7 +1962,7 @@ void configure_ru(int idx, RU_t *ru = RC.ru[idx]; RRU_config_t *config = (RRU_config_t *)arg; RRU_capabilities_t *capabilities = (RRU_capabilities_t *)arg; - nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; int ret; LOG_I(PHY, "Received capabilities from RRU %d\n",idx); @@ -1926,15 +1985,15 @@ void configure_ru(int idx, //config->tdd_config_S[0] = ru->nr_frame_parms->tdd_config_S; config->att_tx[0] = ru->att_tx; config->att_rx[0] = ru->att_rx; - config->N_RB_DL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; - config->N_RB_UL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; + config->N_RB_DL[0] = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value; + config->N_RB_UL[0] = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value; config->threequarter_fs[0] = ru->nr_frame_parms->threequarter_fs; /* if (ru->if_south==REMOTE_IF4p5) { config->prach_FreqOffset[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset; config->prach_ConfigIndex[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; LOG_I(PHY,"REMOTE_IF4p5: prach_FrequOffset %d, prach_ConfigIndex %d\n", config->prach_FreqOffset[0],config->prach_ConfigIndex[0]);*/ - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, ru->nr_frame_parms); + nr_init_frame_parms(&ru->config, ru->nr_frame_parms); nr_phy_init_RU(ru); } @@ -1942,23 +2001,23 @@ void configure_rru(int idx, void *arg) { RRU_config_t *config = (RRU_config_t *)arg; RU_t *ru = RC.ru[idx]; - nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; ru->nr_frame_parms->nr_band = config->band_list[0]; ru->nr_frame_parms->dl_CarrierFreq = config->tx_freq[0]; ru->nr_frame_parms->ul_CarrierFreq = config->rx_freq[0]; if (ru->nr_frame_parms->dl_CarrierFreq == ru->nr_frame_parms->ul_CarrierFreq) { - gNB_config->cell_config.frame_duplex_type.value = TDD; + cfg->cell_config.frame_duplex_type.value = TDD; //ru->nr_frame_parms->tdd_config = config->tdd_config[0]; //ru->nr_frame_parms->tdd_config_S = config->tdd_config_S[0]; } else - gNB_config->cell_config.frame_duplex_type.value = FDD; + cfg->cell_config.frame_duplex_type.value = FDD; ru->att_tx = config->att_tx[0]; ru->att_rx = config->att_rx[0]; - int mu = gNB_config->ssb_config.scs_common.value; - gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0]; - gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0]; + int mu = cfg->ssb_config.scs_common.value; + cfg->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0]; + cfg->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0]; ru->nr_frame_parms->threequarter_fs = config->threequarter_fs[0]; //ru->nr_frame_parms->pdsch_config_common.referenceSignalPower = ru->max_pdschReferenceSignalPower-config->att_tx[0]; @@ -1973,7 +2032,7 @@ void configure_rru(int idx, } fill_rf_config(ru,ru->rf_config_file); - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, ru->nr_frame_parms); + nr_init_frame_parms(&ru->config, ru->nr_frame_parms); nr_phy_init_RU(ru); } diff --git a/executables/nr-softmodem-common.h b/executables/nr-softmodem-common.h index ccb3f28d98..c968fee7b6 100644 --- a/executables/nr-softmodem-common.h +++ b/executables/nr-softmodem-common.h @@ -57,6 +57,7 @@ #define CONFIG_HLP_DLSHIFT "dynamic shift for LLR compuation for TM3/4 (default 0)\n" #define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n" #define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n" +#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n" #define CONFIG_HLP_DMAMAP "sets flag for improved EXMIMO UE performance\n" #define CONFIG_HLP_EXCCLK "tells hardware to use a clock reference (0:internal(default), 1:external, 2:gpsdo)\n" #define CONFIG_HLP_USIM "use XOR autentication algo in case of test usim mode\n" @@ -89,6 +90,7 @@ #define CONFIG_HLP_EMULATE_RF "Emulated RF enabled(disable by defult)\n" #define CONFIG_HLP_PARALLEL_CMD "three config for level of parallelism 'PARALLEL_SINGLE_THREAD', 'PARALLEL_RU_L1_SPLIT', or 'PARALLEL_RU_L1_TRX_SPLIT'\n" #define CONFIG_HLP_WORKER_CMD "two option for worker 'WORKER_DISABLE' or 'WORKER_ENABLE'\n" +#define CONFIG_HLP_USRP_THREAD "having extra thead for usrp tx\n" #define CONFIG_HLP_DISABLNBIOT "disable nb-iot, even if defined in config\n" #define CONFIG_HLP_USRP_ARGS "set the arguments to identify USRP (same syntax as in UHD)\n" @@ -143,6 +145,10 @@ extern int sync_var; extern int transmission_mode; extern double cpuf; +extern int emulate_rf; +extern int numerology; +extern int usrp_tx_thread; + extern volatile int start_eNB; extern volatile int start_UE; diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index f473d0161b..bf77125975 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -178,10 +178,12 @@ extern void reset_opp_meas(void); extern void print_opp_meas(void); extern void init_eNB_afterRU(void); +extern void *udp_eNB_task(void *args_p); int transmission_mode=1; int emulate_rf = 0; int numerology = 0; +int usrp_tx_thread = 0; static char *parallel_config = NULL; @@ -384,10 +386,10 @@ int create_gNB_tasks(uint32_t gnb_nb) { if (gnb_nb > 0) { /* Last task to create, others task must be ready before its start */ - if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { + /*if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { LOG_E(GNB_APP, "Create task for gNB APP failed\n"); return -1; - } + }*/ if(itti_create_task(TASK_SCTP, sctp_eNB_task, NULL) < 0){ LOG_E(SCTP, "Create task for SCTP failed\n"); return -1; @@ -402,35 +404,39 @@ int create_gNB_tasks(uint32_t gnb_nb) { } } - /* - if (EPC_MODE_ENABLED) { - if (gnb_nb > 0) { - if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { - LOG_E(SCTP, "Create task for SCTP failed\n"); - return -1; - } + if (EPC_MODE_ENABLED && (get_softmodem_params()->phy_test==0 && get_softmodem_params()->do_ra==0)) { + if (gnb_nb > 0) { + /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { + LOG_E(SCTP, "Create task for SCTP failed\n"); + return -1; + } - if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { - LOG_E(S1AP, "Create task for S1AP failed\n"); - return -1; - } - if(!emulate_rf){ - if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { - LOG_E(UDP_, "Create task for UDP failed\n"); - return -1; - } - } + if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { + LOG_E(S1AP, "Create task for S1AP failed\n"); + return -1; + }*/ - if (itti_create_task (TASK_GTPV1_U, >pv1u_eNB_task, NULL) < 0) { - LOG_E(GTPU, "Create task for GTPV1U failed\n"); - return -1; - } + + if(!emulate_rf){ + if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { + LOG_E(UDP_, "Create task for UDP failed\n"); + return -1; } + } + if (itti_create_task (TASK_GTPV1_U, >pv1u_gNB_task, NULL) < 0) { + LOG_E(GTPU, "Create task for GTPV1U failed\n"); + return -1; + } } - */ + } + if (gnb_nb > 0) { + if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { + LOG_E(GNB_APP, "Create task for gNB APP failed\n"); + return -1; + } LOG_I(NR_RRC,"Creating NR RRC gNB Task\n"); if (itti_create_task (TASK_RRC_GNB, rrc_gnb_task, NULL) < 0) { @@ -819,6 +825,10 @@ int main( int argc, char **argv ) } openair0_cfg[0].threequarter_fs = threequarter_fs; + EPC_MODE_ENABLED = !IS_SOFTMODEM_NOS1; //!get_softmodem_params()->phy_test; + + if (get_softmodem_params()->do_ra) + AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n"); #if T_TRACER T_Config_Init(); @@ -954,7 +964,9 @@ if(!IS_SOFTMODEM_NOS1) scopeParms_t p; p.argc=&argc; p.argv=argv; - startScope(&p); + p.gNB=RC.gNB[0]; + p.ru=RC.ru[0]; + gNBinitScope(&p); } if (nfapi_mode != 1 && nfapi_mode != 2) { diff --git a/executables/nr-softmodem.h b/executables/nr-softmodem.h index 27e3ba1e3e..d113ae45aa 100644 --- a/executables/nr-softmodem.h +++ b/executables/nr-softmodem.h @@ -34,6 +34,7 @@ {"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \ {"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)¶llel_config, defstrval:NULL, TYPE_STRING, 0}, \ {"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \ + {"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, iptr:&usrp_tx_thread, defstrval:0, TYPE_INT, 0}, \ {"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \ } diff --git a/executables/nr-ue.c b/executables/nr-ue.c index dbee6f1e6f..2f99027b75 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -21,7 +21,7 @@ #include "executables/thread-common.h" #include "executables/nr-uesoftmodem.h" -#include "LAYER2/NR_MAC_UE/mac.h" +#include "NR_MAC_UE/mac.h" //#include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface_extern.h" @@ -32,7 +32,7 @@ #include "PHY/phy_extern_nr_ue.h" #include "PHY/INIT/phy_init.h" #include "PHY/MODULATION/modulation_UE.h" -#include "LAYER2/NR_MAC_UE/mac_proto.h" +#include "NR_MAC_UE/mac_proto.h" #include "RRC/NR_UE/rrc_proto.h" //#ifndef NO_RAT_NR @@ -142,15 +142,24 @@ void init_nr_ue_vars(PHY_VARS_NR_UE *ue, uint8_t abstraction_flag) { + int nb_connected_gNB = 1, gNB_id; + memcpy(&(ue->frame_parms), frame_parms, sizeof(NR_DL_FRAME_PARMS)); ue->Mod_id = UE_id; ue->mac_enabled = 1; + // Setting UE mode to NOT_SYNCHED by default + for (gNB_id = 0; gNB_id < nb_connected_gNB; gNB_id++){ + ue->UE_mode[gNB_id] = NOT_SYNCHED; + ue->prach_resources[gNB_id] = (NR_PRACH_RESOURCES_t *)malloc16_clear(sizeof(NR_PRACH_RESOURCES_t)); + } + // initialize all signal buffers - init_nr_ue_signal(ue,1,abstraction_flag); + init_nr_ue_signal(ue, nb_connected_gNB, abstraction_flag); + // intialize transport - init_nr_ue_transport(ue,abstraction_flag); + init_nr_ue_transport(ue, abstraction_flag); } /*! @@ -358,82 +367,32 @@ static void UE_synch(void *arg) { void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { - uint32_t rb_size, rb_start; - uint16_t rnti, l_prime_mask, n_rb0, n_rb1, pdu_bit_map; - uint8_t nr_of_symbols, start_symbol_index, mcs_index, mcs_table, nrOfLayers, harq_process_id, rv_index, dmrs_config_type; - uint8_t ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, ptrs_time_density, ptrs_freq_density; - nr_dcireq_t dcireq; - nr_scheduled_response_t scheduled_response; - // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI - if (proc->nr_tti_tx == 8 || UE->frame_parms.frame_type == FDD){ + fapi_nr_config_request_t *cfg = &UE->nrUE_config; + int tx_slot_type = nr_ue_slot_select(cfg, proc->frame_tx, proc->nr_tti_tx); + uint8_t gNB_id = 0; - dcireq.module_id = UE->Mod_id; - dcireq.gNB_index = 0; - dcireq.cc_id = 0; - dcireq.frame = proc->frame_rx; - dcireq.slot = proc->nr_tti_rx; + if (tx_slot_type == NR_UPLINK_SLOT || tx_slot_type == NR_MIXED_SLOT){ - scheduled_response.dl_config = NULL; - scheduled_response.ul_config = &dcireq.ul_config_req; - scheduled_response.tx_request = NULL; - scheduled_response.module_id = UE->Mod_id; - scheduled_response.CC_id = 0; - scheduled_response.frame = proc->frame_rx; - scheduled_response.slot = proc->nr_tti_rx; - //--------------------------Temporary configuration-----------------------------// - rnti = 0x1234; - rb_size = 50; - rb_start = 0; - nr_of_symbols = 12; - start_symbol_index = 2; - nrOfLayers = 1; - mcs_index = 9; - mcs_table = 0; - harq_process_id = 0; - rv_index = 0; - l_prime_mask = get_l_prime(nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); - dmrs_config_type = 0; - ptrs_mcs1 = 2; - ptrs_mcs2 = 4; - ptrs_mcs3 = 10; - n_rb0 = 25; - n_rb1 = 75; - pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; - ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, mcs_index, mcs_table); - ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, rb_size); - //------------------------------------------------------------------------------// + // trigger L2 to run ue_scheduler thru IF module + // [TODO] mapping right after NR initial sync + if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) { + nr_uplink_indication_t ul_indication; + memset((void*)&ul_indication, 0, sizeof(ul_indication)); - scheduled_response.ul_config->slot = 8; - scheduled_response.ul_config->number_pdus = 1; - scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rnti = rnti; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_size = rb_size; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_start = rb_start; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nr_of_symbols = nr_of_symbols; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_process_id; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t)); - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + ul_indication.module_id = UE->Mod_id; + ul_indication.gNB_index = gNB_id; + ul_indication.cc_id = UE->CC_id; + ul_indication.frame_rx = proc->frame_rx; + ul_indication.slot_rx = proc->nr_tti_rx; + ul_indication.frame_tx = proc->frame_tx; + ul_indication.slot_tx = proc->nr_tti_tx; - if (1 << ptrs_time_density >= nr_of_symbols) { - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + UE->if_inst->ul_indication(&ul_indication); } - nr_ue_scheduled_response(&scheduled_response); - if (UE->mode != loop_through_memory) { - uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx]; + uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_rx]; phy_procedures_nrUE_TX(UE,proc,0,thread_id); } } @@ -441,41 +400,26 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { - nr_dcireq_t dcireq; - nr_scheduled_response_t scheduled_response; - uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period; + fapi_nr_config_request_t *cfg = &UE->nrUE_config; + int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx); + uint8_t gNB_id = 0; - //program DCI for slot 1 - //TODO: all of this has to be moved to the MAC!!! - if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || UE->frame_parms.frame_type == FDD){ - dcireq.module_id = UE->Mod_id; - dcireq.gNB_index = 0; - dcireq.cc_id = 0; - dcireq.frame = proc->frame_rx; - dcireq.slot = proc->nr_tti_rx; - nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){ - // we should have received a DL DCI here, so configure DL accordingly - scheduled_response.dl_config = &dcireq.dl_config_req; - scheduled_response.ul_config = NULL; - scheduled_response.tx_request = NULL; - scheduled_response.module_id = UE->Mod_id; - scheduled_response.CC_id = 0; - if (!((proc->frame_rx)%(1<<(ssb_period-1)))) { - if(proc->frame_rx > dcireq.dl_config_req.sfn) - UE->frame_gap = proc->frame_rx - dcireq.dl_config_req.sfn; - if(proc->frame_rx < dcireq.dl_config_req.sfn) - UE->frame_gap = dcireq.dl_config_req.sfn - proc->frame_rx; - proc->frame_rx = dcireq.dl_config_req.sfn; + if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) { + nr_downlink_indication_t dl_indication; + memset((void*)&dl_indication, 0, sizeof(dl_indication)); + + dl_indication.module_id = UE->Mod_id; + dl_indication.gNB_index = gNB_id; + dl_indication.cc_id = UE->CC_id; + dl_indication.frame = proc->frame_rx; + dl_indication.slot = proc->nr_tti_rx; + + UE->if_inst->dl_indication(&dl_indication, NULL); } - scheduled_response.frame = proc->frame_rx; - scheduled_response.slot = proc->nr_tti_rx; - - nr_ue_scheduled_response(&scheduled_response); - } // Process Rx data for one sub-frame - if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 ) { #ifdef UE_SLOT_PARALLELISATION phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL ); #else @@ -510,6 +454,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { } } */ + } /*! @@ -526,7 +471,7 @@ typedef struct processingData_s { } processingData_t; void UE_processing(void *arg) { - processingData_t *rxtxD=(processingData_t *) arg; + processingData_t *rxtxD = (processingData_t *) arg; UE_nr_rxtx_proc_t *proc = &rxtxD->proc; PHY_VARS_NR_UE *UE = rxtxD->UE; @@ -556,9 +501,7 @@ void UE_processing(void *arg) { } processSlotRX(UE, proc); - processSlotTX(UE, proc); - } void dummyWrite(PHY_VARS_NR_UE *UE,openair0_timestamp timestamp, int writeBlockSize) { @@ -633,8 +576,9 @@ void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { } int computeSamplesShift(PHY_VARS_NR_UE *UE) { + if (IS_SOFTMODEM_RFSIM) { - LOG_E(PHY,"SET rx_offset %d \n",UE->rx_offset); + LOG_D(PHY,"SET rx_offset %d \n",UE->rx_offset); //UE->rx_offset_diff=0; return 0; } @@ -704,8 +648,11 @@ void *UE_thread(void *arg) { if (res) { syncRunning=false; syncData_t *tmp=(syncData_t *)NotifiedFifoData(res); - // shift the frame index with all the frames we trashed meanwhile we perform the synch search - decoded_frame_rx=(tmp->proc.decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER; + if (UE->is_synchronized) { + decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx); + // shift the frame index with all the frames we trashed meanwhile we perform the synch search + decoded_frame_rx=(decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER; + } delNotifiedFIFO_elt(res); } else { readFrame(UE, ×tamp, true); @@ -750,6 +697,7 @@ void *UE_thread(void *arg) { absolute_slot++; + // whatever means thread_idx // Fix me: will be wrong when slot 1 is slow, as slot 2 finishes // Slot 3 will overlap if RX_NB_TH is 2 @@ -762,13 +710,13 @@ void *UE_thread(void *arg) { curMsg->UE=UE; // update thread index for received subframe curMsg->UE->current_thread_id[slot_nr] = thread_idx; - curMsg->proc.CC_id = 0; + curMsg->proc.CC_id = UE->CC_id; curMsg->proc.nr_tti_rx= slot_nr; curMsg->proc.subframe_rx=slot_nr/(nb_slot_frame/10); curMsg->proc.nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame; curMsg->proc.subframe_tx=curMsg->proc.nr_tti_rx; - curMsg->proc.frame_rx = ((absolute_slot/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER; - curMsg->proc.frame_tx = (((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER; + curMsg->proc.frame_rx = (absolute_slot/nb_slot_frame) % MAX_FRAME_NUMBER; + curMsg->proc.frame_tx = ((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame) % MAX_FRAME_NUMBER; curMsg->proc.decoded_frame_rx=-1; //LOG_I(PHY,"Process slot %d thread Idx %d total gain %d\n", slot_nr, thread_idx, UE->rx_total_gain_dB); @@ -857,8 +805,9 @@ void *UE_thread(void *arg) { usleep(200); } - if ( decoded_frame_rx != curMsg->proc.frame_rx && - ((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx ) + if ( (decoded_frame_rx != curMsg->proc.frame_rx) && + (((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx) && + (((decoded_frame_rx+2) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx)) LOG_E(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n", decoded_frame_rx, curMsg->proc.frame_rx ); diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 9b2b704833..6d3bbc9038 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -76,36 +76,11 @@ unsigned short config_frames[4] = {2,9,11,13}; #include #include -#include - - -/* Callbacks, globals and object handlers */ - -extern void reset_stats( FL_OBJECT *, long ); -//extern void initTpool(char *params, tpool_t *pool, bool performanceMeas); - -/* Forms and Objects */ - -typedef struct { - FL_FORM *stats_form; - void *vdata; - char *cdata; - long ldata; - FL_OBJECT *stats_text; - FL_OBJECT *stats_button; -} FD_stats_form; - -extern FD_stats_form *create_form_stats_form( void ); - -#include "PHY/TOOLS/nr_phy_scope.h" //#include "stats.h" // current status is that every UE has a DL scope for a SINGLE eNB (eNB_id=0) +#include "PHY/TOOLS/nr_phy_scope.h" // at eNB 0, an UL scope for every UE -FD_phy_scope_nrue *form_nrue[NUMBER_OF_UE_MAX]; //FD_lte_phy_scope_enb *form_enb[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; -//FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; -char title[255]; -static pthread_t forms_thread; //xforms #include #include "executables/softmodem-common.h" @@ -198,6 +173,7 @@ uint64_t num_missed_slots=0; // counter for the number of missed slots int transmission_mode=1; int numerology = 0; +int usrp_tx_thread = 0; /* flag set by eNB conf file to specify if the radio head is local or remote (default option is local) */ //uint8_t local_remote_radio = BBU_LOCAL_RADIO_HEAD; @@ -274,7 +250,7 @@ void exit_function(const char *file, const char *function, const int line, const } -void reset_stats(FL_OBJECT *button, long arg) { +void reset_stats(long arg) { //int i,j,k; /*PHY_VARS_eNB *phy_vars_eNB = PHY_vars_eNB_g[0][0]; @@ -304,35 +280,6 @@ void reset_stats(FL_OBJECT *button, long arg) { }*/ } -static void *scope_thread(void *arg) { - sleep(5); - - while (!oai_exit) { - phy_scope_nrUE(form_nrue[0], - PHY_vars_UE_g[0][0], - 0,0,1); - usleep(100*1000); - } - - pthread_exit((void *)arg); -} - - -void init_scope(void) { - int fl_argc=1; - - if (do_forms==1) { - char *name="5G-UE-scope"; - fl_initialize (&fl_argc, &name, NULL, 0, 0); - int UE_id = 0; - form_nrue[UE_id] = create_phy_scope_nrue(); - sprintf (title, "NR DL SCOPE UE"); - fl_show_form (form_nrue[UE_id]->phy_scope_nrue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - threadCreate(&forms_thread, scope_thread, NULL, "scope", -1, OAI_PRIORITY_RT_LOW); - } - -} - void *l2l1_task(void *arg) { MessageDef *message_p = NULL; int result; @@ -720,6 +667,9 @@ int main( int argc, char **argv ) { PHY_vars_UE_g = malloc(sizeof(PHY_VARS_NR_UE **)); PHY_vars_UE_g[0] = malloc(sizeof(PHY_VARS_NR_UE *)*MAX_NUM_CCs); + if (get_softmodem_params()->do_ra) + AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n"); + for (int CC_id=0; CC_idofdm_symbol_size); frame_parms[CC_id]->nb_antennas_tx = nb_antenna_tx; @@ -746,11 +696,6 @@ int main( int argc, char **argv ) { init_nr_ue_vars(UE[CC_id],frame_parms[CC_id],0,abstraction_flag); - if (get_softmodem_params()->phy_test==1) - UE[CC_id]->mac_enabled = 0; - else - UE[CC_id]->mac_enabled = 1; - UE[CC_id]->mac_enabled = 1; UE[CC_id]->if_inst = nr_ue_if_module_init(0); UE[CC_id]->UE_scan = UE_scan; @@ -763,15 +708,49 @@ int main( int argc, char **argv ) { UE[CC_id]->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off; UE[CC_id]->tx_power_max_dBm = tx_max_power[CC_id]; - if (frame_parms[CC_id]->frame_type==FDD) { + if (UE[CC_id]->frame_parms.frame_type == FDD) { UE[CC_id]->N_TA_offset = 0; } else { - if (frame_parms[CC_id]->N_RB_DL == 100) - UE[CC_id]->N_TA_offset = 624; - else if (frame_parms[CC_id]->N_RB_DL == 50) - UE[CC_id]->N_TA_offset = 624/2; - else if (frame_parms[CC_id]->N_RB_DL == 25) - UE[CC_id]->N_TA_offset = 624/4; + int N_RB = UE[CC_id]->frame_parms.N_RB_DL; + int N_TA_offset = UE[CC_id]->frame_parms.ul_CarrierFreq < 6e9 ? 400 : 431; // reference samples for 25600Tc @ 30.72 Ms/s for FR1, same @ 61.44 Ms/s for FR2 + double factor=1; + switch (UE[CC_id]->frame_parms.numerology_index) { + case 0: //15 kHz scs + AssertFatal(N_TA_offset == 400, "scs_common 15kHz only for FR1\n"); + if (N_RB <= 25) factor = .25; // 7.68 Ms/s + else if (N_RB <=50) factor = .5; // 15.36 Ms/s + else if (N_RB <=75) factor = 1.0; // 30.72 Ms/s + else if (N_RB <=100) factor = 1.0; // 30.72 Ms/s + else AssertFatal(1==0,"Too many PRBS for mu=0\n"); + break; + case 1: //30 kHz sc + AssertFatal(N_TA_offset == 400, "scs_common 30kHz only for FR1\n"); + if (N_RB <= 106) factor = 2.0; // 61.44 Ms/s + else if (N_RB <= 275) factor = 4.0; // 122.88 Ms/s + break; + case 2: //60 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + break; + case 3: //120 kHz scs + AssertFatal(N_TA_offset == 431, "scs_common 120kHz only for FR2\n"); + break; + case 4: //240 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + if (N_RB <= 32) factor = 1.0; // 61.44 Ms/s + else if (N_RB <= 66) factor = 2.0; // 122.88 Ms/s + else AssertFatal(1==0,"N_RB %d is too big for curretn FR2 implementation\n",N_RB); + break; + + if (N_RB == 100) + UE[CC_id]->N_TA_offset = 624; + else if (N_RB == 50) + UE[CC_id]->N_TA_offset = 624/2; + else if (N_RB == 25) + UE[CC_id]->N_TA_offset = 624/4; + } + if (UE[CC_id]->frame_parms.threequarter_fs == 1) factor = factor*.75; + UE[CC_id]->N_TA_offset = (int)(N_TA_offset * factor); + LOG_I(PHY,"UE %d Setting N_TA_offset to %d samples (factor %f, UL Freq %lu, N_RB %d)\n", UE[CC_id]->Mod_id, UE[CC_id]->N_TA_offset, factor, UE[CC_id]->frame_parms.ul_CarrierFreq, N_RB); } } @@ -782,7 +761,8 @@ int main( int argc, char **argv ) { memset (&UE_PF_PO[0][0], 0, sizeof(UE_PF_PO_t)*NUMBER_OF_UE_MAX*MAX_NUM_CCs); configure_linux(); mlockall(MCL_CURRENT | MCL_FUTURE); - init_scope(); + if (do_forms) + nrUEinitScope(PHY_vars_UE_g[0][0]); number_of_cards = 1; for(int CC_id=0; CC_id #include "PHY/defs_nr_UE.h" #include "SIMULATION/ETH_TRANSPORT/proto.h" -#include /***************************************************************************************************************************************/ /* command line options definitions, CMDLINE_XXXX_DESC macros are used to initialize paramdef_t arrays which are then used as argument diff --git a/executables/softmodem-common.h b/executables/softmodem-common.h index 0ac7b6449e..449d2e0957 100644 --- a/executables/softmodem-common.h +++ b/executables/softmodem-common.h @@ -55,6 +55,7 @@ extern "C" #define CONFIG_HLP_DUMPFRAME "dump UE received frame to rxsig_frame0.dat and exit\n" #define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n" #define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n" +#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n" #define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n" #define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0" #define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n" @@ -97,6 +98,7 @@ extern "C" #define SPLIT73 softmodem_params.split73 #define TP_CONFIG softmodem_params.threadPoolConfig #define PHY_TEST softmodem_params.phy_test +#define DO_RA softmodem_params.do_ra #define WAIT_FOR_SYNC softmodem_params.wait_for_sync #define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag #define CHAIN_OFFSET softmodem_params.chain_offset @@ -114,6 +116,7 @@ extern "C" {"split73", CONFIG_HLP_SPLIT73, 0, strptr:(char **)&SPLIT73, defstrval:NULL, TYPE_STRING, sizeof(SPLIT73)},\ {"thread-pool", CONFIG_HLP_TPOOL, 0, strptr:(char **)&TP_CONFIG, defstrval:"n", TYPE_STRING, sizeof(TP_CONFIG)}, \ {"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \ + {"do-ra", CONFIG_HLP_DORA, PARAMFLAG_BOOL, iptr:&DO_RA, defintval:0, TYPE_INT, 0}, \ {"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \ {"clock-source", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \ {"time-source", CONFIG_HLP_TME, 0, uptr:&TIMING_SOURCE, defintval:0, TYPE_UINT, 0}, \ @@ -205,6 +208,7 @@ typedef struct { char split73[1024]; char threadPoolConfig[1024]; int phy_test; + int do_ra; uint8_t usim_test; int emulate_rf; int wait_for_sync; //eNodeB only diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h index cbcd26c3e3..e1d06335f5 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h @@ -18,6 +18,7 @@ #define FAPI_NR_RX_PDU_TYPE_SIB 0x02 #define FAPI_NR_RX_PDU_TYPE_DLSCH 0x03 #define FAPI_NR_DCI_IND 0x04 +#define FAPI_NR_RX_PDU_TYPE_RAR 0x05 #define FAPI_NR_SIBS_MASK_SIB1 0x1 @@ -42,6 +43,7 @@ #define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01 #define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02 +#define FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH 0x03 #define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01 diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 2c3809f5d4..246ab13e86 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -62,7 +62,7 @@ typedef struct { uint8_t CoreSetType; uint8_t precoder_granularity; uint16_t pdcch_dmrs_scrambling_id; - + uint16_t scrambling_rnti; uint8_t tci_state_pdcch; uint8_t tci_present_in_dci; } fapi_nr_coreset_t; @@ -158,22 +158,29 @@ typedef struct { fapi_nr_tx_request_body_t *tx_request_body; } fapi_nr_tx_request_t; - typedef struct { - uint8_t preamble_index; - uint8_t prach_configuration_index; - uint16_t preamble_length; - uint8_t power_ramping_step; - uint16_t preamble_received_target_power; - uint8_t msg1_fdm; - uint8_t msg1_frequency_start; - uint8_t zero_correlation_zone_config; - uint8_t subcarrier_spacing; - uint8_t restrictedset_config; - uint16_t root_sequence_index; - uint16_t rsrp_threshold_ssb; - uint16_t rsrp_threshold_sul; - uint16_t prach_freq_offset; - } fapi_nr_ul_config_prach_pdu; +/// This struct replaces: +/// PRACH-ConfigInfo from 38.331 RRC spec +/// PRACH-ConfigSIB or PRACH-Config +typedef struct { + /// PHY cell ID + uint16_t phys_cell_id; + /// Num PRACH occasions + uint8_t num_prach_ocas; + /// PRACH format + uint8_t prach_format; + /// Num RA + uint8_t num_ra; + uint8_t prach_start_symbol; + /// 38.211 (NCS 38.211 6.3.3.1). + uint16_t num_cs; + /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2). + uint16_t root_seq_id; + /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set. + uint8_t restricted_set; + /// see TS 38.211 (6.3.3.2). + uint16_t freq_msg1; + // nfapi_nr_ul_beamforming_t beamforming; +} fapi_nr_ul_config_prach_pdu; typedef struct { diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 54b592202d..e342ab0b67 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -86,7 +86,7 @@ typedef enum { NFAPI_NR_PHY_MSG_TYPE_CRC_INDICATION= 0X86, NFAPI_NR_PHY_MSG_TYPE_UCI_INDICATION= 0X87, NFAPI_NR_PHY_MSG_TYPE_SRS_INDICATION= 0X88, - NFAPI_NR_PHY_MSG_TYPE_PACH_INDICATION= 0X89 + NFAPI_NR_PHY_MSG_TYPE_RACH_INDICATION= 0X89 //RESERVED 0X8a ~ 0xff } nfapi_nr_phy_msg_type_e; @@ -623,22 +623,35 @@ typedef struct { //table 3-37 -#define DCI_PAYLOAD_BTYE_LEN 12 //? TS38.212 sec 7.3.1 +#define DCI_PAYLOAD_BYTE_LEN 8 // 12 ? TS38.212 sec 7.3.1 +#define MAX_DCI_CORESET 8 -typedef struct -{ - uint16_t rnti;// - uint16_t scrambling_id;// - uint16_t scrambling_rnti;/* */ - uint8_t cce_index;// - uint8_t aggregation_level;// - nfapi_nr_tx_precoding_and_beamforming_t* precoding_and_beamforming_list; - //tx power info - uint8_t beta_pdcch_1_0;/*PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of -SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */ - uint8_t power_control_offset_ss;//PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB - uint16_t payload_size_bits;//The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0-> DCI_PAYLOAD_BTYE_LEN*8 - uint8_t payload[DCI_PAYLOAD_BTYE_LEN];//DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB +typedef struct { + // The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. + uint16_t RNTI[MAX_DCI_CORESET]; + // For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, + // otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 + uint16_t ScramblingId[MAX_DCI_CORESET]; + // For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. + // Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 + uint16_t ScramblingRNTI[MAX_DCI_CORESET]; + // CCE start Index used to send the DCI Value: 0->135 + uint8_t CceIndex[MAX_DCI_CORESET]; + // Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 + uint8_t AggregationLevel[MAX_DCI_CORESET]; + // Precoding and Beamforming structure See Table 3-43 + nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; + // PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. + // This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] + // Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps + uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; + // PDCCH power value used for all other PDCCH Formats. + // This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB + uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; + // The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BYTE_LEN*8 + uint16_t PayloadSizeBits[MAX_DCI_CORESET]; + // DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB + uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; } nfapi_nr_dl_dci_pdu_t; @@ -653,9 +666,6 @@ typedef struct { uint16_t *beamIdx[275]; } nr_beamforming_t; -#define MAX_DCI_CORESET 8 -#define DCI_PAYLOAD_BYTE_LEN 8 - typedef struct { ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 uint16_t BWPSize; @@ -685,26 +695,8 @@ typedef struct { uint8_t precoderGranularity; ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot uint16_t numDlDci; - ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. - uint16_t RNTI[MAX_DCI_CORESET]; - ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 - uint16_t ScramblingId[MAX_DCI_CORESET]; - ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 - uint16_t ScramblingRNTI[MAX_DCI_CORESET]; - ///CCE start Index used to send the DCI Value: 0->135 - uint8_t CceIndex[MAX_DCI_CORESET]; - ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 - uint8_t AggregationLevel[MAX_DCI_CORESET]; - ///Precoding and Beamforming structure See Table 3-43 - nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; - ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps - uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; - ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB - uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; -///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8 - uint16_t PayloadSizeBits[MAX_DCI_CORESET]; - ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB - uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; + ///DL DCI PDU + nfapi_nr_dl_dci_pdu_t dci_pdu; } nfapi_nr_dl_tti_pdcch_pdu_rel15_t; typedef struct { @@ -1037,10 +1029,12 @@ typedef struct { uint16_t phys_cell_id; uint8_t num_prach_ocas; + // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities + // We added 9 = A1/B1 10 = A2/B2 11 A3/B3 uint8_t prach_format; uint8_t num_ra; uint8_t prach_start_symbol; - uint16_t num_cs;// + uint16_t num_cs; nfapi_nr_ul_beamforming_t beamforming; } nfapi_nr_prach_pdu_t; @@ -1126,6 +1120,7 @@ typedef struct uint16_t ul_dmrs_symb_pos; uint8_t dmrs_config_type; uint16_t ul_dmrs_scrambling_id; + uint16_t pusch_identity; uint8_t scid; uint8_t num_dmrs_cdm_grps_no_data; uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used @@ -1498,7 +1493,7 @@ typedef struct //for dci_pusch_pdu typedef struct { - uint8_t pdu_bit_map; + uint8_t pduBitmap; uint32_t handle; uint16_t rnti; uint8_t ul_cqi; @@ -1513,7 +1508,7 @@ typedef struct //for PUCCH PDU Format 0/1 typedef struct { - uint8_t pdu_bit_map; + uint8_t pduBitmap; uint32_t handle; uint16_t rnti; uint8_t pucch_format;//PUCCH format Value: 0 -> 1 0: PUCCH Format0 1: PUCCH Format1 @@ -1529,7 +1524,7 @@ typedef struct //PUCCH PDU Format 2/3/4 typedef struct { - uint8_t pdu_bit_map; + uint8_t pduBitmap; uint32_t handle; uint16_t rnti; uint8_t pucch_format;//PUCCH format Value: 0 -> 2 0: PUCCH Format2 1: PUCCH Format3 2: PUCCH Format4 @@ -1566,7 +1561,7 @@ typedef struct uint16_t sfn; uint16_t slot; uint16_t num_ucis; - nfapi_nr_uci_t uci_list[NFAPI_MAX_NUM_UCI_INDICATION]; + nfapi_nr_uci_t *uci_list; } nfapi_nr_uci_indication_t; diff --git a/nfapi/open-nFAPI/nfapi/src/nfapi.c b/nfapi/open-nFAPI/nfapi/src/nfapi.c index 156a48ec05..61c6875bc6 100644 --- a/nfapi/open-nFAPI/nfapi/src/nfapi.c +++ b/nfapi/open-nFAPI/nfapi/src/nfapi.c @@ -526,7 +526,7 @@ uint32_t pullarray8(uint8_t **in, uint8_t out[], uint32_t max_len, uint32_t len, return 0; } - if((end - out) >= sizeof(uint8_t) * len) + if((end - (*in)) >= sizeof(uint8_t) * len) { memcpy(out, (*in), len); (*in)+=len; diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index b3c9f3117c..72d85b1b14 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -27,9 +27,7 @@ #include "SIMULATION/TOOLS/sim.h" #include "PHY/CODING/nrLDPC_extern.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -// extern "C" { #include "openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h" -// } #define MAX_NUM_DLSCH_SEGMENTS 16 #define MAX_BLOCK_LENGTH 8448 @@ -105,7 +103,7 @@ int test_ldpc(short No_iteration, time_stats_t *time_optim, time_stats_t *time_decoder, n_iter_stats_t *dec_iter, - short run_cuda) + short run_cuda) { //clock initiate //time_stats_t time,time_optim,tinput,tprep,tparity,toutput, time_decoder; @@ -398,23 +396,24 @@ int test_ldpc(short No_iteration, decParams.numMaxIter=No_iteration; decParams.outMode = nrLDPC_outMode_BIT; //decParams.outMode =nrLDPC_outMode_LLRINT8; - - + set_compact_BG(Zc,BG); + init_LLR_DMA_for_CUDA(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length); for(j=0;j 1280, 2401 -> 2560 @@ -561,7 +561,7 @@ int main(int argc, char *argv[]) block_length = atoi(optarg); break; - case 'G': + case 'G': run_cuda = atoi(optarg); break; diff --git a/openair1/PHY/CODING/TESTBENCH/polartest.c b/openair1/PHY/CODING/TESTBENCH/polartest.c index 806d8de28c..d9adf3e24f 100644 --- a/openair1/PHY/CODING/TESTBENCH/polartest.c +++ b/openair1/PHY/CODING/TESTBENCH/polartest.c @@ -12,7 +12,6 @@ #include "PHY/CODING/coding_defs.h" #include "SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -//#include "PHY/NR_TRANSPORT/nr_transport.h" //#include "common/utils/LOG/log.h" //#define DEBUG_DCI_POLAR_PARAMS @@ -27,7 +26,7 @@ int main(int argc, char *argv[]) { //Default simulation values (Aim for iterations = 1000000.) int decoder_int16=0; - int itr, iterations = 1000, arguments, polarMessageType = 0; //0=PBCH, 1=DCI, -1=UCI + int itr, iterations = 1000, arguments, polarMessageType = 0; //0=PBCH, 1=DCI, 2=UCI double SNRstart = -20.0, SNRstop = 0.0, SNRinc= 0.5; //dB double SNR, SNR_lin; int16_t nBitError = 0; // -1 = Decoding failed (All list entries have failed the CRC checks). @@ -42,6 +41,7 @@ int main(int argc, char *argv[]) switch (arguments) { case 's': SNRstart = atof(optarg); + SNRstop = SNRstart + 2; break; case 'd': @@ -91,7 +91,7 @@ int main(int argc, char *argv[]) case 'k': testLength=atoi(optarg); - if (testLength < 12 || testLength > 60) { + if (testLength < 12 || testLength > 127) { printf("Illegal packet bitlength %d \n",testLength); exit(-1); } @@ -120,12 +120,13 @@ int main(int argc, char *argv[]) crcTableInit(); if (polarMessageType == 0) { //PBCH - aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL; + aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL; } else if (polarMessageType == 1) { //DCI - coderLength = 108*aggregation_level; - } else if (polarMessageType == -1) { //UCI - printf("UCI testing not supported yet\n"); - exit(-1); + coderLength = 108*aggregation_level; + } else if (polarMessageType == 2) { //UCI + //pucch2 parameters, 1 symbol, aggregation_level = NPRB + AssertFatal(aggregation_level>2,"For UCI formats, aggregation (N_RB) should be > 2\n"); + coderLength = 16*aggregation_level; } //Logging diff --git a/openair1/PHY/CODING/coding_defs.h b/openair1/PHY/CODING/coding_defs.h index 9b111309cd..7f466c7097 100644 --- a/openair1/PHY/CODING/coding_defs.h +++ b/openair1/PHY/CODING/coding_defs.h @@ -382,12 +382,24 @@ unsigned int crc16 (unsigned char * inptr, int bitlen); @param bitlen length of inputs in bits*/ unsigned int crc12 (unsigned char * inptr, int bitlen); +/*!\fn uint32_t crc12(uint8_t *inPtr, int32_t bitlen) +\brief This computes an 11-bit crc based on 3GPP NR specifications. +@param inPtr Pointer to input byte stream +@param bitlen length of inputs in bits*/ +unsigned int crc11 (unsigned char * inptr, int bitlen); + /*!\fn uint32_t crc8(uint8_t *inPtr, int32_t bitlen) \brief This computes a 8-bit crc based on 3GPP UMTS specifications. @param inPtr Pointer to input byte stream @param bitlen length of inputs in bits*/ unsigned int crc8 (unsigned char * inptr, int bitlen); +/*!\fn uint32_t crc8(uint8_t *inPtr, int32_t bitlen) +\brief This computes a 6-bit crc based on 3GPP NR specifications. +@param inPtr Pointer to input byte stream +@param bitlen length of inputs in bits*/ +unsigned int crc6 (unsigned char * inptr, int bitlen); + int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type); /*!\fn void phy_viterbi_dot11_sse2(int8_t *y, uint8_t *decoded_bytes, uint16_t n,int offset,int traceback) @@ -463,6 +475,7 @@ uint32_t nr_compute_tbs(uint16_t Qm, uint16_t nb_symb_sch, uint16_t nb_dmrs_prb, uint16_t nb_rb_oh, + uint8_t tb_scaling, uint8_t Nl); uint32_t nr_compute_tbslbrm(uint16_t table, diff --git a/openair1/PHY/CODING/crc_byte.c b/openair1/PHY/CODING/crc_byte.c index ee5c302adb..555f314429 100644 --- a/openair1/PHY/CODING/crc_byte.c +++ b/openair1/PHY/CODING/crc_byte.c @@ -90,7 +90,9 @@ static unsigned int crc24bTable[256]; static unsigned int crc24cTable[256]; static unsigned short crc16Table[256]; static unsigned short crc12Table[256]; +static unsigned short crc11Table[256]; static unsigned char crc8Table[256]; +static unsigned char crc6Table[256]; void crcTableInit (void) { @@ -102,7 +104,9 @@ void crcTableInit (void) crc24cTable[c] = crcbit (&c, 1, poly24c); crc16Table[c] = (unsigned short) (crcbit (&c, 1, poly16) >> 16); crc12Table[c] = (unsigned short) (crcbit (&c, 1, poly12) >> 16); + crc11Table[c] = (unsigned short) (crcbit (&c, 1, poly11) >> 16); crc8Table[c] = (unsigned char) (crcbit (&c, 1, poly8) >> 24); + crc6Table[c] = (unsigned char) (crcbit (&c, 1, poly6) >> 24); } while (++c); } @@ -207,6 +211,24 @@ crc12 (unsigned char * inptr, int bitlen) return crc; } +unsigned int +crc11 (unsigned char * inptr, int bitlen) +{ + int octetlen, resbit; + unsigned int crc = 0; + octetlen = bitlen / 8; /* Change in octets */ + resbit = (bitlen % 8); + + while (octetlen-- > 0) { + crc = (crc << 8) ^ (crc11Table[(*inptr++) ^ (crc >> 24)] << 16); + } + + if (resbit > 0) + crc = (crc << resbit) ^ (crc11Table[((*inptr) >> (8 - resbit)) ^ (crc >> (32 - resbit))] << 16); + + return crc; +} + unsigned int crc8 (unsigned char * inptr, int bitlen) { @@ -225,6 +247,24 @@ crc8 (unsigned char * inptr, int bitlen) return crc; } +unsigned int +crc6 (unsigned char * inptr, int bitlen) +{ + int octetlen, resbit; + unsigned int crc = 0; + octetlen = bitlen / 8; /* Change in octets */ + resbit = (bitlen % 8); + + while (octetlen-- > 0) { + crc = crc6Table[(*inptr++) ^ (crc >> 24)] << 24; + } + + if (resbit > 0) + crc = (crc << resbit) ^ (crc8Table[((*inptr) >> (8 - resbit)) ^ (crc >> (32 - resbit))] << 24); + + return crc; +} + int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type) { uint32_t crc=0,oldcrc=0; @@ -284,6 +324,7 @@ int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type) AssertFatal(1,"Invalid crc_type \n"); } + if (crc == oldcrc) return(1); else diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu index 68ca2f450f..931d500338 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu @@ -12,8 +12,8 @@ #include #include #include -#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h" -#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h" +#include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" +#include "PHY/CODING/nrLDPC_decoder/nrLDPCdecoder_defs.h" #include "bgs/BG1_I0" #include "bgs/BG1_I1" @@ -32,7 +32,7 @@ #include "bgs/BG2_I6" #include "bgs/BG2_I7" -#define MAX_ITERATION 5 +#define MAX_ITERATION 2 #define MC 1 #define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } @@ -49,13 +49,21 @@ typedef struct{ char y; short value; } h_element; +#include "bgs/BG1_compact_in_C.h" +__device__ char dev_const_llr[68*384]; +__device__ char dev_dt [46*68*384]; +__device__ char dev_llr[68*384]; +__device__ unsigned char dev_tmp[68*384]; h_element h_compact1 [46*19] = {}; h_element h_compact2 [68*30] = {}; -__device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 -__device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 +__device__ h_element dev_h_compact1[46*19]; // used in kernel 1 +__device__ h_element dev_h_compact2[68*30]; // used in kernel 2 + +// __device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 +// __device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 // row and col element count __device__ __constant__ char h_ele_row_bg1_count[46] = { @@ -92,9 +100,93 @@ __global__ void warmup() // warm up gpu for time measurement } +extern "C" +void warmup_for_GPU(){ + + warmup<<<20,1024 >>>(); + +} + +extern "C" +void set_compact_BG(int Zc,short BG){ + + int row,col; + if(BG == 1){ + row = 46; + col = 68; + } + else{ + row = 42; + col = 52; + } + int compact_row = 30; + int compact_col = 19; + if(BG==2){compact_row = 10, compact_col = 23;} + int memorySize_h_compact1 = row * compact_col * sizeof(h_element); + int memorySize_h_compact2 = compact_row * col * sizeof(h_element); + int lift_index = 0; + short lift_set[][9] = { + {2,4,8,16,32,64,128,256}, + {3,6,12,24,48,96,192,384}, + {5,10,20,40,80,160,320}, + {7,14,28,56,112,224}, + {9,18,36,72,144,288}, + {11,22,44,88,176,352}, + {13,26,52,104,208}, + {15,30,60,120,240}, + {0} + }; + + for(int i = 0; lift_set[i][0] != 0; i++){ + for(int j = 0; lift_set[i][j] != 0; j++){ + if(Zc == lift_set[i][j]){ + lift_index = i; + break; + } + } + } + printf("\nZc = %d BG = %d\n",Zc,BG); + switch(lift_index){ + case 0: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I0, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I0, memorySize_h_compact2) ); + break; + case 1: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I1, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I1, memorySize_h_compact2) ); + break; + case 2: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I2, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I2, memorySize_h_compact2) ); + break; + case 3: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I3, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I3, memorySize_h_compact2) ); + break; + case 4: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I4, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I4, memorySize_h_compact2) ); + break; + case 5: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I5, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I5, memorySize_h_compact2) ); + break; + case 6: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I6, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I6, memorySize_h_compact2) ); + break; + case 7: + cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I7, memorySize_h_compact1) ); + cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I7, memorySize_h_compact2) ); + break; + } + + // return 0; +} + // Kernel 1 -__global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) +__global__ void ldpc_cnp_kernel_1st_iter(/*char * dev_llr,*/ int BG, int row, int col, int Zc) { // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp %d\n", threadIdx.x); int iMCW = blockIdx.y; // codeword id @@ -153,7 +245,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, for(int i = 0; i < s; i++){ // v0: Best performance so far. 0.75f is the value of alpha. sq = 1 - 2 * ((Q_sign >> i) & 0x01); - R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); + R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); // write results to global memory h_element_t = dev_h_compact1[i*row+iBlkRow]; int addr_temp = offsetR + h_element_t.y * row * Zc; @@ -163,7 +255,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, } // Kernel_1 -__global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) +__global__ void ldpc_cnp_kernel(/*char * dev_llr, char * dev_dt,*/ int BG, int row, int col, int Zc) { // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp\n"); int iMCW = blockIdx.y; @@ -223,7 +315,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, // The 2nd recursion for(int i = 0; i < s; i ++){ sq = 1 - 2 * ((Q_sign >> i) & 0x01); - R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); + R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); // write results to global memory @@ -236,7 +328,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, // Kernel 2: VNP processing __global__ void -ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int BG, int row, int col, int Zc) +ldpc_vnp_kernel_normal(/*char * dev_llr, char * dev_dt, char * dev_const_llr,*/ int BG, int row, int col, int Zc) { int iMCW = blockIdx.y; int iBlkCol = blockIdx.x; @@ -276,7 +368,7 @@ ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int } -__global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc) +__global__ void pack_decoded_bit(/*char *dev, unsigned char *host,*/ int col, int Zc) { __shared__ unsigned char tmp[128]; int iMCW = blockIdx.y; @@ -284,15 +376,15 @@ __global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc int btid = threadIdx.x; tmp[btid] = 0; - if(dev[tid] < 0){ + if(dev_llr[tid] < 0){ tmp[btid] = 1 << (7-(btid&7)); } __syncthreads(); if(threadIdx.x < 16){ - host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; + dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; for(int i = 0; i < 8; i++){ - host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; + dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; } } } @@ -369,18 +461,11 @@ void read_BG(int BG, int *h, int row, int col) */ } - extern "C" -int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder) -{ - // alloc mem - //unsigned char *decision = (unsigned char*)p_out; - - uint16_t Zc = p_decParams->Z; - uint8_t BG = p_decParams->BG; - uint8_t numMaxIter = p_decParams->numMaxIter; - e_nrLDPC_outMode outMode = p_decParams->outMode; +void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length){ + uint16_t Zc = p_decParams->Z; + uint8_t BG = p_decParams->BG; uint8_t row,col; if(BG == 1){ row = 46; @@ -390,96 +475,41 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8 row = 42; col = 52; } - int compact_row = 30, compact_col = 19, lift_index=0;; - if(BG==2){compact_row = 10, compact_col = 23;} + unsigned char *hard_decision = (unsigned char*)p_out; + int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; + cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); + cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); + cudaDeviceSynchronize(); - short lift_set[][9] = { - {2,4,8,16,32,64,128,256}, - {3,6,12,24,48,96,192,384}, - {5,10,20,40,80,160,320}, - {7,14,28,56,112,224}, - {9,18,36,72,144,288}, - {11,22,44,88,176,352}, - {13,26,52,104,208}, - {15,30,60,120,240}, - {0} - }; - - for(int i = 0; lift_set[i][0] != 0; i++){ - for(int j = 0; lift_set[i][j] != 0; j++){ - if(Zc == lift_set[i][j]){ - lift_index = i; - break; - } - } +} + +extern "C" +int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder) +{ + + + uint16_t Zc = p_decParams->Z; + uint8_t BG = p_decParams->BG; + uint8_t numMaxIter = p_decParams->numMaxIter; + e_nrLDPC_outMode outMode = p_decParams->outMode; + cudaError_t cudaStatus; + uint8_t row,col; + if(BG == 1){ + row = 46; + col = 68; } - - int *h = NULL; - switch(lift_index){ - case 0: - h = (BG == 1)? h_base_0:h_base_8; - break; - case 1: - h = (BG == 1)? h_base_1:h_base_9; - break; - case 2: - h = (BG == 1)? h_base_2:h_base_10; - break; - case 3: - h = (BG == 1)? h_base_3:h_base_11; - break; - case 4: - h = (BG == 1)? h_base_4:h_base_12; - break; - case 5: - h = (BG == 1)? h_base_5:h_base_13; - break; - case 6: - h = (BG == 1)? h_base_6:h_base_14; - break; - case 7: - h = (BG == 1)? h_base_7:h_base_15; - break; + else{ + row = 42; + col = 52; } - /* pack BG in compact graph */ - read_BG(BG, h, row, col); - - - int memorySize_h_compact1 = row * compact_col * sizeof(h_element); - int memorySize_h_compact2 = compact_row * col * sizeof(h_element); -// cpu - int memorySize_hard_decision = col * Zc * sizeof(unsigned char) * MC; - - // alloc memory unsigned char *hard_decision = (unsigned char*)p_out; - // gpu int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; - int memorySize_dt_cuda = row * Zc * col * sizeof(char) * MC; - - -// alloc memory - char *dev_llr; - char *dev_dt; - char *dev_const_llr; - unsigned char *dev_tmp; + cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); + cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); - cudaCheck( cudaMalloc((void **)&dev_tmp, memorySize_hard_decision) ); - cudaCheck( cudaMalloc((void **)&dev_llr, memorySize_llr_cuda) ); - cudaCheck( cudaMalloc((void **)&dev_const_llr, memorySize_llr_cuda) ); - cudaCheck( cudaMalloc((void **)&dev_dt, memorySize_dt_cuda) ); - -// memcpy host to device - - cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, h_compact1, memorySize_h_compact1) ); - cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, h_compact2, memorySize_h_compact2) ); - cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); -start_meas(time_decoder); - cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); - - // Define CUDA kernel dimension int blockSizeX = Zc; dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks @@ -488,61 +518,35 @@ start_meas(time_decoder); dim3 dimGridKernel2(col, MC, 1); dim3 dimBlockKernel2(blockSizeX, 1, 1); cudaDeviceSynchronize(); - - cudaEvent_t start, end; - float time; - warmup<<>>(); - warmup<<>>(); - - - cudaEventCreate(&start); - cudaEventCreate(&end); - cudaEventRecord(start, 0); - -// cudaProfilerStart(); - // lauch kernel + for(int ii = 0; ii < MAX_ITERATION; ii++){ // first kernel if(ii == 0){ ldpc_cnp_kernel_1st_iter <<>> - (dev_llr, dev_dt, BG, row, col, Zc); + (/*dev_llr,*/ BG, row, col, Zc); }else{ ldpc_cnp_kernel <<>> - (dev_llr, dev_dt, BG, row, col, Zc); + (/*dev_llr,*/ BG, row, col, Zc); } - // second kernel - - ldpc_vnp_kernel_normal - <<>> - (dev_llr, dev_dt, dev_const_llr, BG, row, col, Zc); - + ldpc_vnp_kernel_normal + <<>> + // (dev_llr, dev_const_llr,BG, row, col, Zc); + (BG, row, col, Zc); } + int pack = (block_length/128)+1; dim3 pack_block(pack, MC, 1); - pack_decoded_bit<<>>(dev_llr, dev_tmp, col, Zc); - - - cudaEventRecord(end, 0); - cudaEventSynchronize(end); - cudaEventElapsedTime(&time, start, end); + pack_decoded_bit<<>>(/*dev_llr,*/ /*dev_tmp,*/ col, Zc); - - //cudaCheck( cudaMemcpy((*)hard_decision, (const void*)dev_tmp, memorySize_hard_decision, cudaMemcpyDeviceToHost) ); - cudaCheck( cudaMemcpy((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char), cudaMemcpyDeviceToHost) ); + cudaCheck( cudaMemcpyFromSymbol((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char)) ); cudaDeviceSynchronize(); -stop_meas(time_decoder); - cudaCheck( cudaFree(dev_llr) ); - cudaCheck( cudaFree(dev_dt) ); - cudaCheck( cudaFree(dev_const_llr) ); - cudaCheck( cudaFree(dev_tmp) ); - - //free(hard_decision); + return MAX_ITERATION; } diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h index e74f42b3d3..c8868f0a85 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h @@ -1,8 +1,6 @@ #ifndef __NR_LDPC_DECODER_LYC__H__ #define __NR_LDPC_DECODER_LYC__H__ -#include "nrLDPC_types.h" -#include "nrLDPC_init_mem.h" /*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h * \brief LDPC cuda support BG1 all length @@ -25,4 +23,10 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder); +void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length); + +void warmup_for_GPU(void); + +void set_compact_BG(int Zc, short BG); + #endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h deleted file mode 100644 index 9c64c262b9..0000000000 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - - /*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h - * \brief LDPC cuda support BG1 all length - * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN - * \email tyhsu@cs.nctu.edu.tw - * \date 13-05-2020 - * \version - * \note - * \warning - */ - - -/*!\file nrLDPC_defs.h - * \brief Defines all constants and buffers for the LDPC decoder - * \author Sebastian Wagner (TCL Communications) Email: - * \date 27-03-2018 - * \version 1.0 - * \note - * \warning -* */ - -#ifndef __NR_LDPC_DEFS__H__ -#define __NR_LDPC_DEFS__H__ - -// ============================================================================== -// DEFINES - -/** Maximum lifting size */ -#define NR_LDPC_ZMAX 384 - -/** Number of columns in BG1 */ -#define NR_LDPC_NCOL_BG1 68 -/** Number of rows in BG1 */ -#define NR_LDPC_NROW_BG1 46 -/** Number of edges/entries in BG1 */ -#define NR_LDPC_NUM_EDGE_BG1 316 -/** Number of check node (CN) groups in BG1 - A CN group is defined by its number of connected bit nodes. */ -#define NR_LDPC_NUM_CN_GROUPS_BG1 9 -/** First column in BG1 that is connected to only a single CN */ -#define NR_LDPC_START_COL_PARITY_BG1 26 - -/** Number of columns in BG1 for rate 1/3 = 22/(68-2) */ -#define NR_LDPC_NCOL_BG1_R13 NR_LDPC_NCOL_BG1 -/** Number of columns in BG1 for rate 2/3 = 22/(35-2) */ -#define NR_LDPC_NCOL_BG1_R23 35 -/** Number of columns in BG1 for rate 8/9 ~ 22/(27-2) */ -#define NR_LDPC_NCOL_BG1_R89 27 - -/** Number of bit node (BN) groups in BG1 for rate 1/3 - A BN group is defined by its number of connected CNs. */ -#define NR_LDPC_NUM_BN_GROUPS_BG1_R13 30 -/** Number of bit node (BN) groups in BG1 for rate 2/3 */ -#define NR_LDPC_NUM_BN_GROUPS_BG1_R23 8 -/** Number of bit node (BN) groups in BG1 for rate 8/9 */ -#define NR_LDPC_NUM_BN_GROUPS_BG1_R89 5 - -/** Number of columns in BG2 */ -#define NR_LDPC_NCOL_BG2 52 -/** Number of rows in BG2 */ -#define NR_LDPC_NROW_BG2 42 -/** Number of edges/entries in BG2 */ -#define NR_LDPC_NUM_EDGE_BG2 197 -/** Number of check node (CN) groups in BG2 - A CN group is defined by its number of connected bit nodes. */ -#define NR_LDPC_NUM_CN_GROUPS_BG2 6 -/** First column in BG2 that is connected to only a single CN */ -#define NR_LDPC_START_COL_PARITY_BG2 14 - -/** Number of columns in BG2 for rate 1/5 = 10/(52-2) */ -#define NR_LDPC_NCOL_BG2_R15 NR_LDPC_NCOL_BG2 -/** Number of columns in BG2 for rate 1/3 = 10/(32-2) */ -#define NR_LDPC_NCOL_BG2_R13 32 -/** Number of columns in BG2 for rate 2/3 = 10/(17-2) */ -#define NR_LDPC_NCOL_BG2_R23 17 - -/** Number of bit node (BN) groups in BG2 for rate 1/5 - A BN group is defined by its number of connected CNs. */ -#define NR_LDPC_NUM_BN_GROUPS_BG2_R15 23 -/** Number of bit node (BN) groups in BG2 for rate 1/3 */ -#define NR_LDPC_NUM_BN_GROUPS_BG2_R13 10 -/** Number of bit node (BN) groups in BG2 for rate 2/3 */ -#define NR_LDPC_NUM_BN_GROUPS_BG2_R23 6 - -/** Worst case size of the CN processing buffer */ -#define NR_LDPC_SIZE_CN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX -/** Worst case size of the BN processing buffer */ -#define NR_LDPC_SIZE_BN_PROC_BUF NR_LDPC_NUM_EDGE_BG1*NR_LDPC_ZMAX - -/** Maximum number of possible input LLR = NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX */ -#define NR_LDPC_MAX_NUM_LLR 26112 - -// ============================================================================== -// GLOBAL CONSTANT VARIABLES - -/** Start addresses for the cnProcBuf for each CN group in BG1*/ -static const uint32_t lut_startAddrCnGroups_BG1[NR_LDPC_NUM_CN_GROUPS_BG1] = {0, 1152, 8832, 43392, 61824, 75264, 81408, 88320, 92160}; -/** Start addresses for the cnProcBuf for each CN group in BG2*/ -static const uint32_t lut_startAddrCnGroups_BG2[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 6912, 37632, 54912, 61824, 67968}; - -/** Number of BNs of CN group for BG1. - E.g. 10 means that there is a CN group where every CN is connected to 10 BNs */ -static const uint8_t lut_numBnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {3, 4, 5, 6, 7, 8, 9, 10, 19}; -/** Number of rows/CNs in every CN group for rate = 1/3 BG1, e.g. 5 rows of CNs connected to 4 BNs */ -static const uint8_t lut_numCnInCnGroups_BG1_R13[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 5, 18, 8, 5, 2, 2, 1, 4}; -/** Number of rows/CNs in every CN group for rate = 2/3 BG1, e.g. 3 rows of CNs connected to 7 BNs */ -static const uint8_t lut_numCnInCnGroups_BG1_R23[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 3, 2, 2, 1, 4}; -/** Number of rows/CNs in every CN group for rate = 8/9 BG1, e.g. 4 rows of CNs connected to 19 BNs */ -static const uint8_t lut_numCnInCnGroups_BG1_R89[NR_LDPC_NUM_CN_GROUPS_BG1] = {1, 0, 0, 0, 0, 0, 0, 0, 4}; - -/** Number of connected BNs for every column in BG1 rate = 1/3, e.g. in first column all BNs are connected to 30 CNs */ -static const uint8_t lut_numEdgesPerBn_BG1_R13[NR_LDPC_START_COL_PARITY_BG1] = {30, 28, 7, 11, 9, 4, 8, 12, 8, 7, 12, 10, 12, 11, 10, 7, 10, 10, 13, 7, 8, 11, 12, 5, 6, 6}; -/** Number of connected BNs for every column in BG1 rate = 2/3, e.g. in first column all BNs are connected to 12 CNs */ -static const uint8_t lut_numEdgesPerBn_BG1_R23[NR_LDPC_START_COL_PARITY_BG1] = {12, 11, 4, 5, 5, 3, 4, 5, 5, 3, 6, 6, 6, 6, 5, 3, 6, 5, 6, 4, 5, 6, 6, 3, 3, 2}; -/** Number of connected BNs for every column in BG1 rate = 8/9, e.g. in first column all BNs are connected to 5 CNs */ -static const uint8_t lut_numEdgesPerBn_BG1_R89[NR_LDPC_START_COL_PARITY_BG1] = {5, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2}; - -/** Number of BNs of CN group for BG2. - E.g. 3 means that there is a CN group where every CN is connected to 3 BNs */ -static const uint8_t lut_numBnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {3, 4, 5, 6, 8, 10}; -/** Number of rows/CNs in every CN group for rate = 1/5 BG2, e.g. 6 rows of CNs connected to 3 BNs */ -static const uint8_t lut_numCnInCnGroups_BG2_R15[NR_LDPC_NUM_CN_GROUPS_BG2] = {6, 20, 9, 3, 2, 2}; -/** Number of rows/CNs in every CN group for rate = 1/3 BG2, e.g. 8 rows of CNs connected to 4 BNs */ -static const uint8_t lut_numCnInCnGroups_BG2_R13[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 8, 7, 3, 2, 2}; -/** Number of rows/CNs in every CN group for rate = 2/3 BG2, e.g. 1 row of CNs connected to 4 BNs */ -static const uint8_t lut_numCnInCnGroups_BG2_R23[NR_LDPC_NUM_CN_GROUPS_BG2] = {0, 1, 0, 2, 2, 2}; - -/** Number of connected BNs for every column in BG2 rate = 1/5, e.g. in first column all BNs are connected to 22 CNs */ -static const uint8_t lut_numEdgesPerBn_BG2_R15[NR_LDPC_START_COL_PARITY_BG2] = {22, 23, 10, 5, 5, 14, 7, 13, 6, 8, 9, 16, 9, 12}; -/** Number of connected BNs for every column in BG2 rate = 1/3, e.g. in first column all BNs are connected to 14 CNs */ -static const uint8_t lut_numEdgesPerBn_BG2_R13[NR_LDPC_START_COL_PARITY_BG2] = {14, 16, 2, 4, 4, 6, 6, 8, 6, 6, 6, 13, 5, 7}; -/** Number of connected BNs for every column in BG2 rate = 2/3, e.g. in first column all BNs are connected to 6 CNs */ -static const uint8_t lut_numEdgesPerBn_BG2_R23[NR_LDPC_START_COL_PARITY_BG2] = { 6, 5, 2, 3, 3, 4, 3, 4, 3, 4, 3, 5, 2, 2}; - -// Number of groups for bit node processing -/** Number of connected CNs for every column/BN in BG1 for rate = 1/3, Worst case is BG1 with up to 30 CNs connected to one BN - E.g. 42 parity BNs connected to single CN */ - // BG1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 -static const uint8_t lut_numBnInBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {42, 0, 0, 1, 1, 2, 4, 3, 1, 4, 3, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}; -/** Number of connected CNs for every column/BN in BG1 for rate = 2/3 */ -static const uint8_t lut_numBnInBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 9, 1, 5, 3, 7, 8, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -/** Number of connected CNs for every column/BN in BG1 for rate = 8/9 */ -static const uint8_t lut_numBnInBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 1, 3,21, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -/** Number of connected CNs for every column/BN in BG2 for rate = 1/5, Worst case is BG1 with up to 30 CNs connected to one BN - E.g. 38 parity BNs connected to single CN */ - // BG2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 -static const uint8_t lut_numBnInBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {38, 0, 0, 0, 2, 1, 1, 1, 2, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0}; -/** Number of connected CNs for every column/BN in BG2 for rate = 1/3 */ -static const uint8_t lut_numBnInBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {18, 1, 0, 2, 1, 5, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -/** Number of connected CNs for every column/BN in BG2 for rate = 2/3 */ -static const uint8_t lut_numBnInBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = { 3, 3, 5, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -// Start addresses for the bnProcBuf for each BN group -// BG1 -/** Start address for every BN group within the BN processing buffer for BG1 rate = 1/3 */ -static const uint32_t lut_startAddrBnGroups_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 17664, 19584, 24192, 34944, 44160, 47616, 62976, 75648, 94080, 99072, 109824}; -/** Start address for every BN group within the BN processing buffer for BG1 rate = 2/3 */ -static const uint32_t lut_startAddrBnGroups_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 4224, 9984, 14592, 28032, 46464, 50688}; -/** Start address for every BN group within the BN processing buffer for BG1 rate = 8/9 */ -static const uint32_t lut_startAddrBnGroups_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 2688, 26880, 28416}; - -/** Start address for every BN group within the LLR processing buffer for BG1 rate = 1/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG1_R13[NR_LDPC_NUM_BN_GROUPS_BG1_R13] = {0, 16128, 16512, 16896, 17664, 19200, 20352, 20736, 22272, 23424, 24960, 25344, 25728}; -/** Start address for every BN group within the LLR processing buffer for BG1 rate = 2/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG1_R23[NR_LDPC_NUM_BN_GROUPS_BG1_R23] = {0, 3456, 3840, 5760, 6912, 9600, 12672, 13056}; -/** Start address for every BN group within the LLR processing buffer for BG1 rate = 8/9 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG1_R89[NR_LDPC_NUM_BN_GROUPS_BG1_R89] = {0, 384, 1536, 9600, 9984}; - -// BG2 -/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/5 */ -static const uint32_t lut_startAddrBnGroups_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 18432, 20736, 23424, 26496, 33408, 37248, 41856, 46848, 52224, 58368, 66816}; -/** Start address for every BN group within the BN processing buffer for BG2 rate = 1/3 */ -static const uint32_t lut_startAddrBnGroups_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7680, 10752, 12672, 24192, 26880, 29952, 34944, 40320}; -/** Start address for every BN group within the BN processing buffer for BG2 rate = 2/3 */ -static const uint32_t lut_startAddrBnGroups_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 3456, 9216, 13824, 17664}; - -/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/5 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG2_R15[NR_LDPC_NUM_BN_GROUPS_BG2_R15] = {0, 14592, 15360, 15744, 16128, 16512, 17280, 17664, 18048, 18432, 18816, 19200, 19584}; -/** Start address for every BN group within the LLR processing buffer for BG2 rate = 1/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG2_R13[NR_LDPC_NUM_BN_GROUPS_BG2_R13] = {0, 6912, 7296, 8064, 8448, 10368, 10752, 11136, 11520, 11904}; -/** Start address for every BN group within the LLR processing buffer for BG2 rate = 2/3 */ -static const uint16_t lut_startAddrBnGroupsLlr_BG2_R23[NR_LDPC_NUM_BN_GROUPS_BG2_R23] = {0, 1152, 2304, 4224, 5376, 6144}; - -/** Vector of 32 '1' in int8 for application with AVX2 */ -static const int8_t ones256_epi8[32] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; -/** Vector of 32 '0' in int8 for application with AVX2 */ -static const int8_t zeros256_epi8[32] __attribute__ ((aligned(32))) = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; -/** Vector of 32 '127' in int8 for application with AVX2 */ -static const int8_t maxLLR256_epi8[32] __attribute__ ((aligned(32))) = {127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127}; - -#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h deleted file mode 100644 index bdaa118e1f..0000000000 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_init_mem.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*!\file nrLDPC_init_mem.h - * \brief Defines the function to initialize the LDPC decoder and sets correct LUTs. - * \author Sebastian Wagner (TCL Communications) Email: - * \date 07-12-2018 - * \version 1.0 - * \note - * \warning - */ - -#ifndef __NR_LDPC_INIT_MEM__H__ -#define __NR_LDPC_INIT_MEM__H__ - -#include -#include "nrLDPC_defs.h" -#include "nrLDPC_types.h" - -#ifndef malloc32_clear -/** - \brief Allocates 32 byte aligned memory and initializes to zero - \param size Input size in bytes - \return Pointer to memory -*/ -static inline void* malloc32_clear(size_t size) -{ - void* ptr = (void*) memalign(32, size+32); - memset(ptr, 0, size); - return ptr; -} -#endif - -/** - \brief Allocates and initializes the internal decoder processing buffers - \param p_decParams Pointer to decoder parameters - \param p_lut Pointer to decoder LUTs - \return Number of LLR values -*/ -static inline t_nrLDPC_procBuf* nrLDPC_init_mem(void) -{ - t_nrLDPC_procBuf* p_procBuf = (t_nrLDPC_procBuf*) malloc32_clear(sizeof(t_nrLDPC_procBuf)); - - if (p_procBuf) - { - p_procBuf->cnProcBuf = (int8_t*) malloc32_clear(NR_LDPC_SIZE_CN_PROC_BUF*sizeof(int8_t)); - p_procBuf->cnProcBufRes = (int8_t*) malloc32_clear(NR_LDPC_SIZE_CN_PROC_BUF*sizeof(int8_t)); - p_procBuf->bnProcBuf = (int8_t*) malloc32_clear(NR_LDPC_SIZE_BN_PROC_BUF*sizeof(int8_t)); - p_procBuf->bnProcBufRes = (int8_t*) malloc32_clear(NR_LDPC_SIZE_BN_PROC_BUF*sizeof(int8_t)); - p_procBuf->llrRes = (int8_t*) malloc32_clear(NR_LDPC_MAX_NUM_LLR *sizeof(int8_t)); - p_procBuf->llrProcBuf = (int8_t*) malloc32_clear(NR_LDPC_MAX_NUM_LLR *sizeof(int8_t)); - } - - return(p_procBuf); -} - -static inline void nrLDPC_free_mem(t_nrLDPC_procBuf* p_procBuf) -{ - free(p_procBuf->cnProcBuf); - free(p_procBuf->cnProcBufRes); - free(p_procBuf->bnProcBuf); - free(p_procBuf->bnProcBufRes); - free(p_procBuf->llrRes); - free(p_procBuf->llrProcBuf); - - free(p_procBuf); -} -#endif diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h deleted file mode 100644 index 34322a7780..0000000000 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*!\file nrLDPC_types.h - * \brief Defines all types for the LDPC decoder - * \author Sebastian Wagner (TCL Communications) Email: - * \date 27-03-2018 - * \version 1.0 - * \note - * \warning - */ - -#ifndef __NR_LDPC_TYPES__H__ -#define __NR_LDPC_TYPES__H__ - -#include "PHY/TOOLS/time_meas.h" -#include "nrLDPC_defs.h" - -// ============================================================================== -// TYPES - -/** - Structure containing the pointers to the LUTs. - */ -typedef struct nrLDPC_lut { - const uint32_t* startAddrCnGroups; /**< Start addresses for CN groups in CN processing buffer */ - const uint8_t* numCnInCnGroups; /**< Number of CNs in every CN group */ - const uint8_t* numBnInBnGroups; /**< Number of CNs in every BN group */ - const uint32_t* startAddrBnGroups; /**< Start addresses for BN groups in BN processing buffer */ - const uint16_t* startAddrBnGroupsLlr; /**< Start addresses for BN groups in LLR processing buffer */ - const uint16_t** circShift[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT for circular shift values for all CN groups and Zs */ - const uint32_t** startAddrBnProcBuf[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT of start addresses of CN groups in BN proc buffer */ - const uint8_t** bnPosBnProcBuf[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT of BN positions in BG for CN groups */ - const uint16_t* llr2llrProcBufAddr; /**< LUT for transferring input LLRs to LLR processing buffer */ - const uint8_t* llr2llrProcBufBnPos; /**< LUT BN position in BG */ - const uint8_t** posBnInCnProcBuf[NR_LDPC_NUM_CN_GROUPS_BG1]; /**< LUT for llr2cnProcBuf */ -} t_nrLDPC_lut; - -/** - Enum with possible LDPC output formats. - */ -typedef enum nrLDPC_outMode { - nrLDPC_outMode_BIT, /**< 32 bits per uint32_t output */ - nrLDPC_outMode_BITINT8, /**< 1 bit per int8_t output */ - nrLDPC_outMode_LLRINT8 /**< Single LLR value per int8_t output */ -} e_nrLDPC_outMode; - -/** - Structure containing LDPC decoder parameters. - */ -typedef struct nrLDPC_dec_params { - uint8_t BG; /**< Base graph */ - uint16_t Z; /**< Lifting size */ - uint8_t R; /**< Decoding rate: Format 15,13,... for code rates 1/5, 1/3,... */ - uint8_t numMaxIter; /**< Maximum number of iterations */ - e_nrLDPC_outMode outMode; /**< Output format */ -} t_nrLDPC_dec_params; - -/** - Structure containing LDPC decoder processing time statistics. - */ -typedef struct nrLDPC_time_stats { - time_stats_t llr2llrProcBuf; /**< Statistics for function llr2llrProcBuf */ - time_stats_t llr2CnProcBuf; /**< Statistics for function llr2CnProcBuf */ - time_stats_t cnProc; /**< Statistics for function cnProc */ - time_stats_t cnProcPc; /**< Statistics for function cnProcPc */ - time_stats_t bnProcPc; /**< Statistics for function bnProcPc */ - time_stats_t bnProc; /**< Statistics for function bnProc */ - time_stats_t cn2bnProcBuf; /**< Statistics for function cn2bnProcBuf */ - time_stats_t bn2cnProcBuf; /**< Statistics for function bn2cnProcBuf */ - time_stats_t llrRes2llrOut; /**< Statistics for function llrRes2llrOut */ - time_stats_t llr2bit; /**< Statistics for function llr2bit */ - time_stats_t total; /**< Statistics for total processing time */ -} t_nrLDPC_time_stats; - -/** - Structure containing the processing buffers - */ -typedef struct nrLDPC_procBuf { - int8_t* cnProcBuf; /**< CN processing buffer */ - int8_t* cnProcBufRes; /**< Buffer for CN processing results */ - int8_t* bnProcBuf; /**< BN processing buffer */ - int8_t* bnProcBufRes; /**< Buffer for BN processing results */ - int8_t* llrRes; /**< Buffer for LLR results */ - int8_t* llrProcBuf; /**< LLR processing buffer */ -} t_nrLDPC_procBuf; - -#endif diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c index 53119a1c2b..18db8a01fb 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c @@ -569,7 +569,7 @@ int8_t polar_decoder_dci(double *input, } void init_polar_deinterleaver_table(t_nrPolar_params *polarParams) { - AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); + AssertFatal(polarParams->K > 17, "K = %d < 18, is not allowed\n",polarParams->K); AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K); int bit_i,ip,ipmod64; int numbytes = polarParams->K>>3; @@ -670,7 +670,9 @@ uint32_t polar_decoder_int16(int16_t *input, A32_flip[1+offset]=((uint8_t *)&Aprime)[2]; A32_flip[2+offset]=((uint8_t *)&Aprime)[1]; A32_flip[3+offset]=((uint8_t *)&Aprime)[0]; - crc = (uint64_t)(crc24c(A32_flip,8*offset+len)>>8); + if (crclen == 24) crc = (uint64_t)((crc24c(A32_flip,8*offset+len)>>8)&0xffffff); + else if (crclen == 11) crc = (uint64_t)((crc11(A32_flip,8*offset+len)>>21)&0x7ff); + else if (crclen == 6) crc = (uint64_t)((crc6(A32_flip,8*offset+len)>>26)&0x3f); } else if (len<=64) { Ar = (B[0]>>crclen) | (B[1]<<(64-crclen));; uint8_t A64_flip[8+offset]; @@ -688,7 +690,9 @@ uint32_t polar_decoder_int16(int16_t *input, A64_flip[5+offset]=((uint8_t *)&Aprime)[2]; A64_flip[6+offset]=((uint8_t *)&Aprime)[1]; A64_flip[7+offset]=((uint8_t *)&Aprime)[0]; - crc = (uint64_t)(crc24c(A64_flip,8*offset+len)>>8); + if (crclen==24) crc = (uint64_t)(crc24c(A64_flip,8*offset+len)>>8)&0xffffff; + else if (crclen==11) crc = (uint64_t)(crc11(A64_flip,8*offset+len)>>21)&0x7ff; + else if (crclen==6) crc = (uint64_t)(crc6(A64_flip,8*offset+len)>>26)&0x3f; } #if 0 diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c index daa2346098..42d500ae86 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c @@ -197,8 +197,10 @@ decoder_node_t *add_nodes(int level, int first_leaf_index, t_nrPolar_params *pol } for (int i=0;iinformation_bit_pattern[i+first_leaf_index]>0) - all_frozen_below=0; + if (polarParams->information_bit_pattern[i+first_leaf_index]>0) { + all_frozen_below=0; + break; + } } if (all_frozen_below==0) diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h index 6e01a05d0f..a44a08a701 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h @@ -146,7 +146,7 @@ void polar_encoder_dci(uint32_t *in, uint16_t n_RNTI); void polar_encoder_fast(uint64_t *A, - uint32_t *out, + void *out, int32_t crcmask, uint8_t ones_flag, t_nrPolar_params *polarParams); diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c index 8e4b45f744..27c062c217 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c @@ -295,8 +295,8 @@ static inline void polar_rate_matching(t_nrPolar_params *polarParams,void *in,vo void build_polar_tables(t_nrPolar_params *polarParams) { // build table b -> c' - AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); - AssertFatal(polarParams->K < 129, "K = %d > 64, is not supported yet\n",polarParams->K); + AssertFatal(polarParams->K > 17, "K = %d < 18, is not possible\n",polarParams->K); + AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K); int bit_i,ip; int numbytes = polarParams->K>>3; int residue = polarParams->K&7; @@ -327,7 +327,7 @@ void build_polar_tables(t_nrPolar_params *polarParams) { AssertFatal(polarParams->N==512 || polarParams->N==256 || polarParams->N==128,"N = %d, not done yet\n",polarParams->N); // build G bit vectors for information bit positions and convert the bit as bytes tables in nr_polar_kronecker_power_matrices.c to 64 bit packed vectors. // keep only rows of G which correspond to information/crc bits - polarParams->G_N_tab = (uint64_t **)malloc(polarParams->K * sizeof(int64_t *)); + polarParams->G_N_tab = (uint64_t **)malloc((polarParams->K + polarParams->n_pc) * sizeof(int64_t *)); int k=0; for (int i=0; iN; i++) { @@ -408,18 +408,18 @@ void build_polar_tables(t_nrPolar_params *polarParams) { } void polar_encoder_fast(uint64_t *A, - uint32_t *out, + void *out, int32_t crcmask, uint8_t ones_flag, t_nrPolar_params *polarParams) { - AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); + // AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K); AssertFatal(polarParams->payloadBits < 65, "payload bits = %d > 64, is not supported yet\n",polarParams->payloadBits); uint64_t B[4]= {0,0,0,0},Cprime[4]= {0,0,0,0}; int bitlen = polarParams->payloadBits; // append crc AssertFatal(bitlen<129,"support for payloads <= 128 bits\n"); - AssertFatal(polarParams->crcParityBits == 24,"support for 24-bit crc only for now\n"); + // AssertFatal(polarParams->crcParityBits == 24,"support for 24-bit crc only for now\n"); //int bitlen0=bitlen; uint64_t tcrc=0; uint8_t offset = 0; @@ -444,7 +444,9 @@ void polar_encoder_fast(uint64_t *A, A32_flip[1+offset]=((uint8_t *)&Aprime)[2]; A32_flip[2+offset]=((uint8_t *)&Aprime)[1]; A32_flip[3+offset]=((uint8_t *)&Aprime)[0]; - tcrc = (uint64_t)((crcmask^(crc24c(A32_flip,8*offset+bitlen)>>8))); + if (polarParams->crcParityBits == 24) tcrc = (uint64_t)(((crcmask^(crc24c(A32_flip,8*offset+bitlen)>>8)))&0xffffff); + else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)(((crcmask^(crc11(A32_flip,bitlen)>>21)))&0x7ff); + else if (polarParams->crcParityBits == 6) tcrc = (uint64_t)(((crcmask^(crc6(A32_flip,bitlen)>>26)))&0x3f); } else if (bitlen<=64) { uint8_t A64_flip[8+offset]; if (ones_flag) { @@ -461,7 +463,8 @@ void polar_encoder_fast(uint64_t *A, A64_flip[5+offset]=((uint8_t *)&Aprime)[2]; A64_flip[6+offset]=((uint8_t *)&Aprime)[1]; A64_flip[7+offset]=((uint8_t *)&Aprime)[0]; - tcrc = (uint64_t)((crcmask^(crc24c(A64_flip,8*offset+bitlen)>>8))); + if (polarParams->crcParityBits == 24) tcrc = (uint64_t)((crcmask^(crc24c(A64_flip,8*offset+bitlen)>>8)))&0xffffff; + else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)((crcmask^(crc11(A64_flip,bitlen)>>21)))&0x7ff; } else if (bitlen<=128) { uint8_t A128_flip[16+offset]; @@ -479,7 +482,8 @@ void polar_encoder_fast(uint64_t *A, A128_flip[10+offset]=((uint8_t*)&Aprime)[5]; A128_flip[11+offset]=((uint8_t*)&Aprime)[4]; A128_flip[12+offset]=((uint8_t*)&Aprime)[3]; A128_flip[13+offset]=((uint8_t*)&Aprime)[2]; A128_flip[14+offset]=((uint8_t*)&Aprime)[1]; A128_flip[15+offset]=((uint8_t*)&Aprime)[0]; - tcrc = (uint64_t)((crcmask^(crc24c(A128_flip,8*offset+bitlen)>>8))); + if (polarParams->crcParityBits == 24) tcrc = (uint64_t)((crcmask^(crc24c(A128_flip,8*offset+bitlen)>>8)))&0xffffff; + else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)((crcmask^(crc11(A128_flip,bitlen)>>21)))&0x7ff; } int n; @@ -522,6 +526,7 @@ void polar_encoder_fast(uint64_t *A, #ifdef DEBUG_POLAR_ENCODER + printf("Polar encoder: (N,K) : (%d,%d)\n",polarParams->N,polarParams->K); if (polarParams->K<65) printf("A %llx B %llx Cprime %llx (payload bits %d,crc %x)\n", (unsigned long long)(A[0]&(((uint64_t)1<>8); } -#endif + #endif /* printf("Bbytes : %x.%x.%x.%x.%x.%x.%x.%x\n",Bbyte[0],Bbyte[1],Bbyte[2],Bbyte[3],Bbyte[4],Bbyte[5],Bbyte[6],Bbyte[7]); printf("%llx,%llx,%llx,%llx,%llx,%llx,%llx,%llx\n",polarParams->cprime_tab[0][Bbyte[0]] , polarParams->cprime_tab[1][Bbyte[1]] , @@ -671,5 +676,5 @@ void polar_encoder_fast(uint64_t *A, } } memset((void*)out,0,polarParams->encoderLength>>3); - polar_rate_matching(polarParams,(void *)D,(void *)out); + polar_rate_matching(polarParams,(void *)D, out); } diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h b/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h index 42051eb1b5..1ab664e5a2 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h @@ -33,8 +33,8 @@ #ifndef __NR_POLAR_UCI_DEFS__H__ #define __NR_POLAR_UCI_DEFS__H__ -#define NR_POLAR_UCI_MESSAGE_TYPE -1 //int8_t -#define NR_POLAR_UCI_CRC_ERROR_CORRECTION_BITS 3 +#define NR_POLAR_UCI_PUCCH_MESSAGE_TYPE 2 //int8_t +#define NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS 3 #define NR_POLAR_PUCCH_PAYLOAD_BITS 32 #define NR_POLAR_PUCCH_E 32 diff --git a/openair1/PHY/CODING/nr_polar_init.c b/openair1/PHY/CODING/nr_polar_init.c index f6a06b3f7f..f6a700117d 100644 --- a/openair1/PHY/CODING/nr_polar_init.c +++ b/openair1/PHY/CODING/nr_polar_init.c @@ -43,11 +43,12 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, uint8_t aggregation_level, int decoder_flag) { t_nrPolar_params *currentPtr = *polarParams; - uint16_t aggregation_prime = nr_polar_aggregation_prime(aggregation_level); + uint16_t aggregation_prime = (messageType >= 2) ? aggregation_level : nr_polar_aggregation_prime(aggregation_level); //Parse the list. If the node is already created, return without initialization. while (currentPtr != NULL) { //printf("currentPtr->idx %d, (%d,%d)\n",currentPtr->idx,currentPtr->payloadBits,currentPtr->encoderLength); + //LOG_D(PHY,"Looking for index %d\n",(messageType * messageLength * aggregation_prime)); if (currentPtr->idx == (messageType * messageLength * aggregation_prime)) return; else currentPtr = currentPtr->nextPtr; } @@ -55,8 +56,9 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, // printf("currentPtr %p (polarParams %p)\n",currentPtr,polarParams); //Else, initialize and add node to the end of the linked list. t_nrPolar_params *newPolarInitNode = calloc(sizeof(t_nrPolar_params),1); - + if (newPolarInitNode != NULL) { + // LOG_D(PHY,"Setting new polarParams index %d, messageType %d, messageLength %d, aggregation_prime %d\n",(messageType * messageLength * aggregation_prime),messageType,messageLength,aggregation_prime); newPolarInitNode->idx = (messageType * messageLength * aggregation_prime); newPolarInitNode->nextPtr = NULL; //printf("newPolarInitNode->idx %d, (%d,%d,%d:%d)\n",newPolarInitNode->idx,messageType,messageLength,aggregation_prime,aggregation_level); @@ -87,15 +89,44 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, newPolarInitNode->crcCorrectionBits = NR_POLAR_DCI_CRC_ERROR_CORRECTION_BITS; newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P //printf("Initializing polar parameters for DCI (K %d, E %d, L %d)\n",newPolarInitNode->payloadBits,newPolarInitNode->encoderLength,aggregation_level); - } else if (messageType == -1) { //UCI + } else if (messageType == 2) { //UCI PUCCH2 + AssertFatal(aggregation_level>2,"Aggregation level (%d) for PUCCH 2 encoding is NPRB and should be > 2\n",aggregation_level); + AssertFatal(messageLength>11,"Message length %d is too short for polar encoding of UCI\n",messageLength); + newPolarInitNode->n_max = NR_POLAR_PUCCH_N_MAX; + newPolarInitNode->i_il = NR_POLAR_PUCCH_I_IL; + newPolarInitNode->encoderLength = aggregation_level * 16; + + newPolarInitNode->i_seg = 0; + + if ((messageLength >= 360 && newPolarInitNode->encoderLength >= 1088)|| + (messageLength >= 1013)) newPolarInitNode->i_seg = 1; + + newPolarInitNode->crcParityBits = 11; + newPolarInitNode->n_pc = 0; + newPolarInitNode->n_pc_wm = 0; + + if (messageLength < 20) { + newPolarInitNode->crcParityBits = 6; + newPolarInitNode->n_pc = 3; + if ((newPolarInitNode->encoderLength - messageLength - 6 + 3) < 193) newPolarInitNode->n_pc_wm = 1; + } + + + + newPolarInitNode->i_bil = NR_POLAR_PUCCH_I_BIL; + + newPolarInitNode->payloadBits = messageLength; + newPolarInitNode->crcCorrectionBits = NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS; + //newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P + //LOG_D(PHY,"New polar node, encoderLength %d, aggregation_level %d\n",newPolarInitNode->encoderLength,aggregation_level); } else { AssertFatal(1 == 0, "[nr_polar_init] Incorrect Message Type(%d)", messageType); } newPolarInitNode->K = newPolarInitNode->payloadBits + newPolarInitNode->crcParityBits; // Number of bits to encode. newPolarInitNode->N = nr_polar_output_length(newPolarInitNode->K, - newPolarInitNode->encoderLength, - newPolarInitNode->n_max); + newPolarInitNode->encoderLength, + newPolarInitNode->n_max); newPolarInitNode->n = log2(newPolarInitNode->N); newPolarInitNode->G_N = nr_polar_kronecker_power_matrices(newPolarInitNode->n); //polar_encoder vectors: @@ -191,16 +222,19 @@ t_nrPolar_params *nr_polar_params (int8_t messageType, nr_polar_init(polarList_ext != NULL ? polarList_ext : &polarList, messageType,messageLength,aggregation_level,decoding_flag); t_nrPolar_params *polarParams=polarList_ext != NULL ? *polarList_ext : polarList; - const int tag=messageType * messageLength * nr_polar_aggregation_prime(aggregation_level); + const int tag=messageType * messageLength * (messageType>=2 ? aggregation_level : nr_polar_aggregation_prime(aggregation_level)); + + while (polarParams != NULL) { + // LOG_D(PHY,"nr_polar_params : tag %d (from nr_polar_init %d)\n",tag,polarParams->idx); if (polarParams->idx == tag) return polarParams; polarParams = polarParams->nextPtr; } - AssertFatal(false,"Polar Init tables internal failure\n"); + AssertFatal(false,"Polar Init tables internal failure, no polarParams found\n"); return NULL; } diff --git a/openair1/PHY/CODING/nr_rate_matching.c b/openair1/PHY/CODING/nr_rate_matching.c index 0cffc2d852..5294e79b9f 100644 --- a/openair1/PHY/CODING/nr_rate_matching.c +++ b/openair1/PHY/CODING/nr_rate_matching.c @@ -364,8 +364,8 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, if (ind < Foffset) { // case where we have some bits before the filler and the rest after memcpy((void*)e,(void*)(w+ind),Foffset-ind); - if (E + F <= Ncb) { // E+F doesn't contain all coded bits - memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F-ind),E-Foffset+ind); + if (E + F <= Ncb-ind) { // E+F doesn't contain all coded bits + memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F),E-Foffset+ind); k=E; } else { @@ -375,11 +375,12 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, } else { if (E + F <= Ncb-ind) { //E+F doesn't contain all coded bits - memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F-ind),E-Foffset+ind); + memcpy((void*)(e),(void*)(w+ind),E); k=E; } else { - + memcpy((void*)(e),(void*)(w+ind),Ncb-ind); + k=Ncb-ind; } } diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 813d419429..9e095d5ab5 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -25,7 +25,8 @@ #include "PHY/NR_REFSIG/nr_refsig.h" #include "PHY/INIT/phy_init.h" #include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" #include "TDD-Config.h" @@ -39,7 +40,6 @@ #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_REFSIG/nr_refsig.h" #include "SCHED_NR/fapi_nr_l1.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "nfapi_nr_interface.h" /* @@ -153,11 +153,11 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } } - nr_init_pdsch_dmrs(gNB, cfg->cell_config.phy_cell_id.value); //PUSCH DMRS init gNB->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(2*sizeof(uint32_t ***)); + uint32_t ****pusch_dmrs = gNB->nr_gold_pusch_dmrs; for(int nscid=0; nscid<2; nscid++) { @@ -176,6 +176,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } uint32_t Nid_pusch[2] = {cfg->cell_config.phy_cell_id.value,cfg->cell_config.phy_cell_id.value}; + LOG_D(PHY,"Initializing PUSCH DMRS Gold sequence with (%x,%x)\n",Nid_pusch[0],Nid_pusch[1]); nr_gold_pusch(gNB, &Nid_pusch[0]); /// Transport init necessary for NR synchro @@ -232,6 +233,8 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, */ prach_vars->prach_ifft = (int32_t *)malloc16_clear(1024*2*sizeof(int32_t)); + init_prach_list(gNB); + int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value; printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]); @@ -405,7 +408,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, fp->dl_CarrierFreq = 3500000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value); fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000); fp->nr_band = 78; - fp->threequarter_fs= 0; +// fp->threequarter_fs= 0; gNB_config->carrier_config.dl_bandwidth.value = config_bandwidth(mu, N_RB_DL, fp->nr_band); @@ -417,6 +420,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, void nr_phy_config_request(NR_PHY_Config_t *phy_config) { uint8_t Mod_id = phy_config->Mod_id; + uint8_t short_sequence, num_sequences, rootSequenceIndex, fd_occasion; NR_DL_FRAME_PARMS *fp = &RC.gNB[Mod_id]->frame_parms; nfapi_nr_config_request_scf_t *gNB_config = &RC.gNB[Mod_id]->gNB_config; @@ -480,6 +484,14 @@ void nr_phy_config_request(NR_PHY_Config_t *phy_config) { return; } + fd_occasion = 0; + nfapi_nr_prach_config_t *prach_config = &gNB_config->prach_config; + short_sequence = prach_config->prach_sequence_length.value; + num_sequences = prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value; + rootSequenceIndex = prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value; + + compute_nr_prach_seq(short_sequence, num_sequences, rootSequenceIndex, RC.gNB[Mod_id]->X_u); + RC.gNB[Mod_id]->configured = 1; LOG_I(PHY,"gNB %d configured\n",Mod_id); } @@ -492,6 +504,12 @@ void init_nr_transport(PHY_VARS_gNB *gNB) { LOG_I(PHY, "Initialise nr transport\n"); uint16_t grid_size = cfg->carrier_config.dl_grid_size[fp->numerology_index].value; + for (i=0; ipucch[i] = new_gNB_pucch(); + AssertFatal(gNB->pucch[i]!=NULL,"Can't initialize pucch %d \n", i); + } + for (i=0; inb_log_antennas=0; for (int n=0;ngNB_config; + cfg = &ru->config; if (cfg->carrier_config.num_tx_ant.value > ru->nb_log_antennas) ru->nb_log_antennas = cfg->carrier_config.num_tx_ant.value; } + // copy configuration from gNB[0] in to RU, assume that all gNB instances sharing RU use the same configuration (at least the parts that are needed by the RU, numerology and PRACH) + AssertFatal(ru->nb_log_antennas > 0 && ru->nb_log_antennas < 13, "ru->nb_log_antennas %d ! \n",ru->nb_log_antennas); if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals // Time-domain signals @@ -107,7 +110,8 @@ int nr_phy_init_RU(RU_t *ru) { ru->prach_rxsigF = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*)); for (i=0; inb_rx; i++) { - ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*2*sizeof(int16_t) ); + // largest size for PRACH FFT is 4x98304 (16*24576) + ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( 4*98304*2*sizeof(int16_t) ); LOG_D(PHY,"[INIT] prach_vars->rxsigF[%d] = %p\n",i,ru->prach_rxsigF[i]); } @@ -144,6 +148,8 @@ int nr_phy_init_RU(RU_t *ru) { ru->common.sync_corr = (uint32_t*)malloc16_clear( LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*sizeof(uint32_t)*fp->samples_per_subframe_wCP ); + init_prach_ru_list(ru); + return(0); } diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index 5a60d15e2b..1729ac0d9e 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -77,19 +77,19 @@ void phy_config_sib2_ue(uint8_t Mod_id,int CC_id, LOG_I(PHY,"[UE%d] Applying radioResourceConfigCommon from eNB%d\n",Mod_id,eNB_id); - fp->prach_config_common.rootSequenceIndex =radioResourceConfigCommon->prach_Config.rootSequenceIndex; + ue->prach_vars[eNB_id]->prach_pdu.root_seq_id =radioResourceConfigCommon->prach_Config.rootSequenceIndex; - fp->prach_config_common.prach_Config_enabled=1; - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_ConfigIndex; - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.highSpeedFlag; - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig; - fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_FreqOffset; + ue->prach_vars[eNB_id]->prach_Config_enabled=1; + //ue->prach_vars[eNB_id]->prach_pdu.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_ConfigIndex; + ue->prach_vars[eNB_id]->prach_pdu.restricted_set =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.highSpeedFlag; + ue->prach_vars[eNB_id]->prach_pdu.num_cs =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig; + //ue->prach_vars[eNB_id]->prach_pdu.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_FreqOffset; - compute_prach_seq(fp->prach_config_common.rootSequenceIndex, - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag, - fp->frame_type,ue->X_u); + //compute_prach_seq(fp->prach_config_common.rootSequenceIndex, + // fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + // fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, + // fp->prach_config_common.prach_ConfigInfo.highSpeedFlag, + // fp->frame_type,ue->X_u); @@ -226,12 +226,12 @@ void phy_config_sib13_ue(uint8_t Mod_id,int CC_id,uint8_t eNB_id,int mbsfn_Area_ LOG_I(PHY,"[UE%d] Handover triggered: Applying radioResourceConfigCommon from eNB %d\n", Mod_id,eNB_id); - fp->prach_config_common.rootSequenceIndex =radioResourceConfigCommon->prach_Config.rootSequenceIndex; - fp->prach_config_common.prach_Config_enabled=1; - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex; - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->highSpeedFlag; - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->zeroCorrelationZoneConfig; - fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_FreqOffset; + ue->prach_vars[eNB_id]->prach_pdu.root_seq_id =radioResourceConfigCommon->prach_Config.rootSequenceIndex; + ue->prach_vars[eNB_id]->prach_Config_enabled=1; + //ue->prach_vars[eNB_id]->prach_pdu.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex; + ue->prach_vars[eNB_id]->prach_pdu.restricted_set =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->highSpeedFlag; + ue->prach_vars[eNB_id]->prach_pdu.num_cs =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->zeroCorrelationZoneConfig; + //ue->prach_vars[eNB_id]->prach_pdu.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_FreqOffset; // prach_fmt = get_prach_fmt(radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex,fp->frame_type); // N_ZC = (prach_fmt <4)?839:139; @@ -239,12 +239,12 @@ void phy_config_sib13_ue(uint8_t Mod_id,int CC_id,uint8_t eNB_id,int mbsfn_Area_ // prach_root_sequence_map4[fp->prach_config_common.rootSequenceIndex]; //compute_prach_seq(u,N_ZC, PHY_vars_UE_g[Mod_id]->X_u); - compute_prach_seq(PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.rootSequenceIndex, - PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, - fp->frame_type, - PHY_vars_UE_g[Mod_id][CC_id]->X_u); + //compute_prach_seq(PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.rootSequenceIndex, + // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, + // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, + // fp->frame_type, + // PHY_vars_UE_g[Mod_id][CC_id]->X_u); fp->pucch_config_common.deltaPUCCH_Shift = 1+radioResourceConfigCommon->pucch_ConfigCommon->deltaPUCCH_Shift; @@ -958,7 +958,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, // enable MIB/SIB decoding by default ue->decode_MIB = 1; ue->decode_SIB = 1; - init_prach_tables(839); + + init_nr_prach_tables(839); + return 0; } diff --git a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c index aaa138fcd9..f85162e095 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c @@ -112,18 +112,12 @@ int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms, } -int lte_est_timing_advance_pusch(PHY_VARS_eNB *eNB, - module_id_t UE_id) +int lte_est_timing_advance_pusch(LTE_DL_FRAME_PARMS *frame_parms, + int32_t **ul_ch_estimates_time) { int temp, i, aa, max_pos=0, max_val=0; short Re,Im; - RU_t *ru; - ru = RC.ru[UE_id]; - LTE_DL_FRAME_PARMS *frame_parms = (eNB==NULL) ? ru->frame_parms : &eNB->frame_parms; - LTE_eNB_PUSCH *eNB_pusch_vars = (eNB!=NULL) ? eNB->pusch_vars[UE_id] : (LTE_eNB_PUSCH*)NULL; - RU_CALIBRATION *calibration = &ru->calibration; - int32_t **ul_ch_estimates_time = (eNB==NULL) ? calibration->drs_ch_estimates_time : eNB_pusch_vars->drs_ch_estimates_time; uint8_t cyclic_shift = 0; int sync_pos = (frame_parms->ofdm_symbol_size-cyclic_shift*frame_parms->ofdm_symbol_size/12)%(frame_parms->ofdm_symbol_size); @@ -149,7 +143,7 @@ int lte_est_timing_advance_pusch(PHY_VARS_eNB *eNB, max_pos = max_pos-frame_parms->ofdm_symbol_size; //#ifdef DEBUG_PHY - LOG_D(PHY,"frame %d: max_pos = %d, sync_pos=%d\n",eNB->proc.frame_rx,max_pos,sync_pos); + LOG_D(PHY,"max_pos = %d, sync_pos=%d\n",max_pos,sync_pos); //#endif //DEBUG_PHY return max_pos - sync_pos; diff --git a/openair1/PHY/LTE_ESTIMATION/lte_estimation.h b/openair1/PHY/LTE_ESTIMATION/lte_estimation.h index 01883224db..fc40280853 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_estimation.h +++ b/openair1/PHY/LTE_ESTIMATION/lte_estimation.h @@ -220,8 +220,12 @@ void phy_adjust_gain (PHY_VARS_UE *phy_vars_ue, uint32_t rx_power_fil_dB, unsigned char eNB_id); -int lte_ul_channel_estimation(PHY_VARS_eNB *phy_vars_eNB, +int32_t lte_ul_channel_estimation(LTE_DL_FRAME_PARMS *frame_parms, L1_rxtx_proc_t *proc, + LTE_eNB_ULSCH_t * ulsch, + int32_t **ul_ch_estimates, + int32_t **ul_ch_estimates_time, + int32_t **rxdataF_ext, module_id_t UE_id, uint8_t l, uint8_t Ns); @@ -258,7 +262,8 @@ int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms, unsigned char number_of_cards, short coef); -int lte_est_timing_advance_pusch(PHY_VARS_eNB* phy_vars_eNB,module_id_t UE_id); +int lte_est_timing_advance_pusch(LTE_DL_FRAME_PARMS *frame_parms, + int32_t **ul_ch_estimates_time); void lte_eNB_I0_measurements(PHY_VARS_eNB *phy_vars_eNB, int subframe, diff --git a/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c index 7caaf07406..755111feb8 100644 --- a/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c +++ b/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c @@ -34,23 +34,17 @@ static int16_t ru_90c[2*128] = {32767, 0,32766, -402,32758, -804,32746, -1206,32 #define SCALE 0x3FFF -int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB, +int32_t lte_ul_channel_estimation(LTE_DL_FRAME_PARMS *frame_parms, L1_rxtx_proc_t *proc, + LTE_eNB_ULSCH_t * ulsch, + int32_t **ul_ch_estimates, + int32_t **ul_ch_estimates_time, + int32_t **rxdataF_ext, module_id_t UE_id, unsigned char l, unsigned char Ns) { - RU_t *ru; - ru = RC.ru[UE_id]; - LTE_DL_FRAME_PARMS *frame_parms = (eNB!=NULL) ? &eNB->frame_parms : ru->frame_parms; - LTE_eNB_PUSCH *pusch_vars = (eNB!=NULL) ? eNB->pusch_vars[UE_id] : NULL; - RU_CALIBRATION *calibration = &ru->calibration; - int32_t **ul_ch_estimates = (eNB!=NULL) ? pusch_vars->drs_ch_estimates : calibration->drs_ch_estimates; - AssertFatal(ul_ch_estimates != NULL, "ul_ch_estimates is null (eNB %p, pusch %p, pusch->drs_ch_estimates %p, pusch->drs_ch_estimates[0] %p ul_ch_estimates %p UE_id %d)\n",eNB,pusch_vars, - pusch_vars->drs_ch_estimates,pusch_vars->drs_ch_estimates[0],ul_ch_estimates,UE_id); - int32_t **ul_ch_estimates_time = (eNB!=NULL) ? pusch_vars->drs_ch_estimates_time : calibration->drs_ch_estimates_time; + AssertFatal(ul_ch_estimates != NULL, "ul_ch_estimates is null "); AssertFatal(ul_ch_estimates_time != NULL, "ul_ch_estimates_time is null\n"); - int32_t **rxdataF_ext = (eNB!=NULL) ? pusch_vars->rxdataF_ext : calibration->rxdataF_ext; - int subframe = proc->subframe_rx; uint8_t harq_pid; @@ -83,16 +77,16 @@ int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB, #endif int32_t temp_in_ifft_0[2048*2] __attribute__((aligned(32))); - if (eNB->ulsch[UE_id]->ue_type > 0) harq_pid = 0; + if (ulsch->ue_type > 0) harq_pid = 0; else { harq_pid = subframe2harq_pid(frame_parms,proc->frame_rx,subframe); } - uint16_t N_rb_alloc = eNB->ulsch[UE_id]->harq_processes[harq_pid]->nb_rb; + uint16_t N_rb_alloc = ulsch->harq_processes[harq_pid]->nb_rb; int32_t tmp_estimates[N_rb_alloc*12] __attribute__((aligned(16))); Msc_RS = N_rb_alloc*12; cyclic_shift = (frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift + - eNB->ulsch[UE_id]->harq_processes[harq_pid]->n_DMRS2 + + ulsch->harq_processes[harq_pid]->n_DMRS2 + frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.nPRS[(subframe<<1)+Ns]) % 12; Msc_idx_ptr = (uint16_t *) bsearch(&Msc_RS, dftsizes, 34, sizeof(uint16_t), compareints); @@ -276,7 +270,7 @@ int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB, #if T_TRACER if (aa == 0) - T(T_ENB_PHY_UL_CHANNEL_ESTIMATE, T_INT(0), T_INT(eNB->ulsch[UE_id]->rnti), + T(T_ENB_PHY_UL_CHANNEL_ESTIMATE, T_INT(0), T_INT(ulsch->rnti), T_INT(proc->frame_rx), T_INT(subframe), T_INT(0), T_BUFFER(ul_ch_estimates_time[0], 512 * 4)); diff --git a/openair1/PHY/LTE_TRANSPORT/dci_tools.c b/openair1/PHY/LTE_TRANSPORT/dci_tools.c index ce409de131..8de011acef 100644 --- a/openair1/PHY/LTE_TRANSPORT/dci_tools.c +++ b/openair1/PHY/LTE_TRANSPORT/dci_tools.c @@ -2006,11 +2006,6 @@ void fill_ulsch(PHY_VARS_eNB *eNB,int UE_id,nfapi_ul_config_ulsch_pdu *ulsch_pdu return; } - //AssertFatal(ulsch->harq_processes[harq_pid]->nb_rb>0,"nb_rb = 0\n"); - if(ulsch->harq_processes[harq_pid]->nb_rb == 0) { - LOG_E(PHY, "fill_ulsch UE_id %d nb_rb = 0\n", UE_id); - } - ulsch->harq_processes[harq_pid]->frame = frame; ulsch->harq_processes[harq_pid]->subframe = subframe; ulsch->harq_processes[harq_pid]->handled = 0; diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c index 15eb5206a1..14036ad43a 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c @@ -422,6 +422,6 @@ int dlsch_encoding(PHY_VARS_eNB *eNB, else r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C)); } - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); return(0); } diff --git a/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c b/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c index f357e385f0..1b23fc99bf 100644 --- a/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c +++ b/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c @@ -1047,7 +1047,11 @@ void rx_ulsch(PHY_VARS_eNB *eNB, l%(frame_parms->symbols_per_tti/2), l/(frame_parms->symbols_per_tti/2), frame_parms); - lte_ul_channel_estimation(eNB,proc, + lte_ul_channel_estimation(&eNB->frame_parms,proc, + eNB->ulsch[UE_id], + eNB->pusch_vars[UE_id]->drs_ch_estimates, + eNB->pusch_vars[UE_id]->drs_ch_estimates_time, + eNB->pusch_vars[UE_id]->rxdataF_ext, UE_id, l%(frame_parms->symbols_per_tti/2), l/(frame_parms->symbols_per_tti/2)); diff --git a/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c b/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c index 2fd84f563c..556a9f2d23 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c @@ -821,15 +821,14 @@ int rx_pdsch(PHY_VARS_UE *ue, pllr_symbol_cw0 += llr_offset_symbol; pllr_symbol_cw1 += llr_offset_symbol; - /* - LOG_I(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %p @LLR Buff(symb) %p\n", + LOG_D(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %p @LLR Buff(symb) %p energy: %d\n", frame, subframe,symbol, nb_rb,dlsch0_harq->Qm, pdsch_vars[eNB_id]->llr_length[symbol], pdsch_vars[eNB_id]->llr_offset[symbol], (int16_t*)pdsch_vars[eNB_id]->llr[0], - pllr_symbol_cw0); - */ + pllr_symbol_cw0, + signal_energy(pdsch_vars[eNB_id]->rxdataF_comp0[0], 7*2*frame_parms->N_RB_DL*12)); switch (dlsch0_harq->Qm) { case 2 : if ((rx_type==rx_standard) || (codeword_TB1 == -1)) { diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index b27b692e66..dbfe93adee 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -34,6 +34,8 @@ void nr_modulation(uint32_t *in, offset = (mod_order==2)? NR_MOD_TABLE_QPSK_OFFSET : (mod_order==4)? NR_MOD_TABLE_QAM16_OFFSET : \ (mod_order==6)? NR_MOD_TABLE_QAM64_OFFSET: (mod_order==8)? NR_MOD_TABLE_QAM256_OFFSET : 0; + LOG_D(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); + for (int i=0; iframe_parms; NR_UE_COMMON *common_vars = &ue->common_vars; @@ -339,7 +339,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, #endif - dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][rx_offset], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); #if UE_TIMING_TRACE stop_meas(&ue->rx_dft_stats); @@ -363,7 +363,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, dft(dftsize,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly - dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][rx_offset], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } #if UE_TIMING_TRACE @@ -395,12 +395,13 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, int sample_offset, int no_prefix) { - uint32_t slot_offset; - uint32_t rxdata_offset; + int32_t slot_offset, rxdata_offset; unsigned int nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples); unsigned int nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples0); + int tmp_dft_in[8192] __attribute__ ((aligned (32))); + dft_size_idx_t dftsize; switch (frame_parms->ofdm_symbol_size) { @@ -443,14 +444,29 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, slot_offset = frame_parms->get_samples_slot_timestamp(Ns,frame_parms,0); - if(symbol == 0) rxdata_offset = slot_offset + nb_prefix_samples0 - SOFFSET; else rxdata_offset = slot_offset + nb_prefix_samples0 + (symbol * (frame_parms->ofdm_symbol_size + nb_prefix_samples)) - SOFFSET; - dft(dftsize,(int16_t *)&rxdata[rxdata_offset], - (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); + if(sample_offset>rxdata_offset) { + memcpy((void *)tmp_dft_in, + (void *) &rxdata[frame_parms->samples_per_frame-sample_offset+rxdata_offset], + (sample_offset-rxdata_offset)*sizeof(int)); + + memcpy((void *)&tmp_dft_in[sample_offset-rxdata_offset], + (void *) &rxdata[0], + (frame_parms->ofdm_symbol_size-sample_offset+rxdata_offset)*sizeof(int)); + + dft(dftsize,(int16_t *)&tmp_dft_in, + (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); + } + else + dft(dftsize,(int16_t *)&rxdata[rxdata_offset-sample_offset], + (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); + + // clear DC carrier from OFDM symbols + rxdataF[symbol * frame_parms->ofdm_symbol_size] = 0; return(0); } diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index f94a82c111..3f7c7817f7 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -28,7 +28,7 @@ #include "PHY/NR_UE_ESTIMATION/filt16a_32.h" //#define DEBUG_CH - +//#define DEBUG_PUSCH int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, unsigned char Ns, @@ -116,7 +116,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// - nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->dmrs_config_type); + if (pusch_pdu->transform_precoding==1) // if transform precoding is disabled + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type); + else + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type); //------------------------------------------------// @@ -129,8 +132,9 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size)); #ifdef DEBUG_PUSCH + printf("symbol_offset %d, nushift %d\n",symbol_offset,nushift); printf("ch est pilot addr %p RB_DL %d\n",&pilot[0], gNB->frame_parms.N_RB_UL); - printf("k %d, first_carrier %d\n",k,gNB->frame_parms.first_carrier_offset); + printf("bwp_start_subcarrier %d, k %d, first_carrier %d\n",bwp_start_subcarrier,k,gNB->frame_parms.first_carrier_offset); printf("rxF addr %p p %d\n", rxF,p); printf("ul_ch addr %p nushift %d\n",ul_ch,nushift); #endif @@ -145,7 +149,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])); printf("pilot 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]); - printf("data 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[2],rxF[3],&rxF[2],ch[0],ch[1],pil[0],pil[1]); + printf("data 0 : rxF - > (%d,%d)\n",rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fl, @@ -163,6 +167,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data 1 : rxF - > (%d,%d)\n",rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fml, ch, @@ -178,6 +183,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot 2 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data 2 : rxF - > (%d,%d)\n",rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmm, ch, @@ -198,7 +204,8 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH - printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fml, ch, @@ -214,6 +221,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmm, ch, @@ -235,6 +243,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fm, ch, @@ -253,6 +262,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])); printf("pilot %u: rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmr, ch, @@ -268,6 +278,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH printf("pilot %u: rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+2,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fr, ch, @@ -275,70 +286,69 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, 8); - // check if PRB crosses DC and improve estimates around DC - if ((bwp_start_subcarrier < gNB->frame_parms.ofdm_symbol_size) && (bwp_start_subcarrier+nb_rb_pusch*12 >= gNB->frame_parms.ofdm_symbol_size)) { - ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; - uint16_t idxDC = 2*(gNB->frame_parms.ofdm_symbol_size - bwp_start_subcarrier); - uint16_t idxPil = idxDC/2; - re_offset = k; - pil = (int16_t *)&pilot[0]; - pil += (idxPil-2); - ul_ch += (idxDC-4); - ul_ch = memset(ul_ch, 0, sizeof(int16_t)*10); - re_offset = (re_offset+idxDC/2-2) % gNB->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); - ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - - // for proper allignment of SIMD vectors - if((gNB->frame_parms.N_RB_UL&1)==0) { + // check if PRB crosses DC and improve estimates around DC + if ((bwp_start_subcarrier < gNB->frame_parms.ofdm_symbol_size) && (bwp_start_subcarrier+nb_rb_pusch*12 >= gNB->frame_parms.ofdm_symbol_size)) { + ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; + uint16_t idxDC = 2*(gNB->frame_parms.ofdm_symbol_size - bwp_start_subcarrier); + uint16_t idxPil = idxDC/2; + re_offset = k; + pil = (int16_t *)&pilot[0]; + pil += (idxPil-2); + ul_ch += (idxDC-4); + ul_ch = memset(ul_ch, 0, sizeof(int16_t)*10); + re_offset = (re_offset+idxDC/2-2) % gNB->frame_parms.ofdm_symbol_size; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - multadd_real_vector_complex_scalar(fdcl, - ch, - ul_ch-4, - 8); + // for proper allignment of SIMD vectors + if((gNB->frame_parms.N_RB_UL&1)==0) { + + multadd_real_vector_complex_scalar(fdcl, + ch, + ul_ch-4, + 8); - pil += 4; - re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); - ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); + pil += 4; + re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - multadd_real_vector_complex_scalar(fdcr, - ch, - ul_ch-4, - 8); - } else { + multadd_real_vector_complex_scalar(fdcr, + ch, + ul_ch-4, + 8); + } + else { + multadd_real_vector_complex_scalar(fdclh, + ch, + ul_ch, + 8); - multadd_real_vector_complex_scalar(fdclh, - ch, - ul_ch, - 8); + pil += 4; + re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - pil += 4; - re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); - ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - - multadd_real_vector_complex_scalar(fdcrh, - ch, - ul_ch, - 8); + multadd_real_vector_complex_scalar(fdcrh, + ch, + ul_ch, + 8); + } } - - } #ifdef DEBUG_PDSCH - ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; - for(uint16_t idxP=0; idxPframe_parms.ofdm_symbol_size) { + switch (gNB->frame_parms.ofdm_symbol_size) { case 128: idft(IDFT_128,(int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c index 8718fc8610..7042c152fd 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.c +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c @@ -33,7 +33,32 @@ #include "PHY/NR_REFSIG/ss_pbch_nr.h" #include "PHY/NR_REFSIG/dmrs_nr.h" -/***********************************************************************/ + + +uint8_t allowed_xlsch_re_in_dmrs_symbol(uint16_t k, + uint16_t start_sc, + uint8_t numDmrsCdmGrpsNoData, + uint8_t dmrs_type) { + uint8_t delta; + uint16_t diff; + if (k>start_sc) + diff = k-start_sc; + else + diff = start_sc-k; + for (int i = 0; i 2) - LOG_E(PHY,"Bad PUSCH DMRS config type %d\n", dmrs_type); + LOG_E(PHY,"PUSCH DMRS config type %d not valid\n", dmrs_type+1); if ((p>=1000) && (p<((dmrs_type==pusch_dmrs_type1) ? 1008 : 1012))) { if (gNB->frame_parms.Ncp == NORMAL) { - - for (int i=0; i>5])>>((i<<1)&0x1f))&1)<<1) ^ (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1); - ((int16_t*)output)[i<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - ((int16_t*)output)[(i<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; + ((int16_t*)output)[k<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; + ((int16_t*)output)[(k<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; #ifdef DEBUG_PUSCH - printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb); - printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]); - printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), - (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]); + printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb); + printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]); + printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), + (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[k<<1], ((int16_t*)output)[(k<<1)+1]); #endif + } } else { LOG_E(PHY,"extended cp not supported for PUSCH DMRS yet\n"); @@ -102,7 +105,6 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, } - int nr_pdsch_dmrs_rx(PHY_VARS_NR_UE *ue, unsigned int Ns, unsigned int *nr_gold_pdsch, diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c index 472d03e649..4b007f1292 100644 --- a/openair1/PHY/NR_REFSIG/nr_gold.c +++ b/openair1/PHY/NR_REFSIG/nr_gold.c @@ -88,6 +88,7 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) uint16_t N_n_scid[NR_MAX_NB_CODEWORDS]={Nid, Nid}; // Not correct, appropriate scrambling IDs have to be updated to support DCI 1_1 uint8_t n_scid=0; // again works only for 1_0 for (uint8_t slot=0; slotslots_per_frame; slot++) { + for (uint8_t symb=0; symbsymbols_per_slot; symb++) { reset = 1; x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid)); diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h index d18f6405d7..1bf2ef4fb2 100644 --- a/openair1/PHY/NR_REFSIG/nr_refsig.h +++ b/openair1/PHY/NR_REFSIG/nr_refsig.h @@ -48,6 +48,7 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned short p, unsigned char lp, unsigned short nb_pusch_rb, + uint32_t re_offset, uint8_t dmrs_type); void init_scrambling_luts(void); diff --git a/openair1/PHY/NR_REFSIG/scrambling_luts.c b/openair1/PHY/NR_REFSIG/scrambling_luts.c index 9d957de0f7..790d3f7719 100644 --- a/openair1/PHY/NR_REFSIG/scrambling_luts.c +++ b/openair1/PHY/NR_REFSIG/scrambling_luts.c @@ -27,6 +27,7 @@ #include "PHY/impl_defs_nr.h" #include "PHY/sse_intrin.h" +#include __m64 byte2m64_re[256]; __m64 byte2m64_im[256]; @@ -42,7 +43,7 @@ void init_byte2m64(void) { byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>5)&1)),2); byte2m64_re[s] = _mm_insert_pi16(byte2m64_re[s],(1-2*((s>>6)&1)),3); byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>7)&1)),3); - printf("init_scrambling_luts: s %x (%d) ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n", + LOG_T(PHY,"init_scrambling_luts: s %x (%d) ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n", ((uint16_t*)&s)[0], (1-2*(s&1)), ((int16_t*)&byte2m64_re[s])[0],((int16_t*)&byte2m64_im[s])[0], diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index d62687bd9c..a29211b55b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -131,12 +131,13 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, void nr_pdcch_scrambling(uint32_t *in, uint32_t size, uint32_t Nid, - uint32_t n_RNTI, + uint32_t scrambling_RNTI, uint32_t *out) { uint8_t reset; uint32_t x1, x2, s=0; reset = 1; - x2 = (n_RNTI<<16) + Nid; + x2 = (scrambling_RNTI<<16) + Nid; + LOG_D(PHY,"PDCCH Scrambling x2 %x : scrambling_RNTI %x \n", x2, scrambling_RNTI); for (int i=0; iCceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED, "Interleaved CCE REG MAPPING not supported\n"); uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)? - (n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) - uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) + (n_rb*6) : (pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) + uint32_t encoded_length = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType); dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset @@ -228,18 +229,20 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, /// DCI payload processing // CRC attachment + Scrambling + Channel coding + Rate matching uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; - uint16_t n_RNTI = pdcch_pdu_rel15->RNTI[d]; - uint16_t Nid = pdcch_pdu_rel15->ScramblingId[d]; - + + uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d]; + uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d]; + uint16_t scrambling_RNTI = pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[d]; + t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, - pdcch_pdu_rel15->PayloadSizeBits[d], - pdcch_pdu_rel15->AggregationLevel[d], + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], + pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], 0,NULL); - polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr); + polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], (void*)encoder_output, n_RNTI,1,currentPtr); #ifdef DEBUG_CHANNEL_CODING - printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]); + printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", - ((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]); + ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1]); printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5); for (int i=0; i>5; i++) @@ -249,7 +252,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, #endif /// Scrambling uint32_t scrambled_output[NR_MAX_DCI_SIZE_DWORD]= {0}; - nr_pdcch_scrambling(encoder_output, encoded_length, Nid, n_RNTI, scrambled_output); + nr_pdcch_scrambling(encoder_output, encoded_length, Nid, scrambling_RNTI, scrambled_output); #ifdef DEBUG_CHANNEL_CODING printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\t [4]->0x%08x\t [5]->0x%08x\t \ [6]->0x%08x \t [7]->0x%08x \t [8]->0x%08x \t [9]->0x%08x\t [10]->0x%08x\t [11]->0x%08x\n", @@ -272,8 +275,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, cset_start_sc -= frame_parms.ofdm_symbol_size; /*Reorder REG list for a freq first mapping*/ - uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE; - uint8_t reg_idx0 = pdcch_pdu_rel15->CceIndex[d]*NR_NB_REG_PER_CCE; + uint8_t reg_idx0 = pdcch_pdu_rel15->dci_pdu.CceIndex[d]*NR_NB_REG_PER_CCE; + uint8_t nb_regs = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*NR_NB_REG_PER_CCE; /*Mapping the encoded DCI along with the DMRS */ for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) { @@ -295,8 +298,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, for (int m=0; mCceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) { - ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (2*amp * mod_dmrs[l][dmrs_idx<<1]) >> 15; - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (2*amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; + ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15; + ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; #ifdef DEBUG_PDCCH_DMRS printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index c7b14571b7..02ecfc4404 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -140,7 +140,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { int C=-1; for (int d=0;dnumDlDci;d++) { - int L = pdcch_pdu_rel15->AggregationLevel[d]; + int L = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]; if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); @@ -151,10 +151,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { C = N_reg/(bsize*R); } - LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->CceIndex[d]); + LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu.CceIndex[d]); for (uint8_t cce_idx=0; cce_idxcce_list[d][cce_idx]; - cce->cce_idx = pdcch_pdu_rel15->CceIndex[d] + cce_idx; + cce->cce_idx = pdcch_pdu_rel15->dci_pdu.CceIndex[d] + cce_idx; LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { @@ -210,17 +210,17 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, for (int i=0;inumDlDci;i++) { - //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i]; - - int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE); + int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu.RNTI[i],gNB,SEARCH_EXIST_OR_FREE); if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ - LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->RNTI[i],dlsch_id); + LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu.RNTI[i],dlsch_id); return; } dlsch = gNB->dlsch[dlsch_id][0]; - int harq_pid = 0;//extract_harq_pid(i,pdu_rel15); + int num_slots_tdd = (gNB->frame_parms.slots_per_frame)>>(7-gNB->gNB_config.tdd_table.tdd_period.value); + int harq_pid = slot % num_slots_tdd; dlsch->slot_tx[slot] = 1; dlsch->harq_ids[frame%2][slot] = harq_pid; @@ -228,7 +228,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, "illegal harq_pid %d\n",harq_pid); dlsch->harq_mask |= (1<rnti = pdcch_pdu_rel15->RNTI[i]; + dlsch->rnti = pdcch_pdu_rel15->dci_pdu.RNTI[i]; nr_fill_cce_list(gNB,0); /* @@ -248,7 +248,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB, for (int i=0;inumDlDci;i++) { - //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i]; // if there's no DL DCI then generate CCE list if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 4518280f6b..23466132d6 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -34,6 +34,8 @@ #include "nr_dci.h" #include "nr_sch_dmrs.h" #include "PHY/MODULATION/nr_modulation.h" +#include "PHY/NR_REFSIG/dmrs_nr.h" +#include "common/utils/LOG/vcd_signal_dumper.h" //#define DEBUG_DLSCH //#define DEBUG_DLSCH_MAPPING @@ -47,7 +49,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, uint8_t reset, b_idx; uint32_t x1, x2, s=0; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING, 1); reset = 1; x2 = (n_RNTI<<15) + (q<<14) + Nid; @@ -62,7 +64,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, *out ^= (((in[i])&1) ^ ((s>>b_idx)&1))<harq_ids[frame%2][slot]; NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid]; nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs; int16_t **tx_layers = (int16_t**)dlsch->txdataF; int8_t Wf[2], Wt[2], l0, l_prime[2], delta; - uint8_t dmrs_Type = rel15->dmrsConfigType; - int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4; - uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1; - int16_t mod_dmrs[n_dmrs<<1]; - - uint16_t nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; + int nb_re_dmrs; + uint16_t n_dmrs; + if (rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1) { + nb_re_dmrs = 6*rel15->numDmrsCdmGrpsNoData; + n_dmrs = ((rel15->rbSize+rel15->rbStart)*6)<<1; + } + else { + nb_re_dmrs = 4*rel15->numDmrsCdmGrpsNoData; + n_dmrs = ((rel15->rbSize+rel15->rbStart)*4)<<1; + } + uint16_t nb_re; + nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; uint8_t Qm = rel15->qamModOrder[0]; uint32_t encoded_length = nb_re*Qm; + int16_t mod_dmrs[n_dmrs<<1]; /// CRC, coding, interleaving and rate matching AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n"); @@ -193,11 +202,13 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, /// Modulation start_meas(dlsch_modulation_stats); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, 1); for (int q=0; qNrOfCodewords; q++) nr_modulation(scrambled_output[q], encoded_length, Qm, mod_symbs[q]); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, 0); stop_meas(dlsch_modulation_stats); #ifdef DEBUG_DLSCH printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_re); @@ -297,15 +308,16 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, } else { - - ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; - ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; + if( (l != dmrs_symbol) || allowed_xlsch_re_in_dmrs_symbol(k,start_sc,rel15->numDmrsCdmGrpsNoData,dmrs_Type)) { + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; #ifdef DEBUG_DLSCH_MAPPING - printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", -m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], - ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); + printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", + m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); #endif - m++; + m++; + } } if (++k >= frame_parms->ofdm_symbol_size) k -= frame_parms->ofdm_symbol_size; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h index f48905b68c..3a6851ee8f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h @@ -90,7 +90,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, -void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB); +void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr, uint16_t N_RB); void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index f120864184..2f55bde321 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -36,7 +36,7 @@ #include "PHY/CODING/coding_defs.h" #include "PHY/CODING/lte_interleaver_inline.h" #include "PHY/CODING/nrLDPC_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" @@ -49,7 +49,7 @@ //#define DEBUG_DLSCH_FREE 1 -void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) +void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr, uint16_t N_RB) { int i; int r; @@ -130,7 +130,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) } free16(dlsch,sizeof(NR_gNB_DLSCH_t)); - dlsch = NULL; + *dlschptr = NULL; } } @@ -335,13 +335,19 @@ int nr_dlsch_encoding(unsigned char *a, uint32_t E; uint8_t Ilbrm = 1; uint32_t Tbslbrm = 950984; //max tbs - uint8_t nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4; + uint8_t nb_re_dmrs; + + if (rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1) + nb_re_dmrs = 6*rel15->numDmrsCdmGrpsNoData; + else + nb_re_dmrs = 4*rel15->numDmrsCdmGrpsNoData; + uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos); uint16_t R=rel15->targetCodeRate[0]; float Coderate = 0.0; uint8_t Nl = 4; - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_IN); A = rel15->TBSize[0]<<3; @@ -459,6 +465,9 @@ int nr_dlsch_encoding(unsigned char *a, } + F = dlsch->harq_processes[harq_pid]->F; + + Kr = dlsch->harq_processes[harq_pid]->K; for (r=0; rharq_processes[harq_pid]->C; r++) { if (F>0) { @@ -530,7 +539,7 @@ int nr_dlsch_encoding(unsigned char *a, r_offset += E; } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_OUT); return 0; } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c index 2e6fc707bd..7702d770ee 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c @@ -274,25 +274,7 @@ int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { return first_free_index; } -int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { - uint16_t i; - int16_t first_free_index=-1; - - AssertFatal(gNB!=NULL,"gNB is null\n"); - for (i=0; iulsch[i]!=NULL,"gNB->ulsch[%d] is null\n",i); - AssertFatal(gNB->ulsch[i][0]!=NULL,"gNB->ulsch[%d][0] is null\n",i); - LOG_D(PHY,"searching for rnti %x : ulsch_index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,gNB->ulsch[i][0]->harq_mask,gNB->ulsch[i][0]->rnti,first_free_index); - if ((gNB->ulsch[i][0]->harq_mask >0) && - (gNB->ulsch[i][0]->rnti==rnti)) return i; - else if ((gNB->ulsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i; - } - if (type == SEARCH_EXIST) return -1; - if (first_free_index != -1) - gNB->ulsch[first_free_index][0]->rnti = 0; - return first_free_index; -} void nr_fill_dlsch(PHY_VARS_gNB *gNB, int frame, @@ -316,26 +298,3 @@ void nr_fill_dlsch(PHY_VARS_gNB *gNB, } -void nr_fill_ulsch(PHY_VARS_gNB *gNB, - int frame, - int slot, - nfapi_nr_pusch_pdu_t *ulsch_pdu) { - - - int ulsch_id = find_nr_ulsch(ulsch_pdu->rnti,gNB,SEARCH_EXIST_OR_FREE); - AssertFatal( (ulsch_id>=0) && (ulsch_idrnti,ulsch_id); - - NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ulsch_id][0]; - int harq_pid = ulsch_pdu->pusch_data.harq_process_id; - ulsch->rnti = ulsch_pdu->rnti; - //ulsch->rnti_type; - ulsch->harq_mask |= 1<harq_process_id[slot] = harq_pid; - - memcpy((void*)&ulsch->harq_processes[harq_pid]->ulsch_pdu, (void*)ulsch_pdu, sizeof(nfapi_nr_pusch_pdu_t)); - - LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); - -} - diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index b6a4787193..bc33d93811 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -32,7 +32,7 @@ */ #include "PHY/defs_gNB.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/LTE_REFSIG/lte_refsig.h" #include "PHY/sse_intrin.h" @@ -297,7 +297,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, a_reversed |= (((uint64_t)pbch->pbch_a_prime>>i)&1)<<(31-i); /// CRC, coding and rate matching - polar_encoder_fast (&a_reversed, (uint32_t *)pbch->pbch_e, 0, 0, + polar_encoder_fast (&a_reversed, (void*)pbch->pbch_e, 0, 0, nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0,NULL) ); #ifdef DEBUG_PBCH_ENCODING diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 5c4d048a77..2640a86240 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -31,141 +31,247 @@ */ #include "PHY/defs_gNB.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" -extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; -extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; -extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13]; -extern uint16_t NCS_unrestricted_delta_f_RA_5[16]; -extern uint16_t NCS_restricted_TypeA_delta_f_RA_5[16]; -extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14]; -extern uint16_t NCS_unrestricted_delta_f_RA_15[16]; extern uint16_t prach_root_sequence_map_0_3[838]; extern uint16_t prach_root_sequence_map_abc[138]; -extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; -extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; -extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; +extern const char *prachfmt[9]; + +void init_prach_list(PHY_VARS_gNB *gNB) { + + AssertFatal(gNB!=NULL,"gNB is null\n"); + for (int i=0; iprach_vars.list[i].frame=-1; +} + +int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type) { + + uint16_t i; + int16_t first_free_index=-1; + + AssertFatal(gNB!=NULL,"gNB is null\n"); + for (i=0; i %d.%d numRA %d\n", frame,slot,numRA,i, + gNB->prach_vars.list[i].frame,gNB->prach_vars.list[i].slot,gNB->prach_vars.list[i].pdu.num_ra); + if ((gNB->prach_vars.list[i].frame == frame) && + (gNB->prach_vars.list[i].slot == slot) && + (gNB->prach_vars.list[i].pdu.num_ra == numRA)) return i; + else if ((gNB->prach_vars.list[i].frame == -1) && (first_free_index==-1)) first_free_index=i; + } + if (type == SEARCH_EXIST) return -1; + + return first_free_index; +} + +void nr_fill_prach(PHY_VARS_gNB *gNB, + int SFN, + int Slot, + nfapi_nr_prach_pdu_t *prach_pdu) { + + int prach_id = find_nr_prach(gNB,SFN,Slot,prach_pdu->num_ra,SEARCH_EXIST_OR_FREE); + AssertFatal( (prach_id>=0) && (prach_idnum_ra,prach_id); + + gNB->prach_vars.list[prach_id].frame=SFN; + gNB->prach_vars.list[prach_id].slot=Slot; + memcpy((void*)&gNB->prach_vars.list[prach_id].pdu,(void*)prach_pdu,sizeof(*prach_pdu)); + +} + +void init_prach_ru_list(RU_t *ru) { + + AssertFatal(ru!=NULL,"ruis null\n"); + for (int i=0; iprach_list[i].frame=-1; + pthread_mutex_init(&ru->prach_list_mutex,NULL); +} + +int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type) { + + uint16_t i; + int16_t first_free_index=-1; + + AssertFatal(ru!=NULL,"ru is null\n"); + pthread_mutex_lock(&ru->prach_list_mutex); + for (i=0; i %d.%d\n", frame,slot,i, + ru->prach_list[i].frame,ru->prach_list[i].slot); + if ((ru->prach_list[i].frame == frame) && + (ru->prach_list[i].slot == slot)) { + pthread_mutex_unlock(&ru->prach_list_mutex); + return i; + } + else if ((ru->prach_list[i].frame == -1) && (first_free_index==-1)) first_free_index=i; + } + pthread_mutex_unlock(&ru->prach_list_mutex); + if (type == SEARCH_EXIST) return -1; + + return first_free_index; +} + +void nr_fill_prach_ru(RU_t *ru, + int SFN, + int Slot, + nfapi_nr_prach_pdu_t *prach_pdu) { + + int prach_id = find_nr_prach_ru(ru,SFN,Slot,SEARCH_EXIST_OR_FREE); + AssertFatal( (prach_id>=0) && (prach_idprach_list_mutex); + ru->prach_list[prach_id].frame = SFN; + ru->prach_list[prach_id].slot = Slot; + ru->prach_list[prach_id].fmt = prach_pdu->prach_format; + ru->prach_list[prach_id].numRA = prach_pdu->num_ra; + ru->prach_list[prach_id].prachStartSymbol = prach_pdu->prach_start_symbol; + pthread_mutex_unlock(&ru->prach_list_mutex); + +} + +void free_nr_ru_prach_entry(RU_t *ru, + int prach_id) { + + pthread_mutex_lock(&ru->prach_list_mutex); + ru->prach_list[prach_id].frame=-1; + pthread_mutex_unlock(&ru->prach_list_mutex); + +} + void rx_nr_prach_ru(RU_t *ru, + int prachFormat, + int numRA, + int prachStartSymbol, int frame, - int subframe) { + int slot) { AssertFatal(ru!=NULL,"ru is null\n"); int16_t **rxsigF=NULL; NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms; - int16_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; + int slot2=slot; + int16_t *prach[ru->nb_rx]; - uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); + int prach_sequence_length = ru->config.prach_config.prach_sequence_length.value; + + int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[numRA].k1.value; rxsigF = ru->prach_rxsigF; AssertFatal(ru->if_south == LOCAL_RF,"we shouldn't call this if if_south != LOCAL_RF\n"); - for (int aa=0; aanb_rx; aa++) - prach[aa] = (int16_t*)&ru->common.rxdata[aa][(subframe*fp->samples_per_subframe)-ru->N_TA_offset]; - + for (int aa=0; aanb_rx; aa++){ + if (prach_sequence_length == 0) slot2=(slot/fp->slots_per_subframe)*fp->slots_per_subframe; + prach[aa] = (int16_t*)&ru->common.rxdata[aa][(slot2*fp->get_samples_per_slot(slot,fp))-ru->N_TA_offset]; + } + int dftlen=0; int mu = fp->numerology_index; - int Ncp; + int Ncp = 0; int16_t *prach2; - - switch (prach_fmt) { - case 0: - Ncp = 3168; - break; - - case 1: - Ncp = 21024; - break; - - case 2: - Ncp = 4688; - break; - - case 3: - Ncp = 3168; - break; - - case 0xa1: - Ncp = 288/(1<idx,frame,slot2,prachFormat,msg1_frequencystart); + AssertFatal(prachFormat<4,"Illegal prach format %d for length 839\n",prachFormat); + switch (prachFormat) { + case 0: + Ncp = 3168; + break; + + case 1: + Ncp = 21024; + break; + + case 2: + Ncp = 4688; + break; + + case 3: + Ncp = 3168; + break; + + } } + else { + LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %s, msg1_frequencyStart %d,startSymbol %d\n", + ru->idx,frame,slot,prachfmt[prachFormat],msg1_frequencystart,prachStartSymbol); + switch (prachFormat) { + case 0: //A1 + Ncp = 288/(1<N_RB_UL, ru->nb_rx, Ncp); + LOG_D(PHY,"rx_prach: Doing PRACH FFT for nb_rx:%d Ncp:%d\n",ru->nb_rx, Ncp); } AssertFatal(mu==1,"only 30 kHz SCS handled for now\n"); // Note: Assumes PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below int kbar = 1; int K = 24; - if (prach_fmt == 3) { + if (prach_sequence_length == 0 && prachFormat == 3) { K=4; kbar=10; } - else if (prach_fmt > 3) { + else if (prach_sequence_length == 1) { // Note: Assumes that PRACH SCS is same as PUSCH SCS K=1; kbar=2; } - int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; + int n_ra_prb = msg1_frequencystart; int k = (12*n_ra_prb) - 6*fp->N_RB_UL; - int N_ZC = (prach_fmt<4)?839:139; + int N_ZC = (prach_sequence_length==0)?839:139; if (k<0) k+=(fp->ofdm_symbol_size); k*=K; k+=kbar; int reps=1; - int dftlen=0; for (int aa=0; aanb_rx; aa++) { AssertFatal(prach[aa]!=NULL,"prach[%d] is null\n",aa); - // do DFT if (fp->N_RB_UL <= 100) AssertFatal(1==0,"N_RB_UL %d not support for NR PRACH yet\n",fp->N_RB_UL); @@ -173,175 +279,232 @@ void rx_nr_prach_ru(RU_t *ru, if (fp->threequarter_fs==0) { //40 MHz @ 61.44 Ms/s //50 MHz @ 61.44 Ms/s - prach2 = prach[aa] + (Ncp<<2); - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - dft(DFT_49152,prach2,rxsigF[aa],1); - if (prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1); - reps++; - } - if (prach_fmt == 2) { - dft(DFT_49152,prach2+(98304*2),rxsigF[aa]+(98304*2),1); - dft(DFT_49152,prach2+(98304*3),rxsigF[aa]+(98304*3),1); - reps+=2; - } - if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft(DFT_12288,prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); - reps=4; - } - if (prach_fmt >3) { - dft(DFT_2048,prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { - dft(DFT_2048,prach2+4096,rxsigF[aa]+4096,1); + prach2 = prach[aa] + (Ncp<<2); // Ncp is for 30.72 Ms/s, so multiply by 2 for I/Q, and 2 to bring to 61.44 Ms/s + if (prach_sequence_length == 0) { + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { + dftlen=49152; + dft(DFT_49152,prach2,rxsigF[aa],1); + } + if (prachFormat == 1 || prachFormat == 2) { + dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft(DFT_2048,prach2+4096*2,rxsigF[aa]+4096*2,1); - dft(DFT_2048,prach2+4096*3,rxsigF[aa]+4096*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft(DFT_2048,prach2+4096*4,rxsigF[aa]+4096*4,1); - dft(DFT_2048,prach2+4096*5,rxsigF[aa]+4096*5,1); - reps+=2; - } - if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft(DFT_2048,prach2+(3072*i),rxsigF[aa]+(3072*i),1); - reps+=6; + if (prachFormat == 2) { + dft(DFT_49152,prach2+(98304*2),rxsigF[aa]+(98304*2),1); + dft(DFT_49152,prach2+(98304*3),rxsigF[aa]+(98304*3),1); + reps+=2; + } + if (prachFormat == 3) { + dftlen=12288; + for (int i=0;i<4;i++) dft(DFT_12288,prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); + reps=4; + } + }// 839 sequence + else { + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=64; // 32 samples @ 61.44 Ms/s in first symbol of each half subframe (15/30 kHz only) + + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=2048; + dft(DFT_2048,prach2,rxsigF[aa],1); + if (prachFormat != 7) { // !=C0 + dft(DFT_2048,prach2+4096,rxsigF[aa]+4096,1); + reps++; + } + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft(DFT_2048,prach2+4096*2,rxsigF[aa]+4096*2,1); + dft(DFT_2048,prach2+4096*3,rxsigF[aa]+4096*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft(DFT_2048,prach2+4096*4,rxsigF[aa]+4096*4,1); + dft(DFT_2048,prach2+4096*5,rxsigF[aa]+4096*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft(DFT_2048,prach2+(4096*i),rxsigF[aa]+(4096*i),1); + reps+=6; + } + } + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } - } else { + } else { // threequarter sampling // 40 MHz @ 46.08 Ms/s - prach2 = prach[aa] + (3*Ncp); - AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_36864,prach2,rxsigF[aa],1); - reps++; - } - if (prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_36864,prach2+73728,rxsigF[aa]+73728,1); - reps++; - } - if (prach_fmt == 2) { - dft(DFT_36864,prach2+(98304*2),rxsigF[aa]+(98304*2),1); - dft(DFT_36864,prach2+(98304*3),rxsigF[aa]+(98304*3),1); - reps+=2; - } - if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft(DFT_9216,prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); - reps=4; - } - if (prach_fmt >3) { - dft(DFT_1536,prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { - dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1); + prach2 = prach[aa] + (3*Ncp); // 46.08 is 1.5 * 30.72, times 2 for I/Q + if (prach_sequence_length == 0) { + AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { + dftlen=36864; + dft(DFT_36864,prach2,rxsigF[aa],1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft(DFT_1536,prach2+3072*2,rxsigF[aa]+3072*2,1); - dft(DFT_1536,prach2+3072*3,rxsigF[aa]+3072*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft(DFT_1536,prach2+3072*4,rxsigF[aa]+3072*4,1); - dft(DFT_1536,prach2+3072*5,rxsigF[aa]+3072*5,1); - reps+=2; - } - if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft(DFT_1536,prach2+(3072*i),rxsigF[aa]+(3072*i),1); - reps+=6; - } - } - } + if (prachFormat == 1 || prachFormat == 2) { + dft(DFT_36864,prach2+73728,rxsigF[aa]+73728,1); + reps++; + } + if (prachFormat == 2) { + dft(DFT_36864,prach2+(73728*2),rxsigF[aa]+(73728*2),1); + dft(DFT_36864,prach2+(73728*3),rxsigF[aa]+(73728*3),1); + reps+=2; + } + if (prachFormat == 3) { + dftlen=9216; + for (int i=0;i<4;i++) dft(DFT_9216,prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); + reps=4; + } + } else { + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=48; // 24 samples @ 46.08 Ms/s in first symbol of each half subframe (15/30 kHz only) + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=1536; + dft(DFT_1536,prach2,rxsigF[aa],1); + if (prachFormat != 7) { + dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1); + reps++; + } + + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft(DFT_1536,prach2+3072*2,rxsigF[aa]+3072*2,1); + dft(DFT_1536,prach2+3072*3,rxsigF[aa]+3072*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft(DFT_1536,prach2+3072*4,rxsigF[aa]+3072*4,1); + dft(DFT_1536,prach2+3072*5,rxsigF[aa]+3072*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft(DFT_1536,prach2+(3072*i),rxsigF[aa]+(3072*i),1); + reps+=6; + } + }// mu==1 + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); + } // short format + } // 3/4 sampling + } // <=50 MHz BW else if (fp->N_RB_UL <= 273) { if (fp->threequarter_fs==0) { prach2 = prach[aa] + (Ncp<<3); - dftlen=98304; - //80,90,100 MHz @ 61.44 Ms/s - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - dft(DFT_98304,prach2,rxsigF[aa],1); - if (prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1); - reps++; - } - if (prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1); - dft(DFT_98304,prach2+(196608*2),rxsigF[aa]+(196608*2),1); - reps+=2; - } - if (prach_fmt == 3) { - dft(DFT_24576,prach2+(2*49152),rxsigF[aa]+(2*49152),1); - reps=4; - dftlen=24576; - } - if (prach_fmt >3) { - dftlen=4096; - dft(DFT_4096,prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { - dft(DFT_4096,prach2+8192,rxsigF[aa]+8192,1); + //80,90,100 MHz @ 122.88 Ms/s + + if (prach_sequence_length == 0) { + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { + dftlen=98304; + dft(DFT_98304,prach2,rxsigF[aa],1); + } + if (prachFormat == 1 || prachFormat == 2) { + dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft(DFT_4096,prach2+8192*2,rxsigF[aa]+8192*2,1); - dft(DFT_4096,prach2+8192*3,rxsigF[aa]+8192*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft(DFT_4096,prach2+8192*4,rxsigF[aa]+8192*4,1); - dft(DFT_4096,prach2+8192*5,rxsigF[aa]+8192*5,1); - reps+=2; - } - if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft(DFT_4096,prach2+(8192*i),rxsigF[aa]+(8192*i),1); - reps+=6; + if (prachFormat == 2) { + dft(DFT_98304,prach2+(196608*2),rxsigF[aa]+(196608*2),1); + dft(DFT_98304,prach2+(196608*3),rxsigF[aa]+(196608*3),1); + reps+=2; + } + if (prachFormat == 3) { + dftlen=24576; + for (int i=0;i<4;i++) dft(DFT_24576,prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1); + reps=4; + } + } + else { + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=128; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only) + + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=4096; + dft(DFT_4096,prach2,rxsigF[aa],1); + if (prachFormat != 7) { //!=C0 + dft(DFT_4096,prach2+8192,rxsigF[aa]+8192,1); + reps++; + } + + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft(DFT_4096,prach2+8192*2,rxsigF[aa]+8192*2,1); + dft(DFT_4096,prach2+8192*3,rxsigF[aa]+8192*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft(DFT_4096,prach2+8192*4,rxsigF[aa]+8192*4,1); + dft(DFT_4096,prach2+8192*5,rxsigF[aa]+8192*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft(DFT_4096,prach2+(8192*i),rxsigF[aa]+(8192*i),1); + reps+=6; + } + } + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } } else { AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n"); prach2 = prach[aa] + (6*Ncp); - // 80 MHz @ 46.08 Ms/s - dftlen=73728; - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_73728,prach2,rxsigF[aa],1); - reps++; - } - if (prach_fmt == 1 || prach_fmt == 2) { - dft(DFT_73728,prach2+(2*73728),rxsigF[aa]+(2*73728),1); - reps++; - } - if (prach_fmt == 3) { - dft(DFT_73728,prach2+(4*73728),rxsigF[aa]+(4*73728),1); - reps=4; - dftlen=18432; - } - - if (prach_fmt >3) { - dftlen=3072; - dft(DFT_3072,prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { - dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1); + // 80 MHz @ 92.16 Ms/s + if (prach_sequence_length == 0) { + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { + dftlen=73728; + dft(DFT_73728,prach2,rxsigF[aa],1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft(DFT_3072,prach2+6144*2,rxsigF[aa]+6144*2,1); - dft(DFT_3072,prach2+6144*3,rxsigF[aa]+6144*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { - dft(DFT_3072,prach2+6144*4,rxsigF[aa]+6144*4,1); - dft(DFT_3072,prach2+6144*5,rxsigF[aa]+6144*5,1); - reps+=2; - } - if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft(DFT_3072,prach2+(6144*i),rxsigF[aa]+(6144*i),1); - reps+=6; + if (prachFormat == 1 || prachFormat == 2) { + dft(DFT_73728,prach2+(2*73728),rxsigF[aa]+(2*73728),1); + reps++; + } + if (prachFormat == 3) { + dftlen=18432; + for (int i=0;i<4;i++) dft(DFT_18432,prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1); + reps=4; + } + } else { + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=96; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only) + + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=3072; + dft(DFT_3072,prach2,rxsigF[aa],1); + if (prachFormat != 7) { //!=C0 + dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1); + reps++; + } + + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft(DFT_3072,prach2+6144*2,rxsigF[aa]+6144*2,1); + dft(DFT_3072,prach2+6144*3,rxsigF[aa]+6144*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft(DFT_3072,prach2+6144*4,rxsigF[aa]+6144*4,1); + dft(DFT_3072,prach2+6144*5,rxsigF[aa]+6144*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft(DFT_3072,prach2+(6144*i),rxsigF[aa]+(6144*i),1); + reps+=6; + } + } + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } } } //Coherent combining of PRACH repetitions (assumes channel does not change, to be revisted for "long" PRACH) + LOG_D(PHY,"Doing PRACH combining of %d reptitions N_ZC %d\n",reps,N_ZC); int16_t rxsigF_tmp[N_ZC<<1]; // if (k+N_ZC > dftlen) { // PRACH signal is split around DC int16_t *rxsigF2=rxsigF[aa]; @@ -350,7 +513,7 @@ void rx_nr_prach_ru(RU_t *ru, for (int j=0;jgNB_config.prach_config; NR_DL_FRAME_PARMS *fp; - lte_frame_type_t frame_type; + uint16_t rootSequenceIndex; - uint8_t prach_ConfigIndex; - uint8_t Ncs_config; + int numrootSequenceIndex; uint8_t restricted_set; uint8_t n_ra_prb; int16_t *prachF=NULL; @@ -404,59 +568,35 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32))); int32_t *prach_ifft=(int32_t*)NULL; - nr_frequency_range_e freq_range; + fp = &gNB->frame_parms; - fp = &gNB->frame_parms; - nb_rx = fp->nb_antennas_rx; + nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value; - frame_type = fp->frame_type; - freq_range = fp->freq_range; - rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; - prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; - + rootSequenceIndex = cfg->num_prach_fd_occasions_list[0].prach_root_sequence_index.value; + numrootSequenceIndex = cfg->num_prach_fd_occasions_list[0].num_root_sequences.value; + NCS = prach_pdu->num_cs;//cfg->num_prach_fd_occasions_list[0].prach_zero_corr_conf.value; + int prach_sequence_length = cfg->prach_sequence_length.value; - uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,freq_range); - uint16_t N_ZC = (prach_fmt <4)?839:139; + int msg1_frequencystart = cfg->num_prach_fd_occasions_list[0].k1.value; + // int num_unused_root_sequences = cfg->num_prach_fd_occasions_list[0].num_unused_root_sequences.value; + // cfg->num_prach_fd_occasions_list[0].unused_root_sequences_list + + restricted_set = cfg->restricted_set_config.value; + + uint8_t prach_fmt = prach_pdu->prach_format; + uint16_t N_ZC = (prach_sequence_length==0)?839:139; + + LOG_D(PHY,"L1 PRACH RX: rooSequenceIndex %d, numRootSeqeuences %d, NCS %d, N_ZC %d \n", rootSequenceIndex,numrootSequenceIndex,NCS,N_ZC); prach_ifft = gNB->prach_vars.prach_ifft; prachF = gNB->prach_vars.prachF; if (LOG_DEBUGFLAG(PRACH)){ - if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, prach_ConfigIndex %d , rootSequenceIndex %d\n", subframe,fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart,prach_ConfigIndex,rootSequenceIndex); + if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, rootSequenceIndex %d\n", subframe,msg1_frequencystart,rootSequenceIndex); } - - - - - - int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - if (prach_fmt<3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt==3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt>3){ - NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; - } - - AssertFatal(NCS!=99,"NCS has not been set\n"); - start_meas(&gNB->rx_prach); - prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; + prach_root_sequence_map = (cfg->prach_sequence_length.value==0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; // PDP is oversampled, e.g. 1024 sample instead of 839 // Adapt the NCS (zero-correlation zones) with oversampling factor e.g. 1024/839 @@ -469,16 +609,19 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, *max_preamble_energy=0; + *max_preamble_delay=0; + *max_preamble=0; + for (preamble_index=0 ; preamble_index<64 ; preamble_index++) { if (LOG_DEBUGFLAG(PRACH)){ int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); - if (en>60) LOG_I(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index); + if (en>60) LOG_D(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index); } if (restricted_set == 0) { // This is the relative offset in the root sequence table (5.7.2-4 from 36.211) for the given preamble index preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); - + if (preamble_offset != preamble_offset_old) { preamble_offset_old = preamble_offset; new_dft = 1; @@ -508,13 +651,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // current root depending on rootSequenceIndex int index = (rootSequenceIndex + preamble_offset) % N_ZC; - if (prach_fmt<4) { - // prach_root_sequence_map points to prach_root_sequence_map0_3 - DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); - } else { - // prach_root_sequence_map points to prach_root_sequence_map4 - DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); - } u = prach_root_sequence_map[index]; uint16_t n_group_ra = 0; @@ -559,14 +695,21 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // Compute DFT of RX signal (conjugate input, results in conjugate output) for each new rootSequenceIndex if (LOG_DEBUGFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); - if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, NCS_config %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", - frame,subframe,preamble_index,NCS,Ncs_config,N_ZC/NCS,preamble_offset,preamble_shift,en); + if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", + frame,subframe,preamble_index,NCS,N_ZC/NCS,preamble_offset,preamble_shift,en); } + LOG_D(PHY,"PRACH RX preamble_index %d, preamble_offset %d\n",preamble_index,preamble_offset); + + if (new_dft == 1) { new_dft = 0; Xu=(int16_t*)gNB->X_u[preamble_offset-first_nonzero_root_idx]; + + LOG_D(PHY,"PRACH RX new dft preamble_offset-first_nonzero_root_idx %d\n",preamble_offset-first_nonzero_root_idx); + + memset(prach_ifft,0,((N_ZC==839) ? 2048 : 256)*sizeof(int32_t)); @@ -590,32 +733,31 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, idft(IDFT_1024,prachF,prach_ifft_tmp,1); // compute energy and accumulate over receive antennas for (i=0;i<2048;i++) - prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[i<<1] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; + prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[i<<1] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10; } else { idft(IDFT_256,prachF,prach_ifft_tmp,1); log2_ifft_size = 8; // compute energy and accumulate over receive antennas and repetitions for BR for (i=0;i<256;i++) - prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[(i<<1)] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; + prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[(i<<1)] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10; } - if (LOG_DUMPFLAG(PRACH)) { + if (LOG_DUMPFLAG(PRACH)) { if (aa==0) LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); if (aa==1) LOG_M("prach_rxF_comp1.m","prach_rxF_comp1",prachF,1024,1,1); - } + } }// antennas_rx } // new dft // check energy in nth time shift, for preamble_shift2 = ((preamble_shift==0) ? 0 : ((preamble_shift<*max_preamble_energy) { + LOG_D(PHY,"preamble_index %d, delay %d en %d dB > %d dB\n",preamble_index,i,levdB,*max_preamble_energy); *max_preamble_energy = levdB; *max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate *max_preamble = preamble_index; @@ -623,9 +765,34 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, } }// preamble_index + + // The conversion from *max_preamble_delay from TA value is done here. + // It is normalized to the 30.72 Ms/s, considering the numerology, N_RB and the sampling rate + // See table 6.3.3.1 -1 and -2 in 38211. + + // Format 0, 1, 2: 24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s + // By solving: + // max_preamble_delay * ( (24576*(fs/30.72M)) / 1024 ) / fs = TA * 16 * 64 / 2^mu * Tc + + // Format 3: 6144 samples @ 30.72 Ms/s, 24576 samples @ 122.88 Ms/s + // By solving: + // max_preamble_delay * ( (6144*(fs/30.72M)) / 1024 ) / fs = TA * 16 * 64 / 2^mu * Tc + + // Format >3: 2048/2^mu samples @ 30.72 Ms/s, 2048/2^mu * 4 samples @ 122.88 Ms/s + // By solving: + // max_preamble_delay * ( (2048/2^mu*(fs/30.72M)) / 256 ) / fs = TA * 16 * 64 / 2^mu * Tc + uint16_t *TA = max_preamble_delay; + int mu = fp->numerology_index; + if (cfg->prach_sequence_length.value==0) { + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) *TA = *TA*3*(1<60) { + //int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); + // if (en>60) { int k = (12*n_ra_prb) - 6*fp->N_RB_UL; if (k<0) k+=fp->ofdm_symbol_size; @@ -639,9 +806,9 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); LOG_M("Xu.m","xu",Xu,N_ZC,1,1); LOG_M("prach_ifft0.m","prach_t0",prach_ifft,1024,1,1); - } + // } } /* LOG_DUMPFLAG(PRACH) */ - if (gNB) stop_meas(&gNB->rx_prach); + stop_meas(&gNB->rx_prach); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.h b/openair1/PHY/NR_TRANSPORT/nr_prach.h index 1e2b758035..d158e04c79 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.h +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.h @@ -37,18 +37,6 @@ uint16_t nr_du[838]; /************************************* * The following tables defined for NR **************************************/ -// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz -uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419}; -uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A -uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B - -// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz -uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419}; -uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A -uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B - -// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} -uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; //Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 uint16_t prach_root_sequence_map_0_3[838] = { @@ -105,787 +93,3 @@ uint16_t prach_root_sequence_map_abc[138] = { 51, 88 , 52, 87 , 53, 86 , 54, 85 , 55, 84 , 56, 83 , 57, 82 , 58, 81 , 59, 80 , 60, 79 , 61, 78 , 62, 77 , 63, 76 , 64, 75 , 65, 74 , 66, 73 , 67, 72 , 68, 71 , 69, 70 }; - -// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink -// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. -// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. -// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6 -int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = { -//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 -{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 -{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 -{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9 -{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 -{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 -{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 -{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 -{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 -{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 -{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 -{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4 -{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6 -{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 -{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 -{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7 -{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7 -{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8 -{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9 -{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 -{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 -{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 -{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7 -{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 -{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 -{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9 -{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 -{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 -{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 -{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 -{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 -{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 -{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9 -{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 -{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 -{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 -{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 -{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 -{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 -{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6 -{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7 -{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7 -{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8 -{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9 -{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 -{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 -{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 -{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9 -}; -// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum -int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = { -//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) -{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) -{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) -{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) -{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) -{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) -{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) -{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) -{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) -{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) -{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) -{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) -{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) -{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) -{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) -{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9) -{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) -{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) -{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6) -{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6) -{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6) -{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) -{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) -{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) -{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) -{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) -{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) -{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) -{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) -{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) -{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) -{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) -{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) -{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) -{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) -{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) -{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) -{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) -{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9) -{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9) -{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9) -{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9) -{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9) -{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) -{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9) -{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9) -{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9) -{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9) -{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9) -{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9) -{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) -{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9) -{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2) -{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7) -{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7) -{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) -{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9) -{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) -{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9) -{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9) -{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) -{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) -{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) -{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2) -{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7) -{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7) -{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) -{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9) -{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9) -{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9) -{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9) -{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1) -{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2) -{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4) -{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7) -{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9) -{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9) -{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9) -{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9) -{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) -{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9) -{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9) -{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9) -{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9) -{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9) -{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) -{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9) -{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9) -{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9) -{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9) -{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9) -{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9) -{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9) -{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) -{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9) -}; -// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum -int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { -//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39) -{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7) -{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39) -{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39) -{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7) -{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39) -{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39) -{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39) -{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39) -{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13) -{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13) -{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) -{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39) -{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39) -{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) -{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13) -{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) -{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13) -{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) -{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) -{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) -{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7) -{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xb4, -1, 16, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 16, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 8, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 8, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 4, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 4, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39) -{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39) -{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39) -{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19) -{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13) -{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 586406201480, 2, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) -{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) -{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39) -{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39) -{0xc0, -1, 16, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 16, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 8, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 8, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 8, 1, 2, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 4, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 4, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39) -{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7) -{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39) -{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39) -{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39) -{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) -{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) -{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) -{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) -{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) -{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) -{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39) -{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xa2, 0xb2, 16, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39) -{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39) -{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39) -{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39) -{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) -{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) -{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39) -}; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index e1b80a87a2..a95c519d43 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -34,15 +34,15 @@ #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_UE.h" #include "PHY/NR_TRANSPORT/nr_prach.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" - +#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "T.h" -void init_nr_prach_tables(int N_ZC); -void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { + +/*void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { FILE *fd; @@ -76,23 +76,13 @@ void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { fprintf(fd,"prach_config: n_ra_prboffset = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.msg1_frequencystart); fclose(fd); -} +}*/ // This function computes the du -void nr_fill_du(uint8_t prach_fmt) +void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) { uint16_t iu,u,p; - uint16_t N_ZC; - uint16_t *prach_root_sequence_map; - - if (prach_fmt<4) { - N_ZC = 839; - prach_root_sequence_map = prach_root_sequence_map_0_3; - } else { - N_ZC = 139; - prach_root_sequence_map = prach_root_sequence_map_abc; - } for (iu=0; iu<(N_ZC-1); iu++) { @@ -107,214 +97,49 @@ void nr_fill_du(uint8_t prach_fmt) } -int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) { - - uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - /* - // For FR1 paired - if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && - ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<slots_per_subframe; - // when were in the last slot of the subframe and this is a PRACH subframe ,return 1 - if (((slot%fp->slots_per_subframe) == fp->slots_per_subframe-1)&& - (is_nr_prach_subframe(fp,frame,subframe))) return (1); - else return(0); -} - -uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr) -{ - - if (frame_type==FDD) return (table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink - else if (fr==nr_FR1) return (table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum - else AssertFatal(1==0,"FR2 prach configuration not supported yet\n"); - // For FR2 not implemented. FIXME -} - -void compute_nr_prach_seq(uint16_t rootSequenceIndex, - uint8_t prach_ConfigIndex, - uint8_t zeroCorrelationZoneConfig, - uint8_t highSpeedFlag, - lte_frame_type_t frame_type, - nr_frequency_range_e fr, - uint32_t X_u[64][839]) -{ +void compute_nr_prach_seq(uint8_t short_sequence, + uint8_t num_sequences, + uint8_t rootSequenceIndex, + uint32_t X_u[64][839]){ // Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC) - unsigned int k,inv_u,i,NCS=0,num_preambles; + unsigned int k,inv_u,i; int N_ZC; - uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,fr); + uint16_t *prach_root_sequence_map; - uint16_t u, preamble_offset; - uint16_t n_shift_ra,n_shift_ra_bar, d_start,numshift; - uint8_t not_found; + uint16_t u; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN); -#ifdef NR_PRACH_DEBUG - LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach_fmt %x\n",zeroCorrelationZoneConfig, prach_fmt); -#endif + LOG_D(PHY,"compute_prach_seq: prach short sequence %x, num_sequences %d, rootSequenceIndex %d\n", short_sequence, num_sequences, rootSequenceIndex); - - N_ZC = (prach_fmt < 4) ? 839 : 139; + N_ZC = (short_sequence) ? 139 : 839; //init_prach_tables(N_ZC); //moved to phy_init_lte_ue/eNB, since it takes to long in real-time init_nr_prach_tables(N_ZC); - if (prach_fmt < 4) { - prach_root_sequence_map = prach_root_sequence_map_0_3; - } else { + if (short_sequence) { // FIXME cannot be reached prach_root_sequence_map = prach_root_sequence_map_abc; - } - - -#ifdef PRACH_DEBUG - LOG_I( PHY, "compute_prach_seq: done init prach_tables\n" ); -#endif - - - - - int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - - if (highSpeedFlag== 0) { - -#ifdef PRACH_DEBUG - LOG_I(PHY,"Low speed prach : NCS_config %d\n",zeroCorrelationZoneConfig); -#endif - - AssertFatal(zeroCorrelationZoneConfig<=15, - "FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig]; - if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig]; - if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig]; - - num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC); - - if (NCS>0) num_preambles++; - - preamble_offset = 0; } else { - -#ifdef PRACH_DEBUG - LOG_I( PHY, "high speed prach : NCS_config %"PRIu8"\n", zeroCorrelationZoneConfig ); -#endif - - AssertFatal(zeroCorrelationZoneConfig<=14, - "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - if (prach_fmt<3){ - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME - } - if (prach_fmt==3){ - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME - } - if (prach_fmt>3){ - - } - - nr_fill_du(prach_fmt); - - num_preambles = 64; // compute ZC sequence for 64 possible roots - // find first non-zero shift root (stored in preamble_offset) - not_found = 1; - preamble_offset = 0; - - while (not_found == 1) { - // current root depending on rootSequenceIndex - int index = (rootSequenceIndex + preamble_offset) % N_ZC; - - if (prach_fmt<4) { - // prach_root_sequence_map points to prach_root_sequence_map0_3 - DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); - } else { - // prach_root_sequence_map points to prach_root_sequence_map4 - DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); - } - - u = prach_root_sequence_map[index]; - - uint16_t n_group_ra = 0; - - if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { - n_shift_ra = nr_du[u]/NCS; - d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); - n_group_ra = N_ZC/d_start; - n_shift_ra_bar = max(0,(N_ZC-(nr_du[u]<<1)-(n_group_ra*d_start))/N_ZC); - } else if ( (nr_du[u]>=(N_ZC/3)) && (nr_du[u]<=((N_ZC - NCS)>>1)) ) { - n_shift_ra = (N_ZC - (nr_du[u]<<1))/NCS; - d_start = N_ZC - (nr_du[u]<<1) + (n_shift_ra * NCS); - n_group_ra = nr_du[u]/d_start; - n_shift_ra_bar = min(n_shift_ra,max(0,(nr_du[u]- (n_group_ra*d_start))/NCS)); - } else { - n_shift_ra = 0; - n_shift_ra_bar = 0; - } - - // This is the number of cyclic shifts for the current root u - numshift = (n_shift_ra*n_group_ra) + n_shift_ra_bar; - - // skip to next root and recompute parameters if numshift==0 - if (numshift>0) - not_found = 0; - else - preamble_offset++; - } + prach_root_sequence_map = prach_root_sequence_map_0_3; } -#ifdef PRACH_DEBUG + LOG_D( PHY, "compute_prach_seq: done init prach_tables\n" ); - if (NCS>0) - LOG_I( PHY, "Initializing %u preambles for PRACH (NCS_config %"PRIu8", NCS %u, N_ZC/NCS %u)\n", - num_preambles, zeroCorrelationZoneConfig, NCS, N_ZC/NCS ); + for (i=0; i u=%d\n",index,u); inv_u = nr_ZC_inv[u]; // multiplicative inverse of u @@ -322,8 +147,8 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, // for the unrestricted case X_u[0] is the first root indicated by the rootSequenceIndex for (k=0; k -#include "nfapi_interface.h" - -// Functions below implement 36-211 and 36-212 - -/** @addtogroup _PHY_TRANSPORT_ - * @{ - */ - -void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); - -int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue, - unsigned char eNB_id, - uint8_t subframe, - unsigned char symbol); - -/** \brief Dump OCTAVE/MATLAB files for PMCH debugging - @param phy_vars_ue Pointer to UE variables - @param eNB_id index of eNB in ue variables - @param coded_bits_per_codeword G from 36.211 - @param subframe Index of subframe - @returns 0 on success -*/ -void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe); - - - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qpsk_qpsk(int16_t *stream0_in, - int16_t *stream1_in, - int16_t *stream0_out, - int16_t *rho01, - int32_t length); - -/** \brief This function perform LLR computation for dual-stream (QPSK/QPSK) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr*/ -int32_t nr_dlsch_qpsk_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint16_t pbch_pss_sss_adj, - int16_t **llr128p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qpsk_qam16(int16_t *stream0_in, - int16_t *stream1_in, - short *ch_mag_i, - int16_t *stream0_out, - int16_t *rho01, - int32_t length); - -/** \brief This function perform LLR computation for dual-stream (QPSK/16QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr*/ -int32_t nr_dlsch_qpsk_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t symbol, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint16_t pbch_pss_sss_adj, - int16_t **llr128p); - - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qpsk_qam64(int16_t *stream0_in, - int16_t *stream1_in, - short *ch_mag_i, - int16_t *stream0_out, - int16_t *rho01, - int32_t length); - -/** \brief This function perform LLR computation for dual-stream (QPSK/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr*/ -int32_t nr_dlsch_qpsk_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t symbol, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint16_t pbch_pss_sss_adj, - int16_t **llr128p); - - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/QPSK reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam16_qpsk(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *stream0_out, - short *rho01, - int length); -/** \brief This function perform LLR computation for dual-stream (16QAM/QPSK) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_16qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam16_qam16(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (16QAM/16QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_16qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - uint32_t len, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam16_qam64(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (16QAM/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_16qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qpsk(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_64qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam16(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam16_avx2(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (64QAM/16QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_64qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, - int **dl_ch_mag_i, - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam64(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam64_avx2(int32_t *stream0_in, - int32_t *stream1_in, - int32_t *ch_mag, - int32_t *ch_mag_i, - int16_t *stream0_out, - int32_t *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_64qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, - int **dl_ch_mag_i, - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - uint32_t len, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - //short **llr16p, - uint32_t llr_offset); - - -/** \brief This function generates log-likelihood ratios (decoder input) for single-stream QPSK received waveforms. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr - @param beamforming_mode beamforming mode -*/ -int32_t nr_dlsch_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int16_t *dlsch_llr, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint8_t beamforming_mode); - -/** - \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dlsch_llr llr output - @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation and weighted for mid-point in 16QAM constellation - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adjust Adjustment factor in RE for PBCH/PSS/SSS allocations - @param llr128p pointer to pointer to symbol in dlsch_llr - @param beamforming_mode beamforming mode -*/ - -int32_t nr_dlsch_qpsk_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int32_t **sic_buffer, - int **rho_i, - short *dlsch_llr, - uint8_t num_pdcch_symbols, - uint16_t nb_rb, - uint8_t subframe, - uint16_t mod_order_0, - uint32_t rb_alloc); - -void nr_dlsch_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int16_t *dlsch_llr, - int32_t **dl_ch_mag, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - int16_t **llr32p, - uint8_t beamforming_mode); -/** - \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dlsch_llr llr output - @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by first mid-point of 64-QAM constellation - @param dl_ch_magb Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by second mid-point of 64-QAM constellation - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adjust PBCH/PSS/SSS RE adjustment (in REs) - @param beamforming_mode beamforming mode -*/ -void nr_dlsch_16qam_llr_SIC (NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **sic_buffer, //Q15 - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t num_pdcch_symbols, - int32_t **dl_ch_mag, - uint16_t nb_rb, - uint8_t subframe, - uint16_t mod_order_0, - uint32_t rb_alloc); - -void dlsch_64qam_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **sic_buffer, //Q15 - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t num_pdcch_symbols, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint16_t nb_rb, - uint8_t subframe, - uint16_t mod_order_0, - uint32_t rb_alloc); - -void nr_dlsch_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int16_t *dlsch_llr, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint32_t llr_offset, - uint8_t beamforming_mode); - - -/** \fn dlsch_siso(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - uint8_t l, - uint16_t nb_rb) - \brief This function does the first stage of llr computation for SISO, by just extracting the pilots, PBCH and primary/secondary synchronization sequences. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param l symbol in sub-frame - @param nb_rb Number of RBs in this allocation -*/ - -void dlsch_siso(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - uint8_t l, - uint16_t nb_rb); - -/** \fn dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb) - \brief This function does Alamouti combining on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param symbol Symbol in sub-frame - @param nb_rb Number of RBs in this allocation -*/ -void dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb); - -/** \fn dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb) - \brief This function does antenna selection (based on antenna cycling pattern) on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. Note that this is not LTE, it is just included for comparison purposes. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param symbol Symbol in sub-frame - @param nb_rb Number of RBs in this allocation -*/ -void dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb); - -/** \fn dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int32_t **rho, - int32_t **rho_i, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb, - uint8_t dual_stream_UE) - - \brief This function does maximal-ratio combining for dual-antenna receivers. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho Cross correlation between spatial channels - @param rho_i Cross correlation between signal and inteference channels - @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param symbol Symbol in sub-frame - @param nb_rb Number of RBs in this allocation - @param dual_stream_UE Flag to indicate dual-stream detection -*/ -void dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int32_t **rho, - int32_t **rho_i, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - int32_t **dl_ch_mag_i, - int32_t **dl_ch_magb_i, - uint8_t symbol, - uint16_t nb_rb, - uint8_t dual_stream_UE); - -void dlsch_detection_mrc_TM34(NR_DL_FRAME_PARMS *frame_parms, - NR_UE_PDSCH *lte_ue_pdsch_vars, - int harq_pid, - int round, - unsigned char symbol, - unsigned short nb_rb, - unsigned char dual_stream_UE); - -/** \fn dlsch_extract_rbs_single(int32_t **rxdataF, - int32_t **dl_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - uint16_t pmi, - uint8_t *pmi_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - NR_DL_FRAME_PARMS *frame_parms) - \brief This function extracts the received resource blocks, both channel estimates and data symbols, - for the current allocation and for single antenna eNB transmission. - @param rxdataF Raw FFT output of received signal - @param dl_ch_estimates Channel estimates of current slot - @param rxdataF_ext FFT output for RBs in this allocation - @param dl_ch_estimates_ext Channel estimates for RBs in this allocation - @param pmi subband Precoding matrix indicator - @param pmi_ext Extracted PMI for chosen RBs - @param rb_alloc RB allocation vector - @param symbol Symbol to extract - @param subframe Subframe number - @param vrb_type Flag to indicate distributed VRB type - @param high_speed_flag - @param frame_parms Pointer to frame descriptor -*/ -/*uint16_t nr_dlsch_extract_rbs_single(int32_t **rxdataF, - int32_t **dl_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - uint16_t pmi, - uint8_t *pmi_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms);*/ - -unsigned short nr_dlsch_extract_rbs_single(int **rxdataF, - int **dl_ch_estimates, - int **rxdataF_ext, - int **dl_ch_estimates_ext, - unsigned short pmi, - unsigned char *pmi_ext, - unsigned char symbol, - uint8_t pilots, - unsigned short start_rb, - unsigned short nb_pdsch_rb, - unsigned char nr_tti_rx, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms); - -/** \fn dlsch_extract_rbs_dual(int32_t **rxdataF, - int32_t **dl_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - uint16_t pmi, - uint8_t *pmi_ext, - uint32_t *rb_alloc, - uint8_t symbol, - NR_DL_FRAME_PARMS *frame_parms) - \brief This function extracts the received resource blocks, both channel estimates and data symbols, - for the current allocation and for dual antenna eNB transmission. - @param rxdataF Raw FFT output of received signal - @param dl_ch_estimates Channel estimates of current slot - @param rxdataF_ext FFT output for RBs in this allocation - @param dl_ch_estimates_ext Channel estimates for RBs in this allocation - @param pmi subband Precoding matrix indicator - @param pmi_ext Extracted PMI for chosen RBs - @param rb_alloc RB allocation vector - @param symbol Symbol to extract - @param subframe Subframe index - @param high_speed_flag - @param frame_parms Pointer to frame descriptor -*/ -unsigned short nr_dlsch_extract_rbs_dual(int **rxdataF, - int **dl_ch_estimates, - int **rxdataF_ext, - int **dl_ch_estimates_ext, - unsigned short pmi, - unsigned char *pmi_ext, - unsigned char symbol, - uint8_t pilots, - unsigned short start_rb, - unsigned short nb_rb_pdsch, - unsigned char nr_tti_rx, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms, - MIMO_mode_t mimo_mode); - -/** \fn dlsch_extract_rbs_TM7(int32_t **rxdataF, - int32_t **dl_bf_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_bf_ch_estimates_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms) - \brief This function extracts the received resource blocks, both channel estimates and data symbols, - for the current allocation and for single antenna eNB transmission. - @param rxdataF Raw FFT output of received signal - @param dl_bf_ch_estimates Beamforming channel estimates of current slot - @param rxdataF_ext FFT output for RBs in this allocation - @param dl_bf_ch_estimates_ext Beamforming channel estimates for RBs in this allocation - @param rb_alloc RB allocation vector - @param symbol Symbol to extract - @param subframe Subframe number - @param high_speed_flag - @param frame_parms Pointer to frame descriptor -*/ -uint16_t dlsch_extract_rbs_TM7(int32_t **rxdataF, - int32_t **dl_bf_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_bf_ch_estimates_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms); - -/** \brief This function performs channel compensation (matched filtering) on the received RBs for this allocation. In addition, it computes the squared-magnitude of the channel with weightings for 16QAM/64QAM detection as well as dual-stream detection (cross-correlation) - @param rxdataF_ext Frequency-domain received signal in RBs to be demodulated - @param dl_ch_estimates_ext Frequency-domain channel estimates in RBs to be demodulated - @param dl_ch_mag First Channel magnitudes (16QAM/64QAM) - @param dl_ch_magb Second weighted Channel magnitudes (64QAM) - @param rxdataF_comp Compensated received waveform - @param rho Cross-correlation between two spatial channels on each RX antenna - @param frame_parms Pointer to frame descriptor - @param symbol Symbol on which to operate - @param first_symbol_flag set to 1 on first DLSCH symbol - @param mod_order Modulation order of allocation - @param nb_rb Number of RBs in allocation - @param output_shift Rescaling for compensated output (should be energy-normalizing) - @param phy_measurements Pointer to UE PHY measurements -*/ -void nr_dlsch_channel_compensation(int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - int32_t **rxdataF_comp, - int32_t **rho, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t symbol, - uint8_t start_symbol, - uint8_t first_symbol_flag, - uint8_t mod_order, - uint16_t nb_rb, - uint8_t output_shift, - PHY_NR_MEASUREMENTS *phy_measurements); - -void nr_dlsch_channel_compensation_core(int **rxdataF_ext, - int **dl_ch_estimates_ext, - int **dl_ch_mag, - int **dl_ch_magb, - int **rxdataF_comp, - int **rho, - unsigned char n_tx, - unsigned char n_rx, - unsigned char mod_order, - unsigned char output_shift, - int length, - int start_point); - -void nr_dlsch_deinterleaving(uint8_t symbol, - uint8_t start_symbol, - uint16_t L, - uint16_t *llr, - uint16_t *llr_deint, - uint16_t nb_rb_pdsch); - -void dlsch_dual_stream_correlation(NR_DL_FRAME_PARMS *frame_parms, - unsigned char symbol, - unsigned short nb_rb, - int **dl_ch_estimates_ext, - int **dl_ch_estimates_ext_i, - int **dl_ch_rho_ext, - unsigned char output_shift); - -void dlsch_dual_stream_correlationTM34(NR_DL_FRAME_PARMS *frame_parms, - unsigned char symbol, - unsigned short nb_rb, - int **dl_ch_estimates_ext, - int **dl_ch_estimates_ext_i, - int **dl_ch_rho_ext, - unsigned char output_shift0, - unsigned char output_shift1); -//This function is used to compute multiplications in Hhermitian * H matrix -void conjch0_mult_ch1(int *ch0, - int *ch1, - int32_t *ch0conj_ch1, - unsigned short nb_rb, - unsigned char output_shift0); - -void construct_HhH_elements(int *ch0conj_ch0, - int *ch1conj_ch1, - int *ch2conj_ch2, - int *ch3conj_ch3, - int *ch0conj_ch1, - int *ch1conj_ch0, - int *ch2conj_ch3, - int *ch3conj_ch2, - int32_t *after_mf_00, - int32_t *after_mf_01, - int32_t *after_mf_10, - int32_t *after_mf_11, - unsigned short nb_rb); - -void squared_matrix_element(int32_t *Hh_h_00, - int32_t *Hh_h_00_sq, - unsigned short nb_rb); - -void dlsch_channel_level_TM34_meas(int *ch00, - int *ch01, - int *ch10, - int *ch11, - int *avg_0, - int *avg_1, - unsigned short nb_rb); - -void nr_dlsch_channel_level_median(int **dl_ch_estimates_ext, - int32_t *median, - int n_tx, - int n_rx, - int length, - int start_point); - -void nr_dlsch_detection_mrc_core(int **rxdataF_comp, - int **rxdataF_comp_i, - int **rho, - int **rho_i, - int **dl_ch_mag, - int **dl_ch_magb, - int **dl_ch_mag_i, - int **dl_ch_magb_i, - unsigned char n_tx, - unsigned char n_rx, - int length, - int start_point); - -void det_HhH(int32_t *after_mf_00, - int32_t *after_mf_01, - int32_t *after_mf_10, - int32_t *after_mf_11, - int32_t *det_fin_128, - unsigned short nb_rb); - -void numer(int32_t *Hh_h_00_sq, - int32_t *Hh_h_01_sq, - int32_t *Hh_h_10_sq, - int32_t *Hh_h_11_sq, - int32_t *num_fin, - unsigned short nb_rb); - -uint8_t rank_estimation_tm3_tm4(int *dl_ch_estimates_00, - int *dl_ch_estimates_01, - int *dl_ch_estimates_10, - int *dl_ch_estimates_11, - unsigned short nb_rb); - -void dlsch_channel_compensation_TM56(int **rxdataF_ext, - int **dl_ch_estimates_ext, - int **dl_ch_mag, - int **dl_ch_magb, - int **rxdataF_comp, - unsigned char *pmi_ext, - NR_DL_FRAME_PARMS *frame_parms, - PHY_NR_MEASUREMENTS *phy_measurements, - int eNB_id, - unsigned char symbol, - unsigned char mod_order, - unsigned short nb_rb, - unsigned char output_shift, - unsigned char dl_power_off); - - -void dlsch_channel_compensation_TM34(NR_DL_FRAME_PARMS *frame_parms, - NR_UE_PDSCH *lte_ue_pdsch_vars, - PHY_NR_MEASUREMENTS *phy_measurements, - int eNB_id, - unsigned char symbol, - unsigned char mod_order0, - unsigned char mod_order1, - int harq_pid, - int round, - MIMO_mode_t mimo_mode, - unsigned short nb_rb, - unsigned char output_shift0, - unsigned char output_shift1); - - -/** \brief This function computes the average channel level over all allocated RBs and antennas (TX/RX) in order to compute output shift for compensated signal - @param dl_ch_estimates_ext Channel estimates in allocated RBs - @param frame_parms Pointer to frame descriptor - @param avg Pointer to average signal strength - @param pilots_flag Flag to indicate pilots in symbol - @param nb_rb Number of allocated RBs -*/ -void nr_dlsch_channel_level(int **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - int32_t *avg, - uint8_t symbol, - uint32_t len, - unsigned short nb_rb); - - -void dlsch_channel_level_TM34(int **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - unsigned char *pmi_ext, - int *avg_0, - int *avg_1, - uint8_t symbol, - unsigned short nb_rb, - MIMO_mode_t mimo_mode); - - -void dlsch_channel_level_TM56(int32_t **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - unsigned char *pmi_ext, - int32_t *avg, - uint8_t symbol_mod, - uint16_t nb_rb); - -void dlsch_channel_level_TM7(int32_t **dl_bf_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - int32_t *avg, - uint8_t pilots_flag, - uint16_t nb_rb); - -void nr_dlsch_scale_channel(int32_t **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t **dlsch_ue, - uint8_t symbol, - uint8_t start_symbol, - uint16_t nb_rb); - -/** \brief This is the top-level entry point for DLSCH decoding in UE. It should be replicated on several - threads (on multi-core machines) corresponding to different HARQ processes. The routine first - computes the segmentation information, followed by rate dematching and sub-block deinterleaving the of the - received LLRs computed by dlsch_demodulation for each transport block segment. It then calls the - turbo-decoding algorithm for each segment and stops after either after unsuccesful decoding of at least - one segment or correct decoding of all segments. Only the segment CRCs are check for the moment, the - overall CRC is ignored. Finally transport block reassembly is performed. - @param phy_vars_ue Pointer to ue variables - @param dlsch_llr Pointer to LLR values computed by dlsch_demodulation - @param lte_frame_parms Pointer to frame descriptor - @param dlsch Pointer to DLSCH descriptor - @param frame Frame number - @param subframe Subframe number - @param num_pdcch_symbols Number of PDCCH symbols - @param is_crnti indicates if PDSCH belongs to a CRNTI (necessary for parallelizing decoding threads) - @param llr8_flag If 1, indicate that the 8-bit turbo decoder should be used - @returns 0 on success, 1 on unsuccessful decoding -*/ - -uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag); - -uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - int eNB_id, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag); - -void *nr_dlsch_decoding_2thread0(void *arg); - -void *nr_dlsch_decoding_2thread1(void *arg); - -void nr_dlsch_unscrambling(int16_t* llr, - uint32_t size, - uint8_t q, - uint32_t Nid, - uint32_t n_RNTI); - -uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t subframe, - PDSCH_t dlsch_id, - uint8_t eNB_id); - -/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs - - RB extraction (signal and channel estimates) - - channel compensation (matched filtering) - - RE extraction (pilot, PBCH, synch. signals) - - antenna combining (MRC, Alamouti, cycling) - - LLR computation - This function supports TM1, 2, 3, 5, and 6. - @param PHY_VARS_NR_UE Pointer to PHY variables - @param type Type of PDSCH (SI_PDSCH,RA_PDSCH,PDSCH,PMCH) - @param eNB_id eNb index (Nid1) 0,1,2 - @param eNB_id_i Interfering eNB index (Nid1) 0,1,2, or 3 in case of MU-MIMO IC receiver - @param subframe Subframe number - @param symbol Symbol on which to act (within sub-frame) - @param first_symbol_flag set to 1 on first DLSCH symbol - @param rx_type. rx_type=RX_IC_single_stream will enable interference cancellation of a second stream when decoding the first stream. In case of TM1, 2, 5, and this can cancel interference from a neighbouring cell given by eNB_id_i. In case of TM5, eNB_id_i should be set to n_connected_eNB to perform multi-user interference cancellation. In case of TM3, eNB_id_i should be set to eNB_id to perform co-channel interference cancellation; this option should be used together with an interference cancellation step [...]. In case of TM3, if rx_type=RX_IC_dual_stream, both streams will be decoded by applying the IC single stream receiver twice. - @param i_mod Modulation order of the interfering stream -*/ -int32_t nr_rx_pdsch(PHY_VARS_NR_UE *phy_vars_ue, - PDSCH_t type, - uint8_t eNB_id, - uint8_t eNB_id_i, - uint32_t frame, - uint8_t subframe, - uint8_t symbol, - uint8_t first_symbol_flag, - RX_type_t rx_type, - uint8_t i_mod, - uint8_t harq_pid); - -/*! \brief Extract PSS and SSS resource elements - @param phy_vars_ue Pointer to UE variables - @param[out] pss_ext contain the PSS signals after the extraction - @param[out] sss_ext contain the SSS signals after the extraction - @returns 0 on success -*/ -int pss_sss_extract(PHY_VARS_NR_UE *phy_vars_ue, - int32_t pss_ext[4][72], - int32_t sss_ext[4][72], - uint8_t subframe); - -/*! \brief Extract only PSS resource elements - @param phy_vars_ue Pointer to UE variables - @param[out] pss_ext contain the PSS signals after the extraction - @returns 0 on success -*/ -int pss_only_extract(PHY_VARS_NR_UE *phy_vars_ue, - int32_t pss_ext[4][72], - uint8_t subframe); - -/*! \brief Extract only SSS resource elements - @param phy_vars_ue Pointer to UE variables - @param[out] sss_ext contain the SSS signals after the extraction - @returns 0 on success -*/ -int sss_only_extract(PHY_VARS_NR_UE *phy_vars_ue, - int32_t sss_ext[4][72], - uint8_t subframe); - -/*! \brief Performs detection of SSS to find cell ID and other framing parameters (FDD/TDD, normal/extended prefix) - @param phy_vars_ue Pointer to UE variables - @param tot_metric Pointer to variable containing maximum metric under framing hypothesis (to be compared to other hypotheses - @param flip_max Pointer to variable indicating if start of frame is in second have of RX buffer (i.e. PSS/SSS is flipped) - @param phase_max Pointer to variable (0 ... 6) containing rought phase offset between PSS and SSS (can be used for carrier - frequency adjustment. 0 means -pi/3, 6 means pi/3. - @returns 0 on success -*/ -int rx_sss(PHY_VARS_NR_UE *phy_vars_ue,int32_t *tot_metric,uint8_t *flip_max,uint8_t *phase_max); - -/*! \brief receiver for the PBCH - \returns number of tx antennas or -1 if error -*/ -int nr_rx_pbch( PHY_VARS_NR_UE *ue, - UE_nr_rxtx_proc_t *proc, - NR_UE_PBCH *nr_ue_pbch_vars, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t eNB_id, - uint8_t i_ssb, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag); - -int nr_pbch_detection(UE_nr_rxtx_proc_t *proc, - PHY_VARS_NR_UE *ue, - int pbch_initial_symbol, - runmode_t mode); - -uint16_t rx_pbch_emul(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t eNB_id, - uint8_t pbch_phase); - - -/*! \brief PBCH unscrambling - This is similar to pbch_scrabling with the difference that inputs are signed s16s (llr values) and instead of flipping bits we change signs. - \param frame_parms Pointer to frame descriptor - \param llr Output of the demodulator - \param length Length of the sequence - \param frame_mod4 Frame number modulo 4*/ -void pbch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - int8_t* llr, - uint32_t length, - uint8_t frame_mod4); - - -void generate_64qam_table(void); -void generate_16qam_table(void); -void generate_qpsk_table(void); - -uint16_t extract_crc(uint8_t *dci,uint8_t DCI_LENGTH); - -/*! \brief LLR from two streams. This function takes two streams (qpsk modulated) and calculates the LLR, considering one stream as interference. - \param stream0_in pointer to first stream0 - \param stream1_in pointer to first stream1 - \param stream0_out pointer to output stream - \param rho01 pointer to correlation matrix - \param length*/ -void qpsk_qpsk_TM3456(short *stream0_in, - short *stream1_in, - short *stream0_out, - short *rho01, - int length - ); - -/** \brief Attempt decoding of a particular DCI with given length and format. - @param DCI_LENGTH length of DCI in bits - @param DCI_FMT Format of DCI - @param e e-sequence (soft bits) - @param decoded_output Output of Viterbi decoder -*/ -void dci_decoding(uint8_t DCI_LENGTH, - uint8_t DCI_FMT, - int8_t *e, - uint8_t *decoded_output); - -/** \brief Do 36.213 DCI decoding procedure by searching different RNTI options and aggregation levels. Currently does - not employ the complexity reducing procedure based on RNTI. - @param phy_vars_ue UE variables - @param dci_alloc Pointer to DCI_ALLOC_t array to store results for DLSCH/ULSCH programming - @param do_common If 1 perform search in common search-space else ue-specific search-space - @param eNB_id eNB Index on which to act - @param subframe Index of subframe - @returns bitmap of occupied CCE positions (i.e. those detected) -*/ -uint16_t dci_decoding_procedure(PHY_VARS_NR_UE *phy_vars_ue, - DCI_ALLOC_t *dci_alloc, - int do_common, - int16_t eNB_id, - uint8_t subframe); - -uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_NR_UE *ue, - DCI_ALLOC_t *dci_alloc, - uint8_t DCIFormat, - uint8_t agregationLevel, - int16_t eNB_id, - uint8_t subframe); - -uint16_t dci_decoding_procedure_emul(NR_UE_PDCCH **lte_ue_pdcch_vars, - uint8_t num_ue_spec_dci, - uint8_t num_common_dci, - DCI_ALLOC_t *dci_alloc_tx, - DCI_ALLOC_t *dci_alloc_rx, - int16_t eNB_id); - -/** \brief Compute Q (modulation order) based on I_MCS PDSCH. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS */ -uint8_t get_Qm(uint8_t I_MCS); - -/** \brief Compute Q (modulation order) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213. - @param I_MCS */ -uint8_t get_Qm_ul(uint8_t I_MCS); - -/** \brief Compute I_TBS (transport-block size) based on I_MCS for PDSCH. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS */ -uint8_t get_I_TBS(uint8_t I_MCS); - -/** \brief Compute I_TBS (transport-block size) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213. - @param I_MCS */ -unsigned char get_I_TBS_UL(unsigned char I_MCS); - -/** \brief Compute Q (modulation order) based on downlink I_MCS. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS - @param nb_rb - @return Transport block size */ -uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb); - -/** \brief Compute Q (modulation order) based on uplink I_MCS. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS - @param nb_rb - @return Transport block size */ -uint32_t get_TBS_UL(uint8_t mcs, uint16_t nb_rb); - -/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type - @param N_RB_DL number of PRB on DL - @param indicator for even/odd slot - @param vrb vrb index - @param Ngap Gap indicator -*/ -uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap); - -/* \brief Return prb for a given vrb index - @param vrb_type VRB type (0=localized,1=distributed) - @param rb_alloc_dci rballoc field from DCI -*/ -uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci); - - -/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type - @returns Transmission mode (1-7) -*/ -uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti); - - -/* \brief - @param ra_header Header of resource allocation (0,1) (See sections 7.1.6.1/7.1.6.2 of 36.213 Rel8.6) - @param rb_alloc Bitmap allocation from DCI (format 1,2) - @returns number of physical resource blocks -*/ -uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL); - -int get_G(NR_DL_FRAME_PARMS *frame_parms,uint16_t nb_rb,uint32_t *rb_alloc,uint8_t mod_order,uint8_t Nl,uint8_t num_pdcch_symbols,int frame,uint8_t subframe, uint8_t beamforming_mode); - -int adjust_G(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe); -int adjust_G2(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe,uint8_t symbol); - - -#ifndef modOrder -#define modOrder(I_MCS,I_TBS) ((I_MCS-I_TBS)*2+2) // Find modulation order from I_TBS and I_MCS -#endif - -/** \fn uint8_t I_TBS2I_MCS(uint8_t I_TBS); - \brief This function maps I_tbs to I_mcs according to Table 7.1.7.1-1 in 3GPP TS 36.213 V8.6.0. Where there is two supported modulation orders for the same I_TBS then either high or low modulation is chosen by changing the equality of the two first comparisons in the if-else statement. - \param I_TBS Index of Transport Block Size - \return I_MCS given I_TBS -*/ -uint8_t I_TBS2I_MCS(uint8_t I_TBS); - -/** \fn uint8_t SE2I_TBS(float SE, - uint8_t N_PRB, - uint8_t symbPerRB); - \brief This function maps a requested throughput in number of bits to I_tbs. The throughput is calculated as a function of modulation order, RB allocation and number of symbols per RB. The mapping orginates in the "Transport block size table" (Table 7.1.7.2.1-1 in 3GPP TS 36.213 V8.6.0) - \param SE Spectral Efficiency (before casting to integer, multiply by 1024, remember to divide result by 1024!) - \param N_PRB Number of PhysicalResourceBlocks allocated \sa lte_frame_parms->N_RB_DL - \param symbPerRB Number of symbols per resource block allocated to this channel - \return I_TBS given an SE and an N_PRB -*/ -uint8_t SE2I_TBS(float SE, - uint8_t N_PRB, - uint8_t symbPerRB); -/** \brief This function generates the sounding reference symbol (SRS) for the uplink according to 36.211 v8.6.0. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence. - @param frame_parms LTE DL Frame Parameters - @param soundingrs_ul_config_dedicated Dynamic configuration from RRC during Connection Establishment - @param txdataF pointer to the frequency domain TX signal - @returns 0 on success*/ -int generate_srs(NR_DL_FRAME_PARMS *frame_parms, - SOUNDINGRS_UL_CONFIG_DEDICATED *soundingrs_ul_config_dedicated, - int *txdataF, - int16_t amp, - uint32_t subframe); - - -/*! - \brief This function is similar to generate_srs_tx but generates a conjugate sequence for channel estimation. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence. - @param phy_vars_ue Pointer to PHY_VARS structure - @param eNB_id Index of destination eNB for this SRS - @param amp Linear amplitude of SRS - @param subframe Index of subframe on which to act - @returns 0 on success, -1 on error with message -*/ - -int32_t generate_srs_tx(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t eNB_id, - int16_t amp, - uint32_t subframe); - -/*! - \brief This function generates the downlink reference signal for the PUSCH according to 36.211 v8.6.0. The DRS occuies the RS defined by rb_alloc and the symbols 2 and 8 for extended CP and 3 and 10 for normal CP. -*/ - -int32_t generate_drs_pusch(PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - uint8_t eNB_id, - int16_t amp, - uint32_t subframe, - uint32_t first_rb, - uint32_t nb_rb, - uint8_t ant); - -/*! - \brief This function initializes the Group Hopping, Sequence Hopping and nPRS sequences for PUCCH/PUSCH according to 36.211 v8.6.0. It should be called after configuration of UE (reception of SIB2/3) and initial configuration of eNB (or after reconfiguration of cell-specific parameters). - @param frame_parms Pointer to a NR_DL_FRAME_PARMS structure (eNB or UE)*/ -void init_ul_hopping(NR_DL_FRAME_PARMS *frame_parms); - - -/*! - \brief This function implements the initialization of paging parameters for UE (See Section 7, 36.304).It must be called after setting IMSImod1024 during UE startup and after receiving SIB2 - @param ue Pointer to UE context - @param defaultPagingCycle T from 36.304 (0=32,1=64,2=128,3=256) - @param nB nB from 36.304 (0=4T,1=2T,2=T,3=T/2,4=T/4,5=T/8,6=T/16,7=T/32*/ -int init_ue_paging_info(PHY_VARS_NR_UE *ue, long defaultPagingCycle, long nB); - -int32_t compareints (const void * a, const void * b); - - -void ulsch_modulation(int32_t **txdataF, - int16_t amp, - frame_t frame, - uint32_t subframe, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_ULSCH_t *ulsch); - - - - - - -int generate_ue_dlsch_params_from_dci(int frame, - uint8_t subframe, - void *dci_pdu, - rnti_t rnti, - DCI_format_t dci_format, - NR_UE_PDCCH *pdcch_vars, - NR_UE_PDSCH *pdsch_vars, - NR_UE_DLSCH_t **dlsch, - NR_DL_FRAME_PARMS *frame_parms, - PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - uint16_t si_rnti, - uint16_t ra_rnti, - uint16_t p_rnti, - uint8_t beamforming_mode, - uint16_t tc_rnti); - - -int generate_ue_ulsch_params_from_dci(void *dci_pdu, - rnti_t rnti, - uint8_t subframe, - DCI_format_t dci_format, - PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - uint16_t si_rnti, - uint16_t ra_rnti, - uint16_t p_rnti, - uint16_t cba_rnti, - uint8_t eNB_id, - uint8_t use_srs); - -int32_t generate_ue_ulsch_params_from_rar(PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - uint8_t eNB_id); -double sinr_eff_cqi_calc(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t eNB_id, - uint8_t subframe); - -uint8_t sinr2cqi(double sinr,uint8_t trans_mode); - - -int dump_dci(NR_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci); - -int dump_ue_stats(PHY_VARS_NR_UE *phy_vars_ue, UE_nr_rxtx_proc_t *proc, char* buffer, int length, runmode_t mode, int input_level_dBm); - -void init_transport_channels(uint8_t); - -void generate_RIV_tables(void); - -/*! - \brief Encoding of PUSCH/ACK/RI/ACK from 36-212. - @param a Pointer to ulsch SDU - @param frame_parms Pointer to Frame parameters - @param ulsch Pointer to ulsch descriptor - @param harq_pid HARQ process ID - @param tmode Transmission mode (1-7) - @param control_only_flag Generate PUSCH with control information only - @param Nbundled Parameter for ACK/NAK bundling (36.213 Section 7.3) -*/ -uint32_t ulsch_encoding(uint8_t *a, - PHY_VARS_NR_UE *phy_vars_ue, - uint8_t harq_pid, - uint8_t eNB_id, - uint8_t subframe_rx, - uint8_t tmode, - uint8_t control_only_flag, - uint8_t Nbundled); - -void print_CQI(void *o,UCI_format_t uci_format,uint8_t eNB_id,int N_RB_DL); - -void fill_CQI(NR_UE_ULSCH_t *ulsch,PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id, uint8_t harq_pid,int N_RB_DL, rnti_t rnti, uint8_t trans_mode,double sinr_eff); - -void reset_cba_uci(void *o); - -/** \brief This routine computes the subband PMI bitmap based on measurements (0,1,2,3 for rank 0 and 0,1 for rank 1) in the format needed for UCI - @param meas pointer to measurements - @param eNB_id eNB_id - @param nb_subbands number of subbands - @returns subband PMI bitmap -*/ -uint16_t quantize_subband_pmi(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,int nb_subbands); - -int32_t pmi_convert_rank1_from_rank2(uint16_t pmi_alloc, int tpmi, int nb_rb); - -uint16_t quantize_subband_pmi2(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t a_id,int nb_subbands); - - - -uint64_t cqi2hex(uint32_t cqi); - -uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs); - - -/** \brief This routine extracts a single subband PMI from a bitmap coming from UCI or the pmi_extend function - @param N_RB_DL number of resource blocks - @param mimo_mode - @param pmi_alloc subband PMI bitmap - @param rb resource block for which to extract PMI - @returns subband PMI -*/ -uint8_t get_pmi(uint8_t N_RB_DL,MIMO_mode_t mode, uint32_t pmi_alloc,uint16_t rb); - -int get_nCCE_offset_l1(int *CCE_table, - const unsigned char L, - const int nCCE, - const int common_dci, - const unsigned short rnti, - const unsigned char subframe); - -uint16_t get_nCCE(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi); - -uint16_t get_nquad(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi); - -uint8_t get_mi(NR_DL_FRAME_PARMS *frame,uint8_t subframe); - -uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe); - -uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); - -void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); - -void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - uint8_t subframe, - int8_t* llr, - uint32_t length); - - - -void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - int mbsfn_flag, - NR_UE_DLSCH_t *dlsch, - int G, - int16_t* llr, - uint8_t q, - uint8_t Ns); - -void init_ncs_cell(NR_DL_FRAME_PARMS *frame_parms,uint8_t ncs_cell[20][7]); - -void generate_pucch1x(int32_t **txdataF, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t ncs_cell[20][7], - PUCCH_FMT_t fmt, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, - uint16_t n1_pucch, - uint8_t shortened_format, - uint8_t *payload, - int16_t amp, - uint8_t subframe); - -void generate_pucch2x(int32_t **txdataF, - NR_DL_FRAME_PARMS *fp, - uint8_t ncs_cell[20][7], - PUCCH_FMT_t fmt, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, - uint16_t n2_pucch, - uint8_t *payload, - int A, - int B2, - int16_t amp, - uint8_t subframe, - uint16_t rnti); - -void generate_pucch3x(int32_t **txdataF, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t ncs_cell[20][7], - PUCCH_FMT_t fmt, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, - uint16_t n3_pucch, - uint8_t shortened_format, - uint8_t *payload, - int16_t amp, - uint8_t subframe, - uint16_t rnti); - - -void init_ulsch_power_LUT(void); - -/*! - \brief Check for PRACH TXop in subframe - @param frame_parms Pointer to NR_DL_FRAME_PARMS - @param frame frame index to check - @param subframe subframe index to check - @returns 0 on success -*/ -int is_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,frame_t frame, uint8_t subframe); - -/*! - \brief Generate PRACH waveform - @param phy_vars_ue Pointer to ue top-level descriptor - @param eNB_id Index of destination eNB - @param subframe subframe index to operate on - @param index of preamble (0-63) - @param Nf System frame number - @returns 0 on success - -*/ -int32_t generate_prach(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe,uint16_t Nf); - - -/*! - \brief Helper for MAC, returns number of available PRACH in TDD for a particular configuration index - @param frame_parms Pointer to NR_DL_FRAME_PARMS structure - @returns 0-5 depending on number of available prach -*/ -uint8_t get_num_prach_tdd(module_id_t Mod_id); - -/*! - \brief Return the PRACH format as a function of the Configuration Index and Frame type. - @param prach_ConfigIndex PRACH Configuration Index - @param frame_type 0-FDD, 1-TDD - @returns 0-1 accordingly -*/ -uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type); - -uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr); - -/*! - \brief Helper for MAC, returns frequency index of PRACH resource in TDD for a particular configuration index - @param frame_parms Pointer to NR_DL_FRAME_PARMS structure - @returns 0-5 depending on number of available prach -*/ -uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index); - -/*! - \brief Comp ute DFT of PRACH ZC sequences. Used for generation of prach in UE and reception of PRACH in eNB. - @param rootSequenceIndex PRACH root sequence - #param prach_ConfigIndex PRACH Configuration Index - @param zeroCorrelationZoneConfig PRACH ncs_config - @param highSpeedFlat PRACH High-Speed Flag - @param frame_type TDD/FDD flag - @param Xu DFT output -*/ -void compute_prach_seq(uint16_t rootSequenceIndex, - uint8_t prach_ConfigIndex, - uint8_t zeroCorrelationZoneConfig, - uint8_t highSpeedFlag, - lte_frame_type_t frame_type, - uint32_t X_u[64][839]); - - -void init_prach_tables(int N_ZC); - -void init_unscrambling_lut(void); -void init_scrambling_lut(void); - -/*! - \brief Return the status of MBSFN in this frame/subframe - @param frame Frame index - @param subframe Subframe index - @param frame_parms Pointer to frame parameters - @returns 1 if subframe is for MBSFN -*/ -int is_pmch_subframe(frame_t frame, int subframe, NR_DL_FRAME_PARMS *frame_parms); - -uint8_t is_not_pilot(uint8_t pilots, uint8_t re, uint8_t nushift, uint8_t use2ndpilots); - -uint8_t is_not_UEspecRS(int8_t lprime, uint8_t re, uint8_t nushift, uint8_t Ncp, uint8_t beamforming_mode); - -uint32_t dlsch_decoding_abstraction(double *dlsch_MIPB, - NR_DL_FRAME_PARMS *lte_frame_parms, - NR_UE_DLSCH_t *dlsch, - uint8_t subframe, - uint8_t num_pdcch_symbols); - -// DL power control functions -double get_pa_dB(uint8_t pa); - - -double computeRhoA_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - NR_UE_DLSCH_t *dlsch_ue, - uint8_t dl_power_off, - uint8_t n_antenna_port); - -double computeRhoB_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - PDSCH_CONFIG_COMMON *pdsch_config_common, - uint8_t n_antenna_port, - NR_UE_DLSCH_t *dlsch_ue, - uint8_t dl_power_off); - -/*void compute_sqrt_RhoAoRhoB(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - PDSCH_CONFIG_COMMON *pdsch_config_common, - uint8_t n_antenna_port, - NR_UE_DLSCH_t *dlsch_ue); -*/ - -uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms, - uint8_t prach_ConfigIndex, - uint8_t n_ra_prboffset, - uint8_t tdd_mapindex, uint16_t Nf); - -uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset); - -int nr_rx_pdsch(PHY_VARS_NR_UE *ue, - PDSCH_t type, - unsigned char eNB_id, - unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference - uint32_t frame, - uint8_t nr_tti_rx, - unsigned char symbol, - unsigned char first_symbol_flag, - RX_type_t rx_type, - unsigned char i_mod, - unsigned char harq_pid); - -uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) ; - -uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag); - -/**@}*/ -#endif diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c index 2bc623a66c..3622e61b61 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c @@ -35,12 +35,59 @@ #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/LTE_REFSIG/lte_refsig.h" +int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { + + uint16_t i; + int16_t first_free_index=-1; + + AssertFatal(gNB!=NULL,"gNB is null\n"); + for (i=0; iulsch[i]!=NULL,"gNB->ulsch[%d] is null\n",i); + AssertFatal(gNB->ulsch[i][0]!=NULL,"gNB->ulsch[%d][0] is null\n",i); + LOG_D(PHY,"searching for rnti %x : ulsch_index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,gNB->ulsch[i][0]->harq_mask,gNB->ulsch[i][0]->rnti,first_free_index); + if ((gNB->ulsch[i][0]->harq_mask >0) && + (gNB->ulsch[i][0]->rnti==rnti)) return i; + else if ((gNB->ulsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i; + } + if (type == SEARCH_EXIST) return -1; + if (first_free_index != -1) + gNB->ulsch[first_free_index][0]->rnti = 0; + return first_free_index; +} + +void nr_fill_ulsch(PHY_VARS_gNB *gNB, + int frame, + int slot, + nfapi_nr_pusch_pdu_t *ulsch_pdu) { + + + int ulsch_id = find_nr_ulsch(ulsch_pdu->rnti,gNB,SEARCH_EXIST_OR_FREE); + AssertFatal( (ulsch_id>=0) && (ulsch_idrnti,ulsch_id); + + NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ulsch_id][0]; + int harq_pid = ulsch_pdu->pusch_data.harq_process_id; + ulsch->rnti = ulsch_pdu->rnti; + //ulsch->rnti_type; + ulsch->harq_mask |= 1<harq_process_id[slot] = harq_pid; + + ulsch->harq_processes[harq_pid]->frame=frame; + ulsch->harq_processes[harq_pid]->slot=slot; + ulsch->harq_processes[harq_pid]->handled= 0; + ulsch->harq_processes[harq_pid]->status= NR_ACTIVE; + memcpy((void*)&ulsch->harq_processes[harq_pid]->ulsch_pdu, (void*)ulsch_pdu, sizeof(nfapi_nr_pusch_pdu_t)); + + LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); + +} + void nr_ulsch_unscrambling(int16_t* llr, - uint32_t size, - uint8_t q, - uint32_t Nid, - uint32_t n_RNTI) -{ + uint32_t size, + uint8_t q, + uint32_t Nid, + uint32_t n_RNTI) { + uint8_t reset; uint32_t x1, x2, s=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index 6c6ff4fd05..e00975eee1 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -218,13 +218,13 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch) /// Nfapi ULSCH PDU //nfapi_nr_ul_config_ulsch_pdu ulsch_pdu; ulsch->harq_processes[i]->frame=0; - ulsch->harq_processes[i]->subframe=0; + ulsch->harq_processes[i]->slot=0; ulsch->harq_processes[i]->round=0; ulsch->harq_processes[i]->TPC=0; ulsch->harq_processes[i]->mimo_mode=0; ulsch->harq_processes[i]->dci_alloc=0; ulsch->harq_processes[i]->rar_alloc=0; - ulsch->harq_processes[i]->status=0; + ulsch->harq_processes[i]->status=NR_SCH_IDLE; ulsch->harq_processes[i]->subframe_scheduling_flag=0; ulsch->harq_processes[i]->subframe_cba_scheduling_flag=0; ulsch->harq_processes[i]->phich_active=0; @@ -357,6 +357,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } // harq_process->trials[nfapi_ulsch_pdu_rel15->round]++; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,1); harq_process->TBS = pusch_pdu->pusch_data.tb_size; A = (harq_process->TBS)<<3; @@ -420,7 +422,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, #ifdef DEBUG_ULSCH_DECODING printf("ulsch decoding nr segmentation Z %d\n", harq_process->Z); if (!frame%100) - printf("K %d C %d Z %d\n", harq_process->K, harq_process->C, harq_process->Z); + printf("K %d C %d Z %d \n", harq_process->K, harq_process->C, harq_process->Z); #endif } p_decParams->Z = harq_process->Z; @@ -527,7 +529,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, #ifdef DEBUG_ULSCH_DECODING if (r==0) { write_output("decoder_llr.m","decllr",ulsch_llr,G,1,0); - write_output("decoder_in.m","dec",&harq_process->d[0][0],(3*8*Kr_bytes)+12,1,0); + write_output("decoder_in.m","dec",&harq_process->d[0][0],E,1,0); } printf("decoder input(segment %u) :", r); @@ -608,7 +610,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, #endif ret = ulsch->max_ldpc_iterations + 1; } - nb_total_decod++; if (no_iteration_ldpc > ulsch->max_ldpc_iterations){ @@ -666,8 +667,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ulsch->harq_mask &= ~(1 << harq_pid); } - // LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", - // phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS); + // LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", + // phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS); harq_process->handled = 1; ret = ulsch->max_ldpc_iterations + 1; @@ -689,6 +690,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, // LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); + // Reassembly of Transport block here offset = 0; Kr = harq_process->K; @@ -713,14 +715,14 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, #ifdef DEBUG_ULSCH_DECODING LOG_I(PHY, "Decoder output (payload): \n"); - for (i = 0; i < harq_process->TBS / 8; i++) { + for (i = 0; i < harq_process->TBS ; i++) { //harq_process_ul_ue->a[i] = (unsigned char) rand(); //printf("a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); - printf("0x%02x",harq_process->b[i]); + printf("%02x",harq_process->b[i]); } #endif ulsch->last_iteration_cnt = ret; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,0); return(ret); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 363b67960d..a966db5844 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -222,7 +222,6 @@ void nr_idft(uint32_t *z, uint32_t Msc_PUSCH) } - void nr_ulsch_extract_rbs_single(int32_t **rxdataF, NR_gNB_PUSCH *pusch_vars, unsigned char symbol, @@ -230,9 +229,10 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, nfapi_nr_pusch_pdu_t *pusch_pdu, NR_DL_FRAME_PARMS *frame_parms) { + unsigned short start_re, re, nb_re_pusch; unsigned char aarx; - uint8_t K_ptrs; + uint8_t K_ptrs = 0; uint32_t rxF_ext_index = 0; uint32_t ul_ch0_ext_index = 0; uint32_t ul_ch0_index = 0; @@ -259,8 +259,6 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, is_ptrs_symbol_flag = 0; num_ptrs_symbols = 0; - K_ptrs = (pusch_pdu->pusch_ptrs.ptrs_freq_density)?4:2; - for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) { rxF = (int16_t *)&rxdataF[aarx][symbol * frame_parms->ofdm_symbol_size]; @@ -285,6 +283,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, is_dmrs_re = 0; if (pusch_pdu->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { + K_ptrs = (pusch_pdu->pusch_ptrs.ptrs_freq_density)?4:2; if(is_ptrs_symbol(symbol, pusch_vars->ptrs_symbols)) is_ptrs_symbol_flag = is_ptrs_subcarrier((start_re + re) % frame_parms->ofdm_symbol_size, n_rnti, @@ -313,7 +312,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, ul_ch0_ptrs_ext[ul_ch0_ptrs_ext_index] = ul_ch0_ptrs[ul_ch0_ptrs_index]; #ifdef DEBUG_RB_EXT - printf("rxF_ext[%d] = %d, %d\n", rxF_ext_index, rxF_ext[rxF_ext_index], rxF_ext[rxF_ext_index+1]); + printf("rxF_ext[%d] = (%d,%d)\n", rxF_ext_index>>1, rxF_ext[rxF_ext_index],rxF_ext[rxF_ext_index+1]); #endif ul_ch0_ext_index++; @@ -369,7 +368,6 @@ void nr_ulsch_scale_channel(int **ul_ch_estimates_ext, nb_rb = (2*nb_rb)/3; } - for (rb=0;rb=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol; - for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { for (aarx=0; aarxnb_antennas_rx; aarx++) { //clear average level avg128U = vdupq_n_s32(0); @@ -486,8 +484,7 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, ((int32_t*)&avg128U)[2] + ((int32_t*)&avg128U)[3] ) / (nb_rb*nre); } - - + } #endif } @@ -513,12 +510,12 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, ul_ch = (int16_t *)&ul_ch_estimates_ext[0][symbol*nb_rb*12]; printf("--------------------symbol = %d, mod_order = %d, output_shift = %d-----------------------\n", symbol, mod_order, output_shift); - printf("----------------Before compansation------------------\n"); + printf("----------------Before compensation------------------\n"); - for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx++){ + for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx+=2){ - printf("rxF[%d] = %d\n", prnt_idx, rxF[prnt_idx]); - printf("ul_ch[%d] = %d\n", prnt_idx, ul_ch[prnt_idx]); + printf("rxF[%d] = (%d,%d)\n", prnt_idx>>1, rxF[prnt_idx],rxF[prnt_idx+1]); + printf("ul_ch[%d] = (%d,%d)\n", prnt_idx>>1, ul_ch[prnt_idx],ul_ch[prnt_idx+1]); } @@ -706,7 +703,6 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, if (rho) { - for (aarx=0; aarxnb_antennas_rx; aarx++) { rho128 = (__m128i *)&rho[aarx][symbol*frame_parms->N_RB_UL*12]; ul_ch128 = (__m128i *)&ul_ch_estimates_ext[aarx][symbol*frame_parms->N_RB_UL*12]; @@ -788,7 +784,6 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, #elif defined(__arm__) - unsigned short rb; unsigned char aatx,aarx,symbol_mod,is_dmrs_symbol=0; @@ -990,9 +985,9 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, printf("----------------After compansation------------------\n"); - for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx++){ + for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx+=2){ - printf("rxF[%d] = %d\n", prnt_idx, rxF[prnt_idx]); + printf("rxF[%d] = (%d,%d)\n", prnt_idx>>1, rxF[prnt_idx],rxF[prnt_idx+1]); } @@ -1005,9 +1000,9 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, printf("----------------After computation------------------\n"); - for (print_idx=0;print_idx<12*nb_rb*2;print_idx++){ + for (print_idx=0;print_idx<12*nb_rb*2;print_idx+=2){ - printf("ch_mag[%d] = %d\n", print_idx, ch_mag[print_idx]); + printf("ch_mag[%d] = (%d,%d)\n", print_idx>>1, ch_mag[print_idx],ch_mag[print_idx+1]); } @@ -1015,37 +1010,35 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, } -void nr_rx_pusch(PHY_VARS_gNB *gNB, - uint8_t UE_id, - uint32_t frame, - uint8_t nr_tti_rx, - unsigned char symbol, - unsigned char harq_pid) +int nr_rx_pusch(PHY_VARS_gNB *gNB, + uint8_t ulsch_id, + uint32_t frame, + uint8_t nr_tti_rx, + unsigned char symbol, + unsigned char harq_pid) { - uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol + uint8_t aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol uint32_t nb_re_pusch, bwp_start_subcarrier; uint8_t L_ptrs = 0; // PTRS parameter int avgs; int avg[4]; NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; + nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[ulsch_id][0]->harq_processes[harq_pid]->ulsch_pdu; dmrs_symbol_flag = 0; - first_symbol_flag = 0; - gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0; + gNB->pusch_vars[ulsch_id]->ptrs_sc_per_ofdm_symbol = 0; if(symbol == rel15_ul->start_symbol_index){ - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0; - gNB->pusch_vars[UE_id]->dmrs_symbol = 0; - gNB->pusch_vars[UE_id]->cl_done = 0; - gNB->pusch_vars[UE_id]->ptrs_symbols = 0; - first_symbol_flag = 1; + gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = 0; + gNB->pusch_vars[ulsch_id]->dmrs_symbol = 0; + gNB->pusch_vars[ulsch_id]->cl_done = 0; + gNB->pusch_vars[ulsch_id]->ptrs_symbols = 0; if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { // if there is ptrs pdu L_ptrs = 1<<(rel15_ul->pusch_ptrs.ptrs_time_density); - set_ptrs_symb_idx(&gNB->pusch_vars[UE_id]->ptrs_symbols, + set_ptrs_symb_idx(&gNB->pusch_vars[ulsch_id]->ptrs_symbols, rel15_ul->nr_of_symbols, rel15_ul->start_symbol_index, L_ptrs, @@ -1058,15 +1051,25 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, dmrs_symbol_flag = ((rel15_ul->ul_dmrs_symb_pos)>>symbol)&0x01; if (dmrs_symbol_flag == 1){ - nb_re_pusch = rel15_ul->rb_size * ((rel15_ul->dmrs_config_type==pusch_dmrs_type1)?6:8); - gNB->pusch_vars[UE_id]->dmrs_symbol = symbol; + if (((rel15_ul->ul_dmrs_symb_pos)>>((symbol+1)%frame_parms->symbols_per_slot))&0x01) + AssertFatal(1==0,"Double DMRS configuration is not yet supported\n"); + + if (rel15_ul->dmrs_config_type == 0) { + // if no data in dmrs cdm group is 1 only even REs have no data + // if no data in dmrs cdm group is 2 both odd and even REs have no data + nb_re_pusch = rel15_ul->rb_size *(12 - (rel15_ul->num_dmrs_cdm_grps_no_data*6)); + } + else { + nb_re_pusch = rel15_ul->rb_size *(12 - (rel15_ul->num_dmrs_cdm_grps_no_data*4)); + } + gNB->pusch_vars[ulsch_id]->dmrs_symbol = symbol; } else { nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; } if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { // if there is ptrs pdu - if(is_ptrs_symbol(symbol, gNB->pusch_vars[UE_id]->ptrs_symbols)) - gNB->pusch_vars[UE_id]->ptrs_symbol_index = symbol; + if(is_ptrs_symbol(symbol, gNB->pusch_vars[ulsch_id]->ptrs_symbols)) + gNB->pusch_vars[ulsch_id]->ptrs_symbol_index = symbol; } @@ -1086,75 +1089,88 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, //--------------------- RBs extraction --------------------- //---------------------------------------------------------- - start_meas(&gNB->ulsch_rbs_extraction_stats); - nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, - gNB->pusch_vars[UE_id], - symbol, - dmrs_symbol_flag, - rel15_ul, - frame_parms); - stop_meas(&gNB->ulsch_rbs_extraction_stats); + if (nb_re_pusch > 0) { - nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - frame_parms, - gNB->ulsch[UE_id], - symbol, - dmrs_symbol_flag, - rel15_ul->rb_size, - rel15_ul->dmrs_config_type); - - - if (first_symbol_flag==1) { - - nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - frame_parms, - avg, - symbol, - nb_re_pusch, - rel15_ul->rb_size); - avgs = 0; - - for (aatx=0;aatxnb_antennas_tx;aatx++) - for (aarx=0;aarxnb_antennas_rx;aarx++) - avgs = cmax(avgs,avg[(aatx<<1)+aarx]); - - gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; - - } - - start_meas(&gNB->ulsch_channel_compensation_stats); - nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, - gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - gNB->pusch_vars[UE_id]->ul_ch_mag0, - gNB->pusch_vars[UE_id]->ul_ch_magb0, - gNB->pusch_vars[UE_id]->rxdataF_comp, - (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[UE_id]->rho : NULL, - frame_parms, + start_meas(&gNB->ulsch_rbs_extraction_stats); + nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, + gNB->pusch_vars[ulsch_id], symbol, dmrs_symbol_flag, - rel15_ul->qam_mod_order, - rel15_ul->rb_size, - gNB->pusch_vars[UE_id]->log2_maxh); - stop_meas(&gNB->ulsch_channel_compensation_stats); + rel15_ul, + frame_parms); + stop_meas(&gNB->ulsch_rbs_extraction_stats); + + nr_ulsch_scale_channel(gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext, + frame_parms, + gNB->ulsch[ulsch_id], + symbol, + dmrs_symbol_flag, + rel15_ul->rb_size, + rel15_ul->dmrs_config_type); + + + if (gNB->pusch_vars[ulsch_id]->cl_done==0) { + + nr_ulsch_channel_level(gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext, + frame_parms, + avg, + symbol, + nb_re_pusch, + rel15_ul->rb_size); + + avgs = 0; + + for (aatx=0;aatxnb_antennas_tx;aatx++) + for (aarx=0;aarxnb_antennas_rx;aarx++) + avgs = cmax(avgs,avg[(aatx<<1)+aarx]); + + gNB->pusch_vars[ulsch_id]->log2_maxh = (log2_approx(avgs)/2)+1; + gNB->pusch_vars[ulsch_id]->cl_done = 1; + } + + start_meas(&gNB->ulsch_channel_compensation_stats); + nr_ulsch_channel_compensation(gNB->pusch_vars[ulsch_id]->rxdataF_ext, + gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext, + gNB->pusch_vars[ulsch_id]->ul_ch_mag0, + gNB->pusch_vars[ulsch_id]->ul_ch_magb0, + gNB->pusch_vars[ulsch_id]->rxdataF_comp, + (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[ulsch_id]->rho : NULL, + frame_parms, + symbol, + dmrs_symbol_flag, + rel15_ul->qam_mod_order, + rel15_ul->rb_size, + gNB->pusch_vars[ulsch_id]->log2_maxh); + stop_meas(&gNB->ulsch_channel_compensation_stats); + + + int rxsig = signal_energy(&gNB->pusch_vars[ulsch_id]->rxdataF_comp[0][(symbol*rel15_ul->rb_size*12)], + rel15_ul->rb_size*12); + + if (rxsig==1) return (rxsig); #ifdef NR_SC_FDMA - nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); + nr_idft(&((uint32_t*)gNB->pusch_vars[ulsch_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); #endif //---------------------------------------------------------- //-------------------- LLRs computation -------------------- //---------------------------------------------------------- - start_meas(&gNB->ulsch_llr_stats); - nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], - gNB->pusch_vars[UE_id]->ul_ch_mag0, - gNB->pusch_vars[UE_id]->ul_ch_magb0, - &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order], - rel15_ul->rb_size, - nb_re_pusch, - symbol, - rel15_ul->qam_mod_order); - stop_meas(&gNB->ulsch_llr_stats); + start_meas(&gNB->ulsch_llr_stats); + AssertFatal(gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order+nb_re_pusch*rel15_ul->qam_mod_order < (8*((3*8*6144)+12)) , "Mysterious llr buffer size check"); + nr_ulsch_compute_llr(&gNB->pusch_vars[ulsch_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], + gNB->pusch_vars[ulsch_id]->ul_ch_mag0, + gNB->pusch_vars[ulsch_id]->ul_ch_magb0, + &gNB->pusch_vars[ulsch_id]->llr[gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order], + rel15_ul->rb_size, + nb_re_pusch, + symbol, + rel15_ul->qam_mod_order); + stop_meas(&gNB->ulsch_llr_stats); + + } + + gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset + nb_re_pusch; + return (0); - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch - gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol; - } diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index 6dfbffc46e..501df8bb35 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -20,15 +20,15 @@ */ /*! \file PHY/NR_TRANSPORT/pucch_rx.c -* \brief Top-level routines for decoding the PUCCH physical channel -* \author A. Mico Pereperez, Padarthi Naga Prasanth, Francesco Mani, Raymond Knopp -* \date 2020 -* \version 0.2 -* \company Eurecom -* \email: -* \note -* \warning -*/ + * \brief Top-level routines for decoding the PUCCH physical channel + * \author A. Mico Pereperez, Padarthi Naga Prasanth, Francesco Mani, Raymond Knopp + * \date 2020 + * \version 0.2 + * \company Eurecom + * \email: + * \note + * \warning + */ #include #include #include @@ -44,7 +44,6 @@ #include "PHY/NR_UE_TRANSPORT/pucch_nr.h" #include #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_REFSIG/nr_refsig.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" @@ -53,6 +52,54 @@ //#define DEBUG_NR_PUCCH_RX 1 +NR_gNB_PUCCH_t *new_gNB_pucch(void){ + NR_gNB_PUCCH_t *pucch; + pucch = (NR_gNB_PUCCH_t *)malloc16(sizeof(NR_gNB_PUCCH_t)); + pucch->active = 0; + return (pucch); +} + +int nr_find_pucch(uint16_t rnti, + int frame, + int slot, + PHY_VARS_gNB *gNB) { + + AssertFatal(gNB!=NULL,"gNB is null\n"); + int index = -1; + + for (int i=0; ipucch[i]!=NULL,"gNB->pucch[%d] is null\n",i); + if ((gNB->pucch[i]->active >0) && + (gNB->pucch[i]->pucch_pdu.rnti==rnti) && + (gNB->pucch[i]->frame==frame) && + (gNB->pucch[i]->slot==slot)) return(i); + else if ((gNB->pucch[i]->active == 0) && (index==-1)) index=i; + } + + if (index==-1) + LOG_E(MAC,"PUCCH list is full\n"); + + return(index); +} + +void nr_fill_pucch(PHY_VARS_gNB *gNB, + int frame, + int slot, + nfapi_nr_pucch_pdu_t *pucch_pdu) { + + int id = nr_find_pucch(pucch_pdu->rnti,frame,slot,gNB); + AssertFatal( (id>=0) && (idrnti,id); + + NR_gNB_PUCCH_t *pucch = gNB->pucch[id]; + pucch->frame = frame; + pucch->slot = slot; + pucch->active = 1; + memcpy((void*)&pucch->pucch_pdu, (void*)pucch_pdu, sizeof(nfapi_nr_pucch_pdu_t)); + +} + + int get_pucch0_cs_lut_index(PHY_VARS_gNB *gNB,nfapi_nr_pucch_pdu_t* pucch_pdu) { int i=0; @@ -154,7 +201,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, * Defining cyclic shift hopping TS 38.211 Subclause 6.3.2.2.2 */ // alpha is cyclic shift - double alpha; + //double alpha; // lnormal is the OFDM symbol number in the PUCCH transmission where l=0 corresponds to the first OFDM symbol of the PUCCH transmission //uint8_t lnormal; // lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213] @@ -191,9 +238,9 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, int16_t x_n_re[nr_sequences][24],x_n_im[nr_sequences][24]; for(i=0;inr_of_symbols; l++){ - alpha = nr_cyclic_shift_hopping(pucch_pdu->hopping_id,pucch_pdu->initial_cyclic_shift,mcs[i],l,pucch_pdu->start_symbol_index,slot); + double alpha = nr_cyclic_shift_hopping(pucch_pdu->hopping_id,pucch_pdu->initial_cyclic_shift,mcs[i],l,pucch_pdu->start_symbol_index,slot); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d/%d,mcs %d)\n",u,v,alpha,l,l+pucch_pdu->start_symbol_index,mcs[i]); printf("lut output %d\n",gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index]); @@ -201,14 +248,14 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, alpha=0.0; for (n=0; n<12; n++){ x_n_re[i][(12*l)+n] = (int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15) - - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))); // Re part of base sequence shifted by alpha + - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))); // Re part of base sequence shifted by alpha x_n_im[i][(12*l)+n] =(int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) - + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))); // Im part of base sequence shifted by alpha + + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))); // Im part of base sequence shifted by alpha #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d) %d,%d\n", - u,v,alpha,l,n,x_n_re[i][(12*l)+n],x_n_im[i][(12*l)+n], - (int32_t)(round(32767*cos(alpha*n))), - (int32_t)(round(32767*sin(alpha*n)))); + printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d) %d,%d\n", + u,v,alpha,l,n,x_n_re[i][(12*l)+n],x_n_im[i][(12*l)+n], + (int32_t)(round(32767*cos(alpha*n))), + (int32_t)(round(32767*sin(alpha*n)))); #endif } } @@ -230,12 +277,12 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, r_re[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0]; r_im[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]; - #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch0] mapping to RE \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", - frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size)+re_offset, - l,n,((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0], - ((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]); - #endif +#ifdef DEBUG_NR_PUCCH_RX + printf("\t [nr_generate_pucch0] mapping to RE \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size)+re_offset, + l,n,((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0], + ((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]); +#endif re_offset++; if (re_offset>= frame_parms->ofdm_symbol_size) re_offset-=frame_parms->ofdm_symbol_size; @@ -266,7 +313,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, const int16_t *x_re = table_5_2_2_2_2_Re[u],*x_im = table_5_2_2_2_2_Im[u]; int16_t xr[24] __attribute__((aligned(32))); - int16_t xrt[24] __attribute__((aligned(32))); + //int16_t xrt[24] __attribute__((aligned(32))); int32_t xrtmag=0; int maxpos=0; int n2=0; @@ -300,7 +347,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, n2=0; for (l=0;lnr_of_symbols;l++) { - seq_index = (pucch_pdu->initial_cyclic_shift+ + seq_index = (pucch_pdu->initial_cyclic_shift+ mcs[i]+ gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index])%12; for (n=0;n<12;n++,n2+=2) { @@ -320,14 +367,14 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, uint8_t xrtmag_dB = dB_fixed(xrtmag); -#ifdef DEBUG_NR_PUCCH_RX +//#ifdef DEBUG_NR_PUCCH_RX printf("PUCCH 0 : maxpos %d\n",maxpos); -#endif +//#endif index=maxpos; #endif // first bit of bitmap for sr presence and second bit for acknack presence - uci_pdu->pdu_bit_map = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1); + uci_pdu->pduBitmap = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1); uci_pdu->pucch_format = 0; // format 0 uci_pdu->ul_cqi = 0xff; // currently not valid uci_pdu->timing_advance = 0xffff; // currently not valid @@ -362,8 +409,8 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, uci_pdu->harq->harq_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); uci_pdu->harq->harq_list = (nfapi_nr_harq_t*)malloc(2); - uci_pdu->harq->harq_list[0].harq_value = index&0x01; - uci_pdu->harq->harq_list[1].harq_value = (index>>1)&0x01; + uci_pdu->harq->harq_list[1].harq_value = index&0x01; + uci_pdu->harq->harq_list[0].harq_value = (index>>1)&0x01; if (pucch_pdu->sr_flag == 1) { uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr)); @@ -505,13 +552,13 @@ void nr_decode_pucch1( int32_t **rxdataF, if (l%2 == 0) { // mapping DM-RS signal according to TS38.211 subclause 6.4.1.3.1 z_dmrs_re_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[0]; z_dmrs_im_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[1]; -// printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); + // printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n", amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+n,re_offset, l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]); #endif -// printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); + // printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); } re_offset++; @@ -530,7 +577,7 @@ void nr_decode_pucch1( int32_t **rxdataF, l,lprime); #endif // y_n contains the complex value d multiplied by the sequence r_u_v - if ((intraSlotFrequencyHopping == 1) && (l >= (int)floor(nrofSymbols/2))) n_hop = 1; // n_hop = 1 for second hop + if ((intraSlotFrequencyHopping == 1) && (l >= (int)floor(nrofSymbols/2))) n_hop = 1; // n_hop = 1 for second hop #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] entering function nr_group_sequence_hopping with n_hop=%d, nr_tti_tx=%d\n", @@ -548,18 +595,18 @@ void nr_decode_pucch1( int32_t **rxdataF, } else{ r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15) - - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15))); // Re part of DMRS base sequence shifted by alpha + - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15))); // Re part of DMRS base sequence shifted by alpha r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) - + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha + + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_re[n]))>>15); r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_im[n]))>>15); } -// printf("symbol=%d\tr_u_rx_re=%d\tr_u_rx_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n], r_u_v_alpha_delta_dmrs_im[n]); + // printf("symbol=%d\tr_u_rx_re=%d\tr_u_rx_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n], r_u_v_alpha_delta_dmrs_im[n]); // PUCCH sequence = DM-RS sequence multiplied by d(0) -/* y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15) - - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n) - y_n_im[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_im)>>15) - + (((int32_t)(r_u_v_alpha_delta_im[n])*d_re)>>15))); // Im part of y(n) */ + /* y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15) + - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n) + y_n_im[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_im)>>15) + + (((int32_t)(r_u_v_alpha_delta_im[n])*d_re)>>15))); // Im part of y(n) */ #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] sequence generation \tu=%d \tv=%d \talpha=%lf \tr_u_v_alpha_delta[n=%d]=(%d,%d) \ty_n[n=%d]=(%d,%d)\n", u,v,alpha,n,r_u_v_alpha_delta_re[n],r_u_v_alpha_delta_im[n],n,y_n_re[n],y_n_im[n]); @@ -609,12 +656,12 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]=z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]=z_im_temp; -// printf("symbol=%d\tz_re_rx=%d\tz_im_rx=%d\t",l,(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + // printf("symbol=%d\tz_re_rx=%d\tz_im_rx=%d\t",l,(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, @@ -624,15 +671,15 @@ void nr_decode_pucch1( int32_t **rxdataF, #endif // multiplying with conjugate of low papr sequence z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp; -/* if(z_re_temp<0){ - printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_re[n],z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); - } - printf("z1_re_rx=%d\tz1_im_rx=%d\n",(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); */ + /* if(z_re_temp<0){ + printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_re[n],z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); + } + printf("z1_re_rx=%d\tz1_im_rx=%d\n",(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); */ } } } @@ -643,12 +690,12 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_dmrs_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; -// printf("symbol=%d\tz_dmrs_re_rx=%d\tz_dmrs_im_rx=%d\t",l,(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + // printf("symbol=%d\tz_dmrs_re_rx=%d\tz_dmrs_im_rx=%d\t",l,(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, @@ -658,17 +705,17 @@ void nr_decode_pucch1( int32_t **rxdataF, #endif //finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); -/* if(z_dmrs_re_temp<0){ - printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_dmrs_re[n],z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); - }*/ + - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + /* if(z_dmrs_re_temp<0){ + printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_dmrs_re[n],z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); + }*/ z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; -// printf("z1_dmrs_re_rx=%d\tz1_dmrs_im_rx=%d\n",(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); - /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; - z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ + // printf("z1_dmrs_re_rx=%d\tz1_dmrs_im_rx=%d\n",(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; + z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ } } } @@ -695,9 +742,9 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp; #ifdef DEBUG_NR_PUCCH_RX @@ -708,9 +755,9 @@ void nr_decode_pucch1( int32_t **rxdataF, z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp; } @@ -723,9 +770,9 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_dmrs_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; #ifdef DEBUG_NR_PUCCH_RX @@ -737,14 +784,14 @@ void nr_decode_pucch1( int32_t **rxdataF, #endif //finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; - /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; - z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ + /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; + z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ } } } @@ -796,8 +843,8 @@ void nr_decode_pucch1( int32_t **rxdataF, for(int n=0;n<12;n++){ y_n_re[n]=round(z_re_rx[l*12+n]/floor(nrofSymbols/4))+y_n_re[n]; y_n_im[n]=round(z_im_rx[l*12+n]/floor(nrofSymbols/4))+y_n_im[n]; - } - } + } + } else{ for(int n=0;n<12;n++){ y1_n_re[n]=round(z_re_rx[l*12+n]/round(nrofSymbols/4))+y1_n_re[n]; @@ -829,12 +876,12 @@ void nr_decode_pucch1( int32_t **rxdataF, } //Decoding QPSK or BPSK symbols to obtain payload bits if(nr_bit==1){ - if((d_re+d_im)>0){ - *payload=0; - } - else{ - *payload=1; - } + if((d_re+d_im)>0){ + *payload=0; + } + else{ + *payload=1; + } } else if(nr_bit==2){ if((d_re>0)&&(d_im>0)){ @@ -872,6 +919,9 @@ __m256i *pucch2_lut[9]={pucch2_3bit, pucch2_10bit, pucch2_11bit}; +__m64 pucch2_polar_4bit[16]; +__m128i pucch2_polar_llr_num_lut[256],pucch2_polar_llr_den_lut[256]; + void init_pucch2_luts() { uint32_t out; @@ -880,7 +930,9 @@ void init_pucch2_luts() { for (int b=3;b<12;b++) { for (uint16_t i=0;i<(1< 0 ? -1 : 1; @@ -949,6 +1001,62 @@ void init_pucch2_luts() { *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,15); } } + for (uint16_t i=0;i<16;i++) { + __m64 *lut_i=&pucch2_polar_4bit[i]; + + bit = (i&0x1) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,0); + bit = (i&0x2) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,1); + bit = (i&0x4) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,2); + bit = (i&0x8) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,3); + } + for (int i=0;i<256;i++) { + __m128i *lut_num_i=&pucch2_polar_llr_num_lut[i]; + __m128i *lut_den_i=&pucch2_polar_llr_den_lut[i]; + bit = (i&0x1) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,0); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,0); + + bit = (i&0x10) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,1); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,1); + + bit = (i&0x2) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,2); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,2); + + bit = (i&0x20) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,3); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,3); + + bit = (i&0x4) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,4); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,4); + + bit = (i&0x40) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,5); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,5); + + bit = (i&0x8) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,6); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,6); + + bit = (i&0x80) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,7); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,7); + printf("i %d, lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n",i, + ((int16_t *)lut_num_i)[0], + ((int16_t *)lut_num_i)[1], + ((int16_t *)lut_num_i)[2], + ((int16_t *)lut_num_i)[3], + ((int16_t *)lut_num_i)[4], + ((int16_t *)lut_num_i)[5], + ((int16_t *)lut_num_i)[6], + ((int16_t *)lut_num_i)[7]); + } } @@ -959,7 +1067,9 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, int32_t **rxdataF = gNB->common_vars.rxdataF; NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1); + //pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1); + + AssertFatal(pucch_pdu->nr_of_symbols==1 || pucch_pdu->nr_of_symbols==2, "Illegal number of symbols for PUCCH 2 %d\n",pucch_pdu->nr_of_symbols); @@ -967,7 +1077,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, //extract pucch and dmrs first - int l2=-1; + int l2=pucch_pdu->start_symbol_index; int re_offset = (12*pucch_pdu->prb_start) + (12*pucch_pdu->bwp_start) + frame_parms->first_carrier_offset; if (re_offset>= frame_parms->ofdm_symbol_size) re_offset-=frame_parms->ofdm_symbol_size; @@ -984,6 +1094,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, int16_t r_im_ext2[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); int16_t rd_re_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); int16_t rd_im_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t *r_re_ext_p,*r_im_ext_p,*rd_re_ext_p,*rd_im_ext_p; int16_t *rp[Prx2]; __m64 dmrs_re,dmrs_im; @@ -1000,156 +1111,166 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, for (int aa=0;aanr_of_symbols == 1) { - AssertFatal((pucch_pdu->prb_size&1) == 0,"prb_size %d is not a multiple of 2\n",pucch_pdu->prb_size); - // 24 PRBs contains 48x16-bit, so 6x8x16-bit - for (int prb=0;prbprb_size;prb+=2) { - for (int aa=0;aaprb_size&1) == 0,"prb_size %d is not a multiple of 2\n",pucch_pdu->prb_size); + // 24 PRBs contains 48x16-bit, so 6x8x16-bit + for (int prb=0;prbprb_size;prb+=2) { + for (int aa=0;aa (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext[aa][i],rd_im_ext[aa]); + for (int i=0;i<8;i++) printf("Ant %d PRB %d dmrs[%d] -> (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext_p[i],rd_im_ext_p[i]); + for (int i=0;i<16;i++) printf("Ant %d PRB %d data[%d] -> (%d,%d)\n",aa,prb+(i>>3),i,r_re_ext_p[i],r_im_ext_p[i]); #endif - } // aa - } // prb + rp[aa]+=48; + } // aa + } // prb - // first compute DMRS component - uint32_t x1, x2, s=0; - x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause + // first compute DMRS component + uint32_t x1, x2, s=0; + x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause #ifdef DEBUG_NR_PUCCH_RX - printf("slot %d, start_symbol_index %d, dmrs_scrambling_id %d\n", - slot,pucch_pdu->start_symbol_index,pucch_pdu->dmrs_scrambling_id); + printf("slot %d, start_symbol_index %d, dmrs_scrambling_id %d\n", + slot,pucch_pdu->start_symbol_index,pucch_pdu->dmrs_scrambling_id); #endif - s = lte_gold_generic(&x1, &x2, 1); + s = lte_gold_generic(&x1, &x2, 1); + for (int group=0;group>=5; + corr32_im[group][aa]>>=5; #ifdef DEBUG_NR_PUCCH_RX - printf("Group %d: rd ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n", - group, - rd_re_ext[aa][4],rd_im_ext[aa][4], - rd_re_ext[aa][5],rd_im_ext[aa][5], - rd_re_ext[aa][6],rd_im_ext[aa][6], - rd_re_ext[aa][7],rd_im_ext[aa][7]); + printf("Group %d: corr32 (%d,%d)\n",group,corr32_re[group][aa],corr32_im[group][aa]); #endif - corr32_re[group][aa]+=(rd_re_ext[aa][4]*((int16_t*)&dmrs_re)[0] + rd_im_ext[aa][4]*((int16_t*)&dmrs_im)[0]); - corr32_im[group][aa]+=(-rd_re_ext[aa][4]*((int16_t*)&dmrs_im)[0] + rd_im_ext[aa][4]*((int16_t*)&dmrs_re)[0]); - corr32_re[group][aa]+=(rd_re_ext[aa][5]*((int16_t*)&dmrs_re)[1] + rd_im_ext[aa][5]*((int16_t*)&dmrs_im)[1]); - corr32_im[group][aa]+=(-rd_re_ext[aa][5]*((int16_t*)&dmrs_im)[1] + rd_im_ext[aa][5]*((int16_t*)&dmrs_re)[1]); - corr32_re[group][aa]+=(rd_re_ext[aa][6]*((int16_t*)&dmrs_re)[2] + rd_im_ext[aa][6]*((int16_t*)&dmrs_im)[2]); - corr32_im[group][aa]+=(-rd_re_ext[aa][6]*((int16_t*)&dmrs_im)[2] + rd_im_ext[aa][6]*((int16_t*)&dmrs_re)[2]); - corr32_re[group][aa]+=(rd_re_ext[aa][7]*((int16_t*)&dmrs_re)[3] + rd_im_ext[aa][7]*((int16_t*)&dmrs_im)[3]); - corr32_im[group][aa]+=(-rd_re_ext[aa][7]*((int16_t*)&dmrs_im)[3] + rd_im_ext[aa][7]*((int16_t*)&dmrs_re)[3]); - corr32_re[group][aa]>>=5; - corr32_im[group][aa]>>=5; -#ifdef DEBUG_NR_PUCCH_RX - printf("Group %d: corr32 (%d,%d)\n",group,corr32_re[group][aa],corr32_im[group][aa]); -#endif - } //aa + } //aa - if ((group&3) == 3) s = lte_gold_generic(&x1, &x2, 0); - } // group + if ((group&1) == 1) s = lte_gold_generic(&x1, &x2, 0); + } // group } else { // 2 symbol case - AssertFatal(1==0, "Fill in 2 symbol PUCCH2 case\n"); + AssertFatal(1==0, "Fill in 2 symbol PUCCH2 case\n"); } uint32_t x1, x2, s=0; @@ -1174,47 +1295,47 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, for (int aa=0;aabit_len_csi_part1 + pucch_pdu->bit_len_csi_part2 == 0,"no csi for now\n"); - AssertFatal((pucch_pdu->bit_len_harq+pucch_pdu->sr_flag > 2 ) && (pucch_pdu->bit_len_harq+pucch_pdu->sr_flag < 12),"illegal length (%d,%d)\n",pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); - int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag; - __m256i *rp_re[Prx2]; - __m256i *rp2_re[Prx2]; - __m256i *rp_im[Prx2]; - __m256i *rp2_im[Prx2]; - for (int aa=0;aa>1], - ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[1+(i>>1)]); - } printf("\n"); #endif - // do complex correlation - for (int aa=0;aa corr) { - corr = corr_tmp; - cw_ML=cw; - } } - uint8_t corr_dB = dB_fixed64((uint64_t)corr); - LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB); - uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; + int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag+pucch_pdu->bit_len_csi_part1+pucch_pdu->bit_len_csi_part2; + AssertFatal(nb_bit > 2 && nb_bit< 65,"illegal length (%d : %d,%d,%d,%d)\n",nb_bit,pucch_pdu->bit_len_harq,pucch_pdu->sr_flag,pucch_pdu->bit_len_csi_part1,pucch_pdu->bit_len_csi_part2); - - int harq_bytes=pucch_pdu->bit_len_harq>>3; - if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; - uci_pdu->harq.harq_payload = (uint8_t*)malloc(harq_bytes); - uci_pdu->harq.harq_crc = 2; - for (int i=0;iharq.harq_payload[i] = cw_ML & 255; - cw_ML>>=8; + uint64_t decodedPayload[2]; + uint8_t corr_dB; + int decoderState=2; + if (nb_bit < 12) { // short blocklength case + __m256i *rp_re[Prx2]; + __m256i *rp2_re[Prx2]; + __m256i *rp_im[Prx2]; + __m256i *rp2_im[Prx2]; + for (int aa=0;aa>1], + ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[1+(i>>1)]); + } + printf("\n"); +#endif + // do complex correlation + for (int aa=0;aa (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa, + ((int16_t*)&prod_re[aa])[0],((int16_t*)&prod_re[aa])[1],((int16_t*)&prod_re[aa])[2],((int16_t*)&prod_re[aa])[3], + ((int16_t*)&prod_re[aa])[4],((int16_t*)&prod_re[aa])[5],((int16_t*)&prod_re[aa])[6],((int16_t*)&prod_re[aa])[7], + ((int16_t*)&prod_re[aa])[8],((int16_t*)&prod_re[aa])[9],((int16_t*)&prod_re[aa])[10],((int16_t*)&prod_re[aa])[11], + ((int16_t*)&prod_re[aa])[12],((int16_t*)&prod_re[aa])[13],((int16_t*)&prod_re[aa])[14],((int16_t*)&prod_re[aa])[15]); + printf("prod_im[%d] => (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa, + ((int16_t*)&prod_im[aa])[0],((int16_t*)&prod_im[aa])[1],((int16_t*)&prod_im[aa])[2],((int16_t*)&prod_im[aa])[3], + ((int16_t*)&prod_im[aa])[4],((int16_t*)&prod_im[aa])[5],((int16_t*)&prod_im[aa])[6],((int16_t*)&prod_im[aa])[7], + ((int16_t*)&prod_im[aa])[8],((int16_t*)&prod_im[aa])[9],((int16_t*)&prod_im[aa])[10],((int16_t*)&prod_im[aa])[11], + ((int16_t*)&prod_im[aa])[12],((int16_t*)&prod_im[aa])[13],((int16_t*)&prod_im[aa])[14],((int16_t*)&prod_im[aa])[15]); + +#endif + prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1 + prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]); + prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3 + prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]); + prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3+4+5+6+7 + prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]); + prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3+4+5+6+7+8+9+10+11+12+13+14+15 + prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]); + } + int64_t corr_re=0,corr_im=0; + + int64_t corr_tmp = 0; + for (int aa=0;aa corr) { + corr = corr_tmp; + cw_ML=cw; + } + } + corr_dB = dB_fixed64((uint64_t)corr); + LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB); + decodedPayload[0]=(uint64_t)cw_ML; + } + else { // polar coded case + + t_nrPolar_params *currentPtr = nr_polar_params(2,nb_bit,pucch_pdu->prb_size,1,&gNB->uci_polarParams); + __m64 *rp_re[Prx2]; + __m64 *rp2_re[Prx2]; + __m64 *rp_im[Prx2]; + __m64 *rp2_im[Prx2]; + __m128i llrs[pucch_pdu->prb_size*2]; + + for (int aa=0;aa>1]); + } + printf("\n"); + } +#endif + + // non-coherent LLR computation on groups of 4 REs (half-PRBs) + int32_t corr_re,corr_im,corr_tmp; + __m128i corr16,llr_num,llr_den; + uint64_t corr = 0; + + for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) { + llr_num=_mm_set1_epi16(0);llr_den=_mm_set1_epi16(0); + for (int cw=0;cw<256;cw++) { + corr_tmp=0; + for (int aa=0;aa>4],rp_im[aa][half_prb])),5); + prod_im[aa] = _mm_srai_pi16(_mm_subs_pi16(_mm_mullo_pi16(pucch2_polar_4bit[cw&15],rp2_im[aa][half_prb]), + _mm_mullo_pi16(pucch2_polar_4bit[cw>>4],rp2_re[aa][half_prb])),5); + prod_re[aa] = _mm_hadds_pi16(prod_re[aa],prod_re[aa]);// 0+1 + prod_im[aa] = _mm_hadds_pi16(prod_im[aa],prod_im[aa]); + prod_re[aa] = _mm_hadds_pi16(prod_re[aa],prod_re[aa]);// 0+1+2+3 + prod_im[aa] = _mm_hadds_pi16(prod_im[aa],prod_im[aa]); + + // this is for UL CQI measurement + if (cw==0) corr += ((int64_t)corr32_re[half_prb>>2][aa]*corr32_re[half_prb>>2][aa])+ + ((int64_t)corr32_im[half_prb>>2][aa]*corr32_im[half_prb>>2][aa]); + + + corr_re = ( corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_re[aa]))[0]); + corr_im = ( corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_im[aa]))[0]); + corr_tmp += corr_re*corr_re + corr_im*corr_im; + /* + LOG_D(PHY,"pucch2 half_prb %d cw %d (%d,%d) aa %d: (%d,%d,%d,%d,%d,%d,%d,%d)x(%d,%d,%d,%d,%d,%d,%d,%d) (%d,%d)+(%d,%d) = (%d,%d) => %d\n", + half_prb,cw,cw&15,cw>>4,aa, + ((int16_t*)&pucch2_polar_4bit[cw&15])[0],((int16_t*)&pucch2_polar_4bit[cw>>4])[0], + ((int16_t*)&pucch2_polar_4bit[cw&15])[1],((int16_t*)&pucch2_polar_4bit[cw>>4])[1], + ((int16_t*)&pucch2_polar_4bit[cw&15])[2],((int16_t*)&pucch2_polar_4bit[cw>>4])[2], + ((int16_t*)&pucch2_polar_4bit[cw&15])[3],((int16_t*)&pucch2_polar_4bit[cw>>4])[3], + ((int16_t*)&rp_re[aa][half_prb])[0],((int16_t*)&rp_im[aa][half_prb])[0], + ((int16_t*)&rp_re[aa][half_prb])[1],((int16_t*)&rp_im[aa][half_prb])[1], + ((int16_t*)&rp_re[aa][half_prb])[2],((int16_t*)&rp_im[aa][half_prb])[2], + ((int16_t*)&rp_re[aa][half_prb])[3],((int16_t*)&rp_im[aa][half_prb])[3], + corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2),corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2), + ((int16_t*)(&prod_re[aa]))[0], + ((int16_t*)(&prod_im[aa]))[0], + corr_re, + corr_im, + corr_tmp); + */ + } + corr16 = _mm_set1_epi16((int16_t)(corr_tmp>>8)); + /* + LOG_D(PHY,"half_prb %d cw %d corr16 %d\n",half_prb,cw,corr_tmp>>8); + */ + llr_num = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_num_lut[cw]),llr_num); + llr_den = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_den_lut[cw]),llr_den); + /* + LOG_D(PHY,"lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n", + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[0], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[1], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[2], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[3], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[4], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[5], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[6], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[7]); + + LOG_D(PHY,"llr_num (%d,%d,%d,%d,%d,%d,%d,%d)\n", + ((int16_t*)&llr_num)[0], + ((int16_t*)&llr_num)[1], + ((int16_t*)&llr_num)[2], + ((int16_t*)&llr_num)[3], + ((int16_t*)&llr_num)[4], + ((int16_t*)&llr_num)[5], + ((int16_t*)&llr_num)[6], + ((int16_t*)&llr_num)[7]); + LOG_D(PHY,"llr_den (%d,%d,%d,%d,%d,%d,%d,%d)\n", + ((int16_t*)&llr_den)[0], + ((int16_t*)&llr_den)[1], + ((int16_t*)&llr_den)[2], + ((int16_t*)&llr_den)[3], + ((int16_t*)&llr_den)[4], + ((int16_t*)&llr_den)[5], + ((int16_t*)&llr_den)[6], + ((int16_t*)&llr_den)[7]); + */ + } + // compute llrs + llrs[half_prb] = _mm_subs_epi16(llr_num,llr_den); + LOG_D(PHY,"llrs[%d] : (%d,%d,%d,%d,%d,%d,%d,%d)\n", + half_prb, + ((int16_t*)&llrs[half_prb])[0], + ((int16_t*)&llrs[half_prb])[1], + ((int16_t*)&llrs[half_prb])[2], + ((int16_t*)&llrs[half_prb])[3], + ((int16_t*)&llrs[half_prb])[4], + ((int16_t*)&llrs[half_prb])[5], + ((int16_t*)&llrs[half_prb])[6], + ((int16_t*)&llrs[half_prb])[7]); + } // half_prb + // run polar decoder on llrs + decoderState = polar_decoder_int16((int16_t*)llrs, decodedPayload, 0, currentPtr); + LOG_D(PHY,"UCI decoderState %d, payload[0] %llux\n",decoderState,(unsigned long long)decodedPayload[0]); + if (decoderState>0) decoderState=1; + corr_dB = dB_fixed64(corr); + LOG_D(PHY,"metric %d dB\n",corr_dB); + } + uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; + uci_pdu->pduBitmap=0; + uci_pdu->rnti=pucch_pdu->rnti; + uci_pdu->handle=pucch_pdu->handle; + uci_pdu->pucch_format=0; + uci_pdu->ul_cqi=corr_dB; + // need to fill these field! + uci_pdu->timing_advance=31; + uci_pdu->rssi=0; + if (pucch_pdu->bit_len_harq>0) { + int harq_bytes=pucch_pdu->bit_len_harq>>3; + if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; + uci_pdu->pduBitmap|=1; + uci_pdu->harq.harq_payload = (uint8_t*)malloc(harq_bytes); + uci_pdu->harq.harq_crc = decoderState > 0 ? 1 : 0; + int i=0; + for (;iharq.harq_payload[i] = decodedPayload[0] & 255; + decodedPayload[0]>>=8; + } + uci_pdu->harq.harq_payload[i] = decodedPayload[0] & ((1<<(pucch_pdu->bit_len_harq&7))-1); + decodedPayload[0] >>= pucch_pdu->bit_len_harq; } if (pucch_pdu->sr_flag == 1) { + uci_pdu->pduBitmap|=2; uci_pdu->sr.sr_bit_len = 1; uci_pdu->sr.sr_payload = malloc(1); - uci_pdu->sr.sr_payload[0] = cw_ML; + uci_pdu->sr.sr_payload[0] = decodedPayload[0]&1; + decodedPayload[0] = decodedPayload[0]>>1; } + // csi + if (pucch_pdu->bit_len_csi_part1>0) { + uci_pdu->pduBitmap|=4; + int csi_part1_bytes=pucch_pdu->bit_len_csi_part1>>3; + if ((pucch_pdu->bit_len_csi_part1&7) > 0) csi_part1_bytes++; + uci_pdu->csi_part1.csi_part1_payload = (uint8_t*)malloc(csi_part1_bytes); + uci_pdu->csi_part1.csi_part1_crc = decoderState > 0 ? 1 : 0; + int i=0; + for (;icsi_part1.csi_part1_payload[i] = decodedPayload[0] & 255; + decodedPayload[0]>>=8; + } + uci_pdu->csi_part1.csi_part1_payload[i] = decodedPayload[0] & ((1<<(pucch_pdu->bit_len_csi_part1&7))-1); + decodedPayload[0] >>= pucch_pdu->bit_len_csi_part1; + } + + if (pucch_pdu->bit_len_csi_part2>0) { + uci_pdu->pduBitmap|=8; + } + } diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c index 7f5872e885..b49443c03c 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c @@ -34,8 +34,9 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, PHY_VARS_NR_UE *ue, - module_id_t eNB_id, - uint8_t subframe, + module_id_t gNB_id, + uint8_t frame, + uint8_t subframe, unsigned char clear, short coef) { @@ -59,8 +60,8 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, temp = 0; for (aa=0; aanb_antennas_rx; aa++) { - Re = ((int16_t*)ue->pbch_vars[eNB_id]->dl_ch_estimates_time[aa])[(i<<1)]; - Im = ((int16_t*)ue->pbch_vars[eNB_id]->dl_ch_estimates_time[aa])[1+(i<<1)]; + Re = ((int16_t*)ue->pbch_vars[gNB_id]->dl_ch_estimates_time[aa])[(i<<1)]; + Im = ((int16_t*)ue->pbch_vars[gNB_id]->dl_ch_estimates_time[aa])[1+(i<<1)]; temp += (Re*Re/2) + (Im*Im/2); } @@ -104,17 +105,19 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, //mac_resynch(); //dl_phy_sync_success(ue->Mod_id,ue->proc.proc_rxtx[0].frame_rx,0,1);//ue->common_vars.eNb_id); ue->UE_mode[0] = PRACH; + ue->prach_resources[gNB_id]->sync_frame = frame; + ue->prach_resources[gNB_id]->init_msg1 = 0; } else { ue->UE_mode[0] = PUSCH; } } - if ( ue->rx_offset < 0 ) - ue->rx_offset += frame_parms->samples_per_frame; + if (ue->rx_offset < 0) + ue->rx_offset += frame_parms->samples_per_frame; - if ( ue->rx_offset >= frame_parms->samples_per_frame ) - ue->rx_offset -= frame_parms->samples_per_frame; + if (ue->rx_offset >= frame_parms->samples_per_frame) + ue->rx_offset -= frame_parms->samples_per_frame; diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h index af06f9a98f..1837664391 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h @@ -75,6 +75,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, PHY_VARS_NR_UE *ue, module_id_t eNB_id, + uint8_t frame, uint8_t subframe, unsigned char clear, short coef); @@ -90,6 +91,7 @@ void phy_adjust_gain_nr(PHY_VARS_NR_UE *ue, uint32_t rx_power_fil_dB, uint8_t eNB_id); -int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index); +int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); + #endif diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c index aa1e2b5ade..860ca11d8c 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c @@ -55,8 +55,9 @@ void print_ints(char *s,int *x) } #endif -int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index) -{ +int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index){ + + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; /* if (ue->frame_parms.mode1_flag == 1) @@ -75,9 +76,6 @@ int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index) //(ue->frame_parms.pdsch_config_common.referenceSignalPower*10))/10)); } - - - void nr_ue_measurements(PHY_VARS_NR_UE *ue, unsigned int subframe_offset, unsigned char N0_symbol, diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index ef22b61260..7cde6e31c1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -29,11 +29,15 @@ * \note * \warning */ + #ifdef USER_MODE #include #include #include #endif + +#include "executables/softmodem-common.h" + #include "nr_transport_proto_ue.h" #include "PHY/CODING/nrPolar_tools/nr_polar_dci_defs.h" #include "PHY/phy_extern_nr_ue.h" @@ -799,20 +803,22 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms, #ifdef NR_PDCCH_DCI_RUN -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, - int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id) { +void nr_pdcch_unscrambling(int16_t *z, + uint16_t scrambling_RNTI, + uint32_t length, + uint16_t pdcch_DMRS_scrambling_id, + int16_t *z2) { int i; uint8_t reset; uint32_t x1, x2, s = 0; uint16_t n_id; //{0,1,...,65535} - uint32_t n_rnti; + uint32_t rnti = (uint32_t) scrambling_RNTI; reset = 1; // x1 is set in first call to lte_gold_generic - //do_common=1; - n_id = pdcch_DMRS_scrambling_id; - n_rnti = (uint32_t)crnti; + n_id = pdcch_DMRS_scrambling_id; + x2 = ((rnti<<16) + n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3 - x2 = (((1<<16)*n_rnti)+n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3 + LOG_D(PHY,"PDCCH Unscrambling x2 %x : scrambling_RNTI %x\n", x2, rnti); for (i = 0; i < length; i++) { if ((i & 0x1f) == 0) { @@ -840,38 +846,48 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, rel15 = &pdcch_vars->pdcch_config[i]; int dci_length = rel15->dci_length; + //int gNB_id = 0; int16_t tmp_e[16*108]; + rnti_t n_rnti; for (int j=0;jnumber_of_candidates;j++) { - LOG_D(PHY,"Trying DCI candidate %d, CCE %d (%d), L %d\n",j,rel15->CCE[j],rel15->CCE[j]*9*6*2,rel15->L[j]); int CCEind = rel15->CCE[j]; int L = rel15->L[j]; uint64_t dci_estimation[2]= {0}; - const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList); + const t_nrPolar_params *currentPtrDCI = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L, 1, &ue->polarList); - nr_pdcch_unscrambling(rel15->rnti, - &ue->frame_parms, - slot, - &pdcch_vars->e_rx[CCEind*108], - tmp_e, - L*108, - // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72, - rel15->coreset.pdcch_dmrs_scrambling_id); + LOG_D(PHY, "Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d\n", j, rel15->number_of_candidates, CCEind, CCEind*9*6*2, L); + + nr_pdcch_unscrambling(&pdcch_vars->e_rx[CCEind*108], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); + + #ifdef DEBUG_DCI_DECODING + uint32_t * z = (uint32_t *) &pdcch_vars->e_rx[CCEind*108]; + for (int index_z = 0; index_z < 96; index_z++){ + for (int i=0; i<9; i++) { + LOG_D(PHY,"z[%d]=(%d,%d) \n", (9*index_z + i), *(int16_t *) &z[index_z + i],*(1 + (int16_t *) &z[index_z + i])); + } + } + #endif uint16_t crc = polar_decoder_int16(tmp_e, dci_estimation, 1, currentPtrDCI); - LOG_D(PHY,"Decoded crc %x\n",crc); - if (crc == rel15->rnti) { + + n_rnti = rel15->rnti; + + if (crc == n_rnti) { + LOG_D(PHY,"Decoded crc %x matches rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format); dci_ind->SFN = frame; dci_ind->slot = slot; - dci_ind->dci_list[dci_ind->number_of_dcis].rnti = rel15->rnti; + dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti; dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind; dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format; dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length; memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8); dci_ind->number_of_dcis++; + } else { + LOG_D(PHY,"Decoded crc %x does not match rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format); } } } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index e5cbc4e07a..1a6006c3ba 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -32,6 +32,7 @@ #include "common/utils/LOG/vcd_signal_dumper.h" #include "PHY/defs_nr_UE.h" +#include "SCHED_NR_UE/harq_nr.h" #include "PHY/phy_extern_nr_ue.h" #include "PHY/CODING/coding_extern.h" #include "PHY/CODING/coding_defs.h" @@ -42,6 +43,7 @@ #include "SIMULATION/TOOLS/sim.h" #include "executables/nr-uesoftmodem.h" #include "PHY/CODING/nrLDPC_extern.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" //#define DEBUG_DLSCH_DECODING //#define ENABLE_PHY_PAYLOAD_DEBUG 1 @@ -132,6 +134,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint memset(dlsch,0,sizeof(NR_UE_DLSCH_t)); dlsch->Kmimo = Kmimo; dlsch->Mdlharq = Mdlharq; + dlsch->number_harq_processes_for_pdsch = Mdlharq; dlsch->Nsoft = Nsoft; dlsch->Mlimit = 4; dlsch->max_ldpc_iterations = max_ldpc_iterations; @@ -142,6 +145,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint if (dlsch->harq_processes[i]) { memset(dlsch->harq_processes[i],0,sizeof(NR_DL_UE_HARQ_t)); + init_downlink_harq_status(dlsch->harq_processes[i]); dlsch->harq_processes[i]->first_tx=1; dlsch->harq_processes[i]->b = (uint8_t*)malloc16(dlsch_bytes); @@ -214,16 +218,16 @@ void nr_dlsch_unscrambling(int16_t* llr, } uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag) + short *dlsch_llr, + NR_DL_FRAME_PARMS *frame_parms, + NR_UE_DLSCH_t *dlsch, + NR_DL_UE_HARQ_t *harq_process, + uint32_t frame, + uint16_t nb_symb_sch, + uint8_t nr_tti_rx, + uint8_t harq_pid, + uint8_t is_crnti, + uint8_t llr8_flag) { #if UE_TIMING_TRACE @@ -263,7 +267,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint8_t dmrs_Type = harq_process->dmrsConfigType; AssertFatal(dmrs_Type == 1 || dmrs_Type == 2,"Illegal dmrs_type %d\n",dmrs_Type); - uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4; + uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4; // should be changed based on MAC parameters uint16_t dmrs_length = get_num_dmrs(harq_process->dlDmrsSymbPos); AssertFatal(dmrs_length == 1 || dmrs_length == 2,"Illegal dmrs_length %d\n",dmrs_length); @@ -317,7 +321,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, 0, harq_process->Nl); A = harq_process->TBS; ret = dlsch->max_ldpc_iterations + 1; @@ -326,7 +330,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, harq_process->Qm,harq_process->Nl); G = harq_process->G; - LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d nb_re_dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, nb_re_dmrs,harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); + LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d (%d) G %d nb_re_dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,A/8,G, nb_re_dmrs,harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb); if ((harq_process->R)<1024) Coderate = (float) (harq_process->R) /(float) 1024; @@ -801,8 +805,8 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, //nfapi_nr_config_request_t *cfg = &phy_vars_ue->nrUE_config; //uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value; - uint8_t nb_re_dmrs = (dmrs_type==1)?6:4; - uint16_t length_dmrs = get_num_dmrs(harq_process->dlDmrsSymbPos); + uint8_t nb_re_dmrs = 12;//(dmrs_type==1)?6:4; + uint16_t length_dmrs = get_num_dmrs(dl_config_pdu->dlDmrsSymbPos); uint32_t i,j; // int nbDlProcessing =0; @@ -854,7 +858,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, 0, harq_process->Nl); A = harq_process->TBS; @@ -1431,7 +1435,7 @@ void nr_dlsch_decoding_process(void *arg) uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, 0, harq_process->Nl); A = harq_process->TBS; //2072 for QPSK 1/3 @@ -1697,10 +1701,10 @@ void nr_dlsch_decoding_process(void *arg) } no_iteration_ldpc = nrLDPC_decoder(p_decParams, - (int8_t*)&pl[0], - llrProcBuf, - p_nrLDPC_procBuf, - p_procTime); + (int8_t*)&pl[0], + llrProcBuf, + p_nrLDPC_procBuf, + p_procTime); // Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) { diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index c704efdb1f..a8827b4e92 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -30,6 +30,7 @@ */ #include "PHY/defs_nr_UE.h" #include "PHY/phy_extern_nr_ue.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "nr_transport_proto_ue.h" //#include "SCHED/defs.h" //#include "PHY/defs.h" @@ -131,7 +132,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, unsigned short nb_rb = 0, round; int avgs = 0;// rb; - NR_DL_UE_HARQ_t *dlsch0_harq,*dlsch1_harq = 0; + NR_DL_UE_HARQ_t *dlsch0_harq, *dlsch1_harq = NULL; uint8_t beamforming_mode; @@ -155,82 +156,93 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, uint16_t n_tx=1, n_rx=1; int32_t median[16]; uint32_t len; - + switch (type) { case SI_PDSCH: - pdsch_vars = &ue->pdsch_vars_SI[eNB_id]; + pdsch_vars = ue->pdsch_vars_SI; dlsch = &ue->dlsch_SI[eNB_id]; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; - beamforming_mode = 0; + beamforming_mode = 0; break; case RA_PDSCH: - pdsch_vars = &ue->pdsch_vars_ra[eNB_id]; + pdsch_vars = ue->pdsch_vars_ra; dlsch = &ue->dlsch_ra[eNB_id]; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; - beamforming_mode = 0; + beamforming_mode = 0; + break; case PDSCH: pdsch_vars = ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]]; dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id]; + beamforming_mode = ue->transmission_mode[eNB_id] < 7 ? 0 :ue->transmission_mode[eNB_id]; + dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; + dlsch1_harq = dlsch[1]->harq_processes[harq_pid]; - dlsch[0]->harq_processes[harq_pid]->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); - dlsch[0]->harq_processes[harq_pid]->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); - - //printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status); - LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", - frame,nr_tti_rx,symbol,harq_pid, - dlsch[0]->harq_processes[harq_pid]->status, - dlsch[1]->harq_processes[harq_pid]->status); + //printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status); + LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", frame, nr_tti_rx, symbol, harq_pid, dlsch0_harq->status, dlsch1_harq->status); - if ((dlsch[0]->harq_processes[harq_pid]->status == ACTIVE) && - (dlsch[1]->harq_processes[harq_pid]->status == ACTIVE)){ - codeword_TB0 = dlsch[0]->harq_processes[harq_pid]->codeword; - codeword_TB1 = dlsch[1]->harq_processes[harq_pid]->codeword; + if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status == ACTIVE)){ + codeword_TB0 = dlsch0_harq->codeword; + codeword_TB1 = dlsch1_harq->codeword; dlsch0_harq = dlsch[codeword_TB0]->harq_processes[harq_pid]; dlsch1_harq = dlsch[codeword_TB1]->harq_processes[harq_pid]; -#ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming both TBs are active\n"); -#endif - } - else if ((dlsch[0]->harq_processes[harq_pid]->status == ACTIVE) && - (dlsch[1]->harq_processes[harq_pid]->status != ACTIVE) ) { - codeword_TB0 = dlsch[0]->harq_processes[harq_pid]->codeword; + + #ifdef DEBUG_HARQ + printf("[DEMOD] I am assuming both TBs are active\n"); + #endif + + } else if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status != ACTIVE) ) { + codeword_TB0 = dlsch0_harq->codeword; + codeword_TB1 = -1; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; dlsch1_harq = NULL; - codeword_TB1 = -1; -#ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming only TB0 is active\n"); -#endif - } - else if ((dlsch[0]->harq_processes[harq_pid]->status != ACTIVE) && - (dlsch[1]->harq_processes[harq_pid]->status == ACTIVE) ){ - codeword_TB1 = dlsch[1]->harq_processes[harq_pid]->codeword; - dlsch0_harq = dlsch[1]->harq_processes[harq_pid]; - dlsch1_harq = NULL; + + #ifdef DEBUG_HARQ + printf("[DEMOD] I am assuming only TB0 is active\n"); + #endif + + } else if ((dlsch0_harq->status != ACTIVE) && (dlsch1_harq->status == ACTIVE)){ codeword_TB0 = -1; -#ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch0_harq->codeword); -#endif - } - else { - LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n",nr_tti_rx); + codeword_TB1 = dlsch1_harq->codeword; + dlsch0_harq = NULL; + dlsch1_harq = dlsch[1]->harq_processes[codeword_TB1]; + + #ifdef DEBUG_HARQ + printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch1_harq->codeword); + #endif + + LOG_E(PHY, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported\n"); + return -1; + + } else { + LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n", nr_tti_rx); return(-1); } - beamforming_mode = ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id]; - break; - default: - LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n",nr_tti_rx,type); - return(-1); - break; + break; + + default: + LOG_E(PHY, "[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n", nr_tti_rx, type); + return(-1); + break; + } -#ifdef DEBUG_HARQ - printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode); - printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1); -#endif + + if (dlsch0_harq == NULL) { + LOG_E(PHY, "Done\n"); + return -1; + } + + dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); + dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); + + #ifdef DEBUG_HARQ + printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode); + printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1); + #endif start_rb = dlsch0_harq->start_rb; nb_rb_pdsch = dlsch0_harq->nb_rb; @@ -269,7 +281,6 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, return(-1); } - if (dlsch0_harq->mimo_mode==NR_DUALSTREAM) { DevAssert(dlsch1_harq); } @@ -363,7 +374,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, nr_tti_rx, ue->high_speed_flag, frame_parms); - + } /*else if(beamforming_mode>7) { LOG_W(PHY,"dlsch_demodulation: beamforming mode not supported yet.\n"); }*/ @@ -624,7 +635,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, write_output("rho2_mrc.m","rho2_0",&pdsch_vars[eNB_id]->dl_ch_rho2_ext[0][symbol*frame_parms->N_RB_DL*12],frame_parms->N_RB_DL*12,1,1);//should be almost 0 } */ } - } + } //printf("start compute LLR\n"); if (dlsch0_harq->mimo_mode == NR_DUALSTREAM) { @@ -655,19 +666,19 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, // -> // compute @pointer where llrs should filled for this ofdm-symbol if (first_symbol_flag==1) pdsch_vars[eNB_id]->llr_offset[symbol-1] = 0; - llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1]; - //pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0]; - //pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1]; - pllr_symbol_layer0 = pdsch_vars[eNB_id]->layer_llr[0]; - pllr_symbol_layer1 = pdsch_vars[eNB_id]->layer_llr[1]; - pllr_symbol_layer0 += llr_offset_symbol; - pllr_symbol_layer1 += llr_offset_symbol; - pllr_symbol_cw0 = pdsch_vars[eNB_id]->llr[0]; - pllr_symbol_cw1 = pdsch_vars[eNB_id]->llr[1]; - pllr_symbol_cw0 += llr_offset_symbol; - pllr_symbol_cw1 += llr_offset_symbol; - - pdsch_vars[eNB_id]->llr_offset[symbol] = len*dlsch0_harq->Qm + llr_offset_symbol; + llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1]; + //pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0]; + //pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1]; + pllr_symbol_layer0 = pdsch_vars[eNB_id]->layer_llr[0]; + pllr_symbol_layer1 = pdsch_vars[eNB_id]->layer_llr[1]; + pllr_symbol_layer0 += llr_offset_symbol; + pllr_symbol_layer1 += llr_offset_symbol; + pllr_symbol_cw0 = pdsch_vars[eNB_id]->llr[0]; + pllr_symbol_cw1 = pdsch_vars[eNB_id]->llr[1]; + pllr_symbol_cw0 += llr_offset_symbol; + pllr_symbol_cw1 += llr_offset_symbol; + + pdsch_vars[eNB_id]->llr_offset[symbol] = len*dlsch0_harq->Qm + llr_offset_symbol; /*LOG_I(PHY,"compute LLRs [symbol %d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %x @LLR Buff(symb) %x\n", symbol, @@ -689,13 +700,13 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, case 2 : if ((rx_type==rx_standard) || (codeword_TB1 == -1)) { nr_dlsch_qpsk_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pllr_symbol_cw0, - symbol, - len, - first_symbol_flag, - nb_rb, - beamforming_mode); + pdsch_vars[eNB_id]->rxdataF_comp0, + pllr_symbol_cw0, + symbol, + len, + first_symbol_flag, + nb_rb, + beamforming_mode); } else if (codeword_TB0 == -1){ @@ -964,46 +975,47 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, return(-1); break; } + if (dlsch1_harq) { - switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) { - case 2 : - if (rx_type==rx_standard) { - nr_dlsch_qpsk_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pllr_symbol_cw0, - symbol,len,first_symbol_flag,nb_rb, - beamforming_mode); + switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) { + case 2 : + if (rx_type==rx_standard) { + nr_dlsch_qpsk_llr(frame_parms, + pdsch_vars[eNB_id]->rxdataF_comp0, + pllr_symbol_cw0, + symbol,len,first_symbol_flag,nb_rb, + beamforming_mode); + } + break; + case 4: + if (rx_type==rx_standard) { + nr_dlsch_16qam_llr(frame_parms, + pdsch_vars[eNB_id]->rxdataF_comp0, + pdsch_vars[eNB_id]->llr[0], + pdsch_vars[eNB_id]->dl_ch_mag0, + symbol,len,first_symbol_flag,nb_rb, + pdsch_vars[eNB_id]->llr128, + beamforming_mode); + } + break; + case 6 : + if (rx_type==rx_standard) { + nr_dlsch_64qam_llr(frame_parms, + pdsch_vars[eNB_id]->rxdataF_comp0, + pllr_symbol_cw0, + pdsch_vars[eNB_id]->dl_ch_mag0, + pdsch_vars[eNB_id]->dl_ch_magb0, + symbol,len,first_symbol_flag,nb_rb, + pdsch_vars[eNB_id]->llr_offset[symbol], + beamforming_mode); + } + break; + default: + LOG_W(PHY,"rx_dlsch.c : Unknown mod_order!!!!\n"); + return(-1); + break; } - break; - case 4: - if (rx_type==rx_standard) { - nr_dlsch_16qam_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pdsch_vars[eNB_id]->llr[0], - pdsch_vars[eNB_id]->dl_ch_mag0, - symbol,len,first_symbol_flag,nb_rb, - pdsch_vars[eNB_id]->llr128, - beamforming_mode); - } - break; - case 6 : - if (rx_type==rx_standard) { - nr_dlsch_64qam_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pllr_symbol_cw0, - pdsch_vars[eNB_id]->dl_ch_mag0, - pdsch_vars[eNB_id]->dl_ch_magb0, - symbol,len,first_symbol_flag,nb_rb, - pdsch_vars[eNB_id]->llr_offset[symbol], - beamforming_mode); - } - break; - default: - LOG_W(PHY,"rx_dlsch.c : Unknown mod_order!!!!\n"); - return(-1); - break; - } - } + } //nr_dlsch_deinterleaving(symbol,bundle_L,(int16_t*)pllr_symbol_cw0,(int16_t*)pllr_symbol_cw0_deint, nb_rb_pdsch); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c index 61748a8e56..5c480d6646 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c @@ -38,6 +38,7 @@ #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" //#include "SCHED/defs.h" //#include "SCHED/extern.h" +#include "common/utils/LOG/vcd_signal_dumper.h" #include "common_lib.h" #include @@ -135,7 +136,7 @@ int nr_pbch_detection(UE_nr_rxtx_proc_t * proc, PHY_VARS_NR_UE *ue, int pbch_ini stop_meas(&ue->dlsch_channel_estimation_stats); #endif - current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im+current_ssb->c_re; + current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im*current_ssb->c_im; // generate a list of SSB structures if (best_ssb == NULL) @@ -213,6 +214,9 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, NR_DL_FRAME_PARMS *fp = &ue->frame_parms; int ret=-1; int rx_power=0; //aarx, + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_IN); + LOG_D(PHY,"nr_initial sync ue RB_DL %d\n", fp->N_RB_DL); @@ -477,6 +481,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, } // exit_fun("debug exit"); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_OUT); return ret; } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c index 60306d8e53..612dc6283d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c @@ -505,7 +505,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, return(-1); } */ - if (symbol==1) { + if (symbol==2) { nr_pbch_quantize(pbch_e_rx, (short *)&(nr_ue_pbch_vars->rxdataF_comp[0][symbol*240]), 144); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 013b5ca4a6..79c542cd61 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -19,13 +19,13 @@ * contact@openairinterface.org */ -/*! \file PHY/LTE_TRANSPORT/prach_common.c - * \brief Common routines for UE/eNB PRACH physical channel V8.6 2009-03 - * \author R. Knopp - * \date 2011 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr +/*! \file PHY/NR_TRANSPORT/nr_prach.c + * \brief Routines for UE PRACH physical channel + * \author R. Knopp, G. Casati + * \date 2019 + * \version 0.2 + * \company Eurecom, Fraunhofer IIS + * \email: knopp@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -35,16 +35,14 @@ #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_UE.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" -#include #include "T.h" -#include - - +//#define NR_PRACH_DEBUG 1 extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; @@ -60,77 +58,77 @@ extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; +extern const char *prachfmt[9]; +extern const char *prachfmt03[4]; +// Note: +// - prach_fmt_id is an ID used to map to the corresponding PRACH format value in prachfmt +// WIP todo: +// - take prach start symbol into account +// - idft for short sequence assumes we are transmitting starting in symbol 0 of a PRACH slot +// - Assumes that PRACH SCS is same as PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below +// - Preamble index different from 0 is not detected by gNB +int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ - - - - - - -int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf ) -{ - - //lte_frame_type_t frame_type = ue->frame_parms.frame_type; - //uint8_t tdd_config = ue->frame_parms.tdd_config; NR_DL_FRAME_PARMS *fp=&ue->frame_parms; - uint16_t rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; - uint8_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - uint8_t restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; - uint8_t preamble_index = ue->prach_resources[eNB_id]->ra_PreambleIndex; - //uint8_t tdd_mapindex = ue->prach_resources[eNB_id]->ra_TDD_map_index; - int16_t *prachF = ue->prach_vars[eNB_id]->prachF; + fapi_nr_config_request_t *nrUE_config = &ue->nrUE_config; + NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_id]; + fapi_nr_ul_config_prach_pdu *prach_pdu = &ue->prach_vars[gNB_id]->prach_pdu; + + uint8_t Mod_id, fd_occasion, preamble_index, restricted_set, not_found; + uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset = 0; + uint16_t preamble_shift = 0, preamble_index0, n_shift_ra, n_shift_ra_bar, d_start, numshift, N_ZC, u, offset, offset2, first_nonzero_root_idx; int16_t prach_tmp[98304*2*4] __attribute__((aligned(32))); - int16_t *prach = prach_tmp; - int16_t *prach2; - int16_t amp = ue->prach_vars[eNB_id]->amp; - int16_t Ncp; - uint16_t NCS=0; - uint16_t *prach_root_sequence_map; - uint16_t preamble_offset,preamble_shift; - uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar; - uint16_t d_start=-1,numshift; - uint16_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); - //uint8_t Nsp=2; - //uint8_t f_ra,t1_ra; - uint16_t N_ZC = (prach_fmt<4)?839:139; - uint8_t not_found; - int16_t *Xu; - uint16_t u; - int32_t Xu_re,Xu_im; - uint16_t offset,offset2; - int prach_start; - int i, prach_len=0; - uint16_t first_nonzero_root_idx=0; + int16_t Ncp = 0, amp, *prach, *prach2, *prachF, *Xu; + int32_t Xu_re, Xu_im, samp_count; + int prach_start, prach_sequence_length, i, prach_len, dftlen, mu, kbar, K, n_ra_prb, k; + //int restricted_Type; -#if defined(OAI_USRP) - prach_start = (ue->rx_offset+subframe*fp->samples_per_subframe-ue->hw_timing_advance-ue->N_TA_offset); -#ifdef NR_PRACH_DEBUG - LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, - prach_start, - ue->rx_offset, - ue->hw_timing_advance, - ue->N_TA_offset); -#endif + prach = prach_tmp; + prachF = ue->prach_vars[gNB_id]->prachF; + amp = ue->prach_vars[gNB_id]->amp; + Mod_id = ue->Mod_id; + prach_sequence_length = nrUE_config->prach_config.prach_sequence_length; + N_ZC = (prach_sequence_length == 0) ? 839:139; + mu = nrUE_config->prach_config.prach_sub_c_spacing; + restricted_set = prach_pdu->restricted_set; + rootSequenceIndex = prach_pdu->root_seq_id; + n_ra_prb = prach_pdu->freq_msg1; + NCS = prach_pdu->num_cs; + prach_fmt_id = prach_pdu->prach_format; + preamble_index = prach_resources->ra_PreambleIndex; + fd_occasion = 0; + prach_len = 0; + dftlen = 0; + first_nonzero_root_idx = 0; + kbar = 1; + K = 24; + k = 12*n_ra_prb - 6*fp->N_RB_UL; + //prachStartSymbol = prach_config_pdu->prach_start_symbol + //restricted_Type = 0; + + compute_nr_prach_seq(nrUE_config->prach_config.prach_sequence_length, + nrUE_config->prach_config.num_prach_fd_occasions_list[fd_occasion].num_root_sequences, + nrUE_config->prach_config.num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index, + ue->X_u); + + if (mu == 0) + samp_count = fp->samples_per_subframe; + else + samp_count = (slot%(fp->slots_per_subframe/2)) ? fp->samples_per_slotN0 : fp->samples_per_slot0; + + #if defined (OAI_USRP) + prach_start = (ue->rx_offset + slot*samp_count - ue->hw_timing_advance - ue->N_TA_offset); + #else //normal case (simulation) + prach_start = slot*samp_count - ue->N_TA_offset; + #endif if (prach_start<0) - prach_start+=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); - - if (prach_start>=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)) - prach_start-=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); - -#else //normal case (simulation) - prach_start = subframe*fp->samples_per_subframe-ue->N_TA_offset; - LOG_D(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, - prach_start, - ue->rx_offset, - ue->hw_timing_advance, - ue->N_TA_offset); - -#endif + prach_start += (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); + if (prach_start >= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME)) + prach_start -= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); // First compute physical root sequence /************************************************************************ @@ -140,41 +138,19 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, * NOTE: Restricted set type B is not implemented *************************************************************************/ - int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - if (prach_fmt<3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt==3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt>3){ - NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; - } - - prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; - - // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index - preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); + prach_root_sequence_map = (prach_sequence_length == 0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; if (restricted_set == 0) { + // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index + preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); // This is the \nu corresponding to the preamble index preamble_shift = (NCS==0)? 0 : (preamble_index % (N_ZC/NCS)); preamble_shift *= NCS; } else { // This is the high-speed case -#ifdef NR_PRACH_DEBUG - LOG_I(PHY,"[UE %d] High-speed mode, NCS_config %d\n",ue->Mod_id,Ncs_config); -#endif + #ifdef NR_PRACH_DEBUG + LOG_I(PHY, "PRACH [UE %d] High-speed mode, NCS %d\n", Mod_id, NCS); + #endif not_found = 1; preamble_index0 = preamble_index; @@ -185,8 +161,9 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, while (not_found == 1) { // current root depending on rootSequenceIndex and preamble_offset int index = (rootSequenceIndex + preamble_offset) % N_ZC; + uint16_t n_group_ra = 0; - if (prach_fmt<4) { + if (prach_fmt_id<4) { // prach_root_sequence_map points to prach_root_sequence_map0_3 DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); } else { @@ -196,8 +173,6 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, u = prach_root_sequence_map[index]; - uint16_t n_group_ra = 0; - if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { n_shift_ra = nr_du[u]/NCS; d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); @@ -231,43 +206,49 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, } // now generate PRACH signal -#ifdef NR_PRACH_DEBUG - - if (NCS>0) - LOG_D(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, prach_ConfigIndex %d, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", - rootSequenceIndex,preamble_index,prach_fmt,prach_ConfigIndex,NCS,Ncs_config,N_ZC/NCS, - preamble_offset,preamble_shift); - -#endif + #ifdef NR_PRACH_DEBUG + if (NCS>0) + LOG_I(PHY, "PRACH [UE %d] generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d\n", Mod_id, + rootSequenceIndex, + preamble_index, + prach_sequence_length == 0 ? prachfmt03[prach_fmt_id] : prachfmt[prach_fmt_id], + NCS, + N_ZC, + preamble_offset, + preamble_shift); + #endif // nsymb = (frame_parms->Ncp==0) ? 14:12; - // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*subframe*nsymb; - int kbar = 1; - int K = 24; - if (prach_fmt == 3) { - K=4; - kbar=10; + // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*slot*nsymb; + + if (prach_sequence_length == 0 && prach_fmt_id == 3) { + K = 4; + kbar = 10; + } else if (prach_sequence_length == 1) { + K = 1; + kbar = 2; } - else if (prach_fmt > 3) { - // Note: Assumes that PRACH SCS is same as PUSCH SCS - K=1; - kbar=2; - } - int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; - int k = (12*n_ra_prb) - 6*fp->N_RB_UL; - k = (12*n_ra_prb) - 6*fp->N_RB_UL; + if (k<0) + k += fp->ofdm_symbol_size; - if (k<0) k+=fp->ofdm_symbol_size; + k *= K; + k += kbar; + k *= 2; - k*=K; - k+=kbar; - - LOG_D(PHY,"placing prach in position %d\n",k); - k*=2; + LOG_I(PHY, "PRACH [UE %d] in slot %d, placing PRACH in position %d, msg1 frequency start %d, preamble_offset %d, first_nonzero_root_idx %d\n", Mod_id, + slot, + k, + n_ra_prb, + preamble_offset, + first_nonzero_root_idx); Xu = (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx]; + #if defined (PRACH_WRITE_OUTPUT_DEBUG) + LOG_M("X_u.m", "X_u", (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx], N_ZC, 1, 1); + #endif + /******************************************************** * * In function init_prach_tables: @@ -282,10 +263,86 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, * *********************************************************/ - AssertFatal(prach_fmt>3,"prach_fmt<=3: Fix this for other formats\n"); - int dftlen=2048; - if (fp->N_RB_UL >= 137) dftlen=4096; - if (fp->threequarter_fs==1) dftlen=(3*dftlen)/4; + if (fp->N_RB_UL <= 100) + AssertFatal(1 == 0, "N_RB_UL %d not support for NR PRACH yet\n", fp->N_RB_UL); + else if (fp->N_RB_UL < 137) { + if (fp->threequarter_fs == 0) { + //40 MHz @ 61.44 Ms/s + //50 MHz @ 61.44 Ms/s + if (prach_sequence_length == 0) { + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 49152; + if (prach_fmt_id == 3) + dftlen = 12288; + } // 839 sequence + else { + switch (mu){ + case 1: + dftlen = 2048; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } + } else { // threequarter sampling + // 40 MHz @ 46.08 Ms/s + if (prach_sequence_length == 0) { + AssertFatal(fp->N_RB_UL <= 107, "cannot do 108..136 PRBs with 3/4 sampling\n"); + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 36864; + if (prach_fmt_id == 3) + dftlen = 9216; + } else { + switch (mu){ + case 1: + dftlen = 1536; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } // short format + } // 3/4 sampling + } // <=50 MHz BW + else if (fp->N_RB_UL <= 273) { + if (fp->threequarter_fs == 0) { + //80,90,100 MHz @ 122.88 Ms/s + if (prach_sequence_length == 0) { + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 98304; + if (prach_fmt_id == 3) + dftlen = 24576; + } + } else { // threequarter sampling + switch (mu){ + case 1: + dftlen = 4096; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } + } else { + AssertFatal(fp->N_RB_UL <= 217, "cannot do more than 217 PRBs with 3/4 sampling\n"); + // 80 MHz @ 92.16 Ms/s + if (prach_sequence_length == 0) { + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 73728; + if (prach_fmt_id == 3) + dftlen = 18432; + } else { + switch (mu){ + case 1: + dftlen = 3072; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } + } for (offset=0,offset2=0; offset>15); prachF[k++]= ((Xu_re*nr_ru[offset2<<1]) - (Xu_im*nr_ru[1+(offset2<<1)]))>>15; prachF[k++]= ((Xu_im*nr_ru[offset2<<1]) + (Xu_re*nr_ru[1+(offset2<<1)]))>>15; + if (k==dftlen) k=0; } - switch (fp->N_RB_UL) { - case 6: - memset((void*)prachF,0,4*1536); - break; + #if defined (PRACH_WRITE_OUTPUT_DEBUG) + LOG_M("prachF.m", "prachF", &prachF[1804], 1024, 1, 1); + LOG_M("Xu.m", "Xu", Xu, N_ZC, 1, 1); + #endif - case 15: - memset((void*)prachF,0,4*3072); - break; + if (prach_sequence_length == 0) { - case 25: - memset((void*)prachF,0,4*6144); - break; + AssertFatal(prach_fmt_id < 4, "Illegal PRACH format %d for sequence length 839\n", prach_fmt_id); - case 50: - memset((void*)prachF,0,4*12288); - break; + switch (prach_fmt_id) { + case 0: + Ncp = 3168; + break; + case 1: + Ncp = 21024; + break; + case 2: + Ncp = 4688; + break; + case 3: + Ncp = 3168; + break; + } - case 75: - memset((void*)prachF,0,4*18432); - break; + } else { - case 100: - if (fp->threequarter_fs == 0) - memset((void*)prachF,0,4*24576); - else - memset((void*)prachF,0,4*18432); - break; + //LOG_D(PHY, "PRACH [UE %d] in slot %d, format %d, msg1 frequency start %d startSymbol %d \n", Mod_id, slot, prachfmt[prach_fmt_id], n_ra_prb, prachStartSymbol); - case 106: - memset((void*)prachF,0,4*24576); - break; -} - - int mu = 1; // numerology is hardcoded. FIXME!!! - switch (prach_fmt) { - case 0: - Ncp = 3168; - break; - - case 1: - Ncp = 2*21024; - break; - - case 2: - Ncp = 4688; - break; - - case 3: - Ncp = 3168; - break; - - case 0xa1: - Ncp = 288/(1<N_RB_UL <= 100) AssertFatal(1==0,"N_RB_UL %d not supported for NR PRACH yet\n",fp->N_RB_UL); else if (fp->N_RB_UL < 137) { // 46.08 or 61.44 Ms/s - if (fp->threequarter_fs==0) { //61.44 Ms/s + if (fp->threequarter_fs == 0) { // full sampling @ 61.44 Ms/s Ncp<<=1; // This is after cyclic prefix (Ncp<<1 samples for 30.72 Ms/s, Ncp<<2 samples for 61.44 Ms/s prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft(IDFT_49152,prachF,prach2,1); - // here we have |empty | Prach49152| - memmove(prach,prach+(49152<<1),(Ncp<<3)); - // here we have |Prefix | Prach49152| - prach_len = 49152+Ncp; - dftlen=49152; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft(IDFT_49152,prachF,prach2,1); + // here we have |empty | Prach49152| + memmove(prach,prach+(49152<<1),(Ncp<<2)); + // here we have |Prefix | Prach49152| + prach_len = 49152+Ncp; + } else if (prach_fmt_id == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft(IDFT_49152,prachF,prach2,1); + memmove(prach2+(49152<<1),prach2,(49152<<2)); + // here we have |empty | Prach49152 | Prach49152| + memmove(prach,prach+(49152<<2),(Ncp<<2)); + // here we have |Prefix | Prach49152 | Prach49152| + prach_len = (49152*2)+Ncp; + } else if (prach_fmt_id == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft(IDFT_49152,prachF,prach2,1); + memmove(prach2+(49152<<1),prach2,(49152<<2)); + // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 + memmove(prach2+(49152<<2),prach2,(49152<<3)); + // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152 + memmove(prach,prach+(49152<<3),(Ncp<<2)); + // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152 + prach_len = (49152*4)+Ncp; + } else if (prach_fmt_id == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s + idft(IDFT_12288,prachF,prach2,1); + memmove(prach2+(12288<<1),prach2,(12288<<2)); + // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 + memmove(prach2+(12288<<2),prach2,(12288<<3)); + // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288 + memmove(prach,prach+(12288<<3),(Ncp<<2)); + // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288 + prach_len = (12288*4)+Ncp; + } + } else { // short PRACH sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_2048,prachF,prach2,1); + // here we have |empty | Prach2048 | + if (prach_fmt_id != 7) { + memmove(prach2+(2048<<1),prach2,(2048<<2)); + prach_len = (2048*2)+Ncp; + } + else prach_len = (2048*1)+Ncp; + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x2048 + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_2048,prachF,prach2,1); + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | + prach_len = (2048*4)+Ncp; + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x2048 + Ncp+=32; + prach2 = prach+(Ncp<<1); + idft(IDFT_2048,prachF,prach2,1); + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 + memmove(prach2+(2048<<3),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | + prach_len = (2048*6)+Ncp; + } else if (prach_fmt_id == 6) { // 12x2048 + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_2048,prachF,prach2,1); + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 + memmove(prach2+(2048<<3),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 + memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| + prach_len = (2048*12)+Ncp; + } } - else if (prach_fmt == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft(IDFT_49152,prachF,prach2,1); - memmove(prach2+(49152<<1),prach2,(49152<<2)); - // here we have |empty | Prach49152 | Prach49152| - memmove(prach,prach+(49152<<2),(Ncp<<3)); - // here we have |Prefix | Prach49152 | Prach49152| - prach_len = (49152*2)+Ncp; - dftlen=49152; - } - else if (prach_fmt == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft(IDFT_49152,prachF,prach2,1); - memmove(prach2+(49152<<1),prach2,(49152<<2)); - // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 - memmove(prach2+(49152<<2),prach2,(49152<<3)); - // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152 - memmove(prach,prach+(49152<<3),(Ncp<<3)); - // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152 - prach_len = (49152*4)+Ncp; - dftlen=49152; - } - else if (prach_fmt == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s - idft(IDFT_12288,prachF,prach2,1); - memmove(prach2+(12288<<1),prach2,(12288<<2)); - // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 - memmove(prach2+(12288<<2),prach2,(12288<<3)); - // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288 - memmove(prach,prach+(12288<<3),(Ncp<<3)); - // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288 - prach_len = (12288*4)+Ncp; - dftlen=12288; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - prach2 = prach+(Ncp<<1); - idft(IDFT_2048,prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - if (prach_fmt != 0xc0) { - memmove(prach2+(2048<<1),prach2,(2048<<2)); - prach_len = (2048*2)+Ncp; - } - else prach_len = (2048*1)+Ncp; - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x2048 - idft(IDFT_2048,prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - memmove(prach2+(2048<<1),prach2,(2048<<2)); - // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | - memmove(prach2+(2048<<2),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | - prach_len = (2048*4)+Ncp; - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x2048 - prach2 = prach+(Ncp<<1); - idft(IDFT_2048,prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - memmove(prach2+(2048<<1),prach2,(2048<<2)); - // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 - memmove(prach2+(2048<<2),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 - memmove(prach2+((2048<<1)*3),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | - prach_len = (2048*6)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x2048 - idft(IDFT_2048,prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - memmove(prach2+(2048<<1),prach2,(2048<<2)); - // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 - memmove(prach2+(2048<<2),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 - memmove(prach2+(2048<<3),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 - memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| - prach_len = (2048*12)+Ncp; - } - - } - else { // 46.08 Ms/s + } else { // threequarter sampling @ 46.08 Ms/s Ncp = (Ncp*3)/2; prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { - idft(IDFT_36864,prachF,prach2,1); - dftlen=36864; - // here we have |empty | Prach73728| - memmove(prach,prach+(36864<<1),(Ncp<<2)); - // here we have |Prefix | Prach73728| - prach_len = (36864*1)+Ncp; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { + idft(IDFT_36864,prachF,prach2,1); + // here we have |empty | Prach73728| + memmove(prach,prach+(36864<<1),(Ncp<<2)); + // here we have |Prefix | Prach73728| + prach_len = (36864*1)+Ncp; + } else if (prach_fmt_id == 1) { + idft(IDFT_36864,prachF,prach2,1); + memmove(prach2+(36864<<1),prach2,(36864<<2)); + // here we have |empty | Prach73728 | Prach73728| + memmove(prach,prach+(36864<<2),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| + prach_len = (36864*2)+Ncp; + } else if (prach_fmt_id == 2) { + idft(IDFT_36864,prachF,prach2,1); + memmove(prach2+(36864<<1),prach2,(36864<<2)); + // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 + memmove(prach2+(36864<<2),prach2,(36864<<3)); + // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 + memmove(prach,prach+(36864<<3),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 + prach_len = (36864*4)+Ncp; + } else if (prach_fmt_id == 3) { + idft(IDFT_9216,prachF,prach2,1); + memmove(prach2+(9216<<1),prach2,(9216<<2)); + // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216 + memmove(prach2+(9216<<2),prach2,(9216<<3)); + // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216 + memmove(prach,prach+(9216<<3),(Ncp<<2)); + // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216 + prach_len = (9216*4)+Ncp; + } + } else { // short sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_1536,prachF,prach2,1); + // here we have |empty | Prach1536 | + if (prach_fmt_id != 7) { + memmove(prach2+(1536<<1),prach2,(1536<<2)); + prach_len = (1536*2)+Ncp; + } else prach_len = (1536*1)+Ncp; + + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | + + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x1536 + + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_1536,prachF,prach2,1); + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | + prach_len = (1536*4)+Ncp; + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_1536,prachF,prach2,1); + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 + memmove(prach2+(1536<<3),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | + prach_len = (1536*6)+Ncp; + } else if (prach_fmt_id == 6) { // 12x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_1536,prachF,prach2,1); + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 + memmove(prach2+(1536<<3),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 + memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| + prach_len = (1536*12)+Ncp; + } } - else if (prach_fmt == 1) { - idft(IDFT_36864,prachF,prach2,1); - dftlen=36864; - memmove(prach2+(36864<<1),prach2,(36864<<2)); - // here we have |empty | Prach73728 | Prach73728| - memmove(prach,prach+(36864<<2),(Ncp<<2)); - // here we have |Prefix | Prach73728 | Prach73728| - prach_len = (36864*2)+Ncp; - } - if (prach_fmt == 2) { - idft(IDFT_36864,prachF,prach2,1); - dftlen=36864; - memmove(prach2+(36864<<1),prach2,(36864<<2)); - // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 - memmove(prach2+(36864<<2),prach2,(36864<<3)); - // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 - memmove(prach,prach+(36864<<3),(Ncp<<2)); - // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 - prach_len = (36864*4)+Ncp; - } - else if (prach_fmt == 3) { - idft(IDFT_9216,prachF,prach2,1); - dftlen=36864; - memmove(prach2+(9216<<1),prach2,(9216<<2)); - // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216 - memmove(prach2+(9216<<2),prach2,(9216<<3)); - // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216 - memmove(prach,prach+(9216<<3),(Ncp<<2)); - // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216 - prach_len = (9216*4)+Ncp; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - idft(IDFT_1536,prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - if (prach_fmt != 0xc0) - memmove(prach2+(1536<<1),prach2,(1536<<2)); - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | - prach_len = (1536*2)+Ncp; - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536 - idft(IDFT_1536,prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - memmove(prach2+(1536<<1),prach2,(1536<<2)); - // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | - memmove(prach2+(1536<<2),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | - prach_len = (1536*4)+Ncp; - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x1536 - idft(IDFT_1536,prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - memmove(prach2+(1536<<1),prach2,(1536<<2)); - // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 - memmove(prach2+(1536<<2),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 - memmove(prach2+((1536<<1)*3),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | - prach_len = (1536*6)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x1536 - idft(IDFT_1536,prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - memmove(prach2+(1536<<1),prach2,(1536<<2)); - // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 - memmove(prach2+(1536<<2),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 - memmove(prach2+(1536<<3),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 - memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| - prach_len = (1536*12)+Ncp; - } } - } - else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s - if (fp->threequarter_fs==0) { //122.88 Ms/s + } else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s + if (fp->threequarter_fs == 0) { // full sampling @ 122.88 Ms/s Ncp<<=2; prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s - idft(IDFT_98304,prachF,prach2,1); - dftlen=98304; - // here we have |empty | Prach98304| - memmove(prach,prach+(98304<<1),(Ncp<<2)); - // here we have |Prefix | Prach98304| - prach_len = (98304*1)+Ncp; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s + idft(IDFT_98304,prachF,prach2,1); + // here we have |empty | Prach98304| + memmove(prach,prach+(98304<<1),(Ncp<<2)); + // here we have |Prefix | Prach98304| + prach_len = (98304*1)+Ncp; + } else if (prach_fmt_id == 1) { + idft(IDFT_98304,prachF,prach2,1); + memmove(prach2+(98304<<1),prach2,(98304<<2)); + // here we have |empty | Prach98304 | Prach98304| + memmove(prach,prach+(98304<<2),(Ncp<<2)); + // here we have |Prefix | Prach98304 | Prach98304| + prach_len = (98304*2)+Ncp; + } else if (prach_fmt_id == 2) { + idft(IDFT_98304,prachF,prach2,1); + memmove(prach2+(98304<<1),prach2,(98304<<2)); + // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304 + memmove(prach2+(98304<<2),prach2,(98304<<3)); + // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304 + memmove(prach,prach+(98304<<3),(Ncp<<2)); + // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304 + prach_len = (98304*4)+Ncp; + } else if (prach_fmt_id == 3) { // 4x6144, Ncp 3168 + idft(IDFT_24576,prachF,prach2,1); + memmove(prach2+(24576<<1),prach2,(24576<<2)); + // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576 + memmove(prach2+(24576<<2),prach2,(24576<<3)); + // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576 + memmove(prach,prach+(24576<<3),(Ncp<<2)); + // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576 + prach_len = (24576*4)+Ncp; + } + } else { // short sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_4096,prachF,prach2,1); + // here we have |empty | Prach4096 | + if (prach_fmt_id != 7) { + memmove(prach2+(4096<<1),prach2,(4096<<2)); + prach_len = (4096*2)+Ncp; + } else prach_len = (4096*1)+Ncp; + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) | + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 4x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_4096,prachF,prach2,1); + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | + prach_len = (4096*4)+Ncp; + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_4096,prachF,prach2,1); + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 + memmove(prach2+(4096<<3),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | + prach_len = (4096*6)+Ncp; + } else if (prach_fmt_id == 6) { // 12x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_4096,prachF,prach2,1); + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 + memmove(prach2+(4096<<3),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 + memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| + prach_len = (4096*12)+Ncp; + } } - else if (prach_fmt == 1) { - idft(IDFT_98304,prachF,prach2,1); - dftlen=98304; - memmove(prach2+(98304<<1),prach2,(98304<<2)); - // here we have |empty | Prach98304 | Prach98304| - memmove(prach,prach+(98304<<2),(Ncp<<2)); - // here we have |Prefix | Prach98304 | Prach98304| - prach_len = (98304*2)+Ncp; - } - else if (prach_fmt == 2) { - idft(IDFT_98304,prachF,prach2,1); - dftlen=98304; - memmove(prach2+(98304<<1),prach2,(98304<<2)); - // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304 - memmove(prach2+(98304<<2),prach2,(98304<<3)); - // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304 - memmove(prach,prach+(98304<<3),(Ncp<<2)); - // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304 - prach_len = (98304*4)+Ncp; - } - else if (prach_fmt == 3) { // 4x6144, Ncp 3168 - idft(IDFT_24576,prachF,prach2,1); - dftlen=24576; - memmove(prach2+(24576<<1),prach2,(24576<<2)); - // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576 - memmove(prach2+(24576<<2),prach2,(24576<<3)); - // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576 - memmove(prach,prach+(24576<<3),(Ncp<<2)); - // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576 - prach_len = (24576*4)+(Ncp<<1); - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - idft(IDFT_4096,prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - if (prach_fmt != 0xc0) { - memmove(prach2+(4096<<1),prach2,(4096<<2)); - prach_len = (4096*2)+Ncp; - } - else prach_len = (4096*1)+Ncp; - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) | - - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x4096 - idft(IDFT_4096,prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - memmove(prach2+(4096<<1),prach2,(4096<<2)); - // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | - memmove(prach2+(4096<<2),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | - prach_len = (4096*4)+Ncp; - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x4096 - idft(IDFT_4096,prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - memmove(prach2+(4096<<1),prach2,(4096<<2)); - // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 - memmove(prach2+(4096<<2),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 - memmove(prach2+((4096<<1)*3),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | - prach_len = (4096*6)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x4096 - idft(IDFT_4096,prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - memmove(prach2+(4096<<1),prach2,(4096<<2)); - // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 - memmove(prach2+(4096<<2),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 - memmove(prach2+(4096<<3),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 - memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| - prach_len = (4096*12)+Ncp; - } - } - else { // 92.16 Ms/s + } else { // three quarter sampling @ 92.16 Ms/s Ncp = (Ncp*3); prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { - idft(IDFT_73728,prachF,prach2,1); - dftlen=73728; - // here we have |empty | Prach73728| - memmove(prach,prach+(73728<<1),(Ncp<<4)); - // here we have |Prefix | Prach73728| - prach_len = (73728*1)+Ncp; - } - else if (prach_fmt == 1) { - idft(IDFT_73728,prachF,prach2,1); - dftlen=73728; - memmove(prach2+(73728<<1),prach2,(73728<<2)); - // here we have |empty | Prach73728 | Prach73728| - memmove(prach,prach+(73728<<2),(Ncp<<4)); - // here we have |Prefix | Prach73728 | Prach73728| - prach_len = (73728*2)+Ncp; - } - if (prach_fmt == 2) { - idft(IDFT_73728,prachF,prach2,1); - dftlen=73728; - memmove(prach2+(73728<<1),prach2,(73728<<2)); - // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 - memmove(prach2+(73728<<2),prach2,(73728<<3)); - // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 - memmove(prach,prach+(73728<<3),(Ncp<<4)); - // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 - prach_len = (73728*4)+Ncp; - } - else if (prach_fmt == 3) { - idft(IDFT_18432,prachF,prach2,1); - dftlen=18432; - memmove(prach2+(18432<<1),prach2,(18432<<2)); - // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 - memmove(prach2+(18432<<2),prach2,(18432<<3)); - // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432 - memmove(prach,prach+(18432<<3),(Ncp<<4)); - // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432 - prach_len = (18432*4)+Ncp; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - idft(IDFT_3072,prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - if (prach_fmt != 0xc0) { - memmove(prach2+(3072<<1),prach2,(3072<<2)); - prach_len = (3072*2)+Ncp; - } - else prach_len = (3072*1)+Ncp; - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x3072 - idft(IDFT_3072,prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - memmove(prach2+(3072<<1),prach2,(3072<<2)); - // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 - memmove(prach2+(3072<<2),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 - memmove(prach2+((3072<<1)*3),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | - prach_len = (3072*6)+Ncp; - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x3072 - idft(IDFT_3072,prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - memmove(prach2+(3072<<1),prach2,(3072<<2)); - // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | - memmove(prach2+(3072<<2),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | - prach_len = (3072*4)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x3072 - idft(IDFT_3072,prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - memmove(prach2+(3072<<1),prach2,(3072<<2)); - // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 - memmove(prach2+(3072<<2),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 - memmove(prach2+(3072<<3),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 - memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| - prach_len = (3072*12)+Ncp; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { + idft(IDFT_73728,prachF,prach2,1); + // here we have |empty | Prach73728| + memmove(prach,prach+(73728<<1),(Ncp<<2)); + // here we have |Prefix | Prach73728| + prach_len = (73728*1)+Ncp; + } else if (prach_fmt_id == 1) { + idft(IDFT_73728,prachF,prach2,1); + memmove(prach2+(73728<<1),prach2,(73728<<2)); + // here we have |empty | Prach73728 | Prach73728| + memmove(prach,prach+(73728<<2),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| + prach_len = (73728*2)+Ncp; + } if (prach_fmt_id == 2) { + idft(IDFT_73728,prachF,prach2,1); + memmove(prach2+(73728<<1),prach2,(73728<<2)); + // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 + memmove(prach2+(73728<<2),prach2,(73728<<3)); + // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 + memmove(prach,prach+(73728<<3),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 + prach_len = (73728*4)+Ncp; + } else if (prach_fmt_id == 3) { + idft(IDFT_18432,prachF,prach2,1); + memmove(prach2+(18432<<1),prach2,(18432<<2)); + // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 + memmove(prach2+(18432<<2),prach2,(18432<<3)); + // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432 + memmove(prach,prach+(18432<<3),(Ncp<<2)); + // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432 + prach_len = (18432*4)+Ncp; + } + } else { // short sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_3072,prachF,prach2,1); + // here we have |empty | Prach3072 | + if (prach_fmt_id != 7) { + memmove(prach2+(3072<<1),prach2,(3072<<2)); + prach_len = (3072*2)+Ncp; + } else prach_len = (3072*1)+Ncp; + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_3072,prachF,prach2,1); + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 + memmove(prach2+(3072<<3),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | + prach_len = (3072*6)+Ncp; + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 4x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_3072,prachF,prach2,1); + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | + prach_len = (3072*4)+Ncp; + } else if (prach_fmt_id == 6) { // 12x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft(IDFT_3072,prachF,prach2,1); + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 + memmove(prach2+(3072<<3),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 + memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| + prach_len = (3072*12)+Ncp; + } } } - } - - - - -#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) - int j; - int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe; - LOG_D( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow ); - - for (i=prach_start,j=0; isamples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME,prach_start+prach_len); i++,j++) { - ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; - ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; } - for (i=0; icommon_vars.txdata[0])[2*i] = prach[2*j]; - ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; - } -#else + #ifdef NR_PRACH_DEBUG + LOG_I(PHY, "PRACH [UE %d] N_RB_UL %d prach_start %d, prach_len %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", Mod_id, + fp->N_RB_UL, + prach_start, + prach_len, + ue->rx_offset, + ue->hw_timing_advance, + ue->N_TA_offset); + #endif - LOG_D( PHY, "prach_start=%d\n", prach_start); + #if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) + int j, overflow = prach_start + prach_len - NR_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe; - for (i=0; icommon_vars.txdata[0][prach_start]))[2*i] = prach[2*i]; - ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1]; - } -#endif + #ifdef NR_PRACH_DEBUG + LOG_I( PHY, "PRACH [UE %d] overflow = %d\n", Mod_id, overflow); + #endif + // prach_start=414.730, overflow=-39470 prach_len=6600 fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME 460.800 prach_start+prach_len 421.330 fp->samples_per_subframe 46080 + // from prach_start=414.730 to prach_start+prach_len 421.330 + for (i = prach_start, j = 0; i < min(fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME, prach_start + prach_len); i++, j++) { + ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; + ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; + } -#if defined(PRACH_WRITE_OUTPUT_DEBUG) - LOG_M("prach_txF0.m","prachtxF0",prachF,prach_len-Ncp,1,1); - LOG_M("prach_tx0.m","prachtx0",prach+(Ncp<<1),prach_len-Ncp,1,1); - LOG_M("txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]),fp->samples_per_subframe,1,1); - exit(-1); -#endif + for (i = 0; i < overflow; i++,j++) { + ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; + ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; + } + #else // simulators + for (i=0; icommon_vars.txdata[0][prach_start]))[2*i] = prach[2*i]; + ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1]; + } + #endif - return signal_energy( (int*)prach, 256 ); + //printf("----------------------\n"); + //for(int ii = prach_start; ii<2*(prach_start + prach_len); ii++){ + // printf("PRACH rx data[%d] = %d\n", ii, ue->common_vars.txdata[0][ii]); + //} + //printf(" \n"); + + #if defined(PRACH_WRITE_OUTPUT_DEBUG) + LOG_M("prach_tx0.m", "prachtx0", prach+(Ncp<<1), prach_len-Ncp, 1, 1); + LOG_M("Prach_txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]), 2*(prach_start+prach_len), 1, 1) + #endif + + return signal_energy((int*)prach, 256); } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index 4aae9ef7b4..bde9ae03f1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -37,6 +37,9 @@ #include #include "nfapi_interface.h" +#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1 +#define NR_PUSCH_y 3 // UCI placeholder bit + // Functions below implement 36-211 and 36-212 /** @addtogroup _PHY_TRANSPORT_ @@ -66,24 +69,6 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulsch,unsigned char N_RB_UL); NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); -void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); - -int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue, - unsigned char eNB_id, - uint8_t subframe, - unsigned char symbol); - -/** \brief Dump OCTAVE/MATLAB files for PMCH debugging - @param phy_vars_ue Pointer to UE variables - @param eNB_id index of eNB in ue variables - @param coded_bits_per_codeword G from 36.211 - @param subframe Index of subframe - @returns 0 on success -*/ -void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe); - - - /** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception. @param stream0_in Input from channel compensated (MR combined) stream 0 @param stream1_in Input from channel compensated (MR combined) stream 1 @@ -1402,8 +1387,10 @@ void ulsch_modulation(int32_t **txdataF, NR_UE_ULSCH_t *ulsch); - - +uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k, + uint16_t start_sc, + uint8_t numDmrsCdmGrpsNoData, + uint8_t dmrs_type); int generate_ue_dlsch_params_from_dci(int frame, @@ -1540,11 +1527,11 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, - int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id); - - - +void nr_pdcch_unscrambling(int16_t *z, + uint16_t scrambling_RNTI, + uint32_t length, + uint16_t pdcch_DMRS_scrambling_id, + int16_t *z2); void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, int mbsfn_flag, @@ -1757,9 +1744,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint8_t is_crnti, uint8_t llr8_flag); - - -int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf ); +int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe); void *dlsch_thread(void *arg); /**@}*/ diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h index bb92508934..6b2d5e7255 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h @@ -42,9 +42,8 @@ #include "UTIL/LISTS/list.h" #endif -#include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h" -//#include "../LTE_TRANSPORT/transport_common.h" + // structures below implement 36-211 and 36-212 diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c index 7299b085bb..4b36f91e69 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c @@ -225,7 +225,6 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, unsigned int crc; NR_UL_UE_HARQ_t *harq_process; uint16_t nb_rb ; - uint8_t nb_symb_sch ; uint32_t A, Z, F; uint32_t *pz; uint8_t mod_order; @@ -263,8 +262,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, /////////// ///////////////////////////////////////////////////////////////////////////////////////// - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_IN); LOG_D(PHY,"ulsch coding nb_rb %d, Nl = %d\n", nb_rb, harq_process->pusch_pdu.nrOfLayers); LOG_D(PHY,"ulsch coding A %d G %d mod_order %d\n", A,G, mod_order); @@ -284,6 +282,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, printf("%02x.",a[i]); printf("\n"); */ + if (A > 3824) { // Add 24-bit crc (polynomial A) to payload crc = crc24a(harq_process->a,A)>>8; @@ -313,7 +312,6 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, memcpy(harq_process->b,harq_process->a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc } - /////////// /////////////////////////////////////////////////////////////////////////// @@ -332,6 +330,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, BG = 1; } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, VCD_FUNCTION_IN); Kb=nr_segmentation(harq_process->b, harq_process->c, harq_process->B, @@ -340,6 +339,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, pz, &harq_process->F, BG); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, VCD_FUNCTION_OUT); F = harq_process->F; Kr = harq_process->K; @@ -390,7 +390,11 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, impp.n_segments=harq_process->C; impp.macro_num=0; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, VCD_FUNCTION_IN); + nrLDPC_encoder(harq_process->c,harq_process->d,*pz,Kb,Kr,BG,&impp); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, VCD_FUNCTION_OUT); //stop_meas(te_stats); //printf("end ldpc encoder -- output\n"); @@ -436,6 +440,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, Tbslbrm = nr_compute_tbslbrm(0,nb_rb,harq_process->pusch_pdu.nrOfLayers,harq_process->C); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, VCD_FUNCTION_IN); nr_rate_matching_ldpc(Ilbrm, Tbslbrm, BG, @@ -447,6 +452,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, Kr-F-2*(*pz), harq_process->pusch_pdu.pusch_data.rv_index, E); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, VCD_FUNCTION_OUT); @@ -465,10 +471,14 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, //stop_meas(rm_stats); //start_meas(i_stats); - nr_interleaving_ldpc(E, + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, VCD_FUNCTION_IN); + + nr_interleaving_ldpc(E, mod_order, harq_process->e+r_offset, harq_process->f+r_offset); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, VCD_FUNCTION_OUT); //stop_meas(i_stats); @@ -489,7 +499,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, memcpy(ulsch->g,harq_process->f,G); // g is the concatenated code block - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_OUT); return(0); } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 69b3421ace..93acda23f8 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -98,6 +98,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t thread_id, int gNB_id) { + LOG_D(PHY,"nr_ue_ulsch_procedures hard_id %d %d.%d\n",harq_pid,frame,slot); + uint32_t available_bits, TBS; uint8_t mod_order, cwd_index, num_of_codewords, l; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; @@ -110,7 +112,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t dmrs_type, nb_dmrs_re_per_rb, number_of_symbols, mcs, Nl; int ap, start_symbol, Nid_cell, i; int sample_offsetF, N_RE_prime, N_PRB_oh; - uint16_t n_rnti, ul_dmrs_symb_pos; + uint16_t ul_dmrs_symb_pos; uint8_t data_existing =0; uint8_t L_ptrs, K_ptrs; // PTRS parameters uint16_t beta_ptrs; // PTRS parameter related to power control @@ -146,7 +148,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, rnti = harq_process_ul_ue->pusch_pdu.rnti; ulsch_ue->Nid_cell = Nid_cell; - nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4); + + nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4)*harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data; N_RE_prime = NR_NB_SC_PER_RB*number_of_symbols - nb_dmrs_re_per_rb*number_dmrs_symbols - N_PRB_oh; @@ -165,6 +168,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, number_of_symbols, nb_dmrs_re_per_rb*number_dmrs_symbols, 0, + 0, harq_process_ul_ue->pusch_pdu.nrOfLayers); uint8_t access_mode = SCHEDULED_ACCESS; @@ -176,38 +180,38 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, TBS = harq_process_ul_ue->pusch_pdu.pusch_data.tb_size; data_existing = 0; - if (IS_SOFTMODEM_NOS1){ + if (IS_SOFTMODEM_NOS1){ data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame, slot, 0, ulsch_input_buffer, TBS/8, &access_mode); - //IP traffic to be transmitted + //IP traffic to be transmitted if(data_existing){ - //harq_process_ul_ue->a = (unsigned char*)calloc(TBS/8, sizeof(unsigned char)); + //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char)); memcpy(harq_process_ul_ue->a, ulsch_input_buffer, TBS/8); - - #ifdef DEBUG_MAC_PDU - LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", TBS/8); - for (i = 0; i < TBS / 8; i++) { - printf("0x%02x",harq_process_ul_ue->a[i]); - } - printf("\n"); - #endif - } + } } //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity if (!IS_SOFTMODEM_NOS1 || !data_existing) { //Use zeros for the header bytes in noS1 mode, in order to make sure that the LCID is not valid //and block this traffic from being forwarded to the upper layers at the gNB - uint16_t payload_offset = 5; LOG_D(PHY, "Random data to be tranmsitted: \n"); - //Give the header bytes some dummy value in order to block the random packet at the MAC layer of the receiver - for (i = 0; ia[i] = 0; - for (i = payload_offset; i < TBS / 8; i++) { + //Give the first byte a dummy value (a value not corresponding to any valid LCID based on 38.321, Table 6.2.1-2) + //in order to distinguish the PHY random packets at the MAC layer of the gNB receiver from the normal packets that should + //have a valid LCID (nr_process_mac_pdu function) + harq_process_ul_ue->a[0] = 0x31; + + for (i = 1; i < TBS / 8; i++) { harq_process_ul_ue->a[i] = (unsigned char) rand(); //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); } } +#ifdef DEBUG_MAC_PDU + LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", TBS/8); + for (i = 0; i < TBS / 8; i++) { + printf("%02x",harq_process_ul_ue->a[i]); + } + printf("\n"); +#endif } else { LOG_E(PHY, "[phy_procedures_nrUE_TX] harq_process_ul_ue is NULL !!\n"); return; @@ -220,7 +224,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, unsigned int G = nr_get_G(nb_rb, number_of_symbols, nb_dmrs_re_per_rb, number_dmrs_symbols, mod_order, Nl); - nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid, G); /////////// @@ -264,7 +267,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////DMRS Modulation///////////////////////// /////////// pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; - n_dmrs = (nb_rb*nb_dmrs_re_per_rb*number_dmrs_symbols); + n_dmrs = (nb_rb*((dmrs_type == pusch_dmrs_type1) ? 6:4)*number_dmrs_symbols); int16_t mod_dmrs[n_dmrs<<1]; /////////// //////////////////////////////////////////////////////////////////////// @@ -301,9 +304,9 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, tx_layers = (int16_t **)pusch_ue->txdataF_layers; nr_ue_layer_mapping(UE->ulsch[thread_id][gNB_id], - Nl, - available_bits/mod_order, - tx_layers); + Nl, + available_bits/mod_order, + tx_layers); /////////// //////////////////////////////////////////////////////////////////////// @@ -365,7 +368,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t k_prime=0; - uint8_t is_dmrs, is_ptrs; + uint8_t is_dmrs, is_ptrs, is_dmrs_symbol; uint16_t m=0, n=0, dmrs_idx=0, ptrs_idx = 0; for (l=start_symbol; l> l) & 0x01) { + is_dmrs_symbol = 1; if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%frame_parms->ofdm_symbol_size)) is_dmrs = 1; } @@ -432,18 +437,24 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ptrs_idx++; - } else { + } else if (!is_dmrs_symbol || allowed_xlsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; - #ifdef DEBUG_PUSCH_MAPPING - printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", - m, l, k, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1], - ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]); - #endif + #ifdef DEBUG_PUSCH_MAPPING + printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", + m, l, k, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1], + ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]); + #endif m++; + + } else { + + ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = 0; + ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = 0; + } if (++k >= frame_parms->ofdm_symbol_size) @@ -453,6 +464,9 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, } //} + NR_UL_UE_HARQ_t *harq_process_ulsch=NULL; + harq_process_ulsch = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]; + harq_process_ulsch->status = SCH_IDLE; /////////// //////////////////////////////////////////////////////////////////////// @@ -498,21 +512,51 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, txdata = UE->common_vars.txdata; txdataF = UE->common_vars.txdataF; - for (ap = 0; ap < Nl; ap++) { + if(UE->N_TA_offset > tx_offset) { + int32_t *tmp_idft_out = (int32_t*)malloc16(frame_parms->get_samples_per_slot(slot, frame_parms) * sizeof(int32_t)); + + for(ap = 0; ap < Nl; ap++) { if (frame_parms->Ncp == 1) { // extended cyclic prefix - PHY_ofdm_mod(txdataF[ap], - &txdata[ap][tx_offset], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); + PHY_ofdm_mod(txdataF[ap], + tmp_idft_out, + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); } else { // normal cyclic prefix - nr_normal_prefix_mod(txdataF[ap], - &txdata[ap][tx_offset], - 14, - frame_parms); + nr_normal_prefix_mod(txdataF[ap], + tmp_idft_out, + 14, + frame_parms); + } + + memcpy((void *) &txdata[ap][frame_parms->samples_per_frame - UE->N_TA_offset + tx_offset], + (void *) tmp_idft_out, + (UE->N_TA_offset - tx_offset) * sizeof(int32_t)); + + memcpy((void *) &txdata[ap][0], + (void *) &tmp_idft_out[UE->N_TA_offset - tx_offset], + (frame_parms->get_samples_per_slot(slot, frame_parms) - UE->N_TA_offset + tx_offset) * sizeof(int32_t)); + } + + free(tmp_idft_out); + } else { // UE->N_TA_offset <= tx_offset + for (ap = 0; ap < Nl; ap++) { + if (frame_parms->Ncp == 1) { // extended cyclic prefix + PHY_ofdm_mod(txdataF[ap], + &txdata[ap][tx_offset-UE->N_TA_offset], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); + } else { // normal cyclic prefix + nr_normal_prefix_mod(txdataF[ap], + &txdata[ap][tx_offset-UE->N_TA_offset], + 14, + frame_parms); } } + } /////////// //////////////////////////////////////////////////// diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c index baf34ade92..c977118df3 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c @@ -38,6 +38,7 @@ #include "PHY/defs_nr_UE.h" #include "PHY/NR_REFSIG/ss_pbch_nr.h" +#include "common/utils/LOG/vcd_signal_dumper.h" #define DEFINE_VARIABLES_PSS_NR_H #include "PHY/NR_REFSIG/pss_nr.h" @@ -672,6 +673,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) int **rxdata = NULL; int fo_flag = PHY_vars_UE->UE_fo_compensation; // flag to enable freq offset estimation and compensation + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_FUNCTION_IN); #ifdef DBG_PSS_NR LOG_M("rxdata0_rand.m","rxd0_rand", &PHY_vars_UE->common_vars.rxdata[0][0], frame_parms->samples_per_frame, 1, 1); @@ -710,6 +712,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) #endif + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_FUNCTION_IN); synchro_position = pss_search_time_nr(rxdata, frame_parms, fo_flag, @@ -717,6 +720,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) (int *)&PHY_vars_UE->common_vars.eNb_id, (int *)&PHY_vars_UE->common_vars.freq_offset); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_FUNCTION_OUT); #if TEST_SYNCHRO_TIMING_PSS @@ -749,6 +753,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) } #endif + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_FUNCTION_OUT); return synchro_position; } diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index c8f7268d04..d2a8e64749 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -54,7 +54,8 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + long pucch_GroupHopping, + long hoppingId, int16_t amp, int nr_tti_tx, uint8_t m0, @@ -111,7 +112,7 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, for (int l=0; lpucch_config_common_nr->pucch_GroupHopping,ue->pucch_config_common_nr->hoppingId,n_hop,nr_tti_tx,&u,&v); // calculating u and v value + nr_group_sequence_hopping(pucch_GroupHopping,hoppingId,n_hop,nr_tti_tx,&u,&v); // calculating u and v value alpha = nr_cyclic_shift_hopping(ue->pucch_config_common_nr->hoppingId,m0,mcs,l,startingSymbolIndex,nr_tti_tx); #ifdef DEBUG_NR_PUCCH_TX printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d)\n",u,v,alpha,l); @@ -799,27 +800,47 @@ void nr_generate_pucch1_old(PHY_VARS_NR_UE *ue, } #endif //0 -inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint32_t B,uint8_t *btilde) __attribute__((always_inline)); -inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint32_t B,uint8_t *btilde) { +inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) __attribute__((always_inline)); +inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) { uint32_t x1, x2, s=0; int i; uint8_t c; // c_init=nRNTI*2^15+n_id according to TS 38.211 Subclause 6.3.2.6.1 //x2 = (rnti) + ((uint32_t)(1+nr_tti_tx)<<16)*(1+(fp->Nid_cell<<1)); x2 = ((rnti)<<15)+n_id; - s = lte_gold_generic(&x1, &x2, 1); #ifdef DEBUG_NR_PUCCH_TX - printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x\n",s); + printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x, M_bit %d\n",s,M_bit); #endif - for (i=0; i>i)&1); - btilde[i] = (((B>>i)&1) ^ c); + uint8_t *btildep=btilde; + int M_bit2=M_bit > 31 ? 32 : (M_bit&31), M_bit3=M_bit; + uint32_t B; + for (int iprime=0;iprime<=(M_bit>>5);iprime++,btildep+=32) { + s = lte_gold_generic(&x1, &x2, (iprime==0) ? 1 : 0); + B=((uint32_t*)B64)[iprime]; + for (int n=0;n>n)&1, + (B>>(n+1))&1, + (B>>(n+2))&1, + (B>>(n+3))&1, + (B>>(n+4))&1, + (B>>(n+5))&1, + (B>>(n+6))&1, + (B>>(n+7))&1 + ); + for (i=0; i>i)&1); + btildep[i] = (((B>>i)&1) ^ c); #ifdef DEBUG_NR_PUCCH_TX - //printf("\t\t\t btilde[%d]=%lx from scrambled bit %d\n",i,btilde[i],((B>>i)&1)); + printf("\t\t\t btilde[%d]=%lx from unscrambled bit %d and scrambling %d (%x)\n",i+(iprime<<5),btilde[i],((B>>i)&1),c,s>>i); #endif + } + M_bit3-=32; + M_bit2=M_bit3 > 31 ? 32 : (M_bit3&31); } + #ifdef DEBUG_NR_PUCCH_TX printf("\t\t [nr_pucch2_3_4_scrambling] scrambling M_bit=%d bits\n", M_bit); #endif @@ -909,24 +930,13 @@ void nr_uci_encoding(uint64_t payload, // CRC bits are not attached, and coding small block lengths (subclause 5.3.3) b[0] = encodeSmallBlock((uint16_t*)&payload,A); } else if (A>=12) { - AssertFatal(1==0,"Polar encoding not supported yet for UCI\n"); - // procedure in subclause 6.3.1.2.1 (UCI encoded by Polar code -> subclause 6.3.1.3.1) - /*if ((A>=360 && E>=1088)||(A>=1013)) { - I_seg = 1; - } else { - I_seg = 0; - }*/ - - /*if (A>=20) { - // parity bits (subclause 5.2.1) computed by setting L=11 and using generator polynomial gCRC11(D) (subclause 5.1) - L=11; - } else if (A<=19) { - // parity bits (subclause 5.2.1) computed by setting L=6 and using generator polynomial gCRC6(D) (subclause 5.1) - L=6; - }*/ - - // code block segmentation and CRC attachment is performed according to subclause 5.2.1 - // polar coding subclause 5.3.1 + AssertFatal(A<65,"Polar encoding not supported yet for UCI with more than 64 bits\n"); + t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_UCI_PUCCH_MESSAGE_TYPE, + A, + nrofPRB, + 1, + NULL); + polar_encoder_fast(&payload, b, 0,0,currentPtr); } } @@ -950,10 +960,10 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, printf("\t [nr_generate_pucch2] start function at slot(nr_tti_tx)=%d with payload=%lu and nr_bit=%d\n",nr_tti_tx, payload, nr_bit); #endif // b is the block of bits transmitted on the physical channel after payload coding - uint64_t b; + uint64_t b[16]; // limit to 1024-bit encoded length // M_bit is the number of bits of block b (payload after encoding) uint16_t M_bit; - nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,&b,&M_bit); + nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,(void*)b,&M_bit); /* * Implementing TS 38.211 * Subclauses 6.3.2.5.1 Scrambling (PUCCH format 2) @@ -1119,7 +1129,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, printf("\t [nr_generate_pucch3_4] start function at slot(nr_tti_tx)=%d with payload=%lu and nr_bit=%d\n", nr_tti_tx, payload, nr_bit); #endif // b is the block of bits transmitted on the physical channel after payload coding - uint64_t b; + uint64_t b[16]; // M_bit is the number of bits of block b (payload after encoding) uint16_t M_bit; // parameter PUCCH-F4-preDFT-OCC-length set of {2,4} -> to use table -1 or -2 @@ -1144,7 +1154,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, //nrofPRB = 2; // only for test purposes if (fmt == pucch_format4_nr) nrofPRB = 1; - nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,&b,&M_bit); + nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,(void*)b,&M_bit); /* * Implementing TS 38.211 * Subclauses 6.3.2.6.1 Scrambling (PUCCH formats 3 and 4) diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h index a2446dccf9..0e81045d66 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h @@ -49,7 +49,8 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + long pucch_GroupHopping, + long hoppingId, int16_t amp, int nr_tti_tx, uint8_t m0, diff --git a/openair1/PHY/TOOLS/Makefile b/openair1/PHY/TOOLS/Makefile index c71717dc87..a59700bb7c 100644 --- a/openair1/PHY/TOOLS/Makefile +++ b/openair1/PHY/TOOLS/Makefile @@ -1,16 +1,16 @@ -lte_dfts_sse4: lte_dfts.c - gcc-7 -O3 -std=gnu99 -msse4.1 -o lte_dfts_sse4 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_sse4: oai_dfts.c + gcc-7 -O3 -std=gnu99 -msse4.1 -o oai_dfts_sse4 oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -lte_dfts_avx2: lte_dfts.c - gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o lte_dfts_avx2 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_avx2: oai_dfts.c + gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o oai_dfts_avx2 oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -lte_dfts_avx2.s: lte_dfts.c - gcc -O2 -std=gnu99 -mavx2 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_avx2.s: oai_dfts.c + gcc -O2 -std=gnu99 -mavx2 -S oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -lte_dfts_sse4.s: lte_dfts.c - gcc -O2 -std=gnu99 -msse4.1 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_sse4.s: oai_dfts.c + gcc -O2 -std=gnu99 -msse4.1 -S oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -dft_cycles_avx2: lte_dfts_avx2 - ./lte_dfts_avx2 | egrep cycles +dft_cycles_avx2: oai_dfts_avx2 + ./oai_dfts_avx2 | egrep cycles diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 67ec027a9d..dfb148d34e 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -9,6 +9,8 @@ * * http://www.openairinterface.org/?page_id=698 * + * Author and copyright: Laurent Thomas, open-cells.com + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -24,8 +26,10 @@ #include #include "nr_phy_scope.h" #include "executables/nr-softmodem-common.h" +#include #define TPUT_WINDOW_LENGTH 100 +#define localBuff(NaMe,SiZe) float NaMe[SiZe]; memset(NaMe,0,sizeof(NaMe)); int otg_enabled; FL_COLOR rx_antenna_colors[4] = {FL_RED,FL_BLUE,FL_GREEN,FL_YELLOW}; @@ -36,836 +40,29 @@ float tput_time_ue[NUMBER_OF_UE_MAX][TPUT_WINDOW_LENGTH] = {{0}}; float tput_ue[NUMBER_OF_UE_MAX][TPUT_WINDOW_LENGTH] = {{0}}; float tput_ue_max[NUMBER_OF_UE_MAX] = {0}; - -static void ia_receiver_on_off( FL_OBJECT *button, long arg) -{ - - if (fl_get_button(button)) { - fl_set_object_label(button, "IA Receiver ON"); - // PHY_vars_UE_g[0][0]->use_ia_receiver = 1; - fl_set_object_color(button, FL_GREEN, FL_GREEN); - } else { - fl_set_object_label(button, "IA Receiver OFF"); - // PHY_vars_UE_g[0][0]->use_ia_receiver = 0; - fl_set_object_color(button, FL_RED, FL_RED); - } -} - -static void dl_traffic_on_off( FL_OBJECT *button, long arg) -{ - - if (fl_get_button(button)) { - fl_set_object_label(button, "DL Traffic ON"); - otg_enabled = 1; - fl_set_object_color(button, FL_GREEN, FL_GREEN); - } else { - fl_set_object_label(button, "DL Traffic OFF"); - otg_enabled = 0; - fl_set_object_color(button, FL_RED, FL_RED); - } -} - -FD_phy_scope_gnb *create_phy_scope_gnb( void ) -{ - - FL_OBJECT *obj; - FD_phy_scope_gnb *fdui = fl_malloc( sizeof *fdui ); - - // Define form - fdui->phy_scope_gnb = fl_bgn_form( FL_NO_BOX, 800, 800 ); - - // This the whole UI box - obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" ); - fl_set_object_color( obj, FL_BLACK, FL_BLACK ); - - // Received signal - fdui->rxsig_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)" ); - fl_set_object_boxtype( fdui->rxsig_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->rxsig_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->rxsig_t, FL_WHITE ); // Label color - fl_set_xyplot_ybounds(fdui->rxsig_t,10,70); - - // Time-domain channel response - fdui->chest_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 410, 20, 370, 100, "SRS Frequency Response (samples, abs)" ); - fl_set_object_boxtype( fdui->chest_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_t, FL_WHITE ); // Label color - - // Frequency-domain channel response - fdui->chest_f = fl_add_xyplot( FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency Response (RE, dB)" ); - fl_set_object_boxtype( fdui->chest_f, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_f, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_f, FL_WHITE ); // Label color - fl_set_xyplot_ybounds( fdui->chest_f,30,70); - - // LLR of PUSCH - fdui->pusch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 260, 500, 200, "PUSCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pusch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pusch_llr, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pusch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pusch_llr,2); - - // I/Q PUSCH comp - fdui->pusch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 260, 240, 200, "PUSCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pusch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pusch_comp, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pusch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pusch_comp,2); - fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); - - // I/Q PUCCH comp (format 1) - fdui->pucch_comp1 = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 480, 240, 100, "PUCCH1 Energy (SR)" ); - fl_set_object_boxtype( fdui->pucch_comp1, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pucch_comp1, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pucch_comp1, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pucch_comp1,2); - // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); - - // I/Q PUCCH comp (fromat 1a/b) - fdui->pucch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 600, 240, 100, "PUCCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pucch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pucch_comp, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pucch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pucch_comp,2); - // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); - - // Throughput on PUSCH - fdui->pusch_tput = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 480, 500, 100, "PUSCH Throughput [frame]/[kbit/s]" ); - fl_set_object_boxtype( fdui->pusch_tput, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pusch_tput, FL_BLACK, FL_WHITE ); - fl_set_object_lcolor( fdui->pusch_tput, FL_WHITE ); // Label color - - // Generic eNB Button - fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 20, 600, 240, 40, "" ); - fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); - fl_set_button(fdui->button_0,0); - otg_enabled = 0; - fl_set_object_label(fdui->button_0, "DL Traffic OFF"); - fl_set_object_color(fdui->button_0, FL_RED, FL_RED); - fl_set_object_callback(fdui->button_0, dl_traffic_on_off, 0 ); - - fl_end_form( ); - fdui->phy_scope_gnb->fdui = fdui; - - return fdui; -} - -void phy_scope_gNB(FD_phy_scope_gnb *form, - PHY_VARS_gNB *phy_vars_gnb, - RU_t *phy_vars_ru, - int UE_id) -{ - int i, arx; //int i,i2,arx,atx,ind,k; - NR_DL_FRAME_PARMS *frame_parms = &phy_vars_gnb->frame_parms; - //int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - //uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE - int16_t **rxsig_t, **rxsig_f; - // int16_t **chest_t=NULL; - // int16_t **chest_f=NULL; - // int16_t *pusch_llr=NULL; - // int32_t *pusch_comp=NULL; - // int32_t *pucch1_comp=NULL; - // int32_t *pucch1_thres=NULL; - // int32_t *pucch1ab_comp=NULL; - // float Re,Im,ymax; - float *llr, *bit; - // float I[nsymb_ce*2], Q[nsymb_ce*2]; - // float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; - float *rxsig_t_dB[nb_antennas_rx]; - float *rxsig_f_dB[nb_antennas_rx]; - float time[frame_parms->samples_per_frame]; - // float freq[nsymb_ce*nb_antennas_rx*nb_antennas_tx]; - // uint32_t total_dlsch_bitrate = phy_vars_gnb->total_dlsch_bitrate; - int coded_bits_per_codeword = 0; - // uint8_t harq_pid; // in TDD config 3 it is sf-2, i.e., can be 0,1,2 - int Qm = 2; - - /* - if (!RC.nrmac[0]->UE_info.active[UE_id]) - return; - - // choose max MCS to compute coded_bits_per_codeword - if (phy_vars_gnb->ulsch[UE_id][0]!=NULL) { - for (harq_pid=0; harq_pid<3; harq_pid++) { - //Qm = cmax(phy_vars_gnb->ulsch[UE_id][0]->harq_processes->Qm,Qm); - } - } - */ - coded_bits_per_codeword = frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti; - - for (arx=0; arxsamples_per_frame,sizeof(float)); - rxsig_f_dB[arx] = (float*) calloc(frame_parms->samples_per_slot_wCP,sizeof(float)); - } - llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero - bit = malloc(coded_bits_per_codeword*sizeof(float)); - - rxsig_t = (int16_t**) phy_vars_ru->common.rxdata; - rxsig_f = (int16_t**) phy_vars_ru->common.rxdataF; - //chest_t = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates_time[eNB_id]; - /* chest_t = (int16_t**) phy_vars_gnb->srs_vars[UE_id].srs_ch_estimates; - chest_f = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates; - pusch_llr = (int16_t*) phy_vars_gnb->pusch_vars[UE_id]->llr; - pusch_comp = (int32_t*) phy_vars_gnb->pusch_vars[UE_id]->rxdataF_comp; - pucch1_comp = (int32_t*) phy_vars_gnb->pucch1_stats[UE_id]; - pucch1_thres = (int32_t*) phy_vars_gnb->pucch1_stats_thres[UE_id]; - pucch1ab_comp = (int32_t*) phy_vars_gnb->pucch1ab_stats[UE_id]; - */ - - // Received signal in time domain of receive antenna 0 - if (rxsig_t != NULL) { - if (rxsig_t[0] != NULL) { - for (i=0; isamples_per_frame; i++) { - rxsig_t_dB[0][i] = 10*log10(1.0+(float) ((rxsig_t[0][2*i])*(rxsig_t[0][2*i])+(rxsig_t[0][2*i+1])*(rxsig_t[0][2*i+1]))); - time[i] = (float) i; - } - - fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],frame_parms->samples_per_frame,"","",""); - } - - for (arx=1; arxsamples_per_frame; i++) { - rxsig_t_dB[arx][i] = 10*log10(1.0+(float) ((rxsig_t[arx][2*i])*(rxsig_t[arx][2*i])+(rxsig_t[arx][2*i+1])*(rxsig_t[arx][2*i+1]))); - } - - fl_add_xyplot_overlay(form->rxsig_t,arx,time,rxsig_t_dB[arx],frame_parms->samples_per_frame,rx_antenna_colors[arx]); - } - } - } - - /* - // Channel Impulse Response - if (chest_t != NULL) { - ymax = 0; - - if (chest_t[0] !=NULL) { - for (i=0; i<(frame_parms->ofdm_symbol_size); i++) { - //i2 = (i+(frame_parms->ofdm_symbol_size>>1))%frame_parms->ofdm_symbol_size; - i2=i; - //time2[i] = (float)(i-(frame_parms->ofdm_symbol_size>>1)); - time2[i] = (float)i; - chest_t_abs[0][i] = 10*log10((float) (1+chest_t[0][2*i2]*chest_t[0][2*i2]+chest_t[0][2*i2+1]*chest_t[0][2*i2+1])); - - if (chest_t_abs[0][i] > ymax) - ymax = chest_t_abs[0][i]; - } - - fl_set_xyplot_data(form->chest_t,time2,chest_t_abs[0],(frame_parms->ofdm_symbol_size),"","",""); - } - - for (arx=1; arxofdm_symbol_size>>3); i++) { - chest_t_abs[arx][i] = 10*log10((float) (1+chest_t[arx][2*i]*chest_t[arx][2*i]+chest_t[arx][2*i+1]*chest_t[arx][2*i+1])); - - if (chest_t_abs[arx][i] > ymax) - ymax = chest_t_abs[arx][i]; - } - - fl_add_xyplot_overlay(form->chest_t,arx,time,chest_t_abs[arx],(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); - fl_set_xyplot_overlay_type(form->chest_t,arx,FL_DASHED_XYPLOT); - } - } - - // Avoid flickering effect - // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); - fl_set_xyplot_ybounds(form->chest_t,0,ymax); - } - */ - - // Channel Frequency Response - if (rxsig_f != NULL) { - if (rxsig_f[0] != NULL) { - for (i=0; isamples_per_slot_wCP; i++) { - rxsig_f_dB[0][i] = 10*log10(1.0+(float) ((rxsig_f[0][2*i])*(rxsig_f[0][2*i])+(rxsig_f[0][2*i+1])*(rxsig_f[0][2*i+1]))); - time[i] = (float) i; - } - - fl_set_xyplot_data(form->chest_t,time,rxsig_f_dB[0],frame_parms->samples_per_slot_wCP,"","",""); - } - } - - /* - - for (arx=0; arxchest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); - fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,3); - fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); - fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,nsymb_ce,"","",""); - - for (arx=1; arxchest_f,1,&freq[arx*nsymb_ce],&chest_f_abs[arx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - - // other tx antennas - if (nb_antennas_tx > 1) { - if (nb_antennas_rx > 1) { - for (atx=1; atxchest_f,(atx<<1)+arx,&freq[((atx<<1)+arx)*nsymb_ce],&chest_f_abs[((atx<<1)+arx)*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - } else { // 1 rx antenna - atx=1; - arx=0; - fl_add_xyplot_overlay(form->chest_f,atx,&freq[atx*nsymb_ce],&chest_f_abs[atx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - } - - // PUSCH LLRs - if (pusch_llr != NULL) { - for (i=0; ipusch_llr,bit,llr,coded_bits_per_codeword,"","",""); - } - - // PUSCH I/Q of MF Output - if (pusch_comp!=NULL) { - ind=0; - - for (k=0; ksymbols_per_tti; k++) { - for (i=0; i<12*frame_parms->N_RB_UL; i++) { - I[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i]; - Q[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1]; - ind++; - } - } - - fl_set_xyplot_data(form->pusch_comp,I,Q,ind,"","",""); - } - - // PUSCH I/Q of MF Output - if (pucch1ab_comp!=NULL) { - for (ind=0; ind<10240; ind++) { - - I_pucch[ind] = (float)pucch1ab_comp[2*(ind)]; - Q_pucch[ind] = (float)pucch1ab_comp[2*(ind)+1]; - A_pucch[ind] = pucch1_comp?(10*log10(pucch1_comp[ind])):0; - B_pucch[ind] = ind; - C_pucch[ind] = pucch1_thres?(float)pucch1_thres[ind]:0; - } - fl_set_xyplot_data(form->pucch_comp,I_pucch,Q_pucch,10240,"","",""); - fl_set_xyplot_data(form->pucch_comp1,B_pucch,A_pucch,1024,"","",""); - fl_add_xyplot_overlay(form->pucch_comp1,1,B_pucch,C_pucch,1024,FL_RED); - fl_set_xyplot_ybounds(form->pucch_comp,-5000,5000); - fl_set_xyplot_xbounds(form->pucch_comp,-5000,5000); - - fl_set_xyplot_ybounds(form->pucch_comp1,0,80); - } - - - // PUSCH Throughput - memmove( tput_time_enb[UE_id], &tput_time_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); - memmove( tput_enb[UE_id], &tput_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); - - tput_time_enb[UE_id][TPUT_WINDOW_LENGTH-1] = (float) 0; -// tput_enb[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0; - - fl_set_xyplot_data(form->pusch_tput,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","",""); - - // fl_get_xyplot_ybounds(form->pusch_tput,&ymin,&ymax); - // fl_set_xyplot_ybounds(form->pusch_tput,0,ymax); - - */ - - fl_check_forms(); - - free(llr); - free(bit); -} - -FD_phy_scope_nrue *create_phy_scope_nrue( void ) -{ - - FL_OBJECT *obj; - FD_phy_scope_nrue *fdui = fl_malloc( sizeof *fdui ); - - // Define form - fdui->phy_scope_nrue = fl_bgn_form( FL_NO_BOX, 800, 900 ); - - // This the whole UI box - obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" ); - fl_set_object_color( obj, FL_BLACK, FL_BLACK ); - - // Received signal - fdui->rxsig_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)" ); - fl_set_object_boxtype( fdui->rxsig_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->rxsig_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->rxsig_t, FL_WHITE ); // Label color - fl_set_xyplot_ybounds(fdui->rxsig_t,10,70); - - // Time-domain channel response - fdui->chest_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 410, 20, 370, 100, "Channel Impulse Response (samples, abs)" ); - fl_set_object_boxtype( fdui->chest_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_t, FL_WHITE ); // Label color - - // Frequency-domain channel response - fdui->chest_f = fl_add_xyplot( FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency Response (RE, dB)" ); - fl_set_object_boxtype( fdui->chest_f, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_f, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_f, FL_WHITE ); // Label color - fl_set_xyplot_ybounds( fdui->chest_f,30,70); - - // LLR of PBCH - fdui->pbch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 260, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pbch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pbch_llr, FL_BLACK, FL_GREEN ); - fl_set_object_lcolor( fdui->pbch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pbch_llr,2); - fl_set_xyplot_xgrid( fdui->pbch_llr,FL_GRID_MAJOR); - //fl_set_xyplot_xbounds( fdui->pbch_llr,0,1920); - - // I/Q PBCH comp - fdui->pbch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 260, 240, 100, "PBCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pbch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pbch_comp, FL_BLACK, FL_GREEN ); - fl_set_object_lcolor( fdui->pbch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pbch_comp,2); - // fl_set_xyplot_xbounds( fdui->pbch_comp,-100,100); - // fl_set_xyplot_ybounds( fdui->pbch_comp,-100,100); - - // LLR of PDCCH - fdui->pdcch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 380, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pdcch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdcch_llr, FL_BLACK, FL_CYAN ); - fl_set_object_lcolor( fdui->pdcch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdcch_llr,2); - - // I/Q PDCCH comp - fdui->pdcch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 380, 240, 100, "PDCCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pdcch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdcch_comp, FL_BLACK, FL_CYAN ); - fl_set_object_lcolor( fdui->pdcch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdcch_comp,2); - fl_set_xyplot_xgrid( fdui->pdcch_llr,FL_GRID_MAJOR); - - // LLR of PDSCH - fdui->pdsch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 500, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pdsch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdsch_llr, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pdsch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdsch_llr,2); - fl_set_xyplot_xgrid( fdui->pdsch_llr,FL_GRID_MAJOR); - - // I/Q PDSCH comp - fdui->pdsch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 500, 240, 200, "PDSCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pdsch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdsch_comp, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pdsch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdsch_comp,2); - - // Throughput on PDSCH - fdui->pdsch_tput = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 720, 500, 100, "PDSCH Throughput [frame]/[kbit/s]" ); - fl_set_object_boxtype( fdui->pdsch_tput, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdsch_tput, FL_BLACK, FL_WHITE ); - fl_set_object_lcolor( fdui->pdsch_tput, FL_WHITE ); // Label color - - // Generic UE Button - fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" ); - fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); - //openair_daq_vars.use_ia_receiver = 0; - fl_set_button(fdui->button_0,0); - fl_set_object_label(fdui->button_0, "IA Receiver OFF"); - fl_set_object_color(fdui->button_0, FL_RED, FL_RED); - fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 ); - fl_hide_object(fdui->button_0); - - fl_end_form( ); - fdui->phy_scope_nrue->fdui = fdui; - - return fdui; -} - -void phy_scope_nrUE(FD_phy_scope_nrue *form, - PHY_VARS_NR_UE *phy_vars_ue, - int eNB_id, - int UE_id, - uint8_t subframe) -{ - int i,arx,atx,ind,k; - NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; - //int nsymb_ce = frame_parms->ofdm_symbol_size;//*frame_parms->symbols_per_tti; - int samples_per_frame = frame_parms->samples_per_frame; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB; - int16_t **rxsig_t; - float **rxsig_t_dB; - float *time; - float *corr; - int16_t **chest_t; - int16_t **chest_f; - int16_t *pdsch_llr; - int16_t *pdsch_comp; - //int16_t *pdsch_mag; - int8_t *pdcch_llr; - int16_t *pdcch_comp; - int16_t *pbch_llr; - int16_t *pbch_comp; - float llr_pbch[1920], bit_pbch[1920]; - float *llr, *bit; - float *llr_pdcch, *bit_pdcch; - float *I, *Q; - int num_pdcch_symbols=2; - int num_re = 4500; - int Qm = 2; - int coded_bits_per_codeword = num_re*Qm; - int symbol, first_symbol=2,nb_re; - int nb_rb_pdsch=50,nb_symb_sch=9; - float ymax=1; - float **chest_t_abs; - float Re,Im; - float *chest_f_abs; - float *freq; - static int overlay = 0; - /* - int frame = phy_vars_ue->proc.proc_rxtx[0].frame_rx; - int mcs = 0; - unsigned char harq_pid = 0; - */ - - /* - if (phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]!=NULL) { - harq_pid = phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->current_harq_pid; - - if (harq_pid>=8) - return; - - mcs = phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->mcs; - - // Button 0 - if(!phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->dl_power_off) { - // we are in TM5 - fl_show_object(form->button_0); - } - } - - if (phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]!=NULL) { - num_pdcch_symbols = phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->num_pdcch_symbols; - } - - // coded_bits_per_codeword = frame_parms->N_RB_DL*12*get_Qm(mcs)*(frame_parms->symbols_per_tti); - if (phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]!=NULL) { - coded_bits_per_codeword = get_G(frame_parms, - phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->nb_rb, - phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->rb_alloc_even, - get_Qm(mcs), - phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->Nl, - num_pdcch_symbols, - frame, - subframe, - beamforming_mode); - } else { - coded_bits_per_codeword = 0; //frame_parms->N_RB_DL*12*get_Qm(mcs)*(frame_parms->symbols_per_tti); - } - */ - I = (float*) calloc(frame_parms->ofdm_symbol_size*frame_parms->symbols_per_slot*2,sizeof(float)); - Q = (float*) calloc(frame_parms->ofdm_symbol_size*frame_parms->symbols_per_slot*2,sizeof(float)); - - chest_t_abs = (float**) malloc(nb_antennas_rx*sizeof(float*)); - - for (arx=0; arxofdm_symbol_size,sizeof(float)); - } - - chest_f_abs = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float)); - freq = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float)); - - llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero - bit = malloc(coded_bits_per_codeword*sizeof(float)); - - llr_pdcch = (float*) calloc(12*frame_parms->N_RB_DL*num_pdcch_symbols*2,sizeof(float)); // init to zero - bit_pdcch = (float*) calloc(12*frame_parms->N_RB_DL*num_pdcch_symbols*2,sizeof(float)); - - rxsig_t = (int16_t**) phy_vars_ue->common_vars.rxdata; - rxsig_t_dB = calloc(nb_antennas_rx,sizeof(float*)); - for (arx=0; arxpbch_vars[eNB_id]->dl_ch_estimates_time; - chest_f = (int16_t**) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates; - - pbch_llr = (int16_t*) phy_vars_ue->pbch_vars[eNB_id]->llr; - pbch_comp = (int16_t*) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]; - - pdcch_llr = (int8_t*) phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->llr; - pdcch_comp = (int16_t*) phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->rxdataF_comp[0]; - pdsch_llr = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->llr[0]; // stream 0 - // pdsch_llr = (int16_t*) phy_vars_ue->lte_ue_pdsch_vars_SI[eNB_id]->llr[0]; // stream 0 - pdsch_comp = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->rxdataF_comp0[0]; - //pdsch_mag = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->dl_ch_mag0[0]; - - // Received signal in time domain of receive antenna 0 - if (rxsig_t != NULL) { - if (rxsig_t[0] != NULL) { - for (i=0; irxsig_t,time,rxsig_t_dB[0],samples_per_frame,"","",""); - } - - /* - for (arx=1; arxrxsig_t,arx,time,rxsig_t_dB[arx],FRAME_LENGTH_COMPLEX_SAMPLES,rx_antenna_colors[arx]); - } - } - */ - } - - if (phy_vars_ue->is_synchronized==0) { - for (ind=0;ind<3;ind++) { - /* - if (pss_corr_ue[ind]) { - for (i=0; ichest_t,time,corr,samples_per_frame,"","",""); - else - fl_add_xyplot_overlay(form->chest_t,ind,time,corr,samples_per_frame,rx_antenna_colors[ind]); - - overlay = 1; - } - */ - } - } - else { - - if (overlay) { //there was a previous overlay - fl_clear_xyplot(form->chest_t); - overlay = 0; - } - - // Channel Impulse Response - if (chest_t != NULL) { - ymax = 0; - - if (chest_t[0] !=NULL) { - for (i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) { - chest_t_abs[0][i] = (float) (chest_t[0][2*i]*chest_t[0][2*i]+chest_t[0][2*i+1]*chest_t[0][2*i+1]); - time[i] = (float) i; - - if (chest_t_abs[0][i] > ymax) - ymax = chest_t_abs[0][i]; - } - - fl_set_xyplot_data(form->chest_t,time,chest_t_abs[0],(frame_parms->ofdm_symbol_size>>3),"","",""); - } - /* - for (arx=1; arxofdm_symbol_size>>3); i++) { - chest_t_abs[arx][i] = (float) (chest_t[arx][4*i]*chest_t[arx][4*i]+chest_t[arx][4*i+1]*chest_t[arx][4*i+1]); - - if (chest_t_abs[arx][i] > ymax) - ymax = chest_t_abs[arx][i]; - } - - fl_add_xyplot_overlay(form->chest_t,arx,time,chest_t_abs[arx],(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); - fl_set_xyplot_overlay_type(form->chest_t,arx,FL_DASHED_XYPLOT); - } - } - */ - // Avoid flickering effect - // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); // Does not always work... - fl_set_xyplot_ybounds(form->chest_t,0,(double) ymax); - } - } - - // Channel Frequency Response (includes 5 complex sample for filter) - if (chest_f != NULL) { - ind = 0; - - for (atx=0; atxofdm_symbol_size; k++) { - freq[ind] = (float)ind; - Re = (float)(chest_f[(atx<<1)+arx][6144+(2*k)]); - Im = (float)(chest_f[(atx<<1)+arx][6144+(2*k)+1]); - - chest_f_abs[ind] = (short)10*log10(1.0+((double)Re*Re + (double)Im*Im)); - ind++; - } - } - } - } - - // tx antenna 0 - //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); - //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); - // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); - //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); - fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","",""); - - /* - for (arx=1; arxchest_f,1,&freq[arx*nsymb_ce],&chest_f_abs[arx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - - // other tx antennas - if (nb_antennas_tx > 1) { - if (nb_antennas_rx > 1) { - for (atx=1; atxchest_f,(atx<<1)+arx,&freq[((atx<<1)+arx)*nsymb_ce],&chest_f_abs[((atx<<1)+arx)*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - } else { // 1 rx antenna - atx=1; - arx=0; - fl_add_xyplot_overlay(form->chest_f,atx,&freq[atx*nsymb_ce],&chest_f_abs[atx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - */ - } - - // PBCH LLRs - if (pbch_llr != NULL) { - for (i=0; i<864; i++) { - llr_pbch[i] = (float) pbch_llr[i]; - bit_pbch[i] = (float) i; - } - - fl_set_xyplot_data(form->pbch_llr,bit_pbch,llr_pbch,864,"","",""); - } - - first_symbol=1; - - // PBCH I/Q of MF Output - if (pbch_comp!=NULL) { - for (symbol=first_symbol; symbol<(first_symbol+3); symbol++) { - if (symbol == 2 || symbol == 6) - nb_re = 72; - else - nb_re = 180; - for (i=0; ipbch_comp,I,Q,432,"","",""); - } - - // PDCCH LLRs - if (pdcch_llr != NULL) { - for (i=0; i<100; i++) { //12*frame_parms->N_RB_DL*2*num_pdcch_symbols - llr_pdcch[i] = (float) pdcch_llr[2*24*9 +i]; - bit_pdcch[i] = (float) i; - } - - fl_set_xyplot_data(form->pdcch_llr,bit_pdcch,llr_pdcch,12*frame_parms->N_RB_DL*num_pdcch_symbols,"","",""); - } - - // PDCCH I/Q of MF Output - if (pdcch_comp!=NULL) { - for (i=0; i<100; i++) { - I[i] = pdcch_comp[2*50*12+2*i]; - Q[i] = pdcch_comp[2*50*12+2*i+1]; - } - fl_set_xyplot_data(form->pdcch_comp,I,Q,12*frame_parms->N_RB_DL*num_pdcch_symbols,"","",""); - } - - // PDSCH LLRs - if (pdsch_llr != NULL) { - for (i=0; ipdsch_llr,0,coded_bits_per_codeword); - fl_set_xyplot_data(form->pdsch_llr,bit,llr,coded_bits_per_codeword,"","",""); - } - - first_symbol = 2; - ind = 0; - // PDSCH I/Q of MF Output - if (pdsch_comp!=NULL) { - for (symbol=0;symbolN_RB_DL*12+i) ]; - Q[ind] = pdsch_comp[2*((first_symbol+symbol)*frame_parms->N_RB_DL*12+i)+1]; - ind++; - } - } - - fl_set_xyplot_data(form->pdsch_comp,I,Q,nb_symb_sch*nb_rb_pdsch*12,"","",""); - } - /* - - // PDSCH Throughput - memmove( tput_time_ue[UE_id], &tput_time_ue[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); - memmove( tput_ue[UE_id], &tput_ue[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); - - tput_time_ue[UE_id][TPUT_WINDOW_LENGTH-1] = (float) frame; - tput_ue[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0; - - if (tput_ue[UE_id][TPUT_WINDOW_LENGTH-1] > tput_ue_max[UE_id]) { - tput_ue_max[UE_id] = tput_ue[UE_id][TPUT_WINDOW_LENGTH-1]; - } - - fl_set_xyplot_data(form->pdsch_tput,tput_time_ue[UE_id],tput_ue[UE_id],TPUT_WINDOW_LENGTH,"","",""); - - fl_set_xyplot_ybounds(form->pdsch_tput,0,tput_ue_max[UE_id]); - */ - - fl_check_forms(); - - free(time); - free(corr); - for (arx=0; arx graph->maxX || maxY > graph->maxY || minX < graph->minX || minY < graph->minY ) { + graph->maxX=max(graph->maxX,maxX); + graph->minX=min(graph->minX,minX); + graph->maxY=max(graph->maxY,maxY); + graph->minY=min(graph->minY,minY); + fl_set_xyplot_ybounds(graph->graph, graph->minY, graph->maxY); + fl_set_xyplot_xbounds(graph->graph, graph->minX, graph->maxX); + } +} + +static void oai_xygraph(OAIgraph_t *graph, float *x, float *y, int len, int layer, int NoAutoScale) { + if (layer==0) + fl_set_xyplot_data(graph->graph,x,y,len,"","",""); + else + fl_add_xyplot_overlay(graph->graph,layer,x,y,len,rx_antenna_colors[layer]); + + if ( NoAutoScale && graph->iteration%NoAutoScale == 0) { + float maxX=0, maxY=0, minX=0, minY=0; + + for (int k=0; kiteration++; +} + +static void genericLogPowerPerAntena(OAIgraph_t *graph, const int nb_ant, const scopeSample_t **data, const int len) { + float *values=malloc(len*sizeof(*values)); + float *time=malloc(len*sizeof(*time)); + + for (int ant=0; antcommon.rxdata) + return; + + NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; + genericLogPowerPerAntena(graph, frame_parms->nb_antennas_rx, + (const scopeSample_t **)phy_vars_ru->common.rxdata, + frame_parms->samples_per_frame); +} + +static void timeResponse (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { + const int len=2*phy_vars_gnb->frame_parms.ofdm_symbol_size; + float values[len]; + float time[len]; + const int ant=0; // display antenna 0 for each UE + + for (int ue=0; uepusch_vars[ue]->ul_ch_estimates_time[ant]; + + if (data != NULL) { + for (int i=0; iframe_parms; + genericLogPowerPerAntena(graph, frame_parms->nb_antennas_rx, + (const scopeSample_t **)phy_vars_ru->common.rxdataF, + frame_parms->samples_per_slot_wCP); +} + +static void puschLLR (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { + //int Qm = 2; + int coded_bits_per_codeword =3*8*6144+12; // (8*((3*8*6144)+12)); // frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti; + float llr[coded_bits_per_codeword]; + float bit[coded_bits_per_codeword]; + + for (int ue=0; uepusch_vars[ue]->llr; + + if (pusch_llr) { + for (int i=0; iframe_parms; + int sz=frame_parms->N_RB_UL*12*frame_parms->symbols_per_slot; + float I[sz], Q[sz]; + + for (int ue=0; uepusch_vars[ue]->rxdataF_comp[0]; + + if (pusch_comp) { + for (int k=0; kpucch1ab_stats[UE_id]; + int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id]; + float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; + + for (int ind=0; ind<10240; ind++) { + I_pucch[ind] = (float)pucch1ab_comp[2*(ind)]; + Q_pucch[ind] = (float)pucch1ab_comp[2*(ind)+1]; + A_pucch[ind] = pucch1_comp?(10*log10(pucch1_comp[ind])):0; + B_pucch[ind] = ind; + int32_t *pucch1_thres = (int32_t *) NULL; // phy_vars_gnb->pucch1_stats_thres[UE_id]; + C_pucch[ind] = pucch1_thres?(float)pucch1_thres[ind]:0; + } + + fl_set_xyplot_data(graph,I_pucch,Q_pucch,10240,"","",""); + fl_set_xyplot_data(graph,B_pucch,A_pucch,1024,"","",""); + fl_add_xyplot_overlay(graph,1,B_pucch,C_pucch,1024,FL_RED); + fl_set_xyplot_ybounds(graph,-5000,5000); + fl_set_xyplot_xbounds(graph,-5000,5000); + fl_set_xyplot_ybounds(graph,0,80); + } + */ +} + +static void pucchIQ (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { +} + +static void puschThroughtput (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { + // PUSCH Throughput + /* + memmove( tput_time_enb[UE_id], &tput_time_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); + memmove( tput_enb[UE_id], &tput_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); + tput_time_enb[UE_id][TPUT_WINDOW_LENGTH-1] = (float) 0; + // tput_enb[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0; + fl_set_xyplot_data(graph,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","",""); + // fl_get_xyplot_ybounds(form->pusch_tput,&ymin,&ymax); + // fl_set_xyplot_ybounds(form->pusch_tput,0,ymax); + */ +} + +static OAI_phy_scope_t *create_phy_scope_gnb(void) { + FL_OBJECT *obj; + OAI_phy_scope_t *fdui = calloc(( sizeof *fdui ),1); + // Define form + fdui->phy_scope = fl_bgn_form( FL_NO_BOX, 800, 800 ); + // This the whole UI box + obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" ); + fl_set_object_color( obj, FL_BLACK, FL_WHITE ); + int curY=0,x,y,w,h; + // Received signal + fdui->graph[0] = gNBcommonGraph( timeSignal, FL_NORMAL_XYPLOT, 0, curY, 400, 100, + "Received Signal (Time-Domain, dB)", FL_RED ); + // Time-domain channel response + fdui->graph[1] = gNBcommonGraph( timeResponse, FL_NORMAL_XYPLOT, 410, curY, 400, 100, + "SRS Frequency Response (samples, abs)", FL_RED ); + fl_get_object_bbox(fdui->graph[0].graph,&x, &y,&w, &h); + curY+=h; + // Frequency-domain channel response + fdui->graph[2] = gNBcommonGraph( frequencyResponse, FL_NORMAL_XYPLOT, 0, curY, 800, 100, + "Channel Frequency Response (RE, dB)", FL_RED ); + fl_get_object_bbox(fdui->graph[2].graph,&x, &y,&w, &h); + curY+=h; + // LLR of PUSCH + fdui->graph[3] = gNBcommonGraph( puschLLR, FL_POINTS_XYPLOT, 0, curY, 500, 200, + "PUSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); + // I/Q PUSCH comp + fdui->graph[4] = gNBcommonGraph( puschIQ, FL_POINTS_XYPLOT, 500, curY, 300, 200, + "PUSCH I/Q of MF Output", FL_YELLOW ); + fl_get_object_bbox(fdui->graph[3].graph,&x, &y,&w, &h); + curY+=h; + // I/Q PUCCH comp (format 1) + fdui->graph[5] = gNBcommonGraph( pucchEnergy, FL_POINTS_XYPLOT, 0, curY, 300, 100, + "PUCCH1 Energy (SR)", FL_YELLOW ); + // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); + // I/Q PUCCH comp (fromat 1a/b) + fdui->graph[6] = gNBcommonGraph( pucchIQ, FL_POINTS_XYPLOT, 500, curY, 300, 100, + "PUCCH I/Q of MF Output", FL_YELLOW ); + fl_get_object_bbox(fdui->graph[6].graph,&x, &y,&w, &h); + curY+=h; + // Throughput on PUSCH + fdui->graph[7] = gNBcommonGraph( puschThroughtput, FL_NORMAL_XYPLOT, 0, curY, 500, 100, + "PUSCH Throughput [frame]/[kbit/s]", FL_WHITE ); + fdui->graph[8].graph=NULL; + fl_end_form( ); + fdui->phy_scope->fdui = fdui; + fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, "LTE UL SCOPE gNB"); + return fdui; +} + +static const int scope_enb_num_ue = 1; +void phy_scope_gNB(OAI_phy_scope_t *form, + PHY_VARS_gNB *phy_vars_gnb, + RU_t *phy_vars_ru, + int UE_id) { + static OAI_phy_scope_t *remeberForm=NULL; + + if (form==NULL) + form=remeberForm; + else + remeberForm=form; + + if (form==NULL) return; + + int i=0; + + while (form->graph[i].graph) { + form->graph[i].gNBfunct(form->graph+i, phy_vars_gnb, phy_vars_ru, UE_id); + i++; + } + + fl_check_forms(); +} + +static void *scope_thread_gNB(void *arg) { + scopeParms_t *p=(scopeParms_t *) arg; + //# ifdef ENABLE_XFORMS_WRITE_STATS + // FILE *gNB_stats = fopen("gNB_stats.txt", "w"); + //#endif + size_t stksize=0; + pthread_attr_t atr= {0}; + pthread_attr_getstacksize(&atr, &stksize); + pthread_attr_setstacksize(&atr,32*1024*1024 ); + sleep(3); // no clean interthread barriers + fl_initialize (p->argc, p->argv, NULL, 0, 0); + int nb_ue=min(NUMBER_OF_UE_MAX, scope_enb_num_ue); + OAI_phy_scope_t *form_gnb = create_phy_scope_gnb(); + + while (!oai_exit) { + phy_scope_gNB(form_gnb, p->gNB, p->ru, nb_ue); + usleep(99*1000); + } + + return NULL; +} + +void gNBinitScope(scopeParms_t *p) { + static scopeParms_t parms; + memcpy(&parms,p,sizeof(parms)); + pthread_t forms_thread; + threadCreate(&forms_thread, scope_thread_gNB, &parms, "scope", -1, OAI_PRIORITY_RT_LOW); +} + +static void ueTimeResponse (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // Received signal in time domain of receive antenna 0 + genericLogPowerPerAntena(graph, phy_vars_ue->frame_parms.nb_antennas_rx, + (const scopeSample_t **) phy_vars_ue->common_vars.rxdata, + phy_vars_ue->frame_parms.samples_per_frame); +} + +static void ueChannelResponse (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // Channel Impulse Response + genericPowerPerAntena(graph, phy_vars_ue->frame_parms.nb_antennas_rx, + (const scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time, + phy_vars_ue->frame_parms.ofdm_symbol_size>>3); +} + +static void uePbchFrequencyResp (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // Channel Frequency Response (includes 5 complex sample for filter) + if (!phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates) + return; + + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB; + scopeSample_t **chest_f = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates; + int ind = 0; + float chest_f_abs[frame_parms->ofdm_symbol_size]; + float freq[frame_parms->ofdm_symbol_size]; + + for (int atx=0; atxofdm_symbol_size; k++) { + freq[ind] = (float)ind; + chest_f_abs[ind] = (short)10*log10(1.0+SquaredNorm(chest_f[(atx<<1)+arx][6144+k])); + ind++; + } + } + } + } + + // tx antenna 0 + //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); + //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); + // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); + //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); + oai_xygraph(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,0,10); +} + +static void uePbchLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PBCH LLRs + if ( !phy_vars_ue->pbch_vars[eNB_id]->llr) + return; + + int16_t *pbch_llr = (int16_t *) phy_vars_ue->pbch_vars[eNB_id]->llr; + float llr_pbch[864], bit_pbch[864]; + + for (int i=0; i<864; i++) { + llr_pbch[i] = (float) pbch_llr[i]; + bit_pbch[i] = (float) i; + } + + oai_xygraph(graph,bit_pbch,llr_pbch,864,0,10); +} + +static void uePbchIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PBCH I/Q of MF Output + if (!phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]) + return; + + scopeSample_t *pbch_comp = (scopeSample_t *) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]; + localBuff(I,180*3); + localBuff(Q,180*3); + int first_symbol=1; + int base=0; + + for (int symbol=first_symbol; symbol<(first_symbol+3); symbol++) { + int nb_re; + + if (symbol == 2 || symbol == 6) + nb_re = 72; + else + nb_re = 180; + + AssertFatal(base+nb_re<180*3,""); + + for (int i=0; ipdcch_vars[0][eNB_id]->llr) + return; + + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + uint8_t nb_antennas_tx = frame_parms->nb_antennas_tx; + scopeSample_t **chest_f = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates; + int ind = 0; + float chest_f_abs[frame_parms->ofdm_symbol_size]; + float freq[frame_parms->ofdm_symbol_size]; + + for (int atx=0; atxofdm_symbol_size; k++) { + freq[ind] = (float)ind; + chest_f_abs[ind] = (short)10*log10(1.0+SquaredNorm(chest_f[(atx<<1)+arx][6144+k])); + ind++; + } + } + } + } + + // tx antenna 0 + //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); + //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); + // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); + //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); + oai_xygraph(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,0,10); +} + +static void uePcchIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PDCCH I/Q of MF Output + if (!phy_vars_ue->pdcch_vars[0][eNB_id]->rxdataF_comp[0]) + return; + + int nb=4*273*12; // 12*frame_parms->N_RB_DL*num_pdcch_symbols + localBuff(I,nb*RX_NB_TH_MAX); + localBuff(Q,nb*RX_NB_TH_MAX); + int base=0; + + for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { + scopeSample_t *pdcch_comp = (scopeSample_t *) phy_vars_ue->pdcch_vars[thr][eNB_id]->rxdataF_comp[0]; + + for (int i=0; i< nb; i++) { + I[base+i] = pdcch_comp[i].r; + Q[base+i] = pdcch_comp[i].i; + } + + base+=nb; + } + + oai_xygraph(graph,I,Q,base,0,10); +} + +static void uePdschLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PDSCH LLRs + if (!phy_vars_ue->pdsch_vars[0][eNB_id]->llr[0]) + return; + + int num_re = 4500; + int Qm = 2; + int coded_bits_per_codeword = num_re*Qm; + localBuff(llr,coded_bits_per_codeword*RX_NB_TH_MAX); + localBuff(bit,coded_bits_per_codeword*RX_NB_TH_MAX); + int base=0; + + for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { + int16_t *pdsch_llr = (int16_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->llr[0]; // stream 0 + + for (int i=0; ipdsch_llr,0,coded_bits_per_codeword); + oai_xygraph(graph,bit,llr,base,0,10); +} + +static void uePdschIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PDSCH I/Q of MF Output + if (!phy_vars_ue->pdsch_vars[0][eNB_id]->rxdataF_comp0[0]) + return; + + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + int sz=7*2*frame_parms->N_RB_DL*12; // size of the malloced buffer + localBuff(I,sz*RX_NB_TH_MAX); + localBuff(Q,sz*RX_NB_TH_MAX); + int base=0; + + for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { + scopeSample_t *pdsch_comp = (scopeSample_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->rxdataF_comp0[0]; + + for (int s=0; s tput_ue_max[UE_id]) { + tput_ue_max[UE_id] = tput_ue[UE_id][TPUT_WINDOW_LENGTH-1]; + } + + fl_set_xyplot_data(form->pdsch_tput,tput_time_ue[UE_id],tput_ue[UE_id],TPUT_WINDOW_LENGTH,"","",""); + + fl_set_xyplot_ybounds(form->pdsch_tput,0,tput_ue_max[UE_id]); + */ +} + +static OAI_phy_scope_t *create_phy_scope_nrue( int ID ) { + FL_OBJECT *obj; + OAI_phy_scope_t *fdui = calloc(( sizeof *fdui ),1); + // Define form + fdui->phy_scope = fl_bgn_form( FL_NO_BOX, 800, 900 ); + // This the whole UI box + obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" ); + fl_set_object_color( obj, FL_BLACK, FL_BLACK ); + int curY=0,x,y,w,h; + // Received signal + fdui->graph[0] = nrUEcommonGraph(ueTimeResponse, + FL_NORMAL_XYPLOT, 0, curY, 400, 100, "Received Signal (Time-Domain, dB)", FL_RED ); + // Time-domain channel response + fdui->graph[1] = nrUEcommonGraph(ueChannelResponse, + FL_NORMAL_XYPLOT, 400, curY, 400, 100, "Channel Impulse Response (samples, abs)", FL_RED ); + fl_get_object_bbox(fdui->graph[0].graph,&x, &y,&w, &h); + curY+=h; + // Frequency-domain channel response + fdui->graph[2] = nrUEcommonGraph(uePbchFrequencyResp, + FL_IMPULSE_XYPLOT, 0, curY, 800, 100, "Channel Frequency data (RE, dB)", FL_RED ); + fl_get_object_bbox(fdui->graph[2].graph,&x, &y,&w, &h); + curY+=h; + // LLR of PBCH + fdui->graph[3] = nrUEcommonGraph(uePbchLLR, + FL_POINTS_XYPLOT, 0, curY, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)", FL_GREEN ); + fl_set_xyplot_xgrid(fdui->graph[3].graph,FL_GRID_MAJOR); + // I/Q PBCH comp + fdui->graph[4] = nrUEcommonGraph(uePbchIQ, + FL_POINTS_XYPLOT, 500, curY, 300, 100, "PBCH I/Q of MF Output", FL_GREEN ); + fl_get_object_bbox(fdui->graph[3].graph,&x, &y,&w, &h); + curY+=h; + // LLR of PDCCH + fdui->graph[5] = nrUEcommonGraph(uePcchLLR, + FL_POINTS_XYPLOT, 0, curY, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)", FL_CYAN ); + // I/Q PDCCH comp + fdui->graph[6] = nrUEcommonGraph(uePcchIQ, + FL_POINTS_XYPLOT, 500, curY, 300, 100, "PDCCH I/Q of MF Output", FL_CYAN ); + fl_get_object_bbox(fdui->graph[5].graph,&x, &y,&w, &h); + curY+=h; + // LLR of PDSCH + fdui->graph[7] = nrUEcommonGraph(uePdschLLR, + FL_POINTS_XYPLOT, 0, curY, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); + // I/Q PDSCH comp + fdui->graph[8] = nrUEcommonGraph(uePdschIQ, + FL_POINTS_XYPLOT, 500, curY, 300, 200, "PDSCH I/Q of MF Output", FL_YELLOW ); + fl_get_object_bbox(fdui->graph[8].graph,&x, &y,&w, &h); + curY+=h; + // Throughput on PDSCH + fdui->graph[9] = nrUEcommonGraph(uePdschThroughput, + FL_NORMAL_XYPLOT, 0, curY, 500, 100, "PDSCH Throughput [frame]/[kbit/s]", FL_WHITE ); + fdui->graph[10].graph=NULL; + // Generic UE Button +#if 0 + fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" ); + fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); + //openair_daq_vars.use_ia_receiver = 0; + fl_set_button(fdui->button_0,0); + fl_set_object_label(fdui->button_0, "IA Receiver OFF"); + fl_set_object_color(fdui->button_0, FL_RED, FL_RED); + fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 ); + fl_hide_object(fdui->button_0); +#endif + fl_end_form( ); + fdui->phy_scope->fdui = fdui; + char buf[100]; + sprintf(buf,"NR DL SCOPE UE %d", ID); + fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, buf); + return fdui; +} + +void phy_scope_nrUE(OAI_phy_scope_t *form, + PHY_VARS_NR_UE *phy_vars_ue, + int eNB_id, + int UE_id) { + static OAI_phy_scope_t *remeberForm=NULL; + + if (form==NULL) + form=remeberForm; + else + remeberForm=form; + + if (form==NULL) + return; + + int i=0; + + while (form->graph[i].graph) { + form->graph[i].nrUEfunct(form->graph+i, phy_vars_ue, eNB_id, UE_id); + i++; + } + + fl_check_forms(); +} + + +static void *nrUEscopeThread(void *arg) { + PHY_VARS_NR_UE *ue=(PHY_VARS_NR_UE *)arg; + size_t stksize; + pthread_attr_t atr; + pthread_attr_getstacksize(&atr, &stksize); + pthread_attr_setstacksize(&atr,32*1024*1024 ); + int fl_argc=1; + char *name="5G-UE-scope"; + fl_initialize (&fl_argc, &name, NULL, 0, 0); + OAI_phy_scope_t *form_nrue=create_phy_scope_nrue(0); + + while (!oai_exit) { + phy_scope_nrUE(form_nrue, + ue, + 0,0); + usleep(99*1000); + } + + pthread_exit((void *)arg); +} + +void nrUEinitScope(PHY_VARS_NR_UE *ue) { + pthread_t forms_thread; + threadCreate(&forms_thread, nrUEscopeThread, ue, "scope", -1, OAI_PRIORITY_RT_LOW); +} + +// Kept to put back the functionality soon +#if 0 //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; //char title[255]; -unsigned char scope_enb_num_ue = 1; //static pthread_t forms_thread; //xforms - - -void reset_stats_gNB(FL_OBJECT *button, - long arg) -{ +static void reset_stats_gNB(FL_OBJECT *button, + long arg) { int i,k; //PHY_VARS_gNB *phy_vars_gNB = RC.gNB[0][0]; for (i=0; idlsch[i][0]->Mlimit; j++) { - phy_vars_gNB->UE_stats[i].dlsch_NAK[k][j]=0; - phy_vars_gNB->UE_stats[i].dlsch_ACK[k][j]=0; - phy_vars_gNB->UE_stats[i].dlsch_trials[k][j]=0; - } - phy_vars_gNB->UE_stats[i].dlsch_l2_errors[k]=0; - phy_vars_gNB->UE_stats[i].ulsch_errors[k]=0; - phy_vars_gNB->UE_stats[i].ulsch_consecutive_errors=0; - phy_vars_gNB->UE_stats[i].dlsch_sliding_cnt=0; - phy_vars_gNB->UE_stats[i].dlsch_NAK_round0=0; - phy_vars_gNB->UE_stats[i].dlsch_mcs_offset=0;*/ - } - } -} - - -static void *scope_thread_gNB(void *arg) { - int UE_id; - int ue_cnt=0; -//# ifdef ENABLE_XFORMS_WRITE_STATS -// FILE *gNB_stats = fopen("gNB_stats.txt", "w"); -//#endif - - while (!oai_exit) { - ue_cnt=0; - - for(UE_id=0; UE_idUE_stats[i].dlsch_NAK[k][j]=0; + phy_vars_gNB->UE_stats[i].dlsch_ACK[k][j]=0; + phy_vars_gNB->UE_stats[i].dlsch_trials[k][j]=0; } + phy_vars_gNB->UE_stats[i].dlsch_l2_errors[k]=0; + phy_vars_gNB->UE_stats[i].ulsch_errors[k]=0; + phy_vars_gNB->UE_stats[i].ulsch_consecutive_errors=0; + phy_vars_gNB->UE_stats[i].dlsch_sliding_cnt=0; + phy_vars_gNB->UE_stats[i].dlsch_NAK_round0=0; + phy_vars_gNB->UE_stats[i].dlsch_mcs_offset=0;*/ } - sleep(1); } - -// printf("%s",stats_buffer); -/*#ifdef ENABLE_XFORMS_WRITE_STATS - - if (eNB_stats) { - rewind (gNB_stats); - fwrite (stats_buffer, 1, len, gNB_stats); - fclose (gNB_stats); - } - -#endif - pthread_exit((void *)arg); -}*/ - - return NULL; } -FD_stats_form * create_form_stats_form( void ) { +static FD_stats_form *create_form_stats_form(int ID) { FL_OBJECT *obj; - FD_stats_form *fdui = fl_malloc( sizeof *fdui ); + FD_stats_form *fdui = calloc(( sizeof *fdui ),1); fdui->vdata = fdui->cdata = NULL; fdui->ldata = 0; fdui->stats_form = fl_bgn_form( FL_NO_BOX, 1115, 900 ); @@ -964,24 +813,8 @@ FD_stats_form * create_form_stats_form( void ) { fdui->stats_form->fdui = fdui; return fdui; } +#endif + + -void startScope(scopeParms_t * p) { - //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; - char title[255]; - fl_initialize (p->argc, p->argv, NULL, 0, 0); - /* - form_stats_l2 = create_form_stats_form(); - fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats"); - form_stats = create_form_stats_form(); - fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats"); - */ - - for(int UE_id=0; UE_idphy_scope_gnb, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - } // UE_id - pthread_t forms_thread; - threadCreate(&forms_thread, scope_thread_gNB, NULL, "scope", -1, OAI_PRIORITY_RT_LOW); -} diff --git a/openair1/PHY/TOOLS/nr_phy_scope.h b/openair1/PHY/TOOLS/nr_phy_scope.h index aaee08a554..429537141a 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.h +++ b/openair1/PHY/TOOLS/nr_phy_scope.h @@ -26,71 +26,22 @@ #include #include #include -#include #include "common/ran_context.h" #include -#include #include "PHY/defs_gNB.h" //#include "PHY/defs_nrUE.h" //#include "PHY/impl_defs_top.h" #include "PHY/defs_nr_UE.h" -/* Forms and Objects */ -typedef struct { - FL_FORM * phy_scope_gnb; - FL_OBJECT * rxsig_t; - FL_OBJECT * chest_f; - FL_OBJECT * chest_t; - FL_OBJECT * pusch_comp; - FL_OBJECT * pucch_comp; - FL_OBJECT * pucch_comp1; - FL_OBJECT * pusch_llr; - FL_OBJECT * pusch_tput; - FL_OBJECT * button_0; -} FD_phy_scope_gnb; - -typedef struct { - FL_FORM * phy_scope_nrue; - FL_OBJECT * rxsig_t; - FL_OBJECT * chest_f; - FL_OBJECT * chest_t; - FL_OBJECT * pbch_comp; - FL_OBJECT * pbch_llr; - FL_OBJECT * pdcch_comp; - FL_OBJECT * pdcch_llr; - FL_OBJECT * pdsch_comp; - FL_OBJECT * pdsch_llr; - FL_OBJECT * pdsch_comp1; - FL_OBJECT * pdsch_llr1; - FL_OBJECT * pdsch_tput; - FL_OBJECT * button_0; -} FD_phy_scope_nrue; - typedef struct { int *argc; char **argv; + RU_t *ru; + PHY_VARS_gNB *gNB; } scopeParms_t; -extern unsigned char scope_enb_num_ue; -FD_phy_scope_gnb * create_phy_scope_gnb( void ); -FD_phy_scope_nrue * create_phy_scope_nrue( void ); - - -void phy_scope_gNB(FD_phy_scope_gnb *form, - PHY_VARS_gNB *phy_vars_gnb, - RU_t *phy_vars_ru, - int UE_id); - - -void phy_scope_nrUE(FD_phy_scope_nrue *form, - PHY_VARS_NR_UE *phy_vars_ue, - int eNB_id, - int UE_id, - uint8_t subframe); - - -void startScope(scopeParms_t * p); - +void gNBinitScope(scopeParms_t *p); +void nrUEinitScope(PHY_VARS_NR_UE *ue); extern RAN_CONTEXT_t RC; #endif diff --git a/openair1/PHY/TOOLS/oai_dfts.c b/openair1/PHY/TOOLS/oai_dfts.c index bd516cd1e0..25244eeff5 100644 --- a/openair1/PHY/TOOLS/oai_dfts.c +++ b/openair1/PHY/TOOLS/oai_dfts.c @@ -5353,6 +5353,607 @@ void idft8192(int16_t *x,int16_t *y,unsigned char scale) #endif +int16_t tw16384[3*2*4096]; + +#ifndef __AVX2__ +void dft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd_q15_t xtmp[4096],ytmp[4096],*tw16384_128p=(simd_q15_t *)tw16384,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<4096; i+=4,j++) { + transpose16_ooff(x128+i,xtmp+j,1024); + } + + + dft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + dft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + dft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + dft4096((int16_t*)(xtmp+3072),(int16_t*)(ytmp+3072),1); + + for (i=0; i<1024; i++) { + bfly4(ytmpp,ytmpp+1024,ytmpp+2048,ytmpp+3072, + y128p,y128p+1024,y128p+2048,y128p+3072, + tw16384_128p,tw16384_128p+1024,tw16384_128p+2048); + tw16384_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<256; i++) { + y128[0] = shiftright_int16(y128[0],1); + y128[1] = shiftright_int16(y128[1],1); + y128[2] = shiftright_int16(y128[2],1); + y128[3] = shiftright_int16(y128[3],1); + y128[4] = shiftright_int16(y128[4],1); + y128[5] = shiftright_int16(y128[5],1); + y128[6] = shiftright_int16(y128[6],1); + y128[7] = shiftright_int16(y128[7],1); + y128[8] = shiftright_int16(y128[8],1); + y128[9] = shiftright_int16(y128[9],1); + y128[10] = shiftright_int16(y128[10],1); + y128[11] = shiftright_int16(y128[11],1); + y128[12] = shiftright_int16(y128[12],1); + y128[13] = shiftright_int16(y128[13],1); + y128[14] = shiftright_int16(y128[14],1); + y128[15] = shiftright_int16(y128[15],1); + + y128+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + + + +void idft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd_q15_t xtmp[4096],ytmp[4096],*tw16384_128p=(simd_q15_t *)tw16384,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<4096; i+=4,j++) { + transpose16_ooff(x128+i,xtmp+j,1024); + } + + + idft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + idft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + idft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + idft4096((int16_t*)(xtmp+3072),(int16_t*)(ytmp+3072),1); + + for (i=0; i<1024; i++) { + ibfly4(ytmpp,ytmpp+1024,ytmpp+2048,ytmpp+3072, + y128p,y128p+1024,y128p+2048,y128p+3072, + tw16384_128p,tw16384_128p+1024,tw16384_128p+2048); + tw16384_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<256; i++) { + y128[0] = shiftright_int16(y128[0],scale); + y128[1] = shiftright_int16(y128[1],scale); + y128[2] = shiftright_int16(y128[2],scale); + y128[3] = shiftright_int16(y128[3],scale); + y128[4] = shiftright_int16(y128[4],scale); + y128[5] = shiftright_int16(y128[5],scale); + y128[6] = shiftright_int16(y128[6],scale); + y128[7] = shiftright_int16(y128[7],scale); + y128[8] = shiftright_int16(y128[8],scale); + y128[9] = shiftright_int16(y128[9],scale); + y128[10] = shiftright_int16(y128[10],scale); + y128[11] = shiftright_int16(y128[11],scale); + y128[12] = shiftright_int16(y128[12],scale); + y128[13] = shiftright_int16(y128[13],scale); + y128[14] = shiftright_int16(y128[14],scale); + y128[15] = shiftright_int16(y128[15],scale); + + y128+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + +#else //__AVX2__ +void dft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[2048],ytmp[2048],*tw16384_256p=(simd256_q15_t *)tw16384,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + simd256_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<2048; i+=4,j++) { + transpose16_ooff_simd256(x256+i,xtmp+j,512); + } + + + dft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + dft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); + dft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + dft4096((int16_t*)(xtmp+1536),(int16_t*)(ytmp+1536),1); + + for (i=0; i<512; i++) { + bfly4_256(ytmpp,ytmpp+512,ytmpp+1024,ytmpp+1536, + y256p,y256p+512,y256p+1024,y256p+1536, + tw16384_256p,tw16384_256p+512,tw16384_256p+1024); + tw16384_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<128; i++) { + y256[0] = shiftright_int16_simd256(y256[0],1); + y256[1] = shiftright_int16_simd256(y256[1],1); + y256[2] = shiftright_int16_simd256(y256[2],1); + y256[3] = shiftright_int16_simd256(y256[3],1); + y256[4] = shiftright_int16_simd256(y256[4],1); + y256[5] = shiftright_int16_simd256(y256[5],1); + y256[6] = shiftright_int16_simd256(y256[6],1); + y256[7] = shiftright_int16_simd256(y256[7],1); + y256[8] = shiftright_int16_simd256(y256[8],1); + y256[9] = shiftright_int16_simd256(y256[9],1); + y256[10] = shiftright_int16_simd256(y256[10],1); + y256[11] = shiftright_int16_simd256(y256[11],1); + y256[12] = shiftright_int16_simd256(y256[12],1); + y256[13] = shiftright_int16_simd256(y256[13],1); + y256[14] = shiftright_int16_simd256(y256[14],1); + y256[15] = shiftright_int16_simd256(y256[15],1); + + y256+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + +void idft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[2048],ytmp[2048],*tw16384_256p=(simd256_q15_t *)tw16384,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + simd256_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<2048; i+=4,j++) { + transpose16_ooff_simd256(x256+i,xtmp+j,512); + } + + + idft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + idft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); + idft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + idft4096((int16_t*)(xtmp+1536),(int16_t*)(ytmp+1536),1); + + for (i=0; i<512; i++) { + ibfly4_256(ytmpp,ytmpp+512,ytmpp+1024,ytmpp+1536, + y256p,y256p+512,y256p+1024,y256p+1536, + tw16384_256p,tw16384_256p+512,tw16384_256p+1024); + tw16384_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<128; i++) { + y256[0] = shiftright_int16_simd256(y256[0],1); + y256[1] = shiftright_int16_simd256(y256[1],1); + y256[2] = shiftright_int16_simd256(y256[2],1); + y256[3] = shiftright_int16_simd256(y256[3],1); + y256[4] = shiftright_int16_simd256(y256[4],1); + y256[5] = shiftright_int16_simd256(y256[5],1); + y256[6] = shiftright_int16_simd256(y256[6],1); + y256[7] = shiftright_int16_simd256(y256[7],1); + y256[8] = shiftright_int16_simd256(y256[8],1); + y256[9] = shiftright_int16_simd256(y256[9],1); + y256[10] = shiftright_int16_simd256(y256[10],1); + y256[11] = shiftright_int16_simd256(y256[11],1); + y256[12] = shiftright_int16_simd256(y256[12],1); + y256[13] = shiftright_int16_simd256(y256[13],1); + y256[14] = shiftright_int16_simd256(y256[14],1); + y256[15] = shiftright_int16_simd256(y256[15],1); + + y256+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + +#endif //__AVX2__ + +int16_t tw32768[2*16384] __attribute__((aligned(32))); + +#ifndef __AVX2__ +void dft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simdshort_q15_t xtmp[16384],*xtmpp,*x64 = (simdshort_q15_t *)x; + simd_q15_t ytmp[8192],*tw32768_128p=(simd_q15_t *)tw32768,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i; + simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<256; i++) { + transpose4_ooff(x64 ,xtmpp,8192); + transpose4_ooff(x64+2,xtmpp+1,8192); + transpose4_ooff(x64+4,xtmpp+2,8192); + transpose4_ooff(x64+6,xtmpp+3,8192); + transpose4_ooff(x64+8,xtmpp+4,8192); + transpose4_ooff(x64+10,xtmpp+5,8192); + transpose4_ooff(x64+12,xtmpp+6,8192); + transpose4_ooff(x64+14,xtmpp+7,8192); + transpose4_ooff(x64+16,xtmpp+8,8192); + transpose4_ooff(x64+18,xtmpp+9,8192); + transpose4_ooff(x64+20,xtmpp+10,8192); + transpose4_ooff(x64+22,xtmpp+11,8192); + transpose4_ooff(x64+24,xtmpp+12,8192); + transpose4_ooff(x64+26,xtmpp+13,8192); + transpose4_ooff(x64+28,xtmpp+14,8192); + transpose4_ooff(x64+30,xtmpp+15,8192); + transpose4_ooff(x64+32,xtmpp+16,8192); + transpose4_ooff(x64+34,xtmpp+17,8192); + transpose4_ooff(x64+36,xtmpp+18,8192); + transpose4_ooff(x64+38,xtmpp+19,8192); + transpose4_ooff(x64+40,xtmpp+20,8192); + transpose4_ooff(x64+42,xtmpp+21,8192); + transpose4_ooff(x64+44,xtmpp+22,8192); + transpose4_ooff(x64+46,xtmpp+23,8192); + transpose4_ooff(x64+48,xtmpp+24,8192); + transpose4_ooff(x64+50,xtmpp+25,8192); + transpose4_ooff(x64+52,xtmpp+26,8192); + transpose4_ooff(x64+54,xtmpp+27,8192); + transpose4_ooff(x64+56,xtmpp+28,8192); + transpose4_ooff(x64+58,xtmpp+29,8192); + transpose4_ooff(x64+60,xtmpp+30,8192); + transpose4_ooff(x64+62,xtmpp+31,8192); + x64+=64; + xtmpp+=32; + } + + dft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + dft16384((int16_t*)(xtmp+8192),(int16_t*)(ytmp+4096),1); + + + for (i=0; i<4096; i++) { + bfly2(ytmpp,ytmpp+4096, + y128p,y128p+4096, + tw32768_128p); + tw32768_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + y128p = y128; + + for (i=0; i<512; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); + y128p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + +void idft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simdshort_q15_t xtmp[16384],*xtmpp,*x64 = (simdshort_q15_t *)x; + simd_q15_t ytmp[8192],*tw32768_128p=(simd_q15_t *)tw32768,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i; + simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<256; i++) { + transpose4_ooff(x64 ,xtmpp,8192); + transpose4_ooff(x64+2,xtmpp+1,8192); + transpose4_ooff(x64+4,xtmpp+2,8192); + transpose4_ooff(x64+6,xtmpp+3,8192); + transpose4_ooff(x64+8,xtmpp+4,8192); + transpose4_ooff(x64+10,xtmpp+5,8192); + transpose4_ooff(x64+12,xtmpp+6,8192); + transpose4_ooff(x64+14,xtmpp+7,8192); + transpose4_ooff(x64+16,xtmpp+8,8192); + transpose4_ooff(x64+18,xtmpp+9,8192); + transpose4_ooff(x64+20,xtmpp+10,8192); + transpose4_ooff(x64+22,xtmpp+11,8192); + transpose4_ooff(x64+24,xtmpp+12,8192); + transpose4_ooff(x64+26,xtmpp+13,8192); + transpose4_ooff(x64+28,xtmpp+14,8192); + transpose4_ooff(x64+30,xtmpp+15,8192); + transpose4_ooff(x64+32,xtmpp+16,8192); + transpose4_ooff(x64+34,xtmpp+17,8192); + transpose4_ooff(x64+36,xtmpp+18,8192); + transpose4_ooff(x64+38,xtmpp+19,8192); + transpose4_ooff(x64+40,xtmpp+20,8192); + transpose4_ooff(x64+42,xtmpp+21,8192); + transpose4_ooff(x64+44,xtmpp+22,8192); + transpose4_ooff(x64+46,xtmpp+23,8192); + transpose4_ooff(x64+48,xtmpp+24,8192); + transpose4_ooff(x64+50,xtmpp+25,8192); + transpose4_ooff(x64+52,xtmpp+26,8192); + transpose4_ooff(x64+54,xtmpp+27,8192); + transpose4_ooff(x64+56,xtmpp+28,8192); + transpose4_ooff(x64+58,xtmpp+29,8192); + transpose4_ooff(x64+60,xtmpp+30,8192); + transpose4_ooff(x64+62,xtmpp+31,8192); + x64+=64; + xtmpp+=32; + } + + idft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + idft16384((int16_t*)(xtmp+8192),(int16_t*)(ytmp+4096),1); + + + for (i=0; i<4096; i++) { + ibfly2(ytmpp,ytmpp+4096, + y128p,y128p+4096, + tw32768_128p); + tw32768_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + y128p = y128; + + for (i=0; i<512; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); + y128p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + +#else // __AVX2__ +void dft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[4096],*xtmpp,*x256 = (simd256_q15_t *)x; + simd256_q15_t ytmp[4096],*tw32768_256p=(simd256_q15_t *)tw32768,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + + simd256_q15_t *ytmpp = &ytmp[0]; + int i; + simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<256; i++) { + transpose4_ooff_simd256(x256 ,xtmpp,2048); + transpose4_ooff_simd256(x256+2,xtmpp+1,2048); + transpose4_ooff_simd256(x256+4,xtmpp+2,2048); + transpose4_ooff_simd256(x256+6,xtmpp+3,2048); + transpose4_ooff_simd256(x256+8,xtmpp+4,2048); + transpose4_ooff_simd256(x256+10,xtmpp+5,2048); + transpose4_ooff_simd256(x256+12,xtmpp+6,2048); + transpose4_ooff_simd256(x256+14,xtmpp+7,2048); + transpose4_ooff_simd256(x256+16,xtmpp+8,2048); + transpose4_ooff_simd256(x256+18,xtmpp+9,2048); + transpose4_ooff_simd256(x256+20,xtmpp+10,2048); + transpose4_ooff_simd256(x256+22,xtmpp+11,2048); + transpose4_ooff_simd256(x256+24,xtmpp+12,2048); + transpose4_ooff_simd256(x256+26,xtmpp+13,2048); + transpose4_ooff_simd256(x256+28,xtmpp+14,2048); + transpose4_ooff_simd256(x256+30,xtmpp+15,2048); + transpose4_ooff_simd256(x256+32,xtmpp+16,2048); + transpose4_ooff_simd256(x256+34,xtmpp+17,2048); + transpose4_ooff_simd256(x256+36,xtmpp+18,2048); + transpose4_ooff_simd256(x256+38,xtmpp+19,2048); + transpose4_ooff_simd256(x256+40,xtmpp+20,2048); + transpose4_ooff_simd256(x256+42,xtmpp+21,2048); + transpose4_ooff_simd256(x256+44,xtmpp+22,2048); + transpose4_ooff_simd256(x256+46,xtmpp+23,2048); + transpose4_ooff_simd256(x256+48,xtmpp+24,2048); + transpose4_ooff_simd256(x256+50,xtmpp+25,2048); + transpose4_ooff_simd256(x256+52,xtmpp+26,2048); + transpose4_ooff_simd256(x256+54,xtmpp+27,2048); + transpose4_ooff_simd256(x256+56,xtmpp+28,2048); + transpose4_ooff_simd256(x256+58,xtmpp+29,2048); + transpose4_ooff_simd256(x256+60,xtmpp+30,2048); + transpose4_ooff_simd256(x256+62,xtmpp+31,2048); + x256+=64; + xtmpp+=32; + } + + dft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + dft16384((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + + + for (i=0; i<2048; i++) { + bfly2_256(ytmpp,ytmpp+2048, + y256p,y256p+2048, + tw32768_256p); + tw32768_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + y256p = y256; + + for (i=0; i<64; i++) { + y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); + y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); + y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); + y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); + y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); + y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); + y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); + y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); + y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); + y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); + y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); + y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); + y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); + y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); + y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); + y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); + y256p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + +void idft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[4096],*xtmpp,*x256 = (simd256_q15_t *)x; + simd256_q15_t ytmp[4096],*tw32768_256p=(simd256_q15_t *)tw32768,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + simd256_q15_t *ytmpp = &ytmp[0]; + int i; + simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<64; i++) { + transpose4_ooff_simd256(x256 ,xtmpp,2048); + transpose4_ooff_simd256(x256+2,xtmpp+1,2048); + transpose4_ooff_simd256(x256+4,xtmpp+2,2048); + transpose4_ooff_simd256(x256+6,xtmpp+3,2048); + transpose4_ooff_simd256(x256+8,xtmpp+4,2048); + transpose4_ooff_simd256(x256+10,xtmpp+5,2048); + transpose4_ooff_simd256(x256+12,xtmpp+6,2048); + transpose4_ooff_simd256(x256+14,xtmpp+7,2048); + transpose4_ooff_simd256(x256+16,xtmpp+8,2048); + transpose4_ooff_simd256(x256+18,xtmpp+9,2048); + transpose4_ooff_simd256(x256+20,xtmpp+10,2048); + transpose4_ooff_simd256(x256+22,xtmpp+11,2048); + transpose4_ooff_simd256(x256+24,xtmpp+12,2048); + transpose4_ooff_simd256(x256+26,xtmpp+13,2048); + transpose4_ooff_simd256(x256+28,xtmpp+14,2048); + transpose4_ooff_simd256(x256+30,xtmpp+15,2048); + transpose4_ooff_simd256(x256+32,xtmpp+16,2048); + transpose4_ooff_simd256(x256+34,xtmpp+17,2048); + transpose4_ooff_simd256(x256+36,xtmpp+18,2048); + transpose4_ooff_simd256(x256+38,xtmpp+19,2048); + transpose4_ooff_simd256(x256+40,xtmpp+20,2048); + transpose4_ooff_simd256(x256+42,xtmpp+21,2048); + transpose4_ooff_simd256(x256+44,xtmpp+22,2048); + transpose4_ooff_simd256(x256+46,xtmpp+23,2048); + transpose4_ooff_simd256(x256+48,xtmpp+24,2048); + transpose4_ooff_simd256(x256+50,xtmpp+25,2048); + transpose4_ooff_simd256(x256+52,xtmpp+26,2048); + transpose4_ooff_simd256(x256+54,xtmpp+27,2048); + transpose4_ooff_simd256(x256+56,xtmpp+28,2048); + transpose4_ooff_simd256(x256+58,xtmpp+29,2048); + transpose4_ooff_simd256(x256+60,xtmpp+30,2048); + transpose4_ooff_simd256(x256+62,xtmpp+31,2048); + x256+=64; + xtmpp+=32; + } + + idft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + idft16384((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + + + for (i=0; i<2048; i++) { + ibfly2_256(ytmpp,ytmpp+2048, + y256p,y256p+2048, + tw32768_256p); + tw32768_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + y256p = y256; + + for (i=0; i<256; i++) { + y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); + y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); + y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); + y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); + y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); + y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); + y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); + y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); + y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); + y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); + y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); + y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); + y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); + y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); + y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); + y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); + y256p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + + +#endif + + int16_t twa1536[1024],twb1536[1024]; // 512 x 3 @@ -6061,28 +6662,214 @@ void idft24576(int16_t *input, int16_t *output,unsigned char scale) } int16_t twa36864[24576] __attribute__((aligned(32))); -int16_t twb36884[24576] __attribute__((aligned(32))); +int16_t twb36864[24576] __attribute__((aligned(32))); + // 12288 x 3 void dft36864(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][12288] __attribute__((aligned(32))); + uint32_t tmpo[3][12288] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<12288; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + dft12288((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + dft12288((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + dft12288((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + if (LOG_DUMPFLAG(DEBUG_DFT)) { + LOG_M("dft36864out0.m","o0",tmpo[0],12288,1,1); + LOG_M("dft36864out1.m","o1",tmpo[1],12288,1,1); + LOG_M("dft36864out2.m","o2",tmpo[2],12288,1,1); + } + + for (i=0,i2=0; i<24576; i+=8,i2+=4) { + bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+24576+i),(simd_q15_t*)(output+49152+i), + (simd_q15_t*)(twa36864+i),(simd_q15_t*)(twb36864+i)); + } + + if (scale==1) { + for (i=0; i<576; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); + if (LOG_DUMPFLAG(DEBUG_DFT)) { + LOG_M("out.m","out",output,36864,1,1); + } } + void idft36864(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][12288] __attribute__((aligned(32))); + uint32_t tmpo[3][12288] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<12288; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + idft12288((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + idft12288((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + idft12288((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<24576; i+=8,i2+=4) { + ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+24576+i),(simd_q15_t*)(output+49152+i), + (simd_q15_t*)(twa36864+i),(simd_q15_t*)(twb36864+i)); + } + if (scale==1) { + for (i=0; i<576; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); } int16_t twa49152[32768] __attribute__((aligned(32))); int16_t twb49152[32768] __attribute__((aligned(32))); + // 16384 x 3 void dft49152(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][16384] __attribute__((aligned(32))); + uint32_t tmpo[3][16384] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<16384; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + dft16384((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + dft16384((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + dft16384((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<32768; i+=8,i2+=4) { + bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+32768+i),(simd_q15_t*)(output+65536+i), + (simd_q15_t*)(twa49152+i),(simd_q15_t*)(twb49152+i)); + } + if (scale==1) { + for (i=0; i<768; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); + } void idft49152(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][16384] __attribute__((aligned(32))); + uint32_t tmpo[3][16384] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<16384; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + idft16384((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + idft16384((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + idft16384((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<32768; i+=8,i2+=4) { + ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+32768+i),(simd_q15_t*)(output+65536+i), + (simd_q15_t*)(twa49152+i),(simd_q15_t*)(twb49152+i)); + } + if (scale==1) { + for (i=0; i<768; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); } int16_t twa73728[49152] __attribute__((aligned(32))); @@ -6099,17 +6886,104 @@ void idft73728(int16_t *input, int16_t *output,uint8_t scale) { } -int16_t twa98304[49152] __attribute__((aligned(32))); -int16_t twb98304[49152] __attribute__((aligned(32))); +int16_t twa98304[65536] __attribute__((aligned(32))); +int16_t twb98304[65536] __attribute__((aligned(32))); // 32768 x 3 void dft98304(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][32768] __attribute__((aligned(32))); + uint32_t tmpo[3][32768] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<32768; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + dft32768((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + dft32768((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + dft32768((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<65536; i+=8,i2+=4) { + bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+65536+i),(simd_q15_t*)(output+131072+i), + (simd_q15_t*)(twa98304+i),(simd_q15_t*)(twb98304+i)); + } + if (scale==1) { + for (i=0; i<1536; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); + } void idft98304(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][32768] __attribute__((aligned(32))); + uint32_t tmpo[3][32768] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<32768; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + idft32768((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + idft32768((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + idft32768((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<65536; i+=8,i2+=4) { + ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+65536+i),(simd_q15_t*)(output+131072+i), + (simd_q15_t*)(twa98304+i),(simd_q15_t*)(twb98304+i)); + } + if (scale==1) { + for (i=0; i<1536; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); } @@ -8724,6 +9598,8 @@ int dfts_autoinit(void) init_rad2(2048,tw2048); init_rad4(4096,tw4096); init_rad2(8192,tw8192); + init_rad4(16384,tw16384); + init_rad2(32768,tw32768); init_rad3(1536,twa1536,twb1536); init_rad3(3072,twa3072,twb3072); @@ -8731,6 +9607,10 @@ int dfts_autoinit(void) init_rad3(12288,twa12288,twb12288); init_rad3(18432,twa18432,twb18432); init_rad3(24576,twa24576,twb24576); + init_rad3(36864,twa36864,twb36864); + init_rad3(49152,twa49152,twb49152); + init_rad3(98304,twa98304,twb98304); + init_rad2_rep(24,tw24); init_rad3_rep(36,twa36,twb36); @@ -8770,6 +9650,7 @@ int dfts_autoinit(void) +#ifndef MR_MAIN void dft(uint8_t sizeidx, int16_t *sigF,int16_t *sig,unsigned char scale_flag){ AssertFatal((sizeidx>=0 && sizeidx<(int)DFT_SIZE_IDXTABLESIZE),"Invalid dft size index %i\n",sizeidx); @@ -8780,6 +9661,7 @@ void idft(uint8_t sizeidx, int16_t *sigF,int16_t *sig,unsigned char scale_flag){ AssertFatal((sizeidx>=0 && sizeidx<(int)IDFT_SIZE_IDXTABLESIZE),"Invalid idft size index %i\n",sizeidx); idft_ftab[sizeidx](sigF,sig,scale_flag); }; +#endif /*---------------------------------------------------------------------------------------*/ @@ -8950,9 +9832,9 @@ int main(int argc, char**argv) time_stats_t ts; #ifdef __AVX2__ - simd256_q15_t x[4096],x2[4096],y[4096],tw0,tw1,tw2,tw3; + simd256_q15_t x[16384],x2[16384],y[16384],tw0,tw1,tw2,tw3; #else - simd_q15_t x[8192],y[8192],tw0,tw1,tw2,tw3; + simd_q15_t x[32768],y[32768],tw0,tw1,tw2,tw3; #endif int i; simd_q15_t *x128=(simd_q15_t*)x,*y128=(simd_q15_t*)y; @@ -9514,10 +10396,34 @@ int main(int argc, char**argv) stop_meas(&ts); } - printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + printf("\n\n8192-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); LOG_M("y8192.m","y8192",y,8192,1,1); LOG_M("x8192.m","x8192",x,8192,1,1); + memset((void*)x,0,16384*sizeof(int32_t)); + for (i=2;i<9602;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + for (i=2*(16384-4800);i<32768;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + reset_meas(&ts); + for (i=0; i<10000; i++) { + start_meas(&ts); + dft16384((int16_t *)x,(int16_t *)y,1); + stop_meas(&ts); + } + + printf("\n\n16384-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + LOG_M("y16384.m","y16384",y,16384,1,1); + LOG_M("x16384.m","x16384",x,16384,1,1); + memset((void*)x,0,1536*sizeof(int32_t)); for (i=2;i<1202;i++) { if ((taus() & 1)==0) @@ -9666,6 +10572,56 @@ int main(int argc, char**argv) LOG_M("y24576.m","y24576",y,24576,1,1); LOG_M("x24576.m","x24576",x,24576,1,1); + + memset((void*)x,0,2*18432*sizeof(int32_t)); + for (i=2;i<(2*14402);i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + for (i=2*(36864-14400);i<(36864*2);i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + reset_meas(&ts); + for (i=0; i<10000; i++) { + start_meas(&ts); + dft36864((int16_t *)x,(int16_t *)y,1); + stop_meas(&ts); + } + + printf("\n\n36864-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + LOG_M("y36864.m","y36864",y,36864,1,1); + LOG_M("x36864.m","x36864",x,36864,1,1); + + + memset((void*)x,0,49152*sizeof(int32_t)); + for (i=2;i<28402;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + for (i=2*(49152-14400);i<98304;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + reset_meas(&ts); + for (i=0; i<10000; i++) { + start_meas(&ts); + idft49152((int16_t *)x,(int16_t *)y,1); + stop_meas(&ts); + } + + printf("\n\n49152-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + LOG_M("y49152.m","y49152",y,49152,1,1); + LOG_M("x49152.m","x49152",x,49152,1,1); + /* int dftsizes[33]={24,36,48,60,72,96,108,120,144,180,192,216,240,288,300,324,360,384,432,480,540,576,600,648,720,768,864,900,960,972,1080,1152,1200}; void (*dft)(int16_t *x,int16_t *y,uint8_t scale)[33] = {dft24,dft36,dft48,dft60,dft72,dft96,dft108,dft120,dft144,dft180,dft192,dft216,dft240,dft288,dft300,dft324,dft360,dft384,dft432,dft480,dft540,dft576,dft600,dft648,dft720,dft768,dft864,dft900,dft960,dft972,dft1080,dft1152,dft1200}; for (int n=0;n<33;n++) { @@ -9698,7 +10654,7 @@ int main(int argc, char**argv) LOG_M(ystr,ystr2,y,dftsizes[n]*4,1,1); LOG_M(xstr,xstr2,x,dftsizes[n]*4,1,1); } - + */ return(0); } diff --git a/openair1/PHY/TOOLS/tools_defs.h b/openair1/PHY/TOOLS/tools_defs.h index 61ea785db8..9c9b8aa821 100644 --- a/openair1/PHY/TOOLS/tools_defs.h +++ b/openair1/PHY/TOOLS/tools_defs.h @@ -183,10 +183,6 @@ This function performs optimized fixed-point radix-2 FFT/IFFT. - - - - #ifdef OAIDFTS_MAIN typedef void(*adftfunc_t)(int16_t *sigF,int16_t *sig,unsigned char scale_flag); typedef void(*aidftfunc_t)(int16_t *sigF,int16_t *sig,unsigned char scale_flag); diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h index ce808eddf9..b8083b5ecf 100644 --- a/openair1/PHY/defs_RU.h +++ b/openair1/PHY/defs_RU.h @@ -38,8 +38,7 @@ #include "openairinterface5g_limits.h" #include "PHY/TOOLS/time_meas.h" #include "defs_common.h" -#include - +#include "nfapi_nr_interface_scf.h" #define MAX_BANDS_PER_RRU 4 #define MAX_RRU_CONFIG_SIZE 1024 @@ -186,6 +185,16 @@ typedef struct RU_feptx_t_s{ int index; }RU_feptx_t; +typedef struct { + int frame; + int slot; + int fmt; + int numRA; + int prachStartSymbol; +} RU_PRACH_list_t; + +#define NUMBER_OF_NR_RU_PRACH_MAX 8 + typedef struct RU_proc_t_s { /// Pointer to associated RU descriptor struct RU_t_s *ru; @@ -477,6 +486,8 @@ typedef struct RU_t_s { int att_tx; /// flag to indicate precoding operation in RU int do_precoding; + /// FAPI confiuration + nfapi_nr_config_request_scf_t config; /// Frame parameters struct LTE_DL_FRAME_PARMS *frame_parms; struct NR_DL_FRAME_PARMS *nr_frame_parms; @@ -579,6 +590,10 @@ typedef struct RU_t_s { int32_t *bw_list[NUMBER_OF_eNB_MAX+1]; /// beamforming weight vectors int32_t **beam_weights[NUMBER_OF_eNB_MAX+1][15]; + /// prach commands + RU_PRACH_list_t prach_list[NUMBER_OF_NR_RU_PRACH_MAX]; + /// mutex for prach_list access + pthread_mutex_t prach_list_mutex; /// received frequency-domain signal for PRACH (IF4p5 RRU) int16_t **prach_rxsigF; /// received frequency-domain signal for PRACH BR (IF4p5 RRU) diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index aa794da818..e2cdebff3a 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -43,6 +43,8 @@ #include "PHY/CODING/nrLDPC_extern.h" #include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" +#include "nfapi_nr_interface_scf.h" + #define MAX_NUM_RU_PER_gNB MAX_NUM_RU_PER_eNB #define MAX_PUCCH0_NID 8 @@ -52,6 +54,7 @@ typedef struct { int lut[MAX_PUCCH0_NID][160][14]; } NR_gNB_PUCCH0_LUT_t; + typedef struct { uint32_t pbch_a; uint32_t pbch_a_interleaved; @@ -155,6 +158,14 @@ typedef struct { int16_t sqrt_rho_b; } NR_gNB_DLSCH_t; +typedef struct { + int frame; + int slot; + nfapi_nr_prach_pdu_t pdu; +} gNB_PRACH_list_t; + +#define NUMBER_OF_NR_PRACH_MAX 8 + typedef struct { /// \brief ?. /// first index: ? [0..1023] (hard coded) @@ -165,6 +176,7 @@ typedef struct { int16_t **rxsigF; /// \brief local buffer to compute prach_ifft int32_t *prach_ifft; + gNB_PRACH_list_t list[NUMBER_OF_NR_PRACH_MAX]; } NR_gNB_PRACH; typedef struct { @@ -172,8 +184,8 @@ typedef struct { nfapi_nr_pusch_pdu_t ulsch_pdu; /// Frame where current HARQ round was sent uint32_t frame; - /// Subframe where current HARQ round was sent - uint32_t subframe; + /// Slot where current HARQ round was sent + uint32_t slot; /// Index of current HARQ round for this DLSCH uint8_t round; /// Last TPC command @@ -328,6 +340,15 @@ typedef struct { uint16_t cba_rnti[NUM_MAX_CBA_GROUP]; } NR_gNB_ULSCH_t; +typedef struct { + uint8_t active; + /// Frame where current PUCCH pdu was sent + uint32_t frame; + /// Slot where current PUCCH pdu was sent + uint32_t slot; + /// ULSCH PDU + nfapi_nr_pucch_pdu_t pucch_pdu; +} NR_gNB_PUCCH_t; typedef struct { /// \brief Pointers (dynamic) to the received data in the time domain. @@ -607,9 +628,9 @@ typedef struct { #define MAX_NUM_NR_RX_RACH_PDUS 4 #define MAX_NUM_NR_RX_PRACH_PREAMBLES 4 -#define MAX_UL_PDUS_PER_SLOT 100 -#define MAX_NUM_NR_SRS_PDUS 100 -#define MAX_NUM_NR_UCI_PDUS 100 +#define MAX_UL_PDUS_PER_SLOT 8 +#define MAX_NUM_NR_SRS_PDUS 8 +#define MAX_NUM_NR_UCI_PDUS 8 /// Top-level PHY Data Structure for gNB typedef struct PHY_VARS_gNB_s { @@ -663,10 +684,13 @@ typedef struct PHY_VARS_gNB_s { NR_gNB_COMMON common_vars; NR_gNB_PRACH prach_vars; NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX]; + NR_gNB_PUCCH_t *pucch[NUMBER_OF_NR_PUCCH_MAX]; NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords] NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p; NR_gNB_DLSCH_t *dlsch_PCH; + t_nrPolar_params *uci_polarParams; + uint8_t pbch_configured; char gNB_generate_rar; diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index b2d6a75265..9bdf892ceb 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -782,6 +782,8 @@ typedef struct { int16_t amp; int16_t *prachF; int16_t *prach; + fapi_nr_ul_config_prach_pdu prach_pdu; + uint8_t prach_Config_enabled; } NR_UE_PRACH; // structure used for multiple SSB detection @@ -882,8 +884,6 @@ typedef struct { fapi_nr_config_request_t nrUE_config; - uint16_t frame_gap; - // the following structures are not part of PHY_vars_UE anymore as it is not thread safe. They are now on the stack of the functions that actually need them //nr_downlink_indication_t dl_indication; @@ -930,7 +930,7 @@ typedef struct { uint8_t pucch_sel[10]; uint8_t pucch_payload[22]; - UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_eNB_MAX]; + UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX]; /// cell-specific reference symbols uint32_t lte_gold_table[7][20][2][14]; @@ -965,12 +965,13 @@ typedef struct { char ulsch_no_allocation_counter[NUMBER_OF_CONNECTED_eNB_MAX]; + unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_gNB_MAX]; + uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_gNB_MAX]; + unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_gNB_MAX]; + uint8_t Msg3_startSymbol[NUMBER_OF_CONNECTED_gNB_MAX]; + uint8_t Msg3_Length[NUMBER_OF_CONNECTED_gNB_MAX]; - - unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_eNB_MAX]; - uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_eNB_MAX]; - unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_eNB_MAX]; - PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_eNB_MAX]; + NR_PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_gNB_MAX]; int turbo_iterations, turbo_cntl_iterations; /// \brief ?. /// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded) @@ -1005,8 +1006,6 @@ typedef struct { int dlsch_mtch_trials[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX]; int current_dlsch_cqi[NUMBER_OF_CONNECTED_eNB_MAX]; unsigned char first_run_timing_advance[NUMBER_OF_CONNECTED_eNB_MAX]; - uint8_t generate_prach; - uint8_t generate_nr_prach; uint8_t prach_cnt; uint8_t prach_PreambleIndex; // uint8_t prach_timer; diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index ccc79b7d47..584962c55c 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -198,30 +198,34 @@ typedef struct { nr_reg_t reg_list[NR_NB_REG_PER_CCE]; } nr_cce_t; - -/// PRACH-ConfigInfo from 38.331 RRC spec typedef struct { - /// Parameter: prach-ConfigurationIndex, see TS 38.211 (6.3.3.2). - uint8_t prach_ConfigIndex; - /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set. - uint8_t highSpeedFlag; - /// Restricted Set Config (type A=0 , type B=1) TS 38.211 (6.3.3.1) - uint8_t restrictedSetConfig; - /// 38.211 (NCS 38.211 6.3.3.1). - uint8_t zeroCorrelationZoneConfig; - /// see TS 38.211 (6.3.3.2). - uint8_t msg1_frequencystart; -} NR_PRACH_CONFIG_INFO; - -/// PRACH-ConfigSIB or PRACH-Config -typedef struct { - /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2). - uint16_t rootSequenceIndex; - /// prach_Config_enabled=1 means enabled.} - uint8_t prach_Config_enabled; - /// PRACH Configuration Information - NR_PRACH_CONFIG_INFO prach_ConfigInfo; -} NR_PRACH_CONFIG_COMMON; + /// PRACH format retrieved from prach_ConfigIndex + uint16_t prach_format; + /// Preamble index for PRACH (0-63) + uint8_t ra_PreambleIndex; + /// RACH MaskIndex + uint8_t ra_RACH_MaskIndex; + /// Target received power at gNB. Baseline is range -202..-60 dBm. Depends on delta preamble, power ramping counter and step. + int ra_PREAMBLE_RECEIVED_TARGET_POWER; + /// PRACH index for TDD (0 ... 6) depending on TDD configuration and prachConfigIndex + uint8_t ra_TDD_map_index; + /// RA Preamble Power Ramping Step in dB + uint32_t RA_PREAMBLE_POWER_RAMPING_STEP; + /// + uint8_t RA_PREAMBLE_BACKOFF; + /// + uint8_t RA_SCALING_FACTOR_BI; + /// + uint8_t RA_PCMAX; + /// Corresponding RA-RNTI for UL-grant + uint16_t ra_RNTI; + /// Pointer to Msg3 payload for UL-grant + uint8_t *Msg3; + /// Frame of last completed synch + uint8_t sync_frame; + /// Flag to indicate that prach is ready to start: it is enabled with an initial delay after the sync + uint8_t init_msg1; +} NR_PRACH_RESOURCES_t; typedef struct NR_DL_FRAME_PARMS NR_DL_FRAME_PARMS; @@ -313,8 +317,6 @@ struct NR_DL_FRAME_PARMS { uint8_t nb_antennas_rx; /// Number of common transmit antenna ports in eNodeB (1 or 2) uint8_t nb_antenna_ports_gNB; - /// PRACH_CONFIG - NR_PRACH_CONFIG_COMMON prach_config_common; /// Cyclic Prefix for DL (0=Normal CP, 1=Extended CP) lte_prefix_type_t Ncp; /// shift of pilot position in one RB @@ -350,9 +352,10 @@ struct NR_DL_FRAME_PARMS { uint8_t ssb_index; /// PBCH polar encoder params t_nrPolar_params pbch_polar_params; - }; + + #define KHz (1000UL) #define MHz (1000*KHz) diff --git a/openair1/PHY/impl_defs_nr.h b/openair1/PHY/impl_defs_nr.h index 44f2e314ea..3e09f3f593 100644 --- a/openair1/PHY/impl_defs_nr.h +++ b/openair1/PHY/impl_defs_nr.h @@ -757,11 +757,11 @@ typedef struct { #define MAX_NR_OF_SPATIAL_RELATION_INFOS (8) typedef enum { - pucch_format0_nr = 0, - pucch_format1_nr = 1, - pucch_format2_nr = 2, - pucch_format3_nr = 3, - pucch_format4_nr = 4, + pucch_format0_nr = 1, + pucch_format1_nr = 2, + pucch_format2_nr = 3, + pucch_format3_nr = 4, + pucch_format4_nr = 5 } pucch_format_nr_t; typedef enum { diff --git a/openair1/SCHED/phy_procedures_lte_eNb.c b/openair1/SCHED/phy_procedures_lte_eNb.c index ba03e79e62..558fa8d4eb 100644 --- a/openair1/SCHED/phy_procedures_lte_eNb.c +++ b/openair1/SCHED/phy_procedures_lte_eNb.c @@ -1211,6 +1211,8 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) { } if (!decodeSucess) { + T(T_ENB_PHY_ULSCH_UE_NACK, T_INT(eNB->Mod_id), T_INT(rdata->frame), T_INT(rdata->subframe), T_INT(ulsch->rnti), + T_INT(rdata->harq_pid)); fill_crc_indication(eNB,i,rdata->frame,rdata->subframe,1); // indicate NAK to MAC fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d UE %d Error receiving ULSCH, round %d/%d (ACK %d,%d)\n", @@ -1239,6 +1241,8 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) { fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC ulsch_harq->status = SCH_IDLE; ulsch->harq_mask &= ~(1 << rdata->harq_pid); + T (T_ENB_PHY_ULSCH_UE_ACK, T_INT(eNB->Mod_id), T_INT(rdata->frame), T_INT(rdata->subframe), T_INT(ulsch->rnti), + T_INT(rdata->harq_pid)); } // ulsch not in error if (ulsch_harq->O_ACK>0) @@ -1419,7 +1423,7 @@ void fill_rx_indication(PHY_VARS_eNB *eNB, pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation pdu->data = eNB->ulsch[UE_id]->harq_processes[harq_pid]->decodedBytes; // estimate timing advance for MAC - sync_pos = lte_est_timing_advance_pusch(eNB,UE_id); + sync_pos = lte_est_timing_advance_pusch(&eNB->frame_parms, eNB->pusch_vars[UE_id]->drs_ch_estimates_time); timing_advance_update = sync_pos; // - eNB->frame_parms.nb_prefix_samples/4; //to check // if (timing_advance_update > 10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);} diff --git a/openair1/SCHED/ru_procedures.c b/openair1/SCHED/ru_procedures.c index 8846b77af9..cb03821388 100644 --- a/openair1/SCHED/ru_procedures.c +++ b/openair1/SCHED/ru_procedures.c @@ -693,12 +693,6 @@ void ru_fep_full_2thread(RU_t *ru, 3/(fp->symbols_per_tti/2),// Ns = slot number fp); - /*lte_ul_channel_estimation((PHY_VARS_eNB *)NULL, - proc, - ru->idx, - 3%(fp->symbols_per_tti/2), - 3/(fp->symbols_per_tti/2)); - */ lte_ul_channel_estimation_RRU(fp, calibration->drs_ch_estimates, calibration->drs_ch_estimates_time, @@ -713,7 +707,7 @@ void ru_fep_full_2thread(RU_t *ru, 0,//interpolate, 0 /*eNB->ulsch[ru->idx]->rnti rnti or ru->ulsch[eNB_id]->rnti*/); - check_sync_pos = lte_est_timing_advance_pusch((PHY_VARS_eNB *)NULL, ru->idx); + check_sync_pos = lte_est_timing_advance_pusch(ru->frame_parms, ru->calibration.drs_ch_estimates_time); if (ru->state == RU_CHECK_SYNC) { if ((check_sync_pos >= 0 && check_sync_pos<8) || (check_sync_pos < 0 && check_sync_pos>-8)) { LOG_I(PHY,"~~~~~~~~~~~ check_sync_pos %d, frame %d, cnt %d\n",check_sync_pos,proc->frame_rx,ru->wait_check); diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 5c145a3230..2870f1d42e 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -44,7 +44,7 @@ void handle_nr_nfapi_ssb_pdu(PHY_VARS_gNB *gNB,int frame,int slot, AssertFatal(dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag== 1, "bchPayloadFlat %d != 1\n", dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag); - LOG_I(PHY,"%d.%d : pbch_pdu: %x\n",frame,slot,dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload); + LOG_D(PHY,"%d.%d : pbch_pdu: %x\n",frame,slot,dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload); memcpy((void*)&gNB->ssb_pdu,&dl_tti_pdu->ssb_pdu,sizeof(dl_tti_pdu->ssb_pdu)); } @@ -113,8 +113,6 @@ void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB, nr_fill_ul_dci(gNB,frame,slot); - - } void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, @@ -144,20 +142,25 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ gNB = RC.gNB[Mod_id]; - uint8_t number_dl_pdu = DL_req->dl_tti_request_body.nPDUs; - // uint8_t number_ul_pdu = 0; + uint8_t number_dl_pdu = (DL_req==NULL) ? 0 : DL_req->dl_tti_request_body.nPDUs; uint8_t number_ul_dci_pdu = (UL_dci_req==NULL) ? 0 : UL_dci_req->numPdus; + uint8_t number_ul_tti_pdu = (UL_tti_req==NULL) ? 0 : UL_tti_req->n_pdus; - // if (UL_tti_req != NULL) number_ul_pdu = UL_tti_req->n_pdus; - - LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;\n", - frame,slot, - DL_req->SFN,DL_req->Slot,number_dl_pdu, - TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs); + if (DL_req != NULL && TX_req!=NULL) + LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d/%d DL_req:SFN/SLO:%04d/%d:dl_pdu:%d tx_req:SFN/SLOT:%04d/%d:pdus:%d;ul_dci %d ul_tti %d\n", + frame,slot, + DL_req->SFN,DL_req->Slot,number_dl_pdu, + TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs, + number_ul_dci_pdu,number_ul_tti_pdu); int pdcch_received=0; gNB->num_pdsch_rnti=0; + for (int i=0; idlsch[i][0]->rnti=0; + gNB->dlsch[i][0]->harq_mask=0; + } gNB->pdcch_pdu = NULL; + gNB->ul_dci_pdu = NULL; gNB->pbch_configured=0; for (int i=0;iSFN,DL_req->Slot); handle_nfapi_nr_pdcch_pdu(gNB, frame, slot, &dl_tti_pdu->pdcch_pdu); @@ -184,6 +188,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE: { + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot); nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel15; uint16_t pduIndex = pdsch_pdu_rel15->pduIndex; AssertFatal(TX_req->pdu_list[pduIndex].num_TLV == 1, "TX_req->pdu_list[%d].num_TLV %d != 1\n", @@ -194,13 +199,28 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ } } - if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); + // if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); for (int i=0;iul_dci_pdu_list[i]); + handle_nfapi_nr_ul_dci_pdu(gNB, frame, slot, &UL_dci_req->ul_dci_pdu_list[i]); } - + for (int i = 0; i < number_ul_tti_pdu; i++) { + switch (UL_tti_req->pdus_list[i].pdu_type) { + case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUSCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); + nr_fill_ulsch(gNB,UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pusch_pdu); + break; + case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUCCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); + nr_fill_pucch(gNB,UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pucch_pdu); + break; + case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PRACH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); + nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu; + nr_fill_prach(gNB, UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu); + nr_fill_prach_ru(gNB->RU_list[0], UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu); + break; + } + } } diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index 9054ddbae5..a5d459a7c6 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -32,7 +32,7 @@ #include "PHY/defs_gNB.h" #include "PHY/phy_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "nfapi_nr_interface_scf.h" #include "fapi_nr_l1.h" #include "nfapi_pnf.h" @@ -77,15 +77,14 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, } } - - /* rx_nr_prach(gNB, + rx_nr_prach(gNB, prach_pdu, frame, slot, &max_preamble[0], &max_preamble_energy[0], &max_preamble_delay[0] - );*/ + ); LOG_D(PHY,"[RAPROC] Frame %d, slot %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", frame,slot, diff --git a/openair1/SCHED_NR/nr_ru_procedures.c b/openair1/SCHED_NR/nr_ru_procedures.c index aefeec43e2..560f47059a 100644 --- a/openair1/SCHED_NR/nr_ru_procedures.c +++ b/openair1/SCHED_NR/nr_ru_procedures.c @@ -520,7 +520,7 @@ void nr_fep0(RU_t *ru, int first_half) { ru->common.rxdataF[aa], l, proc->tti_rx, - 0, + ru->N_TA_offset, 0); } } @@ -642,6 +642,8 @@ void nr_fep_full(RU_t *ru, int slot) { // if ((fp->frame_type == TDD) && // (subframe_select(fp,proc->tti_rx) != NR_UPLINK_SLOT)) return; + LOG_D(PHY,"In fep_full for slot = %d\n", proc->tti_rx); + start_meas(&ru->ofdm_demod_stats); if (ru->idx == 0) VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX, 1 ); @@ -655,7 +657,7 @@ void nr_fep_full(RU_t *ru, int slot) { ru->common.rxdataF[aa], l, proc->tti_rx, - 0, + ru->N_TA_offset, 0); } } diff --git a/openair1/SCHED_NR/phy_frame_config_nr.c b/openair1/SCHED_NR/phy_frame_config_nr.c index a36cebd6ae..0ccb13fc7c 100644 --- a/openair1/SCHED_NR/phy_frame_config_nr.c +++ b/openair1/SCHED_NR/phy_frame_config_nr.c @@ -369,6 +369,73 @@ int nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti) } } +/******************************************************************* +* +* NAME : nr_ue_slot_select +* +* DESCRIPTION : function for the UE equivalent to nr_slot_select +* +*********************************************************************/ + +int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti) { + /* for FFD all slot can be considered as an uplink */ + int mu = cfg->ssb_config.scs_common, check_slot = 0; + + if (cfg->cell_config.frame_duplex_type == FDD) { + return (NR_UPLINK_SLOT | NR_DOWNLINK_SLOT); + } + + if (nr_frame%2 == 0) { + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 1) { + check_slot++; + } + } + + if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { + return (NR_UPLINK_SLOT); + } + + check_slot = 0; + + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 0) { + check_slot++; + } + } + + if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { + return (NR_DOWNLINK_SLOT); + } else { + return (NR_MIXED_SLOT); + } + } else { + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[((1<tdd_table.max_tdd_periodicity_list[((1< /************** DEFINE ********************************************/ #define TDD_CONFIG_NB_FRAMES (2) @@ -79,6 +80,7 @@ int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms); @returns nr_slot_t : downlink or uplink */ nr_slot_t nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti); +int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti); /** \brief This function frees tdd configuration for nr * @param frame_parms NR DL Frame parameters diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 60f9d4747a..992c908c5d 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -23,7 +23,6 @@ #include "PHY/defs_gNB.h" #include "sched_nr.h" #include "PHY/NR_REFSIG/dmrs_nr.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" @@ -50,6 +49,8 @@ #include "intertask_interface.h" +//#define DEBUG_RXDATA + uint8_t SSB_Table[38]={0,2,4,6,8,10,12,14,254,254,16,18,20,22,24,26,28,30,254,254,32,34,36,38,40,42,44,46,254,254,48,50,52,54,56,58,60,62}; extern uint8_t nfapi_mode; @@ -143,7 +144,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, if ((cfg->cell_config.frame_duplex_type.value == TDD) && (nr_slot_select(cfg,frame,slot) == NR_UPLINK_SLOT)) return; - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX+offset,1); if (do_meas==1) start_meas(&gNB->phy_proc_tx); @@ -152,12 +153,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, memset(&gNB->common_vars.txdataF[aa][txdataF_offset],0,fp->samples_per_slot_wCP*sizeof(int32_t)); } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,1); if (nfapi_mode == 0 || nfapi_mode == 1) { if ((!(frame%ssb_frame_periodicity))) // generate SSB only for given frames according to SSB periodicity nr_common_signal_procedures(gNB,frame, slot); } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,0); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,0); if (gNB->pdcch_pdu || gNB->ul_dci_pdu) { @@ -166,7 +167,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, gNB->ul_dci_pdu==NULL?0:gNB->ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15.numDlDci, gNB->pdcch_pdu==NULL?0:gNB->pdcch_pdu->pdcch_pdu_rel15.numDlDci); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,1); nr_generate_dci_top(gNB->pdcch_pdu, gNB->ul_dci_pdu, @@ -174,12 +175,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, &gNB->common_vars.txdataF[0][txdataF_offset], AMP, *fp); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,0); } - LOG_D(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti); for (int i=0; inum_pdsch_rnti; i++) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1); + LOG_D(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti); nr_generate_pdsch(gNB->dlsch[i][0], gNB->nr_gold_pdsch_dmrs[slot], gNB->common_vars.txdataF, @@ -197,7 +198,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0); } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,0); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX+offset,0); } @@ -209,8 +210,6 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, // VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX,1); - - if (do_prach_rx(fp,frame,slot)) L1_nr_prach_procedures(gNB,frame,slot/fp->slots_per_subframe); */ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH_id, uint8_t harq_pid) @@ -227,9 +226,12 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH number_symbols = pusch_pdu->nr_of_symbols; for (l = start_symbol; l < start_symbol + number_symbols; l++) - number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; + number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; - nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4); + if (pusch_pdu->dmrs_config_type==pusch_dmrs_type1) + nb_re_dmrs = 6*pusch_pdu->num_dmrs_cdm_grps_no_data; + else + nb_re_dmrs = 4*pusch_pdu->num_dmrs_cdm_grps_no_data; G = nr_get_G(pusch_pdu->rb_size, number_symbols, @@ -238,11 +240,9 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH pusch_pdu->qam_mod_order, pusch_pdu->nrOfLayers); - //---------------------------------------------------------- //------------------- ULSCH unscrambling ------------------- //---------------------------------------------------------- - start_meas(&gNB->ulsch_unscrambling_stats); nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr, G, @@ -266,6 +266,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH G); stop_meas(&gNB->ulsch_decoding_stats); + if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations){ LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id); nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1); @@ -365,6 +366,7 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) for(symbol = 0; symbol < NR_SYMBOLS_PER_SLOT; symbol++) { // nr_slot_fep_ul(gNB, symbol, proc->slot_rx, 0, 0); + for (aa = 0; aa < gNB->frame_parms.nb_antennas_rx; aa++) { nr_slot_fep_ul(&gNB->frame_parms, gNB->common_vars.rxdata[aa], @@ -380,68 +382,91 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; - int num_pdus = UL_tti_req->n_pdus; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,1); + LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d\n",frame_rx,slot_rx); - nfapi_nr_uci_indication_t *uci_indication = &gNB->uci_indication; - uci_indication->sfn = frame_rx; - uci_indication->slot = slot_rx; - uci_indication->num_ucis = 0; + for (int i=0;ipucch[i]; + if (pucch) { + if ((pucch->active == 1) && + (pucch->frame == frame_rx) && + (pucch->slot == slot_rx) ) { + nfapi_nr_pucch_pdu_t *pucch_pdu = &pucch[i].pucch_pdu; + uint16_t num_ucis; - LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus); + switch (pucch_pdu->format_type) { + case 0: - gNB->UL_INFO.rx_ind.number_of_pdus = 0; - gNB->UL_INFO.crc_ind.number_crcs = 0; + num_ucis = gNB->UL_INFO.uci_ind.num_ucis; + gNB->UL_INFO.uci_ind.uci_list = &gNB->uci_pdu_list[0]; + gNB->UL_INFO.uci_ind.sfn = frame_rx; + gNB->UL_INFO.uci_ind.slot = slot_rx; + gNB->uci_pdu_list[num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; + gNB->uci_pdu_list[num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &gNB->uci_pdu_list[num_ucis].pucch_pdu_format_0_1; - for (int i = 0; i < num_pdus; i++) { - switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - { - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); - - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); - - uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); - uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; - uint8_t symbol_start = pusch_pdu->start_symbol_index; - uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; - - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); - } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - } - break; - case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: - { - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx); - - nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[i].pucch_pdu; - switch (pucch_pdu->format_type) { - case 0: - uci_indication->uci_list[uci_indication->num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; - uci_indication->uci_list[uci_indication->num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); - nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &uci_indication->uci_list[uci_indication->num_ucis].pucch_pdu_format_0_1; - - nr_decode_pucch0(gNB, - slot_rx, - uci_pdu_format0, - pucch_pdu); - - uci_indication->num_ucis += 1; + nr_decode_pucch0(gNB, + slot_rx, + uci_pdu_format0, + pucch_pdu); + + gNB->UL_INFO.uci_ind.num_ucis += 1; + pucch->active = 0; break; - case 1: - break; - case 2: - break; - default: - AssertFatal(1==0,"Only PUCCH format 0,1 and 2 are currently supported\n"); - } + default: + AssertFatal(1==0,"Only PUCCH format 0 is currently supported\n"); + } } } } + + for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id][0]; + int harq_pid; + int no_sig; + NR_UL_gNB_HARQ_t *ulsch_harq; + + if ((ulsch) && + (ulsch->rnti > 0)) { + // for for an active HARQ process + for (harq_pid=0;harq_pidharq_processes[harq_pid]; + AssertFatal(ulsch_harq!=NULL,"harq_pid %d is not allocated\n",harq_pid); + if ((ulsch_harq->status == NR_ACTIVE) && + (ulsch_harq->frame == frame_rx) && + (ulsch_harq->slot == slot_rx) && + (ulsch_harq->handled == 0)){ + +#ifdef DEBUG_RXDATA + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; + RU_t *ru = gNB->RU_list[0]; + int slot_offset = frame_parms->get_samples_slot_timestamp(slot_rx,frame_parms,0); + slot_offset -= ru->N_TA_offset; + char name[128]; + FILE *f; + sprintf(name, "rxdata.%d.%d.raw", frame_rx,slot_rx); + f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(&ru->common.rxdata[0][slot_offset],2,frame_parms->get_samples_per_slot(slot_rx,frame_parms)*2, f); + fclose(f); +#endif + + uint8_t symbol_start = ulsch_harq->ulsch_pdu.start_symbol_index; + uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.nr_of_symbols; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,1); + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,0); + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,0); + break; + } + } + } + } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,0); } diff --git a/openair1/SCHED_NR/sched_nr.h b/openair1/SCHED_NR/sched_nr.h index 5f54539b71..b393e9566e 100644 --- a/openair1/SCHED_NR/sched_nr.h +++ b/openair1/SCHED_NR/sched_nr.h @@ -39,6 +39,7 @@ void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, int frame_tx, int slot_tx, int do_meas); void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx); void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx); +void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot,nfapi_nr_prach_pdu_t *prach_pdu); void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot); void nr_feptx_ofdm(RU_t *ru,int frame_tx,int tti_tx); void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx); diff --git a/openair1/SCHED_NR_UE/defs.h b/openair1/SCHED_NR_UE/defs.h index e34ce2b6de..c6aea2ec08 100644 --- a/openair1/SCHED_NR_UE/defs.h +++ b/openair1/SCHED_NR_UE/defs.h @@ -218,6 +218,15 @@ void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index); */ void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index); +/*! \brief UE PRACH procedures. + @param + @param + @param + */ +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t mode); + +int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms, uint32_t frame, uint8_t subframe); + #if 0 /*! \brief Compute ACK/NACK information for PUSCH/PUCCH for UE transmission in subframe n. This function implements table 10.1-1 of 36.213, p. 69. @param frame_parms Pointer to DL frame parameter descriptor @@ -322,13 +331,14 @@ uint16_t nr_get_n1_pucch(PHY_VARS_NR_UE *phy_vars_ue, uint8_t SR); #endif + /*! \brief This function retrieves the PHY UE mode. It is used as a helper function for the UE MAC. @param Mod_id Local UE index on which to act @param CC_id Component Carrier Index - @param eNB_index ID of eNB + @param gNB_index ID of gNB @returns UE mode */ -UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index); +UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_index); /*! \brief This function implements the power control mechanism for PUCCH from 36.213. @param phy_vars_ue PHY variables diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 7439c26eb7..f852ae4ae1 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -34,30 +34,30 @@ #include "fapi_nr_ue_interface.h" #include "fapi_nr_ue_l1.h" +#include "harq_nr.h" //#include "PHY/phy_vars_nr_ue.h" #include "PHY/defs_nr_UE.h" #include "PHY/impl_defs_nr.h" + extern PHY_VARS_NR_UE ***PHY_vars_UE_g; -int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) -{ - +int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ if(scheduled_response != NULL){ - /// module id - module_id_t module_id = scheduled_response->module_id; - /// component carrier id - uint8_t cc_id = scheduled_response->CC_id; + + module_id_t module_id = scheduled_response->module_id; + uint8_t cc_id = scheduled_response->CC_id, thread_id; uint32_t i; - int slot = scheduled_response->slot; + int slot = scheduled_response->slot; + // Note: we have to handle the thread IDs for this. To be revisited completely. - uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; + thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; + NR_UE_DLSCH_t *dlsch0 = NULL; NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; - NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; - //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; - PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; + NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; + //PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; // PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; // PUCCH_Config_t *pucch_config_dedicated = PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; @@ -67,118 +67,155 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) LOG_D(PHY,"Received %d DL pdus\n",dl_config->number_pdus); pdcch_vars->nb_search_space = 0; - for(i=0; inumber_pdus; ++i){ - if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){ - fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15; - memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config)); - pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1; - LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space); - }else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH - // dlsch config pdu - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15; - uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr; - dlsch0->current_harq_pid = current_harq_pid; - dlsch0->active = 1; - dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti; - - //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs; - - NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; + for (i = 0; i < dl_config->number_pdus; ++i){ - dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; - dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; - dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; - dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; - dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; - dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; - dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; - dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; - dlsch0_harq->mcs = dlsch_config_pdu->mcs; - dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; - dlsch0_harq->rvidx = dlsch_config_pdu->rv; - dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; - dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; - dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; - dlsch0_harq->Nl=1; - dlsch0_harq->mcs_table=0; - dlsch0_harq->status = ACTIVE; - LOG_D(MAC,">>>> \tdlsch0->g_pucch=%d\tdlsch0_harq.mcs=%d\n",dlsch0->g_pucch,dlsch0_harq->mcs); + if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI) { - } + fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15; + memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config)); + pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1; + LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space); + + } else { + + if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DLSCH){ + dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; + } + else if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH){ + dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch_ra[0]; + } + + fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15; + uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr; + NR_DL_UE_HARQ_t *dlsch0_harq; + + dlsch0->current_harq_pid = current_harq_pid; + dlsch0->active = 1; + dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti; + //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs; + dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; + + if (dlsch0_harq){ + + dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; + dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; + dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; + dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; + dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; + dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; + dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; + dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; + dlsch0_harq->mcs = dlsch_config_pdu->mcs; + dlsch0_harq->rvidx = dlsch_config_pdu->rv; + dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; + dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; + dlsch0_harq->harq_ack.slot_for_feedback_ack = (slot+dlsch_config_pdu->pdsch_to_harq_feedback_time_ind)%frame_parms.slots_per_frame; + dlsch0_harq->Nl=1; + dlsch0_harq->mcs_table=0; + dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type); + dlsch0_harq->harq_ack.vDAI_DL = dlsch_config_pdu->dai; + LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs); + } + } } - }else{ + } else { pdcch_vars->nb_search_space = 0; } - if(scheduled_response->ul_config != NULL){ + if (scheduled_response->ul_config != NULL){ + fapi_nr_ul_config_request_t *ul_config = scheduled_response->ul_config; - for(i=0; inumber_pdus; ++i){ - if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH){ - // pusch config pdu - nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu = &ul_config->ul_config_list[i].pusch_config_pdu; - uint8_t current_harq_pid = pusch_config_pdu->pusch_data.harq_process_id; - nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &ulsch0->harq_processes[current_harq_pid]->pusch_pdu; - memcpy(pusch_pdu, pusch_config_pdu, sizeof(nfapi_nr_ue_pusch_pdu_t)); + for (i = 0; i < ul_config->number_pdus; ++i){ - ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; - } - if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){ - // pucch config pdu - fapi_nr_ul_config_pucch_pdu *pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu; - uint8_t pucch_resource_id = 0; //FIXME!!! - uint8_t format = 1; // FIXME!!! - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].hoppingId = pucch_config_pdu->hoppingId; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].p0_nominal = pucch_config_pdu->p0_nominal; - /* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used - pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used - pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; - pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; - pucch_config_common->hoppingId = pucch_config_pdu->hoppingId; - pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/ - } - if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PRACH){ - // prach config pdu - fapi_nr_ul_config_prach_pdu *prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; - /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; - frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; - frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; - frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; - frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/ - prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; - } + uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format, gNB_id = 0; + /* PRACH */ + //NR_PRACH_RESOURCES_t *prach_resources; + fapi_nr_ul_config_prach_pdu *prach_config_pdu; + /* PUSCH */ + nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu; + /* PUCCH */ + fapi_nr_ul_config_pucch_pdu *pucch_config_pdu; + PUCCH_ConfigCommon_nr_t *pucch_config_common_nr; + PUCCH_Config_t *pucch_config_dedicated_nr; + PUCCH_format_t *format_params; + + switch (pdu_type){ + + case (FAPI_NR_UL_CONFIG_TYPE_PUSCH): + // pusch config pdu + pusch_config_pdu = &ul_config->ul_config_list[i].pusch_config_pdu; + current_harq_pid = pusch_config_pdu->pusch_data.harq_process_id; + nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &ulsch0->harq_processes[current_harq_pid]->pusch_pdu; + + memcpy(pusch_pdu, pusch_config_pdu, sizeof(nfapi_nr_ue_pusch_pdu_t)); + + ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; + ulsch0->harq_processes[current_harq_pid]->status = ACTIVE; + break; + + case (FAPI_NR_UL_CONFIG_TYPE_PUCCH): + // pucch config pdu + pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu; + pucch_resource_id = 0; //FIXME!!! + format = 1; // FIXME!!! + pucch_config_common_nr = &PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; + pucch_config_dedicated_nr = &PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; + format_params = &pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->format_parameters; + + format_params->initialCyclicShift = pucch_config_pdu->initialCyclicShift; + format_params->nrofSymbols = pucch_config_pdu->nrofSymbols; + format_params->startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; + format_params->nrofPRBs = pucch_config_pdu->nrofPRBs; + format_params->timeDomainOCC = pucch_config_pdu->timeDomainOCC; + format_params->occ_length = pucch_config_pdu->occ_length; + format_params->occ_Index = pucch_config_pdu->occ_Index; + + pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; + pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; + pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used + pucch_config_dedicated_nr->formatConfig[format - 1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used + pucch_config_dedicated_nr->formatConfig[format - 1]->pi2PBSK = pucch_config_pdu->pi2PBSK; + + pucch_config_common_nr->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; + pucch_config_common_nr->hoppingId = pucch_config_pdu->hoppingId; + pucch_config_common_nr->p0_nominal = pucch_config_pdu->p0_nominal; + + /* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used + pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used + pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; + pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; + pucch_config_common->hoppingId = pucch_config_pdu->hoppingId; + pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/ + break; + + case (FAPI_NR_UL_CONFIG_TYPE_PRACH): + // prach config pdu + //prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; + prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; + memcpy((void*)&(PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_pdu), (void*)prach_config_pdu, sizeof(fapi_nr_ul_config_prach_pdu)); + PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_Config_enabled = 1; + break; + + default: + break; + } } - }else{ - + } else { } - if(scheduled_response->tx_request != NULL){ - - }else{ - + if (scheduled_response->tx_request != NULL){ + } else { } } @@ -186,13 +223,15 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) } + + int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){ fapi_nr_config_request_t *nrUE_config = &PHY_vars_UE_g[phy_config->Mod_id][phy_config->CC_id]->nrUE_config; - + if(phy_config != NULL) memcpy(nrUE_config,&phy_config->config_req,sizeof(fapi_nr_config_request_t)); - + return 0; } diff --git a/openair1/SCHED_NR_UE/phy_frame_config_nr.h b/openair1/SCHED_NR_UE/phy_frame_config_nr.h index 81b6d373df..a7e78397fe 100644 --- a/openair1/SCHED_NR_UE/phy_frame_config_nr.h +++ b/openair1/SCHED_NR_UE/phy_frame_config_nr.h @@ -78,6 +78,5 @@ void free_tdd_configuration_nr(NR_DL_FRAME_PARMS *frame_parms); void free_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms); -void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mod); #endif /* PHY_FRAME_CONFIG_NR_H */ diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index e5e48ee0ed..e902977721 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -44,6 +44,7 @@ #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" //#include "PHY/extern.h" #include "SCHED_NR_UE/defs.h" +#include "SCHED_NR_UE/pucch_uci_ue_nr.h" #include "SCHED_NR/extern.h" #include "SCHED_NR_UE/phy_sch_processing_time.h" //#include @@ -53,7 +54,7 @@ #ifdef EMOS #include "SCHED/phy_procedures_emos.h" #endif - +#include "executables/softmodem-common.h" //#define DEBUG_PHY_PROC #define NR_PDCCH_SCHED @@ -66,6 +67,7 @@ #endif #include "LAYER2/NR_MAC_UE/mac_defs.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" #include "common/utils/LOG/log.h" #ifdef EMOS @@ -190,14 +192,13 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, exit(-1); } -#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) -//unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; -/* - unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL) - { +#endif - int gain_dB = power_dBm - power_max_dBm; - int amp_x_100; +unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; + +int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL){ + + int gain_dB = power_dBm - power_max_dBm, amp_x_100 = -1; switch (N_RB_UL) { case 6: @@ -219,37 +220,21 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, amp_x_100 = 408*AMP; // 408 = 100*sqrt(100/6) break; default: - LOG_E(PHY,"Unknown PRB size %d\n",N_RB_UL); - //mac_xface->macphy_exit(""); + LOG_E(PHY, "Unknown PRB size %d\n", N_RB_UL); + return (amp_x_100); break; } if (gain_dB < -30) { - return(amp_x_100/3162); - } else if (gain_dB>0) - return(amp_x_100); + return (amp_x_100/3162); + } else if (gain_dB > 0) + return (amp_x_100); else - return(amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6) - } -*/ + return (amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6) -unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb) -{ - - int gain_dB = power_dBm - power_max_dBm; - double gain_lin; - - gain_lin = pow(10,.1*gain_dB); - if ((nb_rb >0) && (nb_rb <= N_RB_UL)) { - return((int)(AMP*sqrt(gain_lin*N_RB_UL/(double)nb_rb))); - } - else { - LOG_E(PHY,"Illegal nb_rb/N_RB_UL combination (%d/%d)\n",nb_rb,N_RB_UL); - //mac_xface->macphy_exit(""); - } - return(0); + return (amp_x_100); } -#endif +#if 0 void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t nr_tti_rx) { @@ -289,107 +274,6 @@ void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, write_output("dlsch_mag2.m","dlschmag2",ue->pdsch_vars_ra[0]->dl_ch_magb0,300*nsymb,1,1); } -void phy_reset_ue(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - // This flushes ALL DLSCH and ULSCH harq buffers of ALL connected eNBs...add the eNB_index later - // for more flexibility - - uint8_t i,j,k,s; - PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - //[NUMBER_OF_RX_THREAD=2][NUMBER_OF_CONNECTED_eNB_MAX][2]; - for(int l=0; ldlsch[l][i][j]) { - for(k=0; kdlsch[l][i][j]->harq_processes[k]; k++) { - ue->dlsch[l][i][j]->harq_processes[k]->status = SCH_IDLE; - for (s=0; s<10; s++) { - // reset ACK/NACK bit to DTX for all nr_tti_rxs s = 0..9 - ue->dlsch[l][i][j]->harq_ack[s].ack = 2; - ue->dlsch[l][i][j]->harq_ack[s].send_harq_status = 0; - ue->dlsch[l][i][j]->harq_ack[s].vDAI_UL = 0xff; - ue->dlsch[l][i][j]->harq_ack[s].vDAI_DL = 0xff; - } - } - } - } - - //UL HARQ - if(ue->ulsch[i]) { - for(k=0; kulsch[i]->harq_processes[k]; k++) { - ue->ulsch[i]->harq_processes[k]->status = SCH_IDLE; - //Set NDIs for all UL HARQs to 0 - // ue->ulsch[i]->harq_processes[k]->Ndi = 0; - - } - } - - // flush Msg3 buffer - ue->ulsch_Msg3_active[i] = 0; - - } - } -} - -void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - // if contention resolution fails, go back to PRACH - PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PRACH; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti = 0; - LOG_E(PHY,"[UE %d] Random-access procedure fails, going back to PRACH, setting SIStatus = 0, discard temporary C-RNTI and State RRC_IDLE\n",Mod_id); - //mac_xface->macphy_exit(""); -} - -void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - int i; - - LOG_I(PHY,"[UE %d][RAPROC] Random-access procedure succeeded. Set C-RNTI = Temporary C-RNTI\n",Mod_id); - - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->ulsch_Msg3_active[eNB_index] = 0; - PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PUSCH; - - for (i=0; i<8; i++) { - if (PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]) { - PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]->status=IDLE; - PHY_vars_UE_g[Mod_id][CC_id]->dlsch[0][eNB_index][0]->harq_processes[i]->round=0; - PHY_vars_UE_g[Mod_id][CC_id]->dlsch[1][eNB_index][0]->harq_processes[i]->round=0; - PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]->subframe_scheduling_flag=0; - } - } - - -} - -UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index]); - -} -void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint16_t timing_advance) { - - ue->timing_advance = timing_advance*4; - - -#ifdef DEBUG_PHY_PROC - /* TODO: fix this log, what is 'HW timing advance'? */ - /*LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d, HW timing advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx_rx, ue->timing_advance);*/ - LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx, ue->timing_advance); -#endif - -} - uint8_t nr_is_SR_TXOp(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id) { @@ -1380,14 +1264,12 @@ void ulsch_common_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_ #endif +UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_id){ + return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[gNB_id]); +} -void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){ - - // 3GPP TS 38.213 p4.2 - // scale by the scs numerology - int factor_mu = 1 << mu; +uint16_t get_bw_scaling(uint16_t bwp_ul_NB_RB){ uint16_t bw_scaling; - // scale the 16 factor in N_TA calculation in 38.213 section 4.2 according to the used FFT size switch (bwp_ul_NB_RB) { case 32: bw_scaling = 4; break; @@ -1398,13 +1280,37 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com case 273: bw_scaling = 32; break; default: abort(); } + return bw_scaling; +} + +void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){ + + // 3GPP TS 38.213 p4.2 + // scale by the scs numerology + int factor_mu = 1 << mu; + uint16_t bw_scaling = get_bw_scaling(bwp_ul_NB_RB); PHY_vars_UE_g[Mod_id][CC_id]->timing_advance += (ta_command - 31) * bw_scaling / factor_mu; - LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %u\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); + LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %d\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); +} + +// WIP +// - todo: handle TA application as per ch 4.2 TS 38.213 +void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint16_t ta_command) { + + int factor_mu = 1 << ue->frame_parms.numerology_index; + uint16_t bwp_ul_NB_RB = ue->frame_parms.N_RB_UL; + uint16_t bw_scaling = get_bw_scaling(bwp_ul_NB_RB); + + // Transmission timing adjustment (TS 38.213 p4.2) + ue->timing_advance = bw_scaling / factor_mu; + + LOG_D(PHY, "[UE %d] Frame %d Slot %d, Received (RAR) timing advance command %d new value is %u \n", ue->Mod_id, proc->frame_rx, proc->nr_tti_rx, ta_command, ue->timing_advance); } #if 0 + void ue_ulsch_uespec_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t eNB_id, @@ -2312,28 +2218,26 @@ void ue_pucch_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, - uint8_t thread_id) -{ + uint8_t thread_id){ //int32_t ulsch_start=0; int slot_tx = proc->nr_tti_tx; int frame_tx = proc->frame_tx; + uint8_t harq_pid = 0; + runmode_t mode = normal_txrx; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,VCD_FUNCTION_IN); + memset(ue->common_vars.txdataF[0], 0, sizeof(int)*14*ue->frame_parms.ofdm_symbol_size); + LOG_I(PHY,"****** start TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); #if UE_TIMING_TRACE start_meas(&ue->phy_proc_tx); #endif - uint8_t harq_pid = 0; //temporary implementation - - nr_ue_ulsch_procedures(ue, - harq_pid, - frame_tx, - slot_tx, - thread_id, - gNB_id); + if (ue->UE_mode[gNB_id] == PUSCH || get_softmodem_params()->phy_test == 1){ + if (ue->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->status == ACTIVE) + nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, thread_id, gNB_id); /* @@ -2345,33 +2249,30 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } // UE_mode==PUSCH */ - LOG_D(PHY, "Sending data \n"); - nr_ue_pusch_common_procedures(ue, - harq_pid, - slot_tx, - thread_id, - gNB_id, - &ue->frame_parms); + if (get_softmodem_params()->usim_test==0) { + LOG_D(PHY, "Sending PUCCH\n"); + pucch_procedures_ue_nr(ue, + gNB_id, + proc, + TRUE); + } + LOG_D(PHY, "Sending data \n"); + nr_ue_pusch_common_procedures(ue, + harq_pid, + slot_tx, + thread_id, + gNB_id, + &ue->frame_parms); + } //LOG_M("txdata.m","txs",ue->common_vars.txdata[0],1228800,1,1); - -/* - if ((ue->UE_mode[eNB_id] == PRACH) && - (ue->frame_parms.prach_config_common.prach_Config_enabled==1)) { - - // check if we have PRACH opportunity - - if (is_prach_subframe(&ue->frame_parms,frame_tx,nr_tti_tx)) { - - ue_prach_procedures(ue,proc,eNB_id,abstraction_flag,mode); + /* RACH */ + if (get_softmodem_params()->do_ra==1) { + if ((ue->UE_mode[gNB_id] == PRACH) && (ue->prach_vars[gNB_id]->prach_Config_enabled == 1)) { + nr_ue_prach_procedures(ue, proc, gNB_id, mode); } - } // mode is PRACH - else { - ue->generate_prach=0; } -*/ - LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT); @@ -2381,137 +2282,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } - -void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode) { - - int frame_tx = proc->frame_tx; - int nr_tti_tx = proc->nr_tti_tx; - int prach_power; - uint16_t preamble_tx=50; - PRACH_RESOURCES_t prach_resources; - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); - - ue->generate_nr_prach=0; - if (ue->mac_enabled==0){ - ue->prach_resources[eNB_id] = &prach_resources; - ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; - ue->prach_resources[eNB_id]->ra_TDD_map_index = 0; - } - - if (ue->mac_enabled==1){ - - // ask L2 for RACH transport - if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) { - LOG_D(PHY,"Getting PRACH resources\n"); - //ue->prach_resources[eNB_id] = mac_xface->ue_get_rach(ue->Mod_id,ue->CC_id,frame_tx,eNB_id,nr_tti_tx); - // LOG_D(PHY,"Got prach_resources for eNB %d address %p, RRCCommon %p\n",eNB_id,ue->prach_resources[eNB_id],UE_mac_inst[ue->Mod_id].radioResourceConfigCommon); - // LOG_D(PHY,"Prach resources %p\n",ue->prach_resources[eNB_id]); - } -} - -if (ue->prach_resources[eNB_id]!=NULL) { - - ue->generate_nr_prach=1; - ue->prach_cnt=0; -#ifdef SMBV -ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; -#endif - -#ifdef OAI_EMU - ue->prach_PreambleIndex=ue->prach_resources[eNB_id]->ra_PreambleIndex; -#endif - - if (abstraction_flag == 0) { - - LOG_I(PHY,"mode %d\n",mode); - - if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) { - - ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id); - } - else { - ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; - ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; - } - - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n", - ue->Mod_id, - frame_tx, - nr_tti_tx, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - get_nr_PL(ue,eNB_id), - ue->tx_power_dBm[nr_tti_tx], - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, - ue->prach_resources[eNB_id]->ra_TDD_map_index, - ue->prach_resources[eNB_id]->ra_RNTI); - - ue->tx_total_RE[nr_tti_tx] = 96; - -#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) - ue->prach_vars[eNB_id]->amp = nr_get_tx_amp(ue->tx_power_dBm[nr_tti_tx], - ue->tx_power_max_dBm, - ue->frame_parms.N_RB_UL, - 6); -#else - ue->prach_vars[eNB_id]->amp = AMP; -#endif - if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", - ue->Mod_id, - proc->frame_rx, - proc->nr_tti_tx, - ue->tx_power_dBm[nr_tti_tx], - ue->prach_vars[eNB_id]->amp); - - - // start_meas(&ue->tx_prach); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); - -// prach_power = generate_nr_prach(ue,eNB_id,nr_tti_tx,frame_tx); -prach_power = generate_nr_prach(ue,0,9,0); //subframe number hardcoded according to the simulator - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); - // stop_meas(&ue->tx_prach); - LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", - ue->Mod_id, - get_nr_PL(ue,eNB_id), - ue->tx_power_dBm[nr_tti_tx], - dB_fixed(prach_power), - ue->prach_vars[eNB_id]->amp); - }/* else { - UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1; - UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex; - }*/ // commented for compiling as abstraction flag is 0 - - if (ue->mac_enabled==1){ - //mac_xface->Msg1_transmitted(ue->Mod_id,ue->CC_id,frame_tx,eNB_id); - } - -LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n", - ue->Mod_id,frame_tx,nr_tti_tx,eNB_id, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id), - get_nr_PL(ue,eNB_id)); - -} - - -// if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue -if (mode == calib_prach_tx) - ue->prach_resources[eNB_id]=NULL; - -LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", - ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_nr_prach,ue->prach_cnt); - -ue->prach_cnt++; - -if (ue->prach_cnt==3) - ue->generate_nr_prach=0; - -VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); -} - /* void phy_procedures_UE_S_TX(PHY_VARS_NR_UE *ue,uint8_t eNB_id,uint8_t abstraction_flag,relaying_type_t r_type) { @@ -2678,7 +2448,7 @@ void restart_phy(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc, uint8_t eNB_id,uint } #endif //(0) -void nr_ue_pbch_procedures(uint8_t eNB_id, +void nr_ue_pbch_procedures(uint8_t gNB_id, PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t abstraction_flag) @@ -2697,20 +2467,26 @@ void nr_ue_pbch_procedures(uint8_t eNB_id, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_IN); - //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, eNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,eNB_id); + //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, gNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,gNB_id); ret = nr_rx_pbch(ue, proc, - ue->pbch_vars[eNB_id], + ue->pbch_vars[gNB_id], &ue->frame_parms, - eNB_id, + gNB_id, (ue->frame_parms.ssb_index)&7, SISO, ue->high_speed_flag); if (ret==0) { - ue->pbch_vars[eNB_id]->pdu_errors_conseq = 0; + ue->pbch_vars[gNB_id]->pdu_errors_conseq = 0; + // Switch to PRACH state if it is first PBCH after initial synch and no timing correction is performed + if (ue->UE_mode[gNB_id] == NOT_SYNCHED && ue->no_timing_correction == 1){ + ue->UE_mode[gNB_id] = PRACH; + ue->prach_resources[gNB_id]->sync_frame = frame_rx; + ue->prach_resources[gNB_id]->init_msg1 = 0; + } #ifdef DEBUG_PHY_PROC uint16_t frame_tx; @@ -2740,25 +2516,25 @@ void nr_ue_pbch_procedures(uint8_t eNB_id, exit(-1); */ - ue->pbch_vars[eNB_id]->pdu_errors_conseq++; - ue->pbch_vars[eNB_id]->pdu_errors++; + ue->pbch_vars[gNB_id]->pdu_errors_conseq++; + ue->pbch_vars[gNB_id]->pdu_errors++; - if (ue->pbch_vars[eNB_id]->pdu_errors_conseq>=100) { + if (ue->pbch_vars[gNB_id]->pdu_errors_conseq>=100) { LOG_E(PHY,"More that 100 consecutive PBCH errors! Exiting!\n"); exit_fun("More that 100 consecutive PBCH errors! Exiting!\n"); } } if (frame_rx % 100 == 0) { - ue->pbch_vars[eNB_id]->pdu_fer = ue->pbch_vars[eNB_id]->pdu_errors - ue->pbch_vars[eNB_id]->pdu_errors_last; - ue->pbch_vars[eNB_id]->pdu_errors_last = ue->pbch_vars[eNB_id]->pdu_errors; + ue->pbch_vars[gNB_id]->pdu_fer = ue->pbch_vars[gNB_id]->pdu_errors - ue->pbch_vars[gNB_id]->pdu_errors_last; + ue->pbch_vars[gNB_id]->pdu_errors_last = ue->pbch_vars[gNB_id]->pdu_errors; } #ifdef DEBUG_PHY_PROC LOG_D(PHY,"[UE %d] frame %d, slot %d, PBCH errors = %d, consecutive errors = %d!\n", ue->Mod_id,frame_rx, nr_tti_rx, - ue->pbch_vars[eNB_id]->pdu_errors, - ue->pbch_vars[eNB_id]->pdu_errors_conseq); + ue->pbch_vars[gNB_id]->pdu_errors, + ue->pbch_vars[gNB_id]->pdu_errors_conseq); #endif VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_OUT); } @@ -2989,10 +2765,8 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id, pdcch_vars->nb_search_space); #endif - fapi_nr_dci_indication_t dci_ind; - nr_downlink_indication_t dl_indication; - memset((void*)&dci_ind,0,sizeof(dci_ind)); - memset((void*)&dl_indication,0,sizeof(dl_indication)); + fapi_nr_dci_indication_t dci_ind={0}; + nr_downlink_indication_t dl_indication={0}; dci_cnt = nr_dci_decoding_procedure(ue, proc->frame_rx, nr_tti_rx, @@ -3006,11 +2780,12 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id, //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx); for (int i=0; i rnti %x : format %d\n", - ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]], - i, - dci_ind.dci_list[i].rnti, - dci_ind.dci_list[i].dci_format); + LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI %i of %d total DCIs found --> rnti %x : format %d\n", + ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]], + i + 1, + dci_cnt, + dci_ind.dci_list[i].rnti, + dci_ind.dci_list[i].dci_format); } ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]->dci_received += dci_cnt; @@ -3259,7 +3034,7 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB int first_symbol_flag=0; if (!dlsch0) - return; + return; if (dlsch0->active == 0) return; @@ -3268,9 +3043,9 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart; // uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize; uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb; - uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb; - uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol; - uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols; + uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb; + uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol; + uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols; LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos); @@ -3305,17 +3080,35 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB start_meas(&ue->dlsch_llr_stats_parallelization[ue->current_thread_id[nr_tti_rx]][slot]); #endif // process DLSCH received in first slot - nr_rx_pdsch(ue, - pdsch, - eNB_id, - eNB_id_i, - proc->frame_rx, - nr_tti_rx, // nr_tti_rx, - m, - first_symbol_flag, - dual_stream_UE, - i_mod, - dlsch0->current_harq_pid); + // skip DMRS symbols (will have to check later if PDSCH/DMRS are multiplexed + if (((1<harq_processes[harq_pid]->dlDmrsSymbPos) == 0) + nr_rx_pdsch(ue, + pdsch, + eNB_id, + eNB_id_i, + proc->frame_rx, + nr_tti_rx, // nr_tti_rx, + m, + first_symbol_flag, + dual_stream_UE, + i_mod, + dlsch0->current_harq_pid); + else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS) + if (pdsch == RA_PDSCH) ue->pdsch_vars_ra[eNB_id]->llr_offset[m]=ue->pdsch_vars_ra[eNB_id]->llr_offset[m-1]; + else if (pdsch == PDSCH) nr_rx_pdsch(ue, + pdsch, + eNB_id, + eNB_id_i, + proc->frame_rx, + nr_tti_rx, // nr_tti_rx, + m, + first_symbol_flag, + dual_stream_UE, + i_mod, + dlsch0->current_harq_pid); + else AssertFatal(1==0,"not RA_PDSCH or PDSCH\n"); + } + if (pdsch == PDSCH) LOG_D(PHY,"Done processing symbol %d : llr_offset %d\n",m,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m]); #if UE_TIMING_TRACE stop_meas(&ue->dlsch_llr_stats_parallelization[ue->current_thread_id[nr_tti_rx]][slot]); #if DISABLE_LOG_X @@ -3332,103 +3125,153 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB } // CRNTI active } } -#if 0 -void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmode_t mode, int abstraction_flag) { - int frame_rx = proc->frame_rx; - int nr_tti_rx = proc->nr_tti_rx; - int timing_advance; - NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[eNB_id]; - int harq_pid = 0; - uint8_t *rar; - /* - uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); - uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); - */ +// WIP fix: +// - time domain indication hardcoded to 0 for k2 offset +// - extend TS 38.213 ch 8.3 Msg3 PUSCH +// - b buffer +// - ulsch power offset +// - UE_mode == PUSCH case (should be handled by TA updates) +// - harq +// - optimize: mu_pusch, j and table_6_1_2_1_1_2_time_dom_res_alloc_A are already defined in nr_ue_procedures +void nr_process_rar(nr_downlink_indication_t *dl_info) { - LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Received RAR mode %d\n", - ue->Mod_id, - frame_rx, - nr_tti_rx, ue->UE_mode[eNB_id]); + module_id_t module_id = dl_info->module_id; + int cc_id = dl_info->cc_id, frame_rx = dl_info->proc->frame_rx, nr_tti_rx = dl_info->proc->nr_tti_rx, ta_command, k2, delta; + uint8_t gNB_index = dl_info->gNB_index; // *rar; + //fapi_nr_dci_indication_t *dci_ind = dl_info->dci_ind; + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[module_id][cc_id]; + NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[gNB_index]; + UE_MODE_t UE_mode = ue->UE_mode[gNB_index]; + NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_index]; + uint16_t slots_per_frame = ue->frame_parms.slots_per_frame; + uint8_t mu_pusch = 1, sliv_S, sliv_L; + // definition table j Table 6.1.2.1.1-4 + uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1; + uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1 + {j, 0,14}, // row index 1 + {j, 0,12}, // row index 2 + {j, 0,10}, // row index 3 + {j, 2,10}, // row index 4 + {j, 4,10}, // row index 5 + {j, 4,8}, // row index 6 + {j, 4,6}, // row index 7 + {j+1,0,14}, // row index 8 + {j+1,0,12}, // row index 9 + {j+1,0,10}, // row index 10 + {j+2,0,14}, // row index 11 + {j+2,0,12}, // row index 12 + {j+2,0,10}, // row index 13 + {j, 8,6}, // row index 14 + {j+3,0,14}, // row index 15 + {j+3,0,10} // row index 16 + }; + + LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Received RAR mode %d\n", module_id, frame_rx, nr_tti_rx, UE_mode); if (ue->mac_enabled == 1) { - if ((ue->UE_mode[eNB_id] != PUSCH) && - (ue->prach_resources[eNB_id]->Msg3!=NULL)) { - LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Invoking MAC for RAR (current preamble %d)\n", - ue->Mod_id,frame_rx, - nr_tti_rx, - ue->prach_resources[eNB_id]->ra_PreambleIndex); - - /* timing_advance = mac_xface->ue_process_rar(ue->Mod_id, - ue->CC_id, - frame_rx, - ue->prach_resources[eNB_id]->ra_RNTI, - dlsch0->harq_processes[0]->b, - &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload - */ - /* - ue->pdcch_vars[next1_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; - ue->pdcch_vars[next2_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; - */ + if ((UE_mode != PUSCH) && (prach_resources->Msg3 != NULL)) { - if (timing_advance!=0xffff) { + LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Invoking MAC for RAR (current preamble %d)\n", module_id, frame_rx, nr_tti_rx, prach_resources->ra_PreambleIndex); - LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Got rnti %x and timing advance %d from RAR\n", - ue->Mod_id, - frame_rx, - nr_tti_rx, - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - timing_advance); + ta_command = nr_ue_process_rar(ue->Mod_id, + cc_id, + frame_rx, + dlsch0->harq_processes[0]->b, + &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->pdcch_config[0].rnti, + prach_resources->ra_PreambleIndex, + dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload - // remember this c-rnti is still a tc-rnti + if (ta_command != 0xffff) { + LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Got Temporary C-RNTI %x and timing advance %d from RAR\n", + ue->Mod_id, + frame_rx, + nr_tti_rx, + ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->pdcch_config[0].rnti, + ta_command); - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti_is_temporary = 1; - - //timing_advance = 0; - nr_process_timing_advance_rar(ue,proc,timing_advance); - - if (mode!=debug_prach) { - ue->ulsch_Msg3_active[eNB_id]=1; - nr_get_Msg3_alloc(&ue->frame_parms, - nr_tti_rx, - frame_rx, - &ue->ulsch_Msg3_frame[eNB_id], - &ue->ulsch_Msg3_subframe[eNB_id]); - - LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d nr_tti_rx %d: Msg3_frame %d, Msg3_subframe %d\n", - ue->Mod_id, - frame_rx, - nr_tti_rx, - ue->ulsch_Msg3_frame[eNB_id], - ue->ulsch_Msg3_subframe[eNB_id]); - harq_pid = nr_subframe2harq_pid(&ue->frame_parms, - ue->ulsch_Msg3_frame[eNB_id], - ue->ulsch_Msg3_subframe[eNB_id]); - ue->ulsch[eNB_id]->harq_processes[harq_pid]->round = 0; - - ue->UE_mode[eNB_id] = RA_RESPONSE; - // ue->Msg3_timer[eNB_id] = 10; - ue->ulsch[eNB_id]->power_offset = 6; - ue->ulsch_no_allocation_counter[eNB_id] = 0; - } - } else { // PRACH preamble doesn't match RAR - LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", - ue->Mod_id, - ue->prach_resources[eNB_id]->ra_PreambleIndex); + nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); + + if (ue->mode != debug_prach) { + ue->ulsch_Msg3_active[gNB_index] = 1; + // TS 38.213 ch 8.3 Msg3 PUSCH + // PUSCH time domain resource allocation A for normal CP + // TS 38.214 ch 6.1.2.1.1 + k2 = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][0]; + sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][1]; + sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][2]; + + switch (mu_pusch) { + case 0: + delta = 2; + break; + case 1: + delta = 3; + break; + case 2: + delta = 4; + break; + case 3: + delta = 6; + break; + } + + ue->Msg3_startSymbol[gNB_index] = sliv_S; + ue->Msg3_Length[gNB_index] = sliv_L; + ue->ulsch_Msg3_subframe[gNB_index] = (nr_tti_rx + k2 + delta) % slots_per_frame; + if (nr_tti_rx + k2 + delta > slots_per_frame){ + ue->ulsch_Msg3_frame[gNB_index] = (frame_rx + 1) % 1024; + } else { + ue->ulsch_Msg3_frame[gNB_index] = frame_rx; + } + + LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d subframe %d: Msg3_frame %d, Msg3_subframe %d\n", + ue->Mod_id, + frame_rx, + nr_tti_rx, + ue->ulsch_Msg3_frame[gNB_index], + ue->ulsch_Msg3_subframe[gNB_index]); + // harq_pid = subframe2harq_pid(&ue->frame_parms, + // ue->ulsch_Msg3_frame[gNB_index], + // ue->ulsch_Msg3_subframe[gNB_index]); + // ue->ulsch[gNB_index]->harq_processes[harq_pid]->round = 0; + // ue->Msg3_timer[gNB_index] = 10; + // ue->ulsch[gNB_index].power_offset = 6; + // ue->ulsch_no_allocation_counter[gNB_index] = 0; + ue->UE_mode[gNB_index] = RA_RESPONSE; + } + } else { + LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", ue->Mod_id, prach_resources->ra_PreambleIndex); } - } // mode != PUSCH + } + } else { + // rar = dlsch0->harq_processes[0]->b+1; + // ta_command = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); + // nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); } - else { - rar = dlsch0->harq_processes[0]->b+1; - timing_advance = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); - nr_process_timing_advance_rar(ue,proc,timing_advance); - } - } -#endif + +// if contention resolution fails, go back to UE mode PRACH +void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index) { + + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; + ue->UE_mode[gNB_index] = PRACH; + + for (int i=0; i pdcch_vars[i][gNB_index]->pdcch_config[0].rnti = 0; + } + LOG_E(PHY,"[UE %d] [RAPROC] Random-access procedure fails, going back to PRACH\n", Mod_id); +} + +void nr_ra_succeeded(uint8_t Mod_id, + uint8_t CC_id, + uint8_t gNB_index){ + LOG_I(PHY,"[UE %d][RAPROC] RA procedure succeeded. UE set to PUSCH mode\n", Mod_id); + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; + ue->ulsch_Msg3_active[gNB_index] = 0; + ue->UE_mode[gNB_index] = PUSCH; +} void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, @@ -3439,16 +3282,15 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, int *dlsch_errors, runmode_t mode) { - int harq_pid; + int harq_pid = dlsch0->current_harq_pid; int frame_rx = proc->frame_rx; int nr_tti_rx = proc->nr_tti_rx; int ret=0, ret1=0; NR_UE_PDSCH *pdsch_vars; uint8_t is_cw0_active = 0; uint8_t is_cw1_active = 0; - //nfapi_nr_config_request_t *cfg = &ue->nrUE_config; - //uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value; - uint8_t nb_re_dmrs = 6; //(dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; + uint8_t dmrs_type = dlsch0->harq_processes[harq_pid]->dmrsConfigType; + uint8_t nb_re_dmrs = (dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; // TODO: should changed my mac uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value; uint16_t nb_symb_sch = 9; nr_downlink_indication_t dl_indication; @@ -3471,14 +3313,10 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, if (dlsch0==NULL) AssertFatal(0,"dlsch0 should be defined at this level \n"); - - harq_pid = dlsch0->current_harq_pid; is_cw0_active = dlsch0->harq_processes[harq_pid]->status; nb_symb_sch = dlsch0->harq_processes[harq_pid]->nb_symbols; start_symbol = dlsch0->harq_processes[harq_pid]->start_symbol; - - if(dlsch1) is_cw1_active = dlsch1->harq_processes[harq_pid]->status; @@ -3523,32 +3361,32 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, if (frame_rx < *dlsch_errors) *dlsch_errors=0; - if (pdsch==RA_PDSCH) { + if (pdsch == RA_PDSCH) { if (ue->prach_resources[eNB_id]!=NULL) - dlsch0->rnti = ue->prach_resources[eNB_id]->ra_RNTI; + dlsch0->rnti = ue->prach_resources[eNB_id]->ra_RNTI; else { - LOG_E(PHY,"[UE %d] Frame %d, nr_tti_rx %d: FATAL, prach_resources is NULL\n",ue->Mod_id,frame_rx,nr_tti_rx); - //mac_xface->macphy_exit("prach_resources is NULL"); - return; + LOG_E(PHY,"[UE %d] Frame %d, nr_tti_rx %d: FATAL, prach_resources is NULL\n", ue->Mod_id, frame_rx, nr_tti_rx); + //mac_xface->macphy_exit("prach_resources is NULL"); + return; } } - // start ldpc decode for CW 0 - dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb, - nb_symb_sch, - nb_re_dmrs, - length_dmrs, - dlsch0->harq_processes[harq_pid]->Qm, - dlsch0->harq_processes[harq_pid]->Nl); + // start ldpc decode for CW 0 + dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb, + nb_symb_sch, + nb_re_dmrs, + length_dmrs, + dlsch0->harq_processes[harq_pid]->Qm, + dlsch0->harq_processes[harq_pid]->Nl); #if UE_TIMING_TRACE start_meas(&ue->dlsch_unscrambling_stats); #endif nr_dlsch_unscrambling(pdsch_vars->llr[0], - dlsch0->harq_processes[harq_pid]->G, - 0, - ue->frame_parms.Nid_cell, - dlsch0->rnti); + dlsch0->harq_processes[harq_pid]->G, + 0, + ue->frame_parms.Nid_cell, + dlsch0->rnti); #if UE_TIMING_TRACE @@ -3629,10 +3467,10 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, start_meas(&ue->dlsch_unscrambling_stats); #endif nr_dlsch_unscrambling(pdsch_vars->llr[1], - dlsch1->harq_processes[harq_pid]->G, - 0, - ue->frame_parms.Nid_cell, - dlsch1->rnti); + dlsch1->harq_processes[harq_pid]->G, + 0, + ue->frame_parms.Nid_cell, + dlsch1->rnti); #if UE_TIMING_TRACE stop_meas(&ue->dlsch_unscrambling_stats); #endif @@ -3653,31 +3491,31 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, #ifdef UE_DLSCH_PARALLELISATION ret1 = nr_dlsch_decoding_mthread(ue, - proc, - eNB_id, - pdsch_vars->llr[1], - &ue->frame_parms, - dlsch1, - dlsch1->harq_processes[harq_pid], - frame_rx, - nb_symb_sch, - nr_tti_rx, - harq_pid, - pdsch==PDSCH?1:0, - dlsch1->harq_processes[harq_pid]->TBS>256?1:0); + proc, + eNB_id, + pdsch_vars->llr[1], + &ue->frame_parms, + dlsch1, + dlsch1->harq_processes[harq_pid], + frame_rx, + nb_symb_sch, + nr_tti_rx, + harq_pid, + pdsch==PDSCH?1:0, + dlsch1->harq_processes[harq_pid]->TBS>256?1:0); LOG_T(PHY,"UE_DLSCH_PARALLELISATION is defined, ret1 = %d\n", ret1); #else ret1 = nr_dlsch_decoding(ue, - pdsch_vars->llr[1], - &ue->frame_parms, - dlsch1, - dlsch1->harq_processes[harq_pid], - frame_rx, - nb_symb_sch, - nr_tti_rx, - harq_pid, - pdsch==PDSCH?1:0,//proc->decoder_switch, - dlsch1->harq_processes[harq_pid]->TBS>256?1:0); + pdsch_vars->llr[1], + &ue->frame_parms, + dlsch1, + dlsch1->harq_processes[harq_pid], + frame_rx, + nb_symb_sch, + nr_tti_rx, + harq_pid, + pdsch==PDSCH?1:0,//proc->decoder_switch, + dlsch1->harq_processes[harq_pid]->TBS>256?1:0); LOG_T(PHY,"UE_DLSCH_PARALLELISATION is NOT defined, ret1 = %d\n", ret1); printf("start cw1 dlsch decoding\n"); #endif @@ -3699,35 +3537,46 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, #endif LOG_I(PHY,"AbsSubframe %d.%d --> ldpc Decoding for CW1 %5.3f\n", frame_rx%1024, nr_tti_rx,(ue->dlsch_decoding_stats[ue->current_thread_id[nr_tti_rx]].p_time)/(cpuf*1000.0)); + + LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dlsch1->harq_processes[harq_pid]->TBS); } LOG_D(PHY," ------ end ldpc decoder for AbsSubframe %d.%d ------ \n", frame_rx, nr_tti_rx); - - LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS); + LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS); if(retmax_ldpc_iterations+1){ - // fill dl_indication message - dl_indication.module_id = ue->Mod_id; - dl_indication.cc_id = ue->CC_id; - dl_indication.gNB_index = eNB_id; - dl_indication.frame = frame_rx; - dl_indication.slot = nr_tti_rx; - dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance - dl_indication.proc=proc; + // fill dl_indication message + dl_indication.module_id = ue->Mod_id; + dl_indication.cc_id = ue->CC_id; + dl_indication.gNB_index = eNB_id; + dl_indication.frame = frame_rx; + dl_indication.slot = nr_tti_rx; + dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance + dl_indication.proc=proc; - //dl_indication.rx_ind->number_pdus - rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; - rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b; - rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3; - LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length); - rx_ind.number_pdus = 1; + //dl_indication.rx_ind->number_pdus + switch (pdsch) { + case RA_PDSCH: + rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_RAR; + break; + case PDSCH: + rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; + break; + default: + break; + } - //ue->dl_indication.rx_ind = &dlsch1->harq_processes[harq_pid]->b; //no data, only dci for now - dl_indication.dci_ind = NULL; //&ue->dci_ind; - // send to mac - if (ue->if_inst && ue->if_inst->dl_indication) - ue->if_inst->dl_indication(&dl_indication, ul_time_alignment); + rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b; + rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3; + LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length); + rx_ind.number_pdus = 1; + + //ue->dl_indication.rx_ind = &dlsch1->harq_processes[harq_pid]->b; //no data, only dci for now + dl_indication.dci_ind = NULL; //&ue->dci_ind; + // send to mac + if (ue->if_inst && ue->if_inst->dl_indication) + ue->if_inst->dl_indication(&dl_indication, ul_time_alignment); } // TODO CRC check for CW0 @@ -4045,7 +3894,6 @@ void *UE_thread_slot1_dl_processing(void *arg) { } //printf("[slot1 dl processing] AbsSubframe %d.%d LLR Computation Start wait DCI %d\n",frame_rx,nr_tti_rx,wait); - /**** Pdsch Procedure Slot1 ****/ // start slot1 thread for Pdsch Procedure (slot1) // do procedures for C-RNTI @@ -4133,7 +3981,6 @@ void *UE_thread_slot1_dl_processing(void *arg) { #endif #endif - if (pthread_mutex_lock(&proc->mutex_slot1_dl_processing) != 0) { LOG_E( PHY, "[SCHED][UE] error locking mutex for UE RXTX\n" ); exit_fun("noting to add"); @@ -4182,18 +4029,14 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, int nr_tti_rx = proc->nr_tti_rx; int slot_pbch; NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][0]; - NR_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id]; fapi_nr_config_request_t *cfg = &ue->nrUE_config; - uint8_t harq_pid = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->current_harq_pid; - NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; - uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; - uint16_t start_symb_sch = dlsch0_harq->start_symbol; + uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0; uint8_t dci_cnt = 0; NR_DL_FRAME_PARMS *fp = &ue->frame_parms; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_RX, VCD_FUNCTION_IN); - + LOG_D(PHY," ****** start RX-Chain for Frame.Slot %d.%d ****** \n", frame_rx%1024, nr_tti_rx); /* @@ -4201,7 +4044,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); */ - int coreset_nb_rb=0; int coreset_start_rb=0; if (pdcch_vars->nb_search_space > 0) @@ -4236,11 +4078,12 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (ue->no_timing_correction==0) { LOG_I(PHY,"start adjust sync slot = %d no timing %d\n", nr_tti_rx, ue->no_timing_correction); nr_adjust_synch_ue(fp, - ue, - eNB_id, - nr_tti_rx, - 0, - 16384); + ue, + eNB_id, + frame_rx, + nr_tti_rx, + 0, + 16384); } } @@ -4255,10 +4098,10 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, #endif VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_IN); nr_slot_fep(ue, - l, - nr_tti_rx, - 0, - 0); + l, + nr_tti_rx, + 0, + 0); // note: this only works if RBs for PDCCH are contigous! LOG_D(PHY,"pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d\n", @@ -4285,40 +4128,41 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (dci_cnt > 0) { - LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt); + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt); - } else { - LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx); - } -#endif //NR_PDCCH_SCHED + NR_UE_DLSCH_t *dlsch = NULL; + if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){ + dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]; + } else if (ue->dlsch_ra[0]->active == 1){ + dlsch = ue->dlsch_ra[0]; + } + AssertFatal(dlsch != NULL, "Unsupported mode\n"); + uint8_t harq_pid = dlsch->current_harq_pid; + NR_DL_UE_HARQ_t *dlsch0_harq = dlsch->harq_processes[harq_pid]; + uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; + uint16_t start_symb_sch = dlsch0_harq->start_symbol; + int symb_dmrs = -1; - - if (dci_cnt > 0){ LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx); //to update from pdsch config - start_symb_sch = dlsch0_harq->start_symbol; - int symb_dmrs=-1; + for (int i=0;i<4;i++) if (((1<dlDmrsSymbPos) > 0) {symb_dmrs=i;break;} AssertFatal(symb_dmrs>=0,"no dmrs in 0..3\n"); LOG_D(PHY,"Initializing dmrs for symb %d DMRS mask %x\n",symb_dmrs,dlsch0_harq->dlDmrsSymbPos); nr_gold_pdsch(ue,symb_dmrs,0, 1); - - nb_symb_sch = dlsch0_harq->nb_symbols; for (uint16_t m=start_symb_sch;m<(nb_symb_sch+start_symb_sch) ; m++){ nr_slot_fep(ue, - m, //to be updated from higher layer - nr_tti_rx, - 0, - 0); - - + m, //to be updated from higher layer + nr_tti_rx, + 0, + 0); } - //set active for testing, to be removed - ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 1; + } else { + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n", ue->Mod_id, frame_rx, nr_tti_rx); } - else - ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 0; + +#endif //NR_PDCCH_SCHED #if UE_TIMING_TRACE start_meas(&ue->generic_stat); @@ -4332,7 +4176,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, PDSCH, ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0], NULL); - + //printf("phy procedure pdsch start measurement\n"); nr_ue_measurement_procedures(2,ue,proc,eNB_id,nr_tti_rx,mode); @@ -4344,7 +4188,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, write_output("rxF_comp.m","rxFc",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp0[0][0],fp->N_RB_DL*12*14,1,1); write_output("rxF_llr.m","rxFllr",ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr[0],(nb_symb_sch-1)*50*12+50*6,1,0); */ - + //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_OUT); } @@ -4352,11 +4196,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if ((ue->dlsch_SI[eNB_id]) && (ue->dlsch_SI[eNB_id]->active == 1)) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_SI, VCD_FUNCTION_IN); nr_ue_pdsch_procedures(ue, - proc, - eNB_id, - SI_PDSCH, - ue->dlsch_SI[eNB_id], - NULL); + proc, + eNB_id, + SI_PDSCH, + ue->dlsch_SI[eNB_id], + NULL); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_SI, VCD_FUNCTION_OUT); } @@ -4365,11 +4209,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if ((ue->dlsch_p[eNB_id]) && (ue->dlsch_p[eNB_id]->active == 1)) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_P, VCD_FUNCTION_IN); nr_ue_pdsch_procedures(ue, - proc, - eNB_id, - P_PDSCH, - ue->dlsch_p[eNB_id], - NULL); + proc, + eNB_id, + P_PDSCH, + ue->dlsch_p[eNB_id], + NULL); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_P, VCD_FUNCTION_OUT); } @@ -4378,18 +4222,42 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if ((ue->dlsch_ra[eNB_id]) && (ue->dlsch_ra[eNB_id]->active == 1)) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_IN); nr_ue_pdsch_procedures(ue, - proc, - eNB_id, - RA_PDSCH, - ue->dlsch_ra[eNB_id], - NULL); + proc, + eNB_id, + RA_PDSCH, + ue->dlsch_ra[eNB_id], + NULL); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_OUT); + // #if UE_TIMING_TRACE + // start_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[nr_tti_rx]]); + // #endif + + nr_ue_dlsch_procedures(ue, + proc, + eNB_id, + RA_PDSCH, + ue->dlsch_ra[eNB_id], + NULL, + &ue->dlsch_ra_errors[eNB_id], + mode); + + // #if UE_TIMING_TRACE + // stop_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[nr_tti_rx]]); + #if DISABLE_LOG_X + printf("[SFN %d] Slot1: Pdsch Proc %5.2f\n", nr_tti_rx, ue->pdsch_procedures_stat[ue->current_thread_id[nr_tti_rx]].p_time/(cpuf*1000.0)); + printf("[SFN %d] Slot0 Slot1: Dlsch Proc %5.2f\n", nr_tti_rx, ue->dlsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0)); + #else + LOG_D(PHY, "[SFN %d] Slot1: Pdsch Proc %5.2f\n", nr_tti_rx, ue->pdsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0)); + LOG_D(PHY, "[SFN %d] Slot0 Slot1: Dlsch Proc %5.2f\n", nr_tti_rx, ue->dlsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0)); + #endif + // #endif + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_OUT); } // do procedures for C-RNTI if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1) { - + LOG_D(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_IN); @@ -4419,6 +4287,9 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, #endif + // deactivate dlsch once dlsch proc is done + ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 0; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_OUT); } @@ -4624,3 +4495,119 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, return(0); } +// WIP +// todo: +// - set tx_total_RE +// - power control as per 38.213 ch 7.4 +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) { + + int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; // tx_amp + uint16_t /*preamble_tx = 50,*/ pathloss; + uint8_t mod_id = ue->Mod_id; + UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); + NR_PRACH_RESOURCES_t * prach_resources = ue->prach_resources[gNB_id]; + uint8_t nr_prach = 0; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); + + if (ue->mac_enabled == 0){ + // prach_resources->ra_PreambleIndex = preamble_tx; + prach_resources->ra_TDD_map_index = 0; + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; + prach_resources->ra_RNTI = 0x1234; + nr_prach = 1; + } else { + // ask L2 for RACH transport + if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { + LOG_D(PHY, "Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); + // flush Msg3 Buffer + if (prach_resources->Msg3 == NULL){ + for(int i = 0; iulsch_Msg3_active[i] = 0; + } + } + nr_prach = nr_ue_get_rach(ue->prach_resources[gNB_id], mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); + } + } + + if (!prach_resources->init_msg1 && (frame_tx > ue->prach_resources[gNB_id]->sync_frame + 150)){ + ue->prach_cnt = 0; + prach_resources->init_msg1 = 1; + } + + if (ue->prach_resources[gNB_id] != NULL && nr_prach == 1 && prach_resources->init_msg1) { + + pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id); + LOG_D(PHY,"runmode %d\n",runmode); + + if ((ue->mac_enabled == 1) && (runmode != calib_prach_tx)) { + ue->tx_power_dBm[nr_tti_tx] = prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss; + } + + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %x\n", + ue->Mod_id, + frame_tx, + nr_tti_tx, + prach_resources->ra_PreambleIndex, + pathloss, + ue->tx_power_dBm[nr_tti_tx], + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER, + prach_resources->ra_RNTI); + + //ue->tx_total_RE[nr_tti_tx] = 96; // todo + ue->prach_vars[gNB_id]->amp = AMP; + + /* #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) + tx_amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], ue->tx_power_max_dBm, ue->frame_parms.N_RB_UL); + if (tx_amp != -1) + ue->prach_vars[gNB_id]->amp = tx_amp; + #else + ue->prach_vars[gNB_id]->amp = AMP; + #endif */ + + if ((runmode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : PRACH TX power %d dBm, amp %d\n", ue->Mod_id, + proc->frame_rx, + proc->nr_tti_tx, + ue->tx_power_dBm[nr_tti_tx], + ue->prach_vars[gNB_id]->amp); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); + + prach_power = generate_nr_prach(ue, gNB_id, nr_tti_tx); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); + + LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", + ue->Mod_id, + pathloss, + ue->tx_power_dBm[nr_tti_tx], + dB_fixed(prach_power), + ue->prach_vars[gNB_id]->amp); + + if (ue->mac_enabled == 1) + nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id); + + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d: Generated PRACH Msg1 (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n", + ue->Mod_id, + frame_tx, + nr_tti_tx, + gNB_id, + prach_resources->ra_PreambleIndex, + ue->tx_power_dBm[nr_tti_tx], + pathloss); + + LOG_D(PHY,"[UE %d] frame %d nr_tti_tx %d : prach_cnt %d\n", ue->Mod_id, frame_tx, nr_tti_tx, ue->prach_cnt); + + ue->prach_cnt++; + + if (ue->prach_cnt == 3) + ue->prach_cnt = 0; + } + + // if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue + if (runmode == calib_prach_tx) + ue->prach_resources[gNB_id] = NULL; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); +} diff --git a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c index 9632291e67..b51c8afbb0 100644 --- a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c @@ -104,7 +104,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, int P_O_PUCCH = P_O_NOMINAL_PUCCH + P_O_UE_PUCCH; - int16_t PL = get_nr_PL(ue, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */ + int16_t PL = get_nr_PL(ue->Mod_id, ue->CC_id, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */ int16_t delta_F_PUCCH = power_config->deltaF_PUCCH_f[pucch_format]; diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 1b62ff81bf..ccbe502194 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -37,7 +37,6 @@ #include "PHY/defs_nr_UE.h" #include #include -#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" #ifndef NO_RAT_NR @@ -162,6 +161,8 @@ void nr_generate_pucch3_4(int32_t **txdataF, * *********************************************************************/ +static int bwp_id = 1; + bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t *proc, bool reset_harq) { uint8_t sr_payload = 0; @@ -186,12 +187,18 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ int pucch_resource_id = MAX_NB_OF_PUCCH_RESOURCES; int pucch_resource_indicator = MAX_PUCCH_RESOURCE_INDICATOR; int n_HARQ_ACK; + uint16_t crnti=0x1234; int dmrs_scrambling_id=0,data_scrambling_id=0; + + NR_UE_MAC_INST_t *mac = get_mac_inst(0); + NR_PUCCH_Resource_t *pucch_resource; + //NR_UE_MAC_INST_t *mac = get_mac_inst(0); + /* update current context */ - int subframe_number = (proc->nr_tti_rx)/(ue->frame_parms.ttis_per_subframe); + int subframe_number = (proc->nr_tti_rx)/(ue->frame_parms.slots_per_subframe);//ttis_per_subframe); nb_pucch_format_4_in_subframes[subframe_number] = 0; /* reset pucch format 4 counter at current rx position */ int dl_harq_pid = ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid; @@ -214,11 +221,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /* sr_payload = 1 means that this is a positive SR, sr_payload = 0 means that it is a negative SR */ sr_payload = nr_ue_get_SR(Mod_id, - CC_id, - frame_tx, - gNB_id, - 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, - nr_tti_tx); // nr_tti_rx used for meas gap + CC_id, + frame_tx, + gNB_id, + 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + nr_tti_tx); // nr_tti_rx used for meas gap } else { sr_payload = 1; @@ -250,10 +257,10 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } else { /* a resource set and a resource should be find according to payload size */ - pucch_resource_set = find_pucch_resource_set( ue, gNB_id, N_UCI); + pucch_resource_set = find_pucch_resource_set( mac, gNB_id, N_UCI); if (pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) { pucch_resource_indicator = 0; - pucch_resource_id = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set]->pucch_resource_id[pucch_resource_indicator]; /* get the first resource of the set */ + pucch_resource_id = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set]->resourceList.list.array[pucch_resource_indicator][0]; /* get the first resource of the set */ } else { LOG_W(PHY,"PUCCH no resource set found for CSI at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); @@ -299,7 +306,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid]->harq_ack; - if (select_pucch_resource(ue, gNB_id, N_UCI, pucch_resource_indicator, &initial_pucch_id, &pucch_resource_set, + if (select_pucch_resource(ue, mac, gNB_id, N_UCI, pucch_resource_indicator, &initial_pucch_id, &pucch_resource_set, &pucch_resource_id, harq_status) == TRUE) { /* use of initial pucch configuration provided by system information 1 */ /***********************************************************************/ @@ -340,33 +347,43 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /**********************************************/ else if ((pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) && (pucch_resource_id != MAX_NB_OF_PUCCH_RESOURCES)) { /* check that current configuration is supported */ - if ((ue->cell_group_config.physicalCellGroupConfig.harq_ACK_SpatialBundlingPUCCH != FALSE) - || (ue->cell_group_config.physicalCellGroupConfig.pdsch_HARQ_ACK_Codebook != dynamic)) { + if ((mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH != NULL) + || (mac->scg->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook != 1)) { LOG_E(PHY,"PUCCH Unsupported cell group configuration : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); return(FALSE); } - else if (ue->PDSCH_ServingCellConfig.codeBlockGroupTransmission != NULL) { + else if (mac->scg->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { LOG_E(PHY,"PUCCH Unsupported code block group for serving cell config : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); return(FALSE); } - format = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.format; - nb_symbols_total = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols; - starting_symbol_index = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex; - starting_prb = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->startingPRB; + pucch_resource = select_resource_by_id(pucch_resource_id, mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup); + format = pucch_resource->format.present; + nb_symbols_total = get_nb_symbols_pucch(pucch_resource, format); + starting_symbol_index = get_starting_symb_idx(pucch_resource, format); + starting_prb = pucch_resource->startingPRB; second_hop = starting_prb; - time_domain_occ = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC; /* format 1 only */ - occ_length = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length; /* format 4 only */ - occ_Index = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index; /* format 4 only */ - - if ((format == pucch_format0_nr) || (format == pucch_format1_nr)) { - m_0 = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift; + if (format==pucch_format1_nr) + time_domain_occ = pucch_resource->format.choice.format1->timeDomainOCC; + if (format==pucch_format4_nr) { + occ_length = pucch_resource->format.choice.format4->occ_Length; + occ_Index = pucch_resource->format.choice.format4->occ_Index; } - else if ((format == pucch_format3_nr) || (format == pucch_format4_nr)) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->additionalDMRS == enable_feature) { + + m_0 = get_ics_pucch(pucch_resource, format); + AssertFatal(m_0 >= 0, "Invalid m_0\n"); + if (format == pucch_format3_nr) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->additionalDMRS[0] == 1) { index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS; } + } + else if (format == pucch_format4_nr) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4->choice.setup->additionalDMRS[0] == 1) { + index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS; + } + } - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping == feature_enabled) { + if ((format == pucch_format3_nr) || (format == pucch_format4_nr)) { + if (pucch_resource->intraSlotFrequencyHopping[0] == 1) { index_hopping = I_PUCCH_HOPING; } } @@ -385,6 +402,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ int O_CRC = 0; nb_symbols = nb_symbols_total; /* by default, it can be reduced due to symbols reserved for dmrs */ + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[pucch_resource_id]; switch(format) { case pucch_format0_nr: @@ -401,14 +419,14 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } case pucch_format2_nr: { - nb_of_prbs = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs; + nb_of_prbs = pucch_resource->format.choice.format2->nrofPRBs; N_sc_ctrl_RB = N_SC_RB - 4; break; } case pucch_format3_nr: { - nb_of_prbs = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs; - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->pi2PBSK == feature_enabled) { + nb_of_prbs = pucch_resource->format.choice.format3->nrofPRBs; + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->pi2BPSK[0] == 1) { Q_m = BITS_PER_SYMBOL_BPSK; /* set bpsk modulation type with 1 bit per modulation symbol */ } N_sc_ctrl_RB = N_SC_RB; @@ -417,12 +435,12 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } case pucch_format4_nr: { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->pi2PBSK == feature_enabled) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4->choice.setup->pi2BPSK[0] == 1) { Q_m = BITS_PER_SYMBOL_BPSK; /* set bpsk modulation type with 1 bit per modulation symbol */ } nb_symbols = nb_symbols_excluding_dmrs[nb_symbols_total-4][index_additional_dmrs][index_hopping]; nb_of_prbs = 1; - subframe_number = nr_tti_tx/(ue->frame_parms.ttis_per_subframe); + subframe_number = nr_tti_tx/(ue->frame_parms.slots_per_subframe);//ttis_per_subframe); nb_pucch_format_4_in_subframes[subframe_number]++; /* increment number of transmit pucch 4 in current subframe */ NR_TST_PHY_PRINTF("PUCCH Number of pucch format 4 in subframe %d is %d \n", subframe_number, nb_pucch_format_4_in_subframes[subframe_number]); N_sc_ctrl_RB = N_SC_RB/(nb_pucch_format_4_in_subframes[subframe_number]); @@ -434,10 +452,10 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /* drop CSI report if simultaneous HARQ-ACK/SR and periodic/semi-periodic CSI cannot be transmitted at the same time */ if (format != pucch_format0_nr) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1] != NULL) { - max_code_rate = code_rate_r_time_100[ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->maxCodeRate]; /* it is code rate * 10 */ + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) { + max_code_rate = code_rate_r_time_100[mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->maxCodeRate[0]]; /* it is code rate * 10 */ - if ((O_ACK != 0) && (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->simultaneousHARQ_ACK_CSI == disable_feature)) { + if ((O_ACK != 0) && (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->simultaneousHARQ_ACK_CSI[0] == 0)) { N_UCI = N_UCI - O_CSI; O_CSI = cqi_status = ri_status = 0; csi_payload = 0; /* csi should be dropped in this case */ @@ -563,7 +581,8 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ { nr_generate_pucch0(ue,ue->common_vars.txdataF, &ue->frame_parms, - &ue->pucch_config_dedicated[gNB_id], + mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping, + mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId[0], tx_amp, nr_tti_tx, (uint8_t)m_0, @@ -679,8 +698,11 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t int U_DAI_c = 0; int N_m_c_rx = 0; int V_DAI_m_DL = 0; + NR_UE_MAC_INST_t *mac = get_mac_inst(0); - if (ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI == nb_code_n2) { + if (mac->DLbwp[0] == NULL) return 0; + + if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0] == 2) { two_transport_blocks = TRUE; number_of_code_word = 2; } @@ -698,46 +720,49 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t for (int dl_harq_pid = 0; dl_harq_pid < number_pid_dl; dl_harq_pid++) { - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid]->harq_ack; + for (int thread_idx = 0; thread_idx < RX_NB_TH; thread_idx++) { - /* check if current tx slot should transmit downlink acknowlegment */ - if (harq_status->slot_for_feedback_ack == proc->nr_tti_tx) { + harq_status = &ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]->harq_ack; - if (harq_status->ack == DL_ACKNACK_NO_SET) { - LOG_E(PHY,"PUCCH Downlink acknowledgment has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (0); - } - else if (harq_status->vDAI_DL == DL_DAI_NO_SET) { - LOG_E(PHY,"PUCCH Downlink DAI has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (0); - } - else if (harq_status->vDAI_DL > NR_DL_MAX_DAI) { - LOG_E(PHY,"PUCCH Downlink DAI has an invalid value : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (0); - } - else if (harq_status->send_harq_status == 0) { - LOG_E(PHY,"PUCCH Downlink ack can not be transmitted : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return(0); - } - else { + /* check if current tx slot should transmit downlink acknowlegment */ + if (harq_status->slot_for_feedback_ack == proc->nr_tti_tx) { - dai_current = harq_status->vDAI_DL; - - if (dai_current == 0) { - LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return(0); - } else if (dai_current > dai_max) { - dai_max = dai_current; + if (harq_status->ack == DL_ACKNACK_NO_SET) { + LOG_E(PHY,"PUCCH Downlink acknowledgment has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (0); } + else if (harq_status->vDAI_DL == DL_DAI_NO_SET) { + LOG_E(PHY,"PUCCH Downlink DAI has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (0); + } + else if (harq_status->vDAI_DL > NR_DL_MAX_DAI) { + LOG_E(PHY,"PUCCH Downlink DAI has an invalid value : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (0); + } + else if (harq_status->send_harq_status == 0) { + LOG_E(PHY,"PUCCH Downlink ack can not be transmitted : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return(0); + } + else { - number_harq_feedback++; - ack_data[code_word][dai_current - 1] = harq_status->ack; - dai[code_word][dai_current - 1] = dai_current; + dai_current = harq_status->vDAI_DL+1; // DCI DAI to counter DAI conversion + + if (dai_current == 0) { + LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return(0); + } else if (dai_current > dai_max) { + dai_max = dai_current; + } + + number_harq_feedback++; + ack_data[code_word][dai_current - 1] = harq_status->ack; + dai[code_word][dai_current - 1] = dai_current; + } + if (do_reset == TRUE) { + init_downlink_harq_status(ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]); + } } } - if (do_reset == TRUE) { - init_downlink_harq_status(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid]); - } } } @@ -756,8 +781,8 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t U_DAI_c = number_harq_feedback/number_of_code_word; N_m_c_rx = number_harq_feedback; int N_SPS_c = 0; /* FFS TODO_NR multicells and SPS are not supported at the moment */ - if (ue->cell_group_config.physicalCellGroupConfig.harq_ACK_SpatialBundlingPUCCH == FALSE) { - int N_TB_max_DL = ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI; + if (mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH == NULL) { + int N_TB_max_DL = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0]; *n_HARQ_ACK = (((V_DAI_m_DL - U_DAI_c)%4) * N_TB_max_DL) + N_m_c_rx + N_SPS_c; NR_TST_PHY_PRINTF("PUCCH power n(%d) = ( V(%d) - U(%d) )mod4 * N_TB(%d) + N(%d) \n", *n_HARQ_ACK, V_DAI_m_DL, U_DAI_c, N_TB_max_DL, N_m_c_rx); } @@ -853,7 +878,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t * *********************************************************************/ -boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, +boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, int *initial_pucch_id, int *resource_set_id, int *resource_id, NR_UE_HARQ_STATUS_t *harq_status) { boolean_t resource_set_found = FALSE; @@ -861,18 +886,19 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size int current_resource_id = MAX_NB_OF_PUCCH_RESOURCES; pucch_format_nr_t format_pucch; int ready_pucch_resource_id = FALSE; /* in the case that it is already given */ + NR_PUCCH_Resource_t *pucch_resource; /* ini values to unset */ *initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE; //*resource_set_id = MAX_NB_OF_PUCCH_RESOURCE_SETS; //*resource_id = MAX_NB_OF_PUCCH_RESOURCES; - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[0] == NULL) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[0] == NULL) { /* No resource set has been already configured so pucch_configCommon from Sib1 should be used in this case */ if (ue->UE_mode[gNB_id] != PUSCH) { - *initial_pucch_id = ue->pucch_config_common_nr[gNB_id].pucch_ResourceCommon; + *initial_pucch_id = mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon[0]; if (*initial_pucch_id >= NB_INITIAL_PUCCH_RESOURCE) { LOG_E(PHY,"PUCCH Invalid initial resource index : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); *initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE; @@ -897,7 +923,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size } nb_symbols_for_tx = initial_pucch_resource[*initial_pucch_id].nrofSymbols; format_pucch = initial_pucch_resource[*initial_pucch_id].format; - if (check_pucch_format(ue, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { + if (check_pucch_format(mac, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { return (TRUE); } else { @@ -917,7 +943,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size -- This field can take integer values that are multiples of 4. Corresponds to L1 parameter 'N_2' or 'N_3' (see 38.213, section 9.2) */ /* look for the first resource set which supports uci_size number of bits for payload */ - pucch_resource_set_id = find_pucch_resource_set( ue, gNB_id, uci_size); + pucch_resource_set_id = find_pucch_resource_set(mac, gNB_id, uci_size); if (pucch_resource_set_id != MAX_NB_OF_PUCCH_RESOURCE_SETS) { resource_set_found = TRUE; } @@ -932,13 +958,13 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size if (resource_set_found == TRUE) { if (pucch_resource_indicator < MAX_PUCCH_RESOURCE_INDICATOR) { /* check if resource indexing by pucch_resource_indicator of this set is compatible */ - if ((ready_pucch_resource_id == TRUE) || (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->pucch_resource_id[pucch_resource_indicator] != MAX_NB_OF_PUCCH_RESOURCES)) { + if ((ready_pucch_resource_id == TRUE) || (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.array[pucch_resource_indicator][0] != MAX_NB_OF_PUCCH_RESOURCES)) { if (ready_pucch_resource_id == TRUE) { current_resource_id = *resource_id; } else { - int R_PUCCH = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->first_resources_set_R_PUCCH; + int R_PUCCH = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.count; /* is it the first resource and its size exceeds 8 */ if ((pucch_resource_set_id == 0) && (R_PUCCH > MAX_NB_OF_PUCCH_RESOURCES_PER_SET_NOT_0)) { @@ -960,15 +986,22 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size current_resource_id = r_PUCCH; } else { - current_resource_id = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->pucch_resource_id[pucch_resource_indicator]; + current_resource_id = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.array[pucch_resource_indicator][0]; } } - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id] != NULL) { - nb_symbols_for_tx = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id]->format_parameters.nrofSymbols; - format_pucch = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id]->format_parameters.format; + /*uint8_t pucch_resource_count = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.count; + for (uint8_t i=0; iULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.array[i]->pucch_ResourceId == current_resource_id) + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.array[i]; + }*/ - if (check_pucch_format(ue, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[current_resource_id]; + if (pucch_resource != NULL) { + format_pucch = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[current_resource_id]->format.present; + nb_symbols_for_tx = get_nb_symbols_pucch(pucch_resource, format_pucch); + + if (check_pucch_format(mac, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { *resource_set_id = pucch_resource_set_id; *resource_id = current_resource_id; return (TRUE); @@ -1014,9 +1047,10 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size * *********************************************************************/ -int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size) +int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size) { int pucch_resource_set_id = 0; + long *pucch_max_pl_bits = NULL; /* from TS 38.331 field maxPayloadMinus1 -- Maximum number of payload bits minus 1 that the UE may transmit using this PUCCH resource set. In a PUCCH occurrence, the UE @@ -1027,8 +1061,9 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size) */ /* look for the first resource set which supports uci_size number of bits for payload */ while (pucch_resource_set_id < MAX_NB_OF_PUCCH_RESOURCE_SETS) { - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id] != NULL) { - if (uci_size <= ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->maxPayloadMinus1 + 1) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id] != NULL) { + pucch_max_pl_bits = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1; + if (uci_size <= (((pucch_max_pl_bits != NULL) ? *pucch_max_pl_bits : 1706) + 1)) { NR_TST_PHY_PRINTF("PUCCH found resource set %d \n", pucch_resource_set_id); return (pucch_resource_set_id); break; @@ -1057,18 +1092,40 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size) * *********************************************************************/ -boolean_t check_pucch_format(PHY_VARS_NR_UE *ue, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size) +boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size) { pucch_format_nr_t selected_pucch_format; pucch_format_nr_t selected_pucch_format_second; + NR_SetupRelease_PUCCH_FormatConfig_t *identified_format = NULL; - if (format_pucch != pucch_format0_nr) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format_pucch-1] != NULL) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format_pucch-1]->nrofSlots != 1) { - LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (FALSE); - } - } + switch (format_pucch) { + case pucch_format1_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1; + break; + + case pucch_format2_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2; + break; + + case pucch_format3_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3; + break; + + case pucch_format4_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4; + break; + + default: + break; + } + + if ((identified_format != NULL) && (identified_format->choice.setup->nrofSlots[0] != 1)) { + LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (FALSE); } if (nb_symbols_for_tx <= 2) { @@ -1160,7 +1217,7 @@ int trigger_periodic_scheduling_request(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_n return (1); /* period is slot */ } - int16_t N_slot_frame = NR_NUMBER_OF_SUBFRAMES_PER_FRAME * ue->frame_parms.ttis_per_subframe; + int16_t N_slot_frame = NR_NUMBER_OF_SUBFRAMES_PER_FRAME * ue->frame_parms.slots_per_subframe;//ttis_per_subframe; if (((proc->frame_tx * N_slot_frame) + proc->nr_tti_tx - SR_offset)%SR_periodicity == 0) { return (1); } @@ -1219,4 +1276,74 @@ void set_csi_nr(int csi_status, uint32_t csi_payload) } } +uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) +{ + switch (format_type) { + case pucch_format0_nr: + return pucch_resource->format.choice.format0->nrofSymbols; + + case pucch_format1_nr: + return pucch_resource->format.choice.format1->nrofSymbols; + + case pucch_format2_nr: + return pucch_resource->format.choice.format2->nrofSymbols; + + case pucch_format3_nr: + return pucch_resource->format.choice.format3->nrofSymbols; + + case pucch_format4_nr: + return pucch_resource->format.choice.format4->nrofSymbols; + } + return 0; +} + +uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) +{ + switch (format_type) { + case pucch_format0_nr: + return pucch_resource->format.choice.format0->startingSymbolIndex; + + case pucch_format1_nr: + return pucch_resource->format.choice.format1->startingSymbolIndex; + + case pucch_format2_nr: + return pucch_resource->format.choice.format2->startingSymbolIndex; + + case pucch_format3_nr: + return pucch_resource->format.choice.format3->startingSymbolIndex; + + case pucch_format4_nr: + return pucch_resource->format.choice.format4->startingSymbolIndex; + } + return 0; +} + +int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) +{ + switch (format_type) { + case pucch_format0_nr: + return pucch_resource->format.choice.format0->initialCyclicShift; + + case pucch_format1_nr: + return pucch_resource->format.choice.format1->initialCyclicShift; + + default: + return -1; + } + return -1; +} + +NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config) +{ + int n_list = pucch_config->resourceToAddModList->list.count; + NR_PUCCH_Resource_t *pucchres; + AssertFatal(n_list>0,"PUCCH resourceToAddModList is empty\n"); + + for (int i=0; iresourceToAddModList->list.array[i]; + if (pucchres->pucch_ResourceId == resource_id) + return pucchres; + } + return NULL; +} diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h index 85cd969e26..089fae9f55 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h @@ -41,6 +41,9 @@ /************** INCLUDE *******************************************/ #include "PHY/defs_nr_UE.h" +#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" +#include "openair2/LAYER2/NR_MAC_UE/mac_defs.h" +#include "RRC/NR_UE/rrc_proto.h" #ifdef DEFINE_VARIABLES_PUCCH_UE_NR_H #define EXTERN @@ -187,7 +190,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t @param resource_id pucch resource id if any @returns TRUE a pucch resource has been found FALSE no valid pucch resource */ -boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, +boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, int *initial_pucch_id, int *resource_set_id, int *resource_id, NR_UE_HARQ_STATUS_t *harq_status); /** \brief This function select a pucch resource set @@ -196,7 +199,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size @param uci size number of uci bits @returns number of the pucch resource set */ -int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size); +int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size); /** \brief This function check pucch format @param ue context @@ -206,7 +209,7 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size); @param uci size number of uci bits @returns TRUE pucch format matched uci size and constraints, FALSE invalid pucch format */ -boolean_t check_pucch_format(PHY_VARS_NR_UE *ue, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, +boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size); /** \brief This function selects a pucch resource @@ -232,4 +235,11 @@ int get_csi_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint32_t *csi_payload); void set_csi_nr(int csi_status, uint32_t csi_payload); +uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); + +uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); + +int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); + +NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config); #endif /* PUCCH_UCI_UE_NR_H */ diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index 80b26c0bbd..9374050e58 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -40,7 +40,7 @@ #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "SCHED_NR/sched_nr.h" #include "openair1/SIMULATION/TOOLS/sim.h" @@ -66,6 +66,8 @@ PHY_VARS_NR_UE *PHY_vars_UE_g[1][1] = { { NULL } }; uint16_t n_rnti = 0x1234; openair0_config_t openair0_cfg[MAX_CARDS]; +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + int main(int argc, char **argv) { char c; @@ -428,7 +430,7 @@ int main(int argc, char **argv) uint8_t is_crnti = 0, llr8_flag = 0; unsigned int TBS = 8424; unsigned int available_bits; - uint8_t nb_re_dmrs = 6; + uint8_t nb_re_dmrs = 6; // No data in dmrs symbol uint16_t length_dmrs = 1; unsigned char mod_order; uint16_t rate; @@ -442,7 +444,7 @@ int main(int argc, char **argv) mod_order = nr_get_Qm_dl(Imcs, mcs_table); rate = nr_get_code_rate_dl(Imcs, mcs_table); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); - TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl); + TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl); printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order); //dlsch->harq_ids[subframe]= 0; rel15->rbSize = nb_rb; @@ -455,6 +457,7 @@ int main(int argc, char **argv) rel15->dmrsConfigType = NFAPI_NR_DMRS_TYPE1; rel15->dlDmrsSymbPos = 4; rel15->mcsIndex[0] = Imcs; + rel15->numDmrsCdmGrpsNoData = 1; double *modulated_input = malloc16(sizeof(double) * 16 * 68 * 384); // [hna] 16 segments, 68*Zc short *channel_output_fixed = malloc16(sizeof(short) * 16 * 68 * 384); short *channel_output_uncoded = malloc16(sizeof(unsigned short) * 16 * 68 * 384); diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 0b51901b05..137c358d7f 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -28,11 +28,9 @@ #include "common/ran_context.h" #include "common/config/config_userapi.h" #include "common/utils/LOG/log.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" -#include "openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_defs.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_extern.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" +#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" +#include "LAYER2/NR_MAC_UE/mac_defs.h" +#include "LAYER2/NR_MAC_UE/mac_extern.h" #include "PHY/defs_gNB.h" #include "PHY/defs_nr_common.h" #include "PHY/defs_nr_UE.h" @@ -43,7 +41,7 @@ #include "PHY/MODULATION/modulation_UE.h" #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "SCHED_NR/fapi_nr_l1.h" #include "SCHED_NR/sched_nr.h" @@ -55,7 +53,7 @@ #include "LAYER2/NR_MAC_UE/mac_proto.h" //#include "LAYER2/NR_MAC_gNB/mac_proto.h" //#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "NR_asn_constant.h" #include "RRC/NR/MESSAGES/asn1_msg.h" #include "openair1/SIMULATION/RF/rf.h" @@ -139,6 +137,12 @@ int main(int argc, char **argv) int i,aa;//,l; double sigma2, sigma2_dB=10, SNR, snr0=-2.0, snr1=2.0; uint8_t snr1set=0; + float roundStats[50]; + float effRate; + //float psnr; + float eff_tp_check = 0.7; + uint8_t snrRun; + uint32_t TBS; int **txdata; double **s_re,**s_im,**r_re,**r_im; //double iqim = 0.0; @@ -154,6 +158,8 @@ int main(int argc, char **argv) int trial, n_trials = 1, n_errors = 0, n_false_positive = 0; //int n_errors2, n_alamouti; uint8_t transmission_mode = 1,n_tx=1,n_rx=1; + uint8_t round; + uint8_t num_rounds = 4; channel_desc_t *gNB2UE; //uint32_t nsymb,tx_lev,tx_lev1 = 0,tx_lev2 = 0; @@ -205,7 +211,7 @@ int main(int argc, char **argv) FILE *scg_fd=NULL; - while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:")) != -1) { + while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:w")) != -1) { switch (c) { case 'f': scg_fd = fopen(optarg,"r"); @@ -384,6 +390,14 @@ int main(int argc, char **argv) mu = atoi(optarg); break; + case 't': + eff_tp_check = (float)atoi(optarg)/100; + break; + + case 'w': + output_fd = fopen("txdata.dat", "w+"); + break; + default: case 'h': printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", @@ -413,7 +427,9 @@ int main(int argc, char **argv) printf("-c Start symbol for PDSCH (fixed for now)\n"); printf("-j Number of symbols for PDSCH (fixed for now)\n"); printf("-e MSC index\n"); + printf("-t Acceptable effective throughput (in percentage)\n"); printf("-P Print DLSCH performances\n"); + printf("-w Write txdata to binary file (one frame)\n"); exit (-1); break; } @@ -658,7 +674,7 @@ int main(int argc, char **argv) rrc.carrier.MIB = (uint8_t*) malloc(4); rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0); - nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig); + nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup); nr_dcireq_t dcireq; @@ -679,6 +695,9 @@ int main(int argc, char **argv) nr_ue_phy_config_request(&UE_mac->phy_config); + NR_UE_list_t *UE_list = &RC.nrmac[0]->UE_list; + //NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels; + snrRun = 0; for (SNR = snr0; SNR < snr1; SNR += .2) { @@ -696,6 +715,7 @@ int main(int argc, char **argv) reset_meas(&gNB->toutput); n_errors = 0; + effRate = 0; //n_errors2 = 0; //n_alamouti = 0; errors_scrambling=0; @@ -706,94 +726,6 @@ int main(int argc, char **argv) //multipath channel //multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0); - memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); - clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); - if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); - else nr_schedule_css_dlsch_phytest(0,frame,slot); - - - Sched_INFO.module_id = 0; - Sched_INFO.CC_id = 0; - Sched_INFO.frame = frame; - Sched_INFO.slot = slot; - Sched_INFO.DL_req = &gNB_mac->DL_req[0]; - Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0]; - Sched_INFO.UL_dci_req = NULL; - Sched_INFO.TX_req = &gNB_mac->TX_req[0]; - nr_schedule_response(&Sched_INFO); - - if (run_initial_sync) - nr_common_signal_procedures(gNB,frame,slot); - else - phy_procedures_gNB_TX(gNB,frame,slot,0); - - int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP; - - if (n_trials==1) { - LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1); - if (gNB->frame_parms.nb_antennas_tx>1) - LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1); - } - int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); - if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP); - - //TODO: loop over slots - for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { - - if (cyclic_prefix_type == 1) { - PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], - &txdata[aa][tx_offset], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); - } else { - nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], - &txdata[aa][tx_offset], - 14, - frame_parms); - } - } - - if (n_trials==1) { - LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1); - if (gNB->frame_parms.nb_antennas_tx>1) - LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); - } - if (output_fd) - fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); - - int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], - frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - - // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev)); - - for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)); - i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0)); - i++) { - for (aa=0; aanb_antennas_tx; aa++) { - r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]); - r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]); - } - } - - NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; - nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15; - - //AWGN - sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize))) - SNR; - sigma2 = pow(10, sigma2_dB/10); - if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize)); - - for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); - iget_samples_slot_timestamp(slot+1,frame_parms,0); - i++) { - for (aa=0; aanb_antennas_rx; aa++) { - ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - } - } - UE->rx_offset=0; UE_proc.frame_rx = frame; UE_proc.nr_tti_rx= slot; @@ -801,43 +733,147 @@ int main(int argc, char **argv) dcireq.frame = frame; dcireq.slot = slot; + + NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; + + int harq_pid = slot; + NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; + + NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_processes[slot]->pdsch_pdu.pdsch_pdu_rel15; - nr_ue_dcireq(&dcireq); //to be replaced with function pointer later - nr_ue_scheduled_response(&scheduled_response); + UE_harq_process->harq_ack.ack = 0; + round = 0; + UE_harq_process->round = round; + UE_harq_process->first_tx = 1; + + while ((roundharq_ack.ack==0)) { + memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); + clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); + + UE_list->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1); + + UE_list->UE_sched_ctrl[0].harq_processes[harq_pid].round = round; + UE_list->UE_sched_ctrl[0].current_harq_pid = harq_pid; + gNB->dlsch[0][0]->harq_processes[harq_pid]->round = round; - phy_procedures_nrUE_RX(UE, - &UE_proc, - 0, - do_pdcch_flag, - normal_txrx); - - if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= - UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) - n_errors++; + if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); + else nr_schedule_css_dlsch_phytest(0,frame,slot); + Sched_INFO.module_id = 0; + Sched_INFO.CC_id = 0; + Sched_INFO.frame = frame; + Sched_INFO.slot = slot; + Sched_INFO.DL_req = &gNB_mac->DL_req[0]; + Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0]; + Sched_INFO.UL_dci_req = NULL; + Sched_INFO.TX_req = &gNB_mac->TX_req[0]; + nr_schedule_response(&Sched_INFO); + + if (run_initial_sync) + nr_common_signal_procedures(gNB,frame,slot); + else + phy_procedures_gNB_TX(gNB,frame,slot,0); + + int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP; + + if (n_trials==1) { + LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1); + if (gNB->frame_parms.nb_antennas_tx>1) + LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1); + } + int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP); + + //TODO: loop over slots + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { + + if (cyclic_prefix_type == 1) { + PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], + &txdata[aa][tx_offset], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); + } else { + nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], + &txdata[aa][tx_offset], + 14, + frame_parms); + } + } + + if (n_trials==1) { + LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1); + if (gNB->frame_parms.nb_antennas_tx>1) + LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); + } + if (output_fd) { + printf("writing txdata to binary file\n"); + fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); + } + + int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); + + // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev)); + + for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)); + i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0)); + i++) { + + for (aa=0; aanb_antennas_tx; aa++) { + r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]); + r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]); + } + } + + //AWGN + sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize))) - SNR; + sigma2 = pow(10, sigma2_dB/10); + if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize)); + + for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + iget_samples_slot_timestamp(slot+1,frame_parms,0); + i++) { + + for (aa=0; aanb_antennas_rx; aa++) { + ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + } + } + + nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + nr_ue_scheduled_response(&scheduled_response); + + phy_procedures_nrUE_RX(UE, + &UE_proc, + 0, + do_pdcch_flag, + normal_txrx); + + //printf("dlsim round %d ends\n",round); + round++; + } // round //---------------------------------------------------------- //---------------------- count errors ---------------------- //---------------------------------------------------------- - - - NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; - - int harq_pid = dlsch0->current_harq_pid; - NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; - + if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= + UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) + n_errors++; + NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; int16_t *UE_llr = pdsch_vars[0]->llr[0]; - - uint32_t TBS = rel15.TBSize[0]; + TBS = UE_harq_process->TBS;//rel15->TBSize[0]; uint16_t length_dmrs = 1; - uint16_t nb_rb = rel15.rbSize; - uint8_t nb_re_dmrs = rel15.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; - uint8_t mod_order = rel15.qamModOrder[0]; - uint8_t nb_symb_sch = rel15.NrOfSymbols; + uint16_t nb_rb = rel15->rbSize; + uint8_t nb_re_dmrs = rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; + uint8_t mod_order = rel15->qamModOrder[0]; + uint8_t nb_symb_sch = rel15->NrOfSymbols; - available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers); + available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15->nrOfLayers); for (i = 0; i < available_bits; i++) { @@ -877,15 +913,18 @@ int main(int argc, char **argv) if (n_trials == 1) printf("errors_bit = %u (trial %d)\n", errors_bit, trial); } - + roundStats[snrRun]+=((float)round); + if (UE_harq_process->harq_ack.ack==1) effRate += ((float)TBS)/round; } // noise trials + roundStats[snrRun]/=((float)n_trials); + effRate /= n_trials; printf("*****************************************\n"); printf("SNR %f, (false positive %f)\n", SNR, (float) n_errors / (float) n_trials); printf("*****************************************\n"); printf("\n"); - printf("SNR %f : n_errors (negative CRC) = %d/%d, Channel BER %e\n", SNR, n_errors, n_trials,(double)errors_scrambling/available_bits/n_trials); + printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %d bits/slot\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials,effRate,effRate/TBS*100,TBS); printf("\n"); if (n_trials == 1) { @@ -898,7 +937,8 @@ int main(int argc, char **argv) break; } - if ((float)n_errors/(float)n_trials <= target_error_rate) { + //if ((float)n_errors/(float)n_trials <= target_error_rate) { + if (effRate >= (eff_tp_check*TBS)) { printf("PDSCH test OK\n"); break; } @@ -953,8 +993,18 @@ int main(int argc, char **argv) printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC"); */ } + snrRun++; } // NSR + /*if (n_trials>1) { + printf("HARQ stats:\nSNR\tRounds\n"); + psnr = snr0; + for (uint8_t i=0; iphysCellId=0; \ diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c index 9d14391f71..2144652f86 100644 --- a/openair1/SIMULATION/NR_PHY/pbchsim.c +++ b/openair1/SIMULATION/NR_PHY/pbchsim.c @@ -37,7 +37,7 @@ #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" #include "PHY/phy_vars.h" @@ -62,6 +62,8 @@ uint16_t NB_UE_INST = 1; openair0_config_t openair0_cfg[MAX_CARDS]; uint64_t get_softmodem_optmask(void) {return 0;} +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + void nr_phy_config_request_sim_pbchsim(PHY_VARS_gNB *gNB, int N_RB_DL, int N_RB_UL, diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 2ad89ce897..2db5bc905c 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "common/config/config_userapi.h" #include "common/utils/LOG/log.h" @@ -35,115 +36,91 @@ #include "SCHED_NR/sched_nr.h" #include "SCHED_NR_UE/phy_frame_config_nr.h" #include "PHY/phy_vars_nr_ue.h" - #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" +#include "nr_unitary_defs.h" #include "OCG_vars.h" -#include +#define NR_PRACH_DEBUG 1 +#define PRACH_WRITE_OUTPUT_DEBUG 1 PHY_VARS_gNB *gNB; PHY_VARS_NR_UE *UE; RAN_CONTEXT_t RC; RU_t *ru; - double cpuf; - extern uint16_t prach_root_sequence_map0_3[838]; - -void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); - uint16_t NB_UE_INST=1; -volatile int oai_exit=0; - -void exit_function(const char* file, const char* function, const int line,const char *s) { - const char * msg= s==NULL ? "no comment": s; - printf("Exiting at: %s:%d %s(), %s\n", file, line, function, msg); - exit(-1); -} - - -int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe) { - AssertFatal(1==0,"Shouldn't be here ...\n"); - return 0; -} - -uint8_t nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, - sub_frame_t subframe, uint8_t eNB_index, - uint8_t *ulsch_buffer, uint16_t buflen, uint8_t *access_mode) {return(0);} - -int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);} - openair0_config_t openair0_cfg[MAX_CARDS]; uint8_t nfapi_mode=0; -NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);} -int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } +int sl_ahead = 0; -uint64_t get_softmodem_optmask(void) { - return 0; -} +//void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); -int main(int argc, char **argv) -{ +/* temporary dummy implem of get_softmodem_optmask, till basic simulators implemented as device */ +uint64_t get_softmodem_optmask(void) {return 0;} +softmodem_params_t *get_softmodem_params(void) {return 0;} + +void pdcp_run (const protocol_ctxt_t *const ctxt_pP) { return;} + +boolean_t pdcp_data_ind(const protocol_ctxt_t *const ctxt_pP, + const srb_flag_t srb_flagP, + const MBMS_flag_t MBMS_flagP, + const rb_id_t rb_idP, + const sdu_size_t sdu_buffer_sizeP, + mem_block_t *const sdu_buffer_pP) {return(false);} + +void nr_ip_over_LTE_DRB_preconfiguration(void){} +void pdcp_layer_init(void) {} +int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const int8_t channel, const uint8_t* pduP, const sdu_size_t pdu_len) {return 0;} + +int main(int argc, char **argv){ char c; - int i,aa,aarx; - double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0,ue_speed0=0.0,ue_speed1=0.0; - uint8_t snr1set=0; - uint8_t ue_speed1set=0; - int **txdata; - double **s_re,**s_im,**r_re,**r_im; - double iqim=0.0; - int trial; //, ntrials=1; - uint8_t transmission_mode = 1,n_tx=1,n_rx=1; - uint16_t Nid_cell=0; + double sigma2, sigma2_dB = 0, SNR, snr0 = -2.0, snr1 = 0.0, ue_speed0 = 0.0, ue_speed1 = 0.0; + double **s_re, **s_im, **r_re, **r_im, iqim = 0.0, delay_avg = 0, ue_speed = 0, fs, bw; + int i, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1; + int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0; + uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format=0; + uint8_t frame = 1, subframe = 9, slot=19, slot_gNB=19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol; + uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1; + uint32_t tx_lev = 10000, prach_errors = 0, samp_count; //,tx_lev_dB; + uint64_t SSB_positions = 0x01, absoluteFrequencyPointA = 640000; - uint8_t awgn_flag=0; - uint8_t hs_flag=0; - int n_frames=1; - channel_desc_t *UE2gNB; - uint32_t tx_lev=0; //,tx_lev_dB; // int8_t interf1=-19,interf2=-19; - NR_DL_FRAME_PARMS *frame_parms; - - SCM_t channel_model=Rayleigh1; - // uint8_t abstraction_flag=0,calibration_flag=0; // double prach_sinr; - int N_RB_UL=273; - uint32_t prach_errors=0; - uint8_t subframe=9; - uint16_t preamble_energy_list[64],preamble_tx=50,preamble_delay_list[64]; - PRACH_RESOURCES_t prach_resources; - //uint8_t prach_fmt; - //int N_ZC; - int delay = 0; - double delay_avg=0; - double ue_speed = 0; - int NCS_config = 13,rootSequenceIndex=0; - int threequarter_fs = 0; - int mu=1; - uint64_t SSB_positions=0x01; + // uint32_t nsymb; + // uint16_t preamble_max, preamble_energy_max; + FILE *input_fd=NULL; + char* input_file=NULL; + int n_bytes=0; - int loglvl=OAILOG_INFO; + NR_DL_FRAME_PARMS *frame_parms; + NR_PRACH_RESOURCES_t prach_resources; + nfapi_nr_prach_config_t *prach_config; + nfapi_nr_prach_pdu_t *prach_pdu; + fapi_nr_prach_config_t *ue_prach_config; + fapi_nr_ul_config_prach_pdu *ue_prach_pdu; + channel_desc_t *UE2gNB; + SCM_t channel_model = Rayleigh1; cpuf = get_cpu_freq_GHz(); - if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) { exit_fun("[SOFTMODEM] Error, configuration module init failed\n"); } randominit(0); - - while ((c = getopt (argc, argv, "hHaA:Cr:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) { + while ((c = getopt (argc, argv, "hHaA:Cc:r:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) { switch (c) { case 'a': printf("Running AWGN simulation\n"); @@ -152,6 +129,14 @@ int main(int argc, char **argv) //ntrials=1; break; + case 'c': + config_index = atoi(optarg); + break; + + case 'r': + msg1_frequencystart = atoi(optarg); + break; + case 'd': delay = atoi(optarg); break; @@ -215,7 +200,7 @@ int main(int argc, char **argv) break; default: - msg("Unsupported channel model!\n"); + printf("Unsupported channel model!\n"); exit(-1); } @@ -231,13 +216,13 @@ int main(int argc, char **argv) case 's': snr0 = atof(optarg); - msg("Setting SNR0 to %f\n",snr0); + printf("Setting SNR0 to %f\n",snr0); break; case 'S': snr1 = atof(optarg); snr1set=1; - msg("Setting SNR1 to %f\n",snr1); + printf("Setting SNR1 to %f\n",snr1); break; case 'p': @@ -263,7 +248,7 @@ int main(int argc, char **argv) case 'H': printf("High-Speed Flag enabled\n"); - hs_flag = 1; + restrictedSetConfig = 1; break; case 'L': @@ -280,7 +265,7 @@ int main(int argc, char **argv) if ((transmission_mode!=1) && (transmission_mode!=2) && (transmission_mode!=6)) { - msg("Unsupported transmission mode %d\n",transmission_mode); + printf("Unsupported transmission mode %d\n",transmission_mode); exit(-1); } @@ -290,7 +275,7 @@ int main(int argc, char **argv) n_tx=atoi(optarg); if ((n_tx==0) || (n_tx>2)) { - msg("Unsupported number of tx antennas %d\n",n_tx); + printf("Unsupported number of tx antennas %d\n",n_tx); exit(-1); } @@ -300,7 +285,7 @@ int main(int argc, char **argv) n_rx=atoi(optarg); if ((n_rx==0) || (n_rx>2)) { - msg("Unsupported number of rx antennas %d\n",n_rx); + printf("Unsupported number of rx antennas %d\n",n_rx); exit(-1); } @@ -315,6 +300,14 @@ int main(int argc, char **argv) break; case 'F': + input_fd = fopen(optarg,"r"); + input_file = optarg; + + if (input_fd==NULL) { + printf("Problem with filename %s\n",optarg); + exit(-1); + } + break; default: @@ -344,20 +337,20 @@ int main(int argc, char **argv) } } - logInit(); + + if (config_index<67) { prach_sequence_length=0; slot = subframe*2; slot_gNB = 1+(subframe*2); } + uint16_t N_ZC; + N_ZC = prach_sequence_length == 0 ? 839 : 139; + printf("Config_index %d, prach_sequence_length %d\n",config_index,prach_sequence_length); + + // Configure log + logInit(); set_glog(loglvl); T_stdout = 1; - SET_LOG_DEBUG(PRACH); - if (snr1set==0) { - if (n_frames==1) - snr1 = snr0+.1; - else - snr1 = snr0+5.0; - } - + // Configure gNB and RU RC.gNB = (PHY_VARS_gNB**) malloc(2*sizeof(PHY_VARS_gNB *)); RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); memset(RC.gNB[0],0,sizeof(PHY_VARS_gNB)); @@ -367,90 +360,204 @@ int main(int argc, char **argv) memset(RC.ru[0],0,sizeof(RU_t)); RC.nb_RU = 1; - gNB = RC.gNB[0]; - ru = RC.ru[0]; - - - if (ue_speed1set==0) { - if (n_frames==1) - ue_speed1 = ue_speed0+10; - else - ue_speed1 = ue_speed0+50; - } - - printf("SNR0 %f, SNR1 %f\n",snr0,snr1); - - frame_parms = &gNB->frame_parms; - - + gNB = RC.gNB[0]; + ru = RC.ru[0]; + frame_parms = &gNB->frame_parms; + prach_config = &gNB->gNB_config.prach_config; + prach_pdu = &gNB->prach_vars.list[0].pdu; + frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) s_re = malloc(2*sizeof(double*)); s_im = malloc(2*sizeof(double*)); r_re = malloc(2*sizeof(double*)); r_im = malloc(2*sizeof(double*)); - frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) - frame_parms->nb_antennas_tx = n_tx; - frame_parms->nb_antennas_rx = n_rx; - frame_parms->N_RB_DL = N_RB_UL; - frame_parms->N_RB_UL = N_RB_UL; - frame_parms->threequarter_fs = threequarter_fs; + frame_parms->nb_antennas_tx = n_tx; + frame_parms->nb_antennas_rx = n_rx; + frame_parms->N_RB_DL = N_RB_UL; + frame_parms->N_RB_UL = N_RB_UL; + frame_parms->threequarter_fs = threequarter_fs; + frame_parms->frame_type = TDD; + frame_parms->freq_range = nr_FR1; + frame_parms->numerology_index = mu; - - nr_phy_config_request_sim(gNB,N_RB_UL,N_RB_UL,mu,Nid_cell,SSB_positions); - - frame_parms->frame_type = TDD; - frame_parms->freq_range = nr_FR1; + nr_phy_config_request_sim(gNB, N_RB_UL, N_RB_UL, mu, Nid_cell, SSB_positions); //nsymb = (frame_parms->Ncp == 0) ? 14 : 12; - printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d,Frame type %s, Frequency Range %s\n",NUMBER_OF_OFDM_CARRIERS, - frame_parms->Ncp,frame_parms->samples_per_subframe,frame_parms->frame_type == FDD ? "FDD" : "TDD", frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2"); + printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d, Frame type %s, Frequency Range %s\n", + NUMBER_OF_OFDM_CARRIERS, + frame_parms->Ncp, + frame_parms->samples_per_subframe, + frame_parms->frame_type == FDD ? "FDD" : "TDD", + frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2"); - ru->nr_frame_parms=frame_parms; - ru->if_south = LOCAL_RF; - ru->nb_tx = n_tx; - ru->nb_rx = n_rx; + ru->nr_frame_parms = frame_parms; + ru->if_south = LOCAL_RF; + ru->nb_tx = n_tx; + ru->nb_rx = n_rx; + gNB->gNB_config.carrier_config.num_tx_ant.value = 1; + gNB->gNB_config.carrier_config.num_rx_ant.value = 1; + gNB->gNB_config.tdd_table.tdd_period.value = 6; + + gNB->gNB_config.prach_config.num_prach_fd_occasions.value = num_prach_fd_occasions; + gNB->gNB_config.prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(nfapi_nr_num_prach_fd_occasions_t)); + + gNB->proc.slot_rx = slot; + + int ret = get_nr_prach_info_from_index(config_index, + (int)frame, + (int)slot_gNB, + absoluteFrequencyPointA, + mu, + frame_parms->frame_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur); + + if (ret == 0) {printf("No prach in %d.%d, mu %d, config_index %d\n",frame,slot,mu,config_index); exit(-1);} + format0 = format&0xff; // first column of format from table + format1 = (format>>8)&0xff; // second column of format from table + + if (format1 != 0xff) { + switch(format0) { + case 0xa1: + prach_format = 9; + break; + case 0xa2: + prach_format = 10; + break; + case 0xa3: + prach_format = 11; + break; + default: + AssertFatal(1==0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } else { + switch(format0) { + case 0xa1: + prach_format = 0; + break; + case 0xa2: + prach_format = 1; + break; + case 0xa3: + prach_format = 2; + break; + case 0xb1: + prach_format = 3; + break; + case 0xb2: + prach_format = 4; + break; + case 0xb3: + prach_format = 5; + break; + case 0xb4: + prach_format = 6; + break; + case 0xc0: + prach_format = 7; + break; + case 0xc2: + prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1==0, "Invalid PRACH format"); + } + } + + printf("PRACH format %d\n",prach_format); + + prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value = rootSequenceIndex; + prach_config->num_prach_fd_occasions_list[fd_occasion].k1.value = msg1_frequencystart; + prach_config->restricted_set_config.value = restrictedSetConfig; + prach_config->prach_sequence_length.value = prach_sequence_length; + prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig); + prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value = 1+(64/(N_ZC/prach_pdu->num_cs)); + prach_pdu->prach_format = prach_format; + + memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); RC.nb_nr_L1_inst=1; phy_init_nr_gNB(gNB,0,0); nr_phy_init_RU(ru); - set_tdd_config_nr(&gNB->gNB_config, 5000, - 7, 6, - 2, 4); + gNB->common_vars.rxdata = ru->common.rxdata; + set_tdd_config_nr(&gNB->gNB_config, mu, 7, 6, 2, 4); - //configure UE + // Configure UE UE = malloc(sizeof(PHY_VARS_NR_UE)); memset((void*)UE,0,sizeof(PHY_VARS_NR_UE)); PHY_vars_UE_g = malloc(2*sizeof(PHY_VARS_NR_UE**)); PHY_vars_UE_g[0] = malloc(2*sizeof(PHY_VARS_NR_UE*)); PHY_vars_UE_g[0][0] = UE; memcpy(&UE->frame_parms,frame_parms,sizeof(NR_DL_FRAME_PARMS)); - if (init_nr_ue_signal(UE, 1, 0) != 0) - { + UE->nrUE_config.prach_config.num_prach_fd_occasions_list = (fapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(fapi_nr_num_prach_fd_occasions_t)); + + if (init_nr_ue_signal(UE, 1, 0) != 0){ printf("Error at UE NR initialisation\n"); exit(-1); } - txdata = UE->common_vars.txdata; - printf("txdata %p\n",&txdata[0][subframe*frame_parms->samples_per_subframe]); + ue_prach_pdu = &UE->prach_vars[0]->prach_pdu; + ue_prach_config = &UE->nrUE_config.prach_config; + UE->prach_resources[0] = &prach_resources; + txdata = UE->common_vars.txdata; - double fs,bw; + UE->prach_vars[0]->amp = AMP; + ue_prach_pdu->root_seq_id = rootSequenceIndex; + ue_prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig); + ue_prach_pdu->restricted_set = restrictedSetConfig; + ue_prach_pdu->freq_msg1 = msg1_frequencystart; + ue_prach_pdu->prach_format = prach_format; + ue_prach_config->prach_sub_c_spacing = mu; + ue_prach_config->prach_sequence_length = prach_sequence_length; + ue_prach_config->restricted_set_config = restrictedSetConfig; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences = prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value ; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index = rootSequenceIndex; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].k1 = msg1_frequencystart; + + if (preamble_tx == 99) + preamble_tx = (uint16_t)(taus()&0x3f); + + if (n_frames == 1) + printf("raPreamble %d\n",preamble_tx); + + UE->prach_resources[0]->ra_PreambleIndex = preamble_tx; + UE->prach_resources[0]->init_msg1 = 1; + + // Configure channel + bw = N_RB_UL*(180e3)*(1 << frame_parms->numerology_index); + AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n", bw, frame_parms->numerology_index, N_RB_UL); + + if (bw <= 30.72e6) + fs = 30.72e6; + else if (bw <= 61.44e6) + fs = 61.44e6; + else if (bw <= 122.88e6) + fs = 122.88e6; - bw = N_RB_UL*(180e3)*(1<frame_parms.numerology_index); - AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n",bw, gNB->frame_parms.numerology_index,N_RB_UL); - if (bw <= 30.72e6) fs = 30.72e6; - else if (bw <= 61.44e6) fs = 61.44e6; - else if (bw <= 122.88e6) fs = 122.88e6; LOG_I(PHY,"Running with bandwidth %f Hz, fs %f samp/s, FRAME_LENGTH_COMPLEX_SAMPLES %d\n",bw,fs,FRAME_LENGTH_COMPLEX_SAMPLES); - UE2gNB = new_channel_desc_scm(UE->frame_parms.nb_antennas_tx, gNB->frame_parms.nb_antennas_rx, channel_model, - fs, - bw, + fs, + bw, 0.0, delay, 0); @@ -473,97 +580,80 @@ int main(int argc, char **argv) bzero(r_im[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); } - UE->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex; - UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98; - UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config; - UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag; - UE->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0; - UE->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0; + // compute PRACH sequence + compute_nr_prach_seq(prach_config->prach_sequence_length.value, + prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value, + prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value, + gNB->X_u); - - gNB->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0; - - gNB->proc.slot_rx = subframe<<1; - - gNB->common_vars.rxdata = ru->common.rxdata; - - - compute_nr_prach_seq(gNB->frame_parms.prach_config_common.rootSequenceIndex, - gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, - gNB->frame_parms.frame_type, - gNB->frame_parms.freq_range, - gNB->X_u); - - compute_nr_prach_seq(UE->frame_parms.prach_config_common.rootSequenceIndex, - UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, - UE->frame_parms.frame_type, - UE->frame_parms.freq_range, - UE->X_u); - - - - UE->prach_vars[0]->amp = AMP; - - UE->prach_resources[0] = &prach_resources; - - if (preamble_tx == 99) - preamble_tx = (uint16_t)(taus()&0x3f); - - if (n_frames == 1) - printf("raPreamble %d\n",preamble_tx); - - UE->prach_resources[0]->ra_PreambleIndex = preamble_tx; - UE->prach_resources[0]->ra_TDD_map_index = 0; + compute_nr_prach_seq(ue_prach_config->prach_sequence_length, + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences, + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index, + UE->X_u); /*tx_lev = generate_nr_prach(UE, 0, //gNB_id, - subframe, - 0); //Nf */ //commented for testing purpose + subframe); */ //commented for testing purpose UE_nr_rxtx_proc_t proc={0}; - nr_ue_prach_procedures(UE,&proc,0,0,0); - + proc.frame_tx = frame; + proc.nr_tti_tx = slot; + nr_ue_prach_procedures(UE,&proc,0,0); /* tx_lev_dB not used later, no need to set */ //tx_lev_dB = (unsigned int) dB_fixed(tx_lev); - LOG_M("txsig0.m","txs0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1); - //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); + prach_start = subframe*frame_parms->samples_per_subframe-UE->N_TA_offset; + + #ifdef NR_PRACH_DEBUG + LOG_M("txsig0.m", "txs0", &txdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1); + LOG_M("txsig0_frame.m","txs0", txdata[0],frame_parms->samples_per_frame,1,1); + #endif // multipath channel - dump_nr_prach_config(&gNB->frame_parms,subframe); + // dump_nr_prach_config(&gNB->frame_parms,subframe); - for (i=0; i<2*frame_parms->samples_per_subframe; i++) { + for (i = 0; i < frame_parms->samples_per_subframe<<1; i++) { for (aa=0; aa<1; aa++) { if (awgn_flag == 0) { - s_re[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); - s_im[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + s_re[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); + s_im[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]); } else { for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { if (aa==0) { - r_re[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); - r_im[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + r_re[aarx][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); + r_im[aarx][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]); } else { - r_re[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); - r_im[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + r_re[aarx][i] += ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); + r_im[aarx][i] += ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]); } } } } } + if (snr1set == 0) { + if (n_frames == 1) + snr1 = snr0 + .1; + else + snr1 = snr0 + 5.0; + } + + printf("SNR0 %f, SNR1 %f\n", snr0, snr1); + + if (ue_speed1set == 0) { + if (n_frames == 1) + ue_speed1 = ue_speed0 + 10; + else + ue_speed1 = ue_speed0 + 50; + } + + rx_prach_start = subframe*frame_parms->samples_per_subframe; + if (n_frames==1) printf("slot %d, rx_prach_start %d\n",slot,rx_prach_start); + uint16_t preamble_rx, preamble_energy; - for (SNR=snr0; SNRsamples_per_subframe,0); + multipath_tv_channel(UE2gNB, s_re, s_im, r_re, r_im, frame_parms->samples_per_tti<<1, 0); } if (n_frames==1) { @@ -594,55 +683,66 @@ int main(int argc, char **argv) 10*log10(tx_lev)); } - for (i=0; isamples_per_subframe; i++) { - for (aa=0; aaframe_parms.nb_antennas_rx; aa++) { - - ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + for (i = 0; i< frame_parms->samples_per_subframe; i++) { + for (aa = 0; aa < frame_parms->nb_antennas_rx; aa++) { + ((short*) &ru->common.rxdata[aa][rx_prach_start])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) &ru->common.rxdata[aa][rx_prach_start])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); } } - uint16_t preamble_rx; - rx_nr_prach_ru(ru, - 0, - subframe); - gNB->prach_vars.rxsigF = ru->prach_rxsigF; + } else { + n_bytes = fread(&ru->common.rxdata[0][rx_prach_start],sizeof(int32_t),frame_parms->samples_per_subframe,input_fd); + printf("fread %d bytes from file %s\n",n_bytes,input_file); + if (n_bytes!=frame_parms->samples_per_subframe) { + printf("expected %d bytes\n",frame_parms->samples_per_subframe); + exit(-1); + } + } - rx_nr_prach(gNB, - 0, - subframe, - &preamble_rx, - preamble_energy_list, - preamble_delay_list); - - if (preamble_rx!=preamble_tx) + + rx_nr_prach_ru(ru, prach_format, numRA, prachStartSymbol, frame, slot); + + gNB->prach_vars.rxsigF = ru->prach_rxsigF; + if (n_frames == 1) printf("ncs %d,num_seq %d\n",prach_pdu->num_cs, prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value); + rx_nr_prach(gNB, prach_pdu, frame, subframe, &preamble_rx, &preamble_energy, &preamble_delay); + + // printf(" preamble_energy %d preamble_rx %d preamble_tx %d \n", preamble_energy, preamble_rx, preamble_tx); + + if (preamble_rx != preamble_tx) prach_errors++; - else { - delay_avg += (double)preamble_delay_list[preamble_tx]; - } + else + delay_avg += (double)preamble_delay; + + N_ZC = (prach_sequence_length) ? 139 : 839; if (n_frames==1) { - printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy_list[0],preamble_delay_list[0]); - - - LOG_M("prach0.m","prach0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1); - LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0],24576,1,1); - LOG_M("rxsig0.m","rxs0", - &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe], - frame_parms->samples_per_subframe,1,1); - LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0],839*4,1,1); - LOG_M("prach_preamble.m","prachp",&gNB->X_u[0],839,1,1); + printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy,preamble_delay); + #ifdef NR_PRACH_DEBUG + LOG_M("prach0.m","prach0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); + LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0], N_ZC, 1, 1); + LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1); + LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1); + LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0], N_ZC, 1, 1); + LOG_M("prach_preamble.m","prachp", &gNB->X_u[0], N_ZC, 1, 1); + LOG_M("ue_prach_preamble.m","prachp", &UE->X_u[0], N_ZC, 1, 1); + #endif } } - printf("SNR %f dB, UE Speed %f km/h: errors %u/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); - //printf("(%f,%f)\n",ue_speed,(double)prach_errors/(double)n_frames); + printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n", SNR, ue_speed, prach_errors, n_frames, delay_avg/(double)(n_frames-prach_errors)); + if (input_fd) + break; + if (prach_errors) + break; + } // UE Speed loop - - //printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); - // printf("(%f,%f)\n",SNR,(double)prach_errors/(double)n_frames); + if (!prach_errors) { + printf("PRACH test OK\n"); + break; + } + if (input_fd) + break; } //SNR loop - for (i=0; i<2; i++) { free(s_re[i]); free(s_im[i]); @@ -655,17 +755,7 @@ int main(int argc, char **argv) free(r_re); free(r_im); + if (input_fd) fclose(input_fd); return(0); - } - - - -/* - for (i=1;i<4;i++) - memcpy((void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[i*12*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*2], - (void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[0], - 12*OFDM_SYMBOL_SIZE_SAMPLES_NO_PREFIX*2); -*/ - diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index a754df4763..004a7b8de8 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -37,7 +37,7 @@ #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/NR_UE_TRANSPORT/pucch_nr.h" #include "SCHED_NR/sched_nr.h" @@ -59,6 +59,8 @@ uint16_t NB_UE_INST = 1; // needed for some functions PHY_VARS_NR_UE * PHY_vars_UE_g[1][1]={{NULL}}; +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + int main(int argc, char **argv) { char c; @@ -84,7 +86,7 @@ int main(int argc, char **argv) int format=0; //uint8_t extended_prefix_flag=0; FILE *input_fd=NULL; - uint8_t nacktoack_flag=0; + //uint8_t nacktoack_flag=0; int16_t amp=0x7FFF; int nr_tti_tx=0; uint64_t actual_payload=0,payload_received; @@ -283,7 +285,7 @@ int main(int argc, char **argv) actual_payload=atoi(optarg); break; case 'T': - nacktoack_flag=(uint8_t)atoi(optarg); + //nacktoack_flag=(uint8_t)atoi(optarg); target_error_rate=0.001; break; default: @@ -336,7 +338,7 @@ int main(int argc, char **argv) } AssertFatal(((format < 2)&&(nr_bit<3)&&(actual_payload<4)) || - ((format == 2)&&(nr_bit>2)&&(nr_bit<12)),"illegal combination format %d, nr_bit %d\n", + ((format == 2)&&(nr_bit>2)&&(nr_bit<65)),"illegal combination format %d, nr_bit %d\n", format,nr_bit); actual_payload &= ((1<pucch_config_common_nr->pucch_GroupHopping; uint32_t hopping_id=UE->pucch_config_common_nr->hoppingId; uint32_t dmrs_scrambling_id = 0, data_scrambling_id=0; + //t_nrPolar_params *currentPtr; + if(format==0){ // for now we are not considering SR just HARQ-ACK if (nr_bit ==0) @@ -467,14 +471,15 @@ int main(int argc, char **argv) mcs=table2_mcs[actual_payload]; else AssertFatal(1==0,"Either nr_bit %d or sr_flag %d must be non-zero\n", nr_bit, sr_flag); } - + else if (format == 2 && nr_bit > 11) gNB->uci_polarParams = nr_polar_params(2, nr_bit, nrofPRB, 1, NULL); + for(SNR=snr0;SNR<=snr1;SNR=SNR+1){ ack_nack_errors=0; n_errors = 0; for (trial=0; trialofdm_symbol_size*sizeof(int)); if(format==0){ - nr_generate_pucch0(UE,txdataF,frame_parms,UE->pucch_config_dedicated,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB); + nr_generate_pucch0(UE,txdataF,frame_parms,PUCCH_GroupHopping,hopping_id,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB); } else if (format == 1){ nr_generate_pucch1(UE,txdataF,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,0,nr_bit); @@ -498,7 +503,7 @@ int main(int argc, char **argv) } int rxlev = signal_energy(&rxdataF[aa][startingSymbolIndex*frame_parms->ofdm_symbol_size], frame_parms->ofdm_symbol_size); - // printf("rxlev %d (%d dB), sigma2 %f dB, SNR %f, TX %f\n",rxlev,dB_fixed(rxlev),sigma2_dB,SNR,10*log10((double)txlev*UE->frame_parms.ofdm_symbol_size/12)); + if (n_trials==1) printf("rxlev %d (%d dB), sigma2 %f dB, SNR %f, TX %f\n",rxlev,dB_fixed(rxlev),sigma2_dB,SNR,10*log10((double)txlev*UE->frame_parms.ofdm_symbol_size/12)); if(format==0){ nfapi_nr_uci_pucch_pdu_format_0_1_t uci_pdu; nfapi_nr_pucch_pdu_t pucch_pdu; @@ -506,6 +511,8 @@ int main(int argc, char **argv) pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1; pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1; pucch_pdu.bit_len_harq = nr_bit; + pucch_pdu.bit_len_csi_part1 = 0; + pucch_pdu.bit_len_csi_part2 = 0; pucch_pdu.sr_flag = sr_flag; pucch_pdu.nr_of_symbols = nrofSymbols; pucch_pdu.hopping_id = hopping_id; @@ -534,7 +541,9 @@ int main(int argc, char **argv) pucch_pdu.subcarrier_spacing = 1; pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1; pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1; - pucch_pdu.bit_len_harq = nr_bit; + pucch_pdu.bit_len_csi_part1 = nr_bit; + pucch_pdu.bit_len_harq = 0; + pucch_pdu.bit_len_csi_part2 = 0; pucch_pdu.sr_flag = 0; pucch_pdu.nr_of_symbols = nrofSymbols; pucch_pdu.hopping_id = hopping_id; @@ -545,14 +554,15 @@ int main(int argc, char **argv) pucch_pdu.dmrs_scrambling_id = dmrs_scrambling_id; pucch_pdu.data_scrambling_id = data_scrambling_id; nr_decode_pucch2(gNB,nr_tti_tx,&uci_pdu,&pucch_pdu); - int harq_bytes=pucch_pdu.bit_len_harq>>3; - if ((pucch_pdu.bit_len_harq&7) > 0) harq_bytes++; - for (int i=0;i>3; + if ((pucch_pdu.bit_len_csi_part1&7) > 0) csi_part1_bytes++; + for (int i=0;i>1)+(((actual_payload^payload_received)&4)>>2)+n_errors; diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index 5881b21b5f..b0557ef1b4 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -37,7 +37,7 @@ #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" @@ -54,6 +54,8 @@ PHY_VARS_NR_UE *UE; RAN_CONTEXT_t RC; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + double cpuf; uint8_t nfapi_mode = 0; uint16_t NB_UE_INST = 1; @@ -391,7 +393,7 @@ int main(int argc, char **argv) mod_order = nr_get_Qm_ul(Imcs, 0); code_rate = nr_get_code_rate_ul(Imcs, 0); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); - TBS = nr_compute_tbs(mod_order,code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl); + TBS = nr_compute_tbs(mod_order,code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl); printf("\nAvailable bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 169b82bf8d..bcaa967a30 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -41,11 +41,11 @@ #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_sch_dmrs.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/TOOLS/tools_defs.h" +#include "SCHED_NR/fapi_nr_l1.h" #include "SCHED_NR/sched_nr.h" #include "SCHED_NR_UE/defs.h" #include "SCHED_NR_UE/fapi_nr_ue_l1.h" @@ -53,10 +53,13 @@ #include "openair1/SIMULATION/RF/rf.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" #include "openair2/RRC/NR/MESSAGES/asn1_msg.h" +//#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" #include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" + #define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0)) #include "SIMULATION/LTE_PHY/common_sim.h" + //#define DEBUG_ULSIM PHY_VARS_gNB *gNB; @@ -108,15 +111,15 @@ int main(int argc, char **argv) int i; double SNR, snr0 = -2.0, snr1 = 2.0; double sigma, sigma_dB; - double snr_step = 1; + double snr_step = .2; uint8_t snr1set = 0; - int slot = 0, frame = 0; + int slot = 8, frame = 0; FILE *output_fd = NULL; //uint8_t write_output_file = 0; int trial, n_trials = 1, n_errors = 0, n_false_positive = 0, delay = 0; uint8_t n_tx = 1, n_rx = 1; //uint8_t transmission_mode = 1; - uint16_t Nid_cell = 0; + //uint16_t Nid_cell = 0; channel_desc_t *gNB2UE; uint8_t extended_prefix_flag = 0; //int8_t interf1 = -21, interf2 = -21; @@ -124,10 +127,9 @@ int main(int argc, char **argv) SCM_t channel_model = AWGN; //Rayleigh1_anticorr; uint16_t N_RB_DL = 106, N_RB_UL = 106, mu = 1; //unsigned char frame_type = 0; - int frame_length_complex_samples,frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; int loglvl = OAILOG_WARNING; - uint64_t SSB_positions=0x01; + //uint64_t SSB_positions=0x01; uint16_t nb_symb_sch = 12; int start_symbol = 2; uint16_t nb_rb = 50; @@ -143,12 +145,13 @@ int main(int argc, char **argv) float target_error_rate = 0.01; int print_perf = 0; cpuf = get_cpu_freq_GHz(); - + int msg3_flag = 0; UE_nr_rxtx_proc_t UE_proc; FILE *scg_fd=NULL; - + int ibwps=24; + int ibwp_rboffset=41; if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0 ) { exit_fun("[NR_ULSIM] Error, configuration module init failed\n"); } @@ -156,208 +159,236 @@ int main(int argc, char **argv) //logInit(); randominit(0); - while ((c = getopt(argc, argv, "d:f:g:h:i:j:l:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) { + while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:i:j:kl:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) { + printf("handling optarg %c\n",c); switch (c) { /*case 'd': frame_type = 1; break;*/ - case 'd': - delay = atoi(optarg); - break; + case 'a': + start_symbol = atoi(optarg); + AssertFatal(start_symbol >= 0 && start_symbol < 13,"start_symbol %d is not in 0..12\n",start_symbol); + break; - case 'f': - scg_fd = fopen(optarg, "r"); + case 'b': + nb_symb_sch = atoi(optarg); + AssertFatal(nb_symb_sch > 0 && nb_symb_sch < 15,"start_symbol %d is not in 1..14\n",nb_symb_sch); + break; + case 'c': + n_rnti = atoi(optarg); + AssertFatal(n_rnti > 0 && n_rnti<=65535,"Illegal n_rnti %x\n",n_rnti); + break; - if (scg_fd == NULL) { - printf("Error opening %s\n", optarg); - exit(-1); - } - - break; - - case 'g': - switch ((char) *optarg) { - case 'A': - channel_model = SCM_A; - break; - - case 'B': - channel_model = SCM_B; - break; - - case 'C': - channel_model = SCM_C; - break; - - case 'D': - channel_model = SCM_D; - break; - - case 'E': - channel_model = EPA; - break; - - case 'F': - channel_model = EVA; - break; - - case 'G': - channel_model = ETU; - break; - - default: - printf("Unsupported channel model!\n"); - exit(-1); - } - - break; + case 'd': + delay = atoi(optarg); + break; + + case 'e': + msg3_flag = 1; + break; + + case 'f': + scg_fd = fopen(optarg, "r"); + + if (scg_fd == NULL) { + printf("Error opening %s\n", optarg); + exit(-1); + } + break; + + case 'g': + switch ((char) *optarg) { + case 'A': + channel_model = SCM_A; + break; + + case 'B': + channel_model = SCM_B; + break; + + case 'C': + channel_model = SCM_C; + break; + + case 'D': + channel_model = SCM_D; + break; + + case 'E': + channel_model = EPA; + break; + + case 'F': + channel_model = EVA; + break; + + case 'G': + channel_model = ETU; + break; + + default: + printf("Unsupported channel model!\n"); + exit(-1); + } + + break; + /*case 'i': interf1 = atoi(optarg); break; - - case 'j': + + case 'j': interf2 = atoi(optarg); break;*/ - case 'l': - nb_symb_sch = atoi(optarg); - break; - - case 'm': - Imcs = atoi(optarg); - break; - - case 'n': - n_trials = atoi(optarg); - break; - - case 'p': - extended_prefix_flag = 1; - break; - - case 'r': - nb_rb = atoi(optarg); - break; - - case 's': - snr0 = atof(optarg); - printf("Setting SNR0 to %f\n", snr0); - break; + case 'k': + printf("Setting threequarter_fs_flag\n"); + openair0_cfg[0].threequarter_fs= 1; + break; + case 'l': + nb_symb_sch = atoi(optarg); + break; + + case 'm': + Imcs = atoi(optarg); + break; + + case 'n': + n_trials = atoi(optarg); + break; + + case 'p': + extended_prefix_flag = 1; + break; + + case 'r': + nb_rb = atoi(optarg); + break; + + case 's': + snr0 = atof(optarg); + printf("Setting SNR0 to %f\n", snr0); + break; + /* - case 'r': - ricean_factor = pow(10,-.1*atof(optarg)); - if (ricean_factor>1) { - printf("Ricean factor must be between 0 and 1\n"); - exit(-1); - } - break; - */ - + case 'r': + ricean_factor = pow(10,-.1*atof(optarg)); + if (ricean_factor>1) { + printf("Ricean factor must be between 0 and 1\n"); + exit(-1); + } + break; + */ + /*case 'x': transmission_mode = atoi(optarg); break;*/ + + case 'y': + n_tx = atoi(optarg); + + if ((n_tx == 0) || (n_tx > 2)) { + printf("Unsupported number of tx antennas %d\n", n_tx); + exit(-1); + } + + break; + + case 'z': + n_rx = atoi(optarg); + + if ((n_rx == 0) || (n_rx > 2)) { + printf("Unsupported number of rx antennas %d\n", n_rx); + exit(-1); + } + + break; + + case 'F': + input_fd = fopen(optarg, "r"); + + if (input_fd == NULL) { + printf("Problem with filename %s\n", optarg); + exit(-1); + } + + break; + + case 'M': + // SSB_positions = atoi(optarg); + break; + + case 'N': + // Nid_cell = atoi(optarg); + break; + + case 'R': + N_RB_DL = atoi(optarg); + N_RB_UL = N_RB_DL; + break; + + case 'S': + snr1 = atof(optarg); + snr1set = 1; + printf("Setting SNR1 to %f\n", snr1); + break; + + case 'P': + print_perf=1; + opp_enabled=1; + break; + + case 'L': + loglvl = atoi(optarg); + break; + + default: + case 'h': + printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", argv[0]); + //printf("-d Use TDD\n"); + printf("-d Introduce delay in terms of number of samples\n"); + printf("-f Number of frames to simulate\n"); + printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n"); + printf("-h This message\n"); + //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n"); + //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); + printf("-s Starting SNR, runs from SNR0 to SNR0 + 10 dB if ending SNR isn't given\n"); + printf("-m MCS value\n"); + printf("-n Number of trials to simulate\n"); + printf("-p Use extended prefix mode\n"); + printf("-t Delay spread for multipath channel\n"); + //printf("-x Transmission mode (1,2,6 for the moment)\n"); + printf("-y Number of TX antennas used in eNB\n"); + printf("-z Number of RX antennas used in UE\n"); + printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); + //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); + printf("-F Input filename (.txt format) for RX conformance testing\n"); + printf("-G raw file containing RRC configuration (generated by gNB)\n"); + printf("-M Multiple SSB positions in burst\n"); + printf("-N Nid_cell\n"); + printf("-O oversampling factor (1,2,4,8,16)\n"); + printf("-R N_RB_DL\n"); + printf("-S Ending SNR, runs from SNR0 to SNR1\n"); + printf("-P Print ULSCH performances\n"); + exit(-1); + break; - case 'y': - n_tx = atoi(optarg); - - if ((n_tx == 0) || (n_tx > 2)) { - printf("Unsupported number of tx antennas %d\n", n_tx); - exit(-1); - } - - break; - - case 'z': - n_rx = atoi(optarg); - - if ((n_rx == 0) || (n_rx > 2)) { - printf("Unsupported number of rx antennas %d\n", n_rx); - exit(-1); - } - - break; - - case 'F': - input_fd = fopen(optarg, "r"); - - if (input_fd == NULL) { - printf("Problem with filename %s\n", optarg); - exit(-1); - } - - break; - - case 'M': - SSB_positions = atoi(optarg); - break; - - case 'N': - Nid_cell = atoi(optarg); - break; - - case 'R': - N_RB_DL = atoi(optarg); - N_RB_UL = N_RB_DL; - break; - - case 'S': - snr1 = atof(optarg); - snr1set = 1; - printf("Setting SNR1 to %f\n", snr1); - break; - - case 'P': - print_perf=1; - opp_enabled=1; - break; - - case 'L': - loglvl = atoi(optarg); - break; - - default: - case 'h': - printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", argv[0]); - //printf("-d Use TDD\n"); - printf("-d Introduce delay in terms of number of samples\n"); - printf("-f Number of frames to simulate\n"); - printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n"); - printf("-h This message\n"); - //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n"); - //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); - printf("-s Starting SNR, runs from SNR0 to SNR0 + 10 dB if ending SNR isn't given\n"); - printf("-m MCS value\n"); - printf("-n Number of trials to simulate\n"); - printf("-p Use extended prefix mode\n"); - printf("-t Delay spread for multipath channel\n"); - //printf("-x Transmission mode (1,2,6 for the moment)\n"); - printf("-y Number of TX antennas used in eNB\n"); - printf("-z Number of RX antennas used in UE\n"); - printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); - //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); - printf("-F Input filename (.txt format) for RX conformance testing\n"); - printf("-G raw file containing RRC configuration (generated by gNB)\n"); - printf("-M Multiple SSB positions in burst\n"); - printf("-N Nid_cell\n"); - printf("-O oversampling factor (1,2,4,8,16)\n"); - printf("-R N_RB_DL\n"); - printf("-S Ending SNR, runs from SNR0 to SNR1\n"); - printf("-P Print ULSCH performances\n"); - exit(-1); - break; } } - + logInit(); set_glog(loglvl); T_stdout = 1; get_softmodem_params()->phy_test = 1; - + get_softmodem_params()->do_ra = 0; + get_softmodem_params()->usim_test = 1; + + if (snr1set == 0) snr1 = snr0 + 10; @@ -382,12 +413,15 @@ int main(int argc, char **argv) gNB->UL_INFO.rx_ind.number_of_pdus = 0; gNB->UL_INFO.crc_ind.number_crcs = 0; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) + + frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; frame_parms->N_RB_DL = N_RB_DL; frame_parms->N_RB_UL = N_RB_UL; frame_parms->Ncp = extended_prefix_flag ? EXTENDED : NORMAL; + RC.nb_nr_macrlc_inst = 1; RC.nb_nr_mac_CC = (int*)malloc(RC.nb_nr_macrlc_inst*sizeof(int)); for (i = 0; i < RC.nb_nr_macrlc_inst; i++) @@ -416,6 +450,7 @@ int main(int argc, char **argv) xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); AssertFatal((gNB->if_inst = NR_IF_Module_init(0))!=NULL,"Cannot register interface"); + gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; // common configuration rrc_mac_config_req_gNB(0,0,1,scc,0,0,NULL); @@ -424,12 +459,14 @@ int main(int argc, char **argv) phy_init_nr_gNB(gNB,0,0); N_RB_DL = gNB->frame_parms.N_RB_DL; + + + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; + //crcTableInit(); //nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_UL, mu, Nid_cell, SSB_positions); - frame_length_complex_samples = frame_parms->samples_per_subframe; - frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP; //configure UE UE = malloc(sizeof(PHY_VARS_NR_UE)); @@ -477,7 +514,7 @@ int main(int argc, char **argv) rrc.carrier.MIB = (uint8_t*) malloc(4); rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0); - nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig); + nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup); nr_ue_phy_config_request(&UE_mac->phy_config); @@ -486,7 +523,11 @@ int main(int argc, char **argv) NR_gNB_ULSCH_t *ulsch_gNB = gNB->ulsch[UE_id][0]; //nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch_gNB->harq_processes[harq_pid]->ulsch_pdu; - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; + nfapi_nr_ul_tti_request_t *UL_tti_req = malloc(sizeof(*UL_tti_req)); + NR_Sched_Rsp_t *Sched_INFO = malloc(sizeof(*Sched_INFO)); + memset((void*)Sched_INFO,0,sizeof(*Sched_INFO)); + Sched_INFO->UL_tti_req=UL_tti_req; + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; NR_UE_ULSCH_t **ulsch_ue = UE->ulsch[0][0]; @@ -533,6 +574,7 @@ int main(int argc, char **argv) printf("\n"); + for (int i=0;i<16;i++) printf("%f\n",gaussdouble(0.0,1.0)); for (SNR = snr0; SNR < snr1; SNR += snr_step) { varArray_t *table_rx=initVarArray(1000,sizeof(double)); @@ -574,19 +616,40 @@ int main(int argc, char **argv) UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); + int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int ibwp_size = ibwps; + int ibwp_start = ibwp_rboffset; + if (msg3_flag == 1) { + if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size)) + pusch_pdu->bwp_start = abwp_start; + else + pusch_pdu->bwp_start = ibwp_start; + pusch_pdu->bwp_size = ibwp_size; + start_rb += (ibwp_start - abwp_start); + printf("msg3: ibwp_size %d, abwp_size %d, ibwp_start %d, abwp_start %d\n", + ibwp_size,abwp_size,ibwp_start,abwp_start); + } + else { + pusch_pdu->bwp_start = abwp_start; + pusch_pdu->bwp_size = abwp_size; + } + pusch_pdu->pdu_bit_map = pdu_bit_map; pusch_pdu->rnti = n_rnti; pusch_pdu->mcs_index = Imcs; pusch_pdu->mcs_table = mcs_table; pusch_pdu->target_code_rate = code_rate; pusch_pdu->qam_mod_order = mod_order; - pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; + pusch_pdu->transform_precoding = 1; + pusch_pdu->data_scrambling_id = *scc->physCellId; pusch_pdu->nrOfLayers = 1; pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << start_symbol; pusch_pdu->dmrs_config_type = 0; - pusch_pdu->ul_dmrs_scrambling_id = 0; + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; pusch_pdu->scid = 0; + pusch_pdu->dmrs_ports = 1; + pusch_pdu->num_dmrs_cdm_grps_no_data = 1; pusch_pdu->resource_alloc = 1; pusch_pdu->rb_start = start_rb; pusch_pdu->rb_size = nb_rb; @@ -604,6 +667,9 @@ int main(int argc, char **argv) pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + // prepare ULSCH/PUSCH reception + nr_schedule_response(Sched_INFO); + // --------- setting parameters for UE -------- scheduled_response.module_id = 0; @@ -627,6 +693,7 @@ int main(int argc, char **argv) ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type = 0; ul_config.ul_config_list[0].pusch_config_pdu.mcs_index = Imcs; ul_config.ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + ul_config.ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = 0; ul_config.ul_config_list[0].pusch_config_pdu.nrOfLayers = precod_nbr_layers; @@ -638,75 +705,135 @@ int main(int argc, char **argv) //there are plenty of other parameters that we don't seem to be using for now. e.g. ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0; - nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); - available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1); - TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, precod_nbr_layers); + nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); + available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1); + TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers); pusch_pdu->pusch_data.tb_size = TBS>>3; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS; - // set FAPI parameters for UE, put them in the scheduled response and call - nr_ue_scheduled_response(&scheduled_response); - /////////////////////////phy_procedures_nr_ue_TX/////////////////////// - /////////// + nr_fill_ulsch(gNB,frame,slot,pusch_pdu); + int slot_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);// - (int)(800*factor); + int slot_length = slot_offset - frame_parms->get_samples_slot_timestamp(slot-1,frame_parms,0); - phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); + for (int i=0;i<(TBS>>3);i++) ulsch_ue[0]->harq_processes[harq_pid]->a[i]=i&0xff; + double scale = 1; - if (n_trials==1) - LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1); + if (input_fd == NULL) { - /////////// - //////////////////////////////////////////////////// - tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + if (SNR==snr0) { + // set FAPI parameters for UE, put them in the scheduled response and call + nr_ue_scheduled_response(&scheduled_response); + + + /////////////////////////phy_procedures_nr_ue_TX/////////////////////// + /////////// + + phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); + + + if (n_trials==1) { + LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_parms->samples_per_subframe*10,1,1); + LOG_M("txsig0F.m","txs0F", UE->common_vars.txdataF[0],frame_parms->ofdm_symbol_size*14,1,1); + } + /////////// + //////////////////////////////////////////////////// + tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + + txlev = signal_energy(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], + frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); + + txlev_float = (double)txlev/scale; // output of signal_energy is fixed point representation + + + //AWGN + } + } + else n_trials = 1; - txlev = signal_energy_amp_shift(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], - frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - txlev_float = (double)txlev/(double)AMP; // output of signal_energy is fixed point representation + sigma_dB = 10*log10(txlev_float)-SNR; + sigma = pow(10,sigma_dB/10); + printf("txlev_float %f, sigma_dB %f\n",10*log10(txlev_float),sigma_dB); n_errors = 0; n_false_positive = 0; - //AWGN - sigma_dB = 10*log10(txlev_float)-SNR; - sigma = pow(10,sigma_dB/10); + errors_scrambling = 0; + errors_decoding = 0; + int error_flag; for (trial = 0; trial < n_trials; trial++) { + + error_flag = 0; + //---------------------------------------------------------- + //------------------------ add noise ----------------------- + //---------------------------------------------------------- + if (input_fd == NULL ) { + for (i=0; inb_antennas_rx; ap++) { + ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i) + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)])/sqrt(scale) + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); // convert to fixed point + ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i)+1 + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)+1])/sqrt(scale) + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); + } + } + } + else { + AssertFatal(frame_parms->nb_antennas_rx == 1, "nb_ant != 1\n"); + // 800 samples is N_TA_OFFSET for FR1 @ 30.72 Ms/s, + AssertFatal(frame_parms->subcarrier_spacing==30000,"only 30 kHz for file input for now (%d)\n",frame_parms->subcarrier_spacing); + double factor = 1; + if (openair0_cfg[0].threequarter_fs== 1) factor =.75; + int ta_offset=1600; + if (N_RB_DL <217) ta_offset=800; + else if (N_RB_DL < 106) ta_offset = 400; - errors_scrambling = 0; - errors_decoding = 0; - - //---------------------------------------------------------- - //------------------------ add noise ----------------------- - //---------------------------------------------------------- - for (i=0; inb_antennas_rx; ap++) { - ((short*) gNB->common_vars.rxdata[ap])[(2*i) + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)*(double)AMP); // convert to fixed point - ((short*) gNB->common_vars.rxdata[ap])[2*i+1 + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)+1]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)*(double)AMP); - } - } - //////////////////////////////////////////////////////////// - - //---------------------------------------------------------- - //------------------- gNB phy procedures ------------------- - //---------------------------------------------------------- - gNB->UL_INFO.rx_ind.number_of_pdus = 0; - gNB->UL_INFO.crc_ind.number_crcs = 0; + fread((void*)&gNB->common_vars.rxdata[0][slot_offset], + sizeof(int16_t), + slot_length<<1, + input_fd); + for (int i=0;i<16;i+=2) printf("slot_offset %d : %d,%d\n", + slot_offset, + ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[i], + ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[1+i]); + fclose(input_fd); + } + //////////////////////////////////////////////////////////// + + //---------------------------------------------------------- + //------------------- gNB phy procedures ------------------- + //---------------------------------------------------------- + gNB->UL_INFO.rx_ind.number_of_pdus = 0; + gNB->UL_INFO.crc_ind.number_crcs = 0; start_meas(&gNB->phy_proc_rx); phy_procedures_gNB_common_RX(gNB, frame, slot); - if (n_trials==1) - LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0],frame_length_complex_samples_no_prefix,1,1); + if (n_trials==1) { + LOG_M("rxsig0.m","rx0",&gNB->common_vars.rxdata[0][0],frame_parms->samples_per_subframe*10,1,1); + LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0]+start_symbol*frame_parms->ofdm_symbol_size,nb_symb_sch*frame_parms->ofdm_symbol_size,1,1); + + } phy_procedures_gNB_uespec_RX(gNB, frame, slot); + if (n_trials == 1) { + LOG_M("rxsigF0_ext.m","rxsF0_ext", + &gNB->pusch_vars[0]->rxdataF_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); + LOG_M("chestF0.m","chF0", + &gNB->pusch_vars[0]->ul_ch_estimates[0][start_symbol*frame_parms->ofdm_symbol_size],frame_parms->ofdm_symbol_size,1,1); + LOG_M("chestF0_ext.m","chF0_ext", + &gNB->pusch_vars[0]->ul_ch_estimates_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); + LOG_M("rxsigF0_comp.m","rxsF0_comp", + &gNB->pusch_vars[0]->rxdataF_comp[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); + } start_meas(&gNB->phy_proc_rx); //////////////////////////////////////////////////////////// if (gNB->ulsch[0][0]->last_iteration_cnt >= - gNB->ulsch[0][0]->max_ldpc_iterations+1) + gNB->ulsch[0][0]->max_ldpc_iterations+1) { + error_flag = 1; n_errors++; - + } + //---------------------------------------------------------- //----------------- count and print errors ----------------- //---------------------------------------------------------- @@ -738,22 +865,30 @@ int main(int argc, char **argv) errors_decoding++; } } - - if (errors_decoding > 0) { + if (n_trials == 1) { + for (int r=0;rharq_processes[harq_pid]->C;r++) + for (int i=0;iharq_processes[harq_pid]->K>>3;i++) { + if ((ulsch_ue[0]->harq_processes[harq_pid]->c[r][i]^ulsch_gNB->harq_processes[harq_pid]->c[r][i]) != 0) printf("************"); + printf("r %d: in[%d] %x, out[%d] %x (%x)\n",r, + i,ulsch_ue[0]->harq_processes[harq_pid]->c[r][i], + i,ulsch_gNB->harq_processes[harq_pid]->c[r][i], + ulsch_ue[0]->harq_processes[harq_pid]->c[r][i]^ulsch_gNB->harq_processes[harq_pid]->c[r][i]); + } + } + if (errors_decoding > 0 && error_flag == 0) { n_false_positive++; if (n_trials==1) printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %u\n" "\x1B[0m", frame, trial, errors_decoding); } - } // trial loop printf("*****************************************\n"); - printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, n_trials); + printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%u\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, available_bits*n_trials); printf("\n"); printf("SNR %f: Channel BLER %e, Channel BER %e\n", SNR,(double)n_errors/n_trials,(double)errors_scrambling/available_bits/n_trials); printf("*****************************************\n"); printf("\n"); - + if (print_perf==1) { printDistribution(&gNB->phy_proc_rx,table_rx,"Total PHY proc rx"); printStatIndent(&gNB->ulsch_channel_estimation_stats,"ULSCH channel estimation time"); @@ -779,7 +914,6 @@ int main(int argc, char **argv) } } // SNR loop - printf("\n"); free(test_input_bit); diff --git a/openair1/SIMULATION/TOOLS/multipath_tv_channel.c b/openair1/SIMULATION/TOOLS/multipath_tv_channel.c index f4835570bf..d344992586 100644 --- a/openair1/SIMULATION/TOOLS/multipath_tv_channel.c +++ b/openair1/SIMULATION/TOOLS/multipath_tv_channel.c @@ -27,18 +27,20 @@ #include "SIMULATION/RF/rf.h" #include -void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length); +void tv_channel(channel_desc_t *desc,double complex ***H,uint32_t length); double frand_a_b(double a, double b); -void tv_conv(double complex **h, double complex *x, double complex *y, uint16_t nb_samples, uint8_t nb_taps, int delay); +void tv_conv(double complex **h, double complex *x, double complex *y, uint32_t nb_samples, uint8_t nb_taps, int delay); void multipath_tv_channel(channel_desc_t *desc, double **tx_sig_re, double **tx_sig_im, double **rx_sig_re, double **rx_sig_im, - uint16_t length, - uint8_t keep_channel) { - double complex **tx,**rx,* **H_t,*rx_temp; //, *tv_H_t; + uint32_t length, + uint8_t keep_channel) +{ + + double complex **tx,**rx,***H_t,*rx_temp;//, *tv_H_t; double path_loss = pow(10,desc->path_loss_dB/20); int i,j,k,dd; dd = abs(desc->channel_offset); @@ -126,7 +128,8 @@ void multipath_tv_channel(channel_desc_t *desc, } //TODO: make phi_rad a parameter of this function -void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length) { +void tv_channel(channel_desc_t *desc,double complex ***H,uint32_t length){ + int i,j,p,l,k; double *alpha,*phi_rad,pi=acos(-1),*w_Hz; alpha = (double *)calloc(desc->nb_paths,sizeof(double)); @@ -193,7 +196,8 @@ void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length) { } // time varying convolution -void tv_conv(double complex **h, double complex *x, double complex *y, uint16_t nb_samples, uint8_t nb_taps, int dd) { +void tv_conv(double complex **h, double complex *x, double complex *y, uint32_t nb_samples, uint8_t nb_taps, int dd){ + int i,j; for(i=0; i<((int)nb_samples-dd); i++) { diff --git a/openair1/SIMULATION/TOOLS/sim.h b/openair1/SIMULATION/TOOLS/sim.h index 0bc5975d99..6071e1e743 100644 --- a/openair1/SIMULATION/TOOLS/sim.h +++ b/openair1/SIMULATION/TOOLS/sim.h @@ -426,21 +426,12 @@ void multipath_tv_channel(channel_desc_t *desc, double **tx_sig_im, double **rx_sig_re, double **rx_sig_im, - uint16_t length, + uint32_t length, uint8_t keep_channel); /**@} */ /**@} */ -void rxAddInput( struct complex16 *input_sig, - struct complex16 *after_channel_sig, - int rxAnt, - channel_desc_t *channelDesc, - int nbSamples, - uint64_t TS, - uint32_t CirSize - ); - int modelid_fromname(char *modelname); double channelmod_get_snr_dB(void); double channelmod_get_sinr_dB(void); diff --git a/openair1/SIMULATION/TOOLS/taus.c b/openair1/SIMULATION/TOOLS/taus.c index 5fe0ce4d78..cdd4aebec3 100644 --- a/openair1/SIMULATION/TOOLS/taus.c +++ b/openair1/SIMULATION/TOOLS/taus.c @@ -21,7 +21,8 @@ #include #include -#include "SIMULATION/TOOLS/sim.h" +//#include "SIMULATION/TOOLS/sim.h" + unsigned int s0, s1, s2, b; diff --git a/openair2/COMMON/platform_constants.h b/openair2/COMMON/platform_constants.h index 1eb58b16b2..77f7e26c67 100644 --- a/openair2/COMMON/platform_constants.h +++ b/openair2/COMMON/platform_constants.h @@ -101,6 +101,7 @@ #define NUMBER_OF_NR_DLSCH_MAX 2//16 #define NUMBER_OF_NR_ULSCH_MAX 2//16 +#define NUMBER_OF_NR_PUCCH_MAX 2 #define NUMBER_OF_NR_SR_MAX 16 diff --git a/openair2/COMMON/s1ap_messages_def.h b/openair2/COMMON/s1ap_messages_def.h index 57201721ce..5e5794fc55 100644 --- a/openair2/COMMON/s1ap_messages_def.h +++ b/openair2/COMMON/s1ap_messages_def.h @@ -66,6 +66,7 @@ MESSAGE_DEF(S1AP_E_RAB_MODIFY_RESP , MESSAGE_PRIORITY_MED, s1ap_e_rab_m MESSAGE_DEF(S1AP_E_RAB_RELEASE_RESPONSE , MESSAGE_PRIORITY_MED, s1ap_e_rab_release_resp_t , s1ap_e_rab_release_resp) MESSAGE_DEF(S1AP_PATH_SWITCH_REQ , MESSAGE_PRIORITY_MED, s1ap_path_switch_req_t , s1ap_path_switch_req) MESSAGE_DEF(S1AP_PATH_SWITCH_REQ_ACK , MESSAGE_PRIORITY_MED, s1ap_path_switch_req_ack_t , s1ap_path_switch_req_ack) +MESSAGE_DEF(S1AP_E_RAB_MODIFICATION_IND , MESSAGE_PRIORITY_MED, s1ap_e_rab_modification_ind_t , s1ap_e_rab_modification_ind) /* S1AP -> RRC messages */ MESSAGE_DEF(S1AP_DOWNLINK_NAS , MESSAGE_PRIORITY_MED, s1ap_downlink_nas_t , s1ap_downlink_nas ) diff --git a/openair2/COMMON/s1ap_messages_types.h b/openair2/COMMON/s1ap_messages_types.h index 8e13e35d65..befab4ebdf 100644 --- a/openair2/COMMON/s1ap_messages_types.h +++ b/openair2/COMMON/s1ap_messages_types.h @@ -45,6 +45,7 @@ #define S1AP_E_RAB_MODIFY_RESP(mSGpTR) (mSGpTR)->ittiMsg.s1ap_e_rab_modify_resp #define S1AP_PATH_SWITCH_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_path_switch_req #define S1AP_PATH_SWITCH_REQ_ACK(mSGpTR) (mSGpTR)->ittiMsg.s1ap_path_switch_req_ack +#define S1AP_E_RAB_MODIFICATION_IND(mSGpTR) (mSGpTR)->ittiMsg.s1ap_e_rab_modification_ind #define S1AP_DOWNLINK_NAS(mSGpTR) (mSGpTR)->ittiMsg.s1ap_downlink_nas #define S1AP_INITIAL_CONTEXT_SETUP_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_initial_context_setup_req @@ -277,12 +278,26 @@ typedef struct e_rab_tobe_added_s { uint8_t drb_ID; /* The transport layer address for the IP packets */ - transport_layer_addr_t eNB_addr; + transport_layer_addr_t sgw_addr; /* S-GW Tunnel endpoint identifier */ uint32_t gtp_teid; } e_rab_tobe_added_t; +typedef struct e_rab_admitted_tobe_added_s { + /* Unique e_rab_id for the UE. */ + uint8_t e_rab_id; + + /* Unique drb_ID for the UE. */ + uint8_t drb_ID; + + /* The transport layer address for the IP packets */ + transport_layer_addr_t gnb_addr; + + /* S-GW Tunnel endpoint identifier */ + uint32_t gtp_teid; +} e_rab_admitted_tobe_added_t; + typedef struct e_rab_tobeswitched_s { @@ -642,6 +657,27 @@ typedef struct s1ap_path_switch_req_ack_s { } s1ap_path_switch_req_ack_t; +typedef struct s1ap_e_rab_modification_ind_s { + + unsigned eNB_ue_s1ap_id:24; + + /* MME UE id */ + uint32_t mme_ue_s1ap_id; + + /* Number of e_rab setup-ed in the list */ + uint8_t nb_of_e_rabs_tobemodified; + + uint8_t nb_of_e_rabs_nottobemodified; + + /* list of e_rab setup-ed by RRC layers */ + e_rab_setup_t e_rabs_tobemodified[S1AP_MAX_E_RAB]; + + e_rab_setup_t e_rabs_nottobemodified[S1AP_MAX_E_RAB]; + + uint16_t ue_initial_id; + +} s1ap_e_rab_modification_ind_t; + // S1AP --> RRC messages typedef struct s1ap_ue_release_command_s { diff --git a/openair2/COMMON/x2ap_messages_types.h b/openair2/COMMON/x2ap_messages_types.h index ed3470a7d6..f0743e60a5 100644 --- a/openair2/COMMON/x2ap_messages_types.h +++ b/openair2/COMMON/x2ap_messages_types.h @@ -315,7 +315,7 @@ typedef struct x2ap_senb_addition_req_ack_s { typedef struct x2ap_ENDC_sgnb_addition_req_s { int ue_x2_id; - + LTE_PhysCellId_t target_physCellId; /* used for RRC->X2AP in source eNB */ int rnti; @@ -363,7 +363,7 @@ typedef struct x2ap_ENDC_sgnb_addition_req_ACK_s { uint8_t nb_e_rabs_admitted_tobeadded; /* list of e_rab to be added by RRC layers */ - e_rab_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB]; + e_rab_admitted_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB]; /* list of e_rab to be setup by RRC layers */ e_rab_t e_rab_param[S1AP_MAX_E_RAB]; @@ -386,6 +386,7 @@ typedef struct x2ap_ENDC_reconf_complete_s { int MeNB_ue_x2_id; int SgNB_ue_x2_id; + LTE_PhysCellId_t target_physCellId; x2ap_sgNB_reconf_response_information_t reconf_response; diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 975ac4e96f..f1daacbb65 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -49,18 +49,13 @@ struct lfds700_misc_prng_state ps[NUM_MAX_ENB]; struct lfds700_ringbuffer_element *dl_mac_config_array[NUM_MAX_ENB]; struct lfds700_ringbuffer_state ringbuffer_state[NUM_MAX_ENB]; -/* the slice config as kept in the underlying system */ -Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES]; -/* a structure that keeps updates which will be reflected in slice_config later */ -Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES]; -/* indicates whether sc_update contains new data */ -int perform_slice_config_update_count = 1; -/* queue of incoming new UE<>slice association commands */ -Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES]; -int n_ue_slice_assoc_updates = 0; -/* mutex for sc_update: do not receive new config and write it at the same time */ -pthread_mutex_t sc_update_mtx = PTHREAD_MUTEX_INITIALIZER; +/* Ringbuffer-related to slice configuration */ +struct lfds700_ringbuffer_element *slice_config_array[NUM_MAX_ENB]; +struct lfds700_ringbuffer_state slice_config_ringbuffer_state[NUM_MAX_ENB]; +/* Ringbuffer-related to slice configuration */ +struct lfds700_ringbuffer_element *ue_assoc_array[NUM_MAX_ENB]; +struct lfds700_ringbuffer_state ue_assoc_ringbuffer_state[NUM_MAX_ENB]; int flexran_agent_mac_stats_reply_ue(mid_t mod_id, Protocol__FlexUeStatsReport **ue_report, @@ -1354,6 +1349,33 @@ void flexran_agent_init_mac_agent(mid_t mod_id) { AssertFatal(i == 0, "posix_memalign(): could not allocate aligned memory for lfds library\n"); lfds700_ringbuffer_init_valid_on_current_logical_core(&ringbuffer_state[mod_id], dl_mac_config_array[mod_id], num_elements, &ps[mod_id], NULL); + + struct lfds700_misc_prng_state scrng; + i = posix_memalign((void **) &slice_config_array[mod_id], + LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES, + sizeof(struct lfds700_ringbuffer_element) * num_elements); + AssertFatal(i == 0, + "posix_memalign(): could not allocate aligned memory\n"); + lfds700_ringbuffer_init_valid_on_current_logical_core( + &slice_config_ringbuffer_state[mod_id], + slice_config_array[mod_id], + num_elements, + &scrng, + NULL); + + struct lfds700_misc_prng_state uarng; + i = posix_memalign((void **) &ue_assoc_array[mod_id], + LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES, + sizeof(struct lfds700_ringbuffer_element) * num_elements); + AssertFatal(i == 0, + "posix_memalign(): could not allocate aligned memory\n"); + lfds700_ringbuffer_init_valid_on_current_logical_core( + &ue_assoc_ringbuffer_state[mod_id], + ue_assoc_array[mod_id], + num_elements, + &uarng, + NULL); + for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { for (j = 0; j < 8; j++) { if (RC.mac && RC.mac[mod_id]) @@ -1465,9 +1487,74 @@ void flexran_agent_fill_mac_cell_config(mid_t mod_id, uint8_t cc_id, conf->si_config->has_sfn = 1; } - /* get a pointer to the config which is maintained in the agent throughout - * its lifetime */ - conf->slice_config = flexran_agent_get_slice_config(mod_id); + conf->slice_config = malloc(sizeof(Protocol__FlexSliceConfig)); + if (conf->slice_config) { + protocol__flex_slice_config__init(conf->slice_config); + Protocol__FlexSliceConfig *sc = conf->slice_config; + + sc->dl = malloc(sizeof(Protocol__FlexSliceDlUlConfig)); + DevAssert(sc->dl); + protocol__flex_slice_dl_ul_config__init(sc->dl); + sc->dl->algorithm = flexran_get_dl_slice_algo(mod_id); + sc->dl->has_algorithm = 1; + sc->dl->n_slices = flexran_get_num_dl_slices(mod_id); + if (sc->dl->n_slices > 0) { + sc->dl->slices = calloc(sc->dl->n_slices, sizeof(Protocol__FlexSlice *)); + DevAssert(sc->dl->slices); + for (int i = 0; i < sc->dl->n_slices; ++i) { + sc->dl->slices[i] = malloc(sizeof(Protocol__FlexSlice)); + DevAssert(sc->dl->slices[i]); + protocol__flex_slice__init(sc->dl->slices[i]); + flexran_get_dl_slice(mod_id, i, sc->dl->slices[i], sc->dl->algorithm); + } + } else { + sc->dl->scheduler = flexran_get_dl_scheduler_name(mod_id); + } + + sc->ul = malloc(sizeof(Protocol__FlexSliceDlUlConfig)); + DevAssert(sc->ul); + protocol__flex_slice_dl_ul_config__init(sc->ul); + sc->ul->algorithm = flexran_get_ul_slice_algo(mod_id); + sc->ul->has_algorithm = 1; + sc->ul->n_slices = flexran_get_num_ul_slices(mod_id); + if (sc->ul->n_slices > 0) { + sc->ul->slices = calloc(sc->ul->n_slices, sizeof(Protocol__FlexSlice *)); + DevAssert(sc->ul->slices); + for (int i = 0; i < sc->ul->n_slices; ++i) { + sc->ul->slices[i] = malloc(sizeof(Protocol__FlexSlice)); + DevAssert(sc->ul->slices[i]); + protocol__flex_slice__init(sc->ul->slices[i]); + flexran_get_ul_slice(mod_id, i, sc->ul->slices[i], sc->ul->algorithm); + } + } else { + sc->ul->scheduler = flexran_get_ul_scheduler_name(mod_id); + } + } +} + +void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf) { + Protocol__FlexSliceConfig *sc = conf->slice_config; + for (int i = 0; i < sc->dl->n_slices; ++i) { + free(sc->dl->slices[i]); + sc->dl->slices[i] = NULL; + /* scheduler names are not freed: we assume we read them directly from the + * underlying memory and do not dispose it */ + } + free(sc->dl->slices); + /* scheduler name is not freed */ + free(sc->dl); + sc->dl = NULL; + for (int i = 0; i < sc->ul->n_slices; ++i) { + free(sc->ul->slices[i]); + sc->ul->slices[i] = NULL; + /* scheduler names are not freed */ + } + free(sc->ul->slices); + /* scheduler name is not freed */ + free(sc->ul); + sc->ul = NULL; + free(conf->slice_config); + conf->slice_config = NULL; } void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id, @@ -1481,10 +1568,12 @@ void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id, ue_conf->rnti = flexran_get_mac_ue_crnti(mod_id, ue_id); ue_conf->has_rnti = 1; - ue_conf->dl_slice_id = flexran_get_ue_dl_slice_id(mod_id, ue_id); - ue_conf->has_dl_slice_id = 1; - ue_conf->ul_slice_id = flexran_get_ue_ul_slice_id(mod_id, ue_id); - ue_conf->has_ul_slice_id = 1; + int dl_id = flexran_get_ue_dl_slice_id(mod_id, ue_id); + ue_conf->dl_slice_id = dl_id; + ue_conf->has_dl_slice_id = dl_id >= 0; + int ul_id = flexran_get_ue_ul_slice_id(mod_id, ue_id); + ue_conf->ul_slice_id = ul_id; + ue_conf->has_ul_slice_id = ul_id >= 0; ue_conf->ue_aggregated_max_bitrate_ul = flexran_get_ue_aggregated_max_bitrate_ul(mod_id, ue_id); ue_conf->has_ue_aggregated_max_bitrate_ul = 1; @@ -1565,6 +1654,15 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) LOG_E(FLEXRAN_AGENT, "MAC agent CM for eNB %d is not registered\n", mod_id); return -1; } + + lfds700_ringbuffer_cleanup(&ringbuffer_state[mod_id], NULL ); + free(dl_mac_config_array[mod_id]); + lfds700_ringbuffer_cleanup(&slice_config_ringbuffer_state[mod_id], NULL ); + free(slice_config_array[mod_id]); + lfds700_ringbuffer_cleanup(&ue_assoc_ringbuffer_state[mod_id], NULL ); + free(ue_assoc_array[mod_id]); + lfds700_misc_library_cleanup(); + AGENT_MAC_xface *xface = agent_mac_xface[mod_id]; xface->flexran_agent_send_sr_info = NULL; xface->flexran_agent_send_sf_trigger = NULL; @@ -1579,234 +1677,91 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) return 0; } -AGENT_MAC_xface *flexran_agent_get_mac_xface(mid_t mod_id) -{ - return agent_mac_xface[mod_id]; +void helper_destroy_mac_slice_config(Protocol__FlexSliceConfig *slice_config) { + if (slice_config->dl) { + if (slice_config->dl->scheduler) + free(slice_config->dl->scheduler); + for (int i = 0; i < slice_config->dl->n_slices; i++) + if (slice_config->dl->slices[i]->scheduler) + free(slice_config->dl->slices[i]->scheduler); + } + if (slice_config->ul) { + if (slice_config->ul->scheduler) + free(slice_config->ul->scheduler); + for (int i = 0; i < slice_config->ul->n_slices; i++) + if (slice_config->ul->slices[i]->scheduler) + free(slice_config->ul->slices[i]->scheduler); + } + + Protocol__FlexCellConfig helper; + helper.slice_config = slice_config; + flexran_agent_destroy_mac_slice_config(&helper); } -void flexran_create_config_structures(mid_t mod_id) -{ - int i; - int n_dl = flexran_get_num_dl_slices(mod_id); - int m_ul = flexran_get_num_ul_slices(mod_id); - slice_config[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); - sc_update[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); - if (!slice_config[mod_id] || !sc_update[mod_id]) return; +void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice_config) { + if (!*slice_config) return; + /* just use the memory and set to NULL in original */ + Protocol__FlexSliceConfig *sc = *slice_config; + *slice_config = NULL; - flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); - for (i = 0; i < n_dl; i++) { - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); - } - for (i = 0; i < m_ul; i++) { - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + enum lfds700_misc_flag overwrite_occurred_flag; + + Protocol__FlexSliceConfig *overwritten_sc; + lfds700_ringbuffer_write(&slice_config_ringbuffer_state[mod_id], + NULL, + (void *)sc, + &overwrite_occurred_flag, + NULL, + (void **)&overwritten_sc, + &ls); + + if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) { + helper_destroy_mac_slice_config(overwritten_sc); + LOG_E(FLEXRAN_AGENT, "lost slice config: too many reconfigurations at once\n"); } } -void flexran_check_and_remove_slices(mid_t mod_id) -{ - Protocol__FlexDlSlice **dl = sc_update[mod_id]->dl; - Protocol__FlexDlSlice **dlreal = slice_config[mod_id]->dl; - int i = 0; - while (i < sc_update[mod_id]->n_dl) { - /* remove slices whose percentage is zero */ - if (dl[i]->percentage > 0) { - ++i; - continue; - } - if (flexran_remove_dl_slice(mod_id, i) < 1) { - LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n", - mod_id, i, dl[i]->id); - ++i; - continue; - } - LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n", - mod_id, i, dl[i]->id); - if (dl[i]->n_sorting > 0) free(dl[i]->sorting); - free(dl[i]->scheduler_name); - if (dlreal[i]->n_sorting > 0) { - dlreal[i]->n_sorting = 0; - free(dlreal[i]->sorting); - } - free(dlreal[i]->scheduler_name); - --sc_update[mod_id]->n_dl; - --slice_config[mod_id]->n_dl; - const size_t last = sc_update[mod_id]->n_dl; - /* we need to memcpy the higher slice to the position we just deleted */ - memcpy(dl[i], dl[last], sizeof(*dl[last])); - memset(dl[last], 0, sizeof(*dl[last])); - memcpy(dlreal[i], dlreal[last], sizeof(*dlreal[last])); - memset(dlreal[last], 0, sizeof(*dlreal[last])); - /* dont increase i but recheck the slice which has been copied to here */ - } - Protocol__FlexUlSlice **ul = sc_update[mod_id]->ul; - Protocol__FlexUlSlice **ulreal = slice_config[mod_id]->ul; - i = 0; - while (i < sc_update[mod_id]->n_ul) { - if (ul[i]->percentage > 0) { - ++i; - continue; - } - if (flexran_remove_ul_slice(mod_id, i) < 1) { - LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n", - mod_id, i, ul[i]->id); - ++i; - continue; - } - LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n", - mod_id, i, ul[i]->id); - free(ul[i]->scheduler_name); - free(ulreal[i]->scheduler_name); - --sc_update[mod_id]->n_ul; - --slice_config[mod_id]->n_ul; - const size_t last = sc_update[mod_id]->n_ul; - /* see DL remarks */ - memcpy(ul[i], ul[last], sizeof(*ul[last])); - memset(ul[last], 0, sizeof(*ul[last])); - memcpy(ulreal[i], ulreal[last], sizeof(*ulreal[last])); - memset(ulreal[last], 0, sizeof(*ulreal[last])); - /* dont increase i but recheck the slice which has been copied to here */ +void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config) { + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + enum lfds700_misc_flag overwrite_occurred_flag; + + Protocol__FlexUeConfig *overwritten_ue_config; + lfds700_ringbuffer_write(&ue_assoc_ringbuffer_state[mod_id], + NULL, + (void *) *ue_config, + &overwrite_occurred_flag, + NULL, + (void **)&overwritten_ue_config, + &ls); + + if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) { + free(overwritten_ue_config); + LOG_E(FLEXRAN_AGENT, "lost UE-slice association: too many UE-slice associations at once\n"); } } -void flexran_agent_slice_update(mid_t mod_id) -{ - int i; - int changes = 0; +void flexran_agent_slice_update(mid_t mod_id) { + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); - if (perform_slice_config_update_count <= 0) return; - perform_slice_config_update_count--; - - pthread_mutex_lock(&sc_update_mtx); - - if (!slice_config[mod_id]) { - /* if the configuration does not exist for agent, create from eNB structure - * and exit */ - flexran_create_config_structures(mod_id); - pthread_mutex_unlock(&sc_update_mtx); - return; + Protocol__FlexSliceConfig *sc = NULL; + struct lfds700_ringbuffer_state *state = &slice_config_ringbuffer_state[mod_id]; + if (lfds700_ringbuffer_read(state, NULL, (void **) &sc, &ls) != 0) { + apply_update_dl_slice_config(mod_id, sc->dl); + apply_update_ul_slice_config(mod_id, sc->ul); + helper_destroy_mac_slice_config(sc); } - /********* read existing config *********/ - /* simply update slice_config all the time and write new config - * (apply_new_slice_dl_config() only updates if changes are necessary) */ - slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id); - slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id); - for (i = 0; i < slice_config[mod_id]->n_dl; i++) { - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); + Protocol__FlexUeConfig *ue_config = NULL; + state = &ue_assoc_ringbuffer_state[mod_id]; + if (lfds700_ringbuffer_read(state, NULL, (void **) &ue_config, &ls) != 0) { + apply_ue_slice_assoc_update(mod_id, ue_config); + free(ue_config); } - for (i = 0; i < slice_config[mod_id]->n_ul; i++) { - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - } - - /********* write new config *********/ - /* check for removal (sc_update[X]->dl[Y].percentage == 0) - * and update sc_update & slice_config accordingly */ - flexran_check_and_remove_slices(mod_id); - - /* create new DL and UL slices if necessary */ - for (i = slice_config[mod_id]->n_dl; i < sc_update[mod_id]->n_dl; i++) { - flexran_create_dl_slice(mod_id, sc_update[mod_id]->dl[i]->id); - } - for (i = slice_config[mod_id]->n_ul; i < sc_update[mod_id]->n_ul; i++) { - flexran_create_ul_slice(mod_id, sc_update[mod_id]->ul[i]->id); - } - slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id); - slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id); - changes += apply_new_slice_config(mod_id, slice_config[mod_id], sc_update[mod_id]); - for (i = 0; i < slice_config[mod_id]->n_dl; i++) { - changes += apply_new_slice_dl_config(mod_id, - slice_config[mod_id]->dl[i], - sc_update[mod_id]->dl[i]); - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - } - for (i = 0; i < slice_config[mod_id]->n_ul; i++) { - changes += apply_new_slice_ul_config(mod_id, - slice_config[mod_id]->ul[i], - sc_update[mod_id]->ul[i]); - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - } - flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - if (n_ue_slice_assoc_updates > 0) { - changes += apply_ue_slice_assoc_update(mod_id); - } - if (changes > 0) - LOG_I(FLEXRAN_AGENT, "[%d] slice configuration: applied %d changes\n", mod_id, changes); - - pthread_mutex_unlock(&sc_update_mtx); -} - -Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) -{ - if (!slice_config[mod_id]) return NULL; - Protocol__FlexSliceConfig *config = NULL; - - pthread_mutex_lock(&sc_update_mtx); - config = flexran_agent_create_slice_config(slice_config[mod_id]->n_dl, - slice_config[mod_id]->n_ul); - if (!config) { - pthread_mutex_unlock(&sc_update_mtx); - return NULL; - } - config->has_intraslice_share_active = 1; - config->intraslice_share_active = slice_config[mod_id]->intraslice_share_active; - config->has_interslice_share_active = 1; - config->interslice_share_active = slice_config[mod_id]->interslice_share_active; - for (int i = 0; i < slice_config[mod_id]->n_dl; ++i) { - if (!config->dl[i]) continue; - config->dl[i]->has_id = 1; - config->dl[i]->id = slice_config[mod_id]->dl[i]->id; - config->dl[i]->has_label = 1; - config->dl[i]->label = slice_config[mod_id]->dl[i]->label; - config->dl[i]->has_percentage = 1; - config->dl[i]->percentage = slice_config[mod_id]->dl[i]->percentage; - config->dl[i]->has_isolation = 1; - config->dl[i]->isolation = slice_config[mod_id]->dl[i]->isolation; - config->dl[i]->has_priority = 1; - config->dl[i]->priority = slice_config[mod_id]->dl[i]->priority; - config->dl[i]->has_position_low = 1; - config->dl[i]->position_low = slice_config[mod_id]->dl[i]->position_low; - config->dl[i]->has_position_high = 1; - config->dl[i]->position_high = slice_config[mod_id]->dl[i]->position_high; - config->dl[i]->has_maxmcs = 1; - config->dl[i]->maxmcs = slice_config[mod_id]->dl[i]->maxmcs; - config->dl[i]->n_sorting = slice_config[mod_id]->dl[i]->n_sorting; - config->dl[i]->sorting = calloc(config->dl[i]->n_sorting, sizeof(Protocol__FlexDlSorting)); - if (!config->dl[i]->sorting) config->dl[i]->n_sorting = 0; - for (int j = 0; j < config->dl[i]->n_sorting; ++j) - config->dl[i]->sorting[j] = slice_config[mod_id]->dl[i]->sorting[j]; - config->dl[i]->has_accounting = 1; - config->dl[i]->accounting = slice_config[mod_id]->dl[i]->accounting; - config->dl[i]->scheduler_name = strdup(slice_config[mod_id]->dl[i]->scheduler_name); - } - for (int i = 0; i < slice_config[mod_id]->n_ul; ++i) { - if (!config->ul[i]) continue; - config->ul[i]->has_id = 1; - config->ul[i]->id = slice_config[mod_id]->ul[i]->id; - config->ul[i]->has_label = 1; - config->ul[i]->label = slice_config[mod_id]->ul[i]->label; - config->ul[i]->has_percentage = 1; - config->ul[i]->percentage = slice_config[mod_id]->ul[i]->percentage; - config->ul[i]->has_isolation = 1; - config->ul[i]->isolation = slice_config[mod_id]->ul[i]->isolation; - config->ul[i]->has_priority = 1; - config->ul[i]->priority = slice_config[mod_id]->ul[i]->priority; - config->ul[i]->has_first_rb = 1; - config->ul[i]->first_rb = slice_config[mod_id]->ul[i]->first_rb; - config->ul[i]->has_maxmcs = 1; - config->ul[i]->maxmcs = slice_config[mod_id]->ul[i]->maxmcs; - config->ul[i]->n_sorting = slice_config[mod_id]->ul[i]->n_sorting; - config->ul[i]->sorting = calloc(config->ul[i]->n_sorting, sizeof(Protocol__FlexUlSorting)); - if (!config->ul[i]->sorting) config->ul[i]->n_sorting = 0; - for (int j = 0; j < config->ul[i]->n_sorting; ++j) - config->ul[i]->sorting[j] = slice_config[mod_id]->ul[i]->sorting[j]; - config->ul[i]->has_accounting = 1; - config->ul[i]->accounting = slice_config[mod_id]->ul[i]->accounting; - config->ul[i]->scheduler_name = strdup(slice_config[mod_id]->ul[i]->scheduler_name); - } - - pthread_mutex_unlock(&sc_update_mtx); - return config; } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h index 2f9f99c740..5a8d4f31aa 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h @@ -115,7 +115,16 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id); /* Inform controller about possibility to update slice configuration */ void flexran_agent_slice_update(mid_t mod_id); -/* return a pointer to the current config */ -Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id); +/* marks slice_config so that it can be applied later. Takes ownership of the + * FlexSliceConfig message */ +void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice); + +/* inserts a new ue_config into the structure keeping ue to slice association + * updates and marks so it can be applied. Takes ownership of the FlexUeConfig message */ +void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config); + +/* free slice_config part of flexCellConfig, filled in + * flexran_agent_fill_mac_cell_config() */ +void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf); #endif diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index a85cbac543..93de0b11ec 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -33,14 +33,6 @@ #include "flexran_agent_mac_internal.h" #include "flexran_agent_mac_slice_verification.h" -/* from flexran_agent_mac.c */ -extern Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES]; -extern Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES]; -extern int perform_slice_config_update_count; -extern Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES]; -extern int n_ue_slice_assoc_updates; -extern pthread_mutex_t sc_update_mtx; - Protocol__FlexranMessage * flexran_agent_generate_diff_mac_stats_report(Protocol__FlexranMessage *new_message, Protocol__FlexranMessage *old_message) { @@ -1033,724 +1025,166 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name) { } -Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) -{ - int i; - Protocol__FlexSliceConfig *fsc = malloc(sizeof(Protocol__FlexSliceConfig)); - if (!fsc) return NULL; - protocol__flex_slice_config__init(fsc); - - /* say there are n_dl slices but reserve memory for up to MAX_NUM_SLICES so - * we don't need to reserve again later */ - fsc->n_dl = n_dl; - fsc->dl = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexDlSlice *)); - if (!fsc->dl) fsc->n_dl = 0; - for (i = 0; i < MAX_NUM_SLICES; i++) { - fsc->dl[i] = malloc(sizeof(Protocol__FlexDlSlice)); - if (!fsc->dl[i]) continue; - protocol__flex_dl_slice__init(fsc->dl[i]); - } - - /* as above */ - fsc->n_ul = m_ul; - fsc->ul = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexUlSlice *)); - if (!fsc->ul) fsc->n_ul = 0; - for (i = 0; i < MAX_NUM_SLICES; i++) { - fsc->ul[i] = malloc(sizeof(Protocol__FlexUlSlice)); - if (!fsc->ul[i]) continue; - protocol__flex_ul_slice__init(fsc->ul[i]); - } - return fsc; -} - -void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s) -{ - s->intraslice_share_active = flexran_get_intraslice_sharing_active(mod_id); - s->has_intraslice_share_active = 1; - s->interslice_share_active = flexran_get_interslice_sharing_active(mod_id); - s->has_interslice_share_active = 1; -} - -void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice) -{ - dl_slice->id = flexran_get_dl_slice_id(mod_id, slice_idx); - dl_slice->has_id = 1; - /* read label from corresponding sc_update entry or give default */ - dl_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB; - dl_slice->has_label = 1; - for (int i = 0; i < sc_update[mod_id]->n_dl; i++) { - if (sc_update[mod_id]->dl[i]->id == dl_slice->id - && sc_update[mod_id]->dl[i]->has_label) { - dl_slice->label = sc_update[mod_id]->dl[i]->label; - break; - } - } - dl_slice->percentage = flexran_get_dl_slice_percentage(mod_id, slice_idx); - dl_slice->has_percentage = 1; - dl_slice->isolation = flexran_get_dl_slice_isolation(mod_id, slice_idx); - dl_slice->has_isolation = 1; - dl_slice->priority = flexran_get_dl_slice_priority(mod_id, slice_idx); - dl_slice->has_priority = 1; - dl_slice->position_low = flexran_get_dl_slice_position_low(mod_id, slice_idx); - dl_slice->has_position_low = 1; - dl_slice->position_high = flexran_get_dl_slice_position_high(mod_id, slice_idx); - dl_slice->has_position_high = 1; - dl_slice->maxmcs = flexran_get_dl_slice_maxmcs(mod_id, slice_idx); - dl_slice->has_maxmcs = 1; - dl_slice->n_sorting = flexran_get_dl_slice_sorting(mod_id, slice_idx, &dl_slice->sorting); - if (dl_slice->n_sorting < 1) dl_slice->sorting = NULL; - dl_slice->accounting = flexran_get_dl_slice_accounting_policy(mod_id, slice_idx); - dl_slice->has_accounting = 1; - const char *s_name = flexran_get_dl_slice_scheduler(mod_id, slice_idx); - if (!dl_slice->scheduler_name - || strcmp(dl_slice->scheduler_name, s_name) != 0) { - dl_slice->scheduler_name = realloc(dl_slice->scheduler_name, strlen(s_name) + 1); - strcpy(dl_slice->scheduler_name, s_name); - } -} - -void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice) -{ - ul_slice->id = flexran_get_ul_slice_id(mod_id, slice_idx); - ul_slice->has_id = 1; - /* read label from corresponding sc_update entry or give default */ - ul_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB; - ul_slice->has_label = 1; - for (int i = 0; i < sc_update[mod_id]->n_ul; i++) { - if (sc_update[mod_id]->ul[i]->id == ul_slice->id - && sc_update[mod_id]->ul[i]->has_label) { - ul_slice->label = sc_update[mod_id]->ul[i]->label; - break; - } - } - ul_slice->percentage = flexran_get_ul_slice_percentage(mod_id, slice_idx); - ul_slice->has_percentage = 1; - /*ul_slice->isolation = flexran_get_ul_slice_isolation(mod_id, slice_idx);*/ - ul_slice->has_isolation = 0; - /*ul_slice->priority = flexran_get_ul_slice_priority(mod_id, slice_idx);*/ - ul_slice->has_priority = 0; - ul_slice->first_rb = flexran_get_ul_slice_first_rb(mod_id, slice_idx); - ul_slice->has_first_rb = 1; - /*ul_slice-> = flexran_get_ul_slice_length_rb(mod_id, slice_idx); - ul_slice->has_length_rb = 0;*/ - ul_slice->maxmcs = flexran_get_ul_slice_maxmcs(mod_id, slice_idx); - ul_slice->has_maxmcs = 1; - ul_slice->n_sorting = 0; - /*if (ul_slice->sorting) { - free(ul_slice->sorting); - ul_slice->sorting = NULL; - } - ul_slice->n_sorting = flexran_get_ul_slice_sorting(mod_id, slice_idx, &ul_slice->sorting); - if (ul_slice->n_sorting < 1) ul_slice->sorting = NULL;*/ - /*ul_slice->accounting = flexran_get_ul_slice_accounting_policy(mod_id, slice_idx);*/ - ul_slice->has_accounting = 0; - const char *s_name = flexran_get_ul_slice_scheduler(mod_id, slice_idx); - if (!ul_slice->scheduler_name - || strcmp(ul_slice->scheduler_name, s_name) != 0) { - ul_slice->scheduler_name = realloc(ul_slice->scheduler_name, strlen(s_name) + 1); - strcpy(ul_slice->scheduler_name, s_name); - } -} - -int check_dl_sorting_update(Protocol__FlexDlSlice *old, Protocol__FlexDlSlice *new) -{ - /* sorting_update => true when old->n_sorting == 0 or different numbers of - * elements; otherwise will check * element-wise */ - int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting); - for (int i = 0; i < old->n_sorting && !sorting_update; ++i) { - sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]); - } - return sorting_update; -} - -int check_ul_sorting_update(Protocol__FlexUlSlice *old, Protocol__FlexUlSlice *new) -{ - /* sorting_update => true when old->n_sorting == 0 or different numbers of - * elements; otherwise will check * element-wise */ - int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting); - for (int i = 0; i < old->n_sorting && !sorting_update; ++i) { - sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]); - } - return sorting_update; -} - -void overwrite_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *exist, Protocol__FlexSliceConfig *update) -{ - if (update->has_intraslice_share_active - && exist->intraslice_share_active != update->intraslice_share_active) { - LOG_I(FLEXRAN_AGENT, "[%d] update intraslice_share_active: %d -> %d\n", - mod_id, exist->intraslice_share_active, update->intraslice_share_active); - exist->intraslice_share_active = update->intraslice_share_active; - exist->has_intraslice_share_active = 1; - } - if (update->has_interslice_share_active - && exist->interslice_share_active != update->interslice_share_active) { - LOG_I(FLEXRAN_AGENT, "[%d] update interslice_share_active: %d -> %d\n", - mod_id, exist->interslice_share_active, update->interslice_share_active); - exist->interslice_share_active = update->interslice_share_active; - exist->has_interslice_share_active = 1; - } -} - -void overwrite_slice_config_dl(mid_t mod_id, Protocol__FlexDlSlice *exist, Protocol__FlexDlSlice *update) -{ - if (update->label != exist->label) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update label: %d -> %d\n", - mod_id, update->id, exist->label, update->label); - exist->label = update->label; - exist->has_label = 1; - } - if (update->percentage != exist->percentage) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update percentage: %d -> %d\n", - mod_id, update->id, exist->percentage, update->percentage); - exist->percentage = update->percentage; - exist->has_percentage = 1; - } - if (update->isolation != exist->isolation) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update isolation: %d -> %d\n", - mod_id, update->id, exist->isolation, update->isolation); - exist->isolation = update->isolation; - exist->has_isolation = 1; - } - if (update->priority != exist->priority) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update priority: %d -> %d\n", - mod_id, update->id, exist->priority, update->priority); - exist->priority = update->priority; - exist->has_priority = 1; - } - if (update->position_low != exist->position_low) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_low: %d -> %d\n", - mod_id, update->id, exist->position_low, update->position_low); - exist->position_low = update->position_low; - exist->has_position_low = 1; - } - if (update->position_high != exist->position_high) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_high: %d -> %d\n", - mod_id, update->id, exist->position_high, update->position_high); - exist->position_high = update->position_high; - exist->has_position_high = 1; - } - if (update->maxmcs != exist->maxmcs) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update maxmcs: %d -> %d\n", - mod_id, update->id, exist->maxmcs, update->maxmcs); - exist->maxmcs = update->maxmcs; - exist->has_maxmcs = 1; - } - if (check_dl_sorting_update(exist, update)) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update sorting array\n", mod_id, update->id); - if (exist->n_sorting != update->n_sorting) { - exist->n_sorting = update->n_sorting; - exist->sorting = realloc(exist->sorting, exist->n_sorting * sizeof(Protocol__FlexDlSorting)); - if (!exist->sorting) exist->n_sorting = 0; - } - for (int i = 0; i < exist->n_sorting; i++) - exist->sorting[i] = update->sorting[i]; - } - if (update->accounting != exist->accounting) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update accounting: %d -> %d\n", - mod_id, update->id, exist->accounting, update->accounting); - exist->accounting = update->accounting; - exist->has_accounting = 1; - } - if (!exist->scheduler_name - || strcmp(update->scheduler_name, exist->scheduler_name) != 0) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update scheduler: %s -> %s\n", - mod_id, update->id, exist->scheduler_name, update->scheduler_name); - if (exist->scheduler_name) free(exist->scheduler_name); - exist->scheduler_name = strdup(update->scheduler_name); - } -} - -void overwrite_slice_config_ul(mid_t mod_id, Protocol__FlexUlSlice *exist, Protocol__FlexUlSlice *update) -{ - if (update->label != exist->label) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update label: %d -> %d\n", - mod_id, update->id, exist->label, update->label); - exist->label = update->label; - exist->has_label = 1; - } - if (update->percentage != exist->percentage) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update percentage: %d -> %d\n", - mod_id, update->id, exist->percentage, update->percentage); - exist->percentage = update->percentage; - exist->has_percentage = 1; - } - if (update->isolation != exist->isolation) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update isolation: %d -> %d\n", - mod_id, update->id, exist->isolation, update->isolation); - exist->isolation = update->isolation; - exist->has_isolation = 1; - } - if (update->priority != exist->priority) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update priority: %d -> %d\n", - mod_id, update->id, exist->priority, update->priority); - exist->priority = update->priority; - exist->has_priority = 1; - } - if (update->first_rb != exist->first_rb) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update first_rb: %d -> %d\n", - mod_id, update->id, exist->first_rb, update->first_rb); - exist->first_rb = update ->first_rb; - exist->has_first_rb = 1; - } - /*if (update->lenght_rb != exist->lenght_rb) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update lenght_rb: %d -> %d\n", - mod_id, update->id, exist->lenght_rb, update->lenght_rb); - exist->lenght_rb = update->lenght_rb; - }*/ - if (update->maxmcs != exist->maxmcs) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update maxmcs: %d -> %d\n", - mod_id, update->id, exist->maxmcs, update->maxmcs); - exist->maxmcs = update->maxmcs; - exist->has_maxmcs = 1; - } - /* TODO - int sorting_update = 0; - int n = min(exist->n_sorting, update->n_sorting); - int i = 0; - while (i < n && !sorting_update) { - sorting_update = sorting_update || (update->sorting[i] != exist->sorting[i]); - i++; - } - if (sorting_update) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update sorting array\n", update->id, mod_id); - if (exist->n_sorting != update->n_sorting) - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] only writing %d elements\n", - mod_id, update->id, n); - for (i = 0; i < n; i++) - exist->sorting[i] = update->sorting[i]; - } - */ - if (update->accounting != exist->accounting) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update accounting: %d -> %d\n", - mod_id, update->id, exist->accounting, update->accounting); - exist->accounting = update->accounting; - exist->has_accounting = 1; - } - if (!exist->scheduler_name - || strcmp(update->scheduler_name, exist->scheduler_name) != 0) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update scheduler: %s -> %s\n", - mod_id, update->id, exist->scheduler_name, update->scheduler_name); - if (exist->scheduler_name) free(exist->scheduler_name); - exist->scheduler_name = strdup(update->scheduler_name); - } -} - -void fill_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *s, Protocol__FlexDlSlice *from) -{ - /* function fills slice with information from another slice or with default - * values (currently slice 0) if from is NULL */ - /* TODO fill the slice depending on the chosen label */ - if (!s->has_label) { - s->has_label = 1; - s->label = from ? from->label : sc_update[mod_id]->dl[0]->label; - } - if (!s->has_percentage) { - s->has_percentage = 1; - s->percentage = from ? from->percentage : sc_update[mod_id]->dl[0]->percentage; - } - if (!s->has_isolation) { - s->has_isolation = 1; - s->isolation = from ? from->isolation : sc_update[mod_id]->dl[0]->isolation; - } - if (!s->has_priority) { - s->has_priority = 1; - s->priority = from ? from->priority : sc_update[mod_id]->dl[0]->priority; - } - if (!s->has_position_low) { - s->has_position_low = 1; - s->position_low = from ? from->position_low : sc_update[mod_id]->dl[0]->position_low; - } - if (!s->has_position_high) { - s->has_position_high = 1; - s->position_high = from ? from->position_high : sc_update[mod_id]->dl[0]->position_high; - } - if (!s->has_maxmcs) { - s->has_maxmcs = 1; - s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->dl[0]->maxmcs; - } - if (s->n_sorting == 0) { - s->n_sorting = from ? from->n_sorting : sc_update[mod_id]->dl[0]->n_sorting; - s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexDlSorting)); - if (!s->sorting) s->n_sorting = 0; - for (int i = 0; i < s->n_sorting; ++i) - s->sorting[i] = from ? from->sorting[i] : sc_update[0]->dl[0]->sorting[i]; - } - if (!s->has_accounting) { - s->accounting = from ? from->accounting : sc_update[mod_id]->dl[0]->accounting; - } - if (!s->scheduler_name) { - s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->dl[0]->scheduler_name); - } -} - -Protocol__FlexDlSlice *get_existing_dl_slice(mid_t mod_id, int id) -{ - for (int i = 0; i < sc_update[mod_id]->n_dl; ++i) { - if (id == sc_update[mod_id]->dl[i]->id) { - return sc_update[mod_id]->dl[i]; - } - } - return NULL; -} - -Protocol__FlexDlSlice *create_new_dl_slice(mid_t mod_id, int id) -{ - LOG_I(FLEXRAN_AGENT, - "[%d] Creating DL slice with ID %d, taking default values from DL slice 0\n", - mod_id, id); - Protocol__FlexDlSlice *to = sc_update[mod_id]->dl[sc_update[mod_id]->n_dl]; - sc_update[mod_id]->n_dl++; - AssertFatal(sc_update[mod_id]->n_dl <= MAX_NUM_SLICES, - "cannot create more than MAX_NUM_SLICES\n"); - to->id = id; - return to; -} - -void fill_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *s, Protocol__FlexUlSlice *from) -{ - /* function fills slice with information from another slice or with default - * values (currently slice 0) if from is NULL */ - /* TODO fill the slice depending on the chosen label */ - if (!s->has_label) { - s->has_label = 1; - s->label = from ? from->label : sc_update[mod_id]->ul[0]->label; - } - if (!s->has_percentage) { - s->has_percentage = 1; - s->percentage = from ? from->percentage : sc_update[mod_id]->ul[0]->percentage; - } - if (!s->has_isolation) { - s->has_isolation = 1; - s->isolation = from ? from->isolation : sc_update[mod_id]->ul[0]->isolation; - } - if (!s->has_priority) { - s->has_priority = 1; - s->priority = from ? from->priority : sc_update[mod_id]->ul[0]->priority; - } - if (!s->has_first_rb) { - s->has_first_rb = 1; - s->first_rb = from ? from->first_rb : sc_update[mod_id]->ul[0]->first_rb; - } - if (!s->has_maxmcs) { - s->has_maxmcs = 1; - s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->ul[0]->maxmcs; - } - if (s->n_sorting == 0) { - s->n_sorting = from ? from->n_sorting : sc_update[0]->ul[0]->n_sorting; - s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexUlSorting)); - if (!s->sorting) s->n_sorting = 0; - for (int i = 0; i < s->n_sorting; ++i) - s->sorting[i] = from ? from->sorting[i] : sc_update[0]->ul[0]->sorting[i]; - } - if (!s->has_accounting) { - s->accounting = from ? from->accounting : sc_update[0]->ul[0]->accounting; - } - if (!s->scheduler_name) { - s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->ul[0]->scheduler_name); - } -} - -Protocol__FlexUlSlice *get_existing_ul_slice(mid_t mod_id, int id) -{ - for (int i = 0; i < sc_update[mod_id]->n_ul; ++i) { - if (id == sc_update[mod_id]->ul[i]->id) { - return sc_update[mod_id]->ul[i]; - } - } - return NULL; -} - -Protocol__FlexUlSlice *create_new_ul_slice(mid_t mod_id, int id) -{ - LOG_I(FLEXRAN_AGENT, - "[%d] Creating UL slice with ID %d, taking default values from UL slice 0\n", - mod_id, id); - Protocol__FlexUlSlice *to = sc_update[mod_id]->ul[sc_update[mod_id]->n_ul]; - sc_update[mod_id]->n_ul++; - AssertFatal(sc_update[mod_id]->n_ul <= MAX_NUM_SLICES, - "cannot create more than MAX_NUM_SLICES\n"); - to->id = id; - return to; -} - -void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *sup) -{ - int verified = 1; - if (!sc_update[mod_id]) { - LOG_E(FLEXRAN_AGENT, "Can not update slice policy (no existing slice profile)\n"); - return; - } - - pthread_mutex_lock(&sc_update_mtx); - /* no need for tests in the current state as there are only two protobuf - * bools for intra-/interslice sharing. The function applies new values if - * applicable */ - overwrite_slice_config(mod_id, sc_update[mod_id], sup); - - if (sup->n_dl == 0) { - LOG_I(FLEXRAN_AGENT, "[%d] no DL slice configuration in flex_slice_config message\n", mod_id); +void update_or_remove_dl(mid_t mod_id, Protocol__FlexSlice *s) { + if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET + && !s->label && !s->scheduler) { + LOG_I(FLEXRAN_AGENT, "remove DL slice ID %d\n", s->id); + const int rc = flexran_remove_dl_slice(mod_id, s); + if (!rc) + LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id); } else { - /* verify slice parameters */ - for (int i = 0; i < sup->n_dl; i++) { - if (!sup->dl[i]->has_id) { - verified = 0; - break; - } - Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id); - /* fill up so that the slice is complete. This way, we don't need to - * worry about it later */ - fill_dl_slice(mod_id, sup->dl[i], dls); - verified = verified && flexran_verify_dl_slice(mod_id, sup->dl[i]); - if (!verified) break; - } - - /* verify group-based parameters (e.g. sum percentage should not exceed - * 100%). Can be used to perform admission control */ - verified = verified && flexran_verify_group_dl_slices(mod_id, - sc_update[mod_id]->dl, sc_update[mod_id]->n_dl, sup->dl, sup->n_dl); - - if (verified) { - for (int i = 0; i < sup->n_dl; i++) { - /* if all verifications were successful, get existing slice for ID or - * create new one and overwrite with the update */ - Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id); - if (!dls) dls = create_new_dl_slice(mod_id, sup->dl[i]->id); - overwrite_slice_config_dl(mod_id, dls, sup->dl[i]); - } - } else { - LOG_E(FLEXRAN_AGENT, "[%d] DL slice verification failed, refusing application\n", mod_id); - } + LOG_I(FLEXRAN_AGENT, "updating DL slice ID %d\n", s->id); + const int rc = flexran_create_dl_slice(mod_id, s); + if (rc < 0) + LOG_W(FLEXRAN_AGENT, + "error while update slice ID %d: flexran_create_dl_slice() -> %d\n", + s->id, rc); } +} - verified = 1; - if (sup->n_ul == 0) { - LOG_I(FLEXRAN_AGENT, "[%d] no UL slice configuration in flex_slice_config message\n", mod_id); +void update_or_remove_ul(mid_t mod_id, Protocol__FlexSlice *s) { + if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET + && !s->label && !s->scheduler) { + LOG_I(FLEXRAN_AGENT, "remove UL slice ID %d\n", s->id); + const int rc = flexran_remove_ul_slice(mod_id, s); + if (!rc) + LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id); } else { - /* verify slice parameters */ - for (int i = 0; i < sup->n_ul; i++) { - if (!sup->ul[i]->has_id) { - verified = 0; - break; - } - Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id); - /* fill up so that the slice is complete. This way, we don't need to - * worry about it later */ - fill_ul_slice(mod_id, sup->ul[i], uls); - verified = verified && flexran_verify_ul_slice(mod_id, sup->ul[i]); - if (!verified) break; - } - - /* verify group-based parameters (e.g. sum percentage should not exceed - * 100%). Can be used to perform admission control */ - verified = verified && flexran_verify_group_ul_slices(mod_id, - sc_update[mod_id]->ul, sc_update[mod_id]->n_ul, sup->ul, sup->n_ul); - - if (verified) { - for (int i = 0; i < sup->n_ul; i++) { - /* if all verifications were successful, get existing slice for ID or - * create new one and overwrite with the update */ - Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id); - if (!uls) uls = create_new_ul_slice(mod_id, sup->ul[i]->id); - overwrite_slice_config_ul(mod_id, uls, sup->ul[i]); - } - } else { - LOG_E(FLEXRAN_AGENT, "[%d] UL slice verification failed, refusing application\n", mod_id); - } + LOG_I(FLEXRAN_AGENT, "updating UL slice ID %d\n", s->id); + const int rc = flexran_create_ul_slice(mod_id, s); + if (rc < 0) + LOG_W(FLEXRAN_AGENT, + "error while updating slice ID %d: flexran_create_ul_slice() -> %d)\n", + s->id, rc); } - pthread_mutex_unlock(&sc_update_mtx); - - perform_slice_config_update_count = 1; } -int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - if (olds->intraslice_share_active != news->intraslice_share_active) { - flexran_set_intraslice_sharing_active(mod_id, news->intraslice_share_active); - changes++; - } - if (olds->interslice_share_active != news->interslice_share_active) { - flexran_set_interslice_sharing_active(mod_id, news->interslice_share_active); - changes++; - } - return changes; -} - -int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - int slice_idx = flexran_find_dl_slice(mod_id, newc->id); - if (slice_idx < 0) { - LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id); - return 0; - } - if (oldc->percentage != newc->percentage) { - flexran_set_dl_slice_percentage(mod_id, slice_idx, newc->percentage); - changes++; - } - if (oldc->isolation != newc->isolation) { - flexran_set_dl_slice_isolation(mod_id, slice_idx, newc->isolation); - changes++; - } - if (oldc->priority != newc->priority) { - flexran_set_dl_slice_priority(mod_id, slice_idx, newc->priority); - changes++; - } - if (oldc->position_low != newc->position_low) { - flexran_set_dl_slice_position_low(mod_id, slice_idx, newc->position_low); - changes++; - } - if (oldc->position_high != newc->position_high) { - flexran_set_dl_slice_position_high(mod_id, slice_idx, newc->position_high); - changes++; - } - if (oldc->maxmcs != newc->maxmcs) { - flexran_set_dl_slice_maxmcs(mod_id, slice_idx, newc->maxmcs); - changes++; - } - if (check_dl_sorting_update(oldc, newc)) { - flexran_set_dl_slice_sorting(mod_id, slice_idx, newc->sorting, newc->n_sorting); - changes++; - } - if (oldc->accounting != newc->accounting) { - flexran_set_dl_slice_accounting_policy(mod_id, slice_idx, newc->accounting); - changes++; - } - if (!oldc->scheduler_name - || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) { - int ret = flexran_set_dl_slice_scheduler(mod_id, slice_idx, newc->scheduler_name); - AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n", - newc->id, slice_idx); - changes++; - } - return changes; -} - -int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - int slice_idx = flexran_find_ul_slice(mod_id, newc->id); - if (slice_idx < 0) { - LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id); - return 0; - } - if (oldc->percentage != newc->percentage) { - flexran_set_ul_slice_percentage(mod_id, slice_idx, newc->percentage); - changes++; - } - if (oldc->isolation != newc->isolation) { - /*flexran_set_ul_slice_isolation(mod_id, slice_idx, newc->isolation); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting isolation is not supported\n", - mod_id, newc->id); - } - if (oldc->priority != newc->priority) { - /*flexran_set_ul_slice_priority(mod_id, slice_idx, newc->priority); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the priority is not supported\n", - mod_id, newc->id); - } - if (oldc->first_rb != newc->first_rb) { - flexran_set_ul_slice_first_rb(mod_id, slice_idx, newc->first_rb); - changes++; - } - /*if (oldc->length_rb != newc->length_rb) { - flexran_set_ul_slice_length_rb(mod_id, slice_idx, newc->length_rb); - changes++; - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting length_rb is not supported\n", - mod_id, newc->id); - }*/ - if (oldc->maxmcs != newc->maxmcs) { - flexran_set_ul_slice_maxmcs(mod_id, slice_idx, newc->maxmcs); - changes++; - } - /*if (check_ul_sorting_update(oldc, newc)) { - flexran_set_ul_slice_sorting(mod_id, slice_idx, newc->sorting, n); - changes++; - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the sorting is not supported\n", - mod_id, newc->id); - }*/ - if (oldc->accounting != newc->accounting) { - /*flexran_set_ul_slice_accounting_policy(mod_id, slice_idx, newc->accounting); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the accounting is not supported\n", - mod_id, newc->id); - } - if (!oldc->scheduler_name - || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) { - int ret = flexran_set_ul_slice_scheduler(mod_id, slice_idx, newc->scheduler_name); - AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n", - newc->id, slice_idx); - changes++; - } - return changes; -} - -void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) -{ - if (n_ue_slice_assoc_updates == MAX_NUM_SLICES) { - LOG_E(FLEXRAN_AGENT, - "[%d] can not handle flex_ue_config message, buffer is full; try again later\n", - mod_id); +void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *dl) { + if (!dl) return; + + Protocol__FlexSliceAlgorithm dl_algo = flexran_get_dl_slice_algo(mod_id); + if (dl->has_algorithm && dl_algo != dl->algorithm) { + LOG_I(FLEXRAN_AGENT, "loading new DL slice algorithm %d\n", dl->algorithm); + dl_algo = dl->algorithm; + flexran_set_dl_slice_algo(mod_id, dl_algo); } + + /* first update existing slices, then create new. Thus, we go through the + * list twice. First round, if a slice exists, handle and mark as such. Then, + * apply all others in the second round */ + if (dl->n_slices > 0) { + if (dl_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n"); + return; + } + int handled_dl[dl->n_slices]; + for (int i = 0; i < dl->n_slices; ++i) { + if (flexran_find_dl_slice(mod_id, dl->slices[i]->id) < 0) { + handled_dl[i] = 0; + continue; + } + update_or_remove_dl(mod_id, dl->slices[i]); + handled_dl[i] = 1; + } + for (int i = 0; i < dl->n_slices; ++i) { + if (handled_dl[i]) + continue; + update_or_remove_dl(mod_id, dl->slices[i]); + } + } + + if (dl->scheduler) { + if (dl_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n"); + return; + } + LOG_I(FLEXRAN_AGENT, "loading DL new scheduling algorithm '%s'\n", dl->scheduler); + const int rc = flexran_set_dl_scheduler(mod_id, dl->scheduler); + if (rc < 0) { + LOG_E(FLEXRAN_AGENT, + "error while updating scheduling algorithm: " + "flexran_update_dl_sched_algo() -> %d)\n", + rc); + return; + } + } +} + +void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *ul) { + if (!ul) + return; + + Protocol__FlexSliceAlgorithm ul_algo = flexran_get_ul_slice_algo(mod_id); + if (ul->has_algorithm && ul_algo != ul->algorithm) { + LOG_I(FLEXRAN_AGENT, "loading new UL slice algorithm %d\n", ul->algorithm); + ul_algo = ul->algorithm; + flexran_set_ul_slice_algo(mod_id, ul_algo); + } + if (ul->n_slices > 0) { + if (ul_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n"); + return; + } + int handled_ul[ul->n_slices]; + for (int i = 0; i < ul->n_slices; ++i) { + if (flexran_find_ul_slice(mod_id, ul->slices[i]->id) < 0) { + handled_ul[i] = 0; + continue; + } + update_or_remove_ul(mod_id, ul->slices[i]); + handled_ul[i] = 1; + } + for (int i = 0; i < ul->n_slices; ++i) { + if (handled_ul[i]) + continue; + update_or_remove_ul(mod_id, ul->slices[i]); + } + } + + if (ul->scheduler) { + if (ul_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n"); + return; + } + LOG_I(FLEXRAN_AGENT, "loading new UL scheduling algorithm '%s'\n", ul->scheduler); + const int rc = flexran_set_ul_scheduler(mod_id, ul->scheduler); + if (rc < 0) { + LOG_E(FLEXRAN_AGENT, + "error while updating scheduling algorithm: " + "flexran_update_dl_sched_algo() -> %d)\n", + rc); + return; + } + } +} + +int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) +{ if (!ue_config->has_rnti) { LOG_E(FLEXRAN_AGENT, "[%d] cannot update UE to slice association, no RNTI in flex_ue_config message\n", mod_id); - return; + return 0; } - if (ue_config->has_dl_slice_id) - LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to DL slice ID %d\n", - mod_id, ue_config->rnti, ue_config->dl_slice_id); - if (ue_config->has_ul_slice_id) - LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to UL slice ID %d\n", - mod_id, ue_config->rnti, ue_config->ul_slice_id); - ue_slice_assoc_update[n_ue_slice_assoc_updates++] = ue_config; - perform_slice_config_update_count = 2; -} - -int apply_ue_slice_assoc_update(mid_t mod_id) -{ - int i; - int changes = 0; - for (i = 0; i < n_ue_slice_assoc_updates; i++) { - int ue_id = find_UE_id(mod_id, ue_slice_assoc_update[i]->rnti); - if (ue_id < 0 || ue_id > MAX_MOBILES_PER_ENB){ - LOG_E(FLEXRAN_AGENT,"UE_id %d is wrong!!\n",ue_id); - continue; - } - if (ue_slice_assoc_update[i]->has_dl_slice_id) { - int slice_idx = flexran_find_dl_slice(mod_id, ue_slice_assoc_update[i]->dl_slice_id); - if (flexran_dl_slice_exists(mod_id, slice_idx)) { - flexran_set_ue_dl_slice_idx(mod_id, ue_id, slice_idx); - changes++; - } else { - LOG_W(FLEXRAN_AGENT, "[%d] DL slice %d does not exist, refusing change\n", - mod_id, ue_slice_assoc_update[i]->dl_slice_id); - } - } - if (ue_slice_assoc_update[i]->has_ul_slice_id) { - int slice_idx = flexran_find_ul_slice(mod_id, ue_slice_assoc_update[i]->ul_slice_id); - if (flexran_ul_slice_exists(mod_id, slice_idx)) { - flexran_set_ue_ul_slice_idx(mod_id, ue_id, slice_idx); - changes++; - } else { - LOG_W(FLEXRAN_AGENT, "[%d] UL slice %d does not exist, refusing change\n", - mod_id, ue_slice_assoc_update[i]->ul_slice_id); - } + int UE_id = flexran_get_mac_ue_id_rnti(mod_id, ue_config->rnti); + if (ue_config->has_dl_slice_id) { + if (flexran_get_dl_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "no DL slice algorithm loaded\n"); + } else { + LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to DL slice ID %d\n", + mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->dl_slice_id); + flexran_set_ue_dl_slice_id(mod_id, UE_id, ue_config->dl_slice_id); } } - n_ue_slice_assoc_updates = 0; - return changes; + if (ue_config->has_ul_slice_id) { + if (flexran_get_ul_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "no UL slice algorithm loaded\n"); + } else { + LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to UL slice ID %d\n", + mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->ul_slice_id); + flexran_set_ue_ul_slice_id(mod_id, UE_id, ue_config->ul_slice_id); + } + } + return 0; } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h index 957fe6065e..9db5d61a11 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h @@ -103,43 +103,11 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name); /*** Functions for handling a slice config ***/ -/* allocate memory for a Protocol__FlexSliceConfig structure with n_dl DL slice - * configs and m_ul UL slice configs */ -Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul); - -/* read the general slice parameters via RAN into the given - * Protocol__FlexSliceConfig struct */ -void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s); - -/* read the DL slice config via the RAN into a given Protocol__FlexDlSlice - * struct */ -void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice); - -/* read the UL slice config via the RAN into a given Protocol__FlexUlSlice - * struct */ -void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice); - -/* reads content of slice over the sc_update structure, so that it can be - * applied later by performing a diff between slice_config and sc_update */ -void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *slice); - -/* apply generic slice parameters (e.g. intra-/interslice sharing activated or - * not) if there are changes. Returns the number of changed parameters. */ -int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news); - -/* apply new configuration of slice in DL if there are changes between the - * parameters. Returns the number of changed parameters. */ -int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc); - -/* apply new configuration of slice in UL if there are changes between the - * parameters. Returns the number of changed parameters. */ -int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc); - -/* inserts a new ue_config into the structure keeping ue to slice association - * updates and marks so it can be applied */ -void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); +/* Prepare the application of a slicing config */ +void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice); +void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice); /* apply a new association between a UE and a slice (both DL and UL) */ -int apply_ue_slice_assoc_update(mid_t mod_id); +int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); #endif /*FLEXRAN_AGENT_MAC_INTERNAL_H_*/ diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c index 67329e91be..6e54e155c2 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c @@ -28,346 +28,3 @@ #include "flexran_agent_mac_slice_verification.h" - -/* overlap check for UL slices, helper type */ -struct sregion_s { - int start; - int length; -}; - -/* forward declaration of locally-used verification functions */ -int flexran_dl_slice_verify_pct(int pct); -int flexran_dl_slice_verify_priority(int prio); -int flexran_dl_slice_verify_position(int pos_low, int pos_high); -int flexran_dl_slice_verify_maxmcs(int maxmcs); -int flexran_ul_slice_verify_pct(int pct); -int flexran_ul_slice_verify_priority(int prio); -int flexran_ul_slice_verify_first_rb(int first_rb); -int flexran_ul_slice_verify_maxmcs(int maxmcs); -int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n); - -int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls) -{ - /* check mandatory parameters */ - if (!dls->has_id) { - LOG_E(FLEXRAN_AGENT, "[%d] Incoming DL slice configuration has no ID\n", mod_id); - return 0; - } - - /* verify parameters individualy */ - /* label is enum */ - if (!flexran_dl_slice_verify_pct(dls->percentage)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice percentage (%d)\n", - mod_id, dls->id, dls->percentage); - return 0; - } - /* isolation is a protobuf bool */ - if (!flexran_dl_slice_verify_priority(dls->priority)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice priority (%d)\n", - mod_id, dls->id, dls->priority); - return 0; - } - if (!flexran_dl_slice_verify_position(dls->position_low, dls->position_high)) { - LOG_E(FLEXRAN_AGENT, - "[%d][DL slice %d] illegal DL slice position low (%d) and/or high (%d)\n", - mod_id, dls->id, dls->position_low, dls->position_high); - return 0; - } - if (!flexran_dl_slice_verify_maxmcs(dls->maxmcs)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice max mcs %d\n", - mod_id, dls->id, dls->maxmcs); - return 0; - } - if (dls->n_sorting == 0) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting in DL slice\n", - mod_id, dls->id); - return 0; - } - if (!dls->sorting) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting found in DL slice\n", - mod_id, dls->id); - return 0; - } - /* sorting is an enum */ - /* accounting is an enum */ - if (!dls->scheduler_name) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no scheduler name found\n", - mod_id, dls->id); - return 0; - } - if (strcmp(dls->scheduler_name, "schedule_ue_spec") != 0) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] setting the scheduler to something " - "different than schedule_ue_spec is currently not allowed\n", - mod_id, dls->id); - return 0; - } - - return 1; -} - -int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing, - int n_ex, Protocol__FlexDlSlice **update, int n_up) -{ - int i, j, n; - int pct, pct_orig; - /* for every update, array points to existing slice, or NULL if update - * creates new slice */ - Protocol__FlexDlSlice *s[n_up]; - for (i = 0; i < n_up; i++) { - s[i] = NULL; - for (j = 0; j < n_ex; j++) { - if (existing[j]->id == update[i]->id) - s[i] = existing[j]; - } - } - - /* check that number of created and number of added slices in total matches - * [1,10] */ - n = n_ex; - for (i = 0; i < n_up; i++) { - /* new slice */ - if (!s[i]) n += 1; - /* slice will be deleted */ - else if (s[i]->percentage == 0) n -= 1; - /* else "only" an update */ - } - - if (n < 1 || n > MAX_NUM_SLICES) { - LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting DL slices (%d -> %d)\n", - mod_id, n_ex, n); - return 0; - } - - /* check that the sum of all slices percentages (including removed/added - * slices) matches [1,100] */ - pct = 0; - for (i = 0; i < n_ex; i++) { - pct += existing[i]->percentage; - } - pct_orig = pct; - for (i = 0; i < n_up; i++) { - /* if there is an existing slice, subtract its percentage and add the - * update's percentage */ - if (s[i]) - pct -= s[i]->percentage; - pct += update[i]->percentage; - } - if (pct < 1 || pct > 100) { - LOG_E(FLEXRAN_AGENT, - "[%d] invalid total RB share for DL slices (%d%% -> %d%%)\n", - mod_id, pct_orig, pct); - return 0; - } - - return 1; -} - -int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls) -{ - /* check mandatory parameters */ - if (!uls->has_id) { - LOG_E(FLEXRAN_AGENT, "[%d] Incoming UL slice configuration has no ID\n", mod_id); - return 0; - } - - /* verify parameters individually */ - /* label is enum */ - if (!flexran_ul_slice_verify_pct(uls->percentage)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n", - mod_id, uls->id, uls->percentage); - return 0; - } - /* isolation is a protobuf bool */ - if (!flexran_ul_slice_verify_priority(uls->priority)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n", - mod_id, uls->id, uls->priority); - return 0; - } - if (!flexran_ul_slice_verify_first_rb(uls->first_rb)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice first RB (%d)\n", - mod_id, uls->id, uls->first_rb); - return 0; - } - if (!flexran_ul_slice_verify_maxmcs(uls->maxmcs)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice max mcs (%d)\n", - mod_id, uls->id, uls->maxmcs); - return 0; - } - /* TODO - if (uls->n_sorting == 0) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting in UL slice\n", - mod_id, uls->id); - return 0; - } - if (!uls->sorting) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting found in UL slice\n", - mod_id, uls->id); - return 0; - } - */ - /* sorting is an enum */ - /* accounting is an enum */ - if (!uls->scheduler_name) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no scheduler name found\n", - mod_id, uls->id); - return 0; - } - if (strcmp(uls->scheduler_name, "schedule_ulsch_rnti") != 0) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] setting the scheduler to something " - "different than schedule_ulsch_rnti is currently not allowed\n", - mod_id, uls->id); - return 0; - } - - return 1; -} - -int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing, - int n_ex, Protocol__FlexUlSlice **update, int n_up) -{ - int i, j, n; - int pct, pct_orig; - /* for every update, array "s" points to existing slice, or NULL if update - * creates new slice; array "offs" gives the offset of this slice */ - Protocol__FlexUlSlice *s[n_up]; - int offs[n_up]; - for (i = 0; i < n_up; i++) { - s[i] = NULL; - offs[i] = 0; - for (j = 0; j < n_ex; j++) { - if (existing[j]->id == update[i]->id) { - s[i] = existing[j]; - offs[i] = j; - } - } - } - - /* check that number of created and number of added slices in total matches - * [1,10] */ - n = n_ex; - for (i = 0; i < n_up; i++) { - /* new slice */ - if (!s[i]) n += 1; - /* slice will be deleted */ - else if (s[i]->percentage == 0) n -= 1; - /* else "only" an update */ - } - - if (n < 1 || n > MAX_NUM_SLICES) { - LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting UL slices (%d -> %d)\n", - mod_id, n_ex, n); - return 0; - } - - /* check that the sum of all slices percentages (including removed/added - * slices) matches [1,100] */ - pct = 0; - for (i = 0; i < n_ex; i++) { - pct += existing[i]->percentage; - } - pct_orig = pct; - for (i = 0; i < n_up; i++) { - /* if there is an existing slice, subtract its percentage and add the - * update's percentage */ - if (s[i]) - pct -= s[i]->percentage; - pct += update[i]->percentage; - } - if (pct < 1 || pct > 100) { - LOG_E(FLEXRAN_AGENT, "[%d] invalid total RB share (%d%% -> %d%%)\n", - mod_id, pct_orig, pct); - return 0; - } - - /* check that there is no overlap in slices resulting as the combination of - * first_rb and percentage */ - struct sregion_s sregion[n]; - const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */ - int k = n_ex; - for (i = 0; i < n_ex; i++) { - sregion[i].start = existing[i]->first_rb; - sregion[i].length = existing[i]->percentage * N_RB / 100; - } - for (i = 0; i < n_up; i++) { - ptrdiff_t d = s[i] ? offs[i] : k++; - AssertFatal(d >= 0 && d < k, "illegal pointer offset (%ld, k=%d)\n", d, k); - sregion[d].start = update[i]->first_rb; - sregion[d].length = update[i]->percentage * N_RB / 100; - } - AssertFatal(k == n, "illegal number of slices while calculating overlap\n"); - if (!check_ul_slice_overlap(mod_id, sregion, k)) { - LOG_E(FLEXRAN_AGENT, "[%d] UL slices are overlapping\n", mod_id); - return 0; - } - - return 1; -} - -int flexran_dl_slice_verify_pct(int pct) -{ - return pct >= 0 && pct <= 100; -} - -int flexran_dl_slice_verify_priority(int prio) -{ - return prio >= 0; -} - -int flexran_dl_slice_verify_position(int pos_low, int pos_high) -{ - return pos_low < pos_high && pos_low >= 0 && pos_high <= N_RBG_MAX; -} - -int flexran_dl_slice_verify_maxmcs(int maxmcs) -{ - return maxmcs >= 0 && maxmcs <= 28; -} - -int flexran_ul_slice_verify_pct(int pct) -{ - return pct >= 0 && pct <= 100; -} - -int flexran_ul_slice_verify_priority(int prio) -{ - return prio >= 0; -} - -int flexran_ul_slice_verify_first_rb(int first_rb) -{ - return first_rb >= 0 && first_rb < 100; -} - -int flexran_ul_slice_verify_maxmcs(int maxmcs) -{ - return maxmcs >= 0 && maxmcs <= 20; -} - -int sregion_compare(const void *_a, const void *_b) -{ - const struct sregion_s *a = (const struct sregion_s *)_a; - const struct sregion_s *b = (const struct sregion_s *)_b; - const int res = a->start - b->start; - if (res < 0) return -1; - else if (res == 0) return 0; - else return 1; -} - -int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n) -{ - int i; - int overlap, op, u; - const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */ - qsort(sr, n, sizeof(sr[0]), sregion_compare); - for (i = 0; i < n; i++) { - u = i == n-1 ? N_RB : sr[i+1].start; - AssertFatal(sr[i].start <= u, "unsorted slice list\n"); - overlap = sr[i].start + sr[i].length - u; - if (overlap <= 0) continue; - op = overlap * 100 / sr[i].length; - LOG_W(FLEXRAN_AGENT, "[%d] slice overlap of %d%% detected\n", mod_id, op); - if (op >= 10) /* more than 10% overlap -> refuse */ - return 0; - } - return 1; -} diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h index a8f4030d36..c9e66b6f88 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h @@ -29,9 +29,3 @@ #include "flexran_agent_common_internal.h" #include "flexran_agent_mac_internal.h" -int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls); -int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing, - int n_ex, Protocol__FlexDlSlice **update, int n_up); -int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls); -int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing, - int n_ex, Protocol__FlexUlSlice **update, int n_up); diff --git a/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c b/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c index 92c9917622..ec907a1956 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c +++ b/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c @@ -921,7 +921,4 @@ int flexran_agent_unregister_rrc_xface(mid_t mod_id) return 0; } -AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id) -{ - return agent_rrc_xface[mod_id]; -} + diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c index 04a47406e1..c2d7cb9e55 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c @@ -125,6 +125,63 @@ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply) { } } +void flexran_agent_handle_mme_update(mid_t mod_id, + size_t n_mme, + Protocol__FlexS1apMme **mme) { + if (n_mme == 0 || n_mme > 1) { + LOG_E(FLEXRAN_AGENT, "cannot handle %lu MMEs yet\n", n_mme); + return; + } + + if (!mme[0]->s1_ip) { + LOG_E(FLEXRAN_AGENT, "no S1 IP present, cannot handle request\n"); + return; + } + + if (mme[0]->has_state + && mme[0]->state == PROTOCOL__FLEX_MME_STATE__FLMMES_DISCONNECTED) { + int rc = flexran_remove_s1ap_mme(mod_id, 1, &mme[0]->s1_ip); + if (rc == 0) + LOG_I(FLEXRAN_AGENT, "remove MME at IP %s\n", mme[0]->s1_ip); + else + LOG_W(FLEXRAN_AGENT, + "could not remove MME: flexran_remove_s1ap_mme() returned %d\n", + rc); + } else { + int rc = flexran_add_s1ap_mme(mod_id, 1, &mme[0]->s1_ip); + if (rc == 0) + LOG_I(FLEXRAN_AGENT, "add MME at IP %s\n", mme[0]->s1_ip); + else + LOG_W(FLEXRAN_AGENT, + "could not add MME: flexran_add_s1ap_mme() returned %d\n", + rc); + } +} + +void flexran_agent_handle_plmn_update(mid_t mod_id, + int CC_id, + size_t n_plmn, + Protocol__FlexPlmn **plmn_id) { + if (n_plmn < 1 || n_plmn > 6) { + LOG_E(FLEXRAN_AGENT, "cannot handle %lu PLMNs\n", n_plmn); + return; + } + + /* We assume the controller has checked all the parameters within each + * plmn_id */ + int rc = flexran_set_new_plmn_id(mod_id, CC_id, n_plmn, plmn_id); + if (rc == 0) { + LOG_I(FLEXRAN_AGENT, "set %lu new PLMNs:\n", n_plmn); + for (int i = 0; i < (int)n_plmn; ++i) + LOG_I(FLEXRAN_AGENT, " MCC %d MNC %d MNC length %d\n", + plmn_id[i]->mcc, plmn_id[i]->mnc, plmn_id[0]->mnc_length); + } else { + LOG_W(FLEXRAN_AGENT, + "could not set new PLMN configuration: flexran_set_new_plmn_id() returned %d\n", + rc); + } +} + int flexran_agent_register_s1ap_xface(mid_t mod_id) { if (agent_s1ap_xface[mod_id]) { LOG_E(FLEXRAN_AGENT, "S1AP agent CM for eNB %d is already registered\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h index 1cca6ac9c1..006eaa1d3c 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h @@ -60,6 +60,17 @@ int flexran_agent_s1ap_stats_reply(mid_t mod_id, /* Free allocated S1AP stats message */ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply); +/* Add or remove MME updates */ +void flexran_agent_handle_mme_update(mid_t mod_id, + size_t n_mme, + Protocol__FlexS1apMme **mme); + +/* Set a new PLMN configuration */ +void flexran_agent_handle_plmn_update(mid_t mod_id, + int CC_id, + size_t n_plmn, + Protocol__FlexPlmn **plmn_id); + /* Register technology specific interface callbacks */ int flexran_agent_register_s1ap_xface(mid_t mod_id); diff --git a/openair2/ENB_APP/MACRLC_paramdef.h b/openair2/ENB_APP/MACRLC_paramdef.h index 55ce9d5059..fcee6142f0 100644 --- a/openair2/ENB_APP/MACRLC_paramdef.h +++ b/openair2/ENB_APP/MACRLC_paramdef.h @@ -58,6 +58,7 @@ #define CONFIG_STRING_MACRLC_SCHED_MODE "scheduler_mode" #define CONFIG_MACRLC_PUSCH10xSNR "puSch10xSnr" #define CONFIG_MACRLC_PUCCH10xSNR "puCch10xSnr" +#define CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO "default_sched_dl_algo" /*-------------------------------------------------------------------------------------------------------------------------------------------------------*/ /* MacRLC configuration parameters */ @@ -84,6 +85,7 @@ {CONFIG_STRING_MACRLC_SCHED_MODE, NULL, 0, strptr:NULL, defstrval:"default", TYPE_STRING, 0}, \ {CONFIG_MACRLC_PUSCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \ {CONFIG_MACRLC_PUCCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \ +{CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO, NULL, 0, strptr:NULL, defstrval:"round_robin_dl", TYPE_STRING, 0}, \ } #define MACRLC_CC_IDX 0 #define MACRLC_TRANSPORT_N_PREFERENCE_IDX 1 @@ -105,6 +107,7 @@ #define MACRLC_SCHED_MODE_IDX 17 #define MACRLC_PUSCH10xSNR_IDX 18 #define MACRLC_PUCCH10xSNR_IDX 19 +#define MACRLC_DEFAULT_SCHED_DL_ALGO_IDX 20 /*---------------------------------------------------------------------------------------------------------------------------------------------------------*/ #endif diff --git a/openair2/ENB_APP/MESSAGES/V2/config_common.proto b/openair2/ENB_APP/MESSAGES/V2/config_common.proto index 733d883c92..2f2267b628 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_common.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_common.proto @@ -61,82 +61,30 @@ enum flex_qam { // // Slice config related structures and enums // -enum flex_dl_sorting { - - CR_ROUND = 0; // Highest HARQ first - CR_SRB12 = 1; // Highest SRB1+2 first - CR_HOL = 2; // Highest HOL first - CR_LC = 3; // Greatest RLC buffer first - CR_CQI = 4; // Highest CQI first - CR_LCP = 5; // Highest LC priority first +enum flex_slice_algorithm { + None = 0; + Static = 1; + NVS = 2; } -enum flex_ul_sorting { - CRU_ROUND = 0; // Highest HARQ first - CRU_BUF = 1; // Highest BSR first - CRU_BTS = 2; // More bytes to schedule first - CRU_MCS = 3; // Highest MCS first - CRU_LCP = 4; // Highest LC priority first - CRU_HOL = 5; // Highest HOL first +message flex_slice_static { + optional uint32 posLow = 1; + optional uint32 posHigh = 2; } -enum flex_dl_accounting_policy { - POL_FAIR = 0; - POL_GREEDY = 1; - POL_NUM = 2; +message flex_slice { + optional uint32 id = 1; + optional string label = 2; + optional string scheduler = 3; + oneof params { + flex_slice_static static = 10; + } } -enum flex_ul_accounting_policy { - POLU_FAIR = 0; - POLU_GREEDY = 1; - POLU_NUM = 2; -} - -enum flex_slice_label { - xMBB = 0; - URLLC = 1; - mMTC = 2; - xMTC = 3; - Other = 4; -} - -message flex_dl_slice { - optional uint32 id = 1; - optional flex_slice_label label = 2; - // should be between 0 and 100 - optional uint32 percentage = 3; - // whether this slice should be exempted form interslice sharing - optional bool isolation = 4; - // increasing value means increasing prio - optional uint32 priority = 5; - // min and max RB to use (in frequency) in the range [0, N_RBG_MAX] - optional uint32 position_low = 6; - optional uint32 position_high = 7; - // maximum MCS to be allowed in this slice - optional uint32 maxmcs = 8; - repeated flex_dl_sorting sorting = 9; - optional flex_dl_accounting_policy accounting = 10; - optional string scheduler_name = 11; -} - -message flex_ul_slice { - optional uint32 id = 1; - optional flex_slice_label label = 2; - // should be between 0 and 100 - optional uint32 percentage = 3; - // whether this slice should be exempted form interslice sharing - optional bool isolation = 4; - // increasing value means increasing prio - optional uint32 priority = 5; - // RB start to use (in frequency) in the range [0, N_RB_MAX] - optional uint32 first_rb = 6; - // TODO RB number - //optional uint32 length_rb = 7; - // maximum MCS to be allowed in this slice - optional uint32 maxmcs = 8; - repeated flex_ul_sorting sorting = 9; - optional flex_ul_accounting_policy accounting = 10; - optional string scheduler_name = 11; +message flex_slice_dl_ul_config { + optional flex_slice_algorithm algorithm = 1; + repeated flex_slice slices = 2; + optional string scheduler = 3; // if no slicing } // diff --git a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto index 324153613d..1a69deec71 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto @@ -49,14 +49,8 @@ message flex_cell_config { } message flex_slice_config { - // whether remaining RBs after first intra-slice allocation will - // be allocated to UEs of the same slice - optional bool intraslice_share_active = 3; - // whether remaining RBs after slice allocation will be allocated - // to UEs of another slice. Isolated slices will be ignored. - optional bool interslice_share_active = 4; - repeated flex_dl_slice dl = 1; - repeated flex_ul_slice ul = 2; + optional flex_slice_dl_ul_config dl = 6; + optional flex_slice_dl_ul_config ul = 7; } message flex_ue_config { diff --git a/openair2/ENB_APP/enb_app.c b/openair2/ENB_APP/enb_app.c index 0e1c7e64bc..7c91e57813 100644 --- a/openair2/ENB_APP/enb_app.c +++ b/openair2/ENB_APP/enb_app.c @@ -273,7 +273,6 @@ void *eNB_app_task(void *args_p) { if (EPC_MODE_ENABLED) { LOG_I(ENB_APP, "[eNB %d] Received %s: associated MME %d\n", instance, ITTI_MSG_NAME (msg_p), S1AP_REGISTER_ENB_CNF(msg_p).nb_mme); - DevAssert(register_enb_pending > 0); register_enb_pending--; /* Check if at least eNB is registered with one MME */ diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 6dcc574746..1d189832b4 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -29,6 +29,7 @@ #include #include +#include #include "common/utils/LOG/log.h" #include "assertions.h" @@ -260,6 +261,16 @@ void RCconfig_macrlc(int macrlc_has_f1[MAX_MAC_INST]) { global_scheduler_mode=SCHED_MODE_DEFAULT; printf("sched mode = default %d [%s]\n",global_scheduler_mode,*(MacRLC_ParamList.paramarray[j][MACRLC_SCHED_MODE_IDX].strptr)); } + + char *s = *MacRLC_ParamList.paramarray[j][MACRLC_DEFAULT_SCHED_DL_ALGO_IDX].strptr; + void *d = dlsym(NULL, s); + AssertFatal(d, "%s(): no default scheduler DL algo '%s' found\n", __func__, s); + // release default, add new + pp_impl_param_t *dl_pp = &RC.mac[j]->pre_processor_dl; + dl_pp->dl_algo.unset(&dl_pp->dl_algo.data); + dl_pp->dl_algo = *(default_sched_dl_algo_t *) d; + dl_pp->dl_algo.data = dl_pp->dl_algo.setup(); + LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", dl_pp->dl_algo.name); }// j=0..num_inst } /*else {// MacRLC_ParamList.numelt > 0 // ignore it @@ -1545,7 +1556,7 @@ int RCconfig_RRC(uint32_t i, eNB_RRC_INST *rrc, int macrlc_has_f1) { RRC_CONFIGURATION_REQ(msg_p).eMBMS_configured = 0; printf("No eMBMS configuration, skipping it\n"); // eMTC configuration - char brparamspath[MAX_OPTNAME_SIZE*2 + 16]; + char brparamspath[MAX_OPTNAME_SIZE*2 + 160]; sprintf(brparamspath,"%s.%s", ccspath, ENB_CONFIG_STRING_EMTC_PARAMETERS); config_get(eMTCParams, sizeof(eMTCParams)/sizeof(paramdef_t), brparamspath); RRC_CONFIGURATION_REQ(msg_p).eMTC_configured = eMTCconfig.eMTC_configured&1; @@ -1554,7 +1565,7 @@ int RCconfig_RRC(uint32_t i, eNB_RRC_INST *rrc, int macrlc_has_f1) { else printf("No eMTC configuration, skipping it\n"); // Sidelink configuration - char SLparamspath[MAX_OPTNAME_SIZE*2 + 16]; + char SLparamspath[MAX_OPTNAME_SIZE*2 + 160]; sprintf(SLparamspath,"%s.%s", ccspath, ENB_CONFIG_STRING_SL_PARAMETERS); config_get( SLParams, sizeof(SLParams)/sizeof(paramdef_t), SLparamspath); // Sidelink Resource pool information diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index dc320ef974..7569ca1ac1 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -306,6 +306,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { if (reply->cell_config[i]->mbsfn_subframe_config_sfalloc) free(reply->cell_config[i]->mbsfn_subframe_config_sfalloc); + /* si_config is shared between MAC and RRC, free here */ if (reply->cell_config[i]->si_config) { for(int j = 0; j < reply->cell_config[i]->si_config->n_si_message; j++) { free(reply->cell_config[i]->si_config->si_message[j]); @@ -316,26 +317,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { } if (reply->cell_config[i]->slice_config) { - for (int j = 0; j < reply->cell_config[i]->slice_config->n_dl; ++j) { - if (reply->cell_config[i]->slice_config->dl[j]->n_sorting > 0) - free(reply->cell_config[i]->slice_config->dl[j]->sorting); - - free(reply->cell_config[i]->slice_config->dl[j]->scheduler_name); - free(reply->cell_config[i]->slice_config->dl[j]); - } - - free(reply->cell_config[i]->slice_config->dl); - - for (int j = 0; j < reply->cell_config[i]->slice_config->n_ul; ++j) { - if (reply->cell_config[i]->slice_config->ul[j]->n_sorting > 0) - free(reply->cell_config[i]->slice_config->ul[j]->sorting); - - free(reply->cell_config[i]->slice_config->ul[j]->scheduler_name); - free(reply->cell_config[i]->slice_config->ul[j]); - } - - free(reply->cell_config[i]->slice_config->ul); - free(reply->cell_config[i]->slice_config); + flexran_agent_destroy_mac_slice_config(reply->cell_config[i]); } free(reply->cell_config[i]); @@ -893,31 +875,40 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot Protocol__FlexranMessage *input = (Protocol__FlexranMessage *)params; Protocol__FlexEnbConfigReply *enb_config = input->enb_config_reply_msg; - if (enb_config->n_cell_config == 0) { - LOG_W(FLEXRAN_AGENT, - "received enb_config_reply message does not contain a cell_config\n"); - *msg = NULL; - return 0; - } - if (enb_config->n_cell_config > 1) LOG_W(FLEXRAN_AGENT, "ignoring slice configs for other cell except cell 0\n"); - if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { - prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); - } else if (enb_config->cell_config[0]->has_eutra_band - && enb_config->cell_config[0]->has_dl_freq - && enb_config->cell_config[0]->has_ul_freq - && enb_config->cell_config[0]->has_dl_bandwidth) { - initiate_soft_restart(mod_id, enb_config->cell_config[0]); - } else if (flexran_agent_get_rrc_xface(mod_id) - && enb_config->cell_config[0]->has_x2_ho_net_control) { - LOG_I(FLEXRAN_AGENT, - "setting X2 HO NetControl to %d\n", - enb_config->cell_config[0]->x2_ho_net_control); - const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control); - if (rc < 0) - LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); + if (enb_config->n_cell_config > 0) { + if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { + prepare_update_slice_config(mod_id, &enb_config->cell_config[0]->slice_config); + } + if (enb_config->cell_config[0]->has_eutra_band + && enb_config->cell_config[0]->has_dl_freq + && enb_config->cell_config[0]->has_ul_freq + && enb_config->cell_config[0]->has_dl_bandwidth) { + initiate_soft_restart(mod_id, enb_config->cell_config[0]); + } + if (flexran_agent_get_rrc_xface(mod_id) + && enb_config->cell_config[0]->has_x2_ho_net_control) { + LOG_I(FLEXRAN_AGENT, + "setting X2 HO NetControl to %d\n", + enb_config->cell_config[0]->x2_ho_net_control); + const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control); + if (rc < 0) + LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); + } + if (flexran_agent_get_rrc_xface(mod_id) && enb_config->cell_config[0]->n_plmn_id > 0) { + flexran_agent_handle_plmn_update(mod_id, + 0, + enb_config->cell_config[0]->n_plmn_id, + enb_config->cell_config[0]->plmn_id); + } + } + + if (flexran_agent_get_s1ap_xface(mod_id) && enb_config->s1ap) { + flexran_agent_handle_mme_update(mod_id, + enb_config->s1ap->n_mme, + enb_config->s1ap->mme); } *msg = NULL; @@ -930,7 +921,11 @@ int flexran_agent_handle_ue_config_reply(mid_t mod_id, const void *params, Proto Protocol__FlexUeConfigReply *ue_config_reply = input->ue_config_reply_msg; for (i = 0; flexran_agent_get_mac_xface(mod_id) && i < ue_config_reply->n_ue_config; i++) - prepare_ue_slice_assoc_update(mod_id, ue_config_reply->ue_config[i]); + prepare_ue_slice_assoc_update(mod_id, &ue_config_reply->ue_config[i]); + /* prepare_ue_slice_assoc_update takes ownership of the individual + * FlexUeConfig messages. Therefore, mark zero messages to not accidentally + * free them twice */ + ue_config_reply->n_ue_config = 0; *msg = NULL; return 0; diff --git a/openair2/ENB_APP/flexran_agent_extern.h b/openair2/ENB_APP/flexran_agent_extern.h index 119bc3d44c..5f17cf4841 100644 --- a/openair2/ENB_APP/flexran_agent_extern.h +++ b/openair2/ENB_APP/flexran_agent_extern.h @@ -41,10 +41,15 @@ AGENT_PHY_xface *flexran_agent_get_phy_xface(mid_t mod_id); /* Control module interface for the communication of the MAC Control Module with the agent */ -AGENT_MAC_xface *flexran_agent_get_mac_xface(mid_t mod_id); + +extern AGENT_MAC_xface *agent_mac_xface[NUM_MAX_ENB]; +#define flexran_agent_get_mac_xface(mod_id) (agent_mac_xface[mod_id]) +/* Control module interface for the communication of the RRC Control Module with the agent */ /* Control module interface for the communication of the RRC Control Module with the agent */ -AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id); +// AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id); +extern AGENT_RRC_xface *agent_rrc_xface[NUM_MAX_ENB]; +#define flexran_agent_get_rrc_xface(mod_id) (agent_rrc_xface[mod_id]) /* Control module interface for the communication of the RRC Control Module with the agent */ AGENT_PDCP_xface *flexran_agent_get_pdcp_xface(mid_t mod_id); diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 32cb8c74e1..79c992a4d7 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -30,6 +30,7 @@ #include "flexran_agent_ran_api.h" #include "s1ap_eNB_ue_context.h" #include "s1ap_eNB_management_procedures.h" +#include "openair2/LAYER2/MAC/slicing/slicing.h" static inline int phy_is_present(mid_t mod_id, uint8_t cc_id) { return RC.eNB && RC.eNB[mod_id] && RC.eNB[mod_id][cc_id]; @@ -3013,471 +3014,293 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti) } /**************************** SLICING ****************************/ -int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { - if (!mac_is_present(mod_id)) return -1; +Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id) { + if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None; - int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id]; - - if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl) - return RC.mac[mod_id]->slice_info.dl[slice_idx].id; - - return 0; + switch (RC.mac[mod_id]->pre_processor_dl.algorithm) { + case STATIC_SLICING: + return PROTOCOL__FLEX_SLICE_ALGORITHM__Static; + default: + return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + } } -void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { +int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return 0; + eNB_MAC_INST *mac = RC.mac[mod_id]; + const int cc_id = 0; + + pp_impl_param_t dl = mac->pre_processor_dl; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + mac->pre_processor_dl = static_dl_init(mod_id, cc_id); + break; + default: + mac->pre_processor_dl.algorithm = 0; + mac->pre_processor_dl.dl = dlsch_scheduler_pre_processor; + mac->pre_processor_dl.dl_algo.data = mac->pre_processor_dl.dl_algo.setup(); + mac->pre_processor_dl.slices = NULL; + break; + } + if (dl.slices) + dl.destroy(&dl.slices); + if (dl.dl_algo.data) + dl.dl_algo.unset(&dl.dl_algo.data); + return 1; +} + +Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id) { + if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + + switch (RC.mac[mod_id]->pre_processor_ul.algorithm) { + case STATIC_SLICING: + return PROTOCOL__FLEX_SLICE_ALGORITHM__Static; + default: + return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + } +} + +int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return 0; + eNB_MAC_INST *mac = RC.mac[mod_id]; + const int cc_id = 0; + + pp_impl_param_t ul = mac->pre_processor_ul; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + mac->pre_processor_ul = static_ul_init(mod_id, cc_id); + break; + default: + mac->pre_processor_ul.algorithm = 0; + mac->pre_processor_ul.ul = ulsch_scheduler_pre_processor; + mac->pre_processor_ul.ul_algo.data = mac->pre_processor_ul.ul_algo.setup(); + mac->pre_processor_ul.slices = NULL; + break; + } + if (ul.slices) + ul.destroy(&ul.slices); + if (ul.ul_algo.data) + ul.ul_algo.unset(&ul.ul_algo.data); + return 1; +} + +int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { + if (!mac_is_present(mod_id)) return -1; + slice_info_t *slices = RC.mac[mod_id]->pre_processor_dl.slices; + if (!slices) return -1; + const int idx = slices->UE_assoc_slice[ue_id]; + return slices->s[idx]->id; +} + +void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; - - if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return; - - if (!flexran_dl_slice_exists(mod_id, slice_idx)) return; - - //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id] = slice_idx; + int idx = flexran_find_dl_slice(mod_id, slice_id); + if (idx < 0) return; + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + dl->move_UE(dl->slices, ue_id, idx); } int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - - int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id]; - - if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul) - return RC.mac[mod_id]->slice_info.ul[slice_idx].id; - - return 0; + slice_info_t *slices = RC.mac[mod_id]->pre_processor_ul.slices; + if (!slices) return -1; + const int idx = slices->UE_assoc_slice[ue_id]; + return slices->s[idx]->id; } -void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { +void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; - - if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return; - - if (!flexran_ul_slice_exists(mod_id, slice_idx)) return; - - //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id] = slice_idx; + int idx = flexran_find_ul_slice(mod_id, slice_id); + if (idx < 0) return; + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + ul->move_UE(ul->slices, ue_id, idx); } -int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl; +int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + void *params = NULL; + switch (s->params_case) { + case PROTOCOL__FLEX_SLICE__PARAMS_STATIC: + params = malloc(sizeof(static_slice_param_t)); + if (!params) return 0; + ((static_slice_param_t *)params)->posLow = s->static_->poslow; + ((static_slice_param_t *)params)->posHigh = s->static_->poshigh; + break; + default: + break; + } + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + char *l = s->label ? strdup(s->label) : NULL; + void *algo = &dl->dl_algo; // default scheduler + if (s->scheduler) { + algo = dlsym(NULL, s->scheduler); + if (!algo) { + free(params); + LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler); + return -15; + } + } + return dl->addmod_slice(dl->slices, s->id, l, algo, params); } -int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return -1; - - int newidx = RC.mac[mod_id]->slice_info.n_dl; - - if (newidx >= MAX_NUM_SLICES) return -1; - - ++RC.mac[mod_id]->slice_info.n_dl; - flexran_set_dl_slice_id(mod_id, newidx, slice_id); - return newidx; +int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + const int idx = flexran_find_dl_slice(mod_id, s->id); + if (idx < 0) return 0; + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + return dl->remove_slice(dl->slices, idx); } int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - int n = sli->n_dl; - - for (int i = 0; i < n; i++) { - if (sli->dl[i].id == slice_id) return i; - } - + slice_info_t *si = RC.mac[mod_id]->pre_processor_dl.slices; + for (int i = 0; i < si->num; ++i) + if (si->s[i]->id == slice_id) + return i; return -1; } -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - - if (sli->n_dl <= 1) return -1; - - if (sli->dl[slice_idx].sched_name) free(sli->dl[slice_idx].sched_name); - - --sli->n_dl; - - /* move last element to the position of the removed one */ - if (slice_idx != sli->n_dl) - memcpy(&sli->dl[slice_idx], &sli->dl[sli->n_dl], sizeof(sli->dl[sli->n_dl])); - - memset(&sli->dl[sli->n_dl], 0, sizeof(sli->dl[sli->n_dl])); - /* all UEs that have been in the old slice are put into slice index 0 */ - //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_dl_slice_idx; - - //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - // if (assoc_list[i] == slice_idx) - // assoc_list[i] = 0; - //} - - return 1; +void flexran_get_dl_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return; + slice_t *s_ = RC.mac[mod_id]->pre_processor_dl.slices->s[slice_idx]; + slice->has_id = 1; + slice->id = s_->id; + slice->label = s_->label; + slice->scheduler = s_->dl_algo.name; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic)); + if (!slice->static_) return; + protocol__flex_slice_static__init(slice->static_); + slice->static_->has_poslow = 1; + slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow; + slice->static_->has_poshigh = 1; + slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC; + break; + default: + break; + } } int flexran_get_num_dl_slices(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.n_dl; -} - -int flexran_get_intraslice_sharing_active(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.intraslice_share_active; -} -void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.intraslice_share_active = intraslice_active; -} - -int flexran_get_interslice_sharing_active(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.interslice_share_active; -} -void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.interslice_share_active = interslice_active; -} - -slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].id; -} -void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].id = slice_id; -} - -int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pct * 100.0f; -} -void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pct = percentage / 100.0f; -} - -int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].isol; -} -void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].isol = is_isolated; -} - -int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].prio; -} -void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].prio = priority; -} - -int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low; -} -void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low = poslow; -} - -int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high; -} -void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high = poshigh; -} - -int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs; -} -void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs = maxmcs; -} - -int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list) { - if (!mac_is_present(mod_id)) return -1; - - if (!(*sorting_list)) { - *sorting_list = calloc(CR_NUM, sizeof(Protocol__FlexDlSorting)); - - if (!(*sorting_list)) return -1; - } - - uint32_t policy = RC.mac[mod_id]->slice_info.dl[slice_idx].sorting; - - for (int i = 0; i < CR_NUM; i++) { - switch (policy >> 4 * (CR_NUM - 1 - i) & 0xF) { - case CR_ROUND: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND; - break; - - case CR_SRB12: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_SRB12; - break; - - case CR_HOL: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_HOL; - break; - - case CR_LC: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LC; - break; - - case CR_CQI: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_CQI; - break; - - case CR_LCP: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LCP; - break; - - default: - /* this should not happen, but a "default" */ - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND; - break; - } - } - - return CR_NUM; -} -void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n) { - if (!mac_is_present(mod_id)) return; - - uint32_t policy = 0; - - for (int i = 0; i < n && i < CR_NUM; i++) { - switch (sorting_list[i]) { - case PROTOCOL__FLEX_DL_SORTING__CR_ROUND: - policy = policy << 4 | CR_ROUND; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_SRB12: - policy = policy << 4 | CR_SRB12; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_HOL: - policy = policy << 4 | CR_HOL; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_LC: - policy = policy << 4 | CR_LC; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_CQI: - policy = policy << 4 | CR_CQI; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_LCP: - policy = policy << 4 | CR_LCP; - break; - - default: /* suppresses warnings */ - policy = policy << 4 | CR_ROUND; - break; - } - } - - /* fill up with 0 == CR_ROUND */ - if (CR_NUM > n) policy = policy << 4 * (CR_NUM - n); - - RC.mac[mod_id]->slice_info.dl[slice_idx].sorting = policy; -} - -Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - - switch (RC.mac[mod_id]->slice_info.dl[slice_idx].accounting) { - case POL_FAIR: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - - case POL_GREEDY: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY; - - default: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - } -} -void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting) { - if (!mac_is_present(mod_id)) return; - - switch (accounting) { - case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR; - return; - - case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_GREEDY; - return; - - default: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR; - return; - } -} - -char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return NULL; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name; -} -int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { if (!mac_is_present(mod_id)) return 0; - - if (RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name) - free(RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name); - - RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name = strdup(name); - RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb = dlsym(NULL, name); - return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb != NULL; + if (!RC.mac[mod_id]->pre_processor_dl.slices) return 0; + return RC.mac[mod_id]->pre_processor_dl.slices->num; } -int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { +int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) { if (!mac_is_present(mod_id)) return -1; + void *params = NULL; + switch (s->params_case) { + case PROTOCOL__FLEX_SLICE__PARAMS_STATIC: + params = malloc(sizeof(static_slice_param_t)); + if (!params) return 0; + ((static_slice_param_t *)params)->posLow = s->static_->poslow; + ((static_slice_param_t *)params)->posHigh = s->static_->poshigh; + break; + default: + break; + } + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + char *l = s->label ? strdup(s->label) : NULL; + void *algo = &ul->ul_algo; // default scheduler + if (s->scheduler) { + algo = dlsym(NULL, s->scheduler); + if (!algo) { + free(params); + LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler); + return -15; + } + } + return ul->addmod_slice(ul->slices, s->id, l, algo, params); +} - int newidx = RC.mac[mod_id]->slice_info.n_ul; - - if (newidx >= MAX_NUM_SLICES) return -1; - - ++RC.mac[mod_id]->slice_info.n_ul; - flexran_set_ul_slice_id(mod_id, newidx, slice_id); - return newidx; +int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + const int idx = flexran_find_ul_slice(mod_id, s->id); + if (idx < 0) return 0; + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + return ul->remove_slice(ul->slices, idx); } int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - int n = sli->n_ul; - - for (int i = 0; i < n; i++) { - if (sli->ul[i].id == slice_id) return i; - } - + slice_info_t *si = RC.mac[mod_id]->pre_processor_ul.slices; + for (int i = 0; i < si->num; ++i) + if (si->s[i]->id == slice_id) + return i; return -1; } -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; +void flexran_get_ul_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return; + slice_t *s_ = RC.mac[mod_id]->pre_processor_ul.slices->s[slice_idx]; + slice->has_id = 1; + slice->id = s_->id; + slice->label = s_->label; + slice->scheduler = s_->ul_algo.name; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic)); + if (!slice->static_) return; + protocol__flex_slice_static__init(slice->static_); + slice->static_->has_poslow = 1; + slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow; + slice->static_->has_poshigh = 1; + slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC; + break; + default: + break; + } - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - - if (sli->n_ul <= 1) return -1; - - if (sli->ul[slice_idx].sched_name) free(sli->ul[slice_idx].sched_name); - - --sli->n_ul; - - /* move last element to the position of the removed one */ - if (slice_idx != sli->n_ul) - memcpy(&sli->ul[slice_idx], &sli->ul[sli->n_ul], sizeof(sli->ul[sli->n_ul])); - - memset(&sli->ul[sli->n_ul], 0, sizeof(sli->ul[sli->n_ul])); - /* all UEs that have been in the old slice are put into slice index 0 */ - //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_ul_slice_idx; - - //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - // if (assoc_list[i] == slice_idx) - // assoc_list[i] = 0; - //} - - return sli->n_ul; } int flexran_get_num_ul_slices(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.n_ul; -} - -int flexran_ul_slice_exists(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul; -} - -slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].id; -} -void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].id = slice_id; -} - -int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].pct * 100.0f; -} -void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].pct = percentage / 100.0f; -} - -int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb; -} - -void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb = first_rb; -} - -int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs; -} -void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { - if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs = maxmcs; -} - -char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return NULL; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name; -} -int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { if (!mac_is_present(mod_id)) return 0; + if (!RC.mac[mod_id]->pre_processor_ul.slices) return 0; + return RC.mac[mod_id]->pre_processor_ul.slices->num; +} - if (RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name) - free(RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name); +char *flexran_get_dl_scheduler_name(mid_t mod_id) { + if (!mac_is_present(mod_id)) return NULL; + return RC.mac[mod_id]->pre_processor_dl.dl_algo.name; +} - RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name = strdup(name); - RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb = dlsym(NULL, name); - return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb != NULL; +int flexran_set_dl_scheduler(mid_t mod_id, char *sched) { + if (!mac_is_present(mod_id)) return -1; + void *d = dlsym(NULL, sched); + if (!d) return -2; + pp_impl_param_t *dl_pp = &RC.mac[mod_id]->pre_processor_dl; + dl_pp->dl_algo.unset(&dl_pp->dl_algo.data); + dl_pp->dl_algo = *(default_sched_dl_algo_t *) d; + dl_pp->dl_algo.data = dl_pp->dl_algo.setup(); + return 0; +} + +char *flexran_get_ul_scheduler_name(mid_t mod_id) { + if (!mac_is_present(mod_id)) return NULL; + return RC.mac[mod_id]->pre_processor_ul.ul_algo.name; +} + +int flexran_set_ul_scheduler(mid_t mod_id, char *sched) { + if (!mac_is_present(mod_id)) return -1; + void *d = dlsym(NULL, sched); + if (!d) return -2; + pp_impl_param_t *ul_pp = &RC.mac[mod_id]->pre_processor_ul; + ul_pp->ul_algo.unset(&ul_pp->ul_algo.data); + ul_pp->ul_algo = *(default_sched_ul_algo_t *) d; + ul_pp->ul_algo.data = ul_pp->ul_algo.setup(); + return 0; } /************************** S1AP **************************/ @@ -3634,6 +3457,168 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM return 0; } +int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) return -1; + if (!rrc_is_present(mod_id)) return -2; + + /* Reconstruct S1AP_REGISTER_ENB_REQ */ + MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, S1AP_REGISTER_ENB_REQ); + RCconfig_S1(m, mod_id); + + const int CC_id = 0; + eNB_RRC_INST *rrc = RC.rrc[CC_id]; + RrcConfigurationReq *conf = &rrc->configuration; + S1AP_REGISTER_ENB_REQ(m).num_plmn = conf->num_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + S1AP_REGISTER_ENB_REQ(m).mcc[i] = conf->mcc[i]; + S1AP_REGISTER_ENB_REQ(m).mnc[i] = conf->mnc[i]; + S1AP_REGISTER_ENB_REQ(m).mnc_digit_length[i] = conf->mnc_digit_length[i]; + } + + /* reconstruct MME list, it might have been updated since initial + * configuration */ + S1AP_REGISTER_ENB_REQ(m).nb_mme = 0; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme; + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = mme->mme_s1_ip.ipv4; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme->mme_s1_ip.ipv4_address); + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = mme->mme_s1_ip.ipv6; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6_address, mme->mme_s1_ip.ipv6_address); + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = mme->broadcast_plmn_num; + for (int i = 0; i < mme->broadcast_plmn_num; ++i) + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = mme->broadcast_plmn_index[i]; + S1AP_REGISTER_ENB_REQ(m).nb_mme += 1; + } + + if (S1AP_REGISTER_ENB_REQ(m).nb_mme + n_mme > S1AP_MAX_NB_MME_IP_ADDRESS) + return -1; + + for (int i = 0; i < n_mme; ++i) { + const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme_ipv4[0]); + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = 1; + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = 0; + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = S1AP_REGISTER_ENB_REQ(m).num_plmn; + for (int i = 0; i < S1AP_REGISTER_ENB_REQ(m).num_plmn; ++i) + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = i; + S1AP_REGISTER_ENB_REQ(m).nb_mme += 1; + } + + itti_send_msg_to_task (TASK_S1AP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m); + + return 0; +} + +int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) return -1; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + if (mme->mme_s1_ip.ipv4 + && strncmp(mme->mme_s1_ip.ipv4_address, mme_ipv4[0], 16) == 0) + break; + } + if (!mme) + return -2; + + MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, SCTP_CLOSE_ASSOCIATION); + SCTP_CLOSE_ASSOCIATION(m).assoc_id = mme->assoc_id; + itti_send_msg_to_task (TASK_SCTP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m); + + switch (mme->state) { + case S1AP_ENB_STATE_WAITING: + s1ap->s1ap_mme_nb -= 1; + if (s1ap->s1ap_mme_pending_nb > 0) + s1ap->s1ap_mme_pending_nb -= 1; + break; + case S1AP_ENB_STATE_CONNECTED: + case S1AP_ENB_OVERLOAD: /* I am not sure the decrements are right here */ + s1ap->s1ap_mme_nb -= 1; + s1ap->s1ap_mme_associated_nb -= 1; + break; + case S1AP_ENB_STATE_DISCONNECTED: + default: + break; + } + RB_REMOVE(s1ap_mme_map, &s1ap->s1ap_mme_head, mme); + + return 0; +} + +int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id) { + if (!rrc_is_present(mod_id)) + return -1; + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) + return -2; + + eNB_RRC_INST *rrc = RC.rrc[CC_id]; + RrcConfigurationReq *conf = &rrc->configuration; + + uint8_t num_plmn_old = conf->num_plmn; + uint16_t mcc[PLMN_LIST_MAX_SIZE]; + uint16_t mnc[PLMN_LIST_MAX_SIZE]; + uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE]; + for (int i = 0; i < num_plmn_old; ++i) { + mcc[i] = conf->mcc[i]; + mnc[i] = conf->mnc[i]; + mnc_digit_length[i] = conf->mnc_digit_length[i]; + } + + conf->num_plmn = (uint8_t) n_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + conf->mcc[i] = plmn_id[i]->mcc; + conf->mnc[i] = plmn_id[i]->mnc; + conf->mnc_digit_length[i] = plmn_id[i]->mnc_length; + } + + rrc_eNB_carrier_data_t *carrier = &rrc->carrier[CC_id]; + extern uint8_t do_SIB1(rrc_eNB_carrier_data_t *carrier, + int Mod_id, + int CC_id, + BOOLEAN_t brOption, + RrcConfigurationReq *configuration); + carrier->sizeof_SIB1 = do_SIB1(carrier, mod_id, CC_id, FALSE, conf); + if (carrier->sizeof_SIB1 < 0) + return -1337; /* SIB1 encoding failed, hell will probably break loose */ + + s1ap->num_plmn = (uint8_t) n_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + s1ap->mcc[i] = plmn_id[i]->mcc; + s1ap->mnc[i] = plmn_id[i]->mnc; + s1ap->mnc_digit_length[i] = plmn_id[i]->mnc_length; + } + + int bpn_failed = 0; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + for (int i = 0; i < mme->broadcast_plmn_num; ++i) { + /* search the new index and update. If we don't find, we count this using + * bpn_failed to now how many broadcast_plmns could not be updated */ + int idx = mme->broadcast_plmn_index[i]; + int omcc = mcc[idx]; + int omnc = mnc[idx]; + int omncl = mnc_digit_length[idx]; + int j = 0; + for (j = 0; j < s1ap->num_plmn; ++j) { + if (s1ap->mcc[j] == omcc + && s1ap->mnc[j] == omnc + && s1ap->mnc_digit_length[j] == omncl) { + mme->broadcast_plmn_index[i] = j; + break; + } + } + if (j == s1ap->num_plmn) /* could not find the old PLMN in the new ones */ + bpn_failed++; + } + } + if (bpn_failed > 0) + return -10000 - bpn_failed; + return 0; +} + int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf){ if (!rrc_is_present(mod_id)) return -1; s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); @@ -3644,7 +3629,7 @@ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_con RB_FOREACH(ue, s1ap_ue_map, &s1ap->s1ap_ue_head){ if (ue->eNB_ue_s1ap_id == enb_ue_s1ap_id) break; } - if (ue == NULL) return -1; + if (!ue) return 0; // UE does not exist: it might be connected but CN did not answer if (ue->mme_ref->mme_s1_ip.ipv4) ue_conf->mme_s1_ip = (char*) &ue->mme_ref->mme_s1_ip.ipv4_address[0]; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index ce32883852..2d8a86f7d0 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -656,156 +656,66 @@ int flexran_agent_rrc_gtp_get_teid_sgw(mid_t mod_id, rnti_t rnti, int index); uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti); /************************** Slice configuration **************************/ +/* Get the currently active DL slicing algorithm */ +Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id); +/* Set the active DL slicing algorithm */ +int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo); + +/* Get the currently active UL slicing algorithm */ +Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id); +/* Set the active UL slicing algorithm */ +int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo); /* Get the DL slice ID for a UE */ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id); - -/* Set the DL slice index(!) for a UE */ -void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +/* Set the DL slice for a UE */ +void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id); /* Get the UL slice ID for a UE */ int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id); +/* Set the UL slice for a UE */ +void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id); -/* Set the UL slice index(!) for a UE */ -void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); - -/* Whether intraslice sharing is active, return boolean */ -int flexran_get_intraslice_sharing_active(mid_t mod_id); -/* Set whether intraslice sharing is active */ -void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active); - -/* Whether intraslice sharing is active, return boolean */ -int flexran_get_interslice_sharing_active(mid_t mod_id); -/* Set whether intraslice sharing is active */ -void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active); +/* Create slice in DL, returns the new slice index */ +int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s); +/* Remove slice in DL, returns new number of slices or -1 on error */ +int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s); +/* Finds slice in DL with given slice_id and returns slice index */ +int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); +/* Return the parameters of slice at index slice_idx */ +void flexran_get_dl_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo); /* Get the number of slices in DL */ int flexran_get_num_dl_slices(mid_t mod_id); -/* Query slice existence in DL. Return is boolean value */ -int flexran_dl_slice_exists(mid_t mod_id, int slice_idx); +/* Create slice in UL, returns the new slice index */ +int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s); +/* Remove slice in UL */ +int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s); -/* Create slice in DL, returns the new slice index */ -int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); /* Finds slice in DL with given slice_id and returns slice index */ -int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); -/* Remove slice in DL, returns new number of slices or -1 on error */ -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); - -/* Get the ID of a slice in DL */ -slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx); -/* Set the ID of a slice in DL */ -void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id); - -/* Get the RB share a slice in DL, value 0-100 */ -int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx); -/* Set the RB share a slice in DL, value 0-100 */ -void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage); - -/* Whether a slice in DL is isolated */ -int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx); -/* Set whether a slice in DL is isolated */ -void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated); - -/* Get the priority of a slice in DL */ -int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx); -/* Get the priority of a slice in DL */ -void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority); - -/* Get the lower end of the frequency range for the slice positioning in DL */ -int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx); -/* Set the lower end of the frequency range for the slice positioning in DL */ -void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow); - -/* Get the higher end of the frequency range for the slice positioning in DL */ -int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx); -/* Set the higher end of the frequency range for the slice positioning in DL */ -void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh); - -/* Get the maximum MCS for slice in DL */ -int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx); -/* Set the maximum MCS for slice in DL */ -void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs); - -/* Get the sorting order of a slice in DL, return value is number of elements - * in sorting_list */ -int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list); -/* Set the sorting order of a slice in DL */ -void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n); - -/* Get the accounting policy for a slice in DL */ -Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx); -/* Set the accounting policy for a slice in DL */ -void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting); - -/* Get the scheduler name for a slice in DL */ -char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx); -/* Set the scheduler name for a slice in DL */ -int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name); - +int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); +/* Return the parameters of slice at index slice_idx */ +void flexran_get_ul_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo); /* Get the number of slices in UL */ int flexran_get_num_ul_slices(mid_t mod_id); -/* Query slice existence in UL. Return is boolean value */ -int flexran_ul_slice_exists(mid_t mod_id, int slice_idx); +/* Get the name of/Set the DL scheduling algorithm. If slicing is active, this + * corresponds to the default algorithm for slices, otherwise the currently + * used one. */ +char *flexran_get_dl_scheduler_name(mid_t mod_id); +int flexran_set_dl_scheduler(mid_t mod_id, char *sched); -/* Create slice in UL, returns the new slice index */ -int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); -/* Finds slice in UL with given slice_id and returns slice index */ -int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); -/* Remove slice in UL */ -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); - -/* Get the ID of a slice in UL */ -slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx); -/* Set the ID of a slice in UL */ -void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id); - -/* Get the RB share a slice in UL, value 0-100 */ -int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx); -/* Set the RB share a slice in UL, value 0-100 */ -void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage); - -/* TODO Whether a slice in UL is isolated */ -/*int flexran_get_ul_slice_isolation(mid_t mod_id, int slice_idx);*/ -/* TODO Set whether a slice in UL is isolated */ -/*void flexran_set_ul_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated);*/ - -/* TODO Get the priority of a slice in UL */ -/*int flexran_get_ul_slice_priority(mid_t mod_id, int slice_idx);*/ -/* TODO Set the priority of a slice in UL */ -/*void flexran_set_ul_slice_priority(mid_t mod_id, int slice_idx, int priority);*/ - -/* Get the first RB for allocation in a slice in UL */ -int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx); -/* Set the first RB for allocation in a slice in UL */ -void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb); - -/* TODO Get the number of RB for the allocation in a slice in UL */ -/*int flexran_get_ul_slice_length_rb(mid_t mod_id, int slice_idx);*/ -/* TODO Set the of number of RB for the allocation in a slice in UL */ -/*void flexran_set_ul_slice_length_rb(mid_t mod_id, int slice_idx, int poshigh);*/ - -/* Get the maximum MCS for slice in UL */ -int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx); -/* Set the maximum MCS for slice in UL */ -void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs); - -/* TODO Get the sorting order of a slice in UL, return value is number of elements - * in sorting_list */ -/*int flexran_get_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting **sorting_list);*/ -/* TODO Set the sorting order of a slice in UL */ -/*void flexran_set_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting *sorting_list, int n);*/ - -/* TODO Get the accounting policy for a slice in UL */ -/*Protocol__UlAccountingPolicy flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx);*/ -/* TODO Set the accounting policy for a slice in UL */ -/*void flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__UlAccountingPolicy accountin);*/ - -/* Get the scheduler name for a slice in UL */ -char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx); -/* Set the scheduler name for a slice in UL */ -int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name); +/* Get the name of/Set the UL scheduler algorithm. Same applies as for the DL + * case */ +char *flexran_get_ul_scheduler_name(mid_t mod_id); +int flexran_set_ul_scheduler(mid_t mod_id, char *sched); /************************** S1AP **************************/ /* Get the number of MMEs to be connected */ @@ -832,6 +742,15 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM /* Get the S1AP UE conf */ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf); +/* Add MMEs and re-issue S1AP Registration Request */ +int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); + +/* Remove MMEs and and cut SCTP to MME */ +int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); + +/* Set a new PLMN configuration */ +int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id); + /********************* general information *****************/ /* get an ID for this BS (or part of a BS) */ uint64_t flexran_get_bs_id(mid_t mod_id); diff --git a/openair2/F1AP/f1ap_cu_ue_context_management.c b/openair2/F1AP/f1ap_cu_ue_context_management.c index a64f2d529b..789ce4c715 100644 --- a/openair2/F1AP/f1ap_cu_ue_context_management.c +++ b/openair2/F1AP/f1ap_cu_ue_context_management.c @@ -226,7 +226,7 @@ int CU_send_UE_CONTEXT_SETUP_REQUEST(instance_t instance, ie->value.choice.ResourceCoordinationTransferContainer.buf = malloc(4); ie->value.choice.ResourceCoordinationTransferContainer.size = 4; - strncpy((char *)ie->value.choice.ResourceCoordinationTransferContainer.buf, "123", 3); + strncpy((char *)ie->value.choice.ResourceCoordinationTransferContainer.buf, "123", 4); OCTET_STRING_fromBuf(&ie->value.choice.ResourceCoordinationTransferContainer, "asdsa1d32sa1d31asd31as", diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h index 4c5da80764..bc4c4cf9d9 100644 --- a/openair2/GNB_APP/RRC_nr_paramsvalues.h +++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h @@ -133,7 +133,8 @@ #define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR" #define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex" #define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing" -#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" +#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" +#define GNB_CONFIG_STRING_MSG3TRANSFPREC "msg3_transformPrecoder" #define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList" #define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble" #define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant" @@ -246,7 +247,7 @@ {GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:-1,TYPE_INT64,0/*17*/},\ {GNB_CONFIG_STRING_INITIALDLBWPK0_1,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->k0,defint64val:-1,TYPE_INT64,0/*18*/},\ {GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*19*/},\ -{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \ {GNB_CONFIG_STRING_INITIALDLBWPK0_2,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->k0,defint64val:-1,TYPE_INT64,0/*21*/},\ {GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*22*/},\ {GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*23*/},\ @@ -311,11 +312,12 @@ {GNB_CONFIG_STRING_RSRPTHRESHOLDSSB,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB,defint64val:19,TYPE_INT64,0/*82*/},\ {GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR,NULL,0,uptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present,defuintval:NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139,TYPE_UINT,0/*83*/},\ {GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139,defint64val:0,TYPE_INT64,0/*84*/},\ -{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \ -{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*86*/},\ -{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*87*/},\ -{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*88*/},\ -{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*89*/}, \ +{GNB_CONFIG_STRING_RESTRICTEDSETCONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \ +{GNB_CONFIG_STRING_MSG3TRANSFPREC,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder,defintval:1,TYPE_INT64,0/*86*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*87*/},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*88*/},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*89*/},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*90*/}, \ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_2,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->k2,defint64val:-1,TYPE_INT64,0},\ @@ -325,7 +327,7 @@ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_4,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->k2,defint64val:-1,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*99*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*100*/}, \ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_5,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_5,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ @@ -335,7 +337,7 @@ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_6,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_7,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*109*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*110*/}, \ {GNB_CONFIG_STRING_INITIALULBWPK2_8,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ @@ -345,7 +347,7 @@ {GNB_CONFIG_STRING_INITIALULBWPK2_10,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*119*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*120*/}, \ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_12,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->k2,defint64val:-1,TYPE_INT64,0},\ @@ -355,7 +357,7 @@ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_14,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->k2,defint64val:-1,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*129*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*130*/}, \ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_15,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_15,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ @@ -365,7 +367,7 @@ {GNB_CONFIG_STRING_PUCCHGROUPHOPPING, NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_GroupHopping,defint64val:NR_PUCCH_ConfigCommon__pucch_GroupHopping_neither,TYPE_INT64,0},\ {GNB_CONFIG_STRING_HOPPINGID, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId,defint64val:40,TYPE_INT64,0},\ {GNB_CONFIG_STRING_P0NOMINAL, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal,defint64val:1,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*139*/}, \ +{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*140*/}, \ {GNB_CONFIG_STRING_SSBPOSITIONSINBURST,NULL,0,u64ptr:&ssb_bitmap,defintval:0xff,TYPE_UINT64,0}, \ {GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0},\ {GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity,defint64val:NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p5,TYPE_INT64,0},\ @@ -379,7 +381,7 @@ {GNB_CONFIG_STRING_NROFUPLINKSLOTS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSlots,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_NROFUPLINKSYMBOLS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSymbols,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_SSPBCHBLOCKPOWER,NULL,0,i64ptr:&scc->ss_PBCH_BlockPower,defint64val:20,TYPE_INT64,0}, \ -{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0/*86*/}} +{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0}} diff --git a/openair2/GNB_APP/gnb_app.c b/openair2/GNB_APP/gnb_app.c index f11e302771..9bdd709262 100644 --- a/openair2/GNB_APP/gnb_app.c +++ b/openair2/GNB_APP/gnb_app.c @@ -71,30 +71,30 @@ static void configure_nr_rrc(uint32_t gnb_id) /*------------------------------------------------------------------------------*/ -/* + static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, const Enb_properties_array_t *enb_properties) { uint32_t gnb_id; - MessageDef *msg_p; + //MessageDef *msg_p; uint32_t register_gnb_pending = 0; for (gnb_id = gnb_id_start; (gnb_id < gnb_id_end) ; gnb_id++) { { - s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse + //s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse // note: there is an implicit relationship between the data structure and the message name - msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse + /*msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse - RCconfig_NR_S1(msg_p, gnb_id); + RCconfig_NR_S1(msg_p, gnb_id);*/ if (gnb_id == 0) RCconfig_nr_gtpu(); - s1ap_register_gNB = &S1AP_REGISTER_ENB_REQ(msg_p); //Message Temporarily reuse - LOG_I(GNB_APP,"default drx %d\n",s1ap_register_gNB->default_drx); + /*s1ap_register_gNB = &S1AP_REGISTER_ENB_REQ(msg_p); //Message Temporarily reuse + LOG_I(GNB_APP,"default drx %d\n",s1ap_register_gNB->default_drx);*/ LOG_I(GNB_APP,"[gNB %d] gNB_app_register for instance %d\n", gnb_id, GNB_MODULE_ID_TO_INSTANCE(gnb_id)); - itti_send_msg_to_task (TASK_S1AP, GNB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p); + //itti_send_msg_to_task (TASK_S1AP, GNB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p); register_gnb_pending++; } @@ -102,7 +102,7 @@ static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, return register_gnb_pending; } -*/ + /*------------------------------------------------------------------------------*/ static uint32_t gNB_app_register_x2(uint32_t gnb_id_start, uint32_t gnb_id_end) { @@ -131,7 +131,7 @@ void *gNB_app_task(void *args_p) uint32_t gnb_nb = RC.nb_nr_inst; uint32_t gnb_id_start = 0; uint32_t gnb_id_end = gnb_id_start + gnb_nb; - uint32_t x2_register_gnb_pending = 0; + uint32_t gnb_id; MessageDef *msg_p = NULL; const char *msg_name = NULL; @@ -170,13 +170,13 @@ void *gNB_app_task(void *args_p) if (is_x2ap_enabled() ) { //&& !NODE_IS_DU(RC.rrc[0]->node_type) LOG_I(X2AP, "X2AP enabled \n"); - x2_register_gnb_pending = gNB_app_register_x2 (gnb_id_start, gnb_id_end); + __attribute__((unused)) uint32_t x2_register_gnb_pending = gNB_app_register_x2 (gnb_id_start, gnb_id_end); } if (EPC_MODE_ENABLED) { /* Try to register each gNB */ //registered_gnb = 0; - //register_gnb_pending = gNB_app_register (gnb_id_start, gnb_id_end);//, gnb_properties_p); + __attribute__((unused)) uint32_t register_gnb_pending = gNB_app_register (gnb_id_start, gnb_id_end);//, gnb_properties_p); } else { /* Start L2L1 task */ msg_p = itti_alloc_new_message(TASK_GNB_APP, INITIALIZE_MESSAGE); diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index e7fd2f3cf8..61aa10e47b 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -54,7 +54,8 @@ #include "common/config/config_userapi.h" //#include "RRC_config_tools.h" #include "gnb_paramdef.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" + #include "NR_asn_constant.h" #include "executables/thread-common.h" #include "NR_SCS-SpecificCarrier.h" @@ -254,10 +255,9 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA = NULL; } - // fix libconfig (asn1c uses long) - scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower-=((long)1<<32); - *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant-=((long)1<<32); - *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal-=((long)1<<32); + // default value for msg3 precoder is NULL (0 means enabled) + if (*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder!=0) + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = NULL; // fix DL and UL Allocation lists @@ -714,10 +714,14 @@ int RCconfig_nr_gtpu(void ) { if (address) { MessageDef *message; AssertFatal((message = itti_alloc_new_message(TASK_GNB_APP, GTPV1U_ENB_S1_REQ))!=NULL,""); - IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); - LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); - GTPV1U_ENB_S1_REQ(message).enb_port_for_S1u_S12_S4_up = gnb_port_for_S1U; - itti_send_msg_to_task (TASK_GTPV1_U, 0, message); // data model is wrong: gtpu doesn't have enb_id (or module_id) + // IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); + // LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); + + + IPV4_STR_ADDR_TO_INT_NWBO ( address, GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); + LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up); + GTPV1U_ENB_S1_REQ(message).enb_port_for_S1u_S12_S4_up = gnb_port_for_S1U; + itti_send_msg_to_task (TASK_GTPV1_U, 0, message); // data model is wrong: gtpu doesn't have enb_id (or module_id) } else LOG_E(GTPU,"invalid address for S1U\n"); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 7621994ab2..1f99f50ece 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -573,10 +573,7 @@ schedule_ue_spec(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_IN); start_meas(&eNB->schedule_dlsch_preprocessor); - dlsch_scheduler_pre_processor(module_idP, - CC_id, - frameP, - subframeP); + eNB->pre_processor_dl.dl(module_idP, CC_id, frameP, subframeP); stop_meas(&eNB->schedule_dlsch_preprocessor); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_OUT); @@ -588,6 +585,7 @@ schedule_ue_spec(module_id_t module_idP, UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; eNB_UE_STATS *eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + eNB_UE_stats->TBS = 0; const rnti_t rnti = ue_template->rnti; // If TDD @@ -679,15 +677,15 @@ schedule_ue_spec(module_id_t module_idP, const uint32_t rbc = allocate_prbs_sub( nb_rb, N_RB_DL, N_RBG, ue_sched_ctrl->rballoc_sub_UE[CC_id]); - if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) { - LOG_D(MAC, - "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n", + if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) + LOG_W(MAC, + "[eNB %d] %d.%d CC_id %d : should not schedule UE %d, its " + "retransmission takes more resources than we have\n", module_idP, frameP, + subframeP, CC_id, UE_id); - continue; - } /* CDRX */ ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer @@ -799,6 +797,7 @@ schedule_ue_spec(module_id_t module_idP, eNB_UE_stats->rbs_used_retx = nb_rb; eNB_UE_stats->total_rbs_used_retx += nb_rb; eNB_UE_stats->dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1; + eNB_UE_stats->TBS = TBS; } else { // Now check RLC information to compute number of required RBs // get maximum TBS size for RLC request @@ -842,13 +841,18 @@ schedule_ue_spec(module_id_t module_idP, if (ue_sched_ctrl->dl_lc_bytes[i] == 0) // no data in this LC! continue; - LOG_D(MAC, "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n", + const uint32_t data = + min(ue_sched_ctrl->dl_lc_bytes[i], + TBS - ta_len - header_length_total - sdu_length_total - 3); + LOG_D(MAC, + "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d " + "bytes from RLC (RRC message)\n", module_idP, frameP, subframeP, lcid, CC_id, - TBS - ta_len - header_length_total - sdu_length_total - 3); + data); sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, rnti, @@ -857,7 +861,7 @@ schedule_ue_spec(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS - ta_len - header_length_total - sdu_length_total - 3, + data, (char *)&dlsch_buffer[sdu_length_total], 0, 0 diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index 78d6f6a3d7..89c2ecc83d 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -2131,33 +2131,36 @@ dump_ue_list(UE_list_t *listP) { * Add a UE to UE_list listP */ inline void add_ue_list(UE_list_t *listP, int UE_id) { - if (listP->head == -1) { - listP->head = UE_id; - listP->next[UE_id] = -1; - } else { - int i = listP->head; - while (listP->next[i] >= 0) - i = listP->next[i]; - listP->next[i] = UE_id; - listP->next[UE_id] = -1; - } + int *cur = &listP->head; + while (*cur >= 0) + cur = &listP->next[*cur]; + *cur = UE_id; } //------------------------------------------------------------------------------ /* - * Remove a UE from the UE_list listP, return the previous element + * Remove a UE from the UE_list listP */ inline int remove_ue_list(UE_list_t *listP, int UE_id) { - listP->next[UE_id] = -1; - if (listP->head == UE_id) { - listP->head = listP->next[UE_id]; - return -1; - } + int *cur = &listP->head; + while (*cur != -1 && *cur != UE_id) + cur = &listP->next[*cur]; + if (*cur == -1) + return 0; + int *next = &listP->next[*cur]; + *cur = listP->next[*cur]; + *next = -1; + return 1; +} - int previous = prev(listP, UE_id); - if (previous != -1) - listP->next[previous] = listP->next[UE_id]; - return previous; +//------------------------------------------------------------------------------ +/* + * Initialize the UE_list listP + */ +inline void init_ue_list(UE_list_t *listP) { + listP->head = -1; + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + listP->next[i] = -1; } //------------------------------------------------------------------------------ @@ -2196,6 +2199,12 @@ add_new_ue(module_id_t mod_idP, UE_info->active[UE_id] = TRUE; add_ue_list(&UE_info->list, UE_id); dump_ue_list(&UE_info->list); + pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl; + if (dl->slices) // inform slice implementation about new UE + dl->add_UE(dl->slices, UE_id); + pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul; + if (ul->slices) // inform slice implementation about new UE + ul->add_UE(ul->slices, UE_id); if (IS_SOFTMODEM_IQPLAYER)// not specific to record/playback ? UE_info->UE_template[cc_idP][UE_id].pre_assigned_mcs_ul = 0; UE_info->UE_template[cc_idP][UE_id].rach_resource_type = rach_resource_type; @@ -2259,6 +2268,12 @@ rrc_mac_remove_ue(module_id_t mod_idP, UE_info->num_UEs--; remove_ue_list(&UE_info->list, UE_id); + pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl; + if (dl->slices) // inform slice implementation about new UE + dl->remove_UE(dl->slices, UE_id); + pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul; + if (ul->slices) // inform slice implementation about new UE + ul->remove_UE(ul->slices, UE_id); /* Clear all remaining pending transmissions */ memset(&UE_info->UE_template[pCC_id][UE_id], 0, sizeof(UE_TEMPLATE)); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 3062e5c964..2de45db856 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -1301,11 +1301,11 @@ schedule_ulsch_rnti(module_id_t module_idP, /* * ULSCH preprocessor: set UE_template-> - * pre_allocated_nb_rb_ul[slice_idx] + * pre_allocated_nb_rb_ul * pre_assigned_mcs_ul * pre_allocated_rb_table_index_ul */ - ulsch_scheduler_pre_processor(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); + mac->pre_processor_ul.ul(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { if (UE_info->UE_template[CC_id][UE_id].rach_resource_type > 0) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 329e262c82..faefc481f6 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -155,9 +155,6 @@ /*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */ #define MIN_MAC_HDR_RLC_SIZE (1 + MIN_RLC_PDU_SIZE) -/*!\brief maximum number of slices / groups */ -#define MAX_NUM_SLICES 10 - #define U_PLANE_INACTIVITY_VALUE 0 /* defined 10ms order (zero means infinity) */ @@ -543,7 +540,6 @@ typedef enum { SCHED_MODE_FAIR_RR /// fair raund robin } SCHEDULER_MODES; - /*! \brief temporary struct for ULSCH sched */ typedef struct { rnti_t rnti; @@ -1150,9 +1146,6 @@ typedef struct { UE_list_t list; int num_UEs; boolean_t active[MAX_MOBILES_PER_ENB]; - - /// Sorting criteria for the UE list in the MAC preprocessor - uint16_t sorting_criteria[MAX_NUM_SLICES][CR_NUM]; } UE_info_t; /*! \brief deleting control information*/ @@ -1171,101 +1164,6 @@ typedef struct { int tail_freelist; ///the tail position of the delete list } UE_free_list_t; -/** - * slice specific scheduler for the DL - */ -typedef void (*slice_scheduler_dl)(module_id_t mod_id, - int slice_idx, - frame_t frame, - sub_frame_t subframe, - int *mbsfn_flag); - -typedef struct { - slice_id_t id; - - /// RB share for each slice - float pct; - - /// whether this slice is isolated from the others - int isol; - - int prio; - - /// Frequency ranges for slice positioning - int pos_low; - int pos_high; - - // max mcs for each slice - int maxmcs; - - /// criteria for sorting policies of the slices - uint32_t sorting; - - /// Accounting policy (just greedy(1) or fair(0) setting for now) - int accounting; - - /// name of available scheduler - char *sched_name; - - /// pointer to the slice specific scheduler in DL - slice_scheduler_dl sched_cb; - -} slice_sched_conf_dl_t; - -typedef void (*slice_scheduler_ul)(module_id_t mod_id, - int slice_idx, - frame_t frame, - sub_frame_t subframe, - unsigned char sched_subframe, - uint16_t *first_rb); - -typedef struct { - slice_id_t id; - - /// RB share for each slice - float pct; - - // MAX MCS for each slice - int maxmcs; - - /// criteria for sorting policies of the slices - uint32_t sorting; - - /// starting RB (RB offset) of UL scheduling - int first_rb; - - /// name of available scheduler - char *sched_name; - - /// pointer to the slice specific scheduler in UL - slice_scheduler_ul sched_cb; - -} slice_sched_conf_ul_t; - - -typedef struct { - /// counter used to indicate when all slices have pre-allocated UEs - //int slice_counter; - - /// indicates whether remaining RBs after first intra-slice allocation will - /// be allocated to UEs of the same slice - int intraslice_share_active; - /// indicates whether remaining RBs after slice allocation will be - /// allocated to UEs of another slice. Isolated slices will be ignored - int interslice_share_active; - - /// number of active DL slices - int n_dl; - slice_sched_conf_dl_t dl[MAX_NUM_SLICES]; - - /// number of active UL slices - int n_ul; - slice_sched_conf_ul_t ul[MAX_NUM_SLICES]; - - /// common rb allocation list between slices - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]; -} slice_info_t; - /** * describes contiguous RBs */ @@ -1274,6 +1172,82 @@ typedef struct { int length; } contig_rbs_t; +/** + * definition of a scheduling algorithm implementation used in the + * default DL scheduler + */ +typedef struct { + char *name; + void *(*setup)(void); + void (*unset)(void **); + int (*run)( + module_id_t, int, int, int, UE_list_t *, int, int, uint8_t *, void *); + void *data; +} default_sched_dl_algo_t; + +/** + * definition of a scheduling algorithm implementation used in the + * default UL scheduler + */ +typedef struct { + char *name; + void *(*setup)(void); + void (*unset)(void **); + int (*run)( + module_id_t, int, int, int, int, int, UE_list_t *, int, int, contig_rbs_t *, void *); + void *data; +} default_sched_ul_algo_t; + +typedef void (*pp_impl_dl)(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe); +typedef void (*pp_impl_ul)(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe, + frame_t sched_frame, + sub_frame_t sched_subframe); + +struct slice_info_s; +typedef struct { + int algorithm; + + /// inform the slice algorithm about a new UE + void (*add_UE)(struct slice_info_s *s, int UE_id); + /// inform the slice algorithm about a UE that disconnected + void (*remove_UE)(struct slice_info_s *s, int UE_id); + /// move a UE to a slice in DL/UL, -1 means don't move (no-op). + void (*move_UE)(struct slice_info_s *s, int UE_id, int idx); + + /// Adds a new slice through admission control. slice_params are + /// algorithm-specific parameters. sched is either a default_sched_ul_algo_t + /// or default_sched_dl_algo_t, depending on whether this implementation + /// handles UL/DL. If slice at index exists, updates existing + /// slice. Returns index of new slice or -1 on failure. + int (*addmod_slice)(struct slice_info_s *s, + int id, + char *label, + void *sched, + void *slice_params); + /// Returns slice through slice_idx. 1 if successful, 0 if not. + int (*remove_slice)(struct slice_info_s *s, uint8_t slice_idx); + + union { + pp_impl_dl dl; + pp_impl_ul ul; + }; + + union { + default_sched_ul_algo_t ul_algo; + default_sched_dl_algo_t dl_algo; + }; + + void (*destroy)(struct slice_info_s **s); + + struct slice_info_s *slices; +} pp_impl_param_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1395,9 +1369,6 @@ typedef struct eNB_MAC_INST_s { uint32_t ul_handle; UE_info_t UE_info; - /// slice-related configuration - slice_info_t slice_info; - ///subband bitmap configuration SBMAP_CONF sbmap_conf; /// CCE table used to build DCI scheduling information @@ -1432,6 +1403,11 @@ typedef struct eNB_MAC_INST_s { UE_free_list_t UE_free_list; /// for scheduling selection SCHEDULER_MODES scheduler_mode; + /// Default scheduler: Pre-processor implementation. Algorithms for UL/DL + /// are called by ULSCH/DLSCH, respectively. Pro-processor implementation can + /// encapsulate slicing. + pp_impl_param_t pre_processor_dl; + pp_impl_param_t pre_processor_ul; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 2cb86c25af..9d49fdffd5 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -187,8 +187,6 @@ void add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP, void init_UE_info(UE_info_t *UE_info); -void init_slice_info(slice_info_t *sli); - int mac_top_init(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, uint8_t HO_active); @@ -661,6 +659,7 @@ int prev(UE_list_t *listP, int nodeP); void add_ue_list(UE_list_t *listP, int UE_id); int remove_ue_list(UE_list_t *listP, int UE_id); void dump_ue_list(UE_list_t *listP); +void init_ue_list(UE_list_t *listP); int UE_num_active_CC(UE_info_t *listP, int ue_idP); int UE_PCCID(module_id_t mod_idP, int ue_idP); rnti_t UE_RNTI(module_id_t mod_idP, int ue_idP); @@ -675,10 +674,10 @@ void set_ul_DAI(int module_idP, void ulsch_scheduler_pre_processor(module_id_t module_idP, int CC_id, - int frameP, + frame_t frameP, sub_frame_t subframeP, - int sched_frameP, - unsigned char sched_subframeP); + frame_t sched_frameP, + sub_frame_t sched_subframeP); int phy_stats_exist(module_id_t Mod_id, int rnti); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 1a88623a1f..af6d1a7ac3 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -45,11 +45,8 @@ extern RAN_CONTEXT_t RC; void init_UE_info(UE_info_t *UE_info) { - int list_el; UE_info->num_UEs = 0; - UE_info->list.head = -1; - for (list_el = 0; list_el < MAX_MOBILES_PER_ENB; list_el++) - UE_info->list.next[list_el] = -1; + init_ue_list(&UE_info->list); memset(UE_info->DLSCH_pdu, 0, sizeof(UE_info->DLSCH_pdu)); memset(UE_info->UE_template, 0, sizeof(UE_info->UE_template)); memset(UE_info->eNB_UE_stats, 0, sizeof(UE_info->eNB_UE_stats)); @@ -57,32 +54,6 @@ void init_UE_info(UE_info_t *UE_info) memset(UE_info->active, 0, sizeof(UE_info->active)); } -void init_slice_info(slice_info_t *sli) -{ - sli->intraslice_share_active = 1; - sli->interslice_share_active = 1; - - sli->n_dl = 1; - memset(sli->dl, 0, sizeof(slice_sched_conf_dl_t) * MAX_NUM_SLICES); - sli->dl[0].pct = 1.0; - sli->dl[0].prio = 10; - sli->dl[0].pos_high = N_RBG_MAX; - sli->dl[0].maxmcs = 28; - sli->dl[0].sorting = 0x012345; - sli->dl[0].sched_name = "schedule_ue_spec"; - sli->dl[0].sched_cb = dlsym(NULL, sli->dl[0].sched_name); - AssertFatal(sli->dl[0].sched_cb, "DLSCH scheduler callback is NULL\n"); - - sli->n_ul = 1; - memset(sli->ul, 0, sizeof(slice_sched_conf_ul_t) * MAX_NUM_SLICES); - sli->ul[0].pct = 1.0; - sli->ul[0].maxmcs = 20; - sli->ul[0].sorting = 0x0123; - sli->ul[0].sched_name = "schedule_ulsch_rnti"; - sli->ul[0].sched_cb = dlsym(NULL, sli->ul[0].sched_name); - AssertFatal(sli->ul[0].sched_cb, "ULSCH scheduler callback is NULL\n"); -} - void mac_top_init_eNB(void) { module_id_t i, j; @@ -129,8 +100,23 @@ void mac_top_init_eNB(void) mac[i]->if_inst = IF_Module_init(i); + mac[i]->pre_processor_dl.algorithm = 0; + mac[i]->pre_processor_dl.dl = dlsch_scheduler_pre_processor; + char *s = "round_robin_dl"; + void *d = dlsym(NULL, s); + AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); + mac[i]->pre_processor_dl.dl_algo = *(default_sched_dl_algo_t *) d; + mac[i]->pre_processor_dl.dl_algo.data = mac[i]->pre_processor_dl.dl_algo.setup(); + + mac[i]->pre_processor_ul.algorithm = 0; + mac[i]->pre_processor_ul.ul = ulsch_scheduler_pre_processor; + s = "round_robin_ul"; + d = dlsym(NULL, s); + AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); + mac[i]->pre_processor_ul.ul_algo = *(default_sched_ul_algo_t *) d; + mac[i]->pre_processor_ul.ul_algo.data = mac[i]->pre_processor_ul.ul_algo.setup(); + init_UE_info(&mac[i]->UE_info); - init_slice_info(&mac[i]->slice_info); } RC.mac = mac; diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 8569d8f166..6477d60021 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -69,31 +69,367 @@ int get_rbg_size_last(module_id_t Mod_id, int CC_id) { return RBGsize; } -int g_start_ue_dl = -1; -int round_robin_dl(module_id_t Mod_id, - int CC_id, - int frame, - int subframe, - UE_list_t *UE_list, - int max_num_ue, - int n_rbg_sched, - uint8_t *rbgalloc_mask) { +void *rr_dl_setup(void) { + void *data = malloc(sizeof(int)); + *(int *) data = 0; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void rr_dl_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int rr_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { DevAssert(UE_list->head >= 0); DevAssert(n_rbg_sched > 0); const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); const int RBGsize = get_min_rb_unit(Mod_id, CC_id); const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); - int num_ue_req = 0; UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request - memset(rb_required, 0, sizeof(rb_required)); - int rbg = 0; for (; !rbgalloc_mask[rbg]; rbg++) ; /* fast-forward to first allowed RBG */ - // Calculate the amount of RBs every UE wants to send. + /* just start with the UE after the one we had last time. If it does not + * exist, this will start at the head */ + int *start_ue = data; + *start_ue = next_ue_list_looped(UE_list, *start_ue); + + int UE_id = *start_ue; + UE_list_t UE_sched; + int *cur_UE = &UE_sched.head; + // Allocate retransmissions, and mark UEs with new transmissions + do { + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + goto skip_ue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + goto skip_ue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + goto skip_ue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + goto skip_ue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) { + *cur_UE = UE_id; + cur_UE = &UE_sched.next[UE_id]; + } + } + +skip_ue: + UE_id = next_ue_list_looped(UE_list, UE_id); + } while (UE_id != *start_ue); + *cur_UE = -1; // mark end + + if (UE_sched.head < 0) + return n_rbg_sched; // no UE has a transmission + + // after allocating retransmissions: pre-allocate CCE, compute number of + // requested RBGs + max_num_ue = min(max_num_ue, n_rbg_sched); + int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request + cur_UE = &UE_sched.head; + while (*cur_UE >= 0 && max_num_ue > 0) { + const int UE_id = *cur_UE; + cur_UE = &UE_sched.next[UE_id]; // go to next + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) { + LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id); + continue; + } + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + const uint32_t B = UE_info->UE_template[CC_id][UE_id].dl_buffer_total; + rb_required[UE_id] = find_nb_rb_DL(mcs, B, n_rbg_sched * RBGsize, RBGsize); + max_num_ue--; + } + *cur_UE = -1; // not all UEs might be allocated, mark end + + /* for one UE after the next: allocate resources */ + cur_UE = &UE_sched.head; + while (*cur_UE >= 0) { + const int UE_id = *cur_UE; + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + rb_required[UE_id] -= sRBG; + if (rb_required[UE_id] <= 0) { + *cur_UE = UE_sched.next[*cur_UE]; + if (*cur_UE < 0) + cur_UE = &UE_sched.head; + } else { + cur_UE = UE_sched.next[*cur_UE] < 0 ? &UE_sched.head : &UE_sched.next[*cur_UE]; + } + n_rbg_sched--; + if (n_rbg_sched <= 0) + break; + for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } + + return n_rbg_sched; +} +default_sched_dl_algo_t round_robin_dl = { + .name = "round_robin_dl", + .setup = rr_dl_setup, + .unset = rr_dl_unset, + .run = rr_dl_run, + .data = NULL +}; + + +void *pf_dl_setup(void) { + void *data = calloc(MAX_MOBILES_PER_ENB, sizeof(float)); + for (int i = 0; i < MAX_MOBILES_PER_ENB; i++) + *(float *) data = 0.0f; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void pf_dl_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int pf_wbcqi_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + UE_list_t UE_sched; // UEs that could be scheduled + int *uep = &UE_sched.head; + float *thr_ue = data; + float coeff_ue[MAX_MOBILES_PER_ENB]; + + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + const float a = 0.0005f; // corresponds to 200ms window + const uint32_t b = UE_info->eNB_UE_stats[CC_id][UE_id].TBS; + thr_ue[UE_id] = (1 - a) * thr_ue[UE_id] + a * b; + + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + continue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + continue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + continue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0) + continue; + + const int mcs = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; + const uint32_t tbs = get_TBS_DL(mcs, RBGsize); + coeff_ue[UE_id] = (float) tbs / thr_ue[UE_id]; + //LOG_I(MAC, " pf UE %d: old TBS %d thr %f MCS %d TBS %d coeff %f\n", + // UE_id, b, thr_ue[UE_id], mcs, tbs, coeff_ue[UE_id]); + *uep = UE_id; + uep = &UE_sched.next[UE_id]; + } + } + *uep = -1; + + while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) { + int *max = &UE_sched.head; /* assume head is max */ + int *p = &UE_sched.next[*max]; + while (*p >= 0) { + /* if the current one has larger coeff, save for later */ + if (coeff_ue[*p] > coeff_ue[*max]) + max = p; + p = &UE_sched.next[*p]; + } + /* remove the max one */ + const int UE_id = *max; + p = &UE_sched.next[*max]; + *max = UE_sched.next[*max]; + *p = -1; + + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + + max_num_ue--; + + /* allocate as much as possible */ + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + int req = find_nb_rb_DL(mcs, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + while (req > 0 && n_rbg_sched > 0) { + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + req -= sRBG; + n_rbg_sched--; + for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } + } + + return n_rbg_sched; +} +default_sched_dl_algo_t proportional_fair_wbcqi_dl = { + .name = "proportional_fair_wbcqi_dl", + .setup = pf_dl_setup, + .unset = pf_dl_unset, + .run = pf_wbcqi_dl_run, + .data = NULL +}; + +void *mt_dl_setup(void) { + return NULL; +} +void mt_dl_unset(void **data) { + *data = NULL; +} +int mt_wbcqi_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + UE_list_t UE_sched; // UEs that could be scheduled + int *uep = &UE_sched.head; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { // check whether there are HARQ retransmissions const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; @@ -133,6 +469,7 @@ int round_robin_dl(module_id_t Mod_id, if (!rbgalloc_mask[rbg]) continue; ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; nb_rbg--; } LOG_D(MAC, @@ -150,90 +487,69 @@ int round_robin_dl(module_id_t Mod_id, return n_rbg_sched; for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } else { - const int dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; - UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = dlsch_mcs1; - rb_required[UE_id] = - find_nb_rb_DL(dlsch_mcs1, - UE_info->UE_template[CC_id][UE_id].dl_buffer_total, - n_rbg_sched * RBGsize, - RBGsize); - if (rb_required[UE_id] > 0) - num_ue_req++; - LOG_D(MAC, - "%d/%d UE_id %d rb_required %d n_rbg_sched %d\n", - frame, - subframe, - UE_id, - rb_required[UE_id], - n_rbg_sched); + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0) + continue; + *uep = UE_id; + uep = &UE_sched.next[UE_id]; } } + *uep = -1; - if (num_ue_req == 0) - return n_rbg_sched; // no UE has a transmission + while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) { + int *max = &UE_sched.head; /* assume head is max */ + int *p = &UE_sched.next[*max]; + while (*p >= 0) { + /* if the current one has better CQI, or the same and more data */ + const uint8_t maxCqi = UE_info->UE_sched_ctrl[*max].dl_cqi[CC_id]; + const uint32_t maxB = UE_info->UE_template[CC_id][*max].dl_buffer_total; + const uint8_t pCqi = UE_info->UE_sched_ctrl[*p].dl_cqi[CC_id]; + const uint32_t pB = UE_info->UE_template[CC_id][*p].dl_buffer_total; + if (pCqi > maxCqi || (pCqi == maxCqi && pB > maxB)) + max = p; + p = &UE_sched.next[*p]; + } + /* remove the max one */ + const int UE_id = *max; + p = &UE_sched.next[*max]; + *max = UE_sched.next[*max]; + *p = -1; - // after allocating retransmissions: build list of UE to allocate. - // if start_UE does not exist anymore (detach etc), start at first UE - if (g_start_ue_dl == -1) - g_start_ue_dl = UE_list->head; - int UE_id = g_start_ue_dl; - UE_list_t UE_sched; - int rb_required_total = 0; - int num_ue_sched = 0; - max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); - int *cur_UE = &UE_sched.head; - while (num_ue_sched < max_num_ue) { - while (rb_required[UE_id] == 0) - UE_id = next_ue_list_looped(UE_list, UE_id); const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); - if (idx < 0) { - LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id); - num_ue_req--; - max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); - UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate + if (idx < 0) continue; - } UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; - *cur_UE = UE_id; - cur_UE = &UE_sched.next[UE_id]; - rb_required_total += rb_required[UE_id]; - num_ue_sched++; - UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate - } - *cur_UE = -1; - /* for one UE after the next: allocate resources */ - for (int UE_id = UE_sched.head; UE_id >= 0; - UE_id = next_ue_list_looped(&UE_sched, UE_id)) { - if (rb_required[UE_id] <= 0) - continue; + max_num_ue--; + + /* allocate as much as possible */ + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + int req = find_nb_rb_DL(mcs, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; - ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; - const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; - ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; - rb_required[UE_id] -= sRBG; - rb_required_total -= sRBG; - if (rb_required_total <= 0) - break; - n_rbg_sched--; - if (n_rbg_sched <= 0) - break; - for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; - } - - /* if not all UEs could be allocated in this round */ - if (num_ue_req > max_num_ue) { - /* go to the first one we missed */ - for (int i = 0; i < max_num_ue; ++i) - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - } else { - /* else, just start with the next UE next time */ - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + while (req > 0 && n_rbg_sched > 0) { + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + req -= sRBG; + n_rbg_sched--; + for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } } return n_rbg_sched; } +default_sched_dl_algo_t maximum_throughput_wbcqi_dl = { + .name = "maximum_throughput_wbcqi_dl", + .setup = mt_dl_setup, + .unset = mt_dl_unset, + .run = mt_wbcqi_dl_run, + .data = NULL +}; // This function stores the downlink buffer for all the logical channels void @@ -295,6 +611,18 @@ store_dlsch_buffer(module_id_t Mod_id, #endif } + /* hack: in schedule_ue_spec, 3 bytes are "reserved" (this should be + * done better). An RLC AM entity may ask for only 2 bytes for + * ACKing and get a TBS of 32 bits and due to these 3 reserved bytes we may + * end up with only 1 byte left for RLC, which is not enough. This hack + * prevents the problem. To be done better at some point. If the function + * schedule_ue_spec is (has been) reworked, this hack can be removed. + * Dig for "TBS - ta_len - header_length_total - sdu_length_total - 3" + * in schedule_ue_spec. + */ + if (UE_template->dl_buffer_total > 0 && UE_template->dl_buffer_total <= 2) + UE_template->dl_buffer_total += 3; + if (UE_template->dl_buffer_total > 0) LOG_D(MAC, "[eNB %d] Frame %d Subframe %d : RLC status for UE %d : total DL buffer size %d and total number of pdu %d \n", @@ -311,19 +639,18 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, frame_t frameP, sub_frame_t subframeP) { - UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + eNB_MAC_INST *mac = RC.mac[Mod_id]; + UE_info_t *UE_info = &mac->UE_info; + const int N_RBG = to_rbg(mac->common_channels[CC_id].mib->message.dl_Bandwidth); const int RBGsize = get_min_rb_unit(Mod_id, CC_id); store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP); UE_list_t UE_to_sched; - UE_to_sched.head = -1; for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) UE_to_sched.next[i] = -1; + int *cur = &UE_to_sched.head; - int first = 1; - int last_UE_id = -1; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; const UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; @@ -356,20 +683,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, } /* define UEs to schedule */ - if (first) { - first = 0; - UE_to_sched.head = UE_id; - } else { - UE_to_sched.next[last_UE_id] = UE_id; - } - UE_to_sched.next[UE_id] = -1; - last_UE_id = UE_id; + *cur = UE_id; + cur = &UE_to_sched.next[UE_id]; } + *cur = -1; if (UE_to_sched.head < 0) return; - uint8_t *vrb_map = RC.mac[Mod_id]->common_channels[CC_id].vrb_map; + uint8_t *vrb_map = mac->common_channels[CC_id].vrb_map; uint8_t rbgalloc_mask[N_RBG_MAX]; int n_rbg_sched = 0; for (int i = 0; i < N_RBG; i++) { @@ -381,14 +703,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, n_rbg_sched += rbgalloc_mask[i]; } - round_robin_dl(Mod_id, - CC_id, - frameP, - subframeP, - &UE_to_sched, - 4, // max_num_ue - n_rbg_sched, - rbgalloc_mask); + mac->pre_processor_dl.dl_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + &UE_to_sched, + 4, // max_num_ue + n_rbg_sched, + rbgalloc_mask, + mac->pre_processor_dl.dl_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for @@ -500,17 +823,28 @@ int pp_find_rb_table_index(int approximate) { return p + 1; } -int g_start_ue_ul = -1; -int round_robin_ul(module_id_t Mod_id, - int CC_id, - int frame, - int subframe, - int sched_frame, - int sched_subframe, - UE_list_t *UE_list, - int max_num_ue, - int num_contig_rb, - contig_rbs_t *rbs) { +void *rr_ul_setup(void) { + void *data = malloc(sizeof(int)); + *(int *) data = 0; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void rr_ul_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int rr_ul_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + int sched_frame, + int sched_subframe, + UE_list_t *UE_list, + int max_num_ue, + int num_contig_rb, + contig_rbs_t *rbs, + void *data) { AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n"); UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length; @@ -650,9 +984,10 @@ int round_robin_ul(module_id_t Mod_id, end = la > lb ? 2 : -1; } - if (g_start_ue_ul == -1) - g_start_ue_ul = UE_list->head; - int sUE_id = g_start_ue_ul; + int *start_ue = data; + if (*start_ue == -1) + *start_ue = UE_list->head; + int sUE_id = *start_ue; int rb_idx_given[MAX_MOBILES_PER_ENB]; memset(rb_idx_given, 0, sizeof(rb_idx_given)); @@ -730,35 +1065,35 @@ int round_robin_ul(module_id_t Mod_id, } } - /* if not all UEs could be allocated in this round */ - if (num_ue_req > max_num_ue) { - /* go to the first one we missed */ - for (int i = 0; i < max_num_ue; ++i) - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); - } else { - /* else, just start with the next UE next time */ - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); - } + /* just start with the next UE next time */ + *start_ue = next_ue_list_looped(UE_list, *start_ue); return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); } +default_sched_ul_algo_t round_robin_ul = { + .name = "round_robin_ul", + .setup = rr_ul_setup, + .unset = rr_ul_unset, + .run = rr_ul_run, + .data = NULL +}; void ulsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, - int frameP, + frame_t frameP, sub_frame_t subframeP, - int sched_frameP, - unsigned char sched_subframeP) { - UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - const int N_RB_UL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].ul_Bandwidth); - COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + frame_t sched_frameP, + sub_frame_t sched_subframeP) { + eNB_MAC_INST *mac = RC.mac[Mod_id]; + UE_info_t *UE_info = &mac->UE_info; + const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &mac->common_channels[CC_id]; UE_list_t UE_to_sched; - UE_to_sched.head = -1; for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) UE_to_sched.next[i] = -1; + int *cur = &UE_to_sched.head; - int last_UE_id = -1; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; @@ -781,13 +1116,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, continue; /* define UEs to schedule */ - if (UE_to_sched.head < 0) - UE_to_sched.head = UE_id; - else - UE_to_sched.next[last_UE_id] = UE_id; - UE_to_sched.next[UE_id] = -1; - last_UE_id = UE_id; + *cur = UE_id; + cur = &UE_to_sched.next[UE_id]; } + *cur = -1; if (UE_to_sched.head < 0) return; @@ -808,16 +1140,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, } } - round_robin_ul(Mod_id, - CC_id, - frameP, - subframeP, - sched_frameP, - sched_subframeP, - &UE_to_sched, - 4, // max_num_ue - n_contig, - rbs); + mac->pre_processor_ul.ul_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + sched_frameP, + sched_subframeP, + &UE_to_sched, + 4, // max_num_ue + n_contig, + rbs, + mac->pre_processor_ul.ul_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for @@ -836,7 +1169,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, continue; print = 1; - uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id], + uint8_t harq_pid = subframe2harqpid(&mac->common_channels[CC_id], sched_frameP, sched_subframeP); LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", frameP, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 5801fabcfb..d8583167dd 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -24,8 +24,8 @@ * \author R. Knopp, K.H. HSU, G. Casati * \date 2019 * \version 0.1 - * \company Eurecom / NTUST / Fraunhofer IIS - * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de + * \company Eurecom / NTUST / Fraunhofer IIS + * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -41,6 +41,10 @@ #define NR_BCCH_BCH 5 // MIB +#define CCCH_PAYLOAD_SIZE_MAX 128 + +#define RAR_PAYLOAD_SIZE_MAX 128 + // For both DL/UL-SCH // Except: // - UL/DL-SCH: fixed-size MAC CE(known by LCID) @@ -67,36 +71,234 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L:8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L1:8; // octet 2 [7:0] - uint8_t L2:8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t R:2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; +// BSR MAC CEs +// TS 38.321 ch. 6.1.3.1 +// Short BSR for a specific logical channel group ID +typedef struct { + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB +} __attribute__ ((__packed__)) NR_BSR_SHORT; + +typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; + +// Long BSR for all logical channel group ID +typedef struct { + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; +} __attribute__ ((__packed__)) NR_BSR_LONG; + +typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; + // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND:6; // octet 1 [5:0] - uint8_t TAGID:2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; +// single Entry PHR MAC CE +// TS 38.321 ch. 6.1.3.8 +typedef struct { + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; +} __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; + + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +// 38.321 ch. 6.1.3.19 +typedef struct { + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4; // octet 2 [7:4] +} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; + +//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE +typedef struct { + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] +} __attribute__ ((__packed__)) NR_TCI_PDCCH; + +//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 +} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; + +//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] +} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; + + +//TS 38.321 sec 6.1.3.12 +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; +} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; + + +//* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// +// - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU +// - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID) +// - R: Reserved bit, set to "0" +// - BI: The Backoff Indicator field identifies the overload condition in the cell. +// - RAPID: The Random Access Preamble IDentifier field identifies the transmitted Random Access Preamble + +/*!\brief RAR MAC subheader with RAPID */ +typedef struct { + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; +} __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; + +/*!\brief RAR MAC subheader with Backoff Indicator */ +typedef struct { + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; +} __attribute__ ((__packed__)) NR_RA_HEADER_BI; + +// TS 38.321 ch. 6.2.3 +typedef struct { + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] +} __attribute__ ((__packed__)) NR_MAC_RAR; + +// DCI pdu structures. Used by both gNB and UE. +typedef struct { + uint16_t val; + uint8_t nbits; +} dci_field_t; + +typedef struct { + + uint8_t format_indicator; //1 bit + uint8_t ra_preamble_index; //6 bits + uint8_t ss_pbch_index; //6 bits + uint8_t prach_mask_index; //4 bits + uint8_t mcs; //5 bits + uint8_t ndi; //1 bit + uint8_t rv; //2 bits + uint8_t harq_pid; //4 bits + uint8_t tpc; //2 bits + uint8_t short_messages_indicator; //2 bits + uint8_t short_messages; //8 bits + uint8_t tb_scaling; //2 bits + uint8_t pucch_resource_indicator; //3 bits + uint8_t system_info_indicator; //1 bit + uint8_t ulsch_indicator; + uint8_t slot_format_indicator_count; + uint8_t *slot_format_indicators; + + uint8_t pre_emption_indication_count; + uint16_t *pre_emption_indications; //14 bit each + + uint8_t block_number_count; + uint8_t *block_numbers; + uint8_t padding; + + dci_field_t mcs2; //variable + dci_field_t ndi2; //variable + dci_field_t rv2; //variable + dci_field_t frequency_domain_assignment; //variable + dci_field_t time_domain_assignment; //variable + dci_field_t frequency_hopping_flag; //variable + dci_field_t vrb_to_prb_mapping; //variable + dci_field_t dai[2]; //variable + dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable + dci_field_t carrier_indicator; //variable + dci_field_t bwp_indicator; //variable + dci_field_t prb_bundling_size_indicator; //variable + dci_field_t rate_matching_indicator; //variable + dci_field_t zp_csi_rs_trigger; //variable + dci_field_t transmission_configuration_indication; //variable + dci_field_t srs_request; //variable + dci_field_t cbgti; //variable + dci_field_t cbgfi; //variable + dci_field_t srs_resource_indicator; //variable + dci_field_t precoding_information; //variable + dci_field_t csi_request; //variable + dci_field_t ptrs_dmrs_association; //variable + dci_field_t beta_offset_indicator; //variable + dci_field_t cloded_loop_indicator; //variable + dci_field_t ul_sul_indicator; //variable + dci_field_t antenna_ports; //variable + dci_field_t dmrs_sequence_initialization; + dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + +} dci_pdu_rel15_t; + // 38.321 ch6.2.1, 38.331 #define DL_SCH_LCID_CCCH 0x00 #define DL_SCH_LCID_DCCH 0x01 #define DL_SCH_LCID_DCCH1 0x02 -#define DL_SCH_LCID_DTCH 0x03 +#define DL_SCH_LCID_DTCH 0x04 #define DL_SCH_LCID_RECOMMENDED_BITRATE 0x2F #define DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT 0x30 #define DL_SCH_LCID_PUCCH_SPATIAL_RELATION_ACT 0x31 @@ -105,7 +307,7 @@ typedef struct { #define DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH 0x34 #define DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH 0x35 #define DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL 0x36 -#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 +#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 #define DL_SCH_LCID_DUPLICATION_ACT 0X38 #define DL_SCH_LCID_SCell_ACT_4_OCT 0X39 #define DL_SCH_LCID_SCell_ACT_1_OCT 0X3A @@ -118,8 +320,8 @@ typedef struct { #define UL_SCH_LCID_CCCH 0x00 #define UL_SCH_LCID_SRB1 0x01 #define UL_SCH_LCID_SRB2 0x02 -#define UL_SCH_LCID_DTCH 0x03 -#define UL_SCH_LCID_SRB3 0x04 +#define UL_SCH_LCID_SRB3 0x03 +#define UL_SCH_LCID_DTCH 0x04 #define UL_SCH_LCID_CCCH_MSG3 0x21 #define UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY 0x35 #define UL_SCH_LCID_MULTI_ENTRY_PHR_4_OCT 0x36 @@ -133,9 +335,9 @@ typedef struct { #define UL_SCH_LCID_L_BSR 0x3E #define UL_SCH_LCID_PADDING 0x3F -#define NR_MAX_NUM_LCID 32 -#define NR_MAX_NUM_LCGID 8 -#define MAX_RLC_SDU_SUBHEADER_SIZE 3 +#define NR_MAX_NUM_LCID 32 +#define NR_MAX_NUM_LCGID 8 +#define MAX_RLC_SDU_SUBHEADER_SIZE 3 #endif /*__LAYER2_MAC_H__ */ diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index cfde40daad..f40d822b6b 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -31,6 +31,1169 @@ */ #include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include + +const uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; + +// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz +uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419}; +uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A +uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B + +// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz +uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419}; +uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A +uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B + +// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} +uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; + +const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; +const char *prachfmt03[]={"0","1","2","3"}; + +uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) { + + LOG_D(MAC,"get_NCS: indx %d,format0 %d, restriced_set_config %d\n", + index,format0,restricted_set_config); + + if (format0 < 3) { + switch(restricted_set_config){ + case 0: + return(NCS_unrestricted_delta_f_RA_125[index]); + case 1: + return(NCS_restricted_TypeA_delta_f_RA_125[index]); + case 2: + return(NCS_restricted_TypeB_delta_f_RA_125[index]); + default: + AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config); + } + } + else { + if (format0 == 3) { + switch(restricted_set_config){ + case 0: + return(NCS_unrestricted_delta_f_RA_5[index]); + case 1: + return(NCS_restricted_TypeA_delta_f_RA_5[index]); + case 2: + return(NCS_restricted_TypeB_delta_f_RA_5[index]); + default: + AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config); + } + } + else + return(NCS_unrestricted_delta_f_RA_15[index]); + } +} + + +// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink +// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. +// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. +// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6 +int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = { +//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration +{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 +{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 +{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 +{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 +{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 +{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 +{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 +{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 +{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 +{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 +{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 +{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 +{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 +{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 +{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 +{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 +{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 +{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9 +{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 +{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 +{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 +{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 +{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 +{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 +{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 +{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 +{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 +{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 +{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 +{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 +{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 +{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 +{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 +{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 +{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 +{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4 +{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6 +{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 +{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 +{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 +{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7 +{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7 +{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8 +{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9 +{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 +{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 +{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 +{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 +{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 +{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 +{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 +{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 +{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 +{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 +{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 +{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7 +{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 +{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 +{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9 +{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 +{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 +{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 +{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 +{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 +{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 +{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 +{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 +{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 +{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 +{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 +{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 +{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 +{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 +{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 +{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9 +{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 +{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 +{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 +{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 +{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 +{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 +{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 +{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 +{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 +{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 +{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 +{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 +{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 +{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 +{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 +{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 +{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6 +{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7 +{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 +{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7 +{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8 +{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9 +{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 +{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 +{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 +{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 +{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 +{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 +{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 +{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 +{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 +{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 +{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 +{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 +{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 +{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 +{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 +{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 +{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 +{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 +{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 +{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 +{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 +{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9 +}; +// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum +int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = { +//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration +{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) +{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) +{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) +{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) +{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) +{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) +{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) +{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) +{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) +{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) +{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) +{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) +{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) +{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) +{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) +{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) +{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9) +{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) +{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) +{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7) +{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6) +{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6) +{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6) +{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6) +{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6) +{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6) +{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) +{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) +{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) +{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) +{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) +{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) +{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) +{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) +{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) +{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) +{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) +{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) +{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) +{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) +{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) +{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) +{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) +{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) +{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) +{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) +{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) +{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9) +{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9) +{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9) +{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9) +{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9) +{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9) +{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9) +{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9) +{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9) +{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) +{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9) +{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9) +{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9) +{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9) +{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9) +{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9) +{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9) +{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9) +{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9) +{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9) +{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9) +{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) +{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9) +{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2) +{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7) +{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7) +{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) +{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9) +{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) +{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9) +{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9) +{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) +{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) +{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) +{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2) +{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7) +{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7) +{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) +{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9) +{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9) +{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) +{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) +{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) +{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) +{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) +{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) +{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) +{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9) +{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9) +{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9) +{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9) +{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9) +{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9) +{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9) +{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1) +{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2) +{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4) +{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7) +{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9) +{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9) +{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9) +{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9) +{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9) +{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9) +{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9) +{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) +{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) +{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) +{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) +{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) +{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) +{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9) +{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) +{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9) +{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9) +{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9) +{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) +{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9) +{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9) +{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9) +{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) +{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9) +{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9) +{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9) +{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9) +{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9) +{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9) +{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9) +{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) +{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) +{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) +{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) +{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) +{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) +{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) +{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) +{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) +{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) +{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) +{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9) +{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9) +{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) +{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) +{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9) +{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) +{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) +{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) +{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9) +{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) +{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) +{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) +{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9) +{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) +{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) +{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) +{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) +{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) +{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) +{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9) +{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) +{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) +{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9) +}; +// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum +int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { +//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration +{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39) +{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39) +{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7) +{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39) +{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39) +{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39) +{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) +{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39) +{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39) +{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39) +{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39) +{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39) +{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7) +{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39) +{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39) +{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39) +{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39) +{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39) +{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13) +{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13) +{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) +{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39) +{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39) +{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) +{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13) +{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) +{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) +{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) +{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39) +{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13) +{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) +{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) +{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) +{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) +{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7) +{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) +{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) +{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) +{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) +{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) +{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) +{0xb4, -1, 16, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 16, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 8, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 8, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) +{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 4, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 4, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39) +{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39) +{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39) +{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39) +{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39) +{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) +{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39) +{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39) +{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19) +{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13) +{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) +{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 586406201480, 2, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) +{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) +{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39) +{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39) +{0xc0, -1, 16, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 16, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 8, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 8, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 8, 1, 2, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) +{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 4, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 4, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39) +{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) +{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7) +{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) +{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) +{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39) +{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) +{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39) +{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) +{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) +{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39) +{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) +{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) +{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) +{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) +{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) +{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) +{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) +{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) +{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) +{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) +{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) +{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39) +{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) +{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) +{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) +{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) +{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) +{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa1, 0xb1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) +{0xa2, 0xb2, 16, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39) +{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39) +{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39) +{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39) +{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39) +{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39) +{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39) +{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) +{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) +{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39) +{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) +{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) +{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39) +{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39) +{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) +{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) +{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39) +}; + + +int get_format0(uint8_t index, + uint8_t unpaired){ + + uint16_t format; + if (unpaired) + format = table_6_3_3_2_3_prachConfig_Index[index][0]; + else + format = table_6_3_3_2_2_prachConfig_Index[index][0]; + + return format; +} + +void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, + uint16_t *slot_period, + uint16_t *offset) { + + switch(ss->monitoringSlotPeriodicityAndOffset->present) { + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1: + *slot_period = 1; + *offset = 0; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2: + *slot_period = 2; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4: + *slot_period = 4; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl4; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5: + *slot_period = 5; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl5; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8: + *slot_period = 8; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl8; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10: + *slot_period = 10; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl10; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16: + *slot_period = 16; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl16; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20: + *slot_period = 20; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl20; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40: + *slot_period = 40; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl40; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80: + *slot_period = 80; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl80; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160: + *slot_period = 160; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl160; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320: + *slot_period = 320; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl320; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640: + *slot_period = 640; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl640; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280: + *slot_period = 1280; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl1280; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560: + *slot_period = 2560; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2560; + break; + default: + AssertFatal(1==0,"Invalid monitoring slot periodicity and offset value\n"); + break; + } +} + +int get_nr_prach_info_from_index(uint8_t index, + int frame, + int slot, + uint32_t pointa, + uint8_t mu, + uint8_t unpaired, + uint16_t *format, + uint8_t *start_symbol, + uint8_t *N_t_slot, + uint8_t *N_dur) { + + int x,y; + int64_t s_map; + uint8_t format2 = 0xff; + + if (pointa > 2016666) { //FR2 + int y2; + uint8_t slot_60khz; + x = table_6_3_3_2_4_prachConfig_Index[index][2]; + y = table_6_3_3_2_4_prachConfig_Index[index][3]; + y2 = table_6_3_3_2_4_prachConfig_Index[index][4]; + // checking n_sfn mod x = y + if ( (frame%x)==y || (frame%x)==y2 ) { + slot_60khz = slot >> (mu-2); // in table slots are numbered wrt 60kHz + s_map = table_6_3_3_2_4_prachConfig_Index[index][5]; + if ( ((s_map>>slot_60khz)&0x01) ) { + if (mu == 3) { + if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 0) ) + return 0; // no prach in even slots @ 120kHz for 1 prach per 60khz slot + } + if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ + *start_symbol = table_6_3_3_2_4_prachConfig_Index[index][6]; + *N_t_slot = table_6_3_3_2_4_prachConfig_Index[index][8]; + *N_dur = table_6_3_3_2_4_prachConfig_Index[index][9]; + if (table_6_3_3_2_4_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_4_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_4_prachConfig_Index[index][0]) | (format2<<8); + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + slot, + index, + pointa, + mu, + unpaired, + *start_symbol, + *N_t_slot, + *N_dur); + } + return 1; + } + else + return 0; // no prach in current slot + } + else + return 0; // no prach in current frame + } + else { + uint8_t subframe; + if (unpaired) { + x = table_6_3_3_2_3_prachConfig_Index[index][2]; + y = table_6_3_3_2_3_prachConfig_Index[index][3]; + if ( (frame%x)==y ) { + subframe = slot >> mu; + s_map = table_6_3_3_2_3_prachConfig_Index[index][4]; + if ( (s_map>>subframe)&0x01 ) { + if (mu == 1) { + if ( (table_6_3_3_2_3_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) ) + return 0; // no prach in even slots @ 30kHz for 1 prach per subframe + } + if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ + *start_symbol = table_6_3_3_2_3_prachConfig_Index[index][5]; + *N_t_slot = table_6_3_3_2_3_prachConfig_Index[index][7]; + *N_dur = table_6_3_3_2_3_prachConfig_Index[index][8]; + if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8); + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d (col 6 %ld) absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + slot, + index, table_6_3_3_2_3_prachConfig_Index[index][6], + pointa, + mu, + unpaired, + *start_symbol, + *N_t_slot, + *N_dur); + } + return 1; + } + else + return 0; // no prach in current slot + } + else + return 0; // no prach in current frame + } + else { // FDD + x = table_6_3_3_2_2_prachConfig_Index[index][2]; + y = table_6_3_3_2_2_prachConfig_Index[index][3]; + if ( (frame%x)==y ) { + subframe = slot >> mu; + s_map = table_6_3_3_2_2_prachConfig_Index[index][4]; + if ( (s_map>>subframe)&0x01 ) { + if (mu == 1) { + if ( (table_6_3_3_2_2_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) ) + return 0; // no prach in even slots @ 30kHz for 1 prach per subframe + } + if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ + *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5]; + *N_t_slot = table_6_3_3_2_2_prachConfig_Index[index][7]; + *N_dur = table_6_3_3_2_2_prachConfig_Index[index][8]; + if (table_6_3_3_2_2_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_2_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_2_prachConfig_Index[index][0]) | (format2<<8); + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + slot, + index, + pointa, + mu, + unpaired, + *start_symbol, + *N_t_slot, + *N_dur); + } + return 1; + } + else + return 0; // no prach in current slot + } + else + return 0; // no prach in current frame + } + } +} + +//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 +uint16_t table_63313[838] = { +129, 710, 140, 699, 120, 719, 210, 629, 168, 671, 84 , 755, 105, 734, 93 , 746, 70 , 769, 60 , 779, +2 , 837, 1 , 838, 56 , 783, 112, 727, 148, 691, 80 , 759, 42 , 797, 40 , 799, 35 , 804, 73 , 766, +146, 693, 31 , 808, 28 , 811, 30 , 809, 27 , 812, 29 , 810, 24 , 815, 48 , 791, 68 , 771, 74 , 765, +178, 661, 136, 703, 86 , 753, 78 , 761, 43 , 796, 39 , 800, 20 , 819, 21 , 818, 95 , 744, 202, 637, +190, 649, 181, 658, 137, 702, 125, 714, 151, 688, 217, 622, 128, 711, 142, 697, 122, 717, 203, 636, +118, 721, 110, 729, 89 , 750, 103, 736, 61 , 778, 55 , 784, 15 , 824, 14 , 825, 12 , 827, 23 , 816, +34 , 805, 37 , 802, 46 , 793, 207, 632, 179, 660, 145, 694, 130, 709, 223, 616, 228, 611, 227, 612, +132, 707, 133, 706, 143, 696, 135, 704, 161, 678, 201, 638, 173, 666, 106, 733, 83 , 756, 91 , 748, +66 , 773, 53 , 786, 10 , 829, 9 , 830, 7 , 832, 8 , 831, 16 , 823, 47 , 792, 64 , 775, 57 , 782, +104, 735, 101, 738, 108, 731, 208, 631, 184, 655, 197, 642, 191, 648, 121, 718, 141, 698, 149, 690, +216, 623, 218, 621, 152, 687, 144, 695, 134, 705, 138, 701, 199, 640, 162, 677, 176, 663, 119, 720, +158, 681, 164, 675, 174, 665, 171, 668, 170, 669, 87 , 752, 169, 670, 88 , 751, 107, 732, 81 , 758, +82 , 757, 100, 739, 98 , 741, 71 , 768, 59 , 780, 65 , 774, 50 , 789, 49 , 790, 26 , 813, 17 , 822, +13 , 826, 6 , 833, 5 , 834, 33 , 806, 51 , 788, 75 , 764, 99 , 740, 96 , 743, 97 , 742, 166, 673, +172, 667, 175, 664, 187, 652, 163, 676, 185, 654, 200, 639, 114, 725, 189, 650, 115, 724, 194, 645, +195, 644, 192, 647, 182, 657, 157, 682, 156, 683, 211, 628, 154, 685, 123, 716, 139, 700, 212, 627, +153, 686, 213, 626, 215, 624, 150, 689, 225, 614, 224, 615, 221, 618, 220, 619, 127, 712, 147, 692, +124, 715, 193, 646, 205, 634, 206, 633, 116, 723, 160, 679, 186, 653, 167, 672, 79 , 760, 85 , 754, +77 , 762, 92 , 747, 58 , 781, 62 , 777, 69 , 770, 54 , 785, 36 , 803, 32 , 807, 25 , 814, 18 , 821, +11 , 828, 4 , 835, 3 , 836, 19 , 820, 22 , 817, 41 , 798, 38 , 801, 44 , 795, 52 , 787, 45 , 794, +63 , 776, 67 , 772, 72 , 767, 76 , 763, 94 , 745, 102, 737, 90 , 749, 109, 730, 165, 674, 111, 728, +209, 630, 204, 635, 117, 722, 188, 651, 159, 680, 198, 641, 113, 726, 183, 656, 180, 659, 177, 662, +196, 643, 155, 684, 214, 625, 126, 713, 131, 708, 219, 620, 222, 617, 226, 613, 230, 609, 232, 607, +262, 577, 252, 587, 418, 421, 416, 423, 413, 426, 411, 428, 376, 463, 395, 444, 283, 556, 285, 554, +379, 460, 390, 449, 363, 476, 384, 455, 388, 451, 386, 453, 361, 478, 387, 452, 360, 479, 310, 529, +354, 485, 328, 511, 315, 524, 337, 502, 349, 490, 335, 504, 324, 515, 323, 516, 320, 519, 334, 505, +359, 480, 295, 544, 385, 454, 292, 547, 291, 548, 381, 458, 399, 440, 380, 459, 397, 442, 369, 470, +377, 462, 410, 429, 407, 432, 281, 558, 414, 425, 247, 592, 277, 562, 271, 568, 272, 567, 264, 575, +259, 580, 237, 602, 239, 600, 244, 595, 243, 596, 275, 564, 278, 561, 250, 589, 246, 593, 417, 422, +248, 591, 394, 445, 393, 446, 370, 469, 365, 474, 300, 539, 299, 540, 364, 475, 362, 477, 298, 541, +312, 527, 313, 526, 314, 525, 353, 486, 352, 487, 343, 496, 327, 512, 350, 489, 326, 513, 319, 520, +332, 507, 333, 506, 348, 491, 347, 492, 322, 517, 330, 509, 338, 501, 341, 498, 340, 499, 342, 497, +301, 538, 366, 473, 401, 438, 371, 468, 408, 431, 375, 464, 249, 590, 269, 570, 238, 601, 234, 605, +257, 582, 273, 566, 255, 584, 254, 585, 245, 594, 251, 588, 412, 427, 372, 467, 282, 557, 403, 436, +396, 443, 392, 447, 391, 448, 382, 457, 389, 450, 294, 545, 297, 542, 311, 528, 344, 495, 345, 494, +318, 521, 331, 508, 325, 514, 321, 518, 346, 493, 339, 500, 351, 488, 306, 533, 289, 550, 400, 439, +378, 461, 374, 465, 415, 424, 270, 569, 241, 598, 231, 608, 260, 579, 268, 571, 276, 563, 409, 430, +398, 441, 290, 549, 304, 535, 308, 531, 358, 481, 316, 523, 293, 546, 288, 551, 284, 555, 368, 471, +253, 586, 256, 583, 263, 576, 242, 597, 274, 565, 402, 437, 383, 456, 357, 482, 329, 510, 317, 522, +307, 532, 286, 553, 287, 552, 266, 573, 261, 578, 236, 603, 303, 536, 356, 483, 355, 484, 405, 434, +404, 435, 406, 433, 235, 604, 267, 572, 302, 537, 309, 530, 265, 574, 233, 606, 367, 472, 296, 543, +336, 503, 305, 534, 373, 466, 280, 559, 279, 560, 419, 420, 240, 599, 258, 581, 229, 610 +}; + +uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, + uint8_t nb_preambles, + uint8_t unpaired) { + + uint8_t config_index = rach_config->rach_ConfigGeneric.prach_ConfigurationIndex; + uint8_t ncs_index = rach_config->rach_ConfigGeneric.zeroCorrelationZoneConfig; + uint16_t format0 = get_format0(config_index, unpaired); + uint16_t NCS = get_NCS(ncs_index, format0, rach_config->restrictedSetConfig); + uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present==NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139) ? 139 : 839; + uint16_t r,u,index,q,d_u,n_shift_ra,n_shift_ra_bar,d_start; + uint32_t w; + uint8_t found_preambles = 0; + uint8_t found_sequences = 0; + + if (rach_config->restrictedSetConfig == 0) { + if (NCS == 0) return nb_preambles; + else { + r = L_ra/NCS; + printf(" found_sequences %u\n", (nb_preambles/r)); + return (nb_preambles/r); + } + } + else{ + index = rach_config->prach_RootSequenceIndex.choice.l839; + while (found_preambles < nb_preambles) { + u = table_63313[index%(L_ra-1)]; + + q = 0; + while (((q*u)%L_ra) != 1) q++; + if (q < 420) d_u = q; + else d_u = L_ra - q; + + uint16_t n_group_ra = 0; + if (rach_config->restrictedSetConfig == 1) { + if ( (d_u<280) && (d_u>=NCS) ) { + n_shift_ra = d_u/NCS; + d_start = (d_u<<1) + (n_shift_ra * NCS); + n_group_ra = L_ra/d_start; + n_shift_ra_bar = max(0,(L_ra-(d_u<<1)-(n_group_ra*d_start))/L_ra); + } else if ( (d_u>=280) && (d_u<=((L_ra - NCS)>>1)) ) { + n_shift_ra = (L_ra - (d_u<<1))/NCS; + d_start = L_ra - (d_u<<1) + (n_shift_ra * NCS); + n_group_ra = d_u/d_start; + n_shift_ra_bar = min(n_shift_ra,max(0,(d_u- (n_group_ra*d_start))/NCS)); + } else { + n_shift_ra = 0; + n_shift_ra_bar = 0; + } + w = n_shift_ra*n_group_ra + n_shift_ra_bar; + found_preambles += w; + found_sequences++; + } + else { + AssertFatal(1==0,"Procedure to find nb of sequences for restricted type B not implemented yet"); + } + } + printf(" found_sequences %u\n", found_sequences); + return found_sequences; + } +} + nr_bandentry_t nr_bandtable[] = { {1, 1920000, 1980000, 2110000, 2170000, 20, 422000, 100}, @@ -373,13 +1536,23 @@ int32_t get_nr_uldl_offset(int nr_bandP) void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, - int x_overhead) { + int x_overhead, + uint8_t numdmrscdmgroupnodata, + uint8_t tb_scaling) { LOG_D(MAC, "TBS calculation\n"); nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15; uint16_t N_PRB_oh = x_overhead; - uint8_t N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 + uint8_t N_PRB_DMRS; + if (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) { + // if no data in dmrs cdm group is 1 only even REs have no data + // if no data in dmrs cdm group is 2 both odd and even REs have no data + N_PRB_DMRS = numdmrscdmgroupnodata*6; + } + else { + N_PRB_DMRS = numdmrscdmgroupnodata*4; + } uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; uint8_t Imcs = pdsch_rel15->mcsIndex[0]; uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; @@ -401,8 +1574,9 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, R, pdsch_rel15->rbSize, N_sh_symb, - N_PRB_DMRS, + N_PRB_DMRS, // FIXME // This should be multiplied by the number of dmrs symbols N_PRB_oh, + tb_scaling, pdsch_rel15->nrOfLayers)>>3; pdsch_rel15->targetCodeRate[0] = R; @@ -558,6 +1732,48 @@ int get_num_dmrs(uint16_t dmrs_mask ) { return(num_dmrs); } +// Table 5.1.2.2.1-1 38.214 +uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) { + + AssertFatal(bwp_size<276,"BWP Size > 275\n"); + + if (bwp_size < 37) return (rbg_size_config ? 4 : 2); + if (bwp_size < 73) return (rbg_size_config ? 8 : 4); + if (bwp_size < 145) return (rbg_size_config ? 16 : 8); + else return 16; +} + +uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { + + uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config); + + return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size); +} + +uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) { + + uint8_t nbitsA = 0; + uint8_t nbitsB = 0; + uint8_t type,length,nbits; + + if (typeA != NULL) { + type = (typeA->choice.setup->dmrs_Type==NULL) ? 1:2; + length = (typeA->choice.setup->maxLength==NULL) ? 1:2; + nbitsA = type + length + 2; + if (typeB == NULL) return nbitsA; + } + if (typeB != NULL) { + type = (typeB->choice.setup->dmrs_Type==NULL) ? 1:2; + length = (typeB->choice.setup->maxLength==NULL) ? 1:2; + nbitsB = type + length + 2; + if (typeA == NULL) return nbitsB; + } + + nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB; + return nbits; +} + + /******************************************************************* * * NAME : get_l0_ul @@ -664,11 +1880,24 @@ uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB) { return 1; } -uint16_t nr_dci_size(nr_dci_format_t format, +uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu, + nr_dci_format_t format, nr_rnti_type_t rnti_type, - uint16_t N_RB) { + uint16_t N_RB, + int bwp_id) { uint16_t size = 0; + uint16_t numRBG = 0; + long rbg_size_config; + int num_entries = 0; + int pusch_antenna_ports = 1; // TODO hardcoded number of antenna ports for pusch + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_PDSCH_Config_t *pdsch_config = bwp->bwp_Dedicated->pdsch_Config->choice.setup; + NR_PUSCH_Config_t *pusch_Config = ubwp->bwp_Dedicated->pusch_Config->choice.setup; + NR_SRS_Config_t *srs_config = ubwp->bwp_Dedicated->srs_Config->choice.setup; switch(format) { /*Only sizes for 0_0 and 1_0 are correct at the moment*/ @@ -676,30 +1905,199 @@ uint16_t nr_dci_size(nr_dci_format_t format, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size + size += nr_dci_size(scc,secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; case NR_UL_DCI_FORMAT_0_1: - /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, SRS request 2 --17 - size += 17; + /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, ULSCH indicator 1 --16 + size += 16; // Carrier indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { + dci_pdu->carrier_indicator.nbits=3; + size += dci_pdu->carrier_indicator.nbits; + } // UL/SUL indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink != NULL) { + dci_pdu->carrier_indicator.nbits=1; + size += dci_pdu->ul_sul_indicator.nbits; + } // BWP Indicator + uint8_t n_ul_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count; + if (n_ul_bwp < 2) + dci_pdu->bwp_indicator.nbits = n_ul_bwp; + else + dci_pdu->bwp_indicator.nbits = 2; + size += dci_pdu->bwp_indicator.nbits; // Freq domain assignment + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pusch_Config->choice.setup->rbg_Size != NULL) + rbg_size_config = 1; + else + rbg_size_config = 0; + numRBG = getNRBG(NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275), + NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275), + rbg_size_config); + if (pusch_Config->resourceAllocation == 0) + dci_pdu->frequency_domain_assignment.nbits = numRBG; + else if (pusch_Config->resourceAllocation == 1) + dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + else + dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; + size += dci_pdu->frequency_domain_assignment.nbits; // Time domain assignment - // VRB to PRB mapping + if (pusch_Config->pusch_TimeDomainAllocationList==NULL) { + if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList==NULL) + num_entries = 16; // num of entries in default table + else + num_entries = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; + } + else + num_entries = pusch_Config->pusch_TimeDomainAllocationList->choice.setup->list.count; + dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); + size += dci_pdu->time_domain_assignment.nbits; // Frequency Hopping flag + if ((pusch_Config->frequencyHopping!=NULL) && (pusch_Config->resourceAllocation != NR_PUSCH_Config__resourceAllocation_resourceAllocationType0)) { + dci_pdu->frequency_hopping_flag.nbits = 1; + size += 1; + } // 1st DAI + if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook==NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) + dci_pdu->dai[0].nbits = 2; + else + dci_pdu->dai[0].nbits = 1; + size += dci_pdu->dai[0].nbits; // 2nd DAI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { //TODO not sure about that + dci_pdu->dai[1].nbits = 2; + size += dci_pdu->dai[1].nbits; + } // SRS resource indicator + if (pusch_Config->txConfig != NULL){ + int count=0; + if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){ + for (int i=0; isrs_ResourceSetToAddModList->list.count; i++) { + if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_codebook) + count++; + } + if (count>1) { + dci_pdu->srs_resource_indicator.nbits = 1; + size += dci_pdu->srs_resource_indicator.nbits; + } + } + else { + int lmin,Lmax = 0; + int lsum = 0; + if ( secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig != NULL) { + if ( secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers != NULL) + Lmax = *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers; + else + AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n"); + } + else + AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n"); + for (int i=0; isrs_ResourceSetToAddModList->list.count; i++) { + if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_nonCodebook) + count++; + if (count < Lmax) lmin = count; + else lmin = Lmax; + for (int k=1;k<=lmin;k++) { + lsum += binomial(count,k); + } + } + dci_pdu->srs_resource_indicator.nbits = (int)ceil(log2(lsum)); + size += dci_pdu->srs_resource_indicator.nbits; + } + } // Precoding info and number of layers + long transformPrecoder; + if (pusch_Config->transformPrecoder == NULL){ + // if transform precoder is null, apply the values from msg3 + if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) + transformPrecoder = 1; + else + transformPrecoder = 0; + } + else + transformPrecoder = *pusch_Config->transformPrecoder; + if (pusch_Config->txConfig != NULL){ + if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){ + if (pusch_antenna_ports > 1) { + if (pusch_antenna_ports == 4) { + if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank>1)) + dci_pdu->precoding_information.nbits = 6-(*pusch_Config->codebookSubset); + else { + if(*pusch_Config->codebookSubset == NR_PUSCH_Config__codebookSubset_nonCoherent) + dci_pdu->precoding_information.nbits = 2; + else + dci_pdu->precoding_information.nbits = 5-(*pusch_Config->codebookSubset); + } + } + else { + AssertFatal(pusch_antenna_ports==2,"Not valid number of antenna ports"); + if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank==2)) + dci_pdu->precoding_information.nbits = 4-(*pusch_Config->codebookSubset); + else + dci_pdu->precoding_information.nbits = 3-(*pusch_Config->codebookSubset); + } + } + } + } + size += dci_pdu->precoding_information.nbits; // Antenna ports + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = NULL; + int xa=0; + int xb=0; + if(pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA != NULL){ + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup; + xa = ul_ant_bits(NR_DMRS_UplinkConfig,transformPrecoder); + } + if(pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB != NULL){ + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + xb = ul_ant_bits(NR_DMRS_UplinkConfig,transformPrecoder); + } + if (xa>xb) + dci_pdu->antenna_ports.nbits = xa; + else + dci_pdu->antenna_ports.nbits = xb; + size += dci_pdu->antenna_ports.nbits; + // SRS request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL) + dci_pdu->srs_request.nbits = 2; + else + dci_pdu->srs_request.nbits = 3; + size += dci_pdu->srs_request.nbits; // CSI request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig != NULL) { + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup->reportTriggerSize != NULL) { + dci_pdu->csi_request.nbits = *secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup->reportTriggerSize; + size += dci_pdu->csi_request.nbits; + } + } // CBGTI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { + int num = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock; + dci_pdu->cbgti.nbits = 2 + (num<<1); + size += dci_pdu->cbgti.nbits; + } // PTRS - DMRS association + if ( (NR_DMRS_UplinkConfig->phaseTrackingRS == NULL && transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) || + transformPrecoder == NR_PUSCH_Config__transformPrecoder_enabled || (*pusch_Config->maxRank==1) ) + dci_pdu->ptrs_dmrs_association.nbits = 0; + else + dci_pdu->ptrs_dmrs_association.nbits = 2; + size += dci_pdu->ptrs_dmrs_association.nbits; // beta offset indicator + if (pusch_Config->uci_OnPUSCH!=NULL){ + if (pusch_Config->uci_OnPUSCH->choice.setup->betaOffsets->present == NR_UCI_OnPUSCH__betaOffsets_PR_dynamic) { + dci_pdu->beta_offset_indicator.nbits = 2; + size += dci_pdu->beta_offset_indicator.nbits; + } + } // DMRS sequence init + if (transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) { + dci_pdu->dmrs_sequence_initialization.nbits = 1; + size += dci_pdu->dmrs_sequence_initialization.nbits; + } break; case NR_DL_DCI_FORMAT_1_0: @@ -709,29 +2107,122 @@ uint16_t nr_dci_size(nr_dci_format_t format, break; case NR_DL_DCI_FORMAT_1_1: + // General note: 0 bits condition is ignored as default nbits is 0. + // Format identifier + size = 1; // Carrier indicator - size += 1; // Format identifier + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { + dci_pdu->carrier_indicator.nbits=3; + size += dci_pdu->carrier_indicator.nbits; + } // BWP Indicator + uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; + if (n_dl_bwp < 2) + dci_pdu->bwp_indicator.nbits = n_dl_bwp; + else + dci_pdu->bwp_indicator.nbits = 2; + size += dci_pdu->bwp_indicator.nbits; // Freq domain assignment - // Time domain assignment - // VRB to PRB mapping + rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; + numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + rbg_size_config); + if (pdsch_config->resourceAllocation == 0) + dci_pdu->frequency_domain_assignment.nbits = numRBG; + else if (pdsch_config->resourceAllocation == 1) + dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + else + dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; + size += dci_pdu->frequency_domain_assignment.nbits; + // Time domain assignment (see table 5.1.2.1.1-1 in 38.214 + if (pdsch_config->pdsch_TimeDomainAllocationList==NULL) { + if (bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList==NULL) + num_entries = 16; // num of entries in default table + else + num_entries = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; + } + else + num_entries = pdsch_config->pdsch_TimeDomainAllocationList->choice.setup->list.count; + dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); + size += dci_pdu->time_domain_assignment.nbits; + // VRB to PRB mapping + if ((pdsch_config->resourceAllocation == 1) && (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver != NULL)) { + dci_pdu->vrb_to_prb_mapping.nbits = 1; + size += dci_pdu->vrb_to_prb_mapping.nbits; + } // PRB bundling size indicator + if (pdsch_config->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling) { + dci_pdu->prb_bundling_size_indicator.nbits = 1; + size += dci_pdu->prb_bundling_size_indicator.nbits; + } // Rate matching indicator + NR_RateMatchPatternGroup_t *group1 = pdsch_config->rateMatchPatternGroup1; + NR_RateMatchPatternGroup_t *group2 = pdsch_config->rateMatchPatternGroup2; + if ((group1 != NULL) && (group2 != NULL)) + dci_pdu->rate_matching_indicator.nbits = 2; + if ((group1 != NULL) != (group2 != NULL)) + dci_pdu->rate_matching_indicator.nbits = 1; + size += dci_pdu->rate_matching_indicator.nbits; // ZP CSI-RS trigger - /// TB1- MCS 5, NDI 1, RV 2 + if (pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL) { + uint8_t nZP = pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; + dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); + } + size += dci_pdu->zp_csi_rs_trigger.nbits; + // TB1- MCS 5, NDI 1, RV 2 size += 8; // TB2 - size += 4 ; // HARQ PID + long *maxCWperDCI = pdsch_config->maxNrofCodeWordsScheduledByDCI; + if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) { + size += 8; + } + // HARQ PID + size += 4; // DAI - size += 2; // TPC PUCCH - size += 3; // PUCCH resource indicator - size += 3; // PDSCH to HARQ timing indicator + if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) { // FIXME in case of more than one serving cell + dci_pdu->dai[0].nbits = 2; + size += dci_pdu->dai[0].nbits; + } + // TPC PUCCH + size += 2; + // PUCCH resource indicator + size += 3; + // PDSCH to HARQ timing indicator + uint8_t I = ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; + dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I)); + size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits; // Antenna ports + NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA; + NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeB; + dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB); + size += dci_pdu->antenna_ports.nbits; // Tx Config Indication - size += 2; // SRS request + long *isTciEnable = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI; + if (isTciEnable != NULL) { + dci_pdu->transmission_configuration_indication.nbits = 3; + size += dci_pdu->transmission_configuration_indication.nbits; + } + // SRS request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL) + dci_pdu->srs_request.nbits = 2; + else + dci_pdu->srs_request.nbits = 3; + size += dci_pdu->srs_request.nbits; // CBGTI - // CBGFI - size += 1; // DMRS sequence init + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { + uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; + long *maxCWperDCI_rrc = pdsch_config->maxNrofCodeWordsScheduledByDCI; + uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; + dci_pdu->cbgti.nbits = maxCBGperTB * maxCW; + size += dci_pdu->cbgti.nbits; + // CBGFI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) { + dci_pdu->cbgfi.nbits = 1; + size += dci_pdu->cbgfi.nbits; + } + } + // DMRS sequence init + size += 1; break; case NR_DL_DCI_FORMAT_2_0: @@ -753,6 +2244,27 @@ uint16_t nr_dci_size(nr_dci_format_t format, return size; } +int ul_ant_bits(NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig, long transformPrecoder) { + + uint8_t type,maxl; + if(NR_DMRS_UplinkConfig->dmrs_Type == NULL) + type = 1; + else + type = 2; + if(NR_DMRS_UplinkConfig->maxLength == NULL) + maxl = 1; + else + maxl = 2; + if (transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) + return( maxl+type+1); + else { + if (type==1) + return (maxl<<1); + else + AssertFatal(1==0,"DMRS type not valid for this choice"); + } +} + int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000}; int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) { @@ -893,3 +2405,20 @@ int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,i AssertFatal(1==0,"Shouldn't get here\n"); return(-1); } + + +int binomial(int n, int k) { + int c = 1, i; + + if (k > n-k) + k = n-k; + + for (i = 1; i <= k; i++, n--) { + if (c/i > UINT_MAX/n) // return 0 on overflow + return 0; + + c = c / i * n + c % i * n / i; + } + return c; +} + diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h index 63c81def82..5c714e4a93 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h @@ -19,12 +19,12 @@ * contact@openairinterface.org */ -/*! \file extern.h +/*! \file nr_mac_extern.h * \brief NR mac externs -* \author G. Casati +* \author Navid Nikaein, Raymond Knopp, Guido Casati * \date 2019 * \version 1.0 -* \email guido.casati@iis.fraunhofer.de +* \email navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de * @ingroup _mac */ @@ -32,10 +32,10 @@ #ifndef __NR_MAC_EXTERN_H__ #define __NR_MAC_EXTERN_H__ -//#include "PHY/defs_common.h" -#include "nr_mac.h" -#include "RRC/LTE/rrc_defs.h" #include "common/ran_context.h" +#include "nr_mac.h" + +/*#include "PHY/defs_common.h"*/ /* extern const uint32_t BSR_TABLE[BSR_TABLE_SIZE]; extern const uint32_t Extended_BSR_TABLE[BSR_TABLE_SIZE]; @@ -43,8 +43,6 @@ extern const uint8_t cqi2fmt0_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern const uint8_t cqi2fmt1x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern const uint8_t cqi2fmt2x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern UE_RRC_INST *UE_rrc_inst; -extern eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 -extern eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 extern const int cqi_to_mcs[16]; extern uint32_t RRC_CONNECTION_FLAG; extern uint8_t rb_table[34]; @@ -52,6 +50,7 @@ extern mac_rlc_am_muilist_t rlc_am_mui; extern SCHEDULER_MODES global_scheduler_mode; extern unsigned char NB_UE_INST;*/ + extern unsigned char NB_INST; extern unsigned char NB_eNB_INST; extern unsigned char NB_RN_INST; @@ -60,8 +59,15 @@ extern unsigned short NODE_ID[1]; /* Scheduler */ extern RAN_CONTEXT_t RC; extern uint8_t nfapi_mode; +extern mac_rlc_am_muilist_t rlc_am_mui; +extern SCHEDULER_MODES global_scheduler_mode; /*#if defined(PRE_SCD_THREAD) +extern const int cqi_to_mcs[16]; +extern uint32_t RRC_CONNECTION_FLAG; +extern uint8_t rb_table[34]; + +#if defined(PRE_SCD_THREAD) extern uint16_t pre_nb_rbs_required[2][MAX_NUM_CCs][NUMBER_OF_UE_MAX]; extern uint8_t dlsch_ue_select_tbl_in_use; extern uint8_t new_dlsch_ue_select_tbl_in_use; @@ -69,4 +75,5 @@ extern boolean_t pre_scd_activeUE[NUMBER_OF_UE_MAX]; extern eNB_UE_STATS pre_scd_eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; #endif*/ + #endif //DEF_H diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index c983023034..5a9620ed01 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -31,11 +31,9 @@ */ //#include "mac_defs.h" -#include "mac_proto.h" - +#include "NR_MAC_UE/mac_proto.h" #include "NR_MAC-CellGroupConfig.h" - -#include "../NR_MAC_gNB/nr_mac_common.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "SCHED_NR/phy_frame_config_nr.h" int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, @@ -151,8 +149,8 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, NR_ServingCellConfigCommon_t *scc = mac->scc; int i; - mac->phy_config.Mod_id = module_id; - mac->phy_config.CC_id = cc_idP; + mac->phy_config.Mod_id = module_id; + mac->phy_config.CC_id = cc_idP; // carrier config @@ -203,12 +201,20 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, } } + lte_frame_type_t frame_type; + uint16_t band; + int32_t offset; + + get_band((cfg->carrier_config.dl_frequency)*1000, + &band, + &offset, + &frame_type); + // cell config cfg->cell_config.phy_cell_id = *scc->physCellId; - cfg->cell_config.frame_duplex_type = 1; - + cfg->cell_config.frame_duplex_type = frame_type; // SSB config cfg->ssb_config.ss_pbch_power = scc->ss_PBCH_BlockPower; @@ -270,6 +276,53 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, LOG_I(PHY,"TDD has been properly configurated\n"); } + // PRACH configuration + + uint8_t nb_preambles = 64; + if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL) + nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles; + + cfg->prach_config.prach_sequence_length = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present-1; + + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) + cfg->prach_config.prach_sub_c_spacing = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; + else + cfg->prach_config.prach_sub_c_spacing = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + cfg->prach_config.restricted_set_config = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig; + + switch (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM) { + case 0 : + cfg->prach_config.num_prach_fd_occasions = 1; + break; + case 1 : + cfg->prach_config.num_prach_fd_occasions = 2; + break; + case 2 : + cfg->prach_config.num_prach_fd_occasions = 4; + break; + case 3 : + cfg->prach_config.num_prach_fd_occasions = 8; + break; + default: + AssertFatal(1==0,"msg1 FDM identifier %ld undefined (0,1,2,3) \n", scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM); + } + + cfg->prach_config.num_prach_fd_occasions_list = (fapi_nr_num_prach_fd_occasions_t *) malloc(cfg->prach_config.num_prach_fd_occasions*sizeof(fapi_nr_num_prach_fd_occasions_t)); + for (i=0; iprach_config.num_prach_fd_occasions; i++) { + cfg->prach_config.num_prach_fd_occasions_list[i].num_prach_fd_occasions = i; + if (cfg->prach_config.prach_sequence_length) + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139; + else + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l839; + + cfg->prach_config.num_prach_fd_occasions_list[i].k1 = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart; + cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig; + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, nb_preambles, frame_type); + //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences = ??? + } + + cfg->prach_config.ssb_per_rach = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present-1; } @@ -281,7 +334,7 @@ int nr_rrc_mac_config_req_ue( // NR_ServingCellConfigCommon_t *sccP, // NR_MAC_CellGroupConfig_t *mac_cell_group_configP, // NR_PhysicalCellGroupConfig_t *phy_cell_group_configP, - NR_SpCellConfig_t *spCell_ConfigP ){ + NR_CellGroupConfig_t *cell_group_config ){ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); @@ -292,17 +345,17 @@ int nr_rrc_mac_config_req_ue( if(mibP != NULL){ mac->mib = mibP; // update by every reception } - - - if(spCell_ConfigP != NULL ){ - mac->servCellIndex = *spCell_ConfigP->servCellIndex; - if (spCell_ConfigP->reconfigurationWithSync) { - mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon; + + if(cell_group_config != NULL ){ + mac->servCellIndex = *cell_group_config->spCellConfig->servCellIndex; + if (cell_group_config->spCellConfig->reconfigurationWithSync) { + mac->rach_ConfigDedicated = cell_group_config->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink; + mac->scc = cell_group_config->spCellConfig->reconfigurationWithSync->spCellConfigCommon; config_common_ue(mac,module_id,cc_idP); - mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity; + mac->crnti = cell_group_config->spCellConfig->reconfigurationWithSync->newUE_Identity; LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti); } - mac->scd = spCell_ConfigP->spCellConfigDedicated; + mac->scg = cell_group_config; /* if(mac_cell_group_configP != NULL){ diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 405ea95eb1..5775e5bfb9 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -37,6 +37,21 @@ #include #include #include "platform_types.h" + +/* PHY */ +#include "PHY/defs_nr_common.h" + +/* IF */ +#include "NR_IF_Module.h" +#include "fapi_nr_ue_interface.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" +#include "LAYER2/MAC/mac.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" + +/* RRC */ #include "NR_DRX-Config.h" #include "NR_SchedulingRequestConfig.h" #include "NR_BSR-Config.h" @@ -46,13 +61,9 @@ #include "NR_MIB.h" #include "NR_MAC-CellGroupConfig.h" #include "NR_PhysicalCellGroupConfig.h" -#include "NR_SpCellConfig.h" +#include "NR_CellGroupConfig.h" #include "NR_ServingCellConfig.h" -#include "fapi_nr_ue_interface.h" -#include "NR_IF_Module.h" -#include "../NR_MAC_gNB/nr_mac_common.h" -#include "PHY/defs_nr_common.h" -#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac.h" + #define NB_NR_UE_MAC_INST 1 /*!\brief Maximum number of logical channl group IDs */ @@ -61,6 +72,7 @@ /*!\brief value for indicating BSR Timer is not running */ #define NR_MAC_UE_BSR_TIMER_NOT_RUNNING (0xFFFF) + typedef enum { SFN_C_MOD_2_EQ_0, SFN_C_MOD_2_EQ_1, @@ -133,24 +145,27 @@ typedef struct { #define MAX_NUM_BWP 2 typedef enum { - RA_IDLE=0, - WAIT_RAR=1, - WAIT_CONTENTION_RESOLUTION=2 + RA_UE_IDLE = 0, + WAIT_RAR = 1, + WAIT_CONTENTION_RESOLUTION = 2, + RA_SUCCEEDED = 3 } RA_state_t; + /*!\brief Top level UE MAC structure */ typedef struct { NR_ServingCellConfigCommon_t *scc; - NR_ServingCellConfig_t *scd; + NR_CellGroupConfig_t *scg; + NR_RACH_ConfigDedicated_t *rach_ConfigDedicated; int servCellIndex; //// MAC config - NR_DRX_Config_t *drx_Config; + NR_DRX_Config_t *drx_Config; NR_SchedulingRequestConfig_t *schedulingRequestConfig; - NR_BSR_Config_t *bsr_Config; - NR_TAG_Config_t *tag_Config; - NR_PHR_Config_t *phr_Config; - NR_RNTI_Value_t *cs_RNTI; - NR_MIB_t *mib; + NR_BSR_Config_t *bsr_Config; + NR_TAG_Config_t *tag_Config; + NR_PHR_Config_t *phr_Config; + NR_RNTI_Value_t *cs_RNTI; + NR_MIB_t *mib; NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP]; NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP]; @@ -163,14 +178,75 @@ typedef struct { SFN_C_TYPE type0_pdcch_ss_sfn_c; uint32_t type0_pdcch_ss_n_c; uint32_t type0_pdcch_consecutive_slots; + int rnti_type; + + /* PDUs */ + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + ULSCH_PDU ulsch_pdu; + + /* Random Access parameters */ /// state of RA procedure RA_state_t ra_state; - /// RA-rnti + /// RA rx frame offset: compensate RA rx offset introduced by OAI gNB. + uint8_t RA_offset; + /// RA-rnti uint16_t ra_rnti; - /// Temporary CRNTI + /// Temporary CRNTI uint16_t t_crnti; - /// CRNTI + /// CRNTI uint16_t crnti; + /// number of attempt for rach + uint8_t RA_attempt_number; + /// Random-access procedure flag + uint8_t RA_active; + /// Random-access window counter + int8_t RA_window_cnt; + /// Random-access Msg3 size in bytes + uint8_t RA_Msg3_size; + /// Random-access prachMaskIndex + uint8_t RA_prachMaskIndex; + /// Flag indicating Preamble set (A,B) used for first Msg3 transmission + uint8_t RA_usedGroupA; + /// BeamfailurerecoveryConfig + NR_BeamFailureRecoveryConfig_t RA_BeamFailureRecoveryConfig; + /// Preamble Tx Counter + uint8_t RA_PREAMBLE_TRANSMISSION_COUNTER; + /// Preamble Power Ramping Counter + uint8_t RA_PREAMBLE_POWER_RAMPING_COUNTER; + /// Random-access backoff counter + int16_t RA_backoff_indicator; + /// Random-access backoff counter + int16_t RA_backoff_cnt; + /// Random-access variable for window calculation (frame of last change in window counter) + uint32_t RA_tx_frame; + /// Random-access variable for window calculation (subframe of last change in window counter) + uint8_t RA_tx_subframe; + /// Scheduled RX frame for RA Msg2 + uint16_t msg2_rx_frame; + /// Scheduled RX slot for RA Msg2 + uint16_t msg2_rx_slot; + /// Random-access Group B maximum path-loss + /// Random-access variable for backoff (frame of last change in backoff counter) + uint32_t RA_backoff_frame; + /// Random-access variable for backoff (subframe of last change in backoff counter) + uint8_t RA_backoff_subframe; + /// Random-access Group B maximum path-loss + uint16_t RA_maxPL; + /// Random-access Contention Resolution Timer active flag + uint8_t RA_contention_resolution_timer_active; + /// Random-access Contention Resolution Timer count value + uint8_t RA_contention_resolution_cnt; + /// Msg3 Delta Preamble + int8_t deltaPreamble_Msg3; + /// Received TPC command (in dB) from RAR + int8_t Msg3_TPC; + /// Flag to monitor if matching RAPID was received in RAR + uint8_t RA_RAPID_found; + /// Flag to monitor if BI was received in RAR + uint8_t RA_BI_found; + /// Flag for the Msg1 generation: enabled at every occurrence of nr prach slot + uint8_t generate_nr_prach; //// FAPI-like interface message fapi_nr_tx_request_t tx_request; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_extern.h b/openair2/LAYER2/NR_MAC_UE/mac_extern.h index 26e0ea2667..54cdc4d149 100644 --- a/openair2/LAYER2/NR_MAC_UE/mac_extern.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_extern.h @@ -90,4 +90,6 @@ extern const int32_t table_38213_10_1_1_c2[5]; // for PUSCH from TS 38.214 subclause 6.1.2.1.1 extern uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]; // for PDSCH from TS 38.214 subclause 5.1.2.1.1 -extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]; \ No newline at end of file +extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]; + +extern dci_pdu_rel15_t *def_dci_pdu_rel15; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 3c625ec2ff..e9d7a97a5d 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -72,7 +72,7 @@ int nr_rrc_mac_config_req_ue( uint8_t gNB_index, NR_MIB_t *mibP, //NR_ServingCellConfigCommon_t *sccP, - NR_SpCellConfig_t *spCell_ConfigP); + NR_CellGroupConfig_t *cell_group_config); /**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst); @@ -84,23 +84,9 @@ NR_UE_MAC_INST_t *get_mac_inst( /**\brief called at each slot, slot length based on numerology. now use u=0, scs=15kHz, slot=1ms performs BSR/SR/PHR procedures, random access procedure handler and DLSCH/ULSCH procedures. - \param module_id module id - \param gNB_index corresponding gNB index - \param cc_id component carrier id - \param rx_frame receive frame number - \param rx_slot receive slot number - \param tx_frame transmit frame number - \param tx_slot transmit slot number*/ -NR_UE_L2_STATE_t nr_ue_scheduler( - const module_id_t module_id, - const uint8_t gNB_index, - const int cc_id, - const frame_t rx_frame, - const slot_t rx_slot, - const int32_t ssb_index, - const frame_t tx_frame, - const slot_t tx_slot); - + \param dl_info DL indication + \param ul_info UL indication*/ +NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_indication_t *ul_info); /* \brief Get SR payload (0,1) from UE MAC @param Mod_id Instance id of UE in machine @@ -115,7 +101,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe); -int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format); +int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format); int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci); uint32_t get_ssb_frame(uint32_t test); @@ -124,8 +110,6 @@ uint32_t get_ssb_slot(uint32_t ssb_index); uint32_t mr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe); - - /* \brief Get payload (MAC PDU) from UE PHY @param module_idP Instance id of UE in machine @param CC_id Component Carrier index @@ -154,16 +138,30 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, uint8_t gNB_index, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); + +uint16_t nr_generate_ulsch_pdu(uint8_t *sdus_payload, + uint8_t *pdu, + uint8_t num_sdus, + uint16_t *sdu_lengths, + uint8_t *sdu_lcids, + uint8_t power_headroom, + uint16_t crnti, + uint16_t truncated_bsr, + uint16_t short_bsr, + uint16_t long_bsr, + unsigned short post_padding, + uint16_t buflen); + int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len); -void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot); +void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot); void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, int dci_format, uint8_t dci_length, uint16_t rnti, uint64_t *dci_pdu, - nr_dci_pdu_rel15_t *nr_pdci_info_extracted); + dci_pdu_rel15_t *nr_pdci_info_extracted); uint8_t @@ -175,5 +173,96 @@ int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, int nrofDownlinkSlots, int nrofDownlinkSymbols, int nrofUplinkSlots, int nrofUplinkSymbols); +/** \brief Function for UE/PHY to compute PUSCH transmit power in power-control procedure. + @param Mod_id Module id of UE + @returns Po_NOMINAL_PUSCH (PREAMBLE_RECEIVED_TARGET_POWER+DELTA_PREAMBLE +*/ +int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t module_idP, uint8_t CC_id); + +/** \brief Function to compute DELTA_PREAMBLE from 38.321 subclause 7.3 + (for RA power ramping procedure and Msg3 PUSCH power control policy) + @param Mod_id Module id of UE + @returns DELTA_PREAMBLE +*/ +int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format); + +/* Random Access */ + +/* \brief This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211 tables 6.3.3.2.x +and fills the PRACH PDU per each FD occasion. +@param module_idP Index of UE instance +@param frameP Frame index +@param slotP Slot index +@returns void +*/ +void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); + +/* \brief Function called by PHY to process the received RAR and check that the preamble matches what was sent by the gNB. It provides the timing advance and t-CRNTI. +@param Mod_id Index of UE instance +@param CC_id Index to a component carrier +@param frame Frame index +@param ra_rnti RA_RNTI value +@param dlsch_buffer Pointer to dlsch_buffer containing RAR PDU +@param t_crnti Pointer to PHY variable containing the T_CRNTI +@param preamble_index Preamble Index used by PHY to transmit the PRACH. This should match the received RAR to trigger the rest of +random-access procedure +@param selected_rar_buffer the output buffer for storing the selected RAR header and RAR payload +@returns timing advance or 0xffff if preamble doesn't match +*/ +uint16_t nr_ue_process_rar(module_id_t mod_id, + int CC_id, + frame_t frameP, + uint8_t * dlsch_buffer, + rnti_t * t_crnti, + uint8_t preamble_index, + uint8_t * selected_rar_buffer); + +void nr_process_rar(nr_downlink_indication_t *dl_info); + +void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame); + +void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); + +void nr_ra_succeeded(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); + +/* \brief Function called by PHY to retrieve information to be transmitted using the RA procedure. +If the UE is not in PUSCH mode for a particular eNB index, this is assumed to be an Msg3 and MAC +attempts to retrieves the CCCH message from RRC. If the UE is in PUSCH mode for a particular eNB +index and PUCCH format 0 (Scheduling Request) is not activated, the MAC may use this resource for +andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 from 36.321) +@param mod_id Index of UE instance +@param CC_id Component Carrier Index +@param frame +@param gNB_id gNB index +@param nr_tti_tx slot for PRACH transmission +@returns indication to generate PRACH to phy */ +uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx); + +/* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321). +@param module_idP Index of UE instance +@param CC_id Component Carrier Index +@param gNB_index gNB index +@param t_id +@param rach_ConfigDedicated +@returns void */ +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated); + +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); + +void nr_ue_msg2_scheduler(module_id_t mod_id, uint16_t rach_frame, uint16_t rach_slot, uint16_t *msg2_frame, uint16_t *msg2_slot); #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c index 61f9ab601e..af9822a5df 100644 --- a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c +++ b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c @@ -50,9 +50,9 @@ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst) //LOG_I(MAC, "[MAIN] init UE MAC functions \n"); //init mac here - nr_ue_mac_inst = (NR_UE_MAC_INST_t *)malloc(sizeof(NR_UE_MAC_INST_t)*NB_NR_UE_MAC_INST); + nr_ue_mac_inst = (NR_UE_MAC_INST_t *)calloc(sizeof(NR_UE_MAC_INST_t),NB_NR_UE_MAC_INST); if (rrc_inst) { - nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config->spCellConfig); + nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config); if (IS_SOFTMODEM_NOS1){ if (rlc_module_init(0) != 0) { diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 396e06ff09..53263747fc 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -21,11 +21,11 @@ /* \file nr_ue_dci_configuration.c * \brief functions for generating dci search procedures based on RRC Serving Cell Group Configuration - * \author R. Knopp + * \author R. Knopp, G. Casati * \date 2020 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr + * \version 0.2 + * \company Eurecom, Fraunhofer IIS + * \email: knopp@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -35,6 +35,8 @@ #include "assertions.h" #include "LAYER2/NR_MAC_UE/mac_extern.h" #include "mac_defs.h" +#include "common/utils/nr/nr_common.h" +#include "executables/softmodem-common.h" #include #ifdef NR_PDCCH_DCI_TOOLS_DEBUG @@ -44,6 +46,7 @@ #endif #define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a) +dci_pdu_rel15_t *def_dci_pdu_rel15; void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) { @@ -59,125 +62,217 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd } -void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) { +void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot) { - // check if DL slot - if (is_nr_DL_slot(mac->scc,slot)==1) { + def_dci_pdu_rel15 = calloc(1,sizeof(dci_pdu_rel15_t)); + + NR_BWP_Downlink_t *bwp; + NR_BWP_DownlinkCommon_t *bwp_Common; + NR_BWP_DownlinkDedicated_t *dl_bwp_Dedicated; + NR_SetupRelease_PDCCH_Config_t *pdcch_Config; + NR_SetupRelease_PDCCH_ConfigCommon_t *pdcch_ConfigCommon; + struct NR_PDCCH_Config__controlResourceSetToAddModList *controlResourceSetToAddModList; + struct NR_PDCCH_Config__searchSpacesToAddModList *searchSpacesToAddModList; + struct NR_UplinkConfig__uplinkBWP_ToAddModList *uplinkBWP_ToAddModList; + NR_SearchSpace_t *NR_SearchSpace; + NR_ControlResourceSet_t *coreset; + + fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; + NR_ServingCellConfig_t *scd = mac->scg->spCellConfig->spCellConfigDedicated; + + uint8_t bwp_id = 1; + int ss_id, sps; + + // get PDCCH configuration(s) (Coreset, SearchSpace, etc...) from BWP Dedicated in serving cell config dedicated (scd) + // get BWP 1, Coreset ID 0, SearchSpace ID 0 (i.e. configured in MIB and in ServingCellConfigCommon) + + // Check dedicated DL BWP + if (mac->DLbwp[0] == NULL) { + NR_SearchSpace_t *ss; + int ss_id = 0; + + AssertFatal(scd->downlinkBWP_ToAddModList != NULL, "downlinkBWP_ToAddModList is null\n"); + AssertFatal(scd->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList->list->count is %d\n", scd->downlinkBWP_ToAddModList->list.count); + mac->DLbwp[0] = scd->downlinkBWP_ToAddModList->list.array[bwp_id - 1]; + + dl_bwp_Dedicated = mac->DLbwp[0]->bwp_Dedicated; + AssertFatal(dl_bwp_Dedicated != NULL, "dl_bwp_Dedicated is null\n"); + + bwp_Common = mac->DLbwp[0]->bwp_Common; + AssertFatal(bwp_Common != NULL, "bwp_Common is null\n"); + + pdcch_Config = dl_bwp_Dedicated->pdcch_Config; + AssertFatal(pdcch_Config != NULL, "pdcch_Config is null\n"); + + pdcch_ConfigCommon = bwp_Common->pdcch_ConfigCommon; + AssertFatal(pdcch_ConfigCommon != NULL, "pdcch_ConfigCommon is null\n"); + AssertFatal(pdcch_ConfigCommon->choice.setup->ra_SearchSpace != NULL, "ra_SearchSpace must be available in DL BWP\n"); + + controlResourceSetToAddModList = pdcch_Config->choice.setup->controlResourceSetToAddModList; + AssertFatal(controlResourceSetToAddModList != NULL, "controlResourceSetToAddModList is null\n"); + + AssertFatal(controlResourceSetToAddModList->list.count == 1, "controlResourceSetToAddModList->list.count=%d\n", controlResourceSetToAddModList->list.count); + + mac->coreset[0][0] = controlResourceSetToAddModList->list.array[0]; + coreset = mac->coreset[0][0]; + AssertFatal(coreset != NULL, "coreset[0][0] is null\n"); - // get BWP 1, Coreset 0, SearchSpace 0 - if (mac->DLbwp[0]==NULL) { - AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); - AssertFatal(mac->scd->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n", - mac->scd->downlinkBWP_ToAddModList->list.count); - mac->DLbwp[0] = mac->scd->downlinkBWP_ToAddModList->list.array[0]; - AssertFatal(mac->DLbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config!=NULL,"pdcch_Config is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL,"controlResourceSetToAddModList is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count==1,"controlResourceSetToAddModList->list.count=%d\n", - mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count); - mac->coreset[0][0] = mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; - AssertFatal(mac->coreset[0][0]!=NULL,"coreset[0][0] is null\n"); - - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, - "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss; - int ss_id=0; - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.countDLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count); - for (int i=0;iDLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { - ss=mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; - AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); - AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); - AssertFatal(*ss->controlResourceSetId == mac->coreset[0][0]->controlResourceSetId,"ss->controlResourceSetId is unknown\n"); - mac->SSpace[0][0][ss_id] = ss; - ss_id++; - } - } - if (mac->ULbwp[0]==NULL) { - AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList!=NULL,"uplinkBWP_ToAddModList is null\n"); - AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count==1,"uplinkBWP_ToAddModList->list->count is %d\n", - mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count); - mac->ULbwp[0] = mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; - AssertFatal(mac->ULbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); - } - // check search spaces - - int ss_id=0; - fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; - int sps =mac->DLbwp[0]->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; - - while(mac->SSpace[0][0][ss_id]!=NULL && - ss_id < mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count) { - - AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); - AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - + searchSpacesToAddModList = pdcch_Config->choice.setup->searchSpacesToAddModList; + AssertFatal(searchSpacesToAddModList != NULL, "searchSpacesToAddModList is null\n"); + AssertFatal(searchSpacesToAddModList->list.count > 0, "searchSpacesToAddModList is empty\n"); + AssertFatal(searchSpacesToAddModList->list.count < FAPI_NR_MAX_SS_PER_CORESET, "too many searchpaces per coreset %d\n", searchSpacesToAddModList->list.count); + + for (int i = 0; i < searchSpacesToAddModList->list.count; i++) { + ss = searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL, "ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL, "ss->searchSpaceType is null\n"); + AssertFatal(*ss->controlResourceSetId == coreset->controlResourceSetId, "ss->controlResourceSetId is unknown\n"); + mac->SSpace[0][0][ss_id] = ss; ss_id++; } - if (mac->ra_state == WAIT_RAR) { - // check for RAR - rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); - dl_config->number_pdus = dl_config->number_pdus + 1; + } + + // Check dedicated UL BWP + if (mac->ULbwp[0] == NULL) { + uplinkBWP_ToAddModList = scd->uplinkConfig->uplinkBWP_ToAddModList; + AssertFatal(uplinkBWP_ToAddModList != NULL, "uplinkBWP_ToAddModList is null\n"); + AssertFatal(uplinkBWP_ToAddModList->list.count == 1, "uplinkBWP_ToAddModList->list->count is %d\n", uplinkBWP_ToAddModList->list.count); + mac->ULbwp[0] = uplinkBWP_ToAddModList->list.array[bwp_id - 1]; + AssertFatal(mac->ULbwp[0]->bwp_Dedicated != NULL, "UL bwp_Dedicated is null\n"); + } + + bwp = mac->DLbwp[0]; + bwp_Common = bwp->bwp_Common; + pdcch_ConfigCommon = bwp_Common->pdcch_ConfigCommon; + dl_bwp_Dedicated = bwp->bwp_Dedicated; + pdcch_Config = dl_bwp_Dedicated->pdcch_Config; + searchSpacesToAddModList = pdcch_Config->choice.setup->searchSpacesToAddModList; + + // check USSs + ss_id = 0; + NR_SearchSpace = mac->SSpace[0][0][ss_id]; + while(NR_SearchSpace != NULL && ss_id < searchSpacesToAddModList->list.count) { + AssertFatal(NR_SearchSpace->monitoringSymbolsWithinSlot != NULL, "NR_SearchSpace->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(NR_SearchSpace->monitoringSymbolsWithinSlot->buf != NULL, "NR_SearchSpace->monitoringSymbolsWithinSlot->buf is null\n"); + ss_id++; + } + + if (mac->crnti > 0) { + + NR_SearchSpace_t *css; + NR_SearchSpace_t *uss = NULL; + NR_ServingCellConfigCommon_t *scc; + NR_SearchSpaceId_t ra_SearchSpaceId; + rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + uint16_t monitoringSymbolsWithinSlot; + uint8_t add_dci = 1; + + AssertFatal(mac->scc != NULL, "scc is null\n"); + + scc = mac->scc; + rel15->dci_format = NR_DL_DCI_FORMAT_1_1; + + // CoReSet configuration + coreset = mac->coreset[0][0]; + rel15->coreset.duration = coreset->duration; + for (int i = 0; i < 6; i++) + rel15->coreset.frequency_domain_resource[i] = coreset->frequencyDomainResources.buf[i]; + + rel15->coreset.CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved ? FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; + + if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) { + struct NR_ControlResourceSet__cce_REG_MappingType__interleaved *interleaved = coreset->cce_REG_MappingType.choice.interleaved; + rel15->coreset.RegBundleSize = (interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2 + interleaved->reg_BundleSize); + rel15->coreset.InterleaverSize = (interleaved->interleaverSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2 + interleaved->interleaverSize); + AssertFatal(scc->physCellId != NULL, "mac->scc->physCellId is null\n"); + rel15->coreset.ShiftIndex = interleaved->shiftIndex != NULL ? *interleaved->shiftIndex : *scc->physCellId; + } else { + rel15->coreset.RegBundleSize = 0; + rel15->coreset.InterleaverSize = 0; + rel15->coreset.ShiftIndex = 0; } - else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) { - rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + + rel15->coreset.CoreSetType = 1; + rel15->coreset.precoder_granularity = coreset->precoderGranularity; + + if (mac->ra_state == WAIT_RAR){ + + NR_BWP_DownlinkCommon_t *initialDownlinkBWP = scc->downlinkConfigCommon->initialDownlinkBWP; + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + AssertFatal(commonSearchSpaceList->list.count > 0, "PDCCH CSS list has 0 elements\n"); + + ra_SearchSpaceId = *pdcch_ConfigCommon->choice.setup->ra_SearchSpace; + + // fetch the CSS for RA from the CSS list + for (int i = 0; i < commonSearchSpaceList->list.count; i++) { + css = commonSearchSpaceList->list.array[i]; + if(css->searchSpaceId == ra_SearchSpaceId) + break; + } + + // check CSSs + if(css != NULL) { + AssertFatal(css->monitoringSymbolsWithinSlot != NULL, "css->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(css->monitoringSymbolsWithinSlot->buf != NULL, "css->monitoringSymbolsWithinSlot->buf is null\n"); + } + + if (frame == mac->msg2_rx_frame && slot == mac->msg2_rx_slot){ + sps = initialDownlinkBWP->genericParameters.cyclicPrefix == NULL ? 14 : 12; + monitoringSymbolsWithinSlot = (css->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (css->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + rel15->rnti = mac->ra_rnti; + rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); + rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); // NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); + rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing; + rel15->dci_length = nr_dci_size(scc,mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); + for (int i = 0; i < sps; i++) + if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) { + rel15->coreset.StartSymbolIndex = i; + break; + } + fill_dci_search_candidates(css, rel15); + } else { + add_dci = 0; + } + } else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION){ + rel15->rnti = mac->t_crnti; - dl_config->number_pdus = dl_config->number_pdus + 1; - } - if (mac->crnti>0) { - rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + + } else { + rel15->rnti = mac->crnti; - rel15->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); - rel15->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); - rel15->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; + rel15->BWPSize = NRRIV2BW(bwp_Common->genericParameters.locationAndBandwidth, 275); + rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); + rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing; + rel15->dci_length = nr_dci_size(scc,mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); // get UE-specific search space - for (ss_id=0;ss_idSSpace[0][0][ss_id]!=NULL;ss_id++) - if (mac->SSpace[0][0][ss_id]->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) break; - AssertFatal(ss_idSSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | - (mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); - - for (int i=0; i>(sps-1-i))&1) { - rel15->coreset.StartSymbolIndex=i; - break; - } - rel15->coreset.duration = mac->coreset[0][0]->duration; - for (int i=0;i<6;i++) - rel15->coreset.frequency_domain_resource[i] = mac->coreset[0][0]->frequencyDomainResources.buf[i]; - - rel15->coreset.CceRegMappingType = mac->coreset[0][0]->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? - FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; - if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) { - rel15->coreset.RegBundleSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize); - rel15->coreset.InterleaverSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize); - AssertFatal(mac->scc->physCellId != NULL,"mac->scc->physCellId is null\n"); - rel15->coreset.ShiftIndex = mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex : *mac->scc->physCellId; + for (ss_id = 0; ss_id < FAPI_NR_MAX_SS_PER_CORESET && mac->SSpace[0][0][ss_id] != NULL; ss_id++){ + uss = mac->SSpace[0][0][ss_id]; + if (uss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) break; } - else { - rel15->coreset.RegBundleSize = 0; - rel15->coreset.InterleaverSize = 0; - rel15->coreset.ShiftIndex = 0; - } - rel15->coreset.CoreSetType = 1; - rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; - if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) - rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; - else - rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; - fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); - rel15->dci_format = NR_DL_DCI_FORMAT_1_0; - rel15->dci_length = nr_dci_size(rel15->dci_format,NR_RNTI_C,rel15->BWPSize); + AssertFatal(ss_id < FAPI_NR_MAX_SS_PER_CORESET, "couldn't find a UE-specific SS\n"); + sps = bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + // for SPS=14 8 MSBs in positions 13 down to 6 + monitoringSymbolsWithinSlot = (uss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (uss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + for (int i = 0; i < sps; i++) + if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) { + rel15->coreset.StartSymbolIndex = i; + break; + } + fill_dci_search_candidates(uss, rel15); + } + + // Scrambling RNTI + if (coreset->pdcch_DMRS_ScramblingID) { + rel15->coreset.pdcch_dmrs_scrambling_id = *coreset->pdcch_DMRS_ScramblingID; + rel15->coreset.scrambling_rnti = mac->t_crnti; + } else { + rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId; + rel15->coreset.scrambling_rnti = 0; + } + + if (add_dci){ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; } } } - - - - diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index a49a3f51a3..47b420d39b 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -31,28 +31,38 @@ */ -/* MAC related headers */ -#include "mac_proto.h" +#include +#include + +/* exe */ +#include "executables/nr-softmodem.h" + +/* RRC*/ +#include "RRC/NR_UE/rrc_proto.h" +#include "NR_RACH-ConfigCommon.h" +#include "NR_RACH-ConfigGeneric.h" +#include "NR_FrequencyInfoDL.h" +#include "NR_PDCCH-ConfigCommon.h" + +/* MAC */ #include "mac_defs.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac.h" -#include "mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "NR_MAC_UE/mac_proto.h" +#include "NR_MAC_UE/mac_extern.h" #include "common/utils/nr/nr_common.h" -//#include "LAYER2/MAC/mac_vars.h" // TODO Note that mac_vars.h is not NR specific and this should be updated - // also, the use of the same should be updated in nr-softmodem and nr-uesoftmodem - -/* PHY UE related headers*/ +/* PHY UE */ #include "SCHED_NR_UE/defs.h" - -#include "RRC/NR_UE/rrc_proto.h" -#include "assertions.h" #include "PHY/defs_nr_UE.h" /*Openair Packet Tracer */ #include "UTIL/OPT/opt.h" #include "OCG.h" #include "executables/softmodem-common.h" -/* log utils */ + +/* utils */ +#include "assertions.h" + #include "common/utils/LOG/log.h" #include "SIMULATION/TOOLS/sim.h" // for taus #include "openair2/LAYER2/NR_MAC_COMMON/nr_mac.h" @@ -60,11 +70,14 @@ #include #include -//int mbms_rab_id = 2047; //#define ENABLE_MAC_PAYLOAD_DEBUG 1 #define DEBUG_EXTRACT_DCI 1 +extern int bwp_id; +extern dci_pdu_rel15_t *def_dci_pdu_rel15; +extern const uint16_t nr_slots_per_frame[5]; + extern void mac_rlc_data_ind ( const module_id_t module_idP, const rnti_t rntiP, @@ -261,7 +274,7 @@ int8_t nr_ue_decode_mib(module_id_t module_id, uint16_t frame_number_4lsb = 0; for (int i=0; i<4; i++) frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i); - uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4] + //uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4] uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5] uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset; @@ -641,100 +654,483 @@ uint32_t get_ssb_frame(uint32_t test){ // 1. TODO: Call RRC for link status return to PHY // 2. TODO: Perform SR/BSR procedures for scheduling feedback // 3. TODO: Perform PHR procedures -NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, - const uint8_t gNB_index, - const int cc_id, - const frame_t rx_frame, - const slot_t rx_slot, - const int32_t ssb_index, - const frame_t tx_frame, - const slot_t tx_slot ){ +NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_indication_t *ul_info){ uint32_t search_space_mask = 0; - NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; - - // check type0 from 38.213 13 if we have no CellGroupConfig - if ( mac->scd == NULL) { - if( ssb_index != -1){ - - if(mac->type0_pdcch_ss_mux_pattern == 1){ - // 38.213 chapter 13 - if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } - if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } + if (dl_info){ + + module_id_t mod_id = dl_info->module_id; + uint32_t gNB_index = dl_info->gNB_index; + int cc_id = dl_info->cc_id; + frame_t rx_frame = dl_info->frame; + slot_t rx_slot = dl_info->slot; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + + fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; + nr_scheduled_response_t scheduled_response; + nr_dcireq_t dcireq; + + // check type0 from 38.213 13 if we have no CellGroupConfig + // TODO: implementation to be completed + if (mac->scg == NULL) { + if(dl_info->ssb_index != -1){ + + if(mac->type0_pdcch_ss_mux_pattern == 1){ + // 38.213 chapter 13 + if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + if(mac->type0_pdcch_ss_mux_pattern == 2){ + // 38.213 Table 13-13, 13-14 + if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + if(mac->type0_pdcch_ss_mux_pattern == 3){ + // 38.213 Table 13-15 + if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + } // ssb_index != -1 + + // Type0 PDCCH search space + if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){ + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1; + + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; + + /* + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set + + LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n", + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti, + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP); + */ + dl_config->number_pdus = dl_config->number_pdus + 1; + mac->scheduled_response.dl_config = dl_config; } - if(mac->type0_pdcch_ss_mux_pattern == 2){ - // 38.213 Table 13-13, 13-14 - if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } + } else { // we have an scg + + dcireq.module_id = mod_id; + dcireq.gNB_index = gNB_index; + dcireq.cc_id = cc_id; + dcireq.frame = rx_frame; + dcireq.slot = rx_slot; + nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + + // we should have received a DL DCI here, so configure DL accordingly + scheduled_response.dl_config = &dcireq.dl_config_req; + scheduled_response.ul_config = NULL; + scheduled_response.tx_request = NULL; + scheduled_response.module_id = mod_id; + scheduled_response.CC_id = cc_id; + scheduled_response.frame = rx_frame; + scheduled_response.slot = rx_slot; + + if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){ + mac->if_module->scheduled_response(&scheduled_response); } - if(mac->type0_pdcch_ss_mux_pattern == 3){ - // 38.213 Table 13-15 - if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } - } - } // ssb_index != -1 - - // Type0 PDCCH search space - if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){ - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1; - - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; - + /* - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set - - LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n", - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti, - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP); - */ - dl_config->number_pdus = dl_config->number_pdus + 1; + if(search_space_mask & type0a_pdcch){ + } + + if(search_space_mask & type1_pdcch){ + } + + if(search_space_mask & type2_pdcch){ + } + + if(search_space_mask & type3_pdcch){ + } + */ } + } else if (ul_info && ul_info->slot_tx == 8) { + module_id_t mod_id = ul_info->module_id; + uint32_t gNB_index = ul_info->gNB_index; + int cc_id = ul_info->cc_id; + frame_t rx_frame = ul_info->frame_rx; + slot_t rx_slot = ul_info->slot_rx; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + + // program PUSCH. this should actually be done upon reception of an UL DCI + nr_dcireq_t dcireq; + nr_scheduled_response_t scheduled_response; + + //--------------------------Temporary configuration-----------------------------// + uint16_t rnti = 0x1234; + uint32_t rb_size = 50; + uint32_t rb_start = 0; + uint8_t nr_of_symbols = 11; + uint8_t start_symbol_index = 0; + uint8_t nrOfLayers = 1; + uint8_t mcs_index = 9; + uint8_t mcs_table = 0; + uint8_t harq_process_id = 0; + uint8_t rv_index = 0; + uint16_t l_prime_mask = get_l_prime(nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); + uint8_t dmrs_config_type = 0; + uint8_t ptrs_mcs1 = 2; + uint8_t ptrs_mcs2 = 4; + uint8_t ptrs_mcs3 = 10; + uint16_t n_rb0 = 25; + uint16_t n_rb1 = 75; + uint16_t pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + uint8_t ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, mcs_index, mcs_table); + uint8_t ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, rb_size); + //------------------------------------------------------------------------------// + + dcireq.module_id = mod_id; + dcireq.gNB_index = gNB_index; + dcireq.cc_id = cc_id; + dcireq.frame = rx_frame; + dcireq.slot = rx_slot; + + scheduled_response.dl_config = NULL; + scheduled_response.ul_config = &dcireq.ul_config_req; + scheduled_response.tx_request = NULL; + scheduled_response.module_id = mod_id; + scheduled_response.CC_id = cc_id; + scheduled_response.frame = rx_frame; + scheduled_response.slot = rx_slot; + + scheduled_response.ul_config->slot = ul_info->slot_tx; + scheduled_response.ul_config->number_pdus = 1; + scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rnti = rnti; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_size = rb_size; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_start = rb_start; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nr_of_symbols = nr_of_symbols; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_process_id; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t)); + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + + if (1 << ptrs_time_density >= nr_of_symbols) { + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + } + + if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){ + mac->if_module->scheduled_response(&scheduled_response); + } + + // TODO: expand + // Note: Contention resolution is currently not active + if (mac->RA_contention_resolution_timer_active == 1) + ue_contention_resolution(mod_id, gNB_index, cc_id, ul_info->frame_tx); } - else { // get PDCCH configuration(s) from SCGConfig - - - - - // get Coreset and SearchSpace Information from spCellConfigDedicated - - - - /* - if(search_space_mask & type0a_pdcch){ - } - - if(search_space_mask & type1_pdcch){ - } - - if(search_space_mask & type2_pdcch){ - } - - if(search_space_mask & type3_pdcch){ - } - */ - } - - - mac->scheduled_response.dl_config = dl_config; - return UE_CONNECTION_OK; } +// Notes: +// - Type1-PDCCH CSS configuration from ra-SearchSpace. +// - Msg2 is scheduled in the mixed slot or in the last dl slot if they are allowed by the Type 1 Common Search Space configuration +// todo: +// - if Type1-PDCCH CSS is not configured in RRC message (Coreset and SearchSpace), UE searches in Type 0 PDCCH CSS. +void nr_ue_msg2_scheduler(module_id_t mod_id, + uint16_t rach_frame, + uint16_t rach_slot, + uint16_t *msg2_frame, + uint16_t *msg2_slot){ + + uint8_t bwp_id = 1; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_CellGroupConfig_t *scg = mac->scg; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_BWP_Downlink_t *bwp = scg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id - 1]; + NR_SearchSpace_t *ss; + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + uint8_t mu = *scc->ssbSubcarrierSpacing; + uint8_t response_window = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow; + uint8_t slot_window, slot_limit, frame_limit; + uint16_t start_next_period, monitoring_slot_period, monitoring_offset; + + // number of mixed slot or of last dl slot if there is no mixed slot + uint16_t last_dl_slot_period = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; + uint16_t nr_dl_symbols = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols; + uint16_t nr_ul_symbols = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols; + + // lenght of tdd period in slots + uint16_t tdd_period_slot = last_dl_slot_period + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + + AssertFatal(commonSearchSpaceList->list.count > 0, "PDCCH common SearchSpace list has 0 elements\n"); + + LOG_D(MAC, "Frame %d, Slot %d: Scheduling Msg2 reception \n", rach_frame, rach_slot); + + // Common searchspace list + for (int i = 0; i < commonSearchSpaceList->list.count; i++) { + ss = commonSearchSpaceList->list.array[i]; + if(ss->searchSpaceId == *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace) + // retrieving ra pdcch monitoring period and offset + find_monitoring_periodicity_offset_common(ss, &monitoring_slot_period, &monitoring_offset); + } + + if (nr_dl_symbols == 0) + last_dl_slot_period--; + if ((nr_dl_symbols > 0) || (nr_ul_symbols > 0)) + tdd_period_slot++; + + // computing start of next period + start_next_period = (rach_slot - (rach_slot % tdd_period_slot) + tdd_period_slot) % nr_slots_per_frame[mu]; + *msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot + *msg2_frame = (*msg2_slot > rach_slot) ? rach_frame : (rach_frame +1); + + switch(response_window){ + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1: + slot_window = 1; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2: + slot_window = 2; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4: + slot_window = 4; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8: + slot_window = 8; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10: + slot_window = 10; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20: + slot_window = 20; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40: + slot_window = 40; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80: + slot_window = 80; + break; + default: + AssertFatal(1==0,"Invalid response window value %d\n",response_window); + } + AssertFatal(slot_window<=nr_slots_per_frame[mu], "Msg2 response window needs to be lower or equal to 10ms"); + + // slot and frame limit to transmit msg2 according to response window + slot_limit = (rach_slot + slot_window)%nr_slots_per_frame[mu]; + frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1); + + // go to previous slot if the current scheduled slot is beyond the response window + // and if the slot is not among the PDCCH monitored ones (38.213 10.1) + while ((*msg2_slot > slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu] + *msg2_slot - monitoring_offset) % monitoring_slot_period != 0)) { + if((*msg2_slot % tdd_period_slot) > 0) + (*msg2_slot)--; + else + AssertFatal(1 == 0, "No available DL slot to schedule reception of msg2 has been found"); + } + LOG_D(MAC, "Scheduled Msg2 reception in Frame %d, Slot %d: \n", *msg2_frame, *msg2_slot); +} + +// This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211, tables 6.3.3.2.x +// It fills the PRACH PDU per each FD occasion. +// PRACH formats 9, 10, 11 are corresponding to dual PRACH format configurations A1/B1, A2/B2, A3/B3. +// - todo: +// - Partial configuration is actually already stored in (fapi_nr_prach_config_t) &mac->phy_config.config_req->prach_config +void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { + + uint8_t config_index, mu, N_dur, N_t_slot, start_symbol; + uint16_t format, format0, format1, ncs; + int msg1_FDM, is_nr_prach_slot, fdm; + + NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP); + + fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; + fapi_nr_ul_config_prach_pdu *prach_config_pdu; + fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; + fapi_nr_prach_config_t *prach_config = &cfg->prach_config; + + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; + config_index = rach_ConfigGeneric->prach_ConfigurationIndex; + + mac->RA_offset = 2; // to compensate the rx frame offset at the gNB + + if (is_nr_UL_slot(scc, slotP)) { + + if (setup->msg1_SubcarrierSpacing) + mu = *setup->msg1_SubcarrierSpacing; + else + mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + is_nr_prach_slot = get_nr_prach_info_from_index(config_index, + (int)frameP, + (int)slotP, + frequencyInfoDL->absoluteFrequencyPointA, + mu, + cfg->cell_config.frame_duplex_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur); + + if (is_nr_prach_slot && mac->ra_state == RA_UE_IDLE) { + + mac->generate_nr_prach = 1; + + fdm = rach_ConfigGeneric->msg1_FDM; + + switch (fdm){ + case 0: + case 1: + case 2: + case 3: + msg1_FDM = 1 << fdm; + break; + default: + AssertFatal(1 == 0, "Unknown msg1_FDM from rach_ConfigGeneric %d\n", fdm); + } + + format0 = format & 0xff; // single PRACH format + format1 = (format >> 8) & 0xff; // dual PRACH format + + ul_config->sfn = frameP; + ul_config->slot = slotP; + + for (int n = 0; n < msg1_FDM; n++) { // one structure per frequency domain occasion + + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PRACH; + prach_config_pdu = &ul_config->ul_config_list[ul_config->number_pdus].prach_config_pdu; + memset(prach_config_pdu, 0, sizeof(fapi_nr_ul_config_prach_pdu)); + ul_config->number_pdus += 1; + + ncs = get_NCS(rach_ConfigGeneric->zeroCorrelationZoneConfig, format0, setup->restrictedSetConfig); + + // filling PRACH PDU for FAPI config request + prach_config_pdu->phys_cell_id = *scc->physCellId; + prach_config_pdu->num_prach_ocas = N_t_slot; + prach_config_pdu->prach_start_symbol = start_symbol; + prach_config_pdu->num_ra = n; + prach_config_pdu->num_cs = ncs; + prach_config_pdu->root_seq_id = prach_config->num_prach_fd_occasions_list[n].prach_root_sequence_index; + prach_config_pdu->restricted_set = prach_config->restricted_set_config; + prach_config_pdu->freq_msg1 = prach_config->num_prach_fd_occasions_list[n].k1; + + if (format1 != 0xff) { + switch(format0) { // dual PRACH format + case 0xa1: + prach_config_pdu->prach_format = 9; + break; + case 0xa2: + prach_config_pdu->prach_format = 10; + break; + case 0xa3: + prach_config_pdu->prach_format = 11; + break; + default: + AssertFatal(1 == 0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } else { + switch(format0) { // single PRACH format + case 0xa1: + prach_config_pdu->prach_format = 0; + break; + case 0xa2: + prach_config_pdu->prach_format = 1; + break; + case 0xa3: + prach_config_pdu->prach_format = 2; + break; + case 0xb1: + prach_config_pdu->prach_format = 3; + break; + case 0xb2: + prach_config_pdu->prach_format = 4; + break; + case 0xb3: + prach_config_pdu->prach_format = 5; + break; + case 0xb4: + prach_config_pdu->prach_format = 6; + break; + case 0xc0: + prach_config_pdu->prach_format = 7; + break; + case 0xc2: + prach_config_pdu->prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1 == 0, "Invalid PRACH format"); + } + } + } + } else { + mac->generate_nr_prach = 0; + } + mac->scheduled_response.ul_config = ul_config; + } +} + +//////////////////////////////////////////////////////////////////////////// +/////////* Random Access Contention Resolution (5.1.35 TS 38.321) *///////// +//////////////////////////////////////////////////////////////////////////// +// Handling contention resolution timer +// WIP todo: +// - beam failure recovery +// - RA completed + +void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + + if (mac->RA_contention_resolution_timer_active == 1) { + if (nr_rach_ConfigCommon){ + LOG_I(MAC, "Frame %d: Contention resolution timer %d/%ld\n", + tx_frame, + mac->RA_contention_resolution_cnt, + ((1 + nr_rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)); + mac->RA_contention_resolution_cnt++; + + if (mac->RA_contention_resolution_cnt == ((1 + nr_rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) { + mac->t_crnti = 0; + mac->RA_active = 0; + mac->RA_contention_resolution_timer_active = 0; + // Signal PHY to quit RA procedure + LOG_E(MAC, "[UE %u] [RAPROC] Contention resolution timer expired, RA failed, discarded TC-RNTI\n", module_id); + nr_ra_failed(module_id, cc_id, gNB_index); + } + } + } +} + #if 0 uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue, uint8_t slot, @@ -1839,9 +2235,14 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; if (pdsch_TimeDomainAllocationList) { - AssertFatal(pdsch_TimeDomainAllocationList->list.count > time_domain_ind, - "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n", - time_domain_ind,pdsch_TimeDomainAllocationList->list.count); + if (time_domain_ind >= pdsch_TimeDomainAllocationList->list.count) { + LOG_E(MAC, "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n", + time_domain_ind, pdsch_TimeDomainAllocationList->list.count); + dlsch_config_pdu->start_symbol = 0; + dlsch_config_pdu->number_symbols = 0; + return -1; + } + int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength; int S,L; SLIV2SL(startSymbolAndLength,&S,&L); @@ -1899,17 +2300,17 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci) { NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - nr_dci_pdu_rel15_t dci_pdu_rel15; LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n", dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits); - nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15); - nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format); - return 0; + nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,def_dci_pdu_rel15); + return (nr_ue_process_dci(module_id, cc_id, gNB_index, def_dci_pdu_rel15, dci->rnti, dci->dci_format)); } -int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ +int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ + + int bwp_id = 1; NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; @@ -1947,16 +2348,15 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu; /* IDENTIFIER_DCI_FORMATS */ /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac, - pusch_config_pdu_0_0,NULL, - dci->time_dom_resource_assignment); - + if (nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_0,NULL,dci->time_domain_assignment.val) < 0) + break; /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - pusch_config_pdu_0_0->frequency_hopping = dci->freq_hopping_flag; + pusch_config_pdu_0_0->frequency_hopping = dci->frequency_hopping_flag.val; + /* MCS */ pusch_config_pdu_0_0->mcs_index = dci->mcs; /* NDI */ @@ -1964,19 +2364,19 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* RV */ pusch_config_pdu_0_0->pusch_data.rv_index = dci->rv; /* HARQ_PROCESS_NUMBER */ - pusch_config_pdu_0_0->pusch_data.harq_process_id = dci->harq_process_number; + pusch_config_pdu_0_0->pusch_data.harq_process_id = dci->harq_pid; /* TPC_PUSCH */ // according to TS 38.213 Table Table 7.1.1-1 - if (dci->tpc_pusch == 0) { + if (dci->tpc == 0) { pusch_config_pdu_0_0->absolute_delta_PUSCH = -4; } - if (dci->tpc_pusch == 1) { + if (dci->tpc == 1) { pusch_config_pdu_0_0->absolute_delta_PUSCH = -1; } - if (dci->tpc_pusch == 2) { + if (dci->tpc == 2) { pusch_config_pdu_0_0->absolute_delta_PUSCH = 1; } - if (dci->tpc_pusch == 3) { + if (dci->tpc == 3) { pusch_config_pdu_0_0->absolute_delta_PUSCH = 4; } /* SUL_IND_0_0 */ // To be implemented, FIXME!!! @@ -2020,16 +2420,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* CARRIER_IND */ /* SUL_IND_0_1 */ /* BANDWIDTH_PART_IND */ - //pusch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind; //FIXME + //pusch_config_pdu_0_1->bandwidth_part_ind = dci->bwp_indicator.val; /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_1,NULL, - dci->time_dom_resource_assignment); + if (nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_1,NULL,dci->time_domain_assignment.val) < 0) + break; /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - pusch_config_pdu_0_1->frequency_hopping = dci->freq_hopping_flag; + pusch_config_pdu_0_1->frequency_hopping = dci->frequency_hopping_flag.val; /* MCS */ pusch_config_pdu_0_1->mcs_index = dci->mcs; /* NDI */ @@ -2037,21 +2437,21 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* RV */ pusch_config_pdu_0_1->pusch_data.rv_index = dci->rv; /* HARQ_PROCESS_NUMBER */ - pusch_config_pdu_0_1->pusch_data.harq_process_id = dci->harq_process_number; + pusch_config_pdu_0_1->pusch_data.harq_process_id = dci->harq_pid; /* FIRST_DAI */ //To be implemented, FIXME!!! /* SECOND_DAI */ //To be implemented, FIXME!!! /* TPC_PUSCH */ // according to TS 38.213 Table Table 7.1.1-1 - if (dci->tpc_pusch == 0) { + if (dci->tpc == 0) { pusch_config_pdu_0_1->absolute_delta_PUSCH = -4; } - if (dci->tpc_pusch == 1) { + if (dci->tpc == 1) { pusch_config_pdu_0_1->absolute_delta_PUSCH = -1; } - if (dci->tpc_pusch == 2) { + if (dci->tpc == 2) { pusch_config_pdu_0_1->absolute_delta_PUSCH = 1; } - if (dci->tpc_pusch == 3) { + if (dci->tpc == 3) { pusch_config_pdu_0_1->absolute_delta_PUSCH = 4; } /* SRS_RESOURCE_IND */ @@ -2069,16 +2469,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][0]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][1]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][2]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][3]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][4]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][5]; } } // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1 @@ -2086,16 +2486,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][6]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][7]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][8]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][9]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][10]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][11]; } } } @@ -2104,12 +2504,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][12]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][13]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][14]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][15]; } } // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1 @@ -2117,12 +2517,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][16]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][17]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18]; - pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19]; + pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][18]; + pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][19]; } } } @@ -2133,24 +2533,24 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6 pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC - pusch_config_pdu_0_1->dmrs_ports = dci->antenna_ports; //TBC + pusch_config_pdu_0_1->dmrs_ports = dci->antenna_ports.val; //TBC } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7 pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC - pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports); //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 3)?(dci->antenna_ports.val-4):(dci->antenna_ports.val); //TBC //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; //FIXME } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11 if (rank == 1){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 1)?2:1; //TBC - pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports); //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 1)?2:1; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val-2):(dci->antenna_ports.val); //TBC } if (rank == 2){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?2:1; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?2:1; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME //pusch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0; //pusch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1; @@ -2175,57 +2575,57 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15 if (rank == 1){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 1)?2:1; //TBC - pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; //TBC - //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1; //FIXME + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 1)?2:1; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 5 ?(dci->antenna_ports.val-6):(dci->antenna_ports.val-2)):dci->antenna_ports.val; //TBC + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 6)?2:1; //FIXME } if (rank == 2){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?2:1; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?2:1; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; // FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 3)?2:1; // FIXME } if (rank == 3){ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3]; - //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports.val][3]; + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME } if (rank == 4){ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3]; - //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4]; - //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports.val][3]; + //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports.val][4]; + //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME } } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19 if (rank == 1){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1; //TBC - pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 1)?((dci->antenna_ports.val > 5)?3:2):1; //TBC + pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 5 ?(dci->antenna_ports.val-6):(dci->antenna_ports.val-2)):dci->antenna_ports.val; //TBC } if (rank == 2){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?((dci->antenna_ports.val > 2)?3:2):1; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2]; + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports.val][2]; } if (rank == 3){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports > 0)?3:2; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?3:2; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3]; + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports.val][3]; } if (rank == 4){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = dci->antenna_ports + 2; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = dci->antenna_ports.val + 2; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME //pusch_config_pdu_0_1->dmrs_ports[0] = 0; //pusch_config_pdu_0_1->dmrs_ports[1] = 1; @@ -2237,53 +2637,53 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23 if (rank == 1){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_20[dci->antenna_ports][0]; //TBC - pusch_config_pdu_0_1->dmrs_ports = table_7_3_1_1_2_20[dci->antenna_ports][1]; //TBC - //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2]; //FIXME + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_20[dci->antenna_ports.val][0]; //TBC + pusch_config_pdu_0_1->dmrs_ports = table_7_3_1_1_2_20[dci->antenna_ports.val][1]; //TBC + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports.val][2]; //FIXME } if (rank == 2){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_21[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_21[dci->antenna_ports.val][0]; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3]; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports.val][3]; //FIXME } if (rank == 3){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_22[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_22[dci->antenna_ports.val][0]; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3]; - //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4]; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports.val][3]; + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports.val][4]; //FIXME } if (rank == 4){ - pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_23[dci->antenna_ports][0]; //TBC + pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_23[dci->antenna_ports.val][0]; //TBC pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME - //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1]; - //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2]; - //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3]; - //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4]; - //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5]; //FIXME + //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports.val][1]; + //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports.val][2]; + //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports.val][3]; + //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports.val][4]; + //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports.val][5]; //FIXME } } /* SRS_REQUEST */ // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - //pusch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 //FIXME + //pusch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request.val & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 //FIXME /* CSI_REQUEST */ - //pusch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request; //FIXME + //pusch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request.val; //FIXME /* CBGTI */ - //pusch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti; //FIXME + //pusch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti.val; //FIXME /* PTRS_DMRS */ if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) || ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){ } else { - //pusch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs; //FIXME + //pusch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs_association.val; //FIXME } /* BETA_OFFSET_IND */ // Table 9.3-3 in [5, TS 38.213] - //pusch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind; //FIXME + //pusch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_indicator.val; //FIXME /* DMRS_SEQ_INI */ // FIXME!! /* UL_SCH_IND */ @@ -2353,18 +2753,17 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr dlsch_config_pdu_1_0->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; /* IDENTIFIER_DCI_FORMATS */ /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ - nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); + nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0, - dci->time_dom_resource_assignment); - + if (nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0,dci->time_domain_assignment.val) < 0) + break; /* dmrs symbol positions*/ dlsch_config_pdu_1_0->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config, mac->scc->dmrs_TypeA_Position, dlsch_config_pdu_1_0->number_symbols); dlsch_config_pdu_1_0->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2; /* VRB_TO_PRB_MAPPING */ - dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; + dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; /* MCS */ dlsch_config_pdu_1_0->mcs = dci->mcs; /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ @@ -2372,9 +2771,9 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ dlsch_config_pdu_1_0->rv = dci->rv; /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number; + dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_pid; /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->dai = dci ->dai; + dlsch_config_pdu_1_0->dai = dci->dai[0].val; /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */ // according to TS 38.214 Table 5.1.3.2-3 if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1; @@ -2383,32 +2782,32 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ // according to TS 38.213 Table 7.2.1-1 - if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1; - if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0; - if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1; - if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3; + if (dci->tpc == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1; + if (dci->tpc == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0; + if (dci->tpc == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1; + if (dci->tpc == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3; /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ - //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! - dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind; + //if (dci->pucch_resource_indicator == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! + //if (dci->pucch_resource_indicator == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_indicator; /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ - dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind; + dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_timing_indicator.val; - LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n", + LOG_D(MAC,"(nr_ue_procedures.c) rnti = %x dl_config->number_pdus = %d\n", dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti, dl_config->number_pdus); LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n", - dci->freq_dom_resource_assignment_DL, + dci->frequency_domain_assignment.val, dlsch_config_pdu_1_0->number_rbs, dlsch_config_pdu_1_0->start_rb); LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n", - dci->time_dom_resource_assignment, + dci->time_domain_assignment.val, dlsch_config_pdu_1_0->number_symbols, dlsch_config_pdu_1_0->start_symbol); LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n", @@ -2423,7 +2822,11 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr dlsch_config_pdu_1_0->pucch_resource_id, dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind); - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + if (mac->ra_rnti == rnti) + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH; + else + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + // dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP; LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type); @@ -2469,145 +2872,143 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* BANDWIDTH_PART_IND */ // dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind; /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ - nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); + nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1, - dci->time_dom_resource_assignment); + if (nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1,dci->time_domain_assignment.val) < 0) + break; + /* dmrs symbol positions*/ + dlsch_config_pdu_1_1->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config, + mac->scc->dmrs_TypeA_Position, + dlsch_config_pdu_1_1->number_symbols); + dlsch_config_pdu_1_1->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2; /* VRB_TO_PRB_MAPPING */ if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0) - dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; + dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; /* PRB_BUNDLING_SIZE_IND */ - dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind; + dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_indicator.val; /* RATE_MATCHING_IND */ - dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind; + dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_indicator.val; /* ZP_CSI_RS_TRIGGER */ - dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger; + dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger.val; /* MCS (for transport block 1)*/ - dlsch_config_pdu_1_1->mcs = dci->tb1_mcs; + dlsch_config_pdu_1_1->mcs = dci->mcs; /* NDI (for transport block 1)*/ - dlsch_config_pdu_1_1->ndi = dci->tb1_ndi; + dlsch_config_pdu_1_1->ndi = dci->ndi; /* RV (for transport block 1)*/ - dlsch_config_pdu_1_1->rv = dci->tb1_rv; + dlsch_config_pdu_1_1->rv = dci->rv; /* MCS (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs; + dlsch_config_pdu_1_1->tb2_mcs = dci->mcs2.val; /* NDI (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi; + dlsch_config_pdu_1_1->tb2_ndi = dci->ndi2.val; /* RV (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv; + dlsch_config_pdu_1_1->tb2_rv = dci->rv2.val; /* HARQ_PROCESS_NUMBER */ - dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number; + dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_pid; /* DAI */ - dlsch_config_pdu_1_1->dai = dci ->dai; + dlsch_config_pdu_1_1->dai = dci->dai[0].val; /* TPC_PUCCH */ // according to TS 38.213 Table 7.2.1-1 - if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1; - if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0; - if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; - if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; + if (dci->tpc == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1; + if (dci->tpc == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0; + if (dci->tpc == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; + if (dci->tpc == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; /* PUCCH_RESOURCE_IND */ - if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + dlsch_config_pdu_1_1->pucch_resource_id = dci->pucch_resource_indicator; /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */ // according to TS 38.213 Table 9.2.3-1 - dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind]; + dlsch_config_pdu_1_1->pdsch_to_harq_feedback_time_ind = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[dci->pdsch_to_harq_feedback_timing_indicator.val][0]; /* ANTENNA_PORTS */ uint8_t n_codewords = 1; // FIXME!!! if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1 - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports.val][4]; } if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2 if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][5]; } if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6]; - dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7]; - dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][6]; + dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][7]; + dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][8]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][9]; } } if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1 if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][4]; } if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][6]; } } if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2 if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][5]; } if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6]; - dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7]; - dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][6]; + dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][7]; + dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][8]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][9]; } } /* TCI */ if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){ // 0 bit if higher layer parameter tci-PresentInDCI is not enabled // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214] - dlsch_config_pdu_1_1->tci_state = dci->tci; + dlsch_config_pdu_1_1->tci_state = dci->transmission_configuration_indication.val; } /* SRS_REQUEST */ // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 + dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request.val & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 /* CBGTI */ - dlsch_config_pdu_1_1->cbgti = dci->cbgti; + dlsch_config_pdu_1_1->cbgti = dci->cbgti.val; /* CBGFI */ - dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi; + dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi.val; /* DMRS_SEQ_INI */ //FIXME!!! @@ -2670,7 +3071,6 @@ void nr_ue_send_sdu(module_id_t module_idP, LOG_D(MAC, "Handling PDU frame %d slot %d\n", frameP, slotP); uint8_t * pduP = pdu; - NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SEND_SDU, VCD_FUNCTION_IN); @@ -2707,7 +3107,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, uint8_t dci_size, uint16_t rnti, uint64_t *dci_pdu, - nr_dci_pdu_rel15_t *dci_pdu_rel15) { + dci_pdu_rel15_t *dci_pdu_rel15) { int rnti_type=-1; if (rnti == mac->ra_rnti) rnti_type = NR_RNTI_RA; @@ -2719,10 +3119,10 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, AssertFatal(rnti_type!=-1,"no identified/handled rnti\n"); AssertFatal(mac->DLbwp[0] != NULL, "DLbwp[0] shouldn't be null here!\n"); AssertFatal(mac->ULbwp[0] != NULL, "ULbwp[0] shouldn't be null here!\n"); - int N_RB = (mac->scd != NULL) ? + int N_RB = (mac->scg != NULL) ? NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) : NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); - int N_RB_UL = (mac->scd != NULL) ? + int N_RB_UL = (mac->scg != NULL) ? NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) : NRRIV2BW(mac->scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); @@ -2736,22 +3136,22 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_DL = *dci_pdu>>(dci_size-pos)&((1<frequency_domain_assignment.val = *dci_pdu>>(dci_size-pos)&((1< %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,N_RB,dci_size-pos,*dci_pdu); + LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu); #endif // Time domain assignment pos+=4; - dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu >> (dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu); + LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping pos++; - dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&0x1; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&0x1; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu); #endif // MCS pos+=5; @@ -2766,28 +3166,30 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); #endif break; - + + mac->rnti_type = rnti_type; + case NR_RNTI_C: // indicating a DL DCI format 1bit pos++; - dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->identifier_dci_formats,1,N_RB,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); #endif // Freq domain assignment (275rb >> fsize = 16) fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos+=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1< %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); #endif uint16_t is_ra = 1; for (int i=0; ifreq_dom_resource_assignment_DL>>i)&1)) { + if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) { is_ra = 0; break; } @@ -2799,7 +3201,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // UL/SUL indicator 1 bit pos++; - dci_pdu_rel15->sul_ind_0_1 = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&1; // SS/PBCH index 6 bits pos+=6; @@ -2815,16 +3217,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // Time domain assignment 4bit pos+=4; - dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,4,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping 1bit pos++; - dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu); #endif // MCS 5bit //bit over 32, so dci_pdu ++ @@ -2850,37 +3252,37 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // HARQ process number 4bit pos+=4; - dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_process_number,4,dci_size-pos,*dci_pdu); + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); #endif // Downlink assignment index 2bit pos+=2; - dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu); #endif // TPC command for scheduled PUCCH 2bit pos+=2; - dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc_pucch,2,dci_size-pos,*dci_pdu); + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); #endif // PUCCH resource indicator 3bit pos+=3; - dci_pdu_rel15->pucch_resource_ind = (*dci_pdu>>(dci_size-pos))&0x7; + dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x7; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_ind,3,dci_size-pos,*dci_pdu); + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); #endif // PDSCH-to-HARQ_feedback timing indicator 3bit pos+=3; - dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&0x7; + dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&0x7; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_time_ind,3,dci_size-pos,*dci_pdu); + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu); #endif } //end else @@ -2902,7 +3304,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, for (int i=0; i<4; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -2924,7 +3326,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, for (int i=0; i<4; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -2937,16 +3339,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, case NR_RNTI_TC: // indicating a DL DCI format 1bit pos++; - dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos+=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; // VRB to PRB mapping 1 bit - dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1; // MCS 5bit //bit over 32, so dci_pdu ++ pos+=5; dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; @@ -2957,16 +3359,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3; // HARQ process number 4bit pos+=4; - dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; // Downlink assignment index – 2 bits pos+=2; - dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3; // TPC command for scheduled PUCCH – 2 bits pos+=2; - dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3; // PDSCH-to-HARQ_feedback timing indicator – 3 bits pos+=3; - dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&7; + dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&7; break; } @@ -2977,17 +3379,17 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, { case NR_RNTI_C: // indicating a DL DCI format 1bit - dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); pos+=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_UL = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; // Frequency hopping flag – 1 bit pos++; - dci_pdu_rel15->freq_hopping_flag= (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1; // MCS 5 bit pos+=5; dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f; @@ -2999,10 +3401,10 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3; // HARQ process number 4bit pos+=4; - dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; // TPC command for scheduled PUSCH – 2 bits pos+=2; - dci_pdu_rel15->tpc_pusch = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3; // UL/SUL indicator – 1 bit /* commented for now (RK): need to get this from BWP descriptor if (cfg->pucch_config.pucch_GroupHopping.value) @@ -3049,6 +3451,90 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, } break; + + case NR_DL_DCI_FORMAT_1_1: + // Format indicator + pos=1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; + // Carrier indicator + pos+=dci_pdu_rel15->carrier_indicator.nbits; + dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<carrier_indicator.nbits)-1); + // BWP Indicator + pos+=dci_pdu_rel15->bwp_indicator.nbits; + dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<bwp_indicator.nbits)-1); + // Frequency domain resource assignment + pos+=dci_pdu_rel15->frequency_domain_assignment.nbits; + dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.nbits)-1); + // Time domain resource assignment + pos+=dci_pdu_rel15->time_domain_assignment.nbits; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<time_domain_assignment.nbits)-1); + // VRB-to-PRB mapping + pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&((1<vrb_to_prb_mapping.nbits)-1); + // PRB bundling size indicator + pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits; + dci_pdu_rel15->prb_bundling_size_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<prb_bundling_size_indicator.nbits)-1); + // Rate matching indicator + pos+=dci_pdu_rel15->rate_matching_indicator.nbits; + dci_pdu_rel15->rate_matching_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<rate_matching_indicator.nbits)-1); + // ZP CSI-RS trigger + pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits; + dci_pdu_rel15->zp_csi_rs_trigger.val = (*dci_pdu>>(dci_size-pos))&((1<zp_csi_rs_trigger.nbits)-1); + //TB1 + // MCS 5bit + pos+=5; + dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; + // New data indicator 1bit + pos+=1; + dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&0x1; + // Redundancy version 2bit + pos+=2; + dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3; + //TB2 + // MCS 5bit + pos+=dci_pdu_rel15->mcs2.nbits; + dci_pdu_rel15->mcs2.val = (*dci_pdu>>(dci_size-pos))&((1<mcs2.nbits)-1); + // New data indicator 1bit + pos+=dci_pdu_rel15->ndi2.nbits; + dci_pdu_rel15->ndi2.val = (*dci_pdu>>(dci_size-pos))&((1<ndi2.nbits)-1); + // Redundancy version 2bit + pos+=dci_pdu_rel15->rv2.nbits; + dci_pdu_rel15->rv2.val = (*dci_pdu>>(dci_size-pos))&((1<rv2.nbits)-1); + // HARQ process number 4bit + pos+=4; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; + // Downlink assignment index + pos+=dci_pdu_rel15->dai[0].nbits; + dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<dai[0].nbits)-1); + // TPC command for scheduled PUCCH 2bit + pos+=2; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&0x3; + // PUCCH resource indicator 3bit + pos+=3; + dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x3; + // PDSCH-to-HARQ_feedback timing indicator + pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits; + dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<pdsch_to_harq_feedback_timing_indicator.nbits)-1); + // Antenna ports + pos+=dci_pdu_rel15->antenna_ports.nbits; + dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<antenna_ports.nbits)-1); + // TCI + pos+=dci_pdu_rel15->transmission_configuration_indication.nbits; + dci_pdu_rel15->transmission_configuration_indication.val = (*dci_pdu>>(dci_size-pos))&((1<transmission_configuration_indication.nbits)-1); + // SRS request + pos+=dci_pdu_rel15->srs_request.nbits; + dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<srs_request.nbits)-1); + // CBG transmission information + pos+=dci_pdu_rel15->cbgti.nbits; + dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<cbgti.nbits)-1); + // CBG flushing out information + pos+=dci_pdu_rel15->cbgfi.nbits; + dci_pdu_rel15->cbgfi.val = (*dci_pdu>>(dci_size-pos))&((1<cbgfi.nbits)-1); + // DMRS sequence init + pos+=1; + dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&0x1; + break; + } } @@ -3067,6 +3553,7 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, uint8_t *pdu_ptr = pduP, rx_lcid, done = 0; int pdu_len = mac_pdu_len; uint16_t mac_ce_len, mac_subheader_len, mac_sdu_len; + NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP); //NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP); //uint8_t scs = UE_mac_inst->mib->subCarrierSpacingCommon; @@ -3227,8 +3714,34 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, break; case DL_SCH_LCID_CON_RES_ID: // 38.321 Ch6.1.3.3 + // WIP todo: handle CCCH_pdu mac_ce_len = 6; + + LOG_I(MAC, "[UE %d][RAPROC] Frame %d : received contention resolution msg: %x.%x.%x.%x.%x.%x, Terminating RA procedure\n", module_idP, frameP, pdu_ptr[0], pdu_ptr[1], pdu_ptr[2], pdu_ptr[3], pdu_ptr[4], pdu_ptr[5]); + if (mac->RA_active == 1) { + LOG_I(MAC, "[UE %d][RAPROC] Frame %d : Clearing RA_active flag\n", module_idP, frameP); + mac->RA_active = 0; + // // check if RA procedure has finished completely (no contention) + // tx_sdu = &mac->CCCH_pdu.payload[3]; + // //Note: 3 assumes sizeof(SCH_SUBHEADER_SHORT) + PADDING CE, which is when UL-Grant has TBS >= 9 (64 bits) + // // (other possibility is 1 for TBS=7 (SCH_SUBHEADER_FIXED), or 2 for TBS=8 (SCH_SUBHEADER_FIXED+PADDING or // SCH_SUBHEADER_SHORT) + // for (i = 0; i < 6; i++) + // if (tx_sdu[i] != payload_ptr[i]) { + // LOG_E(MAC, "[UE %d][RAPROC] Contention detected, RA failed\n", module_idP); + // nr_ra_failed(module_idP, CC_id, eNB_index); + // mac->RA_contention_resolution_timer_active = 0; + // return; + // } + LOG_I(MAC, "[UE %d][RAPROC] Frame %d : Cleared contention resolution timer. Set C-RNTI to TC-RNTI\n", + module_idP, + frameP); + mac->RA_contention_resolution_timer_active = 0; + nr_ra_succeeded(module_idP, CC_id, gNB_index); + mac->crnti = mac->t_crnti; + mac->t_crnti = 0; + mac->ra_state = RA_SUCCEEDED; + } break; case DL_SCH_LCID_PADDING: done = 1; @@ -3294,71 +3807,181 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, } } -//--------------------------------------------------------------------------------- +//////////////////////////////////////////////////////// +/////* ULSCH MAC PDU generation (6.1.2 TS 38.321) *///// +//////////////////////////////////////////////////////// +uint16_t nr_generate_ulsch_pdu(uint8_t *sdus_payload, + uint8_t *pdu, + uint8_t num_sdus, + uint16_t *sdu_lengths, + uint8_t *sdu_lcids, + uint8_t power_headroom, + uint16_t crnti, + uint16_t truncated_bsr, + uint16_t short_bsr, + uint16_t long_bsr, + unsigned short post_padding, + uint16_t buflen) { -uint16_t -nr_generate_ulsch_pdu(uint8_t *mac_pdu, - uint8_t *sdus_payload, - uint8_t num_sdus, - uint16_t *sdu_lengths, - uint8_t *sdu_lcids, - uint16_t *crnti, - uint16_t buflen) { + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) pdu; + unsigned char last_size = 0, i, mac_header_control_elements[16], *ce_ptr, bsr = 0; + int mac_ce_size; + uint16_t offset = 0; - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * ulsch_buffer_ptr = sdus_payload; - uint8_t last_size=0; - uint16_t sdu_length_total=0; - int i; - int offset=0; + LOG_D(MAC, "[UE] Generating ULSCH PDU : num_sdus %d\n", num_sdus); - // 2) Generation of ULSCH MAC SDU subheaders - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate ULSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + #ifdef DEBUG_HEADER_PARSING - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; - } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; - } + for (i = 0; i < num_sdus; i++) + LOG_D(MAC, "[UE] MAC subPDU %d (lcid %d length %d bytes \n", i, sdu_lcids[i], sdu_lengths[i]); - mac_pdu_ptr += last_size; + #endif - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) ulsch_buffer_ptr, sdu_lengths[i]); - ulsch_buffer_ptr+= sdu_lengths[i]; - sdu_length_total+= sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } + // Generating UL MAC subPDUs including MAC SDU and subheader - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[UE] Generating UL MAC subPDUs for SDU with lenght %d ( num_sdus %d )\n", sdu_lengths[i], num_sdus); - // 4) Compute final offset for padding - uint16_t padding_bytes = buflen - offset; - LOG_D(MAC, "Number of padding bytes: %d \n", padding_bytes); - if (padding_bytes > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = UL_SCH_LCID_PADDING; - mac_pdu_ptr++; + if (sdu_lcids[i] != UL_SCH_LCID_CCCH){ + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + } else { // UL CCCH SDU + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = sdu_lcids[i]; + } - } else { - // no MAC subPDU with padding - } + mac_pdu_ptr += last_size; + + // cycle through SDUs, compute each relevant and place ulsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) sdus_payload, sdu_lengths[i]); + sdus_payload += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // Generating UL MAC subPDUs including MAC CEs (MAC CE and subheader) + + ce_ptr = &mac_header_control_elements[0]; + + if (power_headroom) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = UL_SCH_LCID_SINGLE_ENTRY_PHR; + mac_pdu_ptr++; + + // PHR MAC CE (1 octet) + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->PH = power_headroom; + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->R1 = 0; + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->PCMAX = 0; // todo + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->R2 = 0; + + mac_ce_size = sizeof(NR_SINGLE_ENTRY_PHR_MAC_CE); + + // Copying bytes for PHR MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (crnti) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = CRNTI; + mac_pdu_ptr++; + + // C-RNTI MAC CE (2 octets) + * (uint16_t *) ce_ptr = crnti; + mac_ce_size = sizeof(uint16_t); + + // Copying bytes for CRNTI MAC CE to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (truncated_bsr) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = UL_SCH_LCID_S_TRUNCATED_BSR; + mac_pdu_ptr++; + + // Short truncated BSR MAC CE (1 octet) + ((NR_BSR_SHORT_TRUNCATED *) ce_ptr)-> Buffer_size = truncated_bsr; + ((NR_BSR_SHORT_TRUNCATED *) ce_ptr)-> LcgID = 0; // todo + mac_ce_size = sizeof(NR_BSR_SHORT_TRUNCATED); + + bsr = 1 ; + } else if (short_bsr) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = UL_SCH_LCID_S_BSR; + mac_pdu_ptr++; + + // Short truncated BSR MAC CE (1 octet) + ((NR_BSR_SHORT *) ce_ptr)->Buffer_size = short_bsr; + ((NR_BSR_SHORT *) ce_ptr)->LcgID = 0; // todo + mac_ce_size = sizeof(NR_BSR_SHORT); + + bsr = 1 ; + } else if (long_bsr) { + // MAC CE variable subheader + // todo ch 6.1.3.1. TS 38.321 + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = UL_SCH_LCID_L_BSR; + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = 0; + // last_size = 2; + // mac_pdu_ptr += last_size; + + // Short truncated BSR MAC CE (1 octet) + // ((NR_BSR_LONG *) ce_ptr)->Buffer_size0 = short_bsr; + // ((NR_BSR_LONG *) ce_ptr)->LCGID0 = 0; + // mac_ce_size = sizeof(NR_BSR_LONG); // size is variable + } + + if (bsr){ + // Copying bytes for BSR MAC CE to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + // compute offset before adding padding (if necessary) + offset = ((unsigned char *) mac_pdu_ptr - pdu); + uint16_t padding_bytes = 0; + + if(buflen > 0) // If the buflen is provided + padding_bytes = buflen - offset; + + // Compute final offset for padding + if (post_padding > 0 || padding_bytes>0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = UL_SCH_LCID_PADDING; + mac_pdu_ptr++; + } else { + // no MAC subPDU with padding + } + + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - pdu); + + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - pdu)); return offset; } - uint8_t nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t subframe, uint8_t eNB_index, @@ -3431,13 +4054,6 @@ nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, sdu_length_total += sdu_lengths[num_sdus]; sdu_lcids[num_sdus] = lcid; - - //Update total MAC Header size for RLC PDUs - /*if(sdu_lengths[num_sdus]<128) - total_rlc_pdu_header_len += 2; - else - total_rlc_pdu_header_len += 3;*/ - total_rlc_pdu_header_len += MAX_RLC_SDU_SUBHEADER_SIZE; //rlc_pdu_header_len_last; //Update number of SDU @@ -3462,13 +4078,18 @@ nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP, // Generate ULSCH PDU if (num_sdus>0) { - payload_offset = nr_generate_ulsch_pdu(ulsch_buffer, // mac header - ulsch_sdus, + payload_offset = nr_generate_ulsch_pdu(ulsch_sdus, + ulsch_buffer, // mac header num_sdus, // num sdus sdu_lengths, // sdu length sdu_lcids, // sdu lcid - NULL, // crnti - buflen); // long_bsr + 0, // power_headroom + 0, // crnti + 0, // truncated_bsr + 0, // short_bsr + 0, // long_bsr + 0, // post_padding + buflen); // TBS in bytes } else return 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index b5fdea6760..36b81927f8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -44,7 +44,7 @@ #include "SCHED_NR/phy_frame_config_nr.h" #include "NR_MIB.h" -#include "nr_mac_common.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" extern RAN_CONTEXT_t RC; //extern int l2_init_gNB(void); @@ -121,13 +121,23 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm } } + lte_frame_type_t frame_type; + uint16_t band; + int32_t offset; + + get_band((cfg->carrier_config.dl_frequency.value)*1000, + &band, + &offset, + &frame_type); + + RC.nrmac[Mod_idP]->common_channels[0].frame_type = frame_type; // Cell configuration cfg->cell_config.phy_cell_id.value = *scc->physCellId; cfg->cell_config.phy_cell_id.tl.tag = NFAPI_NR_CONFIG_PHY_CELL_ID_TAG; cfg->num_tlv++; - cfg->cell_config.frame_duplex_type.value = 1; + cfg->cell_config.frame_duplex_type.value = frame_type; cfg->cell_config.frame_duplex_type.tl.tag = NFAPI_NR_CONFIG_FRAME_DUPLEX_TYPE_TAG; cfg->num_tlv++; @@ -143,7 +153,11 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm // PRACH configuration - cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present; + uint8_t nb_preambles = 64; + if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL) + nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles; + + cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present-1; cfg->prach_config.prach_sequence_length.tl.tag = NFAPI_NR_CONFIG_PRACH_SEQUENCE_LENGTH_TAG; cfg->num_tlv++; @@ -153,7 +167,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm cfg->prach_config.prach_sub_c_spacing.value = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; cfg->prach_config.prach_sub_c_spacing.tl.tag = NFAPI_NR_CONFIG_PRACH_SUB_C_SPACING_TAG; cfg->num_tlv++; - cfg->prach_config.restricted_set_config.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig; cfg->prach_config.restricted_set_config.tl.tag = NFAPI_NR_CONFIG_RESTRICTED_SET_CONFIG_TAG; cfg->num_tlv++; @@ -192,13 +205,17 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig; cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.tl.tag = NFAPI_NR_CONFIG_PRACH_ZERO_CORR_CONF_TAG; cfg->num_tlv++; + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences.value = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, + nb_preambles, frame_type); + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences.tl.tag = NFAPI_NR_CONFIG_NUM_ROOT_SEQUENCES_TAG; + cfg->num_tlv++; //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences.value = ??? } - cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present; + cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present-1; cfg->prach_config.ssb_per_rach.tl.tag = NFAPI_NR_CONFIG_SSB_PER_RACH_TAG; cfg->num_tlv++; - + // SSB Table Configuration int scs_scaling = 1<<(cfg->ssb_config.scs_common.value); if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA < 600000) @@ -273,8 +290,7 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots, scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols, scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots, - scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols - ); + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols); if (return_tdd !=0){ LOG_E(PHY,"TDD configuration can not be done\n"); @@ -357,6 +373,12 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, if (add_ue == 1) { UE_id = add_new_nr_ue(Mod_idP,rnti); UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup; + uint8_t num_preamble = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.count; + UE_list->preambles[UE_id].num_preambles = num_preamble; + UE_list->preambles[UE_id].preamble_list = (uint8_t *) malloc(num_preamble*sizeof(uint8_t)); + for (int i=0; ipreambles[UE_id].preamble_list[i] = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.array[i]->ra_PreambleIndex; + } LOG_I(PHY,"Added new UE_id %d/%x with initial secondaryCellGroup\n",UE_id,rnti); } else { // secondaryCellGroup has been updated diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 702b034809..e25680e861 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -33,9 +33,9 @@ #include "assertions.h" #include "LAYER2/MAC/mac.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/MAC/mac_proto.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" @@ -59,10 +59,9 @@ #include "executables/softmodem-common.h" +const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160}; uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 }; -uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; - void clear_nr_nfapi_information(gNB_MAC_INST * gNB, int CC_idP, frame_t frameP, @@ -259,18 +258,6 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram } */ -/* -void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { - - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - - // schedule PRACH for iniital BWP - - if (is_initialBWP_prach_subframe(frameP,subframeP)<0) return; - - // fill FAPI -} -*/ /* void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) @@ -318,12 +305,14 @@ void nr_schedule_pucch(int Mod_idP, NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; - NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - NR_sched_pucch *temp_pucch; - int release_pucch = 0; + NR_sched_pucch *curr_pucch; + int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) + nr_ulmix_slots++; - if (curr_pucch != NULL) { - if ((frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { + for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k]; + if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { UL_tti_req->SFN = frameP; UL_tti_req->Slot = slotP; UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE; @@ -334,6 +323,8 @@ void nr_schedule_pucch(int Mod_idP, O_ack = curr_pucch->dai_c; O_uci = O_ack; // for now we are just sending acknacks in pucch + LOG_I(MAC, "Scheduling pucch reception for frame %d slot %d\n", frameP, slotP); + nr_configure_pucch(pucch_pdu, scc, ubwp, @@ -342,16 +333,9 @@ void nr_schedule_pucch(int Mod_idP, O_ack, SR_flag); - release_pucch = 1; + curr_pucch->dai_c = 0; } } - - if (release_pucch) { - temp_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - UE_list->UE_sched_ctrl[UE_id].sched_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch->next_sched_pucch; - free(temp_pucch); - } - } bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){ @@ -372,15 +356,37 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, protocol_ctxt_t ctxt; PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame_txP, slot_txP,module_idP); - int CC_id, UE_id = 0; + + int CC_id; + int UE_id; + uint64_t *dlsch_in_slot_bitmap=NULL; + uint64_t *ulsch_in_slot_bitmap=NULL; + int pucch_sched; + + UE_id=0; + int bwp_id = 1; + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_UE_list_t *UE_list = &gNB->UE_list; NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; NR_COMMON_channels_t *cc = gNB->common_channels; - NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + int num_slots_per_tdd = (slots_per_frame[*scc->ssbSubcarrierSpacing])>>(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity); + + int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) + nr_ulmix_slots++; + + if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) { + for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k], + 0, + sizeof(NR_sched_pucch)); + } + } start_meas(&RC.nrmac[module_idP]->eNB_scheduler); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); pdcp_run(&ctxt); //rrc_rx_tx(&ctxt, CC_id); @@ -388,10 +394,29 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, RC.nrmac[module_idP]->frame = frame_rxP; RC.nrmac[module_idP]->slot = slot_rxP; + dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch + ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch + + // hardcoding dlsch to be in slot 1 + if (!(slot_txP%num_slots_per_tdd)) { + if(slot_txP==0) + *dlsch_in_slot_bitmap = 0x02; + else + *dlsch_in_slot_bitmap = 0x00; + } + + // hardcoding ulsch to be in slot 8 + if (!(slot_rxP%num_slots_per_tdd)) { + if(slot_rxP==0) + *ulsch_in_slot_bitmap = 0x100; + else + *ulsch_in_slot_bitmap = 0x00; + } + // Check if there are downlink symbols in the slot, if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) { - - memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0 + memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1 for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { //mbsfn_status[CC_id] = 0; @@ -407,43 +432,52 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, for (i = 0; i < MAX_MOBILES_PER_GNB; i++) { if (UE_list->active[i]) { - nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; - + nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; rnti = 0;//UE_RNTI(module_idP, i); CC_id = 0;//UE_PCCID(module_idP, i); - - } //END if (UE_list->active[i]) - } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) - */ - - // This schedules MIB - if((slot_txP == 0) && (frame_txP & 7) == 0){ - schedule_nr_mib(module_idP, frame_txP, slot_txP); - } - // TbD once RACH is available, start ta_timer when UE is connected -#if 0 - if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; + } //END if (UE_list->active[i]) + } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) + */ - if (ue_sched_ctl->ta_timer == 0) { - gNB->ta_command = ue_sched_ctl->ta_update; - /* if time is up, then set the timer to not send it for 5 frames - // regardless of the TA value */ - ue_sched_ctl->ta_timer = 100; - /* reset ta_update */ - ue_sched_ctl->ta_update = 31; - /* MAC CE flag indicating TA length */ - gNB->ta_len = 2; - } -#endif + // This schedules MIB + if((slot_txP == 0) && (frame_txP & 7) == 0){ + schedule_nr_mib(module_idP, frame_txP, slot_txP); + } - // Phytest scheduling - if (get_softmodem_params()->phy_test && slot_txP==1){ - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); - // resetting ta flag - gNB->ta_len = 0; - } + if (get_softmodem_params()->phy_test == 0) + nr_schedule_RA(module_idP, frame_txP, slot_txP); + else + UE_list->fiveG_connected[UE_id] = true; + + // Phytest scheduling + + if (get_softmodem_params()->phy_test) { + + // TbD once RACH is available, start ta_timer when UE is connected + if (ue_sched_ctl->ta_timer) + ue_sched_ctl->ta_timer--; + + if (ue_sched_ctl->ta_timer == 0) { + gNB->ta_command = ue_sched_ctl->ta_update; + /* if time is up, then set the timer to not send it for 5 frames + // regardless of the TA value */ + ue_sched_ctl->ta_timer = 100; + /* reset ta_update */ + ue_sched_ctl->ta_update = 31; + /* MAC CE flag indicating TA length */ + gNB->ta_len = 2; + } + } + + if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { + ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; + nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); + // resetting ta flag + gNB->ta_len = 0; + } /* // Allocate CCEs for good after scheduling is done @@ -454,12 +488,22 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } //is_nr_DL_slot if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { - if (get_softmodem_params()->phy_test && slot_rxP==8){ - nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); + + if (get_softmodem_params()->phy_test == 0) { + if (UE_list->fiveG_connected[UE_id]) + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); + schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); + nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); + } + if (get_softmodem_params()->phy_test){ + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); + if (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%num_slots_per_tdd)){ + nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); + } } } stop_meas(&RC.nrmac[module_idP]->eNB_scheduler); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index d74df15eac..2eb4ad498b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -19,44 +19,802 @@ * contact@openairinterface.org */ -/*! \file gNB_scheduler_RA.c - * \brief primitives used for random access - * \author - * \date - * \email: +/*! \file gNB_scheduler_RA.c + * \brief primitives used for random access + * \author Guido Casati + * \date 2019 + * \email: guido.casati@iis.fraunhofer.de * \version */ -#include nr_mac_gNB.h +#include "platform_types.h" -void -schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) -{ +/* MAC */ +#include "nr_mac_gNB.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" - eNB_MAC_INST *mac = RC.mac[module_idP]; - COMMON_channels_t *cc = mac->common_channels; - RA_t *ra; - uint8_t i; +/* Utils */ +#include "common/utils/LOG/log.h" +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "common/utils/nr/nr_common.h" +#include "UTIL/OPT/opt.h" +#include "SIMULATION/TOOLS/sim.h" // for taus + +extern RAN_CONTEXT_t RC; + +const uint8_t nr_slots_per_frame_mac[5] = {10, 20, 40, 80, 160}; + +uint8_t DELTA[4]= {2,3,4,6}; + +void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { + + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = gNB->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0]; + + uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex; + uint8_t mu,N_dur,N_t_slot,start_symbol; + uint16_t format; + + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) + mu = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; + else + mu = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + // prach is scheduled according to configuration index and tables 6.3.3.2.2 to 6.3.3.2.4 + if ( get_nr_prach_info_from_index(config_index, + (int)frameP, + (int)slotP, + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA, + mu, + cc->frame_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur) ) { + + int fdm = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM; + uint16_t format0 = format&0xff; // first column of format from table + uint16_t format1 = (format>>8)&0xff; // second column of format from table + + UL_tti_req->SFN = frameP; + UL_tti_req->Slot = slotP; + for (int n=0; n<(1<pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_prach_pdu_t); + nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].prach_pdu; + memset(prach_pdu,0,sizeof(nfapi_nr_prach_pdu_t)); + UL_tti_req->n_pdus+=1; + + // filling the prach fapi structure + prach_pdu->phys_cell_id = *scc->physCellId; + prach_pdu->num_prach_ocas = N_t_slot; + prach_pdu->prach_start_symbol = start_symbol; + prach_pdu->num_ra = n; + prach_pdu->num_cs = get_NCS(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig, + format0, + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig); + // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities + // We added 9 = A1/B1 10 = A2/B2 11 A3/B3 + if (format1!=0xff) { + switch(format0) { + case 0xa1: + prach_pdu->prach_format = 9; + break; + case 0xa2: + prach_pdu->prach_format = 10; + break; + case 0xa3: + prach_pdu->prach_format = 11; + break; + default: + AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } + else{ + switch(format0) { + case 0xa1: + prach_pdu->prach_format = 0; + break; + case 0xa2: + prach_pdu->prach_format = 1; + break; + case 0xa3: + prach_pdu->prach_format = 2; + break; + case 0xb1: + prach_pdu->prach_format = 3; + break; + case 0xb2: + prach_pdu->prach_format = 4; + break; + case 0xb3: + prach_pdu->prach_format = 5; + break; + case 0xb4: + prach_pdu->prach_format = 6; + break; + case 0xc0: + prach_pdu->prach_format = 7; + break; + case 0xc2: + prach_pdu->prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1==0,"Invalid PRACH format"); + } + } + } + } +} + + +void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot, + uint16_t *msg2_frame, uint16_t *msg2_slot, + NR_ServingCellConfigCommon_t *scc, + uint16_t monitoring_slot_period, + uint16_t monitoring_offset){ + + // preferentially we schedule the msg2 in the mixed slot or in the last dl slot + // if they are allowed by search space configuration + + uint8_t mu = *scc->ssbSubcarrierSpacing; + uint8_t response_window = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow; + uint8_t slot_window; + // number of mixed slot or of last dl slot if there is no mixed slot + uint8_t last_dl_slot_period = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; + // lenght of tdd period in slots + uint8_t tdd_period_slot = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols == 0) + last_dl_slot_period--; + if ((scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols > 0) || (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols > 0)) + tdd_period_slot++; + + // computing start of next period + uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame_mac[mu]; + *msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot + *msg2_frame = (*msg2_slot>(rach_slot))? rach_frame : (rach_frame +1); + + switch(response_window){ + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1: + slot_window = 1; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2: + slot_window = 2; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4: + slot_window = 4; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8: + slot_window = 8; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10: + slot_window = 10; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20: + slot_window = 20; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40: + slot_window = 40; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80: + slot_window = 80; + break; + default: + AssertFatal(1==0,"Invalid response window value %d\n",response_window); + } + AssertFatal(slot_window<=nr_slots_per_frame_mac[mu],"Msg2 response window needs to be lower or equal to 10ms"); + + // slot and frame limit to transmit msg2 according to response window + uint8_t slot_limit = (rach_slot + slot_window)%nr_slots_per_frame_mac[mu]; + //uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1); + + + // go to previous slot if the current scheduled slot is beyond the response window + // and if the slot is not among the PDCCH monitored ones (38.213 10.1) + while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame_mac[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) { + if((*msg2_slot%tdd_period_slot) > 0) + (*msg2_slot)--; + else + AssertFatal(1==0,"No available DL slot to schedule msg2 has been found"); + } +} + + +void nr_initiate_ra_proc(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t slotP, + uint16_t preamble_index, + uint8_t freq_index, + uint8_t symbol, + int16_t timing_offset){ + + uint8_t ul_carrier_id = 0; // 0 for NUL 1 for SUL + NR_SearchSpace_t *ss; + int UE_id = 0; + // ra_rnti from 5.1.3 in 38.321 + uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8); + + uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset; + gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &nr_mac->UE_list; + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + NR_RA_t *ra = &cc->ra[0]; + + // if the preamble received correspond to one of the listed + // the UE sent a RACH either for starting RA procedure or RA procedure failed and UE retries + int pr_found=0; + for (int i=0;ipreambles[UE_id].num_preambles;i++) { + if (preamble_index == UE_list->preambles[UE_id].preamble_list[i]) { + pr_found=1; + break; + } + } + if (pr_found) + UE_list->fiveG_connected[UE_id] = false; + else { + LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: preamble %d does not correspond to any of the ones in rach_ConfigDedicated for UE_id %d\n", + module_idP, preamble_index, UE_id); + return; // if the PRACH preamble does not correspond to any of the ones sent through RRC abort RA proc + } + + // This should be handled differently when we use the initialBWP for RA + ra->bwp_id=1; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); + + LOG_I(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Slot %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); + + if (ra->state == RA_IDLE) { + int loop = 0; + LOG_D(MAC, "Frame %d, Slot %d: Activating RA process \n", frameP, slotP); + ra->state = Msg2; + ra->timing_offset = timing_offset; + ra->preamble_slot = slotP; + + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + AssertFatal(commonSearchSpaceList->list.count>0, + "common SearchSpace list has 0 elements\n"); + // Common searchspace list + for (int i=0;ilist.count;i++) { + ss=commonSearchSpaceList->list.array[i]; + if(ss->searchSpaceId == *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace) + ra->ra_ss=ss; + } + + // retrieving ra pdcch monitoring period and offset + find_monitoring_periodicity_offset_common(ra->ra_ss, + &monitoring_slot_period, + &monitoring_offset); + + nr_schedule_msg2(frameP, slotP, &msg2_frame, &msg2_slot, scc, monitoring_slot_period, monitoring_offset); + + ra->Msg2_frame = msg2_frame; + ra->Msg2_slot = msg2_slot; + + LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP); + + do { + ra->rnti = (taus() % 65518) + 1; + loop++; + } + while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 65519)); + if (loop == 100) { + LOG_E(MAC,"%s:%d:%s: [RAPROC] initialisation random access aborted\n", __FILE__, __LINE__, __FUNCTION__); + abort(); + } + + ra->RA_rnti = ra_rnti; + ra->preamble_index = preamble_index; + UE_list->tc_rnti[UE_id] = ra->rnti; + + LOG_I(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x\n", + module_idP, + CC_id, + frameP, + ra->Msg2_frame, + ra->Msg2_slot, + ra->RA_rnti); + + return; + } + LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: CC_id %d Frame %d initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, preamble_index); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0); +} + +void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ + + //uint8_t i = 0; + int CC_id = 0; + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_RA_t *ra = &cc->ra[0]; start_meas(&mac->schedule_ra); + //for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { + LOG_D(MAC,"RA[state:%d]\n",ra->state); + switch (ra->state){ + case Msg2: + nr_generate_Msg2(module_idP, CC_id, frameP, slotP); + break; + case Msg4: + //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); + break; + case WAIT_Msg4_ACK: + //check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + break; + default: + break; + } + //} + stop_meas(&mac->schedule_ra); +} - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { +void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, + NR_BWP_Uplink_t *ubwp, + sub_frame_t current_slot, + frame_t current_frame, + NR_RA_t *ra) { - for (i = 0; i < NB_RA_PROC_MAX; i++) { + // msg3 is schedulend in mixed slot in the following TDD period + // for now we consider a TBS of 18 bytes - ra = (RA_t *) & cc[CC_id].ra[i]; - //LOG_D(MAC,"RA[state:%d]\n",ra->state); + int mu = ubwp->bwp_Common->genericParameters.subcarrierSpacing; + int StartSymbolIndex, NrOfSymbols, startSymbolAndLength, temp_slot; + ra->Msg3_tda_id = 16; // initialization to a value above limit - if (ra->state == MSG2) - generate_Msg2(module_idP, CC_id, frameP, subframeP, ra); - else if (ra->state == MSG4) - generate_Msg4(module_idP, CC_id, frameP, subframeP, ra); - else if (ra->state == WAITMSG4ACK) - check_Msg4_retransmission(module_idP, CC_id, frameP, subframeP, ra); + for (int i=0; ibwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; i++) { + startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength, &StartSymbolIndex, &NrOfSymbols); + // we want to transmit in the uplink symbols of mixed slot + if (NrOfSymbols == scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols) { + ra->Msg3_tda_id = i; + break; + } + } + AssertFatal(ra->Msg3_tda_id<16,"Unable to find Msg3 time domain allocation in list\n"); - } // for i=0 .. N_RA_PROC-1 - } // CC_id + uint8_t k2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2; - stop_meas(&mac->schedule_ra); + temp_slot = current_slot + k2 + DELTA[mu]; // msg3 slot according to 8.3 in 38.213 + ra->Msg3_slot = temp_slot%nr_slots_per_frame_mac[mu]; + if (nr_slots_per_frame_mac[mu]>temp_slot) + ra->Msg3_frame = current_frame; + else + ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame_mac[mu]); + + ra->msg3_nb_rb = 18; + ra->msg3_first_rb = 0; +} + + +void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_RA_t *ra = &cc->ra[0]; + + if (ra->state == WAIT_Msg3) { + if ((frameP == ra->Msg3_frame) && (slotP == ra->Msg3_slot) ){ + ul_req->SFN = ra->Msg3_frame; + ul_req->Slot = ra->Msg3_slot; + ul_req->pdus_list[ul_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + ul_req->pdus_list[ul_req->n_pdus].pusch_pdu = ra->pusch_pdu; + ul_req->n_pdus+=1; + ra->state = RA_IDLE; + } + } +} + +void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ + + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + NR_RA_t *ra = &cc->ra[0]; + NR_UE_list_t *UE_list = &mac->UE_list; + int UE_id = 0; + + AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti); + + LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); + + nfapi_nr_pusch_pdu_t *pusch_pdu = &ra->pusch_pdu; + memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); + + + AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id); + + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1]; + LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", + frameP, + slotP, + ra->Msg3_frame, + ra->Msg3_slot, + ra->msg3_nb_rb, + ra->msg3_first_rb, + ra->msg3_round, + ra->rnti); + + int startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->startSymbolAndLength; + int start_symbol_index,nr_of_symbols; + SLIV2SL(startSymbolAndLength, &start_symbol_index, &nr_of_symbols); + + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + pusch_pdu->rnti = ra->rnti; + pusch_pdu->handle = 0; + int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); + int ibwp_start = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); + if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size)) + pusch_pdu->bwp_start = abwp_start; + else + pusch_pdu->bwp_start = ibwp_start; + pusch_pdu->bwp_size = ibwp_size; + pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing; + pusch_pdu->cyclic_prefix = 0; + pusch_pdu->mcs_index = 0; + pusch_pdu->mcs_table = 0; + pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); + pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) + pusch_pdu->transform_precoding = 1; + else + pusch_pdu->transform_precoding = 0; + pusch_pdu->data_scrambling_id = *scc->physCellId; + pusch_pdu->nrOfLayers = 1; + pusch_pdu->ul_dmrs_symb_pos = 1<dmrs_config_type = 0; + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. + pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. + pusch_pdu->dmrs_ports = 1; // 6.2.2 in 38.214 only port 0 to be used + pusch_pdu->num_dmrs_cdm_grps_no_data = 2; // no data in dmrs symbols as in 6.2.2 in 38.214 + pusch_pdu->resource_alloc = 1; //type 1 + pusch_pdu->rb_start = ra->msg3_first_rb + ibwp_start - abwp_start; // as for 6.3.1.7 in 38.211 + if (ra->msg3_nb_rb > pusch_pdu->bwp_size) + AssertFatal(1==0,"MSG3 allocated number of RBs exceed the BWP size\n"); + else + pusch_pdu->rb_size = ra->msg3_nb_rb; + pusch_pdu->vrb_to_prb_mapping = 0; + if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->frequencyHopping == NULL) + pusch_pdu->frequency_hopping = 0; + else + pusch_pdu->frequency_hopping = 1; + //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] + pusch_pdu->uplink_frequency_shift_7p5khz = 0; + //Resource Allocation in time domain + pusch_pdu->start_symbol_index = start_symbol_index; + pusch_pdu->nr_of_symbols = nr_of_symbols; + //Optional Data only included if indicated in pduBitmap + pusch_pdu->pusch_data.rv_index = 0; // 8.3 in 38.213 + pusch_pdu->pusch_data.harq_process_id = 0; + pusch_pdu->pusch_data.new_data_indicator = 1; // new data + pusch_pdu->pusch_data.num_cb = 0; + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, + pusch_pdu->target_code_rate, + pusch_pdu->rb_size, + pusch_pdu->nr_of_symbols, + 12, // nb dmrs set for no data in dmrs symbol + 0, //nb_rb_oh + 0, // to verify tb scaling + pusch_pdu->nrOfLayers = 1)>>3; + + // calling function to fill rar message + nr_fill_rar(module_idP, ra, cc->RAR_pdu.payload, pusch_pdu); + +} + +// WIP +// todo: +// - fix me +// - get msg3 alloc (see nr_process_rar) +void nr_generate_Msg2(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t slotP){ + + int UE_id = 0, dci_formats[2], rnti_types[2], mcsIndex; + int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment; + gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; + NR_RA_t *ra = &cc->ra[0]; + NR_UE_list_t *UE_list = &nr_mac->UE_list; + NR_SearchSpace_t *ss = ra->ra_ss; + + uint16_t RA_rnti = ra->RA_rnti; + long locationAndBandwidth; + // uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id; + + // check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD + // get the BW of the PDCCH for PDCCH size and RAR PDSCH size + + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + int dci10_bw; + + if (ra->coreset0_configured == 1) { + AssertFatal(1==0,"This is a standalone condition\n"); + } + else { // on configured BWP or initial LDBWP, bandwidth parameters in DCI correspond size of initialBWP + locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth; + dci10_bw = NRRIV2BW(locationAndBandwidth,275); + } + + if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) { + + nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; + nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; + + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); + + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); + + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + + // Checking if the DCI allocation is feasible in current subframe + if (dl_req->nPDUs == NFAPI_NR_MAX_DL_TTI_PDUS) { + LOG_I(MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, RA_rnti); + return; + } + + LOG_I(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state); + + // This code from this point on will not work on initialBWP or CORESET0 + AssertFatal(ra->bwp_id>0,"cannot work on initialBWP for now\n"); + + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id - 1]; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1]; + + LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW %d\n", dci10_bw); + + mcsIndex = 0; // Qm>2 not allowed for RAR + + pdsch_pdu_rel15->pduBitmap = 0; + pdsch_pdu_rel15->rnti = RA_rnti; + pdsch_pdu_rel15->pduIndex = 0; + + + pdsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; + pdsch_pdu_rel15->CyclicPrefix = 0; + pdsch_pdu_rel15->NrOfCodewords = 1; + pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0); + pdsch_pdu_rel15->qamModOrder[0] = 2; + pdsch_pdu_rel15->mcsIndex[0] = mcsIndex; + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == NULL) + pdsch_pdu_rel15->mcsTable[0] = 0; + else{ + if (*bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == 0) + pdsch_pdu_rel15->mcsTable[0] = 1; + else + pdsch_pdu_rel15->mcsTable[0] = 2; + } + pdsch_pdu_rel15->rvIndex[0] = 0; + pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; + pdsch_pdu_rel15->nrOfLayers = 1; + pdsch_pdu_rel15->transmissionScheme = 0; + pdsch_pdu_rel15->refPoint = 0; + pdsch_pdu_rel15->dmrsConfigType = 0; + pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId; + pdsch_pdu_rel15->SCID = 0; + pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 2; + pdsch_pdu_rel15->dmrsPorts = 1; + pdsch_pdu_rel15->resourceAlloc = 1; + pdsch_pdu_rel15->rbStart = 0; + pdsch_pdu_rel15->rbSize = 6; + pdsch_pdu_rel15->VRBtoPRBMapping = 0; // non interleaved + + for (int i=0; ibwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { + startSymbolAndLength = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength, &StartSymbolIndex_tmp, &NrOfSymbols_tmp); + if (NrOfSymbols_tmp < NrOfSymbols) { + NrOfSymbols = NrOfSymbols_tmp; + StartSymbolIndex = StartSymbolIndex_tmp; + time_domain_assignment = i; // this is short PDSCH added to the config to fit mixed slot + } + } + + AssertFatal(StartSymbolIndex >= 0, "StartSymbolIndex is negative\n"); + + pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex; + pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols; + pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols); + + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->rbStart,dci10_bw); + dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; + dci_pdu_rel15[0].vrb_to_prb_mapping.val = 0; + dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; + dci_pdu_rel15[0].tb_scaling = 0; + + LOG_I(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n", + dci_pdu_rel15[0].frequency_domain_assignment.val, + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + dci10_bw, + dci_pdu_rel15[0].time_domain_assignment.val, + dci_pdu_rel15[0].vrb_to_prb_mapping.val, + dci_pdu_rel15[0].mcs, + dci_pdu_rel15[0].tb_scaling); + + nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, RA_rnti, 0, ss, scc, bwp); + + LOG_I(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x\n", frameP, slotP, RA_rnti); + + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + rnti_types[0] = NR_RNTI_RA; + + LOG_D(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", + pdcch_pdu_rel15->dci_pdu.RNTI[0], + rnti_types[0], + dci_formats[0], + (unsigned long long)pdcch_pdu_rel15->FreqDomainResource, + pdcch_pdu_rel15->StartSymbolIndex, + pdcch_pdu_rel15->DurationSymbols); + + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw,ra->bwp_id); + + dl_req->nPDUs+=2; + + // Program UL processing for Msg3 + nr_get_Msg3alloc(scc, ubwp, slotP, frameP, ra); + LOG_I(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); + nr_add_msg3(module_idP, CC_id, frameP, slotP); + ra->state = WAIT_Msg3; + LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); + + x_Overhead = 0; + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_pdu_rel15[0].tb_scaling); + + // DL TX request + tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; + tx_req->PDU_index = nr_mac->pdu_index[CC_id]++; + tx_req->num_TLV = 1; + tx_req->TLVs[0].length = 8; + nr_mac->TX_req[CC_id].SFN = frameP; + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].Slot = slotP; + memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length); + } +} + +void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ + NR_RA_t *ra = &RC.nrmac[module_idP]->common_channels[CC_id].ra[0]; + LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra->rnti); + ra->state = IDLE; + ra->timing_offset = 0; + ra->RRC_timer = 20; + ra->rnti = 0; + ra->msg3_round = 0; +} + + +///////////////////////////////////// +// Random Access Response PDU // +// TS 38.213 ch 8.2 // +// TS 38.321 ch 6.2.3 // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//| E | T | R A P I D |// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// +//| R | T A |// +//| T A | UL grant |// +//| UL grant |// +//| UL grant |// +//| UL grant |// +//| T C - R N T I |// +//| T C - R N T I |// +///////////////////////////////////// +// UL grant (27 bits) // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//|-------------------|FHF|F_alloc|// +//| Freq allocation |// +//| F_alloc |Time allocation|// +//| MCS | TPC |CSI|// +///////////////////////////////////// +// WIP +// todo: +// - handle MAC RAR BI subheader +// - sending only 1 RAR subPDU +// - UL Grant: hardcoded CSI, TPC, time alloc +// - padding +void nr_fill_rar(uint8_t Mod_idP, + NR_RA_t * ra, + uint8_t * dlsch_buffer, + nfapi_nr_pusch_pdu_t *pusch_pdu){ + + LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); + NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; + NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); + unsigned char csi_req = 0, tpc_command; + //uint8_t N_UL_Hop; + uint8_t valid_bits; + uint32_t ul_grant; + uint16_t f_alloc, prb_alloc, bwp_size, truncation=0; + + tpc_command = 3; // this is 0 dB + + /// E/T/RAPID subheader /// + // E = 0, one only RAR, first and last + // T = 1, RAPID + rarh->E = 0; + rarh->T = 1; + rarh->RAPID = ra->preamble_index; + + /// RAR MAC payload /// + rar->R = 0; + + // TA command + rar->TA1 = (uint8_t) (ra->timing_offset >> 5); // 7 MSBs of timing advance + rar->TA2 = (uint8_t) (ra->timing_offset & 0x1f); // 5 LSBs of timing advance + + // TC-RNTI + rar->TCRNTI_1 = (uint8_t) (ra->rnti >> 8); // 8 MSBs of rnti + rar->TCRNTI_2 = (uint8_t) (ra->rnti & 0xff); // 8 LSBs of rnti + + // UL grant + + ra->msg3_TPC = tpc_command; + + bwp_size = pusch_pdu->bwp_size; + prb_alloc = PRBalloc_to_locationandbandwidth0(ra->msg3_nb_rb, ra->msg3_first_rb, bwp_size); + if (bwp_size>180) { + AssertFatal(1==0,"Initial UBWP larger than 180 currently not supported"); + } + else { + valid_bits = (uint8_t)ceil(log2(bwp_size*(bwp_size+1)>>1)); + } + + if (pusch_pdu->frequency_hopping){ + AssertFatal(1==0,"PUSCH with frequency hopping currently not supported"); + } else { + for (int i=0; imcs_index << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26); + + rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07; + rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff; + rar->UL_GRANT_3 = (uint8_t) (ul_grant >> 8) & 0xff; + rar->UL_GRANT_4 = (uint8_t) ul_grant & 0xff; + } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 2a36425fae..5fa77c6ca7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -31,9 +31,9 @@ */ #include "assertions.h" -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_gNB/nr_mac_gNB.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "UTIL/OPT/opt.h" diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 5233270149..cf2323f571 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -34,9 +34,9 @@ #include "PHY/defs_nr_common.h" #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" /*MAC*/ -#include "LAYER2/NR_MAC_COMMON/nr_mac.h" -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "NR_MAC_gNB/nr_mac_gNB.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/MAC/mac.h" /*NFAPI*/ @@ -44,6 +44,13 @@ /*TAG*/ #include "NR_TAG-Id.h" +//////////////////////////////////////////////////////// +/////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// +//////////////////////////////////////////////////////// +#define OCTET 8 +#define HALFWORD 16 +#define WORD 32 +//#define SIZE_OF_POINTER sizeof (void *) int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -53,20 +60,23 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdu_lcids, unsigned char drx_cmd, unsigned char *ue_cont_res_id, - unsigned short post_padding){ - + unsigned short post_padding) { gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; + unsigned char *dlsch_buffer_ptr = sdus_payload; uint8_t last_size = 0; int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - - // MAC CEs + // MAC CEs uint8_t mac_header_control_elements[16], *ce_ptr; ce_ptr = &mac_header_control_elements[0]; + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); - // 1) Compute MAC CE and related subheaders + // 1) Compute MAC CE and related subheaders // DRX command subheader (MAC CE size 0) if (drx_cmd != 255) { @@ -81,57 +91,216 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, // now TA is always send when ta_timer resets regardless of its value // this is done to avoid issues with the timeAlignmentTimer which is // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len){ + if (gNB->ta_len) { mac_pdu_ptr->R = 0; mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; //last_size = 1; mac_pdu_ptr++; - // TA MAC CE (1 octet) timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64,"timing_advance_cmd %d > 63\n", timing_advance_cmd); + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0){ - tag_id = gNB->tag->tag_Id; + + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; } LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); mac_ce_size = sizeof(NR_MAC_CE_TA); - // Copying bytes for MAC CEs to the mac pdu pointer memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); ce_ptr += mac_ce_size; mac_pdu_ptr += (unsigned char) mac_ce_size; } - // Contention resolution fixed subheader and MAC CE if (ue_cont_res_id) { mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; mac_pdu_ptr++; //last_size = 1; - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, // it contains the first 48 bits of the UL CCCH SDU LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); - + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); // Copying bytes (6 octects) to CEs pointer mac_ce_size = 6; memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - // Copying bytes for MAC CEs to mac pdu pointer memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); ce_ptr += mac_ce_size; mac_pdu_ptr += (unsigned char) mac_ce_size; } + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // 2) Generation of DLSCH MAC SDU subheaders + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); + } + + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } + + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; + + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); + } + + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, + ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); + } else { + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; + } + + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); + + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + } + } + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs for (i = 0; i < num_sdus; i++) { LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); @@ -151,31 +320,27 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, } mac_pdu_ptr += last_size; - - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr+= sdu_lengths[i]; + dlsch_buffer_ptr += sdu_lengths[i]; mac_pdu_ptr += sdu_lengths[i]; } // 4) Compute final offset for padding - if (post_padding > 0) { + if (post_padding > 0) { ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; mac_pdu_ptr++; - - } else { + } else { // no MAC subPDU with padding } // compute final offset offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ -void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ +void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 050f07ba67..8841083796 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -30,8 +30,8 @@ #include "nr_mac_gNB.h" #include "SCHED_NR/sched_nr.h" -#include "mac_proto.h" -#include "nr_mac_common.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_dci.h" #include "executables/nr-softmodem.h" @@ -250,25 +250,26 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, } - - - int configure_fapi_dl_pdu(int Mod_idP, - int *CCEIndex, nfapi_nr_dl_tti_request_body_t *dl_req, - NR_sched_pucch *pucch_sched, + NR_sched_pucch *pucch_sched, uint8_t *mcsIndex, uint16_t *rbSize, uint16_t *rbStart) { + gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; NR_COMMON_channels_t *cc = nr_mac->common_channels; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu; nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; - int TBS, bwp_id = 1, UE_id = 0; + + int TBS; + int bwp_id=1; + int UE_id = 0; + NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; @@ -277,6 +278,9 @@ int configure_fapi_dl_pdu(int Mod_idP, secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); @@ -305,11 +309,12 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->NrOfCodewords = 1; int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9; + int current_harq_pid = UE_list->UE_sched_ctrl[UE_id].current_harq_pid; pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcs,0); pdsch_pdu_rel15->qamModOrder[0] = 2; pdsch_pdu_rel15->mcsIndex[0] = mcs; pdsch_pdu_rel15->mcsTable[0] = 0; - pdsch_pdu_rel15->rvIndex[0] = 0; + pdsch_pdu_rel15->rvIndex[0] = (get_softmodem_params()->phy_test==1) ? 0 : UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round; pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; pdsch_pdu_rel15->nrOfLayers = 1; pdsch_pdu_rel15->transmissionScheme = 0; @@ -324,7 +329,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0; pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize; pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP - // choose shortest PDSCH + int startSymbolAndLength=0; int time_domain_assignment=2; int StartSymbolIndex,NrOfSymbols; @@ -340,62 +345,104 @@ int configure_fapi_dl_pdu(int Mod_idP, scc->dmrs_TypeA_Position, pdsch_pdu_rel15->NrOfSymbols); - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t)); - dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, - pdsch_pdu_rel15->rbStart, - NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); - dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV; - dci_pdu_rel15[0].vrb_to_prb_mapping = 1; + // bwp indicator + int n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; + if (n_dl_bwp < 4) + dci_pdu_rel15[0].bwp_indicator.val = bwp_id; + else + dci_pdu_rel15[0].bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212 + // frequency domain assignment + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation==NR_PDSCH_Config__resourceAllocation_resourceAllocationType1) + dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->rbStart, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + else + AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); + // time domain assignment + dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; + // mcs and rv dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; - dci_pdu_rel15[0].tb_scaling = 1; - - dci_pdu_rel15[0].ra_preamble_index = 25; - dci_pdu_rel15[0].format_indicator = 1; - dci_pdu_rel15[0].ndi = 1; - dci_pdu_rel15[0].rv = 0; - dci_pdu_rel15[0].harq_pid = 0; - dci_pdu_rel15[0].dai = (pucch_sched->dai_c-1)&3; - dci_pdu_rel15[0].tpc = 2; + dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0]; + // harq pid and ndi + dci_pdu_rel15[0].harq_pid = current_harq_pid; + dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi; + // DAI + dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; + + // TPC for PUCCH + dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213 + // PUCCH resource indicator dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator; - dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = pucch_sched->timing_indicator; - + // PDSCH to HARQ TI + dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator; + UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].feedback_slot = pucch_sched->ul_slot; + UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].is_waiting = 1; + // antenna ports + dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 + // dmrs sequence initialization + dci_pdu_rel15[0].dmrs_sequence_initialization.val = pdsch_pdu_rel15->SCID; LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", - dci_pdu_rel15[0].frequency_domain_assignment, + dci_pdu_rel15[0].frequency_domain_assignment.val, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), - dci_pdu_rel15[0].time_domain_assignment, - dci_pdu_rel15[0].vrb_to_prb_mapping, + dci_pdu_rel15[0].time_domain_assignment.val, + dci_pdu_rel15[0].vrb_to_prb_mapping.val, dci_pdu_rel15[0].mcs, dci_pdu_rel15[0].tb_scaling, dci_pdu_rel15[0].ndi, dci_pdu_rel15[0].rv); - - nr_configure_pdcch(pdcch_pdu_rel15, - 1, // ue-specific - scc, - bwp); - - pdcch_pdu_rel15->numDlDci = 1; - pdcch_pdu_rel15->AggregationLevel[0] = 4; - pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0]; - pdcch_pdu_rel15->CceIndex[0] = CCEIndex[0]; - pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0; - pdcch_pdu_rel15->powerControlOffsetSS[0]=1; - + + NR_SearchSpace_t *ss; + int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + + int found=0; + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (ss->searchSpaceType->present == target_ss) { + found=1; + break; + } + } + AssertFatal(found==1,"Couldn't find an adequate searchspace\n"); + + int ret = nr_configure_pdcch(nr_mac, + pdcch_pdu_rel15, + UE_list->rnti[UE_id], + 1, // ue-specific + ss, + scc, + bwp); + if (ret < 0) { + LOG_I(MAC,"CCE list not empty, couldn't schedule PDSCH\n"); + free(dci_pdu_rel15); + return (0); + } + int dci_formats[2]; int rnti_types[2]; - dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats) + dci_formats[0] = NR_DL_DCI_FORMAT_1_1; + else + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + rnti_types[0] = NR_RNTI_C; - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pdsch_pdu_rel15->BWPSize,bwp_id); - LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ + LOG_D(MAC, "DCI params: rnti %x, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", - pdcch_pdu_rel15->RNTI[0], + pdcch_pdu_rel15->dci_pdu.RNTI[0], rnti_types[0], dci_formats[0], (unsigned long long)pdcch_pdu_rel15->FreqDomainResource, @@ -403,7 +450,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdcch_pdu_rel15->DurationSymbols); int x_Overhead = 0; // should be 0 for initialBWP - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu,x_Overhead,pdsch_pdu_rel15->numDmrsCdmGrpsNoData,0); // Hardcode it for now TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; @@ -417,38 +464,84 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->NrOfCodewords, pdsch_pdu_rel15->mcsIndex[0], TBS); + + free(dci_pdu_rel15); return TBS; //Return TBS in bytes } -void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) { +void config_uldci(NR_BWP_Uplink_t *ubwp, + nfapi_nr_pusch_pdu_t *pusch_pdu, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, int *rnti_types, + int time_domain_assignment, + int n_ubwp, int bwp_id) { - dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, - pusch_pdu->rb_start, - NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + switch(dci_formats[(pdcch_pdu_rel15->numDlDci)-1]) { + case NR_UL_DCI_FORMAT_0_0: + dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, + pusch_pdu->rb_start, + NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + + dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment; + dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; + dci_pdu_rel15->mcs = 9; + + dci_pdu_rel15->format_indicator = 0; + dci_pdu_rel15->ndi = 1; + dci_pdu_rel15->rv = 0; + dci_pdu_rel15->harq_pid = 0; + dci_pdu_rel15->tpc = 2; + break; + case NR_UL_DCI_FORMAT_0_1: + dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator; + dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index; + dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id; + dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; + dci_pdu_rel15->dai[0].val = 0; //TODO + // bwp indicator + if (n_ubwp < 4) + dci_pdu_rel15->bwp_indicator.val = bwp_id; + else + dci_pdu_rel15->bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212 + // frequency domain assignment + if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1) + dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, + pusch_pdu->rb_start, + NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + else + AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); + // time domain assignment + dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment; + // mcs + dci_pdu_rel15->mcs = pusch_pdu->mcs_index; + // tpc command for pusch + dci_pdu_rel15->tpc = 2; //TODO + // SRS resource indicator + if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig != NULL) { + if (*ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig == NR_PUSCH_Config__txConfig_codebook) + dci_pdu_rel15->srs_resource_indicator.val = 0; // taking resource 0 for SRS + else + AssertFatal(1==0,"Non Codebook configuration non supported\n"); + } + // Antenna Ports + dci_pdu_rel15->antenna_ports.val = 0; // TODO for now it is hardcoded, it should depends on cdm group no data and rank + // DMRS sequence initialization + dci_pdu_rel15->dmrs_sequence_initialization.val = pusch_pdu->scid; + break; + default : + AssertFatal(1==0,"Valid UL formats are 0_0 and 0_1 \n"); + } - dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV; - dci_pdu_rel15->frequency_hopping_flag = 0; - dci_pdu_rel15->mcs = 9; - - dci_pdu_rel15->format_indicator = 0; - dci_pdu_rel15->ndi = 1; - dci_pdu_rel15->rv = 0; - dci_pdu_rel15->harq_pid = 0; - dci_pdu_rel15->tpc = 2; - LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", - pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], - dci_pdu_rel15->frequency_domain_assignment, - dci_pdu_rel15->time_domain_assignment, - dci_pdu_rel15->frequency_hopping_flag, + pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci], + dci_pdu_rel15->frequency_domain_assignment.val, + dci_pdu_rel15->time_domain_assignment.val, + dci_pdu_rel15->frequency_hopping_flag.val, dci_pdu_rel15->mcs, dci_pdu_rel15->tpc, dci_pdu_rel15->ndi, dci_pdu_rel15->rv); - - dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; - rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; - pdcch_pdu_rel15->numDlDci++; } @@ -484,7 +577,7 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP, tx_req->num_TLV = 1; tx_req->TLVs[0].length = tbs_bytes +2; - memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes);; + memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes); nr_mac->TX_req[CC_id].Number_of_PDUs++; nr_mac->TX_req[CC_id].SFN = frameP; @@ -497,11 +590,11 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, NR_sched_pucch *pucch_sched, nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){ - LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n"); + LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP); int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0; int lcid, offset, i, header_length_last, TBS_bytes; - int UE_id = 0, CCEIndex = -1, CC_id = 0; + int UE_id = 0, CC_id = 0; gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; //NR_COMMON_channels_t *cc = nr_mac->common_channels; @@ -525,27 +618,15 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ta_len = gNB_mac->ta_len; - CCEIndex = allocate_nr_CCEs(gNB_mac, - 1, // bwp_id - 0, // coreset_id - 4, // aggregation, - 1, // search_space, 0 common, 1 ue-specific - UE_id, - 0); // m - - if (CCEIndex == -1) return; - - AssertFatal(CCEIndex>0,"CCEIndex is negative\n"); - int CCEIndices[2]; - CCEIndices[0] = CCEIndex; - TBS_bytes = configure_fapi_dl_pdu(module_idP, - CCEIndices, dl_req, - pucch_sched, + pucch_sched, dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL, dlsch_config!=NULL ? &dlsch_config->rbSize : NULL, dlsch_config!=NULL ? &dlsch_config->rbStart : NULL); + + if (TBS_bytes == 0) + return; //The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving //through the LTE stack @@ -603,22 +684,23 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, break; } } + } //if (IS_SOFTMODEM_NOS1) else { //When the --NOS1 option is not enabled, DLSCH transmissions with random data //occur every time that the current function is called (dlsch phytest mode) + LOG_D(MAC,"Configuring DL_TX in %d.%d\n", frameP, slotP); // fill dlsch_buffer with random data for (i = 0; i < TBS_bytes; i++){ - //mac_sdus[i] = (unsigned char) rand(); - ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); + mac_sdus[i] = (unsigned char) (lrand48()&0xff); + //((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); } - //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths - sdu_lcids[0] = 0x05; // DRB + sdu_lcids[0] = 0x3f; // DRB sdu_lengths[0] = TBS_bytes - ta_len - 3; header_length_total += 2 + (sdu_lengths[0] >= 128); sdu_length_total += sdu_lengths[0]; @@ -652,7 +734,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, offset = nr_generate_dlsch_pdu(module_idP, (unsigned char *) mac_sdus, - (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], //(unsigned char *) mac_pdu, + (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], num_sdus, //num_sdus sdu_lengths, sdu_lcids, @@ -701,7 +783,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; int bwp_id=1; - + int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing; int UE_id = 0; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id); @@ -711,10 +793,15 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count; NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_PUSCH_Config_t *pusch_Config = ubwp->bwp_Dedicated->pusch_Config->choice.setup; nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[Mod_idP]->UL_dci_req[0]; + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); uint16_t rnti = UE_list->rnti[UE_id]; nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu; @@ -729,20 +816,28 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, LOG_D(MAC, "Scheduling UE specific PUSCH\n"); //UL_tti_req = &nr_mac->UL_tti_req[CC_id]; - /* - // original configuration - rel15_ul->rnti = 0x1234; - rel15_ul->ulsch_pdu_rel15.start_rb = 30; - rel15_ul->ulsch_pdu_rel15.number_rbs = 50; - rel15_ul->ulsch_pdu_rel15.start_symbol = 2; - rel15_ul->ulsch_pdu_rel15.number_symbols = 12; - rel15_ul->ulsch_pdu_rel15.nb_re_dmrs = 6; - rel15_ul->ulsch_pdu_rel15.length_dmrs = 1; - rel15_ul->ulsch_pdu_rel15.Qm = 2; - rel15_ul->ulsch_pdu_rel15.mcs = 9; - rel15_ul->ulsch_pdu_rel15.rv = 0; - rel15_ul->ulsch_pdu_rel15.n_layers = 1; - */ + + //Resource Allocation in time domain + int startSymbolAndLength=0; + int time_domain_assignment=1; + int StartSymbolIndex,NrOfSymbols,K2,mapping_type; + + AssertFatal(time_domain_assignmentbwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count, + "time_domain_assignment %d>=%d\n",time_domain_assignment,ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count); + startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols); + pusch_pdu->start_symbol_index = StartSymbolIndex; + pusch_pdu->nr_of_symbols = NrOfSymbols; + + mapping_type = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType; + if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2 != NULL) + K2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2; + else { + if (mu<2) K2=1; + else if(mu==2) K2=2; + else K2=3; + } + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; pusch_pdu->rnti = rnti; pusch_pdu->handle = 0; //not yet used @@ -757,65 +852,147 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->mcs_table = 0; //0: notqam256 [TS38.214, table 5.1.3.1-1] - corresponds to nr_target_code_rate_table1 in PHY pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; - pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.; + if (pusch_Config->transformPrecoder == NULL) { + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) + pusch_pdu->transform_precoding = 1; + else + pusch_pdu->transform_precoding = 0; + } + else + pusch_pdu->transform_precoding = *pusch_Config->transformPrecoder; + if (pusch_Config->dataScramblingIdentityPUSCH != NULL) + pusch_pdu->data_scrambling_id = *pusch_Config->dataScramblingIdentityPUSCH; + else + pusch_pdu->data_scrambling_id = *scc->physCellId; + pusch_pdu->nrOfLayers = 1; - pusch_pdu->resource_alloc = 1; //type 1 - //pusch_pdu->rb_bitmap;// for ressource alloc type 0 - pusch_pdu->rb_start = 0; - pusch_pdu->rb_size = 50; + + //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] + if (pusch_Config->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1) { + pusch_pdu->resource_alloc = 1; //type 1 + pusch_pdu->rb_start = 0; + pusch_pdu->rb_size = 50; + } + else + AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); + pusch_pdu->vrb_to_prb_mapping = 0; - pusch_pdu->frequency_hopping = 0; + + if (pusch_Config->frequencyHopping==NULL) + pusch_pdu->frequency_hopping = 0; + else + pusch_pdu->frequency_hopping = 1; + //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] - pusch_pdu->uplink_frequency_shift_7p5khz = 0; - //Resource Allocation in time domain - pusch_pdu->start_symbol_index = 2; - pusch_pdu->nr_of_symbols = 12; + //pusch_pdu->uplink_frequency_shift_7p5khz = 0; + // -------------------- // ------- DMRS ------- // -------------------- - uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); - pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index; - pusch_pdu->dmrs_config_type = 0; // dmrs-type 1 (the one with a single DMRS symbol in the beginning) - pusch_pdu->ul_dmrs_scrambling_id = 0; // If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id - pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1] - // Should match what is sent in DCI 0_1, otherwise set to 0 - //pusch_pdu->num_dmrs_cdm_grps_no_data; - //pusch_pdu->dmrs_ports; // DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports - // Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011, - // and for each bit 0: DMRS port not used 1: DMRS port used + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig; + if (mapping_type == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA) + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup; + else + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + if (NR_DMRS_UplinkConfig->dmrs_Type == NULL) + pusch_pdu->dmrs_config_type = 0; + else + pusch_pdu->dmrs_config_type = 1; + pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1] + if (pusch_pdu->transform_precoding) { // transform precoding disabled + long *scramblingid; + if (pusch_pdu->scid == 0) + scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0; + else + scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1; + if (scramblingid == NULL) + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; + else + pusch_pdu->ul_dmrs_scrambling_id = *scramblingid; + } + else { + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; + if (NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL) + pusch_pdu->pusch_identity = *NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity; + else + pusch_pdu->pusch_identity = *scc->physCellId; + } + pusch_dmrs_AdditionalPosition_t additional_pos; + if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL) + additional_pos = 2; + else { + if (*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos3) + additional_pos = 3; + else + additional_pos = *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition; + } + pusch_maxLength_t pusch_maxLength; + if (NR_DMRS_UplinkConfig->maxLength == NULL) + pusch_maxLength = 1; + else + pusch_maxLength = 2; + uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, mapping_type, additional_pos, pusch_maxLength); + pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index; + + pusch_pdu->num_dmrs_cdm_grps_no_data = 1; + pusch_pdu->dmrs_ports = 1; // -------------------------------------------------------------------------------------------------------------------------------------------- // -------------------- // ------- PTRS ------- // -------------------- - uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig - uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig - uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig - uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig - uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig - pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table); - pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size); - pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); - pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + if (NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) { + // TODO to be fixed from RRC config + uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig + uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig + uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig + uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig + uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig + pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table); + pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size); + pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); + pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + + pusch_pdu->pdu_bit_map &= PUSCH_PDU_BITMAP_PUSCH_PTRS; // enable PUSCH PTRS + } + else{ +// if(1<pusch_ptrs.ptrs_time_density >= pusch_pdu->nr_of_symbols) + pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + } - if(1<pusch_ptrs.ptrs_time_density >= pusch_pdu->nr_of_symbols) - pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS // -------------------------------------------------------------------------------------------------------------------------------------------- //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] //Optional Data only included if indicated in pduBitmap + // TODO from harq function as in pdsch pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; - pusch_pdu->pusch_data.new_data_indicator = 0; + pusch_pdu->pusch_data.new_data_indicator = 1; + + uint8_t num_dmrs_symb = 0; + + for(int dmrs_counter = pusch_pdu->start_symbol_index; dmrs_counter < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; dmrs_counter++) + num_dmrs_symb += ((pusch_pdu->ul_dmrs_symb_pos >> dmrs_counter) & 1); + + uint8_t N_PRB_DMRS; + if (pusch_pdu->dmrs_config_type == 0) { + N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*6; + } + else { + N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*4; + } + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, pusch_pdu->target_code_rate, pusch_pdu->rb_size, pusch_pdu->nr_of_symbols, - pusch_pdu->dmrs_config_type?4:6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + N_PRB_DMRS * num_dmrs_symb, 0, //nb_rb_oh + 0, pusch_pdu->nrOfLayers)>>3; + + pusch_pdu->pusch_data.num_cb = 0; //CBG not supported //pusch_pdu->pusch_data.cb_present_and_position; //pusch_pdu->pusch_uci; @@ -834,33 +1011,52 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, int dci_formats[2]; int rnti_types[2]; - int CCEIndex = allocate_nr_CCEs(nr_mac, - 1, // bwp_id - 0, // coreset_id - 4, // aggregation, - 1, // search_space, 0 common, 1 ue-specific - UE_id, - 0); // m + NR_SearchSpace_t *ss; + int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + + int found=0; + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (ss->searchSpaceType->present == target_ss) { + found=1; + break; + } + } + AssertFatal(found==1,"Couldn't find an adequate searchspace\n"); + + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats) + dci_formats[0] = NR_UL_DCI_FORMAT_0_1; + else + dci_formats[0] = NR_UL_DCI_FORMAT_0_0; - dci_formats[0] = NR_UL_DCI_FORMAT_0_0; rnti_types[0] = NR_RNTI_C; LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); - nr_configure_pdcch(pdcch_pdu_rel15, - 1, // ue-specific, - scc, - bwp); - - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; - AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); - pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; + int ret = nr_configure_pdcch(nr_mac, + pdcch_pdu_rel15, + UE_list->rnti[UE_id], + 1, // ue-specific, + ss, + scc, + bwp); - LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]); - - config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); - + if (ret < 0) { + LOG_I(MAC,"CCE list not empty, couldn't schedule PUSCH\n"); + UL_tti_req->n_pdus-=1; + return; + } + else { + dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t)); + config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,time_domain_assignment,n_ubwp,bwp_id); + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); + free(dci_pdu_rel15); + } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 6d3f69f217..acb239ee39 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -33,10 +33,10 @@ #include "assertions.h" #include "LAYER2/MAC/mac.h" -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_gNB/nr_mac_gNB.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "common/utils/nr/nr_common.h" @@ -68,8 +68,6 @@ extern RAN_CONTEXT_t RC; -extern int n_active_slices; - // Note the 2 scs values in the table names represent resp. scs_common and pdcch_scs /// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config) uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_15[15] = {2,2,2,3,3,3,1,1,2,2,3,3,1,2,3}; @@ -131,12 +129,11 @@ static inline uint8_t get_max_cces(uint8_t scs) { int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, - int coreset_id, + int list_id, int aggregation, int search_space, // 0 common, 1 ue-specific int UE_id, - int m - ) { + int m) { // uncomment these when we allocate for common search space // NR_COMMON_channels_t *cc = nr_mac->common_channels; // NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; @@ -148,19 +145,20 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, NR_ControlResourceSet_t *coreset; + AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id); + secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + if (search_space == 1) { - AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id); - secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; - bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; - coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[coreset_id]; + coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[list_id]; } else { - AssertFatal(1==0,"Add code for common search space\n"); + coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; } + int coreset_id = coreset->controlResourceSetId; int *cce_list = nr_mac->cce_list[bwp_id][coreset_id]; - int n_rb=0; for (int i=0;i<6;i++) for (int j=0;j<8;j++) { @@ -182,7 +180,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, } int first_cce = aggregation * (( Y + (m*N_cce)/(aggregation*M_s_max) + n_CI ) % CEILIDIV(N_cce,aggregation)); - for (int i=0;iconfig_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL, - "controlResourceSetToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0, - "controlResourceSetToAddModList is empty\n"); - NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; - + NR_ControlResourceSet_t *temp_coreset; + NR_ControlResourceSetId_t coresetid = *ss->controlResourceSetId; + if (ss_type == 0) { // common search space + if (coresetid == 0){ + AssertFatal(1==0,"coreset0 currently not supported\n"); + } + else { + coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; + AssertFatal(coresetid==coreset->controlResourceSetId,"ID of common ss coreset does not correspond to id set in the search space\n"); + } + } + else { + int n_list = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count; + for (int i=0; ibwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[i]; + if (coresetid==temp_coreset->controlResourceSetId) { + coreset = temp_coreset; + cid = i; + break; + } + } + if(coreset==NULL) + AssertFatal(1==0,"Couldn't find coreset with id %ld\n",coresetid); + } pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix; + + // first symbol + //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); + int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + + AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - pdcch_pdu->DurationSymbols = coreset0->duration; + // for SPS=14 8 MSBs in positions 13 downto 6 + uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | + (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + + for (int i=0; i>(sps-1-i))&1) { + pdcch_pdu->StartSymbolIndex=i; + break; + } + } + + pdcch_pdu->DurationSymbols = coreset->duration; - //frequencyDomainResources - /* uint8_t count=0, start=0, start_set=0; - // find coreset descriptor - - uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)| - (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)| - (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)| - (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)| - (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)| - (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3); - - for (int i=0; i<45; i++) - if ((bitmap>>(44-i))&1) { - count++; - if (!start_set) { - start = i; - start_set = 1; - } - } - pdcch_pdu->rb_offset = 6*start; - pdcch_pdu->n_rb = 6*count; - */ for (int i=0;i<6;i++) - pdcch_pdu->FreqDomainResource[i] = coreset0->frequencyDomainResources.buf[i]; - //duration - + pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i]; + //cce-REG-MappingType - pdcch_pdu->CceRegMappingType = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? + pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; + if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - pdcch_pdu->RegBundleSize = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize); - pdcch_pdu->InterleaverSize = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize); + pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize); + pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize); AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n"); - pdcch_pdu->ShiftIndex = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; + pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; } else { pdcch_pdu->RegBundleSize = 0; @@ -478,67 +493,46 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, pdcch_pdu->CoreSetType = 1; //precoderGranularity - pdcch_pdu->precoderGranularity = coreset0->precoderGranularity; - - //TCI states - // - /* - //TCI present - if (coreset0->tci_PresentInDCI != NULL) { - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); - for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { - - } - */ - - for (int i=0;inumDlDci;i++) { - //pdcch-DMRS-ScramblingID - AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); - pdcch_pdu->ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; - } - - /// SearchSpace - - // first symbol - //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); - int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; - - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, - "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss=NULL; - int found=0; - int target_ss = NR_SearchSpace__searchSpaceType_PR_common; - if (ss_type == 1) { - target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - } - - for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { - ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; - AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); - AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); - if (*ss->controlResourceSetId == coreset0->controlResourceSetId && - ss->searchSpaceType->present == target_ss) { - found=1; - break; - } - } - AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - - // for SPS=14 8 MSBs in positions 13 downto 6, - uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | - (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); - - for (int i=0; i>(sps-1-i))&1) { - pdcch_pdu->StartSymbolIndex=i; - break; - } - } + pdcch_pdu->precoderGranularity = coreset->precoderGranularity; + pdcch_pdu->dci_pdu.RNTI[pdcch_pdu->numDlDci]=rnti; + + if (coreset->pdcch_DMRS_ScramblingID != NULL && + ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) { + pdcch_pdu->dci_pdu.ScramblingId[pdcch_pdu->numDlDci] = *coreset->pdcch_DMRS_ScramblingID; + pdcch_pdu->dci_pdu.ScramblingRNTI[pdcch_pdu->numDlDci]=rnti; + } + else { + pdcch_pdu->dci_pdu.ScramblingId[pdcch_pdu->numDlDci] = *scc->physCellId; + pdcch_pdu->dci_pdu.ScramblingRNTI[pdcch_pdu->numDlDci]=0; + } + + uint8_t nr_of_candidates,aggregation_level; + find_aggregation_candidates(&aggregation_level, + &nr_of_candidates, + ss); + + CCEIndex = allocate_nr_CCEs(nr_mac, + 1, // bwp_id + cid, + aggregation_level, + ss->searchSpaceType->present-1, // search_space, 0 common, 1 ue-specific + 0, // UE-id + 0); // m + + if (CCEIndex<0) + return (CCEIndex); + + pdcch_pdu->dci_pdu.AggregationLevel[pdcch_pdu->numDlDci] = aggregation_level; + pdcch_pdu->dci_pdu.CceIndex[pdcch_pdu->numDlDci] = CCEIndex; + + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats==NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) + pdcch_pdu->dci_pdu.beta_PDCCH_1_0[pdcch_pdu->numDlDci]=0; + + pdcch_pdu->dci_pdu.powerControlOffsetSS[pdcch_pdu->numDlDci]=1; + pdcch_pdu->numDlDci++; + return (0); + } else { // this is for InitialBWP AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n"); } @@ -730,21 +724,102 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, } +void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu_rel15, + nr_dci_format_t format, + int bwp_id) { + + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + + switch(format) { + case NR_UL_DCI_FORMAT_0_1: + // format indicator + dci_pdu_rel15->format_indicator = 0; + // carrier indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) + AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n"); + // supplementary uplink + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink != NULL) + AssertFatal(1==0,"Supplementary Uplink currently not supported\n"); + // SRS request + dci_pdu_rel15->srs_request.val = 0; + dci_pdu_rel15->ulsch_indicator = 1; + break; + case NR_DL_DCI_FORMAT_1_1: + // format indicator + dci_pdu_rel15->format_indicator = 1; + // carrier indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) + AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n"); + //vrb to prb mapping + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver==NULL) + dci_pdu_rel15->vrb_to_prb_mapping.val = 0; + else + dci_pdu_rel15->vrb_to_prb_mapping.val = 1; + //bundling size indicator + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling) + AssertFatal(1==0,"Dynamic PRB bundling type currently not supported\n"); + //rate matching indicator + uint16_t msb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1==NULL)?0:1; + uint16_t lsb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2==NULL)?0:1; + dci_pdu_rel15->rate_matching_indicator.val = lsb | (msb<<1); + // aperiodic ZP CSI-RS trigger + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL) + AssertFatal(1==0,"Aperiodic ZP CSI-RS currently not supported\n"); + // transmission configuration indication + if (bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI != NULL) + AssertFatal(1==0,"TCI in DCI currently not supported\n"); + //srs resource set + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching!=NULL) { + NR_SRS_CarrierSwitching_t *cs = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching->choice.setup; + if (cs->srs_TPC_PDCCH_Group!=NULL){ + switch(cs->srs_TPC_PDCCH_Group->present) { + case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_NOTHING: + dci_pdu_rel15->srs_request.val = 0; + break; + case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeA: + AssertFatal(1==0,"SRS TPC PRCCH group type A currently not supported\n"); + break; + case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeB: + AssertFatal(1==0,"SRS TPC PRCCH group type B currently not supported\n"); + break; + } + } + else + dci_pdu_rel15->srs_request.val = 0; + } + else + dci_pdu_rel15->srs_request.val = 0; + // CBGTI and CBGFI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) + AssertFatal(1==0,"CBG transmission currently not supported\n"); + break; + default : + AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 and 0_1 \n"); + } +} + + +void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, + int *rnti_types, + int N_RB, + int bwp_id) { -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, - dci_pdu_rel15_t *dci_pdu_rel15, - int *dci_formats, - int *rnti_types) { - - uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; for (int d=0;dnumDlDci;d++) { - uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; - AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); + uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d]; + int dci_size = nr_dci_size(scc,secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],N_RB,bwp_id); + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = dci_size; + AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); - int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; + if(dci_formats[d]==NR_DL_DCI_FORMAT_1_1 || dci_formats[d]==NR_UL_DCI_FORMAT_0_1) + prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id); /// Payload generation switch(dci_formats[d]) { @@ -754,25 +829,29 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos=fsize; - *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu); // Time domain assignment pos+=4; - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); - LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos)); + LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu); // VRB to PRB mapping pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos); - LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&0x1)<<(dci_size-pos); + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu); // MCS pos+=5; *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); - LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); +#ifdef DEBUG_FILL_DCI + LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); +#endif // TB scaling pos+=2; *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); - LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); +#ifdef DEBUG_FILL_DCI + LOG_I(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); +#endif break; case NR_RNTI_C: @@ -785,13 +864,13 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment (275rb >> fsize = 16) fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos+=fsize; - *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<frequency_domain_assignment.val&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); uint16_t is_ra = 1; for (int i=0; ifrequency_domain_assignment>>i)&1)) { + if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) { is_ra = 0; break; } @@ -803,7 +882,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // UL/SUL indicator 1 bit pos++; - *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos); + *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos); // SS/PBCH index 6 bits pos+=6; @@ -820,13 +899,13 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Time domain assignment 4bit pos+=4; - *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); - LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos)); + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu); // VRB to PRB mapping 1bit pos++; - *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); - LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos); + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu); // MCS 5bit //bit over 32, so dci_pdu ++ pos+=5; @@ -850,8 +929,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Downlink assignment index 2bit pos+=2; - *dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos)); - LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->dai[0].val&3)<<(dci_size-pos)); + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu); // TPC command for scheduled PUCCH 2bit pos+=2; @@ -865,8 +944,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // PDSCH-to-HARQ_feedback timing indicator 3bit pos+=3; - *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos)); - LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&0x7)<<(dci_size-pos)); + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu); } //end else break; @@ -882,12 +961,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4 bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -903,12 +982,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4 bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -924,12 +1003,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4 bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -944,7 +1023,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Downlink assignment index – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val>>(1-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUCCH – 2 bits for (int i=0; i<2; i++) @@ -957,7 +1036,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // PDSCH-to-HARQ_feedback timing indicator – 3 bits for (int i=0; i<3; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val>>(2-i))&1)<<(dci_size-pos++); break; } @@ -972,12 +1051,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -1001,7 +1080,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // UL/SUL indicator – 1 bit /* commented for now (RK): need to get this from BWP descriptor if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++); */ break; @@ -1012,12 +1091,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -1042,12 +1121,223 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, /* commented for now (RK): need to get this information from BWP descriptor if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++); */ break; } break; + + case NR_UL_DCI_FORMAT_0_1: + switch(rnti_types[d]) + { + case NR_RNTI_C: + // Indicating a DL DCI format 1bit + pos=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos); + + // Carrier indicator + pos+=dci_pdu_rel15->carrier_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<carrier_indicator.nbits)-1))<<(dci_size-pos); + + // UL/SUL Indicator + pos+=dci_pdu_rel15->ul_sul_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&((1<ul_sul_indicator.nbits)-1))<<(dci_size-pos); + + // BWP indicator + pos+=dci_pdu_rel15->bwp_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<bwp_indicator.nbits)-1))<<(dci_size-pos); + + // Frequency domain resource assignment + pos+=dci_pdu_rel15->frequency_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<frequency_domain_assignment.nbits)-1)) << (dci_size-pos); + + // Time domain resource assignment + pos+=dci_pdu_rel15->time_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<time_domain_assignment.nbits)-1)) << (dci_size-pos); + + // Frequency hopping + pos+=dci_pdu_rel15->frequency_hopping_flag.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&((1<frequency_hopping_flag.nbits)-1)) << (dci_size-pos); + + // MCS 5bit + pos+=5; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + + // New data indicator 1bit + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos); + + // Redundancy version 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + + // HARQ process number 4bit + pos+=4; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); + + // 1st Downlink assignment index + pos+=dci_pdu_rel15->dai[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<dai[0].nbits)-1))<<(dci_size-pos); + + // 2nd Downlink assignment index + pos+=dci_pdu_rel15->dai[1].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[1].val&((1<dai[1].nbits)-1))<<(dci_size-pos); + + // TPC command for scheduled PUSCH 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); + + // SRS resource indicator + pos+=dci_pdu_rel15->srs_resource_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_resource_indicator.val&((1<srs_resource_indicator.nbits)-1))<<(dci_size-pos); + + // Precoding info and n. of layers + pos+=dci_pdu_rel15->precoding_information.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->precoding_information.val&((1<precoding_information.nbits)-1))<<(dci_size-pos); + + // Antenna ports + pos+=dci_pdu_rel15->antenna_ports.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<antenna_ports.nbits)-1))<<(dci_size-pos); + + // SRS request + pos+=dci_pdu_rel15->srs_request.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<srs_request.nbits)-1))<<(dci_size-pos); + + // CSI request + pos+=dci_pdu_rel15->csi_request.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->csi_request.val&((1<csi_request.nbits)-1))<<(dci_size-pos); + + // CBG transmission information + pos+=dci_pdu_rel15->cbgti.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<cbgti.nbits)-1))<<(dci_size-pos); + + // PTRS DMRS association + pos+=dci_pdu_rel15->ptrs_dmrs_association.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ptrs_dmrs_association.val&((1<ptrs_dmrs_association.nbits)-1))<<(dci_size-pos); + + // Beta offset indicator + pos+=dci_pdu_rel15->beta_offset_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->beta_offset_indicator.val&((1<beta_offset_indicator.nbits)-1))<<(dci_size-pos); + + // DMRS sequence initialization + pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos); + + // UL-SCH indicator + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ulsch_indicator&0x1)<<(dci_size-pos); + + break; + } + break; + + case NR_DL_DCI_FORMAT_1_1: + // Indicating a DL DCI format 1bit + pos=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos); + + // Carrier indicator + pos+=dci_pdu_rel15->carrier_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<carrier_indicator.nbits)-1))<<(dci_size-pos); + + // BWP indicator + pos+=dci_pdu_rel15->bwp_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<bwp_indicator.nbits)-1))<<(dci_size-pos); + + // Frequency domain resource assignment + pos+=dci_pdu_rel15->frequency_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<frequency_domain_assignment.nbits)-1)) << (dci_size-pos); + + // Time domain resource assignment + pos+=dci_pdu_rel15->time_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<time_domain_assignment.nbits)-1)) << (dci_size-pos); + + // VRB-to-PRB mapping + pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&((1<vrb_to_prb_mapping.nbits)-1))<<(dci_size-pos); + + // PRB bundling size indicator + pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator.val&((1<prb_bundling_size_indicator.nbits)-1))<<(dci_size-pos); + + // Rate matching indicator + pos+=dci_pdu_rel15->rate_matching_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator.val&((1<rate_matching_indicator.nbits)-1))<<(dci_size-pos); + + // ZP CSI-RS trigger + pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger.val&((1<zp_csi_rs_trigger.nbits)-1)) << (dci_size-pos); + + //TB1 + // MCS 5bit + pos+=5; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + + // New data indicator 1bit + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos); + + // Redundancy version 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + + //TB2 + // MCS 5bit + pos+=dci_pdu_rel15->mcs2.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs2.val&((1<mcs2.nbits)-1))<<(dci_size-pos); + + // New data indicator 1bit + pos+=dci_pdu_rel15->ndi2.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi2.val&((1<ndi2.nbits)-1))<<(dci_size-pos); + + // Redundancy version 2bit + pos+=dci_pdu_rel15->rv2.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val&((1<rv2.nbits)-1))<<(dci_size-pos); + + // HARQ process number 4bit + pos+=4; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); + + // Downlink assignment index + pos+=dci_pdu_rel15->dai[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<dai[0].nbits)-1))<<(dci_size-pos); + + // TPC command for scheduled PUCCH 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); + + // PUCCH resource indicator 3bit + pos+=3; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos); + + // PDSCH-to-HARQ_feedback timing indicator + pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&((1<pdsch_to_harq_feedback_timing_indicator.nbits)-1))<<(dci_size-pos); + + // Antenna ports + pos+=dci_pdu_rel15->antenna_ports.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<antenna_ports.nbits)-1))<<(dci_size-pos); + + // TCI + pos+=dci_pdu_rel15->transmission_configuration_indication.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication.val&((1<transmission_configuration_indication.nbits)-1))<<(dci_size-pos); + + // SRS request + pos+=dci_pdu_rel15->srs_request.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<srs_request.nbits)-1))<<(dci_size-pos); + + // CBG transmission information + pos+=dci_pdu_rel15->cbgti.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<cbgti.nbits)-1))<<(dci_size-pos); + + // CBG flushing out information + pos+=dci_pdu_rel15->cbgfi.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<cbgfi.nbits)-1))<<(dci_size-pos); + + // DMRS sequence init + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&0x1)<<(dci_size-pos); } } } @@ -1089,7 +1379,6 @@ int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot) { } - int extract_startSymbol(int startSymbolAndLength) { int tmp = startSymbolAndLength/14; int tmp2 = startSymbolAndLength%14; @@ -1153,6 +1442,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ int UE_id; int i; NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; + NR_COMMON_channels_t *cc = RC.nrmac[mod_idP]->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + int num_slots_ul = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols>0) + num_slots_ul++; LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n", mod_idP, rntiP, @@ -1171,6 +1465,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ memset((void *) &UE_list->UE_sched_ctrl[UE_id], 0, sizeof(NR_UE_sched_ctrl_t)); + UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch)); LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n", mod_idP, UE_id, @@ -1187,7 +1482,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ return -1; } - void get_pdsch_to_harq_feedback(int Mod_idP, int UE_id, NR_SearchSpace__searchSpaceType_PR ss_type, @@ -1207,48 +1501,51 @@ void get_pdsch_to_harq_feedback(int Mod_idP, pdsch_to_harq_feedback[i] = i+1; } else { + // searching for a ue specific search space int found=0; - + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); if (ss->searchSpaceType->present == ss_type) { - found=1; - break; + found=1; + break; } } AssertFatal(found==1,"Couldn't find a ue specific searchspace\n"); + + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats == NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) { for (int i=0; i<8; i++) pdsch_to_harq_feedback[i] = i+1; } else { - if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) - pdsch_to_harq_feedback = (uint8_t *)ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK; + if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) { + for (int i=0; i<8; i++) + pdsch_to_harq_feedback[i] = *ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[i]; + } else - AssertFatal(found==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n"); + AssertFatal(0==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n"); } } } - // function to update pucch scheduling parameters in UE list when a USS DL is scheduled void nr_update_pucch_scheduling(int Mod_idP, int UE_id, frame_t frameP, sub_frame_t slotP, int slots_per_tdd, - NR_sched_pucch *sched_pucch) { + int *pucch_id) { NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; - int first_ul_slot_tdd,k; NR_sched_pucch *curr_pucch; + int first_ul_slot_tdd,k,i; uint8_t pdsch_to_harq_feedback[8]; int found = 0; - int i = 0; int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; @@ -1257,98 +1554,59 @@ void nr_update_pucch_scheduling(int Mod_idP, NR_SearchSpace__searchSpaceType_PR ss_type = NR_SearchSpace__searchSpaceType_PR_ue_Specific; get_pdsch_to_harq_feedback(Mod_idP,UE_id,ss_type,pdsch_to_harq_feedback); - // if the list of pucch to be scheduled is empty - if (UE_list->UE_sched_ctrl[UE_id].sched_pucch == NULL) { - sched_pucch->frame = frameP; - sched_pucch->next_sched_pucch = NULL; - sched_pucch->dai_c = 1; - sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - if ( nr_ulmix_slots > 0 ) { + // for each possible ul or mixed slot + for (k=0; kUE_sched_ctrl[UE_id].sched_pucch[k]; + // if there is free room in current pucch structure + if (curr_pucch->dai_cframe = frameP; + curr_pucch->dai_c++; + curr_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource // first pucch occasion in first UL or MIXED slot first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; - for (k=0; kul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; - } - else - AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n"); - } - else - AssertFatal(1==0,"No Uplink Slots in this Frame\n"); - - UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; - } - else { // to be tested - curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - if (curr_pucch->dai_cul_slot % slots_per_tdd)-(slotP % slots_per_tdd)) + i = 0; + while (i<8 && found == 0) { // look if timing indicator is among allowed values + if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd)) found = 1; if (found == 0) i++; } - if (found == 1) { // scheduling this harq-ack in current pucch - sched_pucch = curr_pucch; - sched_pucch->dai_c = 1 + sched_pucch->dai_c; - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; - } - } - if (curr_pucch->dai_c==MAX_ACK_BITS || found == 0) { // if current pucch is full or no timing indicator allowed - // look for pucch occasions in other UL of mixed slots - for (k=scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; kul_slot % slots_per_tdd)) { // skip current scheduled slot (already checked) - i = 0; - while (i<8 && found == 0) { // look if timing indicator is among allowed values - if (pdsch_to_harq_feedback[i]==k-(slotP % slots_per_tdd)) - found = 1; - if (found == 0) i++; - } - if (found == 1) { - if (k<(curr_pucch->ul_slot % slots_per_tdd)) { // we need to add a pucch occasion before current pucch - sched_pucch->frame = frameP; - sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); - sched_pucch->next_sched_pucch = curr_pucch; - sched_pucch->dai_c = 1; - sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; - UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; - } - else { - while (curr_pucch->next_sched_pucch != NULL && k!=(curr_pucch->ul_slot % slots_per_tdd)) - curr_pucch = curr_pucch->next_sched_pucch; - if (curr_pucch == NULL) { // creating a new item in the list - sched_pucch->frame = frameP; - sched_pucch->next_sched_pucch = NULL; - sched_pucch->dai_c = 1; - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; - sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); - curr_pucch->next_sched_pucch = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); - curr_pucch->next_sched_pucch = sched_pucch; - } - else { - if (curr_pucch->dai_c==MAX_ACK_BITS) - found = 0; // if pucch at index k is already full we have to find a new one in a following occasion - else { // scheduling this harq-ack in current pucch - sched_pucch = curr_pucch; - sched_pucch->dai_c = 1 + sched_pucch->dai_c; - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; - } - } - } - } - } + if (found == 1) { + // computing slot in which pucch is scheduled + curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); + curr_pucch->timing_indicator = i; // index in the list of timing indicators + *pucch_id = k; + return; } } } + AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n"); +} + + +void find_aggregation_candidates(uint8_t *aggregation_level, + uint8_t *nr_of_candidates, + NR_SearchSpace_t *ss) { + + if (ss->nrofCandidates->aggregationLevel1 != NR_SearchSpace__nrofCandidates__aggregationLevel1_n0) { + *aggregation_level = 1; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel1; + } + if (ss->nrofCandidates->aggregationLevel2 != NR_SearchSpace__nrofCandidates__aggregationLevel2_n0) { + *aggregation_level = 2; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel2; + } + if (ss->nrofCandidates->aggregationLevel4 != NR_SearchSpace__nrofCandidates__aggregationLevel4_n0) { + *aggregation_level = 4; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel4; + } + if (ss->nrofCandidates->aggregationLevel8 != NR_SearchSpace__nrofCandidates__aggregationLevel8_n0) { + *aggregation_level = 8; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel8; + } + if (ss->nrofCandidates->aggregationLevel16 != NR_SearchSpace__nrofCandidates__aggregationLevel16_n0) { + *aggregation_level = 16; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel16; + } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index eb8d338949..89c3fe69fe 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -28,10 +28,12 @@ * @ingroup _mac */ + #include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "executables/softmodem-common.h" //#define ENABLE_MAC_PAYLOAD_DEBUG 1 + void nr_process_mac_pdu( module_id_t module_idP, uint8_t CC_id, @@ -87,7 +89,13 @@ void nr_process_mac_pdu( /*#ifdef DEBUG_HEADER_PARSING LOG_D(MAC, "[UE] LCID %d, PDU length %d\n", ((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID, pdu_len); #endif*/ - + case UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY: + // 38.321 Ch6.1.3.20 + mac_ce_len = 2; + break; + case UL_SCH_LCID_CONFIGURED_GRANT_CONFIRMATION: + // 38.321 Ch6.1.3.7 + break; case UL_SCH_LCID_S_BSR: //38.321 section 6.1.3.1 //fixed length @@ -170,6 +178,24 @@ void nr_process_mac_pdu( // end of MAC PDU, can ignore the rest. break; + // MAC SDUs + case UL_SCH_LCID_SRB1: + // todo + break; + case UL_SCH_LCID_SRB2: + // todo + break; + case UL_SCH_LCID_SRB3: + // todo + break; + case UL_SCH_LCID_CCCH_MSG3: + // todo + break; + case UL_SCH_LCID_CCCH: + // todo + mac_subheader_len = 2; + break; + case UL_SCH_LCID_DTCH: // check if LCID is valid at current time. if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){ @@ -183,7 +209,7 @@ void nr_process_mac_pdu( mac_subheader_len = 2; } - LOG_D(MAC, "[UE %d] Frame %d : DLSCH -> DL-DTCH %d (gNB %d, %d bytes)\n", module_idP, frameP, rx_lcid, module_idP, mac_sdu_len); + LOG_D(MAC, "[UE %d] Frame %d : ULSCH -> UL-DTCH %d (gNB %d, %d bytes)\n", module_idP, frameP, rx_lcid, module_idP, mac_sdu_len); #if defined(ENABLE_MAC_PAYLOAD_DEBUG) LOG_T(MAC, "[UE %d] First 32 bytes of DLSCH : \n", module_idP); @@ -223,13 +249,12 @@ void nr_process_mac_pdu( pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len ); if (pdu_len < 0) { - LOG_E(MAC, "%s() residual mac pdu length < 0!\n", __func__); + LOG_E(MAC, "%s() residual mac pdu length < 0!, pdu_len: %d\n", __func__, pdu_len); return; } } } - /* * When data are received on PHY and transmitted to MAC */ @@ -276,9 +301,25 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, #endif if (sduP != NULL){ - //UE_scheduling_control->ta_update = timing_advance; + UE_scheduling_control->ta_update = timing_advance; LOG_D(MAC, "Received PDU at MAC gNB \n"); nr_process_mac_pdu(gnb_mod_idP, CC_idP, frameP, sduP, sdu_lenP); } } + else { + // random access pusch with TC-RNTI + if (sduP != NULL) { // if the CRC passed + for (int i = 0; i < MAX_MOBILES_PER_GNB; i++) { + if (UE_list->active[i] == TRUE) { + if (UE_list->tc_rnti[i] == current_rnti) { + // for now the only thing we are doing is set the UE as 5G connected + UE_list->fiveG_connected[i] = true; + LOG_I(MAC, "[gNB %d][RAPROC] PUSCH with TC_RNTI %x received correctly and UE_id %d is now 5G connected\n", + gnb_mod_idP, current_rnti, i); + } + } + } + } + } } + diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index c0f4053c03..74c6841a3a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -31,8 +31,9 @@ #ifndef __LAYER2_NR_MAC_PROTO_H__ #define __LAYER2_NR_MAC_PROTO_H__ -#include "nr_mac_gNB.h" #include "PHY/defs_gNB.h" + +#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" #include "NR_TAG-Id.h" #define MAX_ACK_BITS 2 //only format 0 is available for now @@ -78,19 +79,66 @@ void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slo void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP); +/////// Random Access MAC-PHY interface functions and primitives /////// + +void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); + +/* \brief Function to indicate a received preamble on PRACH. It initiates the RA procedure. +@param module_idP Instance ID of gNB +@param preamble_index index of the received RA request +@param slotP Slot number on which to act +@param timing_offset Offset in samples of the received PRACH w.r.t. eNB timing. This is used to +@param rnti RA rnti corresponding to this PRACH preamble +@param rach_resource type (0=non BL/CE,1 CE level 0,2 CE level 1, 3 CE level 2,4 CE level 3) +*/ +void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, + uint16_t preamble_index, uint8_t freq_index, uint8_t symbol, int16_t timing_offset); + +void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); + +int nr_allocate_CCEs(int module_idP, int CC_idP, frame_t frameP, sub_frame_t slotP, int test_only); + +void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, + NR_BWP_Uplink_t *ubwp, + sub_frame_t current_subframe, + frame_t current_frame, + NR_RA_t *ra); + +/* \brief Function in gNB to fill RAR pdu when requested by PHY. +@param ra Instance of RA resources of gNB +@param dlsch_buffer Pointer to RAR input buffer +@param N_RB_UL Number of UL resource blocks +*/ +void nr_fill_rar(uint8_t Mod_idP, + NR_RA_t * ra, + uint8_t * dlsch_buffer, + nfapi_nr_pusch_pdu_t *pusch_pdu); + + +void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); + +uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs); + +/////// Phy test scheduler /////// + void nr_schedule_css_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP); int configure_fapi_dl_pdu(int Mod_id, - int *CCEIndeces, nfapi_nr_dl_tti_request_body_t *dl_req, NR_sched_pucch *pucch_sched, uint8_t *mcsIndex, uint16_t *rbSize, uint16_t *rbStart); -void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types); +void config_uldci(NR_BWP_Uplink_t *ubwp, + nfapi_nr_pusch_pdu_t *pusch_pdu, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, int *rnti_types, + int time_domain_assignment, + int n_ubwp, int bwp_id); void configure_fapi_dl_Tx(module_id_t Mod_idP, frame_t frameP, @@ -115,7 +163,7 @@ void nr_update_pucch_scheduling(int Mod_idP, frame_t frameP, sub_frame_t slotP, int slots_per_tdd, - NR_sched_pucch *sched_pucch); + int *pucch_id); void get_pdsch_to_harq_feedback(int Mod_idP, int UE_id, @@ -140,6 +188,7 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, uint16_t slot, nfapi_nr_config_request_scf_t cfg); */ + void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, NR_ServingCellConfigCommon_t *scc, NR_BWP_Uplink_t *bwp, @@ -147,23 +196,45 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, uint16_t O_uci, uint16_t O_ack, uint8_t SR_flag); -void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, - int ss_type, - NR_ServingCellConfigCommon_t *scc, - NR_BWP_Downlink_t *bwp); -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, +void find_search_space(int ss_type, + NR_BWP_Downlink_t *bwp, + NR_SearchSpace_t *ss); + +int nr_configure_pdcch(gNB_MAC_INST *nr_mac, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, + uint16_t rnti, + int ss_type, + NR_SearchSpace_t *ss, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Downlink_t *bwp); + +void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, - int *rnti_types); + int *rnti_types, + int N_RB, + int bwp_id); + +void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu_rel15, + nr_dci_format_t format, + int bwp_id); + +void find_aggregation_candidates(uint8_t *aggregation_level, + uint8_t *nr_of_candidates, + NR_SearchSpace_t *ss); + int get_spf(nfapi_nr_config_request_scf_t *cfg); int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); -void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); - void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, - int x_overhead); + int x_overhead, + uint8_t numdmrscdmgroupnodata, + uint8_t tb_scaling); /** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); @@ -182,17 +253,6 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP); int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); -int get_num_dmrs(uint16_t dmrs_mask ); -uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position); -int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength); - -uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table); -uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB); - -uint16_t nr_dci_size(nr_dci_format_t format, - nr_rnti_type_t rnti_type, - uint16_t N_RB); - int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, int coreset_id, @@ -202,9 +262,6 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int m ); -int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); -int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); - int get_dlscs(nfapi_nr_config_request_t *cfg); int get_ulscs(nfapi_nr_config_request_t *cfg); @@ -224,6 +281,14 @@ void config_nr_mib(int Mod_idP, int intraFreqReselection); +void nr_generate_Msg2(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t slotP); + +void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP); + + void nr_process_mac_pdu( module_id_t module_idP, uint8_t CC_id, @@ -231,6 +296,9 @@ void nr_process_mac_pdu( uint8_t *pduP, uint16_t mac_pdu_len); +int binomial(int n, int k); + + /* \brief Function to indicate a received SDU on ULSCH. @param Mod_id Instance ID of gNB @param CC_id Component carrier index diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c index 9e8415776b..56e020838d 100644 --- a/openair2/LAYER2/NR_MAC_gNB/main.c +++ b/openair2/LAYER2/NR_MAC_gNB/main.c @@ -30,8 +30,8 @@ */ -#include "mac_proto.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "assertions.h" #include "LAYER2/PDCP_v10.1.0/pdcp.h" @@ -113,6 +113,11 @@ void mac_top_init_gNB(void) UE_list->next[list_el] = list_el + 1; UE_list->next_ul[list_el] = list_el + 1; UE_list->active[list_el] = FALSE; + for (int list_harq = 0; list_harq < NR_MAX_NB_HARQ_PROCESSES; list_harq++) { + UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].round = 0; + UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].ndi = 0; + UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].is_waiting = 0; + } } UE_list->next[list_el] = -1; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c index e4e3ac05df..df23b64e07 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c +++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c @@ -39,6 +39,7 @@ uint32_t nr_compute_tbs(uint16_t Qm, uint16_t nb_symb_sch, uint16_t nb_dmrs_prb, uint16_t nb_rb_oh, + uint8_t tb_scaling, uint8_t Nl) { @@ -54,7 +55,7 @@ uint32_t nr_compute_tbs(uint16_t Qm, scale = (R>1024)?11:10; // Intermediate number of information bits - Ninfo = (nb_re * R * Qm * Nl)>>scale; + Ninfo = ((nb_re * R * Qm * Nl)>>scale)>>tb_scaling; if (Ninfo <=3824) { n = max(3, floor(log2(Ninfo)) - 6); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h deleted file mode 100644 index 6b043963b0..0000000000 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*! \file mac.h -* \brief MAC data structures, constant, and function prototype -* \author Navid Nikaein and Raymond Knopp, WIE-TAI CHEN -* \date Dec. 2019 -* \version 0.1 -* \company Eurecom -* \email raymond.knopp@eurecom.fr - -*/ - -#ifndef __LAYER2_NR_MAC_COMMON_H__ -#define __LAYER2_NR_MAC_COMMON_H__ - -uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); - -uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); - -uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); - -int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols); - -typedef enum { - NR_DL_DCI_FORMAT_1_0 = 0, - NR_DL_DCI_FORMAT_1_1, - NR_DL_DCI_FORMAT_2_0, - NR_DL_DCI_FORMAT_2_1, - NR_DL_DCI_FORMAT_2_2, - NR_DL_DCI_FORMAT_2_3, - NR_UL_DCI_FORMAT_0_0, - NR_UL_DCI_FORMAT_0_1 -} nr_dci_format_t; - -typedef enum { - NR_RNTI_new = 0, - NR_RNTI_C, - NR_RNTI_RA, - NR_RNTI_P, - NR_RNTI_CS, - NR_RNTI_TC, - NR_RNTI_SP_CSI, - NR_RNTI_SI, - NR_RNTI_SFI, - NR_RNTI_INT, - NR_RNTI_TPC_PUSCH, - NR_RNTI_TPC_PUCCH, - NR_RNTI_TPC_SRS -} nr_rnti_type_t; - -#endif diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index bf9358dd43..f84e7a900c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -42,30 +42,106 @@ #include #include +/* Commmon */ +#include "targets/ARCH/COMMON/common_lib.h" +#include "COMMON/platform_constants.h" +#include "common/ran_context.h" + +/* RRC */ #include "NR_BCCH-BCH-Message.h" #include "NR_CellGroupConfig.h" #include "NR_ServingCellConfigCommon.h" #include "NR_MeasConfig.h" +/* PHY */ +#include "PHY/defs_gNB.h" +#include "PHY/TOOLS/time_meas.h" + +/* Interface */ #include "nfapi_nr_interface_scf.h" #include "NR_PHY_INTERFACE/NR_IF_Module.h" -#include "COMMON/platform_constants.h" -#include "common/ran_context.h" +/* MAC */ #include "LAYER2/MAC/mac.h" #include "LAYER2/MAC/mac_proto.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" -#include "PHY/defs_gNB.h" -#include "PHY/TOOLS/time_meas.h" -#include "targets/ARCH/COMMON/common_lib.h" - -#include "nr_mac_common.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" +#include "NR_TAG.h" +/* Defs */ #define MAX_NUM_BWP 2 #define MAX_NUM_CORESET 2 #define MAX_NUM_CCE 90 +/*!\brief Maximum number of random access process */ +#define NR_NB_RA_PROC_MAX 4 -#include "NR_TAG.h" +typedef enum { + RA_IDLE = 0, + Msg2 = 1, + WAIT_Msg3 = 2, + Msg4 = 3, + WAIT_Msg4_ACK = 4 +} RA_gNB_state_t; + +/*! \brief gNB template for the Random access information */ +typedef struct { + /// Flag to indicate this process is active + RA_gNB_state_t state; + /// BWP id of RA process + int bwp_id; + /// CORESET0 configured flag + int coreset0_configured; + /// Slot where preamble was received + uint8_t preamble_slot; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_slot; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_slot; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Msg3 time domain allocation index + uint8_t Msg3_tda_id; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_slot; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// Msg3 pusch pdu + nfapi_nr_pusch_pdu_t pusch_pdu; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; +} NR_RA_t; /*! \brief gNB common channels */ typedef struct { @@ -73,6 +149,7 @@ typedef struct { int p_gNB; int Ncp; int nr_band; + lte_frame_type_t frame_type; uint64_t dl_CarrierFreq; NR_BCCH_BCH_Message_t *mib; NR_ServingCellConfigCommon_t *ServingCellConfigCommon; @@ -93,7 +170,7 @@ typedef struct { /// Outgoing RAR pdu for PHY RAR_PDU RAR_pdu; /// Template for RA computations - RA_t ra[NB_RA_PROC_MAX]; + NR_RA_t ra[NR_NB_RA_PROC_MAX]; /// VRB map for common channels uint8_t vrb_map[100]; /// VRB map for common channels and retransmissions by PHICH @@ -102,15 +179,87 @@ typedef struct { uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +typedef struct sp_zp_csirs { + bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled + bool act_deact; //Activation/Deactivation indication + uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies + uint8_t bwpid; //Downlink BWP id + uint8_t rsc_id; //SP ZP CSI-RS resource set +} sp_zp_csirs_t; + +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +#define MAX_CSI_RESOURCE_SET 64 +typedef struct csi_rs_im { + bool is_scheduled; + bool act_deact; + uint8_t serv_cellid; + uint8_t bwp_id; + bool im; + uint8_t csi_im_rsc_id; + uint8_t nzp_csi_rsc_id; + uint8_t nb_tci_resource_set_id; + uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; +} csi_rs_im_t; + +typedef struct pdcchStateInd { + bool is_scheduled; + uint8_t servingCellId; + uint8_t coresetId; + uint8_t tciStateId; +} pdcchStateInd_t; + +typedef struct SPCSIReportingpucch { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + bool s0tos3_actDeact[4]; +} SPCSIReportingpucch_t; + +#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 +typedef struct aperiodicCSI_triggerStateSelection { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTriggerStateSelected; + bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; +} aperiodicCSI_triggerStateSelection_t; + +#define MAX_TCI_STATES 128 //38.331 +typedef struct pdschTciStatesActDeact { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTciStateActivated; + bool tciStateActDeact[MAX_TCI_STATES]; +} pdschTciStatesActDeact_t; + +typedef struct UE_info { + sp_zp_csirs_t sp_zp_csi_rs; + csi_rs_im_t csi_im; + pdcchStateInd_t pdcch_state_ind; + SPCSIReportingpucch_t SP_CSI_reporting_pucch; + aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; + pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; +} NR_UE_mac_ce_ctrl_t; + + typedef struct NR_sched_pucch { int frame; int ul_slot; uint8_t dai_c; uint8_t timing_indicator; uint8_t resource_indicator; - struct NR_sched_pucch *next_sched_pucch; } NR_sched_pucch; +typedef struct NR_UE_harq { + uint8_t is_waiting; + uint8_t ndi; + uint8_t round; + uint16_t feedback_slot; +} NR_UE_harq_t; + /*! \brief scheduling control information set through an API */ typedef struct { uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch @@ -118,11 +267,19 @@ typedef struct { NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; + uint8_t current_harq_pid; + NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES]; + int dummy; + NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information } NR_UE_sched_ctrl_t; -/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ -typedef struct { +typedef struct NR_preamble_ue { + uint8_t num_preambles; + uint8_t *preamble_list; +} NR_preamble_ue; +/*! \brief UE list used by gNB to order UEs/CC for scheduling*/ +typedef struct { DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; /// scheduling control info NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; @@ -133,11 +290,14 @@ typedef struct { int avail; int num_UEs; boolean_t active[MAX_MOBILES_PER_GNB]; + boolean_t fiveG_connected[MAX_MOBILES_PER_GNB]; rnti_t rnti[MAX_MOBILES_PER_GNB]; + rnti_t tc_rnti[MAX_MOBILES_PER_GNB]; + NR_preamble_ue preambles[MAX_MOBILES_PER_GNB]; NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; -/*! \brief top level gNB MAC structure */ +/*! \brief top level eNB MAC structure */ typedef struct gNB_MAC_INST_s { /// Ethernet parameters for northbound midhaul interface eth_params_t eth_params_n; @@ -178,7 +338,7 @@ typedef struct gNB_MAC_INST_s { /// UL handle uint32_t ul_handle; - // MAC function execution peformance profiler + // MAC function execution peformance profiler /// processing time of eNB scheduler time_stats_t eNB_scheduler; /// processing time of eNB scheduler for SI @@ -203,66 +363,4 @@ typedef struct gNB_MAC_INST_s { int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; -typedef struct { - uint8_t format_indicator; //1 bit - uint16_t frequency_domain_assignment; //up to 16 bits - uint8_t time_domain_assignment; // 4 bits - uint8_t frequency_hopping_flag; //1 bit - - uint8_t ra_preamble_index; //6 bits - uint8_t ss_pbch_index; //6 bits - uint8_t prach_mask_index; //4 bits - - uint8_t vrb_to_prb_mapping; //0 or 1 bit - uint8_t mcs; //5 bits - uint8_t ndi; //1 bit - uint8_t rv; //2 bits - uint8_t harq_pid; //4 bits - uint8_t dai; //0, 2 or 4 bits - uint8_t dai1; //1 or 2 bits - uint8_t dai2; //0 or 2 bits - uint8_t tpc; //2 bits - uint8_t pucch_resource_indicator; //3 bits - uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - - uint8_t short_messages_indicator; //2 bits - uint8_t short_messages; //8 bits - uint8_t tb_scaling; //2 bits - - uint8_t carrier_indicator; //0 or 3 bits - uint8_t bwp_indicator; //0, 1 or 2 bits - uint8_t prb_bundling_size_indicator; //0 or 1 bits - uint8_t rate_matching_indicator; //0, 1 or 2 bits - uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits - uint8_t transmission_configuration_indication; //0 or 3 bits - uint8_t srs_request; //2 bits - uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits - uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit - uint8_t dmrs_sequence_initialization; //0 or 1 bit - - uint8_t srs_resource_indicator; - uint8_t precoding_information; - uint8_t csi_request; - uint8_t ptrs_dmrs_association; - uint8_t beta_offset_indicator; //0 or 2 bits - - uint8_t slot_format_indicator_count; - uint8_t *slot_format_indicators; - - uint8_t pre_emption_indication_count; - uint16_t *pre_emption_indications; //14 bit - - uint8_t block_number_count; - uint8_t *block_numbers; - - uint8_t ul_sul_indicator; //0 or 1 bit - uint8_t antenna_ports; - - uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits - uint16_t padding; - -} dci_pdu_rel15_t; - - - #endif /*__LAYER2_NR_MAC_GNB_H__ */ diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c index b0e6143de1..3667af2698 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c @@ -503,8 +503,6 @@ pdcp_data_ind( //----------------------------------------------------------------------------- { pdcp_t *pdcp_p = NULL; - list_t *sdu_list_p = NULL; - mem_block_t *new_sdu_p = NULL; uint8_t pdcp_header_len = 0; uint8_t pdcp_tailer_len = 0; pdcp_sn_t sequence_number = 0; @@ -576,7 +574,6 @@ pdcp_data_ind( } } - sdu_list_p = &pdcp_sdu_list; if (sdu_buffer_sizeP == 0) { LOG_W(PDCP, "SDU buffer size is zero! Ignoring this chunk!\n"); @@ -974,9 +971,8 @@ pdcp_data_ind( #endif if (FALSE == packet_forwarded) { - new_sdu_p = get_free_mem_block(sdu_buffer_sizeP - payload_offset + sizeof (pdcp_data_ind_header_t), __func__); + notifiedFIFO_elt_t * new_sdu_p = newNotifiedFIFO_elt(sdu_buffer_sizeP - payload_offset + sizeof (pdcp_data_ind_header_t), 0, NULL, NULL); - if (new_sdu_p) { if ((MBMS_flagP == 0) && (pdcp_p->rlc_mode == RLC_MODE_AM)) { pdcp_p->last_submitted_pdcp_rx_sn = sequence_number; } @@ -984,14 +980,15 @@ pdcp_data_ind( /* * Prepend PDCP indication header which is going to be removed at pdcp_fifo_flush_sdus() */ - memset(new_sdu_p->data, 0, sizeof (pdcp_data_ind_header_t)); - ((pdcp_data_ind_header_t *) new_sdu_p->data)->data_size = sdu_buffer_sizeP - payload_offset; + pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(new_sdu_p); + memset(pdcpHead, 0, sizeof (pdcp_data_ind_header_t)); + pdcpHead->data_size = sdu_buffer_sizeP - payload_offset; AssertFatal((sdu_buffer_sizeP - payload_offset >= 0), "invalid PDCP SDU size!"); // Here there is no virtualization possible // set ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst for IP layer here if (ctxt_pP->enb_flag == ENB_FLAG_NO) { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->rb_id = rb_id; + pdcpHead->rb_id = rb_id; if (EPC_MODE_ENABLED) { /* for the UE compiled in S1 mode, we need 1 here @@ -1002,45 +999,40 @@ pdcp_data_ind( #ifdef UESIM_EXPANSION if (UE_NAS_USE_TUN) { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->inst = ctxt_pP->module_id; } else { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = 0; + pdcpHead->inst = 0; } #else - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->inst = ctxt_pP->module_id; #endif } else { // nfapi_mode if (UE_NAS_USE_TUN) { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->inst = ctxt_pP->module_id; } else { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = 1; + pdcpHead->inst = 1; } } // nfapi_mode } } else { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->rb_id = rb_id + (ctxt_pP->module_id * LTE_maxDRB); - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->rb_id = rb_id + (ctxt_pP->module_id * LTE_maxDRB); + pdcpHead->inst = ctxt_pP->module_id; } if( LOG_DEBUGFLAG(DEBUG_PDCP) ) { static uint32_t pdcp_inst = 0; - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = pdcp_inst++; - LOG_D(PDCP, "inst=%d size=%d\n", ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst, ((pdcp_data_ind_header_t *) new_sdu_p->data)->data_size); + pdcpHead->inst = pdcp_inst++; + LOG_D(PDCP, "inst=%d size=%d\n", pdcpHead->inst, pdcpHead->data_size); } - memcpy(&new_sdu_p->data[sizeof (pdcp_data_ind_header_t)], + memcpy(pdcpHead+1, &sdu_buffer_pP->data[payload_offset], sdu_buffer_sizeP - payload_offset); - - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PDCP, "Printing first bytes of PDCP SDU before adding it to the list: \n"); - for (int i=0; i<30; i++){ - LOG_I(PDCP, "%x", sdu_buffer_pP->data[i]); - } - #endif - list_add_tail_eurecom (new_sdu_p, sdu_list_p); - } + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpHead+1, min(sdu_buffer_sizeP - payload_offset,30) , LOG_DUMP_CHAR, + "Printing first bytes of PDCP SDU before adding it to the list: \n"); + pushNotifiedFIFO(&pdcp_sdu_list, new_sdu_p); /* Print octets of incoming data in hexadecimal form */ LOG_D(PDCP, "Following content has been received from RLC (%d,%d)(PDCP header has already been removed):\n", @@ -2390,7 +2382,7 @@ void nr_ip_over_LTE_DRB_preconfiguration(void){ // 1 + drb_identiy_index; DRB_config->drb_Identity = 1; DRB_config->logicalChannelIdentity = CALLOC(1, sizeof(long)); - *(DRB_config->logicalChannelIdentity) = DRB_config->drb_Identity + 2; //(long) (ue_context_pP->ue_context.e_rab[i].param.e_rab_id + 2); // value : x+2 + *(DRB_config->logicalChannelIdentity) = DRB_config->drb_Identity + 3; //(long) (ue_context_pP->ue_context.e_rab[i].param.e_rab_id + 2); // value : x+2 DRB_rlc_config = CALLOC(1, sizeof(*DRB_rlc_config)); DRB_config->rlc_Config = DRB_rlc_config; @@ -2467,7 +2459,7 @@ void pdcp_layer_init(void) /* * Initialize SDU list */ - list_init(&pdcp_sdu_list, NULL); + initNotifiedFIFO(&pdcp_sdu_list); pdcp_coll_p = hashtable_create ((LTE_maxDRB + 2) * NUMBER_OF_UE_MAX, NULL, pdcp_free); AssertFatal(pdcp_coll_p != NULL, "UNRECOVERABLE error, PDCP hashtable_create failed"); @@ -2540,7 +2532,8 @@ void pdcp_layer_init(void) void pdcp_layer_cleanup (void) //----------------------------------------------------------------------------- { - list_free (&pdcp_sdu_list); + //list_free (&pdcp_sdu_list); + while(pollNotifiedFIFO(&pdcp_sdu_list)) {}; hashtable_destroy(&pdcp_coll_p); #ifdef MBMS_MULTICAST_OUT diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h index e9ac85866c..de8a1b385b 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h @@ -34,10 +34,6 @@ #ifndef __PDCP_H__ # define __PDCP_H__ //----------------------------------------------------------------------------- -#ifndef NON_ACCESS_STRATUM - #include "UTIL/MEM/mem_block.h" - #include "UTIL/LISTS/list.h" -#endif //NON_ACCESS_STRATUM //----------------------------------------------------------------------------- #include "RRC/LTE/rrc_defs.h" #include "COMMON/platform_constants.h" @@ -522,7 +518,7 @@ pdcp_mbms_t pdcp_mbms_array_eNB[NUMBER_OF_eNB_MAX][LTE_maxServiceC sdu_size_t pdcp_output_sdu_bytes_to_write; sdu_size_t pdcp_output_header_bytes_to_write; -list_t pdcp_sdu_list; +notifiedFIFO_t pdcp_sdu_list; int pdcp_sent_a_sdu; pdcp_data_req_header_t pdcp_input_header; unsigned char pdcp_input_sdu_buffer[MAX_IP_PACKET_SIZE]; diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c index d203408e55..6c6bd30070 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c @@ -55,7 +55,6 @@ extern int otg_enabled; #include "common/utils/LOG/log.h" #include "UTIL/OTG/otg_tx.h" #include "nfapi/oai_integration/vendor_ext.h" -#include "UTIL/FIFO/pad_list.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "platform_constants.h" #include "msc.h" @@ -91,7 +90,6 @@ extern struct msghdr nas_msg_rx; extern uint16_t inst_pdcp_list[NUMBER_OF_UE_MAX]; #endif -extern Packet_OTG_List_t *otg_pdcp_buffer; # include "gtpv1u_eNB_task.h" @@ -111,69 +109,60 @@ void debug_pdcp_pc5s_sdu(sidelink_pc5s_element *sl_pc5s_msg, char *title) { } //----------------------------------------------------------------------------- int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { - mem_block_t *sdu_p; + notifiedFIFO_elt_t *sdu_p; int pdcp_nb_sdu_sent = 0; int ret=0; + while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) { + pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p); - while ((sdu_p = list_get_head (&pdcp_sdu_list)) != NULL && ((pdcp_data_ind_header_t *)(sdu_p->data))->inst == ctxt_pP->module_id) { - ((pdcp_data_ind_header_t *)(sdu_p->data))->inst = 0; - int rb_id = ((pdcp_data_ind_header_t *)(sdu_p->data))->rb_id; + /* Note: we ignore the instance ID in the context and use the one in the + * PDCP packet to pick the right socket below */ + + int rb_id = pdcpHead->rb_id; int sizeToWrite= sizeof (pdcp_data_ind_header_t) + - ((pdcp_data_ind_header_t *) sdu_p->data)->data_size; - + pdcpHead->data_size; + void * pdcpData=(void*)(pdcpHead+1); if (rb_id == 10) { //hardcoded for PC5-Signaling if( LOG_DEBUGFLAG(DEBUG_PDCP) ) { - debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)&(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), + debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)pdcpData, "pdcp_fifo_flush_sdus sends a aPC5S message"); } - ret = sendto(pdcp_pc5_sockfd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), + ret = sendto(pdcp_pc5_sockfd, pdcpData, sizeof(sidelink_pc5s_element), 0, (struct sockaddr *)&prose_pdcp_addr,sizeof(prose_pdcp_addr) ); } else if (UE_NAS_USE_TUN) { - //ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); + //ret = write(nas_sock_fd[pdcpHead->inst], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); if(rb_id == mbms_rab_id){ - ret = write(nas_sock_mbms_fd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); - LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); + ret = write(nas_sock_mbms_fd, pdcpData,sizeToWrite ); + LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n", + ret,rb_id,nas_sock_fd[pdcpHead->inst],sizeToWrite); } else { - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PHY, "PDCP output to be sent to TUN interface: \n"); - for (int i = sizeof(pdcp_data_ind_header_t); i < sizeToWrite; i++) { - printf("%02x ",(unsigned char)sdu_p->data[i]); - } - printf("\n"); - #endif - ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); - //LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n"); + ret = write(nas_sock_fd[pdcpHead->inst], pdcpData,sizeToWrite ); + LOG_T(PDCP,"[UE PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n", + ret,rb_id,nas_sock_fd[pdcpHead->inst],sizeToWrite); } } else if (ENB_NAS_USE_TUN) { - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PHY, "PDCP output to be sent to TUN interface: \n"); - for (int i = sizeof(pdcp_data_ind_header_t); i < sizeToWrite; i++) { - printf("%02x ",(unsigned char)sdu_p->data[i]); - } - printf("\n"); - #endif - ret = write(nas_sock_fd[0], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), sizeToWrite); - + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n"); + ret = write(nas_sock_fd[0], pdcpData, sizeToWrite); + LOG_T(PDCP,"[NB PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[0],sizeToWrite); } else if (PDCP_USE_NETLINK) { - memcpy(NLMSG_DATA(nas_nlh_tx), (uint8_t *) sdu_p->data, sizeToWrite); + memcpy(NLMSG_DATA(nas_nlh_tx), (uint8_t *) pdcpHead, sizeToWrite); nas_nlh_tx->nlmsg_len = sizeToWrite; ret = sendmsg(nas_sock_fd[0],&nas_msg_tx,0); } // PDCP_USE_NETLINK AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s), nas_sock_fd[0]: %d\n", errno, strerror(errno), nas_sock_fd[0]); - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PDCP, "Printing first bytes of PDCP SDU before removing it from the list: \n"); - for (int i=0; i<30; i++){ - LOG_I(PDCP, "%x", sdu_p->data[i]); - } - #endif - list_remove_head (&pdcp_sdu_list); - free_mem_block (sdu_p, __func__); + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpData, min(sizeToWrite,30) , LOG_DUMP_CHAR, + "Printing first bytes of PDCP SDU before removing it from the list: \n"); + delNotifiedFIFO_elt (sdu_p); pdcp_nb_sdu_sent ++; } @@ -181,12 +170,13 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { } int pdcp_fifo_flush_mbms_sdus(const protocol_ctxt_t *const ctxt_pP) { - mem_block_t *sdu_p; + notifiedFIFO_elt_t *sdu_p; int pdcp_nb_sdu_sent = 0; //int ret=0; - while ((sdu_p = list_get_head (&pdcp_sdu_list)) != NULL && ((pdcp_data_ind_header_t *)(sdu_p->data))->inst == ctxt_pP->module_id) { - ((pdcp_data_ind_header_t *)(sdu_p->data))->inst = 0; + while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) { + pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p); + AssertFatal(pdcpHead->inst==ctxt_pP->module_id, "To implement correctly multi module id\n"); //int rb_id = ((pdcp_data_ind_header_t *)(sdu_p->data))->rb_id; //int sizeToWrite= sizeof (pdcp_data_ind_header_t) + //((pdcp_data_ind_header_t *) sdu_p->data)->data_size; @@ -212,8 +202,8 @@ int pdcp_fifo_flush_mbms_sdus(const protocol_ctxt_t *const ctxt_pP) { //} // PDCP_USE_NETLINK //AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s)\n", errno, strerror(errno)); - list_remove_head (&pdcp_sdu_list); - free_mem_block (sdu_p, __func__); + //AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s)\n", errno, strerror(errno)); + delNotifiedFIFO_elt (sdu_p); pdcp_nb_sdu_sent ++; } diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c b/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c index 09f29ebe67..4ef952667d 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c @@ -588,9 +588,10 @@ static void check_t_reassembly(nr_rlc_entity_um_t *entity) cur = entity->rx_list; while (cur != NULL && sn_compare_rx(entity, cur->sn, entity->rx_next_reassembly) < 0) { - nr_rlc_free_pdu(cur); + nr_rlc_pdu_t *p = cur; cur = cur->next; entity->rx_list = cur; + nr_rlc_free_pdu(p); } if (sn_compare_rx(entity, entity->rx_next_highest, diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c index ff0d446e3f..bbc4acbd56 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c @@ -72,8 +72,8 @@ void mac_rlc_data_ind ( LOG_I(RLC, "RLC instance for the given UE was not found \n"); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -113,8 +113,8 @@ tbs_size_t mac_rlc_data_req( ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -123,7 +123,7 @@ tbs_size_t mac_rlc_data_req( maxsize = tb_sizeP; ret = rb->generate_pdu(rb, buffer_pP, maxsize); } else { - LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB\n", __FILE__, __LINE__, __FUNCTION__); + LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB, channel_idP: %d\n", __FILE__, __LINE__, __FUNCTION__, channel_idP); exit(1); ret = 0; } @@ -166,8 +166,8 @@ mac_rlc_status_resp_t mac_rlc_status_ind( ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -227,8 +227,8 @@ rlc_buffer_occupancy_t mac_rlc_get_buffer_occupancy_ind( ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -654,7 +654,7 @@ static void add_drb_am(int rnti, struct LTE_DRB_ToAddMod *s) exit(1); } - if (channel_id != drb_id + 2) { + if (channel_id != drb_id + 3) { LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n", __FILE__, __LINE__, __FUNCTION__); exit(1); @@ -737,7 +737,7 @@ static void add_drb_um(int rnti, struct LTE_DRB_ToAddMod *s) exit(1); } - if (channel_id != drb_id + 2) { + if (channel_id != drb_id + 3) { LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n", __FILE__, __LINE__, __FUNCTION__); exit(1); diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h index 464cf3d083..f578faaf38 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h +++ b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h @@ -28,7 +28,7 @@ typedef void nr_rlc_ue_manager_t; typedef struct nr_rlc_ue_t { int rnti; - nr_rlc_entity_t *srb[2]; + nr_rlc_entity_t *srb[3]; nr_rlc_entity_t *drb[5]; } nr_rlc_ue_t; diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 4dacef3dbb..ec969c6741 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -38,6 +38,7 @@ #include "LAYER2/MAC/mac_proto.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "common/ran_context.h" +#include "executables/softmodem-common.h" #define MAX_IF_MODULES 100 @@ -62,90 +63,74 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { if (UL_info->rach_ind.pdu_list[0].num_preamble>0) AssertFatal(UL_info->rach_ind.pdu_list[0].num_preamble==1, "More than 1 preamble not supported\n"); - - /*nr_initiate_ra_proc(UL_info->module_id, + + nr_initiate_ra_proc(UL_info->module_id, UL_info->CC_id, UL_info->rach_ind.sfn, UL_info->rach_ind.slot, UL_info->rach_ind.pdu_list[0].preamble_list[0].preamble_index, UL_info->rach_ind.pdu_list[0].freq_index, UL_info->rach_ind.pdu_list[0].symbol_index, - UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance);*/ + UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance); } } -void handle_nr_sr(NR_UL_IND_t *UL_info) { +void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl) { + // TODO + int max_harq_rounds = 4; // TODO define macro + int num_ucis = UL_info->uci_ind.num_ucis; + nfapi_nr_uci_t *uci_list = UL_info->uci_ind.uci_list; + for (int i = 0; i < num_ucis; i++) { + switch (uci_list[i].pdu_type) { + case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break; - /* if (nfapi_mode == 1) // PNF - { - if (UL_info->sr_ind.sr_indication_body.number_of_srs>0) - { - // oai_nfapi_sr_indication(&UL_info->sr_ind); + case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: { + if (get_softmodem_params()->phy_test == 0) { + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1; + // handle harq + int harq_idx_s = 0; + // iterate over received harq bits + for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) { + // search for the right harq process + for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) { + if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) { + if (uci_pdu->harq->harq_list[harq_bit].harq_value == 0) + sched_ctrl->harq_processes[harq_idx].round++; + if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) || + (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) { + sched_ctrl->harq_processes[harq_idx].ndi ^= 1; + sched_ctrl->harq_processes[harq_idx].round = 0; + } + sched_ctrl->harq_processes[harq_idx].is_waiting = 0; + harq_idx_s = harq_idx + 1; + break; + } + // if gNB fails to receive a ACK/NACK + else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) && + (sched_ctrl->harq_processes[harq_idx].is_waiting)) { + sched_ctrl->harq_processes[harq_idx].round++; + if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) { + sched_ctrl->harq_processes[harq_idx].ndi ^= 1; + sched_ctrl->harq_processes[harq_idx].round = 0; + } + sched_ctrl->harq_processes[harq_idx].is_waiting = 0; + } + } + } + } + break; + } + + case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break; } } - else - { - - for (int i=0;isr_ind.sr_indication_body.number_of_srs;i++) - SR_indication(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi); - - - - } - - UL_info->sr_ind.sr_indication_body.number_of_srs=0;*/ + UL_info->uci_ind.num_ucis = 0; } -void handle_nr_cqi(NR_UL_IND_t *UL_info) { - - /* - for (int i=0;icqi_ind.number_of_cqis;i++) - cqi_indication(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->cqi_ind.cqi_pdu_list[i].rx_ue_information.rnti, - &UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9, - UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu, - &UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information); - - UL_info->cqi_ind.number_of_cqis=0;*/ - -} - -void handle_nr_harq(NR_UL_IND_t *UL_info) { - /* if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF - //LOG_D(PHY, "UL_info->harq_ind.harq_indication_body.number_of_harqs:%d Send to VNF\n", UL_info->harq_ind.harq_indication_body.number_of_harqs); - int retval = oai_nfapi_harq_indication(&UL_info->harq_ind); - - if (retval!=0) { - LOG_E(PHY, "Failed to encode NFAPI HARQ_IND retval:%d\n", retval); - } - - UL_info->harq_ind.harq_indication_body.number_of_harqs = 0; - } - else - { - - for (int i=0;iharq_ind.harq_indication_body.number_of_harqs;i++) - harq_indication(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf), - &UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]); - - UL_info->harq_ind.harq_indication_body.number_of_harqs=0; - }*/ -} void handle_nr_ulsch(NR_UL_IND_t *UL_info) { if(nfapi_mode == 1) { @@ -224,9 +209,10 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { NR_Sched_Rsp_t *sched_info = &Sched_INFO[module_id][CC_id]; NR_IF_Module_t *ifi = if_inst[module_id]; gNB_MAC_INST *mac = RC.nrmac[module_id]; - LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rx_ind:%d crcs:%d]\n", + + LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rach_pdus:%d rx_ind:%d crcs:%d]\n", UL_info->frame,UL_info->slot, - module_id,CC_id, + module_id,CC_id, UL_info->rach_ind.number_of_pdus, UL_info->rx_ind.number_of_pdus, UL_info->crc_ind.number_crcs); if (nfapi_mode != 1) { @@ -244,9 +230,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { // clear DL/UL info for new scheduling round clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot); handle_nr_rach(UL_info); - handle_nr_sr(UL_info); - handle_nr_cqi(UL_info); - handle_nr_harq(UL_info); + handle_nr_uci(UL_info, &mac->UE_list.UE_sched_ctrl[0]); // clear HI prior to handling ULSCH mac->UL_dci_req[CC_id].numPdus = 0; handle_nr_ulsch(UL_info); diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 64a814bcdb..b18831b546 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -32,9 +32,9 @@ #include "PHY/defs_nr_UE.h" #include "NR_IF_Module.h" -#include "mac_proto.h" +#include "NR_MAC_UE/mac_proto.h" #include "assertions.h" -#include "LAYER2/NR_MAC_UE/mac_extern.h" +#include "NR_MAC_UE/mac_extern.h" #include "SCHED_NR_UE/fapi_nr_ue_l1.h" #include "executables/softmodem-common.h" @@ -93,6 +93,14 @@ int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_n */ } +int8_t handle_rar (nr_downlink_indication_t *dl_info){ + + LOG_D(MAC, "handling RAR at MAC layer \n"); + nr_process_rar (dl_info); + return 0; + +} + int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ NR_UE_L2_STATE_t ret; @@ -105,14 +113,18 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ mac->dl_config_request.number_pdus = 0; // clean previous FAPI messages - ret = nr_ue_scheduler( - ul_info->module_id, - ul_info->gNB_index, - ul_info->cc_id, - ul_info->frame, - ul_info->slot, - ul_info->ssb_index, - 0, 0); // TODO check tx/rx frame/slot is need for NR version + ret = nr_ue_scheduler(NULL, ul_info); + + if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra){ + nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); + if (mac->generate_nr_prach){ + //uint16_t monitoring_slot_period, monitoring_offset; + uint16_t rach_frame = mac->scheduled_response.ul_config->sfn; + uint16_t rx_rach_frame = (rach_frame + mac->RA_offset) % MAX_FRAME_NUMBER; // compensate 2 frames offset delay at gNB side + uint16_t rach_slot = mac->scheduled_response.ul_config->slot; + nr_ue_msg2_scheduler(module_id, rx_rach_frame, rach_slot, &mac->msg2_rx_frame, &mac->msg2_rx_slot); + } + } switch(ret){ case UE_CONNECTION_OK: @@ -127,14 +139,13 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ break; } - mac->if_module->scheduled_response(&mac->scheduled_response); return 0; } int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ - + int32_t i; uint32_t ret_mask = 0x0; module_id_t module_id = dl_info->module_id; @@ -142,132 +153,98 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; - dl_config->number_pdus = 0; - ul_config->number_pdus = 0; - //hook up pointers - mac->scheduled_response.dl_config = dl_config; - mac->scheduled_response.ul_config = ul_config; - mac->scheduled_response.tx_request = &mac->tx_request; - mac->scheduled_response.module_id = dl_info->module_id; - mac->scheduled_response.CC_id = dl_info->cc_id; - mac->scheduled_response.frame = dl_info->frame; - mac->scheduled_response.slot = dl_info->slot; + if (!dl_info->dci_ind && !dl_info->rx_ind) { + // UL indication to schedule reception DCI reception + nr_ue_scheduler(dl_info, NULL); + } else { + // UL indication after reception of DCI or DL PDU + dl_config->number_pdus = 0; + ul_config->number_pdus = 0; + //hook up pointers + mac->scheduled_response.dl_config = dl_config; + mac->scheduled_response.ul_config = ul_config; + mac->scheduled_response.tx_request = &mac->tx_request; + mac->scheduled_response.module_id = dl_info->module_id; + mac->scheduled_response.CC_id = dl_info->cc_id; + mac->scheduled_response.frame = dl_info->frame; + mac->scheduled_response.slot = dl_info->slot; - if(dl_info->dci_ind != NULL){ - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); - for(i=0; idci_ind->number_of_dcis; ++i){ - LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis); - // fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci; + if(dl_info->dci_ind != NULL){ + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); + for(i=0; idci_ind->number_of_dcis; ++i){ + LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis); - ret_mask |= (handle_dci(dl_info->module_id, - dl_info->cc_id, - dl_info->gNB_index, - dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND); - - AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" ); - nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response); - - - /*switch((dl_info->dci_ind->dci_list+i)->dci_type){ - case FAPI_NR_DCI_TYPE_0_0: - case FAPI_NR_DCI_TYPE_0_1: - case FAPI_NR_DCI_TYPE_1_1: - case FAPI_NR_DCI_TYPE_2_0: - case FAPI_NR_DCI_TYPE_2_1: - case FAPI_NR_DCI_TYPE_2_2: - case FAPI_NR_DCI_TYPE_2_3: - AssertFatal(1==0, "Not yet support at this moment!\n"); - break; - - case FAPI_NR_DCI_TYPE_1_0: - - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - - // mapping into DL_CONFIG_REQ for DL-SCH - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; - - dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = 0x0000; // TX RNTI: UE-spec - memcpy(dlsch_config_pdu, dci, sizeof(fapi_nr_dci_pdu_rel15_t)); - - dl_config->number_pdus = dl_config->number_pdus + 1; - - ret_mask |= (handle_dci( - dl_info->module_id, - dl_info->cc_id, - dl_info->gNB_index, - dci, - (dl_info->dci_ind->dci_list+i)->rnti, - (dl_info->dci_ind->dci_list+i)->dci_type)) << FAPI_NR_DCI_IND; - - - - break; - - default: - break; - }*/ - - //(dl_info->dci_list+i)->rnti - } - } - - if(dl_info->rx_ind != NULL){ - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - for(i=0; irx_ind->number_pdus; ++i){ - switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ - case FAPI_NR_RX_PDU_TYPE_MIB: - ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB; - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - /*ret_mask |= (handle_bcch_bch( dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.pdu, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.additional_bits, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_index, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_length, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;*/ - break; - case FAPI_NR_RX_PDU_TYPE_SIB: - ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB; - break; - case FAPI_NR_RX_PDU_TYPE_DLSCH: - // ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH; - ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot, ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH; - - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - - /* - // dl_config structure just stores what was received - not really needed - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - dl_config->number_pdus = dl_config->number_pdus + 1; - */ - - /*ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, - dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.pdu, - dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot)) << FAPI_NR_RX_PDU_TYPE_DLSCH; - - */ - break; - default: - - break; + ret_mask |= (handle_dci(dl_info->module_id, + dl_info->cc_id, + dl_info->gNB_index, + dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND); + AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" ); + nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response); } } + + if(dl_info->rx_ind != NULL){ + + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + + for(i=0; irx_ind->number_pdus; ++i){ + + switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ + + case FAPI_NR_RX_PDU_TYPE_MIB: + ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_MIB; + + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + + break; + + case FAPI_NR_RX_PDU_TYPE_SIB: + + ret_mask |= (handle_bcch_dlsch(dl_info->module_id, + dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB; + + break; + + case FAPI_NR_RX_PDU_TYPE_DLSCH: + + ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + dl_info->dci_ind, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, + dl_info->frame, + dl_info->slot, + ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH; + + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + + break; + + case FAPI_NR_RX_PDU_TYPE_RAR: + + ret_mask |= (handle_rar(dl_info)) << FAPI_NR_RX_PDU_TYPE_RAR; + + break; + + default: + break; + } + } + } + + //clean up nr_downlink_indication_t *dl_info + dl_info->rx_ind = NULL; + dl_info->dci_ind = NULL; + } - - //clean up nr_downlink_indication_t *dl_info - dl_info->rx_ind = NULL; - dl_info->dci_ind = NULL; - return 0; } @@ -305,7 +282,12 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) { dl_config->sfn=UE_mac->dl_config_request.sfn; dl_config->slot=UE_mac->dl_config_request.slot; dl_config->number_pdus=0; - - ue_dci_configuration(UE_mac,dl_config,dcireq->frame,dcireq->slot); + + //printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot); + + LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot); + + ue_dci_configuration(UE_mac, dl_config, dcireq->frame, dcireq->slot); + return 0; } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h index 0784e71584..df2d78f0cb 100755 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h @@ -72,7 +72,8 @@ typedef struct { /// NR UE FAPI-like P7 message, direction: L1 to L2 /// data reception indication structure fapi_nr_rx_indication_t *rx_ind; - + /// ssb_index, if ssb is not present in current TTI, value set to -1 + int ssb_index; /// dci reception indication structure fapi_nr_dci_indication_t *dci_ind; @@ -87,11 +88,13 @@ typedef struct { /// component carrier id int cc_id; /// frame - frame_t frame; - /// slot - uint32_t slot; - /// ssb_index, if ssb is not present in current TTI, thie value set to -1 - int ssb_index; + frame_t frame_rx; + /// slot rx + uint32_t slot_rx; + /// frame tx + frame_t frame_tx; + /// slot tx + uint32_t slot_tx; /// dci reception indication structure fapi_nr_dci_indication_t *dci_ind; } nr_uplink_indication_t; diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.c b/openair2/RRC/LTE/MESSAGES/asn1_msg.c index 583e10da94..9ede543003 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.c +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.c @@ -2310,7 +2310,7 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destin return((enc_rval.encoded+7)/8); } -uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) { +uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, uint8_t sel_plmn_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) { asn_enc_rval_t enc_rval; LTE_UL_DCCH_Message_t ul_dcch_msg; LTE_RRCConnectionSetupComplete_t *rrcConnectionSetupComplete; @@ -2323,7 +2323,7 @@ uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uin rrcConnectionSetupComplete->criticalExtensions.choice.c1.present = LTE_RRCConnectionSetupComplete__criticalExtensions__c1_PR_rrcConnectionSetupComplete_r8; rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension=CALLOC(1, sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension)); - rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= 1; + rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= sel_plmn_id; rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME = NULL;//calloc(1,sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME)); /* diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.h b/openair2/RRC/LTE/MESSAGES/asn1_msg.h index dda2340610..640d18a61f 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.h +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.h @@ -142,7 +142,11 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destina /** \brief Generate an RRCConnectionSetupComplete UL-DCCH-Message (UE) @param buffer Pointer to PER-encoded ASN.1 description of UL-DCCH-Message PDU @returns Size of encoded bit stream in bytes*/ -uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, +uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, + uint8_t *buffer, + const uint8_t Transaction_id, + uint8_t sel_plmn_id, + const int dedicatedInfoNASLength, const char *dedicatedInfoNAS); /** \brief Generate an RRCConnectionReconfigurationComplete UL-DCCH-Message (UE) diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 4116f5367e..bdf992c76a 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -128,8 +128,13 @@ static int decode_SIB1_MBMS( const protocol_ctxt_t *const ctxt_pP, const uint8_t * \param ctxt_pP Running context * \param eNB_index Index of corresponding eNB/CH * \param Transaction_id Transaction identifier + * \param sel_plmn_id selected PLMN Identity */ -static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ); +static void rrc_ue_generate_RRCConnectionSetupComplete( + const protocol_ctxt_t *const ctxt_pP, + const uint8_t eNB_index, + const uint8_t Transaction_id, + uint8_t sel_plmn_id); /** \brief Generates/Encodes RRCConnectionReconfigurationComplete message at UE * \param ctxt_pP Running context @@ -367,6 +372,7 @@ char openair_rrc_ue_init( const module_id_t ue_mod_idP, const unsigned char eNB_ rrc_set_state (ue_mod_idP, RRC_STATE_INACTIVE); rrc_set_sub_state (ue_mod_idP, RRC_SUB_STATE_INACTIVE); LOG_I(RRC,"[UE %d] INIT State = RRC_IDLE (eNB %d)\n",ctxt.module_id,eNB_index); + UE_rrc_inst[ctxt.module_id].selected_plmn_identity = 1; UE_rrc_inst[ctxt.module_id].Info[eNB_index].State=RRC_IDLE; UE_rrc_inst[ctxt.module_id].Info[eNB_index].T300_active = 0; UE_rrc_inst[ctxt.module_id].Info[eNB_index].T304_active = 0; @@ -490,7 +496,11 @@ rrc_t310_expiration( } //----------------------------------------------------------------------------- -static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ) { +static void rrc_ue_generate_RRCConnectionSetupComplete( + const protocol_ctxt_t *const ctxt_pP, + const uint8_t eNB_index, + const uint8_t Transaction_id, + uint8_t sel_plmn_id) { uint8_t buffer[100]; uint8_t size; const char *nas_msg; @@ -504,7 +514,7 @@ static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *c nas_msg_length = sizeof(nas_attach_req_imsi); } - size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, nas_msg_length, nas_msg); + size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, sel_plmn_id, nas_msg_length, nas_msg); LOG_I(RRC,"[UE %d][RAPROC] Frame %d : Logical Channel UL-DCCH (SRB1), Generating RRCConnectionSetupComplete (bytes%d, eNB %d)\n", ctxt_pP->module_id,ctxt_pP->frame, size, eNB_index); LOG_D(RLC, @@ -624,7 +634,8 @@ int rrc_ue_decode_ccch( const protocol_ctxt_t *const ctxt_pP, const SRB_INFO *co rrc_ue_generate_RRCConnectionSetupComplete( ctxt_pP, eNB_index, - dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier); + dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier, + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity); rval = 0; break; @@ -2794,44 +2805,43 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, LTE_SystemInformationBlockType1_t *sib1 = UE_rrc_inst[ctxt_pP->module_id].sib1[eNB_index]; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_UE_DECODE_SIB1, VCD_FUNCTION_IN ); LOG_I( RRC, "[UE %d] : Dumping SIB 1\n", ctxt_pP->module_id ); - LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->plmn_Identity; - int mccdigits = PLMN_identity->mcc->list.count; - int mncdigits = PLMN_identity->mnc.list.count; - int mcc; + const int n = sib1->cellAccessRelatedInfo.plmn_IdentityList.list.count; + for (int i = 0; i < n; ++i) { + LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[i]->plmn_Identity; + int mccdigits = PLMN_identity->mcc->list.count; + int mncdigits = PLMN_identity->mnc.list.count; - if (mccdigits == 2) { - mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1]; - } else { - mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2]; + int mcc; + if (mccdigits == 2) { + mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1]; + } else { + mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2]; + } + + int mnc; + if (mncdigits == 2) { + mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1]; + } else { + mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2]; + } + + LOG_I( RRC, "PLMN %d MCC %0*d, MNC %0*d\n", i + 1, mccdigits, mcc, mncdigits, mnc); + // search internal table for provider name + int plmn_ind = 0; + + while (plmn_data[plmn_ind].mcc > 0) { + if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) { + LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short ); + break; + } + + plmn_ind++; + } } - - int mnc; - - if (mncdigits == 2) { - mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1]; - } else { - mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2]; - } - - LOG_I( RRC, "PLMN MCC %0*d, MNC %0*d, TAC 0x%04x\n", mccdigits, mcc, mncdigits, mnc, + LOG_I( RRC, "TAC 0x%04x\n", ((sib1->cellAccessRelatedInfo.trackingAreaCode.size == 2)?((sib1->cellAccessRelatedInfo.trackingAreaCode.buf[0]<<8) + sib1->cellAccessRelatedInfo.trackingAreaCode.buf[1]):0)); LOG_I( RRC, "cellReservedForOperatorUse : raw:%ld decoded:%s\n", sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse, SIBreserved(sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse) ); - // search internal table for provider name - int plmn_ind = 0; - - while (plmn_data[plmn_ind].mcc > 0) { - if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) { - LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short ); - break; - } - - plmn_ind++; - } - - if (plmn_data[plmn_ind].mcc < 0) { - LOG_I( RRC, "Found Unknown operator (no entry in internal table)\n" ); - } LOG_I( RRC, "cellAccessRelatedInfo.cellIdentity : raw:%"PRIu32" decoded:%02x.%02x.%02x.%02x\n", BIT_STRING_to_uint32( &sib1->cellAccessRelatedInfo.cellIdentity ), @@ -2970,6 +2980,7 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, NAS_CELL_SELECTION_CNF (msg_p).rsrp = rsrp; itti_send_msg_to_task(TASK_NAS_UE, ctxt_pP->instance, msg_p); cell_valid = 1; + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity = plmn + 1; break; } } @@ -2980,7 +2991,11 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, MessageDef *msg_p; msg_p = itti_alloc_new_message(TASK_RRC_UE, PHY_FIND_NEXT_CELL_REQ); itti_send_msg_to_task(TASK_PHY_UE, ctxt_pP->instance, msg_p); - LOG_E(RRC, "Synched with a cell, but PLMN doesn't match our SIM, the message PHY_FIND_NEXT_CELL_REQ is sent but lost in current UE implementation! \n"); + LOG_E(RRC, + "Synched with a cell, but PLMN doesn't match our SIM " + "(selected_plmn_identity %d), the message PHY_FIND_NEXT_CELL_REQ " + "is sent but lost in current UE implementation!\n", + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity); } } diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index f050733a13..3c02c45bc1 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -40,6 +40,10 @@ #include "rrc_types.h" //#include "PHY/phy_defs.h" #include "LAYER2/RLC/rlc.h" +#include "RRC/NR/nr_rrc_types.h" +#include "NR_UE-MRDC-Capability.h" +#include "NR_UE-NR-Capability.h" + #include "COMMON/platform_constants.h" #include "COMMON/platform_types.h" @@ -267,6 +271,7 @@ typedef enum UE_STATE_e { RRC_RECONFIGURED, RRC_HO_EXECUTION, RRC_NR_NSA, + RRC_NR_NSA_RECONFIGURED } UE_STATE_t; typedef enum HO_STATE_e { @@ -382,6 +387,7 @@ typedef enum e_rab_satus_e { E_RAB_STATUS_DONE, // from the eNB perspective E_RAB_STATUS_ESTABLISHED, // get the reconfigurationcomplete form UE E_RAB_STATUS_REESTABLISHED, // after HO + E_RAB_STATUS_TOMODIFY, // ENDC NSA E_RAB_STATUS_FAILED, E_RAB_STATUS_TORELEASE // to release DRB between eNB and UE } e_rab_status_t; @@ -568,6 +574,10 @@ typedef struct eNB_RRC_UE_s { LTE_UE_EUTRA_Capability_t *UE_Capability; int UE_Capability_size; + NR_UE_MRDC_Capability_t *UE_Capability_MRDC; + int UE_MRDC_Capability_size; + NR_UE_NR_Capability_t *UE_Capability_nr; + int UE_NR_Capability_size; ImsiMobileIdentity_t imsi; /* KeNB as derived from KASME received from EPC */ @@ -613,6 +623,7 @@ typedef struct eNB_RRC_UE_s { /* Number of e_rab to be modified in the list */ uint8_t nb_of_modify_e_rabs; uint8_t nb_of_failed_e_rabs; + uint8_t nb_of_modify_endc_e_rabs; e_rab_param_t modify_e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; /* list of e_rab to be setup by RRC layers */ e_rab_param_t e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; @@ -627,6 +638,10 @@ typedef struct eNB_RRC_UE_s { uint32_t enb_gtp_teid[S1AP_MAX_E_RAB]; transport_layer_addr_t enb_gtp_addrs[S1AP_MAX_E_RAB]; rb_id_t enb_gtp_ebi[S1AP_MAX_E_RAB]; + // LG: For GTPV1 TUNNELS ENDC + uint32_t gnb_gtp_endc_teid[S1AP_MAX_E_RAB]; + transport_layer_addr_t gnb_gtp_endc_addrs[S1AP_MAX_E_RAB]; + rb_id_t gnb_gtp_endc_ebi[S1AP_MAX_E_RAB]; /* Total number of e_rab already setup in the list */ uint8_t nb_x2u_e_rabs; // LG: For GTPV1 TUNNELS(X2U) @@ -794,6 +809,7 @@ typedef struct UE_RRC_INST_s { Rrc_Sub_State_t RrcSubState; plmn_t plmnID; Byte_t rat; + uint8_t selected_plmn_identity; as_nas_info_t initialNasMsg; OAI_UECapability_t *UECap; uint8_t *UECapability; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 5965e51720..1d44751dca 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -96,6 +96,10 @@ #include "SIMULATION/TOOLS/sim.h" // for taus +#define ASN_MAX_ENCODE_SIZE 4096 +#define NUMBEROF_DRBS_TOBE_ADDED 1 +static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); +static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); extern RAN_CONTEXT_t RC; @@ -113,8 +117,9 @@ extern uint32_t to_earfcn_DL(int eutra_bandP, uint32_t dl_CarrierFreq, uint32_t extern int rrc_eNB_process_security(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, security_capabilities_t *security_capabilities_pP); extern void process_eNB_security_key (const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, uint8_t *security_key_pP); extern int derive_keNB_star(const uint8_t *kenb_32, const uint16_t pci, const uint32_t earfcn_dl, const bool is_rel8_only, uint8_t *kenb_star); -extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, OCTET_STRING_t *scg_RB_config); -extern struct rrc_eNB_ue_context_s * get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); +extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, + OCTET_STRING_t *scg_RB_config); +extern struct rrc_eNB_ue_context_s *get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); pthread_mutex_t rrc_release_freelist; RRC_release_list_t rrc_release_info; @@ -162,7 +167,7 @@ init_SI( AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].SIB1_MBMS!=NULL,PROTOCOL_RRC_CTXT_FMT" init_SI: FATAL, no memory for SIB1_MBMS allocated\n", PROTOCOL_RRC_CTXT_ARGS(ctxt_pP)); RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1_MBMS = do_SIB1_MBMS(&RC.rrc[ctxt_pP->module_id]->carrier[CC_id],ctxt_pP->module_id,CC_id, - configuration + configuration ); LOG_I(RRC, PROTOCOL_RRC_CTXT_FMT" Contents of SIB1-MBMS\n", PROTOCOL_RRC_CTXT_ARGS(ctxt_pP) @@ -2119,7 +2124,27 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), ue_p->Srb0.Tx_buffer.payload_size); } - +#if 0 +void rrc_generate_SgNBReleaseRequest( + const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP +) +//----------------------------------------------------------------------------- +{ + MessageDef *msg; + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_RELEASE_REQ); + memset(&(X2AP_ENDC_SGNB_RELEASE_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_release_req_t)); + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; + LOG_I(RRC, + "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", + ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; +} +#endif //----------------------------------------------------------------------------- /* * Generate the RRC Connection Release to UE. @@ -2139,6 +2164,15 @@ rrc_eNB_generate_RRCConnectionRelease( memset(buffer, 0, RRC_BUF_SIZE); T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); +#if 0 + + if(ue_context_pP != NULL) { + if(ue_context_pP->ue_context.Status == RRC_NR_NSA) { + //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); + } + } + +#endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; ue_context_pP->ue_context.ue_release_timer = 0; @@ -2837,7 +2871,6 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t uint16_t size; int i; MessageDef *message_p = NULL; - /* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */ eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id]; struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated; @@ -3029,7 +3062,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t module_id_t module_id = ctxt_pP->module_id; LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n"); - /* Process the IE drx_Config */ + /* Process the IE drx_Config */ if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) { mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE @@ -3044,8 +3077,8 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n"); } } - /* End of CDRX configuration */ + /* End of CDRX configuration */ sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long)); *sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1)); @@ -3153,7 +3186,9 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (ue_context_pP->ue_context.does_nr) { MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t)); + if (MeasId6 == NULL) exit(1); + MeasId6->measId = 7; MeasId6->measObjectId = 2; MeasId6->reportConfigId = 7; @@ -3211,22 +3246,27 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (ue_context_pP->ue_context.does_nr) { MeasObj2 = calloc(1, sizeof(LTE_MeasObjectToAddMod_t)); + if (MeasObj2 == NULL) exit(1); + MeasObj2->measObjectId = 2; MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; - MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.subcarrierSpacingSSB_r15 = LTE_RS_ConfigSSB_NR_r15__subcarrierSpacingSSB_r15_kHz30; MeasObj2->measObject.choice.measObjectNR_r15.quantityConfigSet_r15 = 1; MeasObj2->measObject.choice.measObjectNR_r15.ext1 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1__bandNR_r15)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->present = LTE_MeasObjectNR_r15__ext1__bandNR_r15_PR_setup; MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->choice.setup = 78; - ASN_SEQUENCE_ADD(&MeasObj_list->list, MeasObj2); } @@ -3242,9 +3282,11 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_A3 = CALLOC(1, sizeof(*ReportConfig_A3)); ReportConfig_A4 = CALLOC(1, sizeof(*ReportConfig_A4)); ReportConfig_A5 = CALLOC(1, sizeof(*ReportConfig_A5)); + if (ue_context_pP->ue_context.does_nr) { ReportConfig_NR = CALLOC(1, sizeof(*ReportConfig_NR)); } + ReportConfig_per->reportConfigId = 1; ReportConfig_per->reportConfig.present = LTE_ReportConfigToAddMod__reportConfig_PR_reportConfigEUTRA; ReportConfig_per->reportConfig.choice.reportConfigEUTRA.triggerType.present = @@ -3357,7 +3399,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15; - ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 0; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80; @@ -3365,9 +3407,13 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrp = TRUE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrq = TRUE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_sinr = TRUE; @@ -3569,7 +3615,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt uint16_t size; int i; MessageDef *message_p = NULL; - /* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */ eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id]; struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated; @@ -3615,7 +3660,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt LTE_C_RNTI_t *cba_RNTI = NULL; int measurements_enabled; uint8_t xid = rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id); //Transaction_id, - #ifdef CBA // Contention Based Access uint8_t *cba_RNTI_buf; cba_RNTI = CALLOC(1, sizeof(LTE_C_RNTI_t)); @@ -3641,8 +3685,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt frameP, ue_mod_idP); } -#endif +#endif T(T_ENB_RRC_CONNECTION_RECONFIGURATION, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), @@ -3777,7 +3821,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt mac_MainConfig->phr_Config->choice.setup.prohibitPHR_Timer = LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf200; // sf20 = 20 subframes // LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf1000 mac_MainConfig->phr_Config->choice.setup.dl_PathlossChange = LTE_MAC_MainConfig__phr_Config__setup__dl_PathlossChange_dB3; // Value dB1 =1 dB, dB3 = 3 dB - /* CDRX Configuration */ mac_MainConfig->drx_Config = NULL; rnti_t rnti = ue_context_pP->ue_id_rnti; @@ -3785,11 +3828,11 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt uint8_t cc_id = ue_context_pP->ue_context.primaryCC_id; LTE_UE_EUTRA_Capability_t *UEcap = ue_context_pP->ue_context.UE_Capability; LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n"); - + /* Process the IE drx_Config */ if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) { mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE - + if (mac_MainConfig->drx_Config == NULL) { LOG_W(RRC, "drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated\n"); } else { @@ -3801,8 +3844,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n"); } } - /* End of CDRX configuration */ + /* End of CDRX configuration */ sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long)); *sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1)); @@ -4319,6 +4362,182 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( } + +//----------------------------------------------------------------------------- +/** + * @fn :encode_CG_ConfigInfo + * @param :enc_buf to store the encoded bits + * @param :ue_context_pP ue context used to fill CG-ConfigInfo + * @param :enc_size to store thre size of encoded size + * this api is to fill and encode CG-ConfigInfo + */ +static int encode_CG_ConfigInfo( + char *buffer, + int buffer_size, + rrc_eNB_ue_context_t *const ue_context_pP, + int *enc_size +) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + struct NR_RadioBearerConfig *rb_config = NULL; + asn_enc_rval_t enc_rval; + int RRC_OK = 1; + int index = 0; + char temp_buff[ASN_MAX_ENCODE_SIZE]; + LTE_UE_CapabilityRAT_ContainerList_t *ue_cap_rat_container_list = NULL; + LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_MRDC; + LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_nr; + int RAT_Container_count = 0; + rb_config = calloc(1,sizeof(struct NR_RadioBearerConfig)); + AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); + + if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { + rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = NUMBEROF_DRBS_TOBE_ADDED; + rb_config->drb_ToAddModList->list.array + = calloc(NUMBEROF_DRBS_TOBE_ADDED, sizeof(struct NR_DRB_ToAddMod *)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + + for(index = 0; index < NUMBEROF_DRBS_TOBE_ADDED; index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + = ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + = calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL + = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL + = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present + = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering + = NR_PDCP_Config__t_Reordering_ms0; + } + + rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); + rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); + rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; + rb_config->securityConfig->keyToUse = calloc(1,sizeof(long)); + *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; + } + + cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); + AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); + cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + + if(ue_context_pP->ue_context.UE_Capability_MRDC) { + RAT_Container_count++; + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_MRDC_Capability,NULL, + (void *)ue_context_pP->ue_context.UE_Capability_MRDC,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + ue_cap_rat_container_MRDC.rat_Type = LTE_RAT_Type_eutra_nr; + OCTET_STRING_fromBuf(&ue_cap_rat_container_MRDC.ueCapabilityRAT_Container, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); + memset((void *)temp_buff,0,sizeof(temp_buff)); + } + + if(ue_context_pP->ue_context.UE_Capability_nr) { + RAT_Container_count++; + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_NR_Capability,NULL, + (void *)ue_context_pP->ue_context.UE_Capability_nr,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + ue_cap_rat_container_nr.rat_Type = LTE_RAT_Type_nr; + OCTET_STRING_fromBuf(&ue_cap_rat_container_nr.ueCapabilityRAT_Container, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); + memset((void *)temp_buff,0,sizeof(temp_buff)); + } + + ue_cap_rat_container_list = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); + ue_cap_rat_container_list->list.count = RAT_Container_count; + ue_cap_rat_container_list->list.size = RAT_Container_count * sizeof(LTE_UE_CapabilityRAT_Container_t); + ue_cap_rat_container_list->list.array = calloc(RAT_Container_count,sizeof(LTE_UE_CapabilityRAT_Container_t *)); + + if(ue_context_pP->ue_context.UE_Capability_MRDC) { + ue_cap_rat_container_list->list.array[0] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t)); + memcpy(ue_cap_rat_container_list->list.array[0],&ue_cap_rat_container_MRDC,sizeof(LTE_UE_CapabilityRAT_Container_t)); + } + + if(ue_context_pP->ue_context.UE_Capability_nr) { + ue_cap_rat_container_list->list.array[1] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t)); + memcpy(ue_cap_rat_container_list->list.array[1],&ue_cap_rat_container_nr,sizeof(LTE_UE_CapabilityRAT_Container_t)); + } + + //this xer_fprint logs can be enabled for additional debugging logs + //xer_fprint(stdout,&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list); + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void *)ue_cap_rat_container_list,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, + (const char *)temp_buff, (enc_rval.encoded+7)>>3); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, + (const char *)temp_buff, (enc_rval.encoded+7)>>3); + // this xer_fprint can be enabled for additional debugging messages + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void *)cg_configinfo); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void *)cg_configinfo, + buffer,buffer_size); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + *enc_size = (enc_rval.encoded+7)/8; + ASN_STRUCT_FREE(asn_DEF_NR_RadioBearerConfig,rb_config); + ASN_STRUCT_FREE(asn_DEF_NR_CG_ConfigInfo,cg_configinfo); + ASN_STRUCT_FREE(asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list); + return RRC_OK; +} +//----------------------------------------------------------------------------- + + + + + + //----------------------------------------------------------------------------- void rrc_eNB_process_MeasurementReport( @@ -4334,6 +4553,8 @@ rrc_eNB_process_MeasurementReport( long ncell_max = -150; uint32_t earfcn_dl; uint8_t KeNB_star[32] = { 0 }; + char enc_buf[ASN_MAX_ENCODE_SIZE] = {0}; + int enc_size = 0; T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); @@ -4392,17 +4613,41 @@ rrc_eNB_process_MeasurementReport( /* TODO: improve NR triggering */ if (measResults2->measId == 7) { - if (ue_context_pP->ue_context.Status != RRC_NR_NSA) { + if ((ue_context_pP->ue_context.Status != RRC_NR_NSA) && (ue_context_pP->ue_context.Status != RRC_NR_NSA_RECONFIGURED)) { MessageDef *msg; ue_context_pP->ue_context.Status = RRC_NR_NSA; - msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; - LOG_I(RRC, - "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", - ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); - return; + if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { + /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ + if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) + LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); + + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId + = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + //For the moment we have a single E-RAB which will be the one to be added to the gNB + //Not sure how to select bearers to be added if there are multiple. + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; + + for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++) { + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = ue_context_pP->ue_context.DRB_configList->list.array[e_rab]->drb_Identity; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, + sizeof(transport_layer_addr_t)); + } + + LOG_I(RRC, + "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", + ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; + } } } @@ -4520,6 +4765,7 @@ rrc_eNB_process_MeasurementReport( } } + //----------------------------------------------------------------------------- void rrc_eNB_generate_HandoverPreparationInformation( @@ -6047,6 +6293,7 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct ue_context_pP->ue_context.e_rab[i].param.nas_pdu.buffer = NULL; } } + LOG_I(RRC, "[eNB %d] Frame %d, Logical Channel DL-DCCH, Generate RRCConnectionReconfiguration handover (bytes %d, UE id %x)\n", ctxt_pP->module_id, ctxt_pP->frame, size, ue_context_pP->ue_context.rnti); @@ -6217,10 +6464,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( LTE_SRB_ToAddModList_t *SRB_configList = ue_context_pP->ue_context.SRB_configList2[xid]; LTE_DRB_ToReleaseList_t *DRB_Release_configList2 = ue_context_pP->ue_context.DRB_Release_configList2[xid]; LTE_DRB_Identity_t *drb_id_p = NULL; - ue_context_pP->ue_context.ue_reestablishment_timer = 0; ue_context_pP->ue_context.ue_rrc_inactivity_timer = 1; // reset rrc inactivity timer - /* CDRX: activated when RRC Connection Reconfiguration Complete is received */ rnti_t rnti = ue_context_pP->ue_id_rnti; module_id_t module_id = ctxt_pP->module_id; @@ -6241,8 +6486,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( LOG_I(RRC, "CDRX configuration activated after RRC Connection Reconfiguration Complete reception\n"); } } - /* End of CDRX processing */ + /* End of CDRX processing */ T(T_ENB_RRC_CONNECTION_RECONFIGURATION_COMPLETE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), @@ -6503,7 +6748,6 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( ue_context_pP->ue_context.nr_capabilities_requested = 1; rrc_eNB_generate_NR_UECapabilityEnquiry(ctxt_pP, ue_context_pP); } - } //----------------------------------------------------------------------------- @@ -7326,33 +7570,34 @@ is_en_dc_supported( */ #define NCE nonCriticalExtension return c != NULL - && c->NCE != NULL - && c->NCE->NCE != NULL - && c->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL - && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; + && c->NCE != NULL + && c->NCE->NCE != NULL + && c->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL + && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == + LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; #undef NCE } @@ -7528,7 +7773,37 @@ rrc_eNB_decode_dcch( LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" UE State = RRC_HO_EXECUTION (xid %ld)\n", PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.rrc_TransactionIdentifier); - } else { + } + else if(ue_context_p->ue_context.Status == RRC_NR_NSA){ + //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete + //including NR specific elements. + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension + ->scg_ConfigResponseNR_r15!=NULL) { + ue_context_p->ue_context.Status = RRC_NR_NSA_RECONFIGURED; + /*Trigger E-RAB Modification Indication */ + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + } + } + } + } + } + } + } + } + else { dedicated_DRB = 0; ue_context_p->ue_context.Status = RRC_RECONFIGURED; LOG_I(RRC, @@ -7537,6 +7812,7 @@ rrc_eNB_decode_dcch( } ue_context_p->ue_context.reestablishment_xid = -1; + } else { dedicated_DRB = 1; ue_context_p->ue_context.Status = RRC_RECONFIGURED; @@ -7884,15 +8160,74 @@ rrc_eNB_decode_dcch( } LOG_I(RRC, "got UE capabilities for UE %x\n", ctxt_pP->rnti); - int eutra_index = -1; for (i = 0; i < ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.count; i++) { - if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == LTE_RAT_Type_eutra) { + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_nr) { + if(ue_context_p->ue_context.UE_Capability_nr) { + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_NR_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_nr, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size, + 0, 0); + + if (LOG_DEBUGFLAG(DEBUG_ASN1)) { + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode nr UE capabilities (%zu bytes)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + } + + ue_context_p->ue_context.UE_NR_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size; + } + + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_eutra_nr) { + if(ue_context_p->ue_context.UE_Capability_MRDC) { + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_MRDC_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_MRDC, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size, + 0, 0); + + if (LOG_DEBUGFLAG(DEBUG_ASN1)) { + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode MRDC UE capabilities (%zu bytes)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + } + + ue_context_p->ue_context.UE_MRDC_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size; + } + + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_eutra) { if (eutra_index != -1) { LOG_E(RRC, "fatal: more than 1 eutra capability\n"); exit(1); } + eutra_index = i; } } @@ -7914,7 +8249,8 @@ rrc_eNB_decode_dcch( ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.buf, ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size, 0, 0); - ue_context_p->ue_context.UE_Capability_size = ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; + ue_context_p->ue_context.UE_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { xer_fprint(stdout, &asn_DEF_LTE_UE_EUTRA_Capability, ue_context_p->ue_context.UE_Capability); @@ -8031,36 +8367,54 @@ rrc_eNB_decode_dcch( return 0; //TTN for D2D } else if (ul_dcch_msg->message.present == LTE_UL_DCCH_MessageType_PR_messageClassExtension) { - LOG_I(RRC, "THINH [LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n"); + LOG_I(RRC, "[LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n"); switch (ul_dcch_msg->message.choice.messageClassExtension.present) { case LTE_UL_DCCH_MessageType__messageClassExtension_PR_NOTHING: /* No components present */ break; case LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2: //SidelinkUEInformation - //case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation - LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n"); - LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP, + if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present == + LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_scgFailureInformationNR_r15){ + if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15. + criticalExtensions.present == LTE_SCGFailureInformationNR_r15__criticalExtensions_PR_c1){ + if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. + choice.c1.present == LTE_SCGFailureInformationNR_r15__criticalExtensions__c1_PR_scgFailureInformationNR_r15){ + if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. + choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15!=NULL) { + LOG_E(RRC, "Received NR scgFailureInformation from UE, failure type: %ld \n", + ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. + choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15->failureType_r15); + xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)ul_dcch_msg); + } + } + } + } + else if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present == LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12){ + //case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation + LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n"); + LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP, "[MSG] RRC SidelinkUEInformation \n"); - MSC_LOG_RX_MESSAGE( - MSC_RRC_ENB, - MSC_RRC_UE, - Rx_sdu, - sdu_sizeP, - MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u", - MSC_AS_TIME_ARGS(ctxt_pP), - ue_context_p->ue_context.rnti, - sdu_sizeP); - LOG_I(RRC, - PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes " - "(SidelinkUEInformation) ---> RRC_eNB\n", - PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), - DCCH, + MSC_LOG_RX_MESSAGE( + MSC_RRC_ENB, + MSC_RRC_UE, + Rx_sdu, + sdu_sizeP, + MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u", + MSC_AS_TIME_ARGS(ctxt_pP), + ue_context_p->ue_context.rnti, sdu_sizeP); - rrc_eNB_process_SidelinkUEInformation( - ctxt_pP, - ue_context_p, - &ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12); + LOG_I(RRC, + PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes " + "(SidelinkUEInformation) ---> RRC_eNB\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + DCCH, + sdu_sizeP); + rrc_eNB_process_SidelinkUEInformation( + ctxt_pP, + ue_context_p, + &ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12); + } break; default: @@ -8633,96 +8987,109 @@ void rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) { } void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, x2ap_ENDC_sgnb_addition_req_ACK_t *m) { + NR_CG_Config_t *CG_Config = NULL; + { + int i; + printf("%d: ", m->rrc_buffer_size); + for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); - NR_CG_Config_t *CG_Config = NULL; + printf("\n"); + } + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_CG_Config, + (void **)&CG_Config, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); - { - int i; - printf("%d: ", m->rrc_buffer_size); - for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); - printf("\n"); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); + return; + } - } - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_NR_CG_Config, - (void **)&CG_Config, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size);//m->rrc_buffer_size); + xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); + // recreate enough of X2 EN-DC Container + AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, + "CG_Config not present\n"); + OCTET_STRING_t *scg_CellGroupConfig = NULL; + OCTET_STRING_t *nr1_conf = NULL; - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); - return; - } - xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); - // recreate enough of X2 EN-DC Container - - AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, - "CG_Config not present\n"); - - OCTET_STRING_t *scg_CellGroupConfig = NULL; - OCTET_STRING_t *nr1_conf = NULL; - - if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig){ - scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig) { + scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; #ifdef DEBUG_SCG_CONFIG - { - int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; - int i; - LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); - for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); - printf("\n"); + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; + int i; + LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); - } + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); + + printf("\n"); + } #endif + } else { + LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); + return; + } - } - else{ - LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); - return; - } - if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config){ - nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config) { + nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; #ifdef DEBUG_SCG_CONFIG - { - int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; - int i; - LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); - for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); - printf("\n"); + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; + int i; + LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); - } + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); + + printf("\n"); + } #endif - } - else{ - LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); - return; + } else { + LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); + return; + } + + protocol_ctxt_t ctxt; + rrc_eNB_ue_context_t *ue_context; + unsigned char buffer[8192]; + int size; + ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); + ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded; + int j=0; + + while(j < m->nb_e_rabs_admitted_tobeadded) { + for (int e_rab_idx=0; e_rab_idxue_context.setup_e_rabs; e_rab_idx++) { + //Update ue_context information with gNB's address and new GTP tunnel ID + if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id) { + memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.length); + ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length; + ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid; + ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY; + break; + } } - protocol_ctxt_t ctxt; - rrc_eNB_ue_context_t *ue_context; - unsigned char buffer[8192]; - int size; + j++; + } - ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); - - PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, - 0, - ENB_FLAG_YES, - m->rnti, - 0, 0); - - size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); - - rrc_data_req(&ctxt, - DCCH, - rrc_eNB_mui++, - SDU_CONFIRM_NO, - size, - buffer, - PDCP_TRANSMISSION_MODE_CONTROL); + PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, + 0, + ENB_FLAG_YES, + m->rnti, + 0, 0); + size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); + rrc_data_req(&ctxt, + DCCH, + rrc_eNB_mui++, + SDU_CONFIRM_NO, + size, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); } @@ -9005,11 +9372,10 @@ void *rrc_enb_process_itti_msg(void *notUsed) { } case X2AP_ENDC_SGNB_ADDITION_REQ_ACK: { - rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); - break; + rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); + break; } - /* Messages from eNB app */ case RRC_CONFIGURATION_REQ: LOG_I(RRC, "[eNB %d] Received %s : %p\n", instance, msg_name_p, &RRC_CONFIGURATION_REQ(msg_p)); @@ -9029,36 +9395,36 @@ void *rrc_enb_process_itti_msg(void *notUsed) { break; case M2AP_SETUP_RESP: - rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p)); + rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p)); break; case M2AP_MBMS_SCHEDULING_INFORMATION: - rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p)); + break; case M2AP_MBMS_SESSION_START_REQ: - rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p)); + break; case M2AP_MBMS_SESSION_STOP_REQ: - rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p)); + break; case M2AP_RESET: - rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p)); - break; + rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p)); + break; case M2AP_ENB_CONFIGURATION_UPDATE_ACK: - rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p)); - break; + rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p)); + break; case M2AP_ERROR_INDICATION: - rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p)); - break; + rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p)); + break; case M2AP_MBMS_SERVICE_COUNTING_REQ: - rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p)); + break; case M2AP_MCE_CONFIGURATION_UPDATE: rrc_eNB_process_M2AP_MCE_CONFIGURATION_UPDATE(&ctxt,&M2AP_MCE_CONFIGURATION_UPDATE(msg_p)); @@ -9095,17 +9461,16 @@ rrc_enb_task( //----------------------------------------------------------------------------- { rrc_enb_init(); - itti_mark_task_ready(TASK_RRC_ENB); LOG_I(RRC,"Entering main loop of RRC message task\n"); while (1) { (void) rrc_enb_process_itti_msg(NULL); -{ - //extern volatile int go_nr; - void rrc_go_nr(void); - //if (go_nr) rrc_go_nr(); -} + { + //extern volatile int go_nr; + void rrc_go_nr(void); + //if (go_nr) rrc_go_nr(); + } } } diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c index 6bbdef181b..1025d46f62 100644 --- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c +++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c @@ -92,6 +92,7 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( } } + //------------------------------------------------------------------------------ boolean_t gtpv_data_req( diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.h b/openair2/RRC/LTE/rrc_eNB_GTPV1U.h index 00c7490359..6318ed4927 100644 --- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.h +++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.h @@ -43,6 +43,13 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( uint8_t *inde_list ); +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +); + /*! \fn rrc_eNB_send_GTPV1U_ENB_DELETE_TUNNEL_REQ(module_id_t enb_mod_idP, const rrc_eNB_ue_context_t* const ue_context_pP) *\brief Send GTPV1U_ENB_DELETE_TUNNEL_REQ message to GTPV1U to destroy all UE-related tunnels. *\param module_id Instance ID of eNB. diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.c b/openair2/RRC/LTE/rrc_eNB_S1AP.c index 59998cebcc..9f92be366b 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.c +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.c @@ -96,36 +96,34 @@ void extract_imsi(uint8_t *pdu_buf, uint32_t pdu_len, rrc_eNB_ue_context_t *ue_c && pdu_len > NAS_MESSAGE_SECURITY_HEADER_SIZE)) return; + /* Decode plain NAS message */ + EMM_msg *e_msg = &nas_msg.plain.emm; + emm_msg_header_t *emm_header = &e_msg->header; + if (header->security_header_type != SECURITY_HEADER_TYPE_NOT_PROTECTED) { /* Decode the message authentication code */ DECODE_U32((char *) pdu_buf+size, header->message_authentication_code, size); /* Decode the sequence number */ DECODE_U8((char *) pdu_buf+size, header->sequence_number, size); - } + /* Decode the security header type and the protocol discriminator */ + DECODE_U8(pdu_buf + size, *(uint8_t *)(emm_header), size); - /* Note: the value of the pointer (i.e. the address) is given by value, so we - * can modify it as we want. The callee retains the original address! */ + /* Check that this is the right message */ + if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE) + return; + } pdu_buf += size; pdu_len -= size; - /* Decode plain NAS message */ - EMM_msg *e_msg = &nas_msg.plain.emm; - emm_msg_header_t *emm_header = &e_msg->header; - /* First decode the EMM message header */ - int e_head_size = 0; /* Check that buffer contains more than only the header */ if (pdu_len <= sizeof(emm_msg_header_t)) return; - /* Decode the security header type and the protocol discriminator */ - DECODE_U8(pdu_buf + e_head_size, *(uint8_t *)(emm_header), e_head_size); + /* First decode the EMM message header */ + int e_head_size = 0; /* Decode the message type */ DECODE_U8(pdu_buf + e_head_size, emm_header->message_type, e_head_size); - /* Check that this is the right message */ - if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE) - return; - pdu_buf += e_head_size; pdu_len -= e_head_size; @@ -2284,3 +2282,75 @@ int s1ap_ue_context_release(instance_t instance, const uint32_t eNB_ue_s1ap_id) }*/ return 0; } + + +int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP) { + MessageDef *msg_p = NULL; + int e_rab = 0; + int e_rab_modify_index = 0; + int e_rab_notmodify_index = 0; + + uint8_t inde_list[ue_context_pP->ue_context.nb_of_e_rabs]; + memset(inde_list, 0, ue_context_pP->ue_context.nb_of_e_rabs*sizeof(uint8_t)); + + msg_p = itti_alloc_new_message (TASK_RRC_ENB, S1AP_E_RAB_MODIFICATION_IND); + + + S1AP_E_RAB_MODIFICATION_IND (msg_p).eNB_ue_s1ap_id = ue_context_pP->ue_context.eNB_ue_s1ap_id; + S1AP_E_RAB_MODIFICATION_IND (msg_p).mme_ue_s1ap_id = ue_context_pP->ue_context.mme_ue_s1ap_id; + + LOG_I (RRC,"E-RAB modification indication: nb nb_of_e_rabs %u status %u\n", + ue_context_pP->ue_context.nb_of_e_rabs, + ue_context_pP->ue_context.e_rab[e_rab].status); + + if (ue_context_pP->ue_context.nb_of_modify_endc_e_rabs > 0){ + S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_tobemodified = ue_context_pP->ue_context.nb_of_modify_endc_e_rabs; + for (e_rab = 0; e_rab < ue_context_pP->ue_context.setup_e_rabs ; e_rab++) { + //Add E-RAB in the list of E-RABs to be modified + if (ue_context_pP->ue_context.e_rab[e_rab].status == E_RAB_STATUS_TOMODIFY) { + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + memcpy(S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].eNB_addr.buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length); + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].eNB_addr.length = ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length; + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].gtp_teid = ue_context_pP->ue_context.gnb_gtp_endc_teid[e_rab]; + e_rab_modify_index++; + } + //Add E-RAB in the list of E-RABs NOT to be modified + else{ + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + memcpy(S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].eNB_addr.buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length); + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].eNB_addr.length = ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length; + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].gtp_teid = ue_context_pP->ue_context.gnb_gtp_endc_teid[e_rab]; + e_rab_notmodify_index++; + } + } + S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_nottobemodified = e_rab_notmodify_index; + } + + if (e_rab_modify_index > 0) { + LOG_I(RRC,"S1AP_E_RAB_MODIFICATION_IND: sending the message: nb_of_erabstobemodified %d, total e_rabs %d, index %d\n", + S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_tobemodified, ue_context_pP->ue_context.setup_e_rabs, e_rab); + MSC_LOG_TX_MESSAGE( + MSC_RRC_ENB, + MSC_S1AP_ENB, + (const char *)&S1AP_E_RAB_MODIFICATION_IND (msg_p), + sizeof(s1ap_e_rab_modification_ind_t), + MSC_AS_TIME_FMT" E RAB MODIFICATION IND UE %X eNB_ue_s1ap_id %u e_rabs:%u succ", + MSC_AS_TIME_ARGS(ctxt_pP), + ue_context_pP->ue_id_rnti, + S1AP_E_RAB_MODIFICATION_IND (msg_p).eNB_ue_s1ap_id, + e_rab_modify_index); + itti_send_msg_to_task (TASK_S1AP, ctxt_pP->instance, msg_p); + } else { + itti_free(ITTI_MSG_ORIGIN_ID(msg_p), msg_p); + } + + return 0; +} + + + diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.h b/openair2/RRC/LTE/rrc_eNB_S1AP.h index e5ff9c27d6..a55d17bfd1 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.h +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.h @@ -285,4 +285,6 @@ int rrc_eNB_send_X2AP_UE_CONTEXT_RELEASE(const protocol_ctxt_t* const ctxt_pP, r int s1ap_ue_context_release(instance_t instance, const uint32_t eNB_ue_s1ap_id); +int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP); + #endif /* RRC_ENB_S1AP_H_ */ diff --git a/openair2/RRC/NR/L2_nr_interface.c b/openair2/RRC/NR/L2_nr_interface.c index 1e8e45ef4d..0905f6d7de 100644 --- a/openair2/RRC/NR/L2_nr_interface.c +++ b/openair2/RRC/NR/L2_nr_interface.c @@ -51,9 +51,8 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, uint8_t *const buffer_pP ){ asn_enc_rval_t enc_rval; - //SRB_INFO *Srb_info; - //uint8_t Sdu_size = 0; - uint8_t sfn_msb = (uint8_t)((frameP>>4)&0x3f); + uint8_t Sdu_size = 0; + uint8_t sfn_msb = (uint8_t)((frameP>>4)&0x3f); #ifdef DEBUG_RRC LOG_D(RRC,"[eNB %d] mac_rrc_data_req to SRB ID=%ld\n",Mod_idP,Srb_id); @@ -62,11 +61,15 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, gNB_RRC_INST *rrc; rrc_gNB_carrier_data_t *carrier; NR_BCCH_BCH_Message_t *mib; + NR_SRB_INFO * srb_info; + char payload_size, *payload_pP; rrc = RC.nrrrc[Mod_idP]; carrier = &rrc->carrier; mib = &carrier->mib; + srb_info = &carrier->Srb0; + /* MIBCH */ if( (Srb_id & RAB_OFFSET ) == MIBCH) { mib->message.choice.mib->systemFrameNumber.buf[0] = sfn_msb << 2; enc_rval = uper_encode_to_buffer(&asn_DEF_NR_BCCH_BCH_Message, @@ -84,10 +87,31 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, return(3); } -//BCCH SIB1 SIBs + /* TODO BCCH SIB1 SIBs */ -//CCCH + /* CCCH */ + if( (Srb_id & RAB_OFFSET ) == CCCH) { + //struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti); + //if (ue_context_p == NULL) return(0); + //eNB_RRC_UE_t *ue_p = &ue_context_p->ue_context; + LOG_D(RRC,"[gNB %d] Frame %d CCCH request (Srb_id %ld)\n", Mod_idP, frameP, Srb_id); + + // srb_info=&ue_p->Srb0; + + payload_size = srb_info->Tx_buffer.payload_size; + + // check if data is there for MAC + if (payload_size > 0) { + payload_pP = srb_info->Tx_buffer.Payload; + LOG_D(RRC,"[gNB %d] CCCH (%p) has %d bytes (dest: %p, src %p)\n", Mod_idP, srb_info, payload_size, buffer_pP, payload_pP); + // Fill buffer + memcpy((void *)buffer_pP, (void*)payload_pP, payload_size); + Sdu_size = payload_size; + srb_info->Tx_buffer.payload_size = 0; + } + return Sdu_size; + } return(0); -} +} \ No newline at end of file diff --git a/openair2/RRC/NR/nr_rrc_defs.h b/openair2/RRC/NR/nr_rrc_defs.h index 02b4154c41..eeb16c3087 100644 --- a/openair2/RRC/NR/nr_rrc_defs.h +++ b/openair2/RRC/NR/nr_rrc_defs.h @@ -319,9 +319,10 @@ typedef struct gNB_RRC_UE_s { uint8_t nb_release_of_e_rabs; e_rab_failed_t e_rabs_release_failed[S1AP_MAX_E_RAB]; // LG: For GTPV1 TUNNELS - uint32_t enb_gtp_teid[S1AP_MAX_E_RAB]; - transport_layer_addr_t enb_gtp_addrs[S1AP_MAX_E_RAB]; - rb_id_t enb_gtp_ebi[S1AP_MAX_E_RAB]; + uint32_t gnb_gtp_teid[S1AP_MAX_E_RAB]; + transport_layer_addr_t gnb_gtp_addrs[S1AP_MAX_E_RAB]; + rb_id_t gnb_gtp_ebi[S1AP_MAX_E_RAB]; + uint32_t ul_failure_timer; uint32_t ue_release_timer; uint32_t ue_release_timer_thres; diff --git a/openair2/RRC/NR/nr_rrc_proto.h b/openair2/RRC/NR/nr_rrc_proto.h index 5770b80595..317282c814 100644 --- a/openair2/RRC/NR/nr_rrc_proto.h +++ b/openair2/RRC/NR/nr_rrc_proto.h @@ -65,9 +65,9 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( struct rrc_gNB_ue_context_s *rrc_gNB_allocate_new_UE_context(gNB_RRC_INST *rrc_instance_pP); -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList); +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t * cg_config_info); -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p); +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m); void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, NR_CellGroupConfig_t *secondaryCellGroup, @@ -89,7 +89,7 @@ int generate_CG_Config(gNB_RRC_INST *rrc, NR_RRCReconfiguration_t *reconfig, NR_RadioBearerConfig_t *rbconfig); -int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo); +int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m); diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index 5ece5f9169..1f341cfdf9 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -95,12 +95,10 @@ mui_t rrc_gNB_mui = 0; void openair_nr_rrc_on(const protocol_ctxt_t *const ctxt_pP) { LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" gNB:OPENAIR NR RRC IN....\n",PROTOCOL_NR_RRC_CTXT_ARGS(ctxt_pP)); - rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.SI, BCCH, 1); RC.nrrrc[ctxt_pP->module_id]->carrier.SI.Active = 1; rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0, CCCH, 1); RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0.Active = 1; - } ///---------------------------------------------------------------------------------------------------------------/// @@ -173,7 +171,6 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ue_context_pP->ue_context.primaryCC_id, physicalCellGroupConfig, physicalcellgroup_config); - do_SpCellConfig(RC.nrrrc[ctxt_pP->module_id], spCellConfig); } @@ -182,57 +179,47 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ///---------------------------------------------------------------------------------------------------------------/// static void init_NR_SI(gNB_RRC_INST *rrc) { - - LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__); - - - - rrc->carrier.MIB = (uint8_t*) malloc16(4); + rrc->carrier.MIB = (uint8_t *) malloc16(4); rrc->carrier.sizeof_MIB = do_MIB_NR(rrc,0); - - LOG_I(NR_RRC,"Done init_NR_SI\n"); - - rrc_mac_config_req_gNB(rrc->module_id, - rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.ssb_SubcarrierOffset, rrc->carrier.pdsch_AntennaPorts, (NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon, - 0, - 0, - (NR_CellGroupConfig_t *)NULL - ); + 0, + 0, // WIP hardcoded rnti + (NR_CellGroupConfig_t *)NULL + ); - - if (get_softmodem_params()->phy_test > 0) { + if (get_softmodem_params()->phy_test > 0 || get_softmodem_params()->do_ra > 0) { // This is for phytest only, emulate first X2 message if uecap.raw file is present FILE *fd; - fd = fopen("uecap.raw","r"); + if (fd != NULL) { char buffer[4096]; int msg_len=fread(buffer,1,4096,fd); LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message; - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, - (uint8_t *)buffer, - msg_len); - + &asn_DEF_LTE_UL_DCCH_Message, + (void **)<E_UL_DCCH_Message, + (uint8_t *)buffer, + msg_len); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); - return; - } + // free the memory + SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + return; + } + fclose(fd); xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); // recreate enough of X2 EN-DC Container AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, - "ueCapabilityInformation not present\n"); + "ueCapabilityInformation not present\n"); NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); @@ -240,42 +227,37 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); - asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void *)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)buffer, - (enc_rval.encoded+7)>>3); - parse_CG_ConfigInfo(rrc,CG_ConfigInfo); - } - else { + (const char *)buffer, + (enc_rval.encoded+7)>>3); + parse_CG_ConfigInfo(rrc,CG_ConfigInfo,NULL); + } else { struct rrc_gNB_ue_context_s *ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); - - LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); - rrc_add_nsa_user(rrc,ue_context_p); - } + LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); + rrc_add_nsa_user(rrc,ue_context_p,NULL); + } } } char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigurationReq *configuration) { protocol_ctxt_t ctxt; - gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gnb_mod_idP, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,gnb_mod_idP); - LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Init...\n", PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); + AssertFatal(rrc != NULL, "RC.nrrrc not initialized!"); AssertFatal(NUMBER_OF_UE_MAX < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow"); AssertFatal(configuration!=NULL,"configuration input is null\n"); rrc->module_id = gnb_mod_idP; rrc->Nb_ue = 0; - rrc->carrier.Srb0.Active = 0; - nr_uid_linear_allocator_init(&rrc->uid_allocator); RB_INIT(&rrc->rrc_ue_head); rrc->initial_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); @@ -285,7 +267,6 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu rrc->carrier.pdsch_AntennaPorts = configuration->pdsch_AntennaPorts; /// System Information INIT LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Checking release \n",PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); - init_NR_SI(rrc); rrc_init_nr_global_param(); openair_nr_rrc_on(&ctxt); @@ -294,49 +275,26 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + asn_dec_rval_t dec_rval = uper_decode_complete(NULL, + &asn_DEF_NR_CG_ConfigInfo, + (void **)&cg_configinfo, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); + gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); + return; + } - LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; - - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size);//m->rrc_buffer_size); - -/* asn_dec_rval_t dec_rval = uper_decode( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size, 0, 0);//m->rrc_buffer_size); -*/ - gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; - - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); - return; - } - xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); - // recreate enough of X2 EN-DC Container - AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, - "ueCapabilityInformation not present\n"); - NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); - CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); - CG_ConfigInfo->criticalExtensions.choice.c1->present = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); - NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; - cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); - asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size); - AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)m->rrc_buffer, - (enc_rval.encoded+7)>>3); - parse_CG_ConfigInfo(rrc,CG_ConfigInfo); - + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); + // recreate enough of X2 EN-DC Container + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, + "ueCapabilityInformation not present\n"); + parse_CG_ConfigInfo(rrc,cg_configinfo,m); } ///---------------------------------------------------------------------------------------------------------------/// @@ -434,16 +392,15 @@ void *rrc_gnb_task(void *args_p) { openair_rrc_gNB_configuration(GNB_INSTANCE_TO_MODULE_ID(instance), &NRRRC_CONFIGURATION_REQ(msg_p)); break; - /* Messages from X2AP */ + /* Messages from X2AP */ case X2AP_ENDC_SGNB_ADDITION_REQ: - LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); - rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); - break; + LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); + rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); + break; case X2AP_ENDC_SGNB_RECONF_COMPLETE: - LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); - break; - + LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); + break; default: LOG_E(NR_RRC, "[gNB %d] Received unexpected message %s\n", instance, msg_name_p); diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 581015db56..cacff5cf5c 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -38,48 +38,49 @@ #include "LTE_UE-CapabilityRAT-ContainerList.h" #include "NR_CG-Config.h" -int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo) { - +int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m) { if (CG_ConfigInfo->criticalExtensions.present == NR_CG_ConfigInfo__criticalExtensions_PR_c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo) { - NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; - if (cg_ConfigInfo->ue_CapabilityInfo) { - // Decode UE-CapabilityRAT-ContainerList + NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; + + if (cg_ConfigInfo->ue_CapabilityInfo) { + // Decode UE-CapabilityRAT-ContainerList LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList=NULL; - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, - (void**)&UE_CapabilityRAT_ContainerList, - cg_ConfigInfo->ue_CapabilityInfo->buf, - cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + UE_CapabilityRAT_ContainerList = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, + (void **)&UE_CapabilityRAT_ContainerList, + cg_ConfigInfo->ue_CapabilityInfo->buf, + cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); - } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList); - } - if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); - } - else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); - } - else { + AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); + } + + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); + } + + if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); + } else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); + } else { LOG_E(RRC,"c1 extension not found, returning\n"); - return(-1); + return(-1); } } else { LOG_E(RRC,"Ignoring unknown CG_ConfigInfo extensions\n"); return(-1); } - return(0); + + return(0); } -int generate_CG_Config(gNB_RRC_INST *rrc, - NR_CG_Config_t *cg_Config, - NR_RRCReconfiguration_t *reconfig, - NR_RadioBearerConfig_t *rbconfig) { - - +int generate_CG_Config(gNB_RRC_INST *rrc, + NR_CG_Config_t *cg_Config, + NR_RRCReconfiguration_t *reconfig, + NR_RadioBearerConfig_t *rbconfig) { cg_Config->criticalExtensions.present = NR_CG_Config__criticalExtensions_PR_c1; cg_Config->criticalExtensions.choice.c1 = calloc(1,sizeof(*cg_Config->criticalExtensions.choice.c1)); cg_Config->criticalExtensions.choice.c1->present = NR_CG_Config__criticalExtensions__c1_PR_cg_Config; @@ -91,36 +92,37 @@ int generate_CG_Config(gNB_RRC_INST *rrc, enc_rval.failed_type->name, enc_rval.encoded); cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig = calloc(1,sizeof(OCTET_STRING_t)); OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); total_size = (enc_rval.encoded+7)>>3; - LOG_I(RRC,"Dumping NR_RRCReconfiguration message (%jd bytes)\n",(enc_rval.encoded+7)>>3); - for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { + + for (int i=0; i<(enc_rval.encoded+7)>>3; i++) { printf("%02x",((uint8_t *)buffer)[i]); } + printf("\n"); FILE *fd = fopen("reconfig.raw","w"); - fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); fclose(fd); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, NULL, (void *)rbconfig, buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config = calloc(1,sizeof(OCTET_STRING_t)); OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); LOG_I(RRC,"Dumping scg_RB_Config message (%jd bytes)\n",(enc_rval.encoded+7)>>3); - for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { - printf("%02x",((uint8_t*)buffer)[i]); + + for (int i=0; i<(enc_rval.encoded+7)>>3; i++) { + printf("%02x",((uint8_t *)buffer)[i]); } + printf("\n"); fd = fopen("rbconfig.raw","w"); - fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); fclose(fd); total_size = total_size + ((enc_rval.encoded+7)>>3); - return(total_size); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 763c208dfe..22e31aa48a 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -37,122 +37,211 @@ #include "LTE_UE-CapabilityRAT-ContainerList.h" #include "NR_CG-Config.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" +#include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" +#include "executables/softmodem-common.h" +#include -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) { - +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; + OCTET_STRING_t *ueCapabilityRAT_Container_nr=NULL; OCTET_STRING_t *ueCapabilityRAT_Container_MRDC=NULL; + asn_dec_rval_t dec_rval; int list_size=0; + AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n"); AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count); - for (int i=0;ilist.array[i]->rat_Type == LTE_RAT_Type_nr) ueCapabilityRAT_Container_nr = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; else if (UE_CapabilityRAT_ContainerList->list.array[i]->rat_Type == LTE_RAT_Type_eutra_nr) ueCapabilityRAT_Container_MRDC = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; - } + } - AssertFatal(ueCapabilityRAT_Container_nr!=NULL,"ueCapabilityRAT_Container_nr is NULL\n"); - AssertFatal(ueCapabilityRAT_Container_MRDC!=NULL,"ueCapabilityRAT_Container_MRDC is NULL\n"); // decode and store capabilities ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); - - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_NR_UE_NR_Capability, - (void **)&ue_context_p->ue_context.UE_Capability_nr, - ueCapabilityRAT_Container_nr->buf, - ueCapabilityRAT_Container_nr->size, 0, 0); - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); + if (ueCapabilityRAT_Container_nr != NULL) { + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_NR_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_nr, + ueCapabilityRAT_Container_nr->buf, + ueCapabilityRAT_Container_nr->size, 0, 0); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); ue_context_p->ue_context.UE_Capability_nr = 0; AssertFatal(1==0,"exiting\n"); + } } - dec_rval = uper_decode(NULL, - &asn_DEF_NR_UE_MRDC_Capability, - (void **)&ue_context_p->ue_context.UE_Capability_MRDC, - ueCapabilityRAT_Container_MRDC->buf, - ueCapabilityRAT_Container_MRDC->size, 0, 0); + if (ueCapabilityRAT_Container_MRDC != NULL) { + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_MRDC_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_MRDC, + ueCapabilityRAT_Container_MRDC->buf, + ueCapabilityRAT_Container_MRDC->size, 0, 0); - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); ue_context_p->ue_context.UE_Capability_MRDC = 0; AssertFatal(1==0,"exiting\n"); + } } // dump ue_capabilities - if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { - xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); - } + if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_nr != NULL) ) { + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } - if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { - xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); - } + if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) { + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } - rrc_add_nsa_user(rrc,ue_context_p); + if(cg_config_info && cg_config_info->mcg_RB_Config) { + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void **)&ue_context_p->ue_context.rb_config, + cg_config_info->mcg_RB_Config->buf, + cg_config_info->mcg_RB_Config->size, 0, 0); + + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_config_info->mcg_RB_Config->size); + } + } + + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void *)ue_context_p->ue_context.rb_config); + rrc_add_nsa_user(rrc,ue_context_p, m); } -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p) { - -// generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) +/* generate prototypes for the tree management functions (RB_INSERT used in rrc_add_nsa_user) */ +RB_PROTOTYPE(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s, entries, + rrc_gNB_compare_ue_rnti_id); +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { + // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) rrc_gNB_carrier_data_t *carrier=&rrc->carrier; - MessageDef *msg; msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); - -// NR RRCReconfiguration - + gtpv1u_enb_create_tunnel_req_t create_tunnel_req; + gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp; + protocol_ctxt_t ctxt; + // NR RRCReconfiguration AssertFatal(rrc->Nb_ue < MAX_NR_RRC_UE_CONTEXTS,"cannot add another UE\n"); - ue_context_p->ue_context.reconfig = calloc(1,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_context.secondaryCellGroup = calloc(1,sizeof(NR_CellGroupConfig_t)); - memset((void*)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); + memset((void *)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_context.reconfig->rrc_TransactionIdentifier=0; ue_context_p->ue_context.reconfig->criticalExtensions.present = NR_RRCReconfiguration__criticalExtensions_PR_rrcReconfiguration; NR_RRCReconfiguration_IEs_t *reconfig_ies=calloc(1,sizeof(NR_RRCReconfiguration_IEs_t)); ue_context_p->ue_context.reconfig->criticalExtensions.choice.rrcReconfiguration = reconfig_ies; carrier->initial_csi_index[rrc->Nb_ue] = 0; + if (get_softmodem_params()->phy_test == 1 || get_softmodem_params()->do_ra == 1){ + ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); + fill_default_rbconfig(ue_context_p->ue_context.rb_config); + } fill_default_reconfig(carrier->servingcellconfigcommon, - reconfig_ies, - ue_context_p->ue_context.secondaryCellGroup, - carrier->pdsch_AntennaPorts, - carrier->initial_csi_index[rrc->Nb_ue]); - - ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - - fill_default_rbconfig(ue_context_p->ue_context.rb_config); + reconfig_ies, + ue_context_p->ue_context.secondaryCellGroup, + carrier->pdsch_AntennaPorts, + carrier->initial_csi_index[rrc->Nb_ue]); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); - memset((void*)CG_Config,0,sizeof(*CG_Config)); - int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + memset((void *)CG_Config,0,sizeof(*CG_Config)); + //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + + if(m!=NULL) { + uint8_t inde_list[m->nb_e_rabs_tobeadded]; + memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); + + if (m->nb_e_rabs_tobeadded>0) { + for (int i=0; inb_e_rabs_tobeadded; i++) { + // Add the new E-RABs at the corresponding rrc ue context of the gNB + ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; + ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; + memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); + ue_context_p->ue_context.nb_of_e_rabs++; + //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW + create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; + memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); + inde_list[i] = i; + LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_req.sgw_addr[i].buffer[0], + create_tunnel_req.sgw_addr[i].buffer[1], + create_tunnel_req.sgw_addr[i].buffer[2], + create_tunnel_req.sgw_addr[i].buffer[3], + create_tunnel_req.sgw_addr[i].length, + create_tunnel_req.sgw_S1u_teid[i]); + } + + create_tunnel_req.rnti = ue_context_p->ue_id_rnti; + create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; + RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); + gtpv1u_create_s1u_tunnel( + ctxt.instance, + &create_tunnel_req, + &create_tunnel_resp); + rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + &ctxt, + &create_tunnel_resp, + &inde_list[0]); + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; + + for(int i=0; iue_context.nb_of_e_rabs; i++) { + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); + //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; + LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_resp.enb_addr.buffer[0], + create_tunnel_resp.enb_addr.buffer[1], + create_tunnel_resp.enb_addr.buffer[2], + create_tunnel_resp.enb_addr.buffer[3], + create_tunnel_resp.enb_addr.length, + create_tunnel_resp.enb_S1u_teid[i]); + LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); + } + } else + LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); + } //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size // Send to X2 entity to transport to MeNB asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_Config, - NULL, - (void *)CG_Config, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, - 1024); - + NULL, + (void *)CG_Config, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, + 1024); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = (enc_rval.encoded+7)>>3; - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(0), msg); //Check right id instead of hardcoding - rrc->Nb_ue++; // configure MAC and RLC rrc_mac_config_req_gNB(rrc->module_id, - rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.ssb_SubcarrierOffset, rrc->carrier.pdsch_AntennaPorts, - NULL, - 1, // add_ue flag - ue_context_p->ue_id_rnti, - ue_context_p->ue_context.secondaryCellGroup); + NULL, + 1, // add_ue flag + ue_context_p->ue_id_rnti, + ue_context_p->ue_context.secondaryCellGroup); } diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 1df17a19aa..a7aa38dfe3 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -49,23 +49,19 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, - NR_CellGroupConfig_t *secondaryCellGroup, - int scg_id, - int servCellIndex, - int n_physical_antenna_ports, - int initial_csi_index) { + NR_CellGroupConfig_t *secondaryCellGroup, + int scg_id, + int servCellIndex, + int n_physical_antenna_ports, + int initial_csi_index) { AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); - memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t)); secondaryCellGroup->cellGroupId = scg_id; - NR_RLC_BearerConfig_t *RLC_BearerConfig = calloc(1,sizeof(*RLC_BearerConfig)); - RLC_BearerConfig->logicalChannelIdentity = 4; RLC_BearerConfig->servedRadioBearer = calloc(1,sizeof(*RLC_BearerConfig->servedRadioBearer)); - RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; - + RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; RLC_BearerConfig->servedRadioBearer->choice.drb_Identity=1; RLC_BearerConfig->reestablishRLC=calloc(1,sizeof(*RLC_BearerConfig->reestablishRLC)); *RLC_BearerConfig->reestablishRLC=NR_RLC_BearerConfig__reestablishRLC_true; @@ -73,17 +69,15 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco RLC_BearerConfig->rlc_Config->present = NR_RLC_Config_PR_am; RLC_BearerConfig->rlc_Config->choice.am = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am)); RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength)); - *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; + *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.t_PollRetransmit = NR_T_PollRetransmit_ms45; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollPDU = NR_PollPDU_p64; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollByte = NR_PollByte_kB500; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.maxRetxThreshold = NR_UL_AM_RLC__maxRetxThreshold_t32; - RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength)); *RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_Reassembly = NR_T_Reassembly_ms15; RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_StatusProhibit = NR_T_StatusProhibit_ms15; - RLC_BearerConfig->mac_LogicalChannelConfig = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig)); RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters)); RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->priority = 1; @@ -99,10 +93,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_Mask = false; RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_DelayTimerApplied = false; RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->bitRateQueryProhibitTimer = NULL; - secondaryCellGroup->rlc_BearerToAddModList = calloc(1,sizeof(*secondaryCellGroup->rlc_BearerToAddModList)); ASN_SEQUENCE_ADD(&secondaryCellGroup->rlc_BearerToAddModList->list, RLC_BearerConfig); - secondaryCellGroup->mac_CellGroupConfig=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig)); secondaryCellGroup->mac_CellGroupConfig->drx_Config = NULL; secondaryCellGroup->mac_CellGroupConfig->schedulingRequestConfig = NULL; @@ -126,25 +118,20 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real; - secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false; secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL; - - secondaryCellGroup->physicalCellGroupConfig = calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig)); - secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH=NULL; secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUSCH=NULL; secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1)); *secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=20; - secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; + secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; secondaryCellGroup->physicalCellGroupConfig->tpc_SRS_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->tpc_PUCCH_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->tpc_PUSCH_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->sp_CSI_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->cs_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->ext1=NULL; - secondaryCellGroup->spCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig)); secondaryCellGroup->spCellConfig->servCellIndex = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->servCellIndex)); *secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex; @@ -154,7 +141,26 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; - + /* contention free ra */ + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = calloc(1,sizeof(struct NR_ReconfigurationWithSync__rach_ConfigDedicated)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->present= NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink= calloc(1,sizeof(struct NR_RACH_ConfigDedicated)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra= calloc(1,sizeof(struct NR_CFRA)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->ra_Prioritization= NULL; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions= calloc(1,sizeof(struct NR_CFRA__occasions)); + memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric, + &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t)); + //secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= calloc(1,sizeof(long)); + //*secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion = NR_CFRA__occasions__ssb_perRACH_Occasion_one; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= NULL; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.present = NR_CFRA__resources_PR_ssb; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb = calloc(1,sizeof(struct NR_CFRA__resources__ssb)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ra_ssb_OccasionMaskIndex = 0; + struct NR_CFRA_SSB_Resource *ssbElem = calloc(1,sizeof(struct NR_CFRA_SSB_Resource)); + ssbElem->ssb = 0; + ssbElem->ra_PreambleIndex= 63; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list,ssbElem); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->ext1 = NULL; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->present = NR_SetupRelease_RLF_TimersAndConstants_PR_setup; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup)); @@ -163,21 +169,18 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->n311 = NR_RLF_TimersAndConstants__n311_n1; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1 = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1->t311_v1530 = NR_RLF_TimersAndConstants__ext1__t311_v1530_ms30000; - secondaryCellGroup->spCellConfig->rlmInSyncOutOfSyncThreshold = NULL; - - - secondaryCellGroup->spCellConfig->spCellConfigDedicated = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->tdd_UL_DL_ConfigurationDedicated = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdcch_Config=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); @@ -190,6 +193,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); @@ -351,10 +355,11 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tci15->qcl_Type1.referenceSignal.choice.ssb = 7; tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); +#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -379,6 +384,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = NULL; +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -389,6 +396,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; +#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); @@ -407,17 +415,45 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); + NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); + coreset->controlResourceSetId=1; + // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, + coreset->frequencyDomainResources.buf = calloc(1,6); + coreset->frequencyDomainResources.buf[0] = 0xff; + coreset->frequencyDomainResources.buf[1] = 0xff; + coreset->frequencyDomainResources.buf[2] = 0; + coreset->frequencyDomainResources.buf[3] = 0; + coreset->frequencyDomainResources.buf[4] = 0; + coreset->frequencyDomainResources.buf[5] = 0; + coreset->frequencyDomainResources.size = 6; + coreset->frequencyDomainResources.bits_unused = 3; + coreset->duration=1; + coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; + coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; + + coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); + NR_TCI_StateId_t *tci[8]; + for (int i=0;i<8;i++) { + tci[i]=calloc(1,sizeof(*tci[i])); + *tci[i] = i; + ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); + } + coreset->tci_StatesPDCCH_ToReleaseList = NULL; + coreset->tci_PresentInDCI = NULL; + coreset->pdcch_DMRS_ScramblingID = NULL; + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); ss->searchSpaceId = 1; ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); - *ss->controlResourceSetId=0; + *ss->controlResourceSetId=1; ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; ss->duration=NULL; @@ -474,64 +510,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); - NR_ControlResourceSet_t *coreset0 = calloc(1,sizeof(*coreset0)); - coreset0->controlResourceSetId=1; - // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, - coreset0->frequencyDomainResources.buf = calloc(1,6); - coreset0->frequencyDomainResources.buf[0] = 0xff; - coreset0->frequencyDomainResources.buf[1] = 0xff; - coreset0->frequencyDomainResources.buf[2] = 0; - coreset0->frequencyDomainResources.buf[3] = 0; - coreset0->frequencyDomainResources.buf[4] = 0; - coreset0->frequencyDomainResources.buf[5] = 0; - coreset0->frequencyDomainResources.size = 6; - coreset0->frequencyDomainResources.bits_unused = 3; - coreset0->duration=1; - coreset0->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset0->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - coreset0->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset0->tci_StatesPDCCH_ToAddList)); - NR_TCI_StateId_t *tci[8]; - for (int i=0;i<8;i++) { - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset0->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - coreset0->tci_StatesPDCCH_ToReleaseList = NULL; - coreset0->tci_PresentInDCI = NULL; - coreset0->pdcch_DMRS_ScramblingID = NULL; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, - coreset0); + coreset); bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); - NR_SearchSpace_t *ss3 = calloc(1,sizeof(*ss3)); + NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); - ss3->searchSpaceId=3; - ss3->controlResourceSetId=calloc(1,sizeof(*ss3->controlResourceSetId)); - *ss3->controlResourceSetId=1; - ss3->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss3->monitoringSlotPeriodicityAndOffset)); - ss3->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss3->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; - ss3->duration=NULL; - ss3->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss3->monitoringSymbolsWithinSlot)); - ss3->monitoringSymbolsWithinSlot->buf = calloc(1,2); - ss3->monitoringSymbolsWithinSlot->size = 2; - ss3->monitoringSymbolsWithinSlot->bits_unused = 2; - ss3->monitoringSymbolsWithinSlot->buf[0]=0xc0; - ss3->monitoringSymbolsWithinSlot->buf[1]=0x0; - ss3->nrofCandidates=calloc(1,sizeof(*ss3->nrofCandidates)); - ss3->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss3->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss3->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; - ss3->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss3->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss3->searchSpaceType=calloc(1,sizeof(*ss3->searchSpaceType)); - ss3->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; - ss3->searchSpaceType->choice.common = calloc(1,sizeof(*ss3->searchSpaceType->choice.common)); - ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0=calloc(1,sizeof(*ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); - ss3->searchSpaceType->choice.common->dci_Format2_0=NULL; - ss3->searchSpaceType->choice.common->dci_Format2_2=NULL; - ss3->searchSpaceType->choice.common->dci_Format2_3=NULL; ss2->searchSpaceId=2; ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); @@ -555,10 +540,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); - ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; + ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_1_And_1_1; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, - ss3); ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, ss2); @@ -572,6 +555,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; @@ -583,6 +567,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL; +#if 0 bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); @@ -744,10 +730,11 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); +#endif bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -773,7 +760,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -798,6 +785,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig = NULL; +#if 0 bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -808,6 +797,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; +#endif ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); @@ -816,6 +806,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = calloc(1, sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = 1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); @@ -833,7 +825,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; NR_DMRS_UplinkConfig->dmrs_Type = NULL; - NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; + NR_DMRS_UplinkConfig->dmrs_AdditionalPosition = calloc(1,sizeof(*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition)); + *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition = NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; NR_DMRS_UplinkConfig->maxLength=NULL; NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); @@ -1103,7 +1096,19 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig)); + NR_PUSCH_ServingCellConfig_t *pusch_scc = calloc(1,sizeof(*pusch_scc)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->present = NR_SetupRelease_PUSCH_ServingCellConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup = pusch_scc; + pusch_scc->codeBlockGroupTransmission = NULL; + pusch_scc->rateMatching = NULL; + pusch_scc->xOverhead = NULL; + pusch_scc->ext1=calloc(1,sizeof(*pusch_scc->ext1)); + pusch_scc->ext1->maxMIMO_Layers = calloc(1,sizeof(*pusch_scc->ext1->maxMIMO_Layers)); + *pusch_scc->ext1->maxMIMO_Layers = 1; + pusch_scc->ext1->processingType2Enabled = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; @@ -1123,12 +1128,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=NULL; + //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; +// secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); @@ -1668,7 +1674,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=276; + imres0->freqBand->nrofRBs=106; imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; imres0->periodicityAndOffset->choice.slots320 = 2; @@ -1742,7 +1748,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); csires11->bwp_Id = 1; csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); csires10->csi_ResourceConfigId=10; @@ -1755,7 +1761,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); csires10->bwp_Id = 1; csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); csires2->csi_ResourceConfigId=2; @@ -1768,7 +1774,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); csires2->bwp_Id = 1; csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); csires3->csi_ResourceConfigId=3; @@ -1781,7 +1787,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); csires3->bwp_Id = 1; csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); csires4->csi_ResourceConfigId=4; @@ -1794,7 +1800,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); csires4->bwp_Id = 1; csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); csires5->csi_ResourceConfigId=5; @@ -1807,7 +1813,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); csires5->bwp_Id = 1; csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); csires6->csi_ResourceConfigId=6; @@ -1820,7 +1826,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); csires6->bwp_Id = 1; csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); csires7->csi_ResourceConfigId=7; @@ -1833,7 +1839,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); csires7->bwp_Id = 1; csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); csires8->csi_ResourceConfigId=8; @@ -1846,7 +1852,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); csires8->bwp_Id = 1; csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); csires9->csi_ResourceConfigId=9; @@ -1859,7 +1865,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); csires9->bwp_Id = 1; csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; @@ -2005,30 +2011,26 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco } void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon, - NR_RRCReconfiguration_IEs_t *reconfig, - NR_CellGroupConfig_t *secondaryCellGroup, - int n_physical_antenna_ports, - int initial_csi_index) { - + NR_RRCReconfiguration_IEs_t *reconfig, + NR_CellGroupConfig_t *secondaryCellGroup, + int n_physical_antenna_ports, + int initial_csi_index) { AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); AssertFatal(reconfig!=NULL,"reconfig is null\n"); AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); - // radioBearerConfig reconfig->radioBearerConfig=NULL; // secondaryCellGroup - fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); + fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index); xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); char scg_buffer[1024]; asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); - - reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup)); OCTET_STRING_fromBuf(reconfig->secondaryCellGroup, - (const char*)scg_buffer, - (enc_rval.encoded+7)>>3); + (const char *)scg_buffer, + (enc_rval.encoded+7)>>3); // measConfig reconfig->measConfig=NULL; // lateNonCriticalExtension @@ -2060,15 +2062,15 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { drb_ToAddMod->pdcp_Config->drb->headerCompression.present = NR_PDCP_Config__drb__headerCompression_PR_notUsed; drb_ToAddMod->pdcp_Config->drb->headerCompression.choice.notUsed = 0; - drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL; - drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL; + drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL; + drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL; drb_ToAddMod->pdcp_Config->drb->outOfOrderDelivery=NULL; drb_ToAddMod->pdcp_Config->moreThanOneRLC = NULL; drb_ToAddMod->pdcp_Config->t_Reordering = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->t_Reordering)); *drb_ToAddMod->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0; drb_ToAddMod->pdcp_Config->ext1 = NULL; - + ASN_SEQUENCE_ADD(&rbconfig->drb_ToAddModList->list,drb_ToAddMod); rbconfig->drb_ToReleaseList = NULL; @@ -2082,4 +2084,5 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); } + #endif diff --git a/openair2/RRC/NR_UE/L2_interface_ue.c b/openair2/RRC/NR_UE/L2_interface_ue.c index cb8ded1971..08976522b0 100644 --- a/openair2/RRC/NR_UE/L2_interface_ue.c +++ b/openair2/RRC/NR_UE/L2_interface_ue.c @@ -56,4 +56,15 @@ nr_mac_rrc_data_ind_ue( return(0); +} + +int8_t mac_rrc_nr_data_req_ue(const module_id_t Mod_idP, + const int CC_id, + const frame_t frameP, + const rb_id_t Srb_id, + uint8_t *const buffer_pP ){ + + // todo + + return 0; } \ No newline at end of file diff --git a/openair2/RRC/NR_UE/rrc_UE.c b/openair2/RRC/NR_UE/rrc_UE.c index 87e899845e..44215df218 100755 --- a/openair2/RRC/NR_UE/rrc_UE.c +++ b/openair2/RRC/NR_UE/rrc_UE.c @@ -42,7 +42,7 @@ #include "rrc_defs.h" #include "rrc_proto.h" #include "rrc_vars.h" -#include "mac_proto.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" #include "executables/softmodem-common.h" @@ -319,7 +319,7 @@ NR_UE_RRC_INST_t* openair_rrc_top_init_ue_nr(char* rrc_config_path){ RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ResourceConfig_list, NR_maxNrofCSI_ResourceConfigurations); RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ReportConfig_list, NR_maxNrofCSI_ReportConfigurations); - if (get_softmodem_params()->phy_test==1) { + if (get_softmodem_params()->phy_test==1 || get_softmodem_params()->do_ra==1) { // read in files for RRCReconfiguration and RBconfig FILE *fd; char filename[1024]; diff --git a/openair2/RRC/NR_UE/rrc_defs.h b/openair2/RRC/NR_UE/rrc_defs.h index cb1207757d..6481fb0cea 100644 --- a/openair2/RRC/NR_UE/rrc_defs.h +++ b/openair2/RRC/NR_UE/rrc_defs.h @@ -39,8 +39,8 @@ #include "platform_types.h" -#include "LAYER2/NR_MAC_UE/mac.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac.h" +#include "NR_MAC_UE/mac.h" +#include "NR_MAC_COMMON/nr_mac.h" #include "rrc_list.h" #include "NR_asn_constant.h" #include "NR_MeasConfig.h" diff --git a/openair2/RRC/NR_UE/rrc_proto.h b/openair2/RRC/NR_UE/rrc_proto.h index 6e0d0a10de..7bc7e4b90c 100644 --- a/openair2/RRC/NR_UE/rrc_proto.h +++ b/openair2/RRC/NR_UE/rrc_proto.h @@ -102,6 +102,18 @@ int8_t nr_rrc_ue_decode_NR_DL_DCCH_Message(const module_id_t module_id, const ui \param pdu_len data length of pdu*/ int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const channel_t channel, const uint8_t* pduP, const sdu_size_t pdu_len); +/**\brief + \param module_id module id + \param CC_id component carrier id + \param frame_t frameP + \param rb_id_t SRB id + \param buffer_pP pointer to buffer*/ +int8_t mac_rrc_nr_data_req_ue(const module_id_t Mod_idP, + const int CC_id, + const frame_t frameP, + const rb_id_t Srb_id, + uint8_t *const buffer_pP); + /** @}*/ #endif diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c index b297c96e56..6a037b8ee3 100644 --- a/openair2/X2AP/x2ap_eNB.c +++ b/openair2/X2AP/x2ap_eNB.c @@ -454,10 +454,12 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; int ue_id; - - /* TODO: remove hardcoded value */ - x2ap_eNB_data = x2ap_is_eNB_id_in_list(3584); + LTE_PhysCellId_t target_pci; + target_pci = x2ap_ENDC_sgnb_addition_req->target_physCellId; + x2ap_eNB_data = x2ap_is_eNB_pci_in_list(target_pci); DevAssert(x2ap_eNB_data != NULL); + DevAssert(x2ap_ENDC_sgnb_addition_req != NULL); + instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); @@ -474,7 +476,8 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req->rnti, ue_id, -1); x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_NSA_PREPARE); - x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_eNB_data, ue_id); + x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req, + x2ap_eNB_data, ue_id); } static @@ -489,16 +492,31 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, * as far as I understand.. CROUX */ - + x2ap_id_manager *id_manager; x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *target; - /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; int ue_id; + /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; int id_source; int id_target;*/ instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); + target = x2ap_get_eNB(NULL,x2ap_ENDC_sgnb_addition_req_ACK->target_assoc_id, 0); + DevAssert(target != NULL); + + /* allocate x2ap ID */ + id_manager = &instance_p->id_manager; + ue_id = x2ap_allocate_new_id(id_manager); + if (ue_id == -1) { + X2AP_ERROR("could not allocate a new X2AP UE ID\n"); + exit(1); + } + /* id_source is ue_id, id_target is unknown yet */ + x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req_ACK->rnti, ue_id, + x2ap_ENDC_sgnb_addition_req_ACK->MeNB_ue_x2_id); + x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_SOURCE_OVERALL); + /*target = x2ap_get_eNB(NULL, source_assoc_id, 0); DevAssert(target != NULL);*/ @@ -511,10 +529,36 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, x2ap_set_ids(&instance_p->id_manager, ue_id, x2ap_handover_req_ack->rnti, id_source, id_target);*/ - //target = x2ap_get_eNB(NULL, 17, 0); - target = x2ap_is_eNB_id_in_list (3585); //Currently hardcoded. Need to extract it differently + x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, + x2ap_ENDC_sgnb_addition_req_ACK, ue_id); +} + +/** + * @fn : Function triggers sgnb reconfiguration complete + * @param : IN instance, IN x2ap_reconf_complete +**/ +static +void x2ap_eNB_trigger_sgnb_reconfiguration_complete(instance_t instance, + x2ap_ENDC_reconf_complete_t *x2ap_reconf_complete) +{ + x2ap_eNB_instance_t *instance_p = NULL; + x2ap_eNB_data_t *target = NULL; + int id_source = -1; + int id_target = -1; + LTE_PhysCellId_t target_pci; + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + DevAssert(x2ap_reconf_complete != NULL); + + target_pci = x2ap_reconf_complete->target_physCellId; + target = x2ap_is_eNB_pci_in_list(target_pci); DevAssert(target != NULL); - x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, x2ap_ENDC_sgnb_addition_req_ACK, 0); + + id_source = x2ap_reconf_complete->MeNB_ue_x2_id; + id_target = x2ap_reconf_complete->SgNB_ue_x2_id; + x2ap_eNB_generate_ENDC_x2_SgNB_reconfiguration_complete(instance_p, target, id_source, id_target); + } @@ -594,6 +638,10 @@ void *x2ap_task(void *arg) { LOG_I(X2AP, "Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK \n"); break; + case X2AP_ENDC_SGNB_RECONF_COMPLETE: + x2ap_eNB_trigger_sgnb_reconfiguration_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &X2AP_ENDC_SGNB_RECONF_COMPLETE(received_msg)); + break; case SCTP_INIT_MSG_MULTI_CNF: x2ap_eNB_handle_sctp_init_msg_multi_cnf(ITTI_MESSAGE_GET_INSTANCE(received_msg), &received_msg->ittiMsg.sctp_init_msg_multi_cnf); diff --git a/openair2/X2AP/x2ap_eNB_decoder.c b/openair2/X2AP/x2ap_eNB_decoder.c index 93b82c2765..3762bc06dc 100644 --- a/openair2/X2AP/x2ap_eNB_decoder.c +++ b/openair2/X2AP/x2ap_eNB_decoder.c @@ -144,9 +144,9 @@ int x2ap_eNB_decode_pdu(X2AP_X2AP_PDU_t *pdu, const uint8_t *const buffer, uint3 length, 0, 0); - //if (asn1_xer_print) { + if (asn1_xer_print) { xer_fprint(stdout, &asn_DEF_X2AP_X2AP_PDU, pdu); - //} + } if (dec_ret.code != RC_OK) { X2AP_ERROR("Failed to decode pdu\n"); diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index 0aeabce0d2..a96fa14f48 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1496,7 +1496,8 @@ int x2ap_eNB_generate_ENDC_x2_setup_response( } int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( - x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) + x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, + x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) { X2AP_X2AP_PDU_t pdu; X2AP_SgNBAdditionRequest_t *out; @@ -1507,44 +1508,21 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( uint8_t *buffer; uint32_t len; int ret = 0; - - // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted - // with values coming from RRC. - uint16_t nRencryptionAlgorithms = 0; - uint16_t nRintegrityProtectionAlgorithms = 0; + uint16_t nRencryptionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities.encryption_algorithms; + uint16_t nRintegrityProtectionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities + .integrity_algorithms; uint8_t SgNBSecurityKey[32] = { 0 }; - int uEaggregateMaximumBitRateDownlink = 100000000; - int uEaggregateMaximumBitRateUplink = 100000000; - int e_rabs_tobeadded = 1; - int e_RAB_ID = 1; - int drb_ID = 2; + int uEaggregateMaximumBitRateDownlink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_dl; + int uEaggregateMaximumBitRateUplink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_ul; + int e_rabs_tobeadded = x2ap_ENDC_sgnb_addition_req->nb_e_rabs_tobeadded; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; - long qCI = 1; - X2AP_Pre_emptionCapability_t pre_emptionCapability = X2AP_Pre_emptionCapability_shall_not_trigger_pre_emption; - X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability = X2AP_Pre_emptionVulnerability_not_pre_emptable; - priority_level_t priority_level = PRIORITY_LEVEL_NO_PRIORITY; - e_rab_tobe_added_t e_MCG_rabs_tobeadded; - e_MCG_rabs_tobeadded.gtp_teid = 0; - e_MCG_rabs_tobeadded.eNB_addr.length = 24; - uint8_t buf[20] = { 0 }; - memcpy(e_MCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); - - FILE *fd; - fd = fopen("../../../executables/uecap.raw","r"); - if (fd != NULL) { - OCTET_STRING_t CG_Config_Info; - CG_Config_Info.size = 4096; - CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t)); - int msg_len=fread(CG_Config_Info.buf,1,CG_Config_Info.size,fd); - CG_Config_Info.size = msg_len; - - /*char buffer[4096]; - int msg_len=fread(buffer,1,4096,fd);*/ - LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); - - + long qCI = 0; + X2AP_Pre_emptionCapability_t pre_emptionCapability; + X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability; + priority_level_t priority_level; + memcpy(SgNBSecurityKey, x2ap_ENDC_sgnb_addition_req->kgnb, sizeof(x2ap_ENDC_sgnb_addition_req->kgnb)); /*OCTET_STRING_t CG_Config_Info; CG_Config_Info.size = 4096; CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t));*/ @@ -1614,13 +1592,17 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs__value_PR_E_RABs_ToBeAdded_SgNBAddReq_Item; e_RABS_ToBeAdded_SgNBAddReq_Item = &e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_ToBeAdded_SgNBAddReq_Item; { - e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = drb_ID; - e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID; + e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].drb_ID; + e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].e_rab_id; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + qCI = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.qci; + priority_level = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.priority_level; + pre_emptionCapability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability; + pre_emptionVulnerability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_vulnerability; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.qCI = qCI; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability = pre_emptionCapability; @@ -1628,14 +1610,14 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel = priority_level; //Continue from filling the UL_GTPtunnelEndpointInformation inspired from how it is done for the HO case - INT32_TO_OCTET_STRING(e_MCG_rabs_tobeadded.gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID); - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = e_MCG_rabs_tobeadded.eNB_addr.length/8; - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_MCG_rabs_tobeadded.eNB_addr.length%8; + INT32_TO_OCTET_STRING(x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID); + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.length/8; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.length%8; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf = calloc(1, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); memcpy (e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf, - e_MCG_rabs_tobeadded.eNB_addr.buffer, + x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.buffer, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); } @@ -1648,25 +1630,24 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( ie->id = X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer; ie->criticality = X2AP_Criticality_reject; ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_MeNBtoSgNBContainer; - ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *)calloc(CG_Config_Info.size, sizeof(uint8_t)); - memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, CG_Config_Info.buf, CG_Config_Info.size); - ie->value.choice.MeNBtoSgNBContainer.size = CG_Config_Info.size; //4096; + if(NULL == (ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *) + calloc(x2ap_ENDC_sgnb_addition_req->rrc_buffer_size, sizeof(uint8_t)))) { + X2AP_ERROR("Memory ALLocation failed\n"); + exit(1); + } + memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, x2ap_ENDC_sgnb_addition_req->rrc_buffer, + x2ap_ENDC_sgnb_addition_req->rrc_buffer_size); + ie->value.choice.MeNBtoSgNBContainer.size = x2ap_ENDC_sgnb_addition_req->rrc_buffer_size; ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n"); return -1; } - + free(ie->value.choice.MeNBtoSgNBContainer.buf); MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); - fclose(fd); - } - else { - LOG_I(RRC, "uecap.raw file could not be opened... \n"); - return -1; - } return ret; @@ -1686,26 +1667,14 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in uint8_t *buffer; uint32_t len; int ret = 0; - int MeNB_UE_X2AP_id = ue_id; - int SgNB_UE_X2AP_id = 0; - // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted - // with values coming from RRC. - //uint16_t nRencryptionAlgorithms = 0; - //uint16_t nRintegrityProtectionAlgorithms = 0; - //uint8_t SgNBSecurityKey[32] = { 0 }; - //int uEaggregateMaximumBitRateDownlink = 100000000; - //int uEaggregateMaximumBitRateUplink = 100000000; - int e_rabs_admitted_tobeadded = 1; - int e_RAB_ID = 1; + int MeNB_UE_X2AP_id = x2ap_sgnb_addition_req_ACK->MeNB_ue_x2_id; + int SgNB_UE_X2AP_id = ue_id; + int e_rabs_admitted_tobeadded = x2ap_sgnb_addition_req_ACK->nb_e_rabs_admitted_tobeadded; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; - e_rab_setup_t e_SCG_rabs_tobeadded; - e_SCG_rabs_tobeadded.gtp_teid = 0; - e_SCG_rabs_tobeadded.eNB_addr.length = 24; - uint8_t buf[20] = { 0 }; - memcpy(e_SCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); + DevAssert(instance_p != NULL); DevAssert(x2ap_eNB_data_p != NULL); @@ -1748,21 +1717,21 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs__value_PR_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item = &e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; { - e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].e_rab_id; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item__resource_configuration_PR_sgNBPDCPpresent; - INT32_TO_OCTET_STRING(e_SCG_rabs_tobeadded.gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID); - e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = e_SCG_rabs_tobeadded.eNB_addr.length/8; - e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_SCG_rabs_tobeadded.eNB_addr.length%8; + INT32_TO_OCTET_STRING(x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID); + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.length/8; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.length%8; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf = calloc(1, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); memcpy (e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf, - e_SCG_rabs_tobeadded.eNB_addr.buffer, + x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.buffer, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); } diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.h b/openair2/X2AP/x2ap_eNB_generate_messages.h index 114ed84a68..3dfccc0e52 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.h +++ b/openair2/X2AP/x2ap_eNB_generate_messages.h @@ -70,7 +70,7 @@ int x2ap_gNB_generate_ENDC_x2_setup_request(x2ap_eNB_instance_t *instance_p, x2a int x2ap_eNB_generate_ENDC_x2_setup_response( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p); -int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id); +int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id); int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, x2ap_ENDC_sgnb_addition_req_ACK_t *x2ap_sgnb_addition_req_ACK, int ue_id); diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index afaae1756d..1c6c98cd81 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1652,7 +1652,6 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; MessageDef *msg; - int ue_id; DevAssert (pdu != NULL); x2SgNBAdditionRequest = &pdu->choice.initiatingMessage.value.choice.SgNBAdditionRequest; @@ -1683,20 +1682,9 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); return -1; } - - - // allocate a new X2AP UE ID - ue_id = x2ap_allocate_new_id(&instance_p->id_manager); - if (ue_id == -1) { - X2AP_ERROR("could not allocate a new X2AP UE ID\n"); - // TODO: cancel handover: send HO preparation failure to source eNB - exit(1); - } - // rnti is unknown yet, must not be set to -1, 0 is fine - x2ap_set_ids(&instance_p->id_manager, ue_id, 0, ie->value.choice.UE_X2AP_ID, ue_id); - x2ap_id_set_state(&instance_p->id_manager, ue_id, X2ID_STATE_TARGET); - - X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ue_id; + /* ue_x2_id = MeNB X2AP Id */ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ie->value.choice.UE_X2AP_ID; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_assoc_id = assoc_id; /* X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities */ @@ -1749,13 +1737,22 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability; X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.priority_level = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel; - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.buffer, + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.length = + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; +LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid); + OCTET_STRING_TO_INT32(&e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID, X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid); } @@ -1771,13 +1768,11 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer, true); - X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; - //X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; - if (container->size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s - { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } + if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s + { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); @@ -1891,10 +1886,10 @@ int x2ap_eNB_handle_ENDC_sGNB_addition_response (instance_t instance, X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->e_RAB_ID ; if(e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->en_DC_ResourceConfiguration.pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.buffer, + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer, e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf, e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.length = + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; OCTET_STRING_TO_INT32(&e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID, @@ -1963,7 +1958,7 @@ int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance, instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); - //Allocate an ITTI X2AP_SGNB_ADDITION_REQ message instead + //Allocate an ITTI X2AP_sGNB_reconfiguration_complete message msg = itti_alloc_new_message(TASK_X2AP, X2AP_ENDC_SGNB_RECONF_COMPLETE); /* X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID */ diff --git a/openair3/GTPV1-U/gtpv1u_eNB.c b/openair3/GTPV1-U/gtpv1u_eNB.c index f15f295548..f095cce67d 100644 --- a/openair3/GTPV1-U/gtpv1u_eNB.c +++ b/openair3/GTPV1-U/gtpv1u_eNB.c @@ -943,6 +943,8 @@ gtpv1u_create_s1u_tunnel( memcpy(&create_tunnel_resp_pP->enb_addr.buffer, &RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, sizeof (in_addr_t)); + + LOG_I(GTPU,"Configured GTPu address : %x\n",RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); create_tunnel_resp_pP->enb_addr.length = sizeof (in_addr_t); addrs_length_in_bytes = create_tunnel_req_pP->sgw_addr[i].length / 8; AssertFatal((addrs_length_in_bytes == 4) || @@ -971,6 +973,15 @@ gtpv1u_create_s1u_tunnel( gtpv1u_ue_data_p->bearers[eps_bearer_id - GTPV1U_BEARER_OFFSET].teid_sgw = create_tunnel_req_pP->sgw_S1u_teid[i]; gtpv1u_ue_data_p->num_bearers++; create_tunnel_resp_pP->enb_S1u_teid[i] = s1u_teid; + + LOG_I(GTPU,"Copied to create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_resp_pP->enb_addr.buffer[0], + create_tunnel_resp_pP->enb_addr.buffer[1], + create_tunnel_resp_pP->enb_addr.buffer[2], + create_tunnel_resp_pP->enb_addr.buffer[3], + create_tunnel_resp_pP->enb_addr.length, + create_tunnel_resp_pP->enb_S1u_teid[i]); } else { create_tunnel_resp_pP->enb_S1u_teid[i] = 0; create_tunnel_resp_pP->status = 0xFF; diff --git a/openair3/S1AP/s1ap_eNB.c b/openair3/S1AP/s1ap_eNB.c index 3592cf80a1..c703501847 100644 --- a/openair3/S1AP/s1ap_eNB.c +++ b/openair3/S1AP/s1ap_eNB.c @@ -69,7 +69,6 @@ s1ap_eNB_config_t s1ap_config; static int s1ap_eNB_generate_s1_setup_request( s1ap_eNB_instance_t *instance_p, s1ap_eNB_mme_data_t *s1ap_mme_data_p); - void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t *s1ap_register_eNB); void s1ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_association_resp_t *sctp_new_association_resp); @@ -221,8 +220,21 @@ void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t * /* Trying to connect to provided list of MME ip address */ for (index = 0; index < s1ap_register_eNB->nb_mme; index++) { + net_ip_address_t *mme_ip = &s1ap_register_eNB->mme_ip_address[index]; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &new_instance->s1ap_mme_head) { + /* Compare whether IPv4 and IPv6 information is already present, in which + * wase we do not register again */ + if (mme->mme_s1_ip.ipv4 == mme_ip->ipv4 && (!mme_ip->ipv4 + || strncmp(mme->mme_s1_ip.ipv4_address, mme_ip->ipv4_address, 16) == 0) + && mme->mme_s1_ip.ipv6 == mme_ip->ipv6 && (!mme_ip->ipv6 + || strncmp(mme->mme_s1_ip.ipv6_address, mme_ip->ipv6_address, 46) == 0)) + break; + } + if (mme) + continue; s1ap_eNB_register_mme(new_instance, - &s1ap_register_eNB->mme_ip_address[index], + mme_ip, &s1ap_register_eNB->enb_ip_address, s1ap_register_eNB->sctp_in_streams, s1ap_register_eNB->sctp_out_streams, @@ -361,6 +373,12 @@ void *s1ap_eNB_process_itti_msg(void *notUsed) { } break; + case S1AP_E_RAB_MODIFICATION_IND: { + s1ap_eNB_generate_E_RAB_Modification_Indication(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &S1AP_E_RAB_MODIFICATION_IND(received_msg)); + } + break; + case S1AP_UE_CONTEXT_RELEASE_COMPLETE: { s1ap_ue_context_release_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg), &S1AP_UE_CONTEXT_RELEASE_COMPLETE(received_msg)); @@ -508,3 +526,7 @@ static int s1ap_eNB_generate_s1_setup_request( s1ap_eNB_itti_send_sctp_data_req(instance_p->instance, s1ap_mme_data_p->assoc_id, buffer, len, 0); return ret; } + + + + diff --git a/openair3/S1AP/s1ap_eNB_decoder.c b/openair3/S1AP/s1ap_eNB_decoder.c index 3eb182b159..4635946a05 100644 --- a/openair3/S1AP/s1ap_eNB_decoder.c +++ b/openair3/S1AP/s1ap_eNB_decoder.c @@ -112,6 +112,12 @@ static int s1ap_eNB_decode_successful_outcome(S1AP_S1AP_PDU_t *pdu) { free(res.buffer); break; + case S1AP_ProcedureCode_id_E_RABModificationIndication: + res = asn_encode_to_new_buffer(NULL, ATS_CANONICAL_XER, &asn_DEF_S1AP_S1AP_PDU, pdu); + free(res.buffer); + break; + + default: S1AP_ERROR("Unknown procedure ID (%d) for successfull outcome message\n", (int)pdu->choice.successfulOutcome.procedureCode); diff --git a/openair3/S1AP/s1ap_eNB_encoder.c b/openair3/S1AP/s1ap_eNB_encoder.c index 0cd46214fc..227a3cb6a9 100644 --- a/openair3/S1AP/s1ap_eNB_encoder.c +++ b/openair3/S1AP/s1ap_eNB_encoder.c @@ -118,6 +118,11 @@ int s1ap_eNB_encode_initiating(S1AP_S1AP_PDU_t *pdu, free(res.buffer); break; + case S1AP_ProcedureCode_id_E_RABModificationIndication: + res = asn_encode_to_new_buffer(NULL, ATS_CANONICAL_XER, &asn_DEF_S1AP_S1AP_PDU, pdu); + free(res.buffer); + break; + default: S1AP_DEBUG("Unknown procedure ID (%d) for initiating message\n", (int)pdu->choice.initiatingMessage.procedureCode); diff --git a/openair3/S1AP/s1ap_eNB_handlers.c b/openair3/S1AP/s1ap_eNB_handlers.c index 87abc1ede9..28ee11187e 100644 --- a/openair3/S1AP/s1ap_eNB_handlers.c +++ b/openair3/S1AP/s1ap_eNB_handlers.c @@ -104,6 +104,11 @@ int s1ap_eNB_handle_s1_path_switch_request_failure(uint32_t assoc_ uint32_t stream, S1AP_S1AP_PDU_t *pdu); +static +int s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm(uint32_t assoc_id, + uint32_t stream, + S1AP_S1AP_PDU_t *pdu); + /* Handlers matrix. Only eNB related procedure present here */ s1ap_message_decoded_callback messages_callback[][3] = { { 0, 0, 0 }, /* HandoverPreparation */ @@ -154,6 +159,9 @@ s1ap_message_decoded_callback messages_callback[][3] = { { 0, 0, 0 }, /* UplinkUEAssociatedLPPaTransport */ { 0, 0, 0 }, /* DownlinkNonUEAssociatedLPPaTransport */ { 0, 0, 0 }, /* UplinkNonUEAssociatedLPPaTransport */ + { 0, 0, 0 }, /* UERadioCapabilityMatch */ + { 0, 0, 0 }, /* PWSRestartIndication */ + { 0, s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm, 0 }, /* E_RABModificationIndication */ }; char *s1ap_direction2String(int s1ap_dir) { static char *s1ap_direction_String[] = { @@ -1722,3 +1730,13 @@ int s1ap_eNB_handle_s1_path_switch_request_failure(uint32_t assoc_ // TODO continue return 0; } + +static +int s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm(uint32_t assoc_id, + uint32_t stream, + S1AP_S1AP_PDU_t *pdu){ + + LOG_W(S1AP, "Implementation of S1AP E-RAB Modification confirm handler is pending...\n"); + return 0; +} + diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c index d271ddf6ba..c668e32d1b 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.c +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c @@ -1620,3 +1620,319 @@ int s1ap_eNB_path_switch_req(instance_t instance, return ret; } + + +//----------------------------------------------------------------------------- +/* +* eNB generate a S1 E_RAB Modification Indication towards MME +*/ +/*int s1ap_eNB_generate_E_RAB_Modification_Indication( + instance_t instance, + s1ap_e_rab_modification_ind_t *e_rab_modification_ind) +//----------------------------------------------------------------------------- +{ + struct s1ap_eNB_ue_context_s *ue_context_p = NULL; + S1AP_S1AP_PDU_t pdu; + S1AP_E_RABModificationIndication_t *out = NULL; + S1AP_E_RABModificationIndicationIEs_t *ie = NULL; + S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL; + + S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL; + + + s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL; + s1ap_eNB_instance_p = s1ap_eNB_get_instance(instance); + uint8_t *buffer = NULL; + uint32_t len = 0; + int ret = 0; + DevAssert(s1ap_eNB_instance_p != NULL); + DevAssert(e_rab_modification_ind != NULL); + + int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified; + int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; + + uint32_t CSG_id = 0; + + if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, + e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { + // The context for this eNB ue s1ap id doesn't exist in the map of eNB UEs + S1AP_WARN("Failed to find ue context associated with eNB ue s1ap id: 0x%06x\n", + e_rab_modification_ind->eNB_ue_s1ap_id); + return -1; + } + + // Prepare the S1AP message to encode + memset(&pdu, 0, sizeof(pdu)); + pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage; + pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication; + pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication; + out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication; + // mandatory + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_MME_UE_S1AP_ID; + ie->value.choice.MME_UE_S1AP_ID = e_rab_modification_ind->mme_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_eNB_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_ENB_UE_S1AP_ID; + ie->value.choice.ENB_UE_S1AP_ID = e_rab_modification_ind->eNB_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABToBeModifiedListBearerModInd; + + //The following two for-loops here will probably need to change. We should do a different type of search + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABToBeModifiedItemBearerModIndIEs__value_PR_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd = &E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABToBeModifiedItemBearerModInd; + + { + E_RAB_ToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf = calloc(1, E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_ToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABToBeModifiedListBearerModInd.list, E_RAB_ToBeModifiedItem_BearerModInd_IEs); + } + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs NOT to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + if(num_e_rabs_nottobemodified > 0) { + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABNotToBeModifiedItemBearerModIndIEs__value_PR_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd; + + { + E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_nottobemodified[i].e_rab_id; + + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.length/8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.length%8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf = + calloc(1, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.buffer, + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_nottobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs); + } + } + else{ + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0; + } + + + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo; + ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member; + INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + + if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n"); + return -1; + } + + // Non UE-Associated signalling -> stream = 0 + S1AP_INFO("Size of encoded message: %d \n", len); + s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, + ue_context_p->mme_ref->assoc_id, buffer, + len, ue_context_p->tx_stream); + +//s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0); + return ret; +}*/ + +int s1ap_eNB_generate_E_RAB_Modification_Indication( + instance_t instance, + s1ap_e_rab_modification_ind_t *e_rab_modification_ind) +//----------------------------------------------------------------------------- +{ + struct s1ap_eNB_ue_context_s *ue_context_p = NULL; + S1AP_S1AP_PDU_t pdu; + S1AP_E_RABModificationIndication_t *out = NULL; + S1AP_E_RABModificationIndicationIEs_t *ie = NULL; + S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL; + + //S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL; + //S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL; + + + s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL; + s1ap_eNB_instance_p = s1ap_eNB_get_instance(instance); + uint8_t *buffer = NULL; + uint32_t len = 0; + int ret = 0; + DevAssert(s1ap_eNB_instance_p != NULL); + DevAssert(e_rab_modification_ind != NULL); + + int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified; + //int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; + + //uint32_t CSG_id = 0; + //uint32_t pseudo_gtp_teid = 10; + + if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, + e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { + // The context for this eNB ue s1ap id doesn't exist in the map of eNB UEs + S1AP_WARN("Failed to find ue context associated with eNB ue s1ap id: 0x%06x\n", + e_rab_modification_ind->eNB_ue_s1ap_id); + return -1; + } + + // Prepare the S1AP message to encode + memset(&pdu, 0, sizeof(pdu)); + pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage; + pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication; + pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication; + out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication; + /* mandatory */ + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_MME_UE_S1AP_ID; + ie->value.choice.MME_UE_S1AP_ID = e_rab_modification_ind->mme_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_eNB_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_ENB_UE_S1AP_ID; + ie->value.choice.ENB_UE_S1AP_ID = e_rab_modification_ind->eNB_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABToBeModifiedListBearerModInd; + + //The following two for-loops here will probably need to change. We should do a different type of search + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABToBeModifiedItemBearerModIndIEs__value_PR_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd = &E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABToBeModifiedItemBearerModInd; + + { + E_RAB_ToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf = calloc(1, E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_ToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABToBeModifiedListBearerModInd.list, E_RAB_ToBeModifiedItem_BearerModInd_IEs); + } + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs NOT to be modified list + /*ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + //if(num_e_rabs_nottobemodified > 0) { + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABNotToBeModifiedItemBearerModIndIEs__value_PR_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd; + + { + E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = 10; //e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf = + calloc(1, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + //INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + INT32_TO_OCTET_STRING(pseudo_gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs); + } + // } + //else{ +// ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; +// ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0; +// } / + + + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);*/ + + /*ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo; + ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member; + INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + ie->value.choice.CSGMembershipInfo.cSG_Id.bits_unused=5; + ie->value.choice.CSGMembershipInfo.cellAccessMode = S1AP_CellAccessMode_hybrid; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);*/ + + if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n"); + return -1; + } + + // Non UE-Associated signalling -> stream = 0 + S1AP_INFO("Size of encoded message: %d \n", len); + s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, + ue_context_p->mme_ref->assoc_id, buffer, + len, ue_context_p->tx_stream); + +//s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0); + return ret; +} + + diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.h b/openair3/S1AP/s1ap_eNB_nas_procedures.h index c425719872..47f71cc795 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.h +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.h @@ -52,4 +52,8 @@ int s1ap_eNB_e_rab_release_resp(instance_t instance, int s1ap_eNB_path_switch_req(instance_t instance, s1ap_path_switch_req_t *path_switch_req_p); + +int s1ap_eNB_generate_E_RAB_Modification_Indication( + instance_t instance, s1ap_e_rab_modification_ind_t *e_rab_modification_ind); + #endif /* S1AP_ENB_NAS_PROCEDURES_H_ */ diff --git a/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c b/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c index c4e593ca92..af5ab5ad6d 100644 --- a/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c +++ b/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c @@ -330,7 +330,10 @@ int trx_brf_set_gains(openair0_device* device, { return(0); } - +int trx_brf_write_init(openair0_device *device) +{ + return 0; +} #define RXDCLENGTH 16384 int16_t cos_fsover8[8] = {2047, 1447, 0, -1448, -2047, -1448, 0, 1447}; @@ -1145,6 +1148,7 @@ int device_init(openair0_device *device, device->trx_stop_func = trx_brf_stop; device->trx_set_freq_func = trx_brf_set_freq; device->trx_set_gains_func = trx_brf_set_gains; + device->trx_write_init = trx_brf_write_init; device->openair0_cfg = openair0_cfg; device->priv = (void *)brf; diff --git a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c index c5822a3650..c72e7d4130 100644 --- a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c +++ b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c @@ -197,6 +197,10 @@ int trx_eth_reset_stats(openair0_device* device) return(0); } +int trx_eth_write_init(openair0_device *device) +{ + return 0; +} int ethernet_tune(openair0_device *device, unsigned int option, @@ -415,8 +419,9 @@ int transport_init(openair0_device *device, device->trx_reset_stats_func = trx_eth_reset_stats; device->trx_end_func = trx_eth_end; device->trx_stop_func = trx_eth_stop; - device->trx_set_freq_func = trx_eth_set_freq; - device->trx_set_gains_func = trx_eth_set_gains; + device->trx_set_freq_func = trx_eth_set_freq; + device->trx_set_gains_func = trx_eth_set_gains; + device->trx_write_init = trx_eth_write_init; if (eth->flags == ETH_RAW_MODE) { device->trx_write_func = trx_eth_write_raw; diff --git a/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp b/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp index 5b20d8a8c7..1273097f3b 100644 --- a/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp +++ b/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp @@ -510,6 +510,11 @@ int trx_iris_reset_stats(openair0_device *device) { } +int trx_iris_write_init(openair0_device *device) +{ + return 0; +} + extern "C" { /*! \brief Initialize Openair Iris target. It returns 0 if OK @@ -831,6 +836,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { device->trx_set_freq_func = trx_iris_set_freq; device->trx_set_gains_func = trx_iris_set_gains; device->openair0_cfg = openair0_cfg; + device->trx_write_init = trx_iris_write_init; s->sample_rate = openair0_cfg[0].sample_rate; // TODO: diff --git a/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp b/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp index 9fcfbdf571..79a389bfeb 100644 --- a/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp +++ b/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp @@ -350,6 +350,10 @@ void trx_lms_end(openair0_device *device) { } +int trx_lms_write_init(openair0_device *device) +{ + return 0; +} extern "C" { /*! \brief Initialize Openair LMSSDR target. It returns 0 if OK * \param device the hardware to use @@ -406,6 +410,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg){ device->trx_stop_func = trx_lms_stop; device->trx_set_freq_func = trx_lms_set_freq; device->trx_set_gains_func = trx_lms_set_gains; + device->trx_write_init = trx_lms_write_init; device->openair0_cfg = openair0_cfg; diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp index 08f0cd720b..1377086e8f 100644 --- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp +++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp @@ -70,6 +70,8 @@ * @{ */ +extern int usrp_tx_thread; + typedef struct { @@ -345,7 +347,6 @@ static int trx_usrp_write(openair0_device *device, int flags_msb = (flags>>8)&0xff; int end; - int write_tread = 0; openair0_thread_t *write_thread = &device->write_thread; openair0_write_package_t *write_package = write_thread->write_package; @@ -382,7 +383,7 @@ static int trx_usrp_write(openair0_device *device, last_packet_state = true; } - if(write_tread == 0){ + if(usrp_tx_thread == 0){ #if defined(__x86_64) || defined(__i386__) #ifdef __AVX2__ nsamps2 = (nsamps+7)>>3; @@ -419,6 +420,7 @@ static int trx_usrp_write(openair0_device *device, s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate); s->tx_count++; +VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,1); // bit 3 enables gpio (for backward compatibility) if (flags_msb&8) { // push GPIO bits 7-9 from flags_msb @@ -427,6 +429,7 @@ static int trx_usrp_write(openair0_device *device, s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380); s->usrp->clear_command_time(); } +VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,0); if (cc>1) { std::vector buff_ptrs; @@ -586,7 +589,7 @@ void *trx_usrp_write_thread(void * arg){ return NULL; } -int trx_write_init(openair0_device *device){ +int trx_usrp_write_init(openair0_device *device){ uhd::set_thread_priority_safe(1.0); openair0_thread_t *write_thread = &device->write_thread; @@ -932,7 +935,7 @@ extern "C" { device->trx_stop_func = trx_usrp_stop; device->trx_set_freq_func = trx_usrp_set_freq; device->trx_set_gains_func = trx_usrp_set_gains; - device->trx_write_init = trx_write_init; + device->trx_write_init = trx_usrp_write_init; // hotfix! to be checked later diff --git a/targets/ARCH/rfsimulator/README.md b/targets/ARCH/rfsimulator/README.md index 421cc662bb..9ec0ae5065 100644 --- a/targets/ARCH/rfsimulator/README.md +++ b/targets/ARCH/rfsimulator/README.md @@ -96,11 +96,19 @@ sudo RFSIMULATOR=server ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE- ### Launch UE in another window ```bash -sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path ../../../ci-scripts/rrc-files +sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path . ``` -Note: + +Notes: + 1. can be 127.0.0.1 if both gNB and nrUE executables run on the same host, OR the IP interface address of the remote host running the gNB executable, if the gNB and nrUE run on separate hosts -2. the --rrc_config_path parameter can be omitted (but not necessarily) if the gNB and nrUE run on the same host, in which case the gNB provides the nrUE with the necessary rrc configuration +2. the --rrc_config_path parameter SHALL specify where the 2 RAW files are located (`rbconfig.raw` and `reconfig.raw`). + - If you are running on the same machine and launched the 2 executables (`nr-softmodem` and `nr-uesoftmodem`) from the same directory, nothing has to be done. + - If you launched the 2 executables from 2 different folders, just point to the location where you launched the `nr-softmodem`: + * `sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path /the/path/where/you/launched/nr-softmodem` + - If you are not running on the same machine or launched the 2 executables from 2 different folders, you need to **COPY** the 2 raw files + * `scp usera@machineA:/the/path/where/you/launched/nr-softmodem/r*config.raw userb@machineB:/the/path/where/you/will/launch/nr-uesoftmodem/` + * Obviously this operation SHALL be done before launching the `nr-uesoftmodem` executable. 3. to enable the noS1 mode --noS1 and --nokrnmod 1 options should be added to the command line diff --git a/targets/ARCH/rfsimulator/apply_channelmod.c b/targets/ARCH/rfsimulator/apply_channelmod.c index faf84bb0aa..7aa5d78bf8 100644 --- a/targets/ARCH/rfsimulator/apply_channelmod.c +++ b/targets/ARCH/rfsimulator/apply_channelmod.c @@ -34,6 +34,9 @@ #include #include #include +#include +#include +#include /* Legacy study: @@ -99,8 +102,8 @@ void rxAddInput( struct complex16 *input_sig, struct complex16 *after_channel_si } //l } - out_ptr->r += round(rx_tmp.x*pathLossLinear + noise_per_sample*gaussdouble(0.0,1.0)); - out_ptr->i += round(rx_tmp.y*pathLossLinear + noise_per_sample*gaussdouble(0.0,1.0)); + out_ptr->r += round(rx_tmp.x*pathLossLinear + noise_per_sample*gaussZiggurat(0.0,1.0)); + out_ptr->i += round(rx_tmp.y*pathLossLinear + noise_per_sample*gaussZiggurat(0.0,1.0)); out_ptr++; } @@ -112,3 +115,4 @@ void rxAddInput( struct complex16 *input_sig, struct complex16 *after_channel_si channelDesc->path_loss_dB, 10*log10(noise_per_sample)); } + diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index 222a3e9f80..b7b435f2d9 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -50,6 +50,7 @@ #include "openair1/PHY/defs_UE.h" #define CHANNELMOD_DYNAMICLOAD #include +#include #define PORT 4043 //default TCP port for this simulator #define CirSize 307200 // 100ms is enough @@ -146,6 +147,16 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { // the value channel_model->path_loss_dB seems only a storage place (new_channel_desc_scm() only copy the passed value) // Legacy changes directlty the variable channel_model->path_loss_dB place to place // while calling new_channel_desc_scm() with path losses = 0 + static bool init_done=false; + if (!init_done) { + uint64_t rand; + FILE *h=fopen("/dev/random","r"); + fread(&rand,sizeof(rand),1,h); + fclose(h); + randominit(rand); + tableNor(rand); + init_done=true; + } ptr->channel_model=new_channel_desc_scm(bridge->tx_num_channels,bridge->rx_num_channels, bridge->channelmod, bridge->sample_rate, @@ -469,14 +480,16 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi b->trashingPacket=true; } else if ( b->lastReceivedTS < b->th.timestamp) { int nbAnt= b->th.nbAnt; - + if ( b->th.timestamp-b->lastReceivedTS < CirSize ) { for (uint64_t index=b->lastReceivedTS; index < b->th.timestamp; index++ ) { for (int a=0; a < nbAnt; a++) { b->circularBuf[(index*nbAnt+a)%CirSize].r = 0; b->circularBuf[(index*nbAnt+a)%CirSize].i = 0; } } - + } else { + memset(b->circularBuf, 0, sampleToByte(CirSize,1)); + } if (b->lastReceivedTS != 0 && b->th.timestamp-b->lastReceivedTS > 50 ) LOG_W(HW,"UEsock: %d gap of: %ld in reception\n", fd, b->th.timestamp-b->lastReceivedTS ); b->lastReceivedTS=b->th.timestamp; @@ -561,6 +574,7 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo pthread_mutex_unlock(&Sockmutex); usleep(10000); pthread_mutex_lock(&Sockmutex); + if ( t->lastWroteTS < t->nextTimestamp ) { // Assuming Tx is not done fully in another thread // We can never write is the past from the received time @@ -574,6 +588,7 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo for ( int i=0; i < t->tx_num_channels; i++) samplesVoid[i]=(void *)&v; + LOG_I(HW, "No samples Tx occured, so we send 1 sample to notify it: Tx:%lu, Rx:%lu\n", t->lastWroteTS, t->nextTimestamp); rfsimulator_write_internal(t, t->nextTimestamp, @@ -637,10 +652,11 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo ); else { // no channel modeling sample_t *out=(sample_t *)samplesVoid[a]; - + const int64_t base=t->nextTimestamp*nbAnt+a; for ( int i=0; i < nsamps; i++ ) { - out[i].r+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt+a)%CirSize].r; - out[i].i+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt+a)%CirSize].i; + const int idx=(i*nbAnt+base)%CirSize; + out[i].r+=ptr->circularBuf[idx].r; + out[i].i+=ptr->circularBuf[idx].i; } } // end of no channel modeling } // end for a... @@ -716,7 +732,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { rfsimulator->rx_num_channels=openair0_cfg->rx_num_channels; rfsimulator->sample_rate=openair0_cfg->sample_rate; rfsimulator->tx_bw=openair0_cfg->tx_bw; - randominit(0); + //randominit(0); set_taus_seed(0); return 0; } diff --git a/targets/ARCH/tcp_bridge/tcp_bridge.c b/targets/ARCH/tcp_bridge/tcp_bridge.c index 8b287acfa1..f8c12dcb7a 100644 --- a/targets/ARCH/tcp_bridge/tcp_bridge.c +++ b/targets/ARCH/tcp_bridge/tcp_bridge.c @@ -243,6 +243,11 @@ ts += nsamps; return nsamps; } +int tcp_bridge_write_init(openair0_device *device) +{ + return 0; +} + __attribute__((__visibility__("default"))) int device_init(openair0_device* device, openair0_config_t *openair0_cfg) { @@ -267,6 +272,7 @@ int device_init(openair0_device* device, openair0_config_t *openair0_cfg) device->trx_set_gains_func = tcp_bridge_set_gains; device->trx_write_func = tcp_bridge_write; device->trx_read_func = tcp_bridge_read; + device->trx_write_init = tcp_bridge_write_init; device->priv = tcp_bridge; diff --git a/targets/COMMON/create_nr_tasks.c b/targets/COMMON/create_nr_tasks.c index 24c4115980..13f72b3876 100644 --- a/targets/COMMON/create_nr_tasks.c +++ b/targets/COMMON/create_nr_tasks.c @@ -51,17 +51,17 @@ int create_gNB_tasks(uint32_t gnb_nb) } if (gnb_nb > 0) { - /* Last task to create, others task must be ready before its start */ + // Last task to create, others task must be ready before its start if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { LOG_E(GNB_APP, "Create task for gNB APP failed\n"); return -1; } } -/* + if (EPC_MODE_ENABLED) { if (gnb_nb > 0) { - if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { + /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { LOG_E(SCTP, "Create task for SCTP failed\n"); return -1; } @@ -69,7 +69,7 @@ int create_gNB_tasks(uint32_t gnb_nb) if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { LOG_E(S1AP, "Create task for S1AP failed\n"); return -1; - } + }*/ if(!emulate_rf){ if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { LOG_E(UDP_, "Create task for UDP failed\n"); @@ -84,7 +84,15 @@ int create_gNB_tasks(uint32_t gnb_nb) } } -*/ + + /*if (gnb_nb > 0) { + // Last task to create, others task must be ready before its start + if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { + LOG_E(GNB_APP, "Create task for gNB APP failed\n"); + return -1; + } + }*/ + if (gnb_nb > 0) { LOG_I(NR_RRC,"Creating NR RRC gNB Task\n"); @@ -100,4 +108,4 @@ int create_gNB_tasks(uint32_t gnb_nb) return 0; } -#endif +//#endif diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf index 1363be3bce..d5bc492644 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf index 1fbc8e30ef..93a6c7fbc9 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index fed15739cf..2c37e0d03f 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -46,7 +46,7 @@ gNBs = #initialDownlinkBWP #genericParameters # this is RBstart=0,L=50 (275*(L-1))+RBstart - initialDLBWPlocationAndBandwidth = 13475; + initialDLBWPlocationAndBandwidth = 6366; # subcarrierSpacing # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 initialDLBWPsubcarrierSpacing = 1; @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,12 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 + initialDLBWPstartSymbolAndLength_3 = 57; + #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; @@ -83,7 +89,7 @@ gNBs = pMax = 20; #initialUplinkBWP #genericParameters - initialULBWPlocationAndBandwidth = 13475; + initialULBWPlocationAndBandwidth = 6366; # subcarrierSpacing # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 initialULBWPsubcarrierSpacing = 1; @@ -105,8 +111,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,16 +120,16 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # msg1_SubcarrierSpacing = 1, - # restrictedSetConfig # 0=unrestricted, 1=restricted type A, 2=restricted type B restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) initialULBWPk2_0 = 2; initialULBWPmappingType_0 = 1 @@ -135,6 +141,11 @@ gNBs = # this is SS=0 L=12 initialULBWPstartSymbolAndLength_1 = 69; + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + msg3_DeltaPreamble = 1; p0_NominalWithGrant =-90; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf index 06aa4f6f9f..0b04dc82d1 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf @@ -33,10 +33,10 @@ gNBs = # downlinkConfigCommon #frequencyInfoDL # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) - absoluteFrequencySSB = 633032; + absoluteFrequencySSB = 641032; dl_frequencyBand = 78; - # this is 3480 MHz - dl_absoluteFrequencyPointA = 632000; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; #scs-SpecificCarrierList dl_offstToCarrier = 0; # subcarrierSpacing @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; @@ -105,8 +110,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +119,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # @@ -148,7 +153,7 @@ gNBs = # ssb_PositionsInBurs_BitmapPR # 1=short, 2=medium, 3=long ssb_PositionsInBurst_PR = 2; - ssb_PositionsInBurst_Bitmap = 255; + ssb_PositionsInBurst_Bitmap = 1; # ssb_periodicityServingCell # 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 @@ -237,7 +242,8 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "type=x300"; + sdr_addrs = "type=x300"; + clock_src = "external"; } ); diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf index b82c455ef4..ae17efc9bd 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; @@ -105,8 +110,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +119,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf index 4cbec5b86e..c907dcfe8d 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; @@ -105,8 +110,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +119,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf index 08bfeea7ee..464ce6b9aa 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; @@ -105,8 +110,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +119,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/RT/USER/gNB_usrp.gtkw b/targets/RT/USER/gNB_usrp.gtkw index 6ece894bb6..ebf3a57665 100644 --- a/targets/RT/USER/gNB_usrp.gtkw +++ b/targets/RT/USER/gNB_usrp.gtkw @@ -32,43 +32,50 @@ variables.frame_number_RX1_UE[63:0] variables.trx_ts_ue[63:0] variables.trx_ts[63:0] variables.trx_tst[63:0] -variables.frame_number_RX0_RU[63:0] -variables.tti_number_RX0_RU[63:0] -variables.frame_number_TX0_RU[63:0] -variables.tti_number_TX0_RU[63:0] -@28 -functions.mac_schedule_dlsch -functions.macxface_eNB_dlsch_ulsch_scheduler -@24 -variables.frame_number_RX0_gNB[63:0] -variables.slot_number_RX0_gNB[63:0] -variables.frame_number_TX0_gNB[63:0] -variables.slot_number_TX0_gNB[63:0] -@28 -functions.gNB_thread_rxtx0 -@24 -variables.frame_number_RX1_gNB[63:0] -variables.slot_number_RX1_gNB[63:0] -variables.frame_number_TX1_gNB[63:0] -variables.slot_number_TX1_gNB[63:0] -@28 -functions.gNB_thread_rxtx1 -functions.phy_enb_pdcch_tx -functions.phy_eNB_dlsch_encoding -functions.phy_eNB_dlsch_encoding_w -functions.generate_dlsch +@22 +variables.frame_number_RX0_UE[63:0] @420 variables.frame_number_RX0_UE[63:0] +@24 +variables.frame_number_RX0_RU[63:0] +variables.tti_number_RX0_RU[63:0] +variables.frame_number_RX0_gNB[63:0] +variables.slot_number_RX0_gNB[63:0] +variables.slot_number_RX1_gNB[63:0] +variables.frame_number_RX1_gNB[63:0] @28 functions.phy_procedures_ru_feprx0 functions.phy_procedures_ru_feprx1 +functions.phy_procedures_gNB_uespec_rx +functions.nr_rx_pusch +functions.nr_ulsch_procedures_rx +functions.gNB_ulsch_decoding +@24 +variables.frame_number_TX0_RU[63:0] +variables.frame_number_TX0_gNB[63:0] +variables.frame_number_TX1_gNB[63:0] +variables.tti_number_TX0_RU[63:0] +variables.slot_number_TX0_gNB[63:0] +variables.slot_number_TX1_gNB[63:0] +@29 +functions.mac_schedule_dlsch +@28 +functions.macxface_gNB_dlsch_ulsch_scheduler +functions.gNB_thread_rxtx0 +functions.gNB_thread_rxtx1 +functions.generate_dlsch +functions.phy_procedures_gNB_common_tx +functions.phy_procedures_gNB_tx +functions.gNB_pdcch_tx +functions.gNB_dlsch_encoding +functions.gNB_pdsch_codeword_scrambling +functions.gNB_pdsch_modulation functions.phy_procedures_ru_feptx_ofdm0 functions.phy_procedures_ru_feptx_ofdm1 functions.phy_procedures_ru_feptx_ofdm2 functions.phy_procedures_ru_feptx_prec0 functions.phy_procedures_ru_feptx_prec1 functions.phy_procedures_ru_feptx_prec2 -@22 variables.ru_tx_ofdm_mask[63:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index d2e734f205..4d89020077 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -679,7 +679,11 @@ void rx_rf(RU_t *ru, resynch=1; } - proc->timestamp_rx = ts-ru->ts_offset; + if(get_softmodem_params()->emulate_rf) { + proc->timestamp_rx = old_ts + fp->samples_per_tti; + } else { + proc->timestamp_rx = ts-ru->ts_offset; + } // AssertFatal(rxs == fp->samples_per_tti, // "rx_rf: Asked for %d samples, got %d from SDR\n",fp->samples_per_tti,rxs); @@ -2337,19 +2341,22 @@ void init_RU_proc(RU_t *ru) { LOG_I(PHY,"%s() DJP - added creation of pthread_prach\n", __FUNCTION__); pthread_create( &proc->pthread_prach, attr_prach, ru_thread_prach, (void *)ru ); ru->state=RU_RUN; - fill_rf_config(ru,ru->rf_config_file); - init_frame_parms(ru->frame_parms,1); - ru->frame_parms->nb_antennas_rx = ru->nb_rx; - phy_init_RU(ru); - ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg); - if (ret < 0) { - LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n"); - exit(1); - } + if(!get_softmodem_params()->emulate_rf) + { + fill_rf_config(ru,ru->rf_config_file); + init_frame_parms(ru->frame_parms,1); + ru->frame_parms->nb_antennas_rx = ru->nb_rx; + phy_init_RU(ru); + ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg); + if (ret < 0) { + LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n"); + exit(1); + } - if (setup_RU_buffers(ru)!=0) { - LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n"); - exit(1); + if (setup_RU_buffers(ru)!=0) { + LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n"); + exit(1); + } } } diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c index d8c5e25593..4715a4e995 100644 --- a/targets/RT/USER/lte-softmodem.c +++ b/targets/RT/USER/lte-softmodem.c @@ -170,6 +170,7 @@ extern void init_eNB_afterRU(void); int transmission_mode=1; int emulate_rf = 0; int numerology = 0; +int usrp_tx_thread = 0; THREAD_STRUCT thread_struct; /* struct for ethernet specific parameters given in eNB conf file */ @@ -659,6 +660,7 @@ int main ( int argc, char **argv ) initTpool("n", L1proc->threadPool, true); initNotifiedFIFO(L1proc->respEncode); initNotifiedFIFO(L1proc->respDecode); + RC.eNB[x][CC_id]->proc.L1_proc_tx.threadPool = L1proc->threadPool; } diff --git a/targets/RT/USER/lte-softmodem.h b/targets/RT/USER/lte-softmodem.h index c5fdb5f546..1c537dabe3 100644 --- a/targets/RT/USER/lte-softmodem.h +++ b/targets/RT/USER/lte-softmodem.h @@ -155,6 +155,10 @@ extern int sync_var; extern int transmission_mode; extern double cpuf; +extern int emulate_rf; +extern int numerology; +extern int usrp_tx_thread; + // In lte-enb.c extern void stop_eNB(int); extern void kill_eNB_proc(int inst); diff --git a/targets/RT/USER/lte-uesoftmodem.c b/targets/RT/USER/lte-uesoftmodem.c index 2c9271888b..a45ecd2298 100644 --- a/targets/RT/USER/lte-uesoftmodem.c +++ b/targets/RT/USER/lte-uesoftmodem.c @@ -171,6 +171,8 @@ extern void get_uethreads_params(void); int transmission_mode=1; +int usrp_tx_thread = 0; + char *usrp_args=NULL; char *usrp_clksrc=NULL; From b64b6e85c437282e837f847ef89977a445e1e7ab Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Thu, 6 Aug 2020 15:39:15 +0800 Subject: [PATCH 51/70] fix build_oai and CUDA latency --- cmake_targets/build_oai | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index a7adc33db3..88b8811575 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -701,8 +701,8 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim - # simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" - simlist="ldpctest" + simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" + # simlist="ldpctest" for f in $simlist ; do compilations \ phy_simulators $f \ From 61bdea7584a96161d7355e26ddb7ddd5b3889a82 Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Thu, 6 Aug 2020 15:40:57 +0800 Subject: [PATCH 52/70] fix build_oai and CUDA latency --- ci-scripts/cls_physim.py | 191 + .../gnb_nr_ue_usrp_run_multi_thread.xml | 71 + ci-scripts/xml_files/ldpc_gpu_test.xml | 161 + doc/TESTING_GNB_W_COTS_UE.md | 394 + .../attach_signaling_scheme.jpg | Bin 0 -> 48290 bytes doc/testing_gnb_w_cots_ue_resources/enb.conf | 281 + doc/testing_gnb_w_cots_ue_resources/gnb.conf | 293 + .../oai_enb.log | 1912 + .../oai_fr1_lab.jpg | Bin 0 -> 93188 bytes .../oai_fr1_setup.jpg | Bin 0 -> 252726 bytes .../oai_fr1_setup.vsdx | Bin 0 -> 1291764 bytes .../oai_gnb.log | 38680 ++++++++++++++++ .../nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h | 478 + .../PHY/NR_TRANSPORT/nr_dci_tools_common.c | 62 + .../NR_PHY/nr_dummy_functions_prach.c | 348 + openair2/LAYER2/MAC/slicing/slicing.c | 601 + openair2/LAYER2/MAC/slicing/slicing.h | 74 + .../LAYER2/MAC/slicing/slicing_internal.h | 46 + openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 120 + openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 153 + openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 644 + openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 209 + openair2/RRC/NR/rrc_gNB_GTPV1U.c | 94 + openair2/RRC/NR/rrc_gNB_GTPV1U.h | 39 + openair3/GTPV1-U/gtpv1u_gNB.c | 311 + openair3/GTPV1-U/gtpv1u_gNB_task.h | 37 + patch.diff | 472 + targets/ARCH/rfsimulator/new_channel_sim.c | 108 + targets/ARCH/rfsimulator/rfsimulator.h | 37 + .../CONF/gnb.band78.106PRB.slave.conf | 295 + .../GENERIC-LTE-EPC/CONF/testing_enb.conf | 281 + .../GENERIC-LTE-EPC/CONF/testing_gnb.conf | 293 + 32 files changed, 46685 insertions(+) create mode 100644 ci-scripts/cls_physim.py create mode 100644 ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml create mode 100644 ci-scripts/xml_files/ldpc_gpu_test.xml create mode 100644 doc/TESTING_GNB_W_COTS_UE.md create mode 100755 doc/testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg create mode 100755 doc/testing_gnb_w_cots_ue_resources/enb.conf create mode 100755 doc/testing_gnb_w_cots_ue_resources/gnb.conf create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_enb.log create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.vsdx create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_gnb.log create mode 100644 openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h create mode 100644 openair1/PHY/NR_TRANSPORT/nr_dci_tools_common.c create mode 100644 openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c create mode 100644 openair2/LAYER2/MAC/slicing/slicing.c create mode 100644 openair2/LAYER2/MAC/slicing/slicing.h create mode 100644 openair2/LAYER2/MAC/slicing/slicing_internal.h create mode 100644 openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h create mode 100644 openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c create mode 100644 openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c create mode 100644 openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c create mode 100644 openair2/RRC/NR/rrc_gNB_GTPV1U.c create mode 100644 openair2/RRC/NR/rrc_gNB_GTPV1U.h create mode 100644 openair3/GTPV1-U/gtpv1u_gNB.c create mode 100644 openair3/GTPV1-U/gtpv1u_gNB_task.h create mode 100644 patch.diff create mode 100644 targets/ARCH/rfsimulator/new_channel_sim.c create mode 100644 targets/ARCH/rfsimulator/rfsimulator.h create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py new file mode 100644 index 0000000000..4ca36b8cf0 --- /dev/null +++ b/ci-scripts/cls_physim.py @@ -0,0 +1,191 @@ +# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +# * contributor license agreements. See the NOTICE file distributed with +# * this work for additional information regarding copyright ownership. +# * The OpenAirInterface Software Alliance licenses this file to You under +# * the OAI Public License, Version 1.1 (the "License"); you may not use this file +# * except in compliance with the License. +# * You may obtain a copy of the License at +# * +# * http://www.openairinterface.org/?page_id=698 +# * +# * Unless required by applicable law or agreed to in writing, software +# * distributed under the License is distributed on an "AS IS" BASIS, +# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# * See the License for the specific language governing permissions and +# * limitations under the License. +# *------------------------------------------------------------------------------- +# * For more information about the OpenAirInterface (OAI) Software Alliance: +# * contact@openairinterface.org +# */ +#--------------------------------------------------------------------- +# Python for CI of OAI-eNB + COTS-UE +# +# Required Python Version +# Python 3.x +# +# Required Python Package +# pexpect +#--------------------------------------------------------------------- + +#to use logging.info() +import logging +#to create a SSH object locally in the methods +import sshconnection +#to update the HTML object +import html +from multiprocessing import SimpleQueue +#for log folder maintenance +import os + +class PhySim: + def __init__(self): + self.buildargs = "" + self.runargs = "" + self.eNBIpAddr = "" + self.eNBUserName = "" + self.eNBPassWord = "" + self.eNBSourceCodePath = "" + self.ranRepository = "" + self.ranBranch = "" + self.ranCommitID= "" + self.ranAllowMerge= "" + self.ranTargetBranch= "" + self.exitStatus=0 + self.forced_workspace_cleanup=False + #private attributes + self.__workSpacePath='' + self.__buildLogFile='compile_phy_sim.log' + self.__runLogFile='' + self.__runResults=[] + self.__runLogPath='phy_sim_logs' + + +#----------------- +#PRIVATE Methods +#----------------- + + def __CheckResults_PhySim(self,HTML,CONST,testcase_id): + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + #retrieve run log file and store it locally$ + mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__runLogFile, '.') + mySSH.close() + #parse results looking for Encoding and Decoding mean values + self.__runResults=[] + with open(self.__runLogFile) as f: + for line in f: + if 'mean' in line: + self.__runResults.append(line) + #the values are appended for each mean value (2), so we take these 2 values from the list + info=self.__runResults[0]+self.__runResults[1] + + #once parsed move the local logfile to its folder for tidiness + os.system('mv '+self.__runLogFile+' '+ self.__runLogPath+'/.') + + #updating the HTML with results + html_cell = '
' + info  + '
' + html_queue=SimpleQueue() + html_queue.put(html_cell) + HTML.CreateHtmlTestRowQueue(self.runargs, 'OK', 1, html_queue) + return HTML + + + def __CheckBuild_PhySim(self, HTML, CONST): + self.__workSpacePath=self.eNBSourceCodePath+'/cmake_targets/' + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + #retrieve compile log file and store it locally + mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__buildLogFile, '.') + #delete older run log file + mySSH.command('rm ' + self.__workSpacePath+self.__runLogFile, '\$', 5) + mySSH.close() + #check build result from local compile log file + buildStatus=False + with open(self.__buildLogFile) as f: + #nr_prachsim is the last compile step + if 'nr_prachsim compiled' in f.read(): + buildStatus=True + #update HTML based on build status + if buildStatus: + HTML.CreateHtmlTestRow(self.buildargs, 'OK', CONST.ALL_PROCESSES_OK, 'LDPC') + self.exitStatus=0 + else: + logging.error('\u001B[1m Building Physical Simulators Failed\u001B[0m') + HTML.CreateHtmlTestRow(self.buildargs, 'KO', CONST.ALL_PROCESSES_OK, 'LDPC') + HTML.CreateHtmlTabFooter(False) + #exitStatus=1 will do a sys.exit in main + self.exitStatus=1 + return HTML + + +#-----------------$ +#PUBLIC Methods$ +#-----------------$ + + def Build_PhySim(self,htmlObj,constObj): + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + + #create working dir + mySSH.command('mkdir -p ' + self.eNBSourceCodePath, '\$', 5) + mySSH.command('cd ' + self.eNBSourceCodePath, '\$', 5) + + if not self.ranRepository.lower().endswith('.git'): + self.ranRepository+='.git' + + #git clone + mySSH.command('if [ ! -e .git ]; then stdbuf -o0 git clone ' + self.ranRepository + ' .; else stdbuf -o0 git fetch --prune; fi', '\$', 600) + #git config + mySSH.command('git config user.email "jenkins@openairinterface.org"', '\$', 5) + mySSH.command('git config user.name "OAI Jenkins"', '\$', 5) + + #git clean depending on self.forced_workspace_cleanup captured in xml + if self.forced_workspace_cleanup==True: + logging.info('Cleaning workspace ...') + mySSH.command('echo ' + self.eNBPassWord + ' | sudo -S git clean -x -d -ff', '\$', 30) + else: + logging.info('Workspace cleaning was disabled') + + # if the commit ID is provided, use it to point to it + if self.ranCommitID != '': + mySSH.command('git checkout -f ' + self.ranCommitID, '\$', 5) + # if the branch is not develop, then it is a merge request and we need to do + # the potential merge. Note that merge conflicts should have already been checked earlier + if (self.ranAllowMerge): + if self.ranTargetBranch == '': + if (self.ranBranch != 'develop') and (self.ranBranch != 'origin/develop'): + mySSH.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5) + else: + logging.info('Merging with the target branch: ' + self.ranTargetBranch) + mySSH.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5) + + #build + mySSH.command('source oaienv', '\$', 5) + mySSH.command('cd cmake_targets', '\$', 5) + mySSH.command('mkdir -p log', '\$', 5) + mySSH.command('chmod 777 log', '\$', 5) + mySSH.command('stdbuf -o0 ./build_oai ' + self.buildargs + ' 2>&1 | stdbuf -o0 tee ' + self.__buildLogFile, 'Bypassing the Tests|build have failed', 1500) + + mySSH.close() + #check build status and update HTML object + lHTML = html.HTMLManagement() + lHTML=self.__CheckBuild_PhySim(htmlObj,constObj) + return lHTML + + + def Run_PhySim(self,htmlObj,constObj,testcase_id): + #create run logs folder locally + os.system('mkdir -p ./'+self.__runLogPath) + #log file is tc_.log remotely + self.__runLogFile='physim_'+str(testcase_id)+'.log' + #open a session for test run + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + mySSH.command('cd '+self.__workSpacePath,'\$',5) + #run and redirect the results to a log file + mySSH.command(self.__workSpacePath+'phy_simulators/build/ldpctest ' + self.runargs + ' >> '+self.__runLogFile, '\$', 30) + mySSH.close() + #return updated HTML to main + lHTML = html.HTMLManagement() + lHTML=self.__CheckResults_PhySim(htmlObj,constObj,testcase_id) + return lHTML diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml new file mode 100644 index 0000000000..b4290ae6a3 --- /dev/null +++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml @@ -0,0 +1,71 @@ + + + run-oai-gnb-nr-ue-tx-write-thread + Run-gNB-and-NR-UE-TX-Write-Thread + tasks + 2 + +090103 000001 090104 000002 090108 090109 + + + + + Initialize_eNB + Initialize gNB USRP (Tx-Write-Threading enabled) + -O ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test --usrp-tx-thread-config 1 + NR + + + + IdleSleep + Sleep + 5 + + + + IdleSleep + Waiting for NR UE to synchronize w/ gNB + 180 + + + + Initialize_OAI_UE + Initialize NR UE USRP + --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path . + NR + + + + Terminate_OAI_UE + Terminate NR UE + NR + + + + Terminate_eNB + Terminate gNB + NR + + + diff --git a/ci-scripts/xml_files/ldpc_gpu_test.xml b/ci-scripts/xml_files/ldpc_gpu_test.xml new file mode 100644 index 0000000000..a0191fbd76 --- /dev/null +++ b/ci-scripts/xml_files/ldpc_gpu_test.xml @@ -0,0 +1,161 @@ + + + test-ldpc-gpu + Test-ldpc-GPU + tasks + 1 + 000001 000002 000003 000004 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 000020 000021 + + + + Build_PhySim + Build for physical simulator + --phy_simulators --ninja + FALSE + + + + Run_PhySim + Run LDPC Test with CPU + -l 3872 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 3872 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 4224 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 4224 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 4576 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 4576 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 4928 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 4928 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 5280 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 5280 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 5632 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 5632 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 6336 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 6336 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 7040 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 7040 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 7744 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 7744 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 8448 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 8448 -s10 -n100 -G 1 + + + + + diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md new file mode 100644 index 0000000000..e507050239 --- /dev/null +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -0,0 +1,394 @@ +STATUS 2020/06/26 : information is up to date, but under continuous improvement + +## Table of Contents ## + +1. [Configuration Overview](#configuration-overview) +2. [SW Repository / Branch](#repository) +3. [Architecture Setup](#architecture-setup) +4. [Build / Install](#build-and-install) +5. [Run / Test](#run-and-test) +6. [Test case](#test-case) +7. [Log file monitoring](#log-file-monitoring) +6. [Required tools for debug](#required-tools-for-debug) +7. [Status of interoperability](#status-of-interoperability) + +## Configuration Overview + +* Non Standalone (NSA) configuration : initial Control Plane established between UE and RAN eNB, then User Plane established between UE and gNB, Core network is 4G based supporting rel 15 + +* Commercial UE: Oppo Reno 5G +* OAI Software Defined gNB and eNB +* eNB RF front end: USRP (ETTUS) B200 Mini or B210 +* gNB RF front end: USRP (ETTUS) B200 Mini or B210 (N310 will be needed for MIMO and wider BW's) +* 5G TDD duplexing mode +* 5G FR1 Band n78 (3.5 GHz) +* BW: 40MHz +* Antenna scheme: SISO + +## Repository + +https://gitlab.eurecom.fr/oai/openairinterface5g/tree/develop + +## Architecture Setup + +The scheme below depicts our typical setup: + +![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg) + +The photo depicts the FR1 setup part of the scheme above: + + +![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg) + +## Build and Install + +General guidelines to build eNB and gNB : +See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#building-ues-enodeb-and-gnodeb-executables + + +- **eNB** + +``` +cd /openairinterface5g/ +source oaienv +cd cmake_targets/ +./build_oai -I -w USRP --eNB + +``` + +- **gNB** + +``` +cd /openairinterface5g/ +source oaienv +cd cmake_targets/ +./build_oai -I -w USRP --gNB +``` + + +- **EPC** + +for reference: +https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md + + + +## Configuration Files + +Each component (EPC, eNB, gNB) has its own configuration file. +These config files are passed as arguments of the run command line, using the option -O \ + +Some config examples can be found in the following folder: +https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/develop/targets/PROJECTS/GENERIC-LTE-EPC/CONF + +Also base config files can be found here: +[enb conf file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/enb.conf) +[gnb conf file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/gnb.conf) + +TO DO : attach base confif files + +These files have to be updated manually to set the IP addresses and frequency. + +1- In the **eNB configuration file** : +- look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server +``` + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "**YOUR_EPC_IP_ADDR**"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + +``` + +- look for S1 IP address, and update the **3 fields below** with the IP address of the **eNB** server +``` + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_ENB_IP_ADDR**"; + ENB_INTERFACE_NAME_FOR_S1U = "eth0"; + ENB_IPV4_ADDRESS_FOR_S1U = "**YOUR_ENB_IP_ADDR**"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + ENB_IPV4_ADDRESS_FOR_X2C = "**YOUR_ENB_IP_ADDR**"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + +``` + +2- In the **gNB configuration file** : +- look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server +``` + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "**YOUR_EPC_IP_ADDR**"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); +``` +- look for X2 IP address, and update the **4 fields** with the IP address of the **eNB** server (notice : even if -in principle- S1 MME is not required for gNB setting) +``` + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "**YOUR_ENB_IP_ADDR**"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_ENB_IP_ADDR**"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "**YOUR_ENB_IP_ADDR**"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "**YOUR_ENB_IP_ADDR**"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + +``` + + + +3- The frequency setting requires a manual update in the .C and in the gNB conf file: + + +In the C file **openair2/RRC/LTE/rrc_eNB.c:3217** +set the nrarfcn to the same value as absoluteFrequencySSB in the **gNB config file**, that is **641272** in the example below + +C file : +``` +MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272; +``` + +gNB config file : + +``` + # absoluteFrequencySSB is the central frequency of SSB + absoluteFrequencySSB = 641272; + dl_frequencyBand = 78; + # the carrier frequency is assumed to be in the middle of the carrier, i.e. dl_absoluteFrequencyPointA_kHz + dl_carrierBandwidth*12*SCS_kHz/2 + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; + # subcarrierSpacing + # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; +``` + + +## Run and Test + +The order to run the different components is important: +1- first, CN +2- then, eNB +3- then, gNB +4- finally, switch UE from airplane mode OFF to ON + +It is recommended to redirect the run commands to the same log file (fur further analysis and debug), using ```| tee **YOUR_LOG_FILE**``` especially for eNB and gNB. +It is not very useful for the CN. + +The test takes typically a few seconds, max 10-15 seconds. If it takes more than 30 seconds, there is a problem. + +- **EPC** (on EPC host): + +for reference: +https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md + + + +- **eNB** (on the eNB host): + +Execute: +``` +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O **YOUR_ENB_CONF_FILE** | tee **YOUR_LOG_FILE** + +``` + +For example: +``` +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf | tee mylogfile.log +``` + + + +- **gNB** (on the gNB host) + + +Execute: +``` +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O **YOUR_GNB_CONF_FILE** | tee **YOUR_LOG_FILE** + +``` + +For example: +``` +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf | tee mylogfile.log +``` + + +## Test Case + +The test case corresponds to the UE attachement, that is the UE connection and its initial access in 5G, as depicted below: + +**Source** : https://www.sharetechnote.com/html/5G/5G_LTE_Interworking.html + +![image info](./testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg) + +The test reaches step **12. E-RAB modifcation confirmation** , eventhough not all the messages will appear in the log file. + +## Log file monitoring + +From the log file that is generated, we can monitor several important steps, to assess that the test was successful. +Log files examples can be found here: +[enb log file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oai_enb.log) +[gnb log file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log) + + +- eNB receives UE capabilities information, including its NR capabilites, and triggers sGNB Addition Request message: + +***eNBlog.1315 :*** +``` +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE +... +[RRC] [eNB 0] frame 0 subframe 0: UE rnti 43eb switching to NSA mode +... + + + 27 + + + + + + 111 + + + 0 + + +``` + +- gNB receives sGNB Addition request, processes UE capabilities for the corresponding UE and triggers sGNB Addition Request ACK, carrying NR RRC Reconfiguration message: + + +***gNBlog.2291 :*** +``` + + + 27 + + + + + + 111 + + + 0 + + +``` + + +- Upon reception of the sGNB Addition Request ACK, the eNB sends a new RRCConnectionReconfiguration message containing the NR Reconfiguration. +The UE replies with a Reconfiguration Complete message: + +***eNBlog.1686 :*** +``` +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 1) +``` + +- The Random Access procedure of the UE to the gNB takes place: + +***gNBlog.2382 :*** +``` +[PHY] [gNB 0][RAPROC] Frame 751, slot 19 Initiating RA procedure with +preamble 63, energy 35.7 dB, delay 6 + [0m [0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751, Slot 19 Initiating RA +procedure for preamble index 63 + [0m [0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751 Activating Msg2 +generation in frame 752, slot 7 using RA rnti 10b + [0m [0m[MAC] [gNB 0] [RAPROC] CC_id 0 Frame 752, slotP 7: Generating +RAR DCI, state 1 + [0m [0m[MAC] [RAPROC] DCI type 1 payload: freq_alloc 120 (0,6,24), +time_alloc 3, vrb to prb 0, mcs 0 tb_scaling 0 + [0m [0m[MAC] Frame 752: Subframe 7 : Adding common DL DCI for RA_RNTI 10b + [0m [0m[MAC] Frame 752, Subframe 7: Setting Msg3 reception for Frame +752 Subframe 17 + [0m [0m[PHY] ULSCH received ok +``` + +- The eNB triggers the path switch procedure towards the MME, so that +the traffic can be routed now from the SGW towards the gNB on the S1-U +plane. + +***eNBlog.1691 :*** +``` + + + 50 + + + + + + 0 + + +553648130 + + +``` + + +Eventually, step **12. E-RAB Modification Confirmation** is successfully reached + + + +## Required tools for debug + +- **Wireshark** to trace X2AP and S1AP protocols +- **Ttracer** for 5G messages +- **GDB debugger** to check function calls + + +## Status of interoperability + +The following parts have been validated with FR1 COTS UE: + +- Phone accepts the configurtion provided by OAI eNB: + this validates RRC and X2AP + +- Successful Random Access Procedure: + PRACH is correctly decoded at gNB + Phone correctly receives and decodes msg2 (NR PDCCH Format 1_0 and NR PDSCH) + msg3 is transmitted to gNB according to the configuration sent in msg2, and received correctly at gNB + +- Successful path switch of user plane traffic from 4G to 5G cell (E-RAB modification message): + this validates S1AP + +- Downlink traffic: + PDCCH DCI format 1_1 and correponding PDSCH are decoded correctlyby the phone + ACK/NACK (PUCCH format 0) are successfully received at gNB + +- On going: + validation of HARQ procedures + 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z(^Ub^2fr20Af>BZ(~0>N>sKGTbmG8m&u-)UXb z>Vkf9tq5Q_&cJ-R@9K=xB{*&k54fI_a^;WhiiiWDsXMn$6Va<+ov`BkHedfl;7vf+ zK6p50EDA}oO3@Ha0xq~k+Gz=6r*uS1toXC++n-leT03VkGe>XSF+cRf@56#6&4HP! zsV};}MYo>(cITA6V6>cfbzP~gNU?#!r`fkZFFuu@e{T7rzBCrO;Oe@PO5e9XuY3tS zbD$X{-mkfLzty}h%NYV7@rzH*w?7ZQ=x)r!4-&Tl+otg>!4V|xKIPv1x&E#)XLxMo zeRgfRQhGAoHDvb{mJf3eyz}3DXy&({6Wbp~?E~6DRl5_TGRp%ic8BgO3Cu6d&XmdB zQFL+U_QKom*FTTCM{UazJeS69?_F@kN&n_#-${4&J^X&=#DV1Xt~S?>!+g&H4i%3p es~-Hi{9?)N1d0C)mWzOEUvTWP7$|YZ|2F}Z<34Ku literal 0 HcmV?d00001 diff --git a/doc/testing_gnb_w_cots_ue_resources/enb.conf b/doc/testing_gnb_w_cots_ue_resources/enb.conf new file mode 100755 index 0000000000..58e4e86873 --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/enb.conf @@ -0,0 +1,281 @@ +Active_eNBs = ( "eNB-Eurecom-LTEBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +eNBs = +( + { + # real_time choice in {hard, rt-preempt, no} + real_time = "no"; + ////////// Identification parameters: + eNB_ID = 0xe01; + + cell_type = "CELL_MACRO_ENB"; + + eNB_name = "eNB-Eurecom-LTEBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + plmn_list = ( + { mcc = 222; mnc = 01; mnc_length = 2; } + ); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "eNodeB_3GPP"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + nb_antenna_ports = 1; + ue_TransmissionMode = 1; + frame_type = "FDD"; + tdd_config = 3; + tdd_config_s = 0; + prefix_type = "NORMAL"; + eutra_band = 7; + downlink_frequency = 2680000000L; //2655000000L; + uplink_frequency_offset = -120000000; + + Nid_cell = 0; + N_RB_DL = 25; //100; + Nid_cell_mbsfn = 0; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + prach_root = 0; + tx_gain = 90; + rx_gain = 115; + pbch_repetition = "FALSE"; + prach_config_index = 0; + prach_high_speed = "DISABLE"; + prach_zero_correlation = 1; + prach_freq_offset = 2; + pucch_delta_shift = 1; + pucch_nRB_CQI = 0; + pucch_nCS_AN = 0; + pucch_n1_AN = 0; + pdsch_referenceSignalPower = -29; + pdsch_p_b = 0; + pusch_n_SB = 1; + pusch_enable64QAM = "DISABLE"; + pusch_hoppingMode = "interSubFrame"; + pusch_hoppingOffset = 0; + pusch_groupHoppingEnabled = "ENABLE"; + pusch_groupAssignment = 0; + pusch_sequenceHoppingEnabled = "DISABLE"; + pusch_nDMRS1 = 1; + phich_duration = "NORMAL"; + phich_resource = "ONESIXTH"; + srs_enable = "DISABLE"; + /* srs_BandwidthConfig =; + srs_SubframeConfig =; + srs_ackNackST =; + srs_MaxUpPts =;*/ + + pusch_p0_Nominal = -96; + pusch_alpha = "AL1"; + pucch_p0_Nominal = -96; + msg3_delta_Preamble = 6; + pucch_deltaF_Format1 = "deltaF2"; + pucch_deltaF_Format1b = "deltaF3"; + pucch_deltaF_Format2 = "deltaF0"; + pucch_deltaF_Format2a = "deltaF0"; + pucch_deltaF_Format2b = "deltaF0"; + + rach_numberOfRA_Preambles = 64; + rach_preamblesGroupAConfig = "DISABLE"; +/* + rach_sizeOfRA_PreamblesGroupA = ; + rach_messageSizeGroupA = ; + rach_messagePowerOffsetGroupB = ; +*/ + rach_powerRampingStep = 4; + rach_preambleInitialReceivedTargetPower = -108; + rach_preambleTransMax = 10; + rach_raResponseWindowSize = 10; + rach_macContentionResolutionTimer = 48; + rach_maxHARQ_Msg3Tx = 4; + + pcch_default_PagingCycle = 128; + pcch_nB = "oneT"; + bcch_modificationPeriodCoeff = 2; + ue_TimersAndConstants_t300 = 1000; + ue_TimersAndConstants_t301 = 1000; + ue_TimersAndConstants_t310 = 1000; + ue_TimersAndConstants_t311 = 10000; + ue_TimersAndConstants_n310 = 20; + ue_TimersAndConstants_n311 = 1; + + //Parameters for SIB18 + rxPool_sc_CP_Len = "normal"; + rxPool_sc_Period = "sf40"; + rxPool_data_CP_Len = "normal"; + rxPool_ResourceConfig_prb_Num = 20; + rxPool_ResourceConfig_prb_Start = 5; + rxPool_ResourceConfig_prb_End = 44; + rxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + rxPool_ResourceConfig_offsetIndicator_choice = 0; + rxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; +/* rxPool_dataHoppingConfig_hoppingParameter = 0; + rxPool_dataHoppingConfig_numSubbands = "ns1"; + rxPool_dataHoppingConfig_rbOffset = 0; + rxPool_commTxResourceUC-ReqAllowed = "TRUE"; +*/ + // Parameters for SIB19 + discRxPool_cp_Len = "normal" + discRxPool_discPeriod = "rf32" + discRxPool_numRetx = 1; + discRxPool_numRepetition = 2; + discRxPool_ResourceConfig_prb_Num = 5; + discRxPool_ResourceConfig_prb_Start = 3; + discRxPool_ResourceConfig_prb_End = 21; + discRxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + discRxPool_ResourceConfig_offsetIndicator_choice = 0; + discRxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; + + } + ); + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + enable_measurement_reports = "yes"; + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.199/24"; + + ENB_INTERFACE_NAME_FOR_S1U = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1U = "192.168.18.199/24"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + + ENB_IPV4_ADDRESS_FOR_X2C = "192.168.18.199/24"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="debug"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 160; + puCch10xSnr = 160; + } +); + +THREAD_STRUCT = ( + { + parallel_config = "PARALLEL_RU_L1_TRX_SPLITaaaaaa"; + worker_config = "ENABLE"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 118; + eNB_instances = [0]; + + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; diff --git a/doc/testing_gnb_w_cots_ue_resources/gnb.conf b/doc/testing_gnb_w_cots_ue_resources/gnb.conf new file mode 100755 index 0000000000..db8aef33ba --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/gnb.conf @@ -0,0 +1,293 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 31; //0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=13 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 0; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=1,L=13 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57) + initialDLBWPstartSymbolAndLength_3 = 57; //43; //57; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 5; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; #0x80; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; //8; //7; + nrofDownlinkSymbols = 6; //0; //6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; //0; //4; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.18.199"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.198/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.18.198/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.18.198/24"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_enb.log b/doc/testing_gnb_w_cots_ue_resources/oai_enb.log new file mode 100755 index 0000000000..9b9de24a86 --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/oai_enb.log @@ -0,0 +1,1912 @@ +[CONFIG] get parameters from libconfig ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.minimassive.master.conf , debug flags: 0x00000000 +[CONFIG] function config_libconfig_init returned 0 +[CONFIG] config module libconfig loaded +[LIBCONFIG] config: 1/1 parameters successfully set, (1 to default value) +# /dev/cpu_dma_latency set to 0us +[LIBCONFIG] log_config: 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (46 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (52 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +log init done +Reading in command-line options +[LIBCONFIG] (root): 23/23 parameters successfully set, (19 to default value) +[LIBCONFIG] (root): 5/5 parameters successfully set, (4 to default value) +Getting ENBSParams +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[ENB_APP] Impossible value: PARALLEL_RU_L1_TRX_SPLITaaaaaa +[CONFIG] parallel_conf is set to 0 +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[ENB_APP] Impossible value: ENABLE +[CONFIG] worker_conf is set to 0 +Configuration: nb_rrc_inst 1, nb_L1_inst 1, nb_ru 1 +[LIBCONFIG] loader: 2/2 parameters successfully set, (2 to default value) +[LIBCONFIG] loader.NB_IoT: 2/2 parameters successfully set, (1 to default value) + nb_nbiot_rrc_inst 0, nb_nbiot_L1_inst 0, nb_nbiot_macrlc_inst 0 +[LIBCONFIG] TTracer: 4/4 parameters successfully set, (4 to default value) +configuring for RAU/RRU +CPU Freq is 2.992899 +ITTI init, useMME: 1 +[TMR] Starting itti queue: TASK_UNKNOWN as task 0 +[TMR] Starting itti queue: TASK_TIMER as task 1 +[TMR] Starting itti queue: TASK_L2L1 as task 2 +[TMR] Starting itti queue: TASK_BM as task 3 +[TMR] Starting itti queue: TASK_PHY_ENB as task 4 +[TMR] Starting itti queue: TASK_MAC_ENB as task 5 +[TMR] Starting itti queue: TASK_RLC_ENB as task 6 +[TMR] Starting itti queue: TASK_RRC_ENB_NB_IoT as task 7 +[TMR] Starting itti queue: TASK_PDCP_ENB as task 8 +[TMR] Starting itti queue: TASK_DATA_FORWARDING as task 9 +[TMR] Starting itti queue: TASK_END_MARKER as task 10 +[TMR] Starting itti queue: TASK_RRC_ENB as task 11 +[TMR] Starting itti queue: TASK_RRC_GNB as task 12 +[TMR] Starting itti queue: TASK_RAL_ENB as task 13 +[TMR] Starting itti queue: TASK_S1AP as task 14 +[TMR] Starting itti queue: TASK_X2AP as task 15 +[TMR] Starting itti queue: TASK_M2AP_ENB as task 16 +[TMR] Starting itti queue: TASK_M2AP_MCE as task 17 +[TMR] Starting itti queue: TASK_M3AP as task 18 +[TMR] Starting itti queue: TASK_M3AP_MME as task 19 +[TMR] Starting itti queue: TASK_M3AP_MCE as task 20 +[TMR] Starting itti queue: TASK_SCTP as task 21 +[TMR] Starting itti queue: TASK_ENB_APP as task 22 +[TMR] Starting itti queue: TASK_GNB_APP as task 23 +[TMR] Starting itti queue: TASK_MCE_APP as task 24 +[TMR] Starting itti queue: TASK_MME_APP as task 25 +[TMR] Starting itti queue: TASK_FLEXRAN_AGENT as task 26 +[TMR] Starting itti queue: TASK_PHY_UE as task 27 +[TMR] Starting itti queue: TASK_MAC_UE as task 28 +[TMR] Starting itti queue: TASK_RLC_UE as task 29 +[TMR] Starting itti queue: TASK_PDCP_UE as task 30 +[TMR] Starting itti queue: TASK_RRC_UE as task 31 +[TMR] Starting itti queue: TASK_NAS_UE as task 32 +[TMR] Starting itti queue: TASK_RAL_UE as task 33 +[TMR] Starting itti queue: TASK_MSC as task 34 +[TMR] Starting itti queue: TASK_GTPV1_U as task 35 +[TMR] Starting itti queue: TASK_UDP as task 36 +[TMR] Starting itti queue: TASK_CU_F1 as task 37 +[TMR] Starting itti queue: TASK_DU_F1 as task 38 +[LIBCONFIG] opt: 3/3 parameters successfully set, (3 to default value) +[OPT] OPT disabled +reported resolution = 1 ns +[HW] Version: Branch: NR_RRC_harq_hacks Abrev. Hash: 94fa9c5 Date: Fri Jun 19 18:16:53 2020 +0200 +Runtime table +[PHY] RC.eNB = 0x2b10b70 +[LIBCONFIG] L1s.[0]: 24/24 parameters successfully set, (22 to default value) +[PHY] RC.eNB[0] = 0x2b10c20 +[PHY] RC.eNB[0][0] = 0x7f9fab347010 +[ENB_APP] Initializing northbound interface for L1 +[PHY] l1_north_init_eNB() RC.nb_L1_inst:1 +[PHY] l1_north_init_eNB() RC.nb_L1_CC[0]:1 +[PHY] l1_north_init_eNB() RC.eNB[0][0] installing callbacks +[PHY] read_config_and_init() RC.nb_L1_inst: 1 +[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (15 to default value) +[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (15 to default value) +[MAC] [MAIN] Init function start:nb_macrlc_inst=1 +[PDCP] PDCP layer has been initialized +Configuring local RRC for MACRLC +[ENB_APP] sched mode = default 0 [default] +[MAC] read_config_and_init() RC.nb_macrlc_inst: 1 +[PHY] l1_north_init_eNB() RC.nb_L1_inst:1 +[PHY] l1_north_init_eNB() RC.nb_L1_CC[0]:1 +[PHY] l1_north_init_eNB() RC.eNB[0][0] installing callbacks +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value) +[RRC] Instance 0: Southbound Transport local_mac +[RRC] Setting node_type to ngran_eNB +[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[RRC] num component carriers 1 +[RRC] enb_config::RCconfig_RRC() parameter number: 0, total number of parameters: 78, ccspath: eNBs.[0].component_carriers.[0] + +[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value) +phich.resource 0 (ONESIXTH), phich.duration 0 (NORMAL) +No eMBMS configuration, skipping it +[LIBCONFIG] eNBs.[0].component_carriers.[0].emtc_parameters: 88/88 parameters successfully set, (88 to default value) +No eMTC configuration, skipping it +[LIBCONFIG] eNBs.[0].component_carriers.[0].SLparameters: 39/39 parameters successfully set, (39 to default value) +No SL configuration skipping it +[LIBCONFIG] eNBs.[0].srb1_parameters: 6/6 parameters successfully set, (0 to default value) +[RRC] Node type 0 + [LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] NETWORK_CONTROLLER: 6/6 parameters successfully set, (6 to default value) +[LIBCONFIG] RUs.[0]: 27/27 parameters successfully set, (18 to default value) +Creating RC.ru[0]:0x2b41780 +Setting function for RU 0 to eNodeB_3GPP +[PHY] number of L1 instances 1, number of RU 1, number of CPU cores 4 +[FLEXRAN_AGENT] FlexRAN Agent for eNB 0 is DISABLED +[PDCP] PDCP layer has been initialized +[PDCP] pdcp init,usegtp +[PDCP] ENB pdcp will use tun interface for MBMS +[NETLINK]Opened socket oaitun_enm1 with fd 84 +returnValue 0 +returnValue 0 +returnValue 0 +[OIP] Interface oaitun_enm1 successfully configured, ip address 10.0.2.1, mask 255.255.255.0 broadcast address 10.0.2.255 +[ENB_APP] Creating ENB_APP eNB Task +[TMR] Created Posix thread TASK_ENB_APP +[RRC] Creating RRC eNB Task +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[TMR] Created Posix thread TASK_RRC_ENB +[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value) +[TMR] Created Posix thread TASK_SCTP +[RRC] Entering main loop of RRC message task +[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[TMR] Created Posix thread TASK_S1AP +[TMR] Created Posix thread TASK_UDP +[SCTP] Starting SCTP layer +[S1AP] Starting S1AP layer +[UDP] Initializing UDP task interface +[UDP] Initializing UDP task interface: DONE +[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value) +[LIBCONFIG] eNBs.[0].mme_ip_address.[0]: 5/5 parameters successfully set, (0 to default value) +[LIBCONFIG] eNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 11/11 parameters successfully set, (2 to default value) +[TMR] Created Posix thread TASK_GTPV1_U +[GTPV1U] Configuring GTPu +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0]: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 3/3 parameters successfully set, (0 to default value) +[GTPV1U] Configuring GTPu address : 192.168.18.199 -> c712a8c0 +[ENB_APP] default drx 2 +[ENB_APP] [eNB 0] eNB_app_register via S1AP for instance 0 +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[GTPV1U] Initializing GTPU stack 0x16968b0 +[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value) +[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[S1AP] Registered new eNB[0] and macro eNB id 3585 +[S1AP] [eNB 0] check the mme registration state +[GTPV1U] Tx UDP_INIT IP addr 192.168.18.199 (868) +[UDP] Initializing UDP for local address 192.168.18.199 with port 2152 +[TMR] Created Posix thread TASK_X2AP +[MAC] Creating MAC eNB Task +[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value) +[LIBCONFIG] list eNBs.[0].target_enb_x2_ip_address not found in config file ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.minimassive.master.conf +[LIBCONFIG] eNBs.[0]: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] eNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value) +[UDP] Inserting new descriptor for task 35, sd 85 +[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 11/11 parameters successfully set, (2 to default value) +[UDP] Initializing UDP for local address 192.168.18.199 with port 2152: DONE +[MAC] Starting main loop of MAC message task +[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (1 to default value) +[SCTP] sctp_bindx SCTP_BINDX_ADD_ADDR socket bound to : 192.168.18.199 +[X2AP] Registered new eNB[0] and macro eNB id 3585 +[X2AP] eNB[0] eNB id 3585 acting as a listner (server) +[TMR] Created Posix thread TASK_MAC_ENB +[SCTP] Converted ipv4 address 192.168.18.99 to network type +[RRC] [eNB 0] Received RRC_CONFIGURATION_REQ : 0x2b4a80c +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Init... +[SCTP] connectx assoc_id 903 in progress..., used 1 addresses +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Checking release +[SCTP] Inserted new descriptor for sd 86 in list, nb elements 1, assoc_id 903 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Rel14 RRC detected, MBMS flag 0 +[SCTP] Received SCTP_INIT_MSG_MULTI_REQ +[RRC] [eNB 0] Node type 0 + [SCTP] Creating new listen socket on port 36422 with +[SCTP] ipv4 addresses: +[SCTP] - 192.168.18.199 +[RRC] configuration->schedulingInfoSIB1_BR_r13[CC_id] 0 +[RRC] Configuring MIB (N_RB_DL 25,phich_Resource 0,phich_Duration 0) +[RRC] [MIB] systemBandwidth 2, phich_duration 0, phich_resource 0, sfn 0 +[RRC] [MIB] schedulingInfoSIB1 0 +[RRC] [eNB 0] Configuration SIB2/3, eMBMS = 0 +[RRC] do_SIB23, size 38 + [MAC] Configuring MIB for instance 0, CCid 0 : (band 7,N_RB_DL 25,Nid_cell 0,p 1,DL freq 2680000000,phich_config.resource 0, phich_config.duration 0) +[MAC] config_mib() NFAPI_CONFIG_REQUEST(num_tlv:16) DL_BW:25 UL_BW:25 Ncp 0,p_eNB 1,earfcn 3350,band 7,phich_resource 0 phich_duration 0 phich_power_offset 6000 PSS 6000 SSS 6000 PCI 0 PBCH repetition 0 +[MAC] [CONFIG]SIB2/3 Contents (partial) +[MAC] [CONFIG]pusch_config_common.n_SB = 1 +[MAC] [CONFIG]pusch_config_common.hoppingMode = 0 +[MAC] [CONFIG]pusch_config_common.pusch_HoppingOffset = 0 +[MAC] [CONFIG]pusch_config_common.enable64QAM = 0 +[MAC] [CONFIG]pusch_config_common.groupHoppingEnabled = 1 +[MAC] [CONFIG]pusch_config_common.groupAssignmentPUSCH = 0 +[MAC] [CONFIG]pusch_config_common.sequenceHoppingEnabled = 0 +[MAC] [CONFIG]pusch_config_common.cyclicShift = 1 +[PHY] Configuring MIB for instance 0, CCid 0 : (band 7,N_RB_DL 25, N_RB_UL 25, Nid_cell 0,eNB_tx_antenna_ports 1,Ncp 0,DL freq 3350,phich_config.resource 0, phich_config.duration 0) +[PHY] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 +[PHY] lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32769 +[SCTP] Client association changed: 0 +[SCTP] ---------------------- +[SCTP] Peer addresses: +[SCTP] - [192.168.18.99] +[SCTP] ---------------------- +[SCTP] ---------------------- +[SCTP] SCTP Status: +[SCTP] assoc id .....: 903 +[SCTP] state ........: 4 +[SCTP] instrms ......: 2 +[SCTP] outstrms .....: 2 +[SCTP] fragmentation : 1452 +[SCTP] pending data .: 0 +[SCTP] unack data ...: 0 +[SCTP] rwnd .........: 106496 +[SCTP] peer info : +[SCTP] state ....: 2 +[SCTP] cwnd .....: 4380 +[SCTP] srtt .....: 0 +[SCTP] rto ......: 3000 +[SCTP] mtu ......: 1500 +[SCTP] ---------------------- +[SCTP] Comm up notified for sd 86, assigned assoc_id 903 +[S1AP] 3585 -> 00e010 + + + 17 + + + + + + 59 + + + + 22 F2 10 + + + 00000000111000000001 + + + + + + + 60 + + + eNB-Eurecom-LTEBox + + + + 64 + + + + + 00 01 + + 22 F2 10 + + + + + + + 137 + + + + + + + + + + +[SCTP] Successfully sent 59 bytes on stream 0 for assoc_id 903 +[LIBCONFIG] loader.coding: 2/2 parameters successfully set, (1 to default value) +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 58 received from port 36412, on stream 0, PPID 18 +[S1AP] servedGUMMEIs.list.count 3 +[S1AP] servedPLMNs.list.count 1 +[S1AP] servedPLMNs.list.count 1 +[S1AP] servedPLMNs.list.count 1 +[ENB_APP] [eNB 0] Received S1AP_REGISTER_ENB_CNF: associated MME 1 +[LOADER] library libcoding.so successfully loaded +[PHY] prach_config_common.rootSequenceIndex = 0 +[PHY] prach_config_common.prach_ConfigInfo.prach_ConfigIndex = 0 +[PHY] prach_config_common.prach_ConfigInfo.highSpeedFlag = 0 +[PHY] prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = 1 +[PHY] prach_config_common.prach_ConfigInfo.prach_FreqOffset = 2 +[PHY] pusch_config_common.n_SB = 1 +[PHY] pusch_config_common.hoppingMode = 0 +[PHY] pusch_config_common.pusch_HoppingOffset = 0 +[PHY] pusch_config_common.enable64QAM = 0 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.groupHoppingEnabled = 1 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH = 0 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled = 0 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift = 2 +[PHY] eNB 0/0 configured +[RRC] [eNB] handover active state is 0 +[RRC] [eNB] eMBMS active state is 0 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] ENB:OPENAIR RRC IN.... +[ENB_APP] START MAIN THREADS +RC.nb_L1_inst:1 +Initializing eNB threads single_thread_flag:0 wait_for_sync:0 +[PHY] [lte-softmodem.c] eNB structure about to allocated RC.nb_L1_inst:1 RC.nb_L1_CC[0]:1 +[PHY] [lte-softmodem.c] eNB structure RC.eNB allocated +[PHY] Initializing eNB 0 CC_id 0 single_thread_flag:0 +[PHY] Initializing eNB 0 CC_id 0 +[PHY] Registering with MAC interface module +[PHY] Setting indication lists +[PHY] [lte-softmodem.c] eNB structure allocated +wait_eNBs() +Waiting for eNB L1 instances to all get configured ... sleeping 50ms (nb_L1_inst 1) +RC.nb_L1_CC[0]:1 +eNB L1 are configured +About to Init RU threads RC.nb_RU:1 +Initializing RU threads +[PHY] DJP - delete code above this /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/targets/RT/USER/lte-ru.c:2739 +[PHY] Copying frame parms from eNB 0 to ru 0 +[PHY] Initializing RRU descriptor 0 : (local RF,synch_to_ext_device,0) +configuring ru_id 0 (start_rf 0x5b1a00) +[PHY] Starting ru_thread 0, is_slave 0, send_dmrs 0 +[PHY] Initializing RU proc 0 (eNodeB_3GPP,synch_to_ext_device), +[PHY] init_RU_proc() DJP - added creation of pthread_prach +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[HW] [SCHED][eNB] ru_thread started on CPU 1, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[PHY] thread ru created id=7295 +[PHY] Starting RU 0 (eNodeB_3GPP,synch_to_ext_device), +waiting for sync (ru_thread,-1/0xff4968,0x17af520,0x16952a0) +channel 0, Setting tx_gain offset 0.000000, rx_gain offset 118.000000, tx_freq 2680000000.000000, rx_freq 2560000000.000000 +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[PHY] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 +[PHY] lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 +[PHY] Initializing RU signal buffers (if_south local RF) nb_tx 1 +[HW] [SCHED][eNB] ru_thread_prach started on CPU 2, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[PHY] [INIT] common.txdata[0] = 0x7f9fafc66010 (307200 bytes) +[PHY] ru_thread_prach() RU configured - RACH processing thread running +[LIBCONFIG] loader.dfts: 2/2 parameters successfully set, (1 to default value) +[LOADER] library libdfts.so successfully loaded +[PHY] nb_tx 1 +[PHY] rxdata_7_5kHz[0] 0x2b9c1c0 for RU 0 +[PHY] [INIT] common.txdata_BF= 0x2b4ae80 (8 bytes) +[PHY] txdataF_BF[0] 0x2bba1e0 for RU 0 +[PHY] rxdataF[0] 0x2bc1200 for RU 0 +[LIBCONFIG] device.recplay: 7/7 parameters successfully set, (7 to default value) +[LIBCONFIG] device: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] loader.oai_device: 2/2 parameters successfully set, (1 to default value) +[LOADER] library liboai_device.so successfully loaded +[HW] UHD version 3.13.0.HEAD-0-g0ddc19e5 (3.13.0) +[HW] Found USRP b200 +Found USRP b200 +[HW] Clock source set neither in usrp_args nor on command line, using default! +[HW] Time source set neither in usrp_args nor on command line, using default! +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32769 +[SCTP] Client association changed: 0 +[SCTP] Comm up notified for sd 87, assigned assoc_id 904 +[SCTP] ---------------------- +[SCTP] SCTP Status: +[SCTP] assoc id .....: 904 +[SCTP] state ........: 4 +[SCTP] instrms ......: 32 +[SCTP] outstrms .....: 32 +[SCTP] fragmentation : 1452 +[SCTP] pending data .: 0 +[SCTP] unack data ...: 0 +[SCTP] rwnd .........: 106496 +[SCTP] peer info : +[SCTP] state ....: 2 +[SCTP] cwnd .....: 4380 +[SCTP] srtt .....: 0 +[SCTP] rto ......: 3000 +[SCTP] mtu ......: 1500 +[SCTP] ---------------------- +x2ap_eNB_handle_sctp_association_ind at 1 (called for instance 0) +here comes the tree (instance 0): +--------------------------------------------- +--------------------------------------------- +x2ap_eNB_handle_sctp_association_ind at 2 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 2 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id 0 +--------------------------------------------- +x2ap_eNB_handle_sctp_association_ind at 3 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 2 +nextstream 0 +in_streams 32 out_streams 32 +cnx_id 1 assoc_id 904 +--------------------------------------------- +[SCTP] Found data for descriptor 95 +[SCTP] [904][95] Msg of length 66 received from port 36422, on stream 0, PPID 27 + + + 36 + + + + + + 244 + + + + + + 252 + + + + 22 F2 10 + + + 00000000000000000000111000000000 + + + + + + + 253 + + + + + + 0 + + 22 F2 10 + + 000000000000000000000000111000000000 + + + 00 64 90 + + 22 F2 10 + + + + + 0 + + + 1 + + + 80 + + + + + + + + + + + + 00 + + + + + + + + + + + + + + +[X2AP] X2AP_ProcedureCode_id_endcX2Setup message! +[X2AP] TAC: 006490 +[X2AP] PLMN: 22f210 + + + 36 + + + + + + 246 + + + + + + 21 + + + + 22 F2 10 + + + 00000000111000000001 + + + + + + + 250 + + + + + + 0 + + 22 F2 10 + + 0000000011100000000100000000 + + + 00 01 + + 22 F2 10 + + + + 21350 + 3350 + + + + + + + + + + + + + + + + + + +[SCTP] Successfully sent 53 bytes on stream 0 for assoc_id 904 +[SCTP] Found data for descriptor 95 +[SCTP] Received notification for sd 95, type 32777 +[HW] cal 0: freq 3500000000.000000, offset 44.000000, diff 940000000.000000 +[HW] cal 1: freq 2660000000.000000, offset 49.800000, diff 100000000.000000 +[HW] cal 2: freq 2300000000.000000, offset 51.000000, diff 260000000.000000 +[HW] cal 3: freq 1880000000.000000, offset 53.000000, diff 680000000.000000 +[HW] cal 4: freq 816000000.000000, offset 57.000000, diff 1744000000.000000 +[HW] RX Gain 0 118.000000 (55.800000) => 62.200000 (max 76.000000) +[HW] USRP TX_GAIN:89.75 gain_range:89.75 tx_gain:0.00 +[HW] Actual master clock: 30.720000MHz... +[HW] Actual clock source internal... +[HW] Actual time source internal... +[HW] RF board max packet size 1916, size for 100µs jitter 768 +[HW] rx_max_num_samps 768 +[HW] RX Channel 0 +[HW] Actual RX sample rate: 7.680000MSps... +[HW] Actual RX frequency: 2.560000GHz... +[HW] Actual RX gain: 62.000000... +[HW] Actual RX bandwidth: 20.000000M... +[HW] Actual RX antenna: RX2... +[HW] TX Channel 0 +[HW] Actual TX sample rate: 7.680000MSps... +[HW] Actual TX frequency: 2.680000GHz... +[HW] Actual TX gain: 89.750000... +[HW] Actual TX bandwidth: 20.000000M... +[HW] Actual TX antenna: TX/RX... +[HW] Actual TX packet size: 1916 +[HW] Device timestamp: 1.703971... +[HW] [RAU] has loaded USRP B200 device. +setup_RU_buffers: frame_parms = 0x7f9fab347e68 +[PHY] Signaling main thread that RU 0 (is_slave 0,send_dmrs 0) is ready in state RU_RUN +wait RUs +[ENB_APP] Waiting for RUs to be configured ... RC.ru_mask:00 +[PHY] RUs configured +[ENB_APP] RC.nb_RU:1 +ALL RUs ready - init eNBs +[ENB_APP] Not NFAPI mode - call init_eNB_afterRU() +[PHY] init_eNB_afterRU() RC.nb_inst:1 +[PHY] RC.nb_CC[inst]:1 +[PHY] RC.nb_CC[inst:0][CC_id:0]:0x7f9fab347010 +[PHY] [eNB 0] phy_init_lte_eNB() About to wait for eNB to be configured[PHY] [eNB 0] Initializing DL_FRAME_PARMS : N_RB_DL 25, PHICH Resource 1, PHICH Duration 0 nb_antennas_tx:0 nb_antennas_rx:1 nb_antenna_ports_eNB:1 PRACH[rootSequenceIndex:0 prach_Config_enabled:1 configIndex:0 highSpeed:0 zeroCorrelationZoneConfig:1 freqOffset:2] +[PHY] [eNB 0] Initializing DL_FRAME_PARMS : N_RB_DL 25, PHICH Resource 1, PHICH Duration 0 +pcfich_reg : 0,12,25,37 +[PHY] [INIT] NB_ANTENNA_PORTS_ENB:6 fp->nb_antenna_ports_eNB:1 +[PHY] [INIT] common_vars->txdataF[0] = 0x7f9fafb87010 (286720 bytes) +[PHY] [INIT] common_vars->txdataF[5] = 0x7f9fa80ff010 (286720 bytes) +[PHY] Mapping RX ports from 1 RUs to eNB 0 +[PHY] Overwriting eNB->prach_vars.rxsigF[0]:0x330a6c0 +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] eNB->num_RU:1 +[PHY] Attaching RU 0 antenna 0 to eNB antenna 0 +[PHY] init_eNB_afterRU() ************* DJP ***** eNB->frame_parms.nb_antennas_tx:0 - GOING TO HARD CODE TO 1[PHY] inst 0, CC_id 0 : nb_antennas_rx 1 +[PHY] Initialise transport +[PHY] init_eNB_proc(inst:0) RC.nb_CC[inst]:1 +[PHY] Initializing eNB processes instance:0 CC_id 0 +[PHY] eNB->single_thread_flag:0 +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[HW] [SCHED][eNB] eNB_thread_prach started on CPU 0, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[ENB_APP] ALL RUs ready - ALL eNBs ready +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[HW] [SCHED][eNB] eNB_thread_prach_br started on CPU 0, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[ENB_APP] Sending sync to all threads +[MME_APP] Creating MME_APP eNB Task +got sync (ru_thread) +[TMR] Created Posix thread TASK_MME_APP +[HW] Time in secs now: 22168192 +[LIBCONFIG] MMEs.[0]: 1/1 parameters successfully set, (1 to default value) +[MCE_APP] Creating MCE_APP eNB Task +[HW] Time in secs last pps: 21747824 +[PHY] RU 0 rf device ready +[TMR] Created Posix thread TASK_MCE_APP +[LIBCONFIG] MCEs.[0]: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] MCEs.[0]: 1/1 parameters successfully set, (1 to default value) +[ENB_APP] TYPE TO TERMINATE +[ENB_APP] [MCE 0] MCE_app_register via M3AP for instance 0 +[HW] [recv] received 0 samples out of 7680 +[HW] ERROR_CODE_OVERFLOW (Out of sequence error) + +[PHY] rx_rf: Asked for 7680 samples, got 0 from SDR +[PHY] problem receiving samples[MAC] SCHED_MODE = 0 +[PHY] rx_rf: rfdevice timing drift of 22200737 samples (ts_off 0) +[PHY] prach_I0 = 0.0 dB +[PHY] max_I0 18, min_I0 0 +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb] Decoding UL CCCH 59.e8.a9.2.18.72 (0x3a52693) +[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb] Accept new connection from UE random UE identity (0x8721908a9e000000) MME code 0 TMSI 0 cause 1 +[MAC] UE 0 RNTI 43eb adding LC 1 idx 0 to scheduling control (total 1) +[MAC] UE 0 RNTI 43eb adding LC 2 idx 1 to scheduling control (total 2) +[MAC] Added physicalConfigDedicated 0x7f9f600085d0 for 0.0 +[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb]CALLING RLC CONFIG SRB1 (rbid 1) +add new uid is 0 43eb + +[PDCP] [FRAME 00738][eNB][MOD 00][RNTI 43eb][SRB 01] Action ADD LCID 1 (SRB id 1) configured with SN size 5 bits and RLC AM +[MAC] generate_Msg4 ra->Msg4_frame SFN/SF: 739.2, frameP SFN/SF: 739.2 FOR eNB_Mod: 0 +[MAC] [eNB 0][RAPROC] CC_id 0 Frame 739, subframeP 2: Generating Msg4 with RRC Piggyback (RNTI 43eb) +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 6] CC_id 0 740.6 ULSCH in error in round 0, ul_cqi 132, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 741.4 ULSCH in error in round 1, ul_cqi 138, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 742.2 ULSCH in error in round 2, ul_cqi 134, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 743.0 ULSCH in error in round 3, ul_cqi 132, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 743.8 ULSCH in error in round 0, ul_cqi 140, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 744.6 ULSCH in error in round 1, ul_cqi 140, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 745.4 ULSCH in error in round 2, ul_cqi 142, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 746.2 ULSCH in error in round 3, ul_cqi 143, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 747.0 ULSCH in error in round 0, ul_cqi 143, UE_id 0, RNTI 43eb (len 63) +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 0] CC_id 0 748.8 ULSCH in error in round 0, ul_cqi 146, UE_id 0, RNTI 43eb (len 63) +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] [RAPROC] Logical Channel UL-DCCH, processing LTE_RRCConnectionSetupComplete from UE (SRB1 Active) +[NAS] AttachRequest.c:40 EMM - attach_request len = 97 +[NAS] UeNetworkCapability.c:46 decode_ue_network_capability len = 7 +[NAS] UeNetworkCapability.c:63 uenetworkcapability decoded UMTS + +[NAS] UeNetworkCapability.c:74 uenetworkcapability decoded GPRS + +[NAS] UeNetworkCapability.c:82 uenetworkcapability decoded=6 + +[NAS] UeNetworkCapability.c:86 uenetworkcapability then decoded=8 + +[NAS] AttachRequest.c:285 EMM: Can't decode the message with iei 111 + +[S1AP] [eNB 0] Build S1AP_NAS_FIRST_REQ adding in s_TMSI: GUMMEI mme_code 1 mme_group_id 32768 ue 43eb +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_CONNECTED +[S1AP] [eNB 0] Chose MME 'MME 1' (assoc_id 903) through GUMMEI MCC 222 MNC 1 MMEGI 32768 MMEC 1 +[S1AP] Found usable eNB_ue_s1ap_id: 0x06692d 420141(10) +[S1AP] GUMMEI_ID_PRESENT + + + 12 + + + + + + 8 + + + 420141 + + + + 26 + + + + 17 A0 9C 9B 3F 04 07 41 02 0B F6 22 F2 10 80 00 + 01 00 00 00 37 07 F0 70 C0 40 10 00 10 00 2A 02 + 1F D0 11 D1 27 23 80 80 21 10 01 00 00 10 81 06 + 00 00 00 00 83 06 00 00 00 00 00 0D 00 00 0A 00 + 00 05 00 00 10 00 00 11 00 52 22 F2 10 00 01 5C + 0A 00 31 04 E5 E0 34 01 90 11 03 57 58 A6 5D 01 + 00 E0 C1 6F 04 F0 00 70 00 + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 134 + + + + + + + 75 + + + + 22 F2 10 + 80 00 + 01 + + + + + + + + +[SCTP] Successfully sent 164 bytes on stream 1 for assoc_id 903 +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 32 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 3] CC_id 0 752.3 ULSCH in error in round 0, ul_cqi 146, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 752.8 ULSCH in error in round 0, ul_cqi 152, UE_id 0, RNTI 43eb (len 63) + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 17 A8 76 C5 F5 05 07 56 08 29 22 10 10 00 00 11 + 04 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 68 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 65 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 4] CC_id 0 761.2 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63) +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 10 PUCCH SNR 10 + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 17 9B EE 3B BF 06 07 53 08 ED CA A1 31 56 26 D7 + E1 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 68 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 51 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + 47 86 59 47 B7 00 07 5E + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 59 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 38 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 27 F5 4A 60 81 01 02 1F DA 28 09 03 6F 61 69 04 + 69 70 76 34 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 71 bytes on stream 1 for assoc_id 903 +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 235 received from port 36412, on stream 1, PPID 18 +[S1AP] Received NAS message with the E_RAB setup procedure +[RRC] [eNB 0] Received S1AP_INITIAL_CONTEXT_SETUP_REQ: ue_initial_id 1, eNB_ue_s1ap_id 420141, nb_of_e_rabs 1 +[GTPV1U] Configured GTPu address : c712a8c0 +[GTPV1U] Copied to create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.199 length 4 gtp teid 3396329693 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (3396329693, 3396329693) bearer UE context index 0, msg index 0, id 5, gtp addr len 4 +[RRC] [eNB 0][UE 43eb] Selected security algorithms (0x7f9f9400213c): 0, 2, changed +[RRC] [eNB 0][UE 43eb] Saved security key 107FB5D1A79727631F15C38738093134AAF72931EA06D9495605EDB00D8D8044 +[RRC]  +KeNB:10 7f b5 d1 a7 97 27 63 1f 15 c3 87 38 09 31 34 aa f7 29 31 ea 06 d9 49 56 05 ed b0 0d 8d 80 44 +[RRC]  +KRRCenc:1b 33 28 35 5a 74 f3 6a 05 c6 cf 34 e9 be 54 63 7b a8 5a 48 1d 72 54 67 ae b0 12 a4 1d 3b 7d 86 +[RRC]  +KRRCint:ba a3 e0 18 79 1e 68 44 c6 60 dd c9 a8 8c 65 c2 e8 74 09 da 28 d6 f2 d9 6f ad da 41 d7 ec 8e 71 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate SecurityModeCommand (bytes 3) +[RRC] calling rrc_data_req :securityModeCommand +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received securityModeComplete on UL-DCCH 1 from UE +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate UECapabilityEnquiry (bytes 3) +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE +[RRC] got UE capabilities for UE 43eb +[RRC] drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated +[RRC] [eNB 0] frame 0: requesting A2, A3, A4, and A5 event reporting + + + 22 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 74 + + + + 04 43 DA 01 08 87 7D DB 80 51 81 80 01 04 0C 20 + 71 63 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF + CC 58 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C + 00 8C 85 3C 10 65 3A 54 95 1F C0 77 7E 00 00 00 + 00 02 04 BD 80 00 00 08 09 DF 00 00 00 02 F5 C0 + 0C 00 A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 + 03 04 01 82 00 C1 08 60 84 30 42 18 21 0A 08 03 + 04 01 82 00 C1 00 60 84 30 42 18 20 0C 10 06 08 + 03 04 01 82 00 A1 80 01 04 30 00 20 86 00 04 10 + C0 00 82 18 00 10 43 00 02 08 40 00 61 00 01 84 + 00 82 10 00 18 40 08 21 00 01 84 00 82 10 00 18 + 40 08 21 00 01 84 00 82 10 02 08 60 08 43 0C 01 + 08 61 80 21 0C 30 04 21 84 00 86 10 02 18 40 08 + 61 00 21 84 00 86 10 02 18 60 08 43 0C 01 08 61 + 80 21 0C 30 04 21 84 00 86 10 02 18 40 08 61 00 + 21 84 00 86 10 02 18 41 08 61 04 21 84 10 86 08 + 43 04 21 82 10 C1 08 60 04 84 00 86 10 02 18 40 + 08 61 00 21 84 00 86 10 02 18 21 0C 10 86 10 00 + 18 40 00 60 80 30 03 00 25 A0 7D 54 6C 1E 00 00 + 35 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 10 + 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 06 + 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 80 + 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 00 + 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 00 + 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 02 + 08 0D A1 00 0F F0 00 40 05 7C 20 63 00 02 08 3B + 60 00 80 8C 10 41 5B 08 18 C0 00 82 0E 98 00 20 + 23 04 10 54 C2 06 30 00 20 83 8C 00 08 28 41 04 + 14 60 83 84 00 08 20 E3 00 02 0A 00 41 05 18 20 + E0 00 02 08 2B E1 03 00 00 10 01 DB 00 04 04 00 + 82 0A D8 40 C0 00 04 10 74 C0 01 01 00 20 82 A6 + 10 30 00 01 04 1C 20 00 41 40 08 20 A1 04 1C 00 + 00 41 05 7C 20 61 00 02 08 3B 60 00 80 84 10 41 + 5B 08 18 40 00 82 0E 98 00 20 21 04 10 54 C2 06 + 10 00 20 82 BE 10 34 C0 01 00 35 F0 81 A6 00 08 + 08 C1 05 08 20 06 BE 10 14 C2 06 30 00 20 A1 04 + 00 D7 C2 02 98 40 46 08 38 40 00 80 1A F8 40 D3 + 00 04 04 60 82 80 10 03 5F 08 0A 61 03 18 00 10 + 50 02 00 6B E1 01 4C 20 23 04 1C 00 00 40 09 7C + 20 69 80 02 02 30 41 09 7C 20 29 84 0C 60 00 41 + 09 7C 20 63 00 02 0A 10 48 09 7C 20 63 00 02 02 + 10 49 09 7C 20 23 04 1C 20 00 48 09 7C 20 23 04 + 0C 20 00 49 09 7C 20 63 00 02 0A 10 40 09 7C 20 + 63 00 02 02 10 41 09 7C 20 23 04 1C 20 00 40 09 + 7C 20 23 04 0C 20 00 41 09 7C 20 63 00 02 0A 00 + 40 09 7C 20 23 04 1C 00 00 40 0F 6C 00 10 11 82 + 0A 10 41 40 08 21 AD 84 0C 60 00 41 42 08 28 01 + 04 35 B0 80 8C 10 70 80 01 05 00 20 86 B6 10 11 + 82 0A 10 41 C0 00 04 10 B6 C0 01 01 18 20 A1 04 + 10 96 C2 06 30 00 20 A1 04 10 96 C2 02 30 41 C2 + 00 04 10 B6 C0 01 01 18 20 A0 04 10 96 C2 06 30 + 00 20 A0 04 10 96 C2 02 30 41 C0 00 04 10 F4 C0 + 01 01 18 20 A1 04 14 00 82 1A 98 40 C6 00 04 14 + 20 82 80 10 43 53 08 08 C1 07 08 00 10 50 02 08 + 6A 61 01 18 20 A1 04 1C 00 00 41 0B 4C 00 10 11 + 82 0A 10 41 09 4C 20 63 00 02 0A 10 41 09 4C 20 + 23 04 1C 20 00 41 0B 4C 00 10 11 82 0A 00 41 09 + 4C 20 63 00 02 0A 00 41 09 4C 20 23 04 1C 00 00 + 41 0B 18 00 10 50 82 0A 00 41 09 18 20 E1 00 02 + 0A 00 41 09 18 20 A1 04 1C 00 00 41 07 18 04 12 + 50 82 08 28 C1 27 08 00 10 41 C6 00 04 14 20 92 + 0A 30 41 C2 01 04 90 31 80 41 24 25 F0 81 A6 00 + 08 08 01 00 25 F0 80 A6 10 30 00 01 00 2D B0 00 + 40 42 08 28 01 04 25 B0 81 84 00 08 28 01 04 25 + B0 80 84 10 70 00 01 04 2D 30 00 40 42 08 28 01 + 04 25 30 81 84 00 08 28 01 04 25 30 80 84 10 70 + 00 01 04 1C 20 00 41 40 09 20 A1 04 1C 00 00 49 + 09 7C 20 69 80 02 02 10 41 09 7C 20 29 84 0C 20 + 00 41 05 7C 20 61 00 02 48 18 40 20 92 07 28 08 + 24 EB B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F + FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF + FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF + FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC + 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 + BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF + FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF + EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF + F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 + FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 + FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF + FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF + 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF + 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F + FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF + FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF + FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB + 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC + AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF + FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F + FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF + FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F F6 CE C0 00 0F D8 81 B3 B0 + 00 00 8F 9D 80 00 1A C0 00 00 08 78 78 BC 5E 1E + 1E 1E 1D 0F 0E 43 C3 A1 E1 E1 E1 E1 C0 00 08 78 + 78 78 71 17 8B C5 E1 E1 E1 E1 E1 E1 E1 E2 F1 78 + BC 3C 3C 3C 3C 39 17 00 01 F5 80 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 80 82 00 80 20 08 02 00 80 20 08 02 00 + 80 20 08 02 00 80 20 08 02 00 80 20 08 02 00 80 + 60 01 80 06 00 18 00 60 01 80 04 00 40 04 00 40 + 04 00 40 04 00 40 04 00 40 04 00 40 06 00 18 00 + 60 01 80 04 00 40 04 00 40 04 00 40 06 00 18 00 + 60 01 80 04 00 40 04 00 40 04 00 40 04 00 40 04 + 00 20 08 02 00 80 00 40 04 00 40 04 00 40 04 00 + 40 04 00 20 08 04 00 40 02 00 00 1F 04 01 20 03 + E6 57 9A 04 01 4B 1F FF FF FF FF FF FE 69 4B BC + 50 0F 80 04 20 09 86 00 00 00 00 00 05 50 92 48 + 81 01 00 02 F2 42 0B 51 40 01 34 00 00 00 + + + + + [RRC] RRCConnectionReconfiguration Encoded 1796 bits (225 bytes) +[RRC] [eNB 0] Frame 0, Logical Channel DL-DCCH, Generate LTE_RRCConnectionReconfiguration (bytes 225, UE id 43eb) + [RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB + + + [PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][SRB 02] Action ADD LCID 2 (SRB id 2) configured with SN size 5 bits and RLC AM + + +[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][DRB 01] Action ADD LCID 3 (DRB id 1) configured with SN size 12 bits and RLC AM +[SCTP] Successfully sent 2206 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 2) +[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][SRB 02] Action MODIFY LCID 2 RB id 2 reconfigured with SN size 5 and RLC AM +[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][DRB 01] Action MODIFY LCID 3 RB id 1 reconfigured with SN size 1 and RLC AM +[RRC] [eNB 0] Frame 0 CC 0 : SRB2 is now active +[RRC] [eNB 0] Frame 0 : Logical Channel UL-DCCH, Received LTE_RRCConnectionReconfigurationComplete from UE rnti 43eb, reconfiguring DRB 1/LCID 3 +[RRC] [eNB 0] Frame 0 : Logical Channel UL-DCCH, Received LTE_RRCConnectionReconfigurationComplete from UE 0, reconfiguring DRB 1/LCID 3 +[MAC] UE 0 RNTI 43eb adding LC 3 idx 2 to scheduling control (total 3) +[MAC] Added physicalConfigDedicated 0x7f9f600085d0 for 0.0 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate NR UECapabilityEnquiry (bytes 27) +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[S1AP] initial_ctxt_resp_p: e_rab ID 5, enb_addr 192.168.18.199, SIZE 4 + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + 27 22 5C 78 F3 02 07 43 00 03 52 00 C2 + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 64 bytes on stream 1 for assoc_id 903 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE +[RRC] got UE capabilities for UE 43eb +[MAC] [eNB 0][PUSCH 7] CC_id 0 796.7 ULSCH in error in round 0, ul_cqi 152, UE_id 0, RNTI 43eb (len 63) +[RRC] [eNB 0] frame 0 subframe 0: UE rnti 43eb switching to NSA mode +[RRC] Read in 2056 bytes for uecap + + + 27 + + + + + + 111 + + + 0 + + + + 248 + + + + + 0000000000000000 + + + 0000000000000000 + + + + + + 203 + + + + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + + + + + 204 + + + + 100000000 + 100000000 + + + + + 205 + + + + + 209 + + + + 5 + 1 + + + + + + + + + 1 + + 15 + + + + + + + 11000000101010000001001001100011 + + 00 00 00 02 + + + + + + + + + + + 206 + + + + 3A 03 08 78 8D DB 80 51 81 80 01 04 0C 20 71 63 + 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF CC 58 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C 00 8C + 85 3C 10 65 3A 54 97 1F C0 68 FE 00 00 00 00 02 + 04 BD 80 00 00 08 09 DF 00 00 00 02 EE C0 0C 00 + A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 03 04 + 01 82 10 C1 08 60 84 30 42 18 20 0C 10 06 08 43 + 04 21 82 00 C1 00 60 80 30 40 18 20 0C 10 06 18 + 02 10 C3 00 42 18 60 08 43 0C 01 08 61 80 21 0C + 30 04 21 86 00 84 30 C0 10 86 10 02 18 40 08 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 10 02 18 20 0C 10 06 18 02 10 C3 00 42 18 60 08 + 43 0C 01 08 61 00 21 84 00 86 10 02 18 41 08 61 + 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 86 + 10 42 18 41 08 60 84 30 42 18 21 0C 10 86 00 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 08 43 04 21 82 00 C1 00 60 04 B4 7D 54 6C 1E 00 + 00 2E 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 + 10 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 + 06 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 + 80 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 + 00 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 + 00 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 + 02 08 0D A1 00 0F F0 00 40 07 4C 00 10 11 82 08 + 2A 61 03 18 00 10 41 C7 00 04 04 60 82 0A 38 40 + C6 00 04 10 71 80 01 05 08 20 82 8C 10 70 80 01 + 04 1C 60 00 41 40 08 20 A3 04 1C 00 00 41 07 4C + 00 10 10 02 08 2A 61 03 00 00 10 41 C2 00 04 14 + 00 82 0A 10 41 C0 00 04 10 76 C0 01 01 08 20 82 + B6 10 30 80 01 04 1D 30 00 40 42 08 20 A9 84 0C + 20 00 41 07 1C 00 10 10 82 08 28 E1 03 08 00 10 + 43 D3 00 04 04 60 82 84 12 50 02 08 6A 61 03 18 + 00 10 50 82 4A 00 41 0D 4C 20 23 04 1C 20 00 49 + 40 08 21 A9 84 04 60 82 84 12 70 00 01 04 3D 30 + 00 40 46 08 28 41 05 00 20 86 A6 10 31 80 01 05 + 08 20 A0 04 10 D4 C2 02 30 41 C2 00 04 14 00 82 + 1A 98 40 46 08 28 41 07 00 00 10 42 D3 00 04 04 + 60 82 84 12 42 53 08 18 C0 00 82 84 12 42 53 08 + 08 C1 07 08 00 12 42 D3 00 04 04 60 82 84 10 42 + 53 08 18 C0 00 82 84 10 42 53 08 08 C1 07 08 00 + 10 42 D3 00 04 04 60 82 80 10 42 53 08 18 C0 00 + 82 80 10 42 53 08 08 C1 07 00 00 10 41 D3 00 04 + 04 60 92 0A 98 40 C6 00 04 90 F1 C0 01 01 18 20 + A1 04 14 00 82 1A 38 40 C6 00 04 14 20 82 80 10 + 43 47 08 08 C1 07 08 00 10 50 02 08 68 E1 01 18 + 20 A1 04 1C 00 00 41 0B 1C 00 10 11 82 0A 10 41 + 09 1C 20 63 00 02 0A 10 41 09 1C 20 23 04 1C 20 + 00 41 0B 18 00 12 50 82 0A 00 41 09 18 24 E1 00 + 02 0A 00 41 09 18 24 A1 04 1C 00 00 41 0B 18 00 + 10 50 82 4A 00 41 09 18 20 E1 00 02 4A 00 41 09 + 18 20 A1 04 9C 00 00 41 0B 18 00 10 50 82 0A 00 + 41 09 18 20 E1 00 02 0A 00 41 09 18 20 A1 04 1C + 00 00 41 07 18 04 12 50 82 08 28 C1 27 08 00 10 + 41 C6 00 04 14 20 92 0A 30 41 C2 01 04 90 31 80 + 41 24 2D 30 00 40 42 09 28 01 04 25 30 81 84 00 + 09 28 01 04 25 30 80 84 12 70 00 01 04 2D 30 00 + 40 42 08 28 01 04 25 30 81 84 00 08 28 01 04 25 + 30 80 84 10 70 00 01 04 1C 20 10 49 40 08 20 A1 + 04 9C 00 00 41 07 4C 00 10 10 82 48 2A 61 03 08 + 00 12 40 C2 01 04 9B B6 3F FF FF E5 7F FB 1F FF + FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF + 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF + 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F + FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF + FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF + FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB + 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC + AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF + FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F + FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF + FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF + B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF + CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F + FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 + FF B1 FF FF FF 2B FF B6 76 00 00 7E C4 0D 9D 80 + 00 04 7C EC 00 00 BA 00 00 00 8B C5 E2 F1 78 78 + 78 78 72 1E 1E 1E 1E 1E 1E 3F 8F C2 1E 1E 1E 1E + 1E 1E 1E 1E 1E 1E 2F 17 8B 90 F0 F0 F0 F1 78 BC + 5E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1C 8B 80 0F 74 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 04 04 10 04 01 00 40 10 + 04 01 00 40 10 04 01 00 40 10 04 01 00 40 10 04 + 03 00 0C 00 30 00 C0 03 00 0C 00 30 00 C0 02 00 + 20 02 00 20 02 00 20 02 00 20 02 00 10 04 03 00 + 0C 00 30 00 C0 02 00 20 02 00 20 02 00 20 02 00 + 20 02 00 20 02 00 20 01 00 40 10 04 00 02 00 20 + 02 00 20 02 00 20 01 00 40 10 04 00 3E 08 02 40 + 07 CC AF 34 08 02 96 3F FF FF FF FF FF FC D2 97 + 78 A0 1F 00 08 40 13 0C 00 00 00 00 00 0A A1 34 + 91 02 02 00 05 E4 84 12 E2 80 02 6B C0 C0 04 00 + 01 04 10 40 00 28 C8 00 00 08 80 00 05 58 E1 00 + 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 0E 22 + 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 10 00 + A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 42 54 + 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 1A 02 + 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 00 02 + 0C 30 00 1A 55 30 62 00 11 C0 48 16 0C 01 C4 D0 + 00 00 00 40 04 03 40 4D 01 04 40 41 4E 9C 00 02 + 00 01 00 80 80 10 02 00 + + + + + + + + +[SCTP] Successfully sent 2161 bytes on stream 0 for assoc_id 904 +[SCTP] Found data for descriptor 95 +[SCTP] Received notification for sd 95, type 32777 +[SCTP] Found data for descriptor 95 +[SCTP] [904][95] Msg of length 371 received from port 36422, on stream 0, PPID 27 + + + 27 + + + + + + 111 + + + 0 + + + + 207 + + + 0 + + + + 210 + + + + + 213 + + + + 5 + + + + + + + + + + 11000000101010000001001011000110 + + 92 CC 30 02 + + + + + + + + + + + 211 + + + + 18 04 09 A8 44 09 92 E2 07 8E 01 90 43 7E 30 D0 + 41 E6 41 C8 54 1E 21 00 83 2B A1 6E 63 00 1A 4E + 47 C0 13 49 C4 00 00 00 26 96 18 DE 35 00 05 38 + 05 10 0D 60 1B 40 39 D2 02 68 00 01 34 E4 E1 8D + E3 2A 31 00 0D 66 66 BE E4 E0 24 BC A1 5B C2 C5 + 8F 68 9C 2E 00 50 E0 18 04 21 60 3B 00 91 19 1F + 5E 24 62 00 1A CC CD 00 03 F0 DB 00 10 1C 02 D9 + 00 92 00 20 24 04 63 2C E1 96 65 14 0F FF F8 00 + 00 00 08 70 00 41 03 08 14 30 73 70 44 30 00 00 + 80 80 1A 70 0A 20 1A C0 36 80 72 CA 80 40 FF FF + 80 00 00 00 87 00 04 10 30 81 43 07 0D C2 10 C0 + 00 08 05 90 01 01 20 23 25 61 52 C0 E1 04 16 0E + 0C 10 E1 00 71 28 1C 00 00 20 5E F4 01 00 02 00 + 00 0F 40 01 41 00 19 73 86 59 95 18 80 06 B3 33 + 5F 72 70 12 5E 50 AD E1 62 C7 B4 4E 17 00 28 70 + 6A A4 1A 80 81 04 42 0C 20 30 08 C0 03 40 43 00 + 0C 01 8A 17 B4 08 28 5E C9 07 91 A2 B3 80 00 40 + 00 7F 42 10 84 00 80 40 25 81 C2 08 2C 1C 18 21 + C2 00 E2 50 38 00 00 40 BD E8 02 00 04 00 00 1E + 80 02 82 00 70 01 01 88 00 40 A0 49 40 BC 16 00 + 60 00 + + + + + + + + +[X2AP] x2ap_eNB_decode_successfuloutcome_message! +[X2AP] X2AP Association id: 904 +322: 180409a8440992e2078e0190437e30d041e641c8541e2100832ba16e63001a4e47c01349c4000000269618de3500053805100d601b4039d20268000134e4e18de32a31000d6666bee4e024bca15bc2c58f689c2e0050e0180421603b0091191f5e2462001acccd0003f0db00101c02d9009200202404632ce19665140ffff8000000087000410308143073704430000080801a700a201ac0368072ca8040ffff8000000087000410308143070dc210c00008059001012023256152c0e104160e0c10e10071281c0000205ef401000200000f400141001973865995188006b3335f7270125e50ade162c7b44e170028706aa41a808104420c203008c0034043000c018a17b408285ec90791a2b3800040007f4210840080402581c2082c1c1821c200e25038000040bde802000400001e80028200700101880040a04940bc16006000 + + + + + + 08 81 32 5C 40 F1 C0 32 08 6F C6 1A 08 3C C8 39 + 0A 83 C4 20 10 65 74 2D CC 60 03 49 C8 F8 02 69 + 38 80 00 00 04 D2 C3 1B C6 A0 00 A7 00 A2 01 AC + 03 68 07 3A 40 4D 00 00 26 9C 9C 31 BC 65 46 20 + 01 AC CC D7 DC 9C 04 97 94 2B 78 58 B1 ED 13 85 + C0 0A 1C 03 00 84 2C 07 60 12 23 23 EB C4 8C 40 + 03 59 99 A0 00 7E 1B 60 02 03 80 5B 20 12 40 04 + 04 80 8C 65 9C 32 CC A2 81 FF FF 00 00 00 01 0E + 00 08 20 61 02 86 0E 6E 08 86 00 00 10 10 03 4E + 01 44 03 58 06 D0 0E 59 50 08 1F FF F0 00 00 00 + 10 E0 00 82 06 10 28 60 E1 B8 42 18 00 01 00 B2 + 00 20 24 04 64 AC 2A 58 1C 20 82 C1 C1 82 1C 20 + 0E 25 03 80 00 04 0B DE 80 20 00 40 00 01 E8 00 + 28 20 03 2E 70 CB 32 A3 10 00 D6 66 6B EE 4E 02 + 4B CA 15 BC 2C 58 F6 89 C2 E0 05 0E 0D 54 83 50 + 10 20 88 41 84 06 01 18 00 68 08 60 01 80 31 42 + F6 81 05 0B D9 20 F2 34 56 70 00 08 00 0F E8 42 + 10 80 10 08 04 B0 38 41 05 83 83 04 38 40 1C 4A + 07 00 00 08 17 BD 00 40 00 80 00 03 D0 00 50 40 + 0E 00 20 31 00 + + 14 09 28 17 82 C0 0C 00 + + + + +[RRC] Dumping scg_CellGroupConfig: 3090881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100 +[RRC] Dumping scg_RB_Config: 81409281782c00c00 +[RRC] Dumping nr_SecondaryCellGroupConfig: 3090881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100 +[RRC] Dumping nr_RadioBearerConfig1: 81409281782c00c00 +len = 336 + 22 02 8c 00 23 08 10 00 ac 24 a0 82 1e 32 04 d4 22 04 c9 71 03 c7 00 c8 21 bf 18 68 20 f3 20 e4 2a 0f 10 80 41 95 d0 b7 31 80 0d 27 23 e0 09 a4 e2 00 00 00 13 4b 0c 6f 1a 80 02 9c 02 88 06 b0 0d a0 1c e9 01 34 00 00 9a 72 70 c6 f1 95 18 80 06 b3 33 5f 72 70 12 5e 50 ad e1 62 c7 b4 4e 17 00 28 70 0c 02 10 b0 1d 80 48 8c 8f af 12 31 00 0d 66 66 80 01 f8 6d 80 08 0e 01 6c 80 49 00 10 12 02 31 96 70 cb 32 8a 07 ff fc 00 00 00 04 38 00 20 81 84 0a 18 39 b8 22 18 00 00 40 40 0d 38 05 10 0d 60 1b 40 39 65 40 20 7f ff c0 00 00 00 43 80 02 08 18 40 a1 83 86 e1 08 60 00 04 02 c8 00 80 90 11 92 b0 a9 60 70 82 0b 07 06 08 70 80 38 94 0e 00 00 10 2f 7a 00 80 01 00 00 07 a0 00 a0 80 0c b9 c3 2c ca 8c 40 03 59 99 af b9 38 09 2f 28 56 f0 b1 63 da 27 0b 80 14 38 35 52 0d 40 40 82 21 06 10 18 04 60 01 a0 21 80 06 00 c5 0b da 04 14 2f 64 83 c8 d1 59 c0 00 20 00 3f a1 08 42 00 40 20 12 c0 e1 04 16 0e 0c 10 e1 00 71 28 1c 00 00 20 5e f4 01 00 02 00 00 0f 40 01 41 00 38 00 80 c4 00 00 00 20 50 24 a0 5e 0b 00 30 00 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 1) +[RRC] E-RAB modification indication: nb nb_of_e_rabs 1 status 4 +[RRC] S1AP_E_RAB_MODIFICATION_IND: sending the message: nb_of_erabstobemodified 1, total e_rabs 1, index 1 + + + 50 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 199 + + + + + 200 + + + + 5 + + 11000000101010000001001011000110 + + 92 CC 30 02 + + + + + + + + + + + +[S1AP] Size of encoded message: 43 +[S1AP] initial context setup response: failed e_rab ID 5 +[SCTP] Successfully sent 43 bytes on stream 1 for assoc_id 903 +[SCTP] Sctp_sendmsg failed: Message too long +[GTPV1U] NW_GTP_END_MARKER +[PDCP] Handed SDU is of size 0! Ignoring... +[GTPV1U] PDCP data request failed, cause: [UE:43eb]RB is not configured! +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 34 received from port 36412, on stream 1, PPID 18 +[S1AP] Implementation of S1AP E-RAB Modification confirm handler is pending... +[MAC] [eNB 0][PUSCH 1] CC_id 0 874.5 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 15 PUCCH SNR 16 +[RRC] UE rnti 43eb failure timer 0/8 +[PHY] prach_I0 = 0.0 dB +[PHY] max_I0 19, min_I0 12 +[MAC] [eNB 0][PUSCH 4] CC_id 0 73.2 ULSCH in error in round 0, ul_cqi 159, UE_id 0, RNTI 43eb (len 63) +[X2AP] X2 has 1 process ongoing +[MAC] [eNB 0][PUSCH 7] CC_id 0 114.3 ULSCH in error in round 0, ul_cqi 165, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 10 +[X2AP] X2 has 1 process ongoing +[MAC] [eNB 0][PUSCH 0] CC_id 0 218.4 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 226.2 ULSCH in error in round 0, ul_cqi 164, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 13 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 19 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 13 +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[MAC] [eNB 0][PUSCH 2] CC_id 0 753.0 ULSCH in error in round 0, ul_cqi 164, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 15 PUCCH SNR 16 + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 27 D6 DB 4F 5E 03 07 45 0B 0B F6 22 F2 10 80 00 + 01 00 00 00 37 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 72 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 25 received from port 36412, on stream 1, PPID 18 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate RRCConnectionRelease (bytes 3) +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[MAC] [eNB 0][PUSCH 3] CC_id 0 927.5 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 928.3 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 929.1 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 929.9 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 930.7 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 931.5 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 932.3 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 933.1 ULSCH in error in round 3, ul_cqi 128, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 933.9 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 934.7 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 935.5 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 936.3 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 936.8 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 937.6 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 938.4 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 939.2 ULSCH in error in round 3, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 940.0 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 940.8 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 941.6 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 942.4 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 943.2 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 944.0 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 944.8 ULSCH in error in round 2, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 945.6 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 946.4 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 947.2 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 948.0 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 948.8 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 949.6 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 950.4 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 951.2 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 952.0 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 952.8 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 953.6 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 954.4 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 955.2 ULSCH in error in round 3, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 956.0 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 956.8 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 957.6 ULSCH in error in round 2, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 958.4 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 959.2 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 960.0 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 960.8 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 961.6 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] UE 0 rnti 43eb: UL Failure timer 1 +[RRC] S1AP removed entry in hashtable s1ap_id2_s1ap_ids for eNB_ue_s1ap_id 420141 +[RRC] S1AP removed entry in hashtable initial_id2_s1ap_ids for ue_initial_id 1 +[S1AP] Removed UE context eNB_ue_s1ap_id 420141 +[SCTP] Successfully sent 24 bytes on stream 1 for assoc_id 903 +[RRC] Removing UE 43eb instance after UE_CONTEXT_RELEASE_Complete (ue_release_timer_rrc timeout) +[RRC] [eNB 0] Removing UE RNTI 43eb +[RRC] Put UE 43eb into freeList +[RRC] clean_eNb_dlsch dlsch[2] UE 43eb +[MAC] clean eNb uci_vars[0] UE 43eb +[MAC] clean eNb uci_vars[1] UE 43eb +[MAC] clean eNb uci_vars[2] UE 43eb +[MAC] clean eNb uci_vars[3] UE 43eb +[RRC] remove UE 43eb from ul_config_pdu_list 0/1 +[MAC] Removing UE 0 from Primary CC_id 0 (rnti 43eb) +[PDCP] remove uid is 0/0 43eb +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Removed UE context +[RRC] [release_UE_in_freeList] remove UE 43eb from freeList +[X2AP] X2 has 1 process ongoing +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[PHY] prach_I0 = 0.0 dB +[PHY] max_I0 18, min_I0 12 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing + \ No newline at end of file diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg new file mode 100755 index 0000000000000000000000000000000000000000..fccbd9a8a325b26a69a5be87d22852b0b840aad9 GIT binary patch literal 93188 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function config_libconfig_init returned 0 +[CONFIG] config module libconfig loaded +[LIBCONFIG] config: 1/1 parameters successfully set, (1 to default value) +Send signal 35 to display resource usage... +[LIBCONFIG] log_config: 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (46 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (52 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +log init done +[HW] # /dev/cpu_dma_latency set to 10 us +[HW] Can't set cpu frequency +Reading in command-line options +[GNB_APP] Getting GNBSParams +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[CONFIG] parallel_conf is set to 0 +[CONFIG] worker_conf is set to 1 +Configuration: nb_rrc_inst 1, nb_nr_L1_inst 1, nb_ru 1 +[LIBCONFIG] (root): 23/23 parameters successfully set, (19 to default value) +[LIBCONFIG] (root): 5/5 parameters successfully set, (4 to default value) +[LIBCONFIG] TTracer: 4/4 parameters successfully set, (4 to default value) +configuring for RAU/RRU +CPU Freq is 3.092986 +[TMR] Starting itti queue: TASK_UNKNOWN as task 0 +[TMR] Starting itti queue: TASK_TIMER as task 1 +[TMR] Starting itti queue: TASK_L2L1 as task 2 +[TMR] Starting itti queue: TASK_BM as task 3 +[TMR] Starting itti queue: TASK_PHY_ENB as task 4 +[TMR] Starting itti queue: TASK_MAC_ENB as task 5 +[TMR] Starting itti queue: TASK_RLC_ENB as task 6 +[TMR] Starting itti queue: TASK_RRC_ENB_NB_IoT as task 7 +[TMR] Starting itti queue: TASK_PDCP_ENB as task 8 +[TMR] Starting itti queue: TASK_DATA_FORWARDING as task 9 +[TMR] Starting itti queue: TASK_END_MARKER as task 10 +[TMR] Starting itti queue: TASK_RRC_ENB as task 11 +[TMR] Starting itti queue: TASK_RRC_GNB as task 12 +[TMR] Starting itti queue: TASK_RAL_ENB as task 13 +[TMR] Starting itti queue: TASK_S1AP as task 14 +[TMR] Starting itti queue: TASK_X2AP as task 15 +[TMR] Starting itti queue: TASK_M2AP_ENB as task 16 +[TMR] Starting itti queue: TASK_M2AP_MCE as task 17 +[TMR] Starting itti queue: TASK_M3AP as task 18 +[TMR] Starting itti queue: TASK_M3AP_MME as task 19 +[TMR] Starting itti queue: TASK_M3AP_MCE as task 20 +[TMR] Starting itti queue: TASK_SCTP as task 21 +[TMR] Starting itti queue: TASK_ENB_APP as task 22 +[TMR] Starting itti queue: TASK_GNB_APP as task 23 +[TMR] Starting itti queue: TASK_MCE_APP as task 24 +[TMR] Starting itti queue: TASK_MME_APP as task 25 +[TMR] Starting itti queue: TASK_FLEXRAN_AGENT as task 26 +[TMR] Starting itti queue: TASK_PHY_UE as task 27 +[TMR] Starting itti queue: TASK_MAC_UE as task 28 +[TMR] Starting itti queue: TASK_RLC_UE as task 29 +[TMR] Starting itti queue: TASK_PDCP_UE as task 30 +[TMR] Starting itti queue: TASK_RRC_UE as task 31 +[TMR] Starting itti queue: TASK_NAS_UE as task 32 +[TMR] Starting itti queue: TASK_RAL_UE as task 33 +[TMR] Starting itti queue: TASK_MSC as task 34 +[TMR] Starting itti queue: TASK_GTPV1_U as task 35 +[TMR] Starting itti queue: TASK_UDP as task 36 +[TMR] Starting itti queue: TASK_CU_F1 as task 37 +[TMR] Starting itti queue: TASK_DU_F1 as task 38 +[LIBCONFIG] opt: 3/3 parameters successfully set, (3 to default value) +[OPT] OPT disabled +[NETLINK] Error opening socket -1 (93:Protocol not supported) +[NETLINK] Opened socket with fd -1 +[NETLINK] Error fcntl (9:Bad file descriptor) +[HW] Version: Branch: NR_RRC_harq_hacks Abrev. Hash: 94fa9c5 Date: Fri Jun 19 18:16:53 2020 +0200 +Wait for the ITTI initialize message +[TMR] Created Posix thread TASK_L2L1 +[SCTP] Starting SCTP layer +[TMR] Created Posix thread TASK_SCTP +[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] gNBs.[0]: 1/1 parameters successfully set, (0 to default value) +[TMR] Created Posix thread TASK_X2AP +[UDP] Initializing UDP task interface +[UDP] Initializing UDP task interface: DONE +[TMR] Created Posix thread TASK_UDP +[TMR] Created Posix thread TASK_GTPV1_U +[GTPV1U] Initializing GTPU stack 0x17ce250 +[PHY] gNB_app_task() Task ready initialize structures +[TMR] Created Posix thread TASK_GNB_APP +[NR_RRC] Creating NR RRC gNB Task +[NR_PHY] RC.gNB = 0x7f518c0008c0 +[LIBCONFIG] L1s.[0]: 24/24 parameters successfully set, (22 to default value) +[NR_PHY] RC.gNB[0] = 0x7f51a2f08010 +[NR_RRC] Entering main loop of NR_RRC message task +[TMR] Created Posix thread TASK_RRC_GNB +Initializing northbound interface for L1 +[PHY] l1_north_init_gNB() RC.nb_nr_L1_inst:1 +[PHY] Installing callbacks for IF_Module - UL_indication +[MAC] Allocating shared L1/L2 interface structure for instance 0 @ 0x7f518c001970 +[PHY] l1_north_init_gNB() RC.gNB[0] installing callbacks +[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (17 to default value) +[MAC] [MAIN] Init function start:nb_nr_macrlc_inst=1 +NFAPI MODE:MONOLITHIC +START MAIN THREADS +RC.nb_nr_L1_inst:1 +Initializing gNB threads single_thread_flag:1 wait_for_sync:0 +[PHY] gNB L1 structure RC.gNB allocated @ 0x7f518c0008c0 +[PHY] [lte-softmodem.c] gNB structure RC.gNB[0] allocated @ 0x7f51a2f08010 +[PHY] Initializing gNB 0 single_thread_flag:1 +[PHY] Initializing gNB 0 +[PHY] Registering with MAC interface module (before 0x7f518c001970) +[PHY] Installing callbacks for IF_Module - UL_indication +[PHY] Registering with MAC interface module (after 0x7f518c001970) +[PHY] Setting indication lists +[PHY] [nr-softmodem.c] gNB structure allocated +wait_gNBs() +Waiting for gNB L1 instances to all get configured ... sleeping 50ms (nb_nr_sL1_inst 1) +[PDCP] PDCP layer has been initialized +[PHY] Installing callbacks for IF_Module - UL_indication +[PHY] gNB_app_task() RC.nb_nr_L1_inst:1 +[PHY] l1_north_init_gNB() RC.nb_nr_L1_inst:1 +[PHY] Installing callbacks for IF_Module - UL_indication +[PHY] l1_north_init_gNB() RC.gNB[0] installing callbacks +[GNB_APP] Allocating gNB_RRC_INST for 1 instances +[PHY] gNB_app_task() RC.nb_nr_inst:1 RC.nrrrc:0x7f518c002860 +[PHY] gNB_app_task() Creating RRC instance RC.nrrrc[0]:0x7f518c002ad0 (1 of 1) +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0]: 14/14 parameters successfully set, (8 to default value) +[LIBCONFIG] gNBs.[0].servingCellConfigCommon.[0]: 155/155 parameters successfully set, (83 to default value) +[RRC] Read in ServingCellConfigCommon (PhysCellId 0, ABSFREQSSB 641272, DLBand 78, ABSFREQPOINTA 640000, DLBW 106,RACH_TargetReceivedPower -100 +Checking element 15 : 4294967295 +removing pdsch_TimeDomainAllocationList element 15 +List size now 15 +Checking element 14 : 4294967295 +removing pdsch_TimeDomainAllocationList element 14 +List size now 14 +Checking element 13 : 4294967295 +removing pdsch_TimeDomainAllocationList element 13 +List size now 13 +Checking element 12 : 4294967295 +removing pdsch_TimeDomainAllocationList element 12 +List size now 12 +Checking element 11 : 4294967295 +removing pdsch_TimeDomainAllocationList element 11 +List size now 11 +Checking element 10 : 4294967295 +removing pdsch_TimeDomainAllocationList element 10 +List size now 10 +Checking element 9 : 4294967295 +removing pdsch_TimeDomainAllocationList element 9 +List size now 9 +Checking element 8 : 4294967295 +removing pdsch_TimeDomainAllocationList element 8 +List size now 8 +Checking element 7 : 4294967295 +removing pdsch_TimeDomainAllocationList element 7 +List size now 7 +Checking element 6 : 4294967295 +removing pdsch_TimeDomainAllocationList element 6 +List size now 6 +Checking element 5 : 4294967295 +removing pdsch_TimeDomainAllocationList element 5 +List size now 5 +Checking element 4 : 4294967295 +removing pdsch_TimeDomainAllocationList element 4 +List size now 4 +Checking element 3 : 0 +Checking element 2 : 0 +Checking element 1 : 0 +Checking element 0 : 0 +NRRRC 0: Southbound Transport local_mac +[LIBCONFIG] gNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +SSB SCO 31 +pdsch_AntennaPorts 1 +[GNB_APP] Sending configuration message to NR_RRC task +[X2AP] X2AP enabled +[X2AP] GNB_ID: 0 +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[NR_RRC] Received message NRRRC_CONFIGURATION_REQ +[NR_RRC] [gNB 0] Received NRRRC_CONFIGURATION_REQ : 0x7f518c00407c +[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Init... +[LIBCONFIG] gNBs.[0]: 14/14 parameters successfully set, (8 to default value) +[LIBCONFIG] gNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0].target_enb_x2_ip_address.[0]: 3/3 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0]: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value) +[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Checking release +[LIBCONFIG] gNBs.[0].NETWORK_INTERFACES: 7/7 parameters successfully set, (0 to default value) +[GTPV1U] Configuring GTPu +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[NR_RRC] Done init_NR_SI +[LIBCONFIG] gNBs.[0].NETWORK_INTERFACES: 3/3 parameters successfully set, (0 to default value) +[MAC] Configuring common parameters from NR ServingCellConfig +[PHY] config_common() dl_BandwidthP:40 +[GTPV1U] Configuring GTPu address : 192.168.18.198 -> c612a8c0 +[PHY] Computing dl_frequency (pointA 640000 => 3600000000 (dlmin 3300000, nr_bandtable[27].N_OFFs_DL 620000)) +[PHY] config_common() dl_BandwidthP:40 +[GNB_APP] [gNB 0] gNB_app_register for instance 0 +[GTPV1U] Tx UDP_INIT IP addr 192.168.18.198 (868) +[PHY] Computing dl_frequency (pointA 640000 => 3600000000 (dlmin 3300000, nr_bandtable[27].N_OFFs_DL 620000)) +[PHY] Scanning band 1, dl_min 2110000, ul_min 1920000 +[PHY] Scanning band 2, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 3, dl_min 1805000, ul_min 1710000 +[PHY] Scanning band 5, dl_min 869000, ul_min 824000 +[PHY] Scanning band 7, dl_min 2620000, ul_min 2500000 +[UDP] Initializing UDP for local address 192.168.18.198 with port 2152 +[PHY] Scanning band 8, dl_min 925000, ul_min 880000 +[PHY] Scanning band 12, dl_min 728000, ul_min 698000 +[PHY] Scanning band 20, dl_min 791000, ul_min 832000 +[PHY] Scanning band 25, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 28, dl_min 758000, ul_min 703000 +[PHY] Scanning band 34, dl_min 2010000, ul_min 2010000 +[PHY] Scanning band 38, dl_min 2570000, ul_min 2570000 +[PHY] Scanning band 39, dl_min 1880000, ul_min 1880000 +[PHY] Scanning band 40, dl_min 2300000, ul_min 2300000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 50, dl_min 1432000, ul_min 1432000 +[PHY] Scanning band 51, dl_min 1427000, ul_min 1427000 +[PHY] Scanning band 66, dl_min 2110000, ul_min 1710000 +[PHY] Scanning band 70, dl_min 1995000, ul_min 1695000 +[PHY] Scanning band 71, dl_min 617000, ul_min 663000 +[PHY] Scanning band 74, dl_min 1475000, ul_min 1427000 +[PHY] Scanning band 75, dl_min 1432000, ul_min 0 +[PHY] Scanning band 76, dl_min 1427000, ul_min 0 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 80, dl_min 0, ul_min 1710000 +[PHY] Scanning band 81, dl_min 0, ul_min 860000 +[PHY] Scanning band 82, dl_min 0, ul_min 832000 +[PHY] Scanning band 83, dl_min 0, ul_min 703000 +[PHY] Scanning band 84, dl_min 0, ul_min 1920000 +[PHY] Scanning band 86, dl_min 0, ul_min 1710000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] DL frequency 3600000000: band 78, frame_type 1, UL frequency 3600000000 + found_sequences 16 +[MAC] Set TX/RX antenna number to 1 (num ssb 1: 80000000,0) +[MAC] Setting TDD configuration period to 6 +[PHY] TDD has been properly configurated +[MAC] rrc_mac_config_req_gNB() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/NR_MAC_gNB/config.c:345 RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req:0x60f680 +[PHY] Scanning band 1, dl_min 2110000, ul_min 1920000 +[PHY] Scanning band 2, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 3, dl_min 1805000, ul_min 1710000 +[PHY] Scanning band 5, dl_min 869000, ul_min 824000 +[PHY] Scanning band 7, dl_min 2620000, ul_min 2500000 +[PHY] Scanning band 8, dl_min 925000, ul_min 880000 +[PHY] Scanning band 12, dl_min 728000, ul_min 698000 +[PHY] Scanning band 20, dl_min 791000, ul_min 832000 +[PHY] Scanning band 25, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 28, dl_min 758000, ul_min 703000 +[PHY] Scanning band 34, dl_min 2010000, ul_min 2010000 +[PHY] Scanning band 38, dl_min 2570000, ul_min 2570000 +[PHY] Scanning band 39, dl_min 1880000, ul_min 1880000 +[PHY] Scanning band 40, dl_min 2300000, ul_min 2300000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 50, dl_min 1432000, ul_min 1432000 +[PHY] Scanning band 51, dl_min 1427000, ul_min 1427000 +[PHY] Scanning band 66, dl_min 2110000, ul_min 1710000 +[PHY] Scanning band 70, dl_min 1995000, ul_min 1695000 +[PHY] Scanning band 71, dl_min 617000, ul_min 663000 +[PHY] Scanning band 74, dl_min 1475000, ul_min 1427000 +[PHY] Scanning band 75, dl_min 1432000, ul_min 0 +[PHY] Scanning band 76, dl_min 1427000, ul_min 0 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 80, dl_min 0, ul_min 1710000 +[PHY] Scanning band 81, dl_min 0, ul_min 860000 +[PHY] Scanning band 82, dl_min 0, ul_min 832000 +[PHY] Scanning band 83, dl_min 0, ul_min 703000 +[PHY] Scanning band 84, dl_min 0, ul_min 1920000 +[PHY] Scanning band 86, dl_min 0, ul_min 1710000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] DL frequency 3619080000: band 78, frame_type 1, UL frequency 3619080000 +[PHY] Configuring MIB for instance 0, : (Nid_cell 0,DL freq 3619080000, UL freq 3619080000) +[PHY] Initializing frame parms for mu 1, N_RB 106, Ncp 0 +[X2AP] Registered new eNB[0] and home eNB id 3584 +[X2AP] eNB[0] eNB id 3584 acting as a listner (server) +[SCTP] Received SCTP_INIT_MSG_MULTI_REQ +[UDP] Inserting new descriptor for task 35, sd 85 +[UDP] Initializing UDP for local address 192.168.18.198 with port 2152: DONE +[PHY] gNB 0 configured +[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] gNB:OPENAIR NR RRC IN.... +[SCTP] Creating new listen socket on port 36422 with +[SCTP] ipv4 addresses: +[SCTP] - 192.168.18.198 +[X2AP] eNB[0] eNB id 3584 acting as an initiator (client) +[SCTP] Converted ipv4 address 192.168.18.199 to network type +[SCTP] sctp_connectx SUCCESS, used 1 addresses assoc_id 136 +[SCTP] Inserted new descriptor for sd 87 in list, nb elements 2, assoc_id 136 +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32769 +[SCTP] Client association changed: 0 +[SCTP] ---------------------- +[SCTP] Peer addresses: +[SCTP] - [192.168.18.199] +[SCTP] ---------------------- +[SCTP] ---------------------- +[SCTP] SCTP Status: +[SCTP] assoc id .....: 136 +[SCTP] state ........: 4 +[SCTP] instrms ......: 32 +[SCTP] outstrms .....: 32 +[SCTP] fragmentation : 1452 +[SCTP] pending data .: 0 +[SCTP] unack data ...: 0 +[SCTP] rwnd .........: 106496 +[SCTP] peer info : +[SCTP] state ....: 2 +[SCTP] cwnd .....: 4380 +[SCTP] srtt .....: 0 +[SCTP] rto ......: 3000 +[SCTP] mtu ......: 1500 +[SCTP] ---------------------- +[SCTP] Comm up notified for sd 87, assigned assoc_id 136 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id -1 +--------------------------------------------- +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id -1 +--------------------------------------------- +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id -1 +--------------------------------------------- +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 32 out_streams 32 +cnx_id 1 assoc_id 136 +--------------------------------------------- +[X2AP] 3584 -> 00000e +[X2AP] TAC: 25744 -> 006490 + + + 36 + + + + + + 244 + + + + + + 252 + + + + 22 F2 10 + + + 00000000000000000000111000000000 + + + + + + + 253 + + + + + + 0 + + 22 F2 10 + + 000000000000000000000000111000000000 + + + 00 64 90 + + 22 F2 10 + + + + + 0 + + + 1 + + + 80 + + + + + + + + + + + + 00 + + + + + + + + + + + + + + +[SCTP] Successfully sent 66 bytes on stream 0 for assoc_id 136 +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32777 +[SCTP] Found data for descriptor 87 +[SCTP] [136][87] Msg of length 53 received from port 36422, on stream 0, PPID 27 + + + 36 + + + + + + 246 + + + + + + 21 + + + + 22 F2 10 + + + 00000000111000000001 + + + + + + + 250 + + + + + + 0 + + 22 F2 10 + + 0000000011100000000100000000 + + + 00 01 + + 22 F2 10 + + + + 21350 + 3350 + + + + + + + + + + + + + + + + + + +[X2AP] x2ap_eNB_decode_successfuloutcome_message! +gNB L1 are configured +About to Init RU threads RC.nb_RU:1 +Initializing RU threads +configuring RU from file +[LIBCONFIG] RUs.[0]: 27/27 parameters successfully set, (17 to default value) +Set RU mask to 1 +Creating RC.ru[0]:0x3ae67d0 +Setting function for RU 0 to gNodeB_3GPP +[PHY] number of L1 instances 1, number of RU 1, number of CPU cores 10 +[PHY] DJP - delete code above this /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-ru.c:2251 +[PHY] Copying frame parms from gNB in RC to gNB 0 in ru 0 and frame_parms in ru +configuring ru_id 0 (start_rf 0x5b7120) +[PHY] Starting ru_thread 0 +[PHY] Initializing RU proc 0 (,synch_to_ext_device), +[PHY] Starting RU 0 (,synch_to_ext_device), +[PHY] Initializing frame parms for mu 1, N_RB 106, Ncp 0 +[PHY] fp->scs=30000 +[PHY] fp->ofdm_symbol_size=1536 +[PHY] fp->nb_prefix_samples0=132 +[PHY] fp->nb_prefix_samples=108 +[PHY] fp->slots_per_subframe=2 +[PHY] fp->samples_per_subframe_wCP=43008 +[PHY] init_RU_proc() DJP - added creation of pthread_prach +[PHY] fp->samples_per_frame_wCP=430080 +[PHY] fp->samples_per_subframe=46080 +[PHY] fp->samples_per_frame=460800 +[PHY] fp->dl_CarrierFreq=3619080000 +[PHY] fp->ul_CarrierFreq=3619080000 +channel 0, Setting tx_gain offset 0.000000, rx_gain offset 114.000000, tx_freq 3619080000.000000, rx_freq 3619080000.000000 +[PHY] Initializing RU signal buffers (if_south local RF) nb_tx 1 +[PHY] [INIT] common.txdata[0] = 0x7f5198339040 (1843200 bytes) +[PHY] nb_tx 1 +[PHY] rxdata_7_5kHz[0] 0x7f51980c1040 for RU 0 +[PHY] init feptx thread 0 +[PHY] [INIT] common.txdata_BF= 0x7f517c000aa0 (8 bytes) +[PHY] txdataF_BF[0] 0x7f51a2e9c040 for RU 0 +[PHY] init feptx thread 1 +wait RUs +[PHY] Waiting for RUs to be configured ... RC.ru_mask:01 +[PHY] rxdataF[0] 0x7f51a2e47040 for RU 0 +[PHY] [INIT] nr_phy_init_RU() RC.nb_nr_L1_inst:1 +[LIBCONFIG] device.recplay: 7/7 parameters successfully set, (7 to default value) +[LIBCONFIG] device: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] loader: 2/2 parameters successfully set, (2 to default value) +[LIBCONFIG] loader.oai_device: 2/2 parameters successfully set, (1 to default value) +[LOADER] library liboai_device.so successfully loaded +[HW] UHD version 3.15.0.0-0-gaea0e2de (3.15.0) +[HW] Found USRP b200 +Found USRP b200 +[PHY] ru_thread_prach() RACH waiting for RU to be configured +[HW] Time source set neither in usrp_args nor on command line, using default! +[HW] cal 0: freq 3500000000.000000, offset 44.000000, diff 119080000.000000 +[HW] cal 1: freq 2660000000.000000, offset 49.800000, diff 959080000.000000 +[HW] cal 2: freq 2300000000.000000, offset 51.000000, diff 1319080000.000000 +[HW] cal 3: freq 1880000000.000000, offset 53.000000, diff 1739080000.000000 +[HW] cal 4: freq 816000000.000000, offset 57.000000, diff 2803080000.000000 +[HW] RX Gain 0 114.000000 (44.000000) => 70.000000 (max 76.000000) +[HW] USRP TX_GAIN:89.75 gain_range:89.75 tx_gain:0.00 +[HW] Actual master clock: 46.080000MHz... +[HW] Actual clock source internal... +[HW] Actual time source internal... +[PHY] ru_thread_prach() RACH waiting for RU to be configured +[HW] RF board max packet size 1916, size for 100µs jitter 4608 +[HW] rx_max_num_samps 1916 +[HW] RX Channel 0 +[HW] Actual RX sample rate: 46.080000MSps... +[HW] Actual RX frequency: 3.619080GHz... +[HW] Actual RX gain: 70.000000... +[HW] Actual RX bandwidth: 40.000000M... +[HW] Actual RX antenna: RX2... +[HW] TX Channel 0 +[HW] Actual TX sample rate: 46.080000MSps... +[HW] Actual TX frequency: 3.619080GHz... +[HW] Actual TX gain: 89.750000... +[HW] Actual TX bandwidth: 40.000000M... +[HW] Actual TX antenna: TX/RX... +[HW] Actual TX packet size: 1916 +[HW] Device timestamp: 2.171687... +[HW] [RAU] has loaded USRP B200 device. +setup_RU_buffers: frame_parms = 0x7f51a2ec7010 +[PHY] RU 0 Setting N_TA_offset to 600 samples (factor 1.500000, UL Freq 3600000, N_RB 106) +[PHY] Signaling main thread that RU 0 is ready +waiting for sync (ru_thread,-1/0xf53a58,0x18e6f00,0x17ccc40) +RC.ru_mask:00 +[PHY] RUs configured +ALL RUs READY! +RC.nb_RU:1 +ALL RUs ready - init gNBs +Not NFAPI mode - call init_eNB_afterRU() +[PHY] init_eNB_afterRU() RC.nb_nr_inst:1 +[PHY] RC.nb_nr_CC[inst:0]:0x7f51a2f08010 +[PHY] [gNB 0] phy_init_nr_gNB() About to wait for gNB to be configured +[LIBCONFIG] loader.dfts: 2/2 parameters successfully set, (1 to default value) +[LOADER] library libdfts.so successfully loaded +init_scrambling_luts: s 0 (1) ((1,1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 1 (-1) ((-1,1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 2 (1) ((1,-1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 3 (-1) ((-1,-1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 4 (1) ((1,1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 5 (-1) ((-1,1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 6 (1) ((1,-1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 7 (-1) ((-1,-1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 8 (1) ((1,1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s 9 (-1) ((-1,1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s a (1) ((1,-1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s b (-1) ((-1,-1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s c (1) ((1,1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s d (-1) ((-1,1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s e (1) ((1,-1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s f (-1) ((-1,-1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s 10 (1) ((1,1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 11 (-1) ((-1,1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 12 (1) ((1,-1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 13 (-1) ((-1,-1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 14 (1) ((1,1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 15 (-1) ((-1,1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 16 (1) ((1,-1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 17 (-1) ((-1,-1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 18 (1) ((1,1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 19 (-1) ((-1,1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1a (1) ((1,-1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1b (-1) ((-1,-1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1c (1) ((1,1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1d (-1) ((-1,1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1e (1) ((1,-1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1f (-1) ((-1,-1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 20 (1) ((1,1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 21 (-1) ((-1,1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 22 (1) ((1,-1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 23 (-1) ((-1,-1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 24 (1) ((1,1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 25 (-1) ((-1,1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 26 (1) ((1,-1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 27 (-1) ((-1,-1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 28 (1) ((1,1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 29 (-1) ((-1,1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2a (1) ((1,-1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2b (-1) ((-1,-1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2c (1) ((1,1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2d (-1) ((-1,1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2e (1) ((1,-1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2f (-1) ((-1,-1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 30 (1) ((1,1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 31 (-1) ((-1,1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 32 (1) ((1,-1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 33 (-1) ((-1,-1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 34 (1) ((1,1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 35 (-1) ((-1,1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 36 (1) ((1,-1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 37 (-1) ((-1,-1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 38 (1) ((1,1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 39 (-1) ((-1,1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3a (1) ((1,-1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3b (-1) ((-1,-1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3c (1) ((1,1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3d (-1) ((-1,1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3e (1) ((1,-1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3f (-1) ((-1,-1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 40 (1) ((1,1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 41 (-1) ((-1,1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 42 (1) ((1,-1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 43 (-1) ((-1,-1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 44 (1) ((1,1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 45 (-1) ((-1,1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 46 (1) ((1,-1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 47 (-1) ((-1,-1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 48 (1) ((1,1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 49 (-1) ((-1,1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4a (1) ((1,-1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4b (-1) ((-1,-1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4c (1) ((1,1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4d (-1) ((-1,1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4e (1) ((1,-1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4f (-1) ((-1,-1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 50 (1) ((1,1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 51 (-1) ((-1,1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 52 (1) ((1,-1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 53 (-1) ((-1,-1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 54 (1) ((1,1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 55 (-1) ((-1,1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 56 (1) ((1,-1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 57 (-1) ((-1,-1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 58 (1) ((1,1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 59 (-1) ((-1,1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5a (1) ((1,-1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5b (-1) ((-1,-1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5c (1) ((1,1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5d (-1) ((-1,1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5e (1) ((1,-1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5f (-1) ((-1,-1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 60 (1) ((1,1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 61 (-1) ((-1,1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 62 (1) ((1,-1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 63 (-1) ((-1,-1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 64 (1) ((1,1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 65 (-1) ((-1,1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 66 (1) ((1,-1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 67 (-1) ((-1,-1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 68 (1) ((1,1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 69 (-1) ((-1,1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6a (1) ((1,-1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6b (-1) ((-1,-1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6c (1) ((1,1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6d (-1) ((-1,1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6e (1) ((1,-1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6f (-1) ((-1,-1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 70 (1) ((1,1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 71 (-1) ((-1,1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 72 (1) ((1,-1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 73 (-1) ((-1,-1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 74 (1) ((1,1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 75 (-1) ((-1,1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 76 (1) ((1,-1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 77 (-1) ((-1,-1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 78 (1) ((1,1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 79 (-1) ((-1,1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7a (1) ((1,-1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7b (-1) ((-1,-1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7c (1) ((1,1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7d (-1) ((-1,1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7e (1) ((1,-1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7f (-1) ((-1,-1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 80 (1) ((1,1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 81 (-1) ((-1,1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 82 (1) ((1,-1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 83 (-1) ((-1,-1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 84 (1) ((1,1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 85 (-1) ((-1,1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 86 (1) ((1,-1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 87 (-1) ((-1,-1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 88 (1) ((1,1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 89 (-1) ((-1,1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8a (1) ((1,-1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8b (-1) ((-1,-1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8c (1) ((1,1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8d (-1) ((-1,1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8e (1) ((1,-1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8f (-1) ((-1,-1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 90 (1) ((1,1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 91 (-1) ((-1,1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 92 (1) ((1,-1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 93 (-1) ((-1,-1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 94 (1) ((1,1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 95 (-1) ((-1,1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 96 (1) ((1,-1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 97 (-1) ((-1,-1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 98 (1) ((1,1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 99 (-1) ((-1,1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9a (1) ((1,-1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9b (-1) ((-1,-1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9c (1) ((1,1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9d (-1) ((-1,1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9e (1) ((1,-1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9f (-1) ((-1,-1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s a0 (1) ((1,1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a1 (-1) ((-1,1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a2 (1) ((1,-1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a3 (-1) ((-1,-1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a4 (1) ((1,1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a5 (-1) ((-1,1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a6 (1) ((1,-1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a7 (-1) ((-1,-1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a8 (1) ((1,1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s a9 (-1) ((-1,1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s aa (1) ((1,-1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ab (-1) ((-1,-1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ac (1) ((1,1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ad (-1) ((-1,1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ae (1) ((1,-1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s af (-1) ((-1,-1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s b0 (1) ((1,1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b1 (-1) ((-1,1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b2 (1) ((1,-1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b3 (-1) ((-1,-1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b4 (1) ((1,1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b5 (-1) ((-1,1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b6 (1) ((1,-1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b7 (-1) ((-1,-1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b8 (1) ((1,1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s b9 (-1) ((-1,1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s ba (1) ((1,-1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bb (-1) ((-1,-1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bc (1) ((1,1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bd (-1) ((-1,1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s be (1) ((1,-1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bf (-1) ((-1,-1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s c0 (1) ((1,1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c1 (-1) ((-1,1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c2 (1) ((1,-1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c3 (-1) ((-1,-1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c4 (1) ((1,1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c5 (-1) ((-1,1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c6 (1) ((1,-1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c7 (-1) ((-1,-1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c8 (1) ((1,1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s c9 (-1) ((-1,1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s ca (1) ((1,-1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cb (-1) ((-1,-1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cc (1) ((1,1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cd (-1) ((-1,1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s ce (1) ((1,-1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cf (-1) ((-1,-1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s d0 (1) ((1,1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d1 (-1) ((-1,1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d2 (1) ((1,-1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d3 (-1) ((-1,-1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d4 (1) ((1,1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d5 (-1) ((-1,1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d6 (1) ((1,-1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d7 (-1) ((-1,-1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d8 (1) ((1,1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s d9 (-1) ((-1,1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s da (1) ((1,-1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s db (-1) ((-1,-1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s dc (1) ((1,1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s dd (-1) ((-1,1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s de (1) ((1,-1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s df (-1) ((-1,-1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s e0 (1) ((1,1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e1 (-1) ((-1,1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e2 (1) ((1,-1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e3 (-1) ((-1,-1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e4 (1) ((1,1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e5 (-1) ((-1,1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e6 (1) ((1,-1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e7 (-1) ((-1,-1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e8 (1) ((1,1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s e9 (-1) ((-1,1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ea (1) ((1,-1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s eb (-1) ((-1,-1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ec (1) ((1,1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ed (-1) ((-1,1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ee (1) ((1,-1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ef (-1) ((-1,-1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s f0 (1) ((1,1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f1 (-1) ((-1,1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f2 (1) ((1,-1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f3 (-1) ((-1,-1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f4 (1) ((1,1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f5 (-1) ((-1,1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f6 (1) ((1,-1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f7 (-1) ((-1,-1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f8 (1) ((1,1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f9 (-1) ((-1,1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fa (1) ((1,-1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fb (-1) ((-1,-1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fc (1) ((1,1),(-1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fd (-1) ((-1,1),(-1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fe (1) ((1,-1),(-1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s ff (-1) ((-1,-1),(-1,-1),(-1,-1),(-1,-1)) +in 0, out 0 +in 1, out ffffffff +in 2, out 4ba5a933 +in 3, out b45a56cc +in 4, out 7d910e5a +in 5, out 826ef1a5 +in 6, out 3634a769 +in 7, out c9cb5896 +[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value) +[LOADER] library libldpc.so successfully loaded +[PHY] Initialise nr transport +[PHY] Allocating Transport Channel Buffers for PUCCH 0/2 +[PHY] Allocating Transport Channel Buffers for PUCCH 1/2 +[PHY] Allocating Transport Channel Buffers for DLSCH 0/2 +[PHY] Allocating Transport Channel Buffers for DLSCH 1/2 +[PHY] Allocating Transport Channel Buffer for ULSCH, UE 0 +[PHY] Allocating Transport Channel Buffer for ULSCH, UE 1 +Before ULSCH init : 0x3f4b300 +ULSCH_id 0 : 0x3f4b300 +ULSCH_id 0 (before rx antenna alloc) : 0x3f4b300 +ULSCH_id 0 (before llr alloc) : 0x3f4b300 +ULSCH_id 0 (after llr alloc) : 0x3f4b300 +ULSCH_id 1 : 0x3f4b300 +ULSCH_id 1 (before rx antenna alloc) : 0x3f4b300 +ULSCH_id 1 (before llr alloc) : 0x3f4b300 +ULSCH_id 1 (after llr alloc) : 0x3f4b300 +After ULSCH init : 0x3f4b300 +[PHY] Mapping RX ports from 1 RUs to gNB 0 +[PHY] gNB->num_RU:1 +[PHY] Attaching RU 0 antenna 0 to gNB antenna 0 +[PHY] Initializing gNB processes instance:0 CC_id 0 +[PHY] gNB->single_thread_flag:1 +ALL RUs ready - ALL gNBs ready +Sending sync to all threads +About to call end_configmodule() from main() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-softmodem.c:983 +[CONFIG] calling config module end function... +got sync (ru_thread) +[CONFIG] free 398 config value pointers +Called end_configmodule() from main() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-softmodem.c:985 +TYPE TO TERMINATE +Entering ITTI signals handler +[HW] Time in secs now: 112963128 +[HW] Time in secs last pps: 80717015 +[PHY] RU 0 rf device ready +[PHY] RU 0 no asynch_south interface +initializing tx write thread +end of tx write thread +[PHY] tx write thread ready +[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes +[PHY] ru_thread_prach() RACH waiting for RU to be configured +[PHY] ru_thread_prach() RU configured - RACH processing thread running +[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 216, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 224, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 232, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 240, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 248, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 256, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 264, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 272, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 280, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 288, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 296, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 304, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 312, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 320, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 328, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 336, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 344, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 352, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 360, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 368, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 376, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 384, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 392, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 400, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 408, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 416, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 424, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 432, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 440, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 448, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 456, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 464, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 472, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 480, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 488, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 496, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 504, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 512, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 520, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 528, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 536, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 544, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 552, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 560, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 568, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 576, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 584, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 592, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 600, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 608, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 616, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 624, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 632, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 640, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 648, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 656, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 664, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 672, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 680, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 688, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 696, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 704, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 712, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 720, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 728, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 736, slot 0: Adding BCH PDU in position 0 (length 3) +[SCTP] Found data for descriptor 87 +[SCTP] [136][87] Msg of length 2161 received from port 36422, on stream 0, PPID 27 + + + 27 + + + + + + 111 + + + 0 + + + + 248 + + + + + 0000000000000000 + + + 0000000000000000 + + + + + + 203 + + + + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + + + + + 204 + + + + 100000000 + 100000000 + + + + + 205 + + + + + 209 + + + + 5 + 1 + + + + + + + + + 1 + + 15 + + + + + + + 11000000101010000001001001100011 + + 00 00 00 02 + + + + + + + + + + + 206 + + + + 3A 03 08 78 8D DB 80 51 81 80 01 04 0C 20 71 63 + 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF CC 58 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C 00 8C + 85 3C 10 65 3A 54 97 1F C0 68 FE 00 00 00 00 02 + 04 BD 80 00 00 08 09 DF 00 00 00 02 EE C0 0C 00 + A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 03 04 + 01 82 10 C1 08 60 84 30 42 18 20 0C 10 06 08 43 + 04 21 82 00 C1 00 60 80 30 40 18 20 0C 10 06 18 + 02 10 C3 00 42 18 60 08 43 0C 01 08 61 80 21 0C + 30 04 21 86 00 84 30 C0 10 86 10 02 18 40 08 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 10 02 18 20 0C 10 06 18 02 10 C3 00 42 18 60 08 + 43 0C 01 08 61 00 21 84 00 86 10 02 18 41 08 61 + 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 86 + 10 42 18 41 08 60 84 30 42 18 21 0C 10 86 00 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 08 43 04 21 82 00 C1 00 60 04 B4 7D 54 6C 1E 00 + 00 2E 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 + 10 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 + 06 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 + 80 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 + 00 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 + 00 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 + 02 08 0D A1 00 0F F0 00 40 07 4C 00 10 11 82 08 + 2A 61 03 18 00 10 41 C7 00 04 04 60 82 0A 38 40 + C6 00 04 10 71 80 01 05 08 20 82 8C 10 70 80 01 + 04 1C 60 00 41 40 08 20 A3 04 1C 00 00 41 07 4C + 00 10 10 02 08 2A 61 03 00 00 10 41 C2 00 04 14 + 00 82 0A 10 41 C0 00 04 10 76 C0 01 01 08 20 82 + B6 10 30 80 01 04 1D 30 00 40 42 08 20 A9 84 0C + 20 00 41 07 1C 00 10 10 82 08 28 E1 03 08 00 10 + 43 D3 00 04 04 60 82 84 12 50 02 08 6A 61 03 18 + 00 10 50 82 4A 00 41 0D 4C 20 23 04 1C 20 00 49 + 40 08 21 A9 84 04 60 82 84 12 70 00 01 04 3D 30 + 00 40 46 08 28 41 05 00 20 86 A6 10 31 80 01 05 + 08 20 A0 04 10 D4 C2 02 30 41 C2 00 04 14 00 82 + 1A 98 40 46 08 28 41 07 00 00 10 42 D3 00 04 04 + 60 82 84 12 42 53 08 18 C0 00 82 84 12 42 53 08 + 08 C1 07 08 00 12 42 D3 00 04 04 60 82 84 10 42 + 53 08 18 C0 00 82 84 10 42 53 08 08 C1 07 08 00 + 10 42 D3 00 04 04 60 82 80 10 42 53 08 18 C0 00 + 82 80 10 42 53 08 08 C1 07 00 00 10 41 D3 00 04 + 04 60 92 0A 98 40 C6 00 04 90 F1 C0 01 01 18 20 + A1 04 14 00 82 1A 38 40 C6 00 04 14 20 82 80 10 + 43 47 08 08 C1 07 08 00 10 50 02 08 68 E1 01 18 + 20 A1 04 1C 00 00 41 0B 1C 00 10 11 82 0A 10 41 + 09 1C 20 63 00 02 0A 10 41 09 1C 20 23 04 1C 20 + 00 41 0B 18 00 12 50 82 0A 00 41 09 18 24 E1 00 + 02 0A 00 41 09 18 24 A1 04 1C 00 00 41 0B 18 00 + 10 50 82 4A 00 41 09 18 20 E1 00 02 4A 00 41 09 + 18 20 A1 04 9C 00 00 41 0B 18 00 10 50 82 0A 00 + 41 09 18 20 E1 00 02 0A 00 41 09 18 20 A1 04 1C + 00 00 41 07 18 04 12 50 82 08 28 C1 27 08 00 10 + 41 C6 00 04 14 20 92 0A 30 41 C2 01 04 90 31 80 + 41 24 2D 30 00 40 42 09 28 01 04 25 30 81 84 00 + 09 28 01 04 25 30 80 84 12 70 00 01 04 2D 30 00 + 40 42 08 28 01 04 25 30 81 84 00 08 28 01 04 25 + 30 80 84 10 70 00 01 04 1C 20 10 49 40 08 20 A1 + 04 9C 00 00 41 07 4C 00 10 10 82 48 2A 61 03 08 + 00 12 40 C2 01 04 9B B6 3F FF FF E5 7F FB 1F FF + FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF + 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF + 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F + FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF + FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF + FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB + 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC + AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF + FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F + FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF + FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF + B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF + CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F + FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 + FF B1 FF FF FF 2B FF B6 76 00 00 7E C4 0D 9D 80 + 00 04 7C EC 00 00 BA 00 00 00 8B C5 E2 F1 78 78 + 78 78 72 1E 1E 1E 1E 1E 1E 3F 8F C2 1E 1E 1E 1E + 1E 1E 1E 1E 1E 1E 2F 17 8B 90 F0 F0 F0 F1 78 BC + 5E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1C 8B 80 0F 74 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 04 04 10 04 01 00 40 10 + 04 01 00 40 10 04 01 00 40 10 04 01 00 40 10 04 + 03 00 0C 00 30 00 C0 03 00 0C 00 30 00 C0 02 00 + 20 02 00 20 02 00 20 02 00 20 02 00 10 04 03 00 + 0C 00 30 00 C0 02 00 20 02 00 20 02 00 20 02 00 + 20 02 00 20 02 00 20 01 00 40 10 04 00 02 00 20 + 02 00 20 02 00 20 01 00 40 10 04 00 3E 08 02 40 + 07 CC AF 34 08 02 96 3F FF FF FF FF FF FC D2 97 + 78 A0 1F 00 08 40 13 0C 00 00 00 00 00 0A A1 34 + 91 02 02 00 05 E4 84 12 E2 80 02 6B C0 C0 04 00 + 01 04 10 40 00 28 C8 00 00 08 80 00 05 58 E1 00 + 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 0E 22 + 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 10 00 + A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 42 54 + 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 1A 02 + 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 00 02 + 0C 30 00 1A 55 30 62 00 11 C0 48 16 0C 01 C4 D0 + 00 00 00 40 04 03 40 4D 01 04 40 41 4E 9C 00 02 + 00 01 00 80 80 10 02 00 + + + + + + + + +[X2AP] X2AP_ProcedureCode_id_sgNBAdditionPreparation message! +[X2AP] X2AP Association id: 136 +[RRC] x2u tunnel: index 0 target sgw ip 192.168.18.99 length 32 gtp teid 0 +[NR_RRC] Received message X2AP_ENDC_SGNB_ADDITION_REQ +[NR_RRC] Received ENDC sgNB addition request from X2AP + + + + + 1 + + + + + + + + DD B8 05 18 18 00 10 40 C2 07 16 30 81 12 44 CC + 19 36 70 FA 14 A9 93 A8 5A FC C5 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FD FF 3F FA FA 20 C0 08 C8 53 C1 06 53 + A5 49 71 FC 06 8F E0 00 00 00 00 20 4B D8 00 00 + 00 80 9D F0 00 00 00 2E EC 00 C0 0A 00 40 00 40 + 0A 00 60 04 82 00 C1 00 60 80 30 40 18 21 0C 10 + 86 08 43 04 21 82 00 C1 00 60 84 30 42 18 20 0C + 10 06 08 03 04 01 82 00 C1 00 61 80 21 0C 30 04 + 21 86 00 84 30 C0 10 86 18 02 10 C3 00 42 18 60 + 08 43 0C 01 08 61 00 21 84 00 86 10 02 18 40 08 + 61 00 21 84 00 86 10 02 18 40 08 61 00 21 82 00 + C1 00 61 80 21 0C 30 04 21 86 00 84 30 C0 10 86 + 10 02 18 40 08 61 00 21 84 10 86 10 42 18 41 08 + 61 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 + 86 08 43 04 21 82 10 C1 08 60 06 10 02 18 40 08 + 61 00 21 84 00 86 10 02 18 40 08 60 84 30 42 18 + 20 0C 10 06 00 4B 47 D5 46 C1 E0 00 02 E8 18 C0 + 00 82 06 00 00 20 81 82 00 08 00 61 00 02 08 18 + 60 00 80 06 20 00 20 01 8E 00 08 00 65 80 02 00 + 19 80 00 80 06 80 00 20 01 A2 00 08 00 69 00 02 + 00 1A 60 00 80 06 C0 00 20 01 B2 00 08 00 6D 80 + 02 00 0B 81 00 05 F0 80 07 08 00 20 01 CA 00 08 + 20 73 00 02 00 1C E0 00 82 07 40 00 20 80 DA 10 + 00 FF 00 04 00 74 C0 01 01 18 20 82 A6 10 31 80 + 01 04 1C 70 00 40 46 08 20 A3 84 0C 60 00 41 07 + 18 00 10 50 82 08 28 C1 07 08 00 10 41 C6 00 04 + 14 00 82 0A 30 41 C0 00 04 10 74 C0 01 01 00 20 + 82 A6 10 30 00 01 04 1C 20 00 41 40 08 20 A1 04 + 1C 00 00 41 07 6C 00 10 10 82 08 2B 61 03 08 00 + 10 41 D3 00 04 04 20 82 0A 98 40 C2 00 04 10 71 + C0 01 01 08 20 82 8E 10 30 80 01 04 3D 30 00 40 + 46 08 28 41 25 00 20 86 A6 10 31 80 01 05 08 24 + A0 04 10 D4 C2 02 30 41 C2 00 04 94 00 82 1A 98 + 40 46 08 28 41 27 00 00 10 43 D3 00 04 04 60 82 + 84 10 50 02 08 6A 61 03 18 00 10 50 82 0A 00 41 + 0D 4C 20 23 04 1C 20 00 41 40 08 21 A9 84 04 60 + 82 84 10 70 00 01 04 2D 30 00 40 46 08 28 41 24 + 25 30 81 8C 00 08 28 41 24 25 30 80 8C 10 70 80 + 01 24 2D 30 00 40 46 08 28 41 04 25 30 81 8C 00 + 08 28 41 04 25 30 80 8C 10 70 80 01 04 2D 30 00 + 40 46 08 28 01 04 25 30 81 8C 00 08 28 01 04 25 + 30 80 8C 10 70 00 01 04 1D 30 00 40 46 09 20 A9 + 84 0C 60 00 49 0F 1C 00 10 11 82 0A 10 41 40 08 + 21 A3 84 0C 60 00 41 42 08 28 01 04 34 70 80 8C + 10 70 80 01 05 00 20 86 8E 10 11 82 0A 10 41 C0 + 00 04 10 B1 C0 01 01 18 20 A1 04 10 91 C2 06 30 + 00 20 A1 04 10 91 C2 02 30 41 C2 00 04 10 B1 80 + 01 25 08 20 A0 04 10 91 82 4E 10 00 20 A0 04 10 + 91 82 4A 10 41 C0 00 04 10 B1 80 01 05 08 24 A0 + 04 10 91 82 0E 10 00 24 A0 04 10 91 82 0A 10 49 + C0 00 04 10 B1 80 01 05 08 20 A0 04 10 91 82 0E + 10 00 20 A0 04 10 91 82 0A 10 41 C0 00 04 10 71 + 80 41 25 08 20 82 8C 12 70 80 01 04 1C 60 00 41 + 42 09 20 A3 04 1C 20 10 49 03 18 04 12 42 D3 00 + 04 04 20 92 80 10 42 53 08 18 40 00 92 80 10 42 + 53 08 08 41 27 00 00 10 42 D3 00 04 04 20 82 80 + 10 42 53 08 18 40 00 82 80 10 42 53 08 08 41 07 + 00 00 10 41 C2 01 04 94 00 82 0A 10 49 C0 00 04 + 10 74 C0 01 01 08 24 82 A6 10 30 80 01 24 0C 20 + 10 49 BB 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF + B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF + CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F + FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 + FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF + FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD + 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE + 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F + FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF + FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF + FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC + 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 + BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF + FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF + EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF + F2 BF FB 67 60 00 07 EC 40 D9 D8 00 00 47 CE C0 + 00 0B A0 00 00 08 BC 5E 2F 17 87 87 87 87 21 E1 + E1 E1 E1 E1 E3 F8 FC 21 E1 E1 E1 E1 E1 E1 E1 E1 + E1 E2 F1 78 B9 0F 0F 0F 0F 17 8B C5 E1 E1 E1 E1 + E1 E1 E1 E1 E1 E1 E1 C8 B8 00 F7 40 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 40 41 00 40 10 04 01 00 40 10 04 01 + 00 40 10 04 01 00 40 10 04 01 00 40 30 00 C0 03 + 00 0C 00 30 00 C0 03 00 0C 00 20 02 00 20 02 00 + 20 02 00 20 02 00 20 01 00 40 30 00 C0 03 00 0C + 00 20 02 00 20 02 00 20 02 00 20 02 00 20 02 00 + 20 02 00 10 04 01 00 40 00 20 02 00 20 02 00 20 + 02 00 10 04 01 00 40 03 E0 80 24 00 7C CA F3 40 + 80 29 63 FF FF FF FF FF FF CD 29 77 8A 01 F0 00 + 84 01 30 C0 00 00 00 00 00 AA 13 49 10 20 20 00 + 5E 48 41 2E 28 00 26 BC 0C 00 40 00 10 41 04 00 + 02 8C 80 00 00 88 00 00 + + + + + + E1 00 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 + 0E 22 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 + 10 00 A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 + 42 54 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 + 1A 02 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 + 00 02 0C 30 00 1A 55 30 + + + + + + 01 1C 04 81 60 C0 1C 4D 00 00 00 04 00 40 34 04 + D0 10 44 04 14 E9 C0 00 20 00 10 08 08 01 00 20 + + + + + + + + + + +[NR_RRC] Returning new UE context at 0x7f5188003980 + + 1 + + + 4 + + 1 + + + + + + + + + + + + + + + + + + + + + 1 + + + 1 + + + + + + + + + + + + + + + 0 + + + + + + + + + + + + + + + + + + + 20 + + + + 1 + + + 0 + + + 641272 + + 78 + + 640000 + + + 0 + + 106 + + + + + + 6366 + + + + + 0 + 0 + + + + + + + 0 + + 40 + + + 0 + + 53 + + + 0 + + 54 + + + 0 + + 57 + + + + + + + + + + 78 + + + + 0 + + 106 + + + 20 + + + + 6366 + + + + + + 98 + + 0 + 13 + -100 + + + + + + + + + 19 + + 1 + + + + + + + + + + + 2 + + 55 + + + 2 + + 69 + + + 7 + + 52 + + + 1 + -90 + + + + + 0 + + 40 + -90 + + + + + + + + 10000000 + + + + + + + + + + 7 + 6 + 2 + 4 + + + -25 + + 9195 + + + + + + + 98 + + 0 + 13 + -100 + + + + + + + + + + 0 + 63 + + + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + + + 28875 + + + + + + 1 + + 111111111111111100000000000000000000000000000 + + 1 + + + + + + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + + + 1 + 1 + + + + + 11000000000000 + + + + + + + + + + + + + + + + + 1 + + + + + + + 0 + + 40 + + + 0 + + 53 + + + 0 + + 54 + + + 0 + + 57 + + + + + + + + + + + 1 + + 111111111111111100000000000000000000000000000 + + 1 + + + + + + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + + + + 2 + 1 + + + + + 11000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + 1 + + + + + + + + + + + + + + + + 0 + 0 + + + + + + 0 + + 0 + + + + + + + + 1 + + + + + + + 0 + + 0 + + + + 1 + 2 + + + + + -80 + + + + + 0 + + + + 0 + 0 + + + + 2 + + + + 0 + 0 + + 61 + 0 + 0 + + + + + + + 40 + + + 0 + + + + + + + + + + 1 + + + 28875 + + + + + + 98 + + 0 + 13 + -100 + + + + + + + + + 19 + + 1 + + + + + + + + + + + 2 + + 55 + + + 2 + + 69 + + + 7 + + 52 + + + 1 + -90 + + + + + 0 + + 40 + -90 + + + + + + + + + 0 + + 1 + 2 + + + + 1 + + 3 + 4 + + + + + + 1 + 48 + + + 0 + 1 + 13 + + + + + 2 + 48 + + + 0 + 1 + 12 + + + + + 3 + 40 + + + 16 + 1 + 13 + + + + + 4 + 40 + + + 16 + 1 + 12 + + + + + + + + + + + 2 + 3 + 4 + 5 + 6 + 7 + 0 + 0 + + + + 1 + + 0 + + 0 + 1 + + + + + 0 + 0 + 0 + 0 + 0 + + + 1 + 0 + + + + + 0 + + 0 + + + + + + + + + + + + + + + + + + + + 0 + 0 + + + + + + 0 + + 0 + + + + + + + + 1 + + + + + + + 0 + + 0 + + + + 1 + 2 + + + + + -80 + + + + + 0 + + + + 0 + 0 + + + + 2 + + + + 0 + 0 + + 61 + 0 + 0 + + + + + + + 40 + + + 0 + + + + + + + + + + 1 + + + + + 2 + + + + 0 + + + + + + + + 5 + + 1 + + + + + + + + + + + + + + + + + + + + +[RRC] Dumping NR_RRCReconfiguration message (309 bytes) +0881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100 +[RRC] Dumping scg_RB_Config message (8 bytes) +1409281782c00c00 +[RRC] S1-U tunnel: index 0 target sgw ip 192.168.18.99 length 32 gtp teid 2 +[GTPV1U] Configured GTPu address : c612a8c0 +[GTPV1U] Copied to create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.198 length 4 gtp teid 2462855170 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 23eb] rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (2462855170, 2462855170) bearer UE context index 0, msg index 0, id 5, gtp addr len 4 +[RRC] S1-U create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.198 length 4 gtp teid 2462855170 +[RRC] X2AP sGNB Addition Request: index 0 target gNB ip 192.168.18.198 length 32 gtp teid 2462855170 +[MAC] [gNB 0] Adding UE with rnti 23eb (next avail 0, num_UEs 0) +[MAC] gNB 0] Add NR UE_id 0 : rnti 23eb +[PHY] Added new UE_id 0/23eb with initial secondaryCellGroup + + + 27 + + + + + + 111 + + + 0 + + + + 207 + + + 0 + + + + 210 + + + + + 213 + + + + 5 + + + + + + + + + + 11000000101010000001001011000110 + + 92 CC 30 02 + + + + + + + + + + + 211 + + + + 18 04 09 A8 44 09 92 E2 07 8E 01 90 43 7E 30 D0 + 41 E6 41 C8 54 1E 21 00 83 2B A1 6E 63 00 1A 4E + 47 C0 13 49 C4 00 00 00 26 96 18 DE 35 00 05 38 + 05 10 0D 60 1B 40 39 D2 02 68 00 01 34 E4 E1 8D + E3 2A 31 00 0D 66 66 BE E4 E0 24 BC A1 5B C2 C5 + 8F 68 9C 2E 00 50 E0 18 04 21 60 3B 00 91 19 1F + 5E 24 62 00 1A CC CD 00 03 F0 DB 00 10 1C 02 D9 + 00 92 00 20 24 04 63 2C E1 96 65 14 0F FF F8 00 + 00 00 08 70 00 41 03 08 14 30 73 70 44 30 00 00 + 80 80 1A 70 0A 20 1A C0 36 80 72 CA 80 40 FF FF + 80 00 00 00 87 00 04 10 30 81 43 07 0D C2 10 C0 + 00 08 05 90 01 01 20 23 25 61 52 C0 E1 04 16 0E + 0C 10 E1 00 71 28 1C 00 00 20 5E F4 01 00 02 00 + 00 0F 40 01 41 00 19 73 86 59 95 18 80 06 B3 33 + 5F 72 70 12 5E 50 AD E1 62 C7 B4 4E 17 00 28 70 + 6A A4 1A 80 81 04 42 0C 20 30 08 C0 03 40 43 00 + 0C 01 8A 17 B4 08 28 5E C9 07 91 A2 B3 80 00 40 + 00 7F 42 10 84 00 80 40 25 81 C2 08 2C 1C 18 21 + C2 00 E2 50 38 00 00 40 BD E8 02 00 04 00 00 1E + 80 02 82 00 70 01 01 88 00 40 A0 49 40 BC 16 00 + 60 00 + + + + + + + + +[X2AP] Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK +[SCTP] Successfully sent 371 bytes on stream 0 for assoc_id 136 +[MAC] Frame 744, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 752, slot 0: Adding BCH PDU in position 0 (length 3) +[PHY] [gNB 0][RAPROC] Frame 751, slot 19 Initiating RA procedure with preamble 63, energy 35.7 dB, delay 6 +[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751, Slot 19 Initiating RA procedure for preamble index 63 +[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751 Activating Msg2 generation in frame 752, slot 7 using RA rnti 10b +[MAC] [gNB 0] [RAPROC] CC_id 0 Frame 752, slotP 7: Generating RAR DCI, state 1 +[MAC] [RAPROC] DCI type 1 payload: freq_alloc 120 (0,6,24), time_alloc 3, vrb to prb 0, mcs 0 tb_scaling 0 +[MAC] Frame 752: Subframe 7 : Adding common DL DCI for RA_RNTI 10b +[MAC] Frame 752, Subframe 7: Setting Msg3 reception for Frame 752 Subframe 17 +[PHY] ULSCH received ok +[MAC] [gNB 0][RAPROC] PUSCH with TC_RNTI c497 received correctly and UE_id 0 is now 5G connected +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 753 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 753 slot 8 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 754 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 754 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 754 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 755 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 755 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 755 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 756 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 756 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 756 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32777 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 757 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 757 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 757 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 758 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 758 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 758 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 759 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 759 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 759 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 760, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 760 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 760 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 760 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 761 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 761 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 761 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 762 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 762 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 762 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 763 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 763 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 763 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 764 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 764 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 764 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 765 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 765 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 765 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 766 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 766 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 766 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 767 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 767 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 767 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 768, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 768 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 768 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 768 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 769 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 770 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 770 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 770 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 771 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 771 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 771 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 772 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 772 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 772 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 773 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 773 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 773 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 774 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 774 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 774 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 775 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 775 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 775 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 776, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 776 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 776 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 776 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 777 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 777 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 777 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 778 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 778 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 778 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 779 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 779 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 779 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 780 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 780 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 780 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 781 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 781 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 781 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 782 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 782 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 782 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 783 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 783 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 783 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 784, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 784 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 784 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 784 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 785 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 785 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 785 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 786 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 786 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 786 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 787 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 787 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 787 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 788 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 788 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 788 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 789 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 789 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 789 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 790 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 790 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 790 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 791 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 791 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 791 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 792, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 792 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 792 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 792 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 793 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 793 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 793 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 794 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 794 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 794 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 795 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 795 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 795 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 796 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 796 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 796 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 797 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 797 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 797 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 798 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 798 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 798 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 799 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 799 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 799 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 800, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 800 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 800 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 800 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 801 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 801 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 801 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 802 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 802 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 802 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 803 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 803 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 803 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 804 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 804 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 804 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 805 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 805 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 805 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 806 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 806 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 806 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 807 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 808, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 808 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 808 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 808 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 809 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 809 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 809 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 810 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 810 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 810 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 811 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 811 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 811 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 812 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 812 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 812 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 813 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 813 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 813 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 814 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 814 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 814 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 815 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 815 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 815 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 816, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 816 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 816 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 816 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 817 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 817 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 817 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 818 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 818 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 818 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 819 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 819 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 819 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 820 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 820 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 820 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 821 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 821 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 821 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 822 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 822 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 822 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 823 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 823 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 823 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 824, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 824 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 824 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 824 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 825 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 825 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 825 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 826 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 826 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 826 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 827 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 827 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 827 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 828 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 828 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 828 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 829 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 829 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 829 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 830 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 830 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 830 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 831 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 831 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 831 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 832, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 832 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 832 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 832 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 833 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 833 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 833 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 834 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 834 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 834 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 835 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 835 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 835 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 836 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 836 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 836 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 837 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 837 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 837 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 838 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 838 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 838 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 839 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 839 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 839 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 840, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 840 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 840 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 840 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 841 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 841 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 841 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 842 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 842 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 842 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 843 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 843 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 843 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 844 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 844 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 844 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 845 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 845 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 845 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 846 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 846 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 846 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 847 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 847 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 847 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 848, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 848 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 848 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 848 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 849 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 849 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 849 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 850 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 850 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 850 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 851 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 851 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 851 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 852 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 852 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 852 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 853 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 853 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 853 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 854 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 854 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 854 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 855 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 855 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 855 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 856, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 856 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 856 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 856 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 857 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 857 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 857 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 858 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 858 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 858 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 859 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 859 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 859 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 860 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 860 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 860 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 861 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 861 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 861 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 862 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 862 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 862 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 863 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 863 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 863 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 864, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 864 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 864 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 864 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 865 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 865 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 865 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 866 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 866 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 866 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 867 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 867 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 867 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 868 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 868 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 868 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 869 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 869 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 869 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 870 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 870 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 870 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 871 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 871 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 871 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 872, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 872 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 872 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 872 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 873 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 873 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 873 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 874 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 874 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 874 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 875 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 875 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 875 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 876 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 876 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 876 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 877 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 877 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 877 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 878 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 878 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 878 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 879 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 879 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 879 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 880, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 880 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 880 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 880 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 881 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 881 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 881 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 882 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 882 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 882 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 883 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 883 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 883 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 884 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 884 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 884 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 885 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 885 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 885 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 886 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 886 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 886 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 887 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 887 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 887 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 888, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 888 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 888 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 888 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 889 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 889 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 889 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 890 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 890 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 890 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 891 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 891 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 891 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 892 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 892 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 892 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 893 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 893 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 893 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 894 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 894 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 894 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 895 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 895 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 895 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 896, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 896 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 896 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 896 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 897 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 897 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 897 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 898 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 898 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 898 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 899 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 899 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 899 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 900 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 900 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 900 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 901 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 901 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 901 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 902 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 902 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 902 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 903 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 903 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 903 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 904, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 904 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 904 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 904 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 905 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 905 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 905 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 906 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 906 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 906 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 907 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 907 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 907 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 908 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 908 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 908 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 909 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 909 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 909 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 910 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 910 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 910 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 911 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 911 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 911 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 912, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 912 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 912 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 912 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 913 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 913 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 913 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 914 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 914 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 914 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 915 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 915 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 915 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 916 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 916 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 916 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 917 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 917 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 917 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 918 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 918 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 918 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 919 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 919 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 919 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 920, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 920 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 920 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 920 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 921 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 921 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 921 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 922 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 922 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 922 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 923 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 923 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 923 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 924 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 924 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 924 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 925 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 925 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 925 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 926 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 926 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 926 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 927 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 927 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 927 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 928, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 928 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 928 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 928 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 929 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 929 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 929 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 930 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 930 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 930 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 931 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 931 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 931 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 932 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 932 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 932 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 933 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 933 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 933 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 934 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 934 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 934 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 935 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 935 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 935 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 936, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 936 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 937 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 937 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 937 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 938 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 938 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 938 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 939 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 939 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 939 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 940 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 940 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 940 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 941 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 941 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 941 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 942 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 942 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 942 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 943 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 943 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 943 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 944, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 944 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 944 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 944 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 945 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 945 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 945 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 946 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 946 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 946 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 947 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 947 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 947 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 948 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 948 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 948 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 949 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 949 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 949 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 950 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 950 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 950 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 951 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 951 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 951 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 952, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 952 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 952 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 952 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 953 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 953 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 953 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 954 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 954 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 954 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 955 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 955 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 955 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 956 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 956 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 956 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 957 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 957 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 957 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 958 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 958 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 958 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 959 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 959 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 959 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 960, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 960 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 960 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 960 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 961 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 961 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 961 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 962 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 962 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 962 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 963 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 963 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 963 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 964 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 964 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 964 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 965 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 965 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 965 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 966 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 966 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 966 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 967 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 967 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 967 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 968, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 968 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 968 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 968 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 969 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 969 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 969 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 970 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 970 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 970 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 971 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 971 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 971 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 972 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 972 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 972 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 973 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 973 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 973 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 974 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 974 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 974 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 975 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 975 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 975 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 976, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 976 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 976 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 976 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 977 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 977 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 977 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 978 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 978 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 978 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 979 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 979 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 979 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 980 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 980 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 980 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 981 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 981 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 981 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 982 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 982 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 982 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 983 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 983 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 983 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 984, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 984 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 984 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 984 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 985 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 985 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 985 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 986 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 986 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 986 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 987 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 987 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 987 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 988 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 988 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 988 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 989 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 989 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 989 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 990 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 990 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 990 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 991 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 991 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 991 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 992, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 992 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 992 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 992 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 993 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 993 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 993 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 994 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 994 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 994 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 995 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 995 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 995 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 996 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 996 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 996 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 997 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 997 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 997 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 998 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 998 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 998 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 999 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 999 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 999 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 1000, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1000 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1000 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1000 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1001 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1001 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1001 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1002 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1002 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1002 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1003 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1003 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1003 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1004 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1005 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1005 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1005 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1006 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1006 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1006 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1007 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1007 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1007 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 1008, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1008 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1008 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1008 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1009 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1009 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1009 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1010 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1010 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1010 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1011 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1011 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1011 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1012 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1012 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1012 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1013 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1013 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1013 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1014 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1014 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1014 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1015 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1015 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1015 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 1016, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1016 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1016 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1016 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1017 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1017 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1017 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1018 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1018 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1018 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1019 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1019 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1019 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1020 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1020 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1020 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1021 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1021 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1021 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1022 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1022 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1022 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1023 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1023 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1023 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 0, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 0 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 0 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 0 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 0 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 2 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 2 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 2 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 3 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 3 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 3 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 4 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 4 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 4 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 5 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 5 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 5 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 6 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 6 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 6 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 7 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 7 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 7 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 8 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 8 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 8 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 9 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 10 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 10 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 10 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 11 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 11 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 11 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 12 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 12 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 12 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 13 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 13 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 13 slot 9 +[0mPUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 14 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 14 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 14 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 15 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 15 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 15 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 16 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 16 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 16 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 17 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 17 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 17 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 18 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 18 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 18 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 19 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 19 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 19 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 20 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 20 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 20 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 21 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 21 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 21 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 22 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 22 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 22 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 23 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 23 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 23 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 24 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 24 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 24 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 25 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 25 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 25 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 26 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 26 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 26 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 27 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 27 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 27 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 28 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 28 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 28 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 29 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 29 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 29 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 30 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 30 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 30 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 31 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 31 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 31 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 32 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 32 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 32 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 33 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 33 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 33 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 34 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 34 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 34 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 35 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 35 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 35 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 36 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 36 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 36 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 37 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 37 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 37 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 38 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 38 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 38 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 39 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 39 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 39 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 40 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 40 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 40 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 41 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 41 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 41 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 42 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 42 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 42 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 43 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 43 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 43 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 44 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 44 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 44 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 45 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 45 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 45 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 46 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 46 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 46 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 47 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 47 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 47 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 48 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 48 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 48 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 49 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 49 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 49 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 50 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 50 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 50 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 51 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 51 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 51 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 52 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 52 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 52 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 53 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 53 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 53 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 54 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 54 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 54 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 55 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 55 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 55 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 56 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 56 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 56 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 57 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 57 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 57 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 58 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 58 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 58 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 59 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 59 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 59 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 60 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 60 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 60 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 61 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 61 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 61 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 62 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 62 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 62 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 63 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 63 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 63 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 64 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 64 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 64 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 65 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 65 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 65 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 66 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 66 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 66 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 67 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 67 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 67 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 68 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 68 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 68 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 69 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 69 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 69 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 70 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 70 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 70 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 71 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 71 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 71 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 72 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 72 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 72 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 73 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 73 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 73 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 74 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 74 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 74 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 75 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 75 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 75 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 76 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 76 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 76 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 77 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 77 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 77 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 78 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 78 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 78 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 79 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 79 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 79 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 80 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 80 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 80 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 81 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 81 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 81 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 82 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 82 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 82 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 83 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 83 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 83 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 84 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 84 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 84 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 85 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 85 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 85 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 86 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 86 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 86 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 87 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 87 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 87 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 88 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 88 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 88 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 89 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 89 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 89 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 90 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 90 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 90 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 91 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 91 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 91 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 92 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 92 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 92 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 93 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 93 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 93 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 94 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 94 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 94 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 95 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 95 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 95 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 96 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 96 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 96 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 97 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 97 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 97 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 98 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 98 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 98 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 99 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 99 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 99 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 100 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 100 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 100 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 101 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 101 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 101 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 102 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 102 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 102 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 103 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 103 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 103 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 104 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 104 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 104 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 105 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 105 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 105 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 106 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 106 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 106 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 107 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 107 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 107 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 108 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 108 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 108 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 109 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 109 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 109 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 110 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 110 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 110 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 111 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 111 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 111 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 112 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 112 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 112 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 113 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 113 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 113 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 114 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 114 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 114 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 115 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 115 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 115 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 116 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 116 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 116 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 117 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 117 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 117 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 118 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 118 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 118 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 119 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 119 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 119 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 120 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 120 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 120 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 121 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 121 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 121 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 122 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 123 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 123 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 123 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 124 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 124 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 124 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 125 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 125 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 125 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 126 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 126 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 126 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 127 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 127 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 127 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 128 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 128 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 128 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 129 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 129 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 129 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 130 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 130 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 130 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 131 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 131 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 131 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 132 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 132 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 132 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 133 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 133 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 133 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 134 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 134 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 134 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 135 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 135 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 135 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 136 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 136 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 136 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 137 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 137 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 137 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 138 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 138 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 138 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 139 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 139 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 139 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 140 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 140 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 140 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 141 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 141 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 141 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 142 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 142 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 142 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 143 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 143 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 143 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 144 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 144 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 144 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 145 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 145 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 145 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 146 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 146 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 146 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 147 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 147 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 147 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 148 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 148 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 148 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 149 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 149 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 149 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 150 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 150 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 150 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 151 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 151 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 151 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 152 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 152 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 152 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 153 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 153 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 153 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 154 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 154 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 154 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 155 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 155 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 155 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 156 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 156 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 156 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 157 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 157 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 157 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 158 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 158 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 158 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 159 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 159 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 159 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 160 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 160 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 160 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 161 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 161 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 161 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 162 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 162 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 162 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 163 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 163 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 163 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 164 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 164 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 164 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 165 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 165 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 165 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 166 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 166 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 166 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 167 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 167 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 167 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 168 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 168 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 168 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 169 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 169 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 169 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 170 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 170 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 170 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 171 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 171 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 171 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 172 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 172 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 172 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 173 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 173 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 173 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 174 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 174 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 174 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 175 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 175 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 175 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 176 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 177 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 177 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 177 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 178 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 178 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 178 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 179 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 179 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 179 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 180 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 180 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 180 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 181 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 181 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 181 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 182 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 182 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 182 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 183 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 183 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 183 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 184 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 184 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 184 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 185 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 185 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 185 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 186 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 186 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 186 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 187 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 187 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 187 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 188 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 188 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 188 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 189 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 189 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 189 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 190 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 190 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 190 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 191 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 191 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 191 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 192 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 192 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 192 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 193 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 193 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 193 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 194 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 194 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 194 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 195 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 195 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 195 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 196 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 196 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 196 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 197 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 197 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 197 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 198 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 198 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 198 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 199 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 199 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 199 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 200 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 200 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 200 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 201 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 201 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 201 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 202 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 202 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 202 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 203 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 203 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 203 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 204 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 204 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 204 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 205 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 205 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 205 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 206 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 206 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 206 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 207 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 207 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 207 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 208 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 208 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 208 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 209 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 209 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 209 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 210 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 210 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 210 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 211 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 211 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 211 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 212 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 212 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 212 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 213 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 213 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 213 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 214 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 214 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 214 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 215 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 215 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 215 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 216, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 216 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 216 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 216 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 217 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 217 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 217 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 218 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 218 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 218 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 219 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 219 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 219 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 220 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 220 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 220 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 221 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 221 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 221 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 222 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 222 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 222 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 223 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 223 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 223 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 224, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 224 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 224 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 224 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 225 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 225 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 225 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 226 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 226 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 226 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 227 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 227 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 227 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 228 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 228 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 228 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 229 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 229 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 229 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 230 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 230 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 230 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 231 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 231 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 231 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 232, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 232 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 232 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 232 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 233 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 233 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 233 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 234 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 234 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 234 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 235 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 235 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 235 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 236 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 236 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 236 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 237 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 237 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 237 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 238 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 238 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 238 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 239 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 239 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 239 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 240, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 240 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 240 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 240 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 241 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 241 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 241 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 242 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 242 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 242 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 243 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 243 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 243 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 244 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 244 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 244 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 245 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 245 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 245 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 246 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 246 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 246 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 247 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 247 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 247 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 248, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 248 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 248 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 248 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 249 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 249 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 249 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 250 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 250 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 250 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 251 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 251 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 251 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 252 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 252 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 252 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 253 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 253 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 253 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 254 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 254 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 254 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 255 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 255 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 255 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 256, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 256 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 256 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 256 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 257 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 257 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 257 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 258 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 258 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 258 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 259 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 259 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 259 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 260 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 260 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 260 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 261 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 261 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 261 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 262 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 262 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 262 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 263 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 263 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 263 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 264, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 264 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 264 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 264 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 265 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 265 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 265 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 266 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 266 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 266 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 267 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 267 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 267 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 268 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 268 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 268 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 269 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 269 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 269 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 270 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 270 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 270 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 271 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 271 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 271 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 272, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 272 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 272 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 272 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 273 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 273 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 273 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 274 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 274 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 274 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 275 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 275 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 275 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 276 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 276 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 276 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 277 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 277 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 277 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 278 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 278 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 278 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 279 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 279 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 279 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 280, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 280 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 280 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 280 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 281 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 281 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 281 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 282 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 282 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 282 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 283 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 283 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 283 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 284 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 284 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 284 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 285 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 285 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 285 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 286 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 286 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 286 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 287 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 287 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 287 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 288, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 288 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 288 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 288 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 289 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 289 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 289 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 290 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 290 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 290 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 291 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 291 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 291 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 292 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 292 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 292 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 293 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 293 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 293 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 294 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 294 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 294 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 295 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 295 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 295 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 296, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 296 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 296 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 296 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 297 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 297 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 297 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 298 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 298 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 298 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 299 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 299 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 299 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 300 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 300 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 300 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 301 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 301 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 301 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 302 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 302 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 302 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 303 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 303 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 303 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 304, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 304 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 304 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 304 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 305 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 305 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 305 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 306 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 306 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 306 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 307 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 307 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 307 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 308 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 308 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 308 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 309 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 309 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 309 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 310 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 310 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 310 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 311 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 311 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 311 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 312, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 312 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 312 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 312 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 313 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 313 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 313 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 314 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 314 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 314 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 315 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 315 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 315 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 316 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 316 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 316 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 317 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 317 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 317 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 318 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 318 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 318 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 319 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 319 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 319 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 320, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 320 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 320 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 320 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 321 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 321 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 321 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 322 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 322 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 322 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 323 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 323 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 323 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 324 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 324 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 324 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 325 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 325 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 325 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 326 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 326 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 326 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 327 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 327 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 327 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 328, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 328 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 328 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 328 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 329 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 329 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 329 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 330 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 330 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 330 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 331 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 331 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 331 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 332 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 332 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 332 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 333 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 333 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 333 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 334 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 334 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 334 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 335 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 335 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 335 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 336, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 336 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 336 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 336 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 337 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 337 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 337 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 338 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 338 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 338 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 339 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 339 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 339 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 340 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 340 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 340 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 341 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 341 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 341 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 342 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 342 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 342 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 343 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 343 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 343 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 344, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 344 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 344 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 344 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 345 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 345 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 345 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 346 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 346 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 346 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 347 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 347 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 347 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 348 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 348 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 348 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 349 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 349 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 349 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 350 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 350 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 350 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 351 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 351 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 351 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 352, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 352 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 352 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 352 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 353 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 353 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 353 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 354 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 354 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 354 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 355 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 355 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 355 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 356 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 356 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 356 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 357 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 357 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 357 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 358 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 358 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 358 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 359 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 359 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 359 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 360, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 360 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 360 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 360 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 361 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 361 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 361 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 362 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 362 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 362 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 363 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 363 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 363 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 364 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 364 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 364 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 365 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 365 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 365 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 366 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 366 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 366 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 367 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 367 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 367 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 368, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 368 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 368 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 368 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 369 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 369 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 369 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 370 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 370 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 370 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 371 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 371 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 371 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 372 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 372 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 372 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 373 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 373 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 373 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 374 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 374 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 374 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 375 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 375 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 375 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 376, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 376 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 376 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 376 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 377 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 377 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 377 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 378 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 378 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 378 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 379 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 379 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 379 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 380 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 380 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 380 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 381 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 381 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 381 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 382 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 382 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 382 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 383 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 383 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 383 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 384, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 384 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 384 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 384 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 385 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 385 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 385 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 386 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 386 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 386 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 387 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 387 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 387 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 388 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 388 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 388 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 389 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 389 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 389 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 390 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 390 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 390 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 391 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 391 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 391 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 392, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 392 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 392 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 392 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 393 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 393 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 393 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 394 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 394 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 394 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 395 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 395 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 395 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 396 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 396 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 396 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 397 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 397 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 397 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 398 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 398 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 398 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 399 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 399 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 399 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 400, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 400 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 400 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 400 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 401 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 401 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 401 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 402 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 402 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 402 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 403 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 403 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 403 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 404 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 404 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 404 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 405 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 405 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 405 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 406 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 406 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 406 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 407 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 407 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 407 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 408, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 408 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 408 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 408 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 409 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 409 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 409 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 410 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 410 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 410 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 411 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 411 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 411 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 412 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 412 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 412 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 413 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 413 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 413 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 414 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 414 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 414 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 415 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 415 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 415 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 416, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 416 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 416 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 416 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 417 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 417 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 417 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 418 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 418 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 418 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 419 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 419 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 419 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 420 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 420 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 420 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 421 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 421 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 421 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 422 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 422 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 422 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 423 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 423 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 423 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 424, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 424 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 424 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 424 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 425 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 425 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 425 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 426 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 426 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 426 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 427 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 427 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 427 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 428 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 428 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 428 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 429 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 429 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 429 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 430 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 430 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 430 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 431 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 431 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 431 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 432, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 432 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 432 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 432 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 433 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 433 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 433 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 434 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 434 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 434 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 435 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 435 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 435 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 436 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 436 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 436 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 437 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 437 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 437 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 438 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 438 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 438 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 439 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 439 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 439 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 440, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 440 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 440 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 440 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 441 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 441 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 441 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 442 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 442 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 442 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 443 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 443 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 443 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 444 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 444 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 444 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 445 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 445 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 445 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 446 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 446 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 446 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 447 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 447 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 447 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 448, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 448 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 448 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 448 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 449 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 449 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 449 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 450 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 450 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 450 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 451 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 451 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 451 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 452 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 452 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 452 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 453 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 453 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 453 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 454 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 454 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 454 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 455 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 455 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 455 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 456, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 456 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 456 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 456 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 457 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 457 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 457 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 458 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 458 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 458 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 459 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 459 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 459 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 460 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 460 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 460 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 461 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 461 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 461 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 462 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 462 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 462 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 463 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 463 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 463 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 464, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 464 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 464 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 464 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 465 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 465 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 465 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 466 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 466 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 466 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 467 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 467 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 467 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 468 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 468 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 468 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 469 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 469 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 469 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 470 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 470 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 470 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 471 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 471 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 471 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 472, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 472 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 472 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 472 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 473 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 473 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 473 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 474 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 474 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 474 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 475 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 475 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 475 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 476 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 476 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 476 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 477 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 477 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 477 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 478 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 478 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 478 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 479 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 479 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 479 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 480, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 480 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 480 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 480 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 481 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 481 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 481 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 482 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 482 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 482 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 483 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 483 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 483 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 484 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 484 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 484 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 485 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 485 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 485 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 486 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 486 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 486 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 487 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 487 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 487 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 488, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 488 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 488 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 488 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 489 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 489 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 489 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 490 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 490 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 490 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 491 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 491 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 491 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 492 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 492 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 492 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 493 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 493 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 493 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 494 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 494 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 494 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 495 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 495 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 495 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 496, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 496 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 496 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 496 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 497 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 497 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 497 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 498 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 498 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 498 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 499 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 499 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 499 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 500 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 500 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 500 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 501 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 501 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 501 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 502 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 502 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 502 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 503 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 503 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 503 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 504, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 504 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 504 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 504 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 505 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 505 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 505 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 506 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 506 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 506 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 507 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 507 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 507 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 508 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 508 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 508 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 509 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 509 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 509 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 510 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 510 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 510 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 511 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 511 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 511 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 512, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 512 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 512 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 512 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 513 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 513 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 513 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 514 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 514 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 514 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 515 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 515 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 515 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 516 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 516 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 516 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 517 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 517 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 517 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 518 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 518 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 518 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 519 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 519 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 519 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 520, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 520 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 520 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 520 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 521 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 521 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 521 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 522 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 522 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 522 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 523 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 523 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 523 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 524 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 524 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 524 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 525 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 525 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 525 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 526 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 526 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 526 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 527 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 527 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 527 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 528, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 528 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 528 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 528 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 529 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 529 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 529 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 530 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 530 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 530 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 531 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 531 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 531 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 532 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 532 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 532 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 533 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 533 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 533 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 534 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 534 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 534 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 535 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 535 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 535 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 536, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 536 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 536 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 536 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 537 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 537 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 537 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 538 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 538 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 538 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 539 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 539 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 539 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 540 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 540 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 540 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 541 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 541 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 541 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 542 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 542 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 542 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 543 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 543 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 543 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 544, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 544 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 544 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 544 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 545 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 545 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 545 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 546 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 546 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 546 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 547 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 547 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 547 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 548 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 548 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 548 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 549 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 549 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 549 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 550 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 550 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 550 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 551 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 551 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 551 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 552, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 552 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 552 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 552 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 553 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 553 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 553 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 554 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 554 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 554 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 555 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 555 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 555 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 556 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 556 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 556 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 557 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 557 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 557 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 558 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 558 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 558 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 559 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 559 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 559 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 560, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 560 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 560 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 560 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 561 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 561 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 561 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 562 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 562 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 562 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 563 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 563 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 563 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 564 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 564 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 564 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 565 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 565 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 565 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 566 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 566 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 566 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 567 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 567 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 567 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 568, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 568 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 568 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 568 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 569 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 569 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 569 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 570 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 570 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 570 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 571 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 571 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 571 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 572 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 572 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 572 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 573 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 573 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 573 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 574 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 574 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 574 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 575 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 575 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 575 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 576, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 576 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 576 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 576 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 577 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 577 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 577 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 578 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 578 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 578 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 579 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 579 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 579 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 580 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 580 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 580 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 581 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 581 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 581 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 582 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 582 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 582 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 583 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 583 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 583 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 584, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 584 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 584 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 584 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 585 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 585 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 585 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 586 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 586 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 586 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 587 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 587 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 587 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 588 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 588 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 588 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 589 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 589 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 589 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 590 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 590 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 590 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 591 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 591 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 591 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 592, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 592 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 592 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 592 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 593 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 593 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 593 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 594 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 594 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 594 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 595 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 595 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 595 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 596 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 596 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 596 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 597 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 597 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 597 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 598 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 598 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 598 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 599 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 599 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 599 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 600, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 600 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 600 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 600 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 601 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 601 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 601 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 602 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 602 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 602 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 603 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 603 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 603 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 604 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 604 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 604 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 605 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 605 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 605 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 606 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 606 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 606 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 607 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 607 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 607 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 608, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 608 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 608 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 608 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 609 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 609 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 609 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 610 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 610 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 610 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 611 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 611 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 611 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 612 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 612 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 612 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 613 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 613 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 613 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 614 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 614 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 614 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 615 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 615 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 615 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 616, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 616 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 616 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 616 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 617 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 617 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 617 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 618 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 618 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 618 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 619 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 619 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 619 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 620 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 620 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 620 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 621 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 621 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 621 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 622 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 622 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 622 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 623 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 623 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 623 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 624, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 624 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 624 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 624 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 625 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 625 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 625 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 626 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 626 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 626 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 627 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 627 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 627 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 628 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 628 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 628 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 629 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 629 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 629 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 630 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 630 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 630 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 631 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 631 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 631 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 632, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 632 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 632 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 632 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 633 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 633 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 633 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 634 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 634 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 634 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 635 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 635 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 635 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 636 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 636 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 636 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 637 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 637 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 637 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 638 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 638 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 638 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 639 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 639 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 639 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 640, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 640 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 640 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 640 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 641 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 641 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 641 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 642 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 642 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 642 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 643 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 643 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 643 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 644 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 644 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 644 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 645 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 645 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 645 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 646 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 646 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 646 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 647 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 647 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 647 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 648, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 648 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 648 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 648 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 649 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 649 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 649 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 650 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 650 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 650 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 651 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 651 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 651 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 652 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 652 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 652 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 653 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 653 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 653 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 654 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 654 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 654 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 655 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 655 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 655 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 656, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 656 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 656 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 656 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 657 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 657 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 657 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 658 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 658 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 658 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 659 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 659 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 659 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 660 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 660 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 660 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 661 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 661 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 661 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 662 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 662 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 662 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 663 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 663 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 663 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 664, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 664 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 664 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 664 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 665 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 665 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 665 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 666 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 666 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 666 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 667 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 667 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 667 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 668 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 668 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 668 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 669 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 669 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 669 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 670 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 670 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 670 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 671 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 671 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 671 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 672, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 672 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 672 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 672 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 673 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 673 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 673 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 674 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 674 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 674 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 675 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 675 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 675 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 676 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 676 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 676 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 677 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 677 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 677 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 678 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 678 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 678 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 679 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 679 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 679 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 680, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 680 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 680 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 680 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 681 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 681 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 681 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 682 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 682 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 682 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 683 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 683 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 683 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 684 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 684 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 684 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 685 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 685 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 685 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 686 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 686 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 686 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 687 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 687 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 687 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 688, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 688 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 688 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 688 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 689 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 689 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 689 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 690 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 690 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 690 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 691 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 691 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 691 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 692 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 692 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 692 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 693 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 693 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 693 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 694 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 694 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 694 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 695 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 695 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 695 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 696, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 696 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 696 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 696 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 697 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 697 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 697 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 698 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 698 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 698 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 699 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 699 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 699 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 700 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 700 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 700 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 701 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 701 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 701 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 702 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 702 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 702 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 703 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 703 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 703 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 704, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 704 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 704 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 704 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 705 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 705 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 705 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 706 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 706 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 706 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 707 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 707 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 707 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 708 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 708 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 708 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 709 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 709 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 709 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 710 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 710 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 710 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 711 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 711 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 711 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 712, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 712 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 712 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 712 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 713 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 713 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 713 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 714 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 714 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 714 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 715 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 715 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 715 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 716 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 716 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 716 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 717 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 717 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 717 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 718 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 718 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 718 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 719 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 719 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 719 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 720, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 720 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 720 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 720 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 721 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 721 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 721 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 722 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 722 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 722 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 723 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 723 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 723 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 724 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 724 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 724 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 725 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 725 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 725 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 726 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 726 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 726 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 727 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 727 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 727 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 728, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 728 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 728 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 728 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 729 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 729 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 729 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 730 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 730 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 730 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 731 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 731 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 731 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 732 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 732 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 732 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 733 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 733 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 733 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 734 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 734 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 734 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 735 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 735 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 735 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 736, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 736 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 736 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 736 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 737 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 737 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 737 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 738 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 738 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 738 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 739 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 739 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 739 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 740 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 740 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 740 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 741 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 741 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 741 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 742 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 742 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 742 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 743 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 743 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 743 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 744, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 744 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 744 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 744 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 745 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 745 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 745 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 746 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 746 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 746 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 747 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 747 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 747 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 748 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 748 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 748 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 749 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 749 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 749 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 750 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 750 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 750 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 751 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 751 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 751 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 752, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 752 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 752 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 752 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 753 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 753 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 753 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 754 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 754 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 754 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 755 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 755 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 755 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 756 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 756 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 756 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 757 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 757 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 757 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 758 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 758 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 758 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 759 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 759 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 759 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 760, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 760 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 760 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 760 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 761 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 761 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 761 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 762 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 762 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 762 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 763 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 763 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 763 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 764 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 764 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 764 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 765 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 765 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 765 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 766 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 766 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 766 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 767 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 767 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 767 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 768, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 768 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 768 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 768 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 769 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 770 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 770 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 770 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 771 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 771 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 771 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 772 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 772 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 772 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 773 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 773 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 773 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 774 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 774 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 774 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 775 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 775 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 775 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 776, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 776 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 776 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 776 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 777 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 777 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 777 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 778 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 778 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 778 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 779 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 779 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 779 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 780 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 780 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 780 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 781 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 781 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 781 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 782 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 782 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 782 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 783 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 783 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 783 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 784, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 784 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 784 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 784 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 785 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 785 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 785 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 786 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 786 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 786 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 787 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 787 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 787 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 788 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 788 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 788 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 789 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 789 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 789 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 790 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 790 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 790 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 791 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 791 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 791 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 792, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 792 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 792 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 792 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 793 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 793 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 793 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 794 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 794 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 794 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 795 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 795 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 795 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 796 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 796 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 796 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 797 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 797 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 797 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 798 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 798 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 798 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 799 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 799 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 799 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 800, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 800 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 800 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 800 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 801 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 801 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 801 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 802 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 802 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 802 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 803 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 803 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 803 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 804 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 804 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 804 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 805 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 805 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 805 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 806 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 806 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 806 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 807 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 808, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 808 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 808 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 808 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 809 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 809 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 809 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 810 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 810 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 810 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 811 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 811 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 811 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 812 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 812 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 812 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 813 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 813 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 813 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 814 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 814 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 814 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 815 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 815 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 815 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 816, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 816 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 816 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 816 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 817 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 817 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 817 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 818 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 818 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 818 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 819 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 819 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 819 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 820 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 820 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 820 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 821 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 821 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 821 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 822 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 822 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 822 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 823 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 823 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 823 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 824, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 824 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 824 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 824 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 825 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 825 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 825 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 826 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 826 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 826 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 827 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 827 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 827 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 828 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 828 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 828 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 829 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 829 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 829 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 830 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 830 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 830 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 831 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 831 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 831 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 832, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 832 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 832 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 832 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 833 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 833 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 833 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 834 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 834 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 834 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 835 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 835 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 835 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 836 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 836 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 836 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 837 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 837 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 837 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 838 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 838 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 838 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 839 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 839 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 839 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 840, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 840 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 840 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 840 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 841 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 841 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 841 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 842 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 842 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 842 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 843 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 843 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 843 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 844 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 844 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 844 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 845 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 845 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 845 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 846 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 846 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 846 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 847 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 847 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 847 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 848, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 848 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 848 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 848 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 849 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 849 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 849 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 850 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 850 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 850 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 851 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 851 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 851 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 852 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 852 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 852 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 853 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 853 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 853 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 854 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 854 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 854 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 855 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 855 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 855 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 856, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 856 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 856 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 856 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 857 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 857 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 857 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 858 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 858 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 858 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 859 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 859 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 859 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 860 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 860 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 860 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 861 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 861 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 861 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 862 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 862 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 862 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 863 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 863 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 863 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 864, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 864 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 864 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 864 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 865 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 865 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 865 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 866 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 866 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 866 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 867 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 867 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 867 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 868 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 868 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 868 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 869 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 869 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 869 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 870 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 870 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 870 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 871 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 871 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 871 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 872, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 872 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 872 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 872 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 873 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 873 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 873 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 874 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 874 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 874 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 875 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 875 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 875 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 876 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 876 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 876 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 877 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 877 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 877 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 878 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 878 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 878 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 879 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 879 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 879 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 880, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 880 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 880 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 880 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 881 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 881 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 881 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 882 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 882 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 882 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 883 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 883 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 883 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 884 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 884 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 884 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 885 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 885 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 885 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 886 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 886 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 886 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 887 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 887 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 887 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 888, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 888 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 888 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 888 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 889 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 889 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 889 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 890 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 890 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 890 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 891 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 891 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 891 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 892 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 892 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 892 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 893 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 893 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 893 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 894 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 894 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 894 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 895 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 895 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 895 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 896, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 896 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 896 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 896 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 897 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 897 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 897 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 898 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 898 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 898 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 899 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 899 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 899 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 900 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 900 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 900 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 901 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 901 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 901 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 902 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 902 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 902 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 903 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 903 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 903 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 904, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 904 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 904 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 904 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 905 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 905 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 905 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 906 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 906 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 906 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 907 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 907 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 907 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 908 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 908 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 908 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 909 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 909 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 909 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 910 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 910 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 910 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 911 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 911 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 911 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 912, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 912 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 912 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 912 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 913 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 913 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 913 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 914 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 914 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 914 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 915 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 915 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 915 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 916 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 916 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 916 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 917 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 917 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 917 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 918 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 918 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 918 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 919 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 919 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 919 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 920, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 920 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 920 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 920 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 921 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 921 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 921 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 922 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 922 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 922 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 923 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 923 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 923 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 924 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 924 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 924 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 925 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 925 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 925 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 926 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 926 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 926 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 927 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 927 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 927 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 928, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 928 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 928 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 928 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 929 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 929 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 929 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 930 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 930 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 930 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 931 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 931 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 931 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 932 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 932 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 932 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 933 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 933 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 933 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 934 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 934 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 934 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 935 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 935 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 935 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 936, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 936 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 937 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 937 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 937 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 938 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 938 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 938 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 939 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 939 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 939 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 940 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 940 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 940 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 941 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 941 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 941 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 942 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 942 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 942 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 943 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 943 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 943 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 944, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 944 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 944 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 944 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 945 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 945 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 945 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 946 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 946 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 946 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 947 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 947 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 947 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 948 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 948 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 948 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 949 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 949 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 949 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 950 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 950 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 950 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 951 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 951 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 951 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 952, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 952 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 952 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 952 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 953 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 953 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 953 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 954 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 954 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 954 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 955 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 955 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 955 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 956 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 956 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 956 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 957 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 957 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 957 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 958 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 958 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 958 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 959 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 959 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 959 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 960, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 960 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 960 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 960 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 961 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 961 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 961 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 962 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 962 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 962 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 963 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 963 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 963 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 964 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 964 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 964 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 965 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 965 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 965 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 966 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 966 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 966 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 967 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 967 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 967 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 968, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 968 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 968 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 968 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 969 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 969 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 969 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 970 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 970 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 970 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 971 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 971 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 971 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 972 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 972 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 972 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 973 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 973 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 973 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 974 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 974 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 974 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 975 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 975 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 975 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 976, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 976 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 976 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 976 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 977 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 977 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 977 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 978 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 978 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 978 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 979 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 979 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 979 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 980 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 980 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 980 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 981 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 981 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 981 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 982 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 982 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 982 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 983 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 983 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 983 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 984, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 984 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 984 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 984 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 985 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 985 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 985 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 986 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 986 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 986 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 987 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 987 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 987 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 988 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 988 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 988 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 989 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 989 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 989 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 990 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 990 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 990 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 991 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 991 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 991 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 992, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 992 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 992 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 992 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 993 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 993 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 993 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 994 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 994 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 994 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 995 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 995 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 995 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 996 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 996 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 996 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 997 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 997 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 997 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 998 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 998 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 998 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 999 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 999 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 999 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 1000, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1000 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1000 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1000 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1001 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1001 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1001 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1002 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1002 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1002 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1003 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1003 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1003 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1004 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1005 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1005 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1005 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1006 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1006 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1006 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1007 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1007 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1007 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 1008, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1008 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1008 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1008 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1009 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1009 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1009 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1010 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1010 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1010 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1011 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1011 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1011 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1012 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1012 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1012 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1013 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1013 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1013 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1014 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1014 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1014 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1015 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1015 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1015 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 1016, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1016 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1016 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1016 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1017 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1017 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1017 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1018 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1018 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1018 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1019 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1019 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1019 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1020 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1020 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1020 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1021 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1021 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1021 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1022 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1022 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1022 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1023 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1023 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1023 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 0, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 0 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 0 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 0 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 0 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 2 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 2 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 2 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 3 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 3 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 3 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 4 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 4 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 4 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 5 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 5 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 5 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 6 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 6 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 6 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 7 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 7 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 7 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 8 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 8 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 8 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 9 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 10 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 10 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 10 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 11 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 11 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 11 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 12 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 12 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 12 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 13 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 13 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 13 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 14 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 14 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 14 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 15 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 15 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 15 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 16 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 16 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 16 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 17 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 17 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 17 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 18 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 18 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 18 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 19 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 19 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 19 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 20 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 20 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 20 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 21 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 21 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 21 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 22 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 22 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 22 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 23 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 23 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 23 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 24 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 24 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 24 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 25 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 25 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 25 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 26 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 26 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 26 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 27 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 27 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 27 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 28 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 28 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 28 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 29 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 29 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 29 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 30 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 30 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 30 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 31 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 31 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 31 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 32 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 32 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 32 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 33 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 33 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 33 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 34 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 34 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 34 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 35 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 35 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 35 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 36 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 36 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 36 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 37 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 37 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 37 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 38 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 38 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 38 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 39 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 39 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 39 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 40 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 40 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 40 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 41 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 41 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 41 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 42 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 42 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 42 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 43 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 43 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 43 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 44 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 44 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 44 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 45 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 45 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 45 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 46 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 46 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 46 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 47 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 47 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 47 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 48 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 48 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 48 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 49 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 49 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 49 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 50 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 50 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 50 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 51 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 51 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 51 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 52 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 52 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 52 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 53 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 53 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 53 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 54 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 54 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 54 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 55 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 55 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 55 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 56 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 56 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 56 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 57 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 57 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 57 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 58 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 58 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 58 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 59 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 59 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 59 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 60 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 60 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 60 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 61 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 61 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 61 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 62 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 62 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 62 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 63 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 63 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 63 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 64 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 64 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 64 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 65 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 65 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 65 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 66 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 66 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 66 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 67 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 67 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 67 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 68 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 68 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 68 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 69 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 69 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 69 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 70 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 70 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 70 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 71 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 71 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 71 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 72 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 72 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 72 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 73 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 73 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 73 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 74 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 74 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 74 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 75 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 75 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 75 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 76 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 76 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 76 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 77 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 77 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 77 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 78 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 78 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 78 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 79 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 79 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 79 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 80 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 80 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 80 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 81 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 81 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 81 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 82 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 82 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 82 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 83 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 83 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 83 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 84 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 84 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 84 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 85 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 85 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 85 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 86 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 86 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 86 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 87 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 87 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 87 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 88 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 88 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 88 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 89 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 89 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 89 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 90 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 90 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 90 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 91 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 91 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 91 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 92 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 92 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 92 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 93 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 93 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 93 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 94 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 94 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 94 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 95 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 95 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 95 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 96 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 96 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 96 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 97 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 97 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 97 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 98 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 98 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 98 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 99 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 99 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 99 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 100 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 100 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 100 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 101 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 101 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 101 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 102 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 102 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 102 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 103 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 103 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 103 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 104 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 104 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 104 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 105 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 105 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 105 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 106 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 106 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 106 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 107 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 107 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 107 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 108 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 108 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 108 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 109 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 109 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 109 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 110 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 110 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 110 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 111 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 111 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 111 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 112 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 112 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 112 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 113 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 113 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 113 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 114 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 114 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 114 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 115 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 115 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 115 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 116 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 116 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 116 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 117 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 117 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 117 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 118 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 118 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 118 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 119 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 119 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 119 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 120 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 120 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 120 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 121 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 121 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 121 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 122 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 123 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 123 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 123 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 124 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 124 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 124 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 125 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 125 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 125 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 126 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 126 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 126 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 127 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 127 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 127 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 128 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 128 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 128 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 129 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 129 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 129 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 130 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 130 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 130 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 131 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 131 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 131 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 132 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 132 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 132 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 133 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 133 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 133 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 134 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 134 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 134 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 135 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 135 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 135 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 136 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 136 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 136 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 137 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 137 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 137 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 138 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 138 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 138 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 139 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 139 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 139 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 140 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 140 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 140 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 141 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 141 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 141 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 142 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 142 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 142 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 143 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 143 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 143 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 144 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 144 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 144 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 145 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 145 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 145 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 146 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 146 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 146 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 147 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 147 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 147 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 148 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 148 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 148 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 149 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 149 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 149 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 150 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 150 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 150 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 151 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 151 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 151 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 152 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 152 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 152 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 153 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 153 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 153 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 154 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 154 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 154 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 155 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 155 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 155 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 156 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 156 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 156 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 157 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 157 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 157 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 158 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 158 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 158 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 159 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 159 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 159 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 160 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 160 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 160 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 161 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 161 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 161 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 162 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 162 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 162 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 163 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 163 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 163 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 164 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 164 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 164 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 165 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 165 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 165 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 166 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 166 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 166 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 167 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 167 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 167 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 168 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 168 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 168 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 169 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 169 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 169 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 170 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 170 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 170 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 171 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 171 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 171 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 172 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 172 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 172 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 173 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 173 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 173 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 174 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 174 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 174 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 175 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 175 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 175 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 176 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 177 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 177 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 177 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 178 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 178 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 178 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 179 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 179 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 179 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 180 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 180 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 180 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 181 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 181 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 181 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 182 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 182 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 182 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 183 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 183 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 183 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 184 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 184 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 184 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 185 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 185 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 185 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 186 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 186 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 186 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 187 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 187 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 187 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 188 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 188 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 188 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 189 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 189 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 189 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 190 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 190 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 190 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 191 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 191 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 191 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 192 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 192 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 192 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 193 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 193 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 193 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 194 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 194 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 194 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 195 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 195 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 195 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 196 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 196 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 196 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 197 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 197 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 197 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 198 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 198 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 198 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 199 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 199 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 199 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 200 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 200 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 200 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 201 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 201 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 201 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 202 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 202 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 202 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 203 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 203 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 203 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 204 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 204 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 204 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 205 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 205 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 205 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 206 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 206 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 206 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 207 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 207 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 207 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[SCTP] Found data for descriptor 87 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[SCTP] Received notification for sd 87, type 32773 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 3585 (null) +state 1 +nextstream 0 +in_streams 32 out_streams 32 +cnx_id 1 assoc_id 136 +--------------------------------------------- +[X2AP] x2ap_enb_data_p not NULL and sctp state not SCTP_STATE_ESTABLISHED, what to do? +Linux signal Aborted... +/home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/softmodem-common.c:187 signal_handler() Exiting OAI softmodem: softmodem starting exit procedure + +Exiting ru_thread diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h new file mode 100644 index 0000000000..9a6086998e --- /dev/null +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h @@ -0,0 +1,478 @@ + +h_element host_h_compact1_I0 [46*19] = +{{0 ,0,250},{1 ,0,2},{2 ,0,106},{3 ,0,121},{4 ,0,157},{5 ,0,205},{6 ,0,183},{7 ,0,220},{8 ,0,112},{9 ,0,103},{10 ,1,98},{11 ,0,77},{12 ,0,160},{13 ,0,177},{14 ,0,206},{15 ,0,40},{16 ,1,64},{17 ,0,7},{18 ,1,42},{19 ,0,60},{20 ,0,151},{21 ,1,249},{22 ,0,64},{23 ,1,156},{24 ,0,112},{25 ,1,23},{26 ,0,195},{27 ,1,25},{28 ,0,128},{29 ,1,86},{30 ,0,216},{31 ,1,95},{32 ,0,221},{33 ,1,2},{34 ,0,127},{35 ,1,161},{36 ,0,37},{37 ,1,198},{38 ,0,167},{39 ,1,173},{40 ,0,157},{41 ,1,167},{42 ,0,149},{43 ,1,151},{44 ,0,139},{45 ,1,149}, +{0 ,1,69},{1 ,2,239},{2 ,1,111},{3 ,1,89},{4 ,1,102},{5 ,1,236},{6 ,6,22},{7 ,1,44},{8 ,1,4},{9 ,1,182},{10 ,2,149},{11 ,1,41},{12 ,1,42},{13 ,3,248},{14 ,12,55},{15 ,1,96},{16 ,3,49},{17 ,14,164},{18 ,12,233},{19 ,1,73},{20 ,3,186},{21 ,5,121},{22 ,12,142},{23 ,2,147},{24 ,3,86},{25 ,6,136},{26 ,2,243},{27 ,6,104},{28 ,4,165},{29 ,14,236},{30 ,10,73},{31 ,7,177},{32 ,12,112},{33 ,2,187},{34 ,7,167},{35 ,6,197},{36 ,14,105},{37 ,13,220},{38 ,9,151},{39 ,3,139},{40 ,8,137},{41 ,3,173},{42 ,4,157},{43 ,16,163},{44 ,7,157},{45 ,6,151}, +{0 ,2,226},{1 ,3,117},{2 ,2,185},{3 ,3,84},{4 ,26,0},{5 ,3,194},{6 ,10,28},{7 ,4,159},{8 ,3,7},{9 ,10,109},{10 ,4,167},{11 ,12,83},{12 ,10,21},{13 ,7,151},{14 ,15,206},{15 ,10,65},{16 ,11,49},{17 ,16,59},{18 ,13,8},{19 ,7,72},{20 ,9,217},{21 ,16,109},{22 ,13,188},{23 ,10,170},{24 ,4,236},{25 ,7,116},{26 ,4,215},{27 ,8,194},{28 ,19,181},{29 ,18,84},{30 ,13,120},{31 ,22,172},{32 ,14,199},{33 ,11,41},{34 ,15,164},{35 ,12,207},{36 ,15,51},{37 ,23,122},{38 ,10,157},{39 ,7,149},{40 ,17,149},{41 ,9,139},{42 ,24,137},{43 ,18,173},{44 ,9,163},{45 ,10,167}, +{0 ,3,159},{1 ,4,124},{2 ,4,63},{3 ,4,20},{0 ,0,-1},{5 ,12,231},{6 ,11,67},{7 ,7,31},{8 ,12,211},{9 ,11,21},{10 ,7,160},{11 ,16,182},{12 ,11,32},{13 ,20,185},{14 ,16,127},{15 ,13,63},{16 ,20,51},{17 ,17,1},{18 ,18,155},{19 ,8,127},{20 ,11,47},{21 ,20,131},{22 ,17,158},{23 ,18,152},{24 ,11,116},{25 ,14,182},{26 ,15,61},{27 ,49,0},{28 ,21,63},{29 ,25,6},{30 ,24,9},{31 ,25,61},{32 ,24,121},{33 ,21,211},{34 ,17,159},{35 ,22,103},{36 ,18,120},{37 ,59,0},{38 ,12,163},{39 ,19,0},{40 ,62,0},{41 ,18,151},{42 ,64,0},{43 ,25,139},{44 ,22,173},{45 ,67,0}, +{0 ,5,100},{1 ,5,71},{2 ,5,117},{3 ,6,150},{0 ,0,-1},{5 ,16,28},{6 ,13,244},{7 ,8,167},{8 ,16,102},{9 ,13,142},{10 ,8,49},{11 ,21,78},{12 ,13,234},{13 ,23,62},{14 ,17,16},{15 ,18,75},{16 ,22,154},{17 ,21,144},{18 ,19,147},{19 ,10,224},{20 ,22,160},{21 ,21,171},{22 ,44,0},{23 ,45,0},{24 ,22,222},{25 ,47,0},{26 ,48,0},{0 ,0,-1},{28 ,50,0},{29 ,51,0},{30 ,52,0},{31 ,53,0},{32 ,54,0},{33 ,55,0},{34 ,56,0},{35 ,57,0},{36 ,58,0},{0 ,0,-1},{38 ,60,0},{39 ,61,0},{0 ,0,-1},{41 ,63,0},{0 ,0,-1},{43 ,65,0},{44 ,66,0},{0 ,0,-1}, +{0 ,6,10},{1 ,7,222},{2 ,6,93},{3 ,7,131},{0 ,0,-1},{5 ,21,123},{6 ,17,11},{7 ,14,104},{8 ,19,164},{9 ,17,14},{10 ,14,58},{11 ,22,252},{12 ,18,7},{13 ,35,0},{14 ,21,229},{15 ,25,179},{16 ,38,0},{17 ,39,0},{18 ,40,0},{19 ,41,0},{20 ,42,0},{21 ,43,0},{0 ,0,-1},{0 ,0,-1},{24 ,46,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,9,59},{1 ,8,104},{2 ,7,229},{3 ,8,243},{0 ,0,-1},{5 ,22,115},{6 ,18,157},{7 ,29,0},{8 ,21,109},{9 ,18,61},{10 ,32,0},{11 ,23,22},{12 ,34,0},{0 ,0,-1},{14 ,36,0},{15 ,37,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,10,229},{1 ,9,173},{2 ,8,177},{3 ,10,136},{0 ,0,-1},{5 ,27,0},{6 ,20,211},{0 ,0,-1},{8 ,22,241},{9 ,20,216},{0 ,0,-1},{11 ,33,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 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,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,13,9},{1 ,14,109},{2 ,13,142},{3 ,13,219},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,15,195},{1 ,15,132},{2 ,14,225},{3 ,14,211},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,16,23},{1 ,16,142},{2 ,15,225},{3 ,16,240},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,18,190},{1 ,17,155},{2 ,17,245},{3 ,17,76},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,19,35},{1 ,19,255},{2 ,18,205},{3 ,18,244},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,20,239},{1 ,21,28},{2 ,19,251},{3 ,20,144},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}, +{0 ,21,31},{1 ,22,0},{2 ,20,117},{3 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See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file PHY/NR_TRANSPORT/nr_dci_tools_common.c + * \brief + * \author + * \date 2018 + * \version 0.1 + * \company Eurecom + * \email: + * \note + * \warning + */ + +#include "nr_dci.h" + +//#define DEBUG_FILL_DCI + +#include "nr_dlsch.h" + + +void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) { + + uint8_t count=0, start=0, start_set=0; + + uint64_t bitmap = (((uint64_t)FreqDomainResource[0])<<37)| + (((uint64_t)FreqDomainResource[1])<<29)| + (((uint64_t)FreqDomainResource[2])<<21)| + (((uint64_t)FreqDomainResource[3])<<13)| + (((uint64_t)FreqDomainResource[4])<<5)| + (((uint64_t)FreqDomainResource[5])>>3); + + for (int i=0; i<45; i++) + if ((bitmap>>(44-i))&1) { + count++; + if (!start_set) { + start = i; + start_set = 1; + } + } + *rb_offset = 6*start; + *n_rb = 6*count; +} + diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c new file mode 100644 index 0000000000..bfb9150868 --- /dev/null +++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c @@ -0,0 +1,348 @@ +int oai_nfapi_hi_dci0_req(nfapi_hi_dci0_request_t *hi_dci0_req) { return(0); } +int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) { return(0); } +int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return(0); } +int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } +//int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); } +int32_t get_uldl_offset(int nr_bandP) { return(0); } +NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);} +int dummy_nr_ue_dl_indication(nr_downlink_indication_t *dl_info) { return(0); } +int dummy_nr_ue_ul_indication(nr_uplink_indication_t *ul_info) { return(0); } +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file ra_procedures.c + * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15) + * \author R. Knopp, Navid Nikaein, Guido Casati + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de + * \note + * \warning + */ + + +/* +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "PHY_INTERFACE/phy_interface_extern.h" +#include "SCHED_UE/sched_UE.h" +#include "COMMON/mac_rrc_primitives.h" +#include "RRC/LTE/rrc_extern.h" +#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h" +#include "common/utils/LOG/log.h" +#include "UTIL/OPT/opt.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/ + +/* Tools */ +#include "SIMULATION/TOOLS/sim.h" // for taus + +/* RRC */ +#include "NR_RACH-ConfigCommon.h" + +/* PHY */ +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include "PHY/defs_common.h" +#include "PHY/defs_nr_common.h" +#include "PHY/NR_UE_ESTIMATION/nr_estimation.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" +#include "LAYER2/MAC/mac.h" + +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; + +//extern uint8_t nfapi_mode; + +// WIP +// This routine implements Section 5.1.2 (UE Random Access Resource Selection) +// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo + + int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0; + uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; + + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo + + /////////////////////////////////////////////////////////// + //////////* UE Random Access Resource Selection *////////// + /////////////////////////////////////////////////////////// + + // todo: + // - switch initialisation cases + // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + // --- SSB selection, set prach_resources->ra_PreambleIndex + // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 + // --- set PREAMBLE_INDEX to ra_preamble_index + // --- select the SSB signalled by PDCCH + // -- RA initiated for SI request: + // --- SSB selection, set prach_resources->ra_PreambleIndex + + // if (rach_ConfigDedicated) { // This is for network controlled Mobility + // // operation for contention-free RA resources when: + // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; + // return; + // } + + //////////* Contention-based RA preamble selection *////////// + // todo: + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion + + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; + + AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + + nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + + Msg3_size = mac->RA_Msg3_size; + numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; + } else { + // RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* todo cases 10 -15*/ + } + + /* Power offset for preamble selection in dB */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; + } + + PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + mac->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { + // Group B is configured and RA preamble Group A is used + // - todo add condition on CCCH_sdu_size for initiation by CCCH + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + mac->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + mac->RA_usedGroupA = 0; + } + } else { // Msg3 is being retransmitted + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + } + } + + // todo determine next available PRACH occasion + // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured + // - else if SSB is selected above + // - else if CSI-RS is selected above + + ///////////////////////////////////////////////////////////////////////////// + //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// + ///////////////////////////////////////////////////////////////////////////// + // todo: + // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) + // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) + + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) + mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; + + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); + + // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) + // 1) this does not apply to contention-free RA Preamble for beam failure recovery request + // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) + + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used + case 0: + msg1_FDM = 1; + break; + case 1: + msg1_FDM = 2; + break; + case 2: + msg1_FDM = 4; + break; + case 3: + msg1_FDM = 8; + break; + default: + AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); + } + + prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + + // ra_RNTI computation + // - todo: this is for TDD FR1 only + // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier + // - f_id: index of the PRACH occasion in the frequency domain + // - s_id is starting symbol of the PRACH occasion [0...14] + // - t_id is the first slot of the PRACH occasion in a system frame [0...80] + + ul_carrier_id = 0; // NUL + f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; + SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; + s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; + + // Pick the first slot of the PRACH occasion in a system frame + for (i = 0; i < 10; i++){ + if (((SFN_nbr & (1 << i)) >> i) == 1){ + t_id = 2*i; + break; + } + } + prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; + mac->ra_rnti = prach_resources->ra_RNTI; + + LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); +} + +// TbD: RA_attempt_number not used +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + mac->ra_state = WAIT_RAR; + // Start contention resolution timer + mac->RA_attempt_number++; +} + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + // start contention resolution timer + mac->RA_contention_resolution_cnt = 0; + mac->RA_contention_resolution_timer_active = 1; +} + +///////////////////////////////////////////////////////////////////////// +///////* Random Access Preamble Initialization (5.1.1 TS 38.321) */////// +///////////////////////////////////////////////////////////////////////// +/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) +/// Only one RA procedure is ongoing at any point in time in a MAC entity +/// the RA procedure on a SCell shall only be initiated by PDCCH order + +// WIP +// todo TS 38.321: +// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX +// - BWP operation (subclause 5.15 TS 38.321) +// - handle initialization by beam failure recovery +// - handle initialization by handover +// - handle transmission on DCCH using PRACH (during handover, or sending SR for example) +// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader) +// - fix rrc data req logic +// - retrieve TBS +// - add mac_rrc_nr_data_req_ue, etc ... +// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + + diff --git a/openair2/LAYER2/MAC/slicing/slicing.c b/openair2/LAYER2/MAC/slicing/slicing.c new file mode 100644 index 0000000000..9c88f6cffb --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing.c @@ -0,0 +1,601 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing.c + * \brief Generic slicing helper functions and Static Slicing Implementation + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#define _GNU_SOURCE +#include +#include + +#include "assertions.h" +#include "common/utils/LOG/log.h" + +#include "slicing.h" +#include "slicing_internal.h" + +#include "common/ran_context.h" +extern RAN_CONTEXT_t RC; + +#define RET_FAIL(ret, x...) do { LOG_E(MAC, x); return ret; } while (0) + +int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id) { + return si->UE_assoc_slice[UE_id]; +} + +void slicing_add_UE(slice_info_t *si, int UE_id) { + add_ue_list(&si->s[0]->UEs, UE_id); + si->UE_assoc_slice[UE_id] = 0; +} + +void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id) { + const uint8_t i = assoc[UE_id]; + DevAssert(remove_ue_list(&s[i]->UEs, UE_id)); + assoc[UE_id] = -1; +} + +void slicing_remove_UE(slice_info_t *si, int UE_id) { + _remove_UE(si->s, si->UE_assoc_slice, UE_id); +} + +void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to) { + const uint8_t i = assoc[UE_id]; + const int ri = remove_ue_list(&s[i]->UEs, UE_id); + if (!ri) + LOG_W(MAC, "did not find UE %d in DL slice index %d\n", UE_id, i); + add_ue_list(&s[to]->UEs, UE_id); + assoc[UE_id] = to; +} + +void slicing_move_UE(slice_info_t *si, int UE_id, int idx) { + DevAssert(idx >= -1 && idx < si->num); + if (idx >= 0) + _move_UE(si->s, si->UE_assoc_slice, UE_id, idx); +} + +int _exists_slice(uint8_t n, slice_t **s, int id) { + for (int i = 0; i < n; ++i) + if (s[i]->id == id) + return i; + return -1; +} + +slice_t *_add_slice(uint8_t *n, slice_t **s) { + s[*n] = calloc(1, sizeof(slice_t)); + if (!s[*n]) + return NULL; + init_ue_list(&s[*n]->UEs); + *n += 1; + return s[*n - 1]; +} + +slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx) { + if (idx >= *n) + return NULL; + + slice_t *sr = s[idx]; + while (sr->UEs.head >= 0) + _move_UE(s, assoc, sr->UEs.head, 0); + + for (int i = idx + 1; i < *n; ++i) + s[i - 1] = s[i]; + *n -= 1; + s[*n] = NULL; + + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + if (assoc[i] > idx) + assoc[i] -= 1; + + if (sr->label) + free(sr->label); + + return sr; +} + +/************************ Static Slicing Implementation ************************/ + +int addmod_static_slice_dl(slice_info_t *si, + int id, + char *label, + void *algo, + void *slice_params_dl) { + static_slice_param_t *dl = slice_params_dl; + if (dl && dl->posLow > dl->posHigh) + RET_FAIL(-1, "%s(): slice id %d posLow > posHigh\n", __func__, id); + + uint8_t rbgMap[25] = { 0 }; + int index = _exists_slice(si->num, si->s, id); + if (index >= 0) { + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = dl && si->s[s]->id == id ? dl : si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) { + if (rbgMap[i]) + RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + rbgMap[i] = 1; + } + } + /* no problem, can allocate */ + slice_t *s = si->s[index]; + if (label) { + if (s->label) free(s->label); + s->label = label; + } + if (algo) { + s->dl_algo.unset(&s->dl_algo.data); + s->dl_algo = *(default_sched_dl_algo_t *) algo; + if (!s->dl_algo.data) + s->dl_algo.data = s->dl_algo.setup(); + } + if (dl) { + free(s->algo_data); + s->algo_data = dl; + } + return index; + } + + if (!dl) + RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id); + + if (si->num >= MAX_STATIC_SLICES) + RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES); + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) + rbgMap[i] = 1; + } + + for (int i = dl->posLow; i <= dl->posHigh; ++i) + if (rbgMap[i]) + RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + + if (!algo) + RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__); + + slice_t *ns = _add_slice(&si->num, si->s); + if (!ns) + RET_FAIL(-4, "%s(): could not create new slice\n", __func__); + ns->id = id; + ns->label = label; + ns->dl_algo = *(default_sched_dl_algo_t *) algo; + if (!ns->dl_algo.data) + ns->dl_algo.data = ns->dl_algo.setup(); + ns->algo_data = dl; + + return si->num - 1; +} + +int addmod_static_slice_ul(slice_info_t *si, + int id, + char *label, + void *algo, + void *slice_params_ul) { + static_slice_param_t *ul = slice_params_ul; + /* Minimum 3RBs, because LTE stack requires this */ + if (ul && ul->posLow + 2 > ul->posHigh) + RET_FAIL(-1, "%s(): slice id %d posLow + 2 > posHigh\n", __func__, id); + + uint8_t rbMap[110] = { 0 }; + int index = _exists_slice(si->num, si->s, id); + if (index >= 0) { + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *su = ul && si->s[s]->id == id && ul ? ul : si->s[s]->algo_data; + for (int i = su->posLow; i <= su->posHigh; ++i) { + if (rbMap[i]) + RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + rbMap[i] = 1; + } + } + /* no problem, can allocate */ + slice_t *s = si->s[index]; + if (algo) { + s->ul_algo.unset(&s->ul_algo.data); + s->ul_algo = *(default_sched_ul_algo_t *) algo; + if (!s->ul_algo.data) + s->ul_algo.data = s->ul_algo.setup(); + } + if (label) { + if (s->label) free(s->label); + s->label = label; + } + if (ul) { + free(s->algo_data); + s->algo_data = ul; + } + return index; + } + + if (!ul) + RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id); + + if (si->num >= MAX_STATIC_SLICES) + RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES); + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) + rbMap[i] = 1; + } + + for (int i = ul->posLow; i <= ul->posHigh; ++i) + if (rbMap[i]) + RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + + if (!algo) + RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__); + + slice_t *ns = _add_slice(&si->num, si->s); + if (!ns) + RET_FAIL(-4, "%s(): could not create new slice\n", __func__); + ns->id = id; + ns->label = label; + ns->ul_algo = *(default_sched_ul_algo_t *) algo; + if (!ns->ul_algo.data) + ns->ul_algo.data = ns->ul_algo.setup(); + ns->algo_data = ul; + + return si->num - 1; +} + +int remove_static_slice_dl(slice_info_t *si, uint8_t slice_idx) { + if (slice_idx == 0) + return 0; + slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); + if (!sr) + return 0; + free(sr->algo_data); + sr->dl_algo.unset(&sr->dl_algo.data); + free(sr); + return 1; +} + +int remove_static_slice_ul(slice_info_t *si, uint8_t slice_idx) { + if (slice_idx == 0) + return 0; + slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); + if (!sr) + return 0; + free(sr->algo_data); + sr->ul_algo.unset(&sr->ul_algo.data); + free(sr); + return 1; +} + +void static_dl(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe) { + UE_info_t *UE_info = &RC.mac[mod_id]->UE_info; + + store_dlsch_buffer(mod_id, CC_id, frame, subframe); + + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + /* initialize per-UE scheduling information */ + ue_sched_ctrl->pre_nb_available_rbs[CC_id] = 0; + ue_sched_ctrl->dl_pow_off[CC_id] = 2; + memset(ue_sched_ctrl->rballoc_sub_UE[CC_id], 0, sizeof(ue_sched_ctrl->rballoc_sub_UE[CC_id])); + ue_sched_ctrl->pre_dci_dl_pdu_idx = -1; + } + + const int N_RBG = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(mod_id, CC_id); + uint8_t *vrb_map = RC.mac[mod_id]->common_channels[CC_id].vrb_map; + uint8_t rbgalloc_mask[N_RBG_MAX]; + for (int i = 0; i < N_RBG; i++) { + // calculate mask: init to one + "AND" with vrb_map: + // if any RB in vrb_map is blocked (1), the current RBG will be 0 + rbgalloc_mask[i] = 1; + for (int j = 0; j < RBGsize; j++) + rbgalloc_mask[i] &= !vrb_map[RBGsize * i + j]; + } + + slice_info_t *s = RC.mac[mod_id]->pre_processor_dl.slices; + int max_num_ue; + switch (s->num) { + case 1: + max_num_ue = 4; + break; + case 2: + max_num_ue = 2; + break; + default: + max_num_ue = 1; + break; + } + for (int i = 0; i < s->num; ++i) { + if (s->s[i]->UEs.head < 0) + continue; + uint8_t rbgalloc_slice_mask[N_RBG_MAX]; + memset(rbgalloc_slice_mask, 0, sizeof(rbgalloc_slice_mask)); + static_slice_param_t *p = s->s[i]->algo_data; + int n_rbg_sched = 0; + for (int rbg = p->posLow; rbg <= p->posHigh && rbg <= N_RBG; ++rbg) { + rbgalloc_slice_mask[rbg] = rbgalloc_mask[rbg]; + n_rbg_sched += rbgalloc_mask[rbg]; + } + + s->s[i]->dl_algo.run(mod_id, + CC_id, + frame, + subframe, + &s->s[i]->UEs, + max_num_ue, // max_num_ue + n_rbg_sched, + rbgalloc_slice_mask, + s->s[i]->dl_algo.data); + } + + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality + char t[26] = "_________________________"; + t[N_RBG] = 0; + for (int i = 0; i < N_RBG; i++) + for (int j = 0; j < RBGsize; j++) + if (vrb_map[RBGsize*i+j] != 0) + t[i] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + const UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0) + continue; + + LOG_D(MAC, + "%4d.%d UE%d %d RBs allocated, pre MCS %d\n", + frame, + subframe, + UE_id, + ue_sched_ctrl->pre_nb_available_rbs[CC_id], + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1); + + print = 1; + + for (int i = 0; i < N_RBG; i++) { + if (!ue_sched_ctrl->rballoc_sub_UE[CC_id][i]) + continue; + for (int j = 0; j < RBGsize; j++) { + if (vrb_map[RBGsize*i+j] != 0) { + LOG_I(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t); + LOG_E(MAC, "%4d.%d: UE %d allocated at locked RB %d/RBG %d\n", frame, + subframe, UE_id, RBGsize * i + j, i); + } + vrb_map[RBGsize*i+j] = 1; + } + t[i] = '0' + UE_id; + } + } + if (print) + LOG_D(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t); +} + +void static_ul(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe, + frame_t sched_frame, + sub_frame_t sched_subframe) { + UE_info_t *UE_info = &RC.mac[mod_id]->UE_info; + const int N_RB_UL = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &RC.mac[mod_id]->common_channels[CC_id]; + + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_template->pre_assigned_mcs_ul = 0; + UE_template->pre_allocated_nb_rb_ul = 0; + UE_template->pre_allocated_rb_table_index_ul = -1; + UE_template->pre_first_nb_rb_ul = 0; + UE_template->pre_dci_ul_pdu_idx = -1; + } + + slice_info_t *s = RC.mac[mod_id]->pre_processor_ul.slices; + int max_num_ue; + switch (s->num) { + case 1: + max_num_ue = 4; + break; + case 2: + max_num_ue = 2; + break; + default: + max_num_ue = 1; + break; + } + for (int i = 0; i < s->num; ++i) { + if (s->s[i]->UEs.head < 0) + continue; + int last_rb_blocked = 1; + int n_contig = 0; + contig_rbs_t rbs[2]; // up to two contig RBs for PRACH in between + static_slice_param_t *p = s->s[i]->algo_data; + for (int rb = p->posLow; rb <= p->posHigh && rb < N_RB_UL; ++rb) { + if (cc->vrb_map_UL[rb] == 0 && last_rb_blocked) { + last_rb_blocked = 0; + n_contig++; + AssertFatal(n_contig <= 2, "cannot handle more than two contiguous RB regions\n"); + rbs[n_contig - 1].start = rb; + } + if (cc->vrb_map_UL[rb] == 1 && !last_rb_blocked) { + last_rb_blocked = 1; + rbs[n_contig - 1].length = rb - rbs[n_contig - 1].start; + } + } + if (!last_rb_blocked) + rbs[n_contig - 1].length = p->posHigh - rbs[n_contig - 1].start + 1; + + s->s[i]->ul_algo.run(mod_id, + CC_id, + frame, + subframe, + sched_frame, + sched_subframe, + &s->s[i]->UEs, + max_num_ue, // max_num_ue + n_contig, + rbs, + s->s[i]->ul_algo.data); + } + + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality + char t[101] = "__________________________________________________" + "__________________________________________________"; + t[N_RB_UL] = 0; + for (int j = 0; j < N_RB_UL; j++) + if (cc->vrb_map_UL[j] != 0) + t[j] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + if (UE_template->pre_allocated_nb_rb_ul == 0) + continue; + + print = 1; + uint8_t harq_pid = subframe2harqpid(&RC.mac[mod_id]->common_channels[CC_id], + sched_frame, sched_subframe); + LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", + frame, + subframe, + UE_id, + UE_template->pre_allocated_nb_rb_ul, + UE_template->pre_allocated_rb_table_index_ul, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_assigned_mcs_ul, + UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0 ? "(retx)" : ""); + + for (int i = 0; i < UE_template->pre_allocated_nb_rb_ul; ++i) { + /* only check if this is not a retransmission */ + if (UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] == 0 + && cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] == 1) { + + LOG_I(MAC, "%4d.%d UL scheduler allocation list: %s\n", frame, subframe, t); + LOG_E(MAC, + "%4d.%d: UE %d allocated at locked RB %d (is: allocated start " + "%d/length %d)\n", + frame, subframe, UE_id, UE_template->pre_first_nb_rb_ul + i, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_allocated_nb_rb_ul); + } + cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] = 1; + t[UE_template->pre_first_nb_rb_ul + i] = UE_id + '0'; + } + } + if (print) + LOG_D(MAC, + "%4d.%d UL scheduler allocation list: %s\n", + sched_frame, + sched_subframe, + t); +} + +void static_destroy(slice_info_t **si) { + const int n = (*si)->num; + (*si)->num = 0; + for (int i = 0; i < n; ++i) { + slice_t *s = (*si)->s[i]; + if (s->label) + free(s->label); + free(s->algo_data); + free(s); + } + free((*si)->s); + free(*si); +} + +pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { + slice_info_t *si = calloc(1, sizeof(slice_info_t)); + DevAssert(si); + + si->num = 0; + si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t)); + DevAssert(si->s); + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + si->UE_assoc_slice[i] = -1; + + /* insert default slice, all resources */ + static_slice_param_t *dlp = malloc(sizeof(static_slice_param_t)); + dlp->posLow = 0; + dlp->posHigh = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth) - 1; + default_sched_dl_algo_t *algo = &RC.mac[mod_id]->pre_processor_dl.dl_algo; + algo->data = NULL; + DevAssert(0 == addmod_static_slice_dl(si, 0, strdup("default"), algo, dlp)); + const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) + slicing_add_UE(si, UE_id); + + pp_impl_param_t sttc; + sttc.algorithm = STATIC_SLICING; + sttc.add_UE = slicing_add_UE; + sttc.remove_UE = slicing_remove_UE; + sttc.move_UE = slicing_move_UE; + sttc.addmod_slice = addmod_static_slice_dl; + sttc.remove_slice = remove_static_slice_dl; + sttc.dl = static_dl; + // current DL algo becomes default scheduler + sttc.dl_algo = *algo; + sttc.destroy = static_destroy; + sttc.slices = si; + + return sttc; +} + +pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { + slice_info_t *si = calloc(1, sizeof(slice_info_t)); + DevAssert(si); + + si->num = 0; + si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t)); + DevAssert(si->s); + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + si->UE_assoc_slice[i] = -1; + + /* insert default slice, all resources */ + static_slice_param_t *ulp = malloc(sizeof(static_slice_param_t)); + ulp->posLow = 0; + ulp->posHigh = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth) - 1; + default_sched_ul_algo_t *algo = &RC.mac[mod_id]->pre_processor_ul.ul_algo; + algo->data = NULL; + DevAssert(0 == addmod_static_slice_ul(si, 0, strdup("default"), algo, ulp)); + const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) + slicing_add_UE(si, UE_id); + + pp_impl_param_t sttc; + sttc.algorithm = STATIC_SLICING; + sttc.add_UE = slicing_add_UE; + sttc.remove_UE = slicing_remove_UE; + sttc.move_UE = slicing_move_UE; + sttc.addmod_slice = addmod_static_slice_ul; + sttc.remove_slice = remove_static_slice_ul; + sttc.ul = static_ul; + // current DL algo becomes default scheduler + sttc.ul_algo = *algo; + sttc.destroy = static_destroy; + sttc.slices = si; + + return sttc; +} diff --git a/openair2/LAYER2/MAC/slicing/slicing.h b/openair2/LAYER2/MAC/slicing/slicing.h new file mode 100644 index 0000000000..1099b50ea0 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing.h @@ -0,0 +1,74 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing.h + * \brief General slice definition and helper parameters + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#ifndef __SLICING_H__ +#define __SLICING_H__ + +#include "openair2/LAYER2/MAC/mac.h" + +typedef struct slice_s { + /// Arbitrary ID + slice_id_t id; + /// Arbitrary label + char *label; + + union { + default_sched_dl_algo_t dl_algo; + default_sched_ul_algo_t ul_algo; + }; + + /// A specific algorithm's implementation parameters + void *algo_data; + /// Internal data that might be kept alongside a slice's params + void *int_data; + + // list of users in this slice + UE_list_t UEs; +} slice_t; + +typedef struct slice_info_s { + uint8_t num; + slice_t **s; + uint8_t UE_assoc_slice[MAX_MOBILES_PER_ENB]; +} slice_info_t; + +int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id); + +#define STATIC_SLICING 10 +/* only four static slices for UL, DL resp. (not enough DCIs) */ +#define MAX_STATIC_SLICES 4 +typedef struct { + uint16_t posLow; + uint16_t posHigh; +} static_slice_param_t; +pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id); +pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id); + + +#endif /* __SLICING_H__ */ diff --git a/openair2/LAYER2/MAC/slicing/slicing_internal.h b/openair2/LAYER2/MAC/slicing/slicing_internal.h new file mode 100644 index 0000000000..744f8924d9 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing_internal.h @@ -0,0 +1,46 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing_internal.h + * \brief Internal slice helper functions + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#ifndef __SLICING_INTERNAL_H__ +#define __SLICING_INTERNAL_H__ + +#include "slicing.h" + +void slicing_add_UE(slice_info_t *si, int UE_id); + +void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id); +void slicing_remove_UE(slice_info_t *si, int UE_id); + +void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to); +void slicing_move_UE(slice_info_t *si, int UE_id, int idx); + +slice_t *_add_slice(uint8_t *n, slice_t **s); +slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx); + +#endif /* __SLICING_INTERNAL_H__ */ diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h new file mode 100644 index 0000000000..a5e38bf128 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -0,0 +1,120 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file mac.h +* \brief MAC data structures, constant, and function prototype +* \author Navid Nikaein and Raymond Knopp, WIE-TAI CHEN +* \date Dec. 2019 +* \version 0.1 +* \company Eurecom +* \email raymond.knopp@eurecom.fr + +*/ + +#ifndef __LAYER2_NR_MAC_COMMON_H__ +#define __LAYER2_NR_MAC_COMMON_H__ + +#include "NR_PDSCH-Config.h" +#include "NR_CellGroupConfig.h" +#include "nr_mac.h" + +typedef enum { + NR_DL_DCI_FORMAT_1_0 = 0, + NR_DL_DCI_FORMAT_1_1, + NR_DL_DCI_FORMAT_2_0, + NR_DL_DCI_FORMAT_2_1, + NR_DL_DCI_FORMAT_2_2, + NR_DL_DCI_FORMAT_2_3, + NR_UL_DCI_FORMAT_0_0, + NR_UL_DCI_FORMAT_0_1 +} nr_dci_format_t; + +typedef enum { + NR_RNTI_new = 0, + NR_RNTI_C, + NR_RNTI_RA, + NR_RNTI_P, + NR_RNTI_CS, + NR_RNTI_TC, + NR_RNTI_SP_CSI, + NR_RNTI_SI, + NR_RNTI_SFI, + NR_RNTI_INT, + NR_RNTI_TPC_PUSCH, + NR_RNTI_TPC_PUCCH, + NR_RNTI_TPC_SRS +} nr_rnti_type_t; + +uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); + +void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); + +uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); + +uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); + +int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols); + +int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); + +int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); + +uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu, + nr_dci_format_t format, + nr_rnti_type_t rnti_type, + uint16_t N_RB, + int bwp_id); + +void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, + uint16_t *slot_period, + uint16_t *offset); + +int get_nr_prach_info_from_index(uint8_t index, + int frame, + int slot, + uint32_t pointa, + uint8_t mu, + uint8_t unpaired, + uint16_t *format, + uint8_t *start_symbol, + uint8_t *N_t_slot, + uint8_t *N_dur); + +uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, + uint8_t nb_preambles, + uint8_t unpaired); + +int ul_ant_bits(NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig,long transformPrecoder); + +int get_format0(uint8_t index, uint8_t unpaired); + +uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config); + +int get_num_dmrs(uint16_t dmrs_mask ); +uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position); +int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength); + +uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table); +uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB); + +#endif diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c new file mode 100644 index 0000000000..f8bb1e5f8e --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -0,0 +1,153 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file nr_l1_helper.c +* \brief PHY helper functions for PRACH adapted to NR +* \author Guido Casati +* \date 2019 +* \version 2.0 +* \email guido.casati@iis.fraunhofer.de +* @ingroup _mac + +*/ + +#include "PHY/defs_nr_common.h" + +#include "mac_defs.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" + +/* TS 38.321 subclause 7.3 - return DELTA_PREAMBLE values in dB */ +int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_SubcarrierSpacing_t scs = *nr_rach_ConfigCommon->msg1_SubcarrierSpacing; + int prach_sequence_length = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present - 1; + uint8_t prachConfigIndex, mu; + + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + + // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 + + switch (scs){ + case NR_SubcarrierSpacing_kHz15: + mu = 0; + break; + + case NR_SubcarrierSpacing_kHz30: + mu = 1; + break; + + case NR_SubcarrierSpacing_kHz60: + mu = 2; + break; + + case NR_SubcarrierSpacing_kHz120: + mu = 3; + break; + + case NR_SubcarrierSpacing_kHz240: + mu = 4; + break; + + case NR_SubcarrierSpacing_spare3: + mu = 5; + break; + + case NR_SubcarrierSpacing_spare2: + mu = 6; + break; + + case NR_SubcarrierSpacing_spare1: + mu = 7; + break; + + default: + AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %lu\n", scs); + } + + // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211 + + prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + + if (prach_sequence_length == 0) { + AssertFatal(prach_format < 4, "Illegal PRACH format %d for sequence length 839\n", prach_format); + switch (prach_format) { + + // long preamble formats + case 0: + case 3: + return 0; + + case 1: + return -3; + + case 2: + return -6; + } + } else { + switch (prach_format) { // short preamble formats + case 0: + case 3: + return 8 + 3*mu; + + case 1: + case 4: + case 8: + return 5 + 3*mu; + + case 2: + case 5: + return 3 + 3*mu; + + case 6: + return 3*mu; + + case 7: + return 5 + 3*mu; + + default: + AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, prach_format, prachConfigIndex); + } + } + return 0; +} + +/* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ +int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, uint8_t CC_id){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + int8_t receivedTargerPower, delta_preamble; + long preambleReceivedTargetPower; + + AssertFatal(nr_rach_ConfigCommon != NULL, "[UE %d] CCid %d FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id, CC_id); + + preambleReceivedTargetPower = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower; + delta_preamble = nr_get_DELTA_PREAMBLE(mod_id, CC_id, prach_resources->prach_format); + + receivedTargerPower = preambleReceivedTargetPower + delta_preamble + (mac->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; + + return receivedTargerPower; +} diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c new file mode 100644 index 0000000000..56ae14f98b --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -0,0 +1,644 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file ra_procedures.c + * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15) + * \author R. Knopp, Navid Nikaein, Guido Casati + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de + * \note + * \warning + */ + +#include "mac.h" + +/* +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "PHY_INTERFACE/phy_interface_extern.h" +#include "SCHED_UE/sched_UE.h" +#include "COMMON/mac_rrc_primitives.h" +#include "RRC/LTE/rrc_extern.h" +#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h" +#include "common/utils/LOG/log.h" +#include "UTIL/OPT/opt.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/ + +/* Tools */ +#include "SIMULATION/TOOLS/sim.h" // for taus + +/* RRC */ +#include "NR_RACH-ConfigCommon.h" + +/* PHY */ +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include "PHY/defs_common.h" +#include "PHY/defs_nr_common.h" +#include "PHY/NR_UE_ESTIMATION/nr_estimation.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" + +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; +extern const uint16_t nr_slots_per_frame[5]; + +//extern uint8_t nfapi_mode; + +void nr_get_RA_window(NR_UE_MAC_INST_t *mac); + +// WIP +// This routine implements Section 5.1.2 (UE Random Access Resource Selection) +// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric; + + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo + + int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA = 0, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0; + uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size; + + AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; + + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo + + /////////////////////////////////////////////////////////// + //////////* UE Random Access Resource Selection *////////// + /////////////////////////////////////////////////////////// + + // todo: + // - switch initialisation cases + // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + // --- SSB selection, set prach_resources->ra_PreambleIndex + // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 + // --- set PREAMBLE_INDEX to ra_preamble_index + // --- select the SSB signalled by PDCCH + // -- RA initiated for SI request: + // --- SSB selection, set prach_resources->ra_PreambleIndex + + if (rach_ConfigDedicated) { + //////////* Contention free RA *////////// + // - the PRACH preamble for the UE to transmit is set through RRC configuration + // - this is the default mode in current implementation! + // Operation for contention-free RA resources when: + // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // - available CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // - network controlled Mobility + uint8_t cfra_ssb_resource_idx = 0; + prach_resources->ra_PreambleIndex = rach_ConfigDedicated->cfra->resources.choice.ssb->ssb_ResourceList.list.array[cfra_ssb_resource_idx]->ra_PreambleIndex; + LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-free random access procedure... \n", prach_resources->ra_PreambleIndex); + } else { + //////////* Contention-based RA preamble selection *////////// + // todo: + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion + + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; + + Msg3_size = mac->RA_Msg3_size; + + numberOfRA_Preambles = 64; + if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL) + numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles); + + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; + } else { + // RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* todo cases 10 -15*/ + } + + /* Power offset for preamble selection in dB */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; + } + + PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + mac->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { + // Group B is configured and RA preamble Group A is used + // - todo add condition on CCCH_sdu_size for initiation by CCCH + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + mac->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + mac->RA_usedGroupA = 0; + } + } else { // Msg3 is being retransmitted + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + } + } + LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-based random access procedure... \n", prach_resources->ra_PreambleIndex); + } + + // todo determine next available PRACH occasion + // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured + // - else if SSB is selected above + // - else if CSI-RS is selected above + + ///////////////////////////////////////////////////////////////////////////// + //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// + ///////////////////////////////////////////////////////////////////////////// + // todo: + // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) + // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) + + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) + mac->RA_PREAMBLE_POWER_RAMPING_COUNTER++; + + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); + + // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) + // 1) this does not apply to contention-free RA Preamble for beam failure recovery request + // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) + + prach_ConfigIndex = rach_ConfigGeneric->prach_ConfigurationIndex; + + // ra_RNTI computation + // - todo: this is for TDD FR1 only + // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier + // - f_id: index of the PRACH occasion in the frequency domain + // - s_id is starting symbol of the PRACH occasion [0...14] + // - t_id is the first slot of the PRACH occasion in a system frame [0...80] + + ul_carrier_id = 0; // NUL + f_id = rach_ConfigGeneric->msg1_FrequencyStart; + SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; + s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; + + // Pick the first slot of the PRACH occasion in a system frame + for (i = 0; i < 10; i++){ + if (((SFN_nbr & (1 << i)) >> i) == 1){ + t_id = 2*i; + break; + } + } + prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; + mac->ra_rnti = prach_resources->ra_RNTI; + + LOG_D(MAC, "Computed ra_RNTI is %x \n", prach_resources->ra_RNTI); +} + +// TbD: RA_attempt_number not used +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + mac->ra_state = WAIT_RAR; + // Start contention resolution timer + mac->RA_attempt_number++; +} + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + // start contention resolution timer + mac->RA_contention_resolution_cnt = 0; + mac->RA_contention_resolution_timer_active = 1; +} + +///////////////////////////////////////////////////////////////////////// +///////* Random Access Preamble Initialization (5.1.1 TS 38.321) */////// +///////////////////////////////////////////////////////////////////////// +/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) +/// Only one RA procedure is ongoing at any point in time in a MAC entity +/// the RA procedure on a SCell shall only be initiated by PDCCH order +/// in the current implementation, RA is contention free only + +// WIP +// todo TS 38.321: +// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX +// - BWP operation (subclause 5.15 TS 38.321) +// - handle initialization by beam failure recovery +// - handle initialization by handover +// - handle transmission on DCCH using PRACH (during handover, or sending SR for example) +// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader) +// - fix rrc data req logic +// - retrieve TBS +// - add mac_rrc_nr_data_req_ue, etc ... +// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + +uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + uint8_t mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES]; + uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *payload; + //uint8_t ra_ResponseWindow; + uint16_t size_sdu = 0; + unsigned short post_padding; + //fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; + //NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + NR_RACH_ConfigDedicated_t *rach_ConfigDedicated = mac->rach_ConfigDedicated; + + // int32_t frame_diff = 0; + + uint8_t sdu_lcids[NB_RB_MAX] = {0}; + uint16_t sdu_lengths[NB_RB_MAX] = {0}; + int TBS_bytes = 848, header_length_total, num_sdus, offset, preambleTransMax, mac_ce_len; + + AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); + + if (UE_mode == PRACH && prach_resources->init_msg1) { + + LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); + + AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + + if (mac->RA_active == 0) { + /* RA not active - checking if RRC is ready to initiate the RA procedure */ + + LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n"); + + mac->RA_RAPID_found = 0; + + /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ + switch (rach_ConfigGeneric->powerRampingStep){ // in dB + case 0: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 0; + break; + case 1: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 2; + break; + case 2: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 4; + break; + case 3: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 6; + break; + } + + prach_resources->RA_PREAMBLE_BACKOFF = 0; + prach_resources->RA_SCALING_FACTOR_BI = 1; + prach_resources->RA_PCMAX = 0; // currently hardcoded to 0 + + payload = (uint8_t*) &mac->CCCH_pdu.payload; + + mac_ce_len = 0; + num_sdus = 1; + post_padding = 1; + + if (0){ + // initialisation by RRC + // CCCH PDU + // size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id, + // CC_id, + // frame, + // CCCH, + // 1, + // mac_sdus, + // gNB_id, + // 0); + LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id, frame, size_sdu); + } else { + // fill ulsch_buffer with random data + for (int i = 0; i < TBS_bytes; i++){ + mac_sdus[i] = (unsigned char) (lrand48()&0xff); + } + //Sending SDUs with size 1 + //Initialize elements of sdu_lcids and sdu_lengths + sdu_lcids[0] = lcid; + sdu_lengths[0] = TBS_bytes - 3 - post_padding - mac_ce_len; + header_length_total += 2 + (sdu_lengths[0] >= 128); + size_sdu += sdu_lengths[0]; + } + + //mac->RA_tx_frame = frame; + //mac->RA_tx_subframe = nr_tti_tx; + //mac->RA_backoff_frame = frame; + //mac->RA_backoff_subframe = nr_tti_tx; + + if (size_sdu > 0) { + + LOG_I(MAC, "[UE %d] Frame %d: Initialisation Random Access Procedure\n", mod_id, frame); + + mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + mac->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; + mac->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); + mac->RA_prachMaskIndex = 0; + // todo: add the backoff condition here + mac->RA_backoff_cnt = 0; + mac->RA_active = 1; + prach_resources->Msg3 = payload; + + nr_get_RA_window(mac); + + // Fill in preamble and PRACH resources + if (mac->generate_nr_prach) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, rach_ConfigDedicated); + + offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer + (uint8_t *) payload, // UL MAC pdu pointer + num_sdus, // num sdus + sdu_lengths, // sdu length + sdu_lcids, // sdu lcid + 0, // power headroom + 0, // crnti + 0, // truncated bsr + 0, // short bsr + 0, // long_bsr + post_padding, + 0); + + // Padding: fill remainder with 0 + if (post_padding > 0){ + for (int j = 0; j < (TBS_bytes - offset); j++) + payload[offset + j] = 0; // mac_pdu[offset + j] = 0; + } + } + } else { // RACH is active + + //////////////////////////////////////////////////////////////// + /////* Random Access Response reception (5.1.4 TS 38.321) *///// + //////////////////////////////////////////////////////////////// + // Handling ra_responseWindow, RA_PREAMBLE_TRANSMISSION_COUNTER + // and RA_backoff_cnt + // todo: + // - handle beam failure recovery request + // - handle DL assignment on PDCCH for RA-RNTI + // - handle backoff and raResponseWindow params + // - disabled contention resolution as OAI NSA is contention-free based + + // LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", + // mod_id, frame, nr_tti_tx, mac->RA_window_cnt, mac->RA_tx_frame, mac->RA_tx_subframe); + + if (mac->RA_BI_found){ + prach_resources->RA_PREAMBLE_BACKOFF = prach_resources->RA_SCALING_FACTOR_BI * mac->RA_backoff_indicator; + } else { + prach_resources->RA_PREAMBLE_BACKOFF = 0; + } + + if (mac->RA_window_cnt >= 0 && mac->RA_RAPID_found == 1) { + + // mac->ra_state = WAIT_CONTENTION_RESOLUTION; + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR successfully received \n", mod_id, frame, nr_tti_tx); + + } else if (mac->RA_window_cnt == 0 && !mac->RA_RAPID_found) { + + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception failed \n", mod_id, frame, nr_tti_tx); + + mac->ra_state = RA_UE_IDLE; + mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; + + preambleTransMax = -1; + switch (rach_ConfigGeneric->preambleTransMax) { + case 0: + preambleTransMax = 3; + break; + case 1: + preambleTransMax = 4; + break; + case 2: + preambleTransMax = 5; + break; + case 3: + preambleTransMax = 6; + break; + case 4: + preambleTransMax = 7; + break; + case 5: + preambleTransMax = 8; + break; + case 6: + preambleTransMax = 10; + break; + case 7: + preambleTransMax = 20; + break; + case 8: + preambleTransMax = 50; + break; + case 9: + preambleTransMax = 100; + break; + case 10: + preambleTransMax = 200; + break; + } + + // Resetting RA window + nr_get_RA_window(mac); + + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax + 1){ + LOG_D(MAC, "[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n", mod_id, frame, preambleTransMax); + mac->RA_backoff_cnt = rand() % (prach_resources->RA_PREAMBLE_BACKOFF + 1); + mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP += prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1; // 2 dB increment + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); + } + + // compute backoff parameters + // if (mac->RA_backoff_cnt > 0){ + // frame_diff = (sframe_t) frame - mac->RA_backoff_frame; + // if (frame_diff < 0) frame_diff = -frame_diff; + // mac->RA_backoff_frame = frame; + // mac->RA_backoff_subframe = nr_tti_tx; + // } + // compute RA window parameters + // if (mac->RA_window_cnt > 0){ + // frame_diff = (frame_t) frame - mac->RA_tx_frame; + // if (frame_diff < 0) frame_diff = -frame_diff; + // mac->RA_window_cnt -= ((10 * frame_diff) + (nr_tti_tx - mac->RA_tx_subframe)); + // LOG_D(MAC, "[MAC][UE %d][RAPROC] Frame %d, subframe %d: RA Active, adjusted window cnt %d\n", mod_id, frame, nr_tti_tx, mac->RA_window_cnt); + // } + + // mac->RA_tx_frame = frame; + // mac->RA_tx_subframe = nr_tti_tx; + + // Fill in preamble and PRACH resources + if (mac->generate_nr_prach) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); + + } else { + + mac->RA_window_cnt--; + + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", + mod_id, + frame, + nr_tti_tx, + mac->RA_window_cnt); + + // Fill in preamble and PRACH resources + if (mac->generate_nr_prach) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); + + } + } + } else if (UE_mode == PUSCH) { + LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); + AssertFatal(1 == 0, ""); + } + return mac->generate_nr_prach; +} + +void nr_get_RA_window(NR_UE_MAC_INST_t *mac){ + + uint8_t mu, ra_ResponseWindow; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; + NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + + ra_ResponseWindow = rach_ConfigGeneric->ra_ResponseWindow; + + if (setup->msg1_SubcarrierSpacing) + mu = *setup->msg1_SubcarrierSpacing; + else + mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + mac->RA_window_cnt = mac->RA_offset*nr_slots_per_frame[mu]; // taking into account the 2 frames gap introduced by OAI gNB + + switch (ra_ResponseWindow) { + case 0: + mac->RA_window_cnt += 1; + break; + case 1: + mac->RA_window_cnt += 2; + break; + case 2: + mac->RA_window_cnt += 4; + break; + case 3: + mac->RA_window_cnt += 8; + break; + case 4: + mac->RA_window_cnt += 10; + break; + case 5: + mac->RA_window_cnt += 20; + break; + case 6: + mac->RA_window_cnt += 40; + break; + case 7: + mac->RA_window_cnt += 80; + break; + } +} diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c new file mode 100644 index 0000000000..31a865f317 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -0,0 +1,209 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rar_tools_nrUE.c + * \brief RA tools for NR UE + * \author Guido Casati + * \date 2019 + * \version 1.0 + * @ingroup _mac + + */ + +/* Sim */ +#include "SIMULATION/TOOLS/sim.h" + +/* Utils */ +#include "common/utils/LOG/log.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "UTIL/OPT/opt.h" + +/* Common */ +#include "common/ran_context.h" + +/* MAC */ +#include "NR_MAC_UE/mac.h" +#include "NR_MAC_UE/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" +#include + +#define DEBUG_RAR + +// table 7.2-1 TS 38.321 +uint16_t table_7_2_1[16] = { + 5, // row index 0 + 10, // row index 1 + 20, // row index 2 + 30, // row index 3 + 40, // row index 4 + 60, // row index 5 + 80, // row index 6 + 120, // row index 7 + 160, // row index 8 + 240, // row index 9 + 320, // row index 10 + 480, // row index 11 + 960, // row index 12 + 1920, // row index 13 +}; + +///////////////////////////////////// +// Random Access Response PDU // +// TS 38.213 ch 8.2 // +// TS 38.321 ch 6.2.3 // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//| E | T | R A P I D |// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// +//| R | T A |// +//| T A | UL grant |// +//| UL grant |// +//| UL grant |// +//| UL grant |// +//| T C - R N T I |// +//| T C - R N T I |// +///////////////////////////////////// +// UL grant (27 bits) // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//|-------------------|FHF|F_alloc|// +//| Freq allocation |// +//| F_alloc |Time allocation|// +//| MCS | TPC |CSI|// +///////////////////////////////////// +// WIP todo: +// - apply UL grant freq alloc & time alloc as per 8.2 TS 38.213 +// - apply tpc command, csi req, mcs +uint16_t nr_ue_process_rar(module_id_t mod_id, + int CC_id, + frame_t frameP, + uint8_t * dlsch_buffer, + rnti_t * t_crnti, + uint8_t preamble_index, + uint8_t * selected_rar_buffer){ + + NR_UE_MAC_INST_t *ue_mac = get_mac_inst(mod_id); + NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; // RAR subheader pointer + NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); // RAR subPDU pointer + uint8_t n_subPDUs = 0; // number of RAR payloads + uint8_t n_subheaders = 0; // number of MAC RAR subheaders + //uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + unsigned char freq_hopping, msg3_t_alloc, mcs, tpc_command, csi_req; + uint16_t ta_command = 0, msg3_f_alloc, bwp_size; + int f_alloc, mask; + + AssertFatal(CC_id == 0, "RAR reception on secondary CCs is not supported yet\n"); + + while (1) { + n_subheaders++; + if (rarh->T == 1) { + n_subPDUs++; + LOG_D(MAC, "[UE %d][RAPROC] Got RAPID RAR subPDU\n", mod_id); + } else { + n_subPDUs++; + ue_mac->RA_backoff_indicator = table_7_2_1[((NR_RA_HEADER_BI *)rarh)->BI]; + ue_mac->RA_BI_found = 1; + LOG_D(MAC, "[UE %d][RAPROC] Got BI RAR subPDU %d\n", mod_id, ue_mac->RA_backoff_indicator); + } + if (rarh->RAPID == preamble_index) { + LOG_D(PHY, "[UE %d][RAPROC] Found RAR with the intended RAPID %d\n", mod_id, rarh->RAPID); + rar = (NR_MAC_RAR *) (dlsch_buffer + n_subheaders + (n_subPDUs - 1) * sizeof(NR_MAC_RAR)); + ue_mac->RA_RAPID_found = 1; + break; + } + if (rarh->E == 0) { + LOG_I(PHY, "No RAR found with the intended RAPID. \n"); + break; + } else { + rarh += sizeof(NR_MAC_RAR) + 1; + } + }; + + LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", n_subheaders, n_subPDUs); + + // LOG_I(MAC, "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", + // mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); + + if (ue_mac->RA_RAPID_found) { + // TC-RNTI + *t_crnti = rar->TCRNTI_2 + (rar->TCRNTI_1 << 8); + ue_mac->t_crnti = *t_crnti; + ue_mac->rnti_type = NR_RNTI_TC; + // TA command + ta_command = rar->TA2 + (rar->TA1 << 5); + // CSI + csi_req = (unsigned char) (rar->UL_GRANT_4 & 0x01); + // TPC + tpc_command = (unsigned char) ((rar->UL_GRANT_4 >> 1) & 0x07); + switch (tpc_command){ + case 0: + ue_mac->Msg3_TPC = -6; + break; + case 1: + ue_mac->Msg3_TPC = -4; + break; + case 2: + ue_mac->Msg3_TPC = -2; + break; + case 3: + ue_mac->Msg3_TPC = 0; + break; + case 4: + ue_mac->Msg3_TPC = 2; + break; + case 5: + ue_mac->Msg3_TPC = 4; + break; + case 6: + ue_mac->Msg3_TPC = 6; + break; + case 7: + ue_mac->Msg3_TPC = 8; + break; + } + //MCS + mcs = (unsigned char) (rar->UL_GRANT_4 >> 4); + // time and frequency alloc + bwp_size = NRRIV2BW(ue_mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + msg3_t_alloc = (unsigned char) (rar->UL_GRANT_3 & 0x07); + msg3_f_alloc = (uint16_t) ((rar->UL_GRANT_3 >> 4) | (rar->UL_GRANT_2 << 4) | ((rar->UL_GRANT_1 & 0x03) << 12)); + + if (bwp_size < 180) + mask = (1 << ((int) ceil(log2((bwp_size*(bwp_size+1))>>1)))) - 1; + else + mask = (1 << (28 - (int)(ceil(log2((bwp_size*(bwp_size+1))>>1))))) - 1; + + f_alloc = msg3_f_alloc & mask; + + // frequency hopping flag + freq_hopping = (unsigned char) (rar->UL_GRANT_1 >> 2); + } else { + ue_mac->t_crnti = 0; + ta_command = (0xffff); + } + + // move the selected RAR to the front of the RA_PDSCH buffer + memcpy((void *) (selected_rar_buffer + 0), (void *) rarh, 1); + memcpy((void *) (selected_rar_buffer + 1), (void *) rar, sizeof(NR_MAC_RAR)); + + return ta_command; +} diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.c b/openair2/RRC/NR/rrc_gNB_GTPV1U.c new file mode 100644 index 0000000000..9ab1bbf43a --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.c @@ -0,0 +1,94 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_GTPV1U.c + * \brief rrc GTPV1U procedures for gNB + * \author Lionel GAUTHIER, Panos MATZAKOS + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr, panagiotis.matzakos@eurecom.fr + */ + +# include "rrc_defs.h" +# include "rrc_extern.h" +# include "RRC/LTE/MESSAGES/asn1_msg.h" +# include "rrc_eNB_GTPV1U.h" +# include "rrc_eNB_UE_context.h" +# include "msc.h" +# include "openair2/RRC/NR/rrc_gNB_UE_context.h" + +//# if defined(ENABLE_ITTI) +# include "asn1_conversions.h" +# include "intertask_interface.h" +//#endif + +# include "common/ran_context.h" + +extern RAN_CONTEXT_t RC; + +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +) { + rnti_t rnti; + int i; + struct rrc_gNB_ue_context_s *ue_context_p = NULL; + + if (create_tunnel_resp_pP) { + LOG_D(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RX CREATE_TUNNEL_RESP num tunnels %u \n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + create_tunnel_resp_pP->num_tunnels); + rnti = create_tunnel_resp_pP->rnti; + ue_context_p = rrc_gNB_get_ue_context( + RC.nrrrc[ctxt_pP->module_id], + ctxt_pP->rnti); + + for (i = 0; i < create_tunnel_resp_pP->num_tunnels; i++) { + ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]] = create_tunnel_resp_pP->enb_S1u_teid[i]; + ue_context_p->ue_context.gnb_gtp_addrs[inde_list[i]] = create_tunnel_resp_pP->enb_addr; + ue_context_p->ue_context.gnb_gtp_ebi[inde_list[i]] = create_tunnel_resp_pP->eps_bearer_id[i]; + LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (%u, %u) bearer UE context index %u, msg index %u, id %u, gtp addr len %d \n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + create_tunnel_resp_pP->enb_S1u_teid[i], + ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]], + inde_list[i], + i, + create_tunnel_resp_pP->eps_bearer_id[i], + create_tunnel_resp_pP->enb_addr.length); + } + + MSC_LOG_RX_MESSAGE( + MSC_RRC_ENB, + MSC_GTPU_ENB, + NULL,0, + MSC_AS_TIME_FMT" CREATE_TUNNEL_RESP RNTI %"PRIx16" ntuns %u ebid %u enb-s1u teid %u", + 0,0,rnti, + create_tunnel_resp_pP->num_tunnels, + ue_context_p->ue_context.gnb_gtp_ebi[0], + ue_context_p->ue_context.gnb_gtp_teid[0]); + (void)rnti; /* avoid gcc warning "set but not used" */ + return 0; + } else { + return -1; + } +} diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.h b/openair2/RRC/NR/rrc_gNB_GTPV1U.h new file mode 100644 index 0000000000..caff825a7a --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.h @@ -0,0 +1,39 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_GTPV1U.h + * \brief rrc GTPV1U procedures for gNB + * \author Lionel GAUTHIER, Panos MATZAKOS + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr, panagiotis.matzakos@eurecom.fr + */ + +#ifndef RRC_GNB_GTPV1U_H_ +#define RRC_GNB_GTPV1U_H_ + + +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +); diff --git a/openair3/GTPV1-U/gtpv1u_gNB.c b/openair3/GTPV1-U/gtpv1u_gNB.c new file mode 100644 index 0000000000..f13bf13794 --- /dev/null +++ b/openair3/GTPV1-U/gtpv1u_gNB.c @@ -0,0 +1,311 @@ +/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file gtpv1u_gNB.c + * \brief + * \author Sebastien ROUX, Lionel GAUTHIER, Navid Nikaein, Panos MATZAKOS + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr + */ +#include +#include + +#include "mme_config.h" +#include "intertask_interface.h" +#include "msc.h" + +#include "gtpv1u.h" +#include "NwGtpv1u.h" +#include "NwGtpv1uMsg.h" +#include "NwGtpv1uPrivate.h" +#include "NwLog.h" +#include "gtpv1u_eNB_defs.h" +#include "gtpv1_u_messages_types.h" +#include "udp_eNB_task.h" +#include "common/utils/LOG/log.h" +#include "COMMON/platform_types.h" +#include "COMMON/platform_constants.h" +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "common/ran_context.h" +#include "gtpv1u_eNB_defs.h" +#include "gtpv1u_eNB_task.h" +#include "gtpv1u_gNB_task.h" +#include "rrc_eNB_GTPV1U.h" + +#undef GTP_DUMP_SOCKET + +extern unsigned char NB_eNB_INST; + +extern RAN_CONTEXT_t RC; + +extern NwGtpv1uRcT gtpv1u_eNB_send_udp_msg( + NwGtpv1uUdpHandleT udpHandle, + uint8_t *buffer, + uint32_t buffer_len, + uint32_t buffer_offset, + uint32_t peerIpAddr, + uint16_t peerPort); + +extern NwGtpv1uRcT gtpv1u_eNB_log_request(NwGtpv1uLogMgrHandleT hLogMgr, + uint32_t logLevel, + NwCharT *file, + uint32_t line, + NwCharT *logStr); + +static NwGtpv1uRcT gtpv1u_start_timer_wrapper( + NwGtpv1uTimerMgrHandleT tmrMgrHandle, + uint32_t timeoutSec, + uint32_t timeoutUsec, + uint32_t tmrType, + void *timeoutArg, + NwGtpv1uTimerHandleT *hTmr) { + NwGtpv1uRcT rc = NW_GTPV1U_OK; + long timer_id; + + if (tmrType == NW_GTPV1U_TMR_TYPE_ONE_SHOT) { + timer_setup(timeoutSec, + timeoutUsec, + TASK_GTPV1_U, + INSTANCE_DEFAULT, + TIMER_ONE_SHOT, + timeoutArg, + &timer_id); + } else { + timer_setup(timeoutSec, + timeoutUsec, + TASK_GTPV1_U, + INSTANCE_DEFAULT, + TIMER_PERIODIC, + timeoutArg, + &timer_id); + } + + return rc; +} + + +static NwGtpv1uRcT +gtpv1u_stop_timer_wrapper( + NwGtpv1uTimerMgrHandleT tmrMgrHandle, + NwGtpv1uTimerHandleT hTmr) { + NwGtpv1uRcT rc = NW_GTPV1U_OK; + return rc; +} + +/* Callback called when a gtpv1u message arrived on UDP interface */ +NwGtpv1uRcT gtpv1u_gNB_process_stack_req( + NwGtpv1uUlpHandleT hUlp, + NwGtpv1uUlpApiT *pUlpApi) { + boolean_t result = FALSE; + teid_t teid = 0; + hashtable_rc_t hash_rc = HASH_TABLE_KEY_NOT_EXISTS; + gtpv1u_teid_data_t *gtpv1u_teid_data_p = NULL; + protocol_ctxt_t ctxt; + NwGtpv1uRcT rc; + + switch(pUlpApi->apiType) { + /* Here there are two type of messages handled: + * - T-PDU + * - END-MARKER + */ + case NW_GTPV1U_ULP_API_RECV_TPDU: { + uint8_t buffer[4096]; + uint32_t buffer_len; + //uint16_t msgType = NW_GTP_GPDU; + //NwGtpv1uMsgT *pMsg = NULL; + /* Nw-gptv1u stack has processed a PDU. we can schedule it to PDCP + * for transmission. + */ + teid = pUlpApi->apiInfo.recvMsgInfo.teid; + //pMsg = (NwGtpv1uMsgT *) pUlpApi->apiInfo.recvMsgInfo.hMsg; + //msgType = pMsg->msgType; + + if (NW_GTPV1U_OK != nwGtpv1uMsgGetTpdu(pUlpApi->apiInfo.recvMsgInfo.hMsg, + buffer, &buffer_len)) { + LOG_E(GTPU, "Error while retrieving T-PDU"); + } + + itti_free(TASK_UDP, ((NwGtpv1uMsgT *)pUlpApi->apiInfo.recvMsgInfo.hMsg)->msgBuf); +#if defined(GTP_DUMP_SOCKET) && GTP_DUMP_SOCKET > 0 + gtpv1u_eNB_write_dump_socket(buffer,buffer_len); +#endif + rc = nwGtpv1uMsgDelete(RC.gtpv1u_data_g->gtpv1u_stack, + pUlpApi->apiInfo.recvMsgInfo.hMsg); + + if (rc != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uMsgDelete failed: 0x%x\n", rc); + } + + hash_rc = hashtable_get(RC.gtpv1u_data_g->teid_mapping, teid, (void **)>pv1u_teid_data_p); + + if (hash_rc == HASH_TABLE_OK) { +#if defined(LOG_GTPU) && LOG_GTPU > 0 + LOG_D(GTPU, "Received T-PDU from gtpv1u stack teid %u size %d -> enb module id %u ue module id %u rab id %u\n", + teid, + buffer_len, + gtpv1u_teid_data_p->enb_id, + gtpv1u_teid_data_p->ue_id, + gtpv1u_teid_data_p->eps_bearer_id); +#endif + //warning "LG eps bearer mapping to DRB id to do (offset -4)" + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gtpv1u_teid_data_p->enb_id, ENB_FLAG_YES, gtpv1u_teid_data_p->ue_id, 0, 0,gtpv1u_teid_data_p->enb_id); + MSC_LOG_TX_MESSAGE( + MSC_GTPU_ENB, + MSC_PDCP_ENB, + NULL,0, + MSC_AS_TIME_FMT" DATA-REQ rb %u size %u", + 0,0, + (gtpv1u_teid_data_p->eps_bearer_id) ? gtpv1u_teid_data_p->eps_bearer_id - 4: 5-4, + buffer_len); + + result = pdcp_data_req( + &ctxt, + SRB_FLAG_NO, + (gtpv1u_teid_data_p->eps_bearer_id) ? gtpv1u_teid_data_p->eps_bearer_id - 4: 5-4, + 0, // mui + SDU_CONFIRM_NO, // confirm + buffer_len, + buffer, + PDCP_TRANSMISSION_MODE_DATA,NULL, NULL + ); + + if ( result == FALSE ) { + if (ctxt.configured == FALSE ) + LOG_W(GTPU, "gNB node PDCP data request failed, cause: [UE:%x]RB is not configured!\n", ctxt.rnti) ; + else + LOG_W(GTPU, "PDCP data request failed\n"); + + return NW_GTPV1U_FAILURE; + } + } else { + LOG_W(GTPU, "Received T-PDU from gtpv1u stack teid %u unknown size %u", teid, buffer_len); + } + } + break; + + default: { + LOG_E(GTPU, "Received undefined UlpApi (%02x) from gtpv1u stack!\n", + pUlpApi->apiType); + } + } // end of switch + + return NW_GTPV1U_OK; +} + +int gtpv1u_gNB_init(void) { + NwGtpv1uRcT rc = NW_GTPV1U_FAILURE; + NwGtpv1uUlpEntityT ulp; + NwGtpv1uUdpEntityT udp; + NwGtpv1uLogMgrEntityT log; + NwGtpv1uTimerMgrEntityT tmr; + // enb_properties_p = enb_config_get()->properties[0]; + RC.gtpv1u_data_g = (gtpv1u_data_t *)calloc(sizeof(gtpv1u_data_t),1); + LOG_I(GTPU, "Initializing GTPU stack %p\n",&RC.gtpv1u_data_g); + //gtpv1u_data_g.gtpv1u_stack; + /* Initialize UE hashtable */ + RC.gtpv1u_data_g->ue_mapping = hashtable_create (32, NULL, NULL); + AssertFatal(RC.gtpv1u_data_g->ue_mapping != NULL, " ERROR Initializing TASK_GTPV1_U task interface: in hashtable_create returned %p\n", RC.gtpv1u_data_g->ue_mapping); + RC.gtpv1u_data_g->teid_mapping = hashtable_create (256, NULL, NULL); + AssertFatal(RC.gtpv1u_data_g->teid_mapping != NULL, " ERROR Initializing TASK_GTPV1_U task interface: in hashtable_create\n"); + // RC.gtpv1u_data_g.enb_ip_address_for_S1u_S12_S4_up = enb_properties_p->enb_ipv4_address_for_S1U; + //gtpv1u_data_g.udp_data; + RC.gtpv1u_data_g->seq_num = 0; + RC.gtpv1u_data_g->restart_counter = 0; + + /* Initializing GTPv1-U stack */ + if ((rc = nwGtpv1uInitialize(&RC.gtpv1u_data_g->gtpv1u_stack, GTPU_STACK_ENB)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "Failed to setup nwGtpv1u stack %x\n", rc); + return -1; + } + + if ((rc = nwGtpv1uSetLogLevel(RC.gtpv1u_data_g->gtpv1u_stack, + NW_LOG_LEVEL_DEBG)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "Failed to setup loglevel for stack %x\n", rc); + return -1; + } + + /* Set the ULP API callback. Called once message have been processed by the + * nw-gtpv1u stack. + */ + ulp.ulpReqCallback = gtpv1u_gNB_process_stack_req; + memset((void *)&(ulp.hUlp), 0, sizeof(NwGtpv1uUlpHandleT)); + + if ((rc = nwGtpv1uSetUlpEntity(RC.gtpv1u_data_g->gtpv1u_stack, &ulp)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetUlpEntity: %x", rc); + return -1; + } + + /* nw-gtpv1u stack requires an udp callback to send data over UDP. + * We provide a wrapper to UDP task. + */ + udp.udpDataReqCallback = gtpv1u_eNB_send_udp_msg; + memset((void *)&(udp.hUdp), 0, sizeof(NwGtpv1uUdpHandleT)); + + if ((rc = nwGtpv1uSetUdpEntity(RC.gtpv1u_data_g->gtpv1u_stack, &udp)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetUdpEntity: %x", rc); + return -1; + } + + log.logReqCallback = gtpv1u_eNB_log_request; + memset((void *)&(log.logMgrHandle), 0, sizeof(NwGtpv1uLogMgrHandleT)); + + if ((rc = nwGtpv1uSetLogMgrEntity(RC.gtpv1u_data_g->gtpv1u_stack, &log)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetLogMgrEntity: %x", rc); + return -1; + } + + /* Timer interface is more complicated as both wrappers doesn't send a message + * to the timer task but call the timer API functions start/stop timer. + */ + tmr.tmrMgrHandle = 0; + tmr.tmrStartCallback = gtpv1u_start_timer_wrapper; + tmr.tmrStopCallback = gtpv1u_stop_timer_wrapper; + + if ((rc = nwGtpv1uSetTimerMgrEntity(RC.gtpv1u_data_g->gtpv1u_stack, &tmr)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetTimerMgrEntity: %x", rc); + return -1; + } + +#if defined(GTP_DUMP_SOCKET) && GTP_DUMP_SOCKET > 0 + + if ((ret = gtpv1u_eNB_create_dump_socket()) < 0) { + return -1; + } + +#endif + LOG_D(GTPU, "Initializing GTPV1U interface for eNB: DONE\n"); + return 0; +} + +void *gtpv1u_gNB_task(void *args) { + int rc = 0; + rc = gtpv1u_gNB_init(); + AssertFatal(rc == 0, "gtpv1u_eNB_init Failed"); + itti_mark_task_ready(TASK_GTPV1_U); + MSC_START_USE(); + + while(1) { + (void) gtpv1u_eNB_process_itti_msg (NULL); + } + + return NULL; +} + diff --git a/openair3/GTPV1-U/gtpv1u_gNB_task.h b/openair3/GTPV1-U/gtpv1u_gNB_task.h new file mode 100644 index 0000000000..42fae7a714 --- /dev/null +++ b/openair3/GTPV1-U/gtpv1u_gNB_task.h @@ -0,0 +1,37 @@ +/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file gtpv1u_gNB_task.h +* \brief +* \author Lionel Gauthier Panos Matzakos +* \company Eurecom +* \email: lionel.gauthier@eurecom.fr +*/ + +#ifndef GTPV1U_GNB_TASK_H_ +#define GTPV1U_GNB_TASK_H_ + +int gtpv1u_gNB_init(void); + +void *gtpv1u_gNB_task(void *args); + + +#endif /* GTPV1U_GNB_TASK_H_ */ + diff --git a/patch.diff b/patch.diff new file mode 100644 index 0000000000..a85f8df37a --- /dev/null +++ b/patch.diff @@ -0,0 +1,472 @@ +diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai +index 88b8811..a7adc33 100755 +--- a/cmake_targets/build_oai ++++ b/cmake_targets/build_oai +@@ -701,8 +701,8 @@ function main() { + if [ "$SIMUS_PHY" = "1" ] ; then + echo_info "Compiling physical unitary tests simulators" + # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim +- simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" +- # simlist="ldpctest" ++ # simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" ++ simlist="ldpctest" + for f in $simlist ; do + compilations \ + phy_simulators $f \ +diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c +index 345122c..72d85b1 100644 +--- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c ++++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c +@@ -396,17 +396,15 @@ int test_ldpc(short No_iteration, + decParams.numMaxIter=No_iteration; + decParams.outMode = nrLDPC_outMode_BIT; + //decParams.outMode =nrLDPC_outMode_LLRINT8; +- +- ++ set_compact_BG(Zc,BG); ++ init_LLR_DMA_for_CUDA(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length); + for(j=0;j 1280, 2401 -> 2560 +diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu +index 161b362..931d500 100644 +--- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu ++++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu +@@ -32,7 +32,7 @@ + #include "bgs/BG2_I6" + #include "bgs/BG2_I7" + +-#define MAX_ITERATION 5 ++#define MAX_ITERATION 2 + #define MC 1 + + #define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } +@@ -49,13 +49,21 @@ typedef struct{ + char y; + short value; + } h_element; ++#include "bgs/BG1_compact_in_C.h" + ++__device__ char dev_const_llr[68*384]; ++__device__ char dev_dt [46*68*384]; ++__device__ char dev_llr[68*384]; ++__device__ unsigned char dev_tmp[68*384]; + + h_element h_compact1 [46*19] = {}; + h_element h_compact2 [68*30] = {}; + +-__device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 +-__device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 ++__device__ h_element dev_h_compact1[46*19]; // used in kernel 1 ++__device__ h_element dev_h_compact2[68*30]; // used in kernel 2 ++ ++// __device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 ++// __device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 + + // row and col element count + __device__ __constant__ char h_ele_row_bg1_count[46] = { +@@ -92,9 +100,93 @@ __global__ void warmup() + // warm up gpu for time measurement + } + ++extern "C" ++void warmup_for_GPU(){ ++ ++ warmup<<<20,1024 >>>(); ++ ++} ++ ++extern "C" ++void set_compact_BG(int Zc,short BG){ ++ ++ int row,col; ++ if(BG == 1){ ++ row = 46; ++ col = 68; ++ } ++ else{ ++ row = 42; ++ col = 52; ++ } ++ int compact_row = 30; ++ int compact_col = 19; ++ if(BG==2){compact_row = 10, compact_col = 23;} ++ int memorySize_h_compact1 = row * compact_col * sizeof(h_element); ++ int memorySize_h_compact2 = compact_row * col * sizeof(h_element); ++ int lift_index = 0; ++ short lift_set[][9] = { ++ {2,4,8,16,32,64,128,256}, ++ {3,6,12,24,48,96,192,384}, ++ {5,10,20,40,80,160,320}, ++ {7,14,28,56,112,224}, ++ {9,18,36,72,144,288}, ++ {11,22,44,88,176,352}, ++ {13,26,52,104,208}, ++ {15,30,60,120,240}, ++ {0} ++ }; ++ ++ for(int i = 0; lift_set[i][0] != 0; i++){ ++ for(int j = 0; lift_set[i][j] != 0; j++){ ++ if(Zc == lift_set[i][j]){ ++ lift_index = i; ++ break; ++ } ++ } ++ } ++ printf("\nZc = %d BG = %d\n",Zc,BG); ++ switch(lift_index){ ++ case 0: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I0, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I0, memorySize_h_compact2) ); ++ break; ++ case 1: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I1, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I1, memorySize_h_compact2) ); ++ break; ++ case 2: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I2, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I2, memorySize_h_compact2) ); ++ break; ++ case 3: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I3, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I3, memorySize_h_compact2) ); ++ break; ++ case 4: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I4, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I4, memorySize_h_compact2) ); ++ break; ++ case 5: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I5, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I5, memorySize_h_compact2) ); ++ break; ++ case 6: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I6, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I6, memorySize_h_compact2) ); ++ break; ++ case 7: ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I7, memorySize_h_compact1) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I7, memorySize_h_compact2) ); ++ break; ++ } ++ ++ // return 0; ++} ++ + + // Kernel 1 +-__global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) ++__global__ void ldpc_cnp_kernel_1st_iter(/*char * dev_llr,*/ int BG, int row, int col, int Zc) + { + // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp %d\n", threadIdx.x); + int iMCW = blockIdx.y; // codeword id +@@ -153,7 +245,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, + for(int i = 0; i < s; i++){ + // v0: Best performance so far. 0.75f is the value of alpha. + sq = 1 - 2 * ((Q_sign >> i) & 0x01); +- R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); ++ R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); + // write results to global memory + h_element_t = dev_h_compact1[i*row+iBlkRow]; + int addr_temp = offsetR + h_element_t.y * row * Zc; +@@ -163,7 +255,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, + } + + // Kernel_1 +-__global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) ++__global__ void ldpc_cnp_kernel(/*char * dev_llr, char * dev_dt,*/ int BG, int row, int col, int Zc) + { + // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp\n"); + int iMCW = blockIdx.y; +@@ -223,7 +315,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, + // The 2nd recursion + for(int i = 0; i < s; i ++){ + sq = 1 - 2 * ((Q_sign >> i) & 0x01); +- R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); ++ R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); + + + // write results to global memory +@@ -236,7 +328,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, + + // Kernel 2: VNP processing + __global__ void +-ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int BG, int row, int col, int Zc) ++ldpc_vnp_kernel_normal(/*char * dev_llr, char * dev_dt, char * dev_const_llr,*/ int BG, int row, int col, int Zc) + { + int iMCW = blockIdx.y; + int iBlkCol = blockIdx.x; +@@ -276,7 +368,7 @@ ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int + } + + +-__global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc) ++__global__ void pack_decoded_bit(/*char *dev, unsigned char *host,*/ int col, int Zc) + { + __shared__ unsigned char tmp[128]; + int iMCW = blockIdx.y; +@@ -284,15 +376,15 @@ __global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc + int btid = threadIdx.x; + tmp[btid] = 0; + +- if(dev[tid] < 0){ ++ if(dev_llr[tid] < 0){ + tmp[btid] = 1 << (7-(btid&7)); + } + __syncthreads(); + + if(threadIdx.x < 16){ +- host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; ++ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; + for(int i = 0; i < 8; i++){ +- host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; ++ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; + } + } + } +@@ -369,18 +461,38 @@ void read_BG(int BG, int *h, int row, int col) + */ + } + ++extern "C" ++void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length){ ++ ++ uint16_t Zc = p_decParams->Z; ++ uint8_t BG = p_decParams->BG; ++ uint8_t row,col; ++ if(BG == 1){ ++ row = 46; ++ col = 68; ++ } ++ else{ ++ row = 42; ++ col = 52; ++ } ++ unsigned char *hard_decision = (unsigned char*)p_out; ++ int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; ++ cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); ++ cudaDeviceSynchronize(); ++ ++} + + extern "C" + int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder) + { +- // alloc mem +- //unsigned char *decision = (unsigned char*)p_out; ++ + + uint16_t Zc = p_decParams->Z; + uint8_t BG = p_decParams->BG; + uint8_t numMaxIter = p_decParams->numMaxIter; + e_nrLDPC_outMode outMode = p_decParams->outMode; +- ++ cudaError_t cudaStatus; + uint8_t row,col; + if(BG == 1){ + row = 46; +@@ -390,96 +502,14 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8 + row = 42; + col = 52; + } +- int compact_row = 30, compact_col = 19, lift_index=0;; +- if(BG==2){compact_row = 10, compact_col = 23;} +- +- short lift_set[][9] = { +- {2,4,8,16,32,64,128,256}, +- {3,6,12,24,48,96,192,384}, +- {5,10,20,40,80,160,320}, +- {7,14,28,56,112,224}, +- {9,18,36,72,144,288}, +- {11,22,44,88,176,352}, +- {13,26,52,104,208}, +- {15,30,60,120,240}, +- {0} +- }; +- +- for(int i = 0; lift_set[i][0] != 0; i++){ +- for(int j = 0; lift_set[i][j] != 0; j++){ +- if(Zc == lift_set[i][j]){ +- lift_index = i; +- break; +- } +- } +- } +- +- int *h = NULL; +- switch(lift_index){ +- case 0: +- h = (BG == 1)? h_base_0:h_base_8; +- break; +- case 1: +- h = (BG == 1)? h_base_1:h_base_9; +- break; +- case 2: +- h = (BG == 1)? h_base_2:h_base_10; +- break; +- case 3: +- h = (BG == 1)? h_base_3:h_base_11; +- break; +- case 4: +- h = (BG == 1)? h_base_4:h_base_12; +- break; +- case 5: +- h = (BG == 1)? h_base_5:h_base_13; +- break; +- case 6: +- h = (BG == 1)? h_base_6:h_base_14; +- break; +- case 7: +- h = (BG == 1)? h_base_7:h_base_15; +- break; +- } +- /* pack BG in compact graph */ +- read_BG(BG, h, row, col); +- +- +- int memorySize_h_compact1 = row * compact_col * sizeof(h_element); +- int memorySize_h_compact2 = compact_row * col * sizeof(h_element); + +-// cpu +- int memorySize_hard_decision = col * Zc * sizeof(unsigned char) * MC; +- +- + // alloc memory + unsigned char *hard_decision = (unsigned char*)p_out; +- + // gpu + int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; +- int memorySize_dt_cuda = row * Zc * col * sizeof(char) * MC; +- +- +-// alloc memory +- char *dev_llr; +- char *dev_dt; +- char *dev_const_llr; +- unsigned char *dev_tmp; ++ cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); ++ cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); + +- cudaCheck( cudaMalloc((void **)&dev_tmp, memorySize_hard_decision) ); +- cudaCheck( cudaMalloc((void **)&dev_llr, memorySize_llr_cuda) ); +- cudaCheck( cudaMalloc((void **)&dev_const_llr, memorySize_llr_cuda) ); +- cudaCheck( cudaMalloc((void **)&dev_dt, memorySize_dt_cuda) ); +- +-// memcpy host to device +- +- cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, h_compact1, memorySize_h_compact1) ); +- cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, h_compact2, memorySize_h_compact2) ); +- cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); +-start_meas(time_decoder); +- cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); +- +- + // Define CUDA kernel dimension + int blockSizeX = Zc; + dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks +@@ -488,61 +518,35 @@ start_meas(time_decoder); + dim3 dimGridKernel2(col, MC, 1); + dim3 dimBlockKernel2(blockSizeX, 1, 1); + cudaDeviceSynchronize(); +- +- cudaEvent_t start, end; +- float time; +- +- warmup<<>>(); +- warmup<<>>(); + +- +- cudaEventCreate(&start); +- cudaEventCreate(&end); +- cudaEventRecord(start, 0); +- +-// cudaProfilerStart(); +- + // lauch kernel ++ + for(int ii = 0; ii < MAX_ITERATION; ii++){ + // first kernel + if(ii == 0){ + ldpc_cnp_kernel_1st_iter + <<>> +- (dev_llr, dev_dt, BG, row, col, Zc); ++ (/*dev_llr,*/ BG, row, col, Zc); + }else{ + ldpc_cnp_kernel + <<>> +- (dev_llr, dev_dt, BG, row, col, Zc); ++ (/*dev_llr,*/ BG, row, col, Zc); + } +- + // second kernel +- +- ldpc_vnp_kernel_normal +- <<>> +- (dev_llr, dev_dt, dev_const_llr, BG, row, col, Zc); +- ++ ldpc_vnp_kernel_normal ++ <<>> ++ // (dev_llr, dev_const_llr,BG, row, col, Zc); ++ (BG, row, col, Zc); + } ++ + int pack = (block_length/128)+1; + dim3 pack_block(pack, MC, 1); +- pack_decoded_bit<<>>(dev_llr, dev_tmp, col, Zc); +- +- +- cudaEventRecord(end, 0); +- cudaEventSynchronize(end); +- cudaEventElapsedTime(&time, start, end); ++ pack_decoded_bit<<>>(/*dev_llr,*/ /*dev_tmp,*/ col, Zc); + +- +- //cudaCheck( cudaMemcpy((*)hard_decision, (const void*)dev_tmp, memorySize_hard_decision, cudaMemcpyDeviceToHost) ); +- cudaCheck( cudaMemcpy((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char), cudaMemcpyDeviceToHost) ); ++ cudaCheck( cudaMemcpyFromSymbol((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char)) ); + cudaDeviceSynchronize(); +-stop_meas(time_decoder); +- +- cudaCheck( cudaFree(dev_llr) ); +- cudaCheck( cudaFree(dev_dt) ); +- cudaCheck( cudaFree(dev_const_llr) ); +- cudaCheck( cudaFree(dev_tmp) ); + +- //free(hard_decision); ++ + return MAX_ITERATION; + + } +diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h +index 0e78f98..c8868f0 100644 +--- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h ++++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h +@@ -23,4 +23,10 @@ + + int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder); + ++void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length); ++ ++void warmup_for_GPU(void); ++ ++void set_compact_BG(int Zc, short BG); ++ + #endif diff --git a/targets/ARCH/rfsimulator/new_channel_sim.c b/targets/ARCH/rfsimulator/new_channel_sim.c new file mode 100644 index 0000000000..0501babd20 --- /dev/null +++ b/targets/ARCH/rfsimulator/new_channel_sim.c @@ -0,0 +1,108 @@ +/* +* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +* contributor license agreements. See the NOTICE file distributed with +* this work for additional information regarding copyright ownership. +* The OpenAirInterface Software Alliance licenses this file to You under +* the OAI Public License, Version 1.1 (the "License"); you may not use this file +* except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.openairinterface.org/?page_id=698 +* +* Author and copyright: Laurent Thomas, open-cells.com +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*------------------------------------------------------------------------------- +* For more information about the OpenAirInterface (OAI) Software Alliance: +* contact@openairinterface.org +*/ + + +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include + +// Ziggurat +static double wn[128],fn[128]; +static uint32_t iz,jz,jsr=123456789,kn[128]; +static int32_t hz; +#define SHR3 (jz=jsr, jsr^=(jsr<<13),jsr^=(jsr>>17),jsr^=(jsr<<5),jz+jsr) +#define UNI (0.5+(signed) SHR3 * 0.2328306e-9) + +double nfix(void) { + const double r = 3.442620; + static double x, y; + + for (;;) { + x=hz * wn[iz]; + + if (iz==0) { + do { + x = - 0.2904764 * log (UNI); + y = - log (UNI); + } while (y+y < x*x); + + return (hz>0)? r+x : -r-x; + } + + if (fn[iz]+UNI*(fn[iz-1]-fn[iz])10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + enable_measurement_reports = "yes"; + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.199/24"; + + ENB_INTERFACE_NAME_FOR_S1U = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1U = "192.168.18.199/24"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + + ENB_IPV4_ADDRESS_FOR_X2C = "192.168.18.199/24"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="debug"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 160; + puCch10xSnr = 160; + } +); + +THREAD_STRUCT = ( + { + parallel_config = "PARALLEL_RU_L1_TRX_SPLITaaaaaa"; + worker_config = "ENABLE"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 118; + eNB_instances = [0]; + clock_src = "external"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf new file mode 100644 index 0000000000..b63939add2 --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf @@ -0,0 +1,293 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 31; //0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=13 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 0; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=1,L=13 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57) + initialDLBWPstartSymbolAndLength_3 = 57; //43; //57; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -100; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 5; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; #0x80; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; //8; //7; + nrofDownlinkSymbols = 6; //0; //6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; //0; //4; + + ssPBCH_BlockPower = -25; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.18.199"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.198/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.18.198/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.18.198/24"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + clock_src = "external"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + From 82df0e51b92839888109688f5d4b2eae08a11d14 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 10 Aug 2020 15:19:53 +0200 Subject: [PATCH 53/70] updated tables and 64qam mod --- cmake_targets/CMakeLists.txt | 1 + openair1/PHY/INIT/nr_init.c | 1 + openair1/PHY/MODULATION/nr_modulation.c | 113 ++++++++++++++++++------ openair1/PHY/NR_REFSIG/nr_mod_table.h | 11 ++- openair1/PHY/NR_REFSIG/nr_refsig.h | 2 + openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 2 +- openair1/SIMULATION/NR_PHY/dlsim.c | 33 +++---- 7 files changed, 116 insertions(+), 47 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 0b60172747..23490ce9f6 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1543,6 +1543,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/scrambling_luts.c + ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gen_mod_table.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 9e095d5ab5..136092f2d4 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -132,6 +132,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } } + nr_generate_modulation_table(); nr_init_pdcch_dmrs(gNB, cfg->cell_config.phy_cell_id.value); nr_init_pbch_interleaver(gNB->nr_pbch_interleaver); //PDSCH DMRS init diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index ee880f8c2a..dc3934ffca 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -34,64 +34,123 @@ void nr_modulation(uint32_t *in, int32_t* nr_mod_table32; int32_t* out32 = (int32_t*) out; uint8_t* in_bytes = (uint8_t*) in; + uint64_t* in64 = (uint64_t*) in; + int64_t* out64 = (int64_t*) out; uint8_t idx; - uint16_t u = 1; - uint8_t shift_lut[3] = {0, 2, 4}; + uint32_t i,j; + uint32_t bit_cnt; + uint64_t x,x1,x2; -#if defined(__SSE2__) +#if defined(__AVX2__) + uint16_t *in_2bytes = (uint16_t*) in; + __m256i *nr_mod_table256; + __m256i *out256; +#elif defined(__SSE2__) __m128i *nr_mod_table128; __m128i *out128; - __m64 *nr_mod_table64; - __m64 *out64; #endif offset = (mod_order==2)? NR_MOD_TABLE_QPSK_OFFSET : (mod_order==4)? NR_MOD_TABLE_QAM16_OFFSET : \ (mod_order==6)? NR_MOD_TABLE_QAM64_OFFSET: (mod_order==8)? NR_MOD_TABLE_QAM256_OFFSET : 0; - LOG_D(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); + LOG_I(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); switch (mod_order) { case 6: - nr_mod_table32 = (int32_t*) nr_mod_table; - for (int i=0; i>((i*mod_order)&0x1f)) & mask); - if ((((i+1)*mod_order)>32*u) && (i!=0)) - idx |= (in[(i*mod_order/32)+1]<>12)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x>>24)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x>>36)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x>>48)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x2 = (x>>60); + x = in64[i*3+1]; + x2 |= x<<4; + x1 = x2&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>12)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>24)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>36)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>48)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x2 = ((x>>56)&0xf0) | (x2>>60); + x = in64[i*3+2]; + x2 |= x<<8; + x1 = x2&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>12)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>24)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>36)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x2>>48)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x2 = ((x>>52)&0xff0) | (x2>>60); + out64[j++] = nr_64qam_mod_table[x2]; + } + i *= 24; + bit_cnt = i * 8; + while (bit_cnt < length) { + x = *((uint32_t*)(in_bytes+i)); + x1 = x&4095; + out64[j++] = nr_64qam_mod_table[x1]; + x1 = (x>>12)&4095; + out64[j++] = nr_64qam_mod_table[x1]; + i += 3; + bit_cnt += 24; } return; - + case 8: nr_mod_table32 = (int32_t*) nr_mod_table; - for (int i=0; i>((i*mod_order)&0x1f)) & mask); diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index f644e86359..d42f211e8e 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -28,10 +28,15 @@ #define NR_MOD_TABLE_QAM16_OFFSET 7 #define NR_MOD_TABLE_QAM64_OFFSET 23 #define NR_MOD_TABLE_QAM256_OFFSET 87 -short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = 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+short nr_qpsk_mod_table[8] = {16384,16384,-16384,16384,16384,-16384,-16384,-16384}; +#if defined(__AVX2__) +__m256i nr_qpsk_2byte_mod_table[65536]; +#elif defined(__SSE2__) +__m128i nr_qpsk_byte_mod_table[2048]; +#endif -short nr_qpsk_byte_mod_table[2048] = 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+int64_t nr_16qam_byte_mod_table[1024]; -short nr_qam16_byte_mod_table[1024] = {7327,7327,7327,7327,-7327,7327,7327,7327,7327,-7327,7327,7327,-7327,-7327,7327,7327,21981,7327,7327,7327,-21981,7327,7327,7327,21981,-7327,7327,7327,-21981,-7327,7327,7327,7327,21981,7327,7327,-7327,21981,7327,7327,7327,-21981,7327,7327,-7327,-21981,7327,7327,21981,21981,7327,7327,-21981,21981,7327,7327,21981,-21981,7327,7327,-21981,-21981,7327,7327,7327,7327,-7327,7327,-7327,7327,-7327,7327,7327,-7327,-7327,7327,-7327,-7327,-7327,7327,21981,7327,-7327,7327,-21981,7327,-7327,7327,21981,-7327,-7327,7327,-21981,-7327,-7327,7327,7327,21981,-7327,7327,-7327,21981,-7327,7327,7327,-21981,-7327,7327,-7327,-21981,-7327,7327,21981,21981,-7327,7327,-21981,21981,-7327,7327,21981,-21981,-7327,7327,-21981,-21981,-7327,7327,7327,7327,7327,-7327,-7327,7327,7327,-7327,7327,-7327,7327,-7327,-7327,-7327,7327,-7327,21981,7327,7327,-7327,-21981,7327,7327,-7327,21981,-7327,7327,-7327,-21981,-7327,7327,-7327,7327,21981,7327,-7327,-7327,21981,7327,-7327,7327,-21981,7327,-7327,-7327,-21981,7327,-7327,21981,21981,7327,-7327,-21981,21981,7327,-7327,21981,-21981,7327,-7327,-21981,-21981,7327,-7327,7327,7327,-7327,-7327,-7327,7327,-7327,-7327,7327,-7327,-7327,-7327,-7327,-7327,-7327,-7327,21981,7327,-7327,-7327,-21981,7327,-7327,-7327,21981,-7327,-7327,-7327,-21981,-7327,-7327,-7327,7327,21981,-7327,-7327,-7327,21981,-7327,-7327,7327,-21981,-7327,-7327,-7327,-21981,-7327,-7327,21981,21981,-7327,-7327,-21981,21981,-7327,-7327,21981,-21981,-7327,-7327,-21981,-21981,-7327,-7327,7327,7327,21981,7327,-7327,7327,21981,7327,7327,-7327,21981,7327,-7327,-7327,21981,7327,21981,7327,21981,7327,-21981,7327,21981,7327,21981,-7327,21981,7327,-21981,-7327,21981,7327,7327,21981,21981,7327,-7327,21981,21981,7327,7327,-21981,21981,7327,-7327,-21981,21981,7327,21981,21981,21981,7327,-21981,21981,21981,7327,21981,-21981,21981,7327,-21981,-21981,21981,7327,7327,7327,-21981,7327,-7327,7327,-21981,7327,7327,-7327,-21981,7327,-7327,-7327,-21981,7327,21981,7327,-21981,7327,-21981,7327,-21981,7327,21981,-7327,-21981,7327,-21981,-7327,-21981,7327,7327,21981,-21981,7327,-7327,21981,-21981,7327,7327,-21981,-21981,7327,-7327,-21981,-21981,7327,21981,21981,-21981,7327,-21981,21981,-21981,7327,21981,-21981,-21981,7327,-21981,-21981,-21981,7327,7327,7327,21981,-7327,-7327,7327,21981,-7327,7327,-7327,21981,-7327,-7327,-7327,21981,-7327,21981,7327,21981,-7327,-21981,7327,21981,-7327,21981,-7327,21981,-7327,-21981,-7327,21981,-7327,7327,21981,21981,-7327,-7327,21981,21981,-7327,7327,-21981,21981,-7327,-7327,-21981,21981,-7327,21981,21981,21981,-7327,-21981,21981,21981,-7327,21981,-21981,21981,-7327,-21981,-21981,21981,-7327,7327,7327,-21981,-7327,-7327,7327,-21981,-7327,7327,-7327,-21981,-7327,-7327,-7327,-21981,-7327,21981,7327,-21981,-7327,-21981,7327,-21981,-7327,21981,-7327,-21981,-7327,-21981,-7327,-21981,-7327,7327,21981,-21981,-7327,-7327,21981,-21981,-7327,7327,-21981,-21981,-7327,-7327,-21981,-21981,-7327,21981,21981,-21981,-7327,-21981,21981,-21981,-7327,21981,-21981,-21981,-7327,-21981,-21981,-21981,-7327,7327,7327,7327,21981,-7327,7327,7327,21981,7327,-7327,7327,21981,-7327,-7327,7327,21981,21981,7327,7327,21981,-21981,7327,7327,21981,21981,-7327,7327,21981,-21981,-7327,7327,21981,7327,21981,7327,21981,-7327,21981,7327,21981,7327,-21981,7327,21981,-7327,-21981,7327,21981,21981,21981,7327,21981,-21981,21981,7327,21981,21981,-21981,7327,21981,-21981,-21981,7327,21981,7327,7327,-7327,21981,-7327,7327,-7327,21981,7327,-7327,-7327,21981,-7327,-7327,-7327,21981,21981,7327,-7327,21981,-21981,7327,-7327,21981,21981,-7327,-7327,21981,-21981,-7327,-7327,21981,7327,21981,-7327,21981,-7327,21981,-7327,21981,7327,-21981,-7327,21981,-7327,-21981,-7327,21981,21981,21981,-7327,21981,-21981,21981,-7327,21981,21981,-21981,-7327,21981,-21981,-21981,-7327,21981,7327,7327,7327,-21981,-7327,7327,7327,-21981,7327,-7327,7327,-21981,-7327,-7327,7327,-21981,21981,7327,7327,-21981,-21981,7327,7327,-21981,21981,-7327,7327,-21981,-21981,-7327,7327,-21981,7327,21981,7327,-21981,-7327,21981,7327,-21981,7327,-21981,7327,-21981,-7327,-21981,7327,-21981,21981,21981,7327,-21981,-21981,21981,7327,-21981,21981,-21981,7327,-21981,-21981,-21981,7327,-21981,7327,7327,-7327,-21981,-7327,7327,-7327,-21981,7327,-7327,-7327,-21981,-7327,-7327,-7327,-21981,21981,7327,-7327,-21981,-21981,7327,-7327,-21981,21981,-7327,-7327,-21981,-21981,-7327,-7327,-21981,7327,21981,-7327,-21981,-7327,21981,-7327,-21981,7327,-21981,-7327,-21981,-7327,-21981,-7327,-21981,21981,21981,-7327,-21981,-21981,21981,-7327,-21981,21981,-21981,-7327,-21981,-21981,-21981,-7327,-21981,7327,7327,21981,21981,-7327,7327,21981,21981,7327,-7327,21981,21981,-7327,-7327,21981,21981,21981,7327,21981,21981,-21981,7327,21981,21981,21981,-7327,21981,21981,-21981,-7327,21981,21981,7327,21981,21981,21981,-7327,21981,21981,21981,7327,-21981,21981,21981,-7327,-21981,21981,21981,21981,21981,21981,21981,-21981,21981,21981,21981,21981,-21981,21981,21981,-21981,-21981,21981,21981,7327,7327,-21981,21981,-7327,7327,-21981,21981,7327,-7327,-21981,21981,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+int64_t nr_64qam_mod_table[4096]; #endif diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h index 1bf2ef4fb2..786fb2af35 100644 --- a/openair1/PHY/NR_REFSIG/nr_refsig.h +++ b/openair1/PHY/NR_REFSIG/nr_refsig.h @@ -53,6 +53,8 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, void init_scrambling_luts(void); +void nr_generate_modulation_table(void); + extern __m64 byte2m64_re[256]; extern __m64 byte2m64_im[256]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 23466132d6..ac5a126276 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -150,7 +150,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; uint8_t Qm = rel15->qamModOrder[0]; uint32_t encoded_length = nb_re*Qm; - int16_t mod_dmrs[n_dmrs<<1]; + int16_t mod_dmrs[n_dmrs<<1] __attribute__ ((aligned(256))); /// CRC, coding, interleaving and rate matching AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n"); diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 90aa3f6333..64ab482db8 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -926,22 +926,6 @@ int main(int argc, char **argv) printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %d bits/slot\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials,effRate,effRate/TBS*100,TBS); printf("\n"); - if (n_trials == 1) { - - LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1); - if (UE->frame_parms.nb_antennas_rx>1) - LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1); - LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1); - write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1); - break; - } - - //if ((float)n_errors/(float)n_trials <= target_error_rate) { - if (effRate >= (eff_tp_check*TBS)) { - printf("PDSCH test OK\n"); - break; - } - if (print_perf==1) { printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n", 1000>>*scc->ssbSubcarrierSpacing,dlsch_config.rbSize,dlsch_config.mcsIndex[0], @@ -992,6 +976,23 @@ int main(int argc, char **argv) printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC"); */ } + + if (n_trials == 1) { + + LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1); + if (UE->frame_parms.nb_antennas_rx>1) + LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1); + LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1); + write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1); + break; + } + + //if ((float)n_errors/(float)n_trials <= target_error_rate) { + if (effRate >= (eff_tp_check*TBS)) { + printf("PDSCH test OK\n"); + break; + } + snrRun++; } // NSR From e2afb8662ed82aec23550640b67159099c8086fa Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 10 Aug 2020 15:21:59 +0200 Subject: [PATCH 54/70] new table generator --- openair1/PHY/NR_REFSIG/nr_gen_mod_table.c | 73 +++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 openair1/PHY/NR_REFSIG/nr_gen_mod_table.c diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c new file mode 100644 index 0000000000..4adcfd02d9 --- /dev/null +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c @@ -0,0 +1,73 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +#include "nr_refsig.h" +#include "nr_mod_table.h" +#include + +void nr_generate_modulation_table() { + float sqrt2 = 0.70711; + float sqrt10 = 0.31623; + float sqrt42 = 0.15430; + float sqrt170 = 0.076696; + float val = 32768.0; + uint32_t i,j; + short* table; + + //QPSK m128 + for (i=0; i<256; i++) { + for (j=0; j<4; j++) { + nr_qpsk_byte_mod_table[i*8+(j*2)] = (short)(1-2*((i>>(j*2))&1))*val*sqrt2*sqrt2; + nr_qpsk_byte_mod_table[i*8+(j*2)+1] = (short)(1-2*((i>>(j*2+1))&1))*val*sqrt2*sqrt2; + //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]); + } + } + + //QPSK m256 + table = (short*) nr_qpsk_2byte_mod_table; + for (i=0; i<65536; i++) { + for (j=0; j<8; j++) { + table[i*16+(j*2)] = (short)(1-2*((i>>(j*2))&1))*val*sqrt2*sqrt2; + table[i*16+(j*2)+1] = (short)(1-2*((i>>(j*2+1))&1))*val*sqrt2*sqrt2; + //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]); + } + } + + //16QAM + for (i=0; i<256; i++) { + for (j=0; j<2; j++) { + nr_16qam_byte_mod_table[i*4+(j*2)] = (short)((1-2*((i>>(j*4))&1))*(2-(1-2*((i>>(j*4+2))&1))))*val*sqrt10*sqrt2; + nr_16qam_byte_mod_table[i*4+(j*2)+1] = (short)((1-2*((i>>(j*4+1))&1))*(2-(1-2*((i>>(j*4+3))&1))))*val*sqrt10*sqrt2; + //printf("%d j%d\n",nr_16qam_byte_mod_table[i*4+(j*2)],nr_16qam_byte_mod_table[i*4+(j*2)+1]); + } + } + + //64QAM + table = (short*) nr_64qam_mod_table; + for (i=0; i<4096; i++) { + for (j=0; j<2; j++) { + table[i*4+(j*2)] = (short)((1-2*((i>>(j*6))&1))*(4-(1-2*((i>>(j*6+2))&1))*(2-(1-2*((i>>(j*6+4))&1)))))*val*sqrt42*sqrt2; + table[i*4+(j*2)+1] = (short)((1-2*((i>>(j*6+1))&1))*(4-(1-2*((i>>(j*6+3))&1))*(2-(1-2*((i>>(j*6+5))&1)))))*val*sqrt42*sqrt2; + //printf("%d j%d\n",table[i*4+(j*2)],table[i*4+(j*2)+1]); + } + } +} + From 5e7ce26c10843427f8a78690fb81ced3d3677965 Mon Sep 17 00:00:00 2001 From: Sakthi Date: Mon, 10 Aug 2020 19:14:14 +0200 Subject: [PATCH 55/70] more additions --- openair1/PHY/MODULATION/nr_modulation.c | 4 +--- openair1/PHY/NR_REFSIG/nr_gen_mod_table.c | 29 ++++++++++++++++------- openair1/PHY/NR_REFSIG/nr_mod_table.h | 5 +++- openair1/PHY/NR_TRANSPORT/nr_pbch.c | 10 ++++---- 4 files changed, 31 insertions(+), 17 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index dc3934ffca..8905dcca38 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -22,8 +22,6 @@ #include "nr_modulation.h" #include "PHY/NR_REFSIG/nr_mod_table.h" -extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT]; - void nr_modulation(uint32_t *in, uint32_t length, uint16_t mod_order, @@ -114,7 +112,7 @@ void nr_modulation(uint32_t *in, return; case 8: - nr_mod_table32 = (int32_t*) nr_mod_table; + nr_mod_table32 = (int32_t*) nr_256qam_mod_table; for (i=0; i>(j*2))&1))*val*sqrt2*sqrt2; - nr_qpsk_byte_mod_table[i*8+(j*2)+1] = (short)(1-2*((i>>(j*2+1))&1))*val*sqrt2*sqrt2; - //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]); - } - } +short nr_qpsk_mod_table[8] = {16384,16384,-16384,16384,16384,-16384,-16384,-16384}; +#if defined(__AVX2__) //QPSK m256 table = (short*) nr_qpsk_2byte_mod_table; for (i=0; i<65536; i++) { @@ -50,6 +44,18 @@ void nr_generate_modulation_table() { //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]); } } +#elif defined(__SSE2__) + + //QPSK m128 + table = (short*) nr_qpsk_byte_mod_table; + for (i=0; i<256; i++) { + for (j=0; j<4; j++) { + table[i*8+(j*2)] = (short)(1-2*((i>>(j*2))&1))*val*sqrt2*sqrt2; + table[i*8+(j*2)+1] = (short)(1-2*((i>>(j*2+1))&1))*val*sqrt2*sqrt2; + //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]); + } + } +#endif //16QAM for (i=0; i<256; i++) { @@ -69,5 +75,12 @@ void nr_generate_modulation_table() { //printf("%d j%d\n",table[i*4+(j*2)],table[i*4+(j*2)+1]); } } + + //256QAM + table = (short*) nr_256qam_mod_table; + for (i=0; i<256; i++) { + table[i*2] = (short)((1-2*(i&1))*(8-(1-2*((i>>2)&1))*(4-(1-2*((i>>4)&1))*(2-(1-2*((i>>6)&1))))))*val*sqrt170*sqrt2; + table[i*2+1] = (short)((1-2*((i>>1)&1))*(8-(1-2*((i>>3)&1))*(4-(1-2*((i>>5)&1))*(2-(1-2*((i>>7)&1))))))*val*sqrt170*sqrt2; + } } diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index d42f211e8e..4722ad7b7a 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -28,7 +28,8 @@ #define NR_MOD_TABLE_QAM16_OFFSET 7 #define NR_MOD_TABLE_QAM64_OFFSET 23 #define NR_MOD_TABLE_QAM256_OFFSET 87 -short nr_qpsk_mod_table[8] = {16384,16384,-16384,16384,16384,-16384,-16384,-16384}; + +short nr_qpsk_mod_table[8]; #if defined(__AVX2__) __m256i nr_qpsk_2byte_mod_table[65536]; @@ -39,4 +40,6 @@ __m128i nr_qpsk_byte_mod_table[2048]; int64_t nr_16qam_byte_mod_table[1024]; int64_t nr_64qam_mod_table[4096]; + +int32_t nr_256qam_mod_table[512]; #endif diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index bc33d93811..13dd65d90e 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -40,7 +40,7 @@ //#define DEBUG_PBCH_ENCODING //#define DEBUG_PBCH_DMRS -extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT]; +extern short nr_qpsk_mod_table[8]; uint8_t nr_pbch_payload_interleaving_pattern[32] = {16, 23, 18, 17, 8, 30, 10, 6, 24, 7, 0, 5, 3, 2, 1, 4, 9, 11, 12, 13, 14, 15, 19, 20, 21, 22, 25, 26, 27, 28, 29, 31 @@ -62,8 +62,8 @@ int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs, /// QPSK modulation for (int m=0; m>5])>>((m<<1)&0x1f))&1)<<1) ^ (((gold_pbch_dmrs[((m<<1)+1)>>5])>>(((m<<1)+1)&0x1f))&1); - mod_dmrs[m<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - mod_dmrs[(m<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; + mod_dmrs[m<<1] = nr_qpsk_mod_table[idx<<1]; + mod_dmrs[(m<<1)+1] = nr_qpsk_mod_table[(idx<<1) + 1]; #ifdef DEBUG_PBCH_DMRS printf("m %d idx %d gold seq %d b0-b1 %d-%d mod_dmrs %d %d\n", m, idx, gold_pbch_dmrs[(m<<1)>>5], (((gold_pbch_dmrs[(m<<1)>>5])>>((m<<1)&0x1f))&1), (((gold_pbch_dmrs[((m<<1)+1)>>5])>>(((m<<1)+1)&0x1f))&1), mod_dmrs[(m<<1)], mod_dmrs[(m<<1)+1]); @@ -324,8 +324,8 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, /// QPSK modulation for (int i=0; i>1; i++) { idx = (((pbch->pbch_e[(i<<1)>>5]>>((i<<1)&0x1f))&1)<<1) ^ ((pbch->pbch_e[((i<<1)+1)>>5]>>(((i<<1)+1)&0x1f))&1); - mod_pbch_e[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - mod_pbch_e[(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1)+1]; + mod_pbch_e[i<<1] = nr_qpsk_mod_table[idx<<1]; + mod_pbch_e[(i<<1)+1] = nr_qpsk_mod_table[(idx<<1)+1]; #ifdef DEBUG_PBCH printf("i %d idx %d mod_pbch %d %d\n", i, idx, mod_pbch_e[2*i], mod_pbch_e[2*i+1]); #endif From 76f7840961e3d8ccfa521e14f03120a40b4d9882 Mon Sep 17 00:00:00 2001 From: Sakthi Date: Mon, 10 Aug 2020 19:22:53 +0200 Subject: [PATCH 56/70] bug fixes --- openair1/PHY/MODULATION/nr_modulation.c | 2 +- openair1/PHY/NR_REFSIG/nr_gen_mod_table.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index 8905dcca38..c1cabfb8d8 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -51,7 +51,7 @@ void nr_modulation(uint32_t *in, offset = (mod_order==2)? NR_MOD_TABLE_QPSK_OFFSET : (mod_order==4)? NR_MOD_TABLE_QAM16_OFFSET : \ (mod_order==6)? NR_MOD_TABLE_QAM64_OFFSET: (mod_order==8)? NR_MOD_TABLE_QAM256_OFFSET : 0; - LOG_I(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); + LOG_D(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); switch (mod_order) { diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c index 0f8111b6b0..f7ec99e8e8 100644 --- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c @@ -58,10 +58,11 @@ short nr_qpsk_mod_table[8] = {16384,16384,-16384,16384,16384,-16384,-16384,-1638 #endif //16QAM + table = (short*) nr_16qam_byte_mod_table; for (i=0; i<256; i++) { for (j=0; j<2; j++) { - nr_16qam_byte_mod_table[i*4+(j*2)] = (short)((1-2*((i>>(j*4))&1))*(2-(1-2*((i>>(j*4+2))&1))))*val*sqrt10*sqrt2; - nr_16qam_byte_mod_table[i*4+(j*2)+1] = (short)((1-2*((i>>(j*4+1))&1))*(2-(1-2*((i>>(j*4+3))&1))))*val*sqrt10*sqrt2; + table[i*4+(j*2)] = (short)((1-2*((i>>(j*4))&1))*(2-(1-2*((i>>(j*4+2))&1))))*val*sqrt10*sqrt2; + table[i*4+(j*2)+1] = (short)((1-2*((i>>(j*4+1))&1))*(2-(1-2*((i>>(j*4+3))&1))))*val*sqrt10*sqrt2; //printf("%d j%d\n",nr_16qam_byte_mod_table[i*4+(j*2)],nr_16qam_byte_mod_table[i*4+(j*2)+1]); } } From 10d52466a8d4b34bb8f74b9e67f8f655236d38d2 Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Thu, 13 Aug 2020 14:15:54 +0800 Subject: [PATCH 57/70] Fix CUDA diff with develop --- cmake_targets/build_oai | 4 +- openair1/PHY/CODING/TESTBENCH/ldpctest.c | 8 - .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu | 210 ------------------ .../nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h | 5 +- 4 files changed, 4 insertions(+), 223 deletions(-) diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 88b8811575..a7adc33db3 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -701,8 +701,8 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim - simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" - # simlist="ldpctest" + # simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" + simlist="ldpctest" for f in $simlist ; do compilations \ phy_simulators $f \ diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index e67ed222ee..72d85b1b14 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -402,17 +402,9 @@ int test_ldpc(short No_iteration, start_meas(time_decoder); #ifdef CUDA_FLAG if(run_cuda){ -<<<<<<< HEAD n_iter = nrLDPC_decoder_LYC(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length, time_decoder); } else{ -======= - printf("***********run ldpc by cuda\n"); - n_iter = nrLDPC_decoder_LYC(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length, time_decoder); - } - else{ - printf("**************run ldpc by cpu\n"); ->>>>>>> origin/develop // decode the sequence // decoder supports BG2, Z=128 & 256 //esimated_output=ldpc_decoder(channel_output_fixed, block_length, No_iteration, (double)((float)nom_rate/(float)denom_rate)); diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu index 58c6afbe6e..931d500338 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu @@ -32,11 +32,7 @@ #include "bgs/BG2_I6" #include "bgs/BG2_I7" -<<<<<<< HEAD #define MAX_ITERATION 2 -======= -#define MAX_ITERATION 5 ->>>>>>> origin/develop #define MC 1 #define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } @@ -53,30 +49,21 @@ typedef struct{ char y; short value; } h_element; -<<<<<<< HEAD #include "bgs/BG1_compact_in_C.h" __device__ char dev_const_llr[68*384]; __device__ char dev_dt [46*68*384]; __device__ char dev_llr[68*384]; __device__ unsigned char dev_tmp[68*384]; -======= - ->>>>>>> origin/develop h_element h_compact1 [46*19] = {}; h_element h_compact2 [68*30] = {}; -<<<<<<< HEAD __device__ h_element dev_h_compact1[46*19]; // used in kernel 1 __device__ h_element dev_h_compact2[68*30]; // used in kernel 2 // __device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 // __device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 -======= -__device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 -__device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 ->>>>>>> origin/develop // row and col element count __device__ __constant__ char h_ele_row_bg1_count[46] = { @@ -113,7 +100,6 @@ __global__ void warmup() // warm up gpu for time measurement } -<<<<<<< HEAD extern "C" void warmup_for_GPU(){ @@ -201,11 +187,6 @@ void set_compact_BG(int Zc,short BG){ // Kernel 1 __global__ void ldpc_cnp_kernel_1st_iter(/*char * dev_llr,*/ int BG, int row, int col, int Zc) -======= - -// Kernel 1 -__global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) ->>>>>>> origin/develop { // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp %d\n", threadIdx.x); int iMCW = blockIdx.y; // codeword id @@ -264,11 +245,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, for(int i = 0; i < s; i++){ // v0: Best performance so far. 0.75f is the value of alpha. sq = 1 - 2 * ((Q_sign >> i) & 0x01); -<<<<<<< HEAD R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); -======= - R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); ->>>>>>> origin/develop // write results to global memory h_element_t = dev_h_compact1[i*row+iBlkRow]; int addr_temp = offsetR + h_element_t.y * row * Zc; @@ -278,11 +255,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, } // Kernel_1 -<<<<<<< HEAD __global__ void ldpc_cnp_kernel(/*char * dev_llr, char * dev_dt,*/ int BG, int row, int col, int Zc) -======= -__global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) ->>>>>>> origin/develop { // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp\n"); int iMCW = blockIdx.y; @@ -342,11 +315,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, // The 2nd recursion for(int i = 0; i < s; i ++){ sq = 1 - 2 * ((Q_sign >> i) & 0x01); -<<<<<<< HEAD R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); -======= - R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); ->>>>>>> origin/develop // write results to global memory @@ -359,11 +328,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, // Kernel 2: VNP processing __global__ void -<<<<<<< HEAD ldpc_vnp_kernel_normal(/*char * dev_llr, char * dev_dt, char * dev_const_llr,*/ int BG, int row, int col, int Zc) -======= -ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int BG, int row, int col, int Zc) ->>>>>>> origin/develop { int iMCW = blockIdx.y; int iBlkCol = blockIdx.x; @@ -403,11 +368,7 @@ ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int } -<<<<<<< HEAD __global__ void pack_decoded_bit(/*char *dev, unsigned char *host,*/ int col, int Zc) -======= -__global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc) ->>>>>>> origin/develop { __shared__ unsigned char tmp[128]; int iMCW = blockIdx.y; @@ -415,25 +376,15 @@ __global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc int btid = threadIdx.x; tmp[btid] = 0; -<<<<<<< HEAD if(dev_llr[tid] < 0){ -======= - if(dev[tid] < 0){ ->>>>>>> origin/develop tmp[btid] = 1 << (7-(btid&7)); } __syncthreads(); if(threadIdx.x < 16){ -<<<<<<< HEAD dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; for(int i = 0; i < 8; i++){ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; -======= - host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; - for(int i = 0; i < 8; i++){ - host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; ->>>>>>> origin/develop } } } @@ -510,7 +461,6 @@ void read_BG(int BG, int *h, int row, int col) */ } -<<<<<<< HEAD extern "C" void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length){ @@ -532,28 +482,17 @@ void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8 cudaDeviceSynchronize(); } -======= ->>>>>>> origin/develop extern "C" int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder) { -<<<<<<< HEAD -======= - // alloc mem - //unsigned char *decision = (unsigned char*)p_out; ->>>>>>> origin/develop uint16_t Zc = p_decParams->Z; uint8_t BG = p_decParams->BG; uint8_t numMaxIter = p_decParams->numMaxIter; e_nrLDPC_outMode outMode = p_decParams->outMode; -<<<<<<< HEAD cudaError_t cudaStatus; -======= - ->>>>>>> origin/develop uint8_t row,col; if(BG == 1){ row = 46; @@ -563,7 +502,6 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8 row = 42; col = 52; } -<<<<<<< HEAD // alloc memory unsigned char *hard_decision = (unsigned char*)p_out; @@ -572,98 +510,6 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8 cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); -======= - int compact_row = 30, compact_col = 19, lift_index=0;; - if(BG==2){compact_row = 10, compact_col = 23;} - - short lift_set[][9] = { - {2,4,8,16,32,64,128,256}, - {3,6,12,24,48,96,192,384}, - {5,10,20,40,80,160,320}, - {7,14,28,56,112,224}, - {9,18,36,72,144,288}, - {11,22,44,88,176,352}, - {13,26,52,104,208}, - {15,30,60,120,240}, - {0} - }; - - for(int i = 0; lift_set[i][0] != 0; i++){ - for(int j = 0; lift_set[i][j] != 0; j++){ - if(Zc == lift_set[i][j]){ - lift_index = i; - break; - } - } - } - - int *h = NULL; - switch(lift_index){ - case 0: - h = (BG == 1)? h_base_0:h_base_8; - break; - case 1: - h = (BG == 1)? h_base_1:h_base_9; - break; - case 2: - h = (BG == 1)? h_base_2:h_base_10; - break; - case 3: - h = (BG == 1)? h_base_3:h_base_11; - break; - case 4: - h = (BG == 1)? h_base_4:h_base_12; - break; - case 5: - h = (BG == 1)? h_base_5:h_base_13; - break; - case 6: - h = (BG == 1)? h_base_6:h_base_14; - break; - case 7: - h = (BG == 1)? h_base_7:h_base_15; - break; - } - /* pack BG in compact graph */ - read_BG(BG, h, row, col); - - - int memorySize_h_compact1 = row * compact_col * sizeof(h_element); - int memorySize_h_compact2 = compact_row * col * sizeof(h_element); - -// cpu - int memorySize_hard_decision = col * Zc * sizeof(unsigned char) * MC; - - -// alloc memory - unsigned char *hard_decision = (unsigned char*)p_out; - -// gpu - int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; - int memorySize_dt_cuda = row * Zc * col * sizeof(char) * MC; - - -// alloc memory - char *dev_llr; - char *dev_dt; - char *dev_const_llr; - unsigned char *dev_tmp; - - cudaCheck( cudaMalloc((void **)&dev_tmp, memorySize_hard_decision) ); - cudaCheck( cudaMalloc((void **)&dev_llr, memorySize_llr_cuda) ); - cudaCheck( cudaMalloc((void **)&dev_const_llr, memorySize_llr_cuda) ); - cudaCheck( cudaMalloc((void **)&dev_dt, memorySize_dt_cuda) ); - -// memcpy host to device - - cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, h_compact1, memorySize_h_compact1) ); - cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, h_compact2, memorySize_h_compact2) ); - cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); -start_meas(time_decoder); - cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); - - ->>>>>>> origin/develop // Define CUDA kernel dimension int blockSizeX = Zc; dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks @@ -672,33 +518,14 @@ start_meas(time_decoder); dim3 dimGridKernel2(col, MC, 1); dim3 dimBlockKernel2(blockSizeX, 1, 1); cudaDeviceSynchronize(); -<<<<<<< HEAD // lauch kernel -======= - - cudaEvent_t start, end; - float time; - - warmup<<>>(); - warmup<<>>(); - - - cudaEventCreate(&start); - cudaEventCreate(&end); - cudaEventRecord(start, 0); - -// cudaProfilerStart(); - -// lauch kernel ->>>>>>> origin/develop for(int ii = 0; ii < MAX_ITERATION; ii++){ // first kernel if(ii == 0){ ldpc_cnp_kernel_1st_iter <<>> -<<<<<<< HEAD (/*dev_llr,*/ BG, row, col, Zc); }else{ ldpc_cnp_kernel @@ -720,43 +547,6 @@ start_meas(time_decoder); cudaDeviceSynchronize(); -======= - (dev_llr, dev_dt, BG, row, col, Zc); - }else{ - ldpc_cnp_kernel - <<>> - (dev_llr, dev_dt, BG, row, col, Zc); - } - - // second kernel - - ldpc_vnp_kernel_normal - <<>> - (dev_llr, dev_dt, dev_const_llr, BG, row, col, Zc); - - } - int pack = (block_length/128)+1; - dim3 pack_block(pack, MC, 1); - pack_decoded_bit<<>>(dev_llr, dev_tmp, col, Zc); - - - cudaEventRecord(end, 0); - cudaEventSynchronize(end); - cudaEventElapsedTime(&time, start, end); - - - //cudaCheck( cudaMemcpy((*)hard_decision, (const void*)dev_tmp, memorySize_hard_decision, cudaMemcpyDeviceToHost) ); - cudaCheck( cudaMemcpy((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char), cudaMemcpyDeviceToHost) ); - cudaDeviceSynchronize(); -stop_meas(time_decoder); - - cudaCheck( cudaFree(dev_llr) ); - cudaCheck( cudaFree(dev_dt) ); - cudaCheck( cudaFree(dev_const_llr) ); - cudaCheck( cudaFree(dev_tmp) ); - - //free(hard_decision); ->>>>>>> origin/develop return MAX_ITERATION; } diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h index e82c81d28e..c290cedf7d 100644 --- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h +++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h @@ -23,13 +23,12 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder); -<<<<<<< HEAD + void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length); void warmup_for_GPU(void); void set_compact_BG(int Zc, short BG); -======= ->>>>>>> origin/develop + #endif From bc1c69fead360b3f38226c340dd1f2e26d2ecf0e Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Thu, 13 Aug 2020 16:32:09 +0800 Subject: [PATCH 58/70] fix compile issue --- cmake_targets/build_oai | 4 +- patch.diff | 472 ---------------------------------------- 2 files changed, 2 insertions(+), 474 deletions(-) delete mode 100644 patch.diff diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 939f16d9e3..36af9eaee4 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -711,8 +711,8 @@ function main() { if [ "$SIMUS_PHY" = "1" ] ; then echo_info "Compiling physical unitary tests simulators" # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim - # simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" - simlist="ldpctest" + simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" + # simlist="ldpctest" for f in $simlist ; do compilations \ phy_simulators $f \ diff --git a/patch.diff b/patch.diff deleted file mode 100644 index a85f8df37a..0000000000 --- a/patch.diff +++ /dev/null @@ -1,472 +0,0 @@ -diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai -index 88b8811..a7adc33 100755 ---- a/cmake_targets/build_oai -+++ b/cmake_targets/build_oai -@@ -701,8 +701,8 @@ function main() { - if [ "$SIMUS_PHY" = "1" ] ; then - echo_info "Compiling physical unitary tests simulators" - # TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim -- simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" -- # simlist="ldpctest" -+ # simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim" -+ simlist="ldpctest" - for f in $simlist ; do - compilations \ - phy_simulators $f \ -diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c -index 345122c..72d85b1 100644 ---- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c -+++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c -@@ -396,17 +396,15 @@ int test_ldpc(short No_iteration, - decParams.numMaxIter=No_iteration; - decParams.outMode = nrLDPC_outMode_BIT; - //decParams.outMode =nrLDPC_outMode_LLRINT8; -- -- -+ set_compact_BG(Zc,BG); -+ init_LLR_DMA_for_CUDA(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length); - for(j=0;j 1280, 2401 -> 2560 -diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu -index 161b362..931d500 100644 ---- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu -+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu -@@ -32,7 +32,7 @@ - #include "bgs/BG2_I6" - #include "bgs/BG2_I7" - --#define MAX_ITERATION 5 -+#define MAX_ITERATION 2 - #define MC 1 - - #define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); } -@@ -49,13 +49,21 @@ typedef struct{ - char y; - short value; - } h_element; -+#include "bgs/BG1_compact_in_C.h" - -+__device__ char dev_const_llr[68*384]; -+__device__ char dev_dt [46*68*384]; -+__device__ char dev_llr[68*384]; -+__device__ unsigned char dev_tmp[68*384]; - - h_element h_compact1 [46*19] = {}; - h_element h_compact2 [68*30] = {}; - --__device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 --__device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 -+__device__ h_element dev_h_compact1[46*19]; // used in kernel 1 -+__device__ h_element dev_h_compact2[68*30]; // used in kernel 2 -+ -+// __device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1 -+// __device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2 - - // row and col element count - __device__ __constant__ char h_ele_row_bg1_count[46] = { -@@ -92,9 +100,93 @@ __global__ void warmup() - // warm up gpu for time measurement - } - -+extern "C" -+void warmup_for_GPU(){ -+ -+ warmup<<<20,1024 >>>(); -+ -+} -+ -+extern "C" -+void set_compact_BG(int Zc,short BG){ -+ -+ int row,col; -+ if(BG == 1){ -+ row = 46; -+ col = 68; -+ } -+ else{ -+ row = 42; -+ col = 52; -+ } -+ int compact_row = 30; -+ int compact_col = 19; -+ if(BG==2){compact_row = 10, compact_col = 23;} -+ int memorySize_h_compact1 = row * compact_col * sizeof(h_element); -+ int memorySize_h_compact2 = compact_row * col * sizeof(h_element); -+ int lift_index = 0; -+ short lift_set[][9] = { -+ {2,4,8,16,32,64,128,256}, -+ {3,6,12,24,48,96,192,384}, -+ {5,10,20,40,80,160,320}, -+ {7,14,28,56,112,224}, -+ {9,18,36,72,144,288}, -+ {11,22,44,88,176,352}, -+ {13,26,52,104,208}, -+ {15,30,60,120,240}, -+ {0} -+ }; -+ -+ for(int i = 0; lift_set[i][0] != 0; i++){ -+ for(int j = 0; lift_set[i][j] != 0; j++){ -+ if(Zc == lift_set[i][j]){ -+ lift_index = i; -+ break; -+ } -+ } -+ } -+ printf("\nZc = %d BG = %d\n",Zc,BG); -+ switch(lift_index){ -+ case 0: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I0, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I0, memorySize_h_compact2) ); -+ break; -+ case 1: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I1, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I1, memorySize_h_compact2) ); -+ break; -+ case 2: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I2, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I2, memorySize_h_compact2) ); -+ break; -+ case 3: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I3, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I3, memorySize_h_compact2) ); -+ break; -+ case 4: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I4, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I4, memorySize_h_compact2) ); -+ break; -+ case 5: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I5, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I5, memorySize_h_compact2) ); -+ break; -+ case 6: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I6, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I6, memorySize_h_compact2) ); -+ break; -+ case 7: -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I7, memorySize_h_compact1) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I7, memorySize_h_compact2) ); -+ break; -+ } -+ -+ // return 0; -+} -+ - - // Kernel 1 --__global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) -+__global__ void ldpc_cnp_kernel_1st_iter(/*char * dev_llr,*/ int BG, int row, int col, int Zc) - { - // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp %d\n", threadIdx.x); - int iMCW = blockIdx.y; // codeword id -@@ -153,7 +245,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, - for(int i = 0; i < s; i++){ - // v0: Best performance so far. 0.75f is the value of alpha. - sq = 1 - 2 * ((Q_sign >> i) & 0x01); -- R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); -+ R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); - // write results to global memory - h_element_t = dev_h_compact1[i*row+iBlkRow]; - int addr_temp = offsetR + h_element_t.y * row * Zc; -@@ -163,7 +255,7 @@ __global__ void ldpc_cnp_kernel_1st_iter(char * dev_llr, char * dev_dt, int BG, - } - - // Kernel_1 --__global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, int col, int Zc) -+__global__ void ldpc_cnp_kernel(/*char * dev_llr, char * dev_dt,*/ int BG, int row, int col, int Zc) - { - // if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp\n"); - int iMCW = blockIdx.y; -@@ -223,7 +315,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, - // The 2nd recursion - for(int i = 0; i < s; i ++){ - sq = 1 - 2 * ((Q_sign >> i) & 0x01); -- R_temp = 0.8 * sign * sq * (i != idx_min ? rmin1 : rmin2); -+ R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2); - - - // write results to global memory -@@ -236,7 +328,7 @@ __global__ void ldpc_cnp_kernel(char * dev_llr, char * dev_dt, int BG, int row, - - // Kernel 2: VNP processing - __global__ void --ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int BG, int row, int col, int Zc) -+ldpc_vnp_kernel_normal(/*char * dev_llr, char * dev_dt, char * dev_const_llr,*/ int BG, int row, int col, int Zc) - { - int iMCW = blockIdx.y; - int iBlkCol = blockIdx.x; -@@ -276,7 +368,7 @@ ldpc_vnp_kernel_normal(char * dev_llr, char * dev_dt, char * dev_const_llr, int - } - - --__global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc) -+__global__ void pack_decoded_bit(/*char *dev, unsigned char *host,*/ int col, int Zc) - { - __shared__ unsigned char tmp[128]; - int iMCW = blockIdx.y; -@@ -284,15 +376,15 @@ __global__ void pack_decoded_bit(char *dev, unsigned char *host, int col, int Zc - int btid = threadIdx.x; - tmp[btid] = 0; - -- if(dev[tid] < 0){ -+ if(dev_llr[tid] < 0){ - tmp[btid] = 1 << (7-(btid&7)); - } - __syncthreads(); - - if(threadIdx.x < 16){ -- host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; -+ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0; - for(int i = 0; i < 8; i++){ -- host[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; -+ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i]; - } - } - } -@@ -369,18 +461,38 @@ void read_BG(int BG, int *h, int row, int col) - */ - } - -+extern "C" -+void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length){ -+ -+ uint16_t Zc = p_decParams->Z; -+ uint8_t BG = p_decParams->BG; -+ uint8_t row,col; -+ if(BG == 1){ -+ row = 46; -+ col = 68; -+ } -+ else{ -+ row = 42; -+ col = 52; -+ } -+ unsigned char *hard_decision = (unsigned char*)p_out; -+ int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; -+ cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); -+ cudaDeviceSynchronize(); -+ -+} - - extern "C" - int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder) - { -- // alloc mem -- //unsigned char *decision = (unsigned char*)p_out; -+ - - uint16_t Zc = p_decParams->Z; - uint8_t BG = p_decParams->BG; - uint8_t numMaxIter = p_decParams->numMaxIter; - e_nrLDPC_outMode outMode = p_decParams->outMode; -- -+ cudaError_t cudaStatus; - uint8_t row,col; - if(BG == 1){ - row = 46; -@@ -390,96 +502,14 @@ int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8 - row = 42; - col = 52; - } -- int compact_row = 30, compact_col = 19, lift_index=0;; -- if(BG==2){compact_row = 10, compact_col = 23;} -- -- short lift_set[][9] = { -- {2,4,8,16,32,64,128,256}, -- {3,6,12,24,48,96,192,384}, -- {5,10,20,40,80,160,320}, -- {7,14,28,56,112,224}, -- {9,18,36,72,144,288}, -- {11,22,44,88,176,352}, -- {13,26,52,104,208}, -- {15,30,60,120,240}, -- {0} -- }; -- -- for(int i = 0; lift_set[i][0] != 0; i++){ -- for(int j = 0; lift_set[i][j] != 0; j++){ -- if(Zc == lift_set[i][j]){ -- lift_index = i; -- break; -- } -- } -- } -- -- int *h = NULL; -- switch(lift_index){ -- case 0: -- h = (BG == 1)? h_base_0:h_base_8; -- break; -- case 1: -- h = (BG == 1)? h_base_1:h_base_9; -- break; -- case 2: -- h = (BG == 1)? h_base_2:h_base_10; -- break; -- case 3: -- h = (BG == 1)? h_base_3:h_base_11; -- break; -- case 4: -- h = (BG == 1)? h_base_4:h_base_12; -- break; -- case 5: -- h = (BG == 1)? h_base_5:h_base_13; -- break; -- case 6: -- h = (BG == 1)? h_base_6:h_base_14; -- break; -- case 7: -- h = (BG == 1)? h_base_7:h_base_15; -- break; -- } -- /* pack BG in compact graph */ -- read_BG(BG, h, row, col); -- -- -- int memorySize_h_compact1 = row * compact_col * sizeof(h_element); -- int memorySize_h_compact2 = compact_row * col * sizeof(h_element); - --// cpu -- int memorySize_hard_decision = col * Zc * sizeof(unsigned char) * MC; -- -- - // alloc memory - unsigned char *hard_decision = (unsigned char*)p_out; -- - // gpu - int memorySize_llr_cuda = col * Zc * sizeof(char) * MC; -- int memorySize_dt_cuda = row * Zc * col * sizeof(char) * MC; -- -- --// alloc memory -- char *dev_llr; -- char *dev_dt; -- char *dev_const_llr; -- unsigned char *dev_tmp; -+ cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) ); -+ cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) ); - -- cudaCheck( cudaMalloc((void **)&dev_tmp, memorySize_hard_decision) ); -- cudaCheck( cudaMalloc((void **)&dev_llr, memorySize_llr_cuda) ); -- cudaCheck( cudaMalloc((void **)&dev_const_llr, memorySize_llr_cuda) ); -- cudaCheck( cudaMalloc((void **)&dev_dt, memorySize_dt_cuda) ); -- --// memcpy host to device -- -- cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, h_compact1, memorySize_h_compact1) ); -- cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, h_compact2, memorySize_h_compact2) ); -- cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); --start_meas(time_decoder); -- cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memorySize_llr_cuda, cudaMemcpyHostToDevice) ); -- -- - // Define CUDA kernel dimension - int blockSizeX = Zc; - dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks -@@ -488,61 +518,35 @@ start_meas(time_decoder); - dim3 dimGridKernel2(col, MC, 1); - dim3 dimBlockKernel2(blockSizeX, 1, 1); - cudaDeviceSynchronize(); -- -- cudaEvent_t start, end; -- float time; -- -- warmup<<>>(); -- warmup<<>>(); - -- -- cudaEventCreate(&start); -- cudaEventCreate(&end); -- cudaEventRecord(start, 0); -- --// cudaProfilerStart(); -- - // lauch kernel -+ - for(int ii = 0; ii < MAX_ITERATION; ii++){ - // first kernel - if(ii == 0){ - ldpc_cnp_kernel_1st_iter - <<>> -- (dev_llr, dev_dt, BG, row, col, Zc); -+ (/*dev_llr,*/ BG, row, col, Zc); - }else{ - ldpc_cnp_kernel - <<>> -- (dev_llr, dev_dt, BG, row, col, Zc); -+ (/*dev_llr,*/ BG, row, col, Zc); - } -- - // second kernel -- -- ldpc_vnp_kernel_normal -- <<>> -- (dev_llr, dev_dt, dev_const_llr, BG, row, col, Zc); -- -+ ldpc_vnp_kernel_normal -+ <<>> -+ // (dev_llr, dev_const_llr,BG, row, col, Zc); -+ (BG, row, col, Zc); - } -+ - int pack = (block_length/128)+1; - dim3 pack_block(pack, MC, 1); -- pack_decoded_bit<<>>(dev_llr, dev_tmp, col, Zc); -- -- -- cudaEventRecord(end, 0); -- cudaEventSynchronize(end); -- cudaEventElapsedTime(&time, start, end); -+ pack_decoded_bit<<>>(/*dev_llr,*/ /*dev_tmp,*/ col, Zc); - -- -- //cudaCheck( cudaMemcpy((*)hard_decision, (const void*)dev_tmp, memorySize_hard_decision, cudaMemcpyDeviceToHost) ); -- cudaCheck( cudaMemcpy((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char), cudaMemcpyDeviceToHost) ); -+ cudaCheck( cudaMemcpyFromSymbol((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char)) ); - cudaDeviceSynchronize(); --stop_meas(time_decoder); -- -- cudaCheck( cudaFree(dev_llr) ); -- cudaCheck( cudaFree(dev_dt) ); -- cudaCheck( cudaFree(dev_const_llr) ); -- cudaCheck( cudaFree(dev_tmp) ); - -- //free(hard_decision); -+ - return MAX_ITERATION; - - } -diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h -index 0e78f98..c8868f0 100644 ---- a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h -+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h -@@ -23,4 +23,10 @@ - - int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder); - -+void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length); -+ -+void warmup_for_GPU(void); -+ -+void set_compact_BG(int Zc, short BG); -+ - #endif From 8aa88999fc709e5f85a92dd7f5d673eedf80f6e3 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 14 Aug 2020 11:43:54 +0200 Subject: [PATCH 59/70] fixes --- openair1/PHY/MODULATION/nr_modulation.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index c1cabfb8d8..3ce067fe14 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -27,7 +27,6 @@ void nr_modulation(uint32_t *in, uint16_t mod_order, int16_t *out) { - uint16_t offset; uint16_t mask = ((1<>((i*mod_order)&0x1f)) & mask); - out32[i] = nr_mod_table32[(offset+idx)]; + out32[i] = nr_mod_table32[idx]; } } From 9c01cc66ead61cdefd53009fc3ebad5319a99000 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 14 Aug 2020 16:31:37 +0200 Subject: [PATCH 60/70] diabling avx2 for qpsk --- openair1/PHY/MODULATION/nr_modulation.c | 6 ++++-- openair1/PHY/NR_REFSIG/nr_gen_mod_table.c | 2 +- openair1/PHY/NR_REFSIG/nr_mod_table.h | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index 3ce067fe14..cba5e4ba53 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -38,7 +38,7 @@ void nr_modulation(uint32_t *in, uint32_t bit_cnt; uint64_t x,x1,x2; -#if defined(__AVX2__) +#if 0//defined(__AVX2__) uint16_t *in_2bytes = (uint16_t*) in; __m256i *nr_mod_table256; __m256i *out256; @@ -113,7 +113,9 @@ void nr_modulation(uint32_t *in, out32[i] = nr_mod_table32[in_bytes[i]]; return; -#if defined(__AVX2__) +#if 0//defined(__AVX2__) +// disabling this as it is slower than SSE2 +// (maybe because L1 cache could not hold the large table) case 2: nr_mod_table256 = (__m256i*) nr_qpsk_2byte_mod_table; out256 = (__m256i*) out; diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c index f7ec99e8e8..286df21203 100644 --- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c @@ -34,7 +34,7 @@ void nr_generate_modulation_table() { short nr_qpsk_mod_table[8] = {16384,16384,-16384,16384,16384,-16384,-16384,-16384}; -#if defined(__AVX2__) +#if 0//defined(__AVX2__) //QPSK m256 table = (short*) nr_qpsk_2byte_mod_table; for (i=0; i<65536; i++) { diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index 4722ad7b7a..659d63c8d0 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -31,7 +31,7 @@ short nr_qpsk_mod_table[8]; -#if defined(__AVX2__) +#if 0//defined(__AVX2__) __m256i nr_qpsk_2byte_mod_table[65536]; #elif defined(__SSE2__) __m128i nr_qpsk_byte_mod_table[2048]; From 12feffcc1c9a6f7c4e1944ff1a1f54a350aebaee Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 14 Aug 2020 17:29:51 +0200 Subject: [PATCH 61/70] bugfix --- openair1/PHY/NR_REFSIG/nr_gen_mod_table.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c index 286df21203..350b16d391 100644 --- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c @@ -32,7 +32,14 @@ void nr_generate_modulation_table() { uint32_t i,j; short* table; -short nr_qpsk_mod_table[8] = {16384,16384,-16384,16384,16384,-16384,-16384,-16384}; +nr_qpsk_mod_table[0] = 16384; +nr_qpsk_mod_table[1] = 16384; +nr_qpsk_mod_table[2] = -16384; +nr_qpsk_mod_table[3] = 16384; +nr_qpsk_mod_table[4] = 16384; +nr_qpsk_mod_table[5] = -16384; +nr_qpsk_mod_table[6] = -16384; +nr_qpsk_mod_table[7] = -16384; #if 0//defined(__AVX2__) //QPSK m256 From 92595bb2af08e4ba1cce5d48204e12a42a294bb4 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 14 Aug 2020 18:03:04 +0200 Subject: [PATCH 62/70] further fixes --- openair1/PHY/NR_TRANSPORT/nr_pbch.c | 4 ++-- openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index 13dd65d90e..bd1278b2eb 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -61,7 +61,7 @@ int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs, /// QPSK modulation for (int m=0; m>5])>>((m<<1)&0x1f))&1)<<1) ^ (((gold_pbch_dmrs[((m<<1)+1)>>5])>>(((m<<1)+1)&0x1f))&1); + idx = (((gold_pbch_dmrs[(m<<1)>>5])>>((m<<1)&0x1f))&3); mod_dmrs[m<<1] = nr_qpsk_mod_table[idx<<1]; mod_dmrs[(m<<1)+1] = nr_qpsk_mod_table[(idx<<1) + 1]; #ifdef DEBUG_PBCH_DMRS @@ -323,7 +323,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, /// QPSK modulation for (int i=0; i>1; i++) { - idx = (((pbch->pbch_e[(i<<1)>>5]>>((i<<1)&0x1f))&1)<<1) ^ ((pbch->pbch_e[((i<<1)+1)>>5]>>(((i<<1)+1)&0x1f))&1); + idx = ((pbch->pbch_e[(i<<1)>>5]>>((i<<1)&0x1f))&3); mod_pbch_e[i<<1] = nr_qpsk_mod_table[idx<<1]; mod_pbch_e[(i<<1)+1] = nr_qpsk_mod_table[(idx<<1)+1]; #ifdef DEBUG_PBCH diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h index 6b2d5e7255..918ff5210a 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h @@ -177,7 +177,7 @@ typedef struct { /// Scrambled "b"-sequences (for definition see 36-211 V8.6 2009-03, p.14) uint8_t b_tilde[MAX_NUM_NR_CHANNEL_BITS]; /// Modulated "d"-sequences (for definition see 36-211 V8.6 2009-03, p.14) - uint32_t d_mod[MAX_NUM_NR_RE]; + uint32_t d_mod[MAX_NUM_NR_RE] __attribute__ ((aligned(16))); /// Transform-coded "y"-sequences (for definition see 38-211 V15.3.0 2018-09, subsection 6.3.1.4) uint32_t y[MAX_NUM_NR_RE] __attribute__ ((aligned(16))); /* From dc2d948badb5a6519af0eb6cf47a684c1ea52a79 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 17 Aug 2020 13:55:13 +0200 Subject: [PATCH 63/70] memory bugfix and other minor fixes --- openair1/PHY/MODULATION/nr_modulation.c | 80 +++++++++++------------ openair1/PHY/NR_REFSIG/nr_gen_mod_table.c | 33 ++++------ openair1/PHY/NR_REFSIG/nr_mod_table.h | 5 +- 3 files changed, 54 insertions(+), 64 deletions(-) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index cba5e4ba53..9ad12c1a96 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -38,11 +38,7 @@ void nr_modulation(uint32_t *in, uint32_t bit_cnt; uint64_t x,x1,x2; -#if 0//defined(__AVX2__) - uint16_t *in_2bytes = (uint16_t*) in; - __m256i *nr_mod_table256; - __m256i *out256; -#elif defined(__SSE2__) +#if defined(__SSE2__) __m128i *nr_mod_table128; __m128i *out128; #endif @@ -51,6 +47,44 @@ void nr_modulation(uint32_t *in, switch (mod_order) { +#if defined(__SSE2__) + case 2: + nr_mod_table128 = (__m128i*) nr_qpsk_byte_mod_table; + out128 = (__m128i*) out; + for (i=0; i>((i*2)&0x7)) & mask); + out32[i] = nr_mod_table32[idx]; + i++; + } + return; +#else + case 2: + nr_mod_table32 = (int32_t*) nr_qpsk_mod_table; + for (i=0; i>((i*2)&0x1f)) & mask); + out32[i] = nr_mod_table32[idx]; + } + return; +#endif + + case 4: + out64 = (int64_t*) out; + for (i=0; i>((i*4)&0x7)) & mask); + out32[i] = nr_16qam_mod_table[idx]; + i++; + } + return; + case 6: j = 0; for (i=0; i>((i*mod_order)&0x1f)) & mask); - - out32[i] = nr_mod_table32[idx]; - } } void nr_layer_mapping(int16_t **mod_symbs, diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c index 350b16d391..b0f9e6d03c 100644 --- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c +++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c @@ -21,7 +21,6 @@ #include "nr_refsig.h" #include "nr_mod_table.h" -#include void nr_generate_modulation_table() { float sqrt2 = 0.70711; @@ -32,27 +31,14 @@ void nr_generate_modulation_table() { uint32_t i,j; short* table; -nr_qpsk_mod_table[0] = 16384; -nr_qpsk_mod_table[1] = 16384; -nr_qpsk_mod_table[2] = -16384; -nr_qpsk_mod_table[3] = 16384; -nr_qpsk_mod_table[4] = 16384; -nr_qpsk_mod_table[5] = -16384; -nr_qpsk_mod_table[6] = -16384; -nr_qpsk_mod_table[7] = -16384; - -#if 0//defined(__AVX2__) - //QPSK m256 - table = (short*) nr_qpsk_2byte_mod_table; - for (i=0; i<65536; i++) { - for (j=0; j<8; j++) { - table[i*16+(j*2)] = (short)(1-2*((i>>(j*2))&1))*val*sqrt2*sqrt2; - table[i*16+(j*2)+1] = (short)(1-2*((i>>(j*2+1))&1))*val*sqrt2*sqrt2; - //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]); - } + // QPSK + for (i=0; i<4; i++) { + nr_qpsk_mod_table[i*2] = (short)(1-2*(i&1))*val*sqrt2*sqrt2; + nr_qpsk_mod_table[i*2+1] = (short)(1-2*((i>>1)&1))*val*sqrt2*sqrt2; + //printf("%d j%d\n",nr_qpsk_mod_table[i*2],nr_qpsk_mod_table[i*2+1]); } -#elif defined(__SSE2__) +#if defined(__SSE2__) //QPSK m128 table = (short*) nr_qpsk_byte_mod_table; for (i=0; i<256; i++) { @@ -74,6 +60,13 @@ nr_qpsk_mod_table[7] = -16384; } } + table = (short*) nr_16qam_mod_table; + for (i=0; i<16; i++) { + table[i*2] = (short)((1-2*(i&1))*(2-(1-2*((i>>2)&1))))*val*sqrt10*sqrt2; + table[i*2+1] = (short)((1-2*((i>>1)&1))*(2-(1-2*((i>>3)&1))))*val*sqrt10*sqrt2; + //printf("%d j%d\n",table[i*2],table[i*2+1]); + } + //64QAM table = (short*) nr_64qam_mod_table; for (i=0; i<4096; i++) { diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h index 659d63c8d0..aa8b99f584 100644 --- a/openair1/PHY/NR_REFSIG/nr_mod_table.h +++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h @@ -31,9 +31,8 @@ short nr_qpsk_mod_table[8]; -#if 0//defined(__AVX2__) -__m256i nr_qpsk_2byte_mod_table[65536]; -#elif defined(__SSE2__) +int32_t nr_16qam_mod_table[16]; +#if defined(__SSE2__) __m128i nr_qpsk_byte_mod_table[2048]; #endif From 923070e6c16fc952262c52bbec315773b60979cb Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 18 Aug 2020 15:16:23 +0200 Subject: [PATCH 64/70] mem alignment for dmrs symbs --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 93acda23f8..bc09ad872d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -268,7 +268,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////// pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; n_dmrs = (nb_rb*((dmrs_type == pusch_dmrs_type1) ? 6:4)*number_dmrs_symbols); - int16_t mod_dmrs[n_dmrs<<1]; + int16_t mod_dmrs[n_dmrs<<1] __attribute((aligned(16))); /////////// //////////////////////////////////////////////////////////////////////// From e4755f9c31efd1f30224f721831db973bae5bf14 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 19 Aug 2020 10:27:59 +0200 Subject: [PATCH 65/70] init mod tables fo ue --- cmake_targets/CMakeLists.txt | 1 + openair1/PHY/INIT/nr_init_ue.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index ae1a53d5d4..b68db7ddb0 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1600,6 +1600,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold_ue.c + ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gen_mod_table.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c ${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index 1729ac0d9e..fed58dea12 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -39,6 +39,7 @@ #include "PHY/NR_REFSIG/pss_nr.h" #include "PHY/NR_REFSIG/ul_ref_seq_nr.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" +#include "PHY/NR_REFSIG/nr_refsig.h" //uint8_t dmrs1_tab_ue[8] = {0,2,3,4,6,8,9,10}; @@ -681,6 +682,8 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, ue->bitrate[eNB_id] = 0; ue->total_received_bits[eNB_id] = 0; } + // init NR modulation lookup tables + nr_generate_modulation_table(); /////////////////////////PUSCH init///////////////////////// /////////// From d4603636d310bca9c9ce15c0d0f0c8e535dd3faa Mon Sep 17 00:00:00 2001 From: "NCTU OpinConnect Terng-Yin Hsu/WEI-YING,LIN" Date: Wed, 19 Aug 2020 20:37:29 +0800 Subject: [PATCH 66/70] fix compile problem in non-CUDA environment --- openair1/PHY/CODING/TESTBENCH/ldpctest.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c index 72d85b1b14..b42ac6e4c8 100644 --- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c +++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c @@ -396,9 +396,11 @@ int test_ldpc(short No_iteration, decParams.numMaxIter=No_iteration; decParams.outMode = nrLDPC_outMode_BIT; //decParams.outMode =nrLDPC_outMode_LLRINT8; +#ifdef CUDA_FLAG set_compact_BG(Zc,BG); init_LLR_DMA_for_CUDA(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length); - for(j=0;j 1280, 2401 -> 2560 From 8a10323d2a8f49a08babccce19cea43717d12abe Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 19 Aug 2020 15:52:16 +0200 Subject: [PATCH 67/70] more mem alignment for dmrs --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 4 ++-- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 3344682f20..3a44ebc49a 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -161,7 +161,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, int16_t amp, NR_DL_FRAME_PARMS frame_parms) { - int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1] __attribute__((aligned(128))); // 3 for the max coreset duration + int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1] __attribute__((aligned(16))); // 3 for the max coreset duration uint16_t cset_start_sc; uint8_t cset_start_symb, cset_nsymb; int k,l,k_prime,dci_idx, dmrs_idx; @@ -260,7 +260,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, scrambled_output[6], scrambled_output[7], scrambled_output[8], scrambled_output[9], scrambled_output[10],scrambled_output[11] ); #endif /// QPSK modulation - int16_t mod_dci[NR_MAX_DCI_SIZE>>1] __attribute__((aligned(128))); + int16_t mod_dci[NR_MAX_DCI_SIZE>>1] __attribute__((aligned(16))); nr_modulation(scrambled_output, encoded_length, DMRS_MOD_ORDER, mod_dci); //Qm = 2 as DMRS is QPSK modulated #ifdef DEBUG_DCI diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index ac5a126276..2849986833 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -150,7 +150,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; uint8_t Qm = rel15->qamModOrder[0]; uint32_t encoded_length = nb_re*Qm; - int16_t mod_dmrs[n_dmrs<<1] __attribute__ ((aligned(256))); + int16_t mod_dmrs[n_dmrs<<1] __attribute__ ((aligned(16))); /// CRC, coding, interleaving and rate matching AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n"); From 579f9f969ba08998a64ec5650dbc4f563b8fd57f Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 20 Aug 2020 16:59:02 +0200 Subject: [PATCH 68/70] included check for mod_order --- openair1/PHY/MODULATION/nr_modulation.c | 1 + 1 file changed, 1 insertion(+) diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index 9ad12c1a96..764b02065f 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -150,6 +150,7 @@ void nr_modulation(uint32_t *in, default: break; } + AssertFatal(false,"Invalid or unsupported modulation order %d\n",mod_order); } From 9b58b2c87298019f78a9c434aa780d0d9d5893a4 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Mon, 24 Aug 2020 14:19:14 +0200 Subject: [PATCH 69/70] CI: uniqueness in references Signed-off-by: Raphael Defosseux --- ...nb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml index 3780c52bb7..775ef2e023 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml @@ -21,13 +21,13 @@ --> - test-05-tm1-mbms-nos1-tunnel - Test-05MHz-MBMS-TM1-noS1-tunnel + test-05-tm1-fembms-nos1-tunnel + Test-05MHz-FEMBMS-TM1-noS1-tunnel tasks 2 030201 090109 - 030103 000001 090103 000002 040605 000001 090109 030201 + 030104 000001 090104 000002 040605 000001 090109 030201 @@ -49,7 +49,7 @@ 60 - + Initialize_eNB Initialize eNB (FDD/Band7/5MHz/MBMS) -O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512 @@ -60,7 +60,7 @@ Terminate eNB - + Initialize_OAI_UE Initialize OAI UE (FDD/Band7/5MHz/MBMS) -C 2680000000 -r 25 --ue-rxgain 120 --ue-txgain 0 --ue-max-power 0 --ue-scan-carrier --nokrnmod 1 --noS1 From f0fb73f673585790b400efed28e3425e1d34c8ad Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Mon, 24 Aug 2020 14:19:51 +0200 Subject: [PATCH 70/70] CI: less verbose when running MBMS on UE side Signed-off-by: Raphael Defosseux --- openair1/SCHED_UE/phy_procedures_lte_ue.c | 6 +++--- openair2/LAYER2/MAC/ue_procedures.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openair1/SCHED_UE/phy_procedures_lte_ue.c b/openair1/SCHED_UE/phy_procedures_lte_ue.c index 35631c4ac3..3215718f8e 100644 --- a/openair1/SCHED_UE/phy_procedures_lte_ue.c +++ b/openair1/SCHED_UE/phy_procedures_lte_ue.c @@ -2493,7 +2493,7 @@ if((ue->frame_parms.FeMBMS_active == 0)|| is_fembms_cas_subframe(frame_rx,subfra } if (LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) { - LOG_UI(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n", + LOG_D(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n", ue->Mod_id, frame_rx, subframe_rx, @@ -2504,7 +2504,7 @@ if((ue->frame_parms.FeMBMS_active == 0)|| is_fembms_cas_subframe(frame_rx,subfra ue->frame_parms.phich_config_common.phich_duration, ue->frame_parms.phich_config_common.phich_resource); } - LOG_I(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n", + LOG_D(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n", ue->Mod_id, frame_rx, subframe_rx, @@ -3033,7 +3033,7 @@ void ue_pmch_procedures(PHY_VARS_UE *ue, // if (subframe_rx==9) // mac_xface->macphy_exit("Why are we exiting here?"); } else { // decoding successful - LOG_I(PHY,"[UE %d] Frame %d, subframe %d: PMCH OK (%d,%d), passing to L2 (TBS %d, iter %d,G %d) ret %d\n", + LOG_D(PHY,"[UE %d] Frame %d, subframe %d: PMCH OK (%d,%d), passing to L2 (TBS %d, iter %d,G %d) ret %d\n", ue->Mod_id, frame_rx,subframe_rx, ue->dlsch_mcch_errors[sync_area][0], diff --git a/openair2/LAYER2/MAC/ue_procedures.c b/openair2/LAYER2/MAC/ue_procedures.c index f81c66e269..e97f1bebdd 100644 --- a/openair2/LAYER2/MAC/ue_procedures.c +++ b/openair2/LAYER2/MAC/ue_procedures.c @@ -763,7 +763,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint16_t stop_mtch_val = ((uint16_t)(payload_ptr[2*j] & 0x07) << 8) | (uint16_t)payload_ptr[2*j+1]; UE_mac_inst[module_idP].pmch_lcids[j] = (payload_ptr[2*j] & 0xF8) >> 3; UE_mac_inst[module_idP].pmch_stop_mtch[j] = stop_mtch_val; - LOG_I(MAC,"lcid(%d),stop_mtch_val %d frameP(%d)\n", UE_mac_inst[module_idP].pmch_lcids[j], stop_mtch_val, frameP); + LOG_D(MAC,"lcid(%d),stop_mtch_val %d frameP(%d)\n", UE_mac_inst[module_idP].pmch_lcids[j], stop_mtch_val, frameP); if ((stop_mtch_val >= 2043) && (stop_mtch_val <= 2046)) { LOG_D(MAC,"(reserved)\n"); @@ -772,7 +772,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, UE_mac_inst[module_idP].msi_status_v[j] = 0; if (UE_mac_inst[module_idP].mcch_status==1) { - LOG_I(MAC,"[UE %d] Frame %d : MCH->MSI for sync area %d (eNB %d, %d bytes), LCID(%d)(%d)\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], UE_mac_inst[module_idP].pmch_lcids[j] , UE_mac_inst[module_idP].pmch_stop_mtch[j]); + LOG_D(MAC,"[UE %d] Frame %d : MCH->MSI for sync area %d (eNB %d, %d bytes), LCID(%d)(%d)\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], UE_mac_inst[module_idP].pmch_lcids[j] , UE_mac_inst[module_idP].pmch_stop_mtch[j]); if (UE_mac_inst[module_idP].pmch_stop_mtch[j] < 2043) { UE_mac_inst[module_idP].pmch_stop_mtch[j] += UE_mac_inst[module_idP].msi_current_alloc; @@ -781,7 +781,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, } } } else if (rx_lcids[i] == MCCH_LCHANID) { - LOG_I(MAC,"[UE %d] Frame %d : SDU %d MCH->MCCH for sync area %d (eNB %d, %d bytes)\n",module_idP,frameP, i, sync_area, eNB_index, rx_lengths[i]); + LOG_D(MAC,"[UE %d] Frame %d : SDU %d MCH->MCCH for sync area %d (eNB %d, %d bytes)\n",module_idP,frameP, i, sync_area, eNB_index, rx_lengths[i]); mac_rrc_data_ind_ue(module_idP, CC_id, frameP,0, // unknown subframe